
Decreasing the energy level per instruction is one thing, but of course there are certain things that can be done in order to provide better power management and efficiency. Intel combines several measures that start at a manufacturing level: The 65-nm process provides a good basis for efficient ICs. Clock gating and sleep transistors make sure that all units as well as single transistors that are not needed remain shut down. Enhanced SpeedStep still reduces the clock speed when the system is idle or under a low load, but it is also capable of controlling each core separately. Voltage can also be different in different blocks of the processor.

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Summary
- IDF Spring 2006: The Core Of Intel 3.0
- Intel's Energy Awakening
- Quad Cores In Multi-Chip Packages By 2007
- Core To The Rescue
- Wide Dynamic Execution
- Advanced Digital Media Boost
- Advanced Smart Cache
- Smart Memory Access
- Memory Disambiguation
- Intelligent Power Capability
- The Memory Controller Question
- There Is More To Save
- The Server Challenge
- Mashups To Drive Mobility
- Robson NAND Flash Or Hybrid Hard Drives?
- UMPC
- Conclusion
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