The trend for future multi-core processors is simple: There will be even bigger caches and possibly smaller cores, because this is the only way Intel could possibly make its vision of packing hundreds of cores on a single die come true within the next decade. The next generation of processors, however, will be available in the second half of 2007: Kentsfield in the desktop and Clowertown in the server/workstation space will merge two dual-core Conroe or Woodcrest dies into one package.
This will be described as a multi-chip package and is already being used today with the Pentium D Presler, which is based on two Cedar Mill type Pentium 4 chips. Of course, there are disadvantages, such as L2 cache access: Separated caches create an additional FSB load as soon as one processor needs to access the other's L2 memory. But from a business point of view, this approach definitely makes sense: It will still scale up performance quite a bit, while the implementation is something that can be done based on a 65-nm silicon process. Intel stated that we should not expect monolithic quad-core processors prior to the introduction of 45-nm manufacturing.
The way to quad cores is paved: First there will be multi-chip packages, which will involve the integration of two, dual-core processors into one die.
This is the dual core armada for this year and H1/2007.
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- Quad Cores In Multi-Chip Packages By 2007
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- Wide Dynamic Execution
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- Advanced Smart Cache
- Smart Memory Access
- Memory Disambiguation
- Intelligent Power Capability
- The Memory Controller Question
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- The Server Challenge
- Mashups To Drive Mobility
- Robson NAND Flash Or Hybrid Hard Drives?