
Many times, load instructions have to wait until other instructions are executed, although they have nothing to do with them. The memory disambiguation predictor selects memory loads that are independent from prior write operations in order to execute them ahead of the scheduled point of time (see image). Again, this is a way of making sure that the processor pipeline is provided with data as efficiently as possible, and it masks memory latencies at the same time.


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Summary
- IDF Spring 2006: The Core Of Intel 3.0
- Intel's Energy Awakening
- Quad Cores In Multi-Chip Packages By 2007
- Core To The Rescue
- Wide Dynamic Execution
- Advanced Digital Media Boost
- Advanced Smart Cache
- Smart Memory Access
- Memory Disambiguation
- Intelligent Power Capability
- The Memory Controller Question
- There Is More To Save
- The Server Challenge
- Mashups To Drive Mobility
- Robson NAND Flash Or Hybrid Hard Drives?
- UMPC
- Conclusion
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