Sign in with
Sign up | Sign in

Memory Disambiguation

IDF Spring 2006: Will Intel's Core Architecture Close the Technology Gap?

Many times, load instructions have to wait until other instructions are executed, although they have nothing to do with them. The memory disambiguation predictor selects memory loads that are independent from prior write operations in order to execute them ahead of the scheduled point of time (see image). Again, this is a way of making sure that the processor pipeline is provided with data as efficiently as possible, and it masks memory latencies at the same time.

React To This Article