The Ivy Bridge Core: I Think I Know You

Intel purposely carries over a lot of the technology it introduced with Sandy Bridge, allowing the company to focus more intently on a smoother transition from 32 to 22 nm manufacturing. Thus, the capabilities of an Ivy Bridge-based IA core are very much similar to the prior generation.

Each core still hosts 32 KB of L1 data and L1 instruction cache, along with a 256 KB L2 cache. Moreover, quad-core models like the Core i7-3770K share up to 8 MB of last-level cache. Latencies appear very similar, indicating comparable cache bandwidth as Sandy Bridge.

Intel claims it made subtle adjustments to the IA cores, however, that improve performance in certain situations. Company representatives didn’t go into much detail about core architecture improvements at last year’s IDF, mentioning only that there are about half a dozen features in the core and another six or so more in the memory controller/cache that accelerate IA workloads. Fortunately, it’s easy enough for us to run a handful of single-threaded tests with Turbo Boost disabled to see how Core i7-3770K compares to Core i7-2700K, both operating at 3.5 GHz.

Ivy Bridge takes about three seconds off of our Lame, iTunes, and PDF creation metrics. That’s decidedly less impressive than what Sandy Bridge did compared to Nehalem—but again, it’s a result we expected.

The bottom line for enthusiasts is that Ivy Bridge’s IPC-oriented improvements alone are not compelling enough to warrant an upgrade from Sandy Bridge chips running at similar frequencies. 

Intel does incorporate a pair of security-oriented features that software developers will be able to exploit moving forward: a Digital Random Number Generator instruction and Supervisor Mode Execution Protection.

Designed to be standards-compliant, the DRNG’s purpose is to provide a high-quality and high-performance source of entropy—the measure of a cryptographic key’s unpredictability. As a result, an application can exploit the DRNG, and get reliably good random numbers at up to 2-3 Gb/s. Intel makes the instruction available to operating system- and user-level code at all privilege levels.

The other new feature, abbreviated SMEP, attempts to thwart escalation of privilege attacks that seek access to resources normally protected from a less privileged ring. Simply, it prevents the execution of supervisor mode code in user-mode memory pages.