On Connectivity And Security
TH: You’ve got “PC-like” capability, but not necessarily PC-like connectivity.
TT: In transitioning from a PC to a handheld device, we don’t need to use some of the PC I/Os. We kind of got rid of PCI Express and put in handheld I/Os that are more pertinent to what we need. Things such as MIPI I/Os. MIPI is the handheld I/O organization. To give you an idea, the difference between LVDS and the MIPI interface, just the interface link power is about a 125 mW difference. All these kinds of things allowed us to get to lower power.
TH: I’ve got to believe there’s a need for the platform to accommodate conventional peripherals, like if I wanted to add external storage. How does that get handled from within the device?
TT: For internal storage today, we have basically two channels at 80 MB/s. That’s pretty fast if you consider that smaller laptop drives are at 50 MB/s, so the performance you’re going to get is pretty good here. Now, if you want to add storage later on as you try to turn the phone into a full fledged computer, then you would do it through USB. That’s the key expansion port that we have. We also have SD cards that you could add, both microSD and normal SD.
TH: Is the USB functionality 2.0 or 3.0 already?
TT: No, this will be all 2.0, but it’s kind of “2.0+.” In PCs today, you don’t have link power management on USB. With this generation, we’ve added link power management capability, so it’s added capability. This also supports USB on the Go, so it handles both the client and host controller capabilities.
TH: Process shrink aside, how did Intel get such a significant reduction in dimensions on the motherboard?
TT: We shrunk the platform to half of its former size by taking a number of jellybean components that are usually on the platform and integrating many of them into Langwell, our I/O hub. Some we integrated into the mixed signal IC, including the battery charger, power delivery, voltage regulators, and the audio. This also allows us to switch on and off those rails very fast and ramp up power very fast through that mixed signal processor, Briertown. It allows us to switch the device on and off much faster than would have been possible otherwise.
TH: Does Moorestown support AES New Instructions?
TT: We have a completely separate security accelerator. Think about this thing. You cannot have a checker check itself. For example, when you’re booting up, the security engine goes and verifies the firmware and makes sure the signature on that firmware is okay, while the main engine is still sitting there not ready to go. Only once the security system sort of blesses it can the rest of the system boot. The other thing is that if you want to do like a cryptographic operation away from software being able to touch it, we can do it in this engine without anybody being able to touch and figure out what’s going on inside of it. It’s a separate engine, not part of the Intel architecture. Now, if you’re talking about some of the instructions we are adding on our bigger cores, yes, they will be added, but that will be from a compatibility perspective.
