So how do these guys get their systems humming? The charts below will give you tweakers and overclockers some ideas on what they do to get the performance that both system builders guarantee.
Frequencies And Voltages
| Setting |
Falcon-NW |
Biohazard |
Units / Explanation |
| CPU Frequency |
3.73 |
3.50 |
GHz |
| CPU Multiplier |
11X |
12X |
Times faster than the system clock |
| FSB (Effective Frequency) |
1347 |
1167 |
MHz |
| Ratio of Memory to FSB |
Unlinked |
1:1 |
Unlinked = Asynchronous operation |
| Memory Frequency |
1066 |
1167 |
MHz (effective frequency) |
| SLI-Ready Memory |
Enabled |
Disabled |
Increased drive strengths on certain timings and settings |
| Graphics Core Frequency |
626 |
648 |
MHz |
| Graphics Memory Frequency |
1000 |
1000 |
MHz |
| CPU Core Voltage |
1.6500 |
1.4875 |
Volts |
| CPU FSB Voltage |
1.5 |
1.4 |
Volts |
| Memory Voltage |
2.2000 |
2.2000 |
Volts |
| nForce SPP |
1.500 |
1.500 |
Volts |
| nForce MCP |
1.6000 |
1.5250 |
Volts |
| Hypertransport Voltage |
1.300 |
1.350 |
Volts for the bus |
Memory Timings
| |
Memory Timing |
Falcon-NW |
Biohazard |
Explanation of the Timing |
| tCL |
CAS Latency |
4 |
5 |
Delay between the CAS signal and the availability of valid data on the data pins (DQ) |
| tRCD |
RAS to CAS Delay |
4 |
4 |
Delay before a read/write command after bank activation. The cells need to be stabilized by sense amplifiers for proper operation. |
| tRP |
RAS Precharge (Row to Row) |
4 |
4 |
Time delay needed to close one row access and open a new one |
| tRAS |
RAS Active to Precharge Delay |
15 |
14 |
Minimum RAS activation time delay or the time from the bank activate command until the precharge command an be executed. |
| CMD |
Chip Select Issue Delay (Command Rate) |
2 |
2 |
Time needed between the chip select signal and when commands can be issued to the RAM module IC. |
| tRRD |
RAS to RAS Delay (Between Banks) |
4 |
5 |
Row to Row delay from one bank to one on another active bank |
| tRC |
RAS to RAS Delay - Bank Cycle Time (Same Bank) |
13 |
34 |
Row to Row delay on the same bank. One row discharges and another is activated. (Minimum time of tRAS = tRP) |
| tWR |
Write Recovery Time |
4 |
6 |
Delay between writes to ensure a proper writing to the cells. Ideally tRAS minus tRCD to ensure a premature RAS precharge does not wipe out the data. |
| tWTR |
Write to Read Delay |
9 |
11 |
The delay to prep the bus for read after a write. (Turn on or off the appropriate I/O buffers, clear existing data, etc.) |
| tREF |
DRAM Auto-Refresh Rate |
7.8 |
7.8 |
Rate at with the DRAM's charge is refreshed in micro seconds. Prevents corruption by sending data to sense amplifiers and back to the refreshed cell. |
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