Upgrading And Repairing PCs 21st Edition: Processor Features

Intel Core ix-Series And Atom Processors

The Core i processor family replaced the Core 2 and includes two different microarchitectures: The first generation of Core i processors is based on the Nehalem microarchitecture, and the second generation uses Sandy Bridge microarchitecture.

Nehalem Architecture

The Nehalem microarchitecture’s key features include the integration of the memory controller into the processor, and in some models, the entire northbridge including an optional graphics processor in a separate core on the processor die. The first Core i-series processor was the Core i7 introduced in November 2008. Initially built on a 45 nm process, later Core i-series processors were built on an improved 32 nm process allowing for smaller die, lower power consumption, and greater performance. All support DDR3 memory and include L3 cache, and some models include support for HT Technology. See the following table for details.

There are two main variants in the first-generation (Nehalem) Core i-series Family: high-end versions that use Socket LGA 1366 and more mainstream models that use Socket LGA 1156. The latter mainstream models include a fully integrated northbridge, including a dual-channel DDR3 memory controller, graphics interface, and even an optional full-blown graphics processor. Because the entire northbridge functionality is integrated into the processor, Socket LGA 1156 chips use a slower 2 GB/s DMI as the FSB connection to the Platform Controller Hub component on the motherboard.

Core i 900-series processors using Socket LGA 1366 include a triple-channel DDR3 memory controller and a high-performance FSB called QPI (Quick Path Interconnect) that connects to the northbridge component (called an I/O Hub or IOH) on the motherboard. The IOH implements the PCIe graphics interface.

Core i7 and i5 processors also support Turbo Boost (built-in overclocking), which increases the performance in heavily loaded processor cores while reducing performance to cores that are lightly loaded or have no work to perform. Turbo Boost is configured through the system BIOS.

The table below lists the Intel Core i-series family processors using Nehalem microarchitecture:

Processor
Cores
CPU Speed
L2
L3
Core
Process
Power
HTT
Socket
Core i7 9xxX EE
6
3.33-3.46 GHz
1.5 MB
12 MB
Gulftown
32 nm
130 W
Yes
LGA 1366
Core i7 9xx EE
4
3.2-3.33 GHz
1 MB
8 MB
Bloomfield
45 nm
130 WYes
LGA 1366
Core i7 970
6
3.2 GHz
1.5 MB
12 MB
Gulftown
32 nm
130 WYes
LGA 1366
Core i7 9xx
4
2.66-3.2 GHz
1 MB8 MBBloomfield
45 nm
130 WYes
LGA 1156
Core i7 8xx
4
2.66-3.06 GHz
1 MB8 MBLynnfield
45 nm
82-95 W
Yes
LGA 1156
Core i5 7xx
4
2.4-2.8 GHz
1 MB8 MBLynnfield
45 nm
95 W
No
LGA 1156
Core i5 6xx
2
3.2-3.66 GHz
1 MB4 MB
Clarkdale*
32 nm
73-87 W
Yes
LGA 1156
Core i3 5xx
2
3.93-3.33 GHz
1 MB4 MB
Clarkdale
32 nm
73 W
Yes
LGA 1156

* This CPU core also used by Pentium Processor G6950-60

The initial members of the Core i-series family included the Core i5 and i7 processors. These were later joined by the low-end i3 processors.

Sandy Bridge Architecture

Intel introduced the second generation of Core i-series processors, those based on the Sandy Bridge microarchitecture, in January 2011. The Sandy Bridge microarchitecture includes, as its predecessor did, an integrated memory controller and northbridge functions.

However, Sandy Bridge has many new features, including an in-core graphics processor on some models; the new AVX 256-bit SSE extensions; a new instruction cache for holding up to 1500 decoded micro-ops; a more accurate branch prediction unit; the use of physical registers to store operands; improved power management; Turbo Boost 2.0 for more scaled responses to adjustments in core usage, processor temperature, current, power consumption, and operating system states; and a dedicated video decoding/transcoding/encoding unit known as the multi-format codec (MFX). All Sandy Bridge processors use a 32 nm manufacturing process.

The table below lists the Intel Core i-series family processors using Sandy Bridge microarchitecture:

Processor
Cores
CPU Speed
L2
L3
PowerTB 2.0
HTT
Socket
Core i7 39xx

6

3.2–4.0 GHz

1 MB

12-15 MB

130–150 W

Yes

Yes

LGA 2011

Core i7 38xx

4

3.6 GHz

1 MB

10 MB

130 W

Yes

Yes

LGA 2011

Core i7 2xxx

4

2.80–3.40 GHz

1 MB

8 MB

65–95 W

Yes

Yes

LGA 1155

Core i5 25xx

4

2.3–3.3 GHz

1 MB

6 MB

45–95 W

Yes

No

LGA 1155

Core i5 24xx
4

2.5–3.1 GHz

1 MB

6 MB

65–95 W

Yes

Yes

LGA 1155

Core i5 2390

2

2.7 GHz

1 MB

3 MB

35 W

Yes

Yes

LGA 1155

Core i5 23xx
4

2.8–2.9 GHz

1 MB

6 MB

95 W

Yes

No

LGA 1155

Core i3 21xx
2

2.5–3.1 GHz

1 MB

3 MB

35–65 W

No

Yes

LGA 1155


Sandy Bridge processors using LGA 2011 processor sockets are classified as Sandy Bridge-E.

Sandy Bridge also includes Pentium processors in the 967-997, B940-B980, G620-G645T, and G840-G870 series. These processors feature lower clock speeds, less powerful integrated GPUs, and smaller cache sizes than Core i processors. Celeron processors in the B720, 847E, 787-797, 807-887, B710, B800-B840, G440-G465, and G350-G555 series are also based on Sandy Bridge but feature smaller cache sizes and slower clock speeds than Pentium processors based on Sandy Bridge.

Ivy Bridge Architecture

Intel introduced the third generation of Core i-series processors, those based on the Ivy Bridge microarchitecture, in April 2012. The Ivy Bridge microarchitecture represents an improved version of the Sandy Bridge microarchitecture. Ivy Bridge features support for PCI Express 3.0, a new fabrication process at 22 nm, lower power consumption, support for low-voltage DDR3 memory, and support for DirectX 11 graphics with integrated HD Graphics 4000. Existing Sandy Bridge motherboards can use Ivy Bridge CPUs, but a BIOS update might be needed in some cases. The following table lists Core i-series processors using Ivy Bridge microarchitecture.

The table below lists Intel Core i-series family desktop processors using Ivy Bridge microarchitecture:

Processor
Cores
CPU Speed
L2
L3
Power
TB 2.0
HTT
Socket
Core i7 3770 series
4
2.5-3.4 GHz
1 MB
8 MB
45-77 W
Yes
Yes
LGA 1155
Core i5 35xx
4
2.3-3.4 GHz
1 MB
6 MB
45-77 W
YesNo
LGA 1155
Core i5 34xx*
4
2.9-3.2 GHz
1 MB
6 MB
35-77 W
YesNo
LGA 1155
Core 15 33xx
4
2.7-3.1 GHz
1 MB
6 MB
35-77 W
YesNo
LGA 1155
Core i3 32xx
4
2.8-3.4 GHz
1 MB
3 MB
35-55 W
No
Yes
LGA 1155

Processors with power levels below 35 W are also available but not listed here.

Pentium processors in the G2100 series also use the Ivy Bridge microarchitecture but feature smaller cache sizes and have only two cores without HTT, compared to Core i3’s four cores with HTT.

Intel Atom

Intel introduced its Atom ultra low power processors in 2008 and refreshed the line with new models with integrated graphics (D25xx series) in 2012. Although a few vendors have created very low-end desktop computers using Atom, this processor is designed primarily for netbooks, tablets, home servers, and other specialized uses. It is a 64-bit processor fully compatible with x86 and 64-bit versions of Windows and other operating systems, and some models support HT Technology. However, it supports only SSSE3 instructions, has a 4 GB memory limit, and includes only two cores.

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  • Ugggh, got to page two before being disgusted this time. This author is back to writing fiction.

    The Pentium (5th generation, in case the author didn't know, thus the "Pent"), DID execute x86 instructions. It was the Pentium Pro that didn't. That was the sixth generation.

    CISC and RISC are not arbitary terms, and RISC is better when you have a lot of memory, that's why Intel and AMD use it for x86. They can't execute x86 instructions effectively, so they break it down to RISC type operations, and then execute it. They pay the penalty of adding additional stages in the pipeline which slows down the processor (greater branch mispredict penalty), adds size, and uses power. If they are equal, why would anyone take this penalty?

    Being superscalar has nothing to do with being RISC or CISC. Admittedly, the terms aren't carved in stone, and the term can be misleading, as it's not necessarily the number of instructions that defines RISC. Even so, there are clear differences. RISC has fixed length instructions. CISC generally does not. RISC has much simpler memory addressing modes. The main difference is, RISC does not have microcoding to execute instructions - everything is done in hardware. Obviously, this strongly implies much simpler, easier to execute instructions, which make it superior today. However, code density is less for RISC, and that was very important in the 70s and early 80s when memory was not so large. Even now, better density means better performance, since you'll hit the faster caches more often.

    This article is also wrong about 3D Now! It was not introduced as an alternative to SSE, SSE was introduced as an alternative to 3D Now!, which predated SSE. In reality, 3D Now! was released because the largest difference between the K6 and Intel processors was floating point. Games, or other software that could use 3D Now!, rather than relying entirely on x87 instructions, could show marked performance improvement for the K6-2. It was relatively small to implement, and in the correct workloads could show dramatic improvements. But, of course, almost no one used it.

    The remarks about the dual bus are inaccurate. The reason was that motherboard bus speeds were not able to keep up with microprocessors speeds (starting with the 486DX2). Intel suffered the much slower bus speed to the L2 cache on the Pentium and Pentium MMX, but moved the L2 cache on the same processor package (but not on the same die) with the Pentium Pro. The purpose of having the separate buses was that one could access the L2 cache at a much higher speed; it wasn't limited to the 66 MHz bus speed of the motherboard. The Pentium Pro was never intended to be mainstream, and was too expensive, so Intel moved the L2 cache onto the Slot 1 cartridge, and ran it at half bus speed, which in any case was still much faster than the memory bus.

    That was the main reason they went to the two buses.

    That was as far as I bothered to read this. It's a pity people can't actually do fact checking when they write books, and make up weird stories that only have a passing resemblance to reality.

    And then act like someone winning this misinformation is lucky. Good grief, what a perverse world ...
    13
  • Other Comments
  • Keep it coming.
    2
  • 9412 pins; imagine that.
    1
  • Ugggh, got to page two before being disgusted this time. This author is back to writing fiction.

    The Pentium (5th generation, in case the author didn't know, thus the "Pent"), DID execute x86 instructions. It was the Pentium Pro that didn't. That was the sixth generation.

    CISC and RISC are not arbitary terms, and RISC is better when you have a lot of memory, that's why Intel and AMD use it for x86. They can't execute x86 instructions effectively, so they break it down to RISC type operations, and then execute it. They pay the penalty of adding additional stages in the pipeline which slows down the processor (greater branch mispredict penalty), adds size, and uses power. If they are equal, why would anyone take this penalty?

    Being superscalar has nothing to do with being RISC or CISC. Admittedly, the terms aren't carved in stone, and the term can be misleading, as it's not necessarily the number of instructions that defines RISC. Even so, there are clear differences. RISC has fixed length instructions. CISC generally does not. RISC has much simpler memory addressing modes. The main difference is, RISC does not have microcoding to execute instructions - everything is done in hardware. Obviously, this strongly implies much simpler, easier to execute instructions, which make it superior today. However, code density is less for RISC, and that was very important in the 70s and early 80s when memory was not so large. Even now, better density means better performance, since you'll hit the faster caches more often.

    This article is also wrong about 3D Now! It was not introduced as an alternative to SSE, SSE was introduced as an alternative to 3D Now!, which predated SSE. In reality, 3D Now! was released because the largest difference between the K6 and Intel processors was floating point. Games, or other software that could use 3D Now!, rather than relying entirely on x87 instructions, could show marked performance improvement for the K6-2. It was relatively small to implement, and in the correct workloads could show dramatic improvements. But, of course, almost no one used it.

    The remarks about the dual bus are inaccurate. The reason was that motherboard bus speeds were not able to keep up with microprocessors speeds (starting with the 486DX2). Intel suffered the much slower bus speed to the L2 cache on the Pentium and Pentium MMX, but moved the L2 cache on the same processor package (but not on the same die) with the Pentium Pro. The purpose of having the separate buses was that one could access the L2 cache at a much higher speed; it wasn't limited to the 66 MHz bus speed of the motherboard. The Pentium Pro was never intended to be mainstream, and was too expensive, so Intel moved the L2 cache onto the Slot 1 cartridge, and ran it at half bus speed, which in any case was still much faster than the memory bus.

    That was the main reason they went to the two buses.

    That was as far as I bothered to read this. It's a pity people can't actually do fact checking when they write books, and make up weird stories that only have a passing resemblance to reality.

    And then act like someone winning this misinformation is lucky. Good grief, what a perverse world ...
    13
  • ta152h sir you are correct.
    0
  • Yes you are correct on the bus issue. VESA local bus was designed to overcome the limitations of the ISA bus.

    As for the reason Intel went with a slot design for the Pentium 2 was to prevent AMD from using it. You can patent and trademark a slot design.

    As for the Pentium Pro, it had issues from handling 16bit x86 instruction sets. The solution was to program around it. The was an inherent computational flaw with the Pentium Pro too.
    0
  • I don't think there is a single page that isn't piled with inaccurate or incomplete information.......this is perhaps the worst thing I've ever read on tomshardware and I don't see how you let it get published.
    0
  • Kinda nice for generic info, was hoping for more explanation of some of the finer points of cpu architecture
    0
  • Perhaps the most important thing to note from this is just how clever some of our users are ... so get into the forums and help out the n00bs with their problems guys !!

    :)
    7
  • Not to be anal but aren't all Core i3 processors, dual cores (2). Some have Hyper-Threading to make it like 4 cores. The last chart above should read Core i3 - 2 cores. Just saying...
    1
  • 1464403 said:
    Not to be anal but aren't all Core i3 processors, dual cores (2). Some have Hyper-Threading to make it like 4 cores. The last chart above should read Core i3 - 2 cores. Just saying...


    not on mobile. some mobile i3s are single core, same with the mobile i5s... those are all dual core... with hyperthreading.

    there are even dual core i5s in haswell on the desktop. (they are the ones with a (t) after the number)
    0
  • Well although it is full of minor misinformation it is a good insight for a reader that does not know much about it.
    2
  • please stop putting this crap on the site, its better to post nothing on a slow Friday
    -1
  • Llano is not based on Bulldozer but rather is based on a slightly improved K10 (typically dubbed "K10.5").
    1
  • Do AMD processors also feature reprogrammable microcode? I'm using an FX-8350 and before it I was using a Phenom II X4 925 (unlocked X3 720).
    0
  • Yeah, this wasn't particularly well researched. Quite a few minor mistakes, not to mention it reads like an Intel advertisement, with AMD's contribution to modern PCs being either downplayed or omitted entirely.
    0
  • After seeing that story they had up a couple days ago about HUBS where the person actually talked about what SWITCHES do, not hubs.
    Since then I make sure I come into Tomshardware articles expecting stuff to be incorrect. It makes me sad, I used to come here for new tech info but now I'm not so sure...
    0
  • I worked for Intel during the time period that they released the Pentium MMX processors. They told us that MMX stood for Multi Media eXtensions.
    0
  • "Note: Most applications that formerly used floating-point math now use MMX/SSE instructions instead. These instructions are faster and more accurate than x87 floating-point math."

    Quite the contrary, x87 CAN BE more accurate than SSE but not the way around. X87 knows and uses 80 bit floating point data internally while SEE (and AVX) can only use 64 bit floating point data. This sentence will be true if 128 bit precision is implemented in the future.
    0