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Intel 5000 Chipset Platform Aka Blackford

Quad-Core Xeon Clovertown Rolls Into DP Servers
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The 5000 chipset is available in three different flavors to power your Xeon 5300 platform. 5000V is the value version, for only 32 GB RAM; the two others will support up to 64 GB of fully buffered DDR2 memory (DDR2-533 or 667), with or without ECC, running in dual-channel or quad-channel mode. The Northbridge and Southbridge are interlinked via x4 PCI Express, and the 5000 series offers 20 PCI Express lanes that are configured differently, depending on the chipset model.

The main difference between the E7500 series and the latest 5000 chipset series is the latter's Dual Independent Bus (DIB) architecture. Processors on older Xeon platforms had to share the Front Side Bus, which can represent a bottleneck. Now, each processor socket gets its own interface. Thanks to the clock speed increase to 333 MHz, each processor has a total bandwidth of 10.66 GB/s. Even at 266 MHz it's still 8.33 GB/s.

Feature Set

  Intel 5000X Chipset Intel 5000P Chipset Intel 5000V Chipset
HOST 5000X Chipset 5000P Chipset 5000V Chipset
Target Segment Server Server Server
Processor Dual-Core Intel Xeon processors 5000 series Dual-Core Intel Xeon processors 5000 series Dual-Core Intel Xeon processors 5000 series
Number Processors 1-2 1-2 1-2
System Bus FSB1066/1333 FSB1066/1333 FSB1066/1333
MEMORY CONTROLLER HUB 5000X Chipset 5000P Chipset 5000V Chipset
MCH - Type 5000X MCH 5000P MCH 5000V MCH
MCH Package 1432 FC-BGA 1432 FC-BGA 1432 FC-BGA
MEMORY 5000X Chipset 5000P Chipset 5000V Chipset
Memory Modules FBDIMM FBDIMM FBDIMM
Memory Type DDR2 FBDIMM DDR2 FBDIMM DDR2 FBDIMM
Max Memory 64 GB 64 GB 32 GB
Number of Rows/Devices Up to 8 physical rows, 2 - 8 DIMMs per XMB (max up to 4 XMB) Up to 8 physical rows, 2 - 8 DIMMs per XMB (max up to 4 XMB) Up to 8 physical rows, 2 - 8 DIMMs per XMB (max up to 4 XMB)
Mb Support 256 Mb, 512 Mb, 1 Gb and 2 Gb 256 Mb, 512 Mb, 1 Gb and 2 Gb 256 Mb, 512 Mb, 1 Gb and 2 Gb
ECC/Parity Yes Yes Yes
EXTERNAL GRAPHICS 5000X Chipset 5000P Chipset 5000V Chipset
Interface N/A N/A N/A
I/O CONTROLLER HUB 5000X Chipset 5000P Chipset 5000V Chipset
ICH Type 6321ESB 6321ESB 6321ESB
ICH Package 1284 FC-BGA 1284 FC-BGA 1284 FC-BGA
PCI Support Two independent 64-bit, 133 MHz PCI-X segments Two independent 64-bit, 133 MHz PCI-X segments Two independent 64-bit, 133 MHz PCI-X segments
PCI Masters 6 6 6
IDE Two channel Ultra ATA Two channel Ultra ATA Two channel Ultra ATA
Serial ATA 6 serial ATA (SATA) controller 6 serial ATA (SATA) controller 6 serial ATA (SATA) controller
USB Ports/Controllers 6 USB 2.0 ports 6 USB 2.0 ports 6 USB 2.0 ports
LAN MAC N/A N/A N/A
AC'97 Digital Circuits N/A N/A N/A
MANAGEABILITY 5000X Chipset 5000P Chipset 5000V Chipset
RASUM DIMM sparing, Memory RAID, Memory mirroring, x4 SDDC, Memory ECC, HUB interface ECC, DMA DIMM sparing, Memory RAID, Memory mirroring, x4 SDDC, Memory ECC, HUB interface ECC, DMA DIMM sparing, Memory RAID, x4 SDDC, Memory ECC, HUB interface ECC, DMA
I/O Management SMBus 2.0 Support/GPIO SMBus 2.0 Support/GPIO SMBus 2.0 Support/GPIO
WORKSTATION/SERVER I/O EXPANSION 5000X Chipset 5000P Chipset 5000V Chipset
PCI Controller Type 6700 PXH 64-bit PCI Hub 6700 PXH 64-bit PCI Hub 6700 PXH 64-bit PCI Hub
WSE Package 567 FC-BGA 567 FC-BGA 567 FC-BGA
WSE PCI Support Up to 3 PXH 64-bit hub components, each with a maximum bandwidth up to 4 GB/sec. Up to 3 PXH 64-bit hub components, each with a maximum bandwidth up to 4 GB/sec. Up to 3 PXH 64-bit hub components, each with a maximum bandwidth up to 4 GB/sec.
WSE PCI Masters Each PXH contains two independent 64-bit PCI/PCI-X interfaces.
Maximum PCI interface bus speed: 66 MHz.
Maximum PCI-X interface bus speed: 133 MHz.
Each PXH contains two independent 64-bit PCI/PCI-X interfaces.
Maximum PCI interface bus speed: 66 MHz.
Maximum PCI-X interface bus speed: 133 MHz.
Each PXH contains two independent 64-bit PCI/PCI-X interfaces.
Maximum PCI interface bus speed: 66 MHz.
Maximum PCI-X interface bus speed: 133 MHz.
Memory Controller Features
  • Speculative read to memory launched after address decode
  • Early initiation of defer reply reduces idle latency
  • Defers replies, cross bus snoops, IO snoops and processor requests arbitrate for the FSB using a multi-tier weighted scheme
  • 16 MB SF for improving system performance
  • Eliminates remote/inbound snoops and increases bus efficiency
  • Optional mode to defer memory requests in SF mode instead of completing order mode
  • Weighted arbitration amongst PCIe ports to balance bandwidth
  • Uses FBD protocol capabilities for higher efficiency
  • Higher reordering capabilities than prior generation MC
  • Intelligent rd/wr switching schedules writes while conflicts are present on reads or vice versa
  • All CAS commands issued with auto-precharge
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  • 0 Hide
    Anonymous , April 23, 2011 4:39 AM
    Should I buy one of these xw8400 Workstation Dual Xeon Dual-Core 5160 3.0GHz and put a good card in it?
  • 0 Hide
    Anonymous , April 29, 2011 5:05 PM
    Hello1

    Where can you buy this chip? I need to update my macpro 1,1. Please advise,

    Tony -