Uniprocessor standard architecture systems with well cached CPUs do not usually saturate the bus and do not use pipeline mode as frequently. For this reason, the pipelining capability of the P6 bus and of Rambus do not have a very significant performance impact.

In a P2/450 uniprocessor PC, DRAM bus saturation typically hovers between 1 and 10%. By adding more processors, bus saturation can easily be driven beyond the bandwidth capacity of 100 MHz SDRAM. To solve this problem, multiprocessor platforms may use multiple 64 bit buses, or increase the bus width to 128 bits or 256 bits. These configurations also allow servers to satisfy another important requirement - MEMORY CAPACITY.

Large servers must usually ship with half a gigabyte of DRAM and be configurable up to several gigabytes. This can be accomplished today using wide SDRAM configurations with registered DIMMs. But Rambus presents another problem in this area. Each Rambus interface channel allows only 32 memory ICs. Using 64 Mbit DRAMs, the maximum configuration for a single channel is 256 MBytes. Even in late 1999 or early 2000 when 256Mbit components become available, capacity will still be constrained to 1 GB per channel. In order to meet platform requirements, multiple Rambus channels will be required, or repeater chips must be used to extend the capacity (and increase the latency) of each channel.

There is still a cost barrier that must be addressed in server platforms. With such large configurations, DRAM cost makes up a very large percentage of the non-CPU cost of a system. This significantly increases the pain associated with DRAM cost premiums. Based on current die size estimates, it is reasonable to expect a Rambus price premium of 25-35% over SDRAM. This figure will probably shrink over time, particularly after the transition to 256Mbit technology.