It's time to pick apart High Endurance Technology MLC, because the terminology is fairly new and, frankly, subject to some confusion. According to Intel, HET provides SLC-like write endurance. This is accomplished in two ways:
- Die-screening consumer MLC for marginally higher endurance.
- Increasing the page programming cycle (tProg).
Incidentally, these two traits are what define eMLC. In other words, HET is nothing but a marketing term. At the technology level, Micron tells us that die-screening (picking out the very best dies from a wafer) optimistically results in a two-fold write endurance boost. However, the company is citing an eMLC endurance spec that's six times higher than its consumer-grade MLC. Increasing the page programming cycle makes up the difference, as it potentially increases endurance by a factor of two or three.
|3x nm Lithography||SLC||MLC||eMLC|
|Endurance (P/E Cycles)||100 000||5 000||10 000 - 30 000|
|tProg||0.5 ms||1.2 ms||2 - 2.5 ms|
|tErase||1.5 - 2 ms||3 ms||3 - 5 ms|
|Performance Over Time||Constant||Degrades||Degrades|
Although die-screening seems like an easy (albeit cost-adding) way to cherry-pick the best pieces of memory without compromising performance, increasing the time it takes to program a page doesn't necessarily sound as sexy. The reason why relates back to the difference between MLC and SLC NAND.
Single-level cell flash stores one bit per cell. It is a single-bit binary system, either a "0" or a "1." MLC memory stores up to two bits per cell, so you're looking at four states to represent all possible combinations. Though that works out neatly on paper, there is a cost associated with increasing storage density.
Flash memory only has so much voltage tolerance. You can't just double the voltage to multiply the scale. Instead, you need more sensitivity between each state. This means more programming to manipulate a very precise amount of charge stored in the floating gate. MLC and SLC memory both operate similarly. However, MLC needs more precision in charge placement and charge sensing.
As P/E cycles are slowly consumed over the course of time, however, the read margins that determine the value of each cell start shrinking as a result of:
- loss of charge due to flash cell oxide degradation
- over-programming caused by erratic programming steps
- programming of adjacent erased cells due to heavy read or writes
Consequently, over time, the drive experiences data retention problems and read-related errors. Basically, they wear out. That's not a problem on SLC-based drives because they only have one reference point. But MLC memory is completely different, which is why extending the page programming cycle has a pronounced impact on endurance.
In essence, additional time is spent sending a more precise charge to the memory cell. This increases the probability of writing to a cell within a smaller window, in turn creating much larger reference points and extending the amount of wear each cell can withstand. The result is higher endurance at the expense of less performance. And that, ladies and gentlemen, is the long explanation for the SSD 710's low 2700 IOPS random write rate.
- Intel On Enterprise Storage: No More SLC; Meet HET MLC
- Inside The SSD 710: Something Old And Something New
- HET MLC: Supercharged MLC Or SLC Lite?
- HET MLC: What Does Endurance Really Look Like?
- Test Setup And Firmware Notes
- Benchmark Results: Storage Bench v1.0 & PCMark 7
- Benchmark Results: 4 KB Random And 128 KB Sequential Performance
- Benchmark Results: Enterprise Performance
- Sequential Performance Versus Transfer Size
- Performance Over Time
- Intel's SSD 710: Making Enterprise Storage More Affordable?