Fab D1D in Hillsboro, Oregon, will be 45-nanometerized first in order to be ready for mass manufacturing of final 45 nm products in the second half of 2007. This generation is still going to be based on the processor design that Merom is going to introduce in mid 2006, but due to several modifications in addition to the die shrink it will be called Penryn. According to our information, there won't be many chances in comparison to Merom. The cache size, however, will be increased by 50%, resulting in cache sizes of 3 MB and 6 MB L2 cache for the dual core processor versions.
This is the first time Intel is eventually not deploying doubled L2 caches. Looking back at the last processor generations we had 2 MB, 1 MB, 512 kB and 256 kB, making 4 MB and 8 MB the next logical steps. However, we suppose that Intel decided to slow down the cache size increase in favor of quicker adoption of quad core chips. In addition, Intel could be cooking some new processor features we aren't aware of today and which potentially eat up some of the transistor real estate that the 45 nm shrink enables.
Ridgefield Follows Kentsfield
We all know the current Pentium D 800 series based on the Smithfield processor. It is going to be replaced by the 65 nm Presler as Pentium D 900 in early 2006, while tearing apart the two cores into two physical chips inside a processor package at the same time.
While Intel is going to repeat this procedure in order to put together the quad core product Kentsfield, it is still going to be a 65 nm descendant. The 45 nm Penryn is going to be the basis for two desktop processors called Wolfdale and Ridgefield. Wolfdale is going to be the 3 MB L2 cache desktop version of Penryn, while Ridgefield is targeted for a total of 6 MB cache.