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Synthetics generally do the best job of showing what a given hardware configuration is capable of, even if real-world software doesn’t reflect the same result. In Sandra’s Arithmetic benchmark, we see linear scaling from one Core i7-980X to a pair of Xeon X5680s—equivalent to a pair of 980Xs on the same board.
The Xeon W5580s scale as expected. But because they run 133 MHz slower than the X5680s, you don’t see the 66% scaling that’d result in 196 GIPS and 141 GFLOPS from a pair of 3.33 GHz CPUs.
The same story holds true here. Sandra, optimized for as many threads as you can throw at it, fully employs the resources available on our test systems to scale in an almost-linear manner.
Back when I reviewed the Core i7-980X, Sandra 2010 helped demonstrate the potential of AES-NI in the 32 nm part with AES256 bandwidth numbers as high as 11.1 GB/s. This looks like an omission on Intel’s part. While our Core i7-980X engineering sample includes AES-NI support, as reported by CPU-Z, this feature is not enabled on our Xeon X5680 processors—also confirmed by the latest version of CPU-Z. The result is that effective AES throughput is significantly lower here than what you’d find on a production CPU.
The silver lining is that the multi-socket configurations scale according to execution resources, so the SHA256 scores for a pair of Xeon X5680s are up double compared to the Core i7-980X.
One of the benefits to going with Intel’s Xeon 5600-series is support for DDR3-1333 data rates with two modules per channel. Our dual-socket, triple-channel, 12-slot configuration is perfect for putting that to the test.
The bad news is that we don’t see any bandwidth gain at DDR3-1333 versus the Xeon 5500-series setup, running at DDR3-1066. Fortunately, with a number near 35 GB/s, we’re still far in excess of what previous-generation architectures could have achieved with an off-die memory controller and front side bus. And while scaling isn’t quite 2:1 versus a single-socket Core i7-980X, the bandwidth increase is ample to keep both six-core processors fed with data. We haven’t found many (if any) situations where the Westmere (Nehalem) architecture is starved for data with its triple-channel controller.