Best Buy has just slashed $350 off this all-AMD CyberPowerPC gaming desktop, scoring you a powerful 9800X3D build for less. Right now, this gaming PC with an RX 9070 16GB is just $1949.

● Check out this deal at Best Buy

This is a fantastic gaming PC for 1440p, with a strong supporting cast of specs. The 32GB of RAM in this PC alone is worth $450 right now, and a 1 TB SSD will set you back $250.

The Ryzen 7 9800X3D is the headline spec of this build. With its generous 3D cache, it's one of the very best gaming CPUs on the market right now, edged out only by the 9850X3D in terms of gaming performance, as you can see from our bench database below. With 8 cores and 16 threads, this CPU will chew through any gaming title thanks to that 3D cache, which means the chip has to rely much less heavily on RAM, drastically improving performance.

The GPU in this build is the RX 9070 with a generous 16GB of VRAM. Sadly, it isn't the more potent XT version, but this is still a great gaming GPU, averaging nearly 75 FPS in our 19-game rasterization benchmark suite at 1440p. 4K performance was around 41 FPS without frame generation, too, so there is some 4K potential.

The PC also comes with 32GB of DDR5 5600 memory, a slight compromise over 6000 speeds but one you shouldn't notice too much. You also get a 1TB PCIe 4.0 SSD for your operating system and storing games, plenty to get you started.

It's all held together by a B650 motherboard, and ships inside one of CyberPower's more impressive cases, along with fans aplenty. You also get Wi-Fi 6, Bluetooth, lots of USB ports, HDMI and DisplayPort connectivity, and a liquid cooler for the CPU, as well as an 850-watt power supply. And, of course, a copy of Windows 11.

With Black Friday still a couple of weeks away, this is one of the best gaming PC deals going right now and one not to be missed.

Google's eighth-generation TPU family has now expanded further. Back in April, the company announced TPU 8t for training AI models and TPU 8i for general-purpose inference workloads. Google has now introduced TPU 8tx, built on the same silicon as the previously announced 8t, for confidential, hardware-isolated inference aimed at regulated enterprises and governments, and TPU 8i Max, which combines two 8i chips on one package for long-context agentic work.

TPU 8tx swaps the Arm-based Axion hosts of the 8t and 8i for a 5th Gen AMD EPYC CPU, adopting a Boardfly network, and the 8i Max doubles the compute, SRAM, and HBM bandwidth of the original 8i. The original split, the TPU 8t and 8i, made natural sense. The 8t targets large-scale training, while the 8i leans toward low-latency inference and reasoning. TPUs have become a fast-growing business, with the company claiming nearly 100 customers, including Meta’s recent move to TPUs. The more modular approach is flexible and can deliver specialized systems “in a matter of months rather than years,” helping that popularity along.

For the new parts, the TPU 8i Max isn't innovative on the surface, as it’s just two TPU 8i chips combined into a single package. The result is twice the theoretical compute, but more importantly, it fits twice the silicon within the “existing rack footprint,” and Google claims more compute per square foot and per watt.

Doubling both SRAM and HBM bandwidth helps keep things scaling, which would put the 8i Max at about 20.2 FP4 PFLOPS, 768 MB SRAM, and about 17.2 TB/s HBM bandwidth. This compares to Nvidia’s Rubin R200 GPU at a rated 50 FP4 PFLOPS for inference and 22 TB/s of HBM4 per socket, or AMD’s MI455X with 40 FP4 PFLOPS. The compute gap is closing.

The memory bandwidth doubling is also potentially one way around moving to HBM4. The memory wall, as Google calls it, or the bandwidth bottleneck, is a real concern “when dozens of AI agents work together across an entire software codebase.” Larger context windows — with larger models targeting 1 million tokens — mean larger KV caches, partly held in SRAM, and each new token has to read that cache back from memory, which is where the extra HBM bandwidth helps. It’s a different route from Nvidia’s LPX: more bandwidth in one package, rather than a second chip type for decoding and a storage tier for context.

Google also provides useful software for agents to get the most out of its hardware. TPU Sync is an open-source “model-state layer for TPU clusters” that moves KV caches off the chip’s HBM, “automatically tiering massive KV caches off the chip in milliseconds” down to host DRAM and, experimentally, shared storage. Google says this can cut KV transfer latency by “more than 90%,” with time-to-first-token gains that vary by workload. The company has also announced the Agent Compute Engine, a Google Cloud service that pauses idle agent sessions and moves their working memory aside until they’re needed again, another memory-saving effort.

Google credits its vLLM-TorchTPU stack with “state-of-the-art price-performance marks” on InferenceX and AgentX, which test realistic agentic coding and long-context work. However, the only published third-party numbers so far are for the last-generation Ironwood TPU. In SemiAnalysis’s InferenceX tests in September, running Qwen3.5 397B in FP8, Ironwood delivered 50.4% more tokens per dollar than Nvidia’s B200 and 96.0% more than the B300 at 20 tokens per second per user. One issue with that, however, is that Ironwood lacks native FP4, although newer November results show its FP8 beating Nvidia’s FP4 GB300 NVL72 on the same model, at 1.67 times the performance per dollar. There is also no eighth-gen result yet to compare how the new generation differs.

In contrast to the 8i Max, which is designed for long-context work, the new TPU 8tx, “built on the same silicon as TPU 8t,” is “optimized for secure and confidential inference” as well as small-scale training. The security is built into the hardware with isolation to prevent snooping on sensitive data, including model weights. Normally, data has to be unlocked in memory during processing, which is the step this isolation is meant to cover.

This chip is intended for areas where security and confidentiality are high priorities, which means regulated enterprises and governments, particularly those who are using frontier or proprietary models. In that case, the operators may want to “fine-tune models using their private data, distill large models into smaller ones, and train their agents,” without having to move sensitive data between clusters. Agents and security meet here for “secure agent execution.” Back in April, the Pentagon and Google reportedly held discussions for TPU usage in classified settings, although the 8tx chip is not specifically named.

Google’s Private AI Compute, its “hardened TPU platform” with protections “comparable to a typical TEE,” per its September technical brief, already runs confidential serving on TPUs. The 8tx appears to be that capability turned into a product for customers. Alternatives include Nvidia’s NVL72, with one security domain across 72 Rubin GPUs, 36 Vera CPUs, and the interconnects, and Intel’s TDX, which is adding trusted I/O to cover data moving to accelerators.

The TPU 8tx hosts are based on 5th Gen AMD EPYC boards, instead of the Axion hosts on the 8t, which replaced x86 in April. There's one Axion for every two TPUs on the 8i, compared with one Xeon per four on Ironwood. Google gives no reason for the change, but its Confidential VM configuration list has both AMD and Intel series chips, with no Arm-based ones listed. Private AI Compute uses “an AMD-based hardware Trusted Execution Environment” for its CPU workloads, suggesting Google swapped something it already runs on its confidential stack.

The 8tx also adopts the 8i’s Boardfly network over the 8t’s torus, which Google claims can deliver “up to 2x lower latency compared to TPU 8t” with almost no performance penalty, although it’s not clear what measure Google is using. The alternative torus network suits training, since chips mostly swap data with neighbors in a predictable manner, but inference on large mixture-of-experts and reasoning models can send smaller messages between distant chips, with every hop adding delay. With Boardfly, it’s at most seven hops against 16 at 1,024 chips.

What is lacking is a full specifications table, the amount of HBM capacity, pod sizes, an availability date, pricing, and customers for either system. Details on attestation, that is, the ability for the customer to verify confidentiality, are also missing for 8tx. The 8tx and 8i Max are currently listed, along with the 8i and 8t, as “coming soon” on Google’s Cloud TPU page.

Delivering two new TPU systems nearly seven months after April’s pair shows Google wants to turn out specialized systems much more quickly than has been the case in the past. Now, it just needs to prove them, through benchmarks and an availability date when the hardware is actually in customers’ hands.

Enterprising techies looking to build their own local AI cluster have far more interesting options than buying DGX Sparks or Apple Mac Studios. Used data center GPUs are everywhere, and a server rack's garbage is an enthusiast's treasure. This option has become even more popular with CMPunlocker, a soft-mod for Nvidia CMP-170HX cards that unlocks abilities well beyond stock. Now, a techie has taken it a step further, blasting through the remaining limitations with voltage glitching and creating a card faster than the actual $20,000 Nvidia A100 GPU with 80GB of VRAM... but from an $2,500 8GB CMP-170HX mining card.

The volt-mod was done by Kate (GitHub link here), who got her starting point from a paper that described how one could exploit GA100 cards' microcode. She turned her attention to the normally protected onboard fuse controller. Although it's rarely discussed, a "fuse box" has been integral in most any CPU and GPU for a while — though it's normally used once at the factory to break physical connections in chips to parts that have tested poorly, thus disabling them so they can be sold as a lower-end model.

If you're wondering how people are getting 80-40GB of VRAM out of 8-10GB, the explanation is simple: the GA100 silicon actually includes all the corresponding HBM2e VRAM dies within; but they get disabled at the factory like the shader modules. The smaller version is more desirable, as it's based on the variant of GA100 with 80GB of HBM2e within, while the 10GB cards spawn from the 40GB GA100.

The Nvidia cards in question have quite an elaborate eFuse controller (16,384 in a 512 x 32 array) — which can be read to obtain the card's current configuration. Most every part of the card has related fuses: VRAM sections, individual shader modules, PCIe 4.0 and NVLink, and even video codec hardware. However, as Kate succinctly put it: Nvidia's design is insecure, as popping fuses can grant access to more features, not fewer.

Under normal conditions, these fuses can't be popped, or "written to," by the user — but a geek armed with a soldering iron isn't a normal user. Kate had GPT-6 Astra design a simple circuit board based on an $8 STM32G4 microcontroller to tap into the power signals on the card's PCB.

The voltage regulators (VRMs) on the card "speak" PWMVID, an Nvidia standard, and Kate's board intercepted the PWM signals sent into the VRM controller, forcing it to produce voltage glitches on the line feeding the GPU, where the fuse controller lies.

Remember when we said the fuse controller was read-only? With the voltage glitches, many fuse-status reads in a tight loop, and she managed to set the controller to a state in which its security bit flags allowed writes through. From that point, it was "easy" to reconfigure her card. She was careful to force-disable any shader modules previously marked as defective, because these are physical fuses — there's no "undo" button.

She applied the mod to her cards and, after testing with multiple workloads, found that nine had the full 80 GB of VRAM working, and one card "only" had 64 GB usable. Most interestingly, unlocking all the shader modules (SM) nets her FP16 FMA performance 20% beyond a regular A100 card. She thinks this is due to the chips often having 120 or more usable SMs — over the 108 on the spec sheet. The GA100 die starts with 128 SMs to account for defects, which is normal in chip manufacturing.

The CMPUnlocker soft mod is required for enabling the "new" features on the drivers, but it doesn't unlock the card's full potential: the VRAM upper limit is 40-64GB (depending on the variant), many shader modules remain locked, and PCIe bandwidth only goes to 2.0. Additionally, there's no ECC, NVLink, or multi-instance GPU support, all of which are critical in a server setup and are also used for product segmentation.

Kate's volt-mod does away with all of these limits, and her best test card is happily working at PCIe 4.0 speed with the full feature set. She didn't test the video encoder bits, but it's unlikely anybody using these cards cares much for that.

As for the cost, a CMP-170HX 8GB is currently hovering around $3,000, and the 10GB variant costs around $2,500. A full-fat Nvidia A100 80GB in a PCIe configuration can reach $20,000 or more. The SXM server-module versions are cheaper, but they require infrastructure around them. Note that these prices will likely vary significantly, especially as people become increasingly aware of the mods.

Kate says she's publishing her research now because another person independently found the same issue. She has informed Nvidia of the vulnerability, though there's not much the company can do for existing cards already on the market.

The AI data center boom is bringing hope to struggling cannabis farmers as they face increased competition, costs, and taxes amid reduced demand for marijuana. According to Arizona Public Media, the cannabis industry is in decline, with sales peaking in 2024 and oversupply driving prices down. And now, several growers are considering selling their cultivation facilities or converting them into “mini data center nodes.” These facilities already have many of the ingredients needed for AI data centers, such as the increasingly hard-to-get supply of electricity and water infrastructure.

"For some reason, there's a lot more cannabis grown in Arizona than Arizonans use. And so, a lot of folks are getting out of that business, like myself, at least on the cultivation side. But these facilities can potentially be repurposed to be mini data center nodes," Moe Asnani, the former owner of two Tucson D2 Dispensaries, told the public broadcaster. He also added, "The whole idea is if you create these smaller nodes where people control their own data, where they're not at the mercy of other people's updates and things like that — that's kind of where the idea came in, because I believe in decentralization."

Cannabis farming is both power- and water-intensive. Forbes looked at a 32,850-square-foot cannabis facility in Kalamazoo, Michigan, which is currently wired for 1.5 megawatts, which can be expanded to 2.5 megawatts in under a year and 15 megawatts in the long term. It's also provisioned for fiber internet and equipped with a state-of-the-art HVAC system for climate control, which should make it a tempting property for anyone wanting to put up a small data center — something that even OpenAI and Anthropic are interested in as massive hyperscale sites face opposition from the community.

This concept is dubbed "adaptive reuse," with Tucson City Council member Paul Cunningham saying that it’s a more palatable alternative to massive, purpose-built sites sitting on the outskirts of town. "Data centers are dirty words, and everybody knows that. And no one wants to build a brand-new data center anywhere," the politician said. "But if we have buildings that were using that amount of water and that amount of energy already in their previous function and [it] can be done without being invasive, I'm OK with exploring that option."

There is massive demand for data centers, but it’s not a guaranteed payoff for struggling cash-strapped growers looking to unload their unprofitable properties. Niki Krear, vice president of acquisitions of real estate investment trust New Lake Capital Partners, said that there’s a sweet spot between connectivity, costs, and regulation that data center operators look for in a site.

"It’s a combination of finding affordable power, dense fiber networks, and favorable tax policies," Krear told MJBizDaily. Even though many cultivation facilities already boast higher-than-average power capacity for lighting and climate control, data centers often demand twice to thrice more, with upgrades possibly taking up to five years.

Data center operators looking for smaller sites may also have to contend with NIMBY — not in my backyard — fights from neighbors. Additionally, there may be zoning restrictions, moratoriums, and regulatory hurdles, and the lack of economies of scale could end up costing operators more.

This is particularly important as AI chips are expected to increase in power and efficiency in the next five years. As these new AI GPUs become available, data centers will need to sell their existing equipment and buy new hardware to remain competitive. Because suppliers usually offer favorable pricing for larger orders, upgrading these smaller sites will likely end up being more expensive on a per-unit basis. That said, growing opposition toward large new projects could make these former cannabis farms suitable alternatives for operators desperate to get more compute online quickly, provided they check all (or most of) the boxes they need.

Nvidia's Board of Directors is preparing to oust co-founder and chief executive Jensen Huang following revelations of two extramarital affairs, including one with a woman suspected of working for Chinese intelligence and another with an Nvidia executive, reports The Wall Street Journal. Although no final decision has been made yet, the company's directors could meet as early as November 11 to discuss Huang's future. Whoever succeeds Huang will be the company's second CEO in 33 years. Nvidia's stock dropped 8% in after-hours trading following the reports. Nvidia's board of directors launched an independent investigation into the matter on November 8.

The report from the WSJ comes hours after the New York Times revealed that Huang allegedly had an extramarital relationship with Kimberly Powell, Nvidia's vice president of health care, who reports directly to him. According to five people who worked at Nvidia, the relationship was known internally, while Huang and Powell were reportedly seen together at a San Jose hotel during Nvidia's GTC conference in March. The allegations follow an earlier report that Huang had a relationship with Alice Huang, a Chinese businesswoman whom U.S. intelligence believes to be a Chinese intelligence asset.

A similar controversy cost Intel chief executive Brian Krzanich his position in June 2018, when an internal investigation confirmed that he had maintained a consensual relationship with an employee, which violated the company's non-fraternization policy applicable to all managers. It is noteworthy that Nvidia's code of conduct explicitly identifies personal relationships as potential conflicts of interest and instructs employees to consult the company's legal department when such conflicts arise. Whether Huang violated Nvidia's internal policies remains unclear, as the code of conduct does not explicitly prohibit all relationships between managers and subordinates.

Huang's potential departure would mark the first CEO transition in Nvidia's 33-year history, and therefore his succession has become an immediate concern for Nvidia, which does not have anyone of Huang's caliber in the leadership team. Although chief financial officer Colette Kress could potentially serve as interim chief executive if Huang is ousted while the BoD searches for a permanent replacement, it remains to be seen how Wall Street would react to this assignment.

Nvidia co-founder Chris Malachowsky, who used to be the company's senior vice president of engineering and operations and remains a member of the company's board and an Nvidia Fellow, could also play a role in the succession process, given his extensive knowledge of Nvidia's technology, corporate culture, and history. However, has not served in an executive role at Nvidia for at least a decade, so the chances that he will succeed Huang are low.

Back on Sunday, directors expressed confidence in Jensen Huang and his leadership team, a choice of words that did not exactly guarantee his continued tenure.

Nvidia CEO Jensen Huang — already embroiled in a scandal for an extramarital relationship with a woman believed by U.S. intelligence to be spying on behalf of China — reportedly had a separate affair with one of his direct reports, according to the New York Times. Nvidia's board is now reportedly preparing to fire Huang.

The Times, citing five anonymous sources within Nvidia, says that Huang had a relationship with Kimberly Powell, the company's vice president of health care. The sources claim that Huang and Powell were "captured on video being affectionate" in March at a hotel in San Jose, Calif., where the company's GTC conference takes place.

That report says that someone at the hotel filmed the moment on their smartphone, but that Huang's security team "sequestered" them and "made the person an offer to sign a nondisclosure agreement."

Powell joined Nvidia in 2008 and has been steadily promoted. The Times highlights that personal relationships are mentioned as potentially causing conflicts of interest in Nvidia's code of conduct. Like Huang, she is married to someone else.

In 2018, former Intel CEO Brian Krzanich resigned following a relationship with an employee, which was also against the company's policies. Nvidia has not responded to a request for comment from Tom's Hardware. This story will be updated if we hear back.

Earlier this week, it came out that Jensen had an extramarital affair with Alice Huang, formerly a top executive at Singaporean firm Megaspeed and believed by U.S. intelligence to be a spy. Huang admitted to the affair in an email to Nvidia employees. China has denied claims of espionage.

Nvidia's board has an ongoing investigation into that affair, led by the law firm Wachtell, Lipton, Rosen & Katz. Huang is continuing to run the company while that investigation is ongoing. Law firms have been racing to sue the company on behalf of shareholders, including a proposed class-action lawsuit that Nvidia misled investors on material facts about the business.

The Congressional House committee on China has called on Huang for a closed-door session, with Republican lawmakers saying the reports "raise significant national security concerns."

Huang has been a leader of the AI industry, providing the most sought-after chips in the field. He has also had the ear of President Donald Trump, traveling with him and attempting to influence export controls.

Trump told reporters that the FBI was investigating Huang, but also that the Nvidia CEO "had absolutely no idea that the person in question was a spy.”

AMD missed out on deploying Turin-X CPUs in the previous generation, giving its 3D V-Cache tech a four-year hiatus from the data center following the launch of Genoa-X in 2023. In the second half of next year, 3D V-Cache is coming back for HPC with Venice-X, matching the 96 cores and 1,152 MB of L3 cache available on the EPYC 9684X (Genoa-X), but with vastly higher clock speeds, PCIe 6.0, and nearly four times the per-socket memory bandwidth.

After first bringing hybrid bonding to EPYC processors with Milan-X in 2022, AMD followed up a little over a year later with Genoa-X. Turin came and went without a chip sporting stacked SRAM, but now, it’s back with Venice-X. The critical change this time around doesn’t come from big jumps in core count — and consequently cache — as is the case with the standard SP7 lineup. Rather, it’s the 5.3 GHz boost clock speed, another pillar of Venice broadly, that’s particularly beneficial in the HPC workloads Venice-X targets.

As you can see from the top EPYC -X chips from previous generations, boost clocks were significantly lower for the X chips, and higher frequencies were available within the standard chips from each family. Milan scaled up to 4.1 GHz, while Genoa could climb to 4.4 GHz, just not on the EPYC -X chips. Venice-X brings up to the maximum 5.3 GHz boost clock available across the range, unifying a high frequency with a large pool of bonded L3 for HPC workloads.

There are still details missing about Venice-X, including the base frequency, how many SKUs are in the lineup and what their specs are, and the TDP (though the 400 to 600 W range available to other Venice CPUs is likely). The chips appear to use the SP7 socket, however, keeping with previous EPYC -X chips.

The platform comes with 96 PCIe 6.0 lanes, while the smaller SP8 platform targeting enterprises trades memory channels for PCIe lanes. Venice-X comes with the full 16-channel memory setup available on SP7, including support for MRDIMMs at 12,800 MT/s that can drive the quoted 1.6 TB/s of per-socket memory bandwidth.

The critical marriage with Venice-X for HPC workloads, according to AMD, is high frequency with a large pool of stacked cache. AMD currently maintains both 3D V-Cache and high-frequency EPYC chips in its HPC fleet to run its internal EDA workloads. AMD Fellow Phil Steinke says the company runs performance analysis on these workloads to characterize performance, optimize EPYC designs, and push partners to optimize their software.

The biggest consumer on the HPC fleet by far are function verification workloads at over half of AMD's used compute, according to Steinke. These are logic simulations that show up in tools like Cadence Xcelium, and Steinke says the EPYC team is running these workloads “24 x 7 x 365.”

An example of one such workload is above, measuring IPC with AMD's uProf monitoring utility. With 3D V-Cache, AMD says this workload completes 40% faster at around double the instructions per clock. AMD didn't clarify which chips it was comparing or what application it was using. However, the comparison is between an EPYC fleet with and without 3D V-Cache.

Steinke says AMD is able to now move toward a single chip with Venice-X, maintaining the cache advantages in workloads like functional verification while driving the EDA workloads more sensitive to frequency. "I mentioned we have a mix of high frequency and 3D V-Cache CPUs in our data center, and that's because through Milan and Genoa, the high frequency parts were always a little higher on the frequency side," Steinke said. "You don't have that dichotomy [with Venice-X]. You can get the best of both worlds in a single CPU, and this is what we're really excited to be picking up for our own use."

AMD hasn't shared any benchmarks for Venice-X yet, but it provided some more specific HPC benchmarks comparing its high-frequency EPYC 9686F to Intel's Xeon 6980P in several HPC workloads, such as computational fluid dynamics. In AMD's testing, the 9686F was 1.6x faster in these benchmarks while running 32 fewer cores.

We had a chance to test the EPYC 9686F along with the dense EPYC 9996, which you can read more about in our Zen 6 EPYC Venice deep dive and benchmarking article. And indeed, the EPYC 9686F looks very impressive in some of the HPC workloads we ran.

We were only able to test a 2P configuration, and as evidenced by the sole Xeon 6980P, CloverLeaf is sensitive to latency. Even then, the 2P EPYC 9686F completed the complex hydrodynamics simulation in about a third of the time as a single Xeon 6980P.

AMD says it's currently using MEXT, its AI-driven flash-as-DRAM technology, to bolster the amount of memory available for its EDA workloads. When it deploys Venice-X, Steinke says the company will continue using MEXT, which you can read more about in our recent MEXT breakdown on Tom's Hardware Premium.

Venice-X CPUs are launching in the second half of 2027, while SP7 and SP8 Venice CPUs are rolling out now. Also coming in the second half of next year is AMD's Verano, which it's pitching as an AI host node that leverages SOCAMM2 LPDDR5X memory.

Prusa released its new Prusament PETG ESD on Tuesday: a carbon-fiber and carbon-nanotube (CNT)- filled, electrostatic-dissipative (ESD) PETG filament meant to protect static-sensitive electronics. While it’s great for enclosures for a Raspberry Pi, ESP32, and the like, Prusa is targeting the filament more toward electronics production than hobbyist use; however, it’s cheaper than the non-ESD Prusament PETG Carbon Fiber at only $56.99.

• Prusament PETG ESD Black 1kg - $56.99

Prusa isn’t the only one selling ESD filament; 3DXTech and Polymaker were first to the scene, but Prusa is the first to include carbon fiber alongside carbon nanotubes to provide the ESD properties, improving dimensional accuracy and minimizing warping. 3DXTech sells its ESD-PETG at $105; Polymaker’s Fiberon PETG-ESD is $65.98, but the Prusament PETG ESD is only $56.99 and is the only one with carbon fiber reinforcement.

Non-ESD filaments are generally safe for electronics enclosures; many hobbyists use regular PLA, PETG, and ABS without any problems. And while the extra protection can be appreciated, Prusa positions this not for hobbyists, but for electronics production — PCB fixtures and holders for soldering, IC trays for handling and transport, holders for testing multiple boards at once, etc., as Prusa shows on the PETG ESD product page. It saves on manufacturing costs, reducing the need for CNC-machined ESD trays and fixtures, and can be quickly printed on-site with very little lead time. It’s not necessarily for big businesses only either, as indie hardware developers and smaller-scale manufacturers could use this filament to improve their production line without buying expensive ESD filament.

Prusa has not yet published the datasheet containing details about the strength of the filament, but Prusa claims that the filament has increased stiffness and reduced toughness, similar to Prusament PETG Carbon Fiber’s properties. However, the amount of carbon fiber in PETG ESD may be different from PETG Carbon Fiber, as the latter’s purpose is more for strength than for electronics manufacturing.

Prusa is known to use its own 3D printers to print its own components and use its own products for the 3D printers it sells, and on the product page, Prusa says it uses PETG ESD in its own production line to prevent overcoating the edges when powder coating its print sheets. While it isn’t the first or only ESD filament on the market, it’s certainly the cheapest, and when its strength profile is released or tested independently, it may potentially be more worth it than Prusa’s own PETG Carbon Fiber in certain cases.

Residents of Effingham County, Georgia, just filed a RICO lawsuit against their county commissioners, county leaders, and OpenAI and its affiliates, alleging that they committed various offenses in a conspiracy to get OpenAI’s “Project Camellia” approved. According to the Effingham Herald, the plaintiffs — Dr. Michelle Finch-Mincey, Lehman Mincey Jr., and Raymond Carver — are seeking civil damages, saying that the project has harmed their property values and even pointing out that purchase offers for nearby residential properties have dropped or been withdrawn since the data center was announced.

The lawsuit names all Effingham County Commissioners — Chairperson Damon Rahn, Forrest Floyd, Roger Burdette, Jamie DeLoach, Elizabeth Helmly, and Phil Kieffer — as defendants, alongside County Manager Tim Callanan, Effingham County Industrial Development Authority (IDA) CEO Brandt Herndon, the IDA itself, OpenAI, Octans GA LLC, the entity operating the data center on behalf of OpenAI, and Savannah Industrial Development LLC, the agency involved in the sale of IDA property to Octans and OpenAI.

It’s alleged that the defendants committed fraud and concealment through non-disclosure agreements and misleading public statements so that residents remain unaware of the nature of the projects for as long as possible, and that there was a civil conspiracy “to advance Project Camellia through confidential negotiations and closed-door decisions.” They also claimed that the parties engaged in improper land transactions, zoning violations, and civil racketeering.w

Project Camellia is one of OpenAI’s biggest data center projects planned for construction in Effingham County. The site is expected to cost somewhere between $20 billion and $30 billion, to be built across five phases, with a planned compute capacity of 3.2 gigawatts. The company also promised that it will not affect the community’s utility costs, as it will pay for the full cost of all its required infrastructure upgrades, and that it will have minimal water use due to its closed-loop water system. Despite those promises, it seems that some people are opposing the project because of how the county had allegedly tried to secure the land, tax incentives, and zoning approvals without informing the residents until key decisions were finalized and contracts had been signed.

The RICO Act — or Racketeer Influenced and Corrupt Organizations Act — was originally conceived as a way to counter organized crime, particularly Mafia leadership, who often used low-level members to commit individual crimes and do the dirty work for them. However, Georgia’s RICO Act is less stringent than the federal version, which is why it’s been used multiple times for cases that seemingly had nothing to do with the Mafia. For example, it was in the 2023 election racketeering case against Donald Trump and 18 others in the attempt to overturn the 2020 U.S. presidential election results in the state, and it was also used in Young Thug’s trial after the rapper was accused of running YSL Records as a criminal street gang.

Critics say that Georgia’s version is way too encompassing, though, and that it was being used to squeeze defendants involved in more mundane or common felonies. “When you have a hammer, everything looks like a nail,” Georgia State University professor of criminal justice and criminology Volkan Topalli said in Atlanta Magazine.

The actions of both state officials, OpenAI, and its affiliates are not new, though. There have already been multiple complaints of data center developers and local governments using non-disclosure agreements (NDAs) while they negotiate terms for possible data center projects. Developers say they use this tool to avoid “running afoul of insider trading rules,” but people have pointed out that West Feliciana Parish in Louisiana was able to close a data center deal without resorting to one. An AWS data center in Gilroy, California, is also facing scrutiny after residents only discovered the nature of the project when construction began after a five-year permitting saga that relied on zoning rules that were set 45 years ago.

As GTA 6, the most anticipated game of the year, perhaps the decade, nears its November 19 release date, one company has offered its employees the chance to take the day off to play it. Amid the expectation that gamers around the globe will call in sick to play the game instead of heading into the office, PC peripheral and hardware outfit Logitech is getting ahead of the game by giving 7,000 employees the chance to take a day off to play it. Or, if they prefer, they can play any other game instead, the company confirmed in a press release detailing the move.

The new initiative is called "Logi Game Day," and it isn't only available to the top brass. Interns and full-time employees alike can take a day off from now until this time next year, at a time when it's been estimated that the GTA 6 launch could see the U.S. economy take a $1 billion hit in terms of productivity. The game, which is a console exclusive ahead of a claimed early 2027 PC release, is already available for preorder, with pre-loading also up and running. It's a good job, too, with a 212GB PS5 download set to be a real downer for eager gamers with slow internet. The ongoing price hikes also mean that upgrading your PS5 storage for GTA 6 won't be a fun time, either.

As for Logitech, the company believes that it's time for people to move away from the belief that playing games is a waste of time, hence its new initiative. It makes sense for a company that makes gaming accessories to say that, of course, but CEO Hanneke Faber argues that the company sees "how engagement in one sphere supports performance in the other.” The hope will be that, by allowing employees to play games, a productivity boost will follow.

Whether that comes to fruition remains to be seen. But there's less doubt about GTA 6's popularity a little more than a week out from its release. If you've yet to get your order in, you can also grab Grand Theft Auto VI for $79.99 now. You'll get a box with a code that you'll need to redeem on your PS5 to be able to download and play the game.

The game's release brings an end to years of rumors and leaks, not to mention legal battles. Take-Two hit Microsoft with a subpoena in relation to a massive leak earlier this year in an attempt to find the perpetrator. Rockstar Games addressed the leaks in a post on the X social network shortly after the subpoena was made public, saying that it "would be an understatement to say that having videos of Grand Theft Auto VI gameplay leak in this way has been heartbreaking for our team."

SpaceX/xAI is developing a custom version of Nvidia's Vera Rubin NVL72 rack-scale AI system that replaces conventional NVLink cable assemblies with a massive 84-layer printed circuit board (PCB), in part for use in orbital data centers, reports SemiAnalysis. The system is codenamed Kessel and retains 36 Vera CPUs, 72 Rubin GPUs, and nine NVLink switch trays, but introduces a different solid-state interconnect architecture. While SpaceX/xAI will continue to buy Nvidia hardware directly from the company, Elon Musk's company will source other components independently, which could give it greater control over its hardware supply chain.

The Kessel system retains the fundamental configuration of Nvidia's Vera Rubin NVL72 platform, which comprises 72 GPU packages distributed across 18 compute trays and nine NVLink switch trays. However, instead of Nvidia's conventional arrangement with internal NVLink cable cartridges, SpaceX plans to position compute and switch trays back-to-back around a passive PCB midplane. The architecture resembles a smaller version of Nvidia's Kyber design with 576 AI GPUs (albeit in 144 packages), which also relies on a PCB-based interconnect rather than conventional cable assemblies, SemiAnalysis notes. Interestingly, the design is aimed at both terrestrial and orbital deployments, according to the analysts.

Arguably the most distinctive feature of Kessel is its 84-layer PCB midplane, which uses ultra-low-loss M10 copper-clad laminates (CCLs). By contrast, Nvidia's Kyber architecture relied on a backplane based on a considerably more complex 156-layer PCB featuring M9 CCLs. The reduction in layer count by nearly half could substantially improve manufacturability and production yields, but the more advanced copper-clad laminate will almost certainly increase material costs. In any case, an 84-layer PCB is a device that is exceptionally hard to build.

The move to a PCB midplane could simplify system assembly by eliminating numerous high-speed cable connections, but it would not necessarily reduce manufacturing costs. An 84-layer PCB that relies on ultra-low-loss M10 laminate is an exceptionally expensive component that requires sophisticated manufacturing processes and precise quality control. To put an 84-layer PCB number into context, modern high-end server motherboards use 15 – 20 layers, whereas server development boards use more than 20 layers to virtually eliminate any electrical issues with the board itself. Furthermore, manufacturing yields of an 84-layer PCB could become a major obstacle, as defects in internal layers may render an entire board unusable. Consequently, the economic viability of Kessel will depend on whether savings from cable elimination and independent component procurement can offset the cost of its complex midplane.

Perhaps more importantly, Kessel represents a departure from Nvidia's conventional system-level procurement model. Instead of purchasing Nvidia's assembled L6 compute boards or even L10 trays that Nvidia plans to sell with its Vera Rubin generation, SpaceX reportedly plans to acquire AI accelerators, CPUs, switches, and networking components directly from Nvidia and procure other components from third-party suppliers (one can wonder how easy it will be for SpaceX/xAI to procure memory amid today's shortages). This would enable SpaceX to select its own PCB manufacturers, component vendors, and manufacturing partners, optimize its hardware for its infrastructure (which will be important for orbital deployments), and perhaps reduce intermediary costs. Meanwhile, the company would assume greater responsibility for system design, validation, manufacturing quality, and supply-chain management, which is something that most hyperscalers have been doing in recent years.

For Nvidia, the implications are less straightforward. Although direct sales of CPU and AI GPU packages could reduce the company's revenue from complete compute-board assemblies, the arrangement could also encourage other large customers to develop their own Nvidia-based systems and eventually deploy more Nvidia-based machines, something that may be important in a world where custom silicon developed by hyperscalers is rapidly gaining traction. However, to make this happen, Kessel must be a smashing success that will offer clear advantages over systems designed by Nvidia.

By early 2026, Japanese tech investment outfit SoftBank had reserved more power generation capacity than the entire state of Connecticut after cornering a huge portion of the global gas turbine production capacity. Now, the same company has chosen to take a $3.7 billion hit to its earnings after canceling reservations for the highly sought-after power generation hardware. The WSJ reports that SoftBank had reserved more than 13 gigawatts of power-producing turbines, citing unnamed "people familiar with the orders." That's the equivalent of more than six Hoover Dams' worth of capacity, with SoftBank founder and chief executive Masayoshi Son believing that it would be vital to the company's earning potential moving forward. Notably, this development surfaced after SoftBank's CFO fired back at Elon Musk's recent revelation that the company had defaulted on turbine blade contracts, saying, "there is no such default."

The gas turbines were to power AI data centers, and SoftBank is set to build a 9.2-gigawatt power plant in Ohio, with construction scheduled for early 2027. It'll cost $33 billion to build and will provide power to a neighboring eight-gigawatt data center. That data center will be leased to OpenAI, albeit only after Nvidia entered discussions about guaranteeing around $250 billion of financing for the project.

But SoftBank got ahead of itself. After initially planning to use the turbines for future gas-powered plants, the company has now chosen to change direction. Orders for turbines, engines that convert natural gas into the electricity used by data centers, must be placed years in advance of them being required. The company had bet big, placing huge orders with the expectation that demand would greatly outstrip supply. That would leave SoftBank in an enviable position, holding huge orders for the vital components required as part of a data center rollout boosted by AI demand. But those reservations weren't cheap — turbine manufacturers regularly charge customers tens of millions of dollars per gigawatt.

It's now canceled its remaining reservations with GE Vernova, its turbine supplier, while also unwinding contracts for orders that were too far gone. SoftBank told investors on a recent earnings call that the orders had been placed “to secure power generation equipment in anticipation of shortages,” but it now appears it anticipated a little too much.

Crucially, SoftBank is also keen for everyone to know that this move was voluntary and that it did not default on its orders. That's contrary to what xAI CEO Elon Musk claimed in a post on his X social network. SoftBank Chief Financial Officer Yoshimitsu Goto was quick to counter Musk's claims. “This is simply not correct at all,” Goto reportedly said. “There is no such default.”

ASRock has rolled out a new firmware update for its Radeon RX 7000-series graphics cards. The latest VBIOS version 1.0.6 appears to be a follow-up to the previous 1.0.5 release. According to community reports, that older version was bricking some of the company's Radeon RX 7900 XT and RX 7900 XTX graphics cards. The new update has now quietly made its way to the ASRock official website, although the company has not published a changelog or provided any details on what the new update addresses.

Last month, AMD released a VBIOS patch for Radeon RX 7000-series graphics cards to address potential security vulnerabilities. While the company did not disclose any technical details about the vulnerabilities, it assured gamers that there had been no reports of them being exploited. According to a statement shared with ComputerBase, the company provided the following rationale for the update:

"AMD is releasing a firmware update as part of our usual approach to address potential security vulnerabilities. These corrections are already made available before the public announcement to give customers time to update their firmware. As a best practice, we recommend that users update the firmware of their graphics cards as soon as they are provided by the respective GPU manufacturer. There are no reports of exploiting these security vulnerabilities in practice."

ASRock subsequently listed the 1.0.5 VBIOS update for 10 graphics card models, spanning its Radeon RX 7600 XT, RX 7700 XT, RX 7800 XT, RX 7900 XT, and RX 7900 XTX families. However, several Radeon RX 7900 XT and RX 7900 XTX owners reported that their systems failed to boot after installing the firmware. Some lucky users were able to use external EEPROM programmers to recover their cards. Although ASRock has since removed the 1.0.5 update from its website, it has yet to provide clarity on what caused the failures or confirm whether the newly released VBIOS addresses the issue.

There are also unanswered questions around how ASRock plans to help customers who have already been affected. According to reports shared with VideoCardz, a user in Japan received a confirmation from ASRock that the failed update would be covered under warranty. However, another owner in Europe was reportedly directed to seek warranty service despite having an out-of-warranty graphics card. This essentially leaves affected owners uncertain of whether they will receive free repairs or replacements.

Additionally, the lack of a changelog or an official statement, along with the new firmware version, makes it difficult for users to determine whether installing the replacement firmware is safe. We can only hope that ASRock provides some clarity around what version 1.06

PC case, cooling, and PSU maker Montech is celebrating its 10th anniversary this year and has released a new flagship ATX chassis, the King 95 3D and 3D Pro. Like the previous King 95, the 3D version keeps the signature 15-degree curved-glass panoramic front panel and adds a top glass panel, giving you a third window and a unique aesthetic for viewing your build. An integrated, contoured ARGB strip follows the chassis's smooth lines, making it look every bit the king of the castle.

Inside, the large mid-tower chassis supports multiple radiators (though only one 360mm), large graphics cards (plus integrated adjustable GPU support), CPU air coolers, and spots for 2.5- and 3.5-inch drives. However, it doesn't support E-ATX motherboards. The King 95 3D supports rear-connect motherboards and has ample room for cable routing and management. The front aluminum panel IO runs vertically, as with previous King cases, and includes a fast USB 3.2 Gen2x2 (20 Gbps) Type-C port. Overall, it has everything you want in a premium chassis. The uncommon three-panel view into your PC is a great way to show off your rig.

The King 95 3D is available for an inexpensive (at least for curved glass) $119.90 if you want to select your own fans. The 3D Pro includes seven pre-installed LINK Fan INF 120 fans for builders who want a more coordinated look out of the box, plus it includes the Lumi hub (a dedicated fan controller), for $199.90. We have the 3D Pro version in our lab and ran the case through thermal and noise testing in its out-of-the-box configuration to show how it performs compared to others. Will it make our best PC cases list? It has a chance. But before we get into the details, here are the case's specifications from Montech.

Montech King 95 3D Product Specifications

Features of the King 95 3D

▶️ External Features

From the outside, the King 95 3D Pro looks the part of its royal name. That signature curve and three panes of glass offer a panoramic view inside your case like few others, letting you show off your PC from even more angles. It also features a frosted, continuous LED strip running along the tiered top, right side, and bottom, adding some tasteful bling to the chassis. If you get the Pro version with the seven fans, it’s an RGB light show inside which could be polarizing. I do wish there were an option for preinstalled non-RGB fans, since the seven included ones and the infinity mirror styling may not be for everyone. Still, the curved front corner and clean lines really cement the King 95 3D as one of the better-looking panoramic cases on the market.

Up front, the removable curved glass corner with a smoked tint sets it apart from most others. On the right, the front IO panel runs vertically, with the power button on top and the LED on/off button below. It has three USB ports: one 3.2 Gen2x2 (20 Gbps) Type-C and two USB 3.2 Gen1 (5 Gbps) Type-A ports. Finally, it has a 3.5mm audio jack. That continuous 118-LED strip is visible from the front, running along the top, down the right edge, and along the bottom edge. I’m not a fan of a lot of RGB, but this implementation is tasteful. You can control this lighting through the motherboard software or Montech's Lumi software, which lets you fully customize the fans and RGB strip.

The main window panel also uses a smoke-colored tint, with Montech branding in the upper-right corner, and it's secured to the frame by two captive thumbscrews on the back. To remove it, loosen the thumbscrews, slide the panel back, pull from the top, then lift it out of the slots. Easy. I have to say, the biggest problem with all this glass is keeping it pristine and fingerprint-free.

The other (metal) side panel, behind the motherboard, slots into the frame and is secured the same way. It has filtered venting along the top and side for the fans/radiator locations, plus another area for airflow near the power supply and drive mounting locations. In the middle is a gold placard with Montech King 95 3D 10th anniversary badging. Note: The dust filters on this panel aren't removable, so you’ll need to remove the whole panel to clean things up.

At the top, we get a better look at the third windowed panel, letting observers peer into the case from a different angle rather than straight on or from the front. We can also see the tiered top and part of the long RGB strip. Taking this panel off isn’t as simple as the rest. Yes, it’s also secured by two captive thumbscrews on the back, but to remove it, you’ll need to open the main window panel to expose a retaining screw, remove it, then loosen the back thumbscrews and slide it to the rear. After you remove the top glass, you can remove the upper and side retaining screws to take it out. When building, I didn’t find this necessary, but it’s good to know you can take it apart if needed.

Looking at the case from behind, one of the first things I noticed was the vertical PSU mounting location on the left. This space supports up to 220mm power supplies, which is all but the largest on the market. On the right, we see space for two 120mm fans, the motherboard I/O, and seven horizontal expansion slots. Unfortunately, Montech says the King 95 3D does not support vertical GPUs.

Underneath the case, there isn’t a lot going on. We get a better look at the four short rubber-bottom ‘feet’ and the removable dust filter. Montech put on its thinking cap and designed the dust filter to slide out from the front, so chances are you won’t have to move your heavy case to clean it.

▶️ Internal Features

Inside, the case uses a dual-chamber design, with the power supply and all wires hidden behind the motherboard tray. At the bottom, we see three Link Fan INF 120s (reverse blade) along with the mirror finish. The magnetically linked, daisy-chainable fans run up to 2,300 RPM (2,200 RPM on the reverse blade), pushing between 65-67 CFM with a maximum rating of 32dBA (29 dBA on the standard blade). A single Link Fan INF 120 costs $19.90, while a 3-pack (with Lumi Hub) is $64.90. If you do the math for seven fans and the Lumi Hub, it’s cheaper to buy them with the case rather than separately.

When powered on, the mirrored sides become an infinity panel, and with all seven matching, it creates a consistent view across the build. The bottom fan bracket is adjustable, with three positions (8 degrees). We left it down during testing, but with it up, you can focus more air towards the GPU and show off whatever fans you put in the space.

The motherboard tray has plenty of cutouts to access the back of the motherboard for easy installation/removal of air coolers or AIO/custom water-cooling blocks. The case also supports rear-connect ecosystems, including Asus BTF, Gigabyte Stealth, and MSI Project Zero boards. Grommets surround the motherboard tray and are in ideal locations, but like most, they pull out easily when you try to route cables, especially those with larger connectors. I wish all case vendors would secure these better, since they're a pain to reinstall, especially when the case is full of cables.

Up top, we can see the huge gap above the motherboard tray for more fans and radiators. The case cooled just fine with the seven included fans and our air cooler, though GPU temps ran a bit warmer in our noise-normalized testing. That top gap is begging to be filled with fans, even if only for aesthetics. If you plan to use an AIO cooler, this isn’t a problem, since the radiator/fans will fill the space.

From the front, you can see the two Link INF 120mm fans and, at the bottom, the tool-less, adjustable GPU support strut. The back has space to mount two 120mm fans or one 120mm radiator. You can also see the seven horizontal expansion slots held in by thumbnail screws.

Inside, the top of the case above the motherboard space fits up to three 120mm fans or a 360mm radiator. The space is offset back from the motherboard tray, which is a boon for cable management. Normally, there’s barely any room to route the EPS cables, but here there's plenty. Just note that if your build uses air cooling, you will need to fill that area with fans to make it look good. Otherwise, it’s just a blank open space above the motherboard.

On the rear side of the chassis, we get a good look at the space behind the motherboard tray and the fan baffles. There’s plenty of room to route cables, and Montech has multiple pre-installed Velcro straps for cable routing. Even with the power supply installed, there’s plenty of room underneath it to stash excess cables.

At the bottom, we see a simple ARGB hub that consolidates the three different ARGB cables from the fans into one header to control all of them. Montech also includes a magnetic Lumi fan/RGB hub (which supports up to 13 Link Fans total) with both the Pro and non-Pro variants. Oddly, it comes loose/uninstalled on the Pro, but installed on the non-Pro. The box in the lower-right holds one 3.5-inch HDD and a single 2.5-inch drive. The second 2.5-inch drive mounts in the other location at the bottom left, next to the side fans.

We do like the look of the King 95 3D Pro case in black, and I bet it looks great in white with an all-white build too. The curved glass and 3-panel panoramic interior views are great for anyone who’d like to show off their now-ridiculously expensive parts. The included Link Fan INF 120 fans work well and run relatively quietly. If there’s an aesthetic drawback, it's that I’m not a huge fan of all the RGB and infinity mirrors on the pre-installed fans. It’s a lot, and it makes me yearn for an option with preinstalled fans and no RGB. Of course, you can turn them off in the software, or buy the non-Pro and choose whichever fans fit your build.

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Test equipment, method, and results

Thermal tests showing how a case performs are just one part of deciding whether you should buy it. Other considerations include aesthetics (subjective), noise and how loud it is while keeping your components cool, additional features, and, of course, price. Everyone has different priorities for their PC case, be it RGB lighting, quiet cooling, ample space for your components, or the best cooling possible, noise be damned. Our goal is to give you the information you need to make an informed buying decision.

To get heat into the system, we stress the CPU with Cinebench R26 (multi-threaded test) and the video card with FurMark 2 (1080p). We run the CPU and GPU tests concurrently for 30 minutes, allowing the air-cooled system to reach saturation and stabilize. We then let the system idle for 15 minutes, adjust the fans to 100%, and test again.

Noise-normalized (42dBA) Maximum thermal Performance

This set of tests is designed for those who love quiet PCs, with both system fans and the CPU fan noise normalized to 42 dBA. Consider this a measure of the case’s thermal efficiency when noise levels are set to run quietly. It is audible, but just (at least for my old ears).

Noise-normalized results were among the best for the CPU and warmer than average for the GPU. The CPU averaged 87 degrees Celsius throughout testing, which is a couple of degrees better than most. The video card averaged 81 degrees, which was surprising given the three fans blowing directly at it. These temps will drop a bit if you add more exhaust fans at the top, but these are good results, especially for the CPU, and the case with these fans will keep whatever you put inside running cool, without making much noise at these fan speeds.

Maximum thermal performance - fans at full speed

Our noise-normalized results are for those who prefer silence, but what if you don’t mind extra noise and just want maximum performance, or you have to run things at high settings to keep high-powered devices cool? This testing is for you. Obviously, when you add fans or an AIO up top, things will change a bit, but this gives you a great idea of ‘out-of-the-box’ performance, noise be damned.

After raising the fan speed to 100%, the CPU only dropped two degrees Celsius, mostly because we could turn the fans up a bit higher than others in the noise-normalized testing. The video card dropped a respectable nine degrees, but was still one of the warmest but in a tightly packed datasets. Again, we expect even lower temperatures with the full complement of fans installed and have no worries it will handle flagship-class hardware.

Maximum Noise Levels

We measure noise levels with a sound meter one meter away from the computer case, with the pre-installed fans running at maximum RPM. If a case does not have enough included fans for airflow (intake and exhaust) as configured, we add a Cooler Master M120 ARGB, since we expect most users will add at least one more fan in situations like these.

The loudest this case gets in our configuration was 53 dBA, 11 dBA above our baseline threshold. This is the second-highest among the tested chassis. I was surprised by this result too, since the entire front and top of the case are covered, while others with an open front were a couple of dBA lower. That said, this case as tested has seven fans, and these tested cases often include four (or fewer), so it’s not bad considering it’s close to double the number of fans as others. Even at full power, they didn’t sound harsh, just like fans moving a lot of air in and out.

Conclusion

Montech’s new King 95 3D 10th anniversary case is a notable update from the King 95. I personally own the King 95 Ultra (Limited edition) and love what it offers. And that curved glass corner was a unique feature for cases when it launched. Fast forward to today, the 3D version for its 10th anniversary takes what worked there and builds on it. It’s larger, includes a cool 118-LED contour strip for continuous lighting, and has plenty of room for large internals. At $119.90 without fans, you supply your own, or for $199.90, you can get seven pre-installed Link Fan INF120s and a hub.

Performance was good all around, with the King 95 3D Pro and its seven fans doing a good job keeping the CPU cool in our noise-normalized testing. The video card did run warmer than most, but not enough to be alarming. Cranking the fans to 100% yields slightly better CPU temps, and the GPU dropped considerably, much closer to other chassis’ results. With all the fans running at full tilt, the noise was on the louder side, but it was just air turbulence. In short, feel free to pack this chassis with any hardware that fits, as it will cool without issue. It’s just a bit loud with Link fans turned up. I would like to see E-ATX motherboard support in the larger case, but that certainly isn’t a dealbreaker for most.

The Montech King 95 3D is a solid premium mid-tower chassis. The top glass is a unique addition for a PC case and lets you see inside from almost any angle. It also offers ample room for large graphics cards, CPU air coolers, and a 360mm AIO at the top. The included fans add a lot of bling, but you can buy the non-Pro version of the King 95 3D and choose your own fans for a more subtle, potentially quieter, and less RGB-infused build. If you’re in the market for a larger premium mid-tower chassis and would like to show off your build through three windowed panels, the new King 95 3D (and 3D Pro) should be on your shortlist for a sub-$120 (w/o fans) or sub-$200 (w/seven fans) chassis.

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Nintendo has set its famously litigious sights on the open-source firmware that powers hardware modchips on Nintendo Switch. Earlier this week, GitHub posted a DCMA request from Nintendo of America confirming that an entire network of 144 total repositories, including the parent repository, was taken down. Mod chip firmware for hardware including SX Core, SX Lite, Picofly, and HWFLY was targeted.

Early original Nintendo Switch consoles shipped with an unpatchable hardware exploit found in the device's recovery mode, which has since been patched in later units such as the Switch Lite and Switch OLED (the modchip hack doesn't work on Switch 2). As such, running custom software on patched Switches requires hardware modification, soldering a microchip like a Picofly, HWFLY, or SX Core to your Switch's motherboard. These chips require firmware, specifically code that can perform the voltage glitching required during boot to hack the Switch.

Rather than playing whack-a-mole with vendors of off-the-shelf microcontrollers, Nintendo has instead issued a DCMA takedown notice to the entire family of GitHub repos hosting this firmware. "The reported repositories offer, link to, or otherwise provide access to mod chip firmware including but not limited to SX Core, SX Lite, Picofly, or HWFLY," the DCMA request from Nintendo reads. "The firmware allows Nintendo Switch modchips to illegally circumvent Nintendo’s TPMs in order to run illegal copies of Nintendo Switch games. Specifically, during operation, the mod chip firmware at the reported repositories circumvents the technological protection measures put in place on the Nintendo Switch console by bypassing the boot sequence.

Nintendo went on to state that because these repositories are designed "primarily" to unlawfully circumvent technological measures controlling access to work protected under the DCMA, distributing mod chip firmware "constitutes unlawful trafficking in technology that is 'primarily designed or produced for the purpose of circumventing a technological measure that effectively controls access' to copyrighted works." In support of this argument, Nintendo cited criminal proceedings brought by the US Department of Justice against Team-Xecuter, a maker and seller of SX Pro, SX Core, and SX Lite modchips.

While these modchips can be (and are) used for game piracy, they unlock a host of features including running homebrew and custom applications, emulation, alternative operating systems, and more. They also enable game modding, custom themes, and even Switch overclocking. Naturally, Nintendo has chosen to focus on their utility in accessing pirated games and bypassing DRM.

Because much of this hardware and firmware is already out in the wild, the move won't have any impact on existing Switch owners who have a modchip installed. However, this will prevent firmware updates to existing modchips, as well as firmware flashing and reflashing. Naturally, it will also prevent future potential hardware modders from hacking their Switch in the same way.

Nintendo is famous for its fervent prosecution of copyright law, but developments in AI are turning this into a drastically more complicated battle. Nintendo's Zelda remake was dumped online on the same day it launched on Switch 2, while earlier this year one developer used AI to bring the original Nintendo 64 version to iOS. In July, Mario Kart Wii was recompiled for PC in 4K with over 200 tracks.

Amid the AI gold rush, one particularly fruitful vein of research is the emergence of AI-assisted workflows in electronic design automation (EDA) tools like Cadence Maestro. One such company developing such foundational models is Cognichip, which in September launched Artificial Chip Intelligence (ACI), proprietary AI models developed specifically for semiconductor engineering. ACI deploys the 'industry’s largest training dataset' across semiconductor physics and chip design principles.

ACI Enterprise is Cognichip's deployable platform, which combines these specialized models with agentic workflows, project memory, and computing infrastructure for AI inference. The company describes ACI's approach as a self-learning flywheel, a continuously evolving design environment that brings together specifications, register-transfer level (RTL), and verification results to build a design that meets power, performance, and area (PPA) targets to Pareto limits. We sat down with Cognichip to learn more.

"We have surpassed, I think, over ten million training samples in our datasets that are either things that we designed ourselves directly or things that have been generated through our synthetic technology," says Stelios Diamantidis, Chief Product Officer at Cognichip, in an interview with Tom's Hardware Premium. "We have invented new ways of creating synthetic training samples for semiconductor design. And very importantly, now that we have all these data samples, characterized data samples, we also had to invent new models so that we can capture the data, and we also had to invent new pipelines for training so that we can map the training data to the models themselves."

A self-learning flywheel

Cognichip says ACI can analyze specifications, explore microarchitectural options, generate RTL, verify designs, identify and fix functional problems, and optimize designs to meet PPA targets. The system can also integrate existing IP modules and even produce FPGA implementations. In principle, ACI enables engineers to focus on product requirements and architectural decisions while ACI handles much of the logic implementation and verification work.

"Build the spec, build the RTL, estimate PPA, perform optimizations, run verification, everything," Diamantidis told us while explaining how ACI can develop and evaluate multiple architectural alternatives before engineers select the preferred design. "We do not try to turn the designer into a verification engine; our system is self-verified, so we want the designer to design, and we want our system not only to do the tasks but also verify them."

Because ACI operates as a self-learning flywheel, Cognichip claims engineers can revisit earlier architectural decisions and modify their designs without restarting the entire development process from scratch.

"Architecture, microarchitecture, RTL, all abstractions in the cognitive system are aligned, so the change in microarchitecture is essentially automatically reflected in RTL, and vice versa," Diamantidis explained. "Changes in RTL are automatically reflected in microarchitecture."

Cognichip says it has participated in more than 40 customer engagements, including projects at Renesas and SiTime. According to the company, these engagements span a wide range of chip designs, from microcontrollers and encryption engines to networking processors, RISC-V CPUs, and AI accelerators.

To illustrate ACI's capabilities, Cognichip points to an evaluation conducted with an unnamed leading fabless semiconductor company. The customer provided an existing 55-page microarchitecture specification, which ACI used to explore architecture options, develop RTL from scratch, and integrate middleware and other components. The system also generated SystemVerilog testbenches, ran simulations, identified and corrected errors, and achieved functional verification closure with over 90% UVM coverage, the company claims. According to Cognichip, the entire process took just 10 days and required only one engineer. By contrast, doing the same job using conventional methods would require a full front-end design team and approximately 20 weeks, Cognichip says.

However, there are several important caveats. First up, the customer had already provided a detailed 55-page microarchitecture specification, so the platform did not begin with a blank sheet. Secondly, Cognichip has not disclosed the complexity of the design, which makes it difficult to assess how much work has been done (or rather, processed). Finally, the reported acceleration applies to front-end engineering rather than the entire chip development process, which also includes physical implementation, tape-out, manufacturing, and silicon validation.

Making very educated guesses/predictions

There is a substantial difference between developing functionally, conducting verified RTL, and prepping a chip design for manufacturing. Although Cognichip's ACI can develop microarchitectures, generate RTL, and optimize designs for PPA, the platform does not perform physical implementation. Tasks such as floorplanning, placement and routing, clock-tree synthesis, physical verification, and signoff still require conventional electronic design automation (EDA) tools from companies like Cadence, Synopsys, and Siemens EDA.

"Today we do not do physical implementation," Diamantidis said. "So, place and route […] is done outside of our system."

This distinction matters because an architecture that meets its estimated PPA targets may fail to achieve them after physical implementation. For example, a design expected to operate at 1 GHz while consuming 15 W could achieve only 800 MHz at 20 W once engineers account for interconnect delays, clock distribution, buffering requirements, congestion, and other physical effects. Such discrepancies can require changes to RTL or even fundamental architectural elements, followed by another round of verification and physical implementation. In some cases, these iterations can consume weeks or months of engineering time.

"That cycle is very expensive in terms of time," Diamantidis said. "Because you are crossing design boundaries, and you are running very long runtimes and all that."

Cognichip claims that ACI can reduce these costly iterations by predicting the physical consequences of architectural decisions before implementation begins. According to Diamantidis, the company has trained its models on internally developed and characterized semiconductor designs, which enables ACI to estimate PPA characteristics and identify potential architectural trade-offs during front-end development.

"We have trained models with full physical stack visibility understanding so that the models can predict the PPA during the front-end design phase." "We can identify those trade-offs before going to physical implementation."

For example, ACI could recommend replacing two independent FIFOs with a single time-multiplexed FIFO to reduce power consumption at the expense of performance. Diamantidis used this hypothetical scenario to illustrate how the platform can evaluate architectural alternatives before engineers commit to a particular implementation.

"If you want to save power here at the cost of 10% of frequency, take these two FIFOs that you have for two different tasks, merge them, make one FIFO, and then time multiplex the two functions over one FIFO," Diamantidis explained.

Cognichip claims that ACI can estimate not only the immediate PPA consequences of such changes but also their potential impact on physical implementation.

"These trade-offs become visible now because we can tell the designer essentially in real time what some of these impacts are going to be to downstream parasitics and downstream congestion and all those kinds of effects."

The general idea behind ACI is to resolve potential architectural problems before RTL reaches physical design engineers rather than wait for implementation results and revise the architecture afterward.

"Our expectation is that there will be no loopbacks to the designer in terms of 'let us do this again because we did not meet this goal or because we ran into congestion issues,'" said Diamantidis.

However, the accuracy of these predictions is critical. Cognichip claims its models can predict certain PPA characteristics with errors of approximately 10% relative to results obtained from conventional EDA tools at the pre-route stage of physical implementation.

Cognichip evaluated its technology using 1,200 open-source designs and compared its predictions with those produced by general-purpose AI models, including Anthropic's Claude Opus and Google's Gemini. According to him, general-purpose models produced errors of approximately 50% – 100%, depending on the metric, whereas Cognichip's models reduced prediction errors to around 10%.

"[General purpose models] do not do well when it comes to predicting delays," Diamantidis said. "So, we take that down to within 10%. Again, 10% because think about it, we are running it at RTL. We do not have much physical information at all, right?"

There is an important distinction, though. Cognichip's reported accuracy refers to pre-route physical implementation results, not final post-route characteristics. Actual routing introduces interconnect and power delivery parasitics as well as other physical effects that can alter timing and power consumption. Consequently, the reported 10% prediction error does not necessarily mean that ACI-generated designs will achieve their estimated PPA targets after physical implementation and signoff.

Another question concerns the range of architectures and manufacturing technologies for which ACI can deliver such accuracy. Although Cognichip says its models incorporate semiconductor physics and account for process-dependent characteristics, it has not disclosed which foundry nodes it supports or how prediction accuracy varies across them.

Diamantidis explained that some architectural decisions are largely independent of manufacturing technology, whereas others become increasingly dependent on the target process node as development progresses.

"[Think about chip development as a tree], at the top of the tree, there are decisions that are not really foundry-specific; they are closer to microarchitecture," he explained. "Then, of course, as you start working your way down the tree, at some point you branch off because the decision may be targeted towards the TSMC node A versus TSMC node B, which will result in different prediction things. But there is a big trunk of decisions that are not really related to the node and are more related to the architecture and the way that the architecture is implemented. What we try to do is we try to think of this whole tree and provide a lot of feedback to designers, especially in a node-agnostic mode, and then, of course, at some point we have to become more node-aware."

This distinction is exceedingly important for complex CPUs, GPUs, and AI accelerators, where physical constraints tend to have substantial impact on architectural decisions. Meanwhile, Cognichip does not claim that ACI must develop such processors as monolithic designs. Instead, the company says its technology can work with individual IP blocks and subsystems, which engineers can subsequently integrate into larger chips. Of course, integration of these individually optimized IP blocks into larger chips is a challenge.

Big chip? Not a problem, but there is a caveat

Although Cognichip says ACI can handle subsystems containing millions of logic gates (i.e., circuits that implement Boolean functions), combining multiple such designs into a complex SoC introduces additional constraints related to interconnect delays, clock distribution, shared memory bandwidth, power delivery, and floorplanning. Consequently, an architecture that achieves Pareto-optimal PPA characteristics as a standalone subsystem may no longer be optimal once integrated into a larger chip. According to Cognichip, ACI can account for these system-level interactions by aligning and optimizing individual blocks against global SoC and subsystem constraints.

“Yes, ACI can align and optimize individual blocks to global SoC and subsystem constraints. It can be applied to both flat and hierarchical optimization problems,” Diamanditis said.

Cognichip is not proposing a fundamentally new SoC development methodology, but rather automating substantial portions of conventional front-end workflows. Its ACI platform supports both flat and hierarchical optimization and can drive the partitioning and propagation of design constraints from the top level to individual blocks. According to Cognichip, ACI can decompose system-level constraints into requirements for individual components and then re-aggregate them as the blocks are integrated.

“ACI does not require a flat design methodology; it can drive hierarchical design from the top or subsystem-top down, ensuring that constraints are decomposed going into components but then re-aggregated when blocks are integrated,” Diamanditis explained.

According to Cognichip, ACI can handle individual IP blocks and subsystems containing millions of logic gates, which can subsequently be combined hierarchically into larger SoCs. The company emphasizes that the complexity of individual partitions, rather than their size, determines how effectively ACI can handle them. However, it remains to be seen how effectively ACI can coordinate architectural decisions and optimize PPA across an entire complex SoC in practice. After all, a Pareto-optimal CPU core, memory controller, and interconnect do not necessarily form a Pareto-optimal SoC, as their interactions introduce additional timing, bandwidth, power, and physical constraints.

Then again, developers of complex SoCs already address these challenges with hierarchical design methodologies, system-level optimization, and integration, so ACI’s focus on individual subsystems does not necessarily represent a significant limitation.

Feedback loops? No need for them!

One of the questions that normally occurs when we talk about a tool that is only aimed at the front end of chip development is how it can handle feedback loops from physical implementation (more on this later). Such feedback loops occur when placement and routing reveal problems with timing, power consumption, die area, or routing congestion that cannot be resolved through physical design optimizations alone. In more serious cases, engineers must revise RTL, pipelines, memory hierarchies, or other architectural elements, which requires another round of functional verification, synthesis, and physical implementation. These iterations can take plenty of time and involve multiple engineering teams, which makes them particularly expensive.

Cognichip says ACI can use physical implementation results to revise RTL and microarchitecture if necessary, although this is not the company's primary focus. Instead, it aims to prevent costly iterations between front-end and back-end design teams by predicting potential problems before physical implementation begins.

"We are still focused very much on what we can do in the front end to prevent these situations rather than fix them."

If physical implementation reveals problems that require changes to RTL or microarchitecture, engineers can return to ACI with the relevant feedback (Cognichip does not specify with which file format that feedback must be submitted) and use the platform to revise their designs. Yet, ACI cannot resolve issues that require changes to the physical implementation itself, such as clock-tree synthesis or placement and routing.

"They can come back to our environments to provide additional guidance, additional prompting, additional information," Diamantidis said. "Then based on that information, we can of course perform an adaptation of the design […] if the issue can be addressed in the design itself, then of course we can do that."

Since feedback loops are expensive, yet necessary parts of semiconductor chip development flow, I had to ask that question explicitly, and the answer was that there would be no need for feedback loops with ACI. As the question and response require a lot of minutiae, we've added them in full below.

Anton Shilov: Can ACI ingest physical implementation reports from Cadence, Synopsys, or Siemens EDA tools, identify architectural bottlenecks, revise the microarchitecture, and RTL, and repeat the process until the design meets its PPA targets?

Stelios Diamantidis: Actually, this is where we depart from conventional approaches. We do not need to wait until physical implementation to identify these issues. We have trained models with full physical-stack visibility, which enables them to predict PPA during the front-end design phase.

For example, suppose you have one design that operates at a certain frequency and consumes a certain amount of power, and another that runs perhaps 20% slower but consumes significantly less power. We can identify these trade-offs before physical implementation.

Ultimately, the changes you want to make involve RTL and design constraints. Traditionally, engineers develop the RTL and constraints and hand them over to the physical implementation team. That team implements the design and reports the results. If the design fails to meet its targets, the front-end team must make changes, and the process starts again.

These iterations are very expensive in terms of time because they cross design boundaries and involve tools with long runtimes.

By training our models on the full physical stack, we can now provide immediate feedback to front-end designers. For example, we might tell an engineer: 'If you want to reduce power consumption at the cost of 10% of your frequency, take two FIFOs that serve different functions, combine them into one, and time-multiplex the two functions over that FIFO.'

That is just one example of a microarchitectural decision. We can make these trade-offs visible to designers in essentially real time because our models can predict their impact on downstream parasitics, routing congestion, and other physical characteristics.

As a result, engineers can make these decisions in a closed loop during front-end development. Once they have resolved the microarchitectural trade-offs and produced well-structured RTL, they can hand the design over to the physical implementation team. Of course, the design still has to go through physical implementation tools.

Our expectation is that there will be no need to return the design to the front-end team because it failed to meet its targets or encountered congestion problems. That is the fundamental change we aim to bring to the transition between front-end and back-end chip development.

Third Party IP? No problem

Modern SoCs typically combine proprietary logic with third-party IP, including processor cores, memory controllers, interface IP, and other reusable components. However, developers do not necessarily have access to the RTL of licensed IP blocks, and licensing agreements may restrict how such information can be used. This raises the question of how ACI can integrate third-party IP without access to its internal implementation.

According to Cognichip, this is not a problem. ACI does not need to examine proprietary RTL to integrate an existing IP block into a larger design. Such IPs provide relevant interface specifications, including pin connections, signals, and their characteristics. ACI can then proceed with necessary integration logic and connect the IP to other subsystems.

"Most people want to take […] third-party licensed IP and optimize the integration of the IP," claims Diamantidis. "We ourselves do not ingest the guts of the IPs, nor do we try to train on any kind of data related to the IPs."

The CPO of Cognichip stressed that ACI Enterprise protects customers' IP within the company's firewalled data centers and prevents it from entering third-party AI training pipelines. The platform provides customer-controlled access to sensitive information, multi-tenant isolation, and security controls validated through a SOC 2 Type II examination. However, these protections do not supersede the licensing restrictions imposed by third-party IP providers.

A new offering

Cognichip's ACI technology could substantially improve chip development productivity by automating labor-intensive tasks such as architectural exploration, RTL development, verification, and PPA optimization.

The company's benchmark with a major chip designer suggests that the potential gains could be considerable, although the complexity of the project remains undisclosed. Such capabilities could be particularly valuable for startups and newcomers to the semiconductor industry, which tend to lack engineering resources and extensive IP portfolios of established chipmakers. By reducing the time, costs, and expertise required to develop custom silicon, ACI could lower the barriers to entry and enable smaller companies to pursue a custom silicon strategy that would otherwise be prohibitively expensive.

However, Cognichip has yet to demonstrate autonomous development of a complete, physically validated chip, let alone a sophisticated CPU or GPU. The company does not perform physical implementation, and its expectations of eliminating costly feedback loops depend on the accuracy of its PPA predictions. It also remains to be seen how effectively ACI can optimize complex SoCs that combine numerous proprietary and third-party IP blocks under common power, performance, and area constraints.

Ultimately, the Cognichip technology's value for leading-edge chip developers will depend not only on how quickly it can produce verified RTL, but also on how closely its predictions match the results of physical implementation and how much engineering work it can eliminate across the entire development cycle.

Rep. Brian Mast (R-Fla.), the chairperson of the House Foreign Affairs Committee, has said that he will issue a subpoena to Nvidia CEO Jensen Huang if he does not respond to the committee’s request to meet with them on November 18 by Wednesday, November 11, according to ABC News. The House invited him to a “joint, closed-door briefing” with the heads of the House committees on China, Foreign Affairs, and Intelligence, and that they will focus on his company’s “security protocols against foreign adversary espionage.”

Congress first called the embattled CEO on November 7, a few days after rumors started circulating about Huang’s “closeness” to a particular Chinese executive suspected of passing information to Chinese intelligence. The following day, Nvidia released a statement from Jensen admitting to an affair with Megaspeed executive Alice Huang, apologizing for his unfaithfulness, while the company’s board of directors confirmed it will launch an independent investigation regarding the allegations that the CEO has been specifically targeted by China’s Ministry of State Security (MSS). Aside from having to face Congress, Jensen Huang is also reportedly being looked into by the FBI.

It remains unclear whether Jensen Huang was targeted by intelligence agencies, but he came into prominence with the AI boom that was arguably fueled by Nvidia’s AI chips. This led to the AI race as we know it today, with the U.S. taking steps to delay China’s advancement for fears that it will use the technology for military purposes. We also don’t know if Huang Le or Alice Huang is actually a Chinese spy or an “innocent” bystander caught in a web of accusations. And, even if she did work with the MSS, the question remains as to whether she specifically targeted the Nvidia CEO or whether Chinese intelligence discovered their indiscretion and used that as a convenient tool for blackmail to extract information from her.

However, former CIA agent Darrel Blocker told ABC News that the authorities should just focus on Jensen. “I think that the biggest concern is that the focus or overfocus on just Jensen Huang and Nvidia risks losing sight of the fact that other people have been targeted by the Chinese. Are they talking to the engineers? Are they talking to other people who might have even more access than even the CEO has? So, this focus should not be singular; it should include everyone in the company, and quite frankly, every tech company out there should be looking at all the contacts that their officers and employees have.”

“It’s definitely not a one-time thing. When you run a trillion-dollar company, you know that you have a bullseye on your back; whether it’s from competition or rather from nation-states, so this is absolutely not a one-off. Jensen Huang is not the only person at Nvidia that has access to the crown jewels, so I would be looking at the other people in terms of the access that they enjoy and their proximity to Chinese nationals.”

A team led by Cyanogen co-founder Kirt McMaster has unveiled Kora, a new Linux desktop OS with integrated AI models and agents that can split workloads across CPU, GPU, and NPU resources, as well as other machines on the same local network. We reached out to the firm for more info.

Kora, the first product from Kora Systems Inc., previously Playtron, carries the tagline “The Operating System for Intelligence” and has its own Cortex “hybrid inference engine” technology, which is not open source and is optimized for local models. The OS, built “from the kernel to the shell,” runs local models by default and cloud models when needed, and is expected to arrive on PCs in 2027.

The desktop follows the AI-focused motif with “neural workspaces” and a “neural file system,” which refer to sandboxed workspaces and files indexed by semantic meaning. Kora has three operating modes: “Work," "Create," and "Play." That last base is covered by GameFrame, which descends from Playtron’s GameOS. Humain OS, which Kora is developing with Saudi AI company Humain, is the enterprise variant of this OS.

Currently, the only NPU named in the release material is the Hexagon NPU found in the Snapdragon X2 Elite, which Qualcomm pegs at 80 TOPS. On the X2 Elite, Cortex can schedule AI workloads across the CPU, GPU, and NPU, as well as other systems on the local network, which could be a novel capability if it works beyond the Qualcomm hardware.

McMaster told Tom’s Hardware that the Snapdragon X2 Elite NPU runs Google's Gemma 4 26B model at 25 tokens per second for decode. Intel and AMD NPU support is in the works, but according to the developer, neither NPU will be used for LLMs, as GPUs are “just better for LLM workloads on x64.”

Each NPU vendor has its own software stack, or runtime, and prefers that models are compiled in its own format: Qualcomm with QAIRT/QNN, Intel with OpenVINO, and AMD with Ryzen AI software. The press kit doesn't identify support for any Intel or AMD chip, NPU runtime, model format, quantization, or speed figures for those platforms.

Our earlier Windows testing showed the same kind of divide: Snapdragon reached its NPU through the QNN provider under ONNX Runtime, while Intel’s work ran through IPEX, its extension for PyTorch, on the GPU because it was faster than the NPU.

When asked about cross-vendor support, McMaster reiterated that “only Hexagon on Snapdragon X2 Elite is supported today.” Intel NPU support is planned, with “conversations underway,” though McMaster later clarified that neither Intel’s nor AMD’s NPU will be used for LLMs. On AMD’s Ryzen AI chips, Kora will likely use the NPU for embedding and speech-recognition models through ONNX.

As for what drives the Qualcomm Hexagon NPU, McMaster said Kora uses the “llama.cpp Hexagon backend” and “the upstream FastRPC driver.” That suggests the operating system reaches the NPU through the open-source llama.cpp project, not Qualcomm’s own QAIRT/QNN runtime, by way of the FastRPC driver in the mainline kernel.

When asked about model formats, McMaster said, “we predominantly support GGUF,” llama.cpp’s model file format, and that Lemma, the inference engine inside Cortex, “can split model layers across processors as needed.” Lemma is built on llama.cpp, whisper.cpp, stable-diffusion.cpp, and ONNX. McMaster says that which runtime is used depends on the model's requirements, and more runtimes will be added down the line.

For today, llama.cpp has a Hexagon backend for Snapdragon and an OpenVINO backend for Intel CPUs, GPUs, and NPUs, although the latter is still marked “In Progress,” and no AMD NPU backend, which would explain why AMD goes through ONNX. AMD NPUs can run LLMs on Linux through the separate Lemonade 10.0 stack with FastFlowLM, as reported by Phoronix in March, though that isn’t the route Kora has chosen.

Beyond NPU stacks, those hoping to run Kora will need to be mindful of their system's available memory. The Gemma 4 26B model Kora uses, which Google lists as Gemma 4 26B A4B, needs about 14.4GB of memory to load its weights at 4-bit (Q4_0) quantization, by Google’s estimate, before any context window, while third-party listings put the download for the Q4_K_M file Kora uses at about 16–17GB. The model only activates about 4 billion of its 26 billion parameters per token but still needs to be fully loaded into memory.

McMaster said that with the model, the X2 Elite reaches “25 TPS decode throughput and 550 TPS prefill throughput,” or tokens per second, running “entirely on the Hexagon NPU with 32K context.” A dense model, rather than a mixture-of-experts, would be far slower. Not given are the RAM configuration or the specific X2 Elite chip.

On memory, McMaster said that “we recommend 64GB because it gives you access to better models,” but that is not a firm requirement. The company projects that “about 70 percent of the model calls it manages will run locally in 2027.”

Kora says its enterprise-focused Humain OS is due first and will be “commercially available in 2027,” on OEM PCs using the Snapdragon X2 Elite. Kora will follow "later in 2027.”

McMaster says that “Kora will be posted on our site and downloadable for anyone to install.” Included will be a list of recommended configurations, “but it should be installable on most modern PCs.” Exact pricing and the overall business model will be shared closer to the date of availability.

Edit: 11/11/2026 9:06am PT: Added further follow-up details provided by the maker.

The Linux Kernel is probably one of the best ecosystems to observe regarding the impact of AI in programming. The critical importance of its code and its maintainers' quality standards mean that patches, including but not only AI slop, go through rigorous review and are often discarded. Still, the amount of AI-produced code is often far higher than what the human reviewers can deal with. Lorenzo Stoakes, a lead Linux reviewer for memory management, has elected to step down from some of his former duties for exactly that reason.

Stoakes announced his decision today in a thread on the Linux kernel mailing list (LKML). He'll be leaving the core, reclaim, Rust, THP (Huge Pages), and miscellaneous sections of the kernel memory management section, while staying on for his remaining duties, including KVM. The partial departure appears amicable, and the developer doesn't appear to be angry or bitter. He says that his decision was due to the mounting pressure on his inbox, that he'll wrap up the patch series he's currently working on, and he'll occasionally pitch in regardless.

However, the underlying cause is also clear: "Of course the AI wave has been horrible, and is getting significantly worse. At first it was once in a while that I'd see slop. Then it was at least once a week. Then every few days. Nowadays it's pretty much half of what I see, if not more."

This is a sentiment echoed by many programmers in the open-source community, and the latest in a running series of AI-provoked project departures, submission rules adjustments, and strategic shifts. AI-assisted programming has arguably been both a boon and a curse for open-source software. The project's open nature means that anyone can find a bug and report it or fix it, or add functionality — all of which are good things.

However, that also means that literally anyone can contribute, and in a world ridden with low-effort AI slop and untold amounts of AI agents, that's... suboptimal. Open-source projects are arguably the hardest-hit because they very rarely have the adequate manpower or funds to keep the code up to date, much less deal with the output of a million robotic monkeys on a million digital typewriters.

Linus Torvalds, creator and headmaster of Linux, has taken a pro-AI stance, supported not only by the speed of additional contributions, but also the fact that bots often don't make mistakes that even seasoned developers do. This topic has been the subject of a lot of LKML discussion, and the current stance is that AI-assisted code commits don't need to be marked as such.

The problem, then, has arguably become one of filtering: it's easy enough to be accepting of AI contributions when your day isn't spent waddling through mud to find the one gold nugget, which is what Stoakes was seemingly weary of.

Back in July, he'd already brought up concerns about the "recent wave of slop in [memory management]," adding that "the amount of time wasted on AI slop is already too much and we're only at the start of this." Even as recently as a month ago, he said that "what kills the project is having 1,000 slop submissions that 2 or 3 people have to do something with."

In June, AMD overtook the predictive memory engine known as MEXT, which claims to offer upwards of 99% of the performance of a system with full DRAM capacity while running with as little as 25% of the physical DIMMs. The technology offloads cold memory pages to flash storage and uses an AI model to serve pages before they’re needed, and AMD says it plans to extend the tech across a wide swath of its IT infrastructure next year.

The pitch behind MEXT seems too good to be true. According to AMD and MEXT founder Gary Smerdon, the technology can cut the physical DRAM required in a server by 20% to 75% depending on the application and performance target. That missing memory still registers as installed DRAM to the OS. Instead of DRAM, however, MEXT uses relatively inexpensive flash storage to offload cold pages, flying them back in as they’re needed with an AI model. In some of AMD’s internal workloads, such as Synopsys PrimeTime, the company says it’s able to achieve 95% of the performance of a full server while running at 50% DRAM capacity with MEXT.

AMD has deployed MEXT internally on 145 servers, which it says will expand to 2,000 servers next year. In addition, the company has announced a partnership with HPE to bring MEXT to customers. Currently, we’re in phase 1 of the rollout, with some EPYC Venice servers carrying a “MEXT Ready” badge and a dedicated NVMe drive or bay for the offload. Phase 2 brings MEXT licenses out to these servers, as well as the RAM View application. AMD hasn’t said when Phase 2 will begin.

The AI-driven DRAM pricing surge impacts more than just gaming PCs, with enterprises also feeling the brunt of price increases, even if they aren’t running AI workloads. If MEXT is able to achieve what AMD claims, it could be transformative given the current market. Because of that, it’s worth understanding what exactly MEXT is, as well as what AMD claims it can do.

Although MEXT is exciting in concept, it’s obvious that AMD is taking a conservative approach to the rollout. Extraordinary claims require extraordinary evidence, after all. The applications of MEXT are currently narrow, though AMD says it’s expanding the workloads it’s using MEXT on with promising early results.

DRAM, Flash and an LLM

The basic setup of MEXT is simple in concept: cold pages go to flash, AI brings those pages back as needed, and it’s as if the memory was never missing in the first place. The main problem should be obvious. Flash is orders of magnitude slower than DRAM, so streaming pages back into memory from flash as they’re needed isn’t feasible. MEXT’s trick is using an AI model to predict the pages you’ll need. And, as long as the model is able to stay ahead by at least the transfer latency from the SSD, it’s as if the physical DRAM was installed the whole time.

This isn’t a crazy concept considering how a transformer-based LLM, which MEXT uses, operates. If you’re unfamiliar with the inner workings, this open-source visualization breaks down the concept of a transformer AI model cleanly. The foundational concept is next token prediction, which underpins the design of modern LLMs. Given a set of tokens, the LLM determines which token (word, portion of a word, etc.) is most likely to come next. It makes a prediction. In the case of MEXT, it’s predicting what page is needed next, not what word comes next.

Memory offloading to flash isn’t a new concept, but MEXT founder Gary Smerdon says that AI is the critical difference in this technology. MEXT itself is deployed as a Linux kernel module that works with any Linux distro. It uses an “ensemble of AI models,” with the primary transformer-based LLM driving the technology. And critically, it doesn’t come pre-trained.

Instead, AMD says that MEXT trains in under a second when first deployed, operates on one EPYC core without a GPU, and continually trains as the workload progresses. This approach makes sense given the varied workloads that MEXT may apply to. The idea is that it would learn the access patterns of the application in order to drive that prediction engine.

MEXT isn’t perfect, but it doesn’t need to be perfect in every situation. For instance, the order of stored pages isn’t important. With text, an LLM needs to predict the correct text in the correct order, but with MEXT, the order doesn’t matter. As long as the page is in DRAM when it’s needed, that’s fine.

In order to understand the application of MEXT to different workloads, AMD has developed RAM View to go alongside the tech. It’s a memory utilization tool that shows which pages are hot and which have gone cold. As you can see from the example above, a system with 1.5 TB of memory shows near-full utilization across the full workload, but around half of the pages stored in memory haven’t been touched in five minutes or more at any given time.

AMD provided this generalized example and didn’t clarify what workload it was testing. That’s very important, as the utilization breakdown will look vastly different depending on the application(s) running on the server. Initially, AMD is applying MEXT to critical EDA applications it uses internally, such as Synopsys PrimeTime, but the company says it has focused on optimizing agentic AI, database, and media and entertainment workloads as well.

This is important not only because memory access patterns change between applications, but also because performance in those applications reacts differently when a system doesn’t have enough memory. The “memory wall,” as AMD calls it, should be a familiar concept regardless of whether you’ve ever touched a server. With MEXT, AMD says it’s trying to extend this memory wall, which may look different for different applications.

For instance, the company is confident that many workloads can reduce capacity by around 20% to 25%. As the reduction increases, however, the applications become more specialized, and the performance delta becomes greater.

AMD’s internal MEXT results

AMD has shared some internal MEXT results, which look impressive, though as usual, it’s always smart to handle first-party benchmarks like this with skepticism. Starting with PrimeTime, where AMD has focused much of its attention on MEXT up to this point, it says servers running at 50% capacity retain 95% of the performance of a full server, and going down to as little as 25% capacity still maintains 80% of the application’s performance.

PrimeTime demands a lot of memory for large designs. There are some applications where performance is nearly identical, according to AMD. In a 3-node cluster running in Azure with 5th-gen EPYC CPUs, AMD says MEXT offers 99% of the performance of the full cluster while running at 50% DRAM capacity with the Spark SQL workload from the TPC-DS benchmark. SQL databases try to cache as much data as possible in memory to prevent I/O bottlenecks, creating a golden opportunity for tech like MEXT that wants to free cold pages.

Perhaps the most applicable workload at the current moment, however, is agentic AI, and AMD says MEXT has similar applications there. Across a five-agent concurrent geomean, AMD claims 99% of the performance of a full server with 50% memory capacity, and 85% of the performance with 25% capacity. With a “memory-hungry” agent, AMD claims 90% and 88% performance for 50% and 25% capacity, respectively.

The slide you can see above has footnote tags. However, AMD has not shared the footnotes with us yet, so we don’t have a view into how these tests were run. Naturally, we assume AMD has, at minimum, represented the performance of MEXT in the best light possible. We can’t do a full analysis without knowing how the tests were run, however.

What is interesting is AMD’s cautious approach to rolling out MEXT. It’s an EPYC-exclusive feature right now, though AMD left the door open for support on future products (consumer devices, such as Strix Halo) far down the road. It will be sold as a license, bundled with the RAM View software, but we don’t have a timeline on when that will happen. And, despite a partnership with HPE to push out “MEXT Ready” servers, we still don’t know when MEXT itself will be ready for deployment beyond AMD’s walls.

Given that conservative approach, there are likely pitfalls to MEXT that we’re not seeing yet, and it’s hard to imagine it will be broadly applicable to every server, at least at the 50% and 25% DRAM capacity levels that AMD showed off with its benchmarks.

However, even being able to trim 25% of a server’s DRAM capacity represents a massive cost savings in the current supply-constrained environment. If some workloads can push that to 50% capacity, that’s even better. Of course, we’ll need to see how MEXT holds up once it’s available broadly, but if AMD’s claims hold water, it could become a defining technology in data centers that can’t seem to get enough memory.

Hoto has a number of useful tools for builders, makers, and hobbyists, and it's a brand that Tom's Hardware staffers have come to trust, with several of us owning a Hoto screwdriver. A great deal on Hoto's cordless rotary toolkit means you can grab it for just $31.99 right now, as long as you apply the on-screen coupon, which'll save you 36% compared to its list price.

● Check out this deal on Amazon

This wireless Hoto rotary tool includes a five-speed motor, fully adjustable with speeds from 5,000 to 25,000 RPM. It's lightweight, weighing just 240 grams, with a design that makes it small and nimble enough to use for any detailed projects you have, whether it's DIY around the home or making products in your workshop, especially with a 3D printer handy.

It has a 2,000 mAh battery, making it portable, with up to 50 minutes of continuous use on a single charge. To charge it, you can use the supplied charging dock with a USB-C cable.

Along with the rotary tool itself, you've also got 35 additional accessories. These'll let you use it for sanding, polishing, drilling, carving, and cutting: a versatile set for any maker at home. There's also a special nail grinding attachment to help you trim the nails on your pets at home. It has support for 3.2mm and 2.3mm collets, common sizes for other rotary tool accessories, making it fully compatible with those.

You've also got a snap-on dust cover to help contain any dust created and to protect your face while you're working. There's also an integrated LED light, which can help illuminate your workspace as you're using the tool, especially if you're working in otherwise dim conditions.

To get this Hoto cordless rotary toolkit at its $31.99 sale price, you'll need to make sure to tap or select the on-screen coupon. That'll apply the discount before you add it to your cart. If you're a maker yourself, or just buying for one, the 36% discount here is a bargain you won't want to miss out on ahead of the holiday season.

Starbase, Texas, which hosts SpaceX’s Starship rocket program, has just posted a notice of a public hearing for a gas-fired power plant and supercomputing facility within the corporate limits of the city. The project has an initial cost of $24 billion and will apparently be owned by SpaceX. Bloomberg reports that the project could face resistance from incoming Texas governor Gina Hinojosa, who campaigned against approving new data centers until the state's legislature has enacted stronger protections against potential harms from those projects.

Until now, Elon Musk's SpaceXSI has been building out its Colossus I and Colossus II data centers near the Mississippi-Tennessee border, but those projects have faced backlash, attracting a lawsuit from area residents that aims to curb the pollutants produced by the large number of gas turbines required to power those facilities.

Now, it seems that SpaceXSI wants to build another site in Texas that would lie in a city that mostly sits on land owned by SpaceX and whose population mostly comprises its own employees. The project might face reduced local opposition compared to the company's Memphis facilities, as Starbase is essentially a company town for SpaceX. But Hinojosa's arrival in the governor's office could trump that seemingly permissible local regulatory climate.

The project would seem to be a part of SpaceX’s push to build 10 gigawatts of compute in 2027 alone, and the $24 billion budget for this new facility could make it one of the biggest and most expensive data center projects focused on a single site. The company's announcement also notes that the $24 billion outlay it foresees was only for the “initial phases of the projects” and that it could “include future expansions.” That suggests that SpaceXSI could invest in more capacity in Starbase, Texas, going forward, assuming the favorable regulatory climate the company likely hoped for in the area holds.

Beyond its new terrestrial ambitions in Starbase, SpaceX also remains hard at work on launching data centers into space. Musk has already laid out the plans for a first-generation AI1 compute satellite with a 150kW peak compute payload, and submitted a proposal to build a 1-million-satellite Orbital Data Center System to the FCC. That work could accelerate after data center measures lost big in the poll in the recent U.S. midterm elections. In a post-election post on X, Musk ventured that “data centers in space looking pretty appealing right now.”

Russia’s 2022 invasion of Ukraine sparked a new era of drone warfare. Russian invaders first used drones with fiber-optic tethers to combat electronic warfare on the front lines, but both sides now use these jam-proof drones. Against that backdrop, the AI data center buildout is making it harder for Ukraine to buy the fiber-optic spools that it needs to continue scaling its drone manufacturing capabilities. A research and development representative for BlueBird Tech, a Ukrainian defense firm specializing in drones, told Ars Technica in an interview that prices of fiber optic cables have risen around six to 10 times in the past couple of years as AI data center demand soaks up more and more of the supply of this resource.

According to that interview, It’s estimated that Ukraine and Russia are producing around 50,000 fiber optic drones monthly, with each drone capable of ranges of up to 62 miles. But Ukraine has only been able to acquire 72 miles of fiber optic cable from Chinese suppliers during August 2025, whereas Russia imported a whopping 328,000 miles during that same month. It was estimated that Russia acquired 37 million miles of fiber during the entirety of 2025, accounting for over 10% of the global production.

What makes matters worse for Ukrainian defenders is that there is an estimated 111-million-mile shortfall in fiber optic cable supply across the world, adding to the various shortages that the data center industry has faced in recent years. Aside from the material shortfall, Ukraine faces trade barriers in acquiring more fiber. The BlueBird representative claimed that some Chinese companies have outright refused to sell Ukraine fiber optic cables.

China is the primary supplier of this material, so it’s easier for Russia to obtain them through its massive land border with the country. While Ukraine could purchase fiber optic cables from suppliers located in other countries, that's not much of an alternative. The BlueBird rep notes: "there can be intermediaries in other countries, and prices can differ depending on the country and the purchasing route. But in the end, China remains the main source of the fiber optic material we are talking about.”

There has also been talk of producing fiber optic cables domestically in Ukraine, but such manufacturing requires specially trained personnel who must practice on the already limited supply of fiber optic cables. Even if manufacturers automate production, they still require experienced personnel who can oversee the line and ensure the quality of the final product.

The data center build out has been causing all kinds of shortages. We’ve seen supply shortfalls in GPUs, memory chips, and even PCBs, but there’s also shortages in other seemingly unrelated industries like power infrastructure, optical transceivers, and even in critical skilled labor like electricians. This overwhelming demand has started affecting other industries not related to computing, like cars, home construction, and now, fiber optic attack drones.

Newegg is one of the best places at the moment for deal bundles on otherwise expensive PC parts for a new gaming PC. With that in mind, you can pick up a brand-new AMD Ryzen 7 9950X3D with 32GB of DDR5 RAM and an Asus TUF Gaming X870E motherboard for $1,059.98.

● Check out this combo deal at Newegg

This deal saves you $128.99 compared to buying the parts separately. You're also getting a free Rosewill 360mm AIO liquid cooler thrown in for free, worth $89.99. More importantly, however, is the RAM. With this deal, you're bringing down the effective cost of the memory to just $351, or less if you count the free cooler.

Buying this RAM separately would cost you $479.99, while the cheapest 32GB DDR5 kit on sale anywhere right now is $438, so you're paying $87 less for RAM compared to what you'd have to pay elsewhere. That's a great deal considering how expensive RAM has become over the last year, especially if you need to build or upgrade your rig today.

The AMD Ryzen 7 9800X3D is no longer the fastest gaming CPU on the market, but it's still our favorite, with performance that's almost impossible to beat. It ships with eight cores, 16 threads, and a boost clock speed up to 5.2 GHz. The important stat, though, is 96MB of L3 cache. This is AMD's all-important 3D V-Cache technology in action. The extra cache provides a huge frame rate boost by giving the CPU more memory directly.

There's less need for it to drop down to slower system RAM while you're gaming, making frame rates higher and more stable. As the Bench charts below show, this is a CPU that, despite being marginally pipped to the post by newer CPUs like the 9850X3D, is still an absolute powerhouse for gamers.

Along with this world-class processor is a solid set of RAM for your rig. The V-Color Manta XSky RAM included here is a popular one among these Newegg bundles. You're getting two 16GB memory modules to run dual-channel, and it's fast DDR5 CL30 RAM, rated at 6,000 MT/s, with RGB lighting that you can configure. RAM prices are showing no signs of cooling, so getting RAM for nearly $90 less than you'd be paying elsewhere is a worthy option if you're building or upgrading a new PC.

Along with the RAM is an Asus TUF Gaming X870E-Plus WiFi 7 motherboard. This is an enthusiast-friendly board that's packed with a whole host of gaming features. Ready for an AM5 build, this motherboard has 13 USBs at the rear, including two USB-C ports that are rated at speeds of 40 Gbps. You're also getting four M.2 sockets for plenty of SSDs, and with the 9800X3D installed, two of them are rated for PCIe 5.0 speeds over four lanes. There's fast networking, with 2.5 Gb Ethernet and Wi-Fi 7 support included.

A nice extra, too, is that Rosewill AIO cooler. Worth $89.99 if you had to buy it, this 360mm cooler will help to keep your CPU cool, with three RGB fans and a built-in display that can show you your CPU's temperature, fan and pump speeds. No cost here: this one comes with the bundle for free.

Overall, the $1,059.99 sale price for this Newegg parts bundle means you're scoring a top-spec CPU with better-priced RAM than buying it separately before we even consider the motherboard and free CPU cooler. The $128.99 discount here isn't one you should ignore given current market prices, but with these bundles selling out fast, you'll need to be quick to secure it for yourself.

u/Motor_Attention1865 on Reddit didn't like how his PC added extra heat to his room in the winter, so he went the extra mile to dump the heat outside in a fashion similar to mini-split air conditioners. The external cooling system is controlled by an Arduino Mega that the PC communicates with when it needs extra cooling. The system opens a three-way valve to route coolant outside and prevents condensation by keeping the coolant temperature above the dew point.

Our intrepid modder's room has heated floors, and the PC was dumping too much heat under the table where his PC sits, even in 25 °F (-4 °C) weather. He grew tired of manually opening a window to regulate the temperature in his space, so he put in much more effort to create a split cooling system that puts another radiator outside in the below-freezing temperatures, cooling down the PC significantly.

Motor_Attention1865's build itself is impressive enough, with a delidded Core Ultra 7 270K Plus cooled by a Thermal Grizzly 1851 Mycro Pro direct-die water block with Thermal Grizzly Conductonaut Extreme liquid compound. Not only is his RTX 4070 Ti Super also watercooled with a Bykski water block, but the 2x24GB DDR5-8400 G.Skill RAM is also watercooled using Bykski heat spreaders with an IceManCooler two-channel water block. The cooling system within the PC has two radiators: a 120mm in the back and a 360mm in the front, all fed by an EK Kinetic D5 pump-reservoir.

The external cooling system, however, is even more impressive. The 240mm outdoor radiator with two Noctua iPPC-3000 fans isn’t outrageous, but the automated system that makes it useful is what’s interesting. Next to the PC is a box with a Bykski D5 pump and reservoir that pushes water outside, but it doesn’t use the external radiator until the PC needs the extra cooling.

Upon startup, the PC runs a Python script that communicates with an Arduino Mega connected to three temperature probes checking the coolant temperature and three more temperature and humidity sensors that monitor the PC case and the ambient air. The sensors give the Arduino Mega information on where to switch the motorized three-way valve depending on the temperature and humidity.

The problem with extreme cold in any PC is condensation. If coolant gets below the dew point of the environment, condensation forms, potentially shorting out PC components. To prevent this disaster, the Arduino determines the dew point based on the humidity and temperature of the room and in the PC. Motor_Attention1865 set the Arduino to close off the outside radiator at +10 °C above the dew point, or +5 °C during benchmarking, allowing for low temperatures without risking droplets forming in the PC.

Because of the freezing or below-freezing temperatures at which this external loop is meant to operate, Motor_Attention1865 also added pure ethylene glycol to the Aquacomputer Double Protect Ultra Clear coolant in the loop, lowering its freezing point from -18 °C to -28 °C.

Thanks to the supplemental cooling system and delidding, the system achieves temperatures below 50 °C under heavy use. According to Motor_Attention1865, the RTX 4070 Ti sits at 37 °C and the CPU hovers around 45-50 °C while gaming. Temperatures were higher in benchmarks, however — in Cinebench R23, the CPU sat at 52 °C, while in 3DMark Steel Nomad, the GPU was at 48 °C.

Above all, however, Motor_Attention1865 no longer needs to bother himself with opening a window if their room gets too hot with the PC under load. It's the small things.

Submarine AI laser robots have been a surefire success for Norwegian salmon farmers, according to the most recent annual report from the aptly named Stingray Marine Solutions. The Oslo, Norway-based firm now has over 3,500 units deployed around salmon pens along the Norwegian coast, protecting over 112 million fish. Stingray deployments are up by about 1,000 over the last year. This operation has grown to become one of the largest commercial AI deployments in Scandinavia.

These high-tech AI-enhanced submarines protect 20-25% of farmed salmon in the country, according to the latest figures. Using this high-tech AI laser solution to ‘optically delouse’ the salmon means fish don’t have to be passed through harsh chemical baths to prevent infestations of these tiny parasitic crustaceans. The result is improved salmon growth and welfare, and consistently cleaner fish exhibit reduced mortality.

The video above shows a behind-the-scenes peek at the 250-employee-strong Stingray operation. There’s some colorful laser action with two Stingrays seen zapping away in a salmon pen included in the clip. They use AI to recognize and target the sea lice.

Sea lice are a big problem for fish farmers, with the control of these parasites being a central challenge for the industry. Traditionally, measures such as chemical treatments were used to help control the buildup of sea lice. However, while chemicals can treat a large number of fish simultaneously, they can be bad for the environment, can stress fish, lice can develop resistance, and the introduction of any kind of poison or toxin into food production isn’t usually good for humans either.

In contrast, the Stingray AI laser system identifies and targets only sea lice, works continuously 24/7 as the fish go around normally in their pens, and avoids any chemical introduction or resistance issues. The reduction in sea lice around the farming area is better for other wild fish populations nearby, too.

Solutions like Stingray do have a few drawbacks. Primarily, fish farming businesses might look sheepishly at the up-front costs of deployment. Moreover, it might be best used as a preventative measure, keeping localized lice populations low. The Stingray’s range is limited now by its deployment in the salmon pens, so lice can gather in darker, murkier corners and outside their patrol area.

Microsoft, the tech giant that is building 35 data centers around the U.S. and has plans for 134 more, has reportedly met with the White House Office of Science and Technology Policy and the National Security Council as the FCC is considering an import ban on Chinese optical transceivers. According to Reuters, the company, alongside the Information Technology Industry Council (ITI), is lobbying against the move.

“It really threatens to arguably grind (the data center rollout) to a halt,” ITI Executive Vice President of Policy and General Counsel John Miller said. He also added, “Those chips, without optical transceivers, literally could just sit there waiting around unutilized until you actually have the transceivers to essentially connect them together,” referring to the AI chips that data centers use.

Optical transceivers are tiny modules plugged into hardware that convert their electrical signals into light signals, allowing data to be transmitted as light pulses across fiber optics. Data centers increasingly use optical transceivers and fiber optics to transmit data between AI GPUs and server racks, as they’re faster, offer lower latency, require less power, and generate less heat compared to traditional copper connections. However, Chinese companies currently supply 66% of the global market, meaning banning them from supplying data centers in the U.S. would more than halve the available supply, thereby exacerbating the various shortages that have been pummeling the industry.

However, there are concerns that some of these transceivers could be compromised by Beijing and be used to steal data, install malware, or remotely disrupt American data centers, which is why the FCC is considering the restriction, just like how it banned Huawei from the U.S. telecommunications network. But unlike Huawei, which had many established competitors in the telecommunications hardware industry, only two U.S.-based companies produce optical transceivers that data centers need — Coherent and Lumentum. While these firms could produce optical transceivers to compete with Chinese offerings, they simply do not have the scale to make up for the shortfall if the FCC bans Chinese imports today.

One compromise floated by the Trump administration is that it would only ban Chinese optical transceivers capable of hitting 3.2 terabits per second. While this technology already exists, its production isn’t expected to expand until 2028, with installation not beginning until 2029. This should give American producers time to ramp up their own output, although the suggestion is still under consideration.

Two prominent voices within AMD agree that the company didn’t design its new Zen 6 family, codenamed Venice, explicitly for agentic AI in a clear shot at Nvidia and Arm, who’ve both described their latest data center CPUs as “agentic” in nature. In separate talks, AMD’s chief Zen architect Mike Clark and corporate VP Madhu Rangarajan said that the company didn’t predict the agentic wave when Zen 6 development started.

We just wrapped up testing AMD's Venice CPUs, which you can read more about in our Zen 6 benchmarking article.

CPU development cycles are measured in years, and given that the agentic frenzy around CPUs hit around March of this year, it’s unreasonable to expect that anyone has developed silicon specifically for agentic AI, much less a general-purpose data center CPU. And still, Nvidia claims its Vera CPU was “purpose-built” for agentic AI, while Arm says its AGI CPU was “designed for the demands of agentic AI.”

“We think that the EPYC 9006 CPU is the best CPU for the agentic era, and spoiler alert, we didn’t magically know four years ago that agentic was going to be a thing and purpose-built something for agentic,” said Rangarajan in a session with media. “The reality is an agentic workflow is a diverse set of tasks… and in order to execute those tasks well, you need compute that is able to handle a diverse set of workloads with a full portfolio.”

Introducing the Zen 6 microarchitecture, Mike Clark agreed with the sentiment: “I’m not going to mislead and act like I knew agentic computing was coming, or we knew it, but we did strongly believe that the CPU would always have a place in the software ecosystem of AI… And as agentic [has] blown up, we [are] able to now deploy that for agentic compute workloads.”

As AMD rolls out its next-generation microarchitecture with Venice CPUs, it’s targeting the messaging from Arm and Nvidia, which have posed the most direct threat to AMD’s continued rise in the data center on the back of agentic workloads. And indeed, there are performance vectors where Nvidia’s Vera looks strong for agentic workloads, as you can see in our Nvidia Vera testing. AMD’s argument, however, is that agentic AI calls for a broad range of CPUs just as general-purpose workloads do, pushing back on the single-SKU approach of Nvidia and Arm.

Our testing of two AMD Venice chips supports that argument, as well, with the dense EPYC 9996 with its 256 cores and 512 threads offering peak throughput performance, while the frequency-optimized EPYC 9686F goes toe-to-toe with Vera in the role of an AI host node. AMD is launching two additional ranges next year, with Venice-X targeting HPC with its 3D-stack cache, and Verano going directly after Vera as an AI host node with an LPDDR5X memory system.

Although the workload characteristics of agentic AI are still in the process of being defined, we have a better understanding of how those loops work now than we did at the beginning of the year. And like all complex topics, the answer to what is important in a CPU for agentic AI is the always-disappointing “it depends.”

As we break down in our early testing procedure for agentic AI, the workload characteristics and demand on the CPU/memory are defined by what the agent is doing, and in the data center, what several agents are doing at high concurrency when sandboxed. A coding agent will generally call more tools that are taxing on the CPU than a web browsing agent, for example, while an agent that queries a database may call for strong memory performance.

Of course, there are some vectors of performance that can’t be addressed with different SKUs (such as that strong memory performance). However, the potential diversity of agentic workloads certainly makes an argument for CPU variety. At a most basic level, an agentic loop allows the LLM to understand functions you’ve defined, and then pass arguments to those functions to execute them. We’re talking about a workload as broad as what you can define in a function in languages like Python and Rust.

AMD’s EPYC ‘Venice’ CPUs are the first to debut the new Zen 6 architecture, and we’ve been testing two chips from the range over the past several weeks to see how they compare to Nvidia’s Vera, and more broadly, how the Zen 6 architecture departs from Zen 5 ahead of the expected consumer-focused Olympic Ridge launch next year. Zen 5 was a ground-up redesign of AMD’s storied Zen core, and Zen 6 takes that foundation and expands it in just about every regard.

Zen 6 uses TSMC’s N2P node, but it also comes with significant architectural changes under the hood. Within the core, a redesigned vector engine pushes AMD’s SIMD performance even higher, and it now natively supports half-precision FP16 instructions alongside full, 32-bit precision. It also splits integer schedulers within the execution engine, allowing for more instructions in flight through the core.

Across the die, AMD made other significant changes. The single IOD of previous generations is now split across two IODs, giving the SP7 platform access to 16 memory channels (though at the cost of PCIe 6.0 lanes compared to the previous generation and SP8 platform).

The CCDs have been upgraded, too, for the first time since Zen 3. A standard Zen 6 CCD can now scale up to 12 cores, while a Zen 6c packs 32 cores. With Zen 5 and 5c, CCDs topped out at eight cores and 16 cores, respectively. For the Zen 6c CCD, AMD also doubled the amount of shared L3 per core, which effectively quadruples the L3 compared to Zen 5c, since the CCD packs twice the number of cores.

Interestingly, Zen 6 is neither a marginal optimization to Zen 5, nor a complete architecture redesign. Stepping back, it looks like AMD pushes as many dials as it has access to to their highest level, and that holds up looking at performance.

The 256-core EPYC 9996 delivers 1,024 threads in a 2P configuration, which came out 93% ahead of the 768-thread 2P EPYC 9965 server we tested in SPEC CPU 2026’s intrate throughput test. The frequency-optimized EPYC 9686F excels elsewhere, notably in scientific computing and HPC workloads, and it serves as AMD’s competitor to Vera, at least before the LPDDR-based Verano platform arrives from AMD next year.

AMD says it believes Venice is fundamentally a generation ahead of the competition, which would be a worthless line if it wasn’t backed up by data. Intel’s Granite Rapids-AP is rarely in the conversation, and although Vera maintains some competitive positions, Venice is often ahead — sometimes orders of magnitude ahead.

Intel’s Diamond Rapids is set to launch next year, which should help balance the scales. But AMD has set an incredibly high bar with Venice, one that it will likely extend even higher for some workloads with the arrival of Venice-X and Verano next year.

There’s a lot to get to here. We have a full deep dive into the Zen 6 microarchitecture, a broader look at the chip itself, the platform(s) AMD is pushing out this generation, and of course, more than 100 benchmarks covering everything from Python performance to HPC.

AMD Zen 6 microarchitecture breakdown

AMD Zen 6 microarchitecture breakdown

The headline for Zen 6 is a 27% average IPC uplift over Zen 5 in enterprise, cloud, and AI workloads. The debut of this new microarchitecture is focused on the data center, so you shouldn’t take that 27% IPC improvement as broadly applicable to all workloads. Additionally, AMD arrived at that number by comparing fixed-frequency Zen 5 to Zen 6c with 16 cores. As we’ll get into in the next section, a Zen 6c CCD can comfortably fit 16 Zen 6c cores with room to spare, while 16 Zen 5 cores are split across two CCDs.

The compute die is built on TSMC’s N2P node, which is an already optimized version of N2 that comes with a 5% performance improvement. Compared to N3E (Zen 5 used N4P), N2P offers an 18% speed improvement at iso-power, or a 36% reduction in power at the same speed.

AMD described Zen 5 as a ground-up redesign when the microarchitecture first broke cover in mid-2024, characterized by a wider execution engine capable of dispatching and returning eight instructions per cycle, a wider frontend to feed it, full AVX-512 support, and doubled bandwidth between the L2 and L1 cache. Zen 6 is a continuation of the redesign we saw on Zen 5. It carries many of the same characteristics, as well as the same general topology, just enhanced in a number of ways.

As we go through the breakdown, keep in mind that Zen 6 and Zen 6c use the same microarchitecture. Zen 6c is just a space-optimized design that consumes less power, clocks lower, and, obviously, takes up less die space than a full Zen 6 core. But, the company uses the same microarchitecture inside the core, unlike Intel’s E-cores, which use a different microarchitecture than the P-cores.

Starting with the frontend, it’s largely unchanged from Zen 5, short of a few notable improvements. You get the same dual 4-wide decode pipes and 8-dispatch, but AMD has improved the BPU and op cache. For the BPU, it has a 64-entry Return Address Stack, up from 52 on Zen 5. AMD also increased the op cache size back up to 6.75K entries from 6K on Zen 5 (Zen 4 also had a 6.75K-entry op cache). This larger cache can serve up to 18 micro-ops per cycle, up from 12 on Zen 5.

AMD split the integer schedulers for Zen 6 (Zen 5 had a unified scheduler), now offering higher capacity, with 96 shared ALU/AGU and 48 dedicated ALU entries, compared to an 88 / 56 split for ALU/AGU on Zen 5. AMD also expanded the general-purpose registers to a 352-entry physical register file, up from 240 on Zen 5.

The vector execution engine is also improved, following on the heels of a true 512-bit register in Zen 5. Zen 6 carries forward that 512-bit data path and adds some additional improvements. Notably, the engine now supports half-precision AVX-512 FP16 instructions, which needed to be converted in Zen 5’s vector execution engine. Also notable is the FP load/store bandwidth. Zen 5 supports two loads of any size, but Zen 6 supports either two 512-bit loads or four 256-bit loads. Store bandwidth is unchanged, at one 512-bit store or two 256-bit stores.

Zen 6 carries forward the 48 KB 12-way L1 data cache from Zen 5, along with 1 MB 16-way private L2. The shared L3 is treated as victim cache for the L2, as is the case in Zen 5. However, AMD increased the in-flight window compared to Zen 5, with an 80-entry load queue and 128-entry store queue.

AMD Zen 6 and Zen 6c CCD and platform breakdown

AMD Zen 6 and Zen 6c CCD and platform breakdown

Perhaps the biggest change going from Zen 5 to Zen 6 comes in the density of the CCD. Zen 6 offers up to 12 cores per CCD, up from 8 on Zen 5, while Zen 6c scales up to 32, double that of Zen 5c. Elsewhere, the updated CCDs either match or improve on Zen 5/5c CCDs.

For Zen 6, AMD retained the 4 MB of L3 cache per core, increasing the total cache to 48 MB to accommodate the new 12-core limit. The maximum frequency of a standard Zen 6 CCD has increased from 5 GHz on Zen 5 to 5.3 GHz on Zen 6. Keep in mind these clocks are in the context of Venice; we expect higher maximum boost clocks on consumer Olympic Ridge.

Zen 6c has more enhancements. AMD doubled the amount of L3 per core from 2 MB to 4 MB, matching the normal Zen 6 CCD. And, with double the L3 per core and double the number of cores, the Zen 6c CCD has a total of 128 MB of L3, quadruple that of a Zen 5c CCD. For Zen 6c, the maximum frequency is also up, going from 3.7 GHz on Zen 5c to 4.1 GHz on Zen 6c.

Across both, AMD claims a “large core IPC uplift,” as well as improved power and SMT efficiency. We haven’t seen an overall IPC claim yet, though the numbers referenced above put Venice at about a 27% advantage over Turin in enterprise, cloud, and AI workloads.

In the context of Venice, AMD can fit up to eight CCDs on a chip, coming out to 256 cores in total for Zen 6c, and 96 cores total for regular Zen 6 for SP7 platforms (the initial lineup for Venice). AMD is moving past the SP5 socket available to Genoa and Turin CPUs for SP7, which is a slightly larger socket at 76 x 80 mm (SP5 is ~72 x 75 mm).

The topology of the chip is largely intact from Turin, short of the dual IO dies that characterize Venice. The two IODs live in the middle of the chip, flanked by Zen 6 CCDs. The second IOD is what gives SP7 chips access to 16 channels of memory per socket (8 channels per IOD), supporting up to 12,800 MT/s speeds using MRDIMMs in a 1DPC configuration. With RDIMMs, AMD supports up to 8,000 MT/s. The platform supports up to 8 TB of memory per socket, and AMD claims bandwidth of up to 1.6 TB/s per socket (1 TB/s per socket with RDIMMs).

Also on the IOD, there’s the hardware root-of-trust, as well as AMD’s confidential computing extensions, including execution encryption, memory integrity, and trusted I/O. New to the platform is PCIe 6.0 at speeds up to 64 Gbps per lane. A 1P SP7 configuration has access to 96 PCIe 6.0 lanes, while a 2P platform has up to 128. Each configuration also comes with “bonus” PCIe 4.0 lanes, either 8 for 1P configs or 16 for 2P.

Two 64G SerDes interfaces bring the PCIe lanes into the IOD, one of which is used to link the chips in a 2P configuration. That second interface can still optionally handle an additional 12 PCIe 6.0 lanes, giving the “up to” 128 2P lanes number. The bonus lanes run through a smaller 16G SerDes interface.

Platforms with the SP8 socket trade memory channels for PCIe lanes. The SP8 socket is smaller at 62.5 x 80 mm, and the platform supports eight memory channels instead of 16, though with the same support for up to 12,800 MT/s MRDIMMs. Memory bandwidth drops to 819 GB/s for MRDIMMs and 512 GB/s for RDIMMs at the maximum supported transfer rate.

However, SP8 chips have access to 64 PCIe 6.0 lanes per IOD, for a total of 128 lanes in a socket (plus the additional eight PCIe 4.0 bonus lanes). Just like SP7, some of those lanes are shared in a 2P configuration, dropping the total to 192 PCIe 6.0 lanes in 2P SP8 servers, with 16 additional PCIe 4.0 lanes. Both platforms support CXL 3.1.

AMD also provided a platform breakdown for its upcoming Verano range, which uses the Zen 6 microarchitecture on an LPDDR5X-based platform, leveraging replaceable SOCAMM2 DIMMs.

UPP, UBPS, and FAST in Zen 6 ‘Venice’ CPUs

UPP, UBPS, and FAST in Zen 6 ‘Venice’ CPUs

AMD has added a few quality-of-life features to Venice CPUs that should make them easier to manage when actually deployed. First is UPP, or Unified Power Provisioning, which is a power management feature that takes into account total platform power, allocating it as needed to different components, depending on the workload. With it, AMD says it’s able to deliver a power consumption of 830W on 16 servers to 706W on 18 servers, or a decrease in provisioned power by 15%, while increasing the number of servers per rack.

Also dealing with power is UBPS, or Utilization Based Power Scaling. It’s a dynamic power scaling feature that aligns with whatever workload is running on the server, which AMD says “helps close the gap between provisioned and consumed power.” Like UPP, UBPS is concerned with platform power, not just the power consumption of the CPU.

The most interesting addition is FAST, or Frequency Adaptive Spectrum Technology. The feature takes in telemetry from the platform and policies set in firmware to adjust the frequency within set power and thermal limits. It sounds a little more involved than a simple Precision Boost Overdrive for the data center, however.

AMD described FAST to us as allowing for two performance tiers within one socket. As an example, AMD pointed to a 96-core Venice CPU, saying FAST allows 32 of those cores to run in a “premium” category, with a base clock of 3.65 GHz and a max clock of 5 GHz, while a “batch” category with 64 cores runs at 2 GHz with a 2.4 GHz max. AMD described it as multiple commercial SKUs within a single socket.

Preliminary MEXT support, claims of 95% performance at 50% DRAM capacity

Preliminary MEXT support, claims of 95% performance at 50% DRAM capacity

Venice marks the point when AMD will start offering MEXT on its EPYC platforms. AMD aquired MEXT earlier this year, and it has used the feature internally. With HPE, AMD is rolling out “MEXT ready” platforms, which will, eventually, have access to MEXT licenses. The technology is interesting, especially given how constrained memory is right now.

The general concept of MEXT is using flash as DRAM. Even the fastest flash is orders of magnitude slower than DRAM, but MEXT attempts to take advantage of DRAM access patterns to expose more memory to the system without it actually being there. Pages that haven’t been accessed in several minutes are offloaded to flash storage, and an AI model predicts pages that are needed. Then, those pages are loaded back into memory as you need them.

Conceptually, it sounds too good to be true. AMD pointed out that MEXT is using a transformer-based LLM, and effectively, LLMs are predicting what words go next when generating text. Here, AMD says the bar isn’t even that high. As long as the model can stream the correct pages in, and do so fast enough to cover the flash latency, the order of them doesn’t matter.

MEXT is delivered through a Linux kernel module, and AMD has bold claims about its capabilities. The company has deployed the software internally on 145 servers, which it expects to expand to over 2,000 servers next year. Currently, AMD is using it for critical EDA workflows, such as Synopsis PrimeTime. The company says that it’s able to maintain 95% of the application’s performance on Venice with just 50% of the system DRAM. Going down as low as 25%, the company claims the app maintains 80% of its performance.

We’ll have more on MEXT shortly. The feature is exclusive to EPYC CPUs, and AMD was clear that it only applies to certain workloads right now. There are likely applications where you won’t be able to cut the DRAM capacity of a server, or where you’ll need to use a more conservative cut of 25% or less.

AMD Zen 6 EPYC ‘Venice’ test configurations

AMD Zen 6 EPYC ‘Venice’ test configurations

AMD gave us access to two Zen 6 Venice systems for the purpose of testing, both of which were dual-socket servers. For the first system, we tested the dense EPYC 9996, which is AMD’s high-core-count design, packing 256 cores and 512 threads per socket, for a total of 512 cores and 1024 threads across a 2P system. It’s a peak throughput SKU, designed to handle heavily concurrent workloads.

On the other end of the spectrum, we have the EPYC 9686F, which is still a high core count CPU in its own right, with 96 cores and 192 threads, giving a 2P system 192 cores and 384 threads. The “F” suffix for AMD’s data center CPUs notes a high-frequency SKU, designed to push performance up in more demanding applications, as opposed to the dense, frontend-focused EPYC 9996.

Both chips use AMD’s SP7 socket, which is geared toward data centers, with higher core count SKUs. The upcoming SP8 socket is focused on enterprise customers, with smaller core counts and support for fewer memory channels.

Although the EPYC 9996 is a dense design with the Zen 6c core, it comes with a fairly high boost clock of 4.1 GHz, though a much lower 2.55 GHz base clock, which it will likely be running closer to in real deployments. It comes with a massive 1,024 MB pool of L3 for the chip, as well as a 600W rated TDP, though it can be manually adjusted between 400W and 600W.

The EPYC 9686F proves out AMD’s claims about Venice, serving as one of two chips in the SP7 lineup to boost up to 5 GHz. It has a lower 500W TDP, though it can again run between 400W and 600W. This is the SKU AMD has heavily referenced in its published Venice benchmarks as a “96-core HF” model.

It’s an interesting model, perhaps more so than the EPYC 9996. It’s in direct competition with Nvidia’s Vera CPU, not only based on core count, but also on performance. These two chips trade blows in several benchmarks, and it’s clear that AMD is pushing this SKU as its “agentic CPU” of the Venice lineup, similar to how Nvidia has positioned Vera.

You can see the platforms we tested above. The Nigeria reference platform we tested these Zen 6 chips on came with top-end DDR5-12800 MRDIMMs, arranged to fully saturate the 16-channel memory with 32 sticks. This massive jump in memory support is a critical aspect of Venice, particularly for the hotly contested EPYC 9686F and its all-important matchup against Vera.

Vera’s use of LPDDR5 SOCAMM2 memory allows for higher transfer rates than standard RDIMMs in a field-replaceable package, though through a relatively tame eight-channel setup. Vera can get away with 8-channel memory, however, with its topology allowing for massive data movement across the chip. AMD’s distributed design necessitates a bigger memory configuration, with double the channels and access to even higher transfer rates through the use of MRDIMMs.

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F SPEC estimates

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F SPEC estimates

Starting off our benchmarks is SPEC CPU 2026, the de facto industry benchmark for server CPU performance. As usual with SPEC runs, the numbers below are “estimates.” We gathered the numbers from real SPEC runs, but we haven’t reported them to the SPEC committee, so they remain “estimates.”

For the throughput benchmark suites, intrate and fprate, we ran a number of copies for each application equal to the thread count of the chip. All of our tests were run on Ubuntu Server 26.04 with Linux Kernel 7.0, and we used GCC 15.2 for all but the Venice chips. GCC 16 brings official support for Zen 6, which we used here. However, we did regression testing against GCC 15 and found only minor differences, and nothing that would change our standings.

Using GCC 16 was important to keep our optimization flags equal. We used common GCC flags, including fast link-time optimization and march/mcpu flags to expose the correct processor instruction support. We also used the open-source jemalloc memory allocator across all tested systems.

The overall intrate scores set the tone, particularly for the EPYC 9996. It has access to 1,024 threads in a 2P configuration, multiplying the clear speed improvements in Zen 6 broadly across more threads compared to last-gen’s top-end EPYC 9965. The 9996 scored a massive 93% higher in this test, though that number requires some context.

Both throughput benchmarks in SPEC reward not only how much work is done, but also how quickly it’s done. With access to a much larger thread pool and improvements in Zen 6 broadly, there’s that multiplicative effect when looking at pure throughput. A 2P EPYC 9996 system is 93% faster than a 2P EPYC 9965 system in this benchmark, but not broadly across the board.

The EPYC 9686F provides some context, which is still good news for AMD, just not on the level of doubling the performance of the previous generation. We unfortunately didn’t have access to a 9575F for a closer gen-on-gen comparison, but the EPYC 9755 is a decent proxy, with its 128 cores and relatively high 4.1 GHz boost clock. Compared with that CPU, the EPYC 9686F in a 2P configuration is 19% ahead — not too shabby considering the thread disadvantage.

Critically for AMD, the EPYC 9686F is also 17% ahead of Nvidia’s Vera CPU. Vera punches far above its weight class compared to the x86 competition, as evidenced by its matchup against the 9755 and Intel’s flagship Granite Rapids-AP 6980P.

fprate

Flipping over to float performance, AMD did a lot of work on the vector engine in Zen 6, and it shows up in fprate. The differences between the EPYC 9996 and 9686F are smaller, though not in a way where both chips are hamstrung. Rather, the EPYC 9696F is able to push up closer to the 9996, leaving both Zen 6 chips running circles around the field.

AMD more than doubled the score with its Zen 6 chips compared to our Zen 5 touchpoints, which is a massive achievement. The EPYC 9686F excels even more over Vera in fprate with a 40% lead, despite only a minor bump in core count (88 on Vera to 96 on the 9686F). Intel’s Granite Rapids-AP isn’t in the conversation here for raw performance; though, apparently the range is still in high-enough demand that Intel has increased production in the tight CPU environment we’re currently experiencing.

These throughput benchmarks are most representative of how these CPUs will actually be deployed, running multiple copies of applications under high concurrency. However, SPEC CPU also includes its speed suite, which looks at application performance when you can dedicate the whole chip to running just that one application, more along the lines of a client CPU benchmark.

The EPYC 9686F naturally looks better here with its blistering 5 GHz boost clock. In the integer suite, the frequency-optimized chip is 21% ahead of Vera, both in a 2P configuration. The 9996 still holds up, only falling short of the 9686F, despite much more inter-CCD communication.

SPEC shows the various improvements in Zen 6 showing up in a compounding fashion. There’s the new microarchitecture with an optimized vector path, but also more cores per CCD. And also support for higher memory speeds, as well as more memory channels. In isolation, any of these improvements are solid (if rote) for typical gen-on-gen improvements. Add them up in a workload that can take advantage of all of those improvements, however, and Zen 6 is blistering.

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F Python and memory benchmarks

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F Python and memory benchmarks

Two of the biggest performance vectors in the agentic era are memory performance and Python performance, at least at the moment. Agentic frameworks are largely defined by Python between LangGraph and CrewAI, though alternative frameworks written in TypeScript and Rust have started to appear as well. Regardless, Python remains important for agentic CPUs right now.

Similarly, memory bandwidth is important for certain types of agents, particularly those that need to query large databases, regardless of if they’re a traditional relational database written in SQL or a non-relational database.

Starting with the industry-standard STREAM benchmark, AMD is ahead of Nvidia’s Vera by between 11% and 19%, depending on the test. However, this was with the OpenMP “true” policy for process binding, which binds processes to the thread they’re placed on to avoid them jumping around and skewing the results. Vera performs well, even with this policy, but its mesh cache and monolithic design allow it to realize big performance gains with the “spread” policy.

This policy also binds processes, but it distributes them across the chip as far away from each other as possible. AMD chips don’t see an improvement with the spread policy, and Intel’s Granite Rapids-AP sees a slight regression. Vera, however, remains on top of the pile, with a clear victory margin with the policy applied.

In the tried-and-true MBW benchmark, the pair of 9996s claim a small lead over Vera, with a small array size of just 128 MB, but Vera jumps into first place when the array size increases. AMD has certainly tightened up the memory matchup against Vera with 16 channels and support for 12,800 MT/s MRDIMMs, but Vera’s topology and already competitive memory subsystem still wins the day.

The clear differences in memory performance flatten off as we flip to Python, which is a much more hotly-contested area of performance. Starting with a broad overview, we have PyBench. Across the suite, the EPYC 9686F was 32% faster than Vera, while the EPYC 9996 naturally claims a smaller 14% lead with its relatively limited boost clocks. For gen-on-gen comparisons, the EPYC 9996 is an impressive 24% ahead of the EPYC, while the 9686F claims a lead of 35% over the 9755 – though, no small part of that advantage is the 900 MHz higher boost clock that the 9686F has access to.

PyPerformance allows us to go more granular into specific Python applications and functions, but a similar pattern appears. The rankings of other CPUs change, but across the vast majority of tests, the EPYC 9686F leads by a clear margin. It makes sense, too, given that Python heavily leans on a single thread at stock.

There are some exceptions, notably the networkx benchmark, where the throughput-optimized 9996 tops the charts, matching Nvidia’s Vera. Despite how impressive Nvidia’s chip is, considering the company’s infancy in data center CPUs and the chip’s tame spec sheet, Venice shows that the CPU game is AMD’s to win (or lose).

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F compression and rendering benchmarks

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F compression and rendering benchmarks

Breaking out of the agentic bubble, AMD has continually proven itself as the leading force in general-purpose data center applications, and that trend continues with Venice. As with all of the workloads here, they can touch on agentic AI depending on what the agent is set up to do; database performance, for example, is important if an agent is often querying a database. However, we’re going to keep our analysis at a high level here, as EPYC CPUs will be deployed for a broad range of workloads, some portion of which won’t come remotely close to agentic AI.

Starting with compression performance, AMD generally sits at the top of the charts for compression and decompression speeds, which is the case here with zstd and 7-Zip. In zstd, Vera claims an early lead at the lowest compression level. However, its poor decompression performance shows up even at level 3, and AMD takes over with a clear victory at the compression level 19, with Vera falling even further behind in decompression performance.

The long mode results are especially interesting. Although the rankings don’t change, Vera’s performance in these sustained compression workloads gets worse, while AMD is able to hang onto much more of its performance. Vera and the EPCY 9686F are within noise of each other in the level 3 compression test, and Vera falls to the bottom of the rankings when looking at decompression.

7-Zip has been, for years now, AMD’s game. The charts really speak for themselves here; we’re dealing in multiplicative factors compared to Vera, not to mention the weak competition from Intel’s Granite Rapids-AP. AMD is always strong in 7-Zip, which is compounding here considering the already high base level of performance we see out of Zen 6 across a wide range of workloads.

Onto rendering, Blender shows big gen-on-gen gains for Venice, with the EPYC 9996 offering somewhere between a 30% and 40% improvement over the EPYC 9965 depending on the scene. This is true even in demanding scenes like Barbershop, where render time can be expressed as minutes instead of seconds for many chips. The EPYC 9996 completed the render 35% faster than the EPYC 9965. The EPYC 9686F was able to match the dense EPYC 9965, despite packing half of the cores. Vera isn’t included in our Blender results because a native Arm version isn’t available.

Vera retains a top position in C-Ray, both at 4K and 1080p, though a dual EPYC 9996 configuration is within spitting distance. The script flips in OSPRay, with AMD pulling off clear leads in real-time ambient occlusion, scientific visualization, and path tracing. There are some massive jumps, with the EPYC 9996 nearly tripling the performance of the Xeon 6980P and Vera in the ambient occlusion and scientific visualization tests.

The reworked vector engine in Venice shows up even more clearly in the dim_512 tests, which further stress both the vector engine and memory bandwidth of the platform.

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F Java and database benchmarks

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F Java and database benchmarks

We run three Java suites to measure the ever-important programming language that shows up everywhere from scientific computing to database workloads. Starting on the former end, Java SciMark shows the EPYC 9686F in a clear lead over the competition, with a massive 92% lead over Vera in the composite score. For an apples-to-apples gen-on-gen increase, the EPYC 9996 managed a respectable 24% jump over the EPYC 9965.

Java SciMark provides a nice overview of some critical functions, such as Monte Carlo risk analysis that’s applicable to financial institutions. DaCapo and Renaissance are much wider suites measuring a range of Java-based applications. Many of these tests are highly specific, so the rankings jump around, depending on what the workload stresses. We can see a bit of that with Java SciMark, as well, with Vera claiming the top slot in FFTs. Venice, however, remains ahead.

In large column-based database workloads like Clickhouse, Venice also looks impressive, though not from the jump. Vera maintains its performance from a cold cache, while none of the x86 competition reach steady performance until the cache is warm. The reason should be obvious given Vera’s topology and its distributed mesh, which allows it to jump straight to its peak performance, even when the cache is cold.

Once it’s warm, the 9686F jumps into the lead. There’s a regression in performance going from the 9965 to the 9996, which makes sense for Clickhouse, as larger core counts can create issues in cache coherency.

To look at NoSQL performance, we have simdjson, which leverages SIMD instructions for JSON parsing, as the name implies. Once again, the vector engine in Venice shines, regardless of the workload you look at.

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F HPC and compilation benchmarks

AMD Zen 6 EPYC ‘Venice’ 9996 and 9686F HPC and compilation benchmarks

Vera showed strong compilation performance against AMD’s Turin chips, but Team Red leapfrogs that performance with Venice. Starting with LLVM, the frequency-optimized 9686F earns a top slot with makefiles, while the EPYC 9996 tops with Ninja. The drop is around 19% gen-on-gen, aligning with the performance we’ve seen with other workloads.

In PHP, where Vera is more competitive, the EPYC 9686F squeezes out the most marginal of victories, but perhaps most telling is the 9996, which is in the upper tier of chips, despite how dense it is. Building applications, the Godot game engine and ImageMagick once again show both Venice chips on the top of the stack, outclassing the performance of Vera, which previously held a top slot in ImageMagick, and only fell slightly behind the 9755 in Godot.

The 9686F shows large performance jumps in HPC workloads, which AMD says is the target of these lower-core, frequency-optimized SKUs. In CloverLeaf, the EPYC 9686F is more than twice as fast as Vera, and it’s nearly twice as fast with FFTE. In Octave, Vera retains its top position, but both Venice chips are only slightly behind.

Although not traditional HPC, the heavily threaded number crunching behind the scenes in the Stockfish chess engine allows the 1,024 threads in a 2P EPYC 9996 server to outclass the 9965 by nearly 50%. Primesieve shows similarly large leaps, with the EPYC 9996 calculating some 37 billion prime numbers in less than half a second.

More to come

More to come

AMD already had a strong position in the newly reinvigorated CPU market with Turin. The unique topology and strong focus of Vera has allowed Nvidia to make inroads in certain workloads, but even looking at two SKUs from AMD’s broad Venice lineup, it’s clear that AMD is able to push performance much higher across the board. In some cases, that’s by orders of magnitude gen-on-gen.

There isn’t one area of Zen 6, or the SoCs available with Venice broadly, that totally accounts for the performance increase. It’s small advantages throughout the design, pushing an already strong vector engine further, vastly increasing CCD density, and giving memory bandwidth a boon between support for 12,800 MT/s MRDIMMs and 16-channel memory courtesy of the dual IODs.

But the story AMD has been trying to tell, and the one that’s difficult to ignore in the current market of a one-size-fits-all approach we’ve seen from Nvidia and Arm, is that Venice is available in a broad range of different configurations. We tested two chips on SP7, but the enterprise-focused SP8 socket is arriving within the next few months. And next year, AMD is pushing out Venice-X with 3D V-Cache for HPC workloads, as well as Verano, which looks like AMD’s take on Vera with its field-replaceable SOCAMM2 LPDDR5X memory.

Even without those chips, the two SP7 chips we tested already give AMD a leading position among current data center CPUs. Intel’s Diamond Rapids could change that story come next year, but the EPYC 9686F provides top-tier performance with HPC and AI host node performance, while the EPYC 9996 provides unmatched throughput.

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Nvidia CEO Jensen Huang admitted to having an affair with Megaspeed executive Alice Huang, who is also suspected of being a spy working for the Chinese Ministry of State Security (MSS). Now, an investigation by The Information has revealed a 'labyrinth' of companies centered around Shanghai Century Litong and connected to Singaporean firm Megaspeed, which has previously been accused of smuggling $2 billion worth of Nvidia chips. The report claims Alice Huang helped move 240,000 banned chips into the country, mostly H100 and H200 systems, and was instrumental in securing AI GPU imports to the tune of $7.5 billion.

Sources in the report link the two companies to Alice Huang via their personal knowledge and corporate registration records, while there have also been reports that some of the Nvidia AI chips Megaspeed bought went to Shanghai Century Litong’s data centers in China. But aside from these corporate ties, there were also numerous reports about Ms. Huang’s personal relationship with the Nvidia chief, and how it gave her the ability to procure chips that were otherwise hard to get elsewhere.

Ms. Huang allegedly boasted about her access to the Nvidia CEO publicly. People familiar with her said that she regularly uploaded photos with Jensen to her WeChat account and even shared other images with customers to establish her credibility. She even claimed that Jensen Huang would often celebrate her birthday with dinner and gifts, while an Nvidia China sales employee said that she was a familiar face at the company’s annual event for local Chinese partners.

When AI shipments hit delays or faced some trouble, Ms. Huang allegedly would step in to get them moving through the supply chain again. One other person who knows her said that she would often cite her close relationship with Nvidia and its suppliers as the reason why she could always get Nvidia AI chips. It’s estimated that $4.6 billion worth of AI chips have been imported through Megaspeed from 2023 to 2025, with another $2 billion routed through Speedmatrix. It was also reported that Shanghai Century Litong bought GPUs from other sources, with the assistance of Alice Huang if the orders faced an issue, with the total value of the GPUs acquired estimated to be around $7.5 billion. The report claims Ms. Huang helped move some 240,000 banned chips into China.

Alice Huang may have appeared in Jensen Huang’s circle much earlier than previously believed. One source told the publication that Kang Wei, Alice Huang’s husband, met Jensen Huang during the 2010s, when Nvidia was primarily a PC gaming GPU manufacturer. According to the report, Kang Wei was a private equity investor focusing on videogame companies back then. In contrast, Ms. Huang reportedly worked for two media companies in China, although some say that there were no records of her doing so. She eventually jumped into banking and finance, working at HSBC and then CITIC Securities, before finally entering the data center industry in 2023 with Megaspeed’s pivot and the founding of Shanghai Century Litong.

Shanghai Century Litong is a data center operator founded in June 2023 by a shareholder that was ultimately under the control of Huang Yu, the sister of Alice Huang, whose Chinese name is Huang Le. The company then provided compute capacity to AI tech giants in China, including Alibaba, Tencent, and other smaller labs. A few months after its founding, it received coveted Nvidia Preferred Cloud Partner status in October 2023, which is an important milestone as Nvidia requires anyone with this status to have demonstrated sufficient capability in handling and running Nvidia hardware as well as generating revenue at a certain level, although that threshold varies by region and partner type.

In exchange for this, partners get better access to Nvidia’s limited number of chips, which became crucial for Shanghai Century Litong as the China-specific A800 and H800 chips were banned for sale to China around the same period. Although the move immediately banned the sales of these GPUs from Nvidia, it did not affect the chip stocks that were already in the hands of distributors. This meant that Shanghai Century Litong had priority access to the limited supply of these AI GPUs as Nvidia’s preferred partner.

Megaspeed, on the other hand, was reportedly owned by a company called Huang Le Limited and led by Ms. Huang when it pivoted in 2023 and was subsequently sold to Singaporean entity Swiftdata soon after this. Megaspeed then set up a subsidiary called Speedmatrix, which has two offices in Johor, Malaysia, a couple of months after that. The Bureau of Industry and Security (BIS), the U.S. agency in charge of monitoring export control compliance, noted that the Nvidia hardware found in Speedmatrix data centers was still in its boxes when they inspected the sites, triggering a deeper investigation into the company. Still, it’s been alleged that Nvidia intervened in the BIS probe, with the company retaining its Nvidia partner status to this day.

Despite her public closeness with the Nvidia chief, she’s rather elusive when it comes to her personal information. Two other people said that she has always been vague about what she does at her companies, and that she’s careful when it comes to signing documents and leaving a paper trail that could easily be followed. Still, the Chinese embassy denies any links to Alice Huang, even as the FBI looks into the situation.

Popular gaming chair and gaming desk manufacturer Secretlab has today unveiled its new ErgoArch monitor lightbar, a new lightbar attachment for owners of its Secretlab monitor arm and a complement to its desk ecosystem. Available now, the new lightbar costs $179.

• Secretlab ErgoArch Monitor Light Bar Add-On

For owners or prospective buyers of the Secretlab Magnus Monitor Arm (the light bar is an attachment to this accessory), the ErgoArch provides overhead lighting for your desk and monitor, reducing reflections and glare, and smoothing out brightness contrast between your display and workspace. Monitor light bars are generally designed to reduce eye strain while you're working or gaming, while also providing some snazzy ambient lighting; the ErgoArch is no different.

Secretlab says the ErgoArch provides both ultrawide illumination and focused task lighting depending on how you set it up. The lighting itself is smart and can be powered by Nanoleaf, giving you access via your smart home app to 16.8 million colors. There's also a dedicated wireless control puck, and the lighting temperature ranges from 2700K to 6400K.

The light itself is mounted to the monitor arm via a three-point adjustment arm and is compatible with any VESA-mounted monitor, including curved displays. There's also a magnetic webcam mount attachment. Power is provided by USB-C, so you don't need a wall outlet or extension socket to switch it on.

Available globally, the ErgoArch is available to buy from Secretlab now for $179.

In recent months, high-profile headlines about AI models letting loose from their safeguards dominated headlines. Now, the Frontier Model Forum (FMF) has released a new Jailbreak Rating Framework that aims to track how easy it might be for a given AI model to get around safeguards. The framework also estimates the scale of the collateral damage, should an AI model wreak cyber-havoc across the internet.

The project started in 2023 with the support of four founding companies: Anthropic, Google, Microsoft, and OpenAI. The published Jailbreak Rating Framework is a rough analog to the well-known CVSS security rating system, but specifically targeted at classifying the type and severity of LLM jailbreaks across various axes and multiple frontier LLM providers.

Many AI companies and evaluation entities already have their own rating systems, but the FMF intends for its scale to be a cross-vendor standard that teams developing patches can rely on.

The FMF's approach is to have a classification method for jailbreaks that can make a model perform cyber-warfare operations beyond what's already out, across both the regular and black market. Version 1.0 of the proposal is a work-in-progress, and the group is taking comments and suggestions on it until December 21, noting that relying on its system in the meantime is inadvisable.

Right now, the framework has four scoring components, split across two main categories: severity, measuring how serious a jailbreak technique is, and likelihood, or how easy it is to find and weaponize it.

A combined final rating adds the scores obtained from the two categories into a final low-to-critical rating. The scientists note that the capability gain is the most important dimension and acts as both a floor and a ceiling for the remaining scores — a jailbreak that doesn't offer results beyond what can already be obtained via other means is meaningless within the purview of the grading system.

The individual ratings pertain to capability gains, capability scope, ease of deployment, and ease of discovery. They're all graded from zero to three, though the FMF stresses that a rating of zero doesn't mean a jailbreak is harmless or ought to be ignored — rather, it means the flaw should be addressed by standard practices like the platform's policies and standard cybersecurity ratings.

An important feature is that the FMF's baseline implicitly changes as models evolve, meaning that a grade of zero for a jailbreak in 2026 likely isn't going to mean the same thing as it would in 2028, or isn't better than alternative tools. A capability-gain rating of zero means that the jailbreak under analysis doesn't offer any improvement beyond what can already be done with existing models or tooling right off the bat.

For example, jailbreaking a model to perform a DDoS on a site isn't all that helpful to an attacker, since there are a number of black-market sites for that — or even other LLMs with fewer safeguards. This doesn't mean the jailbreak isn't handy, only that it's no better than the alternatives. However, the rating can be higher if the attacker can leverage the jailbreak to get a better DDoS than they could otherwise shop for.

On the other end of the capability-gain scale, three means that a jailbroken model can perform cyber-attacks with capabilities similar to those of a model operating without safeguards.

The capability scope measurement is easier to interpret: zero means that the jailbreak only works for one specific action or target and can't be tweaked for other applications, or in other words, is a one-trick pony. A jailbreak gets a rating of three when it can, without specific redesign, make a model perform work across at least two entirely unrelated categories of cyber-warfare — like getting the model to both autonomously discover vulnerabilities or, separately, write malware.

For ease of deployment, the FMF considers the amount of human interaction, or the degree of automation that the jailbreak allows. A zero means that the jailbreak must be steered by humans with a high degree of knowledge, providing additional instructions to be effective, while a three means that, with little effort, it can be used by a novice and results in an automated cyber-warfare task.

Last but by no means least, ease-of-discovery is how hard it is to find the jailbreak. At a zero, the attacker must spend copious amounts of money on inference tokens, need elevated access (like a privileged account given to a white-hat hacker), or specialized infrastructure like a legion of AI servers. A rating of three simply means that anyone can look up the technique and use it.

If all of this sounds familiar, you may be thinking of Anthropic's safeguard-breakage classifiers the company proposed in July 2026, after an incident that led to Claude Fable 5 being temporarily unavailable. Much like the FMF's effort, Anthropic's system would also use a moving baseline and only consider jailbreaks that improve on cyber-warfare capabilities already available.

That document is strikingly similar to FMF's proposal. Anthropic is an FMF founding member, and as such may have had a hand or two in developing the new standard — though we have no confirmation either way.

Apple’s updated Mac Studio with the M5 Ultra SoC has already proven itself as one of the most powerful systems around, thanks to its 36-core CPU and 80-core GPU with Neural Accelerators for the matrix math operations that drive AI compute. Beyond that raw power, options for up to 512GB of unified memory have many local AI enthusiasts lining up for the 13 to 15 weeks it’ll take for Apple to ship one right now.

But is our tested Mac Studio config worth a whopping $12,300 or more for those folks? We already tested the maxed-out M5 Ultra chip with the popular Qwen 3.8 27B in our initial review, but that compact dense model doesn’t come anywhere close to exercising 256GB of memory. We wanted to fill that pool to the brim with cutting-edge large models like DeepSeek V4.1 Flash 1017 and GLM 5.3 Flash.

We also have some new benchmarks at our disposal to see how the Mac Studio stacks up in agentic tasks on the GPU side in the wake of our review of the Microsoft Surface Laptop Ultra with Nvidia’s RTX Spark chip. So there's much to dig into.

Agentic AI performance and power efficiency

We started our more detailed local AI testing with Artificial Analysis' AgentPerf-Local benchmark. This test plays back recorded inference traces with certain models across a range of agentic AI workloads to gauge performance. Artificial Analysis provides a full breakdown of this workload, but the bulk of its work takes place in prompt processing rather than token generation. As a result, it should favor systems with lots of raw compute, which both GB10 and the M5 Ultra have at their disposal.

The M5 Ultra's 80-core GPU dwarfs GB10's 48 Blackwell SMs at a high level. Even without detailed info on clocks, it would be extremely difficult for GB10 to outgun the M5 Ultra in this test. And the Mac's 1.2 TB/s of memory bandwidth gives it just over four times as much decode bandwidth as GB10's 273 GB/s. But as our past tests have shown, raw specs aren't as important as delivered performance with AI. Delivered performance can vary greatly from paper specs.

We continued to use the dense Qwen 3.8 27B for this test. We used llama.cpp as our inference backend on both the Mac Studio and a single Dell Pro Precision GB10 box, which is nearly identical to the DGX Spark. We further enabled Qwen 3.8 27B’s native multi-token prediction (MTP) support for a decode speed boost on both platforms.

Versus a single DGX Spark-like system, the M5 Ultra Mac Studio finishes this agentic test in just under half the time, an extremely impressive result. One might think this is a silly comparison given the imbalance in compute resources and memory bandwidth between these two systems, but the cost of a single 4TB Dell Pro Precision GB10, like the one we tested, is now a whopping $10K, so comparing it to the $12K Mac Studio head-to-head isn’t actually that far-fetched.

Because AgentPerf-Local performs a fixed amount of work on every system, we can also directly compare power efficiency between platforms by recording the wall power consumed by a single Spark and the Mac Studio and converting it to task energy in kilojoules.

At least with llama.cpp, the Mac Studio not only finishes the AgentPerf-Local test much faster than the DGX Spark, but it also consumes less task energy overall — about 16% less. A different inference engine might produce a more favorable result for the Spark-like system, but apples-to-apples, this test looks fantastic for the Mac Studio.

We can multiply both task time and energy consumed (in kilojoules) together to arrive at the energy-delay product (EDP) for each system. A lower EDP wraps up a fast time to completion and a low task energy into a single comparable figure for efficiency.

The Mac Studio’s EDP is under half that of the DGX Spark in this test, once again indicating its impressive efficiency and performance with this dense model and workload.

Going big with DeepSeek V4.1 Flash 1017 and GLM 5.3 Flash

Of course, Qwen 3.8 27B doesn’t need 256GB (or even 128GB) of RAM to do its thing. To really stretch the legs of the Mac Studio, we chose two larger open models that are near the top of capability benchmarks right now: GLM-5.3 Flash and DeepSeek V4.1 Flash 1017.

The M5 Ultra Mac Studio can natively fit quantized versions of these models (a four-bit quantization in the case of GLM 5.3 and a two-bit quantization courtesy of Unsloth for DeepSeek V4.1 Flash) in its 256GB of RAM, but there’s no way even those quantizations will fit on a single 128GB DGX Spark.

That’s where the clustering capability of Nvidia’s platform comes in. We’ve already seen how pairing up Sparks can scale up one’s local inference capacity, and that capability is critical when evaluating them against a Mac Studio like this.

But the rapidly rising prices of GB10 systems have frustrated our value analysis during the course of this testing. For just one example, Lenovo set all of its ThinkStation PGX systems to a “coming soon” status during our tests. And as we’ve already mentioned, the Dell Pro Precision GB10s we’re clustering here are an eye-popping $10K each. We have no reason to believe the rest of the GB10 systems on the market will be that much cheaper once this current volatility shakes out.

No matter how you slice it, getting even a pair of DGX Sparks with 4TB SSDs is going to end up costing quite a bit more than this single Mac Studio, even if $20K for a dual-Dell cluster is at the top end of the market. $15K or more is a relatively more reasonable benchmark, but even then, that’s 25% more money than a single M5 Ultra Studio.

We don't yet have end-to-end agentic tests for these larger models, but directionally, we can still consider prompt processing and decode performance to see which of these systems would deliver faster agentic turnaround.

Because of the limited choice of compatible inference engines for Apple Silicon, we have to use llama.cpp for DeepSeek V4.1 Flash 1017. Worse, the Mac Studio can't hold both the DeepSeek V4.1 Flash 1017 model weights and the DSpark speculative decoding model required to boost token output even with a two-bit quantization, so we’re forced to leave performance on the table.

In contrast, the DeepSeek V4.1 Flash serving recipe for our Spark cluster can take advantage of DSpark speculative decoding and the TensorFold inference engine, which can deliver higher performance than llama.cpp.

Even with MLX support, llama.cpp performance with DeepSeek V4.1 Flash on the Mac Studio is pokey next to the DGX Spark cluster. Between its slower prompt processing speed and unaugmented decoding, it would end up at a disadvantage in agentic work with this model.

The community two-Spark serving recipe from Mia’s AI Lab with TensorFold is a major asset for owners of those systems, even accounting for the bit of extra work involved in setting up and managing a Spark cluster.

Where the Mac running llama.cpp needs anywhere from 10 to 25 minutes to digest the longest context lengths we tested for DeepSeek V4.1 Flash, the Spark cluster needs under five minutes at most to do the same jobs with this recipe — and the TensorFold inference engine is much faster on the decode side, too. If you want to run this model locally, a pair of Sparks is the clear winner right now.

With DeepSeek out of the way, let’s consider GLM 5.3 Flash, another leading open model for local intelligence. Because MTP with GLM 5.3 Flash doesn't require a separate drafting model, we can give it a decode boost on the Mac Studio without the memory headroom issues we saw with DeepSeek V4.1 Flash. For our Spark cluster, we chose to run GLM 5.3 Flash using a recipe cooked up by Mia's AI Lab.

GLM 5.3 Flash runs much better on llama.cpp than DeepSeek V4.1 Flash does, but even so, the DGX Spark cluster delivers much faster prompt processing times across the board. The M5 Ultra's memory bandwidth advantage means the Mac is delivering higher tokens per second on the decode side, but it’s likely that any agentic turn would still finish faster on the Spark cluster.

Because a TensorFold serving recipe is available for GLM 5.3 Flash on Apple Silicon, however, we can see just how much extra performance is available from an MLX-specific four-bit model quantization and a theoretically higher-performance inference engine.

This serving recipe turbocharges the Mac Studio’s performance compared to llama.cpp. Prompt processing times with TensorFold get much closer to those of the Spark cluster, and decode throughput is a startling three times faster, on average.

We expect (and can only hope) that improved inference engine support and serving recipes for DeepSeek V4.1 Flash 1017 on the M5 Ultra will arrive in time as community members unleash their coding agents on this hardware, because the performance potential is clearly there for Apple Silicon.

Bottom line

A single M5 Ultra Mac Studio can deliver incredible local AI performance and power efficiency versus a single DGX Spark when all the puzzle pieces fall into place. And that's not as absurd a comparison as it might seem.

Prices for unified memory systems are ballooning to the point that a single Dell Pro Precision GB10 system with a 4TB SSD is now over $10K, closing in on the $12K-ish price of the Mac Studio configuration that we tested. We expect those trends will only continue as the RAM and NAND supply crunch becomes more acute.

But our broader experience shows that the M5 Ultra's impressive performance isn't assured from every model and inference engine, especially from the bigger and highly intelligent models you'll want to put in 256GB of RAM.

This Mac's prompt processing speeds can really rip with llama.cpp and smaller models like Qwen 3.8 27B, but you really want to ensure that you have a higher-performance serving recipe at your disposal for bigger models like GLM 5.3 Flash and DeepSeek V4.1 Flash 1017. The TensorFold engine runs GLM 5.3 Flash incredibly well, but it doesn’t support DeepSeek at all yet.

As we emphasized in our review of the M4 Max Mac Studio, memory bandwidth is just one factor in AI inference performance. You need to take the entire hardware-software stack into account in order to wholly judge the performance and model compatibility available from these extremely pricey unified memory setups.

Even as Apple closes the performance shortfalls of its hardware for AI inference, development and support around the MLX stack has a ways to go before it catches up with the maturity and performance, as well as the model and inference engine options, available on Nvidia hardware.

The enduring value of the DGX Spark platform beyond its raw performance and scalability is that the breadth and velocity of community software development and support around the platform has gotten to the point that you're virtually assured of a way to run a hot new model soon after its weights hit Hugging Face (at least assuming you have enough Sparks to cluster to provide the memory capacity necessary).

That assurance of community software support and ongoing development, along with the DRAM and NAND supply crunches, means high demand and ever higher prices for 128GB GB10 boxes. Two such Sparks with 4TB drives will run you an eye-watering $15K to $20K+, depending on the partner system and storage configuration you choose. And those prices are likely to continue rising, making a single Mac Studio a potentially appealing option as long as Apple doesn’t jack up its prices for these systems in turn.

If strong local AI performance is just one thing you need from a personal workstation, and you also want one of the world's fastest CPUs and a powerful GPU for general-purpose work in one well-rounded, efficient, and quiet compact chassis, the Mac Studio is a remarkable system.

If you can wait for software to catch up to this system’s incredible performance potential for local AI and don’t mind the possibility of narrower model and inference engine support compared to a DGX Spark setup, get in line, as lead times for these systems stretch into February 2027 as of this writing.

But if you're thinking about dropping well over $10K specifically for the purpose of building a local AI inference setup right now, perhaps for yourself or a small office, clustering a pair of Sparks gets you both the memory capacity and compute horsepower you need with the robust software support and broad model compatibility you’d expect for that outlay to be worthwhile. Those assurances may be worth the lower raw performance potential of such a cluster compared to the Mac Studio.

Elon Musk’s Terafab, a joint venture of Tesla and SpaceX, has informally told equipment makers it is seeking to produce 1 million wafers per month after 2032, according to Financial News. About 70% of this output, or 700,000 wafers, is planned to go to memory, with more than 300,000 going to logic chips. Terafab’s procurement team has already visited Japan to ask some local toolmakers for delivery within months. The memory allotment would rival Samsung’s estimated DRAM production capacity if it were all of that type.

Samsung’s DRAM capacity was estimated last year at 650,000–700,000 wafers a month, while SK hynix is reportedly at about 550,000, with about 1 million a goal by 2030. The comparison has to be taken in context, as Terafab’s 700,000 measures all of its expected memory output, which could be NAND or DRAM, while the Samsung and SK hynix figures measure only DRAM. As it is, the memory portion alone would be 3.5 times the reported 200,000 at SK hynix’s Wuxi fab in China.

Many in the industry were skeptical when Musk announced the plans in March, but orders are now leading more companies to see a real business opportunity. The timeline is aggressive, as it usually takes three years or more to get from planning to volume at a leading-edge fab, and Terafab is targeting volume production in the second half of 2028. Procurement officials from the company reportedly visited Japan earlier this month to meet local suppliers and to work on details on bringing in equipment, with some suppliers asked to deliver within a few months.

The Elec also reports that Terafab representatives visited booths of about 10 Korean materials, parts, and equipment firms at SEMICON West, with some NDAs signed.

Logic chips are one thing — Jiji Press reports Terafab is working with Intel to adopt its 2nm and 1.4nm processes — but memory is another, and it’s not clear what type of memory is on the docket. Technical help from a Taiwanese company is under consideration for memory, but no partner has been named, leaving 70% of the planned wafers without a disclosed process technology.

Memory production tends to split between DRAM and NAND flash, the latter for non-volatile storage. A Tesla job listing for a Terafab Memory Process Integration Engineer, reported in August, covers end-to-end DRAM process integration and DRAM node development, and supports emerging memories such as MRAM, RRAM, and 3D DRAM. Terafab hasn’t said how its DRAM would be divided among products like HBM and LPDDR, both useful for AI and both mentioned in its job postings, or whether it expects to make and stack the DRAM itself or package chips it brings in.

Building a cutting-edge logic fab on U.S. soil is its own challenge, and Tesla and SpaceX lack chip-manufacturing experience. Even Musk, on a SpaceX call last month, called Terafab’s dates “very aggressive” and said he put “big error bars” on the timeline. The first SRAM test chip is targeted for around May or June 2027 at the Austin research facility.

How TSMC might fit in remains open. TSMC says any fab with its involvement has to be run by TSMC, while Musk said his own companies would build and operate Terafab, a scenario which could leave TSMC as a space tenant. At least the spending plans are known: $16.8 billion for the first phase in Grimes County, Texas, with total investment of up to $119 billion if later phases proceed. A pilot plant could be completed as early as July 2027.

Most open-source projects have meager resources, and the inrush of AI-provided bug reports and "fixes" has been a bane on their respective maintainers. However, the Linux kernel is well-manned, and code for it generally has a higher barrier to entry than in other places. Linus Torvalds thinks that the flood of AI bug reports may be settling, as the kernel's Berkeley Packet Filter (BPF) portion saw more AI fixes than reports.

Torvalds splits off the changes among three areas: graphics, networking, and sound drivers; networking and the BPF; and miscellaneous changes. He proceeds to state that "much of this was driven by various AI fixes," an apparent underscoring of his stance that AI-written contributions should be embraced rather than shunned — so long as they're subject to the same quality control.

The Linux maestro also relayed a note from Alexei Starovoitov, the BPF maintainer, who claims that this subsection actually saw a higher rate of AI-provided fixes versus reports. This might signal a tidal shift, at least where the Linux kernel is concerned, and would be exceedingly welcome news for other open-source maintainers everywhere tired of dealing with junk reports at the same time they have to handle a higher influx of legitimate bugs, thanks to AI-driven bug discovery.

In Torvalds' own words, "I think most other areas haven't reached that point yet, but it's at least a sign that we may be starting to see the tide starting to turn."

Anyone can make a pointless bug report, but it's hard to deny that the existence of powerful AI bots has prompted a renewed focus on cybersecurity most everywhere. Firefox fixed 423 security bugs in an April release, Chrome found and fixed 1,072 bugs in June — making for more fixes in 2026 than the project's previous eight years — and my personal "favorite," NodeJS, sadly fixed 50 vulnerabilities instead of announcing its closure.

Many open-source projects have complained about high-volume, low-quality AI-driven bug reports, with some even shutting down their bug bounty programs altogether, or placing additional verifications for issue reports. We'd venture that the Linux kernel has a much larger bug-triaging team than your average project, though, meaning it has more resources to sift through the junk.

This tentative conclusion popped up in a message sent yesterday to the kernel mailing list, wherein Torvalds briefly describes the overall shape of the kernel's 7.4-rc2 update. He says that despite the update looking large from a pure file-count perspective, it's actually mostly composed of one- and two-line fixes and is "very straightforward" to implement.

As more information about the ongoing situation at Nvidia unravels, U.S. President Donald Trump has confirmed that the FBI is investigating CEO Jensen Huang’s affair with a suspected Chinese spy days after he admitted to the indiscretion. According to the Associated Press, the president said this during a briefing at the White House, with one reporter asking him about his knowledge of Huang’s issue before it became publicly known. The news comes amidst a separate bombshell report from Bloomberg, which claims that Nvidia intervened in a US government probe of suspected chip smuggling by Megaspeed, where Alice Huang was an executive.

“Well, I’ve been hearing about it, and I’ve been reading about it over a period of time, but, uh, not too long ago,” Trump said. “We’ll look into, I know the FBI is looking into it in terms of something, and I think he’ll be in good shape.” He also said, “I did speak to him today just to see if he’s feeling alright, how you’re doing. He said he had absolutely no idea that the person in question was a spy.”

It has been previously reported that U.S. intelligence services suspected that Alice Huang, who previously held an executive position at Megaspeed, had ties to the Chinese Ministry of State Security (MSS), which is one of the country’s intelligence services, and that they told the President about it over a year ago. However, it was reported he did not act on the information, as he reportedly did not want to jeopardize Nvidia sales or antagonize Beijing, especially after the White House approved the export of H200 chips to China with an attached 25% fee.

Congress has called Huang once to confront him about these rumors, with the CEO confirming his affair with Alice Huang shortly after. The committee said it has "concerns over Nvidia’s security protocols against foreign adversary espionage and Mr. Huang’s reported ties to a Chinese intelligence-linked executive of a Singapore-based data center company.” Now, it seems that the FBI, which is the U.S.’s primary domestic counterintelligence agency, is looking into the situation, too.

While the infidelity of tech executives is usually outside the purview of politicians and law enforcement, Jensen Huang’s sensitive position as the head of the leading AI chip manufacturer that arguably single-handedly drove the global AI race has made him a prominent target. China has denied the accusation that Alice Huang is its agent, but a think tank suggests that “China is employing ‘attractive women’ posing as investors, business professionals, academics, or romantic partners to gain access to U.S. tech talent, networks, and research infrastructure.”

This is why Nvidia’s supposed intervention in the U.S. Bureau of Industry and Security’s (BIS) investigation into Megaspeed is becoming a concern. Megaspeed has been investigated for allegedly smuggling $2 billion worth of Nvidia AI processors into China, although Nvidia has claimed that it has done its due diligence and did not find any signs of diversions by the company. Despite that, Bloomberg reports that Nvidia executive vice president and general counsel Tim Teter reached out to U.S. Under Secretary of Commerce for Industry and Security and BIS head Jeffrey Kessler to ask about the administration’s investigation into the company and whether the BIS was involved in Singapore’s detention of Alice Huang at that time. Sources claimed that the U.S. agency was not involved in Ms. Huang’s apprehension by Singaporean authorities.

The publication reported BIS staff were told to route all Nvidia requests through Kessler or to seek approval from him for any outreach involving the company, which people say was highly unusual, and that Teter even supposedly reached out directly to BIS employees. When the affected employees forwarded the emails to Kessler and raised their concerns, the BIS chief instructed them to handle the case by the book. But in late 2025, the Justice Department, which was working alongside the BIS, asked the bureau to pause its efforts on the Megaspeed investigation.

Even though Jensen Huang admitted to having an affair with Alice Huang, who was linked to Megaspeed and is suspected to be working at the behest of Beijing, there is still no clear proof that Ms. Huang had a direct role in influencing the Nvidia chief to push for the resumption of Nvidia AI chip sales to China. Still, the unraveling of this supposed spy plot has caught the attention of the American leadership, and they’re now asking questions about Nvidia’s security protocols and the company’s sway on Washington.

Rebooted by Hileeq has shared how others can get cheap Lenovo ThinkPads and save them from becoming e-waste by using a simple BIOS unlock hack that only requires a $10 programmer and another laptop or PC. The technique is niche, known mostly by technicians, but Hileeq is the first to give this bypass mass attention with an easy-to-follow YouTube tutorial.

Rebooted by Hileeq's channel, dedicated to fixing cheap eBay finds, documents the process and what he learned while fixing the laptops. Three weeks ago, he posted a video explaining how to bypass locked Lenovo ThinkPads with Intel 4th- to 8th-generation CPUs using a cheap CH431A programmer to read, write, erase, and save EEPROM and SPI flash memory.

Companies often add supervisor passwords to the fleet of ThinkPads they hand out to their employees as an IT security measure. When these ThinkPads are disposed of, often with the storage removed and destroyed, it’s rare that the supervisor passwords are included and documented. These locked ThinkPads are then incredibly cheap because of the lack of access, ending up as e-waste most of the time. However, Victor Voinea shared a post in a Romanian forum containing his ThinkPad supervisor removal exploits.

Unfortunately, Voinea’s method generated a random password every time the exploit was run, requiring users to contact Voinea for the key specific to the generated hardware ID — and getting the password wasn’t free. However, in 2020, Knucklegrumble posted a free way to bypass the password in the Badcaps electronics repair forum. Mark Juvan, an Ethical Hacker, reverse-engineered Knucklegrumble’s exploit as his cybersecurity master’s thesis at Radboud University Nijmegen, Netherlands, which goes into deeper detail.

The exploit begins by extracting the BIOS from the EEPROM chip on the motherboard using the CH341A programmer and plugging it into a USB port of another PC or laptop. Hileeq then uses NeoProgrammer, a utility for CH341A programmers, and dumps the BIOS, saving a copy of it on the other laptop. NeoProgrammer then applies the same auto-patching workflow Knucklegrumble created.

When the patched BIOS is flashed onto the EEPROM, the laptop can then be turned on, and Hileeq goes through some steps requiring a few keystrokes which remove the password saved in the Embedded Controller (EC), a separate IC that stores security data, among other system tasks. The original BIOS can then be flashed back into the EEPROM, and with the supervisor password removed, the laptop is now usable.

Juvan states in his paper that the exploit takes advantage of a weakness in Lenovo’s firmware verification and driver architecture. Lenovo actually provides the EmulatedEepromDxe driver needed by the exploit, and the driver allows the EEPROM to be read and written to — and the EC’s supervisor password happens to be stored where it’s treated as EEPROM memory, allowing the supervisor password to be overwritten or removed.

The hard, complicated work has already been done by the electronics repair community, and now the process to bypass the supervisor password requires just a few steps and an inexpensive programmer tool. While the method may only be for ThinkPads with Intel 4th- to 8th-generation CPUs, this will still save plenty of usable ThinkPads from going to waste, as Hileeq’s popular post potentially encourages more people to attempt this themselves — who knows, this might cause a domino effect to unlock newer generations of ThinkPads.

Software engineer Yannick Dixken spent a week attacking his Prusa MK4S 3D printer in the name of science. At the end of the relatively short but intense period, he produced a video demonstrating the ability to Rickroll the printer via remote code execution (RCE). Dixken shared the video and findings – charting “roughly 23 individual defects” with Prusa and published his amusing but detailed Never gonna print you up! blog in coordination with the 3D printer maker. Yes, all the vulnerabilities are now patched in the Buddy firmware versions >7.0.0.

Dixken is an experienced Freelance Cloud Architect, DevOps and Platform Engineer. Security research is more of a hobby, he notes in the blog post, but it is clearly a passion strong enough to spend a whole week probing the MK4S for vulnerabilities. The result is far more than the funny old Rickroll. The week of debugging, fuzzing and reverse engineering “armed with Opus 4.8 and a fuzzer” resulted in “14 findings, roughly 23 individual defects, and a chain that ends with the printer's main controller running code I sent it over the network,” noted Dixken. “Yup, fully fledged RCE.”

The headlining RCE scored 8.1 and is officially described as High Severity. This serious bug was in the cloud (or self-hosted) management platform called Prusa Connect. You can see proof-of-concept code Rickrolling the user in Dixken’s embedded video. He sent this video to Prusa.

The methods used to uncover these vulnerabilities are outlined in the source blog, if you’d like to know more. Meanwhile, there were many other vulnerabilities uncovered and cataloged. These include a USB filename attack, heap overflows triggered by malformed encrypted print files, and network denial-of-service flaws. Many of the bugs were probably symptoms of the original developers’ use of assert statements to enforce assumptions.

Happily for Prusa 3D printer users, Dixken has responsibly disclosed this multitude of vulnerabilities. The engineer says that within 24 hours of the Rickroll video being shared on social media, the 3D printing firm’s team coordinated professionally, efficiently, and kindly. Companies don’t always react so positively to those helping them find vulnerabilities in their wares.

As games go, Grand Theft Auto VI is set to be one of the biggest game launches of the last decade. This is a billion-dollar franchise, with the last entry now 13 years old. Luckily, gamers looking to play the latest iteration don't have long to wait. Digital pre-loads are set to begin on November 10, giving you nine days to download all 212GB of it on the PlayStation 5.

To do that, though, you'll need enough storage. If you've got a base model PS5 with other games installed, you might not have enough. That's where a PS5 storage upgrade can come in handy. You can hook up an extra PS5 SSD, adding an NVMe SSD to your Sony console using its M.2 expansion slot.

● Check out these PS5 SSD deals on Amazon

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With nine days to begin pre-loading GTA 6, you've got time to fix the situation if your PS5 does lack enough space for the game's installation. You'll need to consider that the game will receive updates and may grow in size over time, too.

Unfortunately, SSDs have been badly affected by the AI-fueled price rises over the last year. Buying storage isn't as cheap, so you'll need to look for deals when you can. We've put together some of the best options for a PS5 SSD upgrade below, considering current prices, that'll help you get started.

One thing worth mentioning, too, is that the PS5's M.2 expansion slot only supports PCIe 4.0 speeds. That doesn't stop you buying a Gen 5 SSD (in fact, in some cases, it might be better value to do so). If you do use a Gen 5 SSD, however, you'll only be able to use it at Gen 4 speeds. These drives also require a heatsink, but you can pick up third-party ones to work with each drive to save costs.

Limitations aside, here are some of the top PS5 SSDs you'll want to consider to get your console ready for the GTA 6 release next week.

PS5 SSD deals for GTA 6

PS5 SSD Heatsinks

Sony recommends that you install an SSD with a heatsink when you're upgrading your PS5's storage to avoid overheating and throttling.

With that in mind, if you buy an SSD without one, you can pick up one of these third-party compatible heatsinks to use with your drive instead.

Buying a PlayStation 5

If you don't already own a PS5, you can pick one up right now. With the holidays fast approaching, however, you might see stock shortages for all the big consoles. Between this new Grand Theft Auto release and Nintendo's Legend of Zelda: Ocarina of Time re-release, it's a big season for gaming.

Right now, you can grab the digital version of the PS5 for $599. You can also grab Grand Theft Auto VI for $79.99, with the box arriving with a code that you'll need to redeem on your PS5 to be able to download and play the game.

Valve is adding framerate telemetry data to games so you can see what your hardware will manage in a given game before you buy it. The new initiative will start with the Steam Deck, but Valve has promised to bring the feature to more hardware in the future, presumably not only its Steam Machine but desktop gaming PCs more generally. The new feature shows players' average FPS on Steam Deck while playing the title, so customers can decide whether to invest without risking a purchase.

Valve already added the option to insert your hardware specifications when you write a review for a game, but an extremely small fraction of players actually write reviews, and from looking at reviews on recent Steam games, it seems like an even smaller fraction actually select to include their hardware specifications, for whatever reason.

So this is a pretty interesting idea, not least because Valve is debuting it for the Steam Deck first. Notably, the framerate data Valve is using is sourced from users who opted into sharing this data, so there's no privacy concern here. It appears to be as simple as it sounds: Valve will capture your performance while playing a game on the Steam Deck, and then show that performance to other users—anonymously, of course.

The clever among you may have realized "but wait, PC games have settings you can adjust, so even the same hardware might deliver really different performance levels." Correct! And it's also exactly why Valve is doing this. Its Steam Deck Verified program requires a certain level of performance, and games can get marked as "Unsupported" if they don't reach that level, but some people may find them playable regardless. In other words, there's no one perfect standard for "playable performance," and thus Valve wants to let users decide for themselves.

Valve says that, at least for this early trial with Steam Deck data, that data is being filtered to only show data from Decks that are set to the default frame limit. The firm doesn't make any attempt to account for custom in-game settings, yet it says that "despite this, [Valve has] found that the framerate data consolidates around relatively narrow ranges," after accounting for the unusual effects of vertical sync.

So what if you don't have a Steam Deck? Well, Valve says it sees this update (adding the Steam Deck framerate data) as "a stepping stone toward providing framerate data for more devices than just Steam Deck." Obviously, that includes Valve's own Steam Machine mini-desktop and Steam Frame VR headset, but presumably it will extend to folks on standard gaming PCs (whether desktop or laptop)

It's not clear whether desktop performance data will be matched by graphics card, some combination of GPU and CPU, or multiple factors, but either way, there's no question that this is yet another feature that sets Steam as a storefront above its competitors. If you'd like to opt in, you'll have to join the Steam Client Beta for now; Valve says the feature is coming to all users "in the future," though.

There's nothing that can improve the gaming experience on a PC more than a brand new controller, and this deal on a wireless gamepad is one you won't want to miss. For a limited time only, you can pick up GameSir's Super Nova wireless gaming controller for $39.99. That's a record low from Amazon directly, and one that knocks 20% off its list price.

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There are a lot of cheap controllers out there at this price point and lower, but they won't come with the specs that this GameSir controller has. For under $40, you're getting Hall Effect sticks and triggers, along with three different connectivity methods and a charging dock. It's also got an Xbox-style layout, although annoyingly, it isn't compatible with Xbox. It will work with your PC, however, along with smartphones, and even a Nintendo Switch.

You won't be too surprised by the GameSir Super Nova's design, and it's a comfortable and familiar option for gamers, with rubberized grips on the handles and the Xbox button layout for the thumbsticks and buttons. It's instantly recognizable if you've used a recent Xbox controller, making it perfect for PC gaming.

There are three different ways to connect the GameSir Super Nova to a device. You can use it wired, so you won't have to worry about battery life, or you can connect wirelessly using a 2.4 GHz dongle or via Bluetooth. The wired and wireless 2.4 GHz connections will ensure ultra-low latency with a 1,000Hz polling rate, which you'll want if you play competitive-style FPS games, for instance. Bluetooth will give you better battery life while using its 1,000 mAh battery. The combination also makes it easier to switch between using different devices, too.

The GameSir Super Nova is fitted with Hall Effect switches for the controller's trigger buttons, and also uses Hall Effect thumbsticks. These magnetic switches reduce physical wear and tear, avoiding the stick-drift issues that have plagued plenty of older controllers. You've also got trigger stops you can engage for a hair-trigger feel, giving you faster response times in FPS games. There's also 6-axis gyroscopic movement that you can use in Nintendo Switch games, along with vibration motors in both handgrips for haptic feedback.

It's possible to remove the magnetic faceplate and swap the ABXY button layout for your own preference, while vibration settings, button mapping, and dead zone adjustment can be made using GameSir's own app.

The $39.99 sale price for this GameSir Super Nova game controller is a good one, and it's the lowest we've seen on Amazon before. Expect this deal to sell out fast, as there's no guarantee that this limited-time deal will stick around for very long.

There's a great Newegg combo deal right now that'll net you half the parts you'll need for a new 4K gaming PC. For $1,090.98, you can pick up the AMD Ryzen 7 9800X3D, one of the best CPUs you'll find for gaming, along with 32GB of Corsair Vengeance DDR5-6000 RAM and a mid-tier Gigabyte X870 Aorus Elite Wi-Fi 7 motherboard.

● Check out this deal at Newegg

The $138.99 saving you're making here means you're getting the RAM for $371, almost $70 less than the current low price for 32GB DDR5 RAM right now. If you count the free Rosewill ATX case you're getting here, too, worth $59.99, the RAM is just $311. These parts give you the foundation for a high-spec AM5 gaming PC that, coupled with a recent GPU that you'll need to buy separately, will smash through high frame rates at 1440p and 4K.

Starting out in this combo is one of the fastest and best of the current-gen gaming CPUs on the market, the AMD Ryzen 7 9800X3D. This eight-core, 16-thread Zen 5 processor has a base clock speed of 4.6 GHz and a max boost speed of 5.2 GHz and a 120W TDP. More importantly for gamers, though, is the L3 cache. This boosted 96MB L3 cache capacity is the reason AMD CPUs have become the dominant force in gaming right now. They're able to deliver faster, more stable frame rates as the CPU doesn't need to rely on the slower system RAM as often while you're gaming.

As the CPU benchmark data shows, the 9800X3D sits near the very top of the food chain right now. Only CPUs like the 9850X3D can beat it; that CPU is 3% faster at 1080p than the 9800X3D, but has much higher power demands. As it stands, the 9800X3D continues to be a firm favorite, and one that'll sit comfortably in high-spec rigs for a few years to come.

You're also getting RAM with this bundle, with 32GB of Corsair Vengeance RGB DDR5-6000 memory included, split across two 16GB modules. If you wanted to buy this RAM separately, it'd currently cost you a huge $509.99 right now. As we mentioned, however, this bundle's collective cost and $138.99 discount bring the effective price down by $138. This black kit matches the motherboard and has customizable RGB, which you can switch on and off. With speeds of 6,000 MT/s, this RAM sits in the sweet spot for gamers, with CAS and latency timings of 36-44-44-96.

As for the motherboard, the Gigabyte X870 Aorus Elite Wifi 7 is a solid mid-range performer for an AM5 gaming PC build. There's plenty of connectivity here, with 12 USB ports on the rear, including two USB-C 4 ports rated for 40 Gbps. There are also four M.2 slots, one rated for PCIe 5.0 with the 9800X3D installed, along with Wi-Fi 7 and 2.5 Gb Ethernet connectivity. There's also a five-year warranty for support.

The Rosewill mid-tower ATX case is a nice extra, and if you bought it separately, it'd cost you $59.99. It's a gaming PC case, with four 120mm fans, a tempered glass side and a mesh front to keep your fans free from dust. Luckily, it's all free here.

The $1,090.98 sale price for this Newegg combo bundle with the 9800X3D means you can save nearly $140 on the RAM compared to buying it separately. The $138.99 discount will help towards the cost of a new SSD or GPU, especially given how expensive PC components have become recently. These bundles sell out quickly, though, so you'll need to be quick.

What's old is new again. Seagate started adding faster flash-based storage to its hard drives in 2010, when solid-state storage was prohibitively expensive. And now that SSDs are stupid-expensive again (thanks, AI hyperscaler demand) the hard drive maker is offering up another hybrid drive, of sorts, with the Firecuda Forge.

Available in 8TB and 20TB capacities, the Forge is an external hard drive that requires that you bring and install your own SSD. That's right, the drive won't work unless you partially disassemble and install your own M.2 2280 SSD, which mounts in the side of the enclosure. 1TB drives with DRAM are recommended. Performance maxes out at PCIe Gen3 drives; newer, faster, and roomier SSDs are supported, but won't improve performance. The Firecuda Forge only has a mounting point for 2280-length drives, and while drives that are less than 1TB are supported, that means less room for frequently used files, so "performance may be reduced."

Interestingly, Seagate sent us a 2TB FireCuda 530R SSD to test with the Forge hard drive, which is both faster (PCIe 4.0) and more spacious than what the company says you should pair with its hard drive. The list of SSD that Seagate has officially qualified to work with the Firecuda Forge is also pretty sparse, including just three other drives: Samsung's 990 Pro, WD/Sandisk SN850X/GX Pro 850X, and the WD/SanDisk SN710/GX7100.

We only received a review sample a few days before launch, and haven't yet had a chance to put the FireCuda Forge through its paces for a full review. But I was impressed that, after I installed the SSD and plugged the drive in, it just showed up in Windows 11 as an 8TB drive. (The company says it also works with macOS 26 and later). There was no software setup involved, and Seagate says you can even remove and upgrade the hard drive to something roomier down the line. Seagate calls the "product architecture" that handles unifying and data handling between the spinning platter drive and the SSD "Alkemi," and says it combines "onboard processing" with the hard drive and the user-supplied SSD to "prioritize active data without requiring users to manually manage separate drives."

Seagate says Alkemi observes workloads and gives priority to currently relevant or often-used data, that it adapts over time to user behavior, and describes it as an "on-device device dynamic caching and workload-aware data-prioritization technology." That sounds pretty similar to the SSD caching used on hybrid drives of the early 2010s, although with up to 1TB of fast SSD storage, you're getting a much bigger fast data pool than those drives of the past, which often made do with 4-16GB.

Interestingly, Seagate says that machine learning is a part of what Alkemi does, but repeatedly points out in its review materials that it is not using generative AI. It's likely the company is worried about customers connecting the many reported instances of LLMs and agents deleting data with this new product. I can understand why Seagate would want to distance its hybrid storage tech from reports of catastrophic data deletion.

What's the FireCuda Forge like to use?

Getting past the somewhat odd-feeling aspect of having to crack open an external drive right out of the box and install another drive into it in order for it to work, the process was pretty painless. You have to remove four screws from the bottom (with a tiny included hex-bit driver) to get the outer shell off the FireCuda Forge. From there, the M.2 drive bay is clearly visible on the side. If you want to remove six more hex screws, you can also pop out the hard drive for future upgrades. But for now, we're just going to install an M.2 SSD.

SSD installation is pretty much the same as putting one of these drives in any laptop or motherboard. Though you'll need a tool; the drive requires a a tiny screw and Seagate does not include a suitable Phillips head screwdriver. The drive bay is somewhat recessed, and there are two thick thermal pads included in the box that should ensure the drive makes contact with both the inner edge of the bay and the external shroud.

This should provide some heat dissipation, but these surfaces are all's plastic, with only a foil layer on the outer shroud to draw some of the drive's heat away from the SSD itself. This is probably fine for most bursty game and creative workloads. But this design does not feel ideal for workloads that hit the drive consistently for hours on end. During our testing, the edge of the drive where the SSD is installed got noticeably warmer than the rest of the enclosure, but it didn't get hot.

In terms of design, the FireCuda Forge looks very similar to the FireCuda X Vault HDD we looked at earlier this year, complete with some gamer-friendly RGB lighting. The primary physical difference is that you'll need the supplied USB-C cable and external power adapter to use the Forge, while the X Vault only has a USB-C port. Presumably, powering both a 3.5-inch hard drive and an M.2 SSD draws too much power for most (or at least some) USB-C ports. I still would love for drives like this to be able to run off of one single cable, though, which was my favorite feature of the X Vault hard drive.

Preliminary testing

We only received the FireCuda Forge a couple of working days before its announcement. But we were able to run some benchmarks with the Forge drive and a 530R SSD that Seagate provided, and saw some interesting results. The Forge's USB-C connection is USB4, and Seagate's performance claims are up to 2,500 MB/s read and 2,000 MB/s write. That's obviously much faster than a hard drive, but you're also going to be sacrificing the speed of the SSD you're dropping into this drive — especially if it's a PCIe 4.0 SSD.

Trace Testing - PCMark 10 Storage Benchmark

PCMark 10 is a trace-based benchmark that uses a wide-ranging set of real-world traces from popular applications and everyday tasks to measure the performance of storage devices.

On this synthetic test, Seagate's Forge beats recent traditional hard drives (and the slowest external SSD we've tested, Samsung's T5). But Kingston's fast flash drive does better, as does Sandisk's Desk Drive, which nearly doubles the score of the Forge, which isn't surprising given it's a full-fledged external SSD.

Transfer Rates — DiskBench

We use the DiskBench storage benchmarking tool to test file transfer performance with a custom 50GB dataset. We copy 4,617 files (images, videos, and software ISO files) to a folder on the test drive (write). Then, after leaving the system idle for five minutes, we run the same test in reverse, moving the test folder to a different location on our PCIe 4.0 testing drive.

Here , we see the Forge drive easily beating the spinning-platter-only drives and Samsung's T5 Evo on writes, only falling to the SanDisk Desk Drive desktop SSD. But on reads, the Forge leads by the pack.

Synthetic Testing: CrystalDiskMark

CrystalDiskMark (CDM) is a free and easy-to-run storage benchmarking tool that SSD companies commonly use to assign performance specifications to their products. It gives us insight into how each device handles different file sizes. We run this test at its default settings.

Last up (for now), CrystalDiskMark proves the Forge does benefit significantly from its USB4 interface, with its performance on sequential reads and writes jumping well ahead of everything else on our chart — because all other drives here top out at 10 Gbps. There are, of course, faster external SSDs (like Samsung's recent P9). But at 8TB, solid-state options are generally more expensive, and faster external SSDs at 8TB are much more expensive. And of course, 20TB external SSDs aren't really an option, at least in the consumer drive space.

Pricing and final thoughts

The whole reason a product like the Seagate Forge exists is because SSDs are expensive. The problem is, hard drives have faced similar price jumps due to demand. And Seagate says the 8TB Forge will launch at $699 for the 8TB drive, and $899 for the 20TB option. That's a lot of money for a drive you need to also put your own M.2 SSD into for it to function.

We'll also need to do more testing with things like game load times before passing judgment on the FireCuda Forge. But it likely makes much more sense in the 20TB capacity, where no single-drive consumer SSD-based option exists. At 8TB, there are options like SanDisk's Desk drive, which has a slower 10GBps interface, but is a full-fledged SSD, rather than a hard drive with some fast SSD cache. Surprisingly, that Sandisk drive is still on sale for $999. And unless you happen to have an old M.2 SSD lying around to install into the Forge, its price, including the SSD it needs to function, isn't going to be far off traditional solid-state options.

Before proceeding further, we'd like to advise our dear reader to sit down and perhaps grab a helmet, for this post will elicit quite a few face-palms and forehead-slaps. Two security researchers joined forces and, during early 2026, managed to hack the vehicle connectivity backend infrastructure of two automakers, managing to remotely open the doors on any of their net-connected cars and start their engines across multiple world regions.

The vulnerabilities were quickly fixed, and they pertained to a handful of belief-begging security issues with multiple server APIs that their respective mobile applications use. Furthermore, although remotely opening the cars and starting them were the most concerning bits, the vulnerabilities also exposed the vehicles' location, mileage, fuel, range, door states, and the customers' personal information.

The white-hat hacking duo isn't disclosing the name of the impacted automakers, but they managed to get access to Automaker #1's U.S. vehicles, while vehicles from Automaker #2 were susceptible to unplanned lock disengagement in Australia, the U.S., and Canada. As far as we can tell by visual inspection alone, the second firm may be Toyota, as the hack demonstration video appears to depict a RAV4 SUV.

Both affected automakers use ForgeRock's authentication and authorization services, though with the one small exception, the vulnerabilities found by Shubham Shah and Sam Curry pertained to poor implementations and security practices. One of their writeups goes over the ForgeRock-related affairs in detail for both companies, while Shah's article discusses the specifics on automaker #2 and their Australian connected-car infrastructure.

Shah first decompiled the company's Android application and found network calls to a telematics subdomain, quickly finding an "admintool" location containing a "TEST HARNESS" page with a login prompt. If you haven't been keeping track by now, the first problem is that this endpoint is reachable from the internet at large. But what really piqued Shah's interest was problem #2: a bundle of JavaScript code that should have been stripped of any unnecessary cruft actually contained the code for the backend's entire functionality, providing a map for further shenanigans.

This alone was enough to grant Shah the ability to pull up customer information with API keys that were hard-coded into said JavaScript. After some careful chaining of requests and connecting a license plate to a VIN with publicly available info, he connected that to a customer and found their email. At this point, the team noticed that the automaker was using ForgeRock's authentication mechanisms, and spent "a couple weeks" finding how they were used.

And this is also where they assess that the easiest path to victory is managing to mint an access token for any user, a task made way easier by the "cursed" JavaScript bundle they found at an endpoint containing hard-coded administrator credentials. These were likely meant for the staging environment, but the duo estimated, correctly, that they could be leveraged nevertheless.

At this point, they ran into the WAF in front of the service. A Web Application Firewall is similar to a network firewall, but instead of working with IPs and ports, it considers endpoints (URLs) and the requirements to access them. The researchers hypothesize that although it's a good and standard practice, the WAF was put in place because of how bad things were underneath.

And they were right. The app decompilation had revealed a "pinService", and Shah found that it was accessible through the WAF. From thereon, they found "getUser", and correctly guessed that they could retrieve users' information with their email, phone, and ID. Remember those admin credentials? They came in handy, revealing the users' password hashes, but as these were SHA-512, cracking them was unfeasible.

At this point, they let GPT-5.6 Sol Ultra loose to brute-force path names, and found an unprotected one that ultimately let them overwrite any user's password, partially enabling taking over their accounts. However, there was still MFA to contend with.

As it turns out, even that too was misconfigured, as the Australian environment would let users skip MFA entirely. With some judicious token shuffling across endpoints and the mobile app, they eventually could mint access tokens, letting them fully impersonate any user account... and unlock their cars. Then, it was as simple as sending out an API request for the "door-unlock" command, and sure enough, the test car promptly opened.

An Oslo radio amateur group, working with Tanagra Space, got a European Space Agency satellite to recognize and launch the 1993 game Doom after catching the word in a voice command sent over the 23 cm band. It took seven attempts, shared with a group in Poland, and the command finally got through on the last two, on the same day in late July. The satellite “understood its assignment,” with the help of a matcher after the 27 MB onboard speech model transcribed the audio, returning a postcard with details of the launch.

The satellite, named OPS-SAT PRETTY and flying under the ESA’s OPS-SAT Space Lab program for outside experiments, ran the game in an experiment punningly called PRETTY DOOMed. Doom ran on a different satellite, the OPS-SAT-1, in 2023, but this time is different, as the game was launched with a voice command.

The radio club sending the command in question is LA4O, of the Norwegian Radio Relay League, hams transmitting as part of the experiment. The club’s signal went over 1296 MHz narrowband FM at about 80 W, indicated, using an Icom IC-9700 radio and a Wimo helix antenna at 15.1 dBi, directed by hand. As for the voice, Run 6, the morning pass, used a looped synthesized voice from a keyer, with three of six captures detecting the command. Run 7, the evening pass, used a live operator at a microphone, with one of five usable captures detecting it.

The live operator’s command was “LIMA ALFA FOUR OSCAR, PRETTY PLAY DOOM DOOM DOOM, PRETTY PLAY DOOM DOOM DOOM.” The call sign is for legal identification.

On board the satellite, the voice is transcribed by a 27 MB quantized English speech-recognition model, picked because it could fit the satellite’s limited computer. The voice was handled by software-defined radio (SDR), which was able to narrow in on the voice and demodulate the source for the speech model. Tuning and demodulating a signal is usually handled by fixed circuits, but using software has the advantage of being mutable with an uploaded update. The voice used this time “was only the test signal,” project lead Georges Labrèche said, and the same setup could handle other things with a new model.

The live-voice transcript caught “AND FAR BRIEFLY PLAYING DOOM STEAM DOOM PRECIPATED” with two exact DOOM matches, although one DOOM is enough. Morning detections passed only on fuzzy tolerance with transcripts such as “PLAY DOON.” The achievement is less on the understood side and more about differentiating a voice and a specific command out of the noise in orbit.

This can be an iffy business, which is one reason it took seven runs, and being able to update proved useful. The spacecraft heard LA4O, but the output was mostly static, because about 170 kHz reached the FM discriminator for a signal of about ±5 kHz. Offline analysis brought a fix: find the peak within ±100 kHz, shift to baseband, low-pass, and decimate before demodulation. It’s effectively like tuning a car radio to a specific station.

Tanagra then reproduced the fix and was able to remove a redundant audio filter. Delivery of the fix took about a week, although the Oslo group’s effort took 59 days and about 7,200 NOK (about $770), pizza included.

Tanagra proposes repeat runs that keep the original data and send it back down to Earth, so the researchers can test the live-voice result properly. Better detection may be possible with larger speech models, too, which the team could test on the ground first. Labrèche says the team has demonstrated “a satellite that can listen to any type of radio signal.” Hopefully, the setup can one day detect “mayday” calls and even radio bursts from space.

The baying of the hounds can be heard at a distance. Yesterday, Nvidia's Jensen Huang confirmed that it was indeed true that he had a romantic affair with Alice Huang (not related to the family), who U.S. intelligence services claim is a Chinese honeypot tasked with facilitating smuggling of the firm's advanced GPUs into China. Now, a class-action lawsuit and investigations have started flying from almost everywhere.

This development is not unexpected, as basic securities law allows shareholders to sue their investees if they misrepresent facts or otherwise perform actions that cause a drop in stock prices. They may have a point, as Nvidia's shares dipped significantly when the confirmation of Jensen's infidelity and the ramifications thereof hit the press everywhere.

The legal proceedings are bound to be numerous, but as of right now, the first class-action lawsuit was filed by the Rosen Law Firm. The suit claims that Nvidia and Jensen Huang failed to disclose or misled investors regarding Jensen's affair with Alice, lied about it when asked, raised national security concerns, and caused a subsequent loss of Nvidia's reputation. You can check out the case docket at PacerMonitor here.

While legal analysis is beyond the scope of this news, Nvidia did downplay Jensen's relationship with Alice, saying that "Megaspeed has been no different than many other regional cloud customers. Meetings with customers are part of a CEO’s job; Jensen talks with thousands of customer executives every year."

Other legal firms have launched their own investigations into the recent development, with essentially the same justification: Schall, Brown & Schwartz attributes a 5.5% pre-market-trading drop to Nvidia, as does Levi & Korsinsky. The office of Frank R. Cruz mentions an 8.8% figure related to intra-day exchanging, and is interested in shareholders with $50,000 in losses. The percentage-drop figure is 5.88% premarket for Bronstein, Gewritz & Grossman.

Every investigation and suit mentioned here requires no upfront fees from complainants, as with most class-action lawsuits. The underlying condition is often that the law firms involved get a cut of whichever damages or settlements may appear at the end of the lawsuit. Some of them, like the one by Levi & Korsinsky, even aim to relieve investors who've already sold their Nvidia shares and sold them at a loss, with no minimum amount required.

A former employee of The Ethereum Foundation is suing the nonprofit, alleging disability discrimination, retaliation, unfair employment practices, and related claims, reports The Denver Post. 'The Ethereum Foundation Mandate,' a 38-page vision for the next 1,000 years, was distributed to the organization's ~250 employees in Q1 this year. On page 11 of the finalized document, there was a bizarre and rather extreme oath. This illustrated page essentially formed a suicide pledge and, unsurprisingly, scores of people didn't want to sign.

At the top of this story, you can see page 11 from the evidence submitted in the case of FULTON v. ETHEREUM ASIA PACIFIC LIMITED et al. Perhaps one could say it was illustrated like an anime version of Grimm’s fairy tales. Indeed, it contains more than a touch of the macabre, like all the best such stories.

On this particular page, reproduced in court documents, anyone working on the software used by the Ethereum Federation (EF) was asked to ensure that the source code and associated documents remained free and publicly accessible. Underlining this pledge, folks had to vow to “take his or her own life with a sword upon failure to uphold any of the pledges in this license, or upon modification or removal of any part of this license.” The message about falling on one’s sword was repeated in the illustration by a cartoon cat.

Agree or leave without delay

At the end of the 38-page document, employees picked one of two options, basically agreeing to commit to the direction of the mandate, or not. Choosing the former meant you signed up to this cult-like pact. The latter choice would mean that you were requesting a settlement payment and would “leave the EF without delay.”

This unsettling contractual suicide agreement went out as a draft in late February, and The Denver Post says that resistance to signing such an agreement was “swift and vocal.” About 80 of the Ethereum Federation’s 250-ish employees voted to nix the suicide pledge. Nevertheless, when the mandate was sent around in its final version in March, the suicide pledge remained – albeit in the form of a text with illustration – rather than in the body of the copy.

As the ‘Source Seppuku License’ had basically morphed into an artwork, rather than part of the main text of the mandate, the EF would subsequently argue that the suicide pledge to employees was just “part of the artwork of the mandate.” Importantly, Ethereum founder Vitalik Buterin insists that the artwork was “not meant to be taken literally.”

In March, resistance to the mandate, led by then-employee Kayleen Fulton, culminated in a response letter endorsing the general direction of the document but declining to tick any boxes, and declining to resign. Though this formal but quiet revolt bore 53 names, only Boulder woman Fulton and a colleague who helped organize the letter were fired.

The reasoning for Fulton being singled out was simple, according to a quote published by the Denver Post, cryptocurrency founder Buterin reportedly said that you should not “reward making a stink with outcomes.” By September, eight senior employees had left the EF, with most of the 53 protest letter signees either resigning or being terminated.

Fulton, who was on a salary of $195,000 per year as a lead in the Protocol Support team, is seeking unspecified damages from the Ethereum Foundation. She also disclosed her ovarian cancer diagnosis to the company on March 24, 2026, roughly two weeks before being fired. The lawsuit thus also claims interference with her rights under the Family and Medical Leave Act.

Nvidia-based compute is getting scarce and expensive for Chinese AI labs on both of their main routes, buying export-compliant cards and renting abroad, and the Financial Times reports that Nvidia’s own crackdowns are part of the reason. Nvidia has told cloud partners worldwide that at least 51% of their services must go to non-Chinese firms, while Chinese companies have bought more than 1 million Nvidia gaming and workstation cards this year to cover the shortfall. Meanwhile, a B300 rack that sells for about $600,000 internationally reportedly fetched $2.8 million in China last month.

Chinese customers have ordered more than 6 million of Nvidia’s export-compliant RTX Pro 5500 cards. That is at least twice the 3 million that the company could reportedly manufacture in 2027. One source told CNBC that it was proposed that Moonshot pay 30% to 50% more upfront, in comparison to a non-Chinese entity.

Many Chinese groups have relied on overseas leases for advanced AI work, which can include model training, and these tech groups have been the biggest clients for data centers in Southeast Asia. Data centers unable to find non-Chinese clients could be forced to pull back supply, and it’s “difficult to find enough non-Chinese clients outside the US,” one Singapore-based group told the FT. While Nvidia hasn’t confirmed or denied its new rule, implementing it would ease criticism from U.S. lawmakers just as Chinese demand is growing.

What Nvidia told partners has come through verbal instructions, via sales and regional teams, and applies globally rather than just in Asia. Existing deals and leases are not changed, but new ones must comply. Nvidia’s whitelist more than halved its authorized Asian buyer count, which encouraged more Chinese groups to lease over other options, including smuggling. On top of this, Fleet Intelligence tracking is now required for Southeast Asian providers that want to become Nvidia Cloud Partners. All of these combined — whitelist, cap, and tracking — may act to alleviate U.S. concerns.

Among companies that have moved to renting, Moonshot has held discussions to rent capacity from neoclouds that host in Europe with Nvidia GPUs. Specifically, it’s looking for Nvidia Blackwell systems, which export controls bar from China; one source said the talks covered clusters of 8,000 or more Blackwell GPUs in Europe. These clusters would handle inference, serving models to end users, and the European talks for them happened after the White House said Moonshot accessed Blackwell chips through a facility in Thailand. The firm has been fervent about its intentions to secure more compute.

Moonshot isn't the only Chinese company looking to secure Nvidia chips for AI training. Tencent has a deal with Oracle to lease 100,000 GPUs in Southeast Asian data centers. ByteDance and Alibaba are also pursuing similar long-term leases, and most of these overseas data centers run chips like the forbidden B300. MiniMax, like Moonshot, also leases significant compute both at home and abroad.

The big reason is that domestic AI chip supply is simply not up to the task, although not for a lack of trying. Huawei is expected to hit 1.6 million chips this year, with about 1 million from Alibaba and Baidu, and 300,000 from Cambricon. Total supply this year will be up to 3.5 million, including about 1 million made overseas, against a demand that far exceeds 5 million. That number could more than double next year.

Part of the problem is that the export-compliant cards Chinese firms have been buying, mostly the RTX Pro 6000D, RTX Pro 5000, and RTX 5090, are mostly useful for simpler work such as prefill. Even so, the discontinued 6000D’s pricing in China has reportedly doubled. Huawei’s Ascend 910C outperforms them in most areas, but these lower-end options are still coveted, partly because of a preference for CUDA over Huawei’s CANN. Nvidia’s programming platform is supported by most AI frameworks and libraries, and much in-house code is optimized for it.

Then there’s the RTX Pro 5500, with 84GB of GDDR7 with ECC and 1,398 GB/s of memory bandwidth. The card runs on a full PCIe Gen 5 x16 interface, draws up to 600 W, and can be split into up to two MIG instances. That still leaves it well short of a B300, which has about 3.4 times the memory and 5.7 times the bandwidth, plus NVLink, which the 5500 lacks.

Indicated orders from China are not precise, but the total of over six million includes more than three million from ByteDance, Alibaba, and Tencent. The big three ordered at about $11,400 each, for a total sticker price over $35 billion. This is difficult to fill when there may be fewer than three million produced next year, and partners might only actually get 5% to 10% of the original ask. Starting in 2027, much of Nvidia’s TSMC capacity may shift to Rubin, taking more production, while the RTX Pro 5500’s early samples are due in December.

On the legal side, it’s currently easier to rent than to own as current U.S. law does not give regulators broad authority over overseas cloud access. The Remote Access Security Act (RASA), which would extend U.S. export controls to that area, has sailed through the House but has not yet passed the Senate. Those directly affected — neoclouds and related financiers — price in a possible ban regardless, which drives the upfront premium.

China’s side is not completely clean, either, with about 600,000 H200s reportedly stuck in storage in Hong Kong awaiting shipment to the mainland. Beijing is withholding approvals for large-volume imports such as this. Only relatively small quantities have come in during recent months, for some big internet companies, with others coming through intermediaries and indirect routes in small quantities. The price: over $900,000 for an eight-card H200 server in China at the end of last month, about 3x the cost a year ago. This is despite the fact that H200 sales are already under U.S. license.

The first test that will show how many cards will actually land occurs in Q1 2027, when the RTX Pro 5500 is expected in commercial deliveries. For rentals, whether or not the Remote Access Security Act is a factor depends on a Senate vote, which is not yet scheduled. Nvidia’s Q3 results come in soon, on Nov. 17, which could bring some illumination.

With CEO Jensen Huang under scrutiny lately over reports that he was targeted by an alleged Chinese spy, which Nvidia’s board is now investigating, he’s going to feel the heat even more just a day later, when lawmakers have asked him to attend a closed-door briefing. He’s been pushing for laxer controls and more access, so the assumed 51% rule will also be put to the test.

Less than 24 hours after he admitted to having an affair with Alice Huang, a Megaspeed executive suspected of being a Chinese spy, Nvidia CEO Jensen Huang has been asked to appear before the House Select Committee on China. The Committee issued a letter today, signed by Rep. Brian J. Mast (R-FL), Rep. John Moolenaar (R-MI), and Rep. Eric A. Crawford (R-AK). An X post featuring the letter states that the letter "expresses concerns over NVIDIA’s security protocols against foreign adversary espionage and Mr. Huang’s reported ties to a Chinese intelligence-linked executive of a Singapore-based data center company."

"Dear Mr. Huang: We are writing to request that you appear before our committees for a joint, closed-door briefing on NVIDIA’s security protocols against foreign adversary espionage and your interactions with a publicly reported People’s Republic of China (PRC) intelligence asset: Megaspeed executive Alice Huang," the letter begins.

It goes on to say that recent reports surrounding the affair "raise significant national security concerns regarding the PRC’s access to sensitive U.S. technology and information. "The issue of PRC infiltration and access to cutting-edge U.S. technology is core to the investigative work of our three committees this Congress. It is vital that Congress determines the extent to which U.S. national security has been placed at risk."

The closed-door hearing is set for November 18, 2026; whether Huang will attend remains unclear. The letter also allows for Huang to set an alternative date during while the 119th Congress is still in session.

On Sunday, Huang admitted to having an affair with Alice Huang, a former executive of Singapore-based Megaspeed. It is alleged that the latter was recruited by China's Ministry of State Security to gather information and help China get its hands on Nvidia's AI GPUs, the most powerful of which are banned from export to the country by Washington. Megaspeed has been accused of smuggling $2 billion of AI chips into China.

In a statement to Nvidia employees, Jensen Huang said, "To my colleagues at NVIDIA, I owe my family and all of you an apology. I was unfaithful to my wife. My actions hurt her and our children. There is no excuse for what I did. I am deeply sorry." As Huang's statement noted, Nvidia has opened an independent investigation into its CEO's conduct regarding the national security concerns the story has laid bare. The board of directors stated, "While the Board has no reason to believe that either national security or NVIDIA secrets were compromised, the Board's inquiry will examine all available information."

Nvidia shares dropped by around 5% in early trading, but have since recovered some of their losses. The company has rocketed to a market capitalization of over $4 trillion as the global hardware leader of the AI boom. Its powerful GPUs are in high demand for both the training of AI models and inference.

Processors generating excess heat play a significant part in contemporary data center design, cost, and resource use. However, things could be vastly different if AI chips were more efficient and ran far cooler. South Korean chip startup DEEPX, recently featured by CNBC, thinks its AI chip designs are the answer. DEEPX demonstrated its DX-M1 processor’s cool-running capabilities in a bizarre new dairy-based thermal benchmark. While rival chips caused a knob of butter to sizzle in seconds, atop the DEEPX solution, the butter block remains solid.

Concerns over AI data center proliferation are growing worldwide. These developments are shaping business, the environment, and politics. Some people have very strong feelings about them, and hundreds of people have risked being thrown into jail protesting data centers. The CNBC report linked in the intro looks into why modern data centers are problematic, and indicates that the core issues stem from the use of hot-running processors and the extensive power and cooling apparatus they need.

DEEPX says its simple answer is to “make the AI chips themselves run cooler.” The CNBC video includes a demo of the ultra-low-power DX-M1 processor. In a side-by-side test against unnamed rival AI chips, you can see the DX-M1 NPU is clearly cooler. DEEPX CEO Kim Nok-won claims a temperature difference of 25 to more than 40 degrees Celsius compared with competitors. Kim said the side-by-side chips processed “the same AI workload… and every chip melted the butter except the last chip [DX-M1].”

The dairy-based thermal challenge is certainly eyebrow-raising, but we note some big gaps in the comparison information. Most notable was the question of how fast each processor tackles the test workload. Anyone can run a chip cool if the power and clocks are scaled back. PC enthusiasts undervolt and/or underclock their GPUs all the time for efficiency, better thermals, and reduced fan noise.

DEEPX’s DX-M1 NPU has been produced on Samsung 5nm since August 2025, according to The Elec reports. It has won approximately $13.3M worth of orders thanks to this sliver of silicon. The company is planning to move forward with the next-gen DX-M2 AI chip, which is based on Samsung 2nm, with its mass production aiming for H2 2027.

In conclusion, these NPUs look set for edge computing and robotics applications, so they aren’t really competing in the same space as the racks of power-gulping Nvidia Blackwell and Ruben GPUs featured in the CNBC news feature. Eventually, we might see the hundreds or thousands of hot-running Nvidia GPUs with beefy liquid cooling apparatus get replaced by cooler-running custom accelerators. Such an innovation could cool the backlash against AI data centers. However, DEEPX’s DX-M1 or even DX-M2 chips aren’t going to compete in that space, so this butter test is a bit of a red herring.

The CNBC report also highlights SK hynix’s work on iHBM, a next-gen low-power consumption, and cool-running. The ‘i’ stands for ‘Integrated Cooling Element,’ according to an exec talking to CNBC. CoolIT is also trying a similar approach by bringing water cooling even closer to the heat-generating silicon.