Hi,
I'm trying to develop a VHDL GDDR5 controller and am slightly confused regarding the JDEC spec document - the different memory configuration possibilities all seem to be short three address bits to attain the capacity specified...?
For example 512M memory, 32x mode, with 8 banks (larger configurations use 16):
Row address bits are A0-A11 (12)
Column address bits are A0-A5 (6)
Bank address bits are: BA0-BA2 (3)
(See JDEC spec document JSED212B.01 pg 12 Table 7 and Table8)
But that only addresses 2^12*2^6*2^3=2Mi addressed locations each of x32bits = 64Mbs....
You can do the same with any other configuration listed and still not get the capacity specified. This isn't related to bank groups or the fact that GDDR5 multiplexes it's address lines but clearly there's something else non-standard (different to DDR3) that I'm missing?
Anyone with insights please advise?
I'm trying to develop a VHDL GDDR5 controller and am slightly confused regarding the JDEC spec document - the different memory configuration possibilities all seem to be short three address bits to attain the capacity specified...?
For example 512M memory, 32x mode, with 8 banks (larger configurations use 16):
Row address bits are A0-A11 (12)
Column address bits are A0-A5 (6)
Bank address bits are: BA0-BA2 (3)
(See JDEC spec document JSED212B.01 pg 12 Table 7 and Table8)
But that only addresses 2^12*2^6*2^3=2Mi addressed locations each of x32bits = 64Mbs....
You can do the same with any other configuration listed and still not get the capacity specified. This isn't related to bank groups or the fact that GDDR5 multiplexes it's address lines but clearly there's something else non-standard (different to DDR3) that I'm missing?
Anyone with insights please advise?
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