Nvidia ostensibly brought back the RTX 3060 12GB in late June to help gamers cope with the ongoing component crisis. Since most of the world's memory is being routed to expensive AI chips, the RTX 3060 12GB offered gamers a 12GB VRAM pool for what was supposed to be a reasonable price... if only the price remained steady. As of today, this five-year-old GPU now costs almost $500 across the world, which is just as much as the RTX 5060.

MSI's Ventus 2X OC variant of the RTX 3060 12GB launched at just $300 on its online store and $340 on Newegg. It's now listed for $480 in both places. That's a 60% increase in less than two months, compared to its lowest price. Similarly, Asus' Dual V2 OC variant was released with a $330 MSRP, which quickly rose to $360 on Newegg, and the same card is now sitting at $500, constituting a 52% price hike from launch.

The cheapest RTX 3060 12GB right now, the Gigabyte Windforce OC Rev 2.0 model, currently costs $460, up 35% from the $340 it arrived at in late June. The same GPU is listed for 417 GBP on Amazon UK, which converts to $566. In Europe, the cheapest variant is once again Asus' Dual V2 OC, costing 386 EUR on Amazon Germany, or roughly $450; price aggregator Geizhals says it was just 330 EUR a month ago.

In comparison, the RTX 5060, which is two generations newer, can be easily had for around $450 from a bunch of different vendors. That GPU is not only significantly faster but also more efficient, while carrying the latest features such as DLSS multi-frame gen support. In our GPU hierarchy, the 5060 is actually just as powerful as the RTX 3070 at 1080p and 1440p, and it carries the same amount of VRAM, 8GB.

That VRAM capacity is the only thing going for the 3060 12GB at this point, and even with extra memory to utilize, the GPU isn't really capable enough to deliver better performance in games. Plus, you can find better deals on the used market, or even renewed offers from big retailers, so the re-launched RTX 3060 12GB just doesn't make sense from any angle right now, despite its still-decent 1080p chops.

The 3060 is cheaper to produce for Nvidia, thanks to its slower GDDR6 memory compared to the GDDR7 you get on the 5060. It's fabricated on the older, less in-demand 8nm node from Samsung, compared to TSMC's N5, which should also help with yield. But none of those manufacturing leniencies seem to be trickling down to the customer. Even the RTX 5050, which can be had for $300, is faster than the revived RTX 3060 12GB.

A Sony PlayStation 3 console modder has shared images and details of their ‘PS3 Pro v3’ design. On the PS3 subreddit, Fun-Equivalent-7785 showcases this project, which includes a heavily customized 3D-printed top case, dual Noctua fans, and liberal use of tin foil. While you may love or hate the new aesthetic, the results seem impressive, with the PS3 overclocked like a champ and running very cool and quiet.

Yes, this is at least the third PS3 Pro mod from Fun-Equivalent-7785, but all projects benefit from refinement. PC builders will be familiar with the dread of unwrapping their motherboards and seeing the revision number is v1.0.0, contrasting with the pleasure of seeing v1.0.3. Moving swiftly back on topic, you can look and read about the first version of this PS3 Pro project here, and there’s also a video about the PS3 Pro v2.

In some comments following the original post, Fun-Equivalent-7785 provides more technical details about the PS Pro v3 mod. They claim that the processors aren’t delidded, nor undervolted. Instead, they have installed “server heatsinks” on Sony’s custom PS3 processors. In front of these, one can clearly see two chunky Noctua fans, presumably pushing much air through the heatsink fins. Tinfoil has been used to shape the ducting. The Noctua fans are somewhat wider than the heatsinks, and overall it is “super silent.”

One screenshot shows an overlay from the ‘PS3 Pro v3’ running. Specifically, we can see the CPU is 40 degrees Celsius, the Reality Synthesizer (AKA the RSX, a GPU) is 42 degrees Celsius, while the fans are only rotating at 24% max RPM. This is while the RSX is overclocked to 750 MHz core and 1,000 MHz memory. A stock PS3 would achieve around 500 MHz core and 650 MHz memory.

Those uprated numbers result in broadly improved performance in PS3 gaming. “Almost every game has a boost in FPS,” crows Fun-Equivalent-7785. The results seem pretty worthwhile, especially if you like the look of this design from Fun-Equivalent-7785.

While it is an interesting project that might inspire you to do something similar with your old PS3, there are some aspects to modding like this that you have to consider. This particular project isn’t a ‘product’ so you can’t just buy a kit to copy it. There aren't yet 3D printer resource files shared on GitHub or similar. We are also not aware of any other shared resources to make it easy for other modders to replicate the PS3 Pro v3 project.

Lastly, please remember, before you risk your precious PS3 under the knife, there can be risks to modding. For example, there are many opportunities to inflict accidental physical damage to electronics when undertaking DIY projects like this. Moreover, overclocking may shorten the lifespan of your console's components, and applying unofficial firmware has the potential to soft- or hard-brick your system.

Data centers are unpopular among U.S. citizens right now, with projects facing resistance and moratoriums across the nation. While we’ve seen over a hundred protests against the developments happen simultaneously, researcher Andy Masley wanted to answer one question: what is driving the pushback against these projects? Is it big tech? AI skepticism? Or maybe even China? But after reviewing data from multiple polls, his answer seems quite simple: the “object-level local environmental and economic harms” that have been widely reported in the media.

Multiple data center sites owned and operated by different hyperscalers have found themselves in hot water with the people surrounding them. The biggest issue that caught the attention of the public is the massive amounts of electricity that these developments use, requiring grid operators like PJM Interconnection to expand their infrastructure to service AI data center needs, which costs billions of dollars. Unfortunately, the capital expenditure for these upgrades has typically been passed on equally to all users, with ratepayers seeing price hikes of up to 76% on their utility bills.

It has gotten to the point that President Donald Trump had to make tech giants, AI hyperscalers, utility operators, and state governors sign a “ratepayer protection pledge” so that AI companies “pay their own way” when it comes to their electricity needs. But this move was too little, too late to halt increased electricity costs to the huge swathe of the American population that PJM Interconnection serves. Oregon is the only state, so far, to have passed a law that requires sites using 20MW or more to pay for their own share, with PGE, the state’s largest power provider, hiking data center bills by 30% while also cutting residential costs by 1.3%.

There have also been reports of two data centers in Georgia and another in Wyoming causing water issues in the surrounding neighborhoods. This includes low water pressure due to excessive consumption, a drop in quality with muddy water pouring out of taps, and water discharges that contaminated a city’s reclamation water supply. Aside from those, there are also problems with noise pollution, like the site that generates noise 24/7, as if “someone set up a vacuum, like in your living room,” and air pollution from mobile turbine generators and dedicated natural gas power plants.

All of these are “object-level” concerns, meaning these are specific issues that exist, have happened on other sites, and are directly observable by other people. However, Masley also points out that some of the coverage of these issues was either overblown or only showed the concerns of the residents, without putting them into the context of the actual project and comparing them with other existing data centers in other areas. Because of this, many people have become fearful that the issues found in other developments will automatically apply to the data center being proposed in their community.

Some data center developers also aren't helping to assuage fears. Some are pushing back against moratoriums and bans, and have begun suing local jurisdictions. One town in Pennsylvania listed 43 specific demands that the developer called “too difficult” and pulled out of negotiations before applying again, with the council calling the move an attempt at “approval by tantrum.”

Atari has officially unveiled the Atari x Activision Collection, a compilation featuring 39 classic Activision games on physical cartridges. An individual cartridge starts at $34.98, while the Ultimate Deluxe Set, which includes all 39 games, costs up to $999.96. Atari and Activision's latest collaboration brings the nostalgia and value of a physical cartridge to long-time retro fans and new gamers who want to relive the classics.

• Check out the Atari x Activision Collection on Atari

At a time when major manufacturers like Sony are giving up on physical media, it is refreshing to see Atari stepping up to keep the tradition of owning your games alive. Many gamers still appreciate physical media, which often goes beyond a simple disc or cartridge. Extras, such as unique artwork or packaging, matter to many collectors.

Although Atari is bringing back an impressive lineup of 39 Activision titles, only a select group, including Pitfall!, River Raid, Megamania, Enduro, Kaboom!, H.E.R.O., Keystone Kapers, Private Eye, Pressure Cooker, River Raid II, The Activision Decathlon, and Pitfall II: Lost Caverns, will arrive as Standard Editions. These Standard Editions are priced at $34.99 each and include a sleek black cartridge and a newly designed, full-color manual.

The Deluxe Edition, on the other hand, retails for $249.99 and comes in four different collections: Treasure, Speed, Secrets, and Victory. Each collection includes 10 games, except one, which has only nine. The Deluxe Edition, as the name implies, features deluxe editions of Activision titles on vibrant, colorful cartridges that will stand out in any collection. The Deluxe Edition also includes 10 woven patches and 10 enamel pins, plus a special collector slipcase to house the games.

Atari x Activision Collection

The Ultimate Deluxe Set, priced at $999.96, represents the pinnacle of the Atari x Activision Collection. The ultra-premium package includes all 39 classic Activision titles, combining the content of all four Deluxe Sets into one big collection. Building on everything offered in the Deluxe Edition, the Ultimate Deluxe Set adds 12 exclusive metal trading cards and a yet-to-be-announced collectible item.

All game cartridges included in the Atari x Activision Collection are fully compatible with the original Atari 2600 and Atari 7800 as well as the more modern Atari 2600+ and Atari 7800+ consoles.

If you want only one or two specific titles from the Atari x Activision Collection, buying individual cartridges is the most affordable option. However, if you are going to buy more than seven, the Deluxe Edition offers significant savings. You end up paying just $24.99 per game instead of the standard $34.99, a discount of up to 29% per title. The Ultimate Deluxe Set will not save you much compared with buying the Deluxe Sets individually. However, you do get the extra goodies and free shipping.

Pre-orders for the Standard Edition cartridges, the Treasure Collection, and the Ultimate Deluxe Set are officially up on Atari's website. These will ship in November 2026. The Speed Collection, Secrets Collection, and Victory Collection, on the other hand, will not be available until Spring 2027, Summer 2027, and Fall 2027, respectively.

It has become a tradition that every single quarter Nvidia reports record results that outpace all of its quarterly results before that. This Wednesday was no exception as the company posted revenue of $96.2 billion, which was up 106% year-over-year, due to rising demand for its AI hardware. But such results come at a cost, as the company has to invest massively in its future. In the second quarter of its fiscal 2027, Nvidia had to commit to procuring memory worth up to $160 billion, which includes its memory supply pact with SK hynix.

Nearly $100 billion revenue per quarter

For the second quarter of Nvidia's FY2027, which ended on July 26, 2026, the company's GAAP revenue hit a record $96.221 billion, up 18% quarter-over-quarter (QoQ) and 106% compared to the same quarter a year ago. Nvidia's net income totaled $59.688 billion, up 126% year-over-year (YoY), as its gross margin reached 75.0%. Sales of Nvidia's Compute & Networking hardware reached $88.299 billion, up 18% sequentially and 114% YoY, whereas sales of its graphics hardware hit $7.922 billion, up 12% sequentially and 46% year-over-year.

"AI has reached its inflection point," said Jensen Huang, founder and CEO of Nvidia. "AI is doing useful work. Its tokens are productive and profitable. Now, compute is revenue. And demand is accelerating. […] We have a golden age of new AI labs and startups, multiple frontier labs scaling in parallel, a thriving open-model ecosystem and physical AI coming online […]. The AI infrastructure buildout is at full steam. Vera Rubin, now in full production, was built to power exactly this moment."

Nvidia's results were driven by sales of its data center-grade AI hardware as various customers bought $89.023 billion worth of equipment, an increase of 18% sequentially and a rise of 117% compared to the same quarter a year ago. Hyperscalers purchased $48.710 billion worth of hardware from Nvidia (up 102% YoY and 13% QoQ), while revenue from AI Clouds, Industrial and Enterprise climbed to $40.313 billion (up 138% YoY and 25% QoQ), an indicator that while hyperscalers still purchase more equipment from Nvidia, the ACIE segment is growing faster. Sales of Nvidia's Edge Computing products were $7.198 billion (up 27% YoY and 13% QoQ), which means that sales of graphics products for PCs were strong despite shortages of GPUs and memory.

Commitments total $279 billion

Nvidia expects demand for its products to remain strong in the coming years. To meet that demand, the company increased its long-term purchase commitments from $119 billion in Q1 FY2027 to $279 billion in the second quarter. Typically, Nvidia's long-term supply commitments included pre-payments and commitments for wafer processing and advanced packaging at TSMC, as well as for HBM memory made by DRAM makers. This time around, Nvidia explicitly says that the bulk of the commitments are 'primarily related to the procurement of memory.'

Such huge commitments indicate that the company projects massive demand for its data center AI products in the coming years. During the conference call with financial analysts and investors, it indicated that its customer forecasts point to doubling demand next year, but Nvidia currently believes its supply chain can support about 70% growth.

"Even though our demand is much greater than 70%, our supply allows us to confidently deliver 70%," Huang said. "The unconstrained would be a lot, a lot higher. […] We have secured a lot of supply, but we just need a lot more."

To that end, the $279 billion supply commitment should be interpreted as not a precautionary inventory-building, but a strategic move to ensure shipment growth. Nvidia is effectively reserving memory and other capacity because it expects demand to exceed what the supply chain can deliver through at least the end of FY2028, as its management explicitly says supply will remain a bottleneck at least through FY2028.

$108 billion per quarter envisioned in Q3

For the third quarter of FY2027, Nvidia expects revenue of approximately $108 billion, ± 2%, with no data center compute revenue from China included in its outlook due to uncertainties with export and import licenses. The company projects a GAAP gross margin of around 74% and expects GAAP operating expenses of approximately $9.2 billion.

Nvidia's NVLink Fusion program gives the company's partners the building blocks necessary to connect custom chips with the NVLink scale-up domain used to join many separate processors into a single coherent system like the Vera Rubin NVL72 rack-scale accelerator. Today, Nvidia is adding a new building block to that toolkit: NVHBM, a custom implementation of the high-bandwidth memory that underpins practically every AI accelerator in use today.

As Nvidia describes it, NVHBM is a custom HBM base die that promises higher bandwidth, lower power usage, and a smaller on-die footprint than traditional HBM4e. Nvidia says it's designed and validated with "leading memory vendors," so it promises custom silicon developers faster time-to-market than implementing commodity HBM from the ground up. But it's worth re-emphasizing that this isn't an HBM replacement. Instead, it's a new building block that Nvidia is only offering to its custom silicon partners.

Memory bandwidth is everything for AI accelerators, and NVHBM promises up to 30% higher bandwidth per stack than standard HBM4e. For memory-bandwidth-bound AI workloads, that higher bandwidth translates into higher throughput, such as a higher tokens-per-second rate for AI inference.

The custom NVHBM base die also reduces the footprint of memory-related circuitry on the main custom accelerator die. Traditionally, the HBM memory controller has been incorporated into the primary silicon die on the package. NVHBM instead moves the memory controller into the base die of the HBM stack and provides a smaller custom PHY that NVLink Fusion customers can then integrate into their designs.

Nvidia says this approach frees up precious package real estate that can then be used for additional compute die area — up to 30% more compute on the primary silicon die. NVHBM further promises to simplify the interposer routing used to join multiple chips together for designs using advanced packaging techniques.

NVHBM also provides power savings versus off-the-shelf HBM4e stacks. As Nvidia has continuously hammered home in the Vera Rubin roll-out, every watt that isn't going into token production is a watt wasted. Nvidia says NVHBM uses 15% less power than commodity HBM4e, and that power savings can be banked for performance-per-watt improvements, reallocated into more functional units for a custom accelerator design, or translated into higher sustained performance within the same power budget.

Higher bandwidth at lower power is a huge win for AI accelerators that are moving massive data structures like model weights and KV caches around, especially when those savings are multiplied across many thousands of chips. The energy saved on data movement can be plowed back into higher performance from the accelerator itself or reallocated to support larger numbers of accelerators within the same fixed power envelope.

But these are, as of now, reasons for Nvidia's prospective partners to consider incorporating NVLink Fusion and NVHBM into their custom designs, not benefits that will materialize in the Rubin rack-scale systems already in production.

Along with NVHBM itself, Nvidia announced that Amazon's Annapurna Labs will be its first partner on NVHBM. , and Annapurna VP Nafea Bshara says: “We look forward to this technology collaboration to benefit future AWS infrastructure designs.” Annapurna's next-generation Trainium 4 AI chips will already support the NVLink Fusion scale-up interface, so it seems likely that follow-on chips will support NVHBM, too.

Groq's former chief architect stood on stage at Hot Chips 2026 and presented his former company's inference chip as Nvidia silicon. Igor Arsovski, now Nvidia's VP of hardware, presented the Groq 3 LPX rack's architecture and published the first third-party benchmark of the hardware: Artificial Analysis measured it at 3,431 output tokens per second on a 100K-context Gemma 4 31B reasoning workload, roughly four times the 870 tokens per second of the next-fastest public endpoint. Arsovski said the rack is already in production, built on the LP30 chip Nvidia obtained through its $20 billion Groq deal in December 2025, the same deal that pushed the Rubin CPX it replaced off Nvidia's roadmap.

SRAM without HBM

Artificial Analysis ran the comparison on a private, pre-release Gemma 4 31B endpoint served through Google Cloud, taking the median of 50 sequential client requests at a concurrency of one, while the public providers it measured against ran shared production serverless endpoints. Serving one request at a time produces the highest per-user token rate the hardware can post, and it's not directly comparable to the multi-tenant conditions the other endpoints run under.

Nvidia's on-stage demo showed a higher figure still, 10,996 tokens per second on the same 31B model, which Igor Arsovski, Nvidia's VP of hardware, flagged on stage as "self-reported" before telling the audience the aim was "third-party verified independent benchmarks that you guys can trust." Gemma 4 31B is also a dense model small enough to sit inside a single LPX rack, and the picture at trillion-parameter mixture-of-experts scale, where memory capacity becomes the main constraint, went unaddressed.

Each LP30 carries roughly 500MB of on-die SRAM and no HBM, so a full LPX rack of 256 chips holds 128GB of memory delivering 40 PB/s of aggregate bandwidth against 315 PFLOPS of FP8 compute, with 350 ns of chip-to-chip latency in a Vera Rubin-compatible, MGX liquid-cooled rack that scales past 1,000 LPUs.

Keeping model weights resident in SRAM rather than streaming them from HBM removes the memory-access latency that dominates single-token decode, and the design drops caches, branch prediction, and out-of-order execution in favor of a fully deterministic pipeline that the compiler schedules at clock-cycle granularity. The architecture descends directly from the Tensor Streaming Processor that Groq, founded by ex-Google TPU engineer Jonathan Ross, described in a 2020 ISCA paper titled Think Fast, the same title Arsovski and Raghavan reused at Hot Chips.

A Rubin GPU carries 288GB of HBM4, roughly 576 times the memory of a single LP30, so a 31-billion-parameter model at FP8 needs on the order of 62 LPUs to hold its weights, and a large mixture-of-experts model runs into four figures of chips across several racks. Capacity is the cost of the SRAM-only design, and it's why Nvidia is describing the LPU as for decode rather than as a general-purpose replacement for its GPUs.

Determinism lets the compiler predict power draw cycle by cycle, which Nvidia uses to pre-order current from the rack's regulators ahead of demand, cutting voltage droop by more than 60% and overshoot by more than 70% against an uncompensated load. The same per-block scheduling lets the hardware equalize heat instead of throttling to the hottest tile, which Arsovski put at roughly 10% to 11% additional performance under a fixed thermal limit. "By doing this, we can actually get more utilization of the chip under the same thermal limit, basically. So we can actually get, again, about 10 to 11% more performance under the same thermal limit. So this is another benefit of deterministic execution."

Across racks, Nvidia synchronizes chips to a single virtual clock in what it calls a plesiosynchronous network, with each chip acting as both processor and router so the fabric needs no adaptive routing or congestion sensing, and clock drift between chips is compensated at the chip-to-chip links. Asked during Q&A about the blast radius of a chip that fails mid-workload, Arsovski said users "would experience the exact same as any other hardware in the industry" and would "just checkpoint it or reconfigure the hardware."

Splitting inference with Rubin

Nvidia is pitching the LPX rack as a decode co-processor bolted onto Vera Rubin NVL72, with Rubin GPUs handling the compute-heavy prefill phase and building the KV cache while the LPUs generate output tokens. Nvidia showed three ways to divide the work: disaggregated prefill and decode; attention-FFN disaggregation, which keeps attention and its cache on GPU HBM while the LPU runs the feed-forward layers; and external-draft speculative decoding, where a small model on the LPU proposes tokens that the GPU verifies in parallel, with only draft tokens crossing the link.

An FPGA bridges the synchronous LPU domain and the asynchronous world of host I/O and GPU hand-offs, and Nvidia's Dynamo runtime, together with an LPU extension to CUDA, orchestrates the split. The company put the gains from these modes at roughly three-to-five-times over Rubin alone on a two-trillion-parameter workload with a 400K-token cached context, all Nvidia-measured.

Cerebras CS4

Cerebras used the same Hot Chips session to present its CS4 wafer-scale system, which chief system architect Jean-Philippe Fricker said runs up to 30 times faster than GPUs and doubles the token rate of the CS3 while carrying 10 times the token capacity. Each CS4 rack packs three wafer-scale engines into a new modular platform Cerebras calls Nexus, built around pluggable compute "backpacks" that separate power, compute, and I/O, and Fricker put its memory bandwidth at 43 PB/s, which he told the audience was "2,000 times higher memory bandwidth than Nvidia's next-generation Rubin chip." Cerebras also has a partner for the prefill side of the same problem: it agreed in July to pair AMD Helios GPUs for prefill with its wafer-scale engines for decode, the same division of labor Nvidia now builds in-house with Groq.

Nvidia pulled the Rubin CPX, its own GDDR7-based long-context accelerator, to focus on shipping the LPU this year, a decision VP Ian Buck laid out at GTC 2026. The $20 billion deal that produced the LP30 was structured as a non-exclusive IP license plus the hiring of Ross, president Sunny Madra, and most of Groq's engineers, a form that avoided a formal merger review. Arsovski opened the Hot Chips talk by calling it "a pinch me moment for the Groq team that's now integrated into the Nvidia group."

Senators Elizabeth Warren and Richard Blumenthal wrote to the FTC and to Nvidia in early 2026, arguing the arrangement acquired Groq "in all but name," and no formal, deal-specific investigation has been confirmed as of late August.

Full Nvidia Groq Hot Chips 2026 presentation

The U.S. Department of Justice and FBI revealed in a statement Wednesday that it had seized domains related to platforms that it claims were operated by China state-sponsored hackers. The press release says the Federal Reserve, Department of Energy, Department of Justice, Department of Health and Human Services, NIH, NASA, and U.S. Senate all experienced "computer intrusion activity."

The Justice Department says a state-sponsored group known as QTFY is responsible for the intrusion, which the U.S. government claims came to be through two pieces of malware: QTRouter and QScan. The release says the People's Republic of China (PRC) Ministry of State Security was among QTFY's paying customers.

According to the U.S. government, QScan "scans and automatically infects thousands of [IoT] devices worldwide." Those devices are then added to the QTRouter network. It's a botnet, but the Justice Department also calls it an "obfuscation layer" to mask the origin of malicious traffic. QTFY's system has been used to compromise U.S. critical infrastructure since 2018, according to the affidavit.

The group is said to be employed by the Nanjing Xinjiuwei Network Technology Company, which we were unable to find any information on.

As part of the action, the Justice Department seized three domains: qtproxy.xyz, qt-proxy.org, and qt-team.com. Those domains now show the seizure notice you can see below.

The investigation into the group began as early as 2019, when the FBI looked into a system intrusion at NASA related to the CVE-2019-11510, which was subsequently patched. The FBI traced the activity back to two Gmail accounts and a phone number with a +86 country code (the code for the PRC).

The group allegedly rented infrastructure from commercial platforms, leading to a series of abuse complaints to the emails by hosting provider Hostwinds. The FBI says the group obtained the three domains it seized between 2022 and 2024, registering them with domain registrar Namecheap and paying through PayPal.

Although the PRC routinely denies hacking activities in the U.S., Chinese officials reportedly acknowledged that the government was behind a series of attacks on U.S. infrastructure late last year. In 2024, 30-year-old wiretap systems deployed by the U.S. government in telecom and internet providers were reportedly compromised by Chinese attackers.

Xbox has unveiled its long-rumored new disc-to-digital service, which will let players who own physical copies of games claim digital entitlements, playing them as if they own digital copies. In an announcement, Microsoft confirmed support will include digital benefits such as Xbox Play Anywhere and Xbox Cloud Gaming.

"Players have spent decades building their XBOX libraries. Some games were purchased on disc. Some were purchased digitally. Many span multiple generations of hardware," the company stated in a blog post on Xbox Wire. Microsoft says the new feature "brings the benefits of digital to physical discs." Xbox Insiders can test the feature from August 31.

The company says that "most" disc-based games for Xbox One and Series X support the new feature. If you insert a game disc into your Xbox One or Series X, you can claim a "digital entitlement" by launching the game.

That means that games you own on disc will be accessible through your digital library, including support for Xbox Play Anywhere and Xbox Cloud Gaming "where supported."

You can also keep using your physical copy as normal. Microsoft says that "thousands" of titles are supported, with more being added over time, but confirms that not every title will be available at launch.

The news will be of some comfort to fans of physical media, especially given recent developments in the gaming sphere, notably Sony's decision to end physical media with its next console. While the move does give physical media a new lease of life in some regards, it still marks a shift away from physical media towards online, digital libraries, encouraging users to transition from physical to digital.

Lux Claridge, the teacher who was arrested in Emporia, Kansas, during an AI data center meeting for clapping, said that the city has dropped the charges against them. According to 404 Media, the Emporia assistant city attorney told Claridge’s lawyer that the case has been dismissed without prejudice in municipal court because of conflicts on the matter. Unfortunately, that doesn’t mean that they’re in the clear yet, as the case has been bumped to the County Attorney’s office for further review.

“Today, I was informed by my attorney that the city has dropped my charges and has passed my information along to the county,” Claridge told the publication. “As far as I know, I’m in the clear unless the county is feeling froggy.” This series of unfortunate events started when the teacher politely clapped five times after a speaker gave their comments against the proposed data center in the city. It seems that the city’s commissioners had warned against clapping and other reactions beforehand, saying that it was disruptive. So, when they clapped, someone from the crowd, presumably someone with authority, asked a police officer to take the next person who claps outside of the venue.

This was when several cops approached Claridge, who asked them to leave, but they stood firm, saying, “I have a right to speak.” When the authorities insisted that they go, they just said, “Drag me out,” after which the four officers cuffed the individual, physically lifted them, and hauled them off to the Lyon County Jail. They were finally let out after eight hours, after which they were charged with disorderly conduct and interfering with a law enforcement officer.

After this incident, the city canceled the public meetings set for August 5 and August 19, 2026, and moved them online. The city said that commissioners were receiving death threats from external sources and that it’s taking the measure to protect the safety of its officials and the public. However, it also didn’t allow public comments, which some are questioning, although it did tell citizens that they can phone in their concerns instead. Nevertheless, the city will return to in-person meetings soon, and it will also open public comments once more, with Claridge quoting Emporia mayor Becky Smith saying that she’s “willing to give us another shot to act like grown-ups.” Emporia is expected to put the data center ban to a vote in November via public ballot. However, it also said that even if the people approve the proposed ordinance, it can only take effect after it has been ruled that the petition is deemed legal in the first place.

For as much as we might discuss the performance of an individual CPU, GPU, or other chip in a rack-scale AI system, the ultimate constraint on the performance of those chips is the amount of power one can get to the building and into each of the racks that contain them. The management and allocation of that power is a major concern for maximum productivity from a data center installation going forward.

During Nvidia's Hot Chips presentation on the Rubin GPU, the company emphasized this hard limit on data center capacity and touted the amount of compute that Vera Rubin NVL72 systems can deliver within an example fixed facility power budget of 100MW.

Nvidia says that the use of all of Vera Rubin’s power management technologies, in tandem with its DSX MaxLPS (Land, Power, Shell) suite of design and site-level dynamic power management resources, will allow operators to provision installations of 40,000 of those next-gen chips GPUs (or about 40 Rubin DGX SuperPODs) within that 100MW budget, and expects that hardware to deliver up to 2 zettaFLOPS (ZFLOPS) for NVFP4 inference and up to 1.4 ZFLOPS for NVFP4 training.

Doing some back-of-the-napkin math for ourselves from publicly available Rubin specs, we feel safe in assuming that those performance figures are estimated, not measured. The maximum number of achievable FLOPS from real-life workloads is likely to be significantly lower for a host of reasons.

But the overall point still stands: getting the most compute out of precious power budgets when planning the AI data centers of the future is going to require more refined planning, monitoring, and facility management than simply applying the coarse measure of estimated peak power draw for every electrical component in the facility. And Nvidia has those building blocks ready for data center constructors in the form of its DSX toolkit.

According to a companion blog post that Nvidia shared, as data center operators provisioned their facilities in the past, many of the assumptions they made around power usage focused on those fixed, worst-case power peaks per rack, potentially leading to inflated power budgets that end up stranding power allocation in racks that will rarely, if ever, use all of it.

In just one example, if there was an application load differential between racks in a cluster such that one system would benefit from having more power sent its way in that moment, it couldn’t be re-routed under a static provisioning scheme. The less-utilized rack would use less of its allocated power budget, and the more heavily loaded one might still run into the limits of an overly conservative guard band.

The DSX MaxLPS approach is meant to overcome the limitations of static power provisioning by instead applying an intelligent, dynamic scheme that is continuously aware of power usage at the chip level, rack level, and groups-of-racks level. Where unused power is available due to workload characteristics or idle capacity, Nvidia's Dynamic Power Software control loop can find and redistribute that energy to systems where it's most needed in the moment, maximizing the number of systems that can be installed and performance per watt from the facility over time.

In Nvidia's measured example of current GB300 racks, within a 540kW power budget and with static provisioning, an operator might be able to install four 135kW systems by statically provisioning for peaks rather than measured values from workloads. But in practice, as much as 170kW of that power budget might sit unused due to differences in rack utilization.

For modern rack-scale systems like Nvidia’s NVL72s, that’s an entire rack and change that could safely be installed within the same power budget, and indeed, that’s just what the company’s example shows. And across those five systems, the amount of reserve power allocated for peaks can be much lower.

At the rack level, DSX MaxLPS offers further flexibility through workload-specific power profiles. Much like the quiet, balanced, and high-performance power modes that client PC users are familiar with, Nvidia has produced rack-level power profiles that can be assigned to systems performing example workloads like inference, training, and more general memory-bound or compute-bound tasks.

As we noted, Nvidia didn’t share measured Rubin power or performance-per-watt results, but it has characterized the benefits of MaxLPS for prior-generation systems running inference workloads to prove the concept.

For a Grace Blackwell GB300 system running DeepSeek-R1, Nvidia says the past fixed-peak regime would have assumed a 1400W GPU TGP and an estimated rack power of 136kW. Applying MaxLPS, however, the typical GPU TGP under this workload falls to 1000W, and the total rack power falls to 101kW, all without affecting delivered performance.

That less conservative envelope translates directly into higher performance per watt, larger numbers of racks that can be installed within the same facility, and ultimately more tokens that can produce revenue for the data center operator or its tenants.

Nvidia further notes that designing a data center with MaxLPS from the start grants an operator greater flexibility over the life of the installation. For example, if a site starts as a training-focused facility outfitted with cutting-edge hardware, each installed system is likely to need a greater share of the available site power for that more intense workload, and so an operator might not want to populate every available floor space for those racks from the get-go.

But later in the life cycle, as training shifts to new generations of hardware and older systems transition into inference roles, the power demands of each GPU and rack will fall, and so a facility with dynamic power provisioning would be able to free up capacity that can then be used to install more hardware within the same facility and to generate more profitable tokens.

Another major component of MaxLPS in data centers deploying Vera Rubin hardware is the use of higher liquid coolant temperatures for the exclusively liquid-cooled Rubin NVL72 racks. Those systems are designed to work with 45 °C inlet coolant temperatures, much higher than for past liquid-cooled systems. We learned more about this “dry cooling” approach during our visit to Nvidia’s Vera Rubin proving grounds earlier this year.

The use of this higher coolant temperature for Rubin installations is important because the mechanical chillers used to shed waste heat in non-evaporative systems also consume a large portion of the site power budget – as much as 40% for past installations, Nvidia says. As with static provisioning for servers, the company notes that those chillers have traditionally been sized for the worst-case scenario that a facility might face, even if they’re operating well below that capacity for much of the year.

Again, this approach strands power that could be dynamically reallocated to compute given the proper operating conditions and site-level monitoring and management. Those chillers might still need to run during the hottest parts of the year, but outside of those conditions, the higher coolant temperature generally enables more power to be put to productive use, improving a site’s power usage effectiveness (PUE) figure, all else equal.

Power for AI data centers, whether generated by public utilities or behind the meter using alternative power sources, is expected to remain one of the most critical constraints for those facilities for the foreseeable future, and we heard that concern from multiple presenters during Hot Chips.

Nvidia’s DSX MaxLPS approach looks ready to provide the building blocks needed for dynamic allocation of that resource to extract the maximum possible performance per watt from Rubin facilities, and it reflects a comprehensive concern for the interplay of power and achievable performance that only seems likely to grow in importance going forward.

Newegg has come out with a new high-end AM5 bundle that pairs the venerable Ryzen 9 9950X3D processor, 32GB (2x16GB) Corsair Vengeance DDR5-6000 RAM, and a premium motherboard in MSI’s MPG X870E Carbon Wifi for only $1,345.99. You save $260 (16%), which, when you apply that beefy combo discount to the 32GB of RAM, makes it only $230, which is a solid deal for these expensive times.

• Check out all the RAM combo deals on Newegg

The RAM portion of the bundle, Corsair’s Vengeance RGB 32GB (2x16GB) DDR5-6000 CL36 RAM kit, is currently available on Newegg for a wallet-emptying $489.99 when bought separately. The good news is that the massive discount brings this RAM down to $230. This black kit matches the MSI X870E Carbon board and features a frosted RGB light bar that runs the length of the sticks. If RGB lighting isn’t your thing and you prefer a stealthy, unassuming look, you can turn it off. The DDR5-6000 speed lands in the sweet spot for the AM5 platform and is a worthwhile, good-looking option. The SK Hynix ICs under the heatsink pair nicely with the MSI board and offer plenty of overclocking headroom.

Next is the Ryzen 9 9950X3D processor. Before the X3D2 came out, this was the flagship X3D SKU and offered not only a lot of cores and threads (16c/32t) but also X3D cache (128MB) on one of the CCDs, which is great for gaming. Clock speeds start at 4.3 GHz, with turbo boosting a couple of cores up to 5.7 GHz. Between the clock speeds, core count, and extra cache, this processor is not only a great gaming CPU, but also awesome for any type of PC work that needs a lot of cores and threads, like video editing, 3D rendering, and even running VMs.

Last but certainly not least is the MSI X870E Carbon Wifi motherboard (one we reviewed in the past. We loved the robust power delivery (perfect for the 9950X3D), the dual Ethernet ports, EZ features, storage options (4x SATA, 4x M.2 sockets - one PCie 5.0) and ample connectivity on the rear I/O, including four USB Type-C ports (2x 40 Gbps). The all-black motherboard sports a cool RGB design element of the MSI dragon on the VRM heatsink to break up the monotony and offers some bling to the inside of your chassis.

In the end, we like this combo as it takes some of the pain out of buying a PC today. Priced at $1,345.99 and at a significant savings of $259.99 (16% off) with a free 240mm Cooler Master Elite AIO ($79.99 value) and AMD Game Bundle ($69.99 value), it will be tough to find a better deal out there for this wicked gaming (and productivity!) bundle.

Fujitsu gave us a detailed look at its 144-core Monaka server CPU at Hot Chips 2026 on August 24, confirming for the first time that the Arm chip runs dual 256-bit SVE2 vector units, down from the 512-bit SVE in its A64FX predecessor, and that its entire last-level cache sits on a separate 5nm die beneath the 2nm compute die.

Ryohei Okazaki, lead architect of Fujitsu's processor development team, presented the design as "a made-in-Japan CPU, specifically engineered for AI performance and power efficiency," built for what the company calls green AI data centers and subsidized by Japan's New Energy and Industrial Technology Development Organization. The chip ships in two SKUs: a 350W air-cooled part at 2.1 GHz base and a 500W liquid-cooled part at 2.9 GHz base, with evaluation samples available now and volume production in 2027.

Three dies, one stack

Monaka splits into three tiers of silicon: a 2nm core die on TSMC N2P, a 5nm SRAM die on TSMC N5 that holds the whole last-level cache, and a 5nm IO die. The core die stacks face-to-face on top of the SRAM die through hybrid bonding, sitting on the cooling side because it runs hottest, while the IO die connects to the SRAM die across a silicon interposer. Fujitsu keeps 2nm silicon under 30% of total die area, a split Okazaki said lets Fujitsu "accelerate the time to market for our 2-nanometer-based chip" by pushing everything that shrinks poorly onto the 5nm SRAM and IO dies.

Putting the full last-level cache on a distinct stacked die separates Monaka from AMD's 3D V-Cache, which bonds extra SRAM on top of a compute die that already carries its own L3, and lines it up closer to Intel's Clearwater Forest, where local cache sits in a base tile with compute stacked above. Fujitsu also moved the low-dropout voltage regulators onto the 5nm SRAM die because analog circuits scale poorly at 2nm, and placed them directly beneath the core's floating-point units to feed per-core dynamic voltage and frequency scaling.

Dr. Ian Cutress of More Than Moore asked whether Fujitsu was "doing anything special to minimize core-to-core latency" given that the core dies sit on opposite sides of the package and traffic routes through the IO die and back. Fujitsu pointed to the face-to-face hybrid bonding between the core and SRAM dies but declined to disclose latency figures.

From 512-bit vectors to 256

Chester Lam of Chips and Cheese asked why Fujitsu narrowed the vector datapath from the 512-bit SVE in A64FX to 256-bit SVE2 in Monaka. Okazaki said the chip is built "for [the] data center" and that Fujitsu wanted to "minimize the core size" for the best cost and performance, with the narrower units also cutting SIMD width for general-purpose code.

A64FX, the 7nm CPU that powered the Fugaku supercomputer and became the first chip to implement Arm SVE, paired its 512-bit vectors with on-package HBM2 for memory-bound HPC. Monaka drops HBM for 12-channel DDR5 at 8000 MT/s and runs two 256-bit SVE2 units per core, each aligned to a 256-bit load/store unit, with FP8 and INT8 matrix support added for inference.

The core carries mainframe-class reliability features Fujitsu inherited from its own processor line: ECC or duplication on the L1 and L2 caches, parity checks on execution units and registers, and a hardware instruction-retry mechanism to recover from transient errors. It also runs a three-level TAGE branch predictor and six ALUs for general-purpose throughput, on a core that Fujitsu measures at roughly 1.47 mm².

Performance estimates and rivals

Fujitsu estimates the 350W SKU at 4,355 GFLOPS in DGEMM and 69.7 TOPS in INT8, and the 500W SKU at 6,013 GFLOPS and 96.2 TOPS, with both parts rated around 500 GB/s in STREAM Triad. The company claims up to two-times AI performance and over 50% TCO reduction against unnamed comparisons, and credits ultra-low-voltage operation, running the core around 30% below nominal voltage for roughly half the power, for holding 144 cores inside the 350W envelope. Okazaki described the voltage technique as delivering "energy saving comparable to moving one generation beyond the 2 nanometers," achieved with custom SRAM and a proprietary CAD flow tuned for non-standard low-voltage operation.

By 2027, Monaka's 144 cores will land in the middle of the Arm server field rather than at the top of it. AWS's Graviton5 reaches 192 Neoverse V3 cores on a single 3nm die, Ampere's roadmap runs to 512 cores in AmpereOne Aurora, and Microsoft's Cobalt 200 packs 132 cores with its own per-core DVFS. Monaka's separation from that group rests on the cache-on-die stack and 12-channel DDR5 bandwidth rather than core count, and its 256-bit SVE2 width matches SiPearl's Rhea1 while exceeding the 128-bit SVE2 common to hyperscaler Arm cores.

NEDO subsidizes Monaka under a green data center program targeting 40% energy savings by 2030, yet the chip's 2nm and 5nm dies come from TSMC rather than a domestic fab. That gap between a made-in-Japan design and Taiwanese manufacturing sits awkwardly against the sovereignty that Fujitsu and RIKEN are seemingly keen to attach to the program.

Japan has committed more than 2 trillion yen to Rapidus for 2nm production in Hokkaido by 2027, and roughly 1.2 trillion yen to TSMC's Kumamoto fabs, and NEDO has separately backed a dedicated 1.4nm AI chip from Fujitsu and IBM Japan to be built entirely in Japan by Rapidus. Monaka predates that domestic capacity, however.

Monaka's successor is already assigned to a flagship machine. FugakuNEXT, the roughly $750 million RIKEN system announced in August last year with Fujitsu and Nvidia, will pair a 1.4nm-class Monaka-X that adds Arm SME2 with Nvidia GPUs linked over NVLink Fusion, the interconnect Nvidia opened to third-party CPUs in 2025. RIKEN targets more than 600 FP8 exaFLOPS within a 40MW envelope and roughly 100 times Fugaku's application performance, with operation around 2030. FugakuNEXT is Japan's first flagship supercomputer to place GPUs at its core, a departure from the CPU-only A64FX design of the original Fugaku.

Fujitsu has firmed up rather than changed the Monaka plan across three years of disclosures, with the core count, node split, and an anticipated launch date of 2027 remaining unchanged since 2023. Fujitsu didn't disclose pricing, and its DGEMM, STREAM, and INT8 figures remain estimates until independent testing at the 2027 launch

Full Fujitsu Monaka Hot Chips 2026 presentation

A Nevada court has found a Las Vegas businessman guilty of 11 counts of wire fraud, two counts of mail fraud, and two counts of money laundering for defrauding over $24 million from hundreds of investors. According to the U.S. Attorney’s Office, Brent Kovar presented Profit Connect to investors as a crypto mining operation that used an artificial intelligence supercomputer for its operations. He promised a fixed rate of return that paid 15% to 30% APR and also came with a 100% money-back guarantee. However, it turned out that the “profits” that the earlier investors made only came from the influx of newer investors, and that the company wasn’t making any money.

Kovar victimized 400 investors, telling them that the company had cryptocurrency reserves worth hundreds of millions of dollars. In reality, it had zero holdings, couldn’t afford to pay investors their interest earnings, and had no way to return their cash despite the offered guarantee. “He used investor money to operate Profit Connect, to buy gifts for employees, to buy a house for himself, and to repay investors as if those repayments came from mining cryptocurrency and verifying cryptocurrency transactions,” the Department of Justice said in its press release.

Profit Connect operated from 2017 to 2021, which is around the same time that Bitcoin made its first major rally, with the cryptocurrency hitting a peak of over $19,000 in December of that year. This, combined with the buzzwords of “AI” and “supercomputer,” made it seem to investors that they were putting money in a groundbreaking new technology that would change the way we do finance. Unfortunately, the venture turned out to be a scam and defrauded investors out of their money with nothing to show for. It’s unclear if the funds that the investors lost will ever be recovered, but Kovar is facing a possibly lengthy jail time of a maximum of 280 years for his crimes.

Another scam rooted in cryptocurrency investment from 2017 saw retail investors lose $2 billion. BitConnect offered a similar guaranteed return on investment for anyone who put up cash on its platform until 2018, but instead of using the deposited money for trading, it was just siphoned off to the organization’s private digital wallet addresses. Even before this, another Ponzi-scheme scammer made off with $6 billion from her victims in China from 2014 until 2017 and converted it into 61,000 Bitcoin. While she has already been arrested, the seized cryptocurrency is still in limbo, so it’s unclear if and when her victims will get their money back.

Microsoft has opened preorders for the Designed for Xbox 25th Anniversary Collection, a set of officially licensed peripherals in translucent "OG Green" marking 25 years since the original Xbox launched on November 15, 2001. Every item comes from a third-party partner rather than Microsoft, and the set leans toward PC and mobile, with three Razer desktop peripherals, two phone controllers, an 8BitDo charging dock, and a PowerA bag built to carry the Asus-made ROG Xbox Ally handhelds. Most units will ship in late October, with the Razer gear dated for October 20.

• Razer Basilisk V3 Pro 35K – XBOX 25 Anniversary Edition
• Razer BlackWidow V4 75% – XBOX 25 Anniversary Edition
• Razer Hammerhead V3 X HyperSpeed – XBOX 25 Anniversary Edition

Razer naturally contributes the priciest pieces, with the Basilisk V3 Pro 35K mouse at $179.99, the BlackWidow V4 75% keyboard at $209.99, and the Hammerhead V3 X HyperSpeed for Xbox earbuds at $119.99, each carrying a $20 premium over the standard model.

The Basilisk pairs Razer's Focus Pro 35K Optical Sensor Gen-2 with up to 140 hours of wireless battery, and the BlackWidow comes with hot-swappable Orange Tactile Switches Gen-3, the same internals as their standard versions. Backbone's Pro controller runs $159.99 in a blind-box format that hides which of three heritage colorways sits inside, GameSir's X5 Lite phone controller lists at $44.99, and 8BitDo's Ultimate Charging Dock lists at $39.99. The translucent green shells revive the look of the original Xbox and its Halo special editions, down to the four-color face-button palette that carries over to the separate anniversary console.

The keyboard carries a dedicated Xbox key that opens Windows Game Bar, the same shortcut the ROG Xbox Ally maps to its own Xbox button, and the collection's other anchors are a bag for that Windows 11 handheld and two clip-on controllers for phones. That composition aligns with the platform that Xbox has become, after Microsoft began rolling Xbox Mode out to Windows 11 desktops and laptops in April, extended the ROG Xbox Ally's full-screen interface across PCs, and started building its next-generation console on a custom AMD chip.

The Xbox Series X25 Limited Edition is the only anniversary product Microsoft makes itself, announced June 7 at the Xbox Games Showcase and due in November alongside a matching Wireless Controller X25 sold separately. It reuses the standard Series X internals with 1TB of storage in a translucent green shell, and Dealabs pricing cited by TechPowerUp puts it near $899, roughly $100 above the current 1TB Series X, though Microsoft hasn't yet confirmed a price.

Finding a good budget laptop under $500 has always been challenging, and rising component costs have pushed even the most basic models over that mark. Chuwi’s UniBook, for $449, looks tempting on paper, pairing Intel's latest entry-level Core processor with a thin metal chassis, a backlit keyboard, and more ports than many of the best laptops. But as with most bargain notebooks, the question is whether spending more is worthwhile, and our overall experience is that the extra you’d spend for the Dell XPS 13 or MacBook Neo gets you a markedly better laptop experience.

Design of the Chuwi UniBook

The UniBook looks more expensive than its $449 price tag suggests. Its aluminum alloy lid and bottom cover give it clean, modern look, while the slim profile helps it blend in with far more expensive ultraportables. It feels solid, with little evidence of flex.

Its compact 0.65-inch profile and 2.64-pound weight make it easy to slip into a bag, and its understated design would look at home in almost any environment. Both the MacBook Neo and the Dell XPS 13 are thinner, and the latter considerably lighter (2.2 pounds), but both are more expensive.

Port selection is the biggest surprise. While many thin-and-light laptops reduce connectivity, Chuwi went the opposite direction, with two USB-C 3.2 Gen 1 ports (both supporting power delivery and DisplayPort), three USB-A ports (two 3.2 Gen 1 and one 2.0), HDMI 1.4b, Gigabit Ethernet, an audio jack, and even a micoSD card slot. Compare this to the USB-C-only selection on the MacBook Neo (which also features a headphone jack) and XPS 13.

Internally, the UniBook’s Wi-Fi 6 and Bluetooth 5.2 standards aren’t the newest, but are perfectly adequate for this laptop’s intended use.

Chuwi UniBook Specifications

Productivity Performance on the Chuwi UniBook

We evaluated the Chuwi UniBook with an Intel Core 3 304 processor, Intel Graphics, 8GB of LPDDR5-6400 memory, and a 256GB PCIe 3.0 SSD.

Our comparison lineup consists of the Apple MacBook Neo and Dell XPS 13. Both laptops start at $699.99 before education discounts, and pack more powerful hardware. The UniBook’s Core 3 304 processor, featuring one performance core and a 4.3 GHz boost, is at a disadvantage next to the Dell’s Core 5 320 processor, which offers two performance cores and a 4.6 GHz boost. Meanwhile, the MacBook Neo uses a smartphone-grade but very capable A18 Pro chip.

The UniBook trailed the XPS 13 and MacBook Neo across the board. Some of this was expected – for instance, its Geekbench multi-core score of 5,889 points was well south of the XPS 13’s 7,952 and the MacBook Neo’s 8,920, a product of its weaker CPU. This followed into its last-place Handbrake showing.

However, its 294 MBps average speed in our 25GB file transfer test was particularly low even for a budget laptop, with less than half the throughput of the MacBook Neo and not even one quarter of the XPS 13’s. You could tell on paper this would happen, givenit's using the older PCIe 3.0 technology.

In daily use, the slow storage drive and single performance core didn’t hamper basic usage. The laptop booted without delay and webpages loaded quickly. With just 8GB of RAM (which can’t be upgraded), multitasking will be limited, but this laptop isn’t aimed at power users.

We normally run 10 loops of Cinebench 2024 or 2026 to stress-test productivity laptops, but both refused to run the UniBook – 2024 cited a GPU memory allocation issue and 2026 crashed at startup. The system’s 8GB of RAM may have been the culprit. As an alternative, we reran our Handbrake video transcoding test. During the test, the Core 3 304 operated at average frequencies of 3.46 GHz on its P-core and 3.1 GHz on its E-cores.

Display on the Chuwi UniBook

The UniBook’s 14-inch, 1920 x 1200 display is serviceable, but it’s also one of the clearest reminders that this is a budget laptop. Though its IPS technology provides wide viewing angles and it benefits from a practical anti-glare surface, dull colors and lack of contrast produce a washed-out picture. Brightness is adequate for indoor use only. In Captain America: Civil War, scenes that should have looked bright and punchy instead appeared subdued, with colors that felt muted rather than lively. For instance, the red on Captain America’s shield skewed more towards orange than red.

The UniBook’s panel covered just 62% of the sRGB color gamut and less than half of DCI-P3, putting it well behind the MacBook Neo and Dell XPS 13. Brightness was also modest at 298.8 nits, more than enough for typical indoor work but not ideal near bright windows or outdoors. For writing, browsing, and streaming casual video, the display is acceptable; for anything else, it is a compromise.

Keyboard and Touchpad on the Chuwi UniBook

The UniBook's keyboard is one of its highlights. Chuwi includes white backlighting, a welcome addition that's often omitted on budget laptops. (Notably, it’s missing from the MacBook Neo.) The keys are comfortably sized and spaced, making it easy to settle into a comfortable typing rhythm. I reached 120 words per minute with perfect accuracy on Monkeytype during my initial run – it felt predictable and responsive, though some keys exhibited occasional rattling that detracted from an otherwise positive typing experience.

The touchpad is compact but responsive and accurate. Its main drawback is the loud mechanical click mechanism, which is noisier than I expected and can become noticeable in quiet environments. Everyone within earshot will know you’re clicking. Otherwise, using the touchpad is comfortable and predictable.

Audio on the Chuwi UniBook

Audio performance is one of the UniBook’s weaker areas. While usable for voice calls, with sufficient volume and clarity, they struggle with entertainment. The sound is thin and lacks bass response, leaving music sounding flat and lacking impact. Listening to Phil Collins’ “Don’t Lose My Number”, for example, I heard almost no bass and the vocals lacked depth. The laptop doesn’t include an audio tuning app with equalizers.

Speaker positioning is also a problem. Because the speakers fire downward from the underside of the chassis near the palm rests, they only perform well when the laptop is on a hard surface. The sound is noticeably muffled if the laptop is in your lap or on a couch or bed.

Upgradeability of the Chuwi UniBook

The Chuwi UniBook offers reasonable upgradeability: the M.2 2280 SSD, M.2 2230 wireless card, and battery can all be changed out by removing the bottom panel. Removing the panel is straightforward, though two different sizes of Philips-head screws are used. The clips on the back edge can then be popped using a plastic pry tool, followed by the sides.

Battery Life on the Chuwi UniBook

Our battery testing consists of web browsing, running OpenGL tests, and streaming videos with the screen at 150 nits while connected to Wi-Fi. The UniBook’s time of 14 hours and 14 minutes is an excellent result for a budget laptop. It practically tied the XPS 13 (14:28) and nosed past the MacBook Neo (13:28).

Heat on the Chuwi UniBook

We normally measure peak laptop surface temperatures while running 10 loops of Cinebench, but that benchmark wouldn’t run on the UniBook. We substituted it with our Handbrake video transcoding test, which fully stressed the CPU for about 12 minutes. The UniBook’s surfaces didn’t stray far from room temperature – we recorded 80 degrees Fahrenheit on the touchpad, 88 F between the keyboard G and H keys, and 92 F on the bottom near the exhaust vents.

Internally, the Core 3 304 ran at an average temperature of 73 degrees Celsius. The exhaust fan was audible but restrained.

Webcam on the Chuwi UniBook

Chuwi’s webcam isn’t great – with just a 720p sensor, images have a soft focus and lack detail. I couldn’t read my wristwatch when I held it more than two feet away. On the bright side, it does offer a privacy shutter, which sometimes even pricier laptops leave out.

Software and Warranty on the Chuwi UniBook

Beyond the usual apps included with Windows 11 Home, Chuwi preloads no other software onto the UniBook.

The laptop is backed by a one-year warranty. Sending the laptop for warranty repairs could prove costly as it will need to be shipped to Hong Kong or Germany at the owners’ expense. (See Chuwi’s warranty policy.)

Chuwi UniBook Configurations

We reviewed the Chuwi UniBook featuring a Core 3 304 processor, Intel Graphics, 8GB of LPDDR5 memory, a 256GB SSD, and a 14-inch IPS 1080p display. It was listed at $449 on Chuwi’s online store at the time of this review, discounted from its $569 MSRP.A second configuration with an Intel Core 5 315, 12GB of RAM, 512GB of storage and a 1080p display that the company claims will cover 100% of the sRGB gamut was listed late in our testing process. As of this writing, the company told us this system is in production but doesn't have a price or release date.

Bottom Line

For buyers seeking a basic ultraportable, the Chuwi UniBook gets a few of the fundamentals right. Solid port selection and respectable battery life stand out in a price bracket where there are typically many compromises. Unfortunately, the compromises stack too quickly: performance that trails far behind machines like the Dell XPS 13 and MacBook Neo, a below-average display, weak speakers and webcam, and the ongoing risk of costly out‑of‑warranty repairs. So while its savings look good on paper, the many downsides and possibility of expensive service make it worthwhile to stretch your budget for a MacBook Neo or XPS 13, both of which are safer long-term investments.

OXMIQ Labs, a GPU IP company, revealed at Hot Chips 2026 that High Bandwidth Flash (HBF) cannot replace High Bandwidth Memory (HBM) across the vast majority of workloads. For some, HBF could emerge as a specialized memory tier for huge but relatively cold datasets. For others, HBF can do more harm than good.

When SanDisk unveiled its High-Bandwidth Flash (HBF) concept in early 2025, the technology pledged to equip AI accelerators with terabytes of relatively inexpensive memory and reduce the need for traditional High-Bandwidth Memory (HBM), a promise that raised a number of doubts from the very beginning.

The emerging HBF specification includes three performance grades. Grade 1 uses an 8-Hi 256GB NAND stack with an 8 GT/s UCIe interface and 384 GB/s bandwidth. Grade 2 uses a 512GB NAND stack with a 16 GT/s UCIe interface and supports 1.536 TB/s bandwidth. Grade 3 reaches 3.072 TB/s using 32 GT/s UCIe 2.0 while retaining the same 512 GB capacity.

Since HBF relies on 3D NAND, it supports read block sizes between 64 bytes and 4 kilobytes, 4KB writes, and 4KB page sizes. While HBF Grade 1 can barely compete against contemporary HBM, HBF Grade 3 can compete against HBM4E, though we have no idea when such memory will be available. However, the main feature of HBF is not necessarily performance per se, but 8 – 16 times more capacity than HBM at roughly the same cost.

Indeed, OXMIQ believes that HBF should be viewed as a high-capacity memory technology rather than inexpensive HBM. Memory economics depend not only on how many gigabytes an application needs to store, but also on how quickly those bytes must be delivered to the processor. As bandwidth demand rises, adding inexpensive but relatively slow HBF eventually becomes less economical than using HBM, according to estimates by OXMIQ.

Cheap memory =/= cheap tokens

OXMIQ demonstrated the trade-off by modeling a 72-GPU rack running the 1-trillion-parameter Kimi-K2 model at FP4. At cost and power parity, an HBM-only configuration provides 20.7 TB of memory and 1,584 TB/s of aggregate bandwidth. Replacing HBM with HBF increases rack capacity by 14 times to a whopping 294.9 TB, but reduces aggregate bandwidth to 922 TB/s. A hybrid configuration with HBM and HBF provides 89.3 TB and between 279 TB/s and 1,418 TB/s, depending on workload conditions. The difference between HBM and HBF bandwidth is the reason why HBF looks excellent when memory capacity limits the system. However, HBF eventually loses when bandwidth/throughput becomes the limiting factor.

In OXMIQ's model, an HBF-only configuration enables each GPU to hold its own Kimi-K2 instance and run 72 model instances per rack. Whereas an HBM-only configuration requires eight GPUs to hold each model instance (meaning compute performance gets wasted) and can therefore run only nine instances per rack. This makes HBF particularly attractive when memory capacity determines the number of GPUs required. However, as the number of simultaneous users and their token-generation rate increase, HBF's lower bandwidth becomes the bottleneck, while the HBM-based rack can make better use of its substantially higher memory bandwidth and ultimately deliver lower cost per token, according to OXMIQ's model.

As a result, HBF can dramatically reduce the number of GPUs needed simply to accommodate a very large model (i.e., enable one HBF-equipped GPU to do the capacity job of eight HBM-equipped GPUs). Nonetheless, if the objective is maximum inference throughput from a fully utilized rack, HBM may remain the better, more economical choice. At the end of the presentation, OXMIQ concludes: 'HBM for the rack, HBF for the box.'

Niche memory?

Although HBF does not benefit all AI workloads and may even harm the performance of many, there are applications that can benefit from a surplus of local memory.

Mixture-of-experts (MoE) models appear to be particularly suitable for HBF. OXMIQ's Kimi-K3 example has 1.56 TB of weights, of which 1.45 TB, or 93%, consists of MoE expert weights. Since only selected experts are activated for each token, this enormous pool is largely write-once and relatively infrequently read. OXMIQ proposes keeping such experts in HBF while placing the remaining, frequently accessed weights in HBM.

Additionally, more local capacity could also reduce communication between accelerators. Conventional expert parallelism distributes experts across GPUs and requires all-to-all communication at every layer. OXMIQ claims that inexpensive HBF capacity could allow considerably more experts to reside locally, reduce the number of expert-parallel shards, and reduce network traffic. In this case, HBF effectively trades memory capacity for interconnect bandwidth and power consumption.

Long-context inference is another potential use case. Sparse-attention models access only a small portion of their large KV cache during each decoding step, which allows the rest to remain in slower HBF memory. OXMIQ believes that HBF could store this large KV cache while the accelerator fetches only the data needed for each step from HBF to HBM.

The HBM-as-cache idea has a serious limitation. Intuitively, one would put popular experts in HBM and cold experts in HBF. Such a strategy works mainly at low batch sizes or when similar queries can be deliberately batched. As batch size rises and queries become more heterogeneous, however, expert popularity flattens, and the workload accesses a broader range of experts, according to OXMIQ. The working set can then outgrow the relatively small HBM cache, which results in more frequent expert transfers from HBF and reduces the performance benefit provided by HBM caching.

The hardest part

OXMIQ does not expect HBF to work simply as slower GPU memory. Instead, it proposes using HBF in place of host DRAM to store large amounts of less frequently accessed data, such as MoE experts and KV cache. Frequently used data would remain in HBM, while even colder data could still be kept in remote memory or SSDs. This certainly contradicts SanDisk's original vision for HBF: sitting next to AI accelerators. Furthermore, adding HBF support will be complicated on many levels.

The software side of HBF is particularly complicated. To achieve maximum bandwidth, HBF requires large transfers — 64 KB reads and 1 MB writes — and data is moved through DMA rather than the CPU/GPU cache hierarchy. When HBF and HBM are used together, software must also decide which data goes into each memory type and manage HBF's limited write endurance.

Meanwhile, current inference software is not ready for such a configuration. OXMIQ says vLLM would need dedicated HBF support to manage memory allocation and data placement, prefetch data before it is needed, and monitor flash endurance, which requires a major software overhaul. An effort like this has to be a joint effort between the HBF hardware vendors, AI accelerator vendors, and inference-framework developers.

At the lowest level, AMD, Nvidia, and other accelerator vendors would need to provide the hardware/driver/runtime mechanisms for efficiently moving data between HBF and HBM. Then vLLM developers, who work with vendors, would implement the higher-level memory allocator and policies that decide which experts/KV blocks live in HBM and which reside in HBF, when they should move, and how to hide HBF latency.

On the one hand, if AMD or Nvidia adopt HBF, they will provide its partners with everything needed to use it, and while this would take time before everything works as intended, this is a straightforward way to add HBF support to AI platforms. On the other hand, the biggest question is whether hardware vendors like AMD or Nvidia need HBF. As per OXMIQ, HBF's advantage is limited to select use cases, so it may not make sense for AMD or Nvidia to support it universally, especially keeping in mind that managing multi-tier memory hierarchy is hard.

SambaNova is perhaps the most obvious candidate to support HBF. Its SN40L already uses a three-tier hierarchy: SRAM => HBM => DDR, with up to 520MB of SRAM, 64GB HBM, and 1.5 TB of DDR. Conceptually, HBF could become another tier or replace some of that DDR capacity. Then again, this is merely speculation.

HBF remains a nascent technology

While we still have a lot to learn about how HBF works, OXMIQ's model suggests that HBF has a much weaker general-purpose value proposition than the original claim made in early 2025 suggested. It is not useless: it is a specialized solution whose strongest applications depend on particular workload characteristics.

The fundamental problem is that HBF solves memory capacity, while modern AI accelerators are frequently constrained by memory bandwidth. OXMIQ's simulation makes this rather obvious: HBF provides about 14X more memory capacity but only 0.6X the aggregate bandwidth of HBM. Once the workload becomes sufficiently bandwidth-intensive, the enormous capacity stops offsetting the bandwidth deficit.

While the hybrid HBM+HBF solution makes sense for some use cases, it is not a magic fix. When HBM is used as an expert cache, heterogeneous requests at larger batch sizes flatten expert popularity, cause the workload to touch more experts, and reduce cache efficiency dramatically.

For now, HBF has three particularly compelling use cases: reduce the number of GPUs required simply to fit huge models, store massive but infrequently accessed MoE expert pools, and keep large KV caches for sparse long-context inference. For MoE models, its large local capacity could also reduce expert parallelism and expensive all-to-all communication between GPUs. In all three cases, HBF makes sense because capacity requirements are enormous while bandwidth demand remains relatively low.

The developer and publisher of the much-awaited game finally released a statement on the leaks of the game that dropped last week. Rockstar Games said on its X account that the gameplay leaks aren’t how it intended for its fans to see the game and also apologized for the massive delay in the release of the title. However, nothing in the post says anything about the alleged leaker’s protest on the pre-selling of digital copies of GTA VI and their other demands.

“It would be an understatement to say that having videos of Grand Theft Auto VI gameplay leak in this way has been heartbreaking for our team, and this is obviously not how we intended for you to see the game after all this time. We are very sorry that everything has taken as long as it has — from getting the game finished (nearly there!) to sharing more details and official gameplay, and providing the community with everything you want to know,” Rockstar said in its statement. It also added, “While it is unfortunate that the intended game experience may now be impacted by some spoilers, we hope that everyone will wait a bit longer to experience the game for themselves on November 19.” Although we still have about three months before the game finally becomes available on Xbox X|S and the PlayStation 5, an extended look at the game is also dropping tomorrow on Netflix.

Cyberleek started leaking gameplay clips, along with a detailed map of Leonidas, last week. While it was initially thought that the leaked clips were already over a year old, another set of leaks revealed that the hacker actually has a complete working build of the game. They even shot out “LEEK” on a wall to prove that they were playing the game and not just downloading or faking clips. Rockstar has been quiet while the leaks were whipping up a storm on the internet, but its parent company, Take-Two Interactive, issued a subpoena to Microsoft to get the Windows device IDs of all the members of three Discord servers.

Gamers just need to be patient a little bit more, as the release is less than 12 weeks away, at least for consoles, as a PC version hasn’t been announced yet. Nevertheless, there are those who are taking advantage of the popularity of the game and have been releasing malware disguised as leaks of GTA VI. Downloading pirated games online has always been problematic, but downloading an unreleased title off the internet is an absolute recipe for disaster. It’s understandable that a few people are so excited about the title that they cannot wait for the official release to get their hands on it, but three months will pass by quickly, especially for those who have been anticipating the next GTA installment for more than a decade now. After all, good things come to those who wait.

Memory and data storage manufacturer Micron announced its exit from the consumer market earlier this year and pledged to honor warranties for existing products. However, according to a recent RMA case on Reddit, the company seems to be struggling to stick to that promise. Instead of replacing a faulty portable SSD, the company offered the customer a refund that was significantly lower than the product’s current retail price.

Explaining their frustrating RMA experience, u/CarefulMeasurement99 said that their Crucial X9 4TB portable SSD stopped working, after which they contacted support, followed the troubleshooting process, and had their RMA approved. Unfortunately, they were later informed that the company did not have any units available for the particular product because the replacement inventory was exhausted. Therefore, instead of providing a 1:1 replacement SSD, the company would issue a refund of $199.99, the same as the original invoice price from last year.

Due to the ongoing NAND and DRAM crisis, almost every memory and storage product has significantly gone up in price. The Crucial X9 4TB is currently priced at over $500 on Amazon, which basically left the customer facing a loss of nearly $300. The customer explicitly refused to accept the offer and told Micron support that they did not want a refund and requested a 1:1 replacement under warranty. They also offered to accept an alternative 4TB SSD model or wait indefinitely until the RMA inventory was restocked.

After a long ordeal, pushing back eventually paid off for the customer. They sent Micron a firm final email rejecting the refund and demanding a 4TB equivalent replacement or alternative. The customer also mentioned that the case was gaining traction on Reddit and pointed out potential action under the FTC and Magnuson-Moss Warranty Act. Within a few hours, the case was escalated to a different representative, who informed them that a “recent inventory update” had revealed limited replacement stock and approved a direct 1:1 replacement.

While the case raises questions about Micron’s initial claim of no replacement units being available, there is no way to independently verify that. That said, this does not appear to be an isolated case. Earlier this month, we reported a similar RMA horror story in which Micron offered a customer a refund instead of replacing their product due to a lack of inventory. Only after further communication did Micron provide an acceptable solution.

d-Matrix presented Raptor, which it calls the first 3D DRAM accelerator for generative inference, at Hot Chips 2026 this week, showing a TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed DRAM die that delivers 100 TB/s of bandwidth from 32GB per card.

Co-founder and CTO Sudeep Bhoja put the vertical interface's energy cost at 0.37 pJ/bit against roughly 2.4 pJ/bit for moving data into an HBM4 base die, calling it "a measured number" from working silicon, and the accompanying ISCA 2026 paper, written with the University of British Columbia, projects around 4.7 times higher throughput per card than HBM-based designs. Bhoja, however, didn't disclose who manufactures the DRAM die.

CEO Sid Sheth told CNBC in June that Raptor is slated to launch in 2027, but at Hot Chips the company gave no firm date or information on volume and pricing, and every performance figure shown, including 988 tokens per second per user on the 2.8-trillion-parameter Kimi K3 model at 1M-token context, is a d-Matrix projection built on early silicon.

The custom DRAM die

Raptor inverts the usual 3D stacking arrangement by putting the logic die on top and the DRAM underneath, so a cold plate sits directly on the compute silicon and the DRAM die doubles as the interposer, carrying PCIe and die-to-die signals down through its TSVs. "For the same amount of power, you can drive the bandwidth up," Bhoja said during the session, "and so we were able to drive the bandwidth up here to 100 terabytes per second."

The one-high stack achieves a power density of roughly 0.5W per square millimeter, which liquid cooling can handle, but the DRAM is designed for a junction temperature of 105°C, where retention collapses from a standard 32ms to 4ms, and the memory must refresh eight times more often. d-Matrix absorbed that penalty by shrinking each microbank to 1,366 rows and about 5.33MB, so a full refresh sweep costs only 1.37% of overall bandwidth.

The die carries 840 banks per chiplet, of which 72 (around 9%) are spares wired into a two-level mux chain the company calls bank chaining, letting any two failed banks anywhere on the die be switched out while channels stay symmetric. A [132,128] Reed-Solomon code on the logic die corrects two symbol errors per 128 bytes, with a CRC behind it. The interface has no PHY, no burst structure, and no sideband pins, so conventional data-bus inversion was impossible; d-Matrix instead compares each 128-byte flit to the previous one and stores a 1-bit inversion tag alongside the ECC metadata, recovering roughly 20% of the I/O power DBI would have saved. At full tilt, the vertical interface still burns 296W of the 422W per-package budget the ISCA paper discloses.

The bank geometry, spare-bank mux tree, refresh behavior, and interleaved ECC columns were all co-designed with the compute die. The 0.37 pJ/bit figure exists only because of that pairing, and no memory maker has anything like this die in its catalog.

Who's supplying it?

d-Matrix has named TSMC for the N4P logic die and Alchip as its ASIC design and 2.5D/3D packaging partner, but neither company operates a DRAM fab, and across the Hot Chips talk, the ISCA paper, and every public announcement since the Pavehawk 3DIMC test silicon came online last September, the firm has never identified who fabricates its custom DRAM. Only three companies make leading-edge DRAM at volume, and all three are allocating capacity to HBM4 lines that are effectively sold out through 2026.

J.P. Morgan estimates DRAM prices will have risen more than 400% between the start of 2024 and the end of 2026. In addition, analysts have recorded contract price increases of 90% to 95% in Q1 2026 alone, and SK hynix CEO Kwak Noh-jung told Reuters in July that "customer demand will remain higher than our supply capacity even beyond 2030."

Nvidia, the memory makers' largest and most leveraged customer, is reportedly testing Rubin Ultra configurations with as little as 192GB because it may not be able to source enough HBM4E. A startup with roughly $450 million raised, asking a memory maker to run a bespoke die with non-standard bank geometry on capacity that could otherwise print HBM, is negotiating from a far weaker position than that, and until the supplier is named, Raptor's 2027 volume plan rests entirely on an unknown, undisclosed dependency.

The die's 11.4 MB/mm² density is roughly half of HBM4's 21.9 to 26.3 MB/mm², Bhoja acknowledged during the Q&A: "A lot of the drop for us was also because we used a not-so-advanced DRAM. And so if we used a more mainline DRAM, just like the HBM4 guys are doing, we would be able to push that up almost all the way to the HBM4 numbers." The density penalty therefore tracks back to whatever foundry arrangement d-Matrix currently has.

32GB per card

Raptor's 32GB per card stands against 192GB to 288GB for HBM4-equipped accelerators, so d-Matrix sizes deployments at rack scale instead: 72 cards carry 2.3TB, enough to hold Kimi K3's weights at 4-bit precision with headroom for around 54 concurrent users at 1M context, by its own calculations. "Even with 32 gigabytes of memory capacity, we are able to solve SOTA models in a scale-up network, so no bits are wasted," Bhoja said.

KV cache growth works against that arithmetic over time, and co-presenter Aayush Ankit, who led Raptor's SoC architecture at d-Matrix before joining Meta's MTIA team, explained the failure mode while dismissing SRAM alternatives: "We are making this unit of compute blazingly fast. Communication becomes a bottleneck soon enough." Once models and context no longer fit a single rack, inference spills into the inter-card synchronization overhead that the vertical bandwidth was meant to eliminate, which the ISCA paper concedes.

Cerebras claimed 969 tokens per second on Llama 3.1 405B in November 2024, with third-party firm Artificial Analysis verifying the figure on live hardware, and that remains the closest published reference point for Raptor's numbers. d-Matrix's 988 tokens per second per user on a model seven times larger would be a step change if it holds water, but no third party has measured Raptor, and the comparison points in the ISCA paper are simulations anchored to early silicon characterization.

Asked by an Nvidia employee about multi-layer stacking plans, Bhoja said: "Our roadmap is still a work in progress, and we have a hard enough time trying to get one-high to work and work around all of the thermal issues of that." Samsung brought its own version of the idea to Hot Chips with zHBM, a concept that stacks HBM directly on the processor and carries a claimed 70% power-efficiency gain over an HBM4E setup, with no production timeline before HBM5. The problem for d-Matrix is that Samsung runs its own DRAM fabs; d-Matrix doesn't. Whether it can get wafers at volume remains to be seen.

Full d-Matrix Hot Chips 2026 presentation

While the unprecedented pace of development of artificial intelligence and its impact on human society is being discussed widely among academic circles, Bill Gates says that nations and governments are not doing enough to prepare their citizens for the upcoming upheaval this technology will deliver. The billionaire said in the GatesNotes blog that the world needs a plan to face the changes that AI will bring, proposing measures including reserving jobs for humans and taxing AI tokens. While other experts and academics equate it with other technologies like computers and the internet, Gates argues that people had decades to get used to the latter and incorporate it in processes and workflows, while the former is already widely available today.

Because of this, he pointed out that people today are facing risks brought about by AI, such as job loss, the use of the tool by bad actors, and the replacement of genuine human relationships, especially among children. Gates said that he will focus on other issues in later posts but dived into the issues of job security and income taxes in his commentary. He said that entry-level jobs have fallen significantly, making it harder for fresh graduates to gain experience and increase their skills. The former Microsoft chairperson acknowledged that society needs time to make adjustments but also pointed out that it might be too late for some unless there is some kind of intervention. “The people who need the most time are the ones who have the least — the accounting worker who’s replaced by a bot or the $20-an-hour worker who loses their job to a $10-an-hour robot,” Gates wrote.

Gates said that as AI and robots improve and replace humans in different tasks, some jobs should be marked as “Human Reserved.” He likened the term to nature reserves, places that people could have developed but didn’t “because the loss would be too great.” These jobs don’t have to be static positions that will stay the same for the rest of time but could be a slow evolution where AI tools are slowly introduced across years and decades. This is particularly important for industries whose practitioners would be displaced by AI and wouldn’t be able to pivot to other skills, citing a 55-year-old who has worked in construction their whole life and is not able to transition to the health industry as an example. He also mentioned that some jobs will never be fully taken over by AI as they require some form of human touch, like education and healthcare.

The billionaire philanthropist also noted that the reduction of human employees would also equate to a reduction in the individual income taxes that governments collect. The U.S. Treasury said that more than half of the federal revenue came from individual income taxes in 2025 and 2026, meaning falling employment would also make a huge impact on the government’s coffers. The current tax setup encourages executives to replace people with robots, which are often tax-deductible expenses. He instead suggested that the government should tax AI tokens and robots — aside from helping the federal balance sheet, it will also motivate businesses to prioritize hiring and keeping people instead of buying machines.

Artificial intelligence is indeed a technological marvel, but it also comes with several risks that must be addressed head-on. Bill Gates says that the debate around AI, its use, and its impact on us should be discussed widely among workers, students, community leaders, religious leaders, parents, educators, and more, not just the few who control it.

Montech is a Taiwanese PC hardware brand with deeper roots than its relatively recent public profile suggests. Founded in 2016 by engineers with over three decades of experience in Taiwan's PC industry, the company entered the Western market in 2019 with a value-focused positioning built around PC cases. Those cases sold well, and the catalog expanded quickly into power supplies, air coolers, liquid coolers, fans, and mechanical keyboards. The ambition from the beginning was to become a full-spectrum component brand rather than a niche case maker, and the PSU division is now central to that effort.

The earlier Century series established Montech's credentials in the mainstream segment, but the Titan PLA line represents a substantially higher level of commitment. Rather than sourcing from a mid-tier OEM and competing on price alone, Montech contracted Seasonic. That is not a trivial decision. Seasonic manufactures some of the best power supplies today and is widely regarded as perhaps the most consistently reliable OEM in the consumer PSU industry, responsible for technically accomplished designs under both its own brand and as the manufacturer behind multiple third-party lines. Montech prints the Seasonic name directly on the Titan PLA packaging, which communicates more about the product's engineering pedigree than any marketing copy could.

Specifications and Design

In the Box

The Titan PLA 750W ships in a large, sturdy cardboard box with a restrained and effective visual theme - a black and polished metal aesthetic with a photograph of the unit printed on the front. The Seasonic OEM designation is printed openly on the packaging. For anyone with even a passing familiarity with the PSU market, that detail is more persuasive than any graphic design choice.

Inside the box, the PSU sits in a synthetic pouch surrounded by foam inserts. The accessory bundle is unexpectedly generous. We found mounting screws, an AC power cable, basic cable ties, five quality reusable cable straps, a set of cable combs, and an ATX jump-start adapter for testing. Few companies at any price point include all of that.

The cables are immediately distinctive. Bright white wiring runs throughout, paired with black connectors across the board. The wires feature an embossed braiding across their full length, giving them a slightly textured, uniform appearance that holds up well in windowed builds. The single 12V-2x6 connector is rated at 600W, which is the full ATX 3.1 specification requirement and not a given on a 750W unit. There are two 6+2 pin PCI Express connectors, which covers the most common configurations at this wattage tier but leaves no margin for extremes. It is a practical limitation worth noting before purchase.

External Appearance

At 160mm length, the Titan PLA 750W is marginally longer than the ATX design guide considers standard. Any quality modern tower case will accommodate it without difficulty, but it is worth verifying clearance in compact enclosures before ordering.

The chassis finish is satin white, excellently applied. A diagonally wired, chromed fan finger guard covers the intake, and chrome decorative elements extend to both side panels. The result is refined without being ostentatious. The top panel is home to a black electrical specification and certification sticker.

The front panel houses the standard power switch, AC receptacle, a small decorative plate, and a toggle switch for the hybrid fan mode. The rear modular connector bank is organized logically, with a subtle black legend identifying each port type. The ports are keyed anyhow, and inserting cables into the wrong connector is practically impossible.

Internal Design

Cooling relies on a Hong Hua HA13525H12F-Z 135mm fan with a fluid dynamic bearing (FDB) engine, rated to a maximum of 2300 RPM. That ceiling is high for a 750W unit and this unit should not need it, although the headroom is appreciated. FDB fans are a reasonable choice at a premium tier, balancing acoustic performance with long-term bearing reliability.

As noted, well, everywhere around the packaging and promotional material of this unit, the OEM is Seasonic. Founded in Taiwan in 1975, Seasonic has a vast reputation in the PC market. The company serves simultaneously as a retail brand and as the manufacturer behind several third-party labels, with past collaborators including Antec, NZXT, and XFX. The Vertex platform, launched in late 2022 as Seasonic's response to the ATX 3.0 and PCIe 5.0 standards, underpins the entire Titan PLA line. The Montech collaboration reportedly required 18 months of development before reaching production, and the unit was first revealed publicly at Computex 2024.

The filtering stage comprises four Y capacitors, two X capacitors, and two filtering inductors, which is a complete and adequate configuration. Two rectifying bridges sit on a dedicated heatsink immediately after the filtration stage.

The APFC stage uses two Infineon 6R190P6 MOSFETs and a CREE diode mounted on the unit's largest heatsink, with passive components consisting of a large encased inductor and two Nippon Chemi-Con 330 μF bulk capacitors. The primary inversion stage is where this design distinguishes itself most clearly from the competition, featuring four Infineon 6R230P6 MOSFETs arranged in a full-bridge LLC converter topology. Full-bridge LLC is a configuration far more commonly reserved for units above 1000W.

On the secondary side, four Nexperia PSMN1R4-40YLD MOSFETs generate the 12V rail via synchronous rectification. The tall secondary-side heatsinks are not in direct thermal contact with the MOSFETs, an unusual arrangement for top-mounted chips, though the thermal results indicate it presents no operational limitation. The 3.3V and 5V rails are derived from DC-to-DC converters on a vertical daughterboard, standard practice in any design of this caliber.

Secondary-side capacitors are almost entirely Nippon Chemi-Con, with a small number of Rubycon electrolytics. Both are Japanese manufacturers with long, consistent track records in the PC enthusiast community for durability and electrical stability. The component selection throughout reflects engineering priorities, not cost reduction.

Cold Test Results (25°C Ambient)

Cold Test Results (25°C Ambient)

For the testing of PSUs, we are using high-precision electronic loads with a maximum power draw of 2700 Watts, a Rigol DS5042M 40 MHz oscilloscope, an Extech 380803 power analyzer, two high-precision UNI-T UT-325 digital thermometers, an Extech HD600 SPL meter, a self-designed hotbox, and various other bits and parts.

At 115 VAC, the Titan PLA 750W averaged 91.1% efficiency across the nominal load range. At 230 VAC, that figure climbed to 92.6%. Both results comfortably clear the Platinum certification thresholds under both Cybenetics and CLEAResult's 80Plus methodology. Efficiency stability is a particular strength here, as the curve holds level across most of the range, peaks near 50% load, and performs well even at low loads.

Fan behavior under cold conditions is excellent. The hybrid mode keeps the fan stationary at low loads and engages the fan once load surpasses roughly 30%, which is earlier than several competing designs allow. Audibility, however, remains minimal across most of the load range. There is a brief speed step approaching maximum output, but the fan does not approach its 2300 RPM ceiling under cold conditions. Internal temperatures are well controlled throughout.

Hot Test Results (~45°C Ambient)

Hot Test Results (~45°C Ambient)

Under elevated ambient temperatures, average efficiency at 115 VAC falls to 89.8%, and 91.3% at 230 VAC. The degradation of more than 1% on average is measurable and slightly above the typical expectation, but no signs of thermal instability or output stress appeared at any load point during sustained testing. The platform handles thermal stress composedly.

Fan behavior expectedly shifts under heat but not as intensely as we are used to. Engagement drops to around 20% load, and the speed ramp is steeper than under cold conditions. The more noteworthy finding is that the fan barely exceeds the speeds it reached during cold testing, even at 100% output. That speaks directly to how well the thermal management architecture performs paired with a relatively stable efficiency design. Internal operating temperatures remain genuinely low across the entire load range.

PSU Quality and Bottom Line

Power Supply Quality

The electrical results are exceptional, with the unit delivering spectacular power quality. Voltage regulation sits at 0.5% on the 12V rail and 0.2% on both the 5V and 3.3V rails. Those figures are outstanding by any standard. Ripple suppression is equally clean, just 26 mV maximum on the 12V rail and 20 mV on both the 5V and 3.3V rails. These are numbers we infrequently get from top-tier products.

During our thorough assessment, we evaluate the essential protection features of every power supply unit we review, including Over Current Protection (OCP), Over Voltage Protection (OVP), Over Power Protection (OPP), and Short Circuit Protection (SCP).

All protection mechanisms, including OCP, OVP, OPP, and SCP, were verified and triggered correctly during testing. The OCP thresholds, however, are set very high: 158% on the 3.3V rail, 160% on the 5V rail, and 146% on the 12V rail. OPP triggered at 146% of rated output during hot testing. The unit sustained power delivery well beyond its 750W nameplate rating for significant time periods before shutting down. Rather than this being an issue and considering the platform, parts, and their ratings, it would seem that this unit deliberately carries substantially more headroom than the nameplate implies. The protection circuitry functions correctly - the thresholds simply reflect what this hardware is actually capable of.

Bottom Line

At the $160 MSRP, the Titan PLA 750W sits at the upper boundary of what the 750W segment will typically support. The competition at that price is real. At the $130 sale price it regularly appears at, the value calculation changes considerably. The electrical performance, component selection, and Seasonic engineering together produce a unit that easily competes technically against products priced $30 to $50 higher from comparable brands.

Taken as a whole, the performance profile of the Titan PLA 750W is difficult to fault. Voltage regulation figures comfortably outclass the majority of the competition at any wattage. Ripple suppression stays at or below 26 mV across all three rails under any load condition tested, including sustained full-load runs under elevated ambient temperatures. The efficiency figures meet the Platinum certification threshold with margin to spare and remain stable across the entire load range rather than peaking sharply at optimal points. Hot testing introduces a degradation which is measurable but entirely manageable, and critically, the unit shows no signs of thermal stress or output instability at any point during sustained high-load operation. The fan management is competent and audibility remains low for the overwhelming majority of real-world operating conditions. These are benchmark-level results and reflect the underlying platform more than any cosmetic or marketing consideration.

The advanced platform design and exceptional quality silicon used by Montech and Seasonic are what stands out about this series. The nearly exclusive use of Nippon Chemi-Con and Rubycon capacitors throughout the secondary stage reinforces that this product was not engineered down to a cost target.

Two 6+2 pin PCI Express connectors cover the most common use cases at this wattage, but the count could become a constraint for some builders. It is the most concrete criticism that can be leveled at an otherwise well-considered overall design. The 12V-2x6 connector is rated at 600W, the white cable aesthetic is genuinely distinctive and well executed, and the chassis finish is among the cleanest examples seen at this price point. The chrome accents could register as excessive depending on personal preference, but the underlying build quality is not in question.

The 10-year warranty is among the longest available in the consumer PSU market and reflects the confidence a Seasonic top-tier platform warrants. For a unit that will typically remain in service for about five years before the next significant system build, that commitment is not a marketing footnote but a meaningful feature that factors directly into total cost of ownership. Warranty length in the PSU segment correlates more reliably with platform quality than almost any other single specification, and a decade of coverage communicates something concrete about how Seasonic and Montech expect this hardware to age. The Titan PLA 750W is a product built by people who knew exactly which OEM to call, and the results confirm that the decision was correct.

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The Dr. Semiconductor YouTube channel only has a few videos, but the man is quickly making a name for himself. He's built a semiconductor cleanroom in his backyard and made his own RAM cells there. Matthew Hartensveld (his real name) needs to figure out a way to package (cut and write) the RAM cells, so he figure he might as well use the opportunity to make some free-range, homemade LEDs while he was at it. This latest adventure is part of his open-source Semiconductor.DIY project.

The entire video is fascinating and information-dense, so we suggest you watch it to get the complete picture. Hartensveld started off with gallium nitride atop a sapphire wafer, that he proceeded to break into shards and clean with a solution including deionized water, acetone, and isopropyl. The primary goal was to etch the top layer of the material in order to define pattern contacts. Chlorine gas would be the obvious answer as that's what's used industrially, but it'd be more than a little hazardous in this setting.

The scientist turned his attention to a household item that makes every nerd happy: lasers. He ordered a powerful one from eBay, and moved it into his bathroom so his dog wouldn't look into it. Hartensveld quickly came across the problem that there was basically no information online about using said laser, and after a few attempts he managed to etch some scribbles on the wafer, and then actual patterns. After this, he test-drove the "LED" shard by smooshing some indium on it and using a 9 V battery, and lo and behold, there was blue light.

Doing so left a deposit of metallic gallium atop the pattern, so he came up with a solution to clean that up to leave the etched parts clearly exposed. Using a vacuum chamber with a two-stage pump that sucked out 99.999999% of the air out, he deposited a nickel/silver layer for the positive contact, then a titanium/silver for the N-contact and top metal, using argon plasma as the top gas. Even still, he later regretted not letting the chamber run for a while longer to draw out yet more air, to reduce residual gas.

At this point, Hartensveld had a fully working blue LED, though still in a wafer. That's right, blue, the color of LED that was a mystery for decades until a dedicated Japanese engineer figured it out. At any rate, the time came to package these LEDs, meaning cut them out of the wafer, and add physical connections. A table saw with very thin blades didn't really worked out, so in pure scientist fashion, Hartensveld turned once again to the laser, focusing it at a specific point to melt away the sapphire substrate. After an adjustment to make this a multi-passs process, he finally had a full cut.

The madlad still needed to add wire connectors, and after evaluating a few options, settled on indium bumps, the same method and material used in digital cameras. Last but not least, since he already had a blue LED on hand, he added a layer of cerium-doped yttrium aluminum garnet (just bought off Alibaba) to add a yellow filter to end up with an ugly but functional white LED.

When Arm introduced its AGI data center CPU, which it will ship starting in late 2026, the company revealed key specifications but omitted many technical details. It said nothing about the processor's performance at the time. This week at Hot Chips 2026, Arm filled many gaps about the architecture and design decisions of its AGI CPU, disclosed that the processor works as planned, published planned configurations, and said it is on track for commercial shipments in the coming months.

Many cores

Arm's AGI is a dual-chiplet data center processor that packs 64, 128, or 136 Neoverse V3 cores (10-wide frontend and decode, 10-wide dispatch, 8-wide retire, 384+ entry OoO window) running at 2.80 GHz – 3.70 GHz. The processor is equipped with two 128-bit vector engines and 2MB of L2 cache per core, as well as up to 272 MB of system-level cache. Each CSS V3 chiplet consists of 50 billion transistors, contains 70 V3 cores, a six-channel memory subsystem supporting up to 3 TB of DDR5-8800 memory (6 TB per socket), and connects to its sibling using a 16 ×16 UCIe macros running at 32 GT/s with an aggregated bandwidth of 2 TB/s. On the I/O side of things, Arm's AGI has 96 PCIe 6.0 lanes utilizing the CXL 3.0 protocol on top for memory expansion, four PCIe 4.0 lanes, and I3C, I2C, and SPI interfaces. The CPU has a thermal design power of 300W.

At a high level, Arm's AGI does not look too different from CPUs from AMD, Intel, and Nvidia: it has many cores, plenty of cache, a high-performance memory subsystem, and dozens of PCIe lanes with CXL. However, several design choices from Arm buck some usual trends from other CPU makers.

Unorthodox design choices

The first thing that catches the eye is that Arm chose two largely self-contained SoC chiplets made on TSMC's N3P technology, which places both compute and I/O on the same die, and decided not to go with the usual heterogeneous multi-chiplet designs used by AMD, Intel, and now Nvidia, all of whom separate compute and I/O chiplets.

While AMD, Intel, and Nvidia use their heterogeneous multi-chiplet approach to pack more compute capability and deliver more performance, it looks like Arm's decision is fundamental to its combination of enormous memory bandwidth (844.8 GB/s when used with DDR5-8800, though such memory still has to make it to the market) and <100-ns DRAM latency. As AGI's memory traffic does not have to travel to another chiplet with a memory controller, it can reduce latency and potentially achieve higher performance in latency-sensitive workloads, including some single-threaded and agentic AI workloads.

Each chiplet uses an 8 × 9 CMN-S3 mesh (a low-latency interconnect) to connect CPU cores, memory, I/O, and accelerators. It incorporates a 128 MB distributed system-level cache, snoop filtering, and hierarchical caching through HN-S, or Super Home Node, a piece of logic that acts as a distribution center for handling traffic and data through the chip to speed up communication.

The important point is that CMN-S3 is not just an internal CPU mesh, as Arm designed the coherent system to extend outside of the die to extend coherency beyond the die and the socket. The approach is conceptually closer to Intel's distributed Xeon 2D mesh (though Xeon is moving on to a 3D mesh with Diamond Rapids) than AMD's EPYC architecture, where compute chiplets connect to a central I/O die that hosts the memory controllers and Infinity Fabric infrastructure. This essentially proves that Arm appears to have optimized AGI's chiplets for memory locality, bandwidth, and latency, but not exactly for compute performance density, modularity, yield, and ease of manufacturing like AMD.

Arm revealed at Hot Chips that each chiplet physically contains 70 Neoverse V3 cores, but the complete product exposes up to 136 cores, which means that four cores are redundant and are incorporated to increase yield.

Capable memory subsystem

Arm positions its AGI CPU primarily for AI servers and agentic AI systems, in particular. Since memory performance plays a big role in many agentic AI workloads, Arm implemented a capable coherent NUMA memory subsystem. The NUMA subsystem features two six-channel DDR5 subsystems located in each chiplet, which can potentially provide a total of up to 845 GB/s of bandwidth. If a core needs memory attached to the other chiplet, the request can cross the coherent die-to-die connection, though at a cost of latency. Arm's goal is to provide as much bandwidth per core as possible, which is why AGI supports everything up to DDR5-8800.

The DDR5 controllers within Arm's AGI CPU are quite sophisticated too. They support numerous features to maximize performance in real-world workloads, including fully out-of-order command scheduling, bank-parallelism-optimized address mapping, and programmable page policies to improve DRAM utilization and extract more effective bandwidth from the memory subsystem, while anti-starvation mechanisms help maintain predictable service under heavy load.

In addition, Arm also implements memory-bandwidth limiting and monitoring through Memory Partitioning and Monitoring (MPAM) along with QoS-based traffic prioritization and congestion feedback to manage contention when multiple cores and I/O devices compete for DRAM bandwidth. The memory subsystem also features extensive RAS capabilities, including single-DRAM-device failure correction with Chipkill-class protection, memory scrubbing, row-hammer mitigation, repair support, error injection, and RAS error logging.

Capable memory subsystem

Now that Arm has shared so many details about its AGI CPU, the lingering question is the performance of the processor itself. Arm still has not published conventional benchmark results such as SPEC CPU2017, SPECrate, integer/floating-point throughput, or direct socket-to-socket comparisons against current AMD EPYC or Intel Xeon processors in real-world server workloads.

The main performance claim that Arm has made is '2X performance per rack versus the latest x86 platforms' based on estimates, which is not even remotely a detailed performance claim. Perhaps, following Nvidia's lead, Arm prefers to compare the per-rack performance of its CPUs, as they are made to work in racks. However, this is clearly an unconventional way to evaluate processors.

Buying a pre-built gaming PC remains one of the surest ways to skirt exorbitant RAM and SSD pricing, as AI drives up the cost of DIY components. Right now at Best Buy, you can get an HP Omen 35L Gaming Desktop with an RTX 5080, a graphics card selling for $1,500 right now, 32GB of DDR5 RAM, 1TB SSD, and an Intel Core i7 CPU for just $2,349, a $750 saving.

Get this deal at Best Buy

Thanks to a slightly older but no less capable processor, this is a bit of a sleeper deal that is really good value in the current market. As noted, the GPU alone now costs around $1,500 to buy. 32GB of DDR5 RAM is $400, so you've almost spent $1,900 on just two components, before you factor in the SSD, CPU, motherboard, cooler, PSU, and case.

As you can see, this PC doesn't contain a benchmark-busting X3D CPU from AMD; however, the Core i7-14700F is a capable 20-core Raptor Lake Refresh. It features eight performance cores and 12 efficiency cores, with boost speeds of up to 5.4GHz. Despite being a couple of years old, it still averages 150 frames per second in our 16-game testing suite at 1080p, and, thanks to its price, it offers the best value (FPS/$) of any CPU we've tested.

The RTX 5080 is the headline component here, as the second-best graphics card on the market, only behind the RTX 5090, which will cost you around $4,800 these days.

With 10,752 CUDA cores and 16GB of VRAM, this will chew through any title, even providing a solid base for 4K gaming, not to mention access to Nvidia's DLSS technology for even more frames.

The RTX 5080 makes the raw power of this gaming PC extremely appealing, and more than makes up for a slightly older CPU, a compromise worth taking in the current economy.

Other specs include a 1TB PCIe 4.0 SSD, 32GB of DDR5 6000 RAM, Wi-Fi 6E, Bluetooth, an 850W PSU, and liquid cooling.

If you fancy a cheeky little PC upgrade that doesn't involve raiding your savings for memory or storage, then how about sprucing up your peripherals? Your mouse and keyboard get the most use and abuse on the daily, and although a good clean and maintenance can extend their life by years, sometimes they just get a little too grotty and need to be swapped out. Keyboards, however, can command a good chunk of cash these days too, so finding a great deal like today's really helps you land a winning upgrade. At Amazon, you can clip a coupon and add the code Q2BJETPO at checkout to pick up the Hexgears low-profile Immersion A3 TKL gaming keyboard for just $42.20. That's a saving of $30.59 on the current list price, and a superb value considering this keeb launched at $159 in 2024.

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The Hexgears Immersion A3 features plenty of bright, gamer-ready RGB lighting with onboard profiles and more available via the Hexgears software. The keyboard also features a small TFT screen that gives you current keyboard info, such as a Caps Lock indicator and battery life updates. You can also upload customizable GIFs to personalize your peripheral further.

The Immersion A3 TKL is very thin, and it doesn’t take up much desk space, thanks to its compact TKL layout. There's a choice of switch types, with all versions available for the same price. Choose between Kailh White Rain (silent, linear), Kailh Black Cloud (tactile), or Kailh Hide Mountain (clicky). All of these switches are low-profile and come pre-lubed, with a total travel distance of 2.8mm. The Immersion A3's PCB is hot-swappable, with other 3-pin switches, so you can change up your low-profile switches in the future if you have a preference or fancy something different.

A wireless, low-profile keyboard for just $42.20 is an absolute bargain, especially with so many features. Its versatile connectivity allows the Immersion A3 to connect to multiple devices easily via 2.4GHz wireless, Bluetooth (up to three connections), or wired via a 5.9-foot (1.8m) USB-A to USB-C cable.

Check out our review of the Hexgears Immersion A3 TKL gaming keyboard for more information if this deal piques your interest.

Developer Xusheng Li has uncovered some previously unknown functionality deep within Microsoft’s Paint and Photos apps. The findings concern GUID watermarks. While these programs clearly add Copilot logo watermarks to images where LLM image generation has played a part in the process, Li also uncovered an invisible watermark and the process behind embedding it. To be clear, both these watermarks are merely to identify/verify imagery where AI has had a role in the creation, so GUID should not be confused with the recent controversies over Microsoft’s GDID traceable device-specific telemetry.

Li says that simple curiosity spurred him to investigate the AI features of the Paint app in Windows 11. The image generation functionality being capable of calling a remote API was expected. However, the dev got more curious when four apparent model files were found in the app path for local processing. Specifically, one of the local files was an ONNX-like model, the other 3 were encrypted ONNX-like files…

With all four files unencrypted and open to probing, investigations led to watermarker.dll being uncovered. Initially, Li thought it was just for visible watermarking tooling, leaving a Copilot logo on the bottom right of the image. It calls the AddPerceptibleWatermark function to do this. However, with curiosity stoked by the DLL file’s larger-than-expected size, the dev decided to ask AI to analyze the file. The AI found there was also a function to embed an invisible watermark.

The invisible watermarking function is called WmkWriteWatermark. Microsoft’s embedding process basically insists on this invisible watermark in its Stable Diffusion image generation output. If WmkWriteWatermark fails for any reason, the generation process will result in an error.

Coalition for Content Provenance and Authenticity (C2PA) credentials

Li provides some further technical insight into the hidden watermark. Most strikingly, he asserts that the watermarking information mixes a server-issued GUID into the pixels. That isn’t the end of the identifying data bundling. “Paint does more than alter the pixels,” notes the dev. “It also attaches C2PA Content Credentials to the saved file. The code responsible for this lives in ProvenanceHelper.dll, backed by provenancesdk.dll.”

In conclusion, even on devices where local image generation occurs, the prompt is still sent to Microsoft servers for moderation, says Li. Moreover, the dev indicates this watermarking is mandatory, and if the process fails, Paint will abort the entire image generation process. In Photos, there is the same GUID mechanism in place when AI is used, but it will still return the image and just log an error if the watermarking process has issues.

It is thought that all this hidden processing “might be related to Article 50 of the EU AI Act, whose transparency rules took effect on August 2, 2026, and require AI-generated content to carry a detectable, machine-readable mark—but not a prompt-specific GUID.”

The U.S. government is looking to move a critical transparency step in the approval of data centers behind closed doors. The Environmental Protection Agency (EPA) has plans to remove a requirement that forces states to seek public feedback on applications for air pollution permits, as reported by The New York Times. The change, if it goes into effect, would apply to a subset of air pollution permits. However, the primary concern is around data centers, as local communities seek to delay, or outright ban, AI data center construction.

The latest proposal applies to permits for a "minor source" of air pollution, which includes landfills, laundromats, steel mills, and, of course, data centers. However, recent analysis of the expansion of AI data centers suggests that environmental impact is growing. The Harvard School of Public Health estimated that the Vantage data center in Loudoun County, Virginia, contributed between $53 million and $99 million in annual health damages, the largest estimate for any single facility ever.

In another example, the analysis conducted by researcher Michael Cork directly influenced a proposal in Fluvanna County, Virginia, to expand a fossil fuel plant. The expansion was ultimately denied based on the findings from the analysis that "shaped the public discussion leading up to the... vote."

The proposal from the EPA would remove, or at least create the opportunity for states to remove, the public discussion that shapes these decisions. The EPA's stance has been that these minor sources don't require federal oversight. However, there's a clear gap when a federal agency decides to stop enforcing federal rules and asks states to step in to make their own decisions.

The Attorneys General from 14 states and three cities signed an open letter opposing the change, writing, "despite the name, even 'minor' sources can pose significant health and environmental impacts." The letter suggests that removing the required publicization of permit applications and 30-day comment period "sidelines these fundamental transparency and democratic safeguards in the name of administrative expediency and relieving regulatory burdens, particularly for accelerating the buildout of data centers and other artificial intelligence (AI) infrastructure."

Although the EPA requires a public comment period after an air pollution permit application, the process has been circumvented in some cases.

In Gilroy, California, an Amazon data center began construction last month without the knowledge of many residents. A years-long approval process between the city and Amazon meant the public comment period had lapsed two years before construction began, leaving the public little time to react. In another case, residents of Festus, Missouri sued the city, arguing that it didn't give the public enough time to review a data center proposal before moving forward with it.

With the EPA's proposed change, responsibility for regulating data centers is placed on the states. Current environmental law allows states to impose stricter environmental standards than the federal minimum, provided the state does not fall below it. The EPA change would allow a state to eliminate the public comment period, since it's not required by federal law.

Currently, a public comment period is still required. The proposed change would go into effect within the next year.

A family from Pierce County in Washington, Seattle, claims that thieves broke into their home and stole a haul of retro Nintendo hardware worth more than $50,000. Amongst other items taken, Fox13 reports the perps made off with more than 850 NES games, collected by the family over the span of some forty years.

According to the report, the thieves simply forced entry to the home by breaking in through the front door. The stricken family told the outlet that it appeared the thieves knew the layout of their home, targeting the master bathroom and making off with a tennis bracelet, amongst other things.

"They’ve been in our home. They know our home layout. They’ve been in our master bathroom. They took my wife’s tennis bracelet," Roger Holler said. The prize haul, however, seems to have been the aforementioned bundle of retro video games.

Holler told the outlet he had begun collecting Nintendo games from 1984, and had spent some 30 years "driving around on the weekends from game store to game store." Holler's son reportedly said the father and son duo would spend up to 10 hours on car journeys, collecting and cleaning the cartridges.

All in all, the collection amounted to 850 NES games, some of which are said to have been worth a small fortune. An image from the report shows five games that appear to be from the collection, likely not worth more than $25 a piece as loose cartridges. They are:

• The Legend of Kage (1987)
• Ice Climber (1985)
• Raid on Bungeling Bay (1987)
• Rygar (1987)
• Donkey Kong 3 (1986)

Depending on the condition and the game, NES titles can indeed fetch astonishing amounts of cash in today's retro market. One lucky scavenger recently discovered a collection of 97 untouched Duck Hunt and Super Mario Bros. cartridges, thought to be worth $10,000 each. In 2024, an ultra-rare NES Gold Nintendo World Championships cartridge sold for $207,400.

Given the stated value of the stolen collection, Holler told the outlet that it "was going to be my grandkids' inheritance or college tuition." Beyond the financial value, Holler lamented the loss of decades of family history.

A fake Israeli think tank credited migration-policy research to an Australian professor of food science, ran a "sovereignty index" that scored Russia above the countries criticizing its war, and filled its site with academic papers lifted from their real authors. OpenAI banned the cluster of ChatGPT accounts behind it on August 25, tracing the operation back to Russia, where operators used VPNs to reach models blocked in the country and drafted mostly English-language posts promoting the outlet across Substack, Telegram, X, Facebook, and LinkedIn. Of 36 articles OpenAI sampled from the International Burke Institute, as the outlet called itself, 34 were copied from real academics, some misattributed to figures including Francis Fukuyama and Noam Chomsky.

OpenAI says that the operators used ChatGPT to write the posts and replies that directed audiences towards the IBI website, which was registered in February last year, while the articles, the country reports, and the index itself weren't produced with OpenAI's models.

Instead of using ChatGPT to write the articles, the operators used the chatbot to strip any wording that might mark them as Russian speakers, yet the non-AI material carried obvious tells. One IBI article referred to Germany's traffic-light coalition as "the Svetofor coalition," a literal rendering of the Russian word for traffic light that no English or German writer would use. A profile that OpenAI tied to the operation described a U.S.-focused Telegram channel as offering "a totally unhackneyed perspective."

This is OpenAI's sixth public threat report since it began making disclosures in early 2024. Since then, its Intelligence & Investigations team says it has disrupted more than 40 malicious networks. Similar findings recur across all of them, with operators bolting AI onto existing workflows for efficiency and distribution, not content generation.

OpenAI placed this campaign at the lower end of Category Three on the Brookings Breakout Scale — a six-category model that measures the real-time impact and spread of disinformation campaigns — with individual posts drawing low view counts and the operation's Telegram channels running between 10,000 and 20,000 followers each.

OpenAI ran the same enforcement against China-linked clusters in June, when it banned accounts behind the "Data Center Bandwagon" campaign that amplified U.S. data center electricity backlash. The ban lands on operators who were already reaching OpenAI's models via VPN, since Russia is blocked from its services, for a campaign that barely reached anyone.

"The significance of the operation lies less in the audience it reached, however, than in the infrastructure it had built," said OpenAI. Anthropic's own AI-capability disclosures drew scrutiny in April, when its claim that Claude Mythos found thousands of severe zero-days proved to rest on 198 manual reviews.

About a month ago, techie Redditor Alternative-Panic69 (Panic) had the idea of acquiring a Radeon 7900 XT with 20 GB of VRAM for LLM use, a significant undertaking in their home country of India. They found one for $550, an excellent deal even by Western standards, and they were off to the races with Qwen and GLM in tow. Panic intended to use this card in a Lenovo M910Q desktop, but the machine wouldn't cooperate, so recently they turned to the next logical thing: a Lenovo Yoga laptop.

As Panic themselves put it, they took the "completely sane decision to perform surgery on [their] laptop." Armed with an ADT-Link PCIe external cable connector wired to the laptop's M.2 slot, a DeepCool PL750D power supply, and some quick bottom-panel removal, they managed to wire everything together in a manner that mostly worked.

With the M.2 slot now unavailable, the first challenge was having somewhere to boot from, a task accomplished by a USB SSD. Getting a picture with the main display hooked into the 7900 XT "worked beautifully", with Furmark doing 500 FPS at 1080p. This arrangement had to go, though, as the display framebuffer(s) were eating into precious VRAM necessary for the models, so the integrated graphics silicon was back to its original assignment.

Panic mused at how "[their] laptop was sitting there looking like it had been converted into a PCIe development board," but ended up having some harsh realizations about trying to wrangle fairly large LLMs (Qwen 35B A3B, GLM-4.7 Flash) exclusively on the GPU, all with a 128K-token context window.

Another Redditor pointed out that was a classical "pick two out of three" situation, and indeed that was the case, as Panic found that ultimately his laptop's memory (or lack thereof) proved to be a serious bottleneck. The large context window needed lots of associated data in RAM, and eventually the available DRAM was exhausted, and the laptop began using swap space, grinding performance to a halt, to the point where the GPU was "being idle, occasionally in bursts."

The story ends in somewhat predictable fashion: as interesting and visually striking this project was, they needed their laptop as an actual mobile device again, so they elected to buy the cheapest AM4 machine they could find to fit the Radeon 7900 XT and the power supply in. As Panic themselves said, "buying an old office tower would have been the sensible solution. I wasn't here to be sensible."

A special edition of the Commodore 64 Ultimate made in collaboration with CD Projekt Red has been announced today. The new Commodore 77 takes its stylish inspiration from Cyberpunk 2077, of course, and is skillfully melded into the game's universe. This isn't just a paint job. Commodore has packed in a faster FPGA, for one thing. It also comes with an exclusive 2MB demo cartridge, a themed Commodore 77 BASIC 2.0 boot screen, and several further flourishes of sheer finesse.

• Check out the new Commodore 77 at Commodore.net

Commodore says that the C77 is the first franchise hardware partnership in the firm's 68-year history. "I have been a fan of the game since its release, and it was rewarding to learn in my discussions with their Joint CEO, Michał Nowakowski, that he was a lifelong Commodore 64 fan in turn," said Peri Fractic, President, CEO, and Chief Product Officer, Commodore, discussing this collaborative product. "For us both, this has been a collaboration where art imitates life, and in turn, life for the denizens of Night City now imitates that art. We hope they enjoy their new terminal."

There's plenty to be said about the artistic style of the new C77, but we'll let the video and images do the talking. It might be worth pointing out some of the finer points, though. Like, yes, that is a brushed metal plate to the right of the keyboard deck, which is distinctly different from the original beige bread bin.

Turning on the C77, there are new experiences to be had. In addition to the custom Cyberpunk 2077-themed Commodore 77 BASIC 2.0 boot screen, there are new menu colors, fitting in with the game universe. Moreover, there's a 2MB Cyberpunk 2077-inspired demo cartridge in the (themed) packaging. You can plug in this cart to enjoy an exclusive, distinctly Cyberpunk demo created by the long-running Polish C64 demo group Arise, with an original soundtrack by chiptune legend LukHash. The audioscape makes use of the C64U's 24 channels of stereo SID chip music, while demo viewers can watch the LEDs behind the Commodore 77’s smoked translucent base light up and dance in time.

Inside the new C77 you won't find the AMD Xilinx Artix‑7 XC7A50T, as used in the C64U. The system instead employs the next-tier Artix-7 XC7A100T with twice the logic, twice the block RAM, and more I/O.

It is interesting to learn about the change of processor, but we don't get any firm hints about how the extra compute resources will be used in the C77. "Word on the neon-soaked street is it will achieve speeds of 77 MHz, vs. the original Commodore 64’s 1 MHz processor speed," teases the official press release, in the only section which mentions the new FPGA. "This is achieved by utilizing the more powerful AMD Artix XC7A100T processor, compared to the 50T found in the Commodore 64 Ultimate."

The C77 is up for preorder from today, at $377. We've already mentioned, and you can see some of the obvious enhancements, but buyers will also get a "custom neon power light, stickers, pins, collectible themed packaging, a custom Cyberpunk 2077 spiral-bound user guide packed with lore, exclusive Cyberpunk 2077-themed type-in BASIC programs, and more." Product shipments will begin in "early 2027."

Incidentally, on Monday, Commodore released the Alien Breed 35th Anniversary Collection for PCs and consoles. That's six classic titles beloved of Amiga gamers, and PC users can wishlist them now on Steam.

Earlier this month, Samsung introduced the industry's first LPDDR5X-PIM memory, adding in-memory logic to the low-power memory standard, and at Hot Chips 2026, it dove into the memory technology that we've previously seen at play through HBM stacks.

PIM, or Processing-in-Memory, is a technology Samsung demoed as early as 2021, piloted through HBM stacks in AMD accelerators. It's a small bit of logic that sits alongside DRAM cells, allowing basic calculations to happen directly in-memory. By handling those basic calculations locally, Samsung is able to eliminate the processor as a bottleneck and speed up, in particular, AI inference. In inference tasks, Samsung says its LPDDR5X-PIM is 2.28x faster than standard LPDDR5X, in fact.

The reason for adding in-memory processing to LPDDR5X is pretty clear: HBM is too damn expensive. Micron warned just a day earning at Hot Chips that the HBM wafer demand is only getting worse, and Samsung opened its presentation with something we're all well aware of. Memory makes up the bulk of AI chip costs, and its share of the pie continues to grow. Add on top of that the power demands of DDR5, much less HBM, and LPDDR5X seems like an ideal target for PIM.

Samsung introduced HBM-PIM in 2023, and at the time, introduced the concept of LPDDR5X-PIM. What it shared at Hot Chips is a real product, taking the concept of LPDDR5X-PIM and putting it through validation. Samsung is also looking ahead for LPDDR6X-PIM, and the company says it hopes to have an initial specification from JEDEC this year.

Bringing in-memory processing to Samsung LPDDR5X

Above, you can see a basic layout of how Samsung integrated PIM into LPDDR5X. Each memory bank has its own PIM, which is an advancement over HBM-PIM, where Samsung had to cut banks to fit the logic. The memory bank, scale register file, and source register file feed parallel MAC trees. Once calculated, the output (either integer or floating point output) is written to a vector register file.

Samsung says its LPDDR5X can operate in two modes: single-bank (traditional DRAM) or multi-bank (PIM). Traditional DRAM controllers work, with commands switching between standard read/write or a PIM read/write depending on the mode. The challenge, according to Samsung, was reordering with conventional DRAM.

Samsung uses what it calls Address Align Mode (AAM) to get around the reordering issue. It maps DRAM addresses to MAC instructions, assigning the VRF/SRF address based on the RA/CA address, respectively, and not the Instruction Register File.

To demonstrate how data moves through the memory cells and calculations are performed, Samsung provided an example of a MAC operation, assuming weight parameters for the data are already written into the cell, and the memory is operating in multi-bank (PIM) mode.

Storing 512 bytes of FP8 activation data, it's first broken down into 16, 256-bit packets, which are written into each of the banks in and noted in the Source Register File.

A PIMX_RD reads the weight data from the DRAM bank, feeding into the MAC trees alongside the data from the SRF. Once the calculation is done, the output vector from each operation is written into the Vector Register File.

Once the calculation is done, a PIMX_WR command transfers the output data back to the DRAM bank. Samsung noted there doesn't need to be a 1:1 relationship between reads and writes, but it's useful for this example. With a VRF size of 1 kbit, a maximum of four calculations can be written to the VRF.

With the output written back to memory banks, the host just needs to read the data from memory. The host switches to single-bank (conventional DRAM) mode and executes 16 reads to gather the output from all of the memory banks.

Samsung LPDDR5X specs and preliminary performance

Samsung's LPDDR5X-PIM looks a lot like LPDDR5X. It uses a standard 561-ball array for packaging, just like LPDDR5X, and Samsung uses two 64-bit ranks with 16 GB modules. The critical number here is bandwidth. With LPDDR5X-9600, peak bandwidth is 76.8 GB/s, but that's increased by eightfold with PIM to 614 GB/s by reducing data movement and keeping basic logic local.

Samsung uses four dies per rank, for a total of eight dies. Not the various registers above, as well, as they're important for the illustration of data flow through Samsung's LPDDR5X-PIM memory.

In Samsung's preliminary benchmarks, LPDDR5X-PIM is impressive. In model run time, Samsung say a 2.28x improvement with PIM, and in tokens per second (TPS), PIM offered a 3.01x increase in performance.

The slide above shows what happened behind the scenes to gather these numbers, with Samsung using an edge AI accelerator — we're not sure which, but perhaps an early Gaia SoC — and testing Llama 3.1 with 8 billion parameters. Notably, the output is different, which one attendee pressed Samsung about. The company says optimizations are ongoing to improve accuracy, but it expects the performance benefit to remain the same.

One of the main advantages of LPDDR5X is right there in the name: low power. With PIM, power consumption becomes more of a concern, but Samsung says it doesn't expect higher power consumption overall compared to conventional DRAM. The presenter noted that peak power consumption will be "much higher" due to the bursty power draw of the PIM, but Samsung still expects overall power draw to be lower than conventional DRAM.

That comes down to extra reads/writes. Although PIM represents a power increase, decreasing the number of times data needs to move between DRAM and the host will lead to overall lower power consumption. "We're not having significant power increase," as Samsung's Karam Hwang put it.

LPDDR5X has, until recently, only had applications in consumer products. However, SOCAMM2 serviceable modules allowed Nvidia to use LPDDR5X as the memory of choice with its Vera CPU. And Intel uses LPDDR5X with its new Crescent Island AI accelerator.

Even with PIM, LPDDR5X doesn't come remotely close to the bandwidth with available with HBM, but it has a lot of applications elsewhere. Samsung's targets of server, client, and mobile are telling, with LPDDR5X-PIM accelerating edge AI on mobile and client devices, as well as arriving in lower-scope accelerators like Crescent Island.

Full Samsung Hot Chips 2026 presentation

Just over one week after Nvidia agreed to backstop up to $105 billion in financing for its data centers, OpenAI arrived at Hot Chips on Tuesday with benchmarks claiming its first in-house chip beats Nvidia's GB300. Jalapeño, the inference ASIC OpenAI co-developed with Broadcom, delivered 1.5 times to 1.9 times more throughput per kilowatt and 1.7 times to 3.6 times lower end-to-end latency than Nvidia's GB200 and GB300 rack systems on SemiAnalysis's public InferenceX suite, with a 700W part going up against accelerators rated at 1,200W and 1,400W. OpenAI plans to begin deploying the chip in its own data centers later this year.

The tests covered three open models: GPT-OSS 120B, DeepSeek R1 670B, and Moonshot AI's 1-trillion-parameter Kimi K2.5, with OpenAI reporting its widest leads at low-latency operating points, where it claims 8.6 times to 104.3 times more throughput per kilowatt at the GB300's fastest previous time-between-tokens settings.

OpenAI normalized the results to each accelerator's published package TDP, though it said Jalapeño's measured sustained power stayed at or below 550W in testing. An appendix comparison using all-in utility power per accelerator, 1.18kW for Jalapeño against 2.55kW for the GB300, produces narrower gaps, as does pitting Jalapeño against a GB300 running multi-token prediction, where the peak efficiency lead shrinks to roughly 1.5 times.

Jalapeño wasn't tested against Vera Rubin, the Nvidia platform that's slated to power the first gigawatt of Nvidia systems OpenAI agreed to deploy in the second half of 2026. The chip also doesn't train models, the workload where Nvidia's hardware remains unchallenged. In addition, the major comparisons ran Jalapeño's single-token prediction against GB300 configurations doing the same, even though Nvidia deployments commonly use multi-token prediction in production. SemiAnalysis, which said it ran InferenceX with OpenAI engineers in the company's lab, described the part as "beating every Nvidia, AMD, and Google chip we have been able to test."

Each Jalapeño package, unveiled in June after a nine-month RTL-to-tapeout cycle, pairs its compute die with six HBM4 stacks, totaling 216 GiB at 15.4 TB/s. The GB300 carries 288GB of HBM3E at a 1,400W rating, so per watt of rated power, OpenAI's chip packs roughly 50% more memory. The company's Hot Chips presentation states that the main bottleneck its architecture targets is exposing aggregate HBM bandwidth, not adding more of it.

That memory is of course the tightest commodity in the semiconductor industry. Samsung, SK hynix, and Micron have sold their HBM capacity through 2027, a shortage so severe that Nvidia is reportedly testing cut-down Rubin Ultra configurations with as little as 192GB, and SK hynix CEO Kwak Noh-jung has warned that 2027 will be the worst year of the crunch. Micron told the same Hot Chips conference on August 23 that HBM consumes roughly three times the wafer area of DDR5 for equivalent capacity, a penalty that widens with each generation. Scaling Jalapeño across the 10GW deployment agreement that OpenAI signed with Broadcom last October would make the company a substantial new claimant to HBM4 supply, which Nvidia currently dominates through multi-year allocation deals with SK hynix.

A second-generation chip is approaching tapeout, expected within months, according to Bloomberg, and concept work on a third generation is underway. The first part reportedly uses a TSMC 3nm-class process, keeping OpenAI in the same wafer, memory, and advanced packaging queues as Blackwell and Rubin for the foreseeable future.

OpenAI is procuring those inputs while deepening its financial dependence on the company it just benchmarked. On August 17, Nvidia agreed to provide up to $105 billion in financing for an OpenAI-leased data center campus in Ohio. "Nvidia is a really good partner, and we continue to need a lot of Nvidia," Richard Ho, OpenAI's vice president of hardware, told Bloomberg in an interview following the announcement.

PC case makers are often chasing trends. One moment, it’s all about RGB, then multiple glass side panels, then wood. Today, it’s all about glass and affordability with the new Hyte Y50 RGB, a panoramic iteration of the company’s iconic Y60 that ditches the vertical GPU riser, adds four RGB fans, and sees its MSRP slashed to just $99.99.

Hyte made its first big splash with the Y60, a unique take on the ever-popular O-11 Dynamic from Lian Li, but with a panoramic design, which allows for even more visibility of your components. The following year saw the launch of the Y70, which featured a 4k touch screen display in place of one of the glass side panels. The Y70 is fun, but expensive at $370.

But enough of those cases, because we’re talking about the Y50 RGB, which comes in four colors (snow white, pitch black, black cherry, strawberry milk and taro milk), and is a more budget-friendly solution, priced at $99. In addition to the fun colors, the chassis includes four interesting aRGB fans, which we’ll delve into in detail later on. That’s enough backstory; it’s time to explore the Hyte Y50 RGB and find out if it earns a spot on our Best PC cases list.

Building in the Hyte Y50 RGB

The Hyte Y50 RGB was an absolute pleasure to build in. There was a fair amount of clearance between the motherboard tray and cable cut-outs, so I didn’t have to perform any wizardry to route a specific cable. This is in large part due to the size of the Y50 – it has enough space to accommodate some larger E-ATX motherboards, as well as standard ATX and smaller form factors.

For perspective, the Hyte Y50 RGB can house GPUs up to 14 inches (360 mm), AIOs up to 360 mm, and CPU tower coolers up to 6.2 inches (160 mm). It's also a dual-chamber design, so there’s even more room behind the motherboard tray for the bulky 24-pin ATX cable. So, go ahead and install that MSI RTX 5090 Suprim! I would mention a giant CPU tower cooler here, like the Scythe Magoroku we reviewed, but the best move with a case like this would be to install an AIO liquid cooler such as the ASRock Phantom Gaming or any from our best AIO coolers list.

The rear of the case has plenty of space to install sleeved PSU cable extensions, or an extra string of SATA or even Molex power cables since it’s a dual-chamber design. If you’re unfamiliar with the term “dual-chamber,” it just means that the case is split, which allows for more room behind the motherboard tray (where the PSU lives) for cables. However, this usually results in a boxier/stout silhouette.

My favorite part of building in the Hyte Y50 RGB was when I discovered that the front-panel IO cable was bridged into one block. Ask anyone who’s built a PC, and they’ll tell you that one of the worst parts is connecting the front IO cables, because they’re tiny, and the text on the board that attempts to explain the correct orientation is even smaller. So, Hyte saves a lot of frustration by combining the headers into a single block that only fits one way.

Features

After I finished building, I realized how many quality-of-life changes Hyte made to the existing design of the Y-series. For example, there’s no longer a giant forehead or chin. In other words, the dead space above and below the glass you see in the Y60/Y70 is effectively gone in the smaller Y50.

While that’s not a drastic change, it’s cool to see the evolution of a design over years and mullitple iterations.

The fans on the side aren’t individual spinners. Instead, they are one piece, which makes for a much easier install and frees up a couple of your motherboard’s fan connectors. Another neat feature is the reverse fan blade orientation, which lets you intake cool air without flipping the fans around just to see the ugly support brace. Hyte didn’t cheap out on the fans' design either: They can spin up to 1,500 RPM, which is respectable for stock case fans. Would I slap these fans onto a radiator? No, but the company does offer the “THICC FR12 RGB” series, which sports the same unibody body design, brighter RGBs, and far-better static pressure if that’s what you are looking to do..

Quite a few glass cases are heavily tinted, preventing you from getting a clear view of your fancy build. But with the Hyte Y50, the glass is as clear as day. That’s good, but it does mean you’ll want to do as good a job as possible organizing and hiding any cables in your build, as well as opting for attractive components. This design is obviously all about showing off.

Despite M.2 drives having long-since overtaken SATA in popularity, Hyte hasn’t forgotten about SATA; sleds are included that can hold a very respectable 6x 2.5-inch or 2x 3.5-inch drives. So, if you’re looking to add lots of storage, you can use more than your motherboard’s M.2 ports.

From the back of the case, you can see the mounting holes for adjusting the height of 120 mm exhaust fan, as well as where the SATA storage sleds slot in, above the horizontal power supply mounting location.

The front IO is the typical pair of USB Type-A (5 Gbps) and a single Type-C (10 Gbps) connector, along with an audio/mic combo jack. I wish Hyte included an RGB control button, but the company, of course, wants you to use its robust Nexus software suite for lighting control.

Obviously, with a case like the Hyte Y50 RGB, support for water cooling has to be abundant, and it is. The top of the case allows for radiators as big as 410 mm long and 46 mm thick. The side can accommodate up to 360 mm, and the rear supports 120 mm, where the included exhaust fan lives.

Since this is a dual-chamber case, you get a ton of room for cables around the back, without having to worry about your side panel bulging outward. While I only installed the minimum amount of hardware here, I could have loaded this case up with storage, expansion cards, and more and still closed the side panel with ease.

Bottom Line

Hyte has made a name for itself in the PC building space as a brand that prioritizes aesthetics first – and usually that means most of its products have landed on the more expensive side of the spectrum. But the rising cost of RAM, storage, and GPUs means enthusiasts are looking for a bargain anywhere they can find one. And for $99.99 with three glass panels and four RGB fans, plus space for high-end components, there’s a lot of value here for those who want to show off their increasingly expensive PC parts.

We dug up another solid gaming combo from Newegg for the week; this one features an excellent gaming CPU in the Ryzen 7 7700X3D, a quality mid-range Asus B650 motherboard, and a single stick of G.Skill Ripjaws M5 Neo DDR5-6000 RAM. Newegg also throws in a free Cooler Master Elite Liquid 240 AIO to sweeten the deal. Priced at only $568.99 ($200 savings/26% off), it’s an inexpensive way into the highly upgradeable AM5 platform.

• Check out this deal on Newegg

For the RAM, this combo offers a single stick of G.Skill’s Ripjaws M5 Neo RGB DDR5-6000 CL36. And while on the surface you may think single-channel RAM isn’t ideal (it isn’t), you’d be surprised to see just how little it loses with AMD X3D chips like the one in this combo. Our recent testing puts a single-DIMM configuration only 3% behind dual channel in gaming with a Ryzen 9 9800X3D, and beats out DDR4 dual channel configurations in single channel (see charts below). If we apply the ~$200 discount to the RAM, that means you get a single 16GB stick for only $70. If you know 16GB isn’t enough for your needs, that same stick is currently running a promo (code NGZF248) for an additional $20 off. If you do the math, that’s ~$320 for 32GB of dual-channel G.Skill goodness, and one of the best deals going by today's standards.

While the Ryzen 7 7700X3D isn’t quite as fast as the 9800X3D, the 8-core 16-thread Zen 4 processor is still one of the top gaming chips and is well ahead of the recently re-released (and expensive, $349.99 at Newegg) Ryzen 7 5800X3D and Intel’s Core Ultra 7 270K Plus. Performance-wise, the 7700X3D is squarely between the faster 7800X3D and slower 7600X3D, and it clearly holds its own among its peers and is a great 1080p/1440p gaming chip while not paying for the more expensive 9000 series X3D chips. Newegg also throws in a free Cooler Master Elite Liquid 240 AIO ($80 value), which pairs nicely with the processor.

Last in this combo is the Asus TUF Gaming B650E-E Wifi. This budget AM5 motherboard has plenty of features and pairs well with the 7700X3D in the combo, even offering drop-in support for the 9000-series and future AM5-based processors should you decide to upgrade. The board has capable power delivery, three M.2 sockets (one PCIe 5.0) and four SATA ports, integrated Wi-Fi 6E and 2.5 GbE networking and is a good base for your AM5 PC.

With many individual component prices still through the roof, combo deals like this are one of the best ways to get the most out of your budget. For under $569, you get one of the fastest gaming processors available, a capable Asus B650 ATX motherboard, 16GB of RAM, and a free 240mm AIO on top of it. In other words, a great way to jump into the AM5 platform without breaking the bank.

Intel's Wildcat Lake is unassuming, launching with the message that it was a cutting-edge alternative to the MacBook Neo with Intel's latest node and some trimmings around the edges. Although Wildcat Lake is, indeed, a budget part with major concessions to reach a market increasingly pushed to the side by powerful PC hardware, it also comes with a major innovation: UCIe.

The Universal Chiplet Interconnect Express (UCIe) specification first debuted in 2022, coincidentally around the time that planning around Wildcat Lake began. Both AMD and Intel have rallied behind UCIe as an open interconnect communications standard, though they've primarily relied on their own chiplet communication technology like AMD's Infinity Fabric. In Wildcat Lake, Intel leveraged UCIe to reduce cost. Further, it was a key technology that allowed Wildcat Lake to exist in the first place.

Opening the Hot Chips 2026 presentation, Intel's Lance Hacking, lead engineer on Wildcat Lake, said the company had the choice between a monolithic design or a basic, low-cost Multi-Chip Package (MCP). Intel has Foveros for advanced 2.5D and 3D packaging, but for a budget part like Wildcat Lake, that wasn't an option.

Choosing to leverage UCIe over an MCP design shaped the Wildcat Lake we have today, setting a roadmap for where Intel could cut compute to save cost and in areas where it would need to optimize to fit the necessary communication channels for the two chiplets.

UCIe integration in Intel Wildcat Lake

As Hacking explained during his presentation, budget parts usually involve an N-1 design. You leverage older IP, trim around the edges to improve the economics of yields, and repackage it as a mainstream part. Wildcat Lake is different in that regard. It's taking Intel's latest, most advanced, and most expensive IP for compute and applying it to the budget domain.

With 18A at the center of the compute and ISMC's N6 handling the I/O die, Intel decided to make an MCP, which comes with some considerations. Advanced packaging allows designers to spend less die space on interconnects and use less power. With UCIe, Wildcat Lake's interconnect is 70% larger than that on Panther Lake, and even then, Intel says the change was worth it from a cost perspective.

Outside of space, power was the primary concern with using UCIe. Battery life, especially for a budget part meant to handle lighter workloads, is extremely important, and UCIe brings increased power demands. UCIe die-to-die is packetized, which led to a challenging design point, particularly around the display.

Intel says that idle systems without panel self-refresh were the "biggest power concern," as display signals need to cross the UCIe connection. To address the issue, Intel says it built a buffer to hold panel refreshes while the system was idle. This buffer is before the UCIe link, and it serves as an additional output buffer alongside the typical display buffer between the memory controller and display engine.

Without a base die for interconnect communication, UCIe also represents a large increase in die area. Intel trimmed a lot on both the compute and I/O dies to account for UCIe.

On the compute die, Intel trimmed down everything. Four Xe cores dropped to two, and without a dedicated ray tracing accelerator, the NPU went from three tiles to a single tile, and the memory subsystem was downgraded to a 64-bit bus, with lower maximum speeds and lower capacity. As mentioned, there were a lot of cuts in the display engine, which was a primary concern for die space and power.

Intel uses three display pipelines instead of four, opting for HBR3 as opposed to the massive bandwidth offered with UHBR20. That still provides 4K60 and can drive three external displays, which is plenty for a device in the class that Wildcat Lake is targeting. Trimming down the compute die allowed Intel to claw back 38% of its die space.

On the I/O die, Intel claimed back 15% die area by removing the camera PHY, reducing PCIe and USB support, and slimming down the audio engine. The camera was completely removed, placing the onus on OEMs to integrate their own controllers.

UCIe 3.0 is capable of up to a data rate of 64 GT/s, but Intel capped the transfer rate in Wildcat Lake at 8 GT/s. That still allowed Wildcat Lake to support mainstream PCIe 4 SSDs and 4K60 external displays, but running at a lower data rate reduces bit-rate errors and therefore allowed Intel to remove some bit-correction systems.

Reducing the cost of Wildcat Lake

Cutting down the compute and I/O dies saves money, but there are several other considerations when talking about the cost of a mobile SoC like Wildcat Lake. The economics need to work in the final product, which Intel touched on in its Hot Chips presentation, both from the perspective of the total bill of materials for OEMs and the yield/loss rate.

The big factor in cost savings was the elimination of the base die, which not only reduces raw material costs but also comes with the yield upside, without advanced packaging.

As usual, Intel bins Wildcat Lake into different SKUs, though it was careful to only attempt recovery where it could. For instance, it could package a single working P-core as a Core 3 304 instead of a 320. However, it didn't attempt recovery in areas that would compromise key design points of Wildcat Lake.

For instance, it didn't attempt recovery on LPE clusters and I/O, as they're critical components of Wildcat Lake. The goal, according to Intel, was to create a stack that customers actually wanted to buy while trying to maximize yields where possible.

Intel also considered the full bill of materials for Wildcat Lake. Intel integrated Wi-Fi 7 and a USB PD controller, cutting costs for OEMs to integrate their own controllers. Perhaps the biggest point of savings was in memory, using a much slimmer bus and a 6-layer PCB as opposed to eight layers. Extending off the chart above is Project Firefly, Intel's initiative to leverage the mobile supply chain for budget laptops.

Interestingly, Intel also included an area that led to higher cost but met the design goals of Wildcat Lake, that being a dedicated power rail for the LPE cluster. The "low-power island," as Intel calls its LPE cluster, is critical to Wildcat Lake considering every SKU comes with only one or two P-cores. That dedicated power rail allows the vast majority of lightweight workloads to run on the LPE cluster and earn back battery life.

Wildcat Lake is one of the more interesting consumer launches we've seen in the past year. There's the MacBook Neo and Snapdragon C competing in the same space, but both use mobile SoCs in the traditional N-1 design point for budget platforms. Wildcat Lake is different, based on Intel's latest node, and leveraging newer open standards to achieve a lower price. That's why it won a Tom's Hardware innovation award for 2026, after all.

Full Intel Wildcat Lake Hot Chips 2026 presentation

We're keeping a close eye on deals that pop up, looking for any and all RAM bargains to be had and adding them to the constantly-updated list below. RAM is expensive right now, but the brutal fact is that it is only going to get more expensive in the months ahead. Inflation on prices is making it hard to find value in the memory market, but there are some deals you can still buy. You might be holding off for the market to stabilize, but signs indicate this problem is going to get worse in 2027, not better. You can also find good deals, often yielding the lowest overall RAM pricing, if you check our RAM bundle page. There, we list combo deals that involve buying multiple items, like a CPU, motherboard, and RAM together, that then yield lower overall pricing.

Because the RAM market is very volatile right now, these deals tend to move quickly, so it's a good idea to act sooner rather than later so you don't miss out on a great opportunity. We're updating this page constantly to keep the deals fresh, but you will have to act fast to snag the last deals on memory we will likely see for at least a year, if not longer.

We've put together a handpicked list of the best options to make your shopping easier. We carefully review offers from different retailers to find the best value for you, drawing on our extensive experience from thorough reviews, detailed benchmarks, and analysis of past prices. We keep a close eye on the latest RAM deals as they come up, highlighting the top choices we've found across various stores.

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• Amazon: Up to 18% off RAM at Amazon

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Also, you can join the Tom's Hardware deals Discord for up-to-the-minute hardware deals.

Intel shared more details of its Crescent Island AI accelerator, powered by the Xe3P architecture, at the Hot Chips symposium this week. Unlike Nvidia's Rubin and AMD's MI455X GPUs, which are high-power, exclusively liquid-cooled chips with massive pools of HBM4 memory that provide maximum performance across both AI training and inference workloads, Crescent Island is designed to fit into a lower-power, inference-first niche in the AI accelerator market.

As a refresher, Crescent Island is a 350W air-cooled PCIe card that uses up to 480 GB of LPDDR5X memory, meaning it can be deployed in traditional servers without exotic power and cooling requirements. We've already learned about some of Crescent Island's DNA from past disclosures, but Intel went deeper into the chip's architectural details at Hot Chips.

Crescent Island is built up from four Xe3P slices, each containing eight Xe Cores, for a total of 32. Each Xe Core has eight Xe Vector Engines and eight XMX matrix accelerators, for a total of 256 of each resource.

The Xe3 graphics architecture, as seen on Intel's Panther Lake processors, already modified the capacity and flexibility of the GPU cache hierarchy to improve utilization and decrease performance-sapping register spills, and Xe3P further refines that hierarchy.

The Xe3P Xe Core has twice the amount of general register file space for working data versus Battlemage. Each Xe Core now has 1MB of general-purpose register file space, up from 512KB on Battlemage and Xe2. In addition, Xe3P offers 512KB of L1 cache or shared local memory per Xe Core, a structure that started out at 256KB on Battlemage and grew by approximately 1.33x on Panther Lake's Xe3 GPU. The chip also has 32MB of shared L2 cache. These expanded caches are meant to serve the chip's larger matrix accelerators on its AI compute-focused mission.

Xe3P boasts a larger systolic depth in its XMX engines than past Xe GPU designs. Xe3P's XMX systolic engines are a 16-deep design, meaning they can process matrices in much larger chunks than the four-deep systolic design of Xe2 and Xe3. Nvidia doesn't discuss the architecture of its Tensor Cores in anywhere near this level of detail, but as an AI inference-focused part, the fact that Xe3P can theoretically work on more elements at once during general matrix-multiply operations is an important capability boost for Crescent Island's inference ambitions.

Intel is also prioritizing a broad range of data types with this chip, from FP4 formats with microscaling support (aka MXFP4) all the way to what it describes as full-rate double-precision (via 64 FP64 FMA units per Xe Core). FP64 isn't widely used in AI workloads, but Intel says that the inclusion of full-rate processing for that data type makes Crescent Island useful as a converged high-performance computing and AI chip.

Each Xe Core also supports sigmoid and tanh transcendental functions, which are important to a variety of operations during AI inference, especially the softmax function. AMD and Nvidia have prioritized the performance of these functions in their recent architectures as well, so the fact that Xe3P offers support for them is key for its AI-first initiatives.

While Crescent Island does have a media codec block featuring four encoders and decoders to help serve up video to multimodal AI models, gamers hoping for a glimpse of future Arc cards won’t find it with this product, as graphics-specific functionality like RT cores has been omitted from this chip to preserve die area for compute functionality.

As a data-center-focused part, Crescent Island offers a full suite of reliability, availability, and serviceability features, including ECC and parity protection across the die and a range of memory reliability features.

As for the specific applications that Crescent Island will target, Intel highlights the rise of mixture-of-experts models paired with speculative decoding as a new class of workload that Crescent Island can serve well.

Speculative decoding strategies vary, but in general, they use a fast, lightweight mechanism to create drafts of future tokens that the main model can then be used to accept or reject, potentially improving decode performance. Not every draft token generated this way will be approved, but much like speculative execution in CPUs, it helps produce useful work from compute resources that would otherwise be left idle.

As model serving recipes pursue more aggressive drafting mechanisms, more compute is required to generate those draft tokens. At a high level, that understanding changes the common perception of decode as being a mostly memory-bandwidth-bound operation.

As an LPDDR5X-powered chip, Crescent Island won't have the eye-popping bandwidth of HBM-backed accelerators at its disposal for maximum performance with traditional autoregressive decode, so any help it can get from these speculative methods will be helpful.

Overall, Intel claims that Crescent Island is built to offer high FLOPS per watt and that it's optimized for compute-bound workloads like prefill (aka prompt processing and KV cache construction). Intel's emphasis on those areas of AI performance, as well as heterogeneous deployments, suggests that this chip could have a niche alongside HBM-backed accelerators whose resources are best used for decode operations.

Intel and its partner SambaNova could both stand to benefit from such an arrangement, as that company's SN50 inference accelerators are explicitly built to benefit from disaggregated prefill processing powered by GPUs. SN50 racks and Crescent Island are both meant to serve as lower-power, air-cooled systems that customers can deploy in existing data centers without dramatic upgrades to power or cooling infrastructure, so there is broad synergy in the shape of those products.

Intel still isn't discussing just how many theoretical compute FLOPS to expect from Crescent Island, nor is it disclosing memory bandwidth figures. But the architectural decisions it's shared so far — getting lots of data close to the compute engines of the chip and processing more of it at once in a relatively narrow power envelope — seem sound in a world where the company is still trying to reset its AI ambitions after a string of high-profile product failures and cancellations.

Intel has promised Crescent Island for a second-half 2026 time frame, and the clock is ticking on that launch window, so we’re eager to learn more about the chip’s final specifications, as well as customer and partner wins, when that launch does occur.

The AI-apocalypse is upon us, and regular consumers are paying that price in a big way. Apple went on a price-hiking spree in late June, leaving only iPhones and AirPods untouched. The bulk of Apple’s computing devices saw price increases ranging from a few hundred bucks to $1,300. Apple is now ushering in a new wave of price increases with the refreshed Mac mini and Mac Studio.

The new M6 Mac mini is now priced at $899, a $100 increase over the already inflated $799 price for the M5 version on June 25th. To put those increases in perspective, the M4 Mac mini had a base price of $599 when it originally launched in October 2024.

The new $799 base price is an even more bitter pill to swallow, given that the headless computer still comes with only 256GB of base SSD storage. One would think that the $300 price increase over the course of two months would at least lead to a doubling of the base storage, but the ongoing memory/storage shortage makes that wish unthinkable; at least in Apple’s eyes.

If you want to see more eye-watering pricing, take a look at the hardware upgrade costs for the base Mac mini. The system comes standard with 16GB of unified memory, but an extra 8GB (taking the total to 24GB) costs a whopping $200. If you want 32GB (the maximum allotment for the M6 chip), that’ll cost you an extra $400.

Things don’t look much better on the storage side, with an upgrade from 256GB to 512GB costing $200. The 1TB and 2TB storage options cost $500 and $1,000, respectively. Apple’s value-leader Mac mini is now in uncharted territory. A maxed-out Mac mini (M6, 32GB, 2TB) costs $2,229.

Even the M5 Pro version of the Mac mini couldn’t escape the AI tax, as the base configuration now costs $1,699, up from $1,599 for the M4 Pro version (June 25 pricing) and a far cry from the $1,399 price of the previous generation earlier in the year. That price gets you a 15-core GPU and a 16-core GPU, while stepping up to the uprated 18-core CPU/20-core GPU version adds $200. Memory upgrades are deflating to the psyche, as upgrading from 24GB to 48GB adds $600, while the 64GB option is $1,000.

Storage options are absolutely mind-boggling: a 1TB SSD requires an additional $300 outlay, while the max 8TB SSD configuration is listed at $3,800. The range-topping configuration (M5 Pro, 18-core CPU/20-core GPU, 64GB, 8TB) costs $6,699.

If there’s any consolation, the new Mac Studio holds the line on pricing ($2,499) in its base configuration (18-core CPU/32-core GPU, 36GB, 512GB). The price stasis is somewhat surprising given the hardware upgrades, including a new M5 Max SoC and PCIe Gen 6 SSD. However, upgrades are pricey, with the 18-core GPU/40-core GPU variant of the M5 Max adding $300 to your bill. The upgraded SoC is the only way to unlock additional memory options (48GB, 64GB, 128GB).

Stepping up the Mac Studio with M5 Ultra more than doubles the base, entry price of the M5 Max config at $5,499. This gets you a 30-core CPU and 64-core GPU, while the upgraded 36-core CPU/80-core GPU is a $1,300 option. 96GB of RAM comes standard, while 256GB is a $4,000 upcharge. SSD options are equally expensive: 2TB costs $500, and 16TB costs $7,500.

No matter which way you slice it, those firmly entrenched in the Apple hardware ecosystem are paying a heavy price for memory/storage shortages. Apple customers are doubly affected, as the company’s traditionally outrageously priced memory and storage upgrades have become even more expensive, putting Apple’s previously value-driven models like the Mac mini out of reach of bargain shoppers.

Apple has today unveiled its next-generation M6 Apple silicon chip, as well as a powerful M5 Ultra. The new chips will debut in new versions of its Mac Mini and Mac Studio, respectively, available to pre-order from today.

The M6 is Apple's first chip on a 2-nanometer process, utilizing a 12-core CPU with two super cores, four performance cores, and six efficiency cores. The chip also features a 12-core GPU and a 12-core GPU featuring neural accelerators, alongside a "Dual 16-core Neural Engine." The top version of the chip has 170GB/s of memory bandwidth.

That dual 16-core neural engine means that there are indeed two neural engines. There's a connection between the engines, allowing them to run one model quickly across both, or two separate models independently.

The M5 Ultra is Apple's first chip using its UltraFusion technology to form a quad-die architecture (The M5 Max chips it is connecting both used two dies). The chip goes up to 36 cores on the CPU and up to 80 cores on the GPU, with 1.2TB/S of unified memory bandwidth, which Apple says is 50% higher than the M3 Ultra. Apple also claims the 36-core CPU with 12 super cores and 25 performance cores will offer "up to 1.25x higher single-threaded performance and up to 1.3x higher multithreaded performance than M3 Ultra."

The M5 Ultra has a 32-core neural engine, but this is different from the dual 16-core neural engine on the M6. Because the M5 Ultra uses a pair of M5 Max chips over UltraFusion, the 32 cores across the dies to run two models in parallel for increased performance.

Both M6 and M5 Ultra feature GPUs with neural accelerators and their fastest cores, marking a leap forward for Apple's graphics processors when it comes to AI.

Apple users who have been maxxing out previous versions of the Mac Mini will be capped at 32GB of memory on the Mac Mini with M6, like a choice the company made due to the component shortage that has been affecting the entire industry. If you want 64GB like the M4 Pro, you'll need the M5 Pro model. But the M5 Ultra in the Mac Studio won't have that problem, with Apple offering up to 512GB of unified memory on that chip.

M6 also features updates to hardware-accelerated ray tracing, dynamic caching, and the shader core, which the company claims will allow for faster rendering and higher frame rates in games.

Mac Mini and Mac Studio

The new Mac Mini and Mac Studio aren't seeing any design changes, though there are substantial internal changes. Both systems are available for pre-order today, but won't arrive to customers and in retail stores until September 22.

Besides the M6 version of the Mac Mini, there will also be versions with M5 Pro. Both models will be bumped to Wi-FI 7 and Bluetooth 6, as well as 2.5Gb Ethernet (up from 1Gb), with a 10Gb option available as an upgrade. The Mac Mini also supports genlock via USB-C, synchronizing displays and cameras to prevent video drift during broadcasts.

For those working with AI, Thunderbolt 5 on the M5 Pro Mac Mini will allow customers to run clusters for on-device models.

The Mac Mini with M6 will start at $899, while the M5 Pro option will begin at $1,699 (each drops $100 for education pricing). Given that the Mac Mini with M4 started at $599, it's seeing substantial price hikes here.

The Mac Studio will come with M5 Max or the new M5 Ultra chip, and Apple is positioning it for on-device AI. It will now offer up to six Thunderbolt 5 ports with support for as many as eight displays. Like the Mac Mini, it's also getting Wi-Fi 7 and Bluetooth 6 with Apple's N1 chip, which debuted in the iPhone 17 lineup. Like the Mac Mini, the Mac Studio also supports genlock for perfectly synced video.

The Mac Studio with M5 Max will start at $2,499 ($2,299 with an education discount), and the M4 Ultra model will start at an eye-watering $5,499 ($5,099 with an education discount).

Both systems will be compatible with macOS 27 Golden Gate, including Siri AI and refinements to the Liquid Glass design introduced in macOS 26 Tahoe.

China is slowing or restricting shipments of materials based on germanium and quartz to Taiwan, which creates supply constraints for multiple industries on the island, according to Nikkei. Companies are reporting problems obtaining germanium- and quartz-based materials as well as permanent magnets from Chinese suppliers as customs procedures extend delivery times. In some cases, Taiwanese manufacturers lose orders while waiting for clearance.

China imposed export controls on germanium in 2023 and on quartz (SiO₂) in late 2024. At one point, China even restricted exports of gallium and germanium to the U.S., but later lifted the ban and imposed an export control regime. Under the regime, the exporter must disclose the customer and intended use by the end user, which enables Chinese authorities to essentially view, and to some degree, control the whole supply chain. China's Ministry of Commerce can approve, reject, or effectively delay the shipment while reviewing it, which is apparently what it does these days.

The Nikkei story strongly suggests that the delays are selective rather than a blanket slowdown of all germanium, quartz, and magnet exports to Taiwan. Germanium, quartz, and magnets can be used widely across many industries. Yet, the report specifically pins germanium and quartz to optics/photonics and semiconductor manufacturing, and permanent neodymium magnets to the aerospace industry that produces high-performance motors for robotics.

While the report does not determine exactly how granular the targeting is, Nikkei's sources specifically come from optical technology, semiconductor equipment, and aerospace companies. Another thing to note is that all of Nikkei's sources come from Taiwan, indicating that China targets select verticals of the island, not the same verticals globally.

In general, the situation looks less like 'no germanium/quartz/magnets for Taiwan' and more like selective friction applied through China's dual-use export-control regime. The particularly interesting part is that Beijing may not need a Taiwan-specific embargo: by examining the material, buyer, end user, and shipment, authorities can potentially slow strategically sensitive supply chains (think optical connectivity for data centers) while allowing less sensitive trade to continue.

Germanium

Germanium is widely used in infrared optics (Ge), silicon photonics (Ge), photodetectors (Ge), and optical fiber (GeO₂). China controls about 63% of the global germanium — both elemental and dioxide — supply, whereas all other countries — led by Belgium, Canada, and Japan — control 37% of the market, according to InvestInGermanium.com. The U.S. mostly gets germanium and germanium dioxide from Belgium and Canada, according to Introl.com. Meanwhile, Belgium and Japan also import germanium from China, which highlights that the world still largely depends on China when it comes to germanium supply.

While infrared optics is certainly a concern for state security as it is used for night-vision equipment, aerospace sensors, and military systems, it looks like China is more concerned about optical connectivity that is crucial for AI data centers.

In silicon photonics, germanium is mainly used to make photodetectors. Silicon cannot efficiently detect light at the ~1.3 µm and 1.55 µm wavelengths commonly used for optical communications, but germanium can. By integrating germanium with silicon waveguides, manufacturers can build high-speed Ge-on-Si photodiodes that convert optical signals into electrical ones. These detectors are used in optical transceivers and data-center interconnects and could play an important role in co-packaged optics (CPO).

Equally important, germanium dioxide is crucial for optical fiber manufacturing. Adding GeO₂ to silica raises its refractive index and enables manufacturers to form a higher-index fiber core surrounded by lower-index silica cladding in a bid to confine light inside the fiber. Germanium doping also increases silica's photosensitivity, which enables fabrication of fiber Bragg gratings used for wavelength filtering, optical communications, lasers, and sensing.

China's dominant position in germanium gives the country potential leverage over multiple layers of the optical connectivity supply chain, from silicon photonics photodetectors all the way to the optical fiber itself. If restrictions cover the appropriate germanium products and persist long enough, they could increase lead times and constrain production across several optical-interconnect segments simultaneously.

However, none of the optical connectivity applications depend exclusively on China. Germanium can come from non-Chinese producers, recycling, inventories, and alternative supply chains, and not every optical fiber necessarily has the same germanium requirements. In fact, the refractive-index difference can also be engineered with other dopants, eliminating the need for germanium or its dioxide completely. Furthermore, the report states that China is slowing clearances for Taiwanese companies, which does not automatically mean it is slowing down clearances for companies based in other countries. Of course, increasing the lead times for Taiwan-based companies can impact multiple optical initiatives, though the actual effect remains to be seen.

Quartz

China produces large volumes of silica sands and quartz sands for glass, construction, fiber optics, semiconductors, and other industrial uses. Quartz (SiO₂) is used very widely in the semiconductor industry both as a component of chipmaking tools and as the base for silicon wafers. Meanwhile, the Nikkei report does not give enough technical specifications of SiO₂ to determine which applications the restrictions target.

It should be noted that semiconductor wafers require high-purity quartz with no impurities (≥99.99% SiO2), and China is not the leading producer of HPQ, so it can hardly use its exports as leverage. This potentially brings us back to the optical connectivity market.

High-purity fused silica (SiO₂), produced from quartz or synthetic silica feedstocks, is the primary glass material used to make most optical fibers as it combines very low optical loss at telecom wavelengths with excellent thermal and mechanical stability as well as chemical resistance. Both the fiber core and cladding are typically silica-based, but their refractive indices are deliberately made slightly different to keep light confined inside the core. A common approach is to dope the SiO₂ core with germanium dioxide (GeO₂) to raise its refractive index, while the surrounding cladding remains mostly SiO₂ with a lower refractive index.

Meanwhile, optical fiber is commonly produced from synthetic ultra-high-purity silica, not from natural crystalline quartz. Manufacturers typically create the fiber preform by chemical vapor deposition using precursors such as SiCl₄, which is oxidized to form extremely pure SiO₂. Then, dopants like GeO₂ can be used to modify the core's refractive index.

That said, China's quartz restrictions can disrupt parts of the optical-component supply chain, but the Nikkei report does not demonstrate that they threaten optical fiber production itself. In fact, germanium/GeO₂ restrictions could be a more direct concern for Ge-doped fiber cores than quartz in general.

Neodymium

While China holds a dominant share of the neodymium production, it does not export control the rare earth material itself, as its real leverage is in processing and refining. NdFeB (neodymium-iron-boron) permanent magnets are used in a wide range of applications, but high-performance grades for aerospace and robotics often contain terbium or dysprosium to increase coercivity and maintain their magnetic properties at high temperatures. China's export controls do not limit neodymium itself or permanent magnets, but NdFeB permanent magnets or magnetic powders containing terbium or dysprosium.

While permanent magnets can be used in HDDs as well as various pumps or motors used in data centers, these applications do not need permanent magnets containing terbium or dysprosium, so it doesn't seem this regulation has anything to do with AI data centers. Yet, it has a lot to do with emerging applications in the aerospace and robotics realms, so slowing down rivals helps China to establish or maintain its lead, as finding cost-effective alternatives to Chinese permanent magnets is not an easy task. Then again, the report only covers companies from Taiwan, and we have no idea how it impacts companies based elsewhere.

A potential play for leverage

Rather than imposing a blanket ban, Beijing appears to be using its dual-use export-control regime to selectively delay shipments based on materials, customers, and end uses to gain leverage over strategically important industries. The biggest potential impact could be on optical connectivity, where China's dominance in germanium supply gives it influence over both silicon-photonics photodetectors and Ge-doped optical fiber.

However, while the effect of the curbs on Taiwanese industries may be significant, what remains unclear is the impact of China's restrictions on the global market.

A Russian Molniya drone carrying an Nvidia Jetson Orin module crashed and killed three civilians at a gas station in Zaporizhzhia last month after choosing its final target without a human pilot, according to a New York Times investigation that cites Ukrainian air defense commanders, drone experts, and the forensic team that examined the wreckage.

Kateryna Bondar, a senior fellow at the Center for Strategic and International Studies, told the paper it's the first documented case of civilian deaths caused by a Russian drone using fully autonomous targeting. The dead were Tetiana Bubynets, a 19-year-old accounting student, and two men aged 41 and 48.

Human operators launched the drone toward the gas station, per the report, but the final aim point was selected onboard by software trained to recognize objects such as propane tanks. The aircraft failed to clear an apartment building on its approach, struck a wall, and detonated near people sheltering below, rather than striking its chosen target.

The strike drone flew in a group of roughly half a dozen aircraft, none of which emitted radio traffic, Ukrainian air defense officials said. Modules recovered from this attack and from intact test drones carried no encryption, so investigators could examine both the terrain imagery loaded for visual navigation and the code specifying which object classes the drone had been trained to attack. "Machines are making decisions to strike," Col. Serhiy Minaiev, Zaporizhzhia's air defense commander, told the NYT. Russia is understood to have begun AI-guided test flights of the mass-produced, fixed-wing Molniya in May, after months of self-targeting trials with the V2U.

Nvidia confirmed to the New York Times that modules photographed in the recovered drones were Jetson Orin minicomputers, hardware that sells for a few hundred dollars. "Our Jetson Orin modules are consumer-grade products sold to students, developers, and startups for a wide range of beneficial applications," an Nvidia spokesperson told Tom's Hardware. "They are not available in Russia and are not designed for military purposes. Pre-owned Jetsons are available through many reseller channels. Although we cannot track products after they are sold, if we determine that any customer is violating U.S. export controls, we will take appropriate action."

Ukrainian investigators have now linked the Jetson Orin to four Russian weapon families. A teardown by Ukraine's GUR intelligence agency last June found one seated on a Chinese Leetop A603 carrier board inside the V2U loitering munition, in combat use since February 2025. Weeks later, a Ukrainian general said the module powered object recognition in the upgraded Shahed MS001, and earlier this month Ukraine reported the same silicon in the S-71M Monochrome cruise missile. Data-center AI accelerators fall under U.S. export controls; edge modules like the Jetson Orin, with variants starting at $249, don't.

Mykhailo Fedorov, Ukraine's recently ousted defense minister, told the NYT that Kyiv tested its own fully autonomous system against fuel storage and military equipment in occupied Crimea in recent months, and Ukrainian quadcopters killed Russian soldiers in autonomous mode as far back as 2024. In Zaporizhzhia, defenses now include roughly 240 miles of anti-drone netting and plastic sheeting propped at odd angles around propane tanks to throw off image recognition.

Asus has finally opened pre-orders for the ROG Xbox Ally X20, an upgraded version of its flagship handheld with an OLED screen and transforming D-Pad. On its own, the system will sell for $1,299.99, while a bundle with the ROG Xreal R1 Edition 20 AR glasses, a dbrand Killswitch case, and a custom Pelican case will cost $2,499.99. The device will be available on October 15 at the Asus Store at Best Buy.

See the Asus ROG Xbox Ally X20 at Asus

See the Asus ROG Xbox Ally X20 at Best Buy

Initially, Asus had only announced the bundle, but later turned around and said a standalone version of its new take on the best handheld gaming PC. Given that this version of the Ally has an OLED screen (one of the biggest drawbacks of the original), it didn't make much sense to force a pair of AR glasses when so many people would want to look at the built-in display.

The original ROG Xbox Ally X, which, released in the fall of 2025, still costs $999.99. This new version, with a translucent shell, the OLED screen, transforming d-pad (from 4-way to 8-way), TMR joysticks, and rubberized grips, will come with a $300 premium before you add the bundle. What isn't changing is the internals: the X20 will still come with an AMD Ryzen AI Z2 Extreme processor.

The dbrand Killswitch in the bundle blocks much of the clear plastic, but has black and gold accents, as well as a built-in kickstand. The Killswitch also includes a skin that shows what's inside the Ally, but given that the black plastic is seethrough, it seems somewhat redundant.

The Pelican case is exactly what you would expect: a black box with red latches. There is a black-and-gold ROG 20th Anniversary logo, but all things considered, this is the most restrained item in the entire anniversary lineup. While I appreciate a case for the device, this is pretty heavy-duty.

The ROG Xreal R1 glasses appear to be functionally identical to the version we reviewed earlier this year, but with black and gold accents.

The ROG Xbox All X20 was originally announced at Computex, along with a suite of twentieth anniversary ROG computer components that cost as much as $15,000 in one PC build. Beyond components and the handheld, there is also a twentieth anniversary monitor, keyboard, mouse, router, and NUC mini PC.

The development of Linux, a free ‘hobby’ operating system, was announced by Linus Torvalds 35 years ago today. On August 25, 1991, the unknown computer science student noted that the budding OS had been “brewing since April, and is starting to get ready.” The first public release of this ‘Minix-like’ OS came the following month, and in a last-minute change by the co-worker who uploaded it, was distributed with the name Linux instead of Freax. In 2026, Linux powers everything from smartphones to supercomputers and oodles of products, like the Steam Deck, in between.

The above commemorative post celebrates Torvalds’ stewardship over the Linux project. However, it is also quick to make clear that “hundreds of maintainers and thousands of contributors” have been instrumental to making this free open source OS a competitive, capable alternative to corporate/paid software, which can “move computing forward for humanity.”

Since 1991, Linux has come a long way on its journey from its humble ‘hobby’ OS beginnings. What started as a kernel with roughly 10,000 lines of code has exploded into 40 million or more lines today. Torvalds was humble about the first release yet proud of features like its multi-threaded filesystem, and the first release being clear of any borrowed Minix code. But the countless contributors over the last 35 years have helped forge an enviable OS, which boasts capabilities and features that must make it a worrying foe for commercial rivals.

There are areas, outside our PC and gaming core, where Linux is actually the biggest fish by far. Industry stats suggest that nearly 80% of web servers, and virtually all of the world’s Top500 supercomputers run a flavor of Linux. It dominates mobile too, with nearly 4 billion Android devices running Linux-derived kernels. Then there are all those embedded systems, encompassing things such as routers to automotive MCUs – so many run Linux.

I feel that Linux has made significant progress towards the fabled ‘year of Linux’ over the last couple of years. Microsoft’s Windows has been its own worst enemy in some respects, pushing people away due to a multitude of concerns. Meanwhile, consumers can see that content creation, productivity, and gaming on Linux PCs are continuously improving.

There was a recent collective sigh of relief in the Linux world, too. Earlier today, we reported on news that the decades-long Linux ownership dispute was effectively killed after Xinuos’ appeal was rejected by the U.S. Court of Appeals. That ruling means much lingering uncertainty over Linux devices facing future licensing claims, maker settlements, audits, and/or forced software rewrites has been banished.

Raghu Sreeramaneni, Micron HBM Design Architecture Fellow, told the Hot Chips 2026 conference on August 23 that the silicon penalty HBM carries against DDR5 is growing with every generation, and that it can’t be closed without giving up performance, something that Micron won’t do. Pressed on whether newer parts narrow the gap, he said it’s "definitely not getting better," putting the current overhead at roughly three times the wafer area of DDR5 for the same capacity. That trajectory is the reason why PC memory hit record prices this year, with conventional DRAM contract prices up 90% to 95% quarter over quarter in the first quarter of 2026.

Wafer mathematics

An HBM4 die fits 256 banks against 32 on a DDR5 die, and it reaches its bandwidth by running those banks in parallel, which requires far more die area for data paths, power delivery, and the through-silicon vias (TSVs) that link each layer to the base die. A single HBM3E die can feed 256 GB/s, while one DDR5 die supplies about 8 GB/s, so matching a given bit count makes the HBM die much larger.

Micron has publicly put that overhead at about three times the wafer area of DDR5, and Sreeramaneni said it traces to an HBM3E-against-DDR5 comparison that grows with each generation as pin speeds, bank counts, stack heights, and die sizes climb higher. He called HBM "probably the most cross-functionally complex solution that we make," and noted that in a two-GPU package, memory accounts for around 90% of the silicon, roughly eight times the area of the GPU dies. HBM already sells for about five times the price of DDR5 per bit, so each wafer a maker moves to it removes a disproportionate share of commodity memory from the market, pushing consumer product prices higher as a consequence.

Conventional DRAM contract prices rose 90% to 95% quarter over quarter in the first quarter of 2026 and a further 58% to 63% in the second. To put that into perspective, a mainstream 32GB DDR5-6000 kit sold for around $392 this month, up from $110 to $140 a year earlier, and 128GB of DDR5 passed $3,399, a 500% rise over 12 months, with European prices up 345% since September last year. Back in February, HP told investors that DRAM now makes up 35% of its PC build cost, up from 15% to 18% a quarter earlier, and Gartner expects PC shipments to fall more than 10% in 2026. While it’s true that the surge eased to 13% to 18% in the third quarter, that happened because consumer electronics makers reached the ceiling of what they could pass on, not because supply improved.

Bandwidth, stacking, and heat

Micron's presentation put compute performance scaling at roughly three times every two years and HBM bandwidth at under two times, a divergence Sreeramaneni summarized by saying "the memory wall is still present, and, in fact, maybe getting worse." HBM4 doubles the host interface to 2,048 I/Os, and Micron's parts run above 11 Gb/s per pin for more than 2.8 TB/s per stack, beyond the 8 Gb/s and 2 TB/s baseline in JEDEC's HBM4 standard.

Each of those gains comes from more parallelism, which enlarges the die again and widens the silicon ratio. Sreeramaneni said there is "a good path to 16 layers of DRAM," but "after 16, there's still a lot of work to be done." Meanwhile, SK hynix used its own Hot Chips talk to describe a 775-micron total-thickness ceiling that caps stacking until the industry adopts hybrid bonding, which SK hynix doesn't expect before HBM5. Micron's HBM4E, due around 2027, moves the logic base die to a TSMC foundry process, part of a wider shift toward customization as AI workloads fragment, which Sreeramaneni described by saying "disaggregation is the buzzword now."

The base die runs hottest because it sits at the bottom of the stack, doing the highest-speed interface work while the heatsink sits at the top. Every layer added between the base and the heatsink then raises thermal resistance. Sreeramaneni said Micron is now "architecting solutions around thermals rather than the other way around," a reversal from a few years ago. Micron highlighted how Meta's Llama 3 paper attributed 17.2% of unexpected interruptions during a 54-day run across 16,384 H100 GPUs to HBM3 memory, the second-largest cause behind failed GPUs, a reliability burden that scales with the amount of HBM in each package.

Share and supply outlook

SK hynix leads the HBM market with a share that Counterpoint Research places at around 58%, down from a high of around 69%, and Micron overtook Samsung for second place last year. Micron began volume shipments of 36GB 12-high HBM4 earlier this year for Nvidia's Vera Rubin platform, with Nvidia CEO Jensen Huang saying in June that all three suppliers are qualified and in production.

Analysts expect DDR5 per-wafer profitability to overtake HBM3E by the end of this year, leaving the three makers little reason to add commodity capacity when server DRAM pays nearly as well per wafer. SK hynix said last October that it had already sold its entire 2026 output, while Apacer's chief executive told investors that supply to independent module makers could fall to 30% of 2026 volumes next year. SK hynix CEO Kwak Noh-jung has called 2027 the worst year for memory supply in the industry's history, with demand outrunning production into 2030.

In response, Nvidia has raised its DGX Spark desktop from $3,999 to $4,699 and warned large customers of AI server price rises above 15%, both tied to memory. Realistically, the squeeze will loosen only under three conditions, none of them likely before new fab capacity comes online and scales up: China's CXMT ramping competitive DDR5 in volume, hybrid bonding arriving before HBM5, which SK hynix has already all but ruled out, or DDR5 profitability slipping back below HBM.

Full Micron Hot Chips 2026 presentation

Nvidia has spent the last several months providing key disclosures about its next-gen Vera CPU for agentic data centers, which it continued at Hot Chips 2026. Although we've already learned a lot about Vera, how it compares to AMD's next-gen Venice CPUs, and the inner workings of the Olympus core, Nvidia provided a bit more color at Hot Chips on spatial multithreading, the memory subsystem, and what types of workloads it's targeting with Vera.

As a quick refresher, Vera is the first CPU with a custom Nvidia core, following up on Grace, which used a stock Arm design. It's shipping as a single, 88-core SKU, and it has some key design differences compared to Nvidia's x86 competition, most notably a multi-threading implementation that Nvidia calls spatial multi-threading, an LPDDR5X memory subsystem, and a monolithic compute die rather than using compute chiplets.

Nvidia says it's designed Vera specifically for agentic AI workloads, a category that's still being defined in terms of performance benchmarking. Many CPU-intensive tasks serve as proxies for agentic workloads (i.e., code compilation), though measuring performance across a full agentic chain is complex and inconsistent. Nvidia, in its own slides (see the end of this article), calls agentic AI the "most complex computing workload in history," after all.

Nvidia provided an example of a headless browser to show the benefits of Vera, using optimized code to mimic how an agent would use a browser. Compared to the 96-core EPYC 9655P, Nvidia says Vera runs 24% faster as browser instances scale.

This slide is a good demonstration of the complexities in measuring traditional workloads and applying that performance to agentic workflows. Agents will often fetch websites for information, but there are several layers where agents can trim back compared to humans; in this case, agents can run through a browsing workflow 4.5x faster by cutting things like GUI rendering, fonts, media decoding, and more.

Another touchstone for agentic performance is code compilation, as agents seek out software to compile on the system. This might be the most direct benchmark of agentic AI performance with current workflows right now. Though, as previously mentioned, agentic chains are long, complex, and involve several different workloads.

Once again, compared to the 96-core EPYC 9655P, Nvidia claims Vera can compile the Linux kernel 22% faster with a native AArch64 target, and 14% faster when cross-compiling for x86.

Nvidia's big cores for agentic AI — another look at Olympus and how it fits into Vera

Nvidia reiterated the importance of the large cores inside Vera, including the large BPU, neural branch predictor, and 10-wide decode. Nvidia has previously disclosed the Olympus core architecture, which you can read about in our Vera deep dive. Broadly speaking, however, it's a wide core optimized for high single-core throughput.

One of the more interesting design points of Vera is spatial multi-threading, which Nvidia described in more detail during its Hot Chips 2026. In short, Nvidia separates core resources on two pipelines, though data and cache can move between threads as needed. To demonstrate the benefit, Nvidia shared the results from SPEC CPU 2017 intrate that you can see below.

This shows the "noisy neighbor" effect. Nvidia measured single-core performance and then measured the same workload with another thread active. Nvidia's data shows that Vera is less concerned with the neighboring thread, whereas a "traditional CPU" sees a larger slowdown. Nvidia didn't clarify which CPU it's comparing Vera to here, however.

Nvidia's slide does a good job illustrating, but it's worth noting the difference compared to traditional SMT nonetheless. With traditional SMT, resources are time-sliced between threads, leading to gaps between BP and decode, as illustrated in the slide. With spatial multithreading in Vera, threads are still fighting for resources within the core. However, spatial multithreading allows Nvidia to deal with the demand of neighboring threads in a deterministic way, leading to a more consistent downturn in per-core performance when the second thread is working.

Nvidia's second-gen Scalable Coherency Fabric (SCF) moves data across the die. Nvidia didn't provide any new disclosures around SCF at Hot Chips, but you can see how the fabric is laid out in the slide below. Centralized Coherency Switch Nodes (CSNs) connect the cores to pools of L3 cache totaling 164 MB and the broader memory subsystem.

At a system level, one of the more interesting choices Nvidia made was to use LPDDR5X as opposed to traditional RDIMMs, a choice that it was only able to make due to the serviceable SOCAMM2 design. Nvidia includes eight SOCAMM2 slots per Vera CPU on a board, offering up to 1.5 TB of capacity with 1.2 TB/s of bandwidth.

LPDDR5X can deliver transfer rates higher than DDR5 RDIMMs, at least compared to single-rank DIMMs. However, it seems the driving force behind LPDDR5X wasn't performance but rather power consumption. One of the pillars of Vera, according to Nvidia's Hot Chips presentation, was to deliver a CPU for power-limited data centers. Micron says its LPDDR5X consumes about a third of the power compared to a traditional RDIMM.

Nvidia demonstrated that point a little differently, using bandwidth per watt as a point of comparison between the LPDDR5X system in Vera and traditional RDIMMs. This illustration does the job, though it could be a bit misleading, measuring power draw against peak bandwidth.

Nvidia tells us that a fully loaded memory system with Vera consumes between 30W and 40W, with 1.5 TB at 9600 MT/s. Power demands for RDIMMs vary wildly depending on capacity, channels, and transfer rate, though power consumption can easily climb over 100W depending on the configuration.

Although Nvidia has deployed Grace in the data center — to the tune of "hundreds of thousands" of standalone servers, apparently — Vera represents Nvidia's first big push to gobble up market share in the expanding agentic CPU market. It's highly targeted, as evidenced by the fact that Nvidia is only delivering a single 88-core SKU, and it's already being put to use in large-scale deployments, with Nvidia announcing yesterday a deployment of Vera at SpaceXAI.

Nvidia has shared the slide above before, which it once again showed at Hot Chips 2026. It's normalizing per-core performance in SPEC CPU 2026 against the AMD EPYC 9755. The core differences explain the big disparity in numbers; in reality, Vera led in overall score by 3%. Regardless, this is the slide Nvidia is using to pitch Vera, claiming it offers a big improvement in the workloads that are most relevant for agentic AI.

The most formidable opponent for Vera isn't Turin, however. It's Venice, which AMD launched in June, and Diamond Rapids, which Intel detailed just moments after Nvidia left the stage. Vera has a lot of interesting talking points already, but it'll be interesting to watch how Nvidia scales (or doesn't scale) its data center CPU business over the next few generations. Perhaps we'll see the firm double down on these agentic workflows, or maybe concessions and product segmentation to appeal to hyperscalers. Time will tell.

Full Nvidia Vera Hot Chips 2026 presentation

If you've been shopping for storage, then you're more than well aware of the incredible prices of SSD and HDD storage options. Gone are the days of super-cheap drives, and welcome to the current economic climate where we try to eke out as many savings as possible on the expensive, yet essential hardware that we rely on for our work and hobbies. On sale at its lowest price since April of this year, you can head to Best Buy and grab an 8TB Seagate Barracuda HDD for $249.99, a saving of $30 on the $279.99 list price.

● Check out this deal at Best Buy

At this price, the drive works out to cost $31.24 per TeraByte. Yes, this is a crazy high price compared to several years ago, but that's not the current reality in which we reside. In today's storage market, it's actually a fair price per TeraByte compared to the competition. We have reviewed the 8TB Seagate Barracuda, so if you'd like to see more information on this HDD to help you in your shopping journey, then please check out our review.

The 8TB Seagate Barracuda isn't the fastest HDD out there. It's designed to be lower in price rather than offer astonishing performance; however, it's perfectly adequate in most situations as long as you're not looking for breakneck speeds. In our PCMark 10 benchmarking test, we use a wide-ranging set of real-world traces from popular applications and everyday tasks to measure the performance of our tested drives. You can see in our tables below that it isn't the fastest drive, but it does beat out some of the competition.

The Seagate Barracuda comes in a standard 3.5-inch metal chassis and is an SMR (shingled magnetic recording) drive with a 256MB cache and 5,400 RPM disk spin speed. A SATA 6Gb/s interface delivers the fastest transfer speeds available for HDDs and makes plug-and-play exceptionally easy.

If you're looking for a disk drive for use in a home server setup or media center, and want something on the cheaper side (cheaper for the current climate) then the Seagate Barracuda range is a one of the main choices available on the HDD market, however, being an SMR drive there are some drawbacks in certain operations, and Seagate only offer a shorter 2-year limited warranty with this HDD.

An AI computing enthusiast has demonstrated Doom running on a custom CPU designed by GPT-5.6 Sol. Angel (@Angaisb_) shared a technical and visual feast with a video of classic Doom running within a pulsing schematic of the CPU, in the sandbox provided by the Turing Complete game environment. Clearly, this shows that GPT-5.6 Sol is capable of constructing a virtual computer system from the basics, and one that is accurate enough to boot and play a port of the original Doom. The model dubbed its CPU design ‘Codex-R32.’

Angel knows Doom is a hugely popular demo to show computing capabilities, despite it being quite a vintage nowadays (1993). So they must have thought it a good idea to show how far agentic coding has come with this tried and trusted ‘people asked for Doom’ metric. They were impressed by the results, concluding that it is “truly insane that we can do stuff like this.”

Despite the accomplishment, another rule of the internet is that there’s always someone who thinks you haven’t pushed far enough. So there were the inevitable remarks about having a shot at Crysis next. Likely grasping for a witty comeback, Angel asked their AI to whip up a response to the unsolicited stretch goal. It didn’t disappoint, suggesting they answer “Absolutely – I just need to build a GPU, add a few gigabytes of RAM, and make a schematic visible from orbit first.”

Indeed, Doom is a relative minnow compared to Crysis, though it still stretches the model and its performance in the sandbox is not what anyone would call playable. “The CPU is built from primitive logic components inside Turing Complete,” the Codex told Angel. “Doom uses the C-based PureDOOM port, compiled into native RV32IM machine code that runs directly on the custom Codex‑R32 CPU.”

Watching the video, you can see the live schematic of the custom CPU with a pulsing visualization of processor gates, registers, memory, ALUs, and other blocks within the Turing Complete computer-science education and puzzle game’s anything-goes sandbox mode. Live stats show the cycle counter, sim speed, memory/register values, and more.

Overall, with this demo, we have a neat visual demo of LLMs not just creating software, but also reinventing hardware at a capable enough level to pass the 'can it run Doom' test.