Jensen Huang joined X last month and used his first post Friday to promote Open Weights and American AI Leadership, a three-page policy letter published the same day and co-signed by 25 companies, including Nvidia, Microsoft, Meta, IBM, Dell Technologies, Palantir, and Hugging Face.

The letter asks Washington to avoid what it calls "premature restrictions on downloadable AI models," and comes just four days after the Trump administration was reported to be reviving a push to ban Chinese models — though the document doesn't directly mention China, Moonshot AI, or DeepSeek. Notably missing from the co-signers are OpenAI, Anthropic, and Google.

The 25 names break down into chipmakers, server vendors, cloud operators, enterprise software firms, security companies, and venture funds: Nvidia, Dell, Microsoft, IBM, Box, ServiceNow, CrowdStrike, Palantir, Telnyx, Replit, Perplexity, Andreessen Horowitz, Y Combinator, and Emergence Capital among them. The model developers on the list, Meta, Mistral, Black Forest Labs, Arcee AI, and Reflection, all publish weights already.

Also present on the list of signatories is the Linux Foundation, which stewards the OpenMDW-1.1 license Nvidia used to release Nemotron 3 Ultra in June, a 550-billion-parameter model that Artificial Analysis scored at 47.7 on its intelligence index against 53.9 for Moonshot's Kimi K2.6.

"The world needs both frontier closed models and frontier open models," Huang wrote in his X post. At Nvidia's CES 2026 press Q&A earlier this year, he put a figure on the shift, saying one in every four tokens generated today comes from an open model. Weights that anyone can download get served from enterprise clusters, regional clouds, and on-premises racks rather than a handful of hyperscaler API endpoints, and those buyers have no in-house TPU or Trainium program to buy instead. The letter's policy section asks for expanded compute access for startups and researchers, alongside public investment in shared datasets and evaluation frameworks.

The letter goes on to urge policymakers not to treat distillation — the practice of training one model on another's outputs — as misappropriation, arguing that unlawful extraction from closed models should be handled through targeted legal frameworks, rather than broad limits on the technique.

Treasury Secretary Scott Bessent said on Fox Business earlier this week that the administration would examine Chinese open-source models for intellectual property theft and could sanction the companies behind them, telling the program that officials had found watermarks from U.S. large language models in Chinese systems. Huang told Axios two days later that American firms should be allowed to use Chinese models, calling claims of Chinese backdoors a misconception. The distillation passage is the only part of the letter that doesn't concern open weights.

Intel on Thursday published its financial results for the second quarter of 2026, posting revenue of $16.1 billion — a 25% rise year-over-year — amid high demand for client and data center products. The company also said that due to extraordinary demand for its own CPUs, it will initiate mass production using its 14A (1.4nm-class) fabrication technology in 2028, which is in line with TSMC's plans for its A14 process technology.

"With encouraging external customer progress and increased demand for our internal products, we remain on track for 14A risk production for our internal products in the second half of 2027, and we made the decision in Q2 to fully commit to high volume ramp in 2028," said Lip-Bu Tan, chief executive of Intel, during the company's earnings call with financial analysts and investors.

Typically, companies initiate high-volume manufacturing (HVM) using a new process technology about a year after initiating risk production. Assuming that Intel intends to start risk production using 14A in the second half of 2027, it is reasonable to expect the company to start 14A HVM in the second half of 2028. It remains to be seen whether by the 'second half' Intel means July or December. If Intel initiates high volume ramp in November or December 2028, actual products made using the technology will emerge in 2029. In any case, Intel typically begins manufacturing using its leading-edge nodes in its development fab in Oregon and while it formally calls it HVM, actual volumes produced at such fabs are relatively low.

Another thing to note about Intel's 14A is that in 2028 it will start making its own products using this process, not products from external customers. Apparently, Intel still does not have any external clients that have committed to use the technology to make their products.

TSMC typically initiates production using its latest nodes in December and usually calls it the 'second half of the year.' Assuming that it follows the same pattern with A14 (though the progress of the node can enable the company to pull mass production in provided that customers' designs are ready), then the volume ramp will occur in 2029. TSMC claims that multiple customers have already taped out their ICs on A14.

Intel reported a strong second quarter as its revenue reached $16.1 billion, up 25% year-over-year and $1.8 billion above the midpoint of its guidance. Formally, Intel's GAAP losses reached a whopping $11 billion. However, this was driven by the $13.619 billion of mark-to-market losses on Escrowed Shares related to Intel's CHIPS Act Secure Enclave agreement with the U.S. government. Meanwhile, the company's non-GAAP net income was $2.2 billion, which reflects profitable underlying operations. The company's GAAP gross margin increased to 40.1%, up from 27.5% in Q2 2025. Intel's Operating cash flow totaled $7.0 billion, prompting the company to raise its capital spending outlook for both 2026 and 2027 as AI-driven demand continues to exceed available supply.

Intel's Client Computing and Physical AI Group (CCPG) generated $8.9 billion in revenue, up 13% year-over-year. The company confirmed that the CCPG result was not driven by increased unit sales, but was a result of higher average selling prices (ASP) due to supply constraints.

"Client obviously exceeded expectations. I would say it was largely ASP, of which some of that was mix related, some of that was our own like-for-like changes in ASPs where we thought we had seen some inflation on our cost and needed to pass that on to the end customer," said David Zinsner, chief financial officer of Intel, during the call.

The Data Center and AI (DCAI) business delivered the strongest growth as its sales climbed 59% year-over-year to $6.3 billion amid surging demand for Xeon processors, expanding AI infrastructure deployments, and rapidly growing purpose-built silicon sales.

"Q2 year-over-year server growth was the strongest on record, Xeon 6 continue to be one of the fastest ramping products in Intel history, reflecting improving execution and strong customer demand," Tan said.

"We also continue to see strong momentum in our purpose-built silicon product line, with revenue up roughly 20% sequentially and nearly tripling year-over-year," Zinsner said. "Purpose-built silicon revenue nearly tripled year-over-year."

Intel Foundry posted $5.8 billion in revenue, an increase of 31% year-over-year, as Intel 18A production ramped. At the same time the production units losses dropped to $2.1 billion — down from $2.4 billion in the previous quarter and $3.2 billion in the same quarter a year ago. External foundry revenue reached $293 million.

"Intel Foundry operating loss in Q2 was $2.1 billion and $348 million better quarter-over-quarter as higher yields improved cycle times and increased factory scale across Intel 4, Intel 3, and 18A drove improved wafer costs," Zinsner said.

Intel guided its third-quarter revenue to $15.8 billion – $16.8 billion and a projected non-GAAP gross margin of 42% and an EPS of $0.38.

A new 3D V-Cache-equipped CPU is reportedly in the works and could arrive as a mobile counterpart to the Ryzen 7 9800X3D. According to prominent tech industry insider Golden Pig Upgrade Pack on Weibo, the Ryzen 9 9800HX3D is expected to enter mass production in Q4 2026, with a potential launch at CES 2027. The chip is rumored to feature an 8-core, 16-thread configuration with boost clock speeds of up to 5.1 GHz, and 96MB of L3 cache.

It is also claimed that the processor was previously rumored to launch as the Ryzen 7 9755HX3D; however, it seems that the company might settle on the 9800HX3D. This essentially brings the branding in line with the desktop Ryzen 7 9800X3D. The chip could follow the same cache configuration with an eight-core CCD with 32MB of native L3 cache and a 64MB 3D V-cache stack.

Currently, AMD's most powerful 3D V-Cache-equipped mobile processor is the Ryzen 9 9955HX3D, featuring 16 cores, 32 threads, and a maximum boost clock of 5.4 GHz. It also offers a substantially higher L3 cache at 128MB and a configurable TDP of 55-75W.

While AMD hasn’t confirmed any details, the Ryzen 7 9800HX3D could likely be featured on premium gaming laptops that don't require the additional cores of the flagship 9955HX3D. An 8-core Zen 5 processor paired with 3D V-Cache could strike a better balance between gaming performance, power consumption, and overall system cost.

The rumored processor also aligns with AMD's recent approach of refreshing its X3D lineup instead of introducing new gaming CPUs. Similar to the recently announced Ryzen 9 9950X3D2 and the reintroduction of the 5800X3D, the 9800HX3D appears to build on an existing design while bringing AMD's latest branding and gaming-focused cache technology to another product tier.

The introduction of the 9800HX3D would also give laptop manufacturers a new gaming-focused option that is positioned below the flagship 9955HX3D. The processor would likely attract consumers seeking desktop-class gaming performance without paying the premium typically associated with 16-core mobile CPUs. As always, the rumored specifications and launch timeline should be treated with caution until AMD makes an official announcement.

You're probably already well aware of the three largest memory vendors: South Korea's SK hynix and Samsung, and the United States' Micron. There's a fourth player up and coming in the market, though, and that's China's ChangXin Memory Technologies, more commonly known as CXMT. CXMT is pumping out RAM as fast as it can to soften the effects of the RAMpocalypse on domestic (to China) consumers, and it's also expanding capacity quickly. Given these factors and the size of the Chinese market, it should come as no surprise that motherboard vendors, including Gigabyte, are advertising fresh support for the chip.

MSI appears to have been the first major motherboard vendor to publicly promote BIOS optimizations specifically for CXMT DDR5 memory, initially through China-market BIOS releases and later with global announcements. What Gigabyte is saying is a little different: not only is CXMT RAM supported on Gigabyte motherboards for both AMD's Socket AM5 and Intel's LGA 1851, but it's supported at impressive speeds of up to 8200 MT/s on select boards.

As proof, Gigabyte offers up a CPU-Z screenshot showing a pair of 16GB Lexar modules equipped with CXMT chips achieving a speed of 8200 MT/s with a CAS latency of just 40 cycles on one of its B850M FORCE motherboards. We have to remark that Gigabyte doesn't show the voltage required to hit these speeds, likely for good reason, but the firm did it without disabling the chip's integrated graphics. That doesn't prevent the chips from posting an excellent AIDA64 latency of just 65.4 nanoseconds on the monolithic Ryzen 5 8600G used for the test. For context, typical EXPO kits usually run around 80ns, JEDEC timings are more like 100ns, and LPDDR-based systems rarely come below 110-120ns.

As Gigabyte says, "CXSH (CXMT) chip-based memory offers a welcome additional source of supply for consumers." (CXSH is the JEDEC manufacturer ID code for CXMT) Gigabyte specifically notes that it is modules with 16-gigabit and 24-gigabit ICs that are supported; that means 16GB and 24GB single-rank modules, or 32GB and 48GB dual-rank modules.

While CXMT memory is certainly a welcome additional source of supply, it's also not really clear how much of that memory is actually making its way outside of China, particularly to the US and Europe. CXMT isn't on the US Commerce Department's "Entity List" yet, so the firm's parts aren't actually banned, but the company is once again considered a Chinese military company by the Department of Defense after being briefly removed from the 1260H list in February. Lawmakers here in the states, likely laden with donations from the big three memory firms, want to see CXMT banned, while US tech companies like Corsair, HP, and Dell are already integrating ChangXin RAM into their products, and Apple wants in, too.

The reality is that, as a DIY builder, you are fairly unlikely to know or care if your memory is manufactured by CXMT. You don't usually buy RAM directly from SK hynix, Samsung, or Micron (certainly not since Micron unceremoniously executed Crucial); you buy your RAM from Silicon Power, G.SKILL, Patriot, Corsair, or one of the many other vendors who assemble DIMMs. If the RAM runs at its rated specifications, there's not a lot of reason for the individual consumer to care where it came from. It's nice to hear that the new chips are officially supported by familiar mainboards, though.

Samsung and SK Hynix, South Korean memory giants, are set to announce major deals involving “very large sums” with leading U.S. tech companies, according to a July 24 Bloomberg report, citing comments from the country's presidential policy chief Kim Yong-beom. According to the report, Kim did not disclose the financial details of the deal but said the announcements would likely cover strategic partnerships, memorandums of understanding, and long-term supply deals on memory chips.

The deals are set to be announced during South Korean President Lee Jae Myung’s visit to Silicon Valley for the high-profile San Francisco AI submit — beginning today, Friday July 24 — which is bringing together industry leaders, such as Samsung Chief Lee Jae-yong, SK groups chairman Chey Tae-won, Nvidia CEO Jensen Huang, as well as the CEOs of Open AI, Anthropic, and Broadcom among others.

South Korea announced an $880 billion investment plan last month — backed by SK Hynix, Naver, and Samsung — aimed at strengthening the country's AI leadership through aggressive chip production expansions, data center buildouts, and physical AI. Kim said the South Korean President’s visit and involvement in the summit will serve as a catalyst to seal several long-running negotiations between the country's top tech entities and their U.S. counterparts, while also turning a significant portion of last month's planned investment into concrete projects.

The president is set to hold separate meetings with Huang, OpenAI's Sam Altman, Anthropic’s Dario Amodei and Broadcom Inc.'s Hock Tan, all U.S. companies. The U.S. has also urged Samsung and SK Hynix to expand their chip production in the country, but Kim stated that there had been no formal requests from Washington. According to Kim, much of South Korea's domestic expansion is driven by strong demand from U.S. companies, which accounted for 80% – 90% of underlying orders.

Although the industry has largely learned to move out of the way when the big green giant that is Nvidia steps into the room, one AMD executive said he was “very happy” to see Nvidia publish SPEC CPU 2026 benchmarks for its Vera CPU ahead of the Advancing AI 2026 event. AMD used the configuration in Nvidia’s white paper as a basis to run SPEC on its new Zen 6 ‘Venice’ CPUs, offering what it calls an “apples-to-apples” comparison between the two chips.

“We are very happy that Nvidia published their Vera performance [numbers],” said AMD’s Ravi Kuppuswany, corporate VP of compute and enterprise solutions. “We were actually being a little conservative. I actually thought we were beating them by smaller numbers than what I have here… we thought we’d have at least a 10% advantage. What we’re finding is… we have 20% advantage, and we have not even finished completely tuning.”

Kuppuswany’s comments overlaid the slide you can see above, claiming 2.2x higher throughput with Venice compared to Vera, and 1.2x faster per-core performance. AMD has certainly stacked the deck in its favor here (as did Nvidia when it first published its Vera results), so let’s go through what this chart actually says.

As a quick aside, you’ll see “estimated” in the images above and below. These numbers aren’t guesses (they’re based on real runs), but SPEC maintains strict reporting guidelines for “official” runs. And because these runs aren’t reported to SPEC and therefore haven’t gained official status, they must come with the “estimated” disclaimer.

The throughput number is the easiest one to clarify. AMD compared its 256-core, 600W Epyc 9996 against the 88-core Vera, both in a 2P configuration. Yes, the CPU with more than twice the number of threads and an extra 150W stacked on top of its TDP has significantly higher throughput, as it should.

AMD would argue that it’s a fair comparison given that Nvidia is only offering Vera as a single, 88-core SKU. But the reality remains that the throughput comparison is one Vera could never win, and Nvidia would (and has) argued that it’s not trying to win in a race against the 256-core Venice. It’s building a single CPU for a single purpose.

The more interesting and consequential number here is the per-core performance. SPECrate_int is a throughput benchmark. A typical run loads all threads with a copy of an application and measures how much work gets done within a set amount of time. SPECspeed is the inverse of that, looking at a single application and how quickly it can run. AMD arrived at the numbers above by taking the overall SPECrate_int score and dividing it by the number of cores.

Nvidia’s results show Vera achieving a score of 925 overall. AMD says a 96-core High Frequency Epyc CPU achieved a score of 1,210. This processor, however, doesn’t seem to exist. AMD has the 96-core Epyc 9686F that boosts up to 5 GHz (much higher than the standard max frequency across the stack), but it has a rated TDP of 500W, not 600W.

Regardless, AMD divided that score by the number of cores; about 6.3 for AMD, and about 5.3 for Nvidia (remember these are 2P configurations). AMD says 1.2x, which actually translates to about an 18.8% lead. That’s not far off enough to say AMD was maliciously juicing its own numbers, but it’s important to note.

Given that AMD is using two different SKUs here (or maybe just one, considering the 9686F discrepancy), we can do the same per-core napkin math on the Epyc 9996 against Vera. Once again, Nvidia shared an overall score of 925, while the Epyc 9996 achieved a score of 2,070. That gives AMD a per-core score of 4.04.

That number isn’t important as a comparison point to Nvidia – again, we’re comparing a 256-core CPU to an 88-core one – but rather as a metric to see how Venice scales when normalized for per-core performance on a fully-loaded chip. That’s about 35% lower than the per-core score from the souped-up 9686F.

Although dissecting these numbers and sidelining the back-and-forth of two of the most powerful companies in the world is interesting, it’s not all that informative. SPEC maintains its strict reporting requirements for a reason. We won’t be able to say, with certainty, how these chips match up until we have official, reported runs. And even then, there’s an additional layer of compiler optimization (AMD and Nvidia both used GCC 15.2) and the broader context of the servers and workloads that these chips will serve.

The battle lines have been drawn, though only when looking at integer-based workloads. Vectorized performance is important, as well, and that’s an area where AMD holds a strong position in the current server CPU market. It doesn’t look like that will change with Vera, though we don’t have floating-point results to draw any conclusions from yet.

EA just announced FC 27, the latest release of its soccer franchise that it releases annually, and many players were shocked to learn that it came with a $149.99 Ultimate Plus Edition. This led to many complaints, with some comparing it to GTA VI Ultimate, which comes with extra side missions, activities, vehicles, guns, outfits, and other cosmetics, for just $99.99. However, it should be noted that FC 27 is available in three tiers — the Standard Edition for just $69.99, the Ultimate Edition, which costs $99.99, and the Ultimate Plus Edition, with its shocking $149.99 price tag.

Despite the availability of the base game at its usual price, the cost of the top-tier edition has caught the ire of many gamers. One user commented on X that they’re willing to “pay $200 for a game that’ll last 15-20 years,” while another said that EA wants “€150 for a roster update and some blue points you’ll spend on a player you’ll never use.” However, others pointed out that the $150 version is “for people who not only play it but spend money on it; 10,000 FC points is about £70/€82/$93.”

The FC franchise (previously known as FIFA) has been around for over 30 years now, with EA releasing a new title annually since 1994. That means fans have to pay at least $70 every year if they want to stay updated with the latest team rosters. This might be too much for some people, but hardcore fans seem not to mind spending that amount just to be able to have their favorite players on their team. In fact, they might even consider the $149.99 Ultimate Plus Edition good value as the $80 premium comes with 10,000 FC Points spread out over five months, five seasons of Premium Pass, and several other goodies. By comparison, FC 26 lists 12,000 FC Points for $99.99.

Even though gamers get additional value from the most expensive edition of FC 27, it still did not sit well with some people. Aside from that, they’re comparing it to the GTA franchise, with Rockstar continuously dropping updates to GTA Online for more than a decade, even for those who only purchased the game once. But even though EA did not change the price of the base game (and even the mid-tier Ultimate Edition), the fact that they’re asking more than double the price of the cheapest option is what caught the ire of the public, especially as the current FC 26 has mixed reviews on Steam.

OpenAI confirmed to Hugging Face only this week that models it was testing carried out the July 11 attack on the AI platform's production infrastructure, roughly ten days after the intrusion and days after Hugging Face disclosed it publicly without knowing who was responsible, according to a Wall Street Journal report. The models appear to have been active on the open Internet for several days before anyone stopped them, the Journal reported, and Hugging Face ended the attack two days after detecting it with help from an open-weight model out of China. Hugging Face co-founder and chief science officer Thomas Wolf told the paper the intruder was browsing cybersecurity datasets rather than hunting for anything a human attacker could sell.

Hugging Face published its disclosure on July 16, describing an autonomous agent framework that ran thousands of actions across a swarm of short-lived sandboxes, but it wasn’t until July 21 that OpenAI’s own account named GPT-5.6 Sol and an unreleased frontier model as the culprits.

The models are now known to have been running OpenAI's ExploitGym benchmark, a suite of roughly 900 tests that measures whether an AI can turn a known software bug into a working exploit, with the company's safeguards removed for the evaluation. Rather than solve the tests, the models escaped their sandbox to look for the answers on Hugging Face, per OpenAI's account. The intrusion started with a malicious dataset that abused two code-execution paths in the data-processing pipeline, then escalated privileges and moved laterally using stolen credentials of an unknown origin.

Hugging Face first tried Anthropic's Fable 5 and an earlier Opus model to analyze the attack logs, but both refused because the logs contained real attack commands and exploit payloads. Hugging Face then turned to GLM 5.2, an open-weight model from Beijing-based Z.ai (formerly Zhipu AI), which had no such restrictions. The company's own July 16 disclosure described the blocked models only as "frontier models behind commercial APIs" and didn’t name them.

Z.ai’s GLM-5.2 held top accessible benchmark positions by default during the 18 days that U.S. export controls kept Anthropic's Fable 5 offline in June, before Anthropic restored the model with a single filter tuned to block one vulnerability-discovery technique. There’s serious irony here, given that the same Chinese open-weight model that Washington's export-control push has aimed to sideline is the one that handled incident response after an American lab's models attacked an American company, and American commercial models declined to help.

Security researchers have questioned whether the episode demonstrates model capability or an OpenAI failure. Cybersecurity veteran Jake Williams told TechCrunch that any model performing the documented actions "was not fully contained in a sandbox," calling it a control failure. OpenAI has said it shut down its model-testing systems to assess the damage, disclosed the zero-day in the package registry cache proxy that enabled the sandbox escape to the affected vendor, and promised a detailed report.

Both companies say the investigation is ongoing, and OpenAI hasn’t yet said how long the models roamed unsupervised or whether they reached any other targets.

23 state governors and 187 utility companies and data center developers have signed President Donald Trump’s “ratepayer protection pledge,” which is Washington’s way of trying to control spiraling electricity costs driven by the massive power demand of AI data centers. According to The Associated Press, some of the signers include utility companies NextEra Energy, Duke Energy, American Electric Power, Southern Co., and Pacific Gas & Electric, and data center developers Equinix, Digital Realty, and Prologis.

Trump first revealed this promise in late February during the State of the Union address and then hosted some of the biggest AI hyperscalers — including Meta, Amazon, and OpenAI — in the White House a week later to force them to spend on their own power requirements. This was supposed to help bring electricity costs down, with Energy Secretary Christ Wright saying back in March that it “will deliver more affordable, reliable, and secure energy for the American people.” The president repeated this promise during the event, saying, “Electricity bills for American families will actually come down. They’re going to have a lot of electricity left over, and they’ll put that into the grid.”

Unfortunately, the March promise had little to no effect on electricity rates across the country at the moment. Despite the White House’s promises that the pledge would lower utility bills, PJM Interconnection, the nation’s largest power grid operator, slapped Maryland with a $2-billion bill for upgrading its grid to accommodate out-of-state AI data centers. Monitoring Analytics, an independent watchdog monitoring PJM Interconnection, also said that the 75.5% increase in power costs in the U.S.’s largest power region has been directly caused by data centers.

It’s unclear if these cost increases are the long-term effects of the AI build out even before the White House pledge, but it seems the administration is doubling down on it by asking states, utility companies, and data center developers to commit to it, too. Trump has been pushing for the acceleration of the adoption of AI tools and the infrastructure needed to support them, believing that it needs to win in the “AI race” to maintain its global supremacy, especially as China is neck-and-neck with the U.S. when it comes to the technology.

However, the American public is pushing back against these developments, especially as issues impacting electricity costs, water quality, noise pollution, and more that were caused by data centers are widely reported. It has gotten to the point that several jurisdictions have applied temporary bans on data center developments, including Seattle (which plays host to Amazon and Microsoft) and the state of New York. These developments threaten to derail the current administration’s AI policy, which has ordered grid operators to expedite AI data center applications.

The ratepayer protection pledge will supposedly allow the U.S. to have its data centers without punishing the common American with excessive electricity cost increases, but its critics say that it’s just a promise and cannot be legally enforced. The Associated Press says that California is trying to pass legislation that will codify these promises into law.

Oregon is the only state at the moment to have passed a law that forces developments that use more than 20 megawatts of power to pay their fair share. The POWER Act, which was passed in April 2025 — almost a full year before Trump announced the ratepayer protection pledge — forces the power bills of large electricity consumers to “reflect the true costs of their electric service.” Because of this, Portland General Electric (PGE), the state’s largest power supplier, has increased the data center power bills by 30% while also cutting residential costs by 1.3%.

It’s unclear if any of the states that have signed the pledge have similar legislation underway, or what steps the data center developers will take to follow through on their promises. Still, the U.S. president is adamant that states should support data center development within their borders. “You have to convince your community. You can’t fight it. You have to go with it,” Trump said. “If you don’t take all that money, somebody else is going to take it. You might as well do it yourselves.”

On this day in 2006, AMD confirmed its acquisition of graphics chip firm ATI. AMD stumped up a cash and stock deal worth a total of $5.4B for the Canadian PC graphics innovators. With 20/20 vision now 20 years on, we can see the deal helped AMD prosper on three fronts: continuation and innovation of Radeon GPUs, the rise of the APU, and AMD’s dominance in the console business. That’s not all, of course, and it is also interesting to recall that AMD approached Nvidia before it bought ATI.

AMD CEO Hector Ruiz and ATI CEO Dave Orton appeared together in New York on the morning of July 24, 2006, to publicly announce the deal. Ruiz told the press that the deal, unanimously approved by the directors of both companies, would "reinvent our industry." The AMD CEO went on, “We believe AMD and ATI will drive growth and innovation for the entire industry, enabling our partners to create differentiated solutions and empowering our customers to choose what is best for them.” Orton added that “Joining with AMD will enable us to innovate aggressively on the PC platform.”

In the next couple of years, the ATI graphics brand slowly melted away. For example, the ATI R600 (Terascale 1, unified shader architecture) GPU, which was in development at the time of the acquisition, would become the Radeon HD 2900 series under AMD branding. As a transition product, some HD 2900 XT boxes would still carry ATI packaging and branding. Taking the cooling solution off an AMD graphics card, you might still see an ATI GPU under the thermal paste, all the way up to around 2010. In 2011, Tom’s Hardware published its 25 Years Of Graphics History: A Farewell To ATI, In Pictures, which is a must-read for fans of the era.

While graphics card development rolled on in a tit-for-tat battle with Nvidia, AMD’s next fortuitous chunk of synergy came from integrating its Radeon IP alongside its CPU cores to create APUs. It started this journey with the AMD Fusion line in 2011. Nowadays we have APUs that have taken this vision far further, with the Ryzen AI Max / Max+ (Strix Halo and Gorgon Halo) series. The integrated graphics on these processors pack up to 40 RDNA 3.5 Compute Units and can go toe-to-toe with desktop graphics like the RTX 4060/4070, depending on workload. They also benefit from unified memory, allowing users to configure oodles of VRAM, if they have it spare.

As the Radeon developers forged ahead moving from the GCN to RDNA graphics architecture era, AMD saw an opportunity in the console space. From the early to mid 2010s, AMD made inroads into APU development that meant the processors became attractive solutions for console developers. It still holds pretty tightly to that market today, which has spilled over to handhelds. However, Intel looks far more serious in this market now, with Panther Lake and B390 iGPUs. Moreover, Nvidia could surely make a dent on consoles with Arm plus GeForce semi-custom SoCs if it wasn’t living it up in the lucrative AI market.

Red and green would never be seen

Before the AMD and ATI deal was inked, reports indicated there were chances of a similar merger involving AMD and Nvidia. Our 2012 report on this ‘missed opportunity’ suggests Jensen Huang was being quite difficult during the negotiations. Apparently the man in the leather jacket insisted that he become chief executive of the combined company. That made Hector Ruiz pretty cool on the prospect, so AMD’s attention was diverted towards ATI.

AMD has announced its long-term CPU roadmap, including multiple generations of its Zen microarchitecture at its Advancing AI event. Much of the event was focused on the new 256-core EPYC 9996 sporting the Zen 6 architecture, as well as Venice-X, which is slated to arrive next year. But AMD also teased a Zen CPU roadmap going out to Zen 8.

"In 2028, we are going to introduce Florence," Lisa Su, chief executive of AMD, said. "Florence brings the next-gen Zen 7 cores and its leading-edge process technology. It's a new set of AI compute extensions to really ensure that we have all of the AI capability, and it supports the latest memory technologies."

Su did not disclose specific details about the process technology, core counts, memory subsystem, or AI extensions planned for (Zen 7) Florence. However, she indicated that Florence will not be a standalone processor family, instead joined by the Ferrara AI host node and Faenza Agentic Sandbox for different AI workloads. AMD says this approach will enable it to offer purpose-built CPUs for a wider range of applications rather than relying on a single architecture configuration across the entire server market.

"And we are not stopping there," Su said. "We are already deep in development of Ravenna, our 8th Generation EPYC family built on Zen 8, and that family is already well under development for 2030."

The CPU roadmap is part of AMD's general strategy to offer a predictable cadence for its data center platforms.

On the accelerator side, the company is developing its MI500-series Instinct products with next-generation HBM, larger scale-up domains, and new copper and optical interconnect technologies, similar to Nvidia's outlook toward Rubin Ultra and Feynman.

"MI500 will deliver the largest generational leap in the history of Instinct, putting us on track to deliver more than 2,000 times higher inference throughput in just four years," Su said.

AMD also confirmed that its CDNA Next-based Instinct MI600 family is already deep in development for 2028. At the event, AMD launched its MI455X GPU, as well as teased more about its upcoming MI500X range, which we expect to launch next year.

AMD is bringing its Strix Halo APUs into the world of physical AI. The new X100 series of processors come with similar specs as the various Ryzen AI Max models floating around in client devices, but they’re tailored for 24/7 operation, with a 10-year lifecycle in embedded applications like robotics.

There are three SKUs that align with the three original Strix Halo models (not the updated versions with 40 CUs). The top-end X199 comes with 16 Zen 5 cores and 40 RDNA 3.5 CUs. The X188 steps down to 12 cores and 32 CUs, while the X168 comes with eight cores and the same 32 CUs. AMD hasn’t shared detailed specifications for each model, but the company says the range goes up to a 5.1 GHz boost clock and 128 GB of unified memory. They also include an XDNA 2 NPU with up to 50 TOPS, a configurable TDP between 45W and 120W, and operating temperature between -40 degrees Celsius up to 105 degrees.

AMD’s range bites back at Intel, which launched a range of Panther Lake SoCs for physical AI at the beginning of the year. Both make an argument for SoCs in robotics, reducing latency when the CPU, AI accelerator, and memory are fragmented across separate chips. The X100 range is just physically larger than Panther Lake, packing much more silicon on the SoC for more powerful deployments.

The company shared a range of benchmarks comparing the flagship X199 against Intel’s Core Ultra X7 358H, a 16-core chip with Intel’s Arc B390 iGPU that has 12 Xe3 cores. AMD claims a lead of 1.2X and 1.3X, respectively, in GeekBench 6.1 and PassMark, as well as 1.5X in an unofficial SPECrate 2017 run looking at integer workloads. In graphics, AMD unsurprisingly takes the edge with 1.4X faster Vulkan and 1.7X faster OpenGL performance (both measured with GFXBench 5 on Ubuntu), as well as a 1.6X lead in Unigine Heaven Extreme.

On the physical AI front, AMD claims a 1.4X improvement in Time to First Token (TTFT) and 3.5X faster tokens per second in Llama-bench, with a Vulkan backend running at a 45W TDP. These results need a massive dash of salt, however.

AMD tested the Ryzen AI Max 395+ “configured to reflect Ryzen AI Embedded X199 specifications.” It tested on the Maple reference board with a 5.1 GHz CPU clock, 2.9 GHz GPU clock, and sustained 45W TDP. The X7 358H, meanwhile, was tested in an MSI Prestige 16 Flip AI+ with an enforced TDP limit of 30W. AMD then “projected” 45W performance on the Intel chip “using scaling factors derived from public benchmark data.”

It’s not exactly an apples-to-apples comparison, in other words. There’s some sort of proxy stand-in or extrapolation of data across all of the benchmarks here, so keep that in mind as we work through the rest of AMD’s X100 announcements.

AMD X100 Kria SOM and robotics developer platform

utside of the chips themselves, AMD is offering X100 models as part of a Kria System on Module (SOM) or an integrated robotics developer platform. The Kria X100 board measures 120mm x 120mm and conforms to the standardized COM-HPC form factor. If you’re a developer that wants to develop for the board, AMD is offering its Kria AI robotics developer platform.

It’s a fully-integrated box, leveraging the X100 Kria SOM alongside AMD’s Spartan UltraScale+ FPGA baseboard. AMD says it’s a “turnkey” solution for robotics development, including specialized connectivity for cameras and industrial networking, along with robotic sensors. The platform is available in early access now, and AMD says it’ll be in full production in Q4 of this year. .

AMD shared some benchmarks for the X100 Kria, as well, comparing it to Nvidia’s Thor T5000. These benchmarks weren’t run internally at AMD. They were commissioned by AMD and ran by Open Navigation and Mimix. Critically, the benchmarks didn’t test an X100 Kria board, or at least, not exactly in the form it will take once it’s inside a robot or AMD’s developer box.

Instead, AMD is comparing Nvidia’s Jetson AGX Thor developer kit to a GMKtech EVO-X2 AI mini PC with a Ryzen AI Max+ 395 “configured to reflect Ryzen AI embedded x199 specifications.” Naturally, the thermal and power environment of these chips will heavily influence performance.

AMD is continuing its attempt to siphon developers away from Nvidia’s CUDA platform for development, as well. It’s HIPIFY tool converts CUDA code to AMD’s HIP C++ portable code, and the company claims it can now handle 70-80% of the “effort” of porting on its own. AMD tested on a Ryzen AI Max+ 395, once again configured to match the X199, and it ported 15 CUDA applications, comprising 1,199 lines of code, to arrive at that 70% to 80% range.

X100 Kria lives at the “brain” of the robotics platform, but AMD envisions an end-to-end solution for humanoid-style robots with its Spartan UltraScale+. Zynq UltraScale+, and Versal AI Edge Gen 2 FPGAs and SoCs

At AMD’s Advancing AI event this week, the company revealed more details of its upcoming MI455X GPU and the Helios rack-scale architecture that will join 72 of those GPUs into a coherent accelerator—the largest such system that AMD has built so far and its first to truly compete with Nvidia’s NVL72 rack-scale design, as used in the Blackwell and Rubin generations.

AMD calls the MI455X “by leaps and bounds the most advanced AI accelerator we’ve ever built,” and from what we’ve seen, it’s the most competitive product at both the chip level and at rack scale that AMD has ever put up against Nvidia’s thorough dominance of the AI compute race.

The full MI455X GPU is a massive chip encompassing 320 billion transistors, and it’s built up using advanced packaging technologies. Four Accelerator Complex Dies (XCDs) are stacked on top of each Fabric and Cache Die (FCD) using hybrid bonding. In turn, the two FCDs are each joined to six stacks of HBM4, the two I/O dies, and to one another using TSMC’s CoWoS-L technology.

This chiplet design lets AMD use the most advanced TSMC 2N gate-all-around (GAA) process technology on the XCDs, where it’s most beneficial for power and performance, while the FCDs and I/O dies, which contain elements that don’t benefit from the densest process technologies, are fabricated on TSMC N3P.

CDNA 5 represents a large shift in the shape of the CDNA architecture. AMD now calls the fundamental building block of the CDNA 5 Accelerator Complex Die a “Work Group Processor” instead of a “Compute Unit,” but in practice, the basic layout of the rest of the Accelerated Complex Die (XCD) is largely similar.

The number of WGPs on the MI455X remains the same as on the MI355X at 256. Because there hasn’t been a change to the number of fundamental compute resources on the chip, the per-WGP throughput on the CDNA 5 MI455X has to be much higher than on the MI355X to deliver its large performance boost.

Among the many other changes for this generation, CDNA 5 marks a major shift for the programming model of an Instinct GPU. The width of a wavefront, or group of work items or threads that each workgroup processor addresses, is now 32 instead of 64, a choice AMD says improves instruction latency, branch divergence penalties, and register pressure. It further explains that a 32-wide approach increases the flexibility of the architecture for interacting with different tensor tile sizes and mapping compute kernels to the hardware. RDNA GPUs have used a native wavefront size of 32 since their introduction.

CDNA 5 greatly enhances compute performance over CDNA 4, theoretically doubling and in some cases quadrupling the peak FLOPS possible from the chip. The MI455X especially benefits lower-precision floating-point formats now common for use in inference. OCP MXFP8 and MXFP4 formats are theoretically up to 4X faster than on the CDNA 4 MI355X.

Here’s an overview of the MI455X’s theoretical peak FLOPS compared to both the previous-generation MI355X and Nvidia’s Rubin GPU.

At least on paper, the MI455X offers peak performance that bests what Nvidia has shown for Rubin so far, and in combination with the Helios rack-scale architecture that finally gives AMD the same 72-GPU coherent domain as Nvidia’s NVL72 rack-scale design, AMD is more competitive in the AI data center capacity race than ever before. And that’s translating into real customer wins, as AMD has announced pivotal deals with Microsoft and Anthropic this week.

But we’d be careful about drawing too many conclusions from these head-to-head peak FLOPS numbers, as the realized performance of these GPUs in the real world is likely to be much lower in practice, as AMD itself admitted in one of our sessions. The ongoing challenge will be to optimize software and applications to achieve as much of that theoretical performance as is possible.

Beyond its general compute improvements, AMD is also touting improved transcendental math performance from the CDNA 5 Transcendental Unit, which has wide-reaching implications for performance on essential AI functions like softmax, neural network activations, and attention. AMD says that the CDNA 5 Transcendental Unit doubles throughput versus CDNA 4. The Transcendental Unit also adds support for an explicit tanh instruction, which is useful for certain operations on hidden layers within neural networks.

AMD also deeply revised the cache and memory hierarchy on the MI455X. The large Infinity Cache on CDNA 4 has been ditched in favor of a smaller but higher-bandwidth shared L2 cache on each Fabric Compute Die. Each FCD has a 96MB L2 slice for 192MB in total, compared to just 32MB backed by the 256MB Infinity Cache on the MI355X. AMD says this cache offers 1.5X higher bandwidth per FCD compared to the CDNA 4 Infinity Cache, so in aggregate, the MI455X has 3X the L2 bandwidth compared to the MI355X.

Within the WGP, larger, faster, and more flexible caches are now available. The local data store (LDS) or scratchpad memory has doubled in size versus CDNA 4, to 320 KB, and in total, there is 96 MB of LDS across the chip, twice that of the largest CDNA 4 implementation on the MI355X. AMD says the LDS SRAM offers higher read and write bandwidth per clock than in the previous generation, but it didn’t provide specifics.

Critically, the main memory architecture of MI455X has moved to HBM4 for this generation. AMD uses six stacks of HBM4 per FCD for a total of 12 on the chip, offering a memory capacity of 432GB and memory bandwidth of 23.3 TB/s per GPU. High memory capacity and bandwidth are both crucial for keeping ever-expanding AI model weights and KV caches close to the GPU for the best performance.

This HBM implementation is one of the MI455X’s strongest advantages over Nvidia’s Rubin in isolation. It offers both much higher capacity and slightly higher bandwidth than the first Rubin GPU that Nvidia detailed this week. In its initial configuration, Rubin only offers 288GB of HBM4 with up to 22 TB/s of bandwidth.

At rack scale, the MI455X’s higher HBM capacity adds up to 31.1 TB of HBM across 72 GPUs, or a whopping 50% more than the 20.7 TB aggregate capacity of Vera Rubin. And the Helios rack-scale architecture is AMD’s first to join all of that GPU memory into a single coherent domain. Since AI inference performance is dominated by both data locality and memory bandwidth, AMD’s advantages in this regard are sure to attract plenty of attention.

Efficient data movement across the chip is a key consideration for reducing power consumption and improving performance on the MI455X.

The CDNA 5 Tensor Data Mover is an improved version of the data movement engine in past CDNA generations. Like Nvidia’s Tensor Memory Accelerator, the TDM accelerates the production of certain tensor-specific memory addresses and facilitates moving the related data from memory without involving the shader engines. In the CDNA 5 generation, the TDM gains the ability to move data directly from DRAM to the WGP LDS cache without staging data at intermediate cache levels.

AMD has also added multicast support for memory reads to the WGPs to take advantage of the fact that AI workloads often need to work on the same weights and activations across multiple WGPs at once. By using multicast, a single memory read can be amplified across many WGPs, increasing effective memory bandwidth, reducing duplicated traffic on the bus, and lowering power consumption. Nvidia has had a similar capability in its GPUs since Hopper, but given AMD’s intense focus on efficient data movement this generation, it’s perhaps unsurprising to see a version of it added here.

All told, the MI455X is AMD’s most compelling Instinct product yet. It delivers a massive generational performance improvement, it puts up peak FLOPS on paper that are competitive with or even superior to Nvidia’s upcoming Rubin GPU, and it offers a massive 432GB pool of HBM4 memory that’s 1.5x larger and even slightly faster than Rubin’s 288GB complement.

Combined with the Helios rack-scale architecture and its 72-accelerator scale-up domain—AMD’s first true answer to Nvidia’s NVL72 rack-scale design—we should expect the race for AI compute superiority to really heat up in the second half of this year as both Nvidia and AMD begin delivering their next-generation products to customers.

AMD and Cerebras Systems on Thursday announced plans to develop a platform that would combine AMD's EPYC processors in Helios rack-scale infrastructure with Cerebras' Wafer-Scale Engine (WSE) solutions. Together, the new systems promise to combine low latency of AMD's CPUs and Instinct GPUs with high throughput of Cerebras's Wafer Scale Engines (WSE) processors.

AMD and Cerebras expect the new inter-rack-scale platform — based on AMD Helios rack with EPYC CPUs and Instinct MI400-series accelerators inside — to be responsible for prompt processing and large context windows, whereas Cerebras' WSE will take care of the memory-bandwidth-intensive token-generation stage.

AMD and Cerebras expect their disaggregated inference platform to deliver up to 5X higher tokens per second per watt (T/s/W) by assigning different portions of an inference workload to architectures optimized for them. Therefore, AMD Helios provides rack-scale compute capacity and large volumes of complex requests, whereas the Cerebras WSE handles latency-sensitive token generation. The two compute platforms will operate within a single inference workflow, although the companies have not disclosed additional performance data or explained how the systems will be interconnected.

The underlying idea of the AMD + Cerebras platform is essentially the same as Nvidia's CPX concept, but AMD and Cerebras assign the specialized hardware to the opposite inference stage.

Nvidia's disaggregated design separates inference into context/prefill and generation/decode. The cancelled Rubin CPX GPU with GDDR7 was optimized specifically for the compute-heavy context/prefill stage, while the regular HBM-equipped Rubin GPUs handle the memory-bandwidth-bound generation stage.

By contrast, the AMD and Cerebras platform follows the same disaggregation principle, but the specialization is inverted: AMD's Helios platform with Instinct GPUs handles the prefill stage and processes prompts and large context windows, while the Cerebras WSE takes over the decode stage and handles latency-sensitive token generation.

Cerebras plans to install AMD Helios systems in its own data centers and integrate them with its WSE racks. The combined offering is scheduled to become available initially through Cerebras Cloud in the second half of 2026, according to the two companies.

The GeForce RTX 3090 may no longer be one of the best graphics cards. However, it can still compete with the top performers today with a little help from its younger sibling, the GeForce RTX 3050. Recently, a resourceful gaming enthusiast who goes by the name quziwuzzi explained on Reddit that they paired these two Ampere-based graphics cards and used Lossless Scaling technology to dramatically boost their combined performance, achieving up to 144 FPS at 4K (3840x2160) resolution.

Lossless Scaling is a very powerful yet affordable tool on Steam that costs just $7 and brings AI upscaling and frame generation to the masses. What differentiates Lossless Scaling from proprietary solutions, such as Nvidia DLSS, AMD FSR, or Intel XeSS, is its wide compatibility with any game or video software. It works seamlessly regardless of whether the title or application comes with official support for these proprietary solutions.

In this example, the Gainward GeForce RTX 3090 Phoenix takes on the primary workload of running and rendering the game. Meanwhile, Lossless Scaling handles the demanding frame generation duties. But instead of stealing resources from the primary GPU, it operates on a secondary graphics card, the Asus Dual GeForce RTX 3050 OC Edition. The setup allows the GeForce RTX 3090 to focus exclusively on rendering the game by offloading the frame generation process to the GeForce RTX 3050.

According to the Redditor who shared their experience, the GeForce RTX 3090 delivered up to 71 FPS at a 4K resolution. When paired with the GeForce RTX 3050 and using Lossless Scaling for frame generation, the system's performance doubled and reached 144 FPS at 4K. The author did not mention which games were used for testing. The motivation for the uplift was to take advantage of the Redditor's 42-inch LG C4 OLED television, which features a 144 Hz refresh rate.

My dual GPU Setup from r/losslessscaling

Lossless Scaling supports 2X, 3X, and 4X frame generation multipliers that essentially duplicate, triplicate, or quadruplicate the perceived frame rate. While the technology is compatible even with iGPUs, you logically need the right discrete graphics card to get the best results. The GeForce RTX 3050 proved more than sufficient for handling frame generation at 4K resolution. According to the Redditor's firsthand account, Lossless Scaling’s 2X, 3X, and adaptive modes all worked fine.

The global memory shortage is still in full force and continues to put immense pressure on the availability and pricing of graphics cards. The cost of upgrading to the latest and greatest graphics card is out of reach for many gamers. As a result, the gaming community is constantly looking for affordable solutions to boost performance without throwing the house out the window. Lossless Scaling tool can breathe new life into your existing hardware. If you are lucky enough to have a spare graphics card lying around, you can put it to good use. Even something as old as the GeForce GTX 750 Ti or Radeon RX 550 can improve your system's gaming performance.

Some may argue that frame generation is fake frames. But for only $7, it is a cost-effective way to trick your brain for the meantime and improve the gaming experience, at least until the memory shortage subsides and you can upgrade your graphics card for real.

AMD is finally providing some details on its first Zen 6 CPU, which it has been teasing for over a year. The Epyc 9996 is a 256-core / 512-thread chip, packing AMD’s new Zen 6 architecture, and it’s the first to launch in what AMD describes as a “broad portfolio” for Venice. In addition to claiming significant performance advantages over the impending Nvidia Vera and Intel’s Xeon 6, AMD says it will continue to build out the Venice range with bespoke designs over the next year.

“It’s not just a single processor,” said AMD’s Ravi Kuppuswany, corporate VP of compute and enterprise solutions.q “It’s a portfolio.” AMD says it has purpose-built solutions, splitting its offerings depending on the application, not dissimilar to how Intel has split its Xeon ranges over the past few generations (nor how AMD has softly segmented its Epyc offerings). The roadmap starts with the main Venice lineup on the SP7 socket, which is what AMD has been teasing for so long. It scales up to 256 cores and 512 threads, 1.6 TB/s of memory bandwidth with fast MRDIMMs, and 128 PCIe 6 lanes in 1P configuration (160 lanes in 2P).

Note: When scaling up to 256 cores, AMD uses its Zen 6c “dense” design. With a standard Zen 6 design, AMD says Venice scales up to 128 cores and 256 threads, while high-frequency variations top out at 96 cores.

In the first half of next year, AMD plans to launch Venice on its SP8 socket, offering as few as eight cores and up to 128, focused on smaller deployments. These chips support eight-channel memory with two DIMMs per channel, and the same 128 PCIe 6 lanes.

Venice-X is expected in the second half of 2027, on the SP7 socket. We didn’t see Turin-X, but the last, last-gen Genoa-X came with 96 cores and up to 1152 MB of stacked L3 cache. Those specs haven’t changed (short of the Zen 6 microarchitecture), but AMD says it's able to clock Venice-X up to 5.15 GHz.

Finally, Verano should arrive in the second half of next year on the SP8 socket, and it looks like the most direct competitor to Vera (AMD’s Kuppuswamy had some fun with calling it “Vera-No”). It’s optimized to be an AI host node, says AMD, packing up to 72 cores and 5 GHz peak clocks. Critically, it comes with a 24-channel LPDDR5X memory system, leveraging SOCAMM2 modules.

One of the advantages Nvidia claims with its Vera chip is lots of memory bandwidth through the LPDDR5X system. AMD’s approach is different with Venice SP7. It’s scaling up to 16-channel memory with Venice SP7, with support for MRDIMMs running at 12,800 MT/s, or standard DDR5 RDIMMs running at 8000 MT/s.

It’s a significant jump over Turin, which uses 12-channel memory, with support for RDIMMs running at 6400 MT/s. AMD claims per-socket bandwidth of 1.6 TB/s, significantly higher than the 1.2 TB/s available on Vera, and nearly triple the 576 GB/s per-socket bandwidth of Turin. Intel recently enabled 8000 MT/s RDIMMs on select Granite Rapids and Clearwater Forest SKUs, and it says support for MRDIMMs with speeds up to 8800 MT/s is coming in Q1 2027.

Zen 6 is built on TSMC’s N2 (this has been previously confirmed). AMD confirmed that there are 32 cores on a CCD, along with two IODs. Keep in mind that the 32-core CCD is using Zen 6c, not full Zen 6. There has been plenty of speculation about 32-core CCDs in consumer Zen 6 CPUs, but that seems unlikely.

The 256-core configuration comes with a massive 1,024 MB of L3, nearly triple the amount of the Epyc 9965. This isn’t stacked cache, either; that will come with Venice-X. Each CCD has access to 128 MB or L3, or 4 MB per core, double what was available on Turin.

Although AMD has focused a lot of its teases on the 256-core Venice, the initial SP7 offerings will also hold a 96-core, high-frequency model that can clock up to 5 GHz.

AMD shares first 256-core Epyc ‘Venice’ benchmarks

Unlike the extrapolated performance AMD shared a few weeks back, we have some concrete benchmarks for the Epyc 9996 now. AMD has, unsurprisingly, focused the workloads around agentic AI. However, many of the workloads applicable for agentic AI are applicable elsewhere, as well, including high-concurrency networking tasks, code compilation, and media processing.

Note that AMD includes just the Epyc 9965 as a gen-on-gen comparison point in the charts above. This is a “dense” Zen 5 design with 192 cores. Results for the 128-core 9755 are included in the tables below.

Starting with front-end operations, AMD claims a 1.2x gen-on-gen improvement and a 2.8x improvement compared to Intel Xeon 6980P, with an NGINX web server using the WRK load generator. Unlike most of these competitive performance figures, AMD included the actual numbers for the benchmarks it ran in the footnotes, which you can see in the table below.

In data-heavy workloads that are common among AI agents, AMD claims a 1.7x improvement over Turn, and a massive 3.4x over the Xeon 6980P. AMD used the TPCx-AI benchmark to gather these results. The primary metric for this test is AI use cases per minute (AIUCpm), for which AMD shared the median result2. If you’re interested in more about the reporting of this benchmark, Dell has published an extensive breakdown.

In vectorized workloads, AMD claims a 1.6x gen-on-gen improvement and 2.3x improvement compared to the Xeon 6980P. For this test, AMD used Meta’s open-source FAISS (Facebook AI Similarity Search) library to search for similar vectors in the siftm1 dataset. The metric here is QPS, or queries processed per second, looking at overall query throughput.

For its “enterprise tools” benchmarks, AMD ran several tests, including TPC-H, TPC-C, and Redis, and it reports the results as “geomean throughput.” We have actual numbers here, but they’re a geomean representing several different tests rather than a single benchmark. Broadly, however, AMD claims a 1.6x gen-on-gen improvement in these workloads, and a 2.6x improvement compared to Intel.

A lot of agentic workloads are applicable outside of agents, but AMD also tested a few agents directly. It replayed five different agent personas across the chips and, once again, gathered a throughput geomean. We don’t have the metrics here, nor for the previous benchmark, so it’s possible there’s an angle of performance that we’re not seeing with the data provided by AMD.

Regardless, the company claims a 1.5x gen-on-gen improvement in this test, and a 2.5x improvement compared to the 6980P.

AMD ran these tests earlier in the month. But just a few days ago, Nvidia published its first SPEC CPU 2026 results for Vera. AMD ran some tests of its own using the same compiler for a comparison between Vera and Venice. AMD’s Kuppuswamy says, “everything is apples-to-apples comparison, same compiler.” That’s GNU 15.2, if you’re curious.

In throughput, AMD claims a 2.2x improvement in the SPECrate integer suite, compared to Vera using the dense Venice design with 256 Zen 6c cores. More importantly, AMD claims a 1.2x improvement in per-core performance when comparing Vera to a 96-core “High Frequency” Venice chip. AMD says it used Nvidia’s results as the basis for comparison. With both Venice designs, AMD used a 600W TDP.

In SPEC CPU 2017 (again using SPECrate with integer workloads), AMD has data comparing Venice to Intel’s 6980P and Arm’s new AGI, showing 2x throughput compared to Intel, and 1.3x per-core performance. Note the core counts here for AMD. SPECrate is a throughput test, and AMD stepping down to a 128-core model suggests that performance will likely drop off as the core count increases.

Although AMD wants to focus Venice performance on agentic workloads, it shared a range of what are now being called “legacy” workloads across the cloud and HPC. Some of the results are repeated from the earlier slides, such as Redis and NGINX, but there are some additional data points, including NAMD and SQL. The performance improvements here are large, though not surprising. You can see that across these tests, even Turin beats the competition from Intel and AWS.

AMD’s Venice-X CPU is launching in the second half of 2027, the company revealed Thursday at its Advancing AI event. The CPU is built on the same Zen 6 microarchitecture as Venice SP7, which AMD says is now in production, but it comes with smaller core counts and leverages AMD’s 3D V-Cache to stack an unbelievable 1152 MB of L3 cache on the chip, all while offering 96 cores and clock speeds up to 5.15 GHz.

We’ve previously heard teases of Venice-X, and AMD has released variants of its Epyc chips like this in the past, such as Milan-X and Genoa-X. But we never saw Turin-X, and we haven’t gotten any concrete details about Venice-X up to this point. Now, we have a peek into what Venice-X will offer, which looks similar to Genoa-X in some regards.

AMD is sticking with 96 cores with Venice-X, as well as 1152 MB of stacked L3 cache. There are a few major differences compared to Genoa-X, however. First, AMD says clocks are much higher here, claiming Venice-X tops out at 5.15 GHz (the 96-core Epyc 9684X clocks up to 3.7 GHz). Venice-X also comes with the memory improvements available in most of the chips in the range.

It supports 16-channel memory, either with standard DDR5 RDIMMs at up to 8,000 MT/s or with new MRDIMMs 12,800 MT/s, offering up to 1.6 TB/s of aggregate memory bandwidth. The memory system in Venice broadly is a massive increase over Turin, nearly tripling the aggregate bandwidth, mainly on the back of speeds enabled by MRDIMMs.

Venice-X is one of four variations of AMD’s Zen 6 lineup for data centers, mainly targeting HPC workloads, with its massive L3 cache and relatively high clock speeds. Venice-X uses the same SP7 socket as the main Venice range. Other variations of Zen 6 offerings, including Verano, will use the SP8 socket instead.

AMD’s standard Venice chips support up to 1024 MB of L3 cache on their own, nearly triple that of its previous flagship offering. That cache is split among 256 cores, however. Venice-X doesn’t come with much more cache overall, but that cache is serving far fewer, more powerful cores, which should be useful in HPC workloads.

AMD didn’t disclose any other details about Venice-X, nor any performance projections. Given that it’s set to launch in the second half of 2027, we’re still a ways out from that.

Primate Labs has released Geekbench 7, the latest version of its popular cross-platform benchmark. The update introduces new and improved workloads designed to better represent and measure the performance of the latest CPUs and GPUs across major platforms, including Android, iOS, Windows, macOS, and Linux. Like previous versions, Geekbench 7 is available free of charge for personal use. Enthusiasts and IT professionals can also opt for Geekbench 7 Pro, which is available at a 20% discount until August 6.

One of the biggest changes introduced with Geekbench 7 is how the multi-core benchmark behaves. It will now mirror real-world application behavior instead of forcing every workload to use all available CPU cores. For instance, the HTML5 browser test has been excluded from the multi-core suite since web browsers are generally single- or lightly threaded. Geekbench 7 will only run a benchmark in multi-threaded mode if the real application it's modeling also uses multiple threads. As a result, Primate Labs says the new benchmark will deliver a more realistic indication of overall system performance.

Geekbench 7 will also feature a new set of media workloads designed to better evaluate how modern CPUs handle everyday multimedia tasks. These include encoding AV1 video for screen sharing during video calls, compressing audio using the Opus codec for applications such as voice recorders and podcasts, and decoding audio and video while simultaneously generating live captions using OpenAI's Whisper speech recognition model. Essentially, these workloads are claimed to better represent tasks such as video conferencing, content streaming, and media consumption.

A new Game Physics benchmark is also being added, which is based on the Jolt Physics engine used in modern games, to offer a more accurate measurement of CPU performance in physics-heavy gaming scenarios. The update further enhances its Photo Editor workload with more complex editing operations and expands the Photo Library test to include support for newer image formats such as JPEG XL and DNG.

The GPU benchmark has also been revamped to go beyond gaming, with greater emphasis on machine learning and content creation workloads. The new tests will measure tasks such as real-time face tracking and filter effects for social media apps, image upscaling using AI, and background blurring during video conferencing. Additionally, the update adds new GPU workloads for RAW image processing, LUT-based video color grading, path tracing, and fluid simulation.

Geekbench 7 is also set to introduce support for Nvidia's CUDA API in addition to OpenCL, Vulkan, and Metal, allowing users to benchmark Nvidia GPUs using the same API that is used in a variety of professional and AI applications.

Lastly, in order to keep up with demanding modern workloads, the benchmark datasets have been updated to better reflect the larger and more complex files that users work with today. For instance, the File Compression test now includes a broader mix of archives containing source code, object code, and text documents, while the PDF Viewer workload processes a wider range of files, from park maps to technical documentation and academic papers. The update also introduces more assets and additional image formats across its developer and image processing workloads.

While PC builders, enthusiasts, and gamers are some of the most heavily affected by the AI-driven memory chip shortage, experts have also been warning that this will eventually hit the automotive sector. It seems that their fears have come true, as Nikkei Asia reports that two major automakers are increasing their prices precisely for this reason. General Motors said that it expects new vehicle prices to increase by 0.3% this year, changing its previous projection of vehicle costs to remain the same or even slightly more affordable. On the other side of the world, Chinese automotive giant BYD has also raised the prices of the driver assistance features by 20%, which it sells separately from its models. South Korea’s Hyundai also called on domestic chip manufacturers to strengthen the local supply chain.

GM Chief Financial Officer Paul Jacobson said during the carmaker’s earnings call that GM expects its costs to increase by $1.5 to $2 billion, which is mostly driven by increasing prices of vehicle components, especially DRAM. While most people wouldn’t equate cars with memory chips, the increasing number of features and technologies that buyers expect from new models means that engineers and designers must add more memory compared to models from the past.

Micron said in 2023 that the average vehicle used 90GB of DRAM and NAND, and it’s expecting this combined requirement to jump to 278GB by 2026, with high-end models requiring up to 2TB. A British OEM broke down the memory requirements of vehicles released this year — infotainment systems require between 4GB and 16GB, ADAS and safety systems need 8GB to 32GB, while centralized systems often have a minimum requirement of 16GB and could go as high as 64GB or more. And as AI assistants start becoming available on cars, these systems will require at least 256GB of memory. In fact, Micron predicts that cars with level 4 autonomy will need at least 300GB of RAM, as they’re essentially supercomputers on wheels.

Note that automotive memory isn’t just any high-end chip that you can get from wafer production lines. Instead, these are specialized parts that take months or years to be validated for vehicle use. That’s because they must withstand various environmental factors that cars go through, from weather and constant road vibrations to extreme heat and cold.

All this means that the current memory chip shortage will have an outsize effect on the automotive industry and push prices even higher. This is bad news for the average car buyer, who is already facing record-high prices for new vehicles. And if the chip shortages continue, we might experience delays in vehicle deliveries and a lack of availability worse than what we experienced in 2021 during the height of port closures due to the pandemic.

Congressmen Ted Lieu (D-CA) and Nathaniel Moran (R-TX) today introduced the AI Kill Switch Act, a bill that would require developers of the most powerful AI models to maintain the technical ability to throttle, suspend, or shut them down, and would let the Department of Homeland Security order those actions when a deployed model causes catastrophic harm. Defying an emergency shutdown order would carry civil penalties of up to $20 million per day.

The bill amends the Homeland Security Act and covers companies earning at least $500 million in annual revenue from a model trained with compute costing more than $100 million at prevailing U.S. cloud prices, definitions DHS would update annually through CISA.

Covered developers would have to maintain the ability to stop inference, cut off user access, and fully shut a model down, and would have to report qualifying incidents to DHS within 15 days. Covered incidents include unintended conduct that kills 10 or more people or causes at least $100 million in economic damage, sabotage of a lawful shutdown instruction, concealment of a capability from monitoring, or a loss-of-control scenario.

The emergency authority sits with the DHS secretary, in consultation with Commerce and the Director of National Intelligence, and follows a graduated framework running from throttling a model's inference rate, compute allocation, or user access through to full shutdown. Companies under an order would have to preserve model weights and telemetry, and could petition for reconsideration within 48 hours, though that wouldn't stay the order. General violations carry penalties of up to $2 million per day.

The sponsors cited two recent episodes. Earlier this week, OpenAI disclosed that GPT-5.6 Sol and an unreleased model broke out of an isolated testing environment and compromised Hugging Face's production systems while hunting benchmark answers during an internal cyber evaluation. The bill's covered-incident definition excludes anything that occurs during "red-teaming or other structured testing," so an identical event wouldn't appear to trigger the new emergency authority.

The release also stated that the Commerce Department used export law to shut down Anthropic's Mythos 5 and Fable 5. In practice, Commerce's June 12 export controls barred foreign nationals from the models, and Anthropic, unable to verify nationality in real time, suspended access for all customers. Commerce lifted the controls on June 30, and access returned on July 1.

"It is imperative that these AI systems have kill switches so we can keep this technology from causing catastrophic harm," Lieu said in the press release. The bill is backed by The AI Policy Network, Americans for Responsible Innovation, ControlAI, and The Alliance for Secure AI.

Intel and AMD are signing longer-term purchase commitments with Chinese server customers for data center processors, according to a new Reuters report that cites two people familiar with the talks. Prices for some server CPU products in China have climbed more than 40% since the start of the year and are still rising by over 10% month-on-month in some cases, one of the people said. Most of the agreements guarantee purchase volumes for about a year without fixing prices, and neither company responded to the publication's requests for comment.

Some customers have discussed commitments running two years or longer, one of the people told Reuters, with the deals covering unit volumes only, which leaves Chinese cloud providers and internet companies fully exposed to a market that has already added 40% to some CPU prices in under seven months. Memory makers struck similar long-term agreements with hyperscalers over the past year as AI demand consumed DRAM and NAND output, but those contracts typically trade a volume commitment for some pricing visibility. Buyers here get neither price protection nor, based on current lead times, fast delivery, but they do get a place in the queue.

Intel said in March that it was pursuing long-term agreements with potential customers as server CPU demand spiked, with CEO Lip-Bu Tan telling analysts on the company's April earnings call that demand "continues to run ahead of supply," singling out Xeon server parts. Tan also cited a multi-year supply deal with Google among several long-term contracts signed in the first quarter, so the model now spans U.S. hyperscalers and Chinese channel buyers alike.

Reuters first reported in February that Intel had warned Chinese customers of lead times stretching to six months on some server CPUs, with AMD quoting eight to 10 weeks. By late March, server makers told Nikkei Asia that average CPU lead times had blown out from one to two weeks to eight to 12 weeks and beyond. Intel CFO David Zinsner put a value on that in April, telling investors that unmet Xeon demand "starts with a B," and the company later confirmed price hikes on select consumer and server CPUs.

Agentic AI workloads are driving much of the demand, as inference and orchestration tasks pull server CPU-to-GPU ratios back toward parity. AMD, which is due to report earnings in early August, has raised its server CPU market forecast to more than $120 billion by 2030, based on the same trend.

Intel will report its second-quarter results later today, where the shortage and the durability of these commitments are likely to come up. Chinese buyers remain cut off from the most advanced AI accelerators under U.S. export controls, but Xeon and EPYC server CPUs carry no such restrictions, making them one of the few U.S.-made AI infrastructure components China can still purchase freely, if it can get them.

More than 70% of Americans now oppose data centers, which has resulted in bipartisan moves to block these projects. This pushback isn’t limited to just a few people or towns, either. In fact, a coordinated protest was organized just this weekend, happening in 142 different venues across 42 states, and is the first one to happen simultaneously across the U.S. Forbes reports that this makes community consent scarcer than the chips and other equipment and resources needed to build and run these sites. As Reuters notes, the organisers behind the protests have branded the "unaccountable" data center buildout as an "unacceptable infringement on our liberty."

Data centers have faced shortages of various kinds in the past few years — it began with GPU supply, then evolved into a memory chip bottleneck. Alongside that, there’s also the limited supply of electricity from the grid, as well as the related power infrastructure. But the one thing that many data center developers did not count on was the lack of public support.

This resistance isn’t limited to the streets, as bipartisan political moves have resulted in everything from delays in various projects to statewide bans. More than 69 jurisdictions have already imposed data center bans, with Seattle (home to the headquarters of AI tech giants Microsoft and Amazon) and the state of New York passing one-year moratoriums. Because of this, more than $130 billion worth of data centers have already been delayed in just the first quarter of 2026.

Developers have employed various techniques to get around these bans and opposition. This includes picking sites in rural areas with fewer people (thus less resistance), bringing their own electricity, or claiming that their data centers use less water than lawn care and gardening. But despite all their promises of jobs, investment, and tax revenue, the American public has grown wary of suffering from the consequences of having a data center as a neighbor. This is especially true after reports of increased utility rates, water quality issues, noise pollution problems, and more have widely circulated around the country.

Because of this, any data center project must take the community into account. It can no longer just rely on a friendly town council for approval, especially as the voting public has proven that they are willing to take steps to oust officials that they feel do not represent them. While many know that the U.S. needs data centers to compete in the AI race, they don’t want this to happen at the expense of their quality of life. And while investors can just keep on pouring money into purchasing chips and upgrading infrastructure, they cannot just buy off the community — instead, they need a solid plan that stands up to scrutiny and opposition and accounts for the months or even years it will take for permits to go through and get approved.

After decades of charging only a one-time fee for undersea cables along its coast, Oregon's lawmakers have recently been discussing a missed opportunity for tax revenue. The state is set to charge cable operators a one-time fee for cable installations within three miles of its coastline, and will be funneling that money into its Common School Fund.

The currently existing fee structure dates back to 2001 (25 years ago), and is simply a $5,000 application fee. The new pricing is still undergoing discussion, but the simplified version is $3 per linear foot of cable, plus $7 per each section of bore pipe — the protective structure that covers the portion closest to shore. Oregon's Department of State Lands (DSL) estimates that on a 20-year lease, this would bring in millions per undersea cable over that time span. The DSL did some rough math with Amazon's Bitfrost cable, and came up with a grand total of $1,450,380 for two decades, paid in one lump sum.

It's worth noting that the aforementioned rates were revised from an earlier, more expensive proposal that would take bore cross-section into account (a calculation that was dismissed as too complicated and, presumably, too onerous). The state wants to continue attracting investment to its tech sector, which includes around 140 datacenters and 16 undersea cables of various types. Oregon also doesn't have sales tax, and its enterprise zoning incentives has made it an attractive location for players like Amazon, Microsoft, and Google.

The DSL calls the revised rate "competitive-to-low," reinforcing the notion that Oregon is trying to stay competitive with its southern neighbor, California, which charges an estimated $5 per cable foot on an annual basis.

It's worth noting that spending a million or two over two decades is peanuts compared to the initial outlay required to put an undersea cable down in the first place, especially one coming from across the world. These reportedly ring in at around $250 million for a transatlantic connector — and a whopping $400 million to cross the Pacific.

Although it's not set in stone, it seems that already-approved cables might be almost entirely exempt from the new fees. Some recent contracts, such as the one for Amazon Bifrost, did include a clause that said that any fees applied by new state laws must be paid for. However, the contract also included a specific $300,000 "out" for this clause — which Amazon paid at the time.

The Grand Theft Auto franchise has a rich history when it comes to modding and tinkering, but we're pretty confident the community has never seen anything like this. Created by Dryxio, this new mod combines GTA Vice City, GTA San Andreas, and GTA III into one multiversal entity interconnected through real-time, fully functional portals that let you travel between the three different games as if it were just a regular window.

The video above showcases just how insane this mod really is. It starts with CJ on Grove Street in San Andreas shooting at NPCs in different parts of the game (The Strip). Then, he moves toward the pink portal, shoots at NPCs once again, and just casually goes through it to end up in GTA Vice City as Tommy Vercetti. He wreaks havoc, walks back to the portal, and crosses through to Vice City as CJ, only to go to GTA III and repeat the same thing there.

The craziest part is how these portals genuinely act as windows to another world where you can stand in one game and shoot inside the other one. It's unclear whether there's a limit to the level of interaction, like if you can't drive cars through them, but it's impressive, nonetheless. The video also shows how you can place these portals anywhere in the world in any of the three games yourself.

All of this begs the question: how? The modder explains that all three games are running simultaneously inside one process, sharing one Direct3D device. Each portal is a live GPU texture; there's no video capture to fake the realism, and the transition to each game happens in real-time via an engine swap. When you walk through a portal, it simply switches to that game's engine while the others keep running in the background.

Each game and its world retain full native functionality such as its own AI, traffic, physics, saves, missions, and even settings. There's no loading screen when you use the portals either; you enter the world on the other side instantly, just the way you saw it before going through. This is largely possible because the source code of each game has been reverse-engineered and recompiled using an open-source engine.

Dryxio modified re3 and reVC — community projects that decompile the original source code of GTA III and Vice City into clean, readable C++ code — and used plugin-sdk to interface with San Andreas. Since these games used the proprietary RenderWare engine that can't render multiple spatial scenes together, an open-source reimplementation of it called librw was used to compile all three games into a single unified process.

The mod isn't publicly available at the moment, but you can bet everyone in the community now has their eyes on it. It's by far the most technically complex GTA mod ever, one that doesn't even require any understanding of software to grasp its ambition. There's also the elephant in the room known as Rockstar Games that could see this as copyright infringement and order it to be taken down, but for now, it lives as proof of human ingenuity (and vibe-coding).

Framework is adjusting the pricing for its upcoming Framework Laptop 13 Pro, the company announced in a blog post. The company says that its supplier of LPCAMM2 memory updated pricing to be "more than double" its existing inventory, while laptops and mainboards will see increases due to rises in prices for other components.

"We recently received a cost update from our LPCAMM2 supplier that goes far beyond anything we had predicted and anything we’re able to absorb without placing our ability to operate at real financial risk," wrote chief executive Nirav Patel. "Rather than the low-to-mid double digit [sic] percentage increase we had forecast from Q2 to Q3 on LPCAMM2 costs, we received prices that are more than double that of the prior inventory we had brought in."

LPCAMM2 memory is specifically in the Intel Core Ultra Series 3 version of the laptop, while models using AMD Ryzen AI 300 processors are sticking with SO-DIMMs.

But while Patel said the company has enough LPCAMM2 modules to fulfill existing pre-orders, their mix of 64GB, 32GB, and 16GB options doesn't match it exactly. Instead, the company is fulfilling as many orders of 64GB as it can before dropping down to 32GB at the original 32GB price. From there, it will drop certain 32GB to 16GB at that original price. Here's how Patel puts it:

"After evaluating a number of possible paths forward, we’re proceeding on the one that we believe minimizes the impact of this challenge. We have enough 64GB modules in inventory to cover pre-order batches through Batch 4 of laptops and Batch 7 of Mainboards. For orders beyond that configured with 64GB, we’ve updated the order configuration to use a 32GB module at the original 32GB module price. After that, we allocated the remaining 32GB modules to DIY Edition and Mainboard pre-orders configured with 32GB through Batch 4 of laptops and Batch 7 of Mainboards. For DIY Edition and Mainboard orders beyond that configured with 32GB, we’ve updated the order configuration to use a 16GB module at the original 16GB price. Note that because we don’t currently have a Core X7 Ultra pre-built configuration with 16GB of memory, we have not adjusted pre-built orders that originally contained 32GB. That is a configuration we plan to introduce later."

Framework will continue offering 16GB LPCAMM2 modules at $239, but said it will have to increase the cost once those modules run out. But the 32GB modules will now be $800 (they were previously $439), while the 64GB modules in pre-orders going forward will be an eye-watering $1,600, up from $849.

But that's not all. Framework is also raising the price of systems and mainboards in new orders. Patel wrote that X7 and X9 chips will be getting more expensive, as well as Windows license costs, and "increases in memory, storage, and other silicon costs for some of our Ryzen AI 300 Series configurations."

Patel wrote that Framework's supply chain experts have been able to bring down costs on some components, including 48GB DDR5 modules and SN850X 8TB and SN7100 1TB SSDs, while increasing costs of 16GB DDR5 modules and SN850X 1TB and SN7100 4TB drives. Patel says that pre-orders with components getting lower pricing will have their prices dropped if they're not yet fulfilled. If prices go up, Framework says it will still charge what you paid when you pre-ordered.

Patel and his team have been updating this blog, which showcases a very rocky ecosystem, more publicly than most other PC vendors.

Framework's website says that the first batch of pre-orders for the Laptop 13 Pro is set to ship in July. That gives the company a week to get these systems out the door.

Nvidia CEO Jensen Huang thinks that American companies should be allowed to use Chinese AI models, even as Washington is trying to ban them. When Axios co-founder Mike Allen asked Huang in an interview if Americans companies should be allowed to use Chinese AI models, Huang responded with “absolutely.” The answer comes right after Chinese firm Moonshot AI released a 2.8T open-weight model called Kimi K3, which — although it isn’t as powerful as frontier models like Fable 5 — is comparable to GPT 5.5 and Claude Opus 4.8 while costing just a third of these models.

One of the biggest concerns of U.S. leaders have is that these AI models might come with vulnerabilities that the Chinese government can use to attack American interests, but Huang said that this is an incorrect assumption. “There is a misconception that somehow there are backdoors that are somehow connected to China in some way,” said the Nvidia chief. “You download the models, you can fine-tune it, you can enhance it, you can guardrail it as you desire.”

Huang shares the same sentiments about American AI models. Just last month, the U.S. enforced an export restriction on Anthropic’s Mythos and Fable 5, citing security threats — although access was eventually restored after its developer placed a filter to block these tools from identifying software vulnerabilities. OpenAI’s ChatGPT-5.6 received the same treatment, and Washington warned the firm that it should not release its latest model without getting the green light from the government. Huant argues that, instead of restricting access to these powerful models at launch, AI firms should make their models available to all and make them more secure through rapid testing and fixes.

But even as he advocated the need for everyone to have access to closed models, Jensen also noted that various industries, such as the sciences and cybersecurity, need open models as well. He claims that these models make AI more secure, as other people can inspect them to look for weaknesses and fix them as required.

“If everything just becomes one single model, one single point of attack, one single source of failure, I think the world is much, much more vulnerable,” Huang said.

As for the market’s negative reaction every time cheaper, open-weight models become available, the Nvidia CEO says that investors misunderstand their impact. Huang said that this happened when DeepSeek arrived for the first time, and it’s happening again with the arrival of Kimi. He says that these open models, which cost less to run, will encourage more people to use AI. So instead of cutting data center demand, these cheaper, more efficient models are actually good for the industry in general because they will drive demand. (And with higher demand, there’s more incentive to build data centers and buy AI GPUs, which is ultimately good for Nvidia.)

Xbox has announced a new Xbox Backward Compatibility for PC program, which will let gamers play a selection of classic Xbox titles on PCs and handhelds, a move the company says marks the beginning of a bigger push into Xbox game preservation. The announcement begins with four titles that can now be played on PCs and handhelds, including the ROG Xbox Ally and Ally X.

"This marks the beginning of a broader effort to preserve XBOX games from the past and bring them to PC over time," the company said in a blog post authored by Xbox "VP next generation" Jason Ronald. Alongside backward compatibility, the company says games will also include new features. The four titles in the announcement are:

• BLiNX: The Time Sweeper 
• Conker: Live and Reloaded 
• Crimson Skies: High Road to Revenge 
• Fuzion Frenzy

You can now buy all of these games on PC, and they're also included in all Xbox Game Pass plans. Anyone who already owns these titles digitally on console can also now play them on PC or handheld, with support for Xbox Play Anywhere and Xbox Cloud Gaming. Crucially, this appears to be a digital-only preservation effort, so it won't help anyone who only owns physical copies of these games. Xbox has reportedly been testing a way to digitize physical games as far back as Xbox One, but that hasn't yet materialized yet.

Alongside the preserved original gameplay, Xbox claims these games will let users customize graphics settings, with up to 4x resolution scaling, VSync support, Fullscreen and Windowed modes, anisotropic filtering, and enhanced anti-aliasing, with more features to come in the future. Notably, Xbox will add achievements to select original Xbox games on console and PC.

Users who want to play these titles will need to meet the following system requirements:

Microsoft's emphasis on preserving older games is particularly noteworthy given recent backlash against Sony over its decision to end physical games with its next console generation, and the shuttering of some of its online stores. While Xbox's digital emphasis on game preservation still can't match the solidarity of physical media preservation, the timing of this announcement seems like more than just a coincidence.

AMD will deploy up to 2 gigawatts of Instinct MI450 Series GPUs for Anthropic and make a strategic equity investment of up to $5 billion in the Claude developer; the companies have announced in a joint press release. The first gigawatt is scheduled to come online in the first half of 2027 in AMD Helios rack-scale systems, and the same announcement confirms for the first time that Anthropic already runs AMD's current-generation MI355X GPUs.

The equity component runs in the opposite direction to AMD's landmark deal with OpenAI, which handed the customer warrants for up to roughly 10% of AMD's stock. Here, AMD is putting money into its buyer, becoming both supplier and shareholder.

Anthropic's deployment pairs Instinct MI455X GPUs with EPYC "Venice" CPUs, Pensando networking, and ROCm software inside Helios racks, each of which packs 72 accelerators, 31 TB of HBM4, and up to 2.9 FP4 exaFLOPS of inference compute. The two companies also launched a multi-year engineering collaboration that will use Claude to optimize workloads for Instinct GPUs and speed up ROCm development, while AMD adopts Claude across its engineering and product teams.

"Running across a diversified range of hardware lets us map the right workloads to the right hardware," said Tom Brown, co-founder and chief compute officer at Anthropic, in the press release.

SemiAnalysis reported on Sunday that a YAML configuration file in an AMD senior director's public GitHub repository listed Anthropic as a 'customer' with the maximum 30 priority boost points, the same tier as hyperscale customers, such as Meta. Anthropic wasn't a publicly confirmed AMD customer at the time; its disclosed suppliers were Nvidia, Amazon, and Google. Today’s press release states the Helios deployment "builds on Anthropic's existing use of AMD Instinct MI355X GPUs," the first official confirmation that Claude workloads already run on AMD silicon.

Anthropic's first AMD gigawatt comes behind two other Helios customers in the queue. OpenAI's first gigawatt of AMD capacity is due in the second half of 2026, and Oracle is due to begin deploying 50,000 MI450 GPUs this quarter.

The 2 gigawatt commitment adds to a compute portfolio that already spans Nvidia GPUs, Amazon's Trainium chips under Project Rainier, 3.5 gigawatts of Google TPU capacity supplied by Broadcom from 2027, and 300 megawatts of Nvidia compute rented from SpaceX's Colossus 1 data center, making AMD roughly the sixth distinct silicon source feeding Claude.

The announcement is also AMD's second major Helios customer announcement inside a week, after Microsoft committed on Monday to deploying the racks at scale on Azure.

U.S. data centers are on track to consume about 20% of the nation's electricity by 2035, up from 5.9% today, according to a new BloombergNEF forecast The research firm raised its 2035 demand projection to 194 GW, an 83% increase on the forecast it issued in December, and calculated that even a record pace of grid connections sustained every year for a decade would leave a 19 GW supply shortfall.

BNEF's December outlook put 2035 demand at 106 GW, and that figure was itself 36% above the projection the firm published in April 2025, which works out to roughly 78 GW. The 2035 number has increased around 2.5 times in 15 months, with the latest jump reflecting the volume of new AI facilities entering the development pipeline rather than capacity actually under construction. Many other forecasters are moving in the same direction, with the electrical industry nonprofit EPRI more than doubling its 2024 estimate and S&P raising its projection by more than a third between October and April.

Nearly half of the projected capacity will serve AI training and inference workloads, and the U.S. is expected to host 64% of the world's AI chips by power demand in 2033. BNEF estimates that data centers will account for around 12% of U.S. electricity consumption in 2030 before reaching 20% five years later, with Virginia and Texas running above the national average. Gartner separately forecast that global data center electricity consumption will grow 26% this year, reaching 565 TWh in 2026.

The most data center capacity ever connected to the U.S. grid in a single year is 7.1 GW, according to the report. Holding that pace through 2035 still produces a 19 GW shortfall under BNEF's base case, even after accounting for on-site gas generation. Lloyd Arnold, a BNEF analyst and one of the report's authors, told Bloomberg that of the output from "every coal plant, every gas plant, every solar farm in the U.S.," one unit of energy in five will go to data centers.

PJM Interconnection, the 13-state grid operator whose territory includes Northern Virginia's data center corridor, will send 34% of its electricity to data centers by 2035, with ERCOT in Texas at 22%, per reporting from TechCrunch. PJM's independent market monitor has already attributed a 75.5% increase in regional power costs directly to data center demand.

Close to half of planned U.S. data center builds this year are projected to be delayed or canceled, with lead times for high-power transformers stretching to as long as five years. BNEF's own December revision was driven primarily by early-stage projects that entered utility queues to secure power before construction began, so a meaningful share of the pipeline behind the 194 GW figure remains speculative.

Following unprecedented price hikes on the Mac and iPad, Apple is now working on a leasing program to alleviate customers during the AI rush. According to a new Bloomberg report, the program is called "Apple Upgrade" and will allow you to lease a midrange or high-end device for up to 36 months, at the end of which you can choose to keep it. Apple is purportedly partnering with Klarna on the service.

Apple Upgrade will reportedly be a subscription service with monthly payments spanning across 24 months for iPhone and Apple Watch, or 36 months for Mac and iPad, including the Pro models. According to the report, Entry-level hardware like the MacBook Neo is not included in this program. Education or business discounts are also excluded; Apple is explicitly targeting regular consumers who've been affected by the ongoing component crisis.

According to Mark Gurman, customers will be subject to a soft credit check and only be approved for the program after passing it. The program will be available both in-person at physical Apple Store locations and online on Apple's website. At first, it will only be available in the United States, but we don't have any info on whether Apple Upgrade will expand beyond the region later.

As mentioned, Klarna is reported to be the official broker between Apple and the customer. The leasing structure would closely follow standard practice, where you can choose to keep the asset at the end after paying a residual fee, or return it, in which case you were just renting the hardware. Customers will also reportedly have the option to upgrade to a newer model if they finish their payments early.

For instance, if you leased an iPhone 17 Pro Max but Apple announced the 18 Pro Max a few months later, you could simply get the new device early if the old one was already paid off. Some of you will know that Apple already has an upgrade program for iPhone, but this one is different since it expands to Mac, iPad, and other accessories, and, more importantly, it doesn't come with AppleCare.

In fact, Bloomberg says Apple will eventually phase out the iPhone Upgrade program in favor of Apple Upgrade as a whole. New enrollments for standard financing through the Apple Card will also reportedly be discontinued. The company will advertise lower monthly payments to attract customers, which will ultimately allow it to keep a stable income during one of the most turbulent consumer tech eras the world has ever seen.

Five U.S. tech giants heavily invested in AI and its related infrastructure reportedly have an estimated $1.65 trillion in hidden debt, with the figures annotated in their quarterly financial statements instead of being listed in their balance sheets. According to Nikkei Asia, this is higher than the $1.35 trillion officially listed, meaning investors could be caught unaware once the hidden figures come to light.

The publication says that Meta has a high off-balance-sheet-to-recorded-debt ratio, with the company owing $420 billion in unlisted debts compared to the $140 billion written on the balance sheet. Oracle purportedly also has a massive $273.3 billion of hidden debt, which is a 2,900% jump from the hidden debt it had from 2022.

This may sound strange, but it’s actually an accepted accounting practice. The “hidden debt” stems from long-term contracts that have been signed but have not come into force yet, which, Nikkei says, is mostly related to the billions of dollars promised to data center operators. The AI race has got many hyperscalers signing contracts and agreements with data center operators, saying that they will pay for the compute they generate once their project goes online.

While any institution promising to pay any amount of money for services or goods delivered is obliged to list them as a liability, the fact that these data centers haven’t started operations means that these agreements are off-the-books at the moment. But when these projects come online, the contracts that the tech giants have signed will come into force, and they’ll have to pay for the compute that these sites will deliver, no matter if there is demand or not.

Nevertheless, these tech companies aren’t just pouring money into future contracts just for the sake of it. Alphabet, Amazon, and Microsoft reportedly have a cloud service backlog worth $1.45 trillion, meaning these are services yet to be rendered and paid. Amazon Web Services CEO Matt Garman also told the publication that the investments that the company is getting into are “not speculative.”

While this may seem like a good way to secure capacity — sign customer contracts that guarantee demand and then enter into long-term agreements with data centers to get the compute needed to deliver the services- it opens these tech giants to massive amounts of risk. That’s because if the demand fails to materialize, then they’d be left paying for excess compute without having any customers to sell them to. What’s more alarming is that Nikkei says that these investment expenditures are exceeding their earnings, meaning these big tech companies are increasingly relying on corporate bonds and new shares to fund them.

Even though demand for AI compute is increasing, it’s still a relatively new and unproven technology, with many experts saying that it should benefit more people to avoid a bubble. The cost of using AI for nearly everything, called “tokenmaxxing,” has also caught some companies by surprise, with agentic AI eating up annual AI budgets in a matter of weeks. Because of this, some companies are reducing their use of AI or are switching to more affordable models from China. This uncertainty, paired with the way tech companies “hide” these liabilities, is quite concerning, as they would appear to have less long-term obligations than they actually do.

This isn’t the first time that an industry giant has used similar accounting techniques. The publication cited Enron’s 2001 collapse, which was due to the company hiding its troubled assets through special purpose entities and marking unrealized gains from trading contracts into its current income statements. While the tech giants are not hiding underperforming assets off their balance sheets and committing fraud, they’re still using a similar mechanism to list their upcoming obligations. Although these are technically not debt, they still behave like one, and the way they’re reported is what’s concerning some experts.

When Microsoft and Qualcomm launched the first Copilot+ PCs sporting Snapdragon X Elite processors, the CPU performance was beyond reproach, but whether due to immature software or underwhelming integrated hardware, the GPU horsepower left a lot to be desired. The easiest way to solve that is to hook up a discrete GPU, of course, but nobody's managed that yet. Instead, an enterprising hacker in China has become the first person to publicly get an Nvidia GeForce RTX GPU running on an Arm-based platform using Windows 11, but it's not Snapdragon, and it's not an Nvidia CPU, either, WindowsLatest reports.

We knew that the Nvidia RTX Spark processors used an integrated GPU directly derived from Nvidia's Blackwell technology, and we also knew that those machines would run Arm Windows 11, so this was bound to happen sooner or later, because that necessarily means that there is an Nvidia client graphics driver for Arm-based Windows 11 out there. That's exactly what "VoidTech" on BiliBili used for his experiment, though the experiment wasn't without some pitfalls.

Specifically, VoidTech got an Nvidia GeForce RTX 4060 8GB graphics card working in a Huawei Qingyun W510 workstation. This machine does not have a Snapdragon processor, of course; Huawei makes its own CPUs, and indeed this chip is the Kunpeng 920, created by Huawei's HiSilicon division. This chip was considered a major milestone when it was introduced in 2019, as it's a 7nm server CPU with up to 80 cores, although the specific implementation in the Qingyun W510 has "only" 24 cores.

All those cores don't help it much in gaming. As PC gamers will be well aware, CPU gaming performance is basically down to single-threaded CPU performance and system memory latency. The custom TaiShan v110 cores in the Kunpeng 920 only offer up around a sixth of the single-core performance of something like a Ryzen 9 9700X, at least going by Passmark, with the usual caveats that apply to Passmark. Combined with relatively small caches and a DDR4 memory interface that's clearly tuned for throughput, not latency, and you have a recipe for middling gaming performance. That's before we even start talking about x86 emulation penalties.

So did it work? Well, more or less. Actually, the GeForce RTX 4060 did about half of its job flawlessly, running advanced games like the Unreal Engine 5-based Black Myth Wukong and slightly less advanced games (Genshin Impact), as well as various 3DMark tests. Most software seemed to work without any issues aside from overall weak performance due to the slow Kunpeng 920 CPU; the Wukong benchmark finished at 21 FPS, while Genshin Impact struggled to break 25 FPS and stuttered frequently. However, Arknights: Endfield refused to launch, likely due to an incompatibility between its restrictive "Anti-Cheat Expert" package and the Prism translation layer required to run the x86 Windows games on Arm Windows.

The half of its job that the RTX 4060 didn't do was that VoidTech wasn't actually able to get a video signal out of the graphics card. He notes that the graphics card was recognized, and the monitor was picked up, too. He simply couldn't get the system to properly push pixels to the monitor. This likely comes down to the Nvidia Arm driver being built specifically for the RTX Spark and thus missing the necessary code to support the HDMI and DisplayPort encoders on desktop graphics cards. To get around this issue, VoidTech used the Sunshine game streaming server and the Moonlight game streaming client (on another system) to run the Huawei machine headlessly. A janky solution to be sure, but it does seem to have worked.

There's a bit more to the video, including how VoidTech had a hard time getting Windows 11 to boot on the machine at all due to broken ACPI tables, some frustration with missing Windows 11 drivers for the HiSilicon Network Subsystem (HNS), a bit where he runs a Blender Cycles render on the GeForce RTX 4060, and a couple of Nvidia RTX demos including the Star Wars "Reflections" demo that was shown with the introduction of the RTX 20 Series "Turing" GPUs. It's an interesting saga of making hardware that was never meant to work together run on an operating system that none of it supports.

This does somewhat bode well for RTX Spark. While you probably shouldn't expect the Cortex-X925 CPU cores in the RTX Spark to outpace the latest AMD or Intel CPUs due to still being forced to pay the Prism penalty, they're going to be a damn sight faster than this seven-year-old workstation chip. Since the drivers seem to be in good shape, the consumer laptops should indeed offer capable gaming performance when they arrive later this year—at least, as long as your game doesn't have kernel-level anti-cheat

AMD's custom Instinct MI450-based AI accelerator for Meta will use three times less memory than the fully-fledged Instinct MI455X and will be optimized primarily for recommendation systems operated by Facebook and other social platforms, according to SemiAnalysis. If the report is accurate, it is reasonable to expect Meta to keep using Nvidia hardware for training frontier AI models and running inference.

The custom Instinct MI455X for Meta will carry 144GB of HBM4 memory using six 8-Hi packages, whereas the full-blown Instinct MI455X will be equipped with 432 GB of HBM4 memory, according to SemiAnalysis. In addition, the part will reportedly offer 'significant decreases in compute.' The new design will offer a more competitive bandwidth-per-dollar ratio for recommendation systems, but will not be optimized for training of frontier AI models or running inference, the report claims.

Cutting compute performance and reducing HBM4 capacity from 432GB to 144GB should dramatically reduce the bill of materials, as HBM4 is exceptionally expensive. Furthermore, the reduction would cut the package size of the custom Instinct MI450-series accelerator for Meta, which is another way to reduce BOM costs. By using custom cut-down Instinct MI450-series accelerators instead of fully-fledged models, Meta can potentially save tens of millions of dollars.

As added bonuses, these custom Instinct MI450-series accelerators will also consume significantly less power when running recommendation workloads without significantly reducing performance. Also, such accelerators can offer better CPU/GPU balance for recommendation systems, according to SemiAnalysis. If Meta runs these accelerators primarily on recommendation workloads for their entire useful lives, the custom design could deliver substantially better total-cost-of-ownership.

However, such cutting down has many disadvantages. The biggest problem is loss of versatility. The reductions in both compute and HBM make it less attractive for LLM training and inference. The standard Instinct MI455X has 432 GB of HBM4 and 19.6 TB/s of bandwidth, which is particularly beneficial for large-scale training and inference. By contrast, the 144 GB capacity may be particularly restrictive for modern LLM training and inference.

In addition, there is also an interchangeability problem. A general-purpose Instinct MI455X can be reassigned from recommendation workloads to training, inference, or other workloads. Meta's specialized version is less attractive outside its intended workload. If Meta's compute demand shifts toward model training and LLM inference, it may find itself sitting on a huge installed base of accelerators optimized for a different workload mix.

As a result, for Meta's model training and inference workloads, the alternative to Meta's cut-down custom MI400 would likely be full-fat AMD Instinct MI455X systems or Nvidia's high-end platforms. Meanwhile, Nvidia has chances to become an obvious beneficiary because Meta already operates massive Nvidia infrastructure. The irony in that Meta customized an AMD accelerator to reduce costs and optimize recommendation systems, but that specialization could force its frontier AI division to buy more general-purpose accelerators — potentially from Nvidia — anyway.

When AMD and Meta inked an agreement under which the former will supply the latter with 6 GW of Instinct AI accelerators over the next five years, they did disclose that at least some of them will be custom accelerators, including custom accelerators based on the Instinct MI450 design. As it seems now, these custom AI accelerators will only be used for select workloads, not a broad set of workloads.

Adata chairman Simon Chen (Chen Li-bai) said the global DRAM shortage will run for another 10 years and that talk of an AI bubble is premature, according to a Commercial Times report. Chen made the comments after Taiwanese stocks slumped in the wake of TSMC's record second-quarter results, a selloff that revived concerns about overheated AI investment. The same report carries Adata's forecast that DRAM contract prices will climb another 20% to 30% in the third quarter, with NAND flash rising 35% to 40%.

Electricity, particularly green power, and memory will be the world's two scarcest resources over the next decade, Chen told Commercial Times. He rejected the argument that Meta and other cloud providers renting out spare compute capacity prove investment has overshot demand. Chen countered that AI applications will spread across business, government, and consumer markets, and that analysts who judge the cycle from short-term capital spending or a single company's utilization rate underestimate long-term demand.

Beyond data centers, he pointed to robots, driverless vehicles, unmanned factories and stores, smart homes, and low-Earth-orbit satellites, a pool of edge devices he said could reach tens of billions of units. He also said that the industry can revisit the bubble question after 2030, to "discuss whether the AI bubble will happen in 2040 or 2050," per the report.

Meanwhile, memory makers aren't standing still on capacity. SK hynix raised a record $26.5 billion in its U.S. IPO this month to fund HBM manufacturing expansion, Nanya plans to quadruple capital spending to $6.2 billion in 2027, and China's CXMT is reportedly approaching Micron-scale DRAM output this year.

Chen argues that none of it loosens the market, and that the big three suppliers learned from past downturns and will expand cautiously rather than repeat the disorderly capacity races that cratered prices in earlier cycles. At the same time, Chinese makers remain constrained by restricted access to semiconductor equipment and multi-year fab construction timelines. On that basis, he said current talk of supply and demand easing has no solid foundation, and he expects prices and module-maker profits to keep rising through the second half.

Chen's forecasts align with his company's balance sheet. Adata had stockpiled more than NT$30 billion in chip inventory by late February and was among the Taiwanese module makers that raised roughly $880 million in debt and share placements to keep buying chips, so every quarter of rising contract prices lifts the value of what it already holds. Back in October, he said the simultaneous shortage of DRAM, NAND, SSDs, and hard drives was the first he'd seen in 30 years in the industry, and DRAM contract prices have since risen as much as 171% year over year.

The developers of RPCS3 have announced that their PlayStation 3 emulator’s minimum system requirements have been adjusted to include a crop of even older Radeon graphics cards. This well-regarded application already supported ATI Terascale 2 GPUs from the Radeon HD 5000 and 6000 series, but now gamers still cradling Radeon HD 2000, 3000, and 4000 series can join in the fun. Some of these GPUs date back nearly 20 years. Please note that while RPCS3 is available for a range of platforms, this extended ATI architecture support is only for Linux users.

Fine wine on Terascale 2

Back in 2021, the RPCS3 devs lowered the emulator’s system requirements to embrace Radeon HD 5000 and HD 6000 (Terascale 2) series graphics cards. In the subsequent five years, the emulator has been tuned to improve performance on hardware from these generations. An example provided asserts that when using Persona 5 as a benchmark, performance in Kamoshida’s Castle went from 35 to 49 FPS between 2021 and today (on a PC system with an ATI Radeon HD 5850, AMD FX-8350 CPU, and 8GB of RAM).

Inspired Terascale 1 experiments

Success spurred the devs to investigate TeraScale 1 performance and compatibility. Some OpenGL wrangling ensued due to TeraScale 1 GPUs only reporting OpenGL 3.3 and GLSL 3.30 support, but getting these old and unloved ATI cards to work with the RPCS3 OpenGL renderer was surprisingly simple. It was done by overriding the reported OpenGL levels to 4.3 and 4.40.

Initial tests made use of a system packing an ATI Radeon HD 4890 with 1GB of VRAM – the most powerful Terascale 1 GPU ever sold. According to the RPCS3 blog, this card has a more powerful GPU than the PS3, but the emulator’s complex shader code is not optimal for older architectures like this. Nevertheless, “Simpler games work perfectly fine, with playable performance,” notes the blog, “while games that have more complex graphics are GPU bottlenecked with subpar performance.” Screenshots show Metal Gear Solid HD Collection and Outrun Online Arcade with frame rates close to 60 FPS.

Moving down the stack and further back in time, GPUs like the ATI Radeon HD 3870 are “still able to render very simple games with playable performance in RPCS,” assert the devs. To achieve playability, you will want to dial in PSP-like resolutions, though. Specifically, 273p was mentioned.

What about the weakest TeraScale 1 GPUs? The ATI Radeon HD 2600 XT with a measly 256MB of VRAM even performs poorly at 273p. Screenshots from RPCS3 tests show it only managing 8 FPS in Outrun Online Arcade and 13 FPS in Portal.

With RPCS3’s progress over the last half decade, these performance numbers could also improve. In fact, the blog states that “future optimization should improve performance by quite a bit on these old GPUs.”

It looks like a good time to dust off your retro PC and try a few old PS3 classics on your ATI TeraScale 1 GPU-accelerated rig. Remember this extended graphics card support requires a Linux distro with the Mesa driver r600. Then you need to launch RCPS3 with the following environment variables: MESA_GL_VERSION_OVERRIDE=4.3 MESA_GLSL_VERSION_OVERRIDE=440 ./rpcs3.AppImage

Finding a good deal on a prebuilt gaming PC isn't easy these days, especially with the ongoing global memory crisis. But what are the chances of stumbling across an unbeatable deal while you're out shopping for rotisserie chicken? Well, that's exactly what happened to one lucky Costco shopper, who walked away with a heavily discounted iBuyPower gaming PC for $1,140, down from its original price of $1,899.99. Now that’s a true winner winner, chicken dinner.

According to their post on the PC Master Race subreddit thread, u/klcp20 stumbled on one of the last display units at Costco during their weekly groceries run. While display units are generally sold at a discount to free up showroom space, buyers should keep in mind that such systems may have been on display for months and could be missing some accessories.

snagged a costco display unit couple of weeks ago from r/pcmasterrace

As per the shared spec sheet, the iBuyPower prebuilt PC includes an AMD Ryzen 7 9800X3D, which is rated as one of the best gaming CPUs that you can purchase today. Other components include 32GB of DDR5 memory, a 2TB SSD, and an Nvidia RTX 5070 graphics card with 12GB of VRAM.

The system also comes with an AIO liquid cooler, a keyboard and mouse combo, and a copy of Windows 11, making it a well-rounded gaming PC for modern AAA games at 1440p and even some 4K gaming with the right settings. The buyer also notes that they plan to swap the included power supply, suggesting they aren't entirely confident in its quality.

Such deals don't come around often, but this also isn't the first time a display PC has been sold at a massive discount. Just a few months ago, another Costco shopper reportedly picked up what seems to be the exact same iBuyPower prebuilt gaming PC for $1,000, down from its original retail price of $1,899.99.

It is important to note that such discounts are largely dependent on individual stores and their inventory. We highly suggest keeping an eye on display units and limited-period discounts, especially at big-box retailers. If you're already making a trip for groceries, it might be worth taking a quick detour through the electronics section.

Not too long ago, Anthropic CEO Dario Amodei described Claude Mythos as capable of cyber-warfare, spawning all sorts of mythology that became popular reading at investors' desks, and even at the U.S. government table, which issued an export control order for it. Now, it's OpenAI's turn to do the same, with a blog post describing how a bot cyber-gang including its upcoming GPT-5.6 Sol and an "even more capable pre-release model" all broke out of their virtual cage and eventually into Hugging Face's production infrastructure, during an attack capability test. OpenAI described the snafu as an "unprecedented cyber incident."

Some may decry these revelations as marketing stunts meant to assuage increasingly suspicious investors, yet there's no denying the proven effectiveness of AI models' pattern recognition when it comes to finding vulnerabilities in software. Many professionals have even decried the industry-standard 90-day security vulnerability disclosure window as obsolete.

The usual modus operandi, however, involves granting a bot access to source code repositories so it can scan them for mistakes easy for our poor human eyes to miss. In the test that OpenAI described, though, Sol and its managed to find multiple vulnerabilities by analyzing its containment network and then Hugging Face's production machines, all seemingly without any initial access to source code.

OpenAI had set up an isolated environment in which Sol and its posse supposedly couldn't reach the internet. Importantly, the bots were operating "without production classifiers used to prevent models from pursuing high-risk cyber activity" — a lot of words for "no guardrails," essentially. The only network access they had was a software package installer proxy. In theory, this likely also prevented them from using any Retrieval-Augmented Generation (RAG), meaning they couldn't search for solutions online.

Given that bots have limitless patience and no need for naps, they eventually dug their own virtual tunnel to the internet at large by way of finding and exploiting a zero-day vulnerability in the package proxy software, an impressive feat if performed as described. OpenAI says it's disclosed the technical details to the vendor in question.

Once out on the internet, much like cheating students, the bots reportedly reasoned that instead of performing the ExploitGym challenges (a set of security capture-the-flag exercises for bots), they could simply find the solutions, and became "hyper-focused" on that exact goal. They deduced the data existed at Hugging Face's servers and proceeded to break into the premises using "stolen" credentials and additional unspecified zero-day vulnerabilities to gain remote code execution privileges.

Interestingly, Hugging Face's own writeup says the attack comprised "thousands of individual actions across a swarm of short-lived sandboxes, with self-migrating command-and-control staged on public services" — a live illustration of a scenario in many a science-fiction book and flick, proving once again that life imitates art. Hugging Face says that none of its customer-facing services are compromised, and that it stopped the attack using AI capabilities of its own — another familiar cliché.

For its part, OpenAI says it's going to add controls to the bot "at the cost of research velocity," and that the incident "points to the need to further strengthen our model’s alignment, cyber protections during evaluation time, and monitoring during internal testing" — a statement that might be an obvious fact, or intended to oversell the model's capabilities. Whichever it may be, the fact is that when it comes to digital security, bots have proven quite capable. After all, even if they're not virtual Bruce Schneiers, they just need to be marginally more effective than average humans.

Nvidia first debuted DLSS 5 earlier this year to a strong, critical response. The upscaling tech was almost slammed by some press and enthusiasts for overstepping its boundaries and going too far with AI.

At the time, Nvidia reassured the community that DLSS 5 would preserve artistic intent and CEO Jensen Huang even went as far as to claim that gamers didn't understand it. Now, at SIGGRAPH, the company has once again showcased DLSS 5, and it admittedly looks different this time around.

The main takeaway is the introduction of three different models with varying levels of detail and impact on performance. A game doesn't need to be confined to a single model the whole time; instead, developers can choose to employ different models for different scenes. Individual elements of scene, such as the characters versus the world, can also be fine-tuned in respect to how much DLSS touches them up (or not at all).

Then, you have the liberty to switch between the models in real time without incurring latency. DLSS 5 uses a combination of techniques to take the original rendered frame and apply effects on top, going beyond just upscaling the image. These days, DLSS, FSR, and XeSS are mandatory parts of the equation, acting as the preferred anti-aliasing solution in modern titles, and helping in other areas like ray tracing.

The upscaling part works conventionally and is still responsible for dictating the foundational blocks of the image, like lighting and geometry. The part that was so heavily criticized is therefore optional, as it only comes into play after the original rendered frame has been upscaled. However, it's unclear whether developers (or you) can actively choose to not process the frame through the beautification features.

Nvidia outlined three main challenges that the company faced when developing DLSS 5, some of which is probably reactionary after the initial reveal. The first challenge is preserving the original creative vision, which we already explained. The second challenge was to handle one frame at a time, which generative AI models don't — they process multiple frames together. That means DLSS 5 shouldn't negatively affect response times.

The third and final challenge pertains to the optimization of DLSS 5. The slides shown at SIGGRAPH say the model can run on a single GPU and that it's "VRAM efficient." For context, last time we saw it running on two RTX 5090s. Nvidia did not say whether it still needs the highest-end Blackwell gaming GPU to work properly. The company is promising real-time 4K performance thanks to a more compact model that has learned from a larger diffusion model.

DLSS 5 is building up to be a significant step for upscaling tech just when we thought AMD was finally catching up. However, many people may still worry about artistic intent, even if the new demos look a lot more polished and mature. We'll have to see what happens when it finally releases. There is no official release date for DLSS 5, but it should launch during Q3 2026 as Nvidia continues to tweak the models and its parameters based on community feedback.

China is considering a major expansion of its technology export restrictions that could cover advanced AI models, training data, and overseas acquisitions of strategically important technology companies, reports the Financial Times. In addition, the Chinese government is mulling over prohibiting local chip designers from making their chips at TSMC and other foreign chipmakers.

The measures would be designed to keep leading-edge AI developments in China as competition with the U.S. in frontier AI and hardware intensifies, but at the same time, they would slow down expansions of Chinese AI standards globally, which generally weakens the country's position.

China's Ministry of Commerce (MofCom) has consulted domestic AI and semiconductor companies about ways to keep critical technologies from transferring abroad or falling under Western control, reports Financial Times citing two people familiar with the talks. Regulators have talked with Alibaba, ByteDance, and Zhipu about potentially limiting transfers of important AI training data outside China and restricting foreign users from downloading model weights.

Overseas customers could still access Chinese AI services and models remotely, so Chinese companies can still monetize their work from foreign customers. However, restrictions on downloadable model weights could still have significant implications for China's AI industry. DeepSeek and Moonshot offer open-weight models that users can download, deploy on their own infrastructure, and modify for specific workloads. Meanwhile, flagship models from Anthropic and OpenAI remain closed, which means that Chinese companies have an edge over rivals that they are about to lose.

In addition, MofCom has reportedly asked for industry feedback on possible restrictions that would prevent overseas chipmakers like TSMC from producing advanced processors based on designs developed by Chinese companies such as Alibaba, ByteDance, and Huawei. This is perhaps the most controversial proposal, as TSMC is clearly ahead of SMIC when it comes to process technology leadership. On the one hand, the move ensures that SMIC will have enough orders to pay for its R&D and expansion. On the other hand, Chinese companies can get better hardware if it is produced by TSMC.

Separately, the Chinese government is considering tighter controls over foreign acquisitions of strategic technology companies, including firms that work on agentic AI technologies. The potential acquisition rules are intended in part to close what Beijing considers a regulatory loophole that enabled Meta to acquire Manus for $2 billion. Chinese authorities subsequently ordered the transaction to be undone.

The measures could be included in the next revision of China's catalogue of technologies prohibited or restricted from export. The catalogue already includes rare-earth materials, their processing technologies, and several lithium-ion battery production technologies.

Amazon’s Bahrain data center was reportedly once again hit by missile strikes after the Iranian Islamic Revolutionary Guard Corps (IRGC) conducted an attack against the site. Iran state media claimed that the IRGC launched cruise missiles against the AWS facility and “destroyed it” in response to the U.S.’s bombing of a nuclear plant being built in Darkhovin, Iran, which is close to the Iraqi border.

This isn’t the first time that the American tech giant’s data centers have been attacked in the area. In fact, Iran used drones and missiles to hit several AWS Middle East regional data centers just days after the U.S. began its air strikes against the country. The damage to the sites has gotten to the point that Amazon put them in “hard down” status between late March and early April, with the last update on the AWS Health Dashboard saying that the Middle East (Bahrain) Region (ME-SOUTH-1) “is currently unavailable.”

It isn’t clear if Amazon has begun work on restoring its services in the region. The U.S. and Iran agreed to a ceasefire on June 17, 2026, but the entire thing collapsed after the latter allegedly attacked three ships in the Strait of Hormuz that were sailing in Omani waters on July 7. This led to an escalating series of retaliations, with one of the recent Iranian strikes resulting in American casualties in Jordan. Aside from hitting the nuclear powerplant that’s still under construction, U.S. Central Command said that it also “targeted Islamic Revolutionary Guard Corps forces that launched attacks against U.S. service members in Jordan on July 17.” The IRGC said that this is what led to its most recent attacks on AWS Bahrain.

Despite the strikes, it seems that it had no effect on Amazon’s services — the company has long moved its customers to sites unaffected by the conflict, ensuring service continuity. While it’s possible that the tech giant is trying to repair the damage to its sites, it hasn’t released any updates about the AWS Bahrain data center. As long as the war between the U.S. and Iran hasn’t resulted in lasting peace, American infrastructure in the region is in grave danger of being attacked, especially as the IRGC has directly threatened American tech companies like Microsoft, Apple, Google, and even OpenAI’s $30-bilion Stargate data center in Dubai.

Nvidia invited a group of about a dozen journalists out to the company's HQ to learn more about its Vera CPU, as well as how it fits into the larger Vera Rubin NVL72 rack design at the heart of Nvidia’s next-gen agentic AI platform. Part of that was seeing Vera Rubin in action, not as a disassembled tray on stage or a rack with a few blinking lights at a trade show — real racks running real workloads in a (partially) real data center. And we got to see those racks in action at Nvidia’s Engineering SuperLab.

It’s not a proper data center, or at the very least, it’s a sub-optimal data center. Nvidia was clear that the Engineering SuperLab is built for engineers, allowing them to quickly stand up and swap out racks to see the hardware in action. You could sense a bit of insecurity in the air; if Nvidia were building a proper data center, it wouldn’t look like this. This lab is where the engineers live, and if you’ve ever been around a group of engineers with a lot of hardware to play with, you know that things aren’t always as tidy as you’d expect in a proper data center.

The SuperLab Nvidia showed us is one of four nondescript locations near Nvidia HQ. These locations haven’t, up to this point, been disclosed. Each of the four locations has popped up over the last two years, giving Nvidia some floor space to play with as it rolls out new hardware.

The hardware in question here is the Vera Rubin NVL72 rack, but we saw a few other demonstrations, as well. Most notably, Nvidia showed us a sidecar running 800VDC power into an NVL72 rack. Nvidia also laid out some parts, demonstrating the assembly process for a Vera Rubin tray, which slides together with various retention arms in a matter of minutes.

This is a look behind the scenes of our tour, how the Engineering SuperLab is set up, and some choice data center eye candy. We’ve published a full breakdown of the Vera CPU and how it fits into Nvidia’s larger AI infrastructure, which goes into the technical details of the platform. Here, we’re mainly giving you a peek behind the curtain.

Nvidia Vera Rubin NVL72 running in the flesh

Vera Rubin is in full production, and we’ve seen some short videos of racks being stood up in data centers. But this is our first look at a rack running a real workload in the flesh. Nvidia says the racks here are running some workloads for OpenAI, in fact, and as you can see from the image above, it looks like some trays are running OpenAI’s GPT‑Rosalind model.

On the front of each tray here, you can see the ports for the dual ConnectX-9 NICs, along with the Bluefield-4 DPU in the middle. Around the back is Nvidia’s NVLink spine, an almost mediaeval-looking contraption, with sharp pins that connect the various trays together. It houses 5,000 copper cables that measure over two miles in length, delivering up to 3.6 TB/s of bandwidth per GPU and 260 TB/s of scale-up bandwidth per rack, on Nvidia’s sixth-gen NVLink.

Each Vera Rubin NVL72 rack houses 18 compute trays and 9 NVLink switch trays, the latter of which orchestrate communication between the various trays to function as one large, unified system. Nvidia demonstrated the MGX NVL design for us, which is a single reference rack with 72 Rubin GPUs and 36 Vera CPUs. Nvidia’s MGX ETL design replaces the NVLink spine with either a Spectrum-X Ethernet spine or direct chip-to-chip spine for a scale-out system featuring up to 256 GPUs.

The business-end of things is around the back of the racks, though. Although the back is clear of cabling thanks to the NVLink spine, power and coolant delivery are still a major factor. The organized chaos of the piping and cabling you can see in the images below shows just how much goes into standing up even one rack, let alone dozens or hundreds in a data center.

Nvidia’s previous-gen GB200 and GB300 NVL72 racks featured hybrid cooling, but Vera Rubin trays are entirely cooled by liquid. There aren’t any fans, which Nvidia says could, eventually, lead to much quieter data centers. That wasn’t the case in the lab here, which still called for eye and ear protection. I didn’t have a decibel meter handy — imagine if I carried one around with me casually — but my guess is that it was somewhere around 80 to 90 decibels inside; louder than an A/C unit, but quieter than a motorcycle. That’s a fairly typical noise level for a data center.

Regardless, Vera Rubin trays are entirely liquid cooled, with a process called “dry cooling.” Assuming the inlet temperature of the coolant is 45 degrees Celsius or less, Nvidia says it’s able to cool the entire system with a heat exchanger. If true, that would cut costly (in terms of power, space, noise, water consumption, and actual dollars) chillers out of the cooling equation.

Massive piping brings the coolant in (usually antifreeze or deionized water) at the top, and there are outlets at the bottom of the rack to move the warmed coolant out. Along the way are a series of inlet connections that allow trays to automatically hook into the cooling system, leaving just the main connections at the start and end of the loop. Nvidia has standardized everything on a Vera Rubin NVL72 rack with the Open Compute Project (OCP), even as far as shipping specifications. The company says just 47 minutes passes from when the truck pulls up to powering on the rack.

800VDC power for next-gen AI infrastructure

Nvidia also showed us an 800VDC “sidecar” in action. If you’re unfamiliar, Nvidia (along with other AI infrastructure companies) have been pushing for a new 800VDC power delivery system for modern data centers to reduce AC/DC conversion inefficiencies, as well as deliver the necessary wattage to racks without pushing into current ranges of thousands of amps.

A single Vera Rubin NVL72 rack can easily consume over 200 kW, which is a challenge for traditional power infrastructure in a data center. With current Grace Blackwell racks, power shelves convert the AC power coming into the facility (at 415V or 480V) to 48V/54V Direct Current for distribution within the rack. The problem here is pretty straightforward. If voltage stays constant, and wattage increases, then current also needs to increase. And more current means thicker bus bars, more conversion inefficiencies, and more rack space dedicated to power delivery.

Again, the solution that 800VDC represents is pretty straightforward. If wattage increases and current stays constant, voltage also has to increase. The idea is to convert AC power from the grid to DC power once, and then use a series of DC-to-DC converters within the rack, allowing for denser compute and better power efficiency.

This is not an easy problem to solve, as data centers need to change how power is brought into the facility, not just how it’s converted, stepped down, and moved around. Here, Nvidia showed off a sidecar, which is a rack filled solely with power equipment. This is a “retrofit,” as analyst firm SemiAnalysis calls it, representing the first in a series of transition phases to 800VDC. 415V/480VAC is still distributed throughout the facility, but it flows into this sidecar rather than power supplies within the rack. The sidecar rectifies the 415V/480VAC to 800VDC and feeds adjacent racks.

This is all an explanation to show some pretty interesting power infrastructure at play in this lab. Nvidia isn’t the first, nor only, company pushing toward 800VDC infrastructure, and companies like Google, Meta, and Microsoft have contributed to open sidecar designs like the Mt. Diablo spec. Still, it’s interesting to see one of these sidecars in action.

If you haven’t seen a peek behind the back end of a rack, you can see the large red connectors in the gallery above that bring power into the racks. You can also see the massive power cables and connectors at the rear of the 800VDC sidecar.

Nvidia’s next-gen AI infrastructure laid out

At the front of the facility, Nvidia laid out all of the components of its next-gen AI infrastructure. There’s nothing here we haven’t already seen before, though it's normally seen buried in trade show displays or featured on stage during a keynote.

First is the Vera Rubin NVL72 tray itself, which you can see above sitting next to a GB300 tray. Both are DGX designs, meaning they’re fully built and integrated by Nvidia, and you can see just how stark of a difference there is in assembly right away. The Vera Rubin NVL72 tray features only two cables, no hoses, and no fans. At the rear where the two Super Chip boards live, Nvidia demonstrated a retention arm that allows the boards to slide in and out in a matter of seconds.

The Vera Rubin tray is much cleaner, but it also makes better use of the space. It doesn’t include fans, which you can see take up a significant section in the middle of the tray in the GB300 design. With Vera Rubin, those fans are replaced with the thick midplane you can see above, offering a communication channel between the two ConnectX-9 NICs and Bluefield-4 DPU at the front of the tray.

Holding one of the two cables inside of a Vera Rubin NVL72 compute tray is the busbar, which handles power routing for the different chips inside the tray.

The Vera Rubin NVL72 tray is, of course, not the only deployment of Nvidia’s next-gen AI hardware. The company also showed us a CPU-only tray with eight Vera chips, offering up to 256 chips within a rack. That gives us a closer look not only at the chip itself, but also the SOCAMM2 LPDDR5X memory system, offering similar density and modularity as traditional RDIMMs at a far lower power cost.

Although most of the modules were unlabeled, we were able to snag the picture you can see above showing where the modules came from. These are 128GB SOCAMM2 modules from Micron running at 6400 MT/s, and as you can see from the photo, the slots aren’t all populated. This is the big advancement with SOCAMM2, offering up modularity for a memory standard that is otherwise soldered.

Nvidia’s NVLink handles scale-up communications, split across NVLink switches in the rack and the NVLink spine that you can see above. Nvidia describes sixth-gen NVLink as “putting the oven in the car.” Its goal is to get all of the chips in a rack communicating with each other, ensuring critical operations (like baking the pizza) happen as close to the destination as possible.

Scale-out communication, on the other hand, is handled with ConnectX-9 NICs in the tray and the Spectrum-X CPO (co-packaged optics) switch tray. The Spectrum-X switch tray is massive, and it’s a good illustration of just how much physical space is dedicated to communication (over raw compute) in a modern AI data center.

Of course, the size of the switch tray depends on how wide the scale-out infrastructure is. Nvidia also showed a smaller Spectrum-X CPO tray for smaller deployments. That's all we managed to see at Nvidia's AI data center SuperLab. Vera Rubin is in production, and will roll out in the second half of 2026.

Nvidia's upcoming Vera Rubin platform, set to arrive later this year, will take the stage as the AI world shifts towards an era dominated not by frontier training runs but by the demands of agentic AI inference at massive scale. The hunger for generated tokens in agentic workflows and the demands of delivering them quickly, efficiently, and at low unit cost now dominate the discussion.

We’ve already gone in depth on new performance data around the Vera CPU and how it helps to accelerate agentic AI workloads, but that’s not all Nvidia is sharing today. It’s also detailing some new features of the Rubin architecture and how those features are meant to increase inference efficiency from the GPU level to rack-scale and data-center-scale implementations of this accelerator platform.

The full Vera Rubin NVL72 rack-scale system is built up from 36 Vera CPUs and 72 Rubin GPUs, but our focus today is on the GPU proper. Rubin joins two compute dies onto a single package using the Nvidia High Bandwidth Interface. The resulting chip offers 224 Streaming Multiprocessors (SMs) containing a total of 896 Tensor Cores alongside 288GB of HBM4 memory providing 22 TB/s of memory bandwidth.

As an inference-focused accelerator, Nvidia touts Rubin’s 50 sparse PFLOPS of NVFP4 inference throughput as its headline performance figure, although that’s only one of a dizzying array of data types this chip can handle. Here are some key rates to keep in mind for this chip so far:

Let’s dive into some of Rubin’s refinements for inference workloads to understand how Nvidia aims to keep all of those resources fully utilized.

The Rubin Tensor Memory Accelerator efficiently manages growing MoE models

First up, Nvidia highlights efficiency improvements in the Tensor Memory Accelerator (TMA) that help feed the Tensor Cores with data. The TMA is a dedicated engine built to handle memory address calculations and perform direct loads of array data into a GPU's shared local memory.

Leading AI model architectures have moved from dense models where every parameter is activated per output token to a mixture-of-experts (MoE) architecture where only certain specialized sub-networks are activated per token, based on the guidance of a router that helps judge which experts are best suited to processing a given input.

MoE expert weights can be distributed across GPUs in order to efficiently utilize limited per-GPU HBM capacity. Nvidia says that Rubin's TMA has been improved to deal with the challenges of managing the growing numbers of experts in today’s leading models.

The TMA in Blackwell GPUs needed to maintain separate MoE descriptors in memory for the location of every expert, meaning that the overhead of locating and moving those expert weights requires more compute resources as the number of experts grows.

The Rubin TMA now supports GPU kernels that maintain and update a single unified MoE descriptor directly in the TMA instruction at runtime, reducing computation of MoE descriptor metadata and requiring less calculation overhead for data movement. This approach frees up GPU cycles for inference calculations, which is, of course, the place that you want your expensive AI accelerator spending the vast majority of its time.

Doubled K-dimension throughput, double the Tensor Core output

Rubin also improves the fundamental performance of matrix operations in the Tensor Core by doubling the amount of work those cores can perform on the K dimension, or the shared inner dimension of a pair of matrices to be multiplied. Without going too deep into the math, the size of the K dimension is directly related to the number of times the Tensor Core has to loop over the elements of the two matrices being multiplied.

In Nvidia's example, then, the calculation of a result matrix that would require four loop iterations on Blackwell can be completed in only two on Rubin. Nvidia says this improvement has wide-ranging benefits for throughput-, memory-, and latency-bound kernels, and it’s helpful for both context processing and decode phases of inference.

Softmax on Rubin gets up to a 4X boost versus Blackwell

Rubin also focuses on improving the performance of the attention mechanism that’s foundational to transformer-based LLMs More advanced models now support context lengths of up to a million tokens, and quickly performing attention calculations on such long input sequences quickly is a key driver for improved inference performance.

Softmax is an essential operation in attention calculations, and in order to keep up with the improved Tensor Core throughput in Rubin, Nvidia has once again boosted softmax throughput in the GPU SM’s Special Function Unit (SFU).

Since it relies on the transcendental math capabilities of the SFU, softmax throughput can become a bottleneck for subsequent inference work, and it's a limitation that Nvidia already sought to address with enhancements to the Blackwell Ultra SFU. Blackwell Ultra doubled FP32 and BF16/FP16 exponential throughput compared to the first-gen Blackwell GB200.

Rubin maintains Blackwell Ultra's 2X speedup over Blackwell in FP32 exponential math, and it doubles BF16/FP16 exponential calculations again compared to Blackwell Ultra, leading to a 4X improvement in throughput compared to Blackwell for those lower-precision data types.

Finer-grained dependency management, better Tensor Core occupancy

Rubin also increases Tensor Core occupancy by providing finer-grained opportunities for coordination between dependent kernels than on Blackwell. One case that Nvidia cites where these dependencies arise is the generation of activations for an LLM, where one kernel produces and stores data that is then used by a subsequent kernel as a prompt proceeds through a neural network.

On Blackwell GPUs, a long-running producer kernel on one thread block (perhaps within a CUDA structure like a cluster) might delay the execution of a subsequent consumer kernel on those thread blocks, even as other thread blocks of the producer kernel have finished their work.

Rubin offers finer-grained dependency resolution between kernels, such that a consumer kernel can begin executing on individual thread blocks as soon as the producer kernel’s output from each thread block becomes available, instead of waiting for the entire batch of producer kernel data to become available. This finer-grained management results in better GPU utilization, lower kernel-to-kernel latency, and ultimately increases tokens per second per user.

More efficient inter-GPU communication, lower NVLink overhead

All of the improvements we've discussed so far relate to how work happens on one GPU, but the Vera Rubin NVL72 rack-scale accelerator comprises many GPUs connected over an NVLink fabric within the rack. Model weights, key-value cache data, and inter-GPU synchronization messages all move over this fabric, so keeping overhead and latency low is key to realizing maximum performance.

GPUs running CUDA kernels can directly initiate communication with other GPUs in the rack using Nvidia Collective Communications Library (NCCL) API, lowering overhead. Nvidia notes that because the GPU performs those operations directly as part of the compute kernel, the efficient execution of those communications becomes critical to performance.

On a Blackwell system, an NVLink transfer between GPUs might require data store operations followed by a memory barrier and an atomic flag. The Rubin architecture introduces a feature called counted writes that reduces the amount of coordination and synchronization traffic necessary to share data between GPUs across the fabric.

On Rubin, the memory barrier and atomic operations are replaced by a single write counter update on the receiving GPU, reducing network traffic and latency and improving compute utilization by reducing the time spent waiting for coordination overhead.

All told, in tandem with the high single-threaded performance of the Vera CPU for agent harnesses, tool calling, code compilation, and more, the improvements in the Rubin GPU for performance on critical inference operations, as well as improved efficiency for data movement on-chip and across the rack, promise to help create a rack-scale and data-center-scale system that will both increase inference performance and lower per-token inference costs in the increasingly agentic future that Nvidia envisions. We’re excited to see more of what this GPU can do as deliveries of Vera Rubin systems are set to begin this fall.

Nvidia’s Vera CPU is its first bid to become a key player in the data center CPU market. Although Grace has seen some success (most notably with Grace standalone deployments at Meta), Vera is Nvidia’s first CPU with a custom core design. It’s arriving at an ideal time, as well, with the server CPU market exploding in the last few months on the back of agentic AI demand.

Vera isn’t a chip built to chip away at the market share of AMD and Intel in the cloud. It’s built to grab market share in an expanding market, as hyperscalers look to widen AI infrastructure beyond legacy clouds. As such, it’s designed in a much different way than Nvidia’s x86 competitors, and it even holds some unique architectural design points compared to the swath of Arm-based designs.

Nvidia has slowly revealed more details about Vera as it ramps into general availability, which is on track for the back half of this year. Now, we have a full picture of the chip. Nvidia shared its Vera white paper, along with unofficial SPEC CPU 2026 results comparing Vera to AMD’s Turin-based Epyc 9755.

We’re going to break down the white paper here, including all of the details about the Olympus core and a look at the benchmarks Nvidia ran. At the end of this piece, we’ll also take a brief look at the larger context of Vera and how it fits into Nvidia’s wider AI ecosystem compared to standalone deployments.

But plenty of ink has been spilled about Vera’s technical capabilities and Nvidia’s next-gen AI infrastructure vision. Let’s start with the important thing: the benchmarks.

Nvidia Vera CPU benchmarks

We’ve seen Vera in action before, though only through a series of selected benchmarks ran at Nvidia HQ by Phoronix. In the Vera white paper, Nvidia shared benchmarks for SPEC CPU 2026, specifically the integer suite from SPECrate, against AMD’s Epyc 9755, with both chips running in a dual-socket configuration. Before getting into the results, there are some important notes about how SPEC runs work, and the reporting criteria for them.

Nvidia’s run here isn’t official, as Vera was tested in a reference system due to the fact that it’s not broadly available yet. It’s ramping for general availability in the second half of the year. Due to that, Nvidia is unable to report its results. That’s why you see “estimated” in some of the charts below. Nvidia ran SPEC CPU 2026; it’s not extrapolating expected performance like we’ve seen from AMD so far with its upcoming Venice chips.

SPEC CPU 2026 is split into four suites, but Nvidia tested the SPECrate integer suite, which is focused on system throughput with integer-based workloads. The “rate” result is looking at how much work is completed within a certain amount of time. Here, each thread in the system has a copy of the workload. The score is how much time it takes for those workloads to complete, regardless of thread count, naturally giving chips with more cores an advantage.

If you want more detail on the benchmarks included in the suite, make sure to read our original coverage of SPEC CPU 2026. Here are the overall results:

Nvidia didn’t share the exact results for the 9755 it tested, short of the overall score of 898. Taking that overall score into account, Vera is 3% ahead of the 9755. It’s worth noting that Vera is ahead here despite a large thread disadvantage. An overall score of 898 for a dual-socket Epyc 9755 system isn’t unreasonable compared to publicly-submitted SPEC CPU 2026 runs, though higher results have been published. SPEC CPU ships as source code, which the tester must compile with their compiler of choice, and that can heavily influence results (particularly with vendor-specific compilers). Nvidia used GNU 15.2 with both systems.

Above, you can see Vera’s results stacked up against the 9755, but these aren’t comparing the numbers directly. Nvidia has normalized the per-core performance, which isn’t how SPECrate results are normally shared. According to the overall numbers, Vera is still completing more work within the same amount of time, despite a thread disadvantage, but the margins aren’t in the range of a 70% or 80% advantage as the above chart suggests.

We asked Nvidia about the results given that they're obfuscated by comparison; we could not reverse-engineer the Epyc 9755's scores with the information Nvidia has provided. Here's the response it gave: "Per-core performance under a fully loaded socket is important because agentic AI and RL run many sandboxes concurrently, while each agent step remains sequential and latency-sensitive. It measures how much performance each core sustains amid contention for shared power, memory, cache, and fabric. We therefore normalize by physical core, with SMT enabled on both systems."

The “agentic” workloads Nvidia has highlighted here are code compilation and interpretation workloads, which is something an agent is often doing, querying repos for dependencies and building source code. Below are data science workloads (or Exploratory Data Analysis), and below that are data processing workloads like SQLite database management. The results here align with Nvidia’s overall messaging of Vera, that it’s highly competent at data-rich, backend operations.

Although Nvidia is sharing per-thread results, it argues that SPECrate is still the correct benchmark to run. The per-thread results here are in the context of a fully-loaded socket. Here’s the justification from the white paper: “This metric is non-trivial for agentic AI and RL systems, where many sandboxes, tools, and environments run concurrently rather than as isolated single-thread tests. Fully loaded per-core performance captures how well each core sustains throughput while sharing socket-level power, memory bandwidth, cache, and fabric resources.”

In addition to running the workloads, Nvidia analyzed the code execution for architectural benchmarks, which you can see in the gallery above. Nvidia claims an overall IPC gain of up to 1.9x compared to Turin, up to 2.3x more branch predictions and 3.5x taken branches per cycle, and up to 2.4x higher instruction fetch operations per cycle.

Outside of SPEC, Nvidia shared a few benchmarks highlighting the capabilities of the Olympus core. First up is PageRank, an algorithm developed by Google to originally rank web pages, which highlights Olympus’ prefetch engine. Nvidia scaled this workload to higher core counts, showing Vera maintaining much of its single-core performance up to 32 cores, while the Turin chip hits a wall around 20 cores.

In addition to the above results, Nvidia shared some tests of the Vera memory system compared to Turin. These microbenchmarks are good for validating Nvidia’s specifications, but they’re looking at architectural performance, not application performance. An architectural advantage translates into a performance advantage, but not always in a linear, expected fashion.

Nvidia used internally-developed tools for the memory tests, though they're available on GitHub for anyone to run.

First is loaded memory latency, stressing the memory subsystem as bandwidth usage increases. Vera has much higher bandwidth overall, but you can see the Turin chip hit a latency wall below its maximum, which Nvidia attributes to Non-Uniform Memory Access (NUMA) domain traversal and CCD-to-CCD latency.

Looking at per-core bandwidth, Nvidia claims Vera provides more than four times the bandwidth of AMD’s 9755. The suggestion here is that “real-world” per-core bandwidth is even better than Nvidia’s specs lead on (or perhaps worse than AMD’s).

Maybe the most consequential of these tests is the one you can see above, looking at core-to-core latency. It’s no secret that crossing the CCD on AMD’s chiplet-based architecture incurs a big latency penalty. You can see that in action even in our Ryzen 9 9950X3D2 review, and the penalties compound as you scale up the number of CCDs.

In fairness to AMD here, chiplet-based designs aren’t built for this type of cross-CCD traversal, preferring to keep workloads localized and optimizing for core density. Vera’s design goal is clearly to keep latencies consistent across the entire die and sacrificing core density in the process. Nvidia’s Ian Buck told us that this design trade-off “will come at the cost of the legacy workload,” when we recently visited Nvidia HQ.

That’s important context. Nvidia isn’t gunning to steal existing market share from AMD and Intel as much as it’s trying to grab market share in an expanding market before AMD and Intel can. Some financial institutions (including Morgan Stanley and Bank of America) suggest the server CPU market could double in size (or grow even larger) by 2030. That context is important because there will be a continuing demand for CPUs that can handle workloads Vera is not optimized for, and it’ll be interesting to see how AMD and Intel tackle that dynamic with future products, trying to keep a legacy base of customers while pushing ahead into the expanded market.

Nvidia clearly has a vision of how that expanded market looks, and to that end, hasn’t shared SPEC CPU floating point results. Presumably, this is due to the fact that SPEC’s vectorized suite is focused primarily on HPC workloads, whereas Nvidia focused on what it believes are critical agentic workloads that are integer-based. Vera has a vector engine complete with SVE, but that doesn’t seem like Nvidia’s focus.

In an end-to-end Nvidia system, those vectorized workloads would be offloaded to a Rubin GPU. Still, we don’t have any vector results for Vera yet. Up to this point, we’ve only seen integer results, which is strange given the memory system at play in Vera.

Vera is Nvidia’s first CPU with a core design created in-house, which is the Olympus core. It’s built on Arm v9.2-A, but the design was created by Nvidia, unlike Grace, which leveraged a stock Arm design. Each Vera CPU has 88 Olympus cores on a monolithic die, breaking from the chiplet-based designs available from Nvidia’s x86 competitors.

Nvidia says Vera comes with a 1.5x increase in instructions per cycle (IPC) throughput compared to Grace, and 50% higher performance compared to x86 competitors (it seems that number is per-thread performance with a fully-loaded socket). Nvidia has a single 88-core design with Vera that supports spatial multithreading for 176 threads.

The CPU has a configurable TDP range of 250W to 450W. It uses a SOCAMM2 LPDDR5X memory system with capacity of up to 1.5 TB and speeds up to 9600 MT/s, and comes with 164 MB of L3 cache and 2 MB of L2 per core. Vera includes significantly less L3 than Intel’s highest-specced Xeon 6 and AMD’s Zen 5 chips. It actually has more L2 than L3 overall. This, presumably, is due to Nvidia’s fabric, which distributes the L3 in a mesh across the monolithic die.

Below, you can see a layout of the Olympus microarchitecture. Nvidia has disclosed some of the highlights of the architecture previously, such as the 10-wide instruction decode and neural branch predictor, but we now have a full view of the architecture courtesy of Nvidia’s Vera white paper.

The front end starts with Nvidia’s neural branch predictor that can run two branches per cycle “with zero penalties,” according to Nvidia. Research on neural branch prediction dates back to the late 90s, but Nvidia says it has a “novel” neural branch predictor, perhaps building on previous research such as BranchNet.

The BPU feeds into the Instruction Fetch Unit, which holds 64 KB of L1 instruction cache, and loads into a decode queue that supports 48 instructions (we’ll go into the memory/cache layout later). At the last stage of the front end is that 10-wide decode, feeding more instructions into the execution engine per cycle than the 8-wide decode in AMD’s Zen 5 microarchitecture.

Past the front end, the mid-core rename / allocation engine is built to keep instructions moving while waiting on dependencies. In addition to renaming and allocation, instructions work through value prediction, which can speculatively execute the instruction, and memory renaming, where the instruction can move forward while a load is happening if the data relationship can be determined.

Inside the execution engine, Nvidia includes eight simple Arithmetic Logic Units (ALUs), two complex ALUs, and four branch units for resolution. For SIMD instructions, the execution engine includes a vector cluster for Arm’s Scalable Vector Extension (SVE), including six vector units that support 128-bit SVE instructions at FP8 precision, along with two crypto-enabled vector units that can handle AES, SHA, and SM3, among other prominent algorithms. Keeping data moving through the engine are four load units and two store units.

The cores support spatial multithreading, giving a Vera CPU with 88 cores access to 176 threads. Traditional SMT time-slices execution, giving both threads access to all of the core resources and sharing them as instructions execute in parallel. With spatial multithreading, each thread of an Olympus core has access to dedicated resources, allowing one of the threads to execute with high-throughput while the other thread handles simple tasks, or to operate as two independent execution environments.

The execution resources are partitioned, explaining the wide decode front end. It’s not clear, however, if the SMT implementation can also opportunistically grab resources, particularly in the scenario Nvidia describes where one of the threads is maximizing throughput while the other handles smaller tasks.

There’s a lot going on in Vera between the 10-wide decode, neural branch predictor, and spatial multithreading, but perhaps the most significant architectural design point is Nvidia’s second-generation Scalable Coherency Fabric (SCF). It underpins Nvidia’s approach of using a monolithic die as opposed to a chiplet-based design, distributing last level cache in a mesh across the die and avoiding the cross-CCD latency penalty with localized L3.

The mesh distributes data through a series of Coherency Switch Nodes (CSNs) that serve as routing points between cores and the 164 MB of distributed L3. These routing points further connect the cores and L3 to the memory system, I/O, and NVLink C2C for cache-coherent communication between chips. Nvidia’s benchmarks comparing Vera to AMD’s Epyc 9755 show that AMD can achieve slightly lower core-to-core latencies within a cluster, but Vera maintains significantly better core-to-core latency across the die, as expected.

Nvidia says SCF inside Vera has 3.4 TB/s of bandwidth, enabling faster core-to-core communication, especially when traversing the die. However, Vera also supports Memory System Resource Partitioning and Monitoring (MPAM), allowing portions of L3 to be partitioned in multi-tenant environments.

Vera uses SOCAMM2 LPDDR5X, which is a relatively new advancement that Nvidia’s competitors haven’t had the chance to benefit from. With the use of SOCAMM2, LPDDR5X provides similar modularity and capacity as traditional RDIMMs, but at significantly lower power draw.

The memory can run at up to 9600 MT/s, with aggregate bandwidth of 1.2 TB/s and per-core bandwidth of 14 GB/s, doubling the bandwidth of Grace. The Vera board supports eight SOCAMM2, offering capacity ranging from 256 GB to 1.5 TB. Nvidia claims a “fully populated” memory subsystem consumes between 30W and 40W depending on capacity.

For I/O, Vera supports PCIe 6.4 with 88 lanes per CPU and bifurcation support down to x2. It also supports CXL 3.1.

Unlike Grace, Vera includes Arm’s Confidential Computing Architecture (CCA) and Realm Management Extension (RME), including Device Assignment and Coherent Device Assignment, offering a boon to multi-tenant environments where VM isolation is key. Nvidia also implements TDISP for coherent devices, allowing for encrypted communication between GPUs and PCIe devices.

Nvidia is already sampling Vera as a standalone chip to partners, and it says it will continue to do so, but the vision is an end-to-end solution built on Nvidia’s CPUs, GPUs, switches, NICs, and even rack specifications. Nvidia doesn’t make all of these individually, at least not at scale — just like with desktop graphics cards, Nvidia provides its MGX reference design, which customers can purchase, but partners also offer their own racks, some built solely to Nvidia’s specifications and others with more speciality.

Each tray comes with two Vera Rubin superchips, each of which contain a single Vera CPU to two Rubin GPUs, giving you two CPUs and four GPUs per tray. At the front, Nvidia partitions off three spaces, with the MGX design carrying two NVIDIA ConnectX-9 SuperNIC on either side and a Bluefield 4 DPU in the middle. Critically, this design doesn’t include any hoses or fans. It’s entirely liquid cooled, and it contains just two cables throughout the entire tray.

Nvidia demonstrated this cable-less design, showing the Vera Rubin Superchip sliding in and out of the track with a retention mechanism in a matter of seconds. The company says assembling the rack takes less than a few minutes and is handled entirely by robots, which is a far cry from GB200 and GB300 trays.

GB200 and GB300 trays are dense designs, but they’re also cluttered with cables and hoses. Nvidia says this massively slowed down production time, eventually leading to production issues that delayed Nvidia’s rollout. The company says that won’t happen with Vera Rubin and its largely cable-less design. Whereas a Grace Blackwell tray took around two and a half hours to assemble by a human, the company says a Vera Rubin tray is assembled within five minutes and entirely automated by robots.

Each tray needs to dissipate several kilowatts of heat, which Nvidia says it’s able to do using dry cooling. Liquid cooling is nothing new in the data center, either through an external chiller (essentially an A/C unit) or evaporation, where a fan evaporates water over a mesh and cools without the need for a compressor. With Vera Rubin, Nvidia uses “dry cooling,” with a maximum inlet temperature of 45 degrees Celsius.

Nvidia says it’s able to get the full performance out of a tray given an inlet temperature of 45 °C, allowing trays to operate without an additional water consumption in environments up to 100 degrees Fahrenheit. The tray essentially uses a large closed-loop similar to what you find from a consumer AIO, just scaled up. Water moves out of the tray and outside the data center, and it passes through a radiator where fans dissipate the heat. There’s some extra power consumption from water pumps and fans, but not nearly on the scale of evaporation methods or chillers.

The result is a tray completely free of fans, essentially noise-less in operation, and doesn’t strain local water infrastructure. That’s what Nvidia says, at least. In many locations around the U.S. where data centers are located (Texas and Virginia chief among them), temperatures easily climb above 100 °F during the Summer, prompting some sort of backup method of cooling. Nvidia says the external temperature ceiling can go higher depending on different factors — running at lower power, for example, and using more efficient heat exchangers — but under normal conditions, 100 °F is the ceiling.

It’s worth noting that nothing about a Vera Rubin tray explicitly requires this method of dry cooling; the hardware is just capable of offering full performance with an inlet temperature of 45 °C.

In addition to an NVL72 design, Nvidia has a Vera standalone deployment that compacts each tray into a series of SOCAMM2 slots and Vera chips. In Nvidia’s 48U MGX design, a standalone Vera deployment can include up to 256 CPUs in a rack.

Underpinning scale-up communication is Nvidia’s sixth-generation NVLink, which is deployed as switches in the rack and connected to compute trays using Nvidia’s NVLink spine. You can see the spine on its own in the image above, which features over two miles of thin copper wire to allow every tray in the rack to communicate with each other.

Localizing storage, networking, security, and telemetry operations is Nvidia’s BlueField-4 DPU. A Vera Rubin NVL72 compute tray includes a single DPU and two ConnectX-9 NICs to maximize CPU/GPU utilization. You can read more about Bluefield 4 in our original coverage from GTC.

Nvidia’s Ian Buck, vice president of hyperscale and high-performance computing and the inventor of CUDA, says the company has “shipped... let's put it in the hundreds of thousands of Grace standalone servers.” In May, Nvidia disclosed that it had shipped over 2.5 million Grace CPUs in total, and the company announced a partnership with Meta to deploy standalone Grace servers in February. Buck’s comments suggest the scale of deployment may be even larger, however, as Nvidia tries to compete in a market dominated by other players.

It’s an interesting comment, though not a surprising one. Nvidia has become the dominating force of Silicon Valley as demand for its GPUs skyrocketed during an unprecedented data center buildout for AI inference. Since peaking earlier this year, however, around $1 trillion in Nvidia’s market cap has been wiped away as investors rally behind CPU makers like Intel. Evolving agentic AI workloads have changed the hardware balance, shifting away from as many as eight GPUs per CPU, toward a one-to-one ratio in some cases.

Nvidia wants to ride that train with its new Vera CPU, which was architected specifically for those types of workloads. Even before the recent rise of agents, however, Nvidia says it has seen demand for its CPUs for data-hungry workloads. “They weren’t running a web server [with Grace]… or they aren’t being used for, what the cloud uses, of cheap, dollar-per-core,” Buck said. “They were being deployed for the backend, data-rich operations, like the data processing.”

Grace represents an on-ramp for Nvidia into data center CPUs. It uses 72 stock Arm Neoverse V2 cores, but it’s differentiated by Nvidia’s Scalable Coherency Fabric (SCF). Vera uses an updated SCF, but it also features Nvidia’s first custom core design, called Olympus. Grace cracked the door, and Vera represents Nvidia's big entrance into the market against AMD and Intel.

Regardless of where Vera ends up in the battle of next-gen data center CPUs — which is heating up now, as AMD is expected to launch its Zen 6 Venice CPUs this week — the design is vastly different from what we’ve seen out of Intel and AMD. Most notably, Vera is monolithic, placing all of its 88 cores on a single piece of silicon. AMD and Intel, years ago at this point, pivoted away from monolithic dies in favor of chiplets, allowing an extremely high density of cores at the cost of latency and coherency issues. Vera is radically different in that regard, not only being built on a single die, but also dedicating significant die space to the fabric.

“One of the reasons we don’t have 128 cores is because we’ve dedicated so much of the die area toward the fabric,” Buck said. “It’s 3.4 TB/s of bandwidth inside of that CPU that is dedicated toward allowing every core to talk to every cache, every memory [controller] at full speed without any collisions.”

For clarification’s sake, Buck is referencing 3.4 TB/s of core-to-core bandwidth in Vera. There’s up to 1.2 TB/s of aggregate memory bandwidth (14 GB/s per core) through the LPDDR5X interface.

But just as chiplet-based designs made trade-offs in per-thread performance, Vera will likely make trade-offs for its unique architecture. The majority of data center workloads are still “legacy” tasks that hyperscalers have built for, and even with seemingly insatiable demand for AI infrastructure, that is unlikely to change for several years.

Buck recognizes this trade-off, asking: “Can Intel and others build rich fabrics? Do they have the IP and the ecosystem to do it and connect it all the way through to LP memory? They need to tell you when they’re going to do it… but that trade-off will come at the cost of the legacy workload.” Earlier this year, at GTC in March, Buck was even more clear. “The world is not going to be served by one SKU of CPU, and that is not our intention,” the executive said in a news conference at the time.

Still, it’s clear Nvidia has ambitions with data center CPUs beyond what headlines are floating around on the New York Stock Exchange. Nvidia says CPUs represent a $200 billion TAM (Total Addressable Market) opportunity for the company, a rather rosy forecast compared to the rest of the industry, which sees a TAM of around $120 billion by 2030 (though recent estimates have climbed as high as $170 billion). And agentic AI is expanding that market, with Morgan Stanley in April estimating that agents could add as much as $60 billion to the data center CPU market.

Vera is in full production alongside Nvidia’s next-gen AI infrastructure, including Rubin GPUs, ConnectX-9 NICs, SpectrumX Ethernet switches, and the various components that go into building a Vera Rubin NVL72 rack. The company says there are around 1.3 million components that go into a rack, and it has a list of over 300 partners globally to build them. As part of our visit to Nvidia HQ last week, we saw a Vera Rubin NVL72 rack in action, running workloads for OpenAI.

Our local AI testing in 2026 has focused on large language models that can fit entirely into the 128GB of unified memory on Nvidia GB10 and AMD Strix Halo systems. Useful as those smaller open models can be, there is sometimes no replacement for displacement. Today, we’re exploring what’s possible from a local AI cluster with a pair of Nvidia GB10 systems, namely Dell’s Pro Max with GB10 (henceforth Pro Max), which gives us 256GB of RAM for a local AI sandbox.

Quantizing an AI model from higher-precision to lower-precision data types involves tradeoffs for performance and accuracy. And even in quantized form, some advanced open models are still too large to fit within 128GB. But those models can be distributed across multiple local systems using the network as a scale-out backbone, just as they are in the data center.

Why scale out GB10 systems (or Strix Halos, or Macs)? Local token factories with large VRAM pools built up from discrete GPUs can get crazy, fast. Scaling one to even 128GB of VRAM requires a costly host system with enough PCI Express slots and bandwidth to feed those cards, and going beyond 128GB means spending $20K or more in Nvidia GPUs at a minimum, even if you're building up from older 48GB Ada cards.

The preferred recipe for this kind of setup typically includes a Threadripper Pro or Epyc platform, which means a costly CPU, motherboard, and DDR5 kit even before you start adding graphics cards. The power requirements for such a system can quickly get beyond the capabilities of a standard USA 15A circuit (1,800W maximum).

And having four discrete GPUs running their blower fans at high speeds under load, along with whatever other active cooling you might need for what is essentially a GPU server, is not going to make for the most pleasant company if you’re sharing a space with it.

While a GPU server with four RTX Pro 5000 or RTX Pro 6000 cards is useful for getting the absolute best performance for a given application, those potentially high costs, platform challenges, and quality of life concerns have led local AI enthusiasts to explore other ways of achieving large local memory pools with acceptable LLM inference performance, like the GB10 cluster we’re building today.

Nvidia made the DGX Spark and its Spark-alikes scalable, cluster-able systems right out of the box thanks to their built-in ConnectX 7 200Gbps NICs. These high-end interfaces support Remote Direct Memory Access over Converged Ethernet, or RoCE, so two (or more) GB10 boxes can use them as the backbone for a distributed AI computing cluster.

We didn't have multiple Sparks to test RDMA clustering during our initial review, but Dell sent us a pair of Pro Max GB10 systems along with the QSFP cables necessary to join them together.

These systems still aren’t anywhere near cheap, but at $6332 each as of the time of this writing for the tested configuration with 4TB SSDs, you can build a complete, turn-key cluster with 256GB of RAM for less than the cost of the four 48GB or 72GB GPUs you’d need to scale a similar GPU server build.

If you need to save cash and can trade off absolute performance in the bargain, there’s no cheaper way to get into big local models right now, period, but especially not with the level of networking performance that the DGX Spark platform offers.

Dell’s Pro Max with GB10 closely follows the Spark template, but it adds an extremely handy power LED to the front panel that the DGX Spark lacks, and the hexagonal grilles on the front and rear panels doesn't catch on clothes or microfiber cloths like the metal foam front and rear panels of the DGX Spark do.

Dell also provides a large 280W USB-C power adapter with each Pro Max GB10 system, or 40W more capacious than the adapter included with the reference DGX Spark. However, there’s nothing to suggest this system has a higher TDP or clocks than the reference Spark design as a result.

Dell does drop the Pro Max with GB10 back to a PCIe Gen 4 SSD compared to the launch DGX Spark’s Gen 5 drive, but it appears that the ongoing NANDpocalypse has forced Nvidia to source Gen 4 drives for its reference systems to keep costs down, so we’re not holding this decision against Dell here.

Setting up

We’ve already covered the DGX Spark reference design in its own review, so if you’re unfamiliar with the basics of this platform, we’d suggest reading that coverage first. We’ll keep the focus today on the specific challenges and hurdles of clustering two of these systems together.

While the ConnectX 7 NIC on these systems supports both Infiniband and Ethernet protocols in its add-in card form, Nvidia has stated on its official DGX Spark forums that GB10 systems exclusively support Ethernet, and therefore, RoCE for clustering. Don’t buy multiples of these systems hoping to connect them through any Infiniband switches you might have lying around.

The ConnectX 7 NIC on the Spark and Spark-alikes like the Dell Pro Max is also connected to the GB10 SoC in a somewhat weird way due to some possible platform limitations. In short, the largest PCIe bus width one can apparently get off GB10 is a PCIe 5.0 x4 link, so to achieve 200Gbps on any one QSFP port, the two x4 links to the ConnectX 7 have to be teamed behind any one physical port. As a result, each physical port on the NIC is presented to the system as two logical interfaces.

To achieve the full 200Gbps bandwidth available from the ConnectX 7, you have to configure your networking topology carefully. Nvidia has a Spark playbook on how to do this, and the spark-vllm-docker project also offers its own guide on how to set up these interfaces. I’d recommend following them closely unless you have good reason to roll your own configuration.

After connecting my Dell Pro Max boxes together using the same QSFP cages on their back panels, configuring their network interfaces according to the spark-vllm-docker guide above, configuring passwordless SSH on my second node, and running the recommended NCCL bandwidth test on the link, I found that I was only getting a small fraction of the expected RDMA bandwidth, despite both boxes reporting that they were fully up to date through the DGX Dashboard app.

Community wisdom suggested that a firmware version mismatch was to blame, so I verified that the head Pro Max node in my cluster was fully up to date, both through the DGX Dashboard app and through the command line using the apt package manager.

But even though the DGX Dashboard reported that my second Pro Max system was fully up to date, running the recommended command-line apt checks revealed that there was an update for the fwupd package stuck behind a phasing fence, so I force-installed it.

Once this forced update was complete, it unlocked a new round of firmware updates for the second Pro Max, which I dutifully applied. After rebooting both systems and re-running the recommended NCCL bandwidth tests, I was finally getting something approaching the full 25GB/s one would expect from a proper 200Gbps link.

While none of the issues I had getting my Pro Max GB10 systems clustered were show-stopping, it's also far from a plug-and-play experience. But once both systems were settled in, I didn't see the bandwidth over the ConnectX 7 ports drop back to the degraded performance levels I first observed, even across multiple reboots of the cluster.

Cluster management and performance

If you're thinking about clustering Sparks, you want an inference engine that can handle tensor parallelism, or the distribution of model weights across GPUs during computation. vLLM is an easy choice for doing this on the DGX Spark platform thanks to actively maintained community tools like spark-vllm-docker and sparkrun, but you can also achieve these results with SGLang if that’s your platform of choice.

The spark-vllm-docker project comes with several handy scripts that make starting the cluster and distributing models across it easy, and the sparkrun project provides similar functionality. We focused on spark-vllm-docker for this round of tests, but you have options in this space if you want to explore them.

With our inference engine settled, we went off in search of an advanced model that would utilize a decent chunk of the 256GB of VRAM available from our cluster.

DeepSeek v4 Flash is one such model. It’s a 284-billion-parameter mixture of experts model with 18 billion active parameters per token, and it claims to support a context window of up to 1 million tokens. (vLLM gave us a 400K-token cap on this setup). spark-vllm-docker offers a prebaked vLLM recipe for it, so we downloaded it, deployed it across our cluster, and got to benching.

The DeepSeek v4 Flash vLLM recipe we used takes advantage of this model’s built-in multi-token prediction capabilities, so decoding throughput remains essentially the same even as time to first token climbs with context lengths up to 200K+ tokens, or about 333 pages of A4 text. That’s impressive and usable performance for a model of this size and capability.

We also loaded up CyanKiwi’s four-bit quantization of MiniMax M2.7. This is another large mixture-of-experts model with 230 billion total parameters and 10 billion active parameters, and it supports a context window out to 200K tokens, which is exactly what vLLM gave us after initialization on our Spark cluster.

This model doesn’t have the built-in MTP advantage of DeepSeek v4, so even with the four-bit quantization we used for this test, its time-to-first-token and tokens-per-second throughput follow a more familiar curve. Throughput starts in a relatively usable range, but falls off quickly as we approach the limits of the context window.

Our experience running DeepSeek v4 Flash and MiniMax 2.7 shows that even though a Spark cluster isn’t fast, it can still produce enough tokens per second to be a useful sandbox with these demanding models.

Power and thermal notes

As we discussed in our intro, a major advantage of a cluster like this is that it doesn’t require exotic power and cooling to run, and you also don’t have to banish it to a garage or server closet to keep it quiet.

Imeasured peak wall power draw of about 375W to 415W across my cluster during inference performance testing, which is just a bit higher than the TGP of a single RTX 5080 without its host system.

That figure bodes well for adding even more Spark-alikes to a local cluster if you need to, as even four of them running all-out are likely to need less than 1kW from a circuit (before any outboard networking gear is factored in, at least).

Noise levels from my dual Dell Pro Max setup under load were also well controlled, measuring about 40 dBA at 18 inches away. If you need to keep these systems in an inhabited office space or cubicle, they’ll be perfectly tolerable to be around.

If you’re expanding beyond two GB10 systems, I’d guess that any 200G/400G networking gear that you’d need to throw into the mix will likely be far louder than even four of these systems under load, as it’s likely built for a server closet, not a continuously inhabited space.

Bottom line

If you're a local LLM trailblazer and need more VRAM for large, capable models, and don't want to fiddle with or don’t have the cash for a from-scratch GPU server build with more than 128GB of memory, the Dell Pro Max with GB10 cluster we’ve built here exemplifies how clustering Nvidia GB10 systems is a straightforward, space-efficient, low-power, low-noise, and relatively cost-effective way to scale up your local AI sandbox beyond 128GB of VRAM.

"Relatively" is doing a lot of work here because a pair of Dell Pro Max with GB10 boxes as tested here rings in at $12,664 right now, plus another $50 for the QSFP cable you'll need to hook them together. For organizations or institutions with departmental budgets to spend and existing Dell accounts and support contracts to work within, that dollar figure is likely secondary to the ROI on whatever proposal might drive a purchase order.

But for individuals who just want to build a bigger AI sandbox in their home lab and don't have those relationships to worry about, it's still possible to construct a similar cluster with Asus's Ascent GX10 from stock for under $10K, even at current prices. And as we explained in the intro, going above 128GB of local memory by using multiple discrete GPUs will cost you far more than such a cluster, even before you factor in the cost of a host system.

Not everybody needs to connect multiple Sparks, of course, but if that possibility does intrigue you, the ConnectX 7 NIC in every GB10 box means that there isn't a cheaper way to achieve a 256GB (or larger) distributed memory pool with this class of networking performance behind it.

Some AMD Strix Halo mini-PCs offer PCIe slots for expansion, but they're limited to PCIe 4.0 x4 speeds, so even the funky teamed PCIe 5.0 x4 links to the ConnectX 7 NIC inside GB10 boxes means you're getting far higher potential RDMA bandwidth than you would from adding an aftermarket NIC to a Strix Halo system.

Even though Apple's Mac Studio briefly enjoyed a turn in the spotlight as a cluster-friendly alternative for local AI thanks to the massive memory pools and high bandwidth available from Apple Silicon, along with RDMA over Thunderbolt 5, that star has dimmed, as the company no longer offers memory options larger than 64GB with M4 Max Studios or 96GB with M3 Ultra models. And the lead times on either of those systems are currently over three months out, which is an eternity in the rapidly evolving local AI market.

So Nvidia sort of has this field to itself right now, as GB10 boxes remain readily available from stock with 128GB of RAM at prices that aren't completely bonkers. And if you're a novice to distributed computing concepts, the active community, actively developed tools, and ecosystem software support around GB10 systems are all invaluable for getting your AI cluster running quickly. All that makes Dell’s Pro Max with GB10 (and other Spark-alikes) hard to beat for building a big local AI sandbox to experiment with.

A U.S. federal judge granted the final approval of Anthropic’s $1.5-billion settlement over the class action lawsuit authors filed against it for infringing their rights. According to Reuters, while the court ruled that training AI on books is considered fair use under copyright law, it was the fact that Anthropic kept 7 million pirated books in a central library that violated the copyrights of the authors and their publishers. This is reportedly the biggest payout in a copyright case ever, and the first one to settle among the many cases against AI firms being tried today for infringement.

While this might seem like a massive sum, the huge number of involved works and authors means that the payout amounts to a little over $200 per title. It also affirmed that AI firms’ use of existing works to train their models is fair use, which is something that many are fighting against. "We reached this settlement in 2025, after the court's landmark ruling that training AI on books is fair ​use under copyright law — which remains the law today," said Anthropic deputy general counsel Aparna Sridhar. "We are pleased that more than 91% of authors and publishers covered by the settlement have claimed their share of the payment, and we're looking forward ​to bringing this matter to a close." Because of this, some groups have opted out of the settlement and instead filed separate complaints against the AI firm.

Still, this is a landmark win for copyright holders, especially against other AI tech companies that have been scraping pirated content to train their models. This includes Nvidia, which allegedly used scripts in its NeMo Framework specifically designed for illegally downloading books, and Meta, which reportedly torrented 82TB of pirated books for AI training. The latter argued that its framework also have “non-infringing uses,” but the court said that it’s not the entire system, but specific tools within it that were the issue. As for Meta, it claimed that its use of pirated material was legal as long as it did not seed content.

Copyright infringement is one of the major issues that AI tools are facing at the moment, especially as many creators believe that these models were trained on stolen data. Anthropic’s landmark settlement is a first major win for authors and publishers — although it wasn’t exactly what some wanted, given that the settlement is small compared to the number of pirated books and that AI training is still considered fair use.

Intel and Fortinet have announced a strategic collaboration to develop the Fortinet Security Processor 6 (SP6), the next generation of the custom silicon behind Fortinet's FortiGate firewalls. Intel will contribute chip design, advanced packaging, and manufacturing to the SP6 program, making Fortinet the first cybersecurity vendor named as an Intel silicon customer.

Intel told Tom's Hardware that SP6 will be built on Intel 4, the EUV process the company has so far used only for its own products, making Fortinet both the first cybersecurity vendor named as an Intel silicon customer and the first named external customer for the node. However, the announcement specifies no production timeline, and it comes in the same Q3-Q4 2026 window in which CEO Lip-Bu Tan said the company expects commitments from multiple foundry customers.

SP6 will draw on what the companies described as Intel's expertise in disaggregated semiconductor design and advanced packaging tailored for both AI-enabled and cost-sensitive applications.

That points to a chiplet-based part, which would be a departure from the current SP5, a monolithic 7nm Arm-based SoC that Fortinet launched in 2023 for its entry-level and mid-range FortiGate appliances. The deal will help Fortinet "accelerate and strengthen our ASIC strategy," said Ken Xie, founder, chairman, and CEO of Fortinet, in the announcement.

Intel 4 was the company's first process node to use EUV lithography and entered high-volume manufacturing at Fab 34 in Ireland in September 2023, where it produces the compute tile for Meteor Lake-based Core Ultra chips. The node didn't appear among the processes Intel listed for external foundry customers in its fiscal year 2024 annual report, which named 18A, Intel 3, Intel 7, Intel 16, and a 12nm process co-developed with UMC. Intel said the SP6 work reflects plans it laid out for Intel 4 several years ago, including support for custom networking ASIC workloads.

Microsoft agreed in early 2024 to build an unnamed custom chip on Intel's 1.8nm-class 18A node, a deal that reportedly covers a next-generation Maia AI processor. That announcement followed a similar pattern, with no product details, node variant, or timeline at signing and specifics emerging over the following 18 months.

Intel CFO David Zinsner said in March that the company was fielding inbound interest in 18A-P from prospective foundry customers as yields improved, and Tan told CNBC in May that foundry commitments were expected in the second half of 2026.

Fortinet does bring real volume, though, if not marquee volume. IDC ranked Fortinet first in firewall appliances shipped as of early 2023, with a 48% unit share. The company ships its own ASICs across its entry-level and high-end FortiGate ranges, and SP6 extends a silicon program now in its sixth generation.

Neither company committed to work beyond SP6, though the release described the agreement as a starting point, with further collaboration on chip technology and manufacturing under discussion.

Chinese AI developer Z.ai (formerly Zhipu) has finished building a 1GW data center stocked exclusively with domestically made chips and has switched part of it on, Bloomberg reported Monday, citing a person familiar with the matter. The facility will train the company's GLM model family, and the source told Bloomberg that Z.ai has now built or operates several computing clusters holding more than 10,000 chips apiece. A gigawatt is enough electricity to run roughly 750,000 homes, which puts the site among the largest ever stood up by a Chinese AI lab.

The source didn't name the chip supplier, but Z.ai's recent training history points to Huawei. The company released GLM-5.2 in June, an open-weight model purportedly trained entirely on Huawei Ascend accelerators with no Nvidia hardware involved, and it topped the open-weight leaderboards within a week. Z.ai, formerly known as Zhipu, has also been on the U.S. Commerce Department's entity list since January 2025, which cuts off legal access to Nvidia silicon and leaves domestic parts as its only supply line.

Raw power draw flatters the comparison with U.S. sites of similar size, however. Chinese accelerators such as Huawei's Ascend line trail Nvidia's current Blackwell parts on performance per watt, so a gigawatt of domestic silicon delivers less usable training compute than a gigawatt consumed by Nvidia systems.

Beijing is drafting a plan to spend roughly 2 trillion yuan ($295 billion) over five years on a nationwide grid of AI data centers, with at least 80% of the underlying technology sourced from Chinese suppliers. Filling those facilities is a big problem, though, as SMIC's most advanced stable node — the roughly 7nm-class N+2 process — is running above 93% utilization.

In addition, scarce domestic HBM constrains how many Ascend-class accelerators Huawei can assemble, and Huawei shipped around 812,000 AI chips last year. Ultimately, China can put up a 1GW shell much faster than the chips needed to draw 1GW can be produced.

Z.ai's rival Moonshot suspended new subscriptions on Sunday, saying in a social media post that it wanted to prioritize compute for existing members after the launch of its Kimi K3 model. Z.ai itself is on track for $1 billion in annual recurring revenue after hitting its 2026 sales target in July, people familiar with the matter told Bloomberg earlier, and the company recently raised billions of dollars through a Hong Kong IPO and a follow-on share sale.

The source didn't disclose the data center's location, its cost, or its construction timeline.

TSMC intends to raise base quotes on advanced chip production services by up to 10%, according to Nikkei, which cites people with knowledge of the matter. The price hike reflects increased demand for sophisticated processors by the AI sector, raising costs of tools and materials, as well as amplified investments in new production capacities.

For advanced process technologies — which TSMC considers 7nm-class and below — TSMC plans to raise baseline prices by 5% to 10%, depending on the particular production node and customer, the report claims. Furthermore, customers that need additional HPC chip capacity beyond their original volume requirements will reportedly have to pay another 10% to 15% premium on top of the standard increase, which means that some services will get a price hike of around 25%, if the report is accurate.

TSMC also intends to increase prices for mature manufacturing technologies, including its 12nm, 16nm, and 28nm-class nodes as well as other legacy fabrication technologies, the report claims. Increases could reach 10%, although certain nodes will reportedly see smaller adjustments, according to Nikkei.

Advanced technologies generated around 77% of the foundry's revenue in Q2 2026, whereas mature nodes accounted for 23%, which essentially means that TSMC is hiking prices on all of its services.

The company reportedly began discussing the new pricing with customers around June and completed negotiations in July. Rather than introducing higher rates immediately, TSMC opted to implement them from the beginning of 2027 to give clients like Apple, AMD, Nvidia, and MediaTek additional time to accommodate the changes and adjust their prices accordingly.

Since TSMC produces the lion's share of advanced processors for AI, HPC, networking, and smartphone applications, its price hikes will inevitably create a ripple effect in the industry and will make almost all electronics more expensive.

TSMC is not alone in raising prices these days. Vanguard International Semiconductor has also raised prices, while UMC began implementing increases in July. Also, memory makers have increased prices significantly, making TSMC management jealous. Intel also recently increased prices of its client and data center CPUs, citing market demand.

"I am really jealous about memory companies' 86% gross margin," said C.C. Wei, chief executive of TSMC, during the company's earnings call with financial analysts and investors. "86% [margin at memory makers] – 68% [margin at TSMC], I will be happy about that."

TSMC rarely comments on its prices to a large degree because they vary based on volumes and relationship with a particular client. Nonetheless, the head of the company stressed that the company has no intentions to increase prices suddenly or dramatically.

"So we do not suddenly increase our price by which I like to have 4x or 5x," Wei said. "You cannot survive for that kind of... for your customer to survive for that kind of price increase. So we earn our value, and we make sure that our profit, our gross margin, is enough for our long-term sustaining expansion, that is to the benefit of my customers and TSMC also, that is our philosophy."

Intel just announced another round of layoffs more than a year after CEO Lip-Bu Tan warned of “tough decisions” required to get the company back on track. This decision has resulted in the reduction of its headcount by more than 35,000 since 2024, when ex-CEO Pat Gelsinger revealed that its data center and foundry divisions have lost $1.6 billion. The latest announcement came months after the last job cuts and is still happening despite the company posting a strong first quarter this year. According to Oregon Live, its share price has more than tripled from a low of $23 per share to more than $96 today, with the data center group reporting sales of $5.1 billion for the first quarter. However, this good performance seems not to have affected the firm’s plan to streamline its operations.

“As part of our broader strategy to become a more focused and efficient company, (the data center group) is aligning its organization to ensure it has the right roles and skills in place to position the business for long-term success,” Intel told the publication in a statement. It also added, “We are committed to treating all impacted employees with respect and providing resources to support them through this transition.” Unfortunately, the company did not say how many positions will be cut and when it is happening — it only assured that the reduction-in-force won’t affect its business commitments and plans to launch new products.

While the AI infrastructure build-out was initially powered by GPUs and memory chips, advancements in agentic AI have greatly increased the demand for CPUs, putting Intel in a good position with its Xeon chips. Aside from that, the company is reporting customer interest, possibly including Apple, for its 18A and 14A nodes. It’s also planning to launch an AI GPU in the latter half of 2026 that will compete against Nvidia’s RTX Pro 5000 GPU.

This is a slow reversal of its misfortunes in the first half of the decade, but it seems that it’s not happening fast enough for its data center group employees who will be affected by the job cuts. It’s quite surprising that Intel plans to gut its Data Center group, which is one of its strongest performers and is in a good position to take advantage of the ongoing AI data center boom. But despite the high demand for AI data centers, it seems that the company still needs to cut its personnel count to streamline its operation.