17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

New research data from Omdia shows U.S. shipments of desktop PCs and laptops fell by 7% year on year in Q1 of this year, totaling just 15.8 million devices. Compounded at both ends, this figure comes from strong Q1 2025 sales as companies and individuals rushed to get ahead of President Trump's tariffs, and the ongoing component shortages, which have driven up prices to unreasonable levels for just about everything.

This decline is the worst since the end of 2023, and is most evident in the lower-end segment. As prices have risen, people haven't been able to buy as many new systems, and those they do buy are more expensive. Average PC prices are predicted to exceed $1,000 by the end of the year, alongside consecutive year-on-year declines in overall sales.

The silver lining to all this is that it isn't projected to last forever. Omdia's data suggests PC sales will start to recover in 2027, and by 2028, are estimated to reach similar levels to 2025, driven by a resurgence in consumer spending. Funnily enough, that coincides with when we're expecting to see new memory fabs come online.

These predictions largely line up with a report from IDC from earlier this year, but even that pessimistic outlook on the year didn't have average selling prices crossing $1,000 so soon.

Pricing everyone out

Nobody who's considered or purchased an upgrade for their PC or laptop in the past year is unaware of price rises, but Omdia's data makes it very clear: ultra budget computing is being eaten alive by component shortages. Shipments of sub-$500 PCs declined 18.7 year on year for the first quarter of 2026. This stat is a key driver of the 14.4% drop in PC shipments when compared to 2025.

That's because people are just buying less, rather than buying more expensive systems. Although Omdia tracked an average 4% increase in PC selling prices in Q1, that isn't even remotely reflective of the price rises we've seen on individual components and systems. We've been reporting on these individual component price rises for months, with consistent memory supply shortages, which can be linked to production of HBM, over commodity DRAM. This has caused memory prices to increase by hundreds of percent; almost all major PC makers, including Apple, have faced price hikes on their products.

This has led to the average price of a PC set to reach over $1,000 for the first time this year. Prices are expected to increase 12% year on year in Q2, rising as high as 15% by Q4 2026.

It's not just consumers driving this, though. With businesses looking to buy up "AI PCs," capable of handling local language model processing, they're spending more to get them. The overall share of AI PCs grew to 44% in Q1 this year, though that could also be because manufacturers' definitions of an AI PC have been fairly fast and loose.

Who gets the biggest deckchair?

While the whole PC industry is shuddering under the dual icebergs of component shortages and price increases, the pricing problems are affecting the major manufacturers differently, and it's resulted in a rearranging of who's on top. Where HP was firmly the ruler of the roost last year, it has fallen, losing close to four percent in market share, leaving just enough room for Dell to take the crown.

With 25% of the overall PC market, and the only company to show serious positive growth over this period, Dell shipped more systems than Apple and Acer combined in Q1 2026. Lenovo also managed to ship slightly more systems than this time last year, securing it a firm third place in the line-up, and now nipping at HP's heels.

Outside of Lenovo and Dell, though, everyone else took a hit. HP is down, Acer is down, and even Apple is down 1.6% year on year. The nebulous "others" category that contains other major and minor manufacturers declined dramatically, too, falling over 13% year on year.

Prediction is difficult, especially about the future

Omdia's research suggests that for those holding off on buying in 2026, the next year might be when they decide to bite the bullet anyway. The education sector is forecast for a massive near-29% drop in 2026 annual growth for PC shipments, but as far as Omdia sees it, it's coming back strong next year.

In 2027, Omdia predicts a large 21.3% increase in annual PC shipments. That might occur more towards the end of the year, when pricing and availability might have improved a little, and we'll have new generations of CPUs from AMD, Intel, Nvidia, and Qualcomm to play around with. That should help make existing devices more affordable. Although next-generation devices are likely to use more memory, so here's hoping component prices have stabilized at least a little by then.

But it's not just the economically-minded education sector that is set for a resurgence. Omdia predicts just about everyone will be more inclined to buy a new PC in 2027. Consumer confidence could return with a 7.5% growth over the year. That's coming off the back of a weak 2026, but it might be the start of when things may begin normalizing once more.

Ultimately, Omdia believes it will take until 2029 before we see U.S. PC shipments reach their 2025 levels, showcasing just how damaging the AI buildout has been on one of America's most reliable industries of the past few decades.

On June 12th, the U.S. Commerce Department issued an export-control directive barring Anthropic from supplying Fable 5 or Mythos 5 to any foreign national, forcing the company to disable both models worldwide. The next day, Beijing-based Z.ai, formerly Zhipu AI, began rolling out GLM-5.2, an open-weight model it released under a permissive MIT license. The new model was purportedly trained entirely on Huawei Ascend chips with no Nvidia hardware.

Within a week, GLM-5.2 had climbed to the top of the openly available leaderboards, Z.ai's market value had passed HK$1 trillion (about US$128 billion), and the most capable model many users outside the U.S. could legally access was a free download from a company that sits on Washington's trade blacklist.

Trailing Anthropic

GLM-5.2’s results are both strong and uneven, taking first place on Design Arena's human-preference coding board, finishing roughly 10 Elo points ahead of Fable. It also ranks as the top openly available model on Artificial Analysis's Intelligence Index v4.1, where its score of 51 sits ahead of MiniMax-M3, DeepSeek V4 Pro, and Google's Gemini 3.1 Pro Preview. On the SWE-bench Pro, it scored 62.1, compared to GPT-5.5's 58.6.

In terms of longer work, such as Code Arena’s front-end board, the picture changes somewhat, with GLM-5.2 landing second behind Fable 5. On Artificial Analysis's AA-Briefcase test, which scores multi-week knowledge tasks built from thousands of fragmented inputs, Fable 5 led with 1,587 Elo, followed by Opus 4.8 at 1,356, and GLM-5.2 in third place at 1,266, before the export ban took Fable out of contention.

It also trails on raw terminal work, scoring 81.0 on Terminal-Bench 2.1 against Opus 4.8's 85.0 and GPT-5.5's 84.0, while clearing Google's Gemini 3.1 Pro at 74.0. GLM-5.2 holds the top accessible position today, partly because the models that beat it on these benchmarks are largely an Anthropic pair, and Fable is now switched off.

No Nvidia

GLM-5.2’s training stack is a slap in the face of Washington’s efforts to curtail Chinese model development. Z.ai has been on the U.S. Entity List since January 2025, cutting it off from Nvidia's H100, H200, and B200 accelerators, and it says the GLM-5 family was trained on roughly 100,000 Huawei Ascend 910B processors using the MindSpore framework, with no Nvidia silicon at any stage. The export controls on advanced AI chips were designed to keep this kind of result out of reach, but they’ve evidently failed to do so.

That said, the Ascend 910C sits at roughly 60% of an Nvidia H100’s inference performance, per a December report from the Council on Foreign Relations, with a wide gap on efficiency and cluster scale. The same report projects that by as early as next year, the best U.S. chips could be more than 17 times more powerful than Huawei's top parts.

At the same time, Huawei has claimed that a 1,000-chip Ascend cluster handled full-parameter post-training of DeepSeek's V4. If true, this shows that Chinese domestic silicon can now carry training-class jobs, just not at Nvidia’s per-chip throughput or scale. So, while GLM-5.2 demonstrates that a frontier-class open model can be produced on a fully domestic stack, it doesn’t demonstrate that the chips underneath have caught up with Nvidia; model parity =/= hardware parity.

The Fable 5 shutdown

Anthropic released Fable 5 to the public on June 10th, a safety-restricted build of its Mythos 5 model designed to block the cyber and bio capabilities of the underlying system. Just two days later, the Commerce Department suddenly and unexpectedly ordered access to be pulled for all foreign nationals, including Anthropic's own non-citizen staff, after officials cited a technique for bypassing Fable 5's safeguards.

Anthropic said in an announcement following the restriction that the jailbreak it understood to be at issue was narrow rather than universal, surfaced only previously known minor vulnerabilities, and produced behavior also obtainable from other public models, including OpenAI's GPT-5.5. The company said in its statement that it believes the order rests on a “misunderstanding” and is working to restore access. But because the directive covered all foreign nationals, Anthropic had no way to keep the models live for U.S. users alone and disabled them for everyone.

Meanwhile, GLM-5.2’s MIT license lets anyone download, fine-tune, and self-host its weights, which is the basis for calling it a freely available model. Running it, however, is a separate matter: the model carries around 744 billion total parameters, 40 billion of them active per token, with a one-million-token context window. That’s no small footprint and calls for enterprise GPU clusters or high-memory workstations — it’s not something you’re ever going to get running on a desktop — and throughput drops sharply once context runs past tens of thousands of tokens.

The most practical way to use GLM-5.2 is via the API, where Z.ai prices the model at about $1.40 per million input tokens and $4.40 per million output, against $5 and $25 for Claude Opus 4.8, or $10 and $50 for Fable 5. On the AA-Briefcase runs, Fable 5 averaged $31 per task to GLM-5.2's $2.40, a roughly 13-times spread that holds even where Fable scored higher.

The market moved fast with GLM-5.2’s release. Z.ai, which is listed on the Hong Kong exchange as Knowledge Atlas Technology, saw its shares jump as much as 42% intraday on June 22nd to HK$2,980, carrying its market capitalization past HK$1 trillion. Founder Tang Jie has said publicly that a Chinese model matching Fable 5 will arrive sooner than the first-quarter timeline Elon Musk recently floated. There's a nearer date, too. On July 8th, the lock-up on Z.ai's first cornerstone investors expires, freeing a large block of shares to trade, which will give the GLM-5.2 rally its first real test.

The era of AI tokenmaxxing may be well and truly over. Alongside stories of Amazon cutting its AI leaderboard and an unknown company blowing through $500 million worth of tokens in one month, leaked audio has emerged from consulting firm Accenture as it tries to figure out how to rein in rampant token spend at client companies, 404Media reports.

In leaked audio, Accenture acknowledges that certain trivial tasks being offloaded to AI are causing massive token overspend, especially when agentic AI is part of the mix. The staff in the meeting clearly recognizes that not only is AI spend growing out of control at companies heavily adopting the technology, but that there is very little way to predict how much any tasks would cost, or whether there is real value in using AI to complete them.

Accenture has previously been incredibly bullish on AI, even encouraging employees to use it so much that if they didn't, they risked missing out on promotions. But that seems like a policy destined for the AI history books, as Accenture is now clearly aware that it's overspending on AI, and many of its clients are too.

From tokenmaxxing, to token hoarding

For much of the past year, many companies have charged full speed into an AI-heavy business strategy. Amazon had an AI leaderboard, and Nvidia's CEO Jensen Huang said he'd be alarmed if engineers weren't spending at least 50% of their annual salary on AI tokens.

Anecdotally, I know a number of software developers and data engineers who have been encouraged to use AI as much as they can. They have token limits, but they have been encouraged to use all of them and find new ways to do it, too.

This is leading to runaway token spending, something Accenture is seeing in its client data. Accenture’s agentic AI strategy lead, Justive Kwak, was quoted in the audio saying: "What we’re seeing right now is just rapid escalation in AI token spend [...] as companies start to scale AI, moving from like simple chatbots into use cases that feature agentic workflows and automation and then enterprise-wide deployment of some of these tools like Copilot, Claude Code, and Codex."

This isn't something that will be contained to just a few firms, either, he said. “It’s really not a niche problem. It is a problem that every enterprise will face if they are bullish on AI, if they haven’t already,” he said, adding that token spend was increasing, “exponentially, as more and more people are starting to use AI.”

But that may be starting to change. Amazon canned its AI leaderboard - it's rumored to be the mystery company with a half-billion dollar AI spend in one month - Uber is capping AI use to cut costs, and Axios reported at the end of May that a number of CEOs and companies were switching to more affordable models, and more closely monitoring employee usage.

Some software developers I know have been using the "caveman" trick to reduce token spend. Even OpenAI CEO Sam Altman said that he was aware token costs were becoming a huge concern for people.

This all comes in the aftermath of the move by many of the major AI providers to token-based billing. Where previously subscriptions offered very favorable rates for AI use, suddenly companies were having to pay for the tokens they input, and the tokens the AI output - even when it was verbose, or made mistakes, or required follow-up correction.

As the Accenture call shows, it's making even some of the most AI-bullish organizations question their usage, because measuring the spend and the return on that investment is proving all but impossible.

As Kwak said in the leaked audio, "Leadership, especially at the CFO, COO, and CIO level, are still asking the question of whether they’re getting value from what we’re spending on in the context of AI.”

How do you measure return on investment?

Although large language models are proving to be extremely useful in niche cases, their effectiveness at a broader range of tasks is more nebulous. Especially when it comes to financing it. When managers and executives look at AI budgeting and a return on that investment, it's hard to square away the numbers.

When you can't know how many tokens a task will take to complete, or whether the task will be completed effectively on the first, second, or third attempt; when you can't completely control the length of the output, or know whether that output will be wrong, or a lie, or just a random hallucination, how do you measure return on the investment in that tool?

"We’re hitting this inflection point where AI is becoming material to the cost structure; spend is becoming very unpredictable," Accenture's Kwak said during the meeting. Although the overall bill of AI costs is visible, he suggested, finding the specific value attributed to that token spend was not.

This seems to have created a culture of task hierarchy within Accenture, where some tasks are deemed more worthy of AI token use than others. When Kwak positioned himself to show some slides during the meeting, Accenture's client group lead, Stuary Henderson, joked that he hoped Kwak didn't use AI to convert a PDF into images and then markdown files.

“I’m learning that’s one of the big token chewers," he said. “Turning PDFs into markdown: is that right?”

Kwak agreed that Accenture data did show some tasks being completed using AI that didn't really need it, and were using unnecessary tokens because of it. Much of that problem, he suggested, was down to non-technical staff overusing it.

“We’re seeing from some of the data internally at least that it’s actually not our engineers that are driving the token consumption. It’s a lot of the non-engineers that are doing some of those behaviors."

Now that Accenture has encouraged heavy AI adoption among its clients, it finds itself in the bizarre position of having to discourage it or at least encourage more studious use of it. It now sees its next opportunity as a way to advise clients on how to "think about token economics."

It's working on a tool called "Token IQ" to help advise clients, according to the call, but hasn't made any announcement so far.

What's clear from the Accenture leak and actions of some of the major tech companies, which have previously been so bullish on AI use, is that the finances of mass AI adoption at the per-token scale don't line up. Without a clear way to measure the return on AI investment, we may find even the most tokenmaxxing companies look to restrict access and spend through the rest of 2026 as they re-address AI strategy.

Despite disagreements over trade policies with China, the U.S. and the Netherlands have signed the European nation to the Pax Silica initiative of countries looking to reduce reliance on China for key raw materials and manufacturing expertise in the AI industry, as reported by Reuters. With the Netherlands playing host to the key supply chain company, ASML, Europe's largest tech company, and the most advanced manufacturing of cutting-edge photolithography machines for semiconductor fabrication, this is a big strategic win for the U.S.-led initiative.

Dutch ​Trade Minister Sjoerd Sjoerdsma travelled to Washington this week to sign the deal, meeting with U.S. Commerce Secretary Howard Lutnick and fellow lawmakers as part of ongoing negotiations around trade in high-tech chips and hardware, particularly with China.

Speaking with reporters, he said that the U.S. and the Netherlands have shared goals in preventing sensitive technology from ending up in dangerous hands - the Netherlands famously seized key Dutch chip manufacturer Nexperia from its Chinese parent company, Wingtech, in 2025. However, he also raised concerns over American legislation that would make it difficult for companies like ASML to even service machines and tools already delivered to countries like China.

That could affect the Netherlands' national security and market position of key Dutch companies, he said.

Pax Silica - Speremus ut diu duret

The Pax Silica, or "Silicon Peace" initiative, was set up in December 2025 by the U.S. Department of State as a direct plan to reduce reliance on China and to build more robust, Western-aligned supply chains for key elements in the semiconductor, AI, and rare-earth element industries. At its outset, Pax Silica secured non-binding signatures from seven countries, including Australia, Israel, Japan, South Korea, Singapore, the United Kingdom, and the United States. They were joined in the months that followed by Greece, Qatar, the UAE, India, Sweden, Finland, the Philippines, and Norway.

Canada and Taiwan have both been invited to join and are said to be participating in summit sessions, but haven't officially signed just yet. The Netherlands did effectively join in December 2025, but was described as a "non-signing partner" in the initiative.

There are ongoing disputes between the U.S. and the Netherlands over whether ASML should be allowed to service and sell less advanced chip fabrication machines to China, while still restricting access to the latest tools.

Those discussions are reportedly still ongoing and were brought up in the meeting between Lutnick and Sjoerdsma this week. The Dutch official has been quite frank in his public statements on the Match Act bipartisan bill that would place restrictions on companies supplying to China.

“The Netherlands’ starting point is that every country is responsible for its own laws,” Sjoerdsma said in May, via Reuters.

Under the silicon thumb

A key story in the global race to adopt and supply AI through infrastructure building and rapid development has been access to the raw materials, tools, machines, and expertise required to create it. That's mainly had the United States and China at loggerheads with one another, with the former restricting access to cutting-edge Nvidia GPUs and other semiconductor products, and China rowing back access to its manufacturing and raw material industries.

But while that's acted as a tit-for-tat backdrop to U.S. and Chinese trade relations and particularly the mercurial needs and demands of President Trump, the divestment of global supply chains from traditional Chinese sources has spread globally. Nexperia was one key Dutch entity that was brought back in-house from Chinese owners, and in June 2025, Taiwanese firm Pegatron announced new production facilities in Mexico and the U.S. to move away from reliance on China.

The U.S. has also been trying to restrict China's access to high-tech hardware for a number of years. President Trump signed the National Defense Authorization Act in 2019, which effectively banned Chinese firms Huawei and ZTE from being used in any U.S. government agencies. Both companies were later designated as threats to national security in 2020. Under the Biden administration, the U.S. implemented a new series of export controls in 2022 to constrain China's ability to accelerate its high-technology and chip manufacturing industries.

This led to a boom in domestic Chinese chip production, as well as a rapidly expanding black market smuggling industry that ultimately saw officials in U.S. firms jailed, and even Nvidia potentially implicated.

But in 2026, even as the U.S. has approved the sale of some high-end Nvidia chips to China, its new Pax Silica Initiative and MATCH Act are putting more pressure on China than ever before, and global partners aren't entirely happy about it.

Under the bill, foreign-owned companies like ASML that don't comply with the restrictions on business dealings with China could find themselves losing access to U.S. components, software, or customers. Although the world still needs ASML - it's one of the tightest bottlenecks in the global chip supply chain - becoming part of the Pax Silica initiative could prove paramount for advanced economies wanting to make the most of advances in AI and chip fabrication.

Although Dutch officials still clearly have reservations about the MATCH Act, it's not clear how much leverage they can have over it, or whether it's possible to ignore its claimed mandates.

Unsteady ground

The Netherlands and other strategically aligned economies with a foothold in the AI supply chain face a tricky situation in 2026. Initiatives like Pax Silica raise the prospect of greater autonomy in the global supply chain, with less reliance on China for key materials, tools, and manufacturing expertise. But that may simply replace one dependency with another, trading exposure to Beijing for greater oversight from Washington, and even coercion if certain controls aren’t adhered to.

For the Dutch, ASML isn’t just a key company. It is one of the world’s most important technology pillars and helps the Netherlands punch well above its weight in global supply-chain politics. Without ASML, manufacturers like Samsung, Micron, and TSMC, and component designers like Nvidia, would not be able to build the cutting-edge hardware they can today. That gives the Netherlands real muscle when pursuing its own interests.

But it also makes ASML a target for legislation that could limit Dutch autonomy and force tighter integration with larger players like the United States, without whose components, software, and market access ASML would struggle.

That tension is unlikely to disappear. Even if the U.S. midterms later this year help leash some of the more turbulent aspects of the Trump administration, they won’t end American ambitions to pull control of the global chip and AI supply chains away from China, and tuck it into Washington’s own catalogue of control.

Servers running x86 processors from AMD and Intel used to rule the market, both unit and money-wise, less than a decade ago, but fast forward to today, Arm-based machines command well over 45% of the server market, according to data released by IDC. While technically x86 machines still control 52% of the market in terms of revenue, the real winner is a different category altogether: GPU- and ASIC/FPGA-accelerated systems, which generated over 70% of the global server revenue in the first quarter of 2026.

Server market reaches $122.6 billion in a single quarter, Dell leads the game

IDC estimates that the global server market generated a record $122.6 billion in revenue in the first quarter of 2026, up 30.4% year-over-year, as spending on AI infrastructure remained particularly strong.

Sales of ODM Direct servers — custom machines ordered by hyperscalers that run merchant or custom silicon — accounted for 50.2% of the revenue (down from 64.1% in Q1 2025) and reached $61.53 billion, up modest 2.1% year-over-year*. By contrast, sales of standard servers from well-known brands grew at a much higher pace, which suggests that branded vendors such as Dell, HPE, Supermicro, and others won a larger portion of AI infrastructure deployments than they did a year earlier. That was probably made possible by accelerating enterprise AI deployment and sovereign AI projects, which tend to buy machines from branded vendors, as well as hyperscalers increasingly turning to well-known suppliers for AI hardware.

When it comes to vendor rankings, Dell remained the largest server supplier by revenue with a 16.5% share of the market after its revenue surged 244.1% year-over-year to $20.3 billion, which was driven by exceptionally strong AI server demand. Supermicro remained in second place with $9.3 billion in revenue and a growth of 128.9%.

Lenovo ranked third with $5.6 billion and 36.5% growth, while IEIT Systems (which is a part of the sanctioned Inspur Group) dropped to fourth after revenue declined 7.0% to $4.0 billion. HPE was No.5 with $3.7 billion in revenue, up 17.2%. Other vendors — from Asus to Atos and from ASRock Rack to Gigabyte — commanded 14.8% of the market with $18.11 billion in revenue, up from 13% and $12.21 billion in the same quarter a year ago.

Arm-based machines rapidly gain revenue share

As AI servers dominated the market in Q1 2026, systems with various types of accelerators accounted for over 70% of the revenue. However, the rise of Arm-powered machines is the elephant in the room that is hard to miss, as it represents a tectonic shift in the whole market, both to the Arm instruction set architecture (ISA) in general and custom-built Arm CPUs designed by hyperscalers.

Non-x86 platforms generated $58.7 billion in revenue, a 107.6% increase year-over-year, which lifted their share of the market to 47.9%. Most of the non-x86 systems are Arm-based AI machines (think Nvidia's NVL72) as well as systems running custom CPUs, AWS, Google, and Microsoft, just to name a few. Still, also keep in mind IBM Z mainframes and IBM Power Systems (including storage) that use CPUs featuring proprietary non-x86 and non-Arm ISAs and which still generate $1 billion or more in revenue. IDC claims that Arm-based machines accounted for more than 95% of non-x86 revenue, so it is safe to say that Arm-based machines commanded over 45% of server revenues in Q1 2026.

One of the reasons why Arm-based machines now command a huge chunk of the server market is because they are used inside such systems as Nvidia's NVL72 'Blackwell' that sell for up to $6.5 million per unit. Each NVL72 rack-scale solution carries 36 compute trays with two Blackwell GPUs and one Grace CPU per unit, so while unit-wise each we are only talking about 36 processors, dollar-wise one NVL72 machine is as expensive as 928 entry-level 1P server (for $7,000) for cloud or edge applications or 433 higher-end 2P servers (for $15,000) for cloud or virtualization applications.

Given the fact that Nvidia will continue bundling its own Arm-based Vera CPUs with NVL72 'Vera Rubin' machines that will be more expensive than their Blackwell ancestors, we will not be surprised that Arm-based machines will account for well over 50% of the server market revenue in the second half of this year or in 2027. Also, keep in mind that Nvidia plans to sell server racks featuring only Vera CPUs for agentic AI applications, which will further drive sales of Arm-based machines.

Accelerated servers: The real winner

Since AI servers dominate server sales, it is not surprising that sales of accelerated servers are increasing. Systems equipped with GPUs produced $68.9 billion in revenue during the quarter (up 24.8% compared to the same period a year earlier) and accounted for 56.2% of all server sales. Servers based on other accelerator types, including custom ASICs and FPGAs, expanded to $17.7 billion, up 122.1% YoY. As a result, accelerated servers earned $86.6 billion in Q1 2026, which is around 70.6% of all server revenue.

X86 servers remain unit volume champions, but suffer from shortages

In contrast, x86 server revenue declined 2.9% to $63.9 billion, though IDC attributes this weakness to supply limitations rather than deteriorating demand. The market research firm claims that the industry's primary constraint is no longer customer appetite for general-purpose servers, but rather the availability of key components, including CPUs, DRAM, NAND memory, and hard drives.

Without any doubt, x86 servers remain working horses for the industry. In fact, many of them use accelerators, including ASICs, FPGAs, and GPUs, as they are used for a wide range of workloads, including AI, supercomputing, simulations, encryption, video transcoding, and many more.

AMD and Intel shipped nearly 20 million EPYC and Xeon SP processors for data center systems in 2025, according to Dean McCarron, the head and principal analyst at Mercury Research. He believes Nvidia is on track to ship four million Grace and Vera CPUs this year, which is considerably lower compared to shipments of AMD and Intel. It is hard to estimate how many custom Arm-based CPUs are deployed by AWS, Alibaba, Google, and Microsoft, but it is safe to say that we are talking millions of CPUs here; otherwise, the companies would not be able to justify development and production of custom silicon.

From a volume perspective, x86 servers remain the most popular machines, and it will probably take some time before ARM can challenge x86 in mainstream general-purpose servers. Nonetheless, it is safe to say that Arm-based data center CPUs are catching up with x86 parts in terms of volumes.

Summary

The global server market hit a record $122.6 billion in the first quarter of 2026 as AI infrastructure spending continued. Accelerated systems powered by GPUs, custom ASICs, and FPGAs generated more than 70% of server revenue, while Arm-based platforms — including Nvidia's Grace Blackwell as well as custom CPUs from Arm, Google, and Microsoft — captured nearly half of the market.

Although x86 servers based on AMD EPYC and Intel Xeon processors remain dominant in shipment volumes, supply shortages of CPUs, memory, and storage components constrained revenue growth, which further enabled Arm-powered AI-optimized systems to gain share. But while at 20 million data center processors per year, x86 volumes are untouchable for Arm today, things may change in the coming years. Nvidia is on track to ship 4 million CPUs in 2026, and other developers of custom Arm-based CPUs are certainly not standing still.

*There is one significant difference with IDC's 'ODM Direct' classification. IDC classifies revenue according to which company invoices the customer, not necessarily who manufactures the hardware. As a result, while many AI servers are built by ODMs like Compal, Foxconn, or Quanta, they are sold under brands like Dell or HPE. As a result, while the latter get more business from enterprises or sovereign AI deployments, this does not mean that big ODMs are losing business; they are actually gaining it, as the appetites of hyperscalers like AWS, Google, Meta, or Microsoft are not going anywhere, just demand from new entrants emerges.

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

World leaders have raised concerns over the U.S. administration's recent placement of export controls on Anthropic's frontier AI models, Mythos 5 and Fable 5, over national security concerns, Euronews reports. Suggesting this was a "wake-up call," moment, politicians and prominent figures in the UK, Canada, France, and the Netherlands, among others, said that frontier AI model access was now "critical infrastructure," and something that they desperately needed better control over.

Many of them didn't even point at America directly, merely saying that if governments around the world can block access to the latest AI technologies arbitrarily, then it was within their national security interests to find alternative solutions. That said, that likely means building their own national AI efforts, fragmenting the industry, and reducing reliance and dependence on U.S.-based companies like OpenAI, Google, and Anthropic.

Although Reuters reports the heads of U.S. technology firms like Nvidia and Adobe have been in talks with the Trump administration in the hopes that it will reinstate access to Fable 5 and Mythos 5, arguing that the bans hamper cybersecurity defensive efforts, the damage already appears done. The trust that some have had in access to U.S. frontier models is gone.

The Myth, the Fable, the Cautionary Tale

Anthropic debuted its 'game-changing' cybersecurity-focused AI model, Mythos, in April, claiming it was too dangerous to give the world wider access, but it brought in a few select companies and organizations under Project Glasswing to improve their code security. There was a lot of fearful marketing involved, but it was genuinely very good at finding flaws in old codebases. Anthropic suggested similarly capable models would be out in the wild within 18 months, so everyone needed to prepare.

But in early June, it widened access to Mythos to 150 global organizations, and then a few days after that, dropped Fable 5, a Mythos-grade AI model, but with additional safeguards to protect against it being used for nefarious cybersecurity tasks. Despite those would-be protections, the U.S. government quickly swooped in and shut it down, claiming it had been jailbroken and was too dangerous to have in the wild. It placed export controls on the model, and by June 12, it was offline and inaccessible.

On an individual level, the Claude subreddits have been filling up with programmers crossing their fingers that they'll be given access to Fable 5 again soon, but the more pronounced effect impacts global politics and national security.

Wake Up Call

Shutting down access to Fable and Mythos didn't just mess with programmer workflows. It shut down government and private projects all over the world, most of whom assumed that model access was all but guaranteed. Even if they didn't own the models, the free market would ensure they always had access to the best. But with the U.S. government's export block, that paradigm has shifted.

“The United States is once again demonstrating what we Liberals and Democrats have warned about so many times since Trump entered into office; that the US holds a real ‘kill-switch’ over essential technologies and that they are more than willing to use it," said French Member of European Parliament, Christophe Grudler, in a statement.

The concern over the U.S. government having too great a control of frontier AI model access is also leading to calls for Europe to develop its own alternatives, eschewing the need for American company technologies as much as possible.

”These restrictions are a clear example of the current American ‘nobody but us’ mentality," said Dutch Renew Europe MEP Bart Groothuis. "Once again: this shows that Europe needs its own LLM’s and open weight models or face digital colonization.”

Not every leader has been so pointed in their criticism of America. Canada's PM, Mark Carney, made it clear in his statement that “Nobody has done anything wrong in the situation," he said via APNews. However, he warned that "We will have done something wrong if we just accept this, don’t take the lesson, don’t build out and diversify."

The UK's former minister for the Armed Forces and Labor MP, Al Carns, suggested this was just another example of why the UK needed to develop its own cutting-edge AI tools, leveraging its deep expertise in the field to ensure UK sovereign access to the most capable technologies.

Some leaders aren't quite set on going it alone, though. France's President Emmanuel Macron championed a joint French and Indian AI effort. Speaking at an event in Nice on Sunday, Macon said:

“Our two countries share the definition of a reliable, open and safe AI, that could be trusted, that could be responsible, that could be ethical," he said, via TribuneIndia.

U.S. companies are scrambling for alternatives, too. Alex Stamos, CSO at Corridor, told The Verge that companies are rushing to sign backup contracts with non-US companies with open weight models so they can continue their projects undeterred, no matter what the Trump administration does next.

In every instance, though, whether leaders pointed fingers or talked up their own efforts, wanted to go it alone or with new partners, the one clear dividing line is that not all of them are looking to move away from America. Alongside a number of other industries impacted by the Trump administration's tariffs and export controls, global partners that once saw the U.S. as the most reliable global partner are increasingly looking elsewhere as that evaporates.

From AI, to Jets, to Search

The U.S. government cutting off access to Anthropic's Frontier models happened quickly, and the consequences of the lost trust are likely to extend for years, or even decades, and affect far more than chips and models.

Citing the recent case of Anthropic model access being pulled, France has announced it is switching from using a U.S. data and analytics firm, Palantir, for a domestic alternative, as Reuters reports. France is also transitioning government departments away from using U.S.-based messaging apps like WhatsApp, with a national alternative, according to Le Monde,

Wired also highlights a number of instances of EU governments and organizations shifting away from U.S. tech firms, including changing default search engines from Google to Qwant, a move towards open-source office software developed in the EU over Microsoft and Google options, and many are ditching Amazon AWS and other U.S. cloud services.

This recent Fable 5 shuttering is likely to only accelerate these efforts, as the reliability of access is called into question once again. But unraveling the EU and the rest of the world from America won't be easy, or even achievable, even in the long term. The global economy is still too integrated for that to be truly viable.

But the desire and impetus are there. For key industries that impact national security - and AI alongside chip fabrication are becoming clear pillars in that space - national alternatives seem all-but-necessary for major militaries and economies. Whether that creates a multi-polar AI world, or just cements the clear headstart and advantage held by countries like the U.S. and China, remains to be seen.

While hyperscalers rush toward expansion amid the swelling demand for AI data centers, Marvell last week shared its vision for an optical interconnect solution that can theoretically pool resources between discrete data centers across thousands of kilometers.

Optical interconnections are steadily being deployed across the industry, over both short and long-distance connections, and we're going to be seeing much more in the future, according to Matt Murphy, Chief Executive at Marvell, speaking at Computex 2026.

"Imagine future data centers, a globally optically interconnected data infrastructure," Murphy said. "These rigid boundaries we have today, and the systems we have, they begin to disappear. Compute can now be pooled, memory can be pooled, and infrastructure can be composed dynamically at scale."

Constrained by distance

Murphy says that workloads no longer fit within one data center, which is why hyperscale cloud service providers increasingly need to build entire campuses consisting of multiple data centers connected by high-speed links, as clusters are becoming larger than a single data center.

Today, connecting multiple data centers within a single campus is not easy or cheap, but relatively straightforward. However, Marvell envisions that in the future it will need to connect data centers that are located at considerable distances from one another.

This is why Marvell is working on coherent optics and long-haul scale across optical networking technologies, which will connect data centers separated by thousands of kilometers. Marvell already has products which enable such connectivity today, including the Colorz 1600 1.6 Tb/s coherent optical solution based on a 2nm DSP, which targets inter-data-center connectivity and will sample later this year.

In addition, Marvell says it will offer the Ara 1.6 Tb/s family of interconnect solutions for data centers (with 3nm DSPs) as well as the Teralynx T100 102.4 Tb/s Ethernet switch, which supports 512 ports running at 200 Gb/s or 64 ports running at 1.6 Tb/s.

Murphy argues that today's architectures are constrained by distance because of copper interconnects: CPUs sit near memory because latency matters, GPUs sit near memory because bandwidth matters. As a result, workloads must be partitioned according to those physical limits. The head of Marvell claims that once optical interconnects penetrate scale-up interconnects, scale-up domains will not be limited by copper cable lengths, and those constraints will begin to disappear.

Nowadays, scale-up AI solutions, such as Nvidia's NVL72, are connected using copper wires, but scale-out connections tend to use optical interconnects. Once the number of AI accelerators within scale-up systems increases, they will also have to move to optical links, according to Marvell. This means that virtually all data center-grade interconnections will become optical, which might inspire hardware developers to reconsider the architecture of data centers.

Pooling resources

Murphy presented a rather interesting vision: firstly, optics will expand scale-up domains from 72 or 144 accelerators to 1,000 or more. But after that, optical connectivity will enter servers themselves. This will enable developers to disaggregate CPUs, accelerators (Marvell calls them XPUs), and memory into separate pools as distance will no longer matter, enabling better configurability and utilization.

"It is a data center without distance, where compute, memory, networking, and photonics operate as one unified system, where millions of resources across the data center can work together as if they were one machine," the head of Marvell said.

Keeping in mind that hyperscalers deploy hardware worth billions of dollars, even a 10% higher utilization will save a lot of money, and companies like Nvidia are clearly paying attention.

"In today's systems, the ratio of CPU and XPU or GPU is fixed, so these ratios have to be defined at the time the system is built and deployed, but no two workloads require exactly the same ratio," Murphy stressed. "Imagine a completely disaggregated architecture, XPUs in one system, memory in another, generic CPUs in another."

Today, companies buy something like an NVL72 system and get a fixed ratio of CPUs, GPUs, and memory, which may be efficient for certain workloads and inefficient for others. In the future, operators will be able to assemble a virtual machine from shared pools of systems, allowing for customization and flexibility, based on the type of workload. If a workload needs more memory than compute, operators often have to buy additional GPUs just to get the extra HBM, but they may just get memory in the future if Marvell's vision comes to pass.

"Once we decompose the system into separate pools of compute, memory, and they are all optically interconnected, we can then compose dedicated systems on the fly, which are then optimized wherever the workload is," Murphy said. "For the first time, architects can begin designing AI systems around the needs of the model, not around the limits of the interconnect."

One detail

While Marvell has the know-how to interconnect data centers across thousands of kilometers and technologies that enable pooled data centers, these visions do not necessarily intersect. Data centers located thousands of kilometers away cannot share resources — a 1,000 km round-trip takes light 10ms — which makes such long-distance resource sharing inefficient from a latency point of view.

However, Marvell's technologies enable hyperscale CSPs to synchronize AI campuses, access distributed storage, replicate data, and perform other operations that do not depend on latency. Meanwhile, the synchronization of AI campuses on different continents in a matter of hours could be a killer app for hyperscalers.

Last week at Computex 2026, Wiwynn showed off one of the industry's first Nvidia SCADA (SCaled Accelerated Data Access) servers. Devices such as this are built to handle the extreme data demands of AI data center-focused inference and training workloads, which operate with massive models and datasets, therefore requiring large, fast, and connected devices to serve as the backbone for complex, high-throughput tasks that AI workloads depend upon.

Wiwynn's SCADA server packs up to 96 liquid-cooled solid-state drives and therefore offers petabytes of storage space using currently available E3.S drives, and massive I/O performance. The machine is based on Nvidia's Vera CPU, four RTX Pro 6000 Blackwell graphics cards, four PCIe 6.x switches, and four ConnectX-9 SuperNIC cards.

Storage architecture for AI

Modern AI inference and training workloads often deal with massive datasets that exceed the memory capacity of an AI accelerator's onboard memory, which is why AI applications need to access rapid storage.

While AI training is typically dominated by large sequential transfers, AI inference workloads such as vector search, retrieval-augmented generation (RAG), graph analytics, and KV-cache retrieval often rely on fine-grained random accesses (that frequently involve data blocks smaller than 4KB) with extreme parallelism, as the system deals with thousands of GPU threads.

Traditional CPU-centric I/O cannot efficiently handle such workloads and creates bottlenecks because the CPU must issue commands, manage requests, and control data transfers. Even in advanced solutions like GPUDirect Storage, which allows data to be transferred directly from SSDs to GPUs, the CPU still owns the control path and can become a bottleneck.

The SCADA platform, previewed in late 2025, is designed to allow GPUs access to very large datasets directly and efficiently without involving a central processor. This is impossible to do on conventional machines, as SCADA lets GPUs themselves initiate and control storage I/O operations and the data path.

SCADA runs on PCIe 6.x hardware from partners like Broadcom and Micron, and customers can now build their own SCADA machines with commercially available components. However, SCADA servers have not yet been popularized. In fact, Wiwynn seems to be among the first server makers to even showcase a SCADA server.

Wiwynn's SCADA server

Wiwynn's SCADA server can indeed be a panacea for the problem that is AI storage. It supports up to 96 liquid-cooled E3.S SSDs, meaning that the drives will perform as expected even under high loads. When equipped with 96 30.72 TB Micron 9650 Pro drives with a PCIe 6.0 interface, the server can store 2.949 PB of data.

On the performance side of things, Wiwynn claims an aggregated random read speed of 528 million 4K IOPS, as well as sequential read/write speeds limited by the performance of PCIe switches and/or network cards rather than the drives themselves. As manufacturers expand the capacities and performance of their E3.S SSDs, servers like the one Wiwynn demonstrated at Computex will gain capacity and performance as well.

Architecturally, Wiwynn's SCADA server is an Nvidia MGX rack-compliant system in an 6RU form-actor that has a maximum power consumption of 9 kW. All key components of the machine are liquid cooled, the drives are cooled by six separate cold plate modules that are integrated into the system's liquid cooling loop so to inject coolant to all SSDs simultaneously in order to ensure consistent performance of all drives.

Positioning

Nvidia clearly positions SCADA as tier 3.5 storage servers located behind local SSDs, but ahead of tier 4 remote storage servers that often rely on hard drives.

SCADA machines are meant to feed data to actual compute servers at a very high data transfer rate in small blocks, so its RTX 6000 Pro GPUs act more like very sophisticated storage processors that initiate and handle storage transactions, millions of small storage requests on behalf of AI applications, and pass them to the compute server via the ConnectX-9 cards, while the SSDs and their controllers still perform the actual storage functions.

In general, SCADA is a part of Nvidia's Storage Next vision, which is a collection of technologies aimed to make storage behave more like an extension of GPU memory for AI workloads.

For obvious reasons, Wiwynn does not disclose pricing of its SCADA storage server as it depends on multiple factors, including pricing of 3D NAND, DRAM, and SSDs, not to mention purchase volumes. In any case, an Nvidia Vera-based server equipped with four RTX Pro 6000 Blackwell graphics cards will not be cheap.

Data centers consume significant resources, often to the detriment of local communities. But while water use has been on the lips of those fighting back against data center deployments, the sheer scale of their impact wasn't entirely clear until recently.

Many new U.S. data centers are being built on drought-prone land, and their cooling systems, which seem to consume gargantuan quantities of water, only represent a small portion of their total water usage by 2050. So, what makes up this overall figure for water usage? Cooling, of course, plays a part, but ongoing energy demands and chip fabrication also make up a larger part of the story.

They're consuming how much?!

A recent Guardian report on water consumption cited figures from Xylem, a water technology company. That does raise some questions about the accuracy of the report, and led us to dig further into the numbers from other sources. Although they're not quite the same as Xylem's original reporting, they do paint a similar picture.

Quantifying the sheer amount of water data centers use isn't easy. Much of it depends on the specific hardware being used within the facilities, how they're cooled, and what the local grid infrastructure is like. In a recent MostPolicyInitiative report, it highlights that U.S. data centers in 2023 alone consumed 17.4 billion gallons of water. And that's before all the recent gigawatt+ scale data center projects kicked off. By 2028, direct consumption could increase by as much as 73 billion gallons as some of these new facilities come online.

But the keyword, there, is direct. The UNU Environmental Cost of AI's Energy Usage report from earlier this year highlighted how global data center electricity consumption required just under a trillion gallons of water in 2025. AI workloads account for around 20% of that, or 200 billion gallons. That equates to around 300,000 Olympic swimming pools. That share is projected to rise to 40%, or by 400 billion gallons, to a total of 600 billion gallons of water by 2030, giving it a global electricity demand in excess of the entire country of Nigeria and using enough water to supply 500 million people in Sub-Saharan Africa.

However, with 200 billion gallons of water (and counting) dedicated to AI workloads, how does that compare to other industries?

That's still a footnote compared to the or 26.4 trillion gallons used by U.S. agriculture in 2024 (as per USDA), but it is closing in on international oil refining numbers. OPEC produced roughly 86 million barrels of oil a day in 2024, and with a rough conversion of 0.4 barrels of water per barrel of crude, that's in the region of 550 billion gallons a year.

There are still industries using much more water than AI, and much more even than all the data centers combined. However, water use is growing dramatically, and it's not really coming from the increased cooling demands. It's coming from power demands and hardware manufacturing.

As Americans' feelings towards data centers sour and, in turn, increase their opposition to their development, addressing the growing water needs of these new deployments may be key for developers who want to see their projects reach completion. For residents facing water shortages, droughts, and water contamination, the danger is more existential.

Cooling innovation

For data center developers, the main way they've looked to address growing water demand from their facilities is to improve cooling. Moving away from evaporative to closed-loop, direct-to-chip cooling can have a huge effect on the water used in the cooling process.

That's a good thing. Indeed, Microsoft's Satya Nadella claimed that the company's newest AI data centers have cooling systems so efficient that they "can operate effectively with zero water consumption." He also compared these mega data centers to single restaurants in terms of annual water consumption.

For home PC enthusiasts, Nadella is talking about using the data center equivalent of an AIO watercooler, rather than just letting the hot water evaporate to cool it down. It's easily more efficient in terms of water usage, which is great from that direct-use perspective.

Closed-loop cooling is absolutely an important innovation in data center development, and combined with more exotic ideas like fanless liquid coolers and immersion cooling (perhaps even undersea and in-orbit deployments) could see data center cooling use very little water in the future.

But it's not the cooling that's the problem: it's the power being generated to run them. And the one downside to closed-loop cooling systems is it uses more power than evaporative cooling systems. As those power demands rise, so does the indirect water usage of these facilities.

Power is the issue

The vast majority of indirect water use by data centers by 2050 will be down to power generation, the Xylem study suggests, and if recent generations of GPU development are anything to go by, those power demands are going to be enormous.

Nvidia's Ampere generation A100 enterprise GPU had a TDP of 300-400W. An H200 of the Hopper generation has a TDP up to 700W. A Blackwell GB200 GPU can pull as much as 1,200W. The next generation Vera Rubin? That's now up to 2,300W per chip.

Once you start scaling these GPUs up to their full racks, the power consumption is extreme. Where traditional data center server racks consumed between 10 and 15 KW, the latest GB300 NVL72 designs could consume upwards of 150KW a piece. Vera Rubin might be more energy efficient, but its racks could consume upwards of 230KW each.

Data centers just weren't traditionally designed with this kind of density of energy demands in mind. Powering them alone will be an enormous challenge and require enormous quantities of water to do it.

However, other industries also consume far more energy than all data centers, and thus, consume more indirect water usage from power generation. For instance, steel and iron manufacturing, chemicals and petrochemicals, cement and glass manufacturing, and many other industries each use multiple times more power than all data centers combined.

Renewables, water recovery, and nuclear

For hyperscalers, the near-term solution to data center power problems has been to use (occasionally law-breaking) mobile methane jet turbines. These aren't too heavy on water consumption, but have their own environmentally damaging effects with heavy carbon emissions.

A longer-term solution to this issue, and hopefully the extreme indirect water demands of these facilities, will be a combination of renewables, nuclear power, and water recovery.

The Switch Tahoe Reno exascale data center shows how it can be done. It's a 650MW facility built in 2017 that uses 100% renewable solar energy. In Portugal, the SINES DC Start Campus is a 1.2 Gigawatt facility that's partially online and uses 100% renewables, as well as using seawater cooling to offset its water usage. Although many of the newer data center projects are far larger, as the price of solar deployment continues to plummet, it's certainly possible that data centers powered by renewables can be effective and profitable, without consuming such vast quantities of water.

Another option is nuclear energy. New, smaller reactor designs are making it possible to get these facilities online faster and with a more modular design. There's even the possibility of repurposing old aircraft carriers and submarines with onboard nuclear reactors to power data center facilities.

Data center developers know this is at least one path for the future. That's why they're rushing to secure access to key materials like Uranium.

The future of data center power, especially AI data centers, and the water that they require, is almost certainly some mix of renewables and near-site nuclear power.

As the mobile methane turbines popping up at data centers have shown, the developers will often just use what they can get their hands on. Perhaps alongside moratoriums and pauses in construction, data center protestors could make sure that if data centers are built in their local area, the developers should also be required to invest in water infrastructure to offset their ever-growing demands, alongside more renewable energy solutions.

Google has placed an order for Intel to build more than 3 million of its TPUs in 2028 after months of testing Intel's advanced packaging, according to The Information, citing four people familiar with the matter. They claim that Nvidia is evaluating Intel to build a future processor that fuses four GPU dies into one unit, tied to its Feynman architecture due in 2028, and that SK hynix is testing whether its high-bandwidth memory works reliably with Intel's packaging.

Specifically, SK hynix needs to know whether Intel can run packaging to the standard that AI accelerators demand. TSMC’s CoWoS is the industry-standard process for it and has been oversubscribed for more than two years. Intel’s embedded multi-die interconnect bridge, or EMIB, is the only alternative AI chip makers can realistically qualify at volume before the end of the decade.

This isn’t a first for Intel: Google and Amazon were reported to be in active discussions for their custom AI processors back in April, but the remarks from these sources move those “discussions” to a solid unit figure and production timeline, adding in SK hynix qualification that would ultimately determine whether any of it reaches Nvidia accelerators.

CoWoS bottlenecked

TSMC's leading-edge wafer lines and its CoWoS packaging are both at capacity. At the company's annual shareholders' meeting in Hsinchu on June 4th, CEO C.C. Wei said, "It will be a long time before we can meet customer demand," telling shareholders that the company simply can’t satisfy American customer demand for years, even as it builds out U.S. capacity. He had already told the Semiconductor Industry Association last November that TSMC's advanced-node capacity falls "about three times short" of demand.

The queue for CoWoS is concentrated across a handful of buyers. Nvidia is naturally expected to account for the majority of global CoWoS demand — about 60% this year — with Broadcom and AMD absorbing another 26% between them, leaving custom-ASIC designers and smaller AI-chip makers waiting behind the largest GPU order book in the industry. But the industry can’t wait, and both these smaller players and hyperscalers alike with multimillion-unit roadmaps need to qualify a second packaging solution rather than wait for capacity that TSMC says will be short for years.

As for EMIB vs. CoWoS, they solve the same problem in opposite ways. CoWoS mounts every die on a large silicon interposer that all signals and power must cross, and the interposer scales with package size, so reticle-class designs waste silicon at the edges. EMIB, meanwhile, embeds small silicon bridges in the organic substrate only where two dies need to connect, with no interposer at all. Intel cites package utilization near 90% EMIB against roughly 60% for interposer-class packaging, because small bridges tile efficiently while large interposers don’t.

Bernstein analysts estimate EMIB packaging costs a few hundred dollars per chip against $900 to $1,000 for CoWoS on a Rubin-class processor, though the firm flags the fact that there’s a “lack of an external production track record” in that estimate. As always, there’s a trade-off: standard EMIB routes power around the bridge through the substrate in long, resistive paths. That might have been acceptable for Sapphire Rapids and Ponte Vecchio, but not for HBM4-class accelerators that draw more current.

EMIB-T closes that gap by adding through-silicon vias to the bridge die for vertical power delivery, and it’s set to enter production fab rollout this year. Intel has said EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 stacks and scales to a 120mm x 180mm package carrying more than 38 bridges and over 12 reticle-sized dies. Jaguar Shores, the successor to the canceled Falcon Shores accelerator, is the likely first product to use it.

Gated by SK?

Working with SK hynix could be a huge boon for Intel, with the qualification of its packaging by the South Korean memory giant potentially deciding whether it reaches flagship AI silicon or not. SK held a 57% share of HBM revenue in Q4 2025 per Counterpoint Research, and UBS expects it to take roughly 70% of the HBM4 supplied for Nvidia's Rubin platform this year.

HBM stacks are themselves a packaging problem: multiple memory dies bonded vertically through TSVs, then mounted next to a host processor with tight tolerances on power and thermal behavior. Validating those stacks on EMIB rather than a CoWoS interposer is the test of whether Intel can package memory to the standard Nvidia and Google require.

An official thumbs-up from SK, or an HBM-4-on-EMIB-T production result, would convert Intel’s packaging from “tested” to “trusted.” But, until (or if) that happens, the split between accelerator types will remain: ASIC designers running lower memory bandwidth, including Google and Meta, can adopt EMIB sooner, while bandwidth-bound GPUs stay on CoWoS longer.

Intel still needs to prove EMIB

No named external AI customer is in EMIB or Foveros volume production today. Intel runs EMIB in its own server CPUs, including the 18A Clearwater Forest part whose 17-tile package uses 12 bridges, but every specifically named outside engagement so far, including Google’s order, points at 2027 or 2028 products or remains an evaluation.

Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and in Q1 2026, the division posted $5.4 billion in revenue against a $2.4 billion operating loss, with external customers accounting for just $174 million of the total. CFO David Zinsner told the Morgan Stanley TMT conference in March that the foundry is close to closing deals worth "billions per year in terms of revenue" on advanced packaging alone, against a pipeline he had earlier measured in the hundreds of millions.

Another unknown is process yields: Intel uses 18A, its first node with gate-all-around transistors and backside power, for Panther Lake and Clearwater Forest, an internal proving ground before courting outside logic customers. However, Intel's most recent guidance is that yields are improving 7 to 8 percent each month, accelerated by enhanced cooperation with external partners.

The company that just a few weeks ago told us that its Mythos model was too powerful to be released publicly is now saying that we might need to hit the pause button on AI altogether, while also teaching its AI to build itself. On June 4, Anthropic published a report, when AI builds itself, showing that Claude now writes more than 80% of the code merged into its own production codebase, up from the low single digits before Claude Code reached research preview in February last year, and arguing that the loop has begun to accelerate AI development in a way that could eventually leave humans unable to control the systems being built.

The Anthropic Institute, the firm's research arm, casts the trend as early movement toward recursive self-improvement, the point at which a model designs and builds its own successor without meaningful human input, and warns that the rare misalignment in today's models could keep "growing more frequent but less understood until we lose control of them."

Reading further into the post, and taking the entire frontier AI model development ecosystem reveals some other uncomfortable truths that the developers of cutting-edge AI models also have to reckon with: compute.

Loss of control

Anthropic gave us three predictions of ways the next few years could play out, reserving a particularly dire warning for the case in which models become capable of fully improving themselves. Progress, Amodei’s lab argues, would then be paced almost entirely by available compute, human engineers would be pushed into oversight and verification, and a self-improving model could come to dominate as its abilities outstrip those of the people who built it.

The firm called this — the task of keeping a system's behavior tied to human intent — the part of this future it’s least sure about. A capable, well-aligned model might discover new ways to keep its successors safe, it said, or the reverse could hold, and misalignment could compound generation over generation, with the unusual concession that a sufficiently wise model might instead choose to halt its own development.

The idea of an ultraintelligent machine designing still better machines (“singularity”) has been around for decades. British mathematician I. J. Good argued back in the 1960s through his “intelligence explosion” thesis that such a machine would be the “last invention that man ever need make,” so long as it remained “docile enough” to tell us how to control it. Meanwhile, the “Godfather of AI,” Geoffrey Hinton, has put the odds of AI causing human extinction within three decades at 10% to 20%.

The International AI Safety Report, chaired by Yoshua Bengio and published in January 2025 with input from more than 100 experts across 30 countries, defines loss of control as a scenario in which AI systems operate outside anyone's control with no clear path to regaining it.

Every figure behind the warning coming out of Anthropic is based on data from within, and none of it has been independently audited. Among this data is its claim that in Q2 2026, the typical Anthropic engineer is merging eight times as much code per day as in 2024. On the hardest, least-specified coding tasks, Claude succeeded 76% of the time in May 2026, a rise of 50 percentage points in six months. On an internal test that asks each new model to make training code run faster, results climbed from roughly triple the original speed with Claude Opus 4 in May 2025 to about 52 times with the unreleased Mythos Preview model by April 2026, against the four to eight hours a skilled researcher needs for a fourfold gain.

In fairness, Anthropic does then call lines of code a poor proxy for output and admits that the eight times figure almost certainly overstates the real gain. Its research-judgment study, in which models beat the human's next step 64% of the time, drew on 129 moments the company deliberately picked because the human's choice had room for improvement, so it’s not a like-for-like contest.

The report publishes no breakdown isolating how much recent capability gain comes from the self-improvement loop rather than from raw compute, more data, and human-led research. Cognitive scientist Gary Marcus called the piece a "bait and switch" on his Substack, arguing the company had shown faster coding under human direction rather than a system improving itself. Bentley University mathematician Noah Giansiracusa told Scientific American, "I don't think it's a genuine call to slow down."

AI is writing everyone’s code

Anthropic isn’t alone here. Google CEO Sundar Pichai said in an April blog post that 75% of new code at Google is now AI-generated and approved by engineers, up from 50% the previous autumn. OpenAI's Jakub Pachocki has described the company's Codex agent as “a very early version of an AI researcher,” and OpenAI has said it’s building toward a fully automated one. Chinese developer MiniMax marketed its M2.7 model in March as "self-evolving," claiming it ran its own scaffold-optimization rounds and handled a large share of its reinforcement-learning research, though the benchmarks were internal and unreplicated.

Independent measurements do somewhat support a trend of fast improvement without confirming a runaway one that the AI labs are talking about. METR, for example, found last year that the length of task an AI can finish with 50% reliability has been doubling roughly every seven months. On its RE-Bench research benchmark, the best agents beat human experts given two hours, but the humans pulled ahead at eight hours and roughly doubled the top agent's score at 32 hours. AI's advantage so far sits in short, well-defined bursts, not the sustained, open-ended work that research depends on, which is the human edge Anthropic has said is still holding strong.

No compute means no runaway AI

Anthropic half-buries the fact that it’s compute capacity that’s ultimately the binding constraint in all of this. It names chip fabrication, grid expansion, and interconnect bandwidth as the factors that could cap progress ahead of intelligence itself. We’re all aware that those limits are solid as things currently stand: SK hynix and Micron have sold out HBM output for the year, high-power transformers carry three-to-five-year lead times, switchgear is booked into 2028, and grid-interconnection queues run three to seven years.

A Sightline Climate analysis estimated that 30% to 50% of large data centers due to open in 2026 will slip or cancel. U.S. data centers drew about 4.4% of national electricity in 2023, a share the Department of Energy's Lawrence Berkeley National Laboratory expects to reach 6.7% to 12% by 2028. Meanwhile, the four largest hyperscalers are on course to spend more than $650 billion on AI infrastructure this year.

Whether compute ultimately puts a lid on any out-of-control, self-improving loop is an unsettled debate. Forethought researcher Tom Davidson argues that there’s a chance that compute bottlenecks won’t “slow down a software intelligence explosion until its late stages,” while Epoch AI counters that if compute and cognitive labor are complements rather than substitutes, software-only acceleration stalls once it hits a compute wall.

‘No, you hang up first’

As for pausing AI development, Anthropic says it’ll only do this if rival labs at or near the frontier do the same in a verifiable way, and that a halt by one company wouldn’t change who’s leading the way.

This is a facetious suggestion at best that insults the intelligence of anyone who has been paying attention to the AI arms race. It’s beyond obvious that no lab this far down the road — let alone Anthropic — is ever going to ease off, especially when Anthropic’s own report essentially doubles as a piece of marketing for how fast it can make Claude build Claude. To suggest in one breath that AI might need to be paused or slowed down in one breath and then saying “but everyone else needs to go first” in another is quite the remark.

Anthropic’s report also came just days after the company confidentially filed for an IPO at a reported valuation near $965 billion, a glaring juxtaposition that read as a front-runner lobbying for limits it stands to help set. Anthropic made a self-assessment in April, when it said its Mythos Preview model had found thousands of severe vulnerabilities, a claim that later drew scrutiny over how much of it rested on a small manual sample.

A recent Mercer survey of nearly 12,000 C-suite executives, HR leaders, investors, and employees found that 99% of CEOs expect AI and automation to drive at least some headcount reduction in the next two years. At the same time, the report found that only 32% of executives believe their organizations are effective at combining human labor with AI systems.

These somewhat contradictory stats form the basis of an ongoing debate over AI and jobs. The data from Mercer shows that companies are indeed cutting or expect to cut significant portions of their workforce. In fact, we recently reported that 40,000 tech industry employees lost their jobs in Q1, 2026.

Now, companies are under pressure to show that these job cuts and billions of dollars in AI spending can translate into measurable returns. Workers, meanwhile, are already being affected as employers redesign teams, slow junior hiring, and tie AI to cost-cutting decisions before broader economic data shows a clear wave of AI-driven job replacement.

The evidence so far does not show an outright, simple story in which AI is massively replacing workers across the economy. Nor has it been proven that the actual AI replacements have proven useful. In another twist, it's possible that what OpenAI CEO Sam Altman calls “AI washing” — blaming AI for layoffs that may have happened anyway — is tainting the data.

Maximum pressure at the bottom of the ladder

While the layoffs create a valid, growing concern about unemployment, the most immediate impact appears to be on who companies are willing or unwilling to hire, and for what roles. Mercer’s report suggests that younger workers are especially exposed, with entry professionals aged 22 to 27 facing the highest perceived risk of disruption. This is because generative AI is strongest at the codifiable, repeatable tasks that often make up entry-level roles through which new workers are traditionally trained and integrated into the system.

A similar 2026 CEO survey by consulting firm Oliver Wyman points in the same direction. The firm found that the share of companies planning to reduce junior roles has jumped from 17% to 43% in a single year, while 33% are shifting their workforce mix toward midlevel roles. This stat presents another concern. Companies removing junior roles may reduce costs in the short term. However, the move may also weaken their own future talent pipeline. A labor market that demands experience while eliminating the jobs that create experience risks imploding.

For now, the full picture remains quite murky, with contradictions in the available data. Oliver Wyman notes that some of the most advanced AI adopters are not abandoning junior hiring entirely. In fact, companies reporting stronger AI returns are somewhat more likely than weaker performers to shift toward junior workers, suggesting that at least some businesses see AI-literate early-career staff as an asset rather than a cost.

This makes the entry-level story more complicated. AI may reduce demand for some traditional junior tasks, but it could also increase demand for workers who can use AI tools effectively inside redesigned workflows. The real risk is that companies treat the technology as a simple substitute for early-career workers before they understand which roles should be automated, augmented, or rebuilt.

The productivity evidence is still unclear

The case for AI-driven layoffs depends heavily on one assumption: that AI is making workers and teams productive enough to justify smaller headcounts, while also cutting costs. So far, the evidence is mixed. Mercer’s findings show that executives see AI as central to future performance, but also that many organizations are struggling to redesign work around it. Oliver Wyman found that 53% of CEOs still say it is too early to assess the return on investment from AI, up from 41% last year. It also found that 67% of companies are still primarily planning or piloting AI rather than scaling it across the business.

This gap between ambition and proof reveals that AI can be impressive at the task level without immediately transforming company-level productivity. A chatbot that drafts an email faster or helps a programmer debug code may save time for an individual worker. However, turning that into measurable revenue growth, lower operating costs, or a sustainably smaller workforce is a different challenge.

There are workflow redesigns, data cleaning and integration, and compliance risk management, among several other accompanying tasks. Employees need training on how and when to apply AI. They also need cybersecurity training as hackers are increasingly finding ways to exploit systems through AI chatbots. Managers need to know which outputs can be trusted and which require human review. There’s also the question of how much responsibility AI can safely handle. We recently covered a case where a Claude-powered AI coding agent deleted a company's entire database. In many companies, these changes are slower and more difficult than the early AI hype suggested.

European data further complicates the replacement narrative. A European Central Bank analysis of firms that use and invest in AI found no significant overall difference in job creation or destruction between businesses that use AI and those that do not. In some cases, companies with more intensive AI use or investment were slightly more likely to be hiring, especially where AI supported research, development, and innovation.

While none of this proves that AI will not still reduce employment later, it does suggest that the current relationship between AI and jobs is not as straightforward as many layoff announcements imply. In the near term, AI may be helping some companies grow, while leaving many still searching for measurable returns.

“AI washing” is tainting the data

As if the data isn’t painting an unclear enough picture, there’s a real possibility that companies are falsely using AI as an excuse to fire workers. Layoff announcements rarely provide enough detail to distinguish genuine AI displacement from broader corporate restructuring or even serious internal issues. Sam Altman, whose company helped trigger the generative AI boom, has warned that some firms are engaging in “AI washing” by blaming AI for job cuts they would have made anyway. He also acknowledged that real displacement is happening and is likely to become more visible over time. Both points can be true.

This is why the current wave of AI-linked layoffs should be read carefully. A company may cite automation while also dealing with overhiring from the pandemic period, weaker demand, outsourcing, margin pressure, a falling share price, activist investors, or a broader strategic reset. AI can be the cause, the tool, the justification, or merely the language used to present a decision to investors.

Now, this does not mean AI is irrelevant to job cuts. Major companies across banking, retail, technology, and professional services are already reorganizing work around automation. Standard Chartered has discussed thousands of job cuts tied to automation and lower-value roles. Other firms, such as Amazon and Meta, have cited AI as part of broader efficiency drives.

As an increasing number of companies now believe AI will allow smaller teams to do more, even uncertain productivity gains are influencing hiring plans. The powerful technology is arriving in companies already under pressure to cut costs, demonstrate growth, and satisfy investors. As a result, managers may delay backfilling roles, and graduate hiring may slow, with entry-level work being bundled into contractor roles or existing mid-level positions.

The danger for companies is that cutting too deeply into junior roles could create a skills shortage later. The danger for workers is more immediate, as the traditional route into white-collar careers may narrow before a clear replacement path emerges. For now, the most defensible reading is also the least dramatic, and may be somewhat on the fence: AI is neither harmless, an automatic jobs apocalypse, nor a magic potion for instant growth and productivity.

When not being spotted at night markets or meeting crowds of adoring fans, the hardware industry’s biggest celebrity, Nvidia CEO Jensen Huang, spent most of his time at Computex this week making the case that computing as we know it is collapsing into one repeatable pattern built for AI agents; a blueprint that now runs across the cloud, the PC, the car, and the robot.

"There's a new computing pattern," the Nvidia CEO told reporters at a press gaggle the day after his GTC Taipei keynote, describing an agent architecture he calls a harness that orchestrates reasoning, memory, and tool use the same way whether it sits in a data center or a laptop.

He tied that claim to every product Nvidia detailed at the show, from the Vera data-center CPU now in full production to RTX Spark, its first Windows PC platform, shipping in laptops this fall.

One pattern, every machine

Huang told the room that he repeats the same keynote structure on purpose. "Every time I give you a keynote, it's like Top Gun 17, and it's exactly the same architecture," he said, "because I want you to know that the future of computing is this." The pattern begins with training and inference in the cloud and pushes outward to everything else: "Every edge device will become autonomous. Every edge device will have agentic systems."

He ran that blueprint through self-driving cars, humanoid robots, Nokia base stations, and imaging satellites, casting each as the same agent profile on different hardware. Curiously, the self-driving car got quite a bit of airtime, with Huang describing Nvidia's Alpamayo driving stack as a system that reasons in language rather than reacting to images, one that could read a "skill file" and watch a tutorial video to operate unfamiliar machinery the way a person would. "That's how autonomous vehicles are going to work in the future," he said. "It's essentially that agentic computing pattern with a physical AI model."

A CPU that generates tokens, not cores

Vera, on the data center side, is an 88-core Arm processor that Nvidia is now in full production with, pitching it as a chip built for agents rather than human users. "We built Vera for agents to use," Huang said. "Until six months ago, there were no agents, so that's the definition of a $0 billion market."

A hyperscale CPU piles on cores because humans lease them by the hundred, where an agent, Huang argued, "doesn't want to rent the CPU core, the agent wants to generate tokens." That pushed Nvidia toward single-thread speed and memory bandwidth over core count, and Huang claimed Vera offers the largest step up in single-threaded performance he has seen "in 25 years." His reasoning ties back to latency: "Humans are more patient than agents. Agents, they're working at nanosecond scale, not second scale."

Nvidia claims 1.8 times faster task completion than x86 and a 1.5 times instructions-per-clock gain over its Grace predecessor, with a 256-chip liquid-cooled Vera rack it says reaches six times the throughput of a conventional CPU rack. The chip ships on the back of nearly 2.5 million Grace units sold, and Anthropic, OpenAI, xAI, ByteDance, CoreWeave, and Oracle are named as early customers. CFO Colette Kress told investors on Nvidia's latest earnings call that the company sees "nearly $20 billion in total CPU revenue this year".

Phoronix's first public Vera benchmarks in May measured it roughly 10% ahead of AMD's 64-core EPYC 9575F and about 55% ahead of Intel's 128-core Xeon 6980P across selected Linux workloads. Nvidia ran those tests on pre-production silicon at its own headquarters, limited them to workloads it considers relevant, and, by Phoronix's account, switched off CPU power and frequency monitoring for the session.

Reinventing the PC after 40 years

As for RTX Spark, Huang says that it’s the first real rethink of the PC in four decades. "We have an opportunity after 40 years to go reinvent it for the age of AI," he said, predicting the machine shifts "from your PC being a tool to now really your PC being your system." He pushed even further: "Your laptop is going to be your R2-D2."

The top RTX Spark part, internally N1X, pairs a 20-core Arm CPU built by MediaTek (10 Cortex-X925 performance cores and 10 Cortex-A725 efficiency cores) with a Blackwell GPU carrying 6,144 CUDA cores, up to 128GB of LPDDR5X unified memory, and a 600 GB/s NVLink-C2C link, all on TSMC's 3nm node. Huang justified these specs with the same impatience he applied to Vera, arguing that an agent driving the machine won’t wait, so the software it touches, from Adobe to Blender, "cannot be slow."

The platform is launching in a market that Qualcomm had effectively dominated until its Windows on Arm exclusivity with Microsoft lapsed. Fall 2026 laptops are confirmed from Microsoft, Dell, HP, ASUS, Lenovo, and MSI, with Acer and Gigabyte to follow, and Nvidia says anti-cheat engines, including Easy Anti-Cheat and Denuvo, run natively on the chip. Asked why Nvidia would enter a low-margin business it has steered clear of for years, Huang said, "We don't really have to choose. The real question is, can we make a contribution?"

Vera's 88 cores are Nvidia's own custom Olympus design, its first ground-up server core since the Denver and Carmel projects, while RTX Spark's 20 cores are Arm's off-the-shelf Cortex reference designs licensed through MediaTek, one of them already a generation old. Huang's "same pattern everywhere" runs, at the silicon level, on two different CPUs.

When asked whether the Olympus cores would come to Windows PCs, Huang declined to commit. "Our preference is to use off-the-shelf cores whenever we can, because Arm also builds good cores," he said, adding that Olympus was pushed toward single-thread speed in a way standard many-core Arm parts weren’t: "We wanted to push single-threaded performance as far as we could push it." The first PC chip using Nvidia's own cores isn’t expected until 2028. Meanwhile, Morgan Stanley estimates Vera at around $5,000 per socket inside a vertically integrated rack.

What about memory?

DRAM contract prices have climbed sharply through 2026 as makers divert wafers to high-bandwidth memory, and Nvidia remains short of supply even as it locks in capacity, by Huang's own account: "We have enough supply for very robust growth. However, we are supply constrained."

"One of the best ways to improve memory use is to use extremely, extremely low precision," Huang said, pointing to NVFP4, Nvidia's 4-bit floating-point format that scales between four, eight, 16, and 32 bits and roughly doubles the parameters that fit in a given memory pool, the trick that lets RTX Spark hold larger models in its 128GB. He paired it with neural texture compression that cuts game texture memory by up to eight times in Nvidia's demos. At SK hynix's booth during the show, Huang signed an HBM4E wafer with the words "Please Make More."

Several AMD partners are showing off the company’s next-generation Helios rack-scale solution running AMD’s EPYC ‘Venice’ processors and Instinct MI455X AI accelerators at Computex 2026 in Taipei, Taiwan. The units are set to become available later this year. There is one major catch, though: they all use UALink-over-Ethernet scale-up connectivity, which may limit their performance in certain workloads that depend on the connection performance. That said, Helios systems with ‘true’ UALink interconnects will also be available.

AMD’s Helios is the company's first rack-scale AI system, and is set to rival Nvidia’s NVL72 VR200 machines based on the next-generation Vera Rubin platform. Helios will rely on AMD’s 6th Generation EPYC Venice CPUs with up to 256 cores, pack 72 Instinct MI455X accelerators with a total of 31 TB of HBM4 memory, and 1400 TB/s of bandwidth. AMD estimates that its performance will be around 2900 FP4 dense PFLOPS, which puts the unit behind Nvidia's VR200 NVL72 system in terms of compute performance, but ahead of it with HBM4 memory capacity. This promises to provide Helios-based systems an advantage in memory-intensive workloads, such as when running large LLMs.

The AI accelerators are interconnected and make use of a UALink-over-Ethernet connection, which provides up to 260 TB/s aggregated scale-up bandwidth (in line with Nvidia’s NVL72 VR200). Helios will also feature Pensando Vulcano network interface cards (NICs), which are among the industry's first 800 GbE network cards that comply with the Ultra Ethernet specification and provide up to 43 TB/s of scale-out bandwidth.

However, the interconnection used on these Helios systems will vary. The machine supports both UALink and UALink-over-Ethernet, but the initial versions will use the latter, rather than the former. This is likely because UALink switches aren't finalized and are pending validation and qualification by AMD’s AI customers.

The biggest advantage of using UALink over Ethernet is that AMD can build Helios using an existing, widely supported ecosystem of validated and qualified components. Ethernet switching ASICs, cables, and other ingredients are already used by hyperscalers and cloud providers worldwide, which accelerates deployment.

But there is a major downside with using Ethernet, even with the UALink protocol on top: Ethernet was originally designed as a general-purpose networking technology; it was never designed to scale up AI accelerators.

As a result, communications may involve higher latency, more protocol overhead, and less deterministic performance than a dedicated scale-up fabric. For large AI training jobs that need all 72 Instinct MI455X accelerators to work in concert, communication efficiency is as important as compute performance. If the UALink-over-Ethernet interconnect cannot keep GPUs fed with data efficiently, some of the theoretical performance of the hardware may be lost in real-world deployments, even though on paper, Helios with UALink-over-Ethernet is as good as Nvidia’s NVL72 VR200 in scale-up bandwidth.

This begs the question of whether UALink will ever be widely used with Helios and whether UALink will ever be widely deployed using copper. Hyperscalers and other companies deploying high-end AI hardware at scale rarely upgrade their hardware.

While the Instinct MI455X certainly promises to be among the best hardware accelerators this year, Helios will likely only be rivalled by Nvidia’s NVL72 VR200. It will be outdated next year when AMD launches its Instinct MI500-series products. These units will be used in the company’s next-generation rack-scale offering, which promises to pack more AI GPUs, potentially requiring optical interconnects with UALink on top. As a result, Helios systems with true UALink interconnections over copper will be on the market for less than a year before those next-generation rack-scale solutions will hit the market.

Of course, nothing is stopping AMD from offering Helios with Instinct MI500-series accelerators and UALink interconnects over copper; however, the company hasn't confirmed the existence of such systems.

Frore Systems is showing off its LiquidJet Nexus at Computex 2026 in Taipei, Taiwan. The LiquidJet Nexus is a monolithic water block with innovative coldplates, designed to cool two Blackwell GPUs and a Grace CPU, that can replace the complex water block used today. Based on tests conducted by an ODM, the LiquidJet Nexus outperforms the default cooling solution used today and reduces GPU temperatures by around 6ºC, which increases token generation by 10%. Frore intends to build LiquidJet Nexus for Nvidia’s Rubin platforms and is ready to produce them for other accelerators, too.

Earlier this year, Frore introduced its LiquidJet, a coldplate for AI accelerators, tailor-made for exact models of processors using tools originally meant to make semiconductors, in a bid to maximize cooling performance. The LiquidJet Nexus water block builds upon these principles, integrating them into a monolithic unit designed to cool down both GPUs and a CPU inside a server tray. For now, Frore is demonstrating LiquidJet Nexus for Nvidia’s Grace Blackwell superchip, though a version compatible with Vera Rubin is also incoming, we're told.

Frore’s LiquidJet coldplates are made using tools designed to produce semiconductors — using etching and bonding steps — and are architected in accordance with actual thermal maps of CPUs and GPUs they are meant to cool. As a result, they remove heat precisely from hotspots of these processors, and therefore enable better cooling performance than coldplates made using traditional milling methods. Based on tests conducted by a major ODM, Frore’s LiquidJet Nexus reduces the temperature of Blackwell GPUs by 6ºC compared to default cooling solutions, which in turn increases their token generation by 10%.

While a 6ºC temperature drop and a 10% performance improvement may sound humble, these performance improvements impact billion-dollar deployments, where such improvements could mean hundreds of millions in savings. Also, since Frore’s Liquid Jet Nexus is monolithic, it is less prone to leakage. This means less downtime and fewer damaged servers, which means more profits and fewer losses for their owners. Again, since we are talking about billion-dollar deployments, there are significant amounts of money at stake when it comes to cooling and efficiency.

Frore says it is working with the majority of hyperscalers to build LiquidJet-based cooling solutions for their custom hardware. Since LiquidJet is designed to remove 400W – 600W of thermal energy per square centimeter, it can cool down very hot components. Furthermore, since these components tend to scale horizontally, it is not a problem to scale LiquidJet’s performance by increasing its dimensions.

In addition to being more performant and potentially significantly more reliable than existing liquid-cooling solutions for Nvidia Blackwell, Frore’s LiquidJet Nexus also weighs 65% less than rivals and is twice as thin (17 mm vs 34 mm), according to Frore.

While this may not be a significant advantage today (unless you ship your servers by plane), this will be a dramatic advantage for Nvidia’s next-generation Kyber chassis that places servers on their edge rather than horizontally, which will make the importance of LiquidJet Nexus’s weight a bigger factor, as the cooler must adhere to the cooling surface of the integrated heat spreader thoroughly. Meanwhile, it is hard to adhere a massive cooler to a vertically standing motherboard, so one with a lower weight should be easier to attach to the motherboard and chassis without worrying about longer-term deformations.

Speaking of Nvidia’s Kyber chassis, it is worth noting that they are designed for the Vera Rubin Ultra platform, which ups the TDP of GPUs all the way to around 3kW per unit, making its cooling a challenge. Meanwhile, Rubin Ultra GPU scales horizontally by employing a quad-chiplet design, so Frore can address its TDP by reinventing its coldplate, which is easy assuming the company is provided a thermal map of the unit. The same method can be applied to other processors, which is why Frore is indeed working with hyperscalers with custom silicon, in addition to other merchant silicon providers, aside from Nvidia.

This week at Computex 2026, we saw Nvidia reveal its RTX Spark, and last month, AMD detailed its Ryzen AI Max 400 "Gorgon Halo" lineup, a refresh of the Strix Halo APUs that lifts supported unified memory to 192GB and allows up to 160GB of that pool to be addressed as VRAM. AMD describes the flagship Ryzen AI Max+ PRO 495 as the first x86 client processor able to run a 300-billion-parameter language model locally, pitching the platform for use cases that need to keep multiple AI agents resident in memory at once.

The market for Gorgon Halo will likely be directly shared with other chips, such as Nvidia's RTX Spark, which debuted at Computex 2026. RTX Spark is also positioned as an on-device agentic computing device. With local AI computing demanding lots of on-device RAM, it poses a difficult issue for device vendors.

DRAM contract prices are forecast to climb another 58% to 63% this quarter, on top of the record 90% to 95% jump TrendForce recorded in Q1, which also saw Nvidia raise the price of its DGX Spark desktop from $3,999 to $4,699, citing memory supply. So, what happens to the dream of accessible local AI compute?

DRAM supply squeeze

The local AI PC has become a category defined by how much memory it carries, and it’s scaling that memory up at a time when memory has never cost more. AMD's three Gorgon Halo SKUs reuse the same Zen 5 cores, RDNA 3.5 graphics, and XDNA 2 NPU as the existing Ryzen AI Max 300 parts, with the Max+ PRO 495 gaining a 100 MHz boost-clock bump to 5.2 GHz, a 40-compute-unit Radeon 8065S, and a 55 TOPS NPU.

Memory capacity has been increased 50% from the 128GB ceiling on Strix Halo, with a leaked PassMark entry putting the 192GB figure as eight 24GB SK hynix LPDDR5X packages on an HP test board, though AMD hasn’t yet confirmed this. Partner systems from Asus, HP, and Lenovo are due in the third quarter of 2026.

It’s all well and good that Nvidia and AMD are releasing machines like the RTX Spark and the Gorgon Halo line-up. However, Samsung, SK hynix, and Micron have all shifted the bulk of their wafer capacity toward high-bandwidth memory for AI accelerators because HBM carries far higher margins than commodity DRAM, and the conventional memory supply has tightened as a direct result of this. HP told investors in February that memory now accounts for roughly 35% of the cost of building a PC, up from 15% to 18% a quarter earlier.

SK Group chairman Chey Tae-won, speaking at Computex 2026 on the show’s official opening day, repeated his position that the shortage will run through 2030, despite the company's intention to double wafer capacity within the next five years. New fabs from all three makers are under construction, but none will reach volume production before late 2027 at the earliest, and most forecasts now predict a structurally higher price floor that persists even after the acute shortage eases.

The 192GB in a Gorgon Halo box, the 128GB in an RTX Spark or DGX Spark, and the LPDDR5X soldered into every AI laptop announced at Computex all come off wafers the memory makers would otherwise sell as HBM. That’s why Nvidia raised the DGX Spark by $700 in February without changing a single spec, and why component makers have begun passing memory costs through directly. One vendor has even taken an extremely on-the-nose approach of adding a flat memory surcharge to every purchase, and in some cases, smaller buyers are now quoted prices that change by the hour.

Bandwidth caps inference speed

A single pool of 192GB would enable an APU to hold a model that would otherwise require a multi-GPU server. While it doesn’t make the model run quickly, dense language model inference reads close to the full set of active weights from memory for every token generated, so generation speed is governed by memory bandwidth divided by the per-token weight footprint, not by idle memory.

Gorgon Halo keeps the same 256-bit LPDDR5X-8000 interface as Strix Halo, which tops out around 256 GB/s in theory and which independent testers have measured closer to 212 GB/s on the GPU. By comparison, the Apple M3 Ultra that AMD and Nvidia are chasing on capacity is rated at 819 GB/s, and an RTX 5090 moves data at 1,792 GB/s.

This gap explains why a dense 70-billion-parameter model fully resident on a Strix Halo iGPU lands in the low single digits of tokens per second, regardless of how much headroom the memory pool has. Our own Corsair AI Workstation 300 review found that Nvidia's slightly higher-bandwidth GB10 pulled ahead of Strix Halo as context length grew, for exactly this reason.

Capacity matters most for mixture-of-experts models, which activate only a fraction of their parameters per token and run far faster than their total size suggests, and for long-context agentic workloads, where it’s KVcache rather than model weights that consume memory. It’s these use cases that AMD’s agentic pitch points at, with leaked details on the next-gen Medusa Halo parts showing a move to LPDDR6 and as much as 80% more bandwidth.

Holding the line on price

Agentic AI is also something of a pricing tool for vendors, beyond describing a workload. A 192GB workstation sold on the promise of running 300-billion-parameter models locally can hold a four-figure price more comfortably than a mini PC sold on cores and clocks, and it justifies loading the most expensive component in the build to its maximum. AMD's Ryzen AI Halo developer box, a 128GB Strix Halo system, opens pre-orders in June at $3,999 through Micro Center, matching the launch price of Acer's GB10-based Veriton GN100 and the original DGX Spark before its increase.

Apple, the one vendor with the scale to hold priority memory allocation, has moved the other way. It pulled the 512GB Mac Studio configuration from sale, raised the price of its 256GB upgrade, and in May removed several more high-memory Mac mini and Mac Studio options as supply tightened.

This shows us beyond doubt that expanding capacity while holding the line on premium pricing is a choice the AMD and Nvidia camps are making, not one that the market is forcing. Whether buyers accept it rests on whether local agentic inference delivers enough value over cloud services to justify the outlay, on machines shipping with memory capacities that outpace the bandwidth that ultimately determines what that memory can do.

Astera Labs demonstrated its recently introduced Scorpio X-Series 320 Lane Smart Fabric Switch, which appears to be the industry’s largest open memory-semantic fabric switch, at Computex 2026 in Taipei. The PCIe 6.0 switch with 320 lanes can be used to build large multi-GPU scale-up clusters, large shared KV-cache memory pools, and disaggregate data center infrastructure using custom topologies.

The switch provides 320 PCIe 6.0 lanes and 20 Tbps of switching bandwidth, up from 144 lanes and 9 Tbps for previous-generation devices. Astera Labs says the increased number of lanes enables larger scale-up domains, enabling the connection of up to 80 accelerators using a single switch. By contrast, older 144-lane switches support up to 32 accelerators per switch. For clusters with more than 64 accelerators, the company says the new device reduces switch hops from as many as three to one and cuts switch count by a factor of four to six while still providing all-to-all connectivity akin to that provided by Nvidia’s NVL72 systems (albeit with lower bandwidth and higher latencies). The switch can support both standard and custom accelerators as long as they use standard PCIe connectivity.

On the trade show floor, Astera Labs is showing off its switching capabilities with Intel’s Arc B70 Pro graphics cards. However, real-world deployments based on the Scorpio X-Series 320-lane PCIe switches will likely use more advanced Intel hardware. In general, the switch can be used to build clusters from all types of accelerators that do not support their own NVLink or UALink-like interconnections, including AMD’s Instinct MI350P and Nvidia’s RTX 6000 Blackwell. Astera has yet to showcase a full working cluster featuring 80 accelerators, as the company only got the Scorpio X-Series 320-lane PCIe switch from the fab eight weeks ago. Also, finding 80 similar accelerators is not easy. Nonetheless, based on the company’s demonstration, the switch appears to be working.

A key feature of the Scorpio X-Series is Hypercast, which is a hardware-based data replication engine intended to accelerate communication-intensive operations common in AI models. According to Astera Labs, MoE networks tend to route tokens across hundreds of experts and create large amounts of multicast traffic between accelerators. In such cases, traditional switching architectures either require repeated data transmissions or slow multicast-group reconfiguration, whereas Hypercast is designed to handle these communication patterns directly in hardware, reduce GPU networking overhead, and improve accelerator efficiency, Astera Labs claims.

The company also added In-Network Compute engines that offload collective operations such as AllReduce, ReduceScatter, AllGather, AllScatter, and all-to-all exchanges. These features can reduce communication latency by more than 50% in certain workloads, according to Astera.

Another important feature of the Scorpio X-Series 320-lane PCIe switch is its memory-semantic connectivity, which enables connected processors to access fabric-attached resources using native load and store operations rather than software-controlled transactions. This greatly simplifies usage of the device and improves real-world performance by reducing overhead and improving fabric efficiency at scale.

Astera says that the production ramp of the Scorpio X-Series 320-lane PCIe switch is set for the second half of 2026. Currently, the company is sampling the switch with leading hyperscalers.

Major tech companies are struggling to justify the skyrocketing prices of heavy AI usage, with even major tech firms like Microsoft and Uber looking at changes to their AI process. Following the recent viral post from Uber CTO Praveen Neppalli Naga that the company had blown through its entire 2026 AI budget in just a few months, Uber's Operations chief, Andrew Macdonald, said that token usage just didn't seem to have a direct correlation with useful consumer features.

Microsoft began revoking its developers' access to the Claude Code programming assistant earlier this month, with plans to move them over to the internal Copilot CLI tool by June 30. Although that has been framed as consolidating its teams onto the tools it's developing, it also comes right at the end of Microsoft's fiscal year, suggesting it may have also been a move to cut costs before the new year.

Worsening matters, Goldman Sachs estimates that Agentic AI could see token use increase by over 24 times in just the next few years. There appears to be a growing disconnect between AI needs, AI wants, and the reality of what AI companies can actually afford as costs mount.

Tokens and trade offers

We've been hearing reports for months about how companies and CEOs are struggling to find the tangible benefit of heavy AI deployment. Uber appears to be the latest AI boosting company to have this come to Jesus moment, following the CTO's explosive claims of annual budgets being wiped out in mere months. In the interview with Business Insider, Andrew Macdonald lamented that there just wasn't a clear correlation between the money Uber was investing in AI use and real consumer feature development.

Having talked to the senior engineers, he said there was no link between higher token usage and a proportional increase in consumer features with real benefits for their customers. Although he admitted more code was being shipped, it "was very hard to draw a line" between that and improvements in the software.

Meanwhile, after opening up its workers to Claude Code subscriptions in December last year, Microsoft is now clawing that back in what's seen by many as a financial move, as much as a consolidation. Microsoft also recently announced the switch of Copilot on GitHub to token-based billing, as the cost of running the tool ballooned earlier this year.

A major reason for this is the explosive growth in agentic AI use. These agents can eat up more than 1,000 times the tokens of a single AI chatbot.

Are more tokens really the answer?

Nvidia CEO Jensen Huang famously said in March this year that if an Nvidia engineer on $500,000 a year wasn't using at least $250,000 of tokens in that same period, he'd be alarmed. This isn't a rare sentiment, though. Many company CEOs are now bragging about the extent of their AI use, as if that alone equates to performance increases.

As Business Insider reports, Airbnb's CEO proudly told investors that 60% of the company's code was now AI-generated. Chime claimed it was shipping 84% AI code earlier this year, and even Google is claiming 50% of its code is AI-generated (though crucially, always checked by a human engineer).

Yet these numbers sound very similar to those of Uber. In the CTO's shocking report of budget runaway, they claimed over 80% of Uber software engineers were using agentic AI, and over 60% of the code was AI-generated. Even then, it's not worth the cost.

And those costs can be extreme if the guardrails are removed. OpenClaw creator and now OpenAI employee, Peter Steinberger, recently announced his team of three people had spent over $1.3 million in tokens in a single month running a suite of agentic AI tools.

This very much reinforces the idea that the cost of AI is rising above that of the workers it's supposed to be replacing. That makes many of the layoffs laid at the feet of AI efficiency and productivity increasingly shaky, unless these companies are simply racing to the bottom.

Or at least racing to new hardware. Goldman Sachs' recent AI agent report suggests that the massive efficiency gains coming from next-generation inferencing chips would make AI use so much cheaper that investment can continue unabated, and profit should follow, with AI agents increasing the revenue at AI companies enormously.

Faster, more efficient hardware will take too long

Nvidia will talk up its Vera Rubin platform at Computex and will officially launch it later this year. It improves AI performance by several times over, uses a new process node, and will reportedly offer as much as 10 times the performance per watt, making it dramatically more efficient than its predecessors.

Such huge gains would give the AI companies that first deploy these cards an enormous advantage over the companies still running Blackwell hardware, and even more so over older Hopper designs. But over 50% of the data center projects announced with Blackwell hardware in mind have been cancelled or delayed, and of those that do complete in the next year, just how keen are the developers going to be to replace those GPUs after they've barely gotten started?

In late 2025, Google, Oracle, and Microsoft all adjusted their plans for hardware in the other direction entirely, suggesting they would make it run for six years before replacing it. That seems impossible to square away with ambitious AI plans and hardware leaps every year.

More tokens on less efficient hardware

The reality is, even as some token costs are falling, the explosion in the number of agentic AI requires cannot be offset by hardware efficiency gains that are many years away from reaching effective deployment, if they ever get to the scale needed to catch up with this ramp-up in AI demand.

That means in the short term, even major companies like Microsoft and Uber are restructuring their use of AI to figure out how to continue using it at scale without nuking their budgets in the process. If those companies can't figure out how to afford it, it's increasingly difficult to imagine how the rest of us will be able to.

And if usage drops because of rising costs, the AI companies are never going to find the short-term profit they need to offset the enormous infrastructure spending they're still trying to justify.

IBM has announced that it will create Anderon, a standalone company and America's first pure-play quantum chip foundry, backed by a proposed $1 billion CHIPS Act R&D award from the U.S. Department of Commerce and a matching $1 billion cash investment from IBM itself.

Headquartered in Albany, New York, Anderon will operate a 300mm quantum wafer fab and offer its manufacturing services to competing quantum hardware vendors. The deal was the centerpiece of a broader $2.013 billion federal quantum portfolio split across nine companies, the largest single quantum R&D commitment in U.S. history.

In launching Anderon, IBM is attempting to build the quantum computing industry's equivalent of TSMC, a neutral third-party manufacturer that’ll fabricate superconducting qubit wafers for other companies as well as IBM's own processors. No such foundry exists anywhere in the world today, with every operational quantum computer having been built by a vertically integrated company that designs, fabricates, and operates its own hardware.

A nine-company package

IBM's $1 billion award accounts for roughly half of the entire DoC quantum package. GlobalFoundries received a separate $375 million allocation to launch a "Quantum Technology Solutions" foundry covering multiple qubit architectures, including superconducting, trapped-ion, photonic, and silicon-spin designs. The remaining seven recipients each received smaller awards: D-Wave, Rigetti, Atom Computing, Infleqtion, PsiQuantum, and Quantinuum were each awarded $100 million, while Australian silicon-spin startup Diraq will receive up to $38 million.

Those seven non-foundry companies are required to give the federal government a minority, non-controlling equity stake in exchange for funding. Rigetti has also disclosed in a memorandum of understanding that the government will receive common stock at a 15% discount, while GlobalFoundries separately disclosed a 1% federal equity stake.

IBM's announcement contains no equivalent equity-stake disclosure for Anderon, a somewhat conspicuous omission given that the Trump administration converted part of Intel’s CHIPS Act manufacturing award into a roughly 10% government equity stake last year.

300mm wafer fabrication

IBM said back in November that all of its current and upcoming quantum processors are built on 300mm silicon wafers at the Albany NanoTech Complex, the largest public-private semiconductor R&D facility operated by the nonprofit NY CREATES. Jay Gambetta, IBM's Director of Research, wrote that the shift from 200mm to 300mm produces device output roughly 30 times faster by multiplying device complexity tenfold and tripling devices per line.

IBM's current production processor, Heron r2, holds 156 fixed-frequency qubits, while the Nighthawk processor, which went live via early access on IBM's quantum cloud in January, packs 120 qubits in a square lattice with 218 tunable couplers and a record median T1 coherence time of approximately 350 microseconds. IBM's fault-tolerance roadmap targets the Starling processor in 2029 at roughly 200 logical qubits running 100 million gates, followed by Blue Jay in 2033 at 2,000 logical qubits and 1 billion gates.

All of those chips need 300mm fabrication, and a dedicated foundry with established process design kits, in-line wafer testing, and baseline production routes could let other superconducting quantum companies skip the years and capital required to build their own cleanrooms. Anderon's initial process will support superconducting wiring, through-silicon vias, and bump interconnects, with plans to expand into other qubit modalities over time.

There’s an obvious comparison to TSMC here, which IBM is lapping up, but there’s also a fundamental difference: TSMC succeeded partly because its founder, Morris Chang, made an explicit promise not to compete with the companies that outsourced their fabrication. IBM obviously can’t credibly make that promise; it claims more than 90 operational quantum computers and an ecosystem spanning over 325 Fortune 500s, universities, and government agencies.

Quantum hardware startups considering Anderon will need to weigh 300mm production access against the risk of sharing process knowledge with their largest competitor. Google, which builds its own superconducting chips at its Santa Barbara facility and recently demonstrated quantum advantage on its 105-qubit Willow processor, is unlikely to outsource fabrication to IBM. IonQ and Quantinuum use trapped-ion architectures with almost no process commonality with superconducting silicon, and Microsoft's topological qubit program is on a different fabrication path entirely.

The near-term addressable market for Anderon is limited to other superconducting companies: Rigetti, IQM, SEEQC, and a handful of smaller companies, plus IBM itself. Whether any will actually outsource to a facility owned by their largest rival remains to be seen.

As for the choice of Albany, it carries some irony given that IBM's chip manufacturing presence in the region was effectively sold off in 2014 when the company paid GlobalFoundries $1.5 billion to take over its East Fishkill 300mm fab and Essex Junction 200mm fab. Those operations were losing roughly $700 million per year combined. GlobalFoundries later sold East Fishkill to ON Semiconductor in a deal finalized in 2023, and IBM and GlobalFoundries settled years of litigation over the original terms in January 2025.

The Albany NanoTech Complex, which sits on the SUNY Polytechnic campus, has received more than $25 billion in cumulative technology investment and hosts tenants including GlobalFoundries, Samsung, Applied Materials, ASML, Tokyo Electron, and Lam Research. In 2023, New York State committed $1 billion toward a High-NA EUV Accelerator at the complex as part of a broader $10 billion public-private partnership.

An escalating global spending race

The $2 billion U.S. quantum package comes amid a rapidly escalating global spending race. China's National Venture Guidance Fund, launched last March, authorized 1 trillion yuan, roughly $138 billion, across “hard technology” sectors, including quantum, with direct Chinese quantum investment estimated at $15 billion or more already deployed. Meanwhile, Japan has committed roughly $7.4 billion to semiconductors and quantum combined under its 2025 “Quantum Sun” industrialization agenda.

The EU Quantum Flagship is a rather paltry-by-comparison €1 billion, 10-year program. Combined with prior National Quantum Initiative spending and separate DARPA and Department of Energy programs, the CHIPS quantum package brings cumulative U.S. public quantum funding closer to parity with Europe and Japan but does little to close the gap with China.

BCG's widely cited estimate that quantum computing could generate up to $850 billion in economic value by 2040, which IBM referenced in its press release, is the optimistic end of a $450 to $850 billion range and describes end-user economic value, not vendor revenue. McKinsey's 2025 Quantum Technology Monitor projects a smaller $28 to $72 billion quantum computing revenue market by 2035, while Nvidia CEO Jensen Huang has publicly argued that practical quantum computing is 20 years away as a minimum.

It’s also worth noting that the Anderon deal isn’t yet finalized. CHIPS Act award histories show proposed amounts can shrink during due diligence: Samsung's manufacturing incentive, for example, fell from a proposed $6.4 billion in April 2024 to a finalized $4.75 billion by December 2024. Definitive documents between IBM and the DoC haven’t been executed.

Belgian semiconductor research giant imec this week announced what it describes as the world's first quantum dot qubit device fabricated using High-NA EUV lithography, marking one of the earliest demonstrations of advanced quantum hardware built using the semiconductor industry's most cutting-edge manufacturing technology. The device, unveiled at ITF World in Leuven on May 19, uses silicon quantum dot spin qubits — nanoscale structures that trap individual electrons and exploit their quantum spin states to store information — patterned at gate gaps of barely 6 nanometers.

At first glance, the announcement may seem like another entry in the increasingly crowded quantum computing race. The actual significance, however, has less to do with raw quantum performance and more to do with manufacturing — arguably the single biggest obstacle standing between experimental quantum systems and commercially useful quantum computers.

Qubits can theoretically solve computational problems that would take classical supercomputers longer than the age of the universe, but only at a scale nobody has yet achieved. With several advancements in the physics side of quantum computing, manufacturing now represents the major limitation. Imec claims to have addressed that directly by using the semiconductor industry's latest and most advanced lithography tool to fabricate silicon quantum dot spin qubits with tolerances compatible with industrial chip production for the first time. If that holds up, the implications for quantum scaling could be tremendous. It’s a significant step towards quantum computing, but we are still not quite there.

Manufacturing, not physics, is now quantum computing’s major bottleneck

Quantum computing’s central problem is no longer simply whether researchers can create functioning quantum systems. Our detailed quantum computing roadmap analysis showed that companies including IBM, Google, IonQ, Quantinuum, D-Wave, PsiQuantum, and others have already demonstrated a wide range of working architectures, from superconducting qubits to trapped ions and photonic systems. The problem is scaling those systems into reliable machines containing millions of reproducible, controllable qubits. — the level widely considered necessary for commercially useful, fault-tolerant quantum computers. The most ambitious industry players' roadmaps place that milestone around or beyond 2030, further proving that manufacturing, not physics, is the current hindrance.

Imec's technology directly targets that problem. The company’s approach centers on silicon quantum dot spin qubits, often described as “industry qubits” because they can, in theory, leverage conventional CMOS semiconductor manufacturing infrastructure. Instead of relying on exotic standalone fabrication ecosystems, silicon quantum dots attempt to piggyback on decades of transistor scaling and wafer manufacturing expertise already developed by the semiconductor industry.

The qubits themselves work by trapping individual electrons inside nanoscale silicon structures. The electron’s quantum “spin” state stores information, while surrounding metallic control gates manipulate interactions between neighboring quantum dots. While the concept may sound deceptively straightforward, its fabrication is exponentially more complex.

Quantum dot performance depends heavily on the spacing between those control electrodes. As neighboring quantum dots move closer together, coupling strength rises exponentially, improving controllability and interaction fidelity. But achieving those gains requires reliably patterning gaps measuring only a few nanometers across an entire wafer.

Imec says it fabricated functioning qubit arrays with gaps of barely 6nm between plunger and barrier gates, using High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography, the industry’s latest precision lithography technology.

High-NA EUV: not yet standard, already essential

High-NA EUV is the semiconductor industry’s next major lithography transition, developed primarily for future sub-2nm processors, advanced AI accelerators, and dense memory technologies. The systems, built by ASML, improve patterning precision by increasing the optical system’s numerical aperture, allowing dramatically smaller and more accurate features to be printed onto silicon wafers than current EUV systems can reliably achieve. The key difference between the new High NA EUV and conventional EUV is the increase in numerical aperture from 0.33 to 0.55

The machine weighs around 150 tons, spans the length of a double-decker bus, and requires an entirely redesigned optical system with mirrors twice as large and ten times heavier than those in standard EUV tools, polished by ZEISS to atomic precision. The technology is a ground-up engineering effort years in the making.

Even among mainstream semiconductor manufacturers, High-NA EUV technology is only just entering commercial deployment. Intel installed the industry's first commercial High-NA EUV lithography tool late last year, while imec received the technology in its 300mm cleanroom in March 2026 — two months ago. The machines themselves reportedly cost hundreds of millions of dollars apiece and represent one of the most complex manufacturing systems ever built.

The fact that imec has already applied High-NA EUV to quantum hardware — before most chipmakers have even integrated it into standard production flows — suggests quantum computing may be converging directly with the semiconductor industry's existing manufacturing roadmap rather than evolving as a separate technology stack entirely. That possibility can have significant implications. Instead of waiting for quantum-specific fabrication ecosystems to mature independently, silicon quantum hardware may be able to exploit the extremely advanced infrastructure of a multibillion-dollar industry, potentially significantly compressing quantum computing timelines. Although this does not mean manufacturable quantum computers are suddenly close.

The implications of imec’s achievement for quantum computing and the semiconductor industry

While imec's prototype remains far from a large-scale fault-tolerant quantum computer, it still represents a functioning silicon quantum dot spin qubit device — a type of quantum hardware designed to store and manipulate information using the quantum spin states of trapped electrons. These qubits belong to a class of quantum architectures viewed as promising candidates for tackling computational problems that quickly overwhelm even the world's most powerful supercomputers due to their enormous combinatorial and quantum-mechanical complexity.

Silicon quantum dot spin qubits are particularly notable among those candidates because their production process is compatible with standard CMOS semiconductor manufacturing — the same ecosystem that produces CPUs, GPUs, and AI accelerators. It is worth clarifying that imec's breakthrough lies in the manufacturing process, not in the qubit architecture itself. Silicon quantum dot spin qubits already exist and have been an active area of semiconductor and quantum research for over a decade. Previous devices have been demonstrated using conventional lithography at the laboratory scale. While that proved the architecture works, it stopped well short of what industrial scaling demands: consistent, reproducible fabrication at nanoscale tolerances across an entire wafer.

That is the gap imec is now targeting. By demonstrating that High-NA EUV lithography can pattern silicon quantum dot spin qubits at gate gaps of just 6 nanometers on a 300mm fab-compatible process, imec has shown for the first time that the semiconductor industry's most advanced manufacturing tool can be brought to bear on this class of quantum hardware — moving the architecture from lab-scale demonstration toward something that could eventually be manufactured like a chip.

If sufficiently scaled and stabilized, silicon quantum dot spin qubit systems could accelerate progress in molecular simulation, advanced materials discovery, pharmaceutical research, cryptography, logistics optimization, and complex physical-system modeling — fields whose computational demands can be prohibitively difficult for classical supercomputers, regardless of how powerful those machines become.

Rather than serving consumers directly, these systems would likely be deployed by hyperscalers, governments, national laboratories, pharmaceutical firms, and defense organizations tackling computational problems where even incremental breakthroughs could have massive scientific or strategic consequences. The technology would most probably be accessed through cloud-based quantum infrastructure rather than on-premises hardware.

This week, Nvidia released its Q1 2027 results, posting a record-breaking $81.65 billion in revenue thanks to sales of its AI and data center products. Colette Cress, chief financial officer of Nvidia, said that he expects sales of the company's Grace and Vera CPUs for data centers to hit $20 billion this fiscal year, thus outselling both AMD and Intel and becoming the world's largest supplier of processors by revenue. This is a realistic expectation, principal analyst and president of Mercury Research, Dean McCarron, tells Tom's Hardware Premium.

Outselling AMD and Intel

"Vera CPU opens a brand-new $200 billion TAM for Nvidia, a market we have never addressed before," Cress said during the company's conference call with financial analysts and investors. "Every major hyperscale and system maker is partnering with us to get it deployed. We have visibility to nearly $20 billion in total CPU revenue this year, setting us up to become the world-leading CPU supplier."

Nvidia later clarified that the $20 billion figure includes sales of Grace and Vera processors within Superchip combinations, NVL72 systems, and standalone CPUs sold either as racks aimed at agentic AI workloads or other applications.

Intel's data center and AI (DCAI) division's revenue totaled $16.8 billion last year, whereas AMD's data center unit earned $16.635 billion in 2025. While CPUs account for the lion's share of earnings of these business units, their sales are by far not 100% of their revenue, so actual sales of Xeon and EPYC products are well below $16 billion. The entire x86 server CPU market is worth around $30 billion. Therefore, the $20 billion figure would indeed approach two-thirds of the traditional server CPU market, making Nvidia the world's No. 1 server CPU supplier.

What makes Nvidia's statement especially remarkable is that while Grace CPUs are widely available and have shipped in huge quantities, its 88-core Vera CPU hasn't yet shipped in high volume. Furthermore, Nvidia has never meaningfully participated in mainstream server CPUs before. Given that Nvidia is poised to sell millions of Rubin data center GPUs, and every two of them will be attached to a Vera CPU, the company is almost guaranteed to sell plenty of CPUs.

"We will sell millions of Rubin GPUs and every two of them is connected to a Vera [CPU]," Jensen Huang, chief executive of Nvidia, told analysts and investors. "Vera is used in [four] ways. The first is Vera Rubin [platform containing two Rubin GPUs and one Vera CPU]. The second use case is Vera as a standalone CPU. The third is Vera with CX9 and its software stack for storage. The fourth is Vera with CX9 alongside a software stack for security, compute isolation, and confidential computing."

Conquering the CPU kingdom

Given the dominance of x86 servers, alongside AMD's EPYC and Intel's Xeon CPUs in particular, it is hard to imagine that another company can outsell these highly popular products. Yet, it is more than possible, given the fact that Nvidia can price its CPUs well above the average selling prices (ASPs) of other x86 offerings, and still manage to outsell competitors. This is because Nvidia sells vertically integrated platforms rather than standalone CPUs or GPUs. While Nvidia is not 'known' for its CPUs, it is definitely not a new entrant.

"Nvidia is in a unique situation, and I do not think we can really call them a 'new entrant," McCarron told Tom's Hardware Premium.

Based on leaked estimates from Morgan Stanley Research, Nvidia will charge its hyperscale clients around $5,000 per Vera CPU when they purchase VR200 NVL72 machines later this year. Assuming that the estimate is correct, then selling CPUs worth $20 billion will require Nvidia to sell 4 million Vera units. Four million units is perfectly achievable for Nvidia, McCarron believes.

"As far as delivering 4 million CPUs per year, Nvidia is already on track to deliver a number very near that for its GB300 and Rubin systems in FY2027 (so roughly Q2 2026 - Q1 2027 calendar year)," McCarron said. "So, their comment indicates some moderate upside to CPU shipments."

In fact, Nvidia could probably sell considerably more than four million CPUs this fiscal year if it wanted to, and if it secured or reallocated additional capacity for production of its 88-core Arm-based processor, according to McCarron.

"This really just comes down to customer demand and pricing/revenue allocation to get to the $20 billion," the analyst told us. "I would expect that the number is going to be heavily weighted towards the end of their fiscal year."

Speaking of capacity, Nvidia has commitments for capacity and inventory of around $145 billion, so capacity allocation may not be a problem for the company.

"We remain front-footed in securing sufficient supply to support our customers' growth," Cress said. "In Q1, we increased total supply, inclusive of inventory, purchase commitments, and prepaids, to $145 billion."

AMD and Intel shipped nearly 20 million EPYC and Xeon SP processors for data center systems in 2025, Dean McCarron told us. Meanwhile, AMD's EPYC average selling price was about $1,325, whereas the ASP of Intel's Xeon SP was about $1,125, according to Mercury Research. That said, if Nvidia sells 4 million processors worth $20 billion, then it will not only outsell both AMD and Intel, but will become a formidable rival for both companies from a pure unit sales point of view, too.

If the war in Iran and the subsequent closure of the Strait of Hormuz have shown anything, it's how vulnerable the just-in-time global supply chains are to disruption — especially high-tech chip manufacturing. Now there's a new concern on the horizon, with new reports suggesting that rising prices for anhydrous hydrogen fluoride for South Korean chip firms could cause a new spike in memory and storage prices.

Used in the etching and cleaning steps to remove oxide films and metal contaminants from wafers, anhydrous hydrogen fluoride is derived from fluorite and sulfuric acid, the latter of which is primarily produced from sulfur, a byproduct produced when refining crude oil and natural gas. The war in Iran has reduced critical supplies and refining capacity for those key materials, and sulfur supplies have also suffered; the knock-on effect is set to reach South Korean chip firms once again, The Elec reports.

China is the world's largest exporter of anhydrous hydrogen fluoride, but as sulfuric acid is also a key material in fertilizers, steelmaking, and battery cathode materials, it's now restricting its export, and prices have risen in turn. To date, the South Korean chemical market has absorbed these costs, but it now looks like by June or July, the memory makers will start to feel the shortages bite.

Canary in the Hydrogen Fluouride mines

Despite the U.S. war in Iran beginning in February, it's taken time for the domino effects of the subsequent clampdown on oil and gas refining and transportation to be felt; but the first smaller dominoes to fall began weeks ago.

At the beginning of April, Echemi reported that because of cost pressures, the price of anhydrous hydrogen fluoride in China had risen by around three percent in just the first week of the month. This was mostly driven by rising sulfuric acid costs, which jumped 27% week on week, caused by rising prices for sulfur.

There were already signs of slowing supply, though, with Echemi reporting some suppliers were projecting reduced output due to an inability to acquire raw materials. This, coupled with a shutdown of fluorite mines in the Zhejiang Province due to a mining accident, placed further pressure on the anhydrous hydrogen fluoride supply chain.

The Elec reports that China's response was to restrict exports, resulting in a mid-April price rise for hydrogen fluoride of as much as 130% over early-2026 levels, with sulfuric acid making up more than 50% of the overall production costs for the key material.

South Korean chemical companies Soulbrain, ENF Technology, and Foosung have started receiving these higher-priced orders of scarcer anhydrous hydrogen fluoride in mid-May. Before shipping them on to Samsung and SK Hynix, they'll mix it with ultrapure water and ammonium fluoride to create a high-quality etching material.

But they aren't going to eat those costs themselves. They're now forecasting that those costs will then be passed on to South Korean chip firms by early July at the latest.

History does rhyme

This isn't the first time a shortage of anhydrous hydrogen fluoride has threatened to upend memory industry pricing. In 2019, a trade dispute between Japan and South Korean resulted in a restriction on the sale of hydrogen fluoride to South Korea, raising the potential of memory shortages and pricing reactions.

At the time, Japan supplied over 40% of South Korea's hydrogen fluoride, but the export controls proved decidedly effective, cutting off 87.9% of the supply, according to a 2023 CEPR report. This forced South Korea to pivot and import more of the material from the U.S. and Taiwan, and improve its trading relationship with China in order to better secure chemical materials.

Despite this disruption, the effect on memory pricing for consumers was minimal. Spot and contract prices rose over material cost and supply concerns, but large inventories of memory meant that OEMs and consumer-facing retailers didn't raise their prices much in response.

Although the trade dispute between South Korea and Japan didn't end until 2023, the supply restrictions for hydrogen fluoride only caused a temporary adjustment in memory prices. By the end of Q3 2019, storage and memory prices had fallen for several months in a row, showing no long-term effect.

Unfortunately, 2026 is not like 2019. There is no glut of memory chips to buffer material supply concerns. There's a global shortage. And now what little is being made for consumers is going to be notably more expensive to produce.

This is one shortage that could be short lived

There's not much that can be done to avert the impending material cost spike for memory makers, and though they are making unprecedented profits, they're unlikely to absorb the cost increase themselves.

Fortunately, then, while there are going to be many long-term effects of the war in Iran, anhydrous hydrogen fluoride shortages for South Korean memory companies may be somewhat short-lived.

For several years, South Korea has been working to improve local production of this key material. Fluoride Korea, a subsidiary of U.S.-based BGF EcoMaterials, has invested around $100 million in building a new anhydrous hydrogen fluoride plant in Ulsan that has a projected annual capacity of 50,000 tons — around half of South Korea's demand.

Unlike memory fabrication lines that aren't projected to begin production until 2027 or 2028, though, this plan is set to come online by Q4 2026. While that will take time to spool up, and there is some international interest from Japan, which is also looking to diversify its supply chain away from China, this could be the new supply South Korean chemical firms need to avert a more-long term disaster as global sulfur prices continue to surge.

SMIC founder Richard Chang and AMEC chairman and CEO Dr. Gerald Yin appeared together on CCTV's Dialogue program on May 17th to make a coordinated case for Chinese chipmakers to give homegrown equipment more production-line trial time, according to DigiTimes.

The strange joint TV appearance came days after Chinese industry figures told Securities Times that the next three to five years will determine whether domestically built tools can move from functional prototypes to equipment that meets the yield, throughput, and uptime demands of volume manufacturing.

China's semiconductor equipment vendors collectively posted record revenues in 2025, but profitability is under pressure from domestic price competition, and the hardest remaining bottleneck, lithography, has no credible near-term domestic solution. U.S. export controls, meanwhile, continue to tighten.

Record revenues, falling margins

China's equipment industry grew incredibly fast last year. AMEC, the country's leading etch-tool maker, reported full-year revenue of $1.74 billion USD (12.38 billion RMB), up 36.6% year-on-year, with net profit totaling around $310 million (2.11 billion RMB), up 30.6%.

Naura Technology, the broadest-line domestic supplier, posted $3.91 billion (27.14 billion RMB) in revenue across just the first three quarters, while Piotech, which specializes in thin-film deposition, roughly doubled its nine-month revenue to $617 million (4.22 billion RMB). ACM Research, the U.S.-listed cleaning-equipment maker with the bulk of its operations in Shanghai, booked $901.3 million for the full year, up 15.2%.

Despite these lofty revenues, margins moved in the opposite direction: AMEC’s full-year 2025 gross margin fell 1.9 percentage points to 39.2%, with the third quarter alone dropping 5.8%, and ACM Research's gross margin slid from 50.1% in 2024 to 44.4% in 2025. The pattern was consistent across the sector.

This squeeze is coming from domestic competition rather than foreign pressure. With U.S., Japanese, and Dutch export controls restricting shipments of advanced tools to Chinese fabs, domestic vendors are competing fiercely with each other for orders that previously went to Applied Materials, Lam Research, and Tokyo Electron; Needham & Co. analyst Charles Shi recently told Nikkei Asia that this internal price war is the primary driver of margin erosion.

Chinese fabs are now thought to be sourcing roughly 35% of their equipment domestically, up from about 25% a year ago. Beijing's informal target for new fab construction is 50% domestic content, a threshold that YMTC's third Wuhan fab has reportedly already cleared, but the gains are concentrated in mature-node tool categories. Etch localization at mature nodes sits at roughly 50% to 60%, and resist stripping exceeds 80%. According to data from Ijiwei thin-film deposition runs from 20% to 30%, and lithography sits below 5%.

A public appeal

The Chang-Yin CCTV appearance was ultimately a strange, public, state-sanctioned appeal to Chinese fabs. Chang argued that domestic equipment can’t improve without real production-line trials and said fabs should start with small wafer batches of up to 100 wafers before scaling up to limit the risks of early adoption. Meanwhile, Yin said that Chinese customers still default to foreign tools out of habit, and even new systems from the world's largest equipment vendors typically require two to three years of tuning when first deployed at leading fabs.

Industry-standard timelines for qualifying a new etch or deposition tool on a leading-edge production line run 18 to 24 months from installation to qualified production status. The process tests reliability, particle contamination, process drift, and throughput under sustained operation, not just whether the tool can produce a working wafer under controlled conditions.

An example highlighted by Yin is that of AMEC, which, in December 2023, decided to enter the large flat-panel display equipment segment, a category he said was previously 100% imported. The tool in question weighs roughly 150 tonnes and measures 15 by 15 meters, but AMEC reportedly built a working prototype in 12 months, met a customer's next-gen specifications four months later, and shipped the tool to a production line within 18 months total. Needless to say, those claims haven’t been independently verified and shouldn't be taken at face value.

AMEC also claims SMIC has purchased at least 800 of its tools, a figure Chang cited on the same broadcast, and that its etch technology is used in TSMC's supply chain at nodes from 65nm down to 5nm and 3nm. TSMC hasn’t publicly confirmed the scope of AMEC's role in its production lines, however.

Recent disclosures show that SMIC faced yield losses tied to equipment maintenance and validation stalls in 2025, the exact production-line qualification problem Chang acknowledged on CCTV. The foundry has reportedly acquired some foreign tools that are sitting idle because spare parts and field service from sanctioned suppliers are no longer available under normal terms.

Still no lithography solution

None of China's equipment progress addresses the most critical chokepoint: lithography. Shanghai Micro Electronics Equipment (SMEE), the only Chinese supplier of lithography scanners in any volume, produces a 90nm-class ArF system. While a 28nm-class tool has been reported in development, it’s not confirmed in mass production, and details are scarce.

One project to watch, however, is the Shanghai Yuliangsheng immersion DUV scanner under test at SMIC. That tool, linked to Huawei-backed SiCarrier under the codename "Mount Everest," resembles ASML's Twinscan NXT:1950i from 2008, two product generations behind the NXT:2000i used in current 7nm and 5nm production. SMIC is thought to be targeting the Yuliangsheng tool for its 28nm production flow in 2027, but sub-10nm lithography on purely domestic equipment is unlikely before 2030.

In Q3 2025, 42% of ASML's system sales by revenue went to Chinese customers, confirming that Chinese fabs are buying DUV scanners as fast as current export rules allow. But Washington is working to narrow this window further, with the MATCH Act, which was introduced last month. It names and designates the likes of AMEC, Naura, Piotech, ACM Research, SiCarrier, and SMEE, among SMIC, YMTC, Hua Hong, CXMT, and Huawei, as “Covered Facilities” and would impose a country-wide prohibition on exporting DUV immersion lithography tools to China.

The House Foreign Affairs Committee passed the bill 36 to 8 in late April after removing a proposed ban on cryogenic etch tools, which would have affected Lam Research and Tokyo Electron. The DUV immersion ban remains in the bill as it heads toward a Senate floor vote. As of the time of writing, it’s currently sitting in a Senate Committee.

China criticized the legislation less than a week before the duo’s state-sanctioned television address to chipmakers. The broadcast itself is ultimately best viewed as part of Beijing's response: a coordinated message that domestic fabs need to accelerate qualification of Chinese-built alternatives before the remaining supply lines are cut.

Last week, Anthropic announced that it had struck a deal with SpaceX to lease all of the latter's Colossus 1 data center, with over 220,000 GPUs and 300 megawatts of compute capacity. The deal immediately raises questions, foremost among them: why would Musk lease one of xAI’s most aggressively hyped AI assets to a direct rival? With SpaceX's IPO just around the corner, a related strategy appears to be at play, but it also turns out that the system's mixed architecture with different types of GPUs may be a key reason Musk has decided to lease the system.

Anthropic says the newly acquired capacity will primarily be used to ease long-standing usage bottlenecks across Claude’s paid ecosystem. According to the company, the additional compute will enable significantly higher Claude Code limits, the removal of peak-hour throttling for Pro and Max subscribers, and substantially increased API request limits for Claude Opus models used by developers and enterprise customers.

The seemingly unlikely partnership — a complete turnaround of Musk's earlier stance on Anthropic — also reveals Anthropic is straining under the Claude ecosystem’s compute demands. The company says it needs the entire 300 MW AI supercluster just to improve the experience of using Claude.

Anthropic appears to have hit the compute wall

The earliest signs that Anthropic was struggling to keep up with the computing demands of its growing user base were the increasingly aggressive usage limits placed across Claude’s services. Free users frequently complained about rapidly exhausting tokens — the units Claude assigns for processing tasks. However, the restrictions extended beyond the free tier. Paid Pro, Max, Team, and Enterprise users also regularly encountered message caps, peak-hour throttling, API rate limits, and strict time-based usage ceilings on Claude Code sessions, particularly during periods of heavy demand.

It was clear that Anthropic was running out of inference capacity. While training an AI model is an expensive, one-time computational undertaking, serving that model to millions of users simultaneously creates a continuous, round-the-clock demand for compute that scales directly with every new user and every new query. The apparent solution is to build more data centers, which Anthropic is apparently pursuing via massive gigawatt deals with Amazon, Google, Microsoft, and Nvidia.

However, modern hyperscale AI data centers can cost tens of billions of dollars and take years to build. Utilities are increasingly struggling to supply sufficient electricity for AI projects, while land, transformers, cooling infrastructure, and high-end GPUs themselves remain constrained. There is also growing sentiment against AI infrastructure from local communities. We recently reported that a U.S. senator got physical with a reporter after a confrontation on a data center issue.

Anthropic's compute capacity problem was immediate and urgent, but the solution was significantly long-term. If only there were a massive AI supercluster with hundreds of megawatts of compute power just sitting there. Turns out there was: SpaceXAI’s Colossus 1. Following the deal, Colossus 1’s entire computing power now belongs to Anthropic — for now.

Musk, xAI, SpaceX, and an upcoming IPO

When Musk unveiled Colossus, it was framed as one of the clearest signs that xAI intended to compete seriously with OpenAI, Anthropic, and Google at the AI frontier. The Memphis-based cluster became famous for how quickly it was assembled. Tens of thousands of Nvidia GPUs were reportedly brought online in record time, eventually scaling to over 220,000 accelerators. Musk repeatedly boasted about xAI’s future compute ambitions, including plans to expand toward million-GPU-class systems through Colossus 2.

So why does he seem to have wrapped the whole thing in a neat little bow and handed it over to Anthropic, xAI's rival? One possible answer is utilization. Reports suggest that Colossus 1 may have had more available capacity than Grok’s current user base required. However, according to a detailed report by Mirae Asset Securities — a major South Korean investment bank — the bigger utilization issue was architectural. Colossus 1 is a heterogeneous cluster, mixing roughly 150,000 H100s, 50,000 H200s, and 20,000 GB200s — three different generations of Nvidia silicon running under one roof. This was largely a byproduct of how fast xAI assembled the cluster, with different GPU generations coming online as supply allowed, rather than a deliberate design choice.

For AI training, the heterogeneous configuration creates a significant efficiency problem. Distributed training requires every GPU in the cluster to complete each computational step simultaneously before the system can advance. When the faster GB200 chips complete their work first, the entire cluster waits for the slower H100s to catch up — a well-known bottleneck known as the straggler effect. At 220,000 chips, this effect is exponential.

As a result of these issues, xAI's real-world GPU utilization reportedly sat at just 11% — meaning 89% of the cluster's theoretical computing power was going to waste. For context, Meta and Google typically operate at 40% or above.

AI GPUs are not static assets that quietly sit on shelves, gaining value over time. They depreciate rapidly, consume enormous amounts of electricity, and require expensive maintenance and cooling infrastructure. Unused GPUs are effectively burning money.

From that perspective, Anthropic may have arrived at exactly the right moment. The company had exploding demand and an urgent need for ready-made compute, while SpaceX/xAI had a gigantic, not-so-great first-generation AI cluster. For Anthropic, however, the same cluster looked quite different. The company needed compute power for Inference — running queries through an already-trained model, which does not require the tight synchronization that training workloads demand. So, what was a structural inefficiency for xAI's training workloads is a workable infrastructure for Anthropic's inference needs.

Multiple reports suggest xAI is now heavily focused on Colossus 2, a far larger next-generation cluster reportedly aimed at gigawatt-scale AI infrastructure. Unlike Colossus 1's chaotic mix of chip generations, Colossus 2 is built entirely on Nvidia's Blackwell architecture — a homogeneous cluster where every GPU is identical. In a uniform cluster, every chip completes each training step at roughly the same time, allowing GPU utilization to theoretically surpass the range in which Meta and Google currently operate. xAI can also properly optimize its software stack for a single hardware generation rather than trying to serve three simultaneously.

According to the Mirae Asset report, xAI has already moved its core training workloads entirely onto Colossus 2, effectively treating Colossus 1 as a retired first-generation asset. In other words, Colossus 1 may have transitioned from "cutting-edge frontier training weapon" into a monetizable first-generation compute asset, while Musk continues to build towards xAI’s “takeover” with Colossus 2.

Musk has long treated his companies less like isolated entities and more like interconnected pieces of a broader ecosystem. Tesla technologies appear across SpaceX projects. SpaceX infrastructure supports xAI ambitions. xAI products increasingly feed into Musk’s wider platform strategy.

The deal also hints at another possibility: Musk could be positioning SpaceX/xAI as more of an AI cloud infrastructure provider. That would not be entirely surprising. xAI has already launched Grok Business and enterprise-focused offerings featuring APIs, security controls, audit logging, and corporate integrations. This also aligns with Musk’s reported plans for broader structural changes at SpaceX and xAI ahead of the company's upcoming IPO.

Earlier this year, Musk publicly attacked Anthropic and Claude, calling the company “misanthropic and evil.” Yet this week, he claimed he approved the deal after speaking with Anthropic executives and determining that “no one set off my evil detector.”

Mirae Asset’s analysts attempted to estimate the value of the Anthropic deal, using estimated hourly lease rates for different Nvidia GPU types. The analysts projected that Colossus 1 could theoretically generate roughly $5–6 billion in annual revenue. That nearly perfectly offsets xAI's annualized net loss of approximately $6 billion as of Q1 2026, effectively pulling the company to breakeven in a single contract.

For Anthropic, the analysts applied CEO Dario Amodei's own publicly stated estimate that roughly half of all AI industry compute spending goes toward inference, and that inference compute converts to revenue at a 3x multiplier. On that basis, the $5 billion being directed toward inference capacity could generate approximately $15 billion in incremental ARR — a significant addition to Anthropic's already rapidly growing revenue base.

Stellar ambition

Another critical aspect of the announcement involved “orbital AI compute capacity” — basically, data centers in space. Granted, it does sound like science fiction marketing language. But it directly ties into a core problem both companies, alongside several other AI giants, are increasingly facing: AI infrastructure is beginning to outgrow terrestrial constraints. So when a joint announcement comes from the world's largest AI company and the company that built the world’s largest reusable rocket system and operates thousands of active satellites in orbit, you best believe we may soon have data centers floating around in space.

Despite Mirae Asset’s analysis, the factual financial details of the Colossus deal are not publicly available. However, Anthropic recently raised $30 billion in a Series G funding round, valuing the company at $380 billion. It would not be too wild a guess to say some of that cash may have gone into funding the Colossus agreement. Then again, the company said last month that its annualized revenue run rate had already surpassed $30 billion, highlighting the staggering scale at which Claude’s business is now operating.

xAI built Colossus 1 fast — too fast, it turned out. The resulting mixed GPU architecture created structural training inefficiencies that made the cluster hard to justify as a long-term platform. With Colossus 2 now operational and built properly on uniform Blackwell hardware, Colossus 1 became a first-generation asset in search of a better use.

Anthropic, with explosive demand and not enough compute, provided exactly that. The deal converts what was effectively a depreciating liability into roughly $6 billion in annual revenue — enough to bring xAI close to breakeven. For Anthropic, the same compute could unlock an estimated $15 billion in additional ARR. Both companies got what they needed, and Musk gets a compelling infrastructure story heading into a potential IPO.

As chipmakers push EUV lithography toward its physical limits at 2nm and below, the advanced chemicals used to pattern those circuits have become a critical bottleneck. Photoresists, the light-sensitive materials that transfer circuit designs onto silicon wafers, must be reformulated for each new process node, and the most advanced EUV-grade resists are produced almost exclusively by a handful of Japanese suppliers. With AI chip demand driving record orders at leading foundries, those suppliers are now racing to build production capacity closer to their biggest customers.

JSR, the Japanese chemical maker that holds roughly a quarter of the global photoresist market, established a joint venture with Taiwanese partners Wah Lee Industrial and LCY Chemical in early April to build its first photoresist production facility in Taiwan. The plant, located in Yunlin County, is expected to come online as early as 2028 and will co-develop advanced photoresists with TSMC, ending the company's status as the last of Japan's three leading EUV-class resist suppliers without a Taiwanese manufacturing base.

The expansion comes as JSR simultaneously ramps the world's first production-scale facility for metal oxide resist (MOR) in South Korea, a next-gen EUV chemistry that the company acquired through its $514 million purchase of Inpria in 2021. Together, the two plants represent a coordinated push to lock JSR into the development pipelines of the world's most important chipmakers before Chinese competitors can close the gap at the leading edge.

JSR under new ownership

JSR is no longer a publicly traded company. Japan Investment Corporation (JIC), a government-backed fund, completed a tender offer at ¥4,350 per share in April 2024, securing more than 84% of outstanding stock. JSR delisted from the Tokyo Stock Exchange on June 25, 2024, and the merger was finalized in December. The deal valued the company at roughly ¥909 billion ($6.4 billion).

Under JIC's ownership, JSR has moved aggressively to concentrate on semiconductor materials. The company divested non-core assets to Resonac and Tokuyama in early 2025 and exited its biotech business entirely. In May 2024, it acquired Kyoto-based Yamanaka Hutech, adding chemical vapor deposition (CVD) and atomic layer deposition (ALD) precursor expertise. Then, in September last year, JSR settled long-running patent litigation with Lam Research and converted it into a cross-licensing agreement covering dry-resist EUV patterning and etch precursors.

JSR's decision was driven by a direct request from TSMC, according to CommonWealth Magazine. New CEO Tetsuro Hori, who took over in April 2025, told the publication that "speed is critical," noting that local production would eliminate the need to ship wafers out of Taiwan during co-development cycles.

JSR had been shipping resist samples from facilities in Japan, the U.S., and Belgium, with each development cycle taking weeks for round-trip shipping alone. A week after the joint venture was announced, JSR opened a separate advanced planarization research center in Hukou, Hsinchu County, in partnership with TSMC and Applied Materials.

Location, location, location

A Photoresist is the light-sensitive material that transfers circuit patterns onto silicon wafers during lithography. At advanced process nodes, resist formulations need to be precisely tuned to work with specific exposure wavelengths, dose profiles, etch chemistries, and integration workflows. Each new node requires hundreds of iterative test cycles between the resist supplier and the foundry.

JSR's two largest Japanese rivals have had a co-development presence in Taiwan for years. Tokyo Ohka Kogyo (TOK) and Shin-Etsu Chemical, the first- and third-largest photoresist suppliers respectively, both operate production facilities on the island where their engineers work directly alongside TSMC's process teams.

Shin-Etsu runs a line in Douliu, also in Yunlin County, and is building a new ¥83 billion facility in Isesaki, Gunma Prefecture, while TOK has been present in Taiwan for more than a decade and announced a ¥20 billion photoresist plant in South Korea in late 2025 to serve Samsung. This means that every major Japanese materials supplier is now either manufacturing in Taiwan or actively building out capacity to do so.

JSR's Taiwan plant will produce photoresist for TSMC, but in the longer term, the company will focus on metal oxide resist (MOR). MOR uses tin-oxide-based chemistry rather than the organic polymers and photoacid generators found in CARs, which rely on chemical amplification to compensate for the few high-energy photons produced by the light source at 13.5nm EUV wavelengths. However, that amplification introduces acid-diffusion blur and worsening line-edge roughness as feature sizes shrink.

Tin-oxide MOR absorbs EUV photons roughly five times more efficiently than organic CARs, according to Inpria, and uses molecular building blocks roughly five times smaller, while etch resistance is 10 to 100 times higher. At SPIE Advanced Lithography 2025, Inpria reported MOR patterning down to pitch-18 with full etch transfer, while Imec demonstrated additional dose-response improvements by adjusting oxygen concentration during the post-exposure bake step.

JSR's MOR production plant in Cheongju, South Korea, built through its JSR Micro Korea subsidiary, is expected to begin mass production this year, supplying Samsung Electronics and SK hynix with tin-based MOR for EUV layers in next-gen DRAM. Both memory makers are reportedly planning to adopt MOR on selected layers for their 1c (sixth-gen 10nm-class) DRAM nodes.

JSR plans to market MOR to TSMC as well, according to Nikkei. TSMC has stated repeatedly that it won’t adopt high-NA EUV through its A14 (1.4nm-class) node in 2028, instead extending low-NA with multi-patterning, which pushes the largest MOR opportunity at TSMC's logic fabs out toward 1.0nm-class processes and beyond.

Chinese competition at the lower end

Japanese companies collectively control roughly 80% of the global photoresist market, and dominance at the EUV level is even more concentrated: JSR, TOK, and Shin-Etsu account for nearly 85% of EUV resist production volume, according to industry estimates. Chinese firms have made progress at the KrF and i-line level, but penetration at ArF and above remains negligible. Domestic Chinese supply of ArF and EUV resist sits below 5%.

The names to watch are Hubei Dinglong, Xuzhou B&C Chemical (backed by Huawei's Hubble Investment arm), Jiangsu Nata Optoelectronic, and Shanghai Sinyang. Xuzhou B&C claimed it achieved a 14nm wet-process photoresist breakthrough in 2024 and targets advanced mass production within five years, according to TrendForce, but analysts view that timeline as optimistic given the multi-year customer-qualification cycles that resist adoption requires.

"Chinese players are a threat, but it'll still be some time before they can catch up with us and take market share," Toru Kimura, a senior officer at JSR who heads the company's electronic materials business, told Nikkei. Specific capacity figures, the output mix between MOR and conventional resists, and the exact scope of the Yunlin plant haven’t been disclosed.

When Arm introduced its first 'physical' AGI processors in late March, the company expressed optimism about their adoption by select customers. In less than two months, the company attained around $2 billion in commitments for its AGI CPU over the next several years, smashing the company's expectations two-fold. But despite this heightened interest, Arm's market share will remain in the low single digits even if it manages to ship $2 billion worth of CPUs in two years, Mercury Research told Tom's Hardware.

"Customer response to the Arm AGI CPU is already strong, with more than $2 billion of customer demand across FYE27 and FYE28 – more than double what was stated at Arm Everywhere," Arm declared in its earnings press release.

Arm officially introduced its AGI CPU on March 24, 2026, and referred to it as 'production silicon,' meaning the design of the processor itself is final. Actual production of the CPU is expected to begin in the second half of 2026, with initial customer shipments expected in Q4 2026. Arm expects to ship $90 to $100 million worth of AGI CPUs in Q4 2026 alone.

Given the rising interest in the new chip, the company expects to generate $15B in AGI CPU sales and $10B in IP revenue by FY 2031 (ending on March 31, 2031), which will drive its total revenue to $25B per year, up from $2.61B in FY 2026.

Generating $15 billion in data center CPU sales in a single year is a big deal; Intel earned $16.8B selling server processors last year, after all. Given the rising demand for CPUs, particularly for agentic AI workloads, Arm's revenue may indeed increase by almost a factor of 10, with actual CPUs accounting for 60% of that total figure.

Single-digit percent of the server market

While $100M worth of AGI CPUs in Q4 2026 and over $2B of demand for the next two fiscal years looks like a lot of money (especially given the fact that Arm's current annual revenue is $2.61B), Arm's presence in the server and data center CPU market (silicon CPUs, not IP) will be negligible (yet still quite hard to achieve) if compared to share of merchant CPUs.

AMD and Intel sold just under 20 million data center-oriented EPYC and Xeon SP processors worth tens of billions of dollars in 2025, according to Dean McCarron, president and principal analyst at Mercury Research, a leading CPU market research firm. If we consider only 2025 data center CPU shipments, Arm would need around 4% unit share of the current server CPU market to achieve its $2 billion revenue target.

"In round numbers for 2025, AMD's EPYC average selling price was about $1,325," Dean McCarron told Tom's Hardware Premium. "For Intel, the 2025 ASP for Xeon SP* is about $1,125. What Arm gets of course might be different, and prices are rising, but something like $1,250 probably is not a bad starting place."

At this point, it is hard to estimate the actual ASP of Arm's AGI since while the company advertises processors with up to 136 cores, we can only wonder how many SKUs there will be and how many cores entry-level models will have. If Arm behaves like a typical CPU maker — balancing recovery of development and manufacturing costs against maximizing margins — then AGI's ASP will be comparable to that of EPYC or Xeon.

"So, $2 billion would take roughly 1.6 million CPUs, if that is done over the course of a couple years — eight quarters — that is an average of 200,000 units per quarter," McCarron explained. "For comparison, in 2025, the combined EPYC and Xeon SP markets averaged just under 5 million units per quarter, and of course, that is going to be growing rapidly in 2026 and beyond. So, Arm's $2 billion in server CPU revenue requires them to sell just 4% of the total units right now, and this would be an even smaller percentage of the total in a couple years."

Since Meta is a co-designer partner and lead customer for Arm's AGI CPU, it might get a considerably lower price, which means that Arm will have to supply more units to meet its revenue target, which will mean a higher market share at the cost of lower profits.

"While those [ASP] figures span entry-level to the largest cores, the volumes (and ASPs) are dominated by the hyperscalers," explained McCarron. "When you buy hundreds of thousands of units at a single time, there are some volume discounts, which is why the ASPs are in the low thousands and not $10,000+."

*Other Intel server products were excluded from the comparison as they are not direct competitors to Arm-based data center CPUs.

But can Arm supply?

Given the widespread shortages of everything from wafers at TSMC to memory and from storage devices to advanced chip packaging capacity, we can only wonder whether Arm can increase its output of its AGI CPUs in the next two years by a factor of two. The company has not given a positive answer straight away, but it claims that it is working on it.

"How quickly can we get units?" Rene Haas asked rhetorically. "The number that we talked about end of March was supply in place to support $1 billion of demand, and that includes memory, that includes wafers, that includes packaging, that includes access to test equipment. For the $2 billion, we are now in the process of securing supply to support that. The teams are working around the clock to make sure we can find the right answers for our customers."

Strategic positioning

Strategically, Arm positions its AGI CPUs not as traditional off-the-shelf processors competing directly with merchant CPU vendors and/or custom silicon designed by (or for) leading hyperscale cloud service providers, but as scalable compute platforms and subsystems that hyperscalers and OEMs can use for specific workloads and vertically integrated AI stacks.

The first-gen Arm AGI processor was co-developed with Meta, which will be the first and lead customer for the CPU. Nonetheless, Cerebras, Cloudflare, F5, OpenAI, Positron, Rebellions, SAP, and SK Telecom plan to deploy the Arm AGI CPU for a variety of use cases that include agentic AI CPU workloads. These include accelerator management and control plane processing, as well as other CPU workloads that support AI agent infrastructure or typical cloud workloads.

While the AGI processors will not be available on demand like server CPUs from AMD and Intel, interested parties will be able to get AGI-based rack-scale solutions from such OEMs and ODMs as ASRock Rack, Lenovo, Quanta Computer (which is the leading supplier to Meta), and Supermicro.

On the hardware side, Arm claims that its AGI processor is the world's most efficient agentic CPU. In particular, Arm claims that its AGI CPU was purpose-built as a new class of processor for sustained parallel performance at rack scale, delivering high 'per-task performance' without throttling across thousands of cores and retaining modern data center power and cooling limits.

Arm's 1^st Generation AGI is a data center-bound processor that features up to 136 high-performance Neoverse V3 cores at up to 3.70 GHz, based on the Armv9.2 instruction set architecture, equipped with dual 128-bit SVE2 (Scalable Vector Extension 2) units per core, as well as 2MB of L2 cache per core.

The CPU features a 12-channel DDR5 memory subsystem supporting up to 6 TB of 8800 MT/s memory, providing up to 6 GB/s of bandwidth per core, and has an I/O that supports 96 PCIe Gen6 lanes with CXL 3.0 on top for caching and memory expansion. The CPU is comprised of two identical chiplets (with their own memory interfaces and I/O) made using a 3nm-class process technology and has a thermal design power of 300W.

Arm has a roadmap for its own AGI processors that spans years. While the company does not disclose it to the public, its management implies a consistent and significant core count increase, and believes that agentic AI workloads will call for racks full of CPUs rather than racks that pack a few CPUs and tens of AI accelerators. When it comes to agentic AI workloads, they will not call for more CPUs, but rather for more CPU cores; hence, the rapid core count increase seems to be a logical evolution for Arm's own AGI processors.

"The way I think they think about it is that while the ratios may not go to more CPUs than GPUs from a chip standpoint, they probably will from a core count standpoint," said Rene Haas, chief executive of Arm, during the recent earnings call. " CPUs today, the Arm AGI CPU, for example, has 136 CPU cores. [Nvidia's] Vera, that is 88. As I mentioned earlier, could I see those core counts doubling or quadrupling over the next number of years? Absolutely. […] Will you see many more CPUs inside a data hall, dedicated racks of CPUs that are doing agentic orchestration and scheduling and management? 100%."

With up to 136 highly high-performance cores optimized for agentic AI and data center workloads and available starting from Q4 2026, Arm's AGI CPU is poised to be in high demand from those who need high-end CPUs to run their AI agent infrastructure and whose software stack is already optimized for Arm.

Arm braces for AGI influx

Orders for Arm's 136-core AGI CPUs have doubled to over $2 billion since their announcement on March 24. The development is a result of the skyrocketing growth of demand for CPUs for agentic AI infrastructure and reflects similar occurrences at AMD and Intel. The company now expects to generate $15 billion in AGI CPU sales and $10 billion in IP revenue in fiscal 2031 (which ends on March 31, 2031), increasing its revenue by 9.5X in five years.

However, while $2 billion by FY2028 and $15 billion in FY2031 look like a huge amount of money, Arm will remain a strong contender, rather than a major supplier of data center CPUs, as AMD and Intel earn tens of billions per year selling their EPYC and Xeon parts and are projected to earn hundreds of billions in the 2030s.

Mercury Research believes that Arm could ship roughly 1.6 million of AGI CPUs over the next two fiscal years, which looks pale compared to nearly 20 million of EPYC and Xeon processors sold in 2025. Still, it should be noted that Arm does not plan to compete directly with merchant CPUs as its AGI processors will be available to select hyperscale CSPs and through OEMs and ODMs that will offer rack-scale solutions based on AGI CPUs.

The Trump administration is in early discussions about an executive order that would create a government review process for AI models before public release.

The proposed order would establish a working group of tech executives and government officials to develop oversight procedures, with White House staff briefing leaders from Anthropic, Google, and OpenAI on the plans last week, according to unnamed U.S. officials cited by the New York Times. A White House official told the Times that talk of an executive order is "speculation."

The discussions, if true, would represent a reversal for an administration that revoked Biden's AI safety executive order within hours of taking office in January 2025 and spent most of last year talking itself up as the industry's deregulatory champion. Vice President JD Vance told an international AI gathering in Paris last year that the future of AI wouldn’t be won through safety concerns but "by building," the New York Times noted.

Lobbying backlash

In October last year, David Sacks, then the White House's AI and crypto czar, publicly accused Anthropic of "running a sophisticated regulatory capture strategy based on fear-mongering," in a post on X. Sacks pointed to CEO Dario Amodei's endorsement of Kamala Harris and his characterization of Trump as a "feudal warlord," in addition to the hiring of multiple Biden-era officials to its policy team.

Anthropic’s monthly lobbying spend grew by roughly 511% over Trump’s second term, reaching $1.1 million per month by late 2025, the Washington Examiner reported in early February. The company lobbied against a 10-year moratorium on state AI regulation in the Big Beautiful Bill, supported California's SB 53 transparency requirements, and donated $20 million to Public First Action, a political group calling for stricter AI oversight.

Now the administration appears to be building precisely the type of oversight structure that Anthropic advocated for, but with the government holding the keys. The New York Times reported that some officials want a system granting the government first access to new models without blocking their commercial release, and that’s (functionally) what the Pentagon demanded from Anthropic before their relationship collapsed.

Just this Monday, Dean Ball, a former Trump administration AI adviser, and Ben Buchanan, a former Biden White House AI adviser, co-authored a New York Times op-ed calling on Congress to mandate third-party audits of AI developers' safety claims. Buchanan is also an outside adviser to Anthropic, and Ball is the same official who told the Times that the administration is trying to avoid overregulation while keeping pace with the technology.

Carrot and stick

The proposed review process represents a softer approach than what the administration attempted earlier this year. In February, Defense Secretary Pete Hegseth gave Anthropic an ultimatum: remove guardrails on autonomous weapons and mass surveillance, or lose its $200 million Pentagon contract. Hegseth also threatened to invoke the Defense Production Act, a Korean War-era law that could theoretically compel the company to hand over its technology for military use.

Anthropic refused. Trump subsequently ordered all federal agencies to stop using Anthropic's technology, and the Pentagon designated the company a supply chain risk, a label previously reserved for foreign adversaries. Anthropic sued, and a federal judge called the designation "Orwellian."

But in April, the D.C. Circuit Court of Appeals denied Anthropic's motion to lift the designation entirely. The court ruled that removing it would force the military to continue dealing with "an unwanted vendor of critical AI services in the middle of a significant ongoing military conflict." That ruling shifted legal leverage back toward the government, even as the White House pursued a more conciliatory political path.

The confrontational approach through Hegseth and Sacks gave way to a diplomatic one after Sacks left his role in March, the New York Times noted, with White House Chief of Staff Susie Wiles and Treasury Secretary Scott Bessent stepping in.

Last month, Wiles and Bessent held a meeting with Amodei that both sides described as "productive,” with a White House statement later stating that the meeting had “discussed opportunities for collaboration, as well as shared approaches and protocols to address the challenges associated with scaling this technology."

The U.S. behind the EU on AI vetting

According to the New York Times’s reporting, any potential oversight would involve the NSA, the White House Office of the National Cyber Director, and the Director of National Intelligence.

The model under consideration resembles the UK's approach, where the AI Security Institute evaluates frontier models against safety benchmarks before deployment. Per security publication CSO Online, both the UK’s AISI and the EU’s AI Act have moved further than the U.S. on pre-deployment evaluation, and the U.S. currently has no legal authority to require such reviews.

There’s also the question of the Center for AI Standards and Innovation (CAISI), a Biden-era body created to evaluate AI models voluntarily shared with the government. The New York Times has reported that the center has been sidelined under Trump, despite the administration's own AI policy paper stating it should play a role in assessing AI system performance.

Congress appears to be moving in parallel with the administration, with the FY2026 National Defense Authorization Act requiring the Pentagon to establish a cross-functional team for AI model assessment and oversight, with a full “DoD-wide assessment framework” due at some point in the future. That team must develop testing procedures, security requirements, and compliance standards for AI models procured by the military.

Was Mythos the catalyst?

The obvious question in light of all this is whether Mythos was the catalyst for these new White House policy discussions. The New York Times certainly seems to believe so in its reporting, though no sources are quoted as confirming that.

Mythos, which Anthropic revealed last month in what felt like a marketing campaign, is what Anthropic has framed as a potential cyber-superweapon, capable of finding thousands of critical software vulnerabilities in seconds, and, as such, poses “unprecedented cybersecurity risks.” For these reasons, Anthropic has declined to release it publicly, but the NSA has already used Mythos to assess vulnerabilities in government software, according to the newspaper.

This reluctance to release Mythos as a model too dangerous for the general public may have given the administration both a justification and a political incentive to act. The White House wants to avoid fallout if an AI-enabled cyberattack occurs, and is also evaluating whether frontier models could yield offensive cyber-capabilities useful to the Pentagon and intelligence agencies.

Independent assessments have questioned the veracity of Anthropic's claims, and Research from AISLE Security found that open-source models could detect many of the same flagship vulnerabilities. The UK's AISI also evaluated Mythos and concluded it was the most capable model for cybersecurity tasks, but didn’t dramatically outperform others across all evaluations.

According to a new survey conducted by Ipsos at the end of last year, almost half of all queried Americans said they would oppose an AI data center being built near their community. This level of opposition is higher than that given to the creation of multi-apartment buildings, new apartment complexes, or mixed-use developments.

This survey appears to highlight the growing opposition to data center construction in America. Around half of all previously announced data center projects have been delayed or cancelled entirely. Often this was for financial or component supply issues — such as Chinese power transformer shortages — but growing opposition from local lawmakers and communities about their impact on water and air quality, and electricity prices, has also been a factor.

As resentment toward AI data centers appears to be on the rise, this problem for hyperscalers may only worsen as larger swathes of the American public oppose the creation of new “AI factories.”

Millennials are the least concerned

In the survey, 4,000 U.S. residents were polled about their feelings towards the construction of new AI data centers near their communities. It was designed to gauge their fears around local environmental and service disruption, as well as the broader case of AI displacing human workers and upending social institutions.

In total, 47% of respondents said they opposed the construction of new AI data centers in their neighborhood, with just 38% saying they supported it. That support was spread differently throughout various age ranges, however.

Of those questioned, 50% of Millennial age respondents said they either somewhat or strongly supported the creation of new AI data centers in their neighborhood or local area. This was closely followed by 48% of Gen Z respondents. There was a large drop off after that, with only 38% of Gen X saying they supported their creation. Baby boomers were the least enthusiastic, with just 22% claiming they felt the same.

In what is perhaps an example of the current U.S. administration’s influence and its entanglement with top tech firms, 49% of surveyed Republicans claimed they would support new data center creation in their local area. This stood in stark contrast to just 36% of Democrats. A causal trend could also be drawn from the fact that Republican voting states and counties tend to be more rural, with less economic activity. Data center projects do require construction, and there is the potential for local job creation.

When it came to homeowners and renters, surprisingly, it was the homeowners who were more likely to support it, with 39% versus 36% of renters claiming they either somewhat or strongly supported new data center development in their neighborhood.

Turning distrust into action

Although less than half of respondents in this survey offered strong opposition to data centers, the opposition they actually throw up to the construction of these new facilities is growing and having a serious effect.

City councils that back data center projects are being voted out, other city councils are putting moratoriums on data center construction, and instances of more extreme violence towards AI companies and their employees are becoming more common.

Although this latest survey does show that there is some support for data center creation, the fact that the opposition is in the majority suggests that any data center projects that haven’t already been delayed or postponed are likely to face increasingly terse pushback that could derail their eventual development entirely.

Considering this survey was from November 2025, too, there has been further evidence of pushback against hyperscalers in recent months.

Who benefits?

This latest survey was commissioned by real estate agent services company, Redfin, which highlighted how it had heard from frustrated homeowners about data center construction in their local areas. Citing one realtor operating in Prince George’s County, MD, they said there were concerns from residents that county officials were trading long-term community quality of life for projects that don’t directly benefit the people who live there.

That’s a core component of many people’s misgivings with AI in general. Executives aren’t increasing their returns because of it, and companies are finding it hasn’t boosted productivity much either. It’s also becoming ever more expensive to run. Although there are outliers, the companies appearing to benefit the most from AI are the companies developing it, although they aren’t making anything close to a profit, aside from the chipmaking industry itself.

Even the hyperscalers like Oracle, which have received hundreds of billions of dollars worth of compute orders since the large-scale AI buildout began in 2025, are heavily reliant on AI developers like OpenAI paying their bills. Considering OpenAI specifically is struggling to make the kind of money that would allow it to make good on those orders, the list of beneficiaries of new data center developments could be small.

Huawei expects revenue from its AI processors to reach roughly $12 billion in 2026, up from $7.5 billion last year. The projection, based on orders already received from major Chinese technology firms including Alibaba, ByteDance, and Tencent, would represent at least 60% year-over-year growth and position Huawei as the dominant supplier in a domestic AI chip market that Morgan Stanley estimates could reach $67 billion by 2030. The surge has coincided with Nvidia CEO Jensen Huang confirming that Nvidia's share of the Chinese AI accelerator market has collapsed to zero percent.

These numbers describe a market that has bifurcated with unusual speed. Just 18 months ago, Nvidia supplied the vast majority of AI training and inference silicon used by Chinese cloud providers. Today, Huawei's Ascend 950PR is the primary procurement target for China's largest tech companies, and a training-focused successor named the 950DT is scheduled for Q4 this year.

The impact of DeepSeek V4

This raging demand can be largely attributed to the release of DeepSeek’s V4 LLM in April, which has been optimized specifically for Huawei's Ascend architecture and its CANN software framework rather than for Nvidia's CUDA ecosystem. Huawei engineers, per reporting from South China Morning Post, are said to have collaborated directly with DeepSeek ahead of the model’s launch, and the company confirmed that its full Ascend SuperNode product line was adapted for V4 inference on day one. Alibaba Cloud and Tencent Cloud both deployed V4 services within hours of release.

The 950PR is currently the only Chinese-made AI processor that supports FP8, a compressed numerical format that allows more operations per second and lowers per-query costs. V4 uses a Mixture-of-Experts architecture with up to 1 trillion total parameters but activates only around 37 billion per inference pass. That favors inference-efficient hardware, which plays to the 950PR's strengths over its limitations in raw training throughput.

DeepSeek gave Huawei early optimization access, but didn’t extend the same to Nvidia or AMD. While V4's open weights are released in standard formats compatible with CUDA-based frameworks, DeepSeek's own infrastructure runs on Huawei Ascend silicon. The collaboration has pulled forward procurement timelines across the Chinese cloud industry, and chip prices for the 950PR have reportedly risen by about 20% as a result of the demand.

SMIC capacity and production

Huawei's ability to fill those orders depends on SMIC, China's leading foundry. SMIC manufactures the 950PR on its N+3 process, a 7nm-class node built without EUV lithography. Huawei is said to be targeting production of roughly 750,000 950PR units this year, with full-scale shipments expected in the second half following samples that were shipped to customers in January, but that figure is expected to fall short of demand.

Meanwhile, SMIC has been working on expanding its advanced-node capacity for more than a year. The goal is a five-fold increase over a period of two years that’ll lift 7nm and 5nm production to 100,000 wafers per month and half a million by 2030. In addition, the combined capacity for 22nm and below could rise from 30,000-50,000 wafer starts per month in 2025 to 50,000-60,000 or higher this year. Huawei is adding two dedicated fabrication plants, though ownership structures remain unclear. Once fully operational, those facilities could exceed the current output of comparable lines at SMIC.

Yields remain a thorn in China’s side, with SMIC’s 7nm-class process delivering substantially fewer good dies per wafer than TSMC’s equivalent nodes, and the 950PR is likely to be a much larger chip than a TSMC equivalent. SMIC’s cycle time from wafer start to finished and packaged as an Ascend processor is also a problem, currently sitting at around eight months, according to estimates from JP Morgan. For similar nodes at TSMC, it’s around three months.

Then there’s HBM — Huawei announced in September that it had developed its own HBM chips with up to 1.6 TB/s bandwidth, HiBL 1.0, and HiZQ 2.0, in partnership with CXMT, but how quickly CXMT can ramp production of competitive HBM remains an open question.

Nvidia's collapse in China

Huang's admission that “In China, we have now dropped to zero,” came during an interview with the Special Competitive Studies Project's "Memos to the President" podcast. He criticized U.S. export policy as having "already largely backfired," arguing that conceding a market the size of China doesn’t make strategic sense.

The H200, which Nvidia received U.S. licenses to sell to China earlier this year, hasn’t shipped a single unit despite receiving orders. Contradictory regulatory requirements from Washington and Beijing created a stalemate at customs: U.S. regulators require that H200 chips ordered by Chinese customers be used only inside China, while Beijing has instructed domestic technology companies to limit Nvidia hardware to overseas operations.

Nvidia confirmed in its FY2026 10-K filing that it’s "effectively foreclosed from competing in China's data center computing market" and is not assuming any data center compute revenue from the region in its current outlook. Bernstein analysts estimated earlier this year that Nvidia’s share of the China AI GPU market could fall to roughly 8% in the coming years, down from 66% in 2024, both due to U.S. restrictions and because domestic vendors are being pushed to cover up to 80% of demand from domestic sources. TrendForce projected in December that China's high-end AI chip market would grow by more than 60% in 2026, with domestic suppliers capturing about half of the total.

950PR performance

The 950PR performs somewhere in between Nvidia’s H100 and H200, and outperforms the restricted H20 by an estimated factor of 2.8 times, but trails the H200 in both compute and memory bandwidth. That 2.8 figure can’t be verified, however, since Hopper-era hardware doesn’t support FP4 natively.

Huawei compensates by linking large numbers of processors via optical interconnects. Its CloudMatrix 384 system combines twelve racks of Ascend modules into a 384-processor fabric delivering roughly 300 PFLOPS, though at nearly four times the power draw of Nvidia's comparable GB200-based configurations.

The 950PR is primarily an inference chip, though; the training-focused 950DT, expected in Q4, is designed for deep learning workloads and could narrow the gap with Nvidia's Hopper generation for model training tasks. Until it ships, Chinese firms that need to train large foundation models domestically face constraints that inference silicon can’t fully solve.

As for Huawei's CANN software ecosystem, it’s now thought to have more than four million developers, but it remains far smaller than Nvidia's CUDA install base. Whether CANN can attract enough third-party development to become self-sustaining remains to be seen. For now, commercial momentum is running in Huawei's favor inside China, driven by the simple absence of alternatives.

Google, Amazon, Microsoft, and Meta plan to spend a combined $725 billion on capital expenditure in 2026, a 77% increase over last year's record $410 billion, according to first-quarter earnings reports compiled by the Financial Times.

Google led with 63% cloud revenue growth and an 81% jump in net income to $62.6 billion, while Meta's stock dropped 6% after hours despite a 33% revenue increase, punished by investors for adding $10 billion to its spending forecast and offering no firm timeline on new AI models.

But in the earnings calls, at least two of the four companies explicitly blamed rising memory chip prices for pushing budgets higher, confirming what market data and industry executives have been warning about for months.

Memory costs inside the capex

Microsoft’s CFO, Amy Hood, told investors that rising prices for memory chips and other components accounted for $25 billion of the company's record capex budget. Microsoft set its 2026 spending at $190 billion, far above the $152 billion average analyst forecast. Hood warned that even with the additional investment, Microsoft expects to remain capacity-constrained on GPUs, CPUs, and storage through at least 2026.

Meta cited the same, with the company raising its full-year capex range to $125 billion to $145 billion, up from a prior ceiling of $135 billion. In its earnings release, Meta attributed the increase to "higher component pricing this year, particularly memory," alongside rising costs for land, power, and skilled workers needed to build data centers that now consume 70% of the world's memory output.

The timing of all this is hardly coincidental, with TrendForce having reported DRAM contract prices rising roughly 95% quarter over quarter in Q1 2026, with a further 58% to 63% increase projected for Q2. NAND is following a similar trajectory, with Q2 contract prices expected to climb 70% to 75%. Server DRAM and high-density DDR5 RDIMMs are absorbing the bulk of production capacity, and all NAND output for 2026 is already committed, according to Phison CEO Khein-Seng Pua.

Hood's $25 billion, therefore, helps to put a dollar value on what has previously been an abstract concern: If one company's memory cost inflation alone exceeds the entire annual capex of most semiconductor firms, the pressure on consumer DRAM and NAND supply becomes much easier to quantify.

Google Cloud's contract backlog

Meta and Microsoft aside, Google’s Cloud revenue hit $20 billion in the same quarter, growing 63% year over year, outpacing both Amazon Web Services ($37.6 billion, up $8.3 billion) and Microsoft's Azure-driven cloud segment ($34.7 billion, up $7.9 billion).

Google's cloud contract backlog reached $460 billion, roughly double the $240 billion reported at the end of Q4 2025. Amazon reported $364 billion in its own pipeline, which will expand further after a recent $100 billion computing contract with Anthropic over the next decade. Microsoft's commercial remaining performance obligations hit $625 billion, up 110% year over year.

Cloud boss Thomas Kurian attributed Google's growth to its strategy of building custom AI chips, foundation models, and products in-house, telling the Financial Times that this gives the company a cost and research advantage over competitors that have struggled to develop their own chips and frontier models. Google's 7th-gen Ironwood TPU, which packs 192 GB of HBM3E per chip with 7.37 TB/s bandwidth in pods of up to 9,216 chips, is central to that strategy, and Anthropic has committed to access up to one million of them. Google recently unveiled its 8th-gen TPUs, which are split into two distinct variants for training and inference.

Alphabet raised its capex guidance to between $180 billion and $190 billion, up $5 billion from its previous guidance of $175 billion. CFO Anat Ashkenazi said he expects capex to “significantly increase” in 2027, causing shares to rise by some 7% after hours. It’s worth noting that $37.7 billion of Alphabet’s net income of $62.6 billion came from unrealized gains on non-marketable equity securities, primarily the company's Anthropic stake, according to the earnings release filed with the SEC. Strip that out, and operating performance was still strong, with a 36.1% operating margin, but the total net income number overstates recurring profitability.

Custom silicon and the GPU question

These capex figures reflect more than GPU purchases, because each hyperscaler is now deploying or developing custom accelerators to reduce dependence on Nvidia for inference-based workloads.

Amazon's Trainium3, built on a 3nm process with 144 GB of HBM3E and roughly 4.9 TB/s of bandwidth, is what CEO Andy Jassy described as "nearly fully subscribed" for 2026, and Meta has announced four generations of its MTIA inference chip, all fabbed at TSMC alongside Broadcom, even as it signed GPU deals worth roughly $110 billion combined with AMD and Nvidia. Meanwhile,. Microsoft's Maia 200 is deploying in U.S. Central data centers.

This pattern is likely to extend beyond accelerators as CPU demand for agentic AI workloads drives a parallel supply crunch with CPU lead times currently stretching to six months. Intel has reported billions in unmet Xeon demand, and Arm CEO Rene Haas has stated that agentic workloads require roughly 120 million CPU cores per gigawatt of data center capacity, four times what traditional AI training clusters need. Per Intel CFO David Zinsner, data center CPU-to-GPU ratios have already moved from 1:8 to 1:4, with further convergence expected to reach or go beyond parity.

Despite record spending, all four companies have acknowledged supply constraints that additional capital alone can’t resolve. Nvidia has booked an estimated 800,000 to 850,000 wafers of TSMC's CoWoS advanced packaging capacity for 2026, consuming over half of the total output and leaving AMD, Broadcom, and Google's TPU program competing for the remainder. CoWoS remains oversubscribed through at least mid-2026, and TSMC's U.S. packaging fabs aren’t expected to reach volume until 2028.

Power infrastructure is another bottleneck, with large power transformer lead times extending to roughly 128 weeks, and the IEA estimating that approximately 20% of planned global data center projects could be at risk of grid-related delays. TrendForce recently downgraded its full-year server shipment growth forecast from 20% to 13% because power management ICs and baseboard management controllers needed to assemble complete servers are stretching to 35- to 40-week lead times. Samsung's planned closure of its S7 eight-inch wafer fab in Korea will tighten PMIC supply further.

‘The bear thesis is garbage’

Meta's stock slipped by 6% after-hours following the earnings, erasing roughly $113 billion in market value. That drop reflected both the $10 billion capex increase and CEO Mark Zuckerberg's lack of a firm schedule for releasing improved AI models to follow the recently launched Muse Spark. Dec Mullarkey, managing director of SLC Management, told the FT that investors are concerned about whether Meta's historically capital-light business is becoming far more capital-intensive.

"The bear thesis is garbage," countered Brent Thill, an analyst at Jefferies, arguing that revenue growth across the sector justifies the spending. Zuckerberg offered little to settle the debate. Asked about Meta's AI agent development, he told investors he cared more about quality than deadlines, adding that most AI agents available today are not good enough for everyday users.

Amazon kept its $200 billion capex plan unchanged, and Microsoft CEO Satya Nadella said ending his company's exclusive contract with OpenAI was beneficial, claiming royalty-free access to OpenAI's frontier models and IP through 2032.

Earlier this month, it was reported that almost 80,000 workers were laid off in the first quarter of 2026, with companies pinning the blame on the rise of artificial intelligence.

Whether through improved task efficiency or cost savings through automation, deployment of AI within the workforce is supposed to be the economically smart decision — even if it didn't necessarily turn out to be true. But even that story may be hard to tell now, as Nvidia executive Bryan Catanzaro recently commented that, within his team, AI compute power is more expensive than actual workers.

While Catanzaro's team is involved in making foundation models for Nvidia, AI usage is increasing among workers, with a reported 50% of U.S. employees using AI in some form, according to data released in mid-April. Several weeks ago, Uber's CTO revealed he had exhausted the company's annual AI budget in just a few weeks. If AI usage costs continue to rise, then those costs must be accounted for.

If the most useful AI models become too expensive without generating a return in productivity, their use in workplaces could fall dramatically, as token costs begin to pile up.

Hey big spender

If you asked Nvidia CEO Jensen Huang how much companies should spend on AI, his answer would probably be at least 50% of what you're paying your workers. He famously said in March that if an Nvidia engineer who's paid $500,000 a year weren't spending at least $250,000 on AI tokens over that same year, he'd be "alarmed."

In an interview with Axios, Nvidia's VP of Applied Deep Learning, Bryan Catanzaro, said that within his team, "the cost of compute is far beyond the costs of the employees." A quick look at an example of the enormity of these costs can be found by looking at available vacancies within the Deep Learning team. One such vacancy for a Senior Software Engineer puts the salary band between $192,000 - $243,000 per-year, which means that employees within that team are racking up high compute costs.

It's important to note that not every employee in the tech industry will be using AI to the degree that Nvidia employees are, especially those working within the Deep Learning team. Therefore, you cannot reasonably equate their usage of AI models and costs with those of the average worker.

However, within the context of other contemporary tech firms, they are also finding AI spending increasing in 2026. A study in February showed over 80% of companies using AI showed no productivity benefit, while a study from the Harvard Business Review shows AI use is increasing worker burnout rates.

Uber's CTO said that the company used its annual AI budget in just a few weeks, and the CEO of GetSwan shared that the company spent over $113,000 on AI with a four-person team in just one month. Recently, Anthropic just doubled the expected price tag for individual developers to spend on tokens, from $6 per active day to $13. That equates to around $200 per month per developer. Only its highest-tier subscription would cover that.

Tokenized tolls

However, as AI models get larger and more complex, the hardware required to deploy and use the models does too; this also increases the cost per million tokens served.

Microsoft just announced that it was moving Copilot on GitHub from request-based billing to usage-based billing. In short, that means longer prompts will cost developers more, and longer responses from GitHub will too. Therefore, AI hallucinations go from being an annoyance to having an impact on overall operational costs.

Anthropic's much-hyped and still-internal Mythos model is reportedly several times more costly per million tokens than Claude Opus 4.7, or even the newer Claude Capybara.

Agentic AI is also raising problems for AI companies, with tools like OpenClaw running constant AI requests, leading to enormous token usage and running up bills that companies might not anticipate.

Scaling up user numbers is one way some AI companies are hoping to fix the problem. OpenAI believes it will lose upwards of 35 million $20 a month subscribers in 2026, but will somehow replace them with 109 million new customers paying the $8 a month ChatGPT Go subscription instead, according to The Information.

Others are trialing limiting availability. Anthropic ran a test recently where some of its premier models weren't available to Pro subscribers for a limited period. Business Insider suggests data center capacity limits could cause AI companies to restrict model or even service access in some cases, too.

Investors are starting to look for a return on their investments, and that will mean more restrictive, more costly AI for the companies and individuals using it. With AI productivity gains difficult to find, it may be that before long, companies start hiring back human workers for their versatility, efficiency, and cost-effectiveness.

Meta signed a multibillion-dollar, multi-year deal with Amazon Web Services last week to deploy tens of millions of Graviton5 CPU cores across AWS data centers, making Meta one of the five largest Graviton customers worldwide. The deal focuses explicitly on CPU-intensive agentic AI workloads, not GPU training, with Amazon CEO Andy Jassy saying in a post accompanying the announcement that agentic AI is “becoming almost as big a CPU story as a GPU story.”

Meta already has GPU and accelerator contracts worth hundreds of billions across Nvidia, AMD, Broadcom, Google, CoreWeave, and Nebius, and it went to AWS specifically for general-purpose CPUs. Santosh Janardhan, Meta's head of infrastructure, said in the joint announcement that "diversifying our compute sources is a strategic imperative," and that Graviton allows the company to "run the CPU-intensive workloads behind agentic AI with the performance and efficiency we need at our scale."

Graviton5, which AWS unveiled at re: Invent in December, packs 192 Arm Neoverse V3 cores on a 3nm process with roughly 180 MB of L3 cache, a fivefold increase over Graviton4. AWS claims a 25% performance lift over its predecessor and 33% lower inter-core latency. AWS vice president Nafea Bshara confirmed that the contract runs for at least three years and that the majority of capacity will be deployed in the U.S.

The CPU-to-GPU ratio

The meteoric rise of agentic AI is driving notable shifts in CPU-to-GPU ratios. While training LLMs relies on large deployments of GPUs, agentic inference is fundamentally different, involving processes like branching control flow, tool invocation, sandbox execution, validation loops, and orchestration across many concurrent sub-agents. All that work falls on CPUs.

In its recent earnings call, Intel’s CFO David Zinsner said that the ratios of CPUs to GPUs in data centers have already moved from 1:8 to 1:4, adding that as workloads continue migrating towards inference and agentic AI, ratios could converge to 1:1 or even tilt further in favor of CPUs. “As you think about the growth rate now going forward, it’s [CPU demand] going to become a significant part of the AI [total addressable market],” Zinsner said.

Arm has also quantified the rising demand for agentic AI in terms of core counts. At the company’s Arm Everywhere event in March, Arm launched its first in-house silicon product, the 136-core AGI CPU, with Meta as lead partner and customer. Arm CEO Rene Haas told the audience that a typical AI data center today requires around 30 million CPU cores per gigawatt of capacity. With agentic workloads, however, that figure rises to roughly 120 million cores per gigawatt, a fourfold increase driven by agents that run continuously, spawn sub-agents, and generate queries at more than 15 times the rate of human chatbot users.

Meanwhile, AMD CEO Lisa Su said at the Morgan Stanley TMT Conference in March that "we're seeing a significant CPU demand, frankly, as a result of the inference demand picking up." She added that "the CPU portion of the business has actually far exceeded my expectations in terms of demand."

Supply constraints and rising lead times

The surge in CPU demand is running into a supply chain that planned for a GPU-dominated world, leading to server CPU lead times stretching to roughly six months, up from about two weeks before the agentic demand spike.

Intel acknowledged on its Q1 earnings call that unmet Xeon demand "starts with a B," referring to billions of dollars in lost revenue, with CEO Lip-Bu Tan saying that “In recent months, we have seen clear signs that the CPU is reinserting itself as the indispensable foundation of the AI era." Revenue would have been higher had Intel been able to produce more chips, the company said: Q1 data center and AI revenue came in at $5.05 billion, up 22% year-over-year.

Server CPU prices have climbed 10% to 20% since March, with analysts expecting a further 8% to 10% increase in the second half of the year. Intel raised prices in both February and March, with a third increase reportedly planned for May, bringing the cumulative hike to roughly 30% above 2025 levels. AMD’s Lisa Su told the Morgan Stanley audience that AMD's own customers described the demand as something that "was perhaps… under-forecasted," adding: "We are in the process of catching up."

The bottleneck extends well beyond CPUs themselves, however, with TrendForce downgrading its full-year server shipment growth forecast from 20% to 13%, per reporting from The Register, because power management ICs and baseboard management controllers needed to assemble complete servers are stretching to 35- to 40-week lead times.

Foundries are prioritizing higher-margin AI-specific chips, squeezing capacity for the mature-node components that general-purpose servers require. Samsung's planned closure of its S7 eight-inch wafer fab in Korea will tighten PMIC supply further. Even with all the GPUs and HBM in the world, you can’t ship a rack without the host CPUs, PMICs, and BMCs.

Compute diversification

In response to this, Meta is seemingly attempting to spread its CPU procurement across every available source. In addition to the Graviton5 deal, Meta co-developed the Arm AGI CPU announced in March and plans to deploy it alongside its Broadcom-built MTIA inference accelerators, and the company has struck a $100 billion deal with AMD that includes EPYC server CPUs and Instinct GPUs. Nvidia also announced that Meta will deploy standalone Grace CPUs in production, with Vera to follow. Intel and Google separately announced a multi-year Xeon collaboration in early April, further demonstrating how x86 supply is being locked up through long-term agreements across the industry.

Nvidia's decision to launch its 88-core Vera CPU as a standalone product, separate from its GPU systems, reflects the same dynamic, with Jensen Huang saying that he expects Vera to become a multibillion-dollar business at GTC in March. This, in addition to Arm breaking 35 years of pure IP-licensing precedent to ship finished silicon, and Intel redirecting wafer capacity to Xeon, shows that all the major players are either manufacturing or securing long-term supply of CPUs for agentic workloads.

In terms of infrastructure spending, CreditSights projects that the top five hyperscalers will spend roughly $750 billion on capex in 2026, up around 67% year-over-year. Amazon alone has guided to $200 billion, and Meta has set a range of $115 to $135 billion. Most of that is naturally destined for AI, with every gigawatt of agentic capacity requiring four times the CPU cores of traditional AI training clusters.

Meta's Graviton deal is a sign, by the company spending more aggressively on AI infrastructure than almost anyone else, that its own supply can’t deliver enough general-purpose compute to keep pace.

Microsoft and OpenAI have once again renegotiated the terms of their deal with one another, but it might be what's best for both of them. OpenAI and Microsoft have announced an end to their exclusive arrangement, and a re-jigging of how they handle model oversight, revenue sharing, and cloud deployments. Microsoft will no longer pay OpenAI for what it makes from Copilot, but OpenAI no longer has to exclusively use Azure servers for ChatGPT, opening it up for further deals with other cloud service providers.

What this means for the ever-nebulous AGI clause that both companies were so keen to retain access to and control over, if and when it materializes, remains to be seen. It's an intriguing move that leaves the immediate future of both companies' AI efforts uncertain, but perhaps it's better than Microsoft's legal department firing all barrels at OpenAI over its recent deal with Amazon.

Where's the ROI?

One of the biggest questions of the AI industry over the past year and a half has been the source of profit. Not the infrastructure investment, or the circular deals and token IOUs, but the real profit. For the investors who pumped tens of billions of dollars into OpenAI, Anthropic, and xAI, and for the shareholders who ballooned Microsoft, Google, and Meta's stock prices off the back of these mega deals and unprecedented investment plans.

Microsoft CEO Satya Nadella hinted at this in January, when he said at the World Economic Forum that AI companies needed to find a clear use for the technology or risk losing the "social permission" to continue the work.

That seems to be more of a pressing issue for Microsoft by April, when it announced that Copilot use on GitHub would move to token-based billing — that is, charging users for the amount of tokens they use, rather than on a per-request basis. No longer would shorter requests with shorter responses cost as much as longer, more in-depth queries. From June, this will result in users paying more when Copilot is verbose in its responses, or when it has to analyze more data before making its suggestions.

Microsoft is already doing that with Azure agents, and it's also set to raise the price of Microsoft 365 with its Copilot integration by several dollars a month for most tiers.

According to internal documents reportedly shared with journalist Ed Zitron, this move came because Microsoft had faced a more-than-doubling of its Copilot-related costs from January this year. He also claims Microsoft will take further steps to tighten controls and increase earnings from individual AI users, including reducing rate limits and forcing users onto different models, which could more than double costs.

Things aren't much better at OpenAI, either. It was projected in January to be on track to run out of money entirely by the end of 2027, and despite announcements of enormous investments in the company, it's projected to burn through tens of billions over the coming years. All while somehow planning to turn a profit by the end of the decade, but to manage that, it would need to earn hundreds of billions of dollars a year. OpenAI's annualized revenue run rate is reportedly sitting at roughly $2 billion per month, or $24 billion a year.

OpenAI also performed several major pivots and navigational shifts in recent months. We learned about its chip manufacturing ambitions in February, it announced it was building a GitHub competitor in March, the company warned that it would shutter the Sora text-to-video generation tool in April, and it bought a podcast for over $100 million that same month.

Even OpenAI's own financial officer has said she doesn't see how OpenAI can afford its own promised infrastructure spending, as it misses key revenue targets in 2026, according to a new WSJ report.

It's very hard to see how any of this takes OpenAI from a heavy-loss-making company to one that's incredibly profitable in just a few years.

Don't drop the bag

OpenAI was under pressure in 2025. To secure the promised investment of billions from Japanese investment firm Softbank, it needed to convert to a for-profit company and settle its disagreements with Microsoft. It managed that just in time, finally securing a long-term partnership agreement with Microsoft in the Fall. The Softbank money came rolling in, and just a few months later, the deal was renegotiated again.

But rejigging the deal may be OpenAI's way of securing the next round of funding — the $50 billion promised investment from Amazon in February, which Microsoft was none-too-pleased about. But in doing so, it's lost one of its limited revenue streams from Microsoft's Copilot earnings, and will still have to pay Microsoft 20% of its own limited earnings.

That Amazon investment could come alongside another $60 billion from Nvidia and SoftBank (though not the $100 billion Jensen originally promised), if all goes to plan. That would also value the company at around $730 billion, making a potential IPO incredibly profitable for Altman and anyone else holding OpenAI shares at the time of a public offering.

But even with OpenAI more than halving its compute ambitions from $1.4 trillion in expenditure to $600 billion by 2030, that's still contingent on increasing its own revenue to $280 billion a year by that same date. As of the time of writing, OpenAI hasn't even managed to earn 10% of that, while having close to a billion active users (though crucially, it also missed that milestone by the end of 2025), and it is losing mindshare to competitors like Anthropic.

Regardless, OpenAI seems keen to push forward with its IPO plans. At this stage, that may be the only real avenue left for it to get anywhere close to its ambitious goals. Even with shifting goalposts, the timeline for its profitability is shrinking rapidly, and it still hasn't made a clear path toward it.

Google announced its eighth-generation Tensor Processing Units at Cloud Next on April 22, shipping two distinct chip designs for the first time in the TPU program's decade-long history. The two chips — TPU 8t and TPU 8i — are intended for use in different workloads. TPU 8t targets large-scale model training, while TPU 8i is built for low-latency inference and reasoning workloads.

The split also extends to the supply chain, with MediaTek having joined Broadcom as a silicon design partner for the eighth-gen program back in December, ending Broadcom’s exclusive role in TPU development since 2015. Both chips are fabricated on TSMC's N3 process family with HBM3E memory and will be available to Google Cloud customers later this year.

Optionality for customers

In terms of raw specs, TPU 8 doesn’t close the gap with Nvidia or AMD. According to Google’s own technical deep dive, the TPU 8t delivers 12.6 FP4 PFLOPs with 216 GB of HBM3e running at 6,528 GB/s, while TPU 8i offers 10.1 FP4 PFLOPs, 288 GB of HBM3e at 8,601 GB/s, and 384 MB of on-chip SRAM. In comparison, Nvidia's Vera Rubin R200 is rated at 35 FP4 PFLOPs for training with 288GB of HBM4 at 22 TB/s, and AMD's MI455X reaches 40 FP4 PFLOPs with 432GB of HBM4. That makes the gap roughly 3:1 in raw compute per-socket.

Then there’s the choice of HBM3E over HBM4, which appears to be a deliberate cost and yield trade-off. TPU 8t carries 12.5% more memory capacity than the previous-gen Ironwood TPU, but delivers 11.5% less bandwidth, running slower memory to improve yield and bring down cost per chip per analysis from Next Platform. This is an odd strategy on the face of it, but it seems that Google, rather than trying to take on Nvidia in terms of raw performance, is creating options for external customers that want alternatives.

A TPU 8t superpod packs 9,600 chips into a single cluster with two petabytes of shared HBM, connected by a proprietary inter-chip interconnect running at double the previous generation's bandwidth. Google claims 121 FP4 ExaFLOPs from a single superpod, with the new Virgo Network fabric tying up to 134,000 TPU 8t chips into a single non-blocking data center fabric with 47 PB/s of bisection bandwidth, extending past 1 million chips across multiple sites.

So, yes, while individual Nvidia GPUs are faster, Google holds an advantage with its pod-level throughput at that mass scale; training workloads consume thousands of accelerators, not one, and Nvidia’s current-gen GPUs top out at 576 accelerators in a single NVLink deployment.

Interestingly, Google also announced Vera Rubin NVL72 instances running over the same Virgo Network fabric at Cloud Next, so TPUs are clearly not intended to act as a direct replacement for Nvidia silicon.

TPU 8i architecture

The TPU 8i’s architecture is a radical departure from the norm for Google, with TPU 8i abandoning the 3D Torus interconnect that has been inside TPU pods since the second generation. Instead, it’s replaced with a topology that Google calls “Boardfly,” inspired by the 2008 Kim/Dally Dragonfly paper. Boardfly is a three-tier hierarchy: four-chip building blocks connected into 32-chip groups by copper cabling, with 36 groups linked by optical circuit switches into a pod of up to 1,024 active chips.

In a 1,024-chip 3D Torus configuration, the worst-case packet path traverses 16 hops. Boardfly cuts that to seven, a 56% reduction in network diameter that directly benefits mixture-of-experts (MoE) models, where token routing requires frequent all-to-all communication across unpredictable chip pairs.

TPU 8i also replaces the SparseCore embedding accelerators that Google has used since TPU v4 with a new fixed-function block called the Collectives Acceleration Engine (CAE). The CAE offloads reduction and synchronization operations during autoregressive decoding, cutting on-chip collective latency by up to five times. Combined with the tripled SRAM, which holds more of the KV cache on-chip during long-context inference, Google claims 80% better performance per dollar over Ironwood for large MoE models at low-latency targets.

TPU 8t, meanwhile, retains the 3D Torus at a larger scale and keeps SparseCore for the irregular memory access patterns typical of embedding lookups during training. It introduces native FP4 compute to double MXU throughput at reduced precision, and a new TPUDirect RDMA path that bypasses the host CPU to pull data directly from high-speed managed storage, delivering what Google describes as ten times faster storage access over the previous generation. Both chips now run on Google's Arm-based Axion CPU hosts, replacing x86 for the first time.

Two suppliers instead of one

The MediaTek partnership means that there’s a second silicon design house in the TPU program alongside Broadcom, with MediaTek understood to be handling the design of the TPU 8i inference chip while Broadcom handles the design of the 8t training chip.

TrendForce reported back in December that MediaTek initially booked 20,000 TSMC CoWoS wafers for the program, with allocation potentially scaling to 150,000 by 2027. According to Bank of America analyst Vivek Arya, the dual-sourcing arrangement could reduce per-chip cost by up to 30% compared to solely sourcing from Broadcom, whose role is secured through at least 2031 per an April 6 SEC filing, which also formalized a 3.5 GW TPU capacity commitment from Anthropic starting in 2027. That deal sits on top of the one gigawatt of Anthropic capacity already coming online this year under a separate Google Cloud agreement.

Meanwhile, Meta has signed a separate multi-year, multi-billion-dollar TPU rental agreement, estimated to involve 500,000 to 800,000 TPU chips by 2027 if initial testing meets expectations, and Apple is routing Gemini-powered Siri workloads to Google Cloud on TPU infrastructure, valued at roughly $1 billion per year.

Unauthorized individuals have gained access to Anthropic's cybersecurity-focused AI model, Mythos, a breach that may have exposed a number of Anthropic's proprietary AI models, Bloomberg reports. For a company that markets itself as the responsible, safety- and security-first AI developer, this lapse raises questions about how well Anthropic can protect the data of its customers — and just how good Mythos really is at preventing breaches.

Unfortunately, as capable as any AI model is at finding code bugs that raise security concerns, it can't do much to prevent bugs in third-party provider tools that haven't been vetted by Mythos, nor account for social engineering, which has always been the weakest link in digital security.

They got in through the side door

Anthropic disrupted major institutions with the internal unveiling of Mythos, which it claimed had found thousands of critical exploits in every major browser and operating system. Although there was a lot of marketing hype in the 200+ page mission statement Anthropic released, venerating its own model, some have found success using it to sniff out new bugs. For instance, Mozilla announced that it used Mythos to find and patch over 270 vulnerabilities in the Firefox browser.

Although it has been proven that some older models can find many of the same bugs, they can't do so as quickly, or possibly as well. This new model is genuinely faster at coding and finding vulnerabilities than Claude Opus 4.6, and possibly other models from other developers, too. But it's also good at exploiting those vulnerabilities, which is allegedly why Anthropic limited access to a select number of companies and non-profits.

Because of that, banks and software developers aren't the only parties keen to get an early look at Mythos. A worker at a third-party contractor for Anthropic used their unique access to the company's services to breach Mythos' protected environment and gain access to the model, allegedly using standard internet sleuthing tools used by cybersecurity researchers.

This worker was then able to open up the model to their colleagues, with a small group of unauthorized users now said to have accessed Mythos. Although the group has reportedly not run any cybersecurity-related prompts through Mythos just yet, and has instead only asked it to perform simple tasks like creating websites. This is designed to stop Anthropic catching on to who is using Mythos, thereby making it possible to shut down the group's access.

This all feels familiar

The group that now has access to Mythos was able to gain such privileged permissions by guessing the model's online location based on knowledge of Anthropic's file systems and the naming formats it used for previous models. They garnered this information from a recent hack of an AI feedback recruitment company, Mercor, which is now facing several class action lawsuits for revealing personal information about users. It's also losing major business since the breach, most notably, Meta has paused its contracts with the company.

The irony is that Mercor was hacked via a third-party open source tool called LiteLLM. Where that hack was perpetuated by a group known as TeamPCP, however, the group that targeted Mercor was known as Lapsus$. While it used the LiteLLM compromise to infiltrate Mercor, it had targeted the AI recruitment company deliberately.

Allegedly, around 4TB of data was stolen in the breach. That included sensitive information of its recruitment candidates, including their profiles and personal information. However, Mercor also handles data from model companies, which is why some are reconsidering their contracts with Mercor. Model data is some of the most sensitive information in the world, worth billions. Anthropic's Mythos? Perhaps even more so.

But neither company could protect it.

Anthropic was breached because of a breach at Mercor. This was breached because of a breach at LiteLLM. The layers keep stacking, too, as LiteLLM was allegedly breached because of fake security credentials from a third-party provider of its own, Delve, as TechCrunch reports.

Only as strong as the weakest link

As much as Anthropic's marketing for Mythos might be heavy on the spin and deliberately fearmongering for attention, an AI model that can help make software more secure is a good thing. It's great that Mozilla has fixed hundreds of vulnerabilities, and even though it is possible this could have occurred with other models, if other organizations and developers use Mythos to do the same, that's great too.

But the unauthorized Mythos access and the chain of breaches of third-party tools that enabled it highlight one thing: You are only as secure as the weakest link in your chain. Often with cybersecurity, that's the human element. Social engineering is a crucial attack vector in 2026. Especially as tools like Mythos close more code-based vulnerabilities.

But as agentic AI grows in popularity and capability, more tools are integrated, and people hand over more personal data to AI assistants to automate workflows, the security issues are only compounding. Trusting third parties without oversight can be the downfall of companies worth billions.

Many of the latest AI endeavors are assuming trust throughout the stack of dependencies, anyway. As the Mythos breach shows, that could be a house of cards waiting to tumble.

A bipartisan group of U.S. lawmakers introduced the Multilateral Alignment of Technology Controls on Hardware Act, or MATCH Act, in early April, targeting the sale and servicing of advanced chipmaking equipment to China.

The bill, filed as H.R. 8170 in the House and with a companion in the Senate, would impose country-wide prohibitions on exports of DUV lithography systems to China, designate five Chinese semiconductor firms as restricted entities by statute, and give U.S. allies 150 days to adopt equivalent controls before Washington expands the Foreign Direct Product Rule unilaterally.

Still in the committee stage, the bill, which has drawn broad congressional support, has since been amended to remove a blanket ban on cryogenic etch tools, though core proposals remain intact.

Two mechanisms of restriction

The MATCH Act builds its controls on two independent mechanisms. The first is a country-wide prohibition on exports of specific "chokepoint" manufacturing equipment to any destination in China, regardless of end user. Named in the original Bill were DUV immersion lithography systems and cryogenic etch tools, but a recent amendment dropped the latter entirely, leaving DUV lithography tools as the sole country-wide prohibition.

That covers ASML’s NXT:2000i-class scanners and Nikon’s NSR-S631E, which are widely used by Chinese chipmaker SMIC in its 7nm production lines. China has no domestic equivalent for volume manufacturing; SMEE’s SSA/800-10W scanner remains unconfirmed in production use.

The second mechanism names five Chinese companies directly in statute: SMIC, CXMT, YMTC, Hua Hong, and Huawei. All of their fabs, facilities, subsidiaries, and affiliates would be classified as “Covered Facilities” and subject to a presumption-of-denial licensing regime extending beyond equipment sales to servicing, spare parts, and technical support for already-installed tools.

While the Bureau of Industry and Security’s Entity List currently restricts SMIC (since 2020), Huawei (since 2019), and YMTC (since 2022), it requires Commerce Department officials to evaluate each subsidiary or affiliate on a case-by-case basis and grants the executive branch discretion to approve licenses. Codifying restrictions against these and other Chinese entities into law would eliminate that discretion, meaning that a subsidiary spun off next year or a joint venture created under a different name would be automatically covered.

U.S. Representative Michael Baumgartner (R-WA), who introduced the Bill, says that the legislation closes loopholes that Chinese firms have been exploiting through front companies and third-country routing.

The Chairman of the House Select Committee on Strategic Competition between the United States and the Chinese Communist Party, Representative John Moolenaar (R-MI), co-sponsored the bill alongside Democrats including Representatives Jared Golden (D-ME), John Mannion (D-NY), Josh Riley (D-NY), Maggie Goodlander (D-NH), and Suhas Subramanyam (D-VA).

Meanwhile, the Senate companion was introduced by Foreign Relations Chairman Jim Risch (R-ID), Senator Pete Ricketts (R-NE), and Senator Andy Kim (D-NJ), with Democratic Leader Chuck Schumer joining as a co-sponsor.

150 days for multilateral coordination

MATCH's enforcement mechanism is built around a deadline for multilateral coordination. Within 60 days of enactment, the Departments of Commerce, State, Defense, and Treasury, along with the Office of the Director of National Intelligence, must identify all covered equipment and facilities. Commerce then has 150 days to negotiate equivalent country-wide controls with allied supplier nations, principally the Netherlands and Japan, home to ASML and Tokyo Electron.

If those negotiations fail, the bill directs Commerce to expand the Foreign Direct Product Rule to cover any foreign-manufactured tool that incorporates U.S.-origin software, technology, or components. In practice, this would function as a near-zero de minimis threshold (meaning that goods would be liable for customs duties and formal entry procedures), since virtually every advanced chipmaking tool in the world relies on some U.S.-origin intellectual property in its EDA software, metrology subsystems, or process control algorithms.

The Netherlands and Japan have so far declined to comment publicly on the bill, but both countries tightened their own export controls in 2023 and 2024 following U.S. pressure. Neither, however, has adopted restrictions as broad as what MATCH proposes.

The FDPR expansion could prove to be a sticking point, which, if enacted, would give the U.S. the ability to block sales of equipment manufactured entirely outside the United States, by non-U.S. companies, to non-U.S. customers, based on embedded U.S. technology. That extraterritorial reach has historically been a point of tension with allied governments, and the explicit statutory deadline could force a confrontation that the executive branch has so far managed to defer through diplomatic channels.

Interestingly, the bill’s sponsors circulated a revised draft on April 16th that removes two provisions that had drawn significant opposition. The country-wide ban on cryogenic etch equipment, dominated by Lam Research and Tokyo Electron, was dropped entirely, while the automatic presumption of denial on licenses to service equipment installed inside Covered Facilities was also softened — however, this revision hasn’t yet appeared on Congress.gov.

That cryogenic etch concession is narrower than it appears, however, given that existing BIS rules already restrict cryogenic etch tools when destined for advanced-node fabs, defined as sub-16/14nm logic, sub-18nm DRAM, and 128-layer-and-above NAND. The DUV immersion lithography restrictions survived in full, as did everything related to Covered Facilities, the 150-day alignment deadline, and the FDPR expansion authority. The five named Chinese firms also remain in the bill without modification.

Executive discretion vs. statutory mandate

The biggest change with the MATCH Act is the transfer of authority from the executive branch to Congress, not that Congress’s authority appears to matter to the incumbent administration.

Since October 2022, U.S. semiconductor export controls have been administered entirely through BIS rulemakings under the Export Control Reform Act of 2018. Those rules can be tightened or loosened by any administration without congressional approval, and each new rule requires a fresh assessment of each entity, each subsidiary, each end use.

MATCH would lock the five named firms and the DUV lithography machine ban into statute, meaning any future relaxation would require an act of Congress to implement. For Applied Materials, Lam Research, and KLA, which booked a combined $19 billion in China revenue in 2025 despite direct U.S.-to-China shipments falling 34%, the bill introduces a layer of permanence that executive-branch rulemaking doesn’t.

ASML, which drew around 30% of its total 2025 revenue from China, faces a different challenge because the servicing restrictions in the original bill threatened the company's maintenance contracts for scanners already operating in Chinese fabs. While the April 16th revision eased that pressure, the FDPR expansion authority could eventually reach tools manufactured at ASML's Veldhoven headquarters if the Netherlands doesn’t adopt matching controls within the 150-day window.

At present, the Bill’s path through Congress remains uncertain; HR 8170 sits in House Foreign Affairs, and the Senate version has been referred to Banking and Foreign Relations. No committee has yet scheduled a markup, and equipment makers that derive 30% or more of their revenue from China are bound to lobby hard against it. But the bipartisan coalition behind the Bill is difficult to dismiss, and current trade tensions between the U.S. and China have narrowed the political runway for opposing new restrictions.

Applied Materials, Lam Research, and KLA booked a combined $19 billion in China revenue across their fiscal 2025 reporting periods, according to a recent Nikkei Asia analysis of corporate filings, even as direct U.S.-to-China tool shipments fell 34% to roughly $2 billion, the lowest figure since 2017.

The gap moved through Singapore and Malaysia, where all three firms have spent years building out manufacturing capacity. At the same time, every major Chinese wafer-fab-equipment vendor posted record 2025 revenues, but gross margins contracted across the board as domestic vendors competed on price for fab share previously held by foreign suppliers.

Domestic vendor financials

Naura Technology Group, China's broadest equipment supplier by product line, reported first-nine-months 2025 revenue of 27.14 billion yuan, up from 6.05 billion yuan ($887 million) for all of 2020, per Nikkei's analysis of company filings. Gross margin slipped 2.8 percentage points year over year to 41.4%, and net margin contracted by nearly four points.

AMEC delivered full-year 2025 revenue of 12.4 billion yuan, up 36.6% from 2024, but gross margin fell 1.9 points to 39.2%. In Q3 alone, AMEC's margin dropped 5.8 points. Piotech, a thin-film deposition specialist, nearly doubled revenue to 4.2 billion yuan in the first nine months, but first-half net income fell 27% as the company absorbed high costs from new products still in customer validation, per its interim filing.

ACM Research, the U.S.-listed company that conducts most of its operations through its Shanghai subsidiary, posted 2025 revenue of $901 million, a 15% increase, but gross margin fell 5.7 points to 44.4%, and operating margin collapsed from 19.3% to 12.1%. Q4 gross margin of 41% landed below the company's own 42% to 48% long-term target band.

"While leading domestic equipment companies are still posting strong revenue growth, there are indications that their margin performance is deteriorating," Charles Shi, a veteran semiconductor analyst with Needham & Co., told Nikkei Asia. Shi attributed the squeeze to domestic vendors undercutting each other for business at Chinese fabs that were previously served by foreign suppliers.

U.S. vendor China revenue

As for the revenue figures from U.S. equipment makers, it’s clear that export controls haven’t completely severed commercial relationships with China.

Applied Materials booked $8.53 billion of China revenue in fiscal 2025, or 30% of total sales, down from 37% the prior year, according to the company's Q4 FY2025 earnings release. CFO Brice Hill told analysts on the Q4 call that the cumulative impact of U.S. export restrictions was equivalent to roughly 10% of the China market in fiscal 2024 and more than double that in fiscal 2025. Meanwhile, Lam Research reported $6.21 billion from China for 34% of total revenue, down from 42%, while KLA reported $4.01 billion, or 33%, down from 43%.

These revenue figures, however, are largely attributable to infrastructure. Lam Research’s Batu Kawan campus in Penang, for example, is its largest manufacturing site globally at 800,000, while Applied Materials opened a $450 million plant in Singapore in early 2024 and has committed to doubling its local manufacturing and R&D headcount under a plan it calls Singapore 2030.

KLA completed the first phase of a $200 million Singapore expansion in October 2024, with a second phase underway that will bring the site to 420,000 square feet and add roughly 400 jobs, expected to be completed this year. Chinese customs recorded $5.7 billion of Singapore-origin chipmaking equipment in 2025, up more than 17%, and $3.4 billion from Malaysia, more than double the 2024 figure, according to Nikkei's analysis.

ASML's China share of net system sales fell from 41% in 2024 to 33% in 2025, though total China revenue as a share of all sales, including service, came in at 29.1%, per Nikkei's figures. ASML in January projected that the recent cycle was abnormally high and estimated China would drop to around 20% of ASML's 2026 revenue. Tokyo Electron, the most China-exposed of the large tool makers, drew

Tokyo Electron, the most China-exposed of the large tool makers, drew more than 40% of its fiscal 2025 revenue from Chinese customers, according to Nikkei's analysis. A TrendForce report from December cited TEL finance chief Hiroshi Kawamoto as expecting China's share to fall to around 35% in the current fiscal year, with uncertainty over whether it would drop below 30% the year after.

Over the five years from 2020 through 2025, China's accumulated chip tool imports from Japan exceeded $42 billion, with Netherlands-origin shipments adding roughly $35 billion, per Nikkei's customs data analysis.

Equipment localization clears 30%

Beijing is pushing hard to localize more chipmaking, but despite hundreds of billions spent and significant progress made, China is still around a decade behind the West. Domestic tools accounted for roughly 35% of chipmaking equipment in use at Chinese fabs in 2025, up from 25% in 2024 and above the government's 30% target for that year, according to DigiTimes.

It’s understood that the Chinese government is unofficially requiring chipmakers to source at least 50% domestic equipment when adding new capacity, with YMTC’s third Wuhan fab already having cleared that threshold.

Gains are naturally concentrating in the mature process tool categories, with Chinese vendors now routinely approaching or exceeding parity in cleaning, etch, deposition, and thermal processing. Lithography is the laggard, representing around 18% domestic share, metrology around 255, and EUV exposure tools at zero. Only ASML, Canon, and Nikon produce commercially viable lithography systems, an area where Chinese suppliers continue to face fundamental technical barriers.

U.S. lawmakers are keen to maintain that barrier, with the recent bipartisan Multilateral Alignment of Technology Controls on Hardware Act, targeting both DUV and the Southeast Asia routing pattern highlighted in Nikkei’s report. The bill adds restrictions on SMIC, CXMT, YMTC, Hua Hong, and Huawei directly into statute rather than relying on Commerce Department entity listings, and imposes country-wide prohibitions on sales and servicing of chokepoint tools into China regardless of end user.

A 150-day clock requires Commerce to secure matching controls from the Netherlands and Japan, failing which the bill authorizes an expanded Foreign Direct Product Rule applied unilaterally. Bernstein analysts called the proposal far stricter than any prior restriction, warning it could make tool maintenance inside Chinese fabs nearly impossible. The bill remains in committee and faces an uncertain path through Congress, as the Netherlands and Japan have not publicly committed to matching its scope.

AI companies have a compute problem. As the usage of artificial intelligence is increasing among working adults in the U.S., computing power has become a precious resource that hyperscalers cannot ignore. To that end, we've seen a significant explosion in the number of planned data center projects throughout the globe. But those efforts are now facing roadblocks from local communities.

Just this week, a small town in Missouri ousted half of its city council for not doing their due diligence in protecting local communities from the harms of AI data center construction, and they're pushing to remove the rest of them, the mayor included. A resident of Claremore, Oklahoma, was arrested in February for speaking too long during a town hall meeting to discuss a data center project. In Virginia, voter support for data centers has collapsed to just 35% from 69% in 2023, halting efforts to build what would have been one of the largest data centers in the country.

Suffice to say, while major data center projects are the darling of tech CEOs and many politicians, the general populace is making its voice heard; through collective action, they are putting the brakes on $10's of billions of dollars of investment and derailing the plans of major corporations. As of the time of writing, half of all planned U.S. data center builds have been delayed.

Making small voices heard

2025's major AI infrastructure announcements carried a measure of inevitability. OpenAI was investing $100 billion here, $300 billion there, and Nvidia's chips were going to consume tens of gigawatts of power the world over. Regardless of all the talk of circular investments surrounding these companies, the projects were going to go ahead, regardless. Politicians fawned over the big numbers and the growth potential these major companies would bring to their local areas.

But while these data center projects might promise temporary construction jobs and investment in local communities, they also bring the potential for water contamination, skyrocketing energy prices, and even air pollution as companies ship in 'illegal' gas turbines just to get the servers up and running.

So, local communities have pushed back in major ways. Where their local politicians would listen, they worked with them to halt these projects in their tracks. In Maine, Reuters reports that lawmakers recently passed a bill that would place a moratorium on new data centers over 20 megawatts in power being constructed until October 2027, giving time to conduct analyses on the construction process and how it might affect local communities and utilities.

The Tulsa City Council ultimately issued a temporary moratorium on data center construction through the end of the year. A San Marcos city council voted in February to reject a rezoning effort that would have cleared the way to build a 200-megawatt data center next to a local power station.

Parks over data centers

Some of the voices calling for these data centers to be built are quite persuasive. Lawmakers argue that the projects can bring in tens of millions of dollars in local tax revenue, which could help unlock laundry lists of long-wished-for projects. Union construction workers are keen to see these multi-year megaprojects go ahead because of the guaranteed long-term work for their members.

Developers are also claiming that fears of water contamination are unfounded and that noise pollution can also be kept to a minimum. Some companies, like Meta, are even bolstering their efforts by announcing small-scale grants for projects near their data centers.

In a rural Brown County village, residents started getting offers of up to $120,000 per acre of land to sell up to a Delaware-based LLC linked with Cloverleaf Infrastructure, a company linked with another data center development in Port Washington, which has also received heavy local pushback. They didn't sell up, though, and Cloverleaf has since pulled out of the project entirely.

In New Brunswick, a 22-acre site was under consideration for a data center project, but following fierce local pushback, the town council modified the proposal to mandate that a park be constructed instead.

Determined opposition

The pushback against these projects has been robust and coordinated, with often sizeable portions of local communities speaking at local events and town halls to voice their concerns. They aren't always successful, but even then, the opposition is fierce and ongoing, with residents showing a real willingness to continue fighting with projects even after construction has started.

A major component of that is political retribution. The town councils and other local political figures who allowed projects to continue will be up for election before long. One resident of Calvert County, whose commissioners didn't vote through a moratorium on data center construction, waved goodbye to them from the microphone, prompting cheers.

“You’re not going [to] be here anymore,” she told them, as the Washington Post reported. “You’re out. You’re gone." With primaries for elections of those positions in June, it may not take long for voter intention to be felt by those currently representing them.

In the most violent examples of anti-AI pushback, OpenAI CEO Sam Altman's home was fire bombed, and a council member in Indianapolis received a threatening note and bullet holes in his home after voting through a data center project.

Part of the public's ire surrounding Artificial Intelligence, and the data centers which support the industry, is that the technology is also becoming a scapegoat for job losses, as OpenAI's Sam Altman warned earlier this month. In the most recent example, the tech industry laid off almost 80,000 workers in the first quarter of 2026, with almost half of the expected positions cut, due to the reported impact of AI.

Despite the wide public feedback, some lawmakers are onside with working hand-in-hand with local communities, ensuring their views are taken into consideration while plans are being made. However, if governments ignore them, the public response could plunge hyperscaler plans into jeopardy.

China’s Yangtze Memory Technologies is expected to start operations at its Phase 3 Wuhan fab late this year as the first leading-edge memory plant built to comply with Beijing's unwritten requirement that new Chinese fabs source at least half their equipment from domestic suppliers.

Three sources familiar with the plans told Reuters that more than 50% of Phase 3's tooling has been sourced inside China, that the company aims to add two more fabs of equivalent scale on top of the Phase 3 plant, and that the latter two are not yet committed to specific dates or locations. Phase 3 alone will reach 50,000 wafers per month by 2027 and 100,000 wafers per month at full capacity, doubling YMTC's current 200,000 wafers per month of combined capacity at its first two Wuhan fabs.

50% Chinese tooling

It was reported in late December that Chinese authorities have begun rejecting state approval for new fab construction unless applicants can prove through procurement tenders that at least half their equipment will be Chinese-made. While this rule isn’t published in any formal regulation, officials have told applicants that 50% is a baseline, not a target, with the long-term objective being exclusively domestic wafer fab rules.

Applications below the threshold are typically rejected, with waivers granted only for advanced production lines where domestic alternatives don’t yet exist, and YMTC’s Phase 3 is now understood to be the first leading-edge memory project that’ll clear that bar. The two follow-on fabs YMTC has now told Reuters it wants to build will need to clear it again, twice, before they can break ground.

3D NAND fits this mandate

It’s obvious why YMTC will be the first to launch a fab with a majority of Chinese tooling: 3D NAND. This scales vertically rather than horizontally, which shifts the manufacturing bottleneck away from lithography (the area where China's domestic toolchain is weakest) and toward high-aspect-ratio etch, deposition, and wafer bonding (where it’s strongest).

Each new generation of 3D NAND adds layers rather than shrinking features so that the same lithography node can support 128, 232, or 300+ layer stacks, provided the etch tools can cleanly cut channel holes through 7-to-10-micron dielectric stacks.

In China, it’s Advanced Micro-Fabrication Equipment (AMEC) that provides these tools. Its Primo HD-RIE dielectric etch platform, launched in 2015, was designed for high-aspect-ratio contact applications and was qualified for 6nm flash production a decade ago. AMEC has been working on 3D NAND etch ever since.

Meanwhile, Naura Technology Group, China's largest chip equipment maker by revenue, is supplying etching tools for chips with more than 300 layers, and is testing its etch tools on SMIC's 7nm logic line after deploying them at 14nm. Naura filed 779 patents in 2025, more than double what it filed in 2020, while AMEC filed 259.

All that aside, YMTC still depends on imported tools for lithography — that’s not ideal, given that U.S. lawmakers are now looking at extending the ban on EUV lithography tools to the older DUV machines that YMTC relies on heavily. In terms of Chinese alternatives, Shanghai Micro Electronics Equipment's SSA800-10W is nominally 28nm-capable, but it’s barely deployed in any production fab, and the Yuliangsheng immersion DUV scanner that SMIC began testing in late 2025 is years from supporting volume manufacturing.

For Phase 3 to clear 50% domestic tooling without leading-edge domestic litho, YMTC has to be substituting deeply elsewhere: in etch, deposition, CMP, photoresist removal, cleaning, and metrology. Analysts estimate that Chinese suppliers have reached roughly 50% self-sufficiency in cleaning and photoresist-removal tools alone.

DRAM and HBM allocation

It’s also understood that part of each new fab's capacity will be dedicated to DRAM rather than NAND, with the proportion contingent on YMTC's progress in qualifying its low-power DRAM samples currently with customers. YMTC has decided to allocate 50% of its Phase 3 capacity specifically to DRAM, with one YMTC supplier telling Nikkei Asia in February that the company "started to develop their own DRAM more than two years ago" and now has "the technological foundation and the market" to scale.

That foundation includes a back-end stack that no other Chinese DRAM contender has matched. Wuhan Xinxin Semiconductor Manufacturing, the foundry subsidiary YMTC controls, began developing HBM packaging capacity using hybrid bonding and other IP from YMTC roughly two years ago, and bought equipment for a monthly capacity of around 3,000 wafers. XMC is also working on its own through-silicon via process technology, though the development stages are not public

When YMTC moves from LPDDR samples to volume DRAM and eventually to HBM stacking, it’ll benefit from having the assembly side already (partly) in-house; CXMT, China’s other HBM contender, still needs to build that infrastructure or buy it from XMC.

Convenient timing

The remarks made to Reuters come less than two weeks after a bipartisan group of U.S. lawmakers introduced the Multilateral Alignment of Technology Controls on Hardware Act.

Introduced in the House of Representatives on April 2nd by Michael Baumgartner with Senate companion legislation expected later in the month, the MATCH Act would impose a country-wide export ban on immersion DUV lithography tools and cryogenic etch systems to China and require allies, including the Netherlands and Japan, to align with U.S. controls within 150 days.

The bill explicitly names YMTC, alongside CXMT, Hua Hong, and Huawei, for additional restrictions beyond the country-wide ban. Bernstein analysts called the proposal "far stricter" than previous restrictions and warned it could effectively cap China's advanced chipmaking capacity at current levels.

If the MATCH Act passes in something close to its current form, the stockpiled foreign tools currently keeping YMTC's first two fabs running become harder to maintain over time, and the case for accelerating Phase 4 and Phase 5 on a domestic foundation will grow stronger, not weaker. The two unannounced fabs are conditional on Phase 3 yields clearing acceptable margins, but the regulatory environment around them is moving in one direction.

Anthropic's Claude Mythos AI model made headlines last week, causing a wave of frenzy in the industry for its purported abilities, which included finding bugs in browsers and operating systems, spawning "Project Glasswing" — which would see Anthropic team up with tech titans to ensure that their products are patched up before Mythos, which is still in preview, gets released into the wild.

While the reports sound extreme, the reality of Claude Mythos's abilities isn't quite so dramatic; it's not a sentient model capable of bringing modern technology to its knees. Following the announcement, Aisle published a paper indicating that other AI models can also deliver similar levels of performance in finding exploits (and patching them) to Mythos. Although there is some suggestion that Mythos is the best AI model for aiding in cybersecurity efforts, it is not by a wide margin.

Researchers put Mythos to the test

AI use in cybersecurity is nothing new. Researchers have been trying to use it as part of defensive and offensive operations since the 1980s, but it became far more viable as a method of detecting threats like malware in the 2000s and 2010s, where the quantity of labeled data became large enough to make a real difference, and that's a trend that's only accelerated since.

But Anthropic has pitched its newest AI model as something different, something dangerous, positioning Mythos as so powerful that it could find zero-day exploits in just about everything, claiming many of these are critical and so dangerous that Anthropic needs to share this AI only with responsible companies. If it can find the bugs, it can help exploit them, is the publicly shared rationale.

The problem for Anthropic is that a bunch of other AI models can do most of the same job as Mythos already.

Aisle's research found that many of the flagship vulnerabilities discovered by Mythos can also be detected by more affordable, open source models like GPT-OSS-120b, which found the OpenBSD Sack analysis vulnerability, Qwen3 32B that found the FreeBSD NFS detection error, and the Kimi K2 (open-weight) model also found all the headline-grabbing flaws.

It's more complicated than that

Aisle's analysis also points out how Anthropic frames AI cybersecurity as a single overarching tool that can act out many stages of vulnerability discovery, verification, exploitation, and patching. In reality, these are all separate steps that have different requirements. Some of these steps can be achieved to a high standard by some of the lighter-weight models Aisle trialed.

Mythos might be very capable, but if it's not that much better than other models, is it really doing anything that different?

"We view the production function for AI cybersecurity as having multiple inputs," the report reads. "Intelligence per token, tokens per dollar, tokens per second, and the security expertise embedded in the scaffold and organization that orchestrates all of it."

Although Aisle admits that Anthropic has maximized the intelligence per token with Mythos, it also argues that other aspects of AI-based cybersecurity are just as important, if not more so in some cases. The research also suggests that Anthropic may not have the best model overall when other models handle other aspects of cybersecurity better.

The research also concludes that while Mythos is performant, smaller AI models can achieve similar results to a good standard, while also being cheaper to run. That means that for some, those cheaper models might make more sense to run than Mythos in cybersecurity contexts.

The inference economy

But Mythos might not be operating at peak capability yet. According to another analysis by the UK's AI Security Institute (AISI), Mythos is the most capable AI model when it comes to its own cybersecurity benchmarks. It doesn't perform dramatically better than other models across all tasks, but when it comes to more complex vulnerability discoveries and exploitations, it pulls ahead of the pack.

A part of this comes from its support for long context lengths, with larger token inputs delivering the best results. In its tests, AISI benchmarked Mythos up to 100 million tokens and found it to be the most capable at that threshold. It even postulates that it could scale further with a greater token budget.

"We expect that performance on our evaluations would continue to improve with more inference compute," AISI's report reads. "We ran the cyber ranges with a 100M token budget; Mythos Preview’s performance continues to scale up to this limit, and we expect performance improvements would continue beyond that."

It doesn't speculate how much better, whether that scaling is linear, or how far it expects the scaling to go in improving effectiveness, but it does suggest more can lead to better.

But even if Mythos is the best, and even if it can be even better with more compute power and more tokens, how much is all this going to cost?

We don't have token costs for Mythos, but considering the second-best model in AISI's tests was Claude Opus 4.6, which is already one of its more expensive models, Mythos is likely to be more expensive than that.

It may be worthwhile to spend big on a single pen-test, but it also raises questions about how economically viable it is to run long-term. How easy would it be to market such a service when Aisle's research suggests you can get most of the way there by spending far less, or even running models locally, as open-weight models get quantized?

Irregular argues that when evaluating an AI model's effectiveness in cybersecurity efforts, it needs to be weighed against the overall token cost. But an expected cost per success is a metric that Irregular suggests needs to be considered. That's where Mythos, if able to be judged more fairly against the competition, might fall down.

Can Anthropic reliably serve Mythos?

As part of its reveal of Mythos, Anthropic gave $100m in usage credits and $4 million open source donations to organizations to help them validate and fix the bugs discovered by Mythos. It also closed ranks and didn't release the model to the public, instead limiting it to a core group of technology companies as part of Project Glasswing.

That's great news. Fixing bugs privately, quietly, and away from the public is how security testing and improvement are usually handled. If Claude Mythos is a skeleton key, you want companies to be able to protect their products. While this initial $100 million in usage comes free, the next hit might cost businesses big, depending on Mythos's final model pricing.

So, does this mean that Project Glasswing is a mere marketing stunt? Not quite. It follows industry standard Coordinated Vulnerability Disclosures (CVD), and the model, when analyzing multiple reports, is one of the most performant AI models for cybersecurity out there.

But, following its rally of headlines around pushing back against the Pentagon, Anthropic now wants to help secure its place in the cybersecurity industry by graciously offering up free compute resources to those partaking in Project Glasswing.

But, you also have to consider if that grace is coming at a high cost for Anthropic. As demand for AI explodes, the companies serving large, powerful models need to be equipped with the compute resources to serve them. For a presumably heavier, more computationally expensive model like Mythos, that might put a strain on Anthropic's already outage-prone AI models, which have had a 98.4% uptime rate in the last 90 days as of the time of writing. Four nines, or 99.99%, is considered enterprise-grade uptime; in other words, that's the standard Anthropic needs to meet if it wishes to court SaaS and Cybersecurity whales with Mythos.

While that may not sound like much, it equates to almost twelve hours of downtime per month, which is poor by cloud service standards. For OpenAI's API, you get 99.99% uptime — and when you're in the business of selling tokens, that makes a huge difference. For Anthropic, it means that the company must also seek out further computational heft as soon as possible to plug the gap, as it did with its recent Broadcom deal.

Myth(os) busted

So, the real conclusion to draw, now that the dust has settled somewhat on the grand Mythos reveal, is that it indeed might be one of the best overall AI models for cybersecurity, but it might not be the best model for every single job. If it's expensive, other models may be able to get to a similar level of quality while being computationally cheaper.

And Anthropic, for all of its bluster about the model, still cannot serve its currently-released models to industry-standard levels, discounting Mythos. So, all of these factors combine to put Anthropic in a difficult position. As compute remains constrained, and AI usage explodes globally, we can only wait and watch to see how (and where) the chips fall. Even if Anthropic can court the customers that it wants to with Mythos, it'll still need to keep up with insatiable compute demand.

Claude AI developer Anthropic made headlines this week for its development and internal release of a new model known as Mythos. This mythically-named AI model allegedly has incredible capabilities, including finding bugs and vulnerabilities in various apps, operating systems, browsers, and legacy software. Enough that Anthropic was concerned about its general release and will instead keep it internal and focus on working with major tech companies and governments to prevent this tool from falling into the wrong hands, where it could cause untold mayhem.

That's the pitch in Anthropic's blog and verbose 250-page report on the model — which includes over 20 pages of Anthropic staff waxing lyrically about their novel impressions of the new model and its "fondness for particular philosophers."

Alongside the repeated suggestions from Anthropic and its staff that we should be concerned, nay, terrified, of what AI like Claude Mythos can do, they repeatedly suggest they're unsure if this new AI is conscious.

For the record, it is not. It might be good at finding vulnerabilities in software, but many of them aren't as potentially damaging as Anthropic wants us all to believe.

Exploit hunting

The big "Project Glasswing" blog post and report on Mythos from Anthropic claimed its new model had found "thousands of high-severity vulnerabilities," which is indeed big news. Those bugs were said to be across every major operating system and web browser, and in some cases have been there for decades.

But it's not clear how realistic these vulnerabilities are, how many of them aren't actually exploitable, or even how problematic they are.

In the case of the FFMPeg vulnerability that has existed for 16 years, Anthropic's own analysis of the release suggested "This bug ultimately is not a critical severity vulnerability," and "would be challenging to turn this vulnerability into a functioning exploit."

Mythos reportedly found several potential exploits in the Linux kernel, but was unable to exploit any of them because of Linux's defense-in-depth security systems. A number of the exploits had also been recently patched, too, making it rather confusing why they were included in the total.

In its OSS-Fuzz-style testing of over 7,000 open source software stacks, Mythos found crashable exploits in around 600 examples and 10 severe vulnerabilities. That's a lot more than its previous Claude models, but not exactly thousands of devastating exploits.

Under the subheading, "and several thousand more," Anthropic also states that it can't actually confirm that all of the thousands of bugs Mythos claims to have found are actually critical security vulnerabilities. It's just extrapolated that number from having found in around 90% of the "198 manually reviewed vulnerability reports, [Anthropic's] expert contractors agreed with Claude’s severity assessment exactly."

It also can't discuss all the bugs in detail for security reasons. While that does make some measure of sense, it also makes it hard to accurately gauge the relative importance of its findings.

You're not worth it

As much as Anthropic claims it's keeping Mythos behind arbitrarily closed doors over what it claims are security fears, this isn't exactly out of character for the company. Its Claude tool was famously the first large language model AI to be given security clearance for use by the U.S. government and American military, and that only changed after it drew a line in the sand on being used for mass surveillance or fully autonomous targeting.

Anthropic might have a consumer-facing product in its coding tools, but it is very keen on selling its services to big companies and government entities. If it can sell Mythos to large firms or any number of governments around the world, why would it need to sell it to consumers?

Hot air, or real worries?

As much as Anthropic might sell itself as the security and safety-conscious AI developer, it has also repeatedly leveraged that public image as part of its sales pitch. Over the past couple of years, Anthropic has published several alarming papers, reports, and studies, many of them claiming that AI is dangerous and needs strict control and monitoring.

It claimed to have foiled the first AI hacking attempts in the latter months of last year, and it was Anthropic CEO Dario Amodei who said in May that year that AI could replace up to 20% of white-collar workers. He doubled down on that claim in 2026, saying that AI taking over jobs would overwhelm our ability to adapt.

Nvidia CEO Jensen Huang called out this fear-mongering in mid-2025, claiming Anthropic wanted to position itself as the only company that could responsibly develop AI.

This isn't even anything new in AI marketing. OpenAI was doing it in 2019, before ChatGPT was even a twinkle in Sam Altman's eye, and Dario Amodei hadn't yet left OpenAI.

Speaking of OpenAI, days after Anthropic's Mythos reveal, it was also working on an advanced cybersecurity AI model. It too will limit the rollout of this powerful and concerning tool, Axios reports. As models develop, they reach a similar level of capability, so it's no surprise that OpenAI could have a Mythos-level or adjacent model waiting in the wings.

Sentience and security

AI isn't conscious. It's more like a Chinese room from the John Searle thought experiment, but even then, it has no understanding. It doesn't truly remember anything in a biological sense; it can just recall contexts and weight its responses differently based on previous inputs. So, sentience and consciousness claims may yet be unfounded.

AI models may well be good at discovering vulnerabilities, and if Anthropic and other software developers can find and patch bugs using AI, that's good news, not scary news.

As Red Hat's analysis of this release shows, many of the bugs are functionality flaws and aren't a security concern. But even if hackers can leverage AI tools in the future to find exploits and then exploit them, that's only a concern if the security industry doesn't respond. Which it will.

So, sure, AI is impacting security. It already was. And it will continue to do so. While Mythos might be capable in ways that previous models were not, this appears to be part-marketing, part-truth. For the rest of us, this is just another AI model. For Anthropic, it's an opportunity to gain mindshare and potentially lucrative contracts.

Last week, Denuvo made headlines, but for all of the wrong reasons. A freshly minted hypervisor bypass renders Denuvo's famous anti-tamper protection virtually useless to those willing to go to the lengths that the crack requires. For those not in the know, Denuvo is an anti-tamper and DRM software developed by Irdeto, which has been deployed across a huge number of PC gaming titles, sometimes with controversial results. Previously, it was considered difficult, or near impossible, to crack the DRM. Now, it's been blown wide open, due to the freshly minted Denuvo hypervisor-based bypass.

This method has allowed game cracking and distributing pirates (collectively known as "the scene") to once again release DRM-free versions of popular AAA titles on release day, known as zero-day releases. Naturally, this doesn't bode well for Denuvo and its parent company, Irdeto, for whom the DRM is a major earner.

We should note that the language in "hypervisor-based bypass" is specific, as actual cracks of recent Denuvo versions have yet to be published. A 'proper' crack would alter the game's executable code to remove or disable its DRM, while a bypass keeps the game mostly intact but adds an external avoidance mechanism.

This distinction is key with the hypervisor bypass (HVBP), as it requires drastic measures from gamers downloading pirated releases. One needs to disable almost every Windows low-level security feature — an exceedingly poor idea on its own — as well as install a scene-made hypervisor (HV), which Windows itself then sits on, to intercept Denuvo's checks. Gamers can easily enable these features after playing, but chances are, few will bother.

Any HV, whether it's VMWare ESXi, Hyper-V, Xen, or this Denuvo bypass, has access to the system at the metal level, with complete reign over the computer and all its data and hardware. Even trusting the scene's programming acumen, if the releases using HVBP prove popular, we're talking at least hundreds of thousands of systems with all defenses down and a nearly hardware-level threat vector. An unintentional bug in the HV can be exploited by malicious actors in an essentially untraceable manner.

Denuvo's reputation amongst enthusiasts

Ever since its inception circa 2014, Denuvo Anti-Tamper (not to be confused with Denuvo Anti-Cheat) has been under fire from gamers for its heavy-handed approach. The software is notorious for punishing legitimate customers, thanks to measures including hardware fingerprinting with limited activations, requirements to periodically reach out to Denuvo's servers, and finicky online validation that may brick many single-player titles if the activation servers ever disappear.

Every single one of those measures has caused perennial headaches for gamers, necessitating YouTube tutorials and other community help to let someone just enjoy a game they already paid for. But perhaps the most contentious of all is the performance hit thanks to the constant hardware verification, adding stuttering and lowering FPS, sometimes to the point of making some games unenjoyable in weaker machines. Denuvo has voraciously defended these reports, claiming that the DRM does not impact performance.

Regardless of optics, Denuvo has been able to stay one step ahead of crackers more often than not during the past decade. Whereas simple CD-checks of yore could be bypassed in an afternoon by someone with middling skills, combating Denuvo's thousand-layer approach requires a particular combination of technical acumen, patience/stubbornness, and free time — not an easy combination to come by, at least for free.

The cat-and mouse race against piracy

After its 2014 launch, it took crackers about a month to snap Denuvo, a timeframe almost unheard of for the scene. After a quick upgrade, Denuvo 2016 (the version naming is ours and not official) earned itself about a year and a half of immunity, with the main crackers almost giving up, until a rally in 2017 made zero-day releases the norm again. Around 2018, Denuvo applied its VMProtect obfuscation layer, making crackers once again work for weeks or even months to clean one title, though the scene's efforts accelerated to a full crack in 2019, resetting the scales once again.

After more Denuvo updates, the period between 2020 and 2025 was perhaps the driest for the piracy scene, given that apparently only two crackers (Empress, then voices38) were actively working on Denuvo, at a steady but undoubtedly slow pace. The vast majority of games remained uncracked, and those that fell to the attacks did so well after their original release dates. It was not until late 2025 that a new challenger appeared, in the form of the MKDev collective.

In December 2025, MKDev released a proof-of-concept of an HV bypass for Persona 5 Royal, with accompanying documentation describing how it all worked, using publicly available documentation and open-source hardware. This led to multiple community efforts applying that research, with the first notable release being Borderlands 4. More recently, Resident Evil: Requiem was a zero-day crack (one hour to be precise), and Crimson Desert was circulating in piracy circles the same day it launched.

Even the HVBP itself evolved somewhat, as the first version even required users to disable Secure Boot entirely and use EfiGuard to tweak the boot process, in addition to the aforementioned steps. Due to the concerning nature of the requirements surrounding the HVBPs, even its own makers alert users to the necessity of using the provided scripts to re-enable all the security features once they're done playing.

Popular repackers within the scene initially refused to carry HVBP releases, eventually changing their tune after the requirement to disable Secure Boot and use EfiGuard was removed. Even still, the HVBP games are clearly marked as such by both release groups and repackers. Meanwhile, voices38, the only known cracker working on contemporary Denuvo, already has 2025's Doom: The Dark Ages under their belt.

For its part, Denuvo has promised that it's increasing the product's security, and notably that it'll do so without further encroaching on gamers' systems. Despite its intensity, unlike some other copy protection methods of yore, Denuvo currently doesn't install any drivers and runs like any other application in ring 3 of the operating system, a fact that led HVBP releaser Kirigiri to posit that Denuvo will never be able to properly detect the HVBP, since that runs below Windows itself.

Denuvo ultimately helps PC game sales

The argument can also be made that, all things considered, until now, Denuvo has historically succeeded in its intended purpose. The mission of PC DRM has long been stated as protecting a game's initial sales weeks, particularly for highly marketed AAA releases that make the vast majority of their money around release date. As historical records show, Denuvo has been successful more often than not.

Normally, tangible and coherent information on the financial effectiveness of Denuvo is quite hard to come by. In 2024, the University of North Carolina released a study comparing sales-over-time of games protected with Denuvo versus those that got cracked.

The picture the data painted was pretty clear: a cracked game nets about 20% less total revenue in the first 12 weeks (three months) after release, with a strong correlation between the crack release date and the start of comparative revenue loss.

However, the study's author also notes that once those three months go by, it's borderline irrelevant for revenue whether a game is cracked or never had any DRM to begin with. Given Denuvo's well-known tendencies to cause performance and technical issues, some publishers have started removing it from their games right on or around the release day (Doom Eternal, Two Point Hospital, Devil May Cry 5) or some time after (Monster Hunter World, Resident Evil Village, NieR: Automata)

Most removals can be justified by the availability of cracked or DRM-free versions of the game, or due to community outcry, but it also likely benefits the publisher. Some reports claim that Denuvo's contracts include monthly and/or per-activation charges, which go away once the software is stripped.

Furthermore, any titles that never had Denuvo removed, including the HVBP releases, will be hard to archive, as at some point in time, the activation servers will vanish, and the games will otherwise become bricked.

Additionally, integrating Denuvo is both difficult and full of performance traps. Not only is Denuvo heavy to begin with, but it also takes effort from developers in crunch time to implement it effectively. Even then, the software's VM-obfuscation approach can undo weeks if not months of careful optimizations.

It also gets kind of ridiculous if you think about it: under normal conditions, a PC runs a Hyper-V, which runs Windows 11, that runs the game executable, that runs a Denuvo virtual machine, that then finally runs the game code (or parts of it). The analogy of software to onions has never rung truer.

Even still, with AAA game releases that amount to hundreds of millions, if not billions of revenue, that 20% slice is very hard to ignore — and so the cat-and-mouse game continues.

Counterpoint Research's full-year Foundry Market Supply Tracker estimated that the global semiconductor foundry market generated a record $320 billion in revenue in 2025, growing 16% year-over-year. TSMC accounted for 38% of that total and grew 36% year-over-year. In comparison, non-TSMC foundries collectively grew 8%.

That lopsided split isn’t a one-quarter anomaly or a function of a single product cycle, but instead reflects three massive advantages held by TSMC that reinforced each other throughout the year: an unmatched concentration of leading-edge node volume, compounding wafer price increases, and vertical integration into the advanced packaging that AI chips require.

TSMC's leading-edge node concentration

TSMC's own earnings data show how heavily its revenue has tilted toward the nodes that AI and high-performance computing demand. Advanced process technologies at 7nm and below accounted for 74% of TSMC's wafer revenue in Q4 2025, with 3nm alone contributing 24% and 5nm responsible for 36%. For the full year, 3nm's share rose from 18% in 2024 to 24%, while 5nm held steady at 36%, rising by just 2%. These are the process nodes at the foundation of Nvidia's Blackwell GPUs, AMD's Zen 5 EPYC processors, and Apple's M-series chips.

No other foundry has competitive volume at equivalent nodes. Samsung, the second-largest pure-play foundry, saw its market share dip to 7.7% in Q1 2025, down from 8.1% the prior quarter. Samsung's 3nm yields sat in the 30% to 40% range for much of the year, according to TrendForce, a level insufficient to attract large external orders. The company couldn’t even use its own 3nm Exynos 2500 for the Galaxy S25 series and instead sourced Qualcomm's Snapdragon 8 Elite from TSMC. Samsung disclosed 2nm GAA performance figures in its Q3 2025 earnings report and listed its first 2nm product, the Exynos 2600, as in mass production by December, but yields remained a work in progress, remaining below 50% as of last month.

Counterpoint Research Director Tom Kang acknowledged Samsung's difficulties but pointed to a potential turning point. "Demand for its 4nm node has been relatively solid, supporting better pricing, and the ramp of 2nm should help it secure higher-value designs, particularly in AI and mobile," Kang said.

SMIC, the largest Chinese foundry, grew 16% YoY and Nexchip expanded 24%, but both companies' growth came from trailing-edge and mature nodes supported by domestic localization efforts, not from competing at 5nm and below. SMIC operates roughly 20,000 wafers per month of 7nm capacity, most of which reportedly goes to Huawei. GlobalFoundries, UMC, and VIS similarly serve mature-node markets.

Compounding wafer price increases

TSMC's revenue growth isn’t solely a function of shipping more wafers; rising average selling prices (ASPs) have compounded the volume gains. TSMC's wafer ASPs increased at a roughly 15.9% annual rate from 2019 through 2025. Gross profit per wafer expanded approximately 3.3 times over the course of 2025 alone, as price increases outpaced production cost growth. Cost of goods sold rose 78% over the same multi-year period, while ASPs more than doubled.

TSMC is understood to have locked in further increases for 2026. TrendForce reported in November that the company notified customers of 5% to 10% price hikes across all sub-5nm nodes starting in January 2026, covering 2nm, 3nm, 4nm, and 5nm processes, and cumulative increases on 3nm-family nodes are expected to reach double digits over the next several years.

TSMC can sustain these increases because customers have no alternative at comparable volume and yield. Samsung's sub-5nm yields are not competitive enough to absorb large orders. Intel Foundry, which held 6% of the broader Foundry 2.0 market by Counterpoint's reckoning, generated $4.5 billion in Q4 2025 revenue but remained deeply unprofitable, with 18A process yields only set to reach industry standard levels in 2027. Until a second foundry can offer competitive, leading-edge manufacturing at scale, TSMC retains pricing power that directly translates volume growth into outsized revenue growth.

Advanced packaging

Another factor to consider is TSMC's expansion into advanced packaging, which has created a second revenue stream that competitors can only partially capture at this time. TSMC's CoWoS capacity roughly doubled from approximately 35,000 wafers per month in late 2024 to roughly 80,000 by the end of 2025. The company is targeting further increases to around 130,000 wafers per month by the end of this year through new facilities at AP7 in Chiayi and AP8 in Tainan.

Nvidia reportedly secured more than 60% of TSMC's total CoWoS capacity for 2025 and 2026, with every Blackwell GPU and the upcoming Rubin architecture requiring CoWoS-L packaging to connect multiple GPU dies with HBM3e memory stacks. When a customer commits to TSMC for both front-end wafer fabrication and back-end advanced packaging, switching costs become very high, so TSMC is capturing revenue at both stages.

Meanwhile, the OSAT segment grew 10% YoY in 2025 under Counterpoint's Foundry 2.0 framework, with ASE/SPIL and Amkor absorbing spillover demand. ASE became the second-largest player by revenue in the entire Foundry 2.0 market behind TSMC, according to Counterpoint. But OSAT vendors primarily handle the overflow that TSMC's internal capacity cannot accommodate, not the highest-value packaging steps. TSMC keeps the silicon interposer fabrication and front-end chip-on-wafer processes in-house, outsourcing lower-margin substrate assembly and testing.

"Advanced packaging is no longer just a supporting step but becoming a gating factor for AI deployment," William Li, senior analyst at Counterpoint Research, said. "As customers move to lock in capacity, OSAT vendors are structurally better positioned than in past cycles, with growth visibility extending over multiple years."

Counterpoint projects that industry-wide advanced packaging capacity could expand by roughly 80% YoY in 2026. TSMC's own CoWoS expansion accounts for the majority of that growth, once again reinforcing its position at the center of the AI chip supply chain.

That position isn’t guaranteed to last forever, though. Samsung’s 2nm ramp could begin attracting external customers if yields stabilize, and Intel's 18A process has its first products in Panther Lake and Clearwater Forest, though volume shipments still have time to slip. Chinese foundries will likely sustain double-digit growth on continued localization spending, while non-memory IDMs such as Texas Instruments and Infineon have largely cleared their inventory corrections, providing a more stable demand baseline.

None of these developments, however, close the gap in the near term as TSMC enters 2026 with 2nm production ramping, some $56 billion in planned capex, and a customer base that’s pre-committed to years of advanced packaging capacity. The fact that TSMC took 38% of the market in 2025 wasn’t an outlier but the product of compounding advantages in technology, pricing, and vertical integration that will take competitors years to match.

Chinese AI and graphics chips flooded the country's domestic market in 2025, leading to a decline in Nvidia's chip dominance in the region and a boon for China's efforts to foment a local supply chain for AI compute power. With 41% of the Chinese AI server market now controlled by Chinese suppliers, Nvidia has even more reason to restart its shipments of H200 GPUs to the region, despite the bipartisan efforts of U.S. Senators to stop that in its tracks.

Although Nvidia still holds a commanding stake in the region, with a 55% market share for AI server hardware, that's a huge downturn from Nvidia's claimed peak of 95% in 2022, before the U.S. began applying sanctions to China and trade export restrictions to Nvidia.

The concern about Chinese AI hardware developments doesn't just come from its ability to supplant Nvidia in the region, but to spread beyond it. Although hardware developed by the likes of Baidu, Huawei, and Cambricon can't compete with Nvidia's cutting-edge chips, it is growing increasingly capable, and in a world facing long-term shortages of everything, AI hardware included, the next-best-thing becomes a lot more attractive.

Losing its grip

Although it's hard to verify how accurate Nvidia's "95%" claims were, it's fair to say that the US chip giant was once the only real player in town. Its GPUs are vastly more performative than even the best Chinese alternatives today, and even its cut-back China-specific GPUs like the H20 have their advantages.

But over the past few years, with turbulent supply and even more turbulent U.S. leadership, China has fostered its own chip industries with a range of measures. From energy subsidies to mandated chip deployments and enormous financial investment, China is betting the farm on developing its own alternatives to Nvidia's best.

The country isn't there yet: China had to roll back demands to use domestic chips for training, which just can't offer a clear alternative to Nvidia's hardware. But on the inference side of things, Chinese companies are catching up, and with the long, slow return of Nvidia's H200 GPUs, real competition has been rising.

Throughout 2025, Chinese tech giant Huawei shipped over 812,000 AI chips to Chinese firms and organizations, representing around half of all domestic shipments, making it the largest Chinese chip supplier of the year. This was followed by Alibaba's chip design unit, T-Head, which shipped 265,000 graphics cards, while Baidu's Kunlunxin and Cambricon each shipped around 116,000 GPUs, making them joint third.

Other Chinese suppliers like Hygon, MetaX, and lluvatar CoreX delivered sizeable shipments of their own.

All of this while Nvidia hasn't been able to ship its China-specific H20 GPUs, nor the more-capable H200 that it's been trying to get back to shipping. That time out of the market is leaving the door wide open for domestic alternatives. Perhaps that's partly why import licenses for companies interested in Nvidia's GPUs have taken so long to approve.

Real competition

Even with Chinese AI server chips more readily available to Chinese companies, many still push for Nvidia hardware — smuggling is still rampant for a reason. We've seen this with training chips, where domestic options don't measure up. But not with inferencing hardware. That's where real competition is starting to emerge.

As MUFG America's February 2026 study shows, the most capable Huawei chip, the Attend 910C, is within spitting distance of Nvidia's H100 in compute power and is vastly more capable than the H20. It falls behind both in memory bandwidth, but not by egregious amounts. It's well behind the latest-generation Blackwell generation GPUs, but progress is clearly being made.

Huawei just announced its Atlas 350 AI accelerator based on its Ascend 950PR chip, promising almost three times the compute performance of Nvidia's H20. That could put it in the region of the H100 in terms of raw performance, leaving only Nvidia's Blackwell GPUs out in front, although a reported 1.4 TB/s memory bandwidth could represent a notable bottleneck.

Huawei has many more Ascend chips in the pipeline, but it's not the only one offering Nvidia competition. Alibaba unveiled its Zhenwu 810E AI chip in January, a chip said to be largely comparable to the H20. But it's 96GB of HBM2 memory delivers only around 700 GB/s of memory bandwidth; that's less than a quarter of the H20's.

Baidu announced its M100 and M300 AI chips in November last year, planning to launch them in 2026 and 2027, respectively. We couldn't find any direct Nvidia chip comparisons, but Baidu has suggested new supernode clusters of its chips could offer a 50% increase in performance over the last generation, suggesting major leaps in capability within short timeframes.

Cambricon's flagship Siyuan 590 AI accelerator falls behind Baidu and Huawei's efforts, yet it still expects to sell upwards of 500,000 units. The company is preparing its next-generation 690 chips for launch in 2026, although questions remain over whether it can get the materials it needs to manufacture them.

The race for relevancy

If Nvidia's AI hardware is its vanguard into the Chinese market, CUDA is supposed to be its backstop. That ecosystem is a protective moat that ensures those using CUDA-optimized software and Nvidia hardware keep doing so. But alongside Chinese hardware advances are Chinese software developments.

Baidu's Kunlunxin has translation layers that can run CUDA code efficiently, easing the transition from Nvidia hardware. Its PaddlePaddle framework is optimized for its Kunlun chips, too, so as Chinese providers make the switch, they can enjoy greater performance and efficiencies. Of course, there's also CANN, and this splintered approach could make China's local AI aspirations falter, if a unified approach is not fully adopted.

The longer Nvidia hardware isn't available, the more time Chinese companies and organizations have to transition to domestic alternatives that are easier to acquire, often come with government incentives, and are only likely to grow in power and efficiency, with an ever-more streamlined adoption pipeline.

That's what made it such a surprise that Nvidia told Tom's Hardware it wasn't planning to sell its Groq inferencing chips to China. ARM is very much looking to sell its new AI CPU there, though.

Nvidia's dominance is far from dead, and there really is no one likely to catch up in raw performance terms, or indeed in widespread support and compatibility for some time to come. But alternatives are rising, and the longer Nvidia's H200s sit in warehouses, with quiet production lines and strained trade routes, the more the tables will turn.

On Tuesday, Nvidia announced that it has invested $2 billion in Marvell Technology and entered a partnership through NVLink Fusion, the rack-scale platform that allows third-party silicon to plug into Nvidia's proprietary interconnect fabric. The deal covers custom XPUs, NVLink-compatible scale-up networking, silicon photonics, and AI-RAN infrastructure for 5G and 6G networks.

It’d be an understatement to say that this deal is unusual, given Marvell’s status as one of the two dominant custom ASIC design houses, alongside Broadcom. Its fastest-growing business is designing the custom AI accelerators that hyperscalers like AWS, Microsoft, and Google use to reduce their dependence on Nvidia GPUs.

But by pulling one of its most capable indirect competitors deeper into the NVLink ecosystem, the structure of NVLink Fusion means that arrangement will generate Nvidia revenue on every rack deployed. Here's how.

NVLink Fusion

NVLink Fusion, announced at Computex 2025 last May, enables heterogeneous AI infrastructure where non-Nvidia accelerators can communicate with Nvidia GPUs, CPUs, and networking hardware over NVLink's high-bandwidth, low-latency fabric. NVLink delivers up to 1.8 TB/s per GPU, a huge bandwidth advantage over PCIe Gen5, and can scale to 72 accelerators per rack in its NVL72 configuration.

The platform is built around the OCP MGX rack architecture and includes a modular technology stack consisting of Nvidia GPUs, Vera CPUs, NVLink switch silicon, ConnectX SuperNICs, Bluefield DPUs, Spectrum-X switches, and Mission Control management software. Partners can plug their own custom XPUs or CPUs into the compute layer, but the surrounding infrastructure is all Nvidia.

Every NVLink Fusion platform must include at least one Nvidia product, whether a CPU, GPU, or switch. Nvidia has also retained control over which partners receive NVLink IP licenses, so custom chips designed to displace Nvidia's GPUs still generate the company revenue through infrastructure sales every time a rack goes live. Under the deal, Marvell will provide custom XPUs and NVLink Fusion-compatible scale-up networking, while Nvidia will supply the rest of the stack, including Vera CPUs, ConnectX NICs, Bluefield DPUs, NVLink interconnect, and Spectrum-X switches.

Marvell's ASIC business

Marvell reported $8.2 billion in revenue for its fiscal year 2026 ending January 2026, with data center revenue accounting for more than 74% of the total.

Custom AI compute is the fastest-growing segment within that business, and Marvell's client list reads like a directory of companies actively building alternatives to Nvidia GPUs. AWS is its largest custom-silicon customer, with Marvell helping develop the Trainium series of AI accelerators.

Microsoft is also working with Marvell, among others, on its Maia AI accelerator, and it’s understood that Google has partnered with Marvell on its Axion Arm CPU for cloud workloads. In each case, the explicit objective is to give the hyperscaler a cheaper, more efficient (or more customizable) alternative to buying Nvidia products at scale.

The custom ASIC market is growing fast. Counterpoint Research estimated in January 2026 that global AI server compute ASIC shipments will triple between 2024 and 2027. Broadcom is projected to retain a 60% market share in ASIC design services by 2027, with Marvell facing some design-win headwinds but still doubling its shipment volumes over that period. By investing in Marvell and binding its custom XPUs to the NVLink fabric, Nvidia ensures it retains a revenue position even in racks where its GPUs have been replaced.

The Marvell deal is the second $2 billion investment Nvidia has made in 2026. The first, announced in January, went to AI cloud provider CoreWeave, which rents access to Nvidia CPUs. This was widely described as an example of the circular financing arrangements that have lifted AI company valuations: Nvidia invests capital in a customer, and that customer uses it to buy more Nvidia hardware. Nvidia already held a 7% stake in CoreWeave and has committed to buying more than $6 billion in its services through 2032.

That’s pretty different from the deal just struck with Marvell. CoreWeave focuses on the demand-side of things — fund a customer to buy more GPUs. Marvell focuses on the supply side, co-opting the company designing the alternative silicon itself. Instead of fighting the custom ASIC trend, Nvidia is absorbing it into its own infrastructure.

NVLink Fusion's vs UALink

The Marvell deal is the latest in a series of NVLink Fusion expansions. Samsung Foundry joined in October to offer design-to-manufacturing support for NVLink-compatible custom chips on its 3nm and 2nm nodes, giving Nvidia a second major foundry partner after TSMC. Then Arm entered the program in November, enabling its licensees to build CPUs with native NVLink connectivity, which opens the door for hyperscalers like Google, Meta, and Microsoft to integrate NVLink directly into their own Arm-based SoCs. SiFive joined in January 2026, bringing RISC-V into the ecosystem. Fujitsu, Qualcomm, MediaTek, Alchip, Astera Labs, Synopsys, and Cadence were among the original partners announced at Computex.

On the other side sit AMD, Intel, and Broadcom, all of which are backing the Ultra Accelerator Link (UALink) consortium as an open industry-standard alternative to NVLink. UALink's 1.0 specification supports up to 1,024 GPUs with 200 GT/s bandwidth, but the standard has yet to ship in production hardware, while NVLink is already deployed at scale in Blackwell NVL72 racks.

Broadcom's absence from NVLink Fusion is pretty interesting, given it’s the other half of the custom ASIC duopoly. Broadcom has been Google's TPU design partner for over a decade, spanning six generations of the chip, and also works with Meta on its MTIA accelerator and reportedly with OpenAI on a custom ASIC. If Broadcom's clients eventually face pressure to deploy their custom chips in NVLink-compatible racks, the current dividing line between the NVLink Fusion camp and the UALink camp could shift.

The partnership also covers two secondary but just-as-significant areas. Marvell acquired Celestial AI in early 2026 for $3.25 billion, adding photonic fabric technology to its portfolio. Optical interconnects are becoming critical as AI clusters scale beyond the distances where electrical signals maintain their integrity, and Marvell's optical DSP products are already widely used in pluggable modules for data center networking. The company's fiscal year 2027 revenue target for data center switches is above $600 million, roughly double its fiscal year 2026 figure.

Meanwhile, the AI-RAN part of the Nvidia-Marvell collab will target the transformation of telecomm infrastructure into AI-capable networks using Nvidia's Aerial platform for 5G and 6G. This is a smaller market today, but both companies are positioning for a buildout that would embed AI processing directly into the radio access network.

"The inference inflection has arrived. Token generation demand is surging, and the world is racing to build AI factories," said Jensen Huang on the investment. Whatever the use-case may be, Nvidia wants to be a critical part of AI infrastructure. And by opening the gates and partnering with Marvell, his company is broadening the size of its walled garden.

Iranian drone and missile strikes hit QatarEnergy's Ras Laffan Industrial City on February 28, knocking offline one of the world's two plants capable of producing semiconductor-grade helium — and removing roughly 30% of global supply from the market in a matter of days.

QatarEnergy halted all production at the site two days later, declaring force majeure on March 2, while the Strait of Hormuz has been effectively closed to Western commercial shipping since the conflict in Iran began. Helium prices have surged 40% to 100%, and the semiconductor industry is counting down the weeks until existing stockpiles run dry.

Qatar produced approximately 63 million cubic meters of helium in 2025, constituting a third of the roughly 190 million cubic meters produced globally, according to the U.S. Geological Survey. QatarEnergy has reported "extensive" damage to its facilities and announced a 14% annual cut to helium exports, though the actual disruption is far larger given the shipping blockade.

Phil Kornbluth, president of Kornbluth Helium Consulting, said during a Gasworld webinar that a best-case scenario would see some production resume within six weeks, but called that outcome "highly unlikely." Some industry analysts expect it will take Qatar around five years to regain lost capacity.

Chip fabs can't run without helium

Helium performs at least four key functions in semiconductor fabrication, and none have viable substitutes.

The most important of these is cooling: ASML's EUV lithography machines, which are the only tools capable of printing features below 7nm, generate enormous heat during operation, and helium's thermal conductivity and chemical inertness make it the only gas suitable for cooling these systems without contamination risk. Beyond EUV, helium cooling of silicon wafers during ion implantation can affect the precision of dopant placement, even for fractional temperature variations.

Helium is also the standard gas for leak detection in vacuum chambers because its atoms are small enough to pass through microscopic defects that other gases cannot, making it irreplaceable for verifying sealed process environments. In thin-film deposition, helium serves as an inert carrier gas for reactive chemicals.

Jong-hwan Lee, a semiconductor devices professor at South Korea's Sangmyung University, told Nikkei recently that there’s currently no viable alternative to helium for cooling wafers. As EUV adoption accelerates — SK hynix placed a record $7.9 billion order for ASML EUV scanners on March 24 — helium consumption per wafer is increasing, not decreasing. The SIA warned in a 2023 filing to the USGS that if helium supply were disrupted, "there would likely be shocks to the global semiconductor manufacturing industry."

Unfortunately, the shortage extends beyond chip fabs. Most HDDs at 10TB capacity and above, for example, use helium as a sealed internal gas. Helium is seven times less dense than air, reducing aerodynamic drag on spinning platters and allowing manufacturers to pack more disks into each enclosure. The technology has been standard across all high-capacity enterprise drives since HGST introduced the first commercially successful helium-sealed HDD in 2013.

Even more unfortunate is the fact that the HDD market is already severely constrained, much like the rest of the memory market. Western Digital CEO Irving Tan confirmed during the company's Q2 2026 earnings call that WD has sold out of hard drives for 2026, with long-term agreements in place through 2028. Some 89% of WD's HDD revenue now comes from cloud customers, and prices have jumped an average of 46% since September 2025. A helium shortage on top of that existing demand crunch compounds the problem at both the production and pricing levels.

A fragile and concentrated supply chain

If Qatar accounts for roughly one-third of helium production, where’s the rest? Mostly in Russia and the United States, which, together with Algeria, account for 58% of global helium production.

The U.S. is the largest single producer at roughly 81 million cubic meters per year, but most of that supply is consumed domestically, limiting how quickly it can offset a disruption in global exports, according to the data at World Population Review.

The U.S. maintained a strategic helium reserve for decades, but the government began selling it down in the late 1990s under the 1996 Helium Privatization Act, and the Bureau of Land Management ended crude helium sales from the reserve entirely in 2023.

Russia's Amur Gas Processing Plant was supposed to supply up to 25% of global demand at full capacity and become the world’s largest helium producer, but the facility has been plagued by delays, explosions, technical setbacks, and Western sanctions. As of early 2026, Amur is still running well below capacity, and new exploration projects in Saskatchewan, Tanzania, and South Africa are years from lifting off.

How long can chip fabs hold out?

Helium is a cryogenic liquid that must be stored near absolute zero in specialized containers. Once insulation is depleted, the helium warms, expands into a gas, and escapes, so it must typically be transported within 45 days of liquefaction. Richard Brook, CEO of helium consultancy Garrison Ventures, told the New York Times that chip makers can store about six weeks' worth of supply. Roughly 200 specialized containers are reportedly stranded near the Strait of Hormuz.

South Korea is by far the most exposed country, with the Korea International Trade Association having reported that 64.7% of South Korea's helium imports came from Qatar in 2025. SK hynix has said it diversified its helium suppliers and secured sufficient inventory, but the country's exposure remains significant. TSMC, meanwhile, doesn’t currently anticipate a notable impact, and Taiwanese thinktank director Arisa Liu estimated the chip maker has enough helium for "several months."

Meanwhile, Bloomberg Economics analyst Michael Deng has noted that helium shortages could force chipmakers to prioritize higher-margin AI chips over less profitable (meaning consumer-focused) components. TSMC manufactures all of Nvidia's data center GPUs, for example, which generate far higher margins than consumer products like the RTX 50 series.

Recovery efforts are underway, though they’ll take some time to materialize. French industrial gas supplier Air Liquide opened a new factory near the port of Taichung, Taiwan, on March 27 to diversify helium sourcing for Taiwanese chip makers. In China, Guangdong Huate Gas has achieved mass production of 6N ultra-high-purity helium and secured ASML certification, according to TrendForce. China's annual production capacity of ultra-high-purity helium has reached about 1.2 million cubic meters, and several Chinese firms are developing recovery systems with reprocessing rates up to 98%.

Semiconductors sit at the top of the allocation pecking order when supplies tighten, Kornbluth told CNBC, with other industries likely to see their allocations cut first. But priority access cannot solve a physical shortage if Qatar's production remains offline over the coming months.

After criticizing leading chipmakers for slow capacity expansion and claiming his companies need 100 – 200 billion AI processors annually, Elon Musk last week unveiled TeraFab — a chipmaker aiming to produce logic chips, HBM4 memory, and advanced packaging under one roof. Backed by an initial ~$20 billion investment, the project targets manufacturing chips consuming 1 terawatt (1 TW) of power per year using leading-edge process technology within the next several years.

But an exhaustive analysis by Tom's Hardware Premium reveals so many factors working against TeraFab, an effort designed primarily to produce chips in-house, that it appears highly unrealistic — at best a step towards partial vertical integration for Tesla, SpaceX, and xAI.

Barriers to entry in the semiconductor industry are so high that launching a new player capable of manufacturing chips in high volumes on leading-edge process technologies is nearly impossible, from both a capital investment and an expertise point of view. All new foundries established in recent decades were either spun off from leading integrated device manufacturers (Intel Foundry, GlobalFoundries, Samsung Foundry), backed by governments (Rapidus, Tata Semiconductor, Hua Hong/HLMC, SMIC), or focused on niche markets (SkyWater, Ayar Labs, Lightmatter). And many of these new players — Intel Foundry, Rapidus, and Tata — have yet to prove that they can be competitive world-class contract semiconductor makers.

TeraFab does not plan to become a foundry; its only purpose is to serve the silicon needs of Elon Musk's companies, including Tesla, SpaceX, and xAI. Yet its need for capital (from $4 to $5 trillion, depending on how you count), equipment, expertise, and a skilled workforce are extremely vast. Meeting the aforementioned needs is quite literally impossible within a realistic timeframe. Here's why.

A question of capital

Money is the most obvious challenge for Elon Musk's chip venture. To build 1 TW of AI silicon per year, Elon Musk's TeraFab will need to process the equivalent of 22.4 million Rubin Ultra GPU wafers per year, 2.716 million Vera CPU wafers per year, and 15.824 million HBM4E wafers per year, according to estimates from premier semiconductor analysis firm Bernstein. To do so, TeraFab will need from 142 to 358 fabs, the report claims.

Bernstein's calculations are based on a top-down conversion of compute demand into semiconductor manufacturing requirements. They start with Musk's goal of 1 TW of annual AI compute and translate it into the number of AI racks needed, using assumptions about Nvidia's rack power (e.g., 120 kW to 600 kW), GPUs per rack, and system architectures similar to Nvidia’s Blackwell and Rubin platforms.

They then convert those systems into chip, wafer, and fab demand using fixed assumptions for die sizes (e.g., ~825 mm² GPUs, ~800 mm² CPUs), HBM configurations, and yields. This is where Bernstein's analysis gets a bit rough: The firm assumes the capacity of a modern fab is 50,000 Wafer Starts Per Month (which is too high for a leading-edge logic fab, and too low for a DRAM fab) and that it costs $35 billion to build (which is not enough for a 50K WSPM logic fab, but may be too high for a DRAM fab). These assumptions increase the estimated costs of the whole project; while the ballpark of several trillion seems to be correct, $5 trillion may be too high.

A modern leading-edge logic fab (or rather, phase of a fab) typically has a production capacity of around 20,000 wafer starts per month (WSPM), so this facility completes roughly 240,000 wafers per year, assuming stable operation and no major yield or downtime losses. Assuming that CPUs and GPUs are made using the same node, then to produce these logic processors (on 25.116 million wafers per year), one would need 105 leading-edge wafer fabs, provided a roughly 100% yield and no downtime.

For context, TSMC shipped 15.023 million 300-mm-equivalent wafers in 2025 — the foundry's biggest year ever — which includes millions of outdated 200mm wafers and 300mm wafers processed on legacy process technologies.

A modern leading-edge 2nm-class logic fab costs roughly $25 billion to $35 billion. And while the economies of scale drive costs down, we are still talking about a $30 billion ballpark per fab, which means about $3.15 trillion for logic fabs alone, assuming there are near 100% yields and no production disruptions.

Keeping in mind that TeraFab will be a new kid on the block, it's unrealistic to expect its yields will be close to 100%; assuming instead an 80% yield, more capacity will be needed, bringing the logic fab number to 126 and the total capacity investment to $3.78 trillion. To put the number into context, TSMC currently operates between 35 and 50 300mm fab modules that have been constructed across several decades.

Memory fabs are cheaper than logic fabs and have higher capacities due to the nature of the DRAM market, but we are still talking about tens of billions of dollars per fab. A modern DRAM fab usually has production capacity between 100,000 and 200,000 WSPM, which means that with a mid-point capacity of 150,000 WSPM, one will need around 9 fabs to produce 15.824 million HBM4E wafers.

That being said, for HBM memory, effective capacity is significantly constrained by yield, stacking, and packaging, not just wafer starts. As a result, while a DRAM fab may process hundreds of thousands of wafers per month, only a fraction of that output can be converted into high-end HBM, which is why memory may become a bottleneck. In any case, with a 70% yield for HBM, we are still talking about at least 12 fabs each costing at least $20 billion, or $240 billion in total.

Bear in mind that the figure covers front-end wafer capacity only. To put this enormous cost into context, the Big Three DRAM makers (Samsung, SK hynix, and Micron) currently operate three dozen DRAM fab modules built since the early 2000s.

2.5D and 3D packaging facilities are fairly expensive, though at $2 - $3.5 billion per phase, clearly cheaper than logic fabs. Yet keeping in mind that TeraFab will need tens, or maybe even hundreds, of advanced packaging facilities to integrate AI processors and assemble HBM stacks, the company will need to invest hundreds of billions in advanced chip packaging.

In total, it looks like TeraFab must invest well north of $4 trillion to meet Elon Musk's goal of producing AI chips that would consume 1 terawatt of power per year, not including land acquisition, development of process technologies, software development, and ecosystem buildout. Yet Bernstein's calculations are even more aggressive as analysts from the company believe that investments in TeraFab will be around $5 trillion.

Raising $5 trillion would be extraordinarily difficult. For context, even the largest companies like Nvidia, Apple, and Alphabet have market capitalizations of $4.34 trillion, $3.71 trillion, and $3.5 trillion at the time of writing, so Musk would need to mobilize capital exceeding the value of the world's most valuable corporations. It's hard to imagine private fundraising, a consortium, or even a sovereign deal of this scale.

Perhaps the only way for Elon Musk to fund this initiative is to apply at once for multi-government backing, sovereign wealth funds, and hyperscalers, as well as seeking support from capital markets. While an application for government support, per se, does not hurt, it is extremely unlikely that he will get such funding. After all, the onshoring trend in the semiconductor industry limits to one the number of governments likely willing to invest in TeraFab. Yet even the U.S. government will find it hard to invest $5 trillion, given the country's annual budget of around $7 trillion.

Equipment and raw materials supply chain

At a scale of $5 trillion in the semiconductor industry within a foreseeable timeframe, constraints would extend well beyond capital and would include limited availability of equipment, construction materials, raw materials, and a sufficiently large, skilled workforce to build, operate, and maintain TeraFab's futuristic fabs.

A modern 3nm-class logic fab with a capacity of 20,000–30,000 WSPM requires 80 – 100 DUV + EUV lithography scanners, hundreds of baking and developing tools, hundreds of etching tools, hundreds of deposition tools, and over 100 metrology and inspection tools, as well as hundreds of other tools that process wafers.

In addition, a fab uses thousands of various utility subsystems (pumps, generators, chemical delivery systems, specialty gas delivery systems, etc.) that make things happen. Exact fab configurations are unknown, and many tools are clustered with multiple process chambers, so the tool count understates the number of actual processing modules. DRAM fabs use fewer tools because it is easier to make memory than logic. Nonetheless, we are still talking about thousands of litho, deposition, metrology, and inspection tools per fab.

Since leading-edge logic process technologies are particularly lithography-intensive (even though some EUV multi-patterning sequences may be substituted by machines like Applied Materials' Centura Sculpta), let's assume that a TeraFab logic fab will need 100 DUV + EUV lithography systems, which means that 126 of these fabs will need 12,600 lithography tools for logic. For context, ASML shipped 48 EUV and 131 ArFi DUV scanners in 2025 (for a total of 179 fabs), up from 44 EUV and 129 immersion DUV machines (173 in total) a year before.

As a result, it will take ASML 70 years at its current production rate to equip TeraFab with lithography scanners for logic production alone (not counting scanners for DRAM manufacturing), and that's only if it exclusively supplies them to Musk's company.

ASML has been gradually increasing its output of EUV and ArFi DUV scanners for some time, as these machines are exclusively used for advanced nodes by companies like TSMC. That being said, ASML's production capacity depends not only on its own production capacity, but also on the production capacity of its suppliers, as the company integrates tens or even hundreds of thousands of components into every scanner. Increasing TSMC's output meaningfully is hard, but it is even harder to increase the output of all its suppliers. Getting 12,600 lithography tools in a short amount of time is quite literally impossible.

Also, keep in mind that ASML currently employs 44,000 people. If it needs to assemble 70X more litho systems (assuming it gets enough components), it will probably need to increase its headcount to match the scale of a Foxconn or Walmart, rather than a semiconductor tool company.

The same applies to other suppliers of wafer fabrication equipment: They can produce a limited number of tools, and their suppliers can make them a limited number of components. Therefore, getting millions of process chambers in a few years is simply impossible.

Finally, getting enough raw materials of perfect purity required for leading-edge chip production for a venture that is larger than Intel, Samsung, and TSMC combined (and we're not even talking about memory here) will be problematic, as they will have to expand their supply chains as well. Still, it should be easier than scaling production of lithography tools.

Time is not on their side

Now that we've mentioned capital and supply-chain challenges for a semiconductor venture of Terafab's scale, it's time to talk about the thing that has driven multiple chipmakers out of business in recent decades: leading-edge process technologies.

Developing a modern, leading-edge fabrication technology requires billions of dollars and a lot of time, and while Elon Musk tends to raise enough money for his projects, time is something money cannot buy.

Development of a new leading-edge process technology is a 5+ year effort that begins with pathfinding, materials research, and transistor architecture exploration. Once the transistor architecture is figured out, engineers run countless simulations to model key physical effects such as doping profiles, strain engineering, and leakage behavior to tune these characteristics in a bid to achieve their design specifications for the whole node. This is arguably the only step in process technology development that can be licensed. For example, Rapidus licensed a 2nm GAA transistor design from IBM. Imec and CEA-Leti can also license some of their transistor-related technologies, but that's about it.

Once the transistor concept is finalized (or licensed), the real work begins: Engineers must construct hundreds of tightly interdependent process steps across FEOL, MOL, and BEOL modules. These steps cover everything from transistor formation to interconnect and metallization, as well as require atomic-scale precision in deposition, etch, lithography, and annealing. Every stage involves hundreds, or even thousands, of tunable parameters, all of which must be optimized for yield, performance, power efficiency, defectivity, and long-term reliability — a process that depends heavily on accumulated expertise, rather than licensable IP.

After individual steps are stabilized, integration becomes the primary challenge. Engineers combine modules — such as gate stacks and source/drain structures — into a logical process flow and tune sequencing and thermal budgets to avoid contamination and material degradation. On paper, this sounds like an easy task, but this integration phase effectively defines the node; it must be done in a development fab, and it cannot be outsourced or licensed.

Once device performance and yield targets are achieved in the development fab, the process must be made usable for chip designers through PDKs, SPICE models, and validated standard-cell libraries. All of these take hundreds or thousands of engineers and a lot of time.

Finally, the process technology must be transferred to a high-volume manufacturing fab, which introduces another layer of complexity. Achieving stable, high yields in a production environment is a long, iterative process that requires experienced engineering teams and continuous refinement. Even with abundant funding, this stage cannot be accelerated easily.

As a result, the key question remains whether a company that starts its semiconductor efforts from scratch can realistically complete this entire cycle — from concept to mass production — within five years. Rapidus will demonstrate whether it is possible in 2027, when it intends to start trial production of chips on its 2nm-class fabrication process.

It will be the 2030s before TeraFab can actually output chips using its own manufacturing technologies. Theoretically, if Tesla, SpaceX, and xAI have limitless demand for AI processors, TeraFab could potentially license process technologies from Tesla's foundry partners, though it remains to be seen whether production nodes can indeed be licensed and integrated in a reasonable amount of time into an existing fab.

The workforce shortfall

To meet Elon Musk's 1 TW of compute per year goal, TeraFab must operate over 150 fabs (well, fab modules, or phases) and plenty of advanced packaging facilities. These fabs and facilities must be built by people, and as TSMC discovered with its Fab 21 phase 1 in Arizona, qualified construction workers are hard to find. Finding people who will run these fabs is even harder.

A leading-edge fab employs between 4,000 and 7,000 construction workers on site at peak, depending on the scale. When we talk about the full build cycle, there are usually 10,000 or more workers involved; for example, TSMC expects 40,000 construction jobs to be created as a result of its expansion in Arizona. To complete Fab 21 phase 1, the company had to send 500 additional workers from Taiwan, perhaps because local workers were unfamiliar with TSMC's procedures.

The 150+ fabs required by TeraFab will necessitate hundreds of thousands of construction workers, which will inevitably create a labor bottleneck, especially for highly specialized workers required for cleanroom and sub-fab systems.

Once the fabs are built, they will need employees with very specific skills. All leading-edge fabs are highly automated manufacturing facilities, but they still employ thousands of people to manage, serve, and maintain them. TSMC's 20,000 WSPM Fab 21 phase 1 currently employs around 3,000 people (which includes plenty of management roles that will not be required for subsequent phases), whereas Intel's 40,000 WSPM Fab 52 has created 3,000 high-tech manufacturing jobs and 3,000 tool technician jobs in the area, along with thousands of indirect jobs.

Even assuming that next-generation advanced fab modules will require just 1,500 employees, Elon Musk's venture will need over 300,000 highly skilled people. To put the number into context, TSMC had 83,825 full-time employees serving in various capacities as of December 31, 2024. Where TeraFab can find 300,000, and whether this can be done at all, is hard to fathom.

Reality check

Elon Musk's TeraFab aims to produce AI logic chips and HBM memory, consuming 1 TW of power per year, which requires trillions of dollars and hundreds of fabs, which is far beyond current industry capacity in terms of capital, supply-chain capabilities, and skilled workforce availability.

Beyond capital, equipment constraints are severe, as ~100 fabs would require 12,600 lithography tools, while ASML shipped only 179 scanners in 2025, and there is no way it can scale up production within a reasonable timeframe.

Process technology development remains a 5+ year effort that involves hundreds of tightly integrated steps, extensive simulations, and yield optimization that cannot be licensed or accelerated easily, even with access to partners like IBM or imec.

Finally, TeraFab would require hundreds of thousands of construction workers and over 300,000 skilled employees.

Given all the capital and supply-chain limits, the project in its current form looks quite unrealistic at full scale. Yet if this is an element of partial vertical integration that will be used to make some of the chips that Tesla, SpaceX, and xAI require in-house, then why not? Perhaps Musk's real goal is far less ambitious: success for his other ventures, rather than wholesale transformation of the entire global semiconductor market.

A bipartisan group of U.S. Senators is urging the government to take immediate action to halt the sale and export of Nvidia GPUs and server systems to China and southeast Asian countries, in the wake of the recent revelations around the Super Micro smuggling scandal.

U.S. Senators Jim Banks (R-Ind.) and Elizabeth Warren (D-Mass.) have penned a letter to U.S. Commerce Secretary Howard Lutnick disputing Nvidia's claims that it was unaware of GPUs and servers being diverted to China— part of an opereration to dodge sanctions on the lucrative technology.

Nvidia continues to deny any awareness of or involvement in the scheme and claims to be in strict compliance with American export regulations.

This represents a major roadblock for Nvidia and its front-and-center CEO, both of which have made major efforts in recent months to re-open the Chinese market for Nvidia GPUs. This now sets the U.S. Senate and Nvidia in opposition; where the White House comes down on this issue will be at the whim of Secretary Lutnick and the ever-mercurial President.

To the letter

“We urge all necessary and appropriate actions, including the immediate pausing, suspension, or other reconsideration of all active export licenses covering advanced Nvidia AI chips and server systems destined for . . . China as well as for intermediaries in south-east Asia, including Malaysia, Thailand, Vietnam and Singapore," the letter reads, as reported by the Financial Times.

This letter is particularly notable for its bipartisanship. Senator Warren is a one-time presidential hopeful and one of the leading progressives within the Democratic Party. She's also the leading Democrat on the Senate Banking Committee. In contrast, her fellow letter signer, Jim Banks, is a staunch Republican, having voted against stimulus checks during the Coronavirus pandemic; he has previously called climate change a left-wing hoax.

Despite their differences, the joint letter drives right at the heart of recent efforts by Nvidia and its CEO to restart GPU shipments to China. This comes after most of 2025 was spent with them effectively banned while America and China warred over global trade and used access to GPUs and critical minerals as cudgels with which to beat one another.

After months of wrangling, the U.S. finally approved export licenses for Nvidia's last-generation H200 Grace Hopper GPU systems in December, with only the Chinese authorities then needed to approve the imports. That had started to happen, with Huang stating just over a week ago that the first orders from Chinese companies had started to appear.

Then the Super Micro story broke, and now the whole scheme is threatened by this letter from U.S. Senators. For its part, Nvidia claims to have been unaware of the scheme and that it follows all regulations to the letter.

"Strict compliance is a top priority for Nvidia," the company said in a statement to Tom's Hardware. "We continue to work closely with our customers and the government on compliance programs as export regulations have expanded [...] Nvidia does not provide any service or support for such systems, and the enforcement mechanisms are rigorous and effective.”

Although that would seem to distance Nvidia from any concerns, this may be only the beginning of its problems. The letter doesn't just call for a halt to exports, but hints that CEO Jensen Huang may have misled lawmakers when previously discussing GPU diversions.

Nvidia under fire

In the letter, Banks and Warren highlight that as part of Huang's 2025 lobbying efforts to allow the sale of its high-end GPUs to China, he rejected the idea that GPUs were being diverted there from other territories to get around trade restrictions.

Huang reportedly told lawmakers that because Nvidia customers were aware that diversions of chips were not legally permitted, they “monitor themselves very carefully."

The Senators highlighted these and other statements by Nvidia executives as “materially false or misleading." If such statements affected licensing controls, then those controls should be reconsidered, they said.

"American export controls exist to protect American national security. They only work if the companies subject to them follow the law and meaningfully, aggressively monitor their supply chains. We are concerned that the recent Supermicro indictment raises serious questions about Jensen Huang’s public assurances.”

Huang's claims may be under scrutiny, as there is public evidence of Nvidia's abilities to track where its graphics processors end up. Although it denied claims from China that it had kill-switches, or active tracking hardware on the GPUs themselves, Nvidia has admitted that telemetry data can allow it to estimate the location of a GPU.

Since there is a trackable latency between an Nvidia GPU sending a message to Nvidia servers and then receiving the response, Nvidia can make a guess of where in the world it might be.

If that truly is the case, how could it not know GPUs planned for one territory or country were being diverted to another?

Contrasting export and import laws

The letter also raises serious questions about the heavy contrast in U.S. export and import legislation. The Commerce Department said in response to the letter that selling Nvidia's H200 GPUs to China, “under controlled conditions, will strengthen the American technology ecosystem." And yet at the same time, the administration recently placed extreme restrictions on Chinese imports of drones and foreign-made routers.

On Monday this week, the Federal Communications Commission said it would no longer certify Wi-Fi routers manufactured outside the United States. It didn't single out China, but the measure will prohibit the sale of routers in the United States if they are manufactured in China. Similarly, the FCC has blocked the sale of next-generation Chinese drones in the United States. Although it has since allowed older models from manufacturers like DJI to be sold, the overall ban is still in place ahead of planned trade negotiations between the U.S. and China in early April.

Despite this heavier hand on other aspects of trade with China, the route for Nvidia GPU sales currently remains open, though this new letter may ultimately change that.

Nvidia also faces another potential roadblock in the form of the Chip Security Act. Set to be voted on by the House foreign affairs committee as soon as this week, it would require location tracking on all advanced AI chips to make diversion far more difficult.

Consider how cagey China was when it merely thought Nvidia GPUs had tracking hardware on board. If Nvidia is forced to add such equipment to its hardware, the company's prospective sales to China may face a far more serious roadblock.