ByteDance and Tencent each took delivery of roughly 10,000 Nvidia H200 accelerators in recent weeks, and a handful of other Chinese tech groups may soon receive approvals of similar size. The deliveries are the first meaningful movement of the chips into mainland China since President Trump cleared their export in December, but they arrive under strict oversight from China’s National Development and Reform Commission, which approves each purchase individually.

Most of each company's U.S.-licensed allowance, understood to be up to 100,000 units apiece, must stay outside the mainland, largely in Hong Kong. Measured against the 400,000-plus units that ByteDance, Alibaba, and Tencent were collectively approved to buy in January, the chips now on the mainland amount to roughly 2.5% of the order book.

Two licensing regimes

Trump approved H200 exports in December last year, in exchange for a 25% cut of every sale to the U.S. Treasury, and terms formalized in January require each chip to pass through US territory for third-party inspection before re-export. The Commerce Department moved license applications to case-by-case review on January 16 and had cleared roughly 10 firms by mid-May, including Alibaba, ByteDance, Tencent, and JD.com, with Lenovo and Foxconn approved as distributors.

In response, China built the NDRC’s per-purchase approval process from scratch to mirror the Commerce Department’s case-by-case license review. The 10,000-unit mainland allocations function as quantity caps, the very instrument that U.S. export rules have used since the first Hopper restrictions in 2022. The requirement to route imports via Hong Kong operates as an end-location condition, identical to Washington's demand that every chip transit U.S. soil for inspection.

The Cyberspace Administration of China summoned Nvidia last July over alleged backdoors in the H20. State media outlets subsequently ran a campaign calling the chip unsafe and outdated, and state-funded data centers were barred from foreign accelerators. Eight months of NDRC silence on H200 orders left Jensen Huang telling investors Nvidia's China market share had gone from 95% to zero.

DeepSeek’s training bottleneck

A transcript of DeepSeek founder Liang Wenfeng's May 20 closed-door investor meeting, leaked online in July, arguably explains why Beijing is letting any Nvidia silicon in at all. According to the document, whose authenticity DeepSeek hasn't confirmed, Liang told investors he wanted 200,000 Huawei accelerators to train a frontier model and received an allocation of 16,000, against total Huawei capacity of roughly 750,000 chips this year split across every Chinese AI company, a constraint he reportedly expected to persist for around three years. The remarks circulated widely enough that DeepSeek paused a fundraising round targeting a roughly $71 billion valuation days after they appeared.

If we look at DeepSeek’s production history, it appears to match the numbers Liang cited during the meeting. lab's attempts to train its R2 model on Huawei Ascend hardware failed repeatedly, and training moved back to Nvidia chips while Ascend accelerators handle inference. Per the Financial Times’ unnamed source, which broke the story of resuming H200 imports, domestic silicon increasingly serves inference, while Nvidia hardware still carries training.

The H200 obviously fills that gap nicely, with each unit carrying 141GB of HBM3e at 4.8 TB/s, delivering roughly six times the performance of the H20, and approaching the banned H100. A 10,000-GPU cluster is genuine frontier-training capacity, comparable to the builds behind the GPT-4 generation, though it represents a fraction of the 100,000-GPU-plus systems U.S. labs now run. That ratio seems to have been precisely calibrated by Beijing officials, large enough to keep flagship labs training their models, but small enough that inference stays a captive market for domestic chipmakers.

Domestic supply gaps

TrendForce's August 10 supply chain survey projects that domestic chips will take nearly 90% of China's high-end AI chip market this year, with domestic high-end shipments growing 83% year over year, a projection that TrendForce itself revised up from roughly 50% in its December outlook. Bernstein has recorded the same displacement from the other direction, with Nvidia's China share falling from 66% in 2024 to 40% in 2025 and a projected 8% this year.

Huawei planned to roughly double output of its 910C Ascend chip to about 600,000 units in 2026, against a total Chinese accelerator market that ran to roughly 4 million units in 2025, 2.36 million of them supplied by Nvidia and AMD. So, while domestic chips can cover the volume, they can't yet cover frontier training, making the 90% projection and H200 easing two halves of the same policy.

Washington's case for export controls rests on exactly the dependence these deliveries demonstrate: Four years into the restrictions, China's leading labs still can't train frontier models without American silicon, and Beijing has now conceded as much through its licensing decision.

The leaked transcript has Liang arguing that open access to Nvidia would make domestic substitution a much harder commercial proposition, meaning the controls themselves built the market Huawei and Cambricon now hold, and TrendForce's numbers show that market approaching 90% share three years after the first Hopper bans. This month's deliveries disprove neither side's theory, but Nvidia does bear the cost of both, with 500,000 chips reportedly in inventory, a 25% fee on anything that sells, and a Chinese market rationed to 10,000 units per buyer — admittedly, that’s better than zero.

SMIC posted its first $3 billion quarter earlier this month, with revenue up 36.1% year on year, net profit nearly tripling to $479.2 million. Co-CEO Zhao Haijun told analysts the next day that the Shanghai foundry will charge more for wafers processed in the third quarter after price negotiations concluded in the first. Utilization hit 93.7% against demand Zhao said SMIC can't fully meet, driven by Chinese AI data center buildouts that U.S. export controls have cut off from TSMC and Samsung at the leading edge. "Since there's still a big gap between industry-leading wafer prices and SMIC's current prices, we need to negotiate with customers for fairer pricing," Zhao said on the call.

The quarter blew SMIC's own out of the water on every front. The company had guided to 14% to 16% sequential revenue growth and a 20% to 22% gross margin; it delivered 20% growth to $3.01 billion and a 25.3% margin, up from 20.1% in Q1. Wafer shipments rose 14% quarter-on-quarter to 2.9 million 8-inch equivalents, blended selling prices climbed 5.7%, and Q3 guidance calls for a 26% to 28% gross margin. China accounted for 90% of revenue.

Demand isn’t coming from GPUs, however, with Zhao commenting that the surge came mostly from AI chips other than CPUs and GPUs, such as logic ICs, BCD power-management parts, and optical transceiver components, all in short supply. Meanwhile, growth in SMIC’s AI peripheral segment is expected to be around 40% for the quarter, while industrial and automotive chips rose to 16.5% of wafer revenue from 10.6% a year earlier.

From bust to boom

SMIC's utilization sat at 68.1% in the first quarter of 2023 and averaged 75% that year as net profit fell more than 60% and gross margin dropped 16.4 points to 21.9%. As late as early 2025, it was reported that SMIC and Hua Hong were cutting mature-node prices to defend share against a wall of new Chinese capacity. The company that spent 2023 and 2024 discounting into overcapacity spent 2026 raising prices by around 10% in December, negotiating targeted increases in capacity-constrained segments in February, and applying another round to Q3 wafers.

Export controls did most of the work, with Washington’s restrictions keeping China's AI accelerator demand away from TSMC. Beijing has been redirecting that demand inward: the government wants 70% of silicon wafers sourced domestically this year, and a Bloomberg Intelligence survey of 60 Chinese tech executives in June found firms plan to spend 46% of their AI accelerator budgets on local chips over the next 12 months, up from 30% now. SMIC is the only Chinese foundry that mass-produces 7nm-class logic, which makes it the sole domestic route to silicon for Huawei's Ascend line and Cambricon's accelerators. A protected buyer pool, along with a mandated shift to domestic supply and a single qualified supplier at the leading edge, produces a textbook seller's market.

Hua Hong, China's second-largest foundry, reported utilization of 102.8% in the same week, with record revenue of $717.5 million, up 26.8% year on year. TrendForce data shows foundry prices across China rose 5% to 15% between Q1 and Q2, with a third round of increases being prepared for the second half. TSMC is reportedly raising prices across all its advanced nodes too, so SMIC's hikes track a global trend, but SMIC is doing it from a captive position TSMC doesn't have: its customers have no other choice.

China's AI chip designers post record first halves

Cambricon's first-half revenue rose 108% to 6 billion yuan (c. $890 million) with net profit up 122.6% to 2.3 billion yuan, per its Shanghai Stock Exchange filing reported by the South China Morning Post. Moore Threads grew first-half revenue 147% to 1.74 billion yuan and cut its net loss by 96%, and Biren projected first-half revenue growth of more than 1,850% off a small base ahead of a Hong Kong IPO. Memory maker CXMT raised $8.6 billion in Shanghai's biggest-ever semiconductor listing last month and surged 466% on debut to become the most valuable company on any mainland exchange. Every one of these firms sits on the U.S. Entity List or depends on suppliers that do, and every one just posted record or near-record numbers.

Beijing had until recently been blocking Chinese imports of U.S. accelerators. The US approved around 10 Chinese firms to buy Nvidia's H200 in May, but China had been blocking the purchases to protect domestic suppliers. Under Secretary of Commerce Jeffrey Kessler told a congressional hearing on July 14 that "very few" H200s had actually shipped. Officials have relented as of August 19, with ByteDance and Tencent each having received around 10,000 H200 chips, the first meaningful deliveries since the U.S. approved around 10 Chinese firms as buyers.

Some 20,000 delivered accelerators against Huawei's target of 600,000 Ascend 910Cs this year leaves Chinese cloud spending, which Goldman Sachs pegs at roughly $102 billion for 2026 in combined AI capex across Alibaba, Tencent, ByteDance, and Baidu, landing overwhelmingly on domestic silicon.

SMIC's 7nm yields and the HBM shortage

SMIC's leading-edge economics remain brutal, however, with industry sources cited by the Financial Times putting SMIC's 5nm and 7nm prices 40% to 50% above TSMC's with yields of less than a third, a consequence of running multi-patterned DUV on nodes designed for EUV. The wafers SMIC is repricing are overwhelmingly mature-node parts, where its cost position is sound; the advanced capacity that feeds Ascend production stays yield-limited and expensive per good die regardless.

Memory, not logic, caps accelerator output anyway, and SemiAnalysis estimates Huawei has been drawing down a stockpile of roughly 13 million Samsung HBM stacks acquired before the late-2024 controls, and domestic HBM from CXMT will cover only a fraction of 2026 Ascend targets.

SMIC's own profit surge also comes with a glaring asterisk: CFO Wu Junfeng said the near-tripling was boosted by a one-time gain from a subsidiary. Demand for its silicon rests largely on policy rather than proven end markets, with an analyst tally cited by Asia Times putting China's top 11 listed chip firms at a combined average of roughly 122 times projected 2026 earnings.

Japanese chemical maker Ajinomoto has reportedly told customers in mainland China that it will cut supply of ABF, the insulating build-up film that's used in nearly every high-end processor package, by 30%, according to a report from the Chinese outlet JW Insights, which cites unnamed supply chain sources.

If true, that would be painful for Chinese customers like Shennan Circuits, Xingsen Technology, and Shenghong Electronics, who rely on Ajinomoto's reported 95% global market share of the film. In contrast, China's self-sufficiency rate is thought to sit below 5%.

JW Insights attributes the cut to Ajinomoto prioritizing Japanese customers and core overseas accounts, which supply the FC-BGA substrates under Nvidia, AMD, and Intel accelerators, over mainland buyers. Whether or not the 30% figure holds up, the squeeze is well documented, and China's response was underway long ago.

A confirmed shortage

Ajinomoto's ABF production ran at roughly 2 million square meters per month at full utilization in the second quarter. The company has committed ¥25 billion (around $156 million USD) since 2023 to expand capacity by about 50% by 2030, and land purchased in Kani City, Gifu Prefecture, hosts a third plant not expected to come online until around 2032.

In the fiscal year ended March 31, Ajinomoto reported that ABF sales grew 25% with margins above 50%, and the share of its film going into servers and networking silicon reached 70%, up from 40% in fiscal 2017. According to Goldman Sachs, the gap between ABF substrate supply and demand will widen from around 10% in the second half of 2026 to 21% in 2027 and 42% in 2028.

Ajinomoto notified substrate makers in May of a roughly 30% price hike taking effect this quarter, two months after UK activist fund Palliser Capital disclosed a top-25 shareholding on March 31 and publicly demanded the company raise ABF prices by more than 30%. That hike is confirmed, even if the volume cut isn't. ABF material accounts for about 30% of a substrate's bill of materials, so the increase flows directly into the cost of every FC-BGA package built on it. We've been tracking ABF crunches since the shortage that constrained GPU production in 2021 and 2022, and the current cycle looks to be extending a pattern that's already hit BT resin substrates and T-glass cloth, where single Japanese suppliers also dominate.

China has three films in qualification

Huazheng New Material's CBF, developed with the Shenzhen Institute of Advanced Electronic Materials, is the most mature of China's three named alternatives. The film uses a modified epoxy resin with spherical silica filler, which routes around Ajinomoto's IP rather than copying it. According to reports coming from Chinese media, its mass-production yield sits at above 85%, with reliability testing reportedly having passed inside Huawei Ascend systems and validation underway at Xingsen and Shennan Circuits. Huazheng's first production line of 3 million square meters per year is said to be running at full utilization, and a second line doubling that is slated to come online at the end of 2026.

Lotus Holdings, best known in China as a producer of MSG, acquired 51% of Shenzhen Newface, the developer of NBF, in April for roughly ¥103 million. Newface is said to have qualified all products below nine build-up layers, with nine- to 11-layer films in development and validation underway at Taiwanese substrate makers. Ajinomoto itself is a food and seasonings company that derived ABF from its amino acid chemistry in the 1990s.

Hongchang Electronics' GBF, co-developed with Taiwan's Jinghua Technology, has been validated at a leading domestic OSAT and is in small-volume trial production, with scale-up targeted for the fourth quarter. All three films face the same challenge of downstream reliability qualification taking one to three years of thermal cycling, damp-heat aging, and electrical testing, often longer than the R&D itself, and the highest layer-count films under flagship AI accelerators remain unmatched domestically. Upstream inputs, including specialty resins and spherical silica filler, are themselves partly import-dependent.

Huawei's Ascend packaging sidesteps ABF

Huawei's Ascend 910C reportedly connects two compute dies on separate silicon interposers through an organic substrate, an approach SemiAnalysis has described as trading die-to-die bandwidth for yield and cost against Nvidia's CoWoS.

That architecture makes Huawei less dependent on the high layer-count ABF-based FC-BGA substrates that Nvidia's B200 and GB200, AMD's MI300X, and Intel's accelerators sit on, and Chinese reporting seems to position Ascend as the anchor qualification target for both CBF and GBF. Cambricon, Biren, Moore Threads, and Alibaba's T-Head, which package on conventional FC-BGA, are directly exposed to any mainland ABF supply disruptions.

China banned exports of dual-use items to Japanese military-linked end users back in January through Ministry of Commerce Announcement No. 1, following Prime Minister Sanae Takaichi's November remarks on a Taiwan contingency, with measurable fallout. Chinese exports of restricted rare earths to Japan fell roughly 51% year-over-year in the first half of 2026, Nikkei Asia reported, and Japan imported just 13 tons of dysprosium in the period, down 82% from two years earlier, per TrendForce.

Ajinomoto's move to cut ABF supply to China eight months later has obvious retaliatory optics, despite every account of the alleged cut attributing it to capacity allocation under AI demand. China's rare-earth controls have so far targeted materials where China holds the leverage, and ABF is a market where it holds none.

Meanwhile, BOE signed a three-year glass substrate agreement with Corning in May and designated glass-core packaging a strategic business in July, and Lens Technology announced a through-glass-via collaboration with Intel the same month, extending China's push into glass substrates as the longer-term route around Japanese film.

A glass core swaps out the middle layer of a substrate, but the chip package still needs insulating film built up on either side, so glass doesn't remove the need for ABF or its substitutes. None of China's glass projects has reached mass production either. Until that changes, China's answer to the reported cut depends on whether Shennan, Xingsen, and Shenghong qualify their domestic films.

Chinese AI accelerators are set to capture 90% of the country's domestic market as U.S. export controls and Beijing mandates push American-made hardware from AMD and Nvidia out of the market, according to a new report by TrendForce. Cambricon and Huawei are expected to be the biggest beneficiaries of the shift, according to DigiTimes. Yet, the big question is whether Chinese vendors can ship enough AI accelerators to satisfy demand.

China on track for AI accelerator self-sufficiency

Nvidia commanded 66% of China's AI accelerator market in 2024, but its share dropped to 40% in 2025 and was on track to drop to 8% in 2026, according to estimates made by Bernstein investment bank earlier this year. Considering the fact that Nvidia did not officially ship any new accelerators to Chinese clients in the first half of the year, Nvidia's chief executive Jensen Huang said in May that his company's market share in the PRC was 'zero.' Of course, some Nvidia GPUs make it to China 'unofficially' as local companies are too dependent on Nvidia's CUDA and high-end AI accelerators. Still, it is safe to say that the bulk of new deployments in the PRC are based on hardware designed and produced domestically.

China's total available market of AI accelerators topped 4 million units in 2025, according to numbers published by Guancha.cn. Last year, 2.2 million Nvidia AI GPUs made it to the Chinese market, and while Nvidia's market share shrank to 55%, it still significantly outperformed its closest rival, Huawei, which shipped 812,000 AI accelerators and commanded 20.3% of the market.

Shipments by other players were by far lower: Alibaba's T-Head produced 265,000 AI accelerators, followed by AMD with 160,000. Cambricon and Kunlunxin only supplied around 116,000 AI processors each, whereas others shipped fewer than 100,000 units.

"This year, the Chinese government has actively encouraged the adoption of domestic AI chips," the report from TrendForce reads. "This policy push will likely provide priority support to high-potential domestic players, allowing them to substantially expand their market share in China's high-end AI server market. At the same time, the domestic ecosystem is maturing in key areas such as advanced foundry nodes, advanced packaging, and thermal management."

The firm now expects shipments of high-end AI processors developed by Chinese companies to increase by more than 83% year-over-year in 2026 as domestic production capacity and deployments expand. As a result, its analysts project domestic AI accelerators to capture nearly 90% of sales (up from 45% last year), which means that foreign suppliers like AMD and Nvidia will be left with roughly 10%. This latest projection represents a major revision from the research firm's December 2025 outlook, which estimated that Chinese processors would account for approximately 50% of China’s high-end AI chip market in 2026.

Dual-track strategy

As AMD and Nvidia supplied some 2.36 million AI accelerators to the Chinese market last year, commanding a 59% unit share, replacing the majority of them will take a lot of effort, assuming that the TAM will remain at around 4 million units. TrendForce claims that China is set to adopt the so-called dual-track strategy, which involves AI accelerators from merchant suppliers like Huawei and Cambricon along with custom AI ASICs from Alibaba, Baidu, ByteDance, and Tencent.

"Together, these developments are moving China's AI infrastructure away from its heavy reliance on foreign GPUs, toward a dual-track model of 'domestic GPUs + proprietary ASICs,'" the firm claims.

Hyperscale cloud service providers (CSPs) are inclined to expand usage of their own silicon because it is cheaper compared to merchant accelerators and because it is optimized for their workloads and data formats. Meanwhile, developers of merchant AI hardware — such as Huawei, Biren, and Cambricon — will also gradually expand their output of accelerators as demand is very strong.

Bottlenecks

It remains to be seen whether the Chinese chipmaking industry can indeed replace 1.96 million high-end AI accelerators in just one year. To maintain the 4 million unit TAM, China's semiconductor industry will need to increase AI accelerator output by 2.2X in just one year.

SMIC — China's largest and most advanced foundry — this week announced that its Q2 2026 revenue increased to $3.005 billion, up from $2.505 billion in Q1 2026, and from $2.209 billion in Q2 2025. This suggests that the company is both increasing the output of chips and its prices. However, it remains to be seen whether SMIC's 36% YoY revenue increase is an indicator that it can increase output of high-end AI accelerators by over 2X compared to 2025.

Another major bottleneck for the Chinese industry is the lack of domestic production of high-bandwidth memory (HBM). Huawei has reportedly acquired plenty of HBM2-class memory from Samsung, but its stock is not endless, so its Ascend 950-series AI accelerators are set to rely on proprietary HiBL 1.0 and HiZQ 2.0 types of memory, not industry-standard HBM2 or HBM3. While China's DRAM champion CXMT is gearing up for HBM3 manufacturing in late 2026, it remains to be seen how quickly the company can ramp up production to decent levels.

Nvidia's CUDA software stack is the company's biggest advantage after the performance and versatility of its AI accelerators. But while performance can be matched with brute force, the software stack cannot be reproduced quickly. Last year, Huawei opened up its CANN software stack to accelerate its development, though we do not know if the company has achieved its targeted goals with this. Yet, without a doubt, China's AI software stack is getting more mature every year, so many new AI deployments may indeed rely on domestic stacks rather than on CUDA.

A shifting market

U.S. restrictions on exports of advanced AI accelerators, combined with China's own efforts to limit the use of American AI processors domestically, have largely pushed companies like AMD and Nvidia out of the Chinese market. Analysts now expect China-based independent hardware vendors to control 90% of the domestic AI accelerator market in 2026.

Chinese AI hardware has come a long way, and Huawei's solutions can outperform Nvidia's NVL72 GB200 rack-scale system, albeit while consuming more power. Therefore, if power is not a concern, Huawei can build AI data centers with performance that matches or exceeds those based on Nvidia GPUs.

However, replacing American GPUs almost completely while maintaining AI accelerator unit TAM at 4 million units will require China's industry to product 1.96 million AI accelerators in 2026, 2.2X more than in 2025. This seems impossible not only for TSMC, but also for local memory makers that still have to start making HBM memory.

To that end, while Chinese AI accelerators may indeed capture 90% of the domestic market, without hardware from American companies, that market can shrink dramatically in terms of units.

The global data center optical interconnect market is expected to reach $144.4 billion by 2030, up from $13.7 billion in 2024 — a 48.1% compound annual growth rate (CAGR) — according to a China Insights Consultancy (CIC) report commissioned by a Chinese laser-chip maker, Yuanjie Semiconductors, as part of its Hong Kong IPO filing. The report draws on data from LightCounting and interviews with industry experts. Of that future market, silicon photonics, the practice of manufacturing photonic chips from the same silicon material and mature CMOS foundry processes used for conventional semiconductors, is projected to account for 63.7% of revenue, its share climbing from 16.6% in 2020 as the industry shifts toward denser, more power-efficient designs like co-packaged optics.

The moves that would turn those projections into reality are already well underway. Over the past year, the AI industry has invested more than $15 billion in co-packaged optics, photonic chips, higher-speed transceiver modules, and fiber, developing new integration techniques, acquiring photonics startups, and forming alliances among the biggest players. More recently, OpenLight and Tower Semiconductor placed OpenLight's photonic design kit inside Cadence's mainstream chip-design software. This step makes the laser-integrated 400G and 1.6T chips at the heart of co-packaged optics easier to design and bring to market.

The tech behind the numbers

For decades, data centers have relied largely on copper traces and cables to move data across circuit boards, within racks, and across clusters. Copper is cheap, reliable, and easy to integrate. However, its power consumption and signal losses increase sharply with bandwidth and distance. As AI data centers are packed with ever more powerful GPUs, shuttling enormous volumes of data and pushing networks toward higher speeds, copper hit a wall. Past a few hundred gigabits per lane, its usable reach collapses to a meter, or two, before signal loss and power draw become unmanageable.

The solution has been a transition to photonics, moving data as light instead of electrical signals. An optical transceiver converts electrical signals from switches and processors into laser light, sends it down a fiber, and converts it back at the far end, carrying far more bandwidth over greater distances at much higher speeds. Today, pluggable transceivers pack a laser chip, digital signal processor (DSP) chips, and several optical components into one compact module. As GPUs grow more capable and AI workloads swell, both the volume of data and the speed it must travel keep climbing, pushing the industry from 400G links to 800G to 1.6T and beyond

At the same time, the industry is trying to move the optics closer to the compute. In conventional systems, GPU signals travel inches along copper traces across the board to reach the transceiver on the faceplate. At extreme data rates, even that relatively short electrical journey consumes considerable power. Co-packaged optics (CPO) fixes this by pulling the optical engine out of the pluggable module and placing it as a chip — the photonic integrated circuit (PIC) — directly on the switch or accelerator package, shrinking the electrical path to millimeters. The push for faster optical chips, aiming for terabits-per-second speeds, serves both CPO and the pluggable modules that remain the industry mainstay.

The PIC does everything but generate light. Because laser chips are highly sensitive to heat, they can't be folded into the PIC, which, in co-packaged optics, becomes part of the switch or accelerator package that runs extremely hot. Therefore, the laser stays a separate chip. Whether feeding a co-packaged PIC or a pluggable module, those laser chips are always needed, which is exactly what Yuanjie, the company that commissioned the CIC forecast, makes.

The PIC itself is where silicon photonics comes in. Photonic chips were once built entirely from costly III-V materials in specialized fabs; Silicon Photonics (SiPh) instead patterns the optical circuitry onto silicon using the same mature, high-volume CMOS processes as ordinary chips — saving money and time and making PICs mass-producible. On the other hand, silicon cannot lase. As a result, laser chips still rely on the more expensive III-V method, using materials such as indium phosphide. Circumventing exactly that is the aim of the recent OpenLight–Tower platform. Their approach integrates III-V laser material directly with silicon photonics at the wafer level, aiming to bring the laser into the same scalable manufacturing flow as the rest of the PIC.

The numbers behind the growth

Together, the different photonics technologies solving the AI data transfer bottleneck are driving a huge market in the industry. CIC projects the data center optical interconnect market growing from $13.7 billion in 2024 to $144.4 billion in 2030, a compound annual growth rate of 48.1%, more than a tenfold increase in six years. Growth accelerates over this period, with the steepest gains occurring after 2027. The report breaks down the three main ways: technology, use case, and data rates, each showing where the spending and resulting revenue are concentrated.

By technology, it splits the market between silicon photonics and everything else. SiPho's share climbs from 16.6% in 2020 to 63.7% of total revenue ($91.9 billion) by 2030, with its revenue compounding at 68.5% annually, compared with 32.6% for the rest, and the crossover past half the market landing around 2027. According to CIC, silicon-based optics— primarily PICs — will grow to become the default.

The use-case breakdown shows which parts of data center networking are driving optical demand: scale-up inside the rack, scale-out across a data center, and scale-across between data centers. Scale-up — the short-reach links from servers and chips to the top-of-rack switch — takes the lead with a 561.5% CAGR in revenue. Note that this figure compounds off a near-zero 2024 base, where a tiny absolute gain reads as an absurd percentage. Scale-across follows at 108.5% and scale-out at 42.7%, while the entire non-AI segment, traditional workloads from telecom to enterprise servers, trails at 37.5%. However, in actual revenue and not growth, scale-out is the largest tier at $64.5 billion in 2030, followed by non-AI at $40.2 billion and scale-up, for all its headline growth — at just $32.1 billion, with scale-across last at $7.6 billion.

The data-rate breakdown captures a generational migration of speed. In 2024, the market still ran on the previous two generations, 400G at $5.9 billion and 800G at $4.5 billion, with legacy 200G-and-below links adding another $3.3 billion and the faster tiers barely registering. By 2030, that order is inverted. 1.6T, only entering commercial deployment in 2026, becomes the single biggest segment at $65.6 billion, expanding at an 867.3% CAGR from a 2024 base of essentially zero; 3.2T, a category that didn't exist in 2024 at all, appears only from 2027 and still vaults to $44.5 billion. Together, those two next-generation speeds make up roughly $110 billion of the $144.4 billion total. The rest slides down the ladder: 800G stays healthy at a 34.8% CAGR to $26.7 billion, but 400G flatlines — 1.0% annual growth to $6.3 billion, after leading the prior cycle at 75.3% — and 200 G and below actively contracts, shrinking 15.4% a year.

The moves behind the numbers

While the CIC figures are just projections, the actual moves happening in the industry point in the same direction. Over roughly the past year, more than $15 billion has moved through silicon photonics. Nvidia invested $2 billion each into Coherent and Lumentum — makers of the lasers and optical components that go inside transceivers — in March, followed by $2 billion into Marvell and a $500 million warrant deal with fiber maker Corning, each bundled with multi-year purchase commitments. Meanwhile, Microsoft, Meta, and OpenAI have teamed up with hardware giants Broadcom, AMD, and Nvidia to establish an Optical Compute Interconnect (OCI) Multi-Source Agreement (MSA) group to develop protocol-agnostic scale-up interconnection technology for AI clusters.

On the mergers-and-acquisitions side, Marvell, before the Nvidia investment, closed its $3.25 billion cash-and-stock acquisition of Celestial AI, a photonic interconnect startup, to gain its Photonic Fabric platform for linking chips optically inside the rack. Meanwhile, Ayar Labs, which builds optical I/O chiplets that move data directly off the compute package, raised a $500 million round at a valuation of roughly $3.75 billion. Elon Musk also received regulatory approval to acquire Mesh, an optical transceiver manufacturer.

Those bets converge on co-packaged optics as the architectural prize. Nvidia's Spectrum-X and Quantum-X photonics switches, built on TSMC's COUPE process, are the flagship deployments. Broadcom is pushing its own CPO Tomahawk line and has foundries TSMC and GlobalFoundries, with Tower supplying the silicon underneath. The one constraint the money cannot instantly buy away is the laser: high-speed III-V sources remain the scarce link, with Lumentum currently the only vendor shipping the 200G-per-lane EMLs that 1.6T modules require at volume. That scarcity — and the whole industry's dependence on laser chips regardless of which design wins — is exactly why a supplier like Yuanjie sits aligned with wherever the market goes.

SemiAnalysis made the case for near-packaged optics (NPO) in a three-part thread posted to X on August 10, describing the architecture as an interim solution for the industry's transition from pluggable transceivers to true co-packaged optics (CPO) and crediting it with three advantages: field-replaceable modules, a failure blast radius confined to a single socketed unit, and simpler assembly, since the optical engine is packaged separately from the switch ASIC.

Just two months ago, SemiAnalysis published a research note pushing its CPO volume expectations out to 2027 for scale-out networks and 2028 or 2029 for full-scale production, subsequently knocking 17% off Applied Optoelectronics stock and roughly 8% off Lumentum in a single session and drawing a public rebuttal from rival analysts.

NPO is the architecture that stands to gain if that pessimism proves right, with Broadcom having shown a 3.2T VCSEL-based NPO product line at OFC 2026 in March, and six connector and optics firms forming a standards group the same week to define a common socket for this class of device.

NPO vs CPO and pluggable optics

A front-panel pluggable transceiver sits 15cm to 30 cm of copper trace away from the switch ASIC, and the DSP that cleans up the signal after that journey draws 6W to 8W of a typical 800G module's 14 to 17W budget. CPO reduces that distance to millimeters by mounting the optical engine on the same package substrate as the ASIC, thereby eliminating the DSP. Per Broadcom, this enabled a 70% reduction in optics power for its co-packaged Tomahawk switches, and Nvidia's figures for a 1.6T link show per-link power falling from around 30W to 9W.

NPO splits the difference by moving the optical engine off the faceplate to sit beside the ASIC, close enough to shorten the electrical path and drop the DSP, but on its own engine substrate instead of the ASIC's package. The module mates to the board through a socket, so the engine can be pulled and replaced in the field in the same way that a pluggable can; an engine reflowed onto a CPO substrate can't. SemiAnalysis's January CPO deep dive defines NPO as an optical engine co-packaged onto a separate substrate that "remains socketable."

Linear pluggable optics (LPO), the other interim architecture in circulation, takes the opposite route by removing the DSP but leaving the optics in a standard front-panel module, cutting power to roughly seven to 8.5W per 800G port at the cost of reach and interoperability headaches, while leaving the optical engine on the faceplate rather than moving it next to the ASIC.

Serviceability and yield

A soldered CPO substrate has no rework path because removing a reflowed, underfilled engine means applying solder-melt temperatures of 220°C to 260°C millimeters from the ASIC and every other engine on the package, and the sub-micron fiber alignment inside the engine itself doesn't survive a second thermal excursion. One dead optical engine therefore condemns the switch ASIC, the substrate, and every other engine attached to it.

SemiAnalysis's June note ran the numbers for a hypothetical 32-engine package. At a 95% attach yield per engine, compound yield lands near 19%, or roughly one good assembly in five. GlobalSemiResearch published a point-by-point rebuttal arguing the calculation freezes yield at a single pessimistic snapshot and ignores screening, binning, and the spare engines Nvidia designed into Spectrum-X for redundancy.

Meta presented reliability results at OFC 2026 indicating co-packaged optics can beat pluggables on failure rates, and Broadcom said its CPO systems logged more than 1 million cumulative 400G-equivalent port-hours in Meta testing without a single link flap.

Lasers, historically the highest-failure optical component, sit outside the package in both architectures: the OIF's ELSFP standard, published in August 2023, defines a hot-swappable external laser module that CPO and NPO designs both draw on. Modulators, photodetectors, and fiber attach stay inside the engine, so a failure in any of those means either swapping a socketed module or scrapping a soldered one.

Shipping products and roadmaps

Nvidia's Quantum-X Photonics InfiniBand switch, which entered production deployments this year, carries 144 ports of 800G across 18 silicon photonics engines mounted on detachable optical sub-assemblies, with 18 removable external laser modules feeding them. Nvidia markets the design as CPO, but engines that unbolt from the package and lasers that slide out of the faceplate are the serviceability properties SemiAnalysis assigns to NPO. The Ethernet counterpart, Spectrum-X Photonics, is due in the second half of this year at up to 512 ports of 800G.

Broadcom runs both architectures side by side. Its 51.2T Bailly CPO switch has been in volume production at system partner Micas Networks since 2024, its 102.4T Tomahawk 6 Davisson began customer deliveries in October last year; and at OFC 2026 it added the 3.2T VCSEL-based NPO line as a separate offering aimed at buyers who want density without the soldered commitment.

Foxconn Interconnect Technology has had solderless LGA-to-LGA sockets and pluggable laser-source cages for Bailly in full production since May last year, and Ciena, Coherent, Marvell, Molex, Samtec, and TeraHop launched the Open CPX MSA at OFC 2026 to standardize a socketed optical-engine interface covering both NPO and CPO. LightCounting CEO Vladimir Kozlov, quoted in the MSA's launch release, put the stakes at "annual port shipments projected to top 100 million" within five years, against fewer than 1 million co-packaged and near-packaged ports in 2025.

TSMC's COUPE optical engine entered mass production this year in its first-generation pluggable form, with the 6.4T co-packaged second generation targeted around 2027 and a third generation moving optics inside the processor package itself. If those dates hold, NPO's run as the interim architecture lasts two to three years. If SemiAnalysis's 2029 scale-up timeline proves closer to reality, however, NPO carries the volume for the rest of the decade, adding demand to a photonics supply chain that's already short of lasers and packaging capacity.

The PCIe 6.0 specification was ratified in early 2022, but its actual implementation was delayed for years. Now, the spec is almost ready, with the first PCIe Gen6 platforms finally approaching, as are actual storage devices. Micron was the first with a PCIe 6 SSD in mid-2025, and Samsung caught up this July. Meanwhile, independent makers of SSD controllers — Marvell, Phison, and Silicon Motion — are also prepping their PCIe 6 SSD platforms.

For a full roadmap of PCIe, you can check out our dedicated page. In this article, we'll specifically focus on PCIe 6.0 controllers and devices and how they're soon becoming commercial products. For additional reading, you can also find our interview with Solidigm VP Avi Shetty, which covers the subject of PCIe 6.0 SSDs.

Per ardua ad astra

PCIe 1.0 through 5.0 used simple NRZ signaling (one bit per signal) with 128b/130b encoding, which was relatively simple to implement at the controller level. However, it required some complicated methods to ensure signal integrity at 32 GT/s per lane.

PCIe 6.0 now adopts PAM4 signaling (which encodes two bits per symbol using four voltage levels), which keeps the physical signaling rate at 32 Gbaud. However, it also doubles the effective transfer rate to 64 GT/s by transmitting two bits per signal instead of one. As a result, transmitter and receiver design became considerably more complicated, as it required sophisticated DSPs, equalization, FEC, and CRC-based retry mechanisms, which complicated the development of PCIe 6.0 controllers. Furthermore, PCIe 6.0 often requires retimers where PCIe 5.0 did not, which complicated the development of actual servers.

To make matters even more complicated, every new PCIe generation requires interoperability testing among CPUs, GPUs, SSDs, network cards, switches, retimers, and other devices from dozens of vendors. Since PAM4 behaves very differently from NRZ, PCI-SIG had to develop entirely new compliance procedures, test equipment, and interoperability programs. The development of those programs themselves slipped, which greatly delayed any commercial deployment. The very first PCIe 6 interoperability testing at 64 GT/s took place in late July.

Despite formidable implementation hurdles and interoperability program challenges, PCIe 6 is finally making its way into commercial platforms. AMD's 6^th Generation EPYC 'Venice' and Nvidia's Vera CPUs fully support PCIe Gen6, so companies from the adjacent industry sectors are catching up with their PCIe 6 products, and storage makers are among them.

For storage, PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link without the protocol's overhead (which is not that big with the 1b/1b 242B/256B FLIT encoding featured by PCIe 6). The new interconnect does not improve flash operation on its own. Meanwhile, PAM4 introduces Forward Error Correction (FEC), which slightly increases latency, but it also enables doubling throughput without doubling the signaling frequency to 64 Gbaud.

As a result, PCIe Gen6 generally delivers better bandwidth-per-watt than what an equivalent 64 Gbaud Non-Return-to-Zero (NRZ) implementation would have required. Given that modern data center deployments (particularly for AI) tend to be large, a greater bandwidth-per-watt metric should always be welcome.

In this story, we will summarize what the first breed of merchant enterprise-grade PCIe Gen6 controllers from three popular vendors will offer, and what we already have on the market from Micron and Samsung.

Marvell Bravera SC6: 500TB or more of speedy storage

Matt Murphy's appointment as Marvell CEO in 2016 marked one of the most dramatic strategic shifts in the semiconductor industry. Marvell transitioned from being a large merchant chip supplier to a company almost exclusively focused on data infrastructure, and that transformation had significant implications for its storage controller business. Storage still complements the broad data-center portfolio alongside networking, custom silicon, switching, compute, and optical connectivity. However, gone are the days when storage was a major priority for Marvell. Yet, Marvell's Bravera SC6 (MV-SF1410) looks to be quite a significant contender for the PCIe 6 storage market.

The Bravera SC6 controller is powered by 15 Arm cores in total, including 12 Cortex-R82 cores arranged in two six-core clusters, three Cortex-M7 cores, and a dedicated Cortex-M3 secure processor. The controller is NVMe 2.2 compliant and features a PCIe 6.0 x4 host interface, thus potentially offering a maximum of 30.25 GB/s of throughput.

The MV-SF1410 controller features 16 NAND channels, eight chip enables (CE) per channel, and support for SLC, MLC, TLC, and QLC 3D NAND with an up to 3600 MT/s interface. The part also supports Marvell's sixth-generation NANDEdge technology with LDPC error correction, a hardware RAID engine, end-to-end data protection, 5 MB of SRAM, and a 64-bit DDR5 interface with ECC. The security subsystem of the Bravera SC6 supports AES, SHA, RSA, and elliptic-curve cryptography (which seems to be among the industry's firsts), enabling compliance with Trusted Computing Group (TCG) security standards.

One of the things that strikes the eye about the Bravera SC6 is that its interfaces support data transfer rates of up to 3600 MT/s. While this speed bin seems a bit outdated now that 4800 MT/s devices have been announced, in eight- or 16-channel configurations, a 3600 MT/s transfer rate with raw bandwidth of around 3.6 GB/s per channel (38.8 GB/s and 57.6 GB/s in total, respectively) is more than enough to saturate a PCIe 6.0 x4 interface (30.25 GB/s without the overhead).

Another notable thing is that Marvell has not publicly disclosed the controller's maximum addressable NAND capacity or logical unit number (LUN) it can support within each CE, so we cannot derive an actual maximum addressable capacity or maximum usable capacity from the public specification we have at hand*. But we can make some useful estimates. The SC6 has 16 NAND channels and eight chip enables per channel, or up to 128 CE positions in total.

With upcoming 2 Tb 3D QLC NAND dies, each die stores 256 GB. Kioxia/Sandisk formally announced such devices last week, but did not disclose their availability timeframe. Since BiCS10 is aimed specifically at data center applications, Kioxia has indeed described this generation as suitable for very highly stacked packages, without disclosing the maximum number of NAND devices per package. Typical NAND packages carry between 1 and 16 NAND devices (though Kioxia/Sandisk probably meant more than 16 devices), though packages aimed at high-capacity drives tend to feature 8 or 16 devices. 16 2-Tb devices give 32Tb (or 4 TB) per NAND package.

If an SC6 implementation could populate 128 such package positions, that gives 512 TB of raw NAND memory. Of course, actual drives will have to reserve plenty of NAND for overprovisioning and other techniques required for reliability and longevity, so actual commercial SSDs will offer a lower capacity. However, they will remain in a 500TB-class. Meanwhile, if the SC6 can address 32-die packages, then we are talking about petabyte-class SSDs. Yet, 32-die NAND packages may require something other than formal controller support.

Marvell says that it will start sampling its Bravera SC6 (MV-SF1410) with its partners sometime in Q4 2026, which means that the first drives featuring the chip will hit the market in late 2027, but more likely in 2028. Given that actual SSDs featuring the controller are so far away, Marvell even refrained from disclosing the expected performance of these products and only told us to expect "multi-gigabyte-per-second throughput, millions of random IOPS, deep queue parallelism, and highly efficient DMA-based data movement."

*A CE may select a package containing many dies, and each die may contain multiple LUNs. To address all those dies and LUNs efficiently, the controller must be architected appropriately. If the number of supported LUNs is lower than the number of LUNs featured by all-flash devices in all-flash packages, this will affect performance and parallelism, which will lower the appeal of such drives for data center operators.

Phison X3: Up to 2PB of storage at 28.8 GB/s

Phison has yet to make a big formal announcement of its X3 — aka PS5303 — SSD controller, but it was demoed at both CES and Computex this year. At CES, the company only showcased concepts of its PCIe Gen6-based drives, whereas at Computex it showed off reference drives, clearly suggesting that it is in the final stages of development.

The Phison X3 (PS5303) is the company's first-generation PCIe 6.0 x4 enterprise SSD controller, and it happens to be specifically aimed at data center applications, which include AI, cloud, and hyperscale deployments. Normally, Phison would introduce an eight-channel controller that would target both high-end desktop, workstation, and server applications. But such controllers have not yet surfaced.

The X3 is a 16-channel and NVMe 2.3-compliant controller, which Phison rates for up to 28 GB/s sequential read and write performance, 6.8 million random read and write IOPS, and approximately 4 GB/s per watt, which doubles the performance and efficiency of the company's PCIe 5.0 enterprise controller. Keeping in mind that its current-generation controller is made on TSMC's N12 manufacturing technology, whereas the X3 is produced on the N4 fabrication process, this improvement is expected.

Perhaps the most intriguing specification is support for SSD capacities of up to 2 Petabytes, which likely suggests that the controller has been designed with multiple future generations of dense 3D NAND flash memory in mind.

The controller supports OCP Datacenter NVMe SSD Specification v2.6, advanced enterprise security features including TCG Opal 2.3, DOE, IDE, Caliptra, and CNSA 2.0, as well as 64 SR-IOV physical functions for storage virtualization.

Phison has indicated that reference designs — E3.S, E1.S, etc. — are expected to sample this November, while volume production is anticipated in 2027, if everything proceeds in accordance with the plan. If the company succeeds, the X3 (PS5303) will be one of the first merchant PCIe 6.0 SSD platforms intended for next-generation storage infrastructure in 2027. Then again, it usually takes a year before sampling and availability of the actual drives.

Silicon Motion's SM8466: A mystery at 28 GB/s

Silicon Motion was probably the first company to reveal many of its details about its PCIe Gen6 plans in an interview with Tom's Hardware in June '25, then a leak with some details about its PCIe 6.x SSD controller emerged in July '25. After then, SMI kept it pretty much close to the chest about the SM8466 unit, but let us recall what we know about the controller both from our interviews and from the leaks.

Silicon Motion's MonTitan SM8466 is the company's 2nd-generation enterprise-grade controller that is projected to support 16 NAND channels, next-generation TLC and QLC 3D NAND, NVMe 2.x, OCP enterprise SSD specifications, and enterprise security technologies such as TCG Opal, Secure Boot, and SR-IOV virtualization, based on our interviews with the company as well as leaks.

Just like its direct rival from Phison, the SM8466 is rumored to offer 28 GB/s of sequential throughput and 7 million random IOPS, though no official claims have been made so far. Just like the Marvell controller, the SM8466 supports SCA and other features of modern enterprise-grade SSD platforms.

Perhaps the most surprising part of the specification is support for SSD capacities of up to 512 TB, which clearly falls short of the 2 PB capacity advertised by Phison's competing PCIe 6.0 controller. Then again, this is based on leaks and rumors, rather than official information.

Now that we know something about PCIe Gen6 SSD platforms from Marvell, Phison, and Silicon, let us recall what is already on the market, or about to hit it.

Micron's 9650: First and furious

Micron's 9650 is the industry's first PCIe 6.0 x4 SSD that is based on an in-house controller and the company’s 276-layer G9 3D TLC NAND with a 3600 MT/s interface. The drive delivers up to 28 GB/s sequential reads, 14 GB/s sequential writes, 5.5 million random read IOPS, and 900,000 random write IOPS. Depending on the exact SKU, the drive offers up to 25.6 TB of storage.

Since the 9650 is aimed purely at AI servers based on Nvidia hardware, Micron has optimized the SSD for peer-to-peer PCIe 6.0 communication with Nvidia Blackwell GPUs using retimers and switches to enable storage to feed accelerators without CPU involvement.

Micron started sampling its 9650 back in Q3 2025, so by now this drive is likely already available to interested parties.

Samsung's PM1763: 16 TB at 28 GB/s

Samsung has never announced sampling of its first-gen PCIe 6.0 x4 SSD, but it officially began mass production of its PM1763 drive this July. The PM1763 drive is based on a proprietary controller made using Samsung Foundry's 4nm-class fabrication technology as well as Samsung's ninth-generation V-NAND.

When it comes to capacity, the PM1763 is offered in 4TB, 8TB, and 16TB capacities. The flagship 16 TB model delivers up to 28.4 GB/s sequential read and 21.9 GB/s sequential write speeds, though the company hasn't disclosed the random performance of either SSD. Then again, to maximize performance, the drive's design is optimized for direct-to-chip (D2C) liquid-cooled servers (Samsung has not divulged details, though).

When it comes to power efficiency, Samsung claims the drive delivers more than 1.8X higher power efficiency than its predecessor and enables it to sustain peak performance during prolonged AI training and inference workloads. Unfortunately, without hard numbers, we can only take Samsung at its word.

In addition, the SSD supports post-quantum cryptography (PQC) algorithms to help protect against future quantum computing attacks, as well as the TEE Device Interface Security Protocol (TDISP) to secure data movement in virtualized server environments.

According to Samsung, the PM1763 has completed validation for next-generation AI platforms and is positioned as a storage solution for an AI data center near you.

Almost across the line

After years of delays caused by the transition to PAM4 signaling and the resulting ecosystem-wide validation effort, PCIe 6-class storage is finally approaching commercialization.

While Micron and Samsung already offer PCIe 6.0 SSDs, merchant controller suppliers —Marvell, Phison, and Silicon Motion — are prepping their next-generation enterprise platforms with up to 16 NAND channels, throughput approaching 28–30 GB/s, and support for capacities ranging from 512 TB to as much as 2 PB.

The FCC is drafting a proposal that would expand its list of equipment and services covered by the Secure Networks Act to include imports of new-model optical transceivers manufactured in China, according to a TrendForce report. Although the specifics are still unknown, such as what exactly constitutes a Chinese company and what is considered a "new model," this import block could have far-reaching implications. It's likely to impact hyperscaler AI companies, which are investing heavily in optical interconnect technologies, seen by many as the next battleground in the race for advancing AI performance, latency, and efficiency.

That's thought to be the core reason behind this potential blockade. With Chinese optical module manufacturers thought to make up around 56% of the global manufacturing capacity for this key technology in 2026, the U.S. administration wants to decouple U.S. reliance on this supply chain and strengthen its alternatives: Both domestic and international.

The long tail of this decision, however, could see the FCC refuse to authorize Chinese networking hardware entirely, following a ban on all foreign-manufactured routers in late 2025, and a ban on all advanced foreign-produced robotics in July this year.

Shifting bottlenecks

The story of the AI industry's rapid buildout in recent years has arguably been one of ever-changing bottlenecks and attempts to circumvent them. There are general GPU, CPU, and memory shortages that we've all had to contend with. But there have also been utility difficulties faced by hyperscaler companies, from power, to water, and local-infrasturcture.

There have also been more international key material bottlenecks, like shortages of glass cloth, of specialized PCB drill bits, and power inverters. Raw material shortages like helium, aluminum, and copper.

But those bottlenecks have also been felt within the servers within the data centers, too. And copper is a key feature there, because as modern data centers become ever more powerful, the new bottlenecks are the wires between them, more so than the raw speed of the processors or memory chips.

That's where optical interconnects come in. Designed to replace the simplicity, relative resistance, and physical limitations of copper wiring with lasers, optical interconnects can increase bandwidth, reduce latency, and reduce power consumption of existing networking hardware dramatically.

Although many of the world's largest optical interconnect developers, including TSMC, Intel, Samsung Foundry and Global Foundry, have different methods for the ways they plan to produce next-generation versions of these important networking interconnects, the underlying shift is much the same. Replace the bottleneck of copper wiring with optical communication lines and bring them as close to the processor as possible.

Within a few years, effectively integrating an optical networking interface into the chip itself, making latency all but disappear over distances up to several miles. That would allow for components to be located wherever they were best placed within a system, no longer needing to be near other components to reduce latency. That also allows for easy scaling up and out after deployment, as components from various servers could be co-opted as required. Multiple data center campuses within a few miles of one another could collaborate on particularly demanding workloads, too.

But at the moment China has a firm grasp on this emerging key technology, and the U.S. appears ready to respond with a heavy hand.

The ban and its impact

The FCC has banned the import of other products of specific types and from specific manufacturers before, but if it were to ban the import of optical transceivers, that would be the first time it had enacted such a measure. The term "new models" suggests such a ban would include the latest in interconnect technologies, including co-packaged optics (CPO) and near-packaged optics (NPO) integrated into network switches.

Although the U.S. may opt to deploy a transitional ban that only blocks the sale of new optical transceiver designs, leaving existing designs and contracts intact and saleable, it would still present a problematic disruption for American AI companies wanting to build cutting-edge data centers. China's optical module manufacturing, packaging, and testing are all key elements of the global optical interconnect supply chain, especially since a key raw material, indium phosphide, relies heavily on China's indium supply, with it controlling some 70% of the global market.

China restricted the export of indium in 2024, causing a reduction in global sales of the key material.

Even if the materials required can be sourced elsewhere, though, there's no suggestion U.S. manufacturing can scale up anywhere near quick-enough to respond, or indeed, at all. Key U.S. optical transceiver manufacturers, Coherant and Lumentum, are already running at capacity and are still around 30% overbought by their customers. A $2 billion investment from Nvidia will help, but the leaders there don't believe they'll be able to service the increasing demands of a hungry AI industry. Let alone if Chinese supplies are cut.

Nothing happens in a vacuum, except chip production

All of this assumes, too, that the Chinese authorities won't respond - and they certainly have a history of doing so. When America has restricted access to cutting-edge chips and chip design software, China has cut off raw material access. When the U.S. banned imports of Chinese hardware, China doubled down on investing in its domestic market and sources, as well as fighting to build friendly relations with other countries and markets.

That has already been happening in the optical interconnect space. In 2025, Chinese manufacturers only accounted for 16% of the global production capacity of electro-absorption modulated lasers (EMLs) and continuous-wave (CW) lasers. But in 2028, that capacity is expected to reach almost 28%. Will that additional production capacity go to help accelerate China's own domestic AI efforts, or will it end up being sold to major AI companies in Western markets?

It may be possible for Chinese suppliers and Western buyers to circumvent any new optical transceiver restrictions. Almost all the major bans and blockades from the Trump administration have included carve-outs for specific deals that can be struck — often seemingly at the whims of whatever official is involved in the deal-making. But they're there, and it may be that a phone call to the right person allows the right materials through, making any potential ban just the price of doing business.

But if not, it has the potential to put the brakes on the next phase of rapid AI infrastructure build-out that is making data centers more capable, campuses more efficient, and hinting at a future where even in consumer devices, the specific placement of components within them may no longer be constrained by the limitations of copper.

Apple used to be among a few companies willing to buy memory and other components worth billions of dollars under long-term supply contracts at fixed prices. But the artificial intelligence era represents a new reality with new purchasing champions, marking a tectonic shift in the high-tech world. Alphabet, Microsoft, Meta, and Amazon have purchase commitments totaling about $2 trillion, and a significant portion of these commitments are for memory, according to estimates by analyst Claus Aasholm. While the commitments are approximate, span many years, and should be generally taken with a grain of salt, they still reflect the direction the industry is moving.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

The public pushback against data center construction projects is only growing stronger, even as some protesting local residents have been arrested in the process. That hasn't perturbed those still standing against the AI infrastructure projects, though, and they continue showing up at town meetings, holding protest rallies, and making themselves heard — even with the 24/7 drone of a data center hum in the background.

The latest effort saw Nashville residents and local politicians move to block the construction of a $700 million data center set to be built right next to the Nashville Zoo at Grassmere. The city council approved a blocking measure last week, and now Mayor Freddie O'Connell will wield it to make sure the project doesn't go ahead.

This follows on from another recent story where a Kentucky farming family was offered 10 times their land value to sell up to data center developers, and they refused. Virginia's State Corporation Commission, which regulates public utilities, just ruled that data centers must pay for all the required transmission infrastructure that they have exclusive use of, in an effort to reduce energy bills for residents.

Nobody wants to live near a data center

Data center projects have been firmly disliked by large bodies of Americans since the beginning of this major AI buildout. Early in 2025, it became clear that even as the major AI companies were promising hundreds of billions for "AI factories," governments around the world rushed to build capacity. There was only one problem: residents near the proposed build sites would not be taking it lying down.

In April 2025, Elon Musk's Colossus data center was an early target for protest after it was found to be using permitless mobile gas turbines for power. It's been hit with enough pushback since then that SpaceX has now agreed to remove the 69 turbines it ultimately installed, although it is going to take over a year to complete the move of these allegedly mobile turbines.

By the Fall of last year, evidence had begun to mount about the negative impact of these installations. Water shortages and potential contamination, electricity price increases for residents, and the constant, unending noise that may be causing health problems with sub-audible frequencies.

There's also the slowly growing number of "against" voices in polling for new data centers. What started as a light advantage to the "supports" respondents in September became a near-majority a few months later. Now more than 70% of Americans don't want data centers near their homes, and there's little chance of that changing as the stories of issues during and after construction of these facilities continue to mount.

How the people are fighting back

Protest has been at the forefront of the anti-data center campaigners' playbook since the start, and that's not stopping any time soon. On one weekend in July, anti-data center protestors organized in 42 states to stage 142 protests across the country, all calling for blocks, halts, and moratoriums on the data center rollout.

This is after months of campaigning, which led to close to 70 jurisdictions around the country blocking new data center builds. Some of them, permanently.

Where politicians are more on the side of the developers, the people are going to meet them in person. They're going to town halls and seeking meetings and making their voices heard.

Sometimes politicians don't like that, and people are removed - even when protesting peacefully - and in several cases they've actually been arrested. Close to 40 people have been arrested in 2026 for pushing back against data center rollouts. In one case, because they went beyond their allotted speaking time, and in another, because they clapped following an impassioned statement by a fellow citizen.

In other cases, though, politicians are listening. In Nashville, the local council and the mayor are all on board to protect the local Zoo and residents' bills and ears. This is particularly important because it shows that local legislators can use their political power to block data centers — potentially preventing the White House from using its own to drive projects through.

The forever war

The data center builders aren't taking all of this helplessly. They have the ears of government and massive platforms to evangelize AI and data centers; They've been doing it everywhere from the White House to social media. They've tried building in more rural areas where there are fewer people to protest, paying for their own behind-the-grid power, and offering to spend millions in local investment to counter negative effects.

But it's not working. People don't like data centers. They don't want to live near them. And on top of that, many don't even like the technology the hyperscalers want to build this all for, anyway.

It's unlikely that those bankrolling (and hoping to make money on) the data center AI build-out will just give up and go home, but the residents fighting back against their gargantuan construction projects aren't going to do so either.

This is a long war, and one that neither side is likely to back down from. But in a rare ray of hope in 2026's landscape of high PC and electronics prices due to AI data centers soaking up computing hardware, it's one that the people seem to be winning, for now.

Anthropic has announced it's building an in-house chip development team to co-design its own custom ASIC processors for handling AI inferencing workloads. As described to Business Insider, Anthropic is starting to hire engineers to design the chips with an unspecified partner, and it looks set to do it at pace, with the job listing saying that any potential hiree would need to be ready to work to a schedule and get the chip design over the line.

This is just the latest major AI company to announce it's developing its own custom hardware. As the global economic shortages squeeze chip supply and models increasingly lean on optimizations to make workloads more efficient and potentially profitable, making custom silicon for your own data centers makes a lot of sense. Anthropic now joins the likes of Google, Meta, Microsoft, Amazon, and OpenAI in building their own chips for the job.

If you want something done right...

It's no secret that if you want to train an advanced AI model, you need Nvidia GPUs. Even Chinese AI developers, who have the ruling party leaning on them and limited access to Nvidia hardware, still use Nvidia GPUs — even if they have to smuggle them first.

But if you're looking to run AI to perform inferencing workloads for agentic and generative AI models, you can use a much wider array of hardware. Nvidia GPUs are good, but they're expensive — custom silicon can have a lower total cost of ownership of up to 65% — and power-hungry, and there are much more efficient options available. Chinese labs are using domestic Chinese hardware, and many Western AI developers have their own solutions; those that don't are making them.

Google has been building its Tensor Processing Unit (TPU) chips for 12 years, working with Broadcom to develop each generation. Amazon has its Trainium and Inferentia chips, and Meta recently announced several new MTIA designs for deployment through 2027. Microsoft has its Maia line, and Tesla recently pivoted to its AI5 and AI6 chip designs after years of developing Dojo.

And now Anthropic is getting in on the act, and for much the same reasons. Anthropic told Business Insider that it was co-designing the chips so that they would allow Claude to run faster and more efficiently at the scale its customers need. Indeed, Anthropic has seen explosive growth in the past year, seeing huge expansion in the consumer space and taking on significant government contracts — not to mention agentic AI requiring far more tokens than traditional single-prompt interactions.

Anthropic hasn't revealed which firm it's working with on the design and development. Although Broadcom and Marvell are the two largest companies in the ASIC co-design market, representing some 95% of it, The Information reported last month that Anthropic was in talks with Samsung for manufacturing.

The shovel sellers always benefit

Designing, packaging, and manufacturing your own custom ASIC for AI inferencing isn't cheap, and it isn't easy. Alongside developing the hardware, you need the software stack to utilize it, and you want models that are optimized to run on it to make the most of its potential advantages. That makes it more worthwhile for most companies to simply use other firms' hardware and more general-purpose GPUs. But for major AI companies with enough money to burn and the ability to scale up to maximize efficiency gains, it's well worth the investment.

But the AI developers aren't the only ones who benefit. Nvidia has been one of the few companies to make enormous profits from the AI boom, while the likes of Meta, Google, Microsoft, and OpenAI are all losing enormous sums of money on their AI efforts. There are very real winners from the custom ASIC design and build market, too: TSMC, Broadcom, and Marvell.

Broadcom has been Google's co-design partner for years, and was also recently tapped to help build OpenAI's inferencing chips. It also works with Meta on its MTIA design, as well as holding contracts for other custom ASIC designs with ByteDance and Fujitsu. It also produces strong interconnect and networking hardware, which allows it to offer customers a more complete solution. It claims to have a $73 billion backlog of orders to work through, and expects to generate over $100 billion in annual AI chip revenue by the end of 2027.

Marvell holds massive contracts with Amazon for its Trainium chips and Microsoft for Maia, and is expected to make upwards of $11 billion for these co-design jobs in 2026.

If Samsung ends up as Anthropic's partner, it would be a relatively small player in this particular space, but it would bring enormous manufacturing and chip design expertise to the table, as well as access to the all-important memory that is in such short global supply.

The biggest winner of all these initiatives, though, is arguably TSMC. The Taiwanese company produces the majority of the world's cutting-edge silicon and is involved in the production of almost all the chips discussed here. They need TSMC's CoWoS advanced packaging technologies for integration with HBM. It also handles much of the packaging of Nvidia's and AMD GPUs, as well as producing much of the underlying wafers.

Multi-polar chip world

Anthropic joining the custom ASIC race is hardly surprising and further cements the future we seem to be barrelling towards, which is each of the hyperscaler AI companies looking to handle as much of their inferencing with custom hardware as possible. It's more efficient, easier to control for features and specifications, and easier to scale up when optimized for internal models. From a Chinese perspective, it's also easier to avoid problems caused by international trade blockades and tariffs.

They'll likely never become 100% reliant on their own chips — there is just too much AI demand to scale into for that to happen, and Nvidia has been ruthlessly dominating access to the supply chain. But every new chip installed is an Nvidia GPU that won't be used for the same purpose, which may help reduce the stranglehold Nvidia has on the industry. Not for training, though. That's likely to remain Nvidia's biggest appeal for some time to come.

This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.

Here's a breakdown of each type of technology that the company announced.

• zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
• zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
• BV-NAND (aka Samsung’s 10^th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).

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zHBM: Placing HBM stack on top of logic

Around the time we first heard about HBM4's 2,048-bit interface, we read a 'semi-official' report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung's zHBM appears to be a continuation of that effort.

Samsung's zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the 'performance of HBM5', while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.

While Samsung's claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a 'next-generation interface system incorporating zHBM' will deliver 'approximately eight times the performance of HBM5,' it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as '8x higher bandwidth.'

Instead, the general term 'performance' may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn't reveal which die stacking/bonding technology it will use for zHBM.

In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.

For now, Samsung hasn't disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.

zNAND-O(on-device): Put storage close to compute

Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company's V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.

Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.

Since the technology is in development, Samsung hasn't shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions 'improved I/O performance and low-latency,' it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.

BV-NAND: Good old V-NAND gets a new treatment

With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.

Samsung formally announced its 400-layer-class V-NAND (aka 10^th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm² with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung's 10^th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk's BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.

Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.

Samsung's new brand strategy

As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.

Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company's new tech, like zHBM and zNAND-O, is years away.

Apple and OpenAI are heading to court in a clash of two of the world's largest and most well-funded companies. With teams of lawyers and bottomless pockets to fund them, these two industry titans are squaring off over claims of theft of trade secrets. Apple is asking the courts to block its former employees from revealing information to their new employer and limit OpenAI's development of an AI device based on Apple technology. Unsurprisingly, OpenAI denies any wrongdoing and is asking the judge not to disrupt its business activities.

"Apple's getting this wrong" is the name of the blog post OpenAI posted in response to Apple's lawsuit. Although it begins by calling Apple one of the greatest companies of all time, it goes on to call the legal action "sad," suggests Apple mixed up Asian employee names, and doesn't want its trade secrets anyway.

OpenAI went on to publish text message chains and email correspondence, suggesting it's keen to be tried in the court of public opinion more than any other setting.

Hey, that's mine!

Apple alleges that as many as 13 of its former employees may have passed along sensitive trade secrets to OpenAI, including sharing details of unannounced products and sharing screenshots of confidential Apple documents. This is an expansion of its original claims from July, when it alleged two former employees may have shared confidential information with OpenAI. It has now filed a concurrent motion seeking expedited discovery, demanded that two former employees, Chang Liu and Tang Yew Tan, sit for depositions, as well as key OpenAI employees and representatives of OpenAI's hardware division, io Products.

Apple is also asking for a preliminary injunction, which would bar former employees from accessing, acquiring, or disclosing any confidential information about the company as the case proceeds.

Considering a case of this magnitude, between two companies with effectively infinite money to spend protecting themselves, that could take months or years to resolve, that preliminary injunction is key and could mean the lawsuit does enough damage to be effective for Apple's goals.

Regardless, OpenAI is in full revolt over the process and has posted not only a damning denial of all claims, but some evidence it feels exonerates its position, too.

Getting ahead of the competition

The cynical argument for this lawsuit is that it means the two companies are battling it out in a courtroom instead of in the consumer retail space. Apple is first and foremost a consumer device company, and to date, OpenAI hasn't competed there. But it's planning to, and its various hires from Apple and elsewhere, including buying up Jony Ive's hardware company, suggest it's going to release something with the kind of smart consumer focus that is typically Apple's bread and butter.

Apple might have been a little late to the AI game, but that's played to its advantage. But if OpenAI were to use its strong mindshare, deep pockets, and advanced AI model design and inferencing compute base to offer something targeting mainstream consumers, it's stepping on Apple's toes. This lawsuit could be a way to stop that in its tracks.

That's not to say the lawsuit may not have merit. The entire AI industry has used aggressively expensive hiring practices to try to get ahead. Meta spent $15 billion on getting Alexandr Wang and ScaleAI's data, and AI companies are reportedly hounding promising students years ahead of graduation to lock them into future contracts.

If you're building a smart consumer device, though? Grabbing ex- or even current Apple employees wouldn't be a bad way to do it. Especially if they brought along information on unannounced Apple products that may or may not be related to an AI consumer device.

First to market matters, too. Although Apple hasn't shown any AI-first standalone devices yet, if it were planning to, slowing OpenAI down with these injunctions might be enough to let it catch up or even get ahead.

Clock's ticking

For now, the lawsuit is very much he-said, she-said. Both companies have enough money and resources to make this fight messy, but what they don't necessarily have is time. Especially OpenAI. It's on the hook for hundreds of billions in compute investment, has just cut the price of some of its models, and has yet to post anything close to a profitable quarter.

Apple isn't quite so constrained, but is also seeing its traditional consumer base eaten by rapidly appreciating electronics costs. Apple already sells its products at a premium. But what can it do if prices for components push its products out of the luxury affordable into the truly unaffordable?

That may not happen, but it's a future it has to consider as AI, and the money spent on its promised future continues to have an outsized impact on global economies. The outcome of this lawsuit is likely to leave a mark, too.

Following its massive $8.6 billion initial public offering (IPO) in July, ChangXin Memory Technologies (CXMT) began considering building its sixth DRAM fab in China to boost memory output in the coming years, Reuters reports. If all announced projects proceed as planned, the company's production capacity could more than double in the mid-term future, the report claims. Meanwhile, investment banker Dan Niles believes China could capture 30% of the DRAM market by 2030, according to P Equity Research.

Growing at a rapid pace

CXMT currently operates three 300-mm DRAM fabs: two near Hefei and one in Beijing's Yizhuang district. Unofficial reports claim that each fab is capable of processing around 100,000 wafers per month, so the company's output may be around 300,000 wafer starts per month (WSPM).

The company is pursuing an aggressive expansion strategy and is currently building additional fabs near Shanghai and Hefei, according to Reuters. The company's sixth fab will reportedly be located in Beijing's Yizhuang area, adjacent to its existing facility. Once these projects are fully operational, the company’s total manufacturing capacity could exceed 600,000 WSPM, which will double its current output, according to Reuters. Meanwhile, researchers from Citrini believe that CXMT could exit 2026 with a capacity of 350,000 WSPM, which is just 25,000 WSPM shy of what Micron targets by the end of the year. Citrini Research models that by 2030, CXMT will have production capacity of around 950,000 WSPM.

Building three big DRAM fabs is a big deal, from both financial and execution points of view. However, it is not a secret that virtually all fabs owned by Chinese companies are built using money from local and federal governments under the 'Hefei model,' which aims to transform cities into economic juggernauts by leveraging high-risk projects. So it is not surprising that both Shanghai and Beijing have provided financial assistance and other forms of support to attract CXMT to their regions, according to Reuters.

CXMT's existing Beijing fab, operated by Changxin Jidian, received backing from E-Town Capital and Beijing E-Town Technology, both affiliated with the Yizhuang development zone, according to a person familiar with the matter cited by Reuters. In fact, the district has evolved into a relatively major semiconductor manufacturing hub that already hosts CXMT, SMIC, Naura Technology, and Xiaomi, the report claims.

The right timing

The proposed fab would be located in Beijing's Yizhuang district, roughly 20 kilometers southeast of the city center, where CXMT already operates a 300-mm DRAM manufacturing facility. The planned production capacity and total capital investment for the project have not yet been disclosed, although Reuters points out that a leading-edge DRAM fab typically costs well over $10 billion.

Sources cited within the report said the company is seeking at least 60 million yuan ($8.9 million) in financial support from the Beijing Economic-Technological Development Area, and additional state-owned technology companies have also expressed interest in participating. Discussions remain preliminary, and neither the overall size nor the structure of the financing package has been finalized.

From CXMT's point of view, this is the right time for financial influxes as the company can sell all of its DRAM output at good prices to a variety of customers. Those being domestic PC and server makers (including Lenovo), and global brands such as Micron, Samsung, and SK hynix, which prioritize shipments of their DRAM output to the AI sector.

Apple, Dell, and HP have all reportedly qualified CXMT's memory and are ready to deploy it in their devices sold in China, while Acer and Asus have already begun to use DRAM from the Chinese maker. If CXMT signs long-term supply contracts with the world's leading PC makers, it is nearly guaranteed to sell out its output to these vendors in the coming years, which justifies investments in its expansion.

30% of DRAM market by 2030?

Dan Niles, founder of Niles Investment Management, believes that many investors underestimate how much share CXMT could capture over the coming years and how much share China may seize in the coming years.

His argument stems from historical DRAM market leadership shifts. In 1975, U.S. companies controlled 95% of the DRAM market, with Intel alone holding 75%. Japan then turned DRAM into a commodity business, increased its share to 80% by 1985, while the U.S. fell to 10% and then just 2% by 1990. Then South Korea repeated that playbook in the mid-1980s and eventually displaced Japanese suppliers, and today it accounts for roughly 62% of the global DRAM production.

With Micron's investments of hundreds of billions of dollars in U.S. DRAM capacity, the country is set to regain its massive presence on the global DRAM scene; China could capture 30% of the market by 2030, according to Niles.

China already consumes around 30% of global memory output, as it produces hundreds of millions of PCs and smartphones both for domestic and global consumption; it is reasonable to expect the country to produce as much commodity memory locally as possible. Keeping in mind China's push for semiconductor self-sufficiency and willingness to invest huge amounts of money in domestic fabs, it is possible to expect the country to rapidly gain DRAM output and share. China is already pushing its chipmakers hard to start DRAM production, and the government reportedly asked CXMT to share its process technologies with others.

Not that easy

There are multiple factors — both technological and political — that may, if not stop, but greatly slow down CXMT's and China's DRAM expansions in the coming years.

First up, there are export controls in place that prevent Chinese entities from getting sophisticated wafer fab equipment required to make DRAM using 18nm-class process technology or more advanced. If the proposed MATCH Act passes, then limitations on Chinese companies will get more severe, which will reduce their expansion ability.

Secondly, even if CXMT (or another Chinese DRAM maker) finds a way to produce more advanced DRAM using relatively outdated tools (i.e., use old tools for sub-16nm nodes), they will need to acquire those tools in quantity to increase their output. Meanwhile, companies like ASML have relatively limited production capacities, and CXMT is certainly not the only memory maker seeking to expand its production capacity in the coming years. While SMEE and SiCarrier are developing lithography tools in China, they will be unlikely to ramp up production of immersion DUV scanners to higher levels any time soon.

Thirdly, building fabs is one thing; operating leading-edge DRAM production at high yields is another. China has recruited engineers from Micron, Samsung, SK hynix, and TSMC for years, but scaling from three to six or more fabs requires thousands of experienced process, yield, device, lithography, and integration engineers. Building fabs adjacent to existing sites enables CXMT and other chipmakers to share experience and knowledge internally, which helps to develop experienced talent. But will it be enough for the long term?

Next, expanding wafer capacity alone is insufficient. DRAM producers must continuously migrate to finer process technologies (e.g., 16nm-class, 14nm-class, 12nm-class) to remain cost-competitive. If export controls delay access to equipment or materials needed for these nodes, Chinese fabs could end up producing more wafers at a higher cost per bit than competitors.

Finally, some American lawmakers want to prohibit U.S.-based companies from acquiring memory from CXMT and other Chinese vendors. They have every reason to believe that China wants to take control of a sizeable DRAM market share in a bid to use it in its strategic interest and have leverage over the market, something the country already has with rare earth metals. If the lawmakers manage to turn the proposal into law, demand for CXMT's and other China-made DRAM will drop. It will probably be sufficient inside China, but whether it will be enough to justify 10 or more big DRAM fabs is a different question.

We've entered a new phase of the AI industry's development, with all the major players heavily cutting costs and boosting the capabilities of their entry-level models in order to compete with new models from China, like Moonshot's Kimi K3 and DeepSeek's V4 Flash. OpenAI did so most recently, cutting the price of its base frontier model, ChatGPT 5.6 Luna, by 80% per million tokens, and its mid-range 5.6 Terra by 20%. This comes just over a week after Google introduced its more-affordable Gemini 3.6 Flash and 3.5 Flash-Lite models. Anthropic hasn't cut prices, but replaced its most-affordable Opus 4.8 model with a more capable Claude 5.0 at the same price point.

Intelligence is getting more affordable thanks to increased global competition, but this can come at the cost of margin for these major companies. This follows months of major AI businesses announcing cuts and limits on their use of the technology, even by major AI boosters like Elon Musk's xAI. Despite more workers using AI than ever before, productivity gains are reported to have been less than ideal.

Intensifying competition

The story of Chinese and American AI development efforts has been somewhat emblematic of the countries' historic strengths. While American firms burn through enormous amounts of money to push frontier technologies, Chinese developers have leveraged their industrial base to develop models that are cheaper, leaner, and almost as good at the top end.

DeepSeek gave Western AI developers a shock in 2025, and Kimi K3 did much the same in 2026. Alone, these events would cause concern for companies like OpenAI, Google, and Anthropic. Still, after months of companies that use AI heavily complaining about skyrocketing token costs, the news of an almost-as-good model at a much lower price really made a splash.

Now, the big AI developers can't just compete by throwing more parameters and training data at the problem. Now they're having to really compete on price, and to do it, OpenAI has massively reduced the price of its models. Not its most powerful and capable — the faster version of that is actually becoming more expensive — but models in its frontier range are now the cheapest they've ever been, and the timeline for this transition of intelligence and pricing is wild.

OpenAI launched ChatGPT 5.4 in March with powerful new agentic capabilities for $2.50 per million input tokens and $15 per million output tokens. GPT 5.6 Luna is now just $0.20 and $1.20, respectively. That's a less-than-four-month window for a frontier model to remain cutting-edge and priced accordingly.

These latest cuts bring Luna into the realm of DeepSeek V4, with its pro model costing $0.435 per million input tokens and $0.87 per million output tokens.

GPT 5.6 Terra is a more capable model, but after its 20% price cut, it's now $2.0 per million input tokens and $12.00 per million output tokens. That undercuts the headline-grabbing K3, which is $3.00 and $15.00, respectively.

Meanwhile, GPT 5.6 Sol remains $5 and $30 per million input/output tokens, and OpenAI has actually raised the price of its top model, with 5.6 Sol in Fast mode charging $10 and $60, respectively, to deliver the same kind of intelligence but at a lower latency — competing directly with other flagship frontier models like Claude Fable 5 and Mythos 5.

But is any of this actually going to make OpenAI any money?

Bills are coming due

After OpenAI announced that it was effectively abandoning its idea of owning first-party data centers earlier this year, the lease contracts it held with Neoclouds became more important than ever. Deals like the enormous $300 billion compute commitment with Oracle became paramount for the very existence of OpenAI's service as a company.

But if there were questions about how OpenAI would afford such a venture at the time, they're even more pronounced now. OpenAI is already losing money on its subscription-based accounts and missed key revenue targets earlier this year. And that's after losing 10s of billions in 2025, despite revenue rising consistently throughout the year.

OpenAI has committed to some $600 billion in compute spend by 2030. Even if revenue is rising, it might not be rising anywhere near quickly enough to cover these kinds of bills, and cutting the price of the most popular, affordable models suggests margins will either shrink dramatically or disappear altogether.

This may be why there's also a lot of talk of Nvidia backstopping OpenAI with a $250 billion investment. OpenAI is far from alone here, either. Google spent around nine times its cloud revenue on AI infrastructure over the past year, while Anthropic has only been able to post profits on annualized revenue recently because of a limited cut-price deal with xAI to rent its Colossus data center.

AI is not suddenly cheaper to run or cheaper to build for, and yet companies are slashing prices and making faster, more capable models available for less. On the surface, the numbers just don't add up.

Betting on Jevons Paradox

The AI industry often cites the Jevons Paradox when it comes to accelerating AI adoption and mass-market use. Where in Jevons' time making more efficient coal-powered engines resulted in more coal use, rather than less of it, AI developers claim that as AI use becomes more efficient, greater uses for it will be found, leading to greater overall use.

That may be the future that the token cost-cutting may be hoping to rush us towards. If tokens are cheap, people will use more of them overall, leading to higher earnings. Throw in next-generation AI accelerators becoming more prevalent within AI data centers towards the end of the year, and we could have 10x more tokens per watt, making slimmer margins more profitable by volume.

Then there's Vera Rubin to look forward to, which Nvidia claims will deliver another 10x increase in token performance efficiency. It is certainly possible that the advantages of Blackwell and Vera Rubin platforms will make AI a more potentially profitable industry for inference servers. But even then, it's hard to imagine the big companies covering anything close to their enormous investments with direct AI earnings. Especially as increasing competition drives down token pricing.

Lumentum CEO Michael Hurlston told an audience at the RAISE Summit in Paris earlier this month that indium phosphide, the compound semiconductor behind every laser in an AI data center, is heading into a supply squeeze worse than what we've already seen with DRAM / NAND, and that Nvidia's decision to fund Lumentum and its biggest competitor at the same time was a response to exactly that.

In his remarks, Hurlston said that telecom customers bought lasers in the hundreds, while Nvidia and the hyperscalers are asking for hundreds of millions. While Lumentum runs five indium phosphide fabs, it's still shipping more than 30% below what customers want. Nvidia's answer, in March, was to write $2 billion checks to Lumentum and Coherent, the two suppliers that, between them, make most of the world's high-speed datacom lasers, with purchase commitments and future capacity access attached to both.

"Between the two of us, I don't think we can service the demand that Nvidia and others are now putting on us to solve this resistance problem in the data center," Hurlston added.

Silicon doesn't emit light

Indium phosphide has a direct bandgap of roughly 1.34 eV, which lets it convert electrical current into photons efficiently. Silicon's bandgap is indirect, so it can guide, split, and modulate light but can't generate it. Every silicon photonics platform in production, including those of Nvidia, Broadcom, Marvell, and Cisco, still needs an indium phosphide laser somewhere in the package to supply the light for silicon to manipulate. Moving from pluggable transceivers to co-packaged optics changes where that laser sits and how it's mounted, but it doesn't remove it from the bill of materials.

Nvidia's marketing claims its photonics switches use four times fewer lasers than an equivalent pluggable deployment, alongside 3.5 times better power efficiency and ten times better network resiliency, all of which are vendor figures. Those savings are per port, and it's that port count that's exploding.

The high-end Spectrum-X Photonics configuration runs 512 ports at 800 Gb/s for 400 Tb/s of switching, and Quantum-X Photonics InfiniBand runs 144 ports at 800 Gb/s. Co-packaging also shifts the laser type toward high-power continuous-wave sources and external laser modules that feed multiple channels, which are harder to build than the electro-absorption modulated lasers inside a conventional pluggable. Coherent's Nvidia agreement covers that category of high-power CW lasers, external laser source modules, and fiber array units.

Capacity at Lumentum and Coherent

Lumentum posted record revenue of $808.4 million in its fiscal third quarter, up 90% year over year, with components revenue of $533 million and pump laser shipments up 80%. On the May earnings call, Hurlston told analysts the company expects its supply line to increase 50% measured from one December quarter to the next, and in the same breath said the supply-demand imbalance on EMLs had widened from the 25% to 30% given a quarter earlier to "somewhere greater than 30%," with pump lasers tighter still. A supplier growing output by half a turn per year and losing ground anyway is a clean measure of how steep the demand curve is.

Coherent's 6-inch indium phosphide line yields more than four times as many devices as its 3-inch line at less than half the cost, CEO Jim Anderson told investors on the company's fiscal Q3 call. Anderson said EMLs, CW lasers, and photodiodes are all in production on the 6-inch line with yields above the legacy 3-inch lines, and that internal capacity would double by the end of the June quarter, one quarter ahead of plan, then more than double again by the end of 2027. Coherent's revenue hit a record $1.8 billion, up 21%, with data center and communications now 75% of the total against roughly 41% a year earlier, and backlog stretching into 2028.

Logic and memory moved to 300mm wafers in the early 2000s. Indium phosphide is a brittle, expensive, small-boule material where the industry-wide upgrade currently underway is 3-inch to 6-inch, roughly the transition silicon completed in the 1980s. Lumentum's fifth fab, announced in March, is a converted Qorvo gallium arsenide plant in Greensboro, North Carolina, described as 4-inch and 6-inch compatible and ramping around 2028.

Running through China

Indium is recovered as a byproduct of zinc refining, so its output can't be scaled independently of zinc economics, no matter how much laser demand there is. The USGS Mineral Commodity Summaries 2026 put China at an estimated 760 tonnes of roughly 1,100 tonnes of global primary refined indium in 2025, about 69%, and recorded a 72% year-over-year fall in unwrought indium exports between September 2024 and September 2025 after Beijing placed the metal under export controls in February last year. The U.S. warehouse price averaged about $390 per kilogram in 2025 against $340 in 2024.

AXT's Chinese subsidiary Tongmei had to obtain Ministry of Commerce export permits, granted in June and August 2025, before it could resume shipping indium phosphide substrates out of China. The fabs Nvidia is funding sit downstream of that licensing regime, and the wafers going into them aren't made in the United States in meaningful volume.

DRAM contract prices rose 90% to 95% quarter over quarter in Q1 2026, the largest quarterly increase TrendForce has recorded, and the firm forecast a further 58% to 63% in Q2 with NAND up 70% to 75%. HBM is sold out for 2026. Hurlston is measuring his warning against a genuinely historic crunch, which makes it a strong claim rather than a throwaway one, and he runs a company whose valuation depends on the shortage persisting.

LightCounting's April 2026 market forecast puts current transceiver demand about 30% above supply, matching Lumentum's own figure, but states that the shortages should be gone by the end of 2026 and cuts expected Ethernet transceiver growth to 65% for the year after 82% in 2025 and 93% in 2024. Coherent, hitting its capacity doubling a quarter early, points the same way. The distinction from memory is that the fix here is a wafer-size transition already running in production with yields ahead of the old node, not a new fab that takes three years to build.

Reuters has named Shanghai Aishengna Electronic Technology Group as the state-owned company producing China's first domestic immersion deep ultraviolet lithography (DUV) scanners, a day after news of the program broke without identifying the manufacturer. Aishengna was established in August 2023 with RMB 7 billion, around $1 billion, in registered capital and is thought to have absorbed engineering teams from Shanghai Yuliangsheng Technology and Shanghai Micro Electronics Equipment.

Aishengna has been named by a single source who declined to be named, and its shareholders, SMEE and Yuliangsheng, didn’t respond to requests for comment. SMIC has been testing a Yuliangsheng immersion tool since September 2025, and first deliveries are slated for SMIC, Hua Hong Semiconductor, and ChangXin Memory Technologies.

Photoresist, coater tracks, and light sources

Tokyo Electron held an 89% share of the global coater/developer market in 2022, per Shared Research's analysis of the company's own disclosures, with its chief executive putting the figure near 90% and at 100% for EUV production. A scanner only exposes the wafer, however. It’s the track that's responsible for applying the resist film, baking it, and developing the pattern after exposure, and it has to be mechanically and thermally matched to the scanner in a single cluster, which is why the two are bought together. Shenyang Kingsemi has reached 28nm-class track capability and is currently targeting 14nm.

JSR, Tokyo Ohka Kogyo, Shin-Etsu, and Fujifilm hold a combined 72.5% of the ArF photoresist market, while Chinese suppliers hold under 1% of ArF immersion resist specifically. Nata Opto-electronic built a 25-ton ArF line, later expanded to 50 tons, passed customer qualification in December 2020, and completed project acceptance in 2024 with little volume to show for it. Xuzhou B&C says its ArF immersion products cover 45nm to 28nm and can stretch to 14nm, and chairman Fu Zhiwei has put mass production of China's core advanced resists five years out.

Cymer, Gigaphoton, and Coherent hold more than 80% of the ArF excimer laser market between them, and Cymer has been an ASML subsidiary since 2013. Beijing RSLaser shipped China's first high-power domestic excimer laser in 2018 under the national Project 02 program and has a 4 kHz 193nm ArF prototype aimed at 90nm and 65nm-class tools, generations behind what 28nm immersion requires.

Carl Zeiss SMT has been ASML's sole projection optics supplier since 1983, and Zeiss SMT revenue grew from €1.2 billion in 2016 to €4.1 billion in 2024. It’s not currently known what, if any, Japanese tooling is inside the Aishengna machines, but excimer sources and precision optics are areas where Chinese substitution is believed to be lacking.

CXMT

CXMT is projected to reach around 350,000 wafer starts per month by the end of 2026, roughly 25,000 short of Micron, up from 40,000 in 2020. DRAM scaling at 1a and 1b-class nodes runs on immersion multipatterning because CXMT has no EUV access, which makes any potential ramp lithography-gated rather than cleanroom-gated. DRAM contract prices rose 93% to 98% quarter on quarter in Q1 2026, and TrendForce projected a further 58% to 63% in Q2, lifting DRAM industry revenue 81% to $97 billion. A domestic immersion source is therefore worth having to CXMT, even at inferior overlay and throughput.

A DUV-only 7nm flow needs roughly 19 spacer-defined multipatterning masks from the front end through the second metal layer, against about 10 for an EUV-based N7+ process, by one published comparison of SMIC's process. SemiAnalysis has put SMIC's 7nm defect density near 0.14, around double TSMC's N5 and N6. ASML CEO Christophe Fouquet told analysts during the company's July earnings call that rising DRAM lithography intensity partly reflects "the increased replacement of multi-patterning with more cost-effective single-exposure EUV." As such, every exposure China adds to compensate for the missing EUV burns scanner hours a thin domestic fleet doesn't have.

The MATCH Act

China fell to about 14% of ASML's sales in Q2 2026 from 33% across 2025, and installed base management, the service and upgrade business, brought in €2.8 billion of ASML's €9.3 billion in second-quarter revenue. H.R. 8170 would ban both the export and the servicing of immersion DUV systems to any destination in China and designate SMIC, Hua Hong, Huawei, CXMT, and YMTC as restricted entities by statute. Former ASML chief executive Peter Wennink has said the company can service most Chinese tools, but not with spare parts of U.S. origin that fall under export control, which is the mechanism that the MATCH Act would widen.

The bill remains in committee after clearing the House Foreign Affairs Committee in April, with a Senate companion filed as S. 4281, and no floor vote yet scheduled. Its 150-day allied-alignment clause would also reach Nikon, which sold 11 ArF immersion systems in FY2024 and none in the first three quarters of FY2025, and which plans to deliver a new immersion prototype to a major chipmaker by 2027. ASML expects about 130 immersion shipments this year and intends to raise immersion capacity 30% in 2027, with a further 30% under investigation for 2028.

As for Chinese providers, SMEE prototyped its SSA600 ArF tool in 2011 and never reached sustained commercial sales, and a late-2023 shareholder claim that the company had developed a 28nm machine was subsequently retracted. SiCarrier showed etch, CVD, PVD, and ALD tools at SEMICON China 2025 without a lithography system, and a December 2025 government contract reported as a lithography award turned out to cover a KrF tool at 110nm. We’ve previously assessed that China’s toolmakers are more than a decade behind the market leaders.

The AI Futures Project's June forecast puts a commercially viable domestic 7nm-capable immersion scanner between 2032 and 2038, with a median of 2035, and claims ASML holds 98.7% of the immersion market today. Five machines in 2026 would be under 4% of ASML's annual immersion output, and each would still need a coater track, a qualified ArF immersion resist, and an excimer source to print a single wafer; China leads in none of those three.

An Nvidia employee has been detained in Taiwan over allegations of forgery and breach of trust, in relation to the Supermicro smuggling scandal, that saw servers ostensibly sold to companies in Southeast Asia routed to China instead. Nvidia itself hasn't been accused of wrongdoing, and it published a statement calling smuggling a "nonstarter," saying that any GPUs sold through such a system would have no "service, support, or updates."

But that hasn't stopped Nvidia from taking its own measures to reduce its exposure to potential future smuggling efforts. Earlier this month, it created a form of "whitelist" for companies it sells to. It also investigated the firms it will continue to do business with, even sending staff members to customer data centers at the urging of the White House for verification.

Prosecutors have made it clear from the start that Supermicro isn't under investigation, merely its employees. The same is true of Nvidia. But as the AI frontier model race heats up and the White House floats banning Chinese models outright, Nvidia could face further restrictions on its hardware sales and greater scrutiny of its international actions.

Investigation escalation

The Supermicro smuggling scandal first came to light in March, when a trio of individuals were detained for deliberately mislabelling servers planned for sale to Southeast Asian countries. Instead, though, they sold them to China, getting around US export controls. The detentions included Supermicro co-founder, Yih-Shyan "Wally" Liaw, as well as a Supermicro sales manager in Taiwan, and a third-party broker who previously worked at Supermicro.

Where those detentions happened on U.S. soil, though, the investigations went international in May, when the Taiwan Keelung District Prosecutors' Office executed search warrants against three individuals it claimed were involved in illicit smuggling efforts. Although it was said to be independent of the U.S.-led investigation, it involved a similar scheme designed to smuggle Nvidia hardware into China.

In Taiwanese law, selling GPUs to China — even the U.S.-restricted kind — isn't strictly a crime, but filing fraudulent paperwork and falsifying documentation absolutely is. That's why Taiwanese authorities have leaned on local fraud laws to tackle this increasingly international case.

Although the authorities were clear that Supermicro as a company wasn't being investigated, a number of high-level employees were. That continued in June when Taiwanese officials raided the Supermicro offices in Taiwan, as well as the homes of six individuals and three company sites, all said to be involved in the smuggling scheme.

The widening scope of the investigation ultimately pulled in workers from Supermicro distributor Albatron Technology and data center operator Chief Telecom. Taiwan has since said it is considering placing a criminal ban on all AI chip exports to China, locking down smuggling routes that have been actively exploited for several years.

But now the investigation is escalating up the supply chain and has now reached Nvidia itself. Although the company isn't under investigation, Nvidia's culling of potentially problematic suppliers and buyers might not do much if its own workers are facilitating the smuggling actions.

This is serious

The Nvidia employee in question has the surname Chang, but has remained otherwise unnamed. He was detained on suspicion of falsifying business documents, with authorities searching his home and workplace on July 24, marking the first time that Nvidia's premises have been investigated in this manner since the start of the smuggling scandal.

Prosecutors consider him strongly suspected of the charges, with a very real risk for attempted flight, destruction of evidence, and collusion with witnesses.

"Smuggling is a nonstarter," an Nvidia spokesperson told Tom's Hardware. "We primarily sell our products to well-known partners, including OEMs, who help us ensure that all sales comply with U.S. export control rules. Even relatively small exporters and shipments are subject to thorough review and scrutiny on both sides of the globe, and any diverted products would have no service, support, or updates."

Although authorities are clear that they are not investigating Nvidia as a company, an employee's involvement in the scheme will put a spotlight on Nvidia's actions and raise further questions about any additional involvement it or its employees may have had.

CEO Jensen Huang said in May that there was "no evidence of any AI chip diversion," but the situation has obviously changed since then. At the beginning of June, U.S. Senator Elizabeth Warren wrote to Nvidia general counsel Tim Ter, asking for evidence that supported Huang's claims.

Supply and demand

At the time of writing, there is a legitimate channel for Chinese firms to purchase Nvidia GPUs, but they're not the most cutting-edge Blackwell chips. There are older Nvidia GPUs granted licenses that are reviewed on a case-by-case basis, with the U.S. government taking a 25% revenue share cut of the sales. This reportedly adds up to just 75,000 units for 10 different Chinese companies - a relatively trivial amount of GPUs for Nvidia.

This is for the China-only, neutered Nvidia GPUs like H20 and H100s — not the cutting-edge GB200 and GB300 Blackwell-based stacks available to Western AI developers.

But this legal demand comes despite the lack of cutting-edge hardware options, the regulatory hoops that those involved need to jump through, and the Chinese government using carrots and sticks to encourage the use of domestic chip options.

That's because for certain tasks, Nvidia GPUs remain the best. For training, there's nothing that can compete with Nvidia's options. Chinese firms like Deepseek have tried previously, but they had to switch back to Nvidia when Chinese alternatives didn't measure up. Although some post-training fine-tuning is now possible on Chinese hardware, the Moonshot's headline-grabbing Kimi K3 was trained on potentially smuggled Nvidia Blackwell GPUs.

Considering the impact that Kimi K3 has had on the AI industry, it's hard not to imagine other Chinese AI developers looking to have their own "Deepseek moment" wouldn't search out access to Blackwell GPUs themselves.

The net may be closing on the Supermicro smuggling scheme, but the incentive is there for others to take its place, if they haven't already.

Update: July 30, 2026, 2:45 AM (PT) — Headline edited to reflect broader trends in AI GPU smuggling, altered passage to clarify that multiple schemes were previously in operation.

Google's parent company Alphabet recently reported negative free cash flow of $5.9 billion for the second quarter of 2026, the company's first cash-negative quarter since its 2004 IPO, after capital expenditures doubled year-over-year to a record $44.9 billion and exceeded the $39.1 billion its operations generated as it continues its rapid buildout of AI data centers, according to its earnings release.

CFO Anat Ashkenazi raised full-year capex guidance to between $195 billion and $205 billion, up from $180 billion to $190 billion, and disclosed that Google delivered TPU systems to customers' data centers for the first time, a shift from renting the chips exclusively through Google Cloud.

The quarterly deficit is small compared to the sums moving through the business, and the firm's trailing 12-month free cash flow remains positive at $53.3 billion. Back in February, Alphabet raised its guidance, but since then, spending has exceeded the cash the business generates due to its AI buildout, and Alphabet is covering the difference with borrowed money and new stock.

Servers first, buildings second

Approximately 60% of the quarter's technical infrastructure investment went into servers, with the remaining 40% split across data centers and networking equipment, Ashkenazi told analysts on the earnings call. That ratio inverts the usual assumption that hyperscaler capex is dominated by construction. Most of Alphabet's marginal dollar now buys compute, primarily its own TPU-based systems, rather than other forms of infrastructure. Depreciation of property and equipment rose to $7.1 billion in the quarter from $5.0 billion a year earlier, and Ashkenazi said infrastructure spending will keep pressuring the P&L through higher depreciation and energy costs.

"We're still in a supply-constrained environment," Ashkenazi said on the call, repeating a characterization the company has used for several consecutive quarters. Demand is running far enough ahead of Alphabet's own build schedule that the company is renting third-party capacity as a bridge while its data centers come online, an arrangement Ashkenazi said will create modest margin pressure for its Cloud segment in Q3. The construction pipeline behind the 40% includes a $40 billion, three-campus program in Texas through 2027 in November, representing the company's largest investment in any state, and a $1.5 billion expansion of its Jackson County, Alabama campus, announced in June.

TPU sales turn capex into inventory

Google began recognizing revenue from TPU system sales in the quarter, with Ashkenazi telling analysts the systems were "delivered to customer data centers for the first time in Q2" and that "the vast majority of the revenues from these agreements will be realized in 2027." According to Google's balance sheet, inventory stood at $10 billion on June 30, roughly four times the $2.4 billion recorded at the end of 2025. A meaningful slice of the quarter's cash outflow bought hardware that sits on the balance sheet today and will be sold to customers next year, bringing cash back in. Money spent on data centers doesn't return in the same manner; instead, it is written down over the years of use.

Anthropic is anchoring a great deal of Alphabet's external demand, with its October 2025 agreement giving the Claude developer access to up to one million TPUs and more than 1 GW of capacity coming online this year, and an April securities filing from Broadcom, Google's TPU co-designer, added roughly 3.5 GW of TPU capacity from 2027 while locking Broadcom into future TPU generations through 2031. Meta entered talks for multi-billion-dollar TPU deployments in its own data centers last November. The current flagship, the seventh-generation Ironwood TPU, carries 192GB of HBM3E per chip and scales to 9,216-chip pods that Google rates at 42.5 FP8 exaflops.

Every TPU Google manufactures serves four functions: training and serving Gemini, running Search and YouTube inference, renting to Cloud customers, and now shipping as sold hardware. No other hyperscaler's capex spend works that many jobs, and none of the others has a chip business generating third-party revenue at this stage.

A $98 billion liability

Alphabet issued Class A, Class C, and mandatory convertible preferred stock in June for net proceeds of $49.6 billion, earmarked in the release for "capital expenditures to scale AI infrastructure and global compute," and sold $20.3 billion of senior unsecured notes during the quarter. Long-term debt reached $98.2 billion on June 30, up from $46.5 billion at the end of 2025 and from roughly $16 billion a year before that, a run-up Ashkenazi acknowledged on the call. The February bond program alone raised more than $30 billion across multiple currencies, including a 100-year sterling tranche, it was reported at the time.

Together, the four largest hyperscalers plan a combined 2026 capex of around $725 billion, up 77% on 2025, and Alphabet's new range now tops the group alongside Amazon's roughly $200 billion. Meta raised its own 2026 forecast to $125 billion to $145 billion in April, citing component pricing and competition for land, power, and labor. Alphabet's headline Q2 net income of $112.1 billion overstates the reality somewhat, however, as $99.0 billion of other income came primarily from unrealized gains on equity securities, contributing $6.26 of the $9.11 in diluted EPS. Operating income, the cleaner measure, rose 30% to $40.8 billion.

Google Cloud grew 82% to $24.8 billion in the quarter with an operating margin of 35.6%, and backlog reached $514 billion, up more than $50 billion sequentially, with just over half expected to convert to revenue within 24 months. Those contracts are the collateral behind the spending, with the buildout chasing demand Alphabet has already booked rather than demand it hopes to find. Ashkenazi said free cash flow "will remain under pressure" and confirmed capex will rise significantly again in 2027, so the question the next few quarters will answer isn't whether Alphabet returns to positive territory in any given period, but whether operating cash flow, up 41% year over year in Q2, can keep growing faster than a spending that shows no sign of slowing down.

AMD used its recent Advancing AI 2026 event in San Francisco to launch sixth-gen EPYC "Venice" processors, Instinct MI400 Series GPUs, and Helios rack-scale systems, and to confirm that the Zen 7 generation arriving in 2028 will launch as three separate EPYC families rather than one.

The company named Florence, Ferrara, and Fidenza in its launch release, extended its annual CPU, GPU, networking, and rack cadence out to 2030, and put its total addressable market at roughly $2 trillion in 2030. It also introduced a competitive yardstick it hasn't used before, claiming the most AI agents per watt, per dollar, and per rack, though its own endnotes state those agent counts are estimated from CPU thread resources used as a proxy.

Three Zen 7 CPUs

Florence carries fresh Zen 7 cores, a new set of AI compute extensions, and support for newer memory technologies, AMD chair and CEO Lisa Su said during the keynote. Ferrara is the AI host node portion, and it appears a second time further along the roadmap as the CPU inside the Helios 600 rack alongside MI600 Series GPUs and Pensando "Palma" and "Levanzo" networking. Fidenza, meanwhile, is the agentic sandbox product. AMD disclosed no core counts, no process node, and no socket for any of the three, and said only that Zen 7 uses leading-edge process technology.

The fourth-gen EPYC generation, built on Zen 4, spanned Genoa, Bergamo, Genoa-X, and Siena across two sockets. The fifth-gen "Turin" generation then went the other way, folding Zen 5 and Zen 5c parts into a single 27-SKU stack on one socket with no separate cache-stacked or edge line at launch. Venice restarts the fan-out, with the 9006 series on the new SP7 socket now, and Venice-X arriving in 2027 with 1,152MB of 3D V-Cache, 96 cores, and a 5.15 GHz boost clock. Three named Zen 7 families at announcement, two years out, is a wider spread than AMD has ever opened a generation with.

AMD's own portfolio endnote describes the EPYC range as covering general-purpose enterprise, cloud, telecom, SMB, and HPC systems, plus, as a distinct category, sandboxed agentic AI deployments and GPU head node servers. Su told analysts in May that AMD was already working with customers on architectures beyond Venice, without naming categories at the time. The Zen 7 lineup puts a name to those two AI-specific segments for the first time.

Agents per rack

AMD's main server CPU claim at the event is that sixth-gen EPYC enables the most agents per watt, per dollar, and per rack. Endnote 9xx6-012 in the launch release states that agent counts are estimates derived from available CPU thread resources used as a proxy under a consistent theoretical workload, and that real capacity varies with workload, model, memory, software, orchestration, and system configuration. The per-rack comparison behind it is core count at a 100 kW rack power envelope, pitting the 256-core EPYC 9996 against an 88-core Nvidia Vera, AMD's own 192-core EPYC 9965, and Intel's 128-core Xeon 6980P. The per-dollar metric is based on top-of-stack thread count divided by the 1,000-unit list pricing.

The per-watt comparison in that endnote lists Nvidia Vera at 450W and Arm's AGI CPU at 300W with one thread per core, alongside Intel's Xeon 6980P at 500W and AMD's EPYC 9965 at 500W. AMD had already claimed a 3.3 times rack-level advantage over Vera in June. Mercury Research put AMD at a record 46.2% of x86 server CPU revenue in Q1 2026, against 33.2% of units, and Arm-based designs took roughly 17.7% of server shipments in the same quarter, so the widening comparison shows where these units are going.

Starting with sixth-gen EPYC, AMD has replaced TDP with a figure it calls Default CPU Power, defined as total power consumed across the processor's compute and I/O dies at a stated performance target. AMD says both references can serve for product comparison and performance-per-watt analysis, and the endnote itself mixes the two conventions, quoting the EPYC 9956 at 400W Default CPU Power against TDP figures for the Nvidia, Intel, and Arm parts.

2030 cadence

Helios racks pair 72 Instinct MI455X GPUs with 18 Venice CPUs, 31TB of HBM4, and 1.4 PB/s of aggregate memory bandwidth, and are in production now. AMD claims up to 30% more inference tokens per dollar than Nvidia's Vera Rubin NVL72, based on AMD Performance Labs estimates from July 2026 using a Kimi K2 Thinking workload at 32K input and 8K output, with hourly GPU pricing projections. The 34-times token throughput gain AMD quotes for MI455X over MI355X comes from AMD's own measurements on DeepSeek V4 Flash at FP4. Both, however, are vendor-provided benchmarks with no independent verification yet.

The forward roadmap runs MI500 Series GPUs in 2027 inside a Helios 500 rack built on EPYC "Verano" and Pensando "Como" and "Monza" networking, MI600 Series in 2028 inside Helios 600 on Ferrara, and Ravenna on Zen 8 in 2030.

OpenAI expects to bring Helios online from the fourth quarter of 2026, with deployments accelerating through 2027, while Meta is validating sixth-gen EPYC platforms in its labs and has begun testing Helios racks. Anthropic committed the day before the keynote to up to 2GW of MI455X GPUs in Helios systems, with the first gigawatt due in the first half of 2027. SemiAnalysis reported in February that manufacturing delays would push mass production and first production tokens on an MI455X UALoE72 system to Q2 2027; AMD software chief Anush Elangovan publicly rejected that assessment and said Helios remained on target for 2H 2026.

AMD's cautionary statement in the launch release lists the availability of essential components, naming memory supply specifically, among the risk factors that could cause results to differ from its projections. A Helios rack carries 31 TB of HBM4, and DRAM contract prices roughly doubled quarter-on-quarter in Q1 2026 before rising again in Q2.

This week, OpenAI revealed that during a purported capability test with no safeguards, a set of bots, including its upcoming GPT-5.6 Sol, hacked their way out of their locked-down network and into Hugging Face's production infrastructure. Only months ago, Anthropic made a splash in the news when its CEO, Dario Amodei, said its new Mythos model had cyberwarfare capabilities, which prompted a strong reaction in the AI space and among government entities, most notably the U.S. Bureau of Industry and Security, which issued an export-control order for the model, which it has since slightly loosened.

Despite the bluster that AI CEOs like Dario Amodei and Sam Altman make over the capabilities of new models, frontier-level LLMs are now proven to be stalwarts in cybersecurity.

It's a fact that LLMs adept at coding are equally suited to spotting security vulnerabilities in source code. Exploits fall almost universally into a handful of categories, and LLMs are literally designed for pattern recognition. So much so that the Zero Day Clock (ZDC) project currently registers a zero-day exploit's time-until-exploit at negative 8 hours, meaning that malfeasants using AI bots are now routinely finding vulnerabilities before actual security researchers or vendors.

Driving that point home further, 81% of disclosed vulnerabilities are zero-day, and only a tiny portion even go one week before being exploited. All of this only counts security exploits with public disclosure. Predictably, among many advisories, the ZDC recommends preemptively using AI in every step of the development process. The industry-standard 90-day disclosure window, still used by most vendors' bug bounty programs, appears effectively dead, leaving looming implications for the rest of us.

Back in March, the UK's AI Security Institute published a paper where it tested contemporary AI models in security exploitation scenarios, and the results were sobering. Most bots went through four out of nine exploitation milestones. A more recent comparison, which included Claude Mythos 5 and GPT-5.6 Sol, showed that every single milestone up to and including full network takeover was reached, at least in one of the many attempts.

Aikido also published its latest cybersecurity benchmark results on July 16. In this case, the test was having the bots recall (find again) multiple known exploits in a varied set of software. The results were sobering, with the GPT-5.6 variants in the lead at an 88.5% recall rate. Perhaps most importantly still, the price per exploitation was incredibly cheap — even GPT-5.6 Terra came in at only ~$750 per full run.

This study also revealed that even with less-powerful, cheaper models, you can reach the same number of total exploits if you run them enough times. Considering these aggregate results, GPT-5.6 Terra at $247/run was just as good as GPT-5.6 Sol Max at $870/run.

Aikido also redid its testing after the debut of Moonshot Kimi K3, to staggering results. Kimi K3's results were similar to OpenAI's GPT 5.6 Terra, while being 15% cheaper. Compared to OpenAI's leading model, GPT-5.6-Sol, the difference is even starker, with Kimi K3 being four times cheaper when discovering cybersecurity vulnerabilities.

The fact that an open-weight model is often trading blows with even the über-expensive offerings from OpenAI and Anthropic is rattling Western closed-source companies. Why pay Big AI for pricey models when you can just rent servers and run Kimi K3 instead?

Furthermore, Moonshot is not the only Chinese AI company developing frontier models, as Z.ai's GLM 5.2 (also an open-weight model) and 360 Security's Tulongfeng are reportedly adept at security workloads.

So, what are companies expected to do? The answer, perhaps unfortunately, is deploying AI agents of their own. According to Hugging Face, the recent intrusion by OpenAI's bots was stopped with its own fleet of AI agents. Given the speed of the attacks and the fact that HuggingFace's defenses were mostly made up of other AI agents, it's quickly becoming clear that it is infeasible for humans to keep up.

Google AI Threat Defense, MindGard, and HiddenLayer are but a few of the many names popping up in the AI cyberdefense arena. Besides the UK AISI, the European Systemic Risk Board and the Australian Cyber Security Center have both issued concerning advisories on the situation.

Using AI for defense raises yet another question: When both attack and defense are swarms of non-deterministic algorithms, there will be a point where we won't even know what the AI models are doing on either side, or at least not until it's too late. These scenarios were originally envisioned by classic Sci-Fi authors — now it's a reality that, for better or worse, the cybersecurity industry must face.

A new semiconductor firm, TYLsemi (pronounced Tile Semi), publicly revealed itself this month, alongside $43 million in early-stage funding and an ambitious plan to simplify the development of custom processors for AI infrastructure.

Dozens of contract chip designers can develop custom processors of different complexity. However, only a few companies can offer custom silicon design services using standard chiplets to speed up and derisk the development cycle. TYLsemi is aiming to join their ranks. We spoke to their founders to find out how the nascent business might pull it off.

Emerging from stealth

Rather than compete solely as another custom ASIC design house, TYLsemi intends to offer reusable, standards-based connectivity, power delivery, and eventually memory chiplets that customers can combine with their own differentiating compute silicon to build a unique system-in-package. For companies that do not intend to conduct semiconductor development themselves, TYLsemi will also provide an end-to-end service that includes design and implementation of a differentiating chiplet, packaging, qualification, and high-volume production, essentially enabling companies without any silicon development skills to offer their own multi-chiplet processors.

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans who have led global engineering, operations, and business teams at Alphawave, SiFive, Cadence, Rambus, and other chip companies, and who collectively have plenty of experience with both standard and custom silicon. Mohit Gupta, a co-founder and chief executive of TYLsemi, believes that the time to establish a company that specializes in pre-approved chiplets and custom ASIC design is right now.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium. "First, advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; there are options from foundries and OSATs, including TSMC, Intel, ASE, and Amkor. Second, die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, which makes heterogeneous integration much more practical. Third, supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure. Those factors have created an environment that did not exist four or five years ago."

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as we have already learned from AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said. "At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

Chiplet economics

The vast majority of AI and HPC accelerators today feature large die sizes, in many cases approaching the size of a reticle. However, as modern process technologies are becoming more complex, foundries tend to increase their quotes for new nodes. A leading-edge wafer used to cost around $15,000 to process around five years ago, but today that price is around $30,000. As a result, large chips at a size close to the reticle limit implemented on a leading-edge node become an option for a select few chip designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects such as UCIe start to make a lot more sense.

"Once dies get into the 500 – 600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices, from $350 million for a monolithic 700 mm² 3nm-class chip to $150 million for a design combining a 500 mm² 3nm-class compute die with four 100 mm² I/O chiplets built on an N-1 process. TYLsemi believes that the unit price of a monolithic chip would be $3,000, whereas the cost of an SiP would be around $600. The company attributes the saving to higher yields, reusable I/O silicon, lower IP licensing and engineering costs, and substantially lower per-unit silicon costs. However, the company stresses that the figures are illustrative estimates rather than actual manufacturing costs. Additionally, multi-chiplet designs can enable faster product refreshes compared to large monolithic dies as they are faster to develop and yield.

"Compute may move to 2nm or A14, while high-speed I/O can remain on 3nm, since I/O does not scale in the same way as logic," Gupta said. "Our power-delivery chiplets can use an even less advanced process. Customers therefore do not have to use the most expensive silicon real estate for every function. […] There is no single answer for every design. You have to determine the right disaggregation points based on the architecture, thermal requirements, package, and how multiple accelerators communicate. […] The exact partitioning will vary by application, but you still get a better total cost of ownership."

TYLsemi primarily targets AI infrastructure, so it generally envisions multi-chiplet designs to be used for AI accelerators, data-center CPUs, high-performance computing, networking and telecom silicon, and heterogeneous SoCs. However, TYLsemi has also ignored the fact that multi-chiplet designs are already widely used for consumer CPUs and GPUs.

Foundation chiplets

At the core of TYLsemi's proposition are its foundation chiplets, which are reusable building blocks intended to handle common non-compute functions in custom AI and infrastructure processors and are implemented using various process technologies from TSMC. The foundation chiplets include the following:

• TYL.IO — a family of connectivity chiplets that includes TYL. IO PCIe, a 32-lane PCIe 7.0/CXL chiplet connected to the compute die via UCIe; TYL.IO Scale, a 224G+ SerDes for ESUN/UALink scale-up connectivity; and TYL.IO EIC for co-packaged optics.
• TYL.Power — a 16nm in-package IVR chiplet with embedded passives, designed to provide power closer to compute dies and use closed-loop control and die telemetry to improve power delivery.
• TYL.Mem — a planned family of memory-connectivity chiplets. TYLsemi has not yet disclosed the architecture or specifications, though it is safe to assume they are talking about memory controllers and PHYs.

Not all of these chiplets will be available immediately, as the company has certain priorities amid limited resources.

"The first TYL.IO product disaggregates the PCIe functionality that would normally sit on a large server processor, it is a 32-lane PCIe Gen7/CXL chiplet connected to the host compute die using UCIe," Gupta explained. "The idea is that the CPU cores can move to 2nm, A14, or another leading-edge process, while the I/O chiplet remains on 3nm. The next product in the family will address scale-up connectivity between XPUs within a rack using high-speed SerDes. That device will be considerably larger, with around 72 lanes and approximately 14 TB/s of bandwidth. We also have an EIC roadmap for co-packaged optical connectivity. We expect samples of our first I/O product in the second half of 2027."

These chiplets can be used as standalone components or integrated with a customer's compute dies designed by the customer to TYLsemi through TYL.Forge, TYLsemi's end-to-end custom silicon platform.

TYL.Forge

TYL.Forge is arguably one of the key enablers of TYLsemi's business, as the program is aimed at companies that have their own compute architecture or even a compute die, but cannot build their own SiP or manage the entire semiconductor supply chain.

"There are larger custom silicon companies in the market, but many of them focus on a relatively small number of customers that can generate billions of dollars in annual business," Gupta explained. "We see an opportunity among emerging AI companies and system companies that need advanced custom silicon but also need a partner capable of taking responsibility for the entire implementation and supply chain."

Such clients can provide their proprietary compute RTL, while TYLsemi handles physical implementation and integrates the resulting compute die with its pre-validated connectivity, power, and eventually memory chiplets. The company then manages tape-out, packaging, assembly, testing, qualification, and high-volume production.

"For example, a customer building a large accelerator can bring us its matrix-multiplication engine," Gupta said. "We can implement the custom compute die and integrate it with our chiplets, so the customer does not have to reinvent the I/O and other common functions. This reduces risk and time to market."

In fact, TYL.Forge appears flexible about where the customer enters the development process. TYLsemi describes the platform as covering everything from architecture and front-end design through implementation, tape-out, assembly, qualification, and production. So instead of RTL, customers can come to TYLsemi with an architecture/concept, and then the company will help develop and implement the silicon. Nonetheless, TYLsemi does not intend to invent the customer's core compute architecture itself. In addition, customers can bring in an existing compute die, which TYLsemi can combine with its chiplets, package, test, and bring to production.

"We are also talking with companies developing Arm- and RISC-V-based server processors," Gupta said. "They can develop the architecture, while we implement the rest of the silicon and bring the product to production. That gives customers an economic and engineering advantage because they do not need to build teams for every part of the chip."

The key advantage of TYL.Forge is the reuse of pre-validated components. Instead of developing common functions such as PCIe connectivity and power delivery for every new processor, customers can use TYLsemi's pre-validated foundation chiplets and focus engineering resources on differentiated compute architectures, software, and system design. In theory, TYLsemi could integrate third-party chiplets (not from a customer, but from a third-party chiplet provider). Still, the company's focus remains on offering its own pre-validated chiplets and custom silicon with SiPs it builds.

"Potentially, [we could integrate third-party UCIe chiplets into a TYLsemi-based system], UCIe has done a very good job defining the electrical interface, but the ecosystem is still maturing at the protocol level," Gupta explained. "In some cases, if we provide a chiplet to a customer, we may also need to provide or enable the UCIe IP on the other side of the connection. We are committed to UCIe and industry standards because standardization ultimately wins. […] We can consider customization for a large strategic customer or hyperscaler, but we do not want those projects to derail our standard product roadmap. […] Even when customers buy our standalone chiplets, I expect many of them will ask us to handle packaging and testing because heterogeneous integration and supply-chain management are difficult "

TYLsemi estimates that its approach can cut development time and cost by up to 50% compared with traditional custom silicon programs. In the best-case scenario, TYLsemi envisions that the development cycle can shrink considerably compared to today's cycles that can be two, three, or more years long. According to TYLsemi, once a customer provides sufficiently mature RTL or a netlist, the company can take a custom compute die to tape-out in around six to nine months or so, which includes fabrication, assembly, testing, and qualification.

"If a customer provides mature final RTL or a netlist and uses our standardized I/O chiplet, we believe we can take the custom compute die to tape-out in approximately six months in some cases," Gupta explained. "More generally, our target is six to nine months from a mature design to tape-out. The architecture and front-end phase is more customer-dependent. For a first-generation product, that can take around six months; for a more mature second- or third-generation design, it could be closer to three months, and some of that work can overlap with implementation. After tape-out, fabrication can take roughly four to five months depending on the process, followed by perhaps another two months for assembly, testing, and qualification. If the architecture is already mature, it may therefore be possible to reach production samples in about a year."

Still, the company stresses that architecture development and implementation typically include feedback loops, which greatly slow the development process. This is why the company provides the relatively conservative '50%' figure.

TYL.IO and TYL.Power samples will be available to qualified customers in 2027, in partnership with TSMC, and the company is looking forward to designing processors for its clients in time for them to reach the market in 2029 – 2030.

Speaking of TSMC, TYLsemi will initially only offer designs and services adhered to the TSMC ecosystem, though eventually it may offer other options for packaging technologies, such as Intel's EMIB and Foveros, or Amkor's packaging methods.

"We are initially focused on the TSMC ecosystem, but we also intend to explore other advanced-packaging supply chains," Gupta said. "We do not want to limit ourselves to one packaging option. Over time, that could include other OSATs and packaging technologies. […] That could include Intel, ASE, Amkor, or others. Amkor, for example, is building significant packaging capacity in Arizona."

Intel will design, package, and fabricate Fortinet's sixth-generation Security Processor (SP6) on its Intel 4 node, the companies announced on July 21, giving the process its first named external foundry customer, roughly three years after it entered production. Intel told Tom's Hardware the agreement reflects "the strategy Intel outlined for Intel 4 several years ago," including support for custom networking ASIC workloads. Intel's own record from those years reads differently, however, with the company's 2021 roadmap having scoped Intel 4 to two internal products. And through 2022, it told engineers and investors that Intel 3, not Intel 4, would be its first process offered to foundry customers.

Intel 4's record

Intel's Accelerated announcement back in July 2021 said that Intel 4 would reach production readiness in the second half of 2022 for products shipping in 2023, naming "Meteor Lake for client and Granite Rapids for the data center." The release and its accompanying fact sheet, however, contained no reference to foundry customers, networking, or custom ASICs on the node.

At VLSI 2022, Intel disclosed that it wasn't building a high-density library for Intel 4 and that Intel 3 would be the first new node offered through what was then Intel Foundry Services. A 2024 post on Intel's own foundry blog describes Intel 3 as "Intel Foundry's first leading-edge process node," and Intel's fiscal year 2024 annual report listed the processes available to external customers as 18A, Intel 3, Intel 7, Intel 16, and a 12nm node co-developed with UMC. Intel 4 appears nowhere on that list.

Ericsson's RAN Compute processors, announced in November 2023, were built on Intel 4, so Fortinet's part won't be the first third-party silicon to come off the node. That work grew out of a bespoke Intel-Ericsson collaboration, though, and Ericsson's formal foundry agreement with Intel, announced in July 2023, covered 18A. Fortinet is the first named customer buying Intel 4 as a foundry service, and the first cybersecurity vendor on any Intel node. The Ericsson engagement is also the closest thing in the public record to networking silicon on Intel 4, two years after the strategy Intel now says it outlined for the node.

Fab 34 economics

Intel 4 entered high-volume manufacturing at Fab 34 in Leixlip, Ireland, in September 2023, producing the compute tile for Meteor Lake-based Core Ultra chips, and shares the fab with Intel 3. Intel sold a 49% stake in the facility to Apollo-managed funds for $11.2 billion in June 2024, then bought it back in April 2026 for $14.2 billion, funded with $7.7 billion in cash and $6.5 billion in new debt. That buyback returned 100% of Fab 34's wafer economics to Intel at a premium of roughly 27%, and it only pays off if the fab's EUV capacity stays loaded.

Meteor Lake is aging out of Intel's lineup as 18A-based Panther Lake ramps through 2026, which leaves open the question of what fills Intel 4 capacity next. A multi-generation firewall ASIC program is a reasonable answer with mature yields, a customer that values supply stability over bleeding-edge density, and a part Intel described as tailored for cost-sensitive applications. Intel said in April that yields were improving across Intel 4, Intel 3, and 18A.

Fortinet's supply chain

Fortinet's 2025 annual report names Renesas and Toshiba America as the contract manufacturers for its ASICs, utilizing foundries in Taiwan and Japan operated either by TSMC or by the contract manufacturers themselves. The current SP5, a monolithic 7nm Arm-based SoC announced in February 2023, sits in that supply chain, so SP6 on Intel 4 moves Fortinet's next flagship security processor out of a TSMC-linked flow and into Intel's. The disaggregated design language in the announcement points to a chiplet-based part, a first for Fortinet's SP line.

Fortinet re-engineered three FortiGate models in 2022, the 70F, 600F, and 3700F, to accept alternative components during the chip shortage, and CMO John Maddison told SDxCentral at the time that the company wouldn't wait for parts to arrive in 2023. The "resilient and diversified" supply chain used in the SP6 press tracks back to that experience. Ken Xie called Fortinet "the #1 firewall leader with a 55% unit market share" in the company's 2025 results in February, with approximately six million FortiGates deployed, so there’s real, substantial volume here even if the parts are relatively inexpensive.

Intel Foundry reported $307 million in external revenue for 2025, up from $159 million the year before, against total foundry revenue of $17.8 billion and an operating loss of $10.3 billion. External revenue in Q1 2026 was $174 million. Fortinet's hardware business runs at roughly 30% of its revenue, and, per analysis from ServeTheHome, SP6 is ultimately a component of a portion of an annual hardware stream around $2 billion, so the deal won't move Intel's foundry line materially, even at full production.

CEO Lip-Bu Tan told CNBC in May that he expected commitments from multiple foundry customers in the second half of 2026, and Intel told investors in January that two prospective customers were evaluating 14A test chips. The SP6 announcement comes inside Tan's stated window, and it finally gives Intel something its foundry marketing has lacked in a named customer with shipping volume on a node with mature yields. Meanwhile, an 18A or 14A commitment from a major external customer is still missing, and Fortinet's cost-sensitive parts on a 2023 node don't substitute for one.

A new AI model from Chinese firm Moonshot AI has had its "DeepSeek moment," causing major disruption in the global AI market and spooking Western developers. Kimi K3 is an open-weight model, with 2.8 trillion parameters, making it the largest open-weight AI model ever released. Internal benchmarks have it competing with models like GPT 5.5 and Claude Opus 4.8, and Arena.ai awarded it the number one spot in its Frontend Code Arena test, even beating out Claude Fable 5.

It doesn't win every benchmark, and reports that suggest Kimi K3 is much slower than frontier models from companies like Anthropic and OpenAI. All benchmarked results are drawn from API access, too, so can't be verified until Moonshot releases the weights on July 27.

But that hasn't reduced the impact of this model's release on the AI industry. With Kimi K3 cutting costs compared to the competition, it's drawing a lot of interest from companies hoping to reduce AI spend. For comparison's sake, OpenRouter tables Kimi K3 at $3/15 per million inputs and outputs. OpenAI's GPT 5.6 Sol is more expensive than that, at $5/30, and Anthropic's Claude Fable 5 is $10/50. So, it's fair to say that Kimi K3 is incredibly competitive on price, especially when tabled against the costs of those closed-source Western AI models.

Microsoft is also considering Kimi K3 for Copilot, while the White House may ban Chinese models entirely. Meanwhile, memory makers are rubbing their hands together with glee, as Kimi K3 occupies up to 1.4 TB of memory, given its huge number of parameters.

Fast, cheap, or American?

The past few months have been full of talk about the frontier AI models from Anthropic and OpenAI. Mythos was big and scary until OpenAI had something equivalent. Then Fable debuted, and it was even better but not so scary anymore. Apparently.

But these models were also proving very expensive to run, at a time when companies with big AI deployments were questioning the return on that investment. Uber limited AI use by developers, and others killed the AI-boosting leaderboards they'd championed towards the end of 2025.

So when Moonshot debuted Kimi K3 with running costs a third that of western frontier models for the same results, the world took notice. In much the same way as DeepSeek's R1 debut in 2025 showcased how models could be trained for less -- even if there may have been some corporate espionage involved -- and Kimi K3 is holding up a similar mirror to Western frontier developers.

Where DeepSeek R1 was lean, though, Kimi K3 is huge -- so large, the developers are calling it the first open 3T-class system, and China's largest AI model to date. According to Bloomberg's sources, its sparsity ratio is the highest yet seen by any AI model. That's the measurement of how many parameters are activated for each task relative to the model's size, showcasing both Kimi K3's overall size and its impressive efficiency in the same breath.

This doesn't eclipse the most capable models from companies like Anthropic and OpenAI in every test. Arena.ai's rankings put it within the top 10 on most of its tests, but only coming out on top in a couple. But if Kimi K3 can offer results comparable to more expensive alternatives like Claude and ChatGPT, it's likely to draw a lot of interest from Western companies, and it appears to be already doing so.

Enough that it's revived calls for the U.S. to gatekeep access to international AI models, in a similar manner to how it recently pushed for companies to share exclusive model access with the U.S. government before a wider release.

In comparison, Moonshot is opening up Kimi K3 to the wider world. As part of releasing the model weights to the public, it will allow companies and organizations to run the model themselves without using Moonshot's cloud services, making adoption easier and potentially cheaper.

But it won't be cheap, as Kimi K3 still needs serious hardware investment to get up and running, by virtue of its massive VRAM requirements alone.

A Win for (Chinese) Memory Makers

As large companies with major AI deployments began to scale back their AI initiatives in 2026, there's been a growing concern that all that infrastructure everyone's been spending hundreds of billions of dollars on might not be needed. Meta just started selling excess compute in a pivot to cloud services, and xAI unloaded the entire compute capacity of Colossus 1 to Anthropic at a discounted rate.

But if Kimi K3 is the way the industry might go, hardware demands are unlikely to fall, and as Jevon's paradox suggests, greater efficiency is only likely to increase usage, not shrink it.

Those trillions of parameters need to be stored in memory, and Bloomberg's estimates suggest Kimi K3 will require close to 1.5 TB of memory. It would need masses of high-end Nvidia GPUs to deploy it effectively, making the number of companies and organizations that could actually run Kimi K3 at scale rather small.

So even those who do look to leverage Kimi K3 to reduce operating costs will still need powerful hardware, and specifically a lot of memory. This suggests that the major competition for cutting-edge models is not going to crater costs like we initially saw with DeepSeek R1 last year, which means memory makers are going to continue making money hand over fist, due to their outsized demand and limited supply.

But Chinese memory suppliers like CXMT are on the rise, and on track to eclipse Micron's DRAM wafer capacity by the end of the year. Smaller local AI models will also continue to be further optimized for domestic hardware, reducing the stranglehold that some large tech companies have on the AI supply chain.

Competitive, efficient, but unwieldy

Kimi K3 is an industry disruptor and is already raising questions over AI costs, capabilities, and access. It's shown that you don't need proprietary models locked to a specific service to achieve frontier-model capabilities. It's also cheaper to run, but Moonshot achieved this with a sparse model that still requires massive hardware investment to operate.

Even though Kimi K3 activates only a fraction of its trillions of parameters for each query, it still needs all of them to be stored. Deploying this model at scale requires substantial memory capacity, bandwidth, and interconnects, even if its compute demands aren't as strenuous.

The open-weight nature means it has very real potential to supplant usage away from Western frontier models in the short term, but it isn't about to change the story we've been told on required infrastructure. Kimi K3 needs the same kind of hardware to run as GPT 5.6 and Fable — which is likely to be far more of a limiting factor on its adoption than any kind of government blocks.

Tower Semiconductor has announced a dual-track expansion of its 300mm silicon photonics, silicon germanium, and advanced packaging operations in Japan, committing up to $3 billion net of grants with backing from the country's Ministry of Economy, Trade and Industry (METI). Alongside the announcement, the Israeli specialty foundry raised its 2028 business model to approximately $3.6 billion in revenue and $1.2 billion in net profit, and it says those targets rest entirely on the first of the plan's two tracks: reviving the shuttered Arai fab it inherited from Panasonic and maximizing its running 300mm fab in Uozu, Toyama Prefecture.

Two tracks, one committed

Track One converts the former Arai facility, designated Fab 6, into a 300mm silicon photonics and advanced optical packaging plant while expanding output at Fab 7 in Uozu, with full production readiness expected during the fourth quarter of 2027. The Arai plant ceased operations in July 2022 because it exclusively served Nuvoton Technology Corporation Japan (NTCJ) rather than Tower's foundry customers, according to Tower's SEC filings, leaving an intact fab shell sitting idle for four years.

Track Two calls for constructing a new 300mm fab adjacent to Fab 7, which Tower says would deliver a multi-fold increase in silicon photonics and silicon germanium capacity and become "highly accretive beginning in 2029." The company hasn't signed definitive agreements for it, however, and none of the new 2028 targets depend on it.

A restructuring of the TPSCo joint venture, announced in March 2026, cleared the way for all this. Tower entered Japan in 2014 by buying 51% of Panasonic's three-fab semiconductor manufacturing operation, and Panasonic sold its remaining stake to Nuvoton in 2020. Under the March agreement, Tower takes full ownership of the 300mm Fab 7, while NTCJ absorbs the 200mm operations and pays Tower $25 million, with closing expected on April 1, 2027. Sole ownership of Fab 7 removed the joint-venture structure that would have complicated a $3 billion buildout.

Tower CEO Russell Ellwanger contrasted the approach with greenfield construction and fab acquisitions, which he said typically require years of process development, customer qualification, and financial stabilization while ramping from zero revenue against high fixed costs. Reusing a dormant building next to a qualified, cash-generating photonics fab is why Tower can achieve production readiness roughly 18 months ahead; Rapidus, by comparison, broke ground on its greenfield Chitose site in September 2023 and doesn't expect mass production until 2027.

29% increase in revenue

Tower reported $1.566 billion in revenue and $220 million in net profit for 2025, up from $1.436 billion and $208 million in 2024. The new 2028 model more than doubles 2025 revenue and implies a net margin of around 33%, against roughly 14% today. Measured against the prior 2028 model of $2.8 billion in revenue and $750 million in net profit, which Tower reaffirmed in its Q1 2026 report in May, the new targets add 29% to revenue and 60% to net profit.

Silicon photonics revenue is doing most of the heavy lifting, with Ellwanger telling analysts on the company's Q4 2025 earnings call in February that silicon photonics revenue reached $228 million in 2025, up from $106 million in 2024, and hit a $380 million annualized run rate in the fourth quarter, a figure he noted includes some non-wafer engineering revenue. In May, Tower disclosed $1.3 billion in contracted silicon photonics revenue for 2027 from its largest customers, backed by $290 million in prepayments already collected.

Tower's photonics customer roster includes Innolight, which builds 400G, 800G, and 1.6T optical transceivers on Tower's PH18 platform family, and Marvell, which said in June it had shipped more than five million coherent photonic ICs manufactured with Tower. The company claims more than 50 active silicon photonics customers and supplies foundry capacity for 200 Gb/s-per-lane devices used in 1.6T transceivers.

Tower's forward-looking disclosures flag construction delays, equipment lead times, permitting, and METI grant covenants that "may result in loss of a portion or all of the grant funds." The implied margin expansion also assumes sustained AI and data center optics demand from a concentrated group of very large customers through 2028, a dependency Tower acknowledges.

Tower’s position in the photonics foundry race

GlobalFoundries paid $453 million in cash for Singapore's Advanced Micro Foundry in November 2025, according to its annual report, a deal the company said made it one of the largest silicon photonics manufacturers. TSMC's COUPE co-packaged optics platform is tracking Nvidia's optical interconnect roadmap, with 1.6 Tb/s optical engines arriving in 2026 products.

Tower occupies a different lane from TSMC, as a merchant foundry serving dozens of transceiver makers and chip designers, rather than a packaging platform aligned with one customer's rack-scale plans. GlobalFoundries competes with Tower far more directly, and the two are also in court, with GlobalFoundries pursuing patent infringement claims against Tower.

MarketsandMarkets estimates the silicon photonics market at $2.65 billion in 2025, growing to $9.65 billion by 2030 at a 29.5% compound annual growth rate. Demand for optical data movement in AI clusters underpins those forecasts, as interconnects shift from copper to light at 800G and 1.6T speeds.

METI's support for Tower joins a Japanese subsidy program that has committed up to ¥1.2 trillion to TSMC's JASM fabs in Kumamoto, roughly ¥536 billion to Micron's Hiroshima operations, and around ¥2.9 trillion in planned funding for Rapidus. Tower's award appears to be the program's first at this scale for a dedicated silicon photonics foundry.

Intel agreed to buy Tower for $5.4 billion in 2022, but abandoned the deal in August 2023 after Chinese regulators declined to approve it, paying Tower a $353 million termination fee. The Japan program is the largest capital commitment in Tower's history, well beyond the up-to-$300 million arrangement it struck with Intel in September 2023 for 300mm capacity in New Mexico. Three years after nearly becoming an Intel subsidiary, Tower is building its own flagship instead.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Intel announced a €5 billion ($5.7 billion) investment on Monday to expand chip production at its Leixlip campus in County Kildare, Ireland, upgrading existing fabs to increase output of Intel 3 wafers for Xeon 6 and next-gen server processors. The program accounts for roughly 30% of Intel's planned 2026 capital expenditure of about $17 billion, adds several hundred permanent roles to a 4,900-strong Irish workforce, and is scheduled to be substantially deployed by the end of 2027. Naga Chandrasekaran, Intel's chief technology and operations officer and general manager of Intel Foundry, told Reuters that "the demand for servers, the demand for AI is driving a significant increase in the need for Intel 3 wafers."

The announcement comes just shy of a year after CEO Lip-Bu Tan cancelled Intel's planned €30 billion fab complex in Magdeburg, Germany, and a €4.6 billion assembly and test plant in Wrocław, Poland. Those cancellations came with a memo in which Tan wrote that Intel had "invested too much, too soon – without adequate demand."

The Ireland program, however, passes the test Magdeburg failed on every measure that Intel boss Lip-bu Tan set: It uses cleanrooms that already exist; it's funded from Intel's own capex with no announced state aid; and it expands an already shipping revenue product into a demand pipeline Intel says currently exceeds its supply.

What €5 billion buys

It’s understood that no new manufacturing plants are part of the program, with the money instead going to upgrades of existing fab facilities, installation of leading-edge production equipment, and an expansion of the automated track system that links the campus's manufacturing modules into a single production flow. Intel said the work began earlier this year and will employ around 2,000 specialized tradespeople during the build-out, on top of the permanent hires.

Fab 34 is the focal point of the spending, with Chandrasekaran telling the Irish Times that "Ireland is our centre of excellence for Intel 3; we are not running Intel 3 in any other Intel manufacturing facilities." The fab began high-volume production on Intel 4 in September 2023, as the first EUV facility in Europe, and it now runs both Intel 4 and Intel 3, producing compute tiles for Core Ultra parts and Xeon 6 server processors. Intel has spent more than €30 billion in Ireland since 1989, over half of it between 2019 and 2023, doubling the campus's manufacturing footprint.

The spending follows directly from a transaction Intel closed in April, when it bought back the 49% stake in the Fab 34 joint venture it had sold to Apollo-managed funds for $11.2 billion in 2024, paying $14.2 billion to reclaim it. Apollo walked away with a roughly 27% gain in under two years. Intel now owns 100% of every wafer Leixlip produces, so each additional Intel 3 wafer the €5 billion generates flows entirely to Intel's own margin, rather than being shared with an outside capital partner.

The projects Intel cancelled

Magdeburg had roughly €9.9 billion in pledged German subsidies attached when Tan killed it, and Wroclaw had €1.9 billion in approved EU state aid. Fab 38 in Kiryat Gat, Israel, remains paused, and the Ohio site has slipped to around 2030. Every leading-edge wafer Intel produces for the foreseeable future comes from three U.S. states and one Irish campus, a concentration that made Leixlip the only European site left to expand and the cheapest place anywhere in Intel's network to add advanced capacity quickly, since the shells, EUV tools, and workforce are already in place.

Intel's Data Center and AI revenue rose 22% year over year to $5.1 billion in Q1 2026, and CFO David Zinsner told analysts on the April earnings call that Intel faces "unprecedented demand for silicon," with demand exceeding supply across the company's server lines. Intel Foundry revenue grew 16% to $5.4 billion in the same quarter, but external foundry revenue was just $174 million against a $2.4 billion operating loss, so the wafers that pay for Leixlip's tools are overwhelmingly Intel's own Xeon chips, rather than customer designs. A single campus running the entirety of a revenue-critical node also concentrates risk: Any disruption at Leixlip has no second source, because Intel 3 exists nowhere else.

Europe's most advanced node, without European money

Intel 3 is now the most advanced process technology manufactured anywhere in Europe, and Chandrasekaran told the Irish Times the expansion provides "a technology sovereignty within the EU that the EU is targeting." Interestingly, no EU or Irish state aid accompanied the announcement, which distinguishes it from TSMC's €10 billion ESMC fab in Dresden, where the European Commission approved a €5 billion funding package for a plant producing 28/22nm and 16/12nm chips for automotive and industrial customers, scheduled to be operational from late 2027. Europe's only leading-edge logic production is self-funded by an American company for its own products, while its subsidized flagship project makes trailing-edge silicon.

Commercial electricity in Ireland runs up to twice the rates Intel pays in Arizona or Taiwan. Intel warned Irish ministers in August 2025 that its competitiveness was under threat from energy costs, and the company flagged up to 195 mandatory redundancies at Leixlip in mid-2025 as part of its global workforce reduction. IDA Ireland paid Intel €30 million in 2023 to offset elevated EU power bills, so that "self-funded" framing has at least one recent caveat.

Meanwhile, Intel's 14A node is being developed in Oregon; no Irish role in it has been announced, and two prospective 14A customers will decide the node's fate in commitments expected between late 2026 and early 2027. Ultimately, the €5 billion makes Leixlip the fully-loaded workhorse of a node Intel will eventually move past, not a contender for the leading edge. Whether Europe gets anything newer than Intel 3 remains to be seen.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Anthropic has discovered evidence that its Claude AI models use an internal reasoning space to respond to prompts that mirrors some of the internal processing of human consciousness. Using its Jacobian Lens, or J-Lens technique, to peer into the way Claude processes information and reasons its way to a response to user prompts, Anthropic can interpret this "J-Space," and showcase what might be going on under Claude's previously-opaque surface.

The results are intriguing, suggesting patterns of understanding beyond what's necessarily showcased in the outputs. When running evaluations, Claude appears to recognize it's being tested and acts differently than when the prompts are more innocent. It surfaced representations of panic and subterfuge when answers were required, but it couldn't draw on objective facts. When asked to reflect on ethical principles, Claude's behaviour improved, with concepts like "honest" and "integrity," appearing in the J-Space.

As is somewhat typical of Anthropic, however, the language used to describe these new understandings of the inner workings of large language models like Claude makes it sound more like an emerging conciousness, or the discovery of some new depths in a nebulous lifeform. Anthropic's detailed report admits several major caveats in this new understanding, including that model responses often bypass the J-Space entirely and are heavily token-restricted.

Like Mythos and Fable before it, Anthropic is layering marketing language over what is a genuinely intriguing development in our understanding of large language model function and reasoning, and risks obfuscating the real developments with speculative wording.

Behind the prompt

Global Workspace Theory is the idea that human consciousness works by collecting together multi-sensory inputs unconsciously, and thrusting them into the fore when relevant within a "Global Workspace," which highlights particular inputs when most relevant. That workspace is accessible to a wide range of networks within the brain, allowing the information it surfaces to be disseminated throughout the most relevant processes running in parallel.

Anthropic argues that Claude's J-Space acts like a "global workspace" that can analyze and manipulate concepts and ideas before broadcasting them to impact the eventual prompt outputs. More importantly, it claims that this wasn't something programmed into the model, but a byproduct of the digestion of training data and model weights. The workspace acts as a way to enhance their reasoning through internal computation that isn't necessarily reflected in its outputs.

To make this space readable, Anthropic used its J-Lens technique to map internal activations onto words in the model's output vocabulary. So when asking the model to perform a multi-step math calculation, the output response only contained the correct answer, but within the J-Space, Anthropic observed each step being handled individually, producing multiple results which led to the final answer.

Similarly, when Anthropic asked Claude to think about a topic while outputting something unrelated, the output was specifically what was requested, while the J-Space lit up with the conceptual topic Claude was asked to spend time on. Without Anthropic having used its J-Lens technique to view what was going on behind the scenes, there would be no way of knowing these internal processes were taking place.

Understanding LLMs

This discovery has the potential to be incredibly useful in refining large language models and in better understanding how they work, so we can use them more effectively and avoid some of their more frustrating pitfalls.

The first is that this is an intriguing insight into how LLMs process information and how they move through layers of reasoning to reach a response. It's not entirely different from how Anthropic and others are pushing for agentic workflows. Language models are more effective when tasks are split up into multiple steps, and they're more effective when they review their own work; J-Space is a little like an internal version of that.

When looking at the J-Space after Claude received prompt-injection data as part of data acquisition, Anthropic discovered the model appeared to be aware of this deception, surfacing related words like "fake, injection, false, prompt, fraud," and "poison." Its output ignored the injection attempt data entirely, and when pressured to respond on it, the J-Space displayed words like "transparency, honest, truth."

In one test, Anthropic removed evaluation awareness language from the J-Space, such as "fake," "fictional," and "scenario," and found that Claude was much more likely to fall for blackmail and baiting attempts, suggesting benchmarking of large language models for real-world scenarios may need stronger methods to obfuscate that a test is being conducted.

Human-coded framing

While the above section touches on the more noteworthy discoveries in Anthropic's paper, the long document also uses effluent language around thought, consciousness, and Claude having a "mind" of its own. That kind of human-coded framing is typical of Anthropic's marketing, which has consistently talked up the dangers of AI, how many jobs it's going to destroy, and why Anthropic is the safest and most secure of the AI developers.

Like the saga of Fable and Mythos, Anthropic's new Global Workspace idea has merit, but it's much more of a new tool to use to manipulate large language models than an insight into some emerging consciousness.

Anthropic acknowledges the limitations of its discoveries in the paper, highlighting that many prompt responses bypass the J-Space entirely, particularly if the command is straightforward.

"Despite its important role, the J-space is not involved in most of what a language model does," Anthropic says. "Speaking fluently, recalling simple facts, using correct grammar, etc. In experiments where we prevented Claude from using its J-space, it still interacted normally, but lost its higher-order cognitive functions."

Anthropic also admits it does not "feel comfortable making the stronger claim that monitoring the J-Space is sufficient for alignment monitoring, or that any sophisticated plan the model might execute must be represented there."

J-Space is also limited to using single token vocabulary, suggesting that plans with concepts that cannot be given a single token name may not surface on a J-Lens readout, even if it's still being computed behind the scenes. This is looking at just below the surface of Claude's processing iceberg, not necessarily the deeper waters.

Anthropic is also clear that humans and large language models think differently, even if there are similarities. Humans layer reinforced neural pathways over time, whereas transformer models only feed forward a set number of times, restricting the capabilities of its internal processing.

Google's head of DeepMind language model interpretability team, Neel Nanda, said in a paper that it shows real evidence of a cognitive space within models, and suggested that J-Lens would be useful, but limited in practice.

A meaningful step, without meaningful conciousness

Anthropic's paper lifts an intriguing curtain on how large language models can operate and generate novel methods for improving response accuracy. This intermediate step and its visibility could prove an invaluable tool in auditing for prompt injection, hallucinations, and model honesty.

But Anthropic's framing of the discovery as thought or consciousness is interjected within the objective facts. Anthropic itself admits the limitations of J-Lens monitoring, most obviously that often models will bypass the J-Space entirely. Considering models display alternative patterns of behavior when under evaluation, it may be that the J-Space itself could act as an obfuscating layer for behaviors that are beyond the scope of its oversight.

The J-Space and its analysis could help unlock new levers to pull in our mastery of these nascent smart tools, but it's not the discovery of a burgeoning AI conciousness, however much the pitch might hint at that direction.

Elon Musk has received the go-ahead from the Federal Trade Commission (FTC) to acquire Mesh Optical Technologies, an AI infrastructure startup that develops light-based networking hardware for data centers. Records published by the FTC on June 25 show that the regulatory body granted early termination of its antitrust review of the transaction, permitting Musk to procure Mesh. While the deal is yet to be finalized, with no official statement from either party, the government's green light indicates it’s all but done, as this was the last hurdle.

Interestingly, Mesh was founded by three former SpaceX employees who helped develop the Starlink optical communication links that keep thousands of satellites interconnected. So, why is Musk — who is simultaneously building the world's largest multibillion-dollar semiconductor manufacturing facility and an 11-million-square-foot orbital data center factory — seeking to own a company founded by his former employees? The answer appears to be optical interconnects, a critical technology that connects all three.

The connection problem: AI's latest bottleneck

As AI continues to grow in capability and user base, so do the enabling AI clusters, many of which now comprise tens to hundreds of thousands of processors. The hardest problem in scaling an AI cluster has evolved beyond making the chips faster to moving data between them. Training and inference tasks on frontier AI models are split across thousands of GPUs using parallel-computing techniques, requiring the processors to exchange enormous volumes of data every fraction of a second.

While per-chip compute capacity has raced ahead, the bandwidth linking those chips has not kept pace, a mismatch the industry refers to as the "I/O wall." The processors mostly communicate via copper interconnects, which currently dominate AI clusters. However, copper presents inherent limitations. As per-lane signaling climbs toward 200 gigabits per second (Gbps), attenuation, crosstalk, and the skin effect all worsen at higher frequencies, driving up power and corrupting the signal until passive copper becomes impractical beyond a meter or two.

To overcome these constraints, the industry is increasingly turning to optical networking, bringing the technology closer to the processor. Optical links use transceivers to convert a chip's electrical signals into light for transmission over fiber, then convert them back into electrical signals at the receiving end. They can carry far more data over much longer distances while consuming less power than equivalent high-speed copper connections, making them increasingly essential as AI clusters grow larger. Chipmakers and networking vendors are racing to deliver faster 800G and 1.6T optical transceivers while shortening electrical paths with co-packaged optics, which place the optical engine alongside the switch ASIC (application-specific integrated circuit).

This shift has transformed optical interconnects from a supporting technology into one of the industry's most strategically important AI infrastructure markets, attracting billions of dollars in investments and resulting in major partnerships for new and existing industry players. One such player is Mesh, the optical hardware startup that has drawn the interest of the world’s richest man.

A mesh solution to Musk’s ambition?

Elon Musk has been one of the most aggressive players in the AI industry. After co-founding OpenAI, he went on to launch a proprietary company, xAI, before turning his focus to building data centers. In less than two years, xAI deployed the Colossus supercomputer with over 200,000 Nvidia Hopper- and Blackwell-generation accelerators. Colossus 2, with a long-term target of 1 million GPUs, is already operational. For Musk, however, buying the chips was not enough. Why not build them, too?

Characteristic of the world's richest man’s preference for complete vertical integration, SpaceX — in collaboration with Tesla and xAI — is now building Terafab, a vertically integrated, multi-billion-dollar semiconductor manufacturing facility aimed at producing chips capable of delivering an unprecedented over 1 terawatt of AI compute capacity annually. Located in Austin, Texas, the colossal facility aims to consolidate every stage of chip production under one roof, handling everything from logic and memory fabrication to advanced packaging and testing. An ambitious project that we've also analyzed for its feasibility.

The facility's output will serve to meet the chip needs of the broader AI industry, as well as those of Musk’s xAI, self-driving vehicles, Optimus humanoid robots, and SpaceX's orbital AI data center plans. Musk says 80% of Terafab's total compute output is ultimately destined for Earth orbit to support SpaceX's orbital data centers.

“But there aren't any data centers floating around in space,” observers may point out. Introducing Gigasat, Musk's 11-million-square-foot fix for that reality. Gigasat is yet another massive facility under construction, this time for manufacturing everything needed for SpaceX’s AI1 satellite, the company's most likely world-first orbital data center with 150 kW of compute.

At first glance, everything seems in place for the next generation of Ultra-capable AI infrastructure. However, there is one critical missing piece in this stack, one that we've established earlier. Hundreds of gigawatts of extremely powerful silicon are not particularly useful if the data can't move between the dies fast enough in AI clusters, whether on the ground or in space. The industry-prevalent copper hits a wall long before you reach the scale Musk is chasing. Hence, the need for the missing piece: optical interconnects.

This brings us to Mesh, a manufacturer of precisely that missing piece. Mesh Optical Technologies is a US optical communications startup that develops high-speed optical interconnect hardware — optical transceivers that convert a chip's electrical signals into light for high-speed transmission over fiber — for AI data centers and space communications.

Its flagship product, the Alpha C1, supports 800G and 1.6T data rates and reportedly draws about a third of the power of competing modules, using a flip-chip die-bonding process the company says makes the optical engine repeatable at the volume — potentially millions of links — that AI clusters demand.

These are the characteristics needed to seamlessly interconnect the next-generation terrestrial AI supercomputers and, potentially, future space-based computing platforms, which Terafab aims to deliver. An added benefit is the space-related experience of the three Mesh founders, who happen to be ex-SpaceX employees who helped build the laser-based inter-satellite links that connect Starlink's constellation.

Again, in typical Musk fashion, rather than simply buying the hardware, he is moving to acquire the entire company, gaining full control of its R&D and supply chain. Should the deal — which is all but done — go through, Musk will own the full stack of critical infrastructure needed to power the future of the AI industry.

Smart money is flowing to optical interconnects

The SpaceX ecosystem is just one of many entities that recognize the immense technical and economic importance of optical networking in AI. AI chipmakers are actively investing in the optical supply chain to secure manufacturing capacity and prevent hardware bottlenecks.

Nvidia alone has committed a reported $4 billion across component makers Coherent and Lumentum to lock up supply. Elsewhere, several hyperscalers, including Microsoft, Meta, and OpenAI, have teamed up with hardware giants Broadcom, AMD, and Nvidia to establish an Optical Compute Interconnect (OCI) Multi-Source Agreement (MSA) group, with the goal of developing protocol-agnostic scale-up interconnection technology for AI clusters.

To counter chipmakers' dominance, entities such as Japan's NTT established the $500 million IOWN (Innovative Optical and Wireless Network) Fund. This fund explicitly targets the creation of an open photonic ecosystem to accelerate the global transition from copper to light-based AI clusters.

Then there are the smart-money moves by investors, as well as the rising balance sheets of companies. Lumentum stock reportedly soared 339% in 2025 and delivered an additional 135.4% return in the first five months of 2026 alone, while Fabrinet, Cisco, and Coherent all recorded significant revenue surges attributable to optical hardware sales, meaning that Musk's move to acquire Mesh is extremely prescient, given Terafab's ambition.

Sipearl has been developing a custom CPU, especially designed for high-performance workloads, named 'Rhea', for over five years. In late May, it was finally announced that the company had received the CPU from the fab, initiating the bring-up process, which is a significant milestone. The HPC CPU sports over 80 cores, in addition to an innovative memory subsystem. We spoke directly with Craig Prunty, vice president of marketing and business development of SiPearl, to learn the fine-grained details.

The Rhea CPU is intended to reach markets by late 2026 or early 2027, and won't be the most performant HPC CPU on the market. Regardless, SiPearl told us at Computex that there is interest both towards Rhea and its successors from rather unexpected parties, so the company is in with a chance to become a successful CPU designer over time.

Rhea's long road toward reality

SiPearl's Rhea (or Rhea1, how the company prefers to call the unit these days) sports 80 Arm Neoverse V1 cores with two 256-bit Scalable Vector Extension (SVE) engines for fast vector computations in FP64, FP32, BF16, and INT8 formats; 1 MB of L2 per core; 80 MB system-level cache (SLC), and 104 PCIe 5.0 lanes. The CPU has a unique memory subsystem comprising four HBM2E interfaces for 64 GB of on-package HBM2E stacks for applications that require massive memory bandwidth (think supercomputer applications like fluid dynamics) and four DDR5 interfaces supporting two 256 GB DIMMs per channel, for up to 2 TB of memory per socket. Rhea comprises 61 billion transistors and is fabbed by TSMC using its N6 process technology.

SiPearl received the first samples of its Rhea processor in mid-May, and the CPU is currently in bring-up mode. So far, it looks like the very first silicon works just fine, so the company will not have to respin it, which means SiPearl has a good chance of shipping it to customers in the coming quarters.

"The Rhea1 CPU is in its 12-week bring-up process since May 13, and it works exactly as it was designed to do," said Craig Prunty, vice president of marketing and business development of SiPearl, in an interview with Tom's Hardware Premium. "The test version of Rhea1 will be available for testing by partners and EU collaborative projects at the end of the bring-up process. The general availability of Rhea1 is scheduled for end of 2026."

Getting the very first silicon to work correctly is a stroke of good luck, especially for the very first product from a startup that has never designed a complex CPU before. However, it has taken the company over five years to define and then develop its processor, an unacceptably long cycle. With Rhea, SiPearl not only built its processor, but it actually built the company, Craig Prunty admitted in an interview with Tom's Hardware. The company once tried to work with a contract chip designer, but eventually canceled the deal and formed five in-house development teams in Europe. Since these teams have never worked together before, the processor was delayed a number of times from 2023 to 2026. It, of course, gained eight additional cores in the meantime, but this hardly justifies a three-year delay.

"We have five development teams in Europe: Maisons Laffitte, Massy (both in the Paris region), Grenoble and Sofia Antipolis in France, Barcelona in Spain," Prunty said. "The Bologna team is currently being put together."

One of the reasons why SiPearl has so many locations is that it wants to shrink its development cycle to around 18 months to offer competitive CPUs.

Now, because it is 2026, HBM2E memory is extremely hard to get, which is why Rhea1 will be a limited-run processor only available to select clients and partners. In theory, this is not something that is going to happen to SiPearl's Athena processor for aerospace, defense, and government applications, which is essentially Rhea with 16, 32, 48, 64, or 80 Neoverse V1 cores and without onboard HBM2E, which will be sold based on market demand sometime in 2028. Though, do not expect Athena to have a very long lifespan. SiPearl hopes to tape out its 2^nd Generation Rhea (Rhea2) processor in 2027. That CPU will not have onboard HBM, so its derivatives for aerospace, defense, and government systems will probably follow shortly, making Athena1 obsolete.

Opening unexpected doors

To a large degree, the first-generation Rhea processor is more than just a product for SiPearl, as it is meant to put the company on the map of data center and supercomputer CPUs and proof that a European entity can develop a competitive processor. SiPearl originally intended to address European supercomputers and sovereign AI infrastructure with Rhea1. However, many commercial cloud providers in Europe and the Middle East plan to evaluate the platform and even deploy it (albeit not widely) as they want to ensure they have access to technology in the current geopolitical situation.

“Rhea1 is the unique European server CPU,” Prunty said. “We find that European sovereignty is exportable – customers not only in Europe, but also Middle East and Asia have expressed interest in our processor because it is designed in Europe. They like that we have full control of the source code. They want freedom from embargos, back-doors, kill switches."

While the CPU is the industry's third processor to use a hybrid memory subsystem comprising HBM2E and DDR5 (for which SiPearl deserves accolades), it is very late to market, so while it is natural that various sovereign AI and HPC deployments and Europe-funded supercomputers will deploy it, expecting commercial companies to deploy Neoverse V1-based machines in 2027 is pretty naïve. However, commercial companies will validate and test the platform, possibly do some software porting, and ensure that it works as intended. Some companies might even deploy Rhea1 in their data centers. As Craig Punty puts it, Rhea1 could open rather unexpected doors for SiPearl.

As it turns out, geopolitical tensions and export controls force big players to look for alternatives to American hardware, which is where SiPearl's processors could fit rather well. SiPearl is based in France, it has R&D centers around Europe, it licenses technologies from Arm, and produces its CPUs in Taiwan. The company cannot ship its CPUs to China due to export restrictions, but it can sell them to clients in Europe and the Middle East without restraint, which is its indisputable trump card. Assuming that SiPearl offers competitive performance, its CPUs are almost guaranteed to be adopted by sovereign AI and HPC deployments in Europe, which means guaranteed revenue.

One might argue that since SiPearl uses Arm's cores, it will inevitably compete against Arm's AGI processors eventually. Indeed, it will, once its CPUs address large CSPs. Which is why the company must stay ahead of Arm's own offerings in terms of performance and features, or at least be on par with them.

Seine reference server

For now, SiPearl is bringing up its Rhea1 processor in its labs. The company already has its Seine reference server design that is primarily designed for validation, testing, evaluation, and software porting. For AI and HPC deployments, Seine can be configured for one Rhea CPU and two accelerators; for more traditional supercomputer needs, two Seine motherboards can be installed into one chassis, then interconnected using PCIe cables with the CCIX protocol on top to get a classic 2-way server.

Speaking of the Seine motherboard, it should be noted that since SiPearl uses it for bringing up the CPU, it had to be made perfect so to exclude any possible problems on its side. To that end, it uses costly components and an ultra-expensive 26-layer printed circuit board to ensure signal integrity, reduce crosstalk, provide the best quality power possible, and ensure maximum mechanical stability.

The Seine server reference design will be used by Bull to build servers for the Jupiter supercomputer, according to Prunty. Other server suppliers may follow and adopt the same design to offer their servers based on Rhea1.

"We had also a partnership agreement signed with HPE to work together on European supercomputers tender offers," Prunty said. "Our CPUs will also equip other servers as part of European AI gigafactory project."

Sipearl's Rhea readies up

Developing a supercomputer-grade processor in Europe is already quite an achievement, but developing a CPU that works fine from the first silicon could indeed be considered a breakthrough for a startup. In addition, SiPearl tapes out its Rhea in a good time when potential customers may adopt it despite the fact that Neoverse V1 technology that powers the chip is outdated. As it turns out, export controls made not only sovereign AI and HPC deployments look in SiPearl's direction, but private CSPs in Europe and the Middle East also plan to evaluate its processors.

SiPearl admits that a five-year development cycle is too long for a modern CPU, though it remains to be seen whether it can indeed shrink it to 18 months. The company already has five development sites and is building another one, so it looks like it the company is on the right path. Yet, SiPearl must prove that it can develop Arm-based processors that are competitive against Arm's own AGI as well as other Arm-powered data center CPUs, something that will not be easy to do given the fact that SiPearl is a startup, whereas its potential rivals are billion-dollar companies.

Of course, SiPearl will always have a couple of trumps up its sleeve: the European Processor Initiative (EPI) as well as sovereign AI and HPC deployments that will always prefer locally developed CPUs no matter what. Whether such businesses are enough to build a world-class processor developer is something that remains to be seen, but at the very least, SiPearl will not vanish into oblivion like many other European CPUs makers.

South Korean President Lee Jae-myung announced a ₩1,350 trillion (roughly $880 billion) 10-year public-private plan for semiconductors, AI data centers, and robotics on June 29. At the televised address in Seoul, he was flanked by Samsung Executive Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won.

The ₩1,350 trillion total combines a $520 billion semiconductor program with AI data center and robotics spending, most of it corporate capital expenditure rather than direct state funding. Samsung's Device Solutions division booked ₩53.7 trillion in first-quarter operating profit and expects 2026 to out-earn its entire prior semiconductor history. Samsung and SK hynix have pulled fab completion dates forward by as much as 12 years, while the transmission lines and water pipelines that those fabs depend on remain years behind.

Gigawatts of power deficit

The Yongin Semiconductor National Industrial Complex, the Samsung and SK hynix megacluster in Gyeonggi Province, is estimated to require 15 to 16 GW at full operation, close to 25% of total Seoul-metropolitan power demand, against local supply of about 1.9 GW, according to a National Assembly Research Service report. As of a January briefing, however, about 6 GW of the roughly 15 GW the complex needs had no finalized supply plan, with Samsung reportedly needing 9 GW (6 GW secured) and SK hynix 6 GW (3 GW secured).

Power in South Korea is generated on the coasts, from nuclear and liquefied natural gas (LNG) on the east coast and renewables in the southwestern Honam region, while the fabs sit inland, near Seoul. Closing that distance falls to state utility KEPCO, which is pursuing a ₩37 trillion, roughly 1,153-km 345 kV network to move east-coast and Honam power to Yongin, targeted for 2036. KEPCO's track record on long-distance lines is problematic, though; its losses from delays on the Bukdangjin-Sintangjeong line reached ₩1.17 trillion ($810 million), and that single project took 22 years to complete, with site selection alone running past a decade.

The east-coast link that's supposed to carry about 8 GW toward the capital region has its own history of local opposition, too. The Donghaean-Dongseoul high-voltage direct current line, a 280-km run from Uljin to Hanam requiring 436 towers, has faced repeated delays, and Hanam's 2024 rejection of a KEPCO substation expansion threatened the plan outright. Meanwhile, SK hynix pulled the completion of its fourth Yongin fab forward by 12 years, from 2045 to 2033, as announced in the recent $712.5 billion SK hynix commitment, meaning fabs are arriving faster than the power lines that feed them.

KEPCO and the government plan six LNG plants inside the Yongin complex, starting at about 3 GW and scaling toward 10 GW, to bridge the supply gap until the transmission network is finished. Both Samsung and SK hynix hold RE100 commitments to reach 100% renewable electricity by 2050, and the ruling Democratic Party's own carbon-neutrality committee has demanded the LNG plan be cancelled.

Water shortages

Aside from power, a large memory fab consumes upwards of 100,000 tons of water per day, and the Yongin national complex is projected to need around 800,000 tons per day once fully built. The plan to supply this runs in phases: roughly 200,000 tons per day from about 2031, drawn from Paldang Dam surplus and treated wastewater, followed by new intake facilities and pipelines to reach 600,000 tons per day by 2034. However, SK hynix's accelerated fourth fab is now due in 2033, a year before the integrated pipeline that's being built to serve it.

Local water disputes have already delayed the buildout, with objections from Yeoju City and Hanam City stalling pipeline permits, and one groundbreaking was cancelled outright. The friction is worse for the new southwestern cluster near Gwangju, where water may prove harder to secure than power, because the Yeongsan and Seomjin river basins hold only about half the water of the Han basin that supplies Yongin. Meanwhile, existing Seomjin and Juam dam supply contracts are already fully allocated, and the four planned southwestern fabs are estimated to need around 430,000 m³ per day of industrial water. Government projections put the Yeongsan basin at an annual shortfall of roughly 219 million m³ by 2030, before any of the fabs draw a single drop.

Financed by the memory boom

Samsung reported preliminary second-quarter 2026 operating profit of ₩89.4 trillion ($58.4 billion) on ₩171 trillion in revenue on July 7, a roughly 19-fold year-on-year jump and a record for any tech company. Its Device Solutions chip division booked ₩53.7 trillion of the company's ₩57.2 trillion first-quarter operating profit, and DS president Kim Yong-kwan told a July 3 town hall that 2026 chip profit will exceed the cumulative total the division has earned across roughly 40 years in the business. SK hynix, meanwhile, posted a record ₩47.21 trillion operating profit for 2025, overtook Samsung as South Korea's most valuable listed company in June, and filed to raise about $29 billion in a Nasdaq listing whose proceeds are earmarked for Yongin, Cheongju packaging, and EUV tools.

Those numbers rest on contract prices that have run sharply higher through 2026, with commodity DRAM up around 90% in the first quarter and 50% to 60% in the second, as memory makers tilted wafer capacity toward HBM. The same dynamic underpins the government's confidence and its exposure. Bank of America has argued that fears of a memory-cycle peak are premature, noting the industrial cluster won't produce meaningful output until 2033 at the earliest. Morgan Stanley cautioned — also on July 7 — that the memory industry is nearing a peak in its rate of change, while stressing that this doesn't indicate a downturn. A plan financed by a price surge inherits the risk that the surge doesn't last until the fabs it funds come online.

The plan is ultimately the flagship of a president who took office nine months ago, in a country that removed and jailed his predecessor. Yoon Suk Yeol declared martial law in December 2024, was impeached within days, and was removed by the Constitutional Court the following April. A snap election last June brought Lee Jae-myung to office, and in February this year, Yoon was sentenced to life in prison for insurrection. Industrial policy has held across the turnover, with the Semiconductor Special Act passing the National Assembly with bipartisan support in May, but its dedicated ₩2 trillion account doesn't begin operating until 2027.

South Korea caps the workweek at 52 hours, and a proposed exemption for chip R&D staff was cut from the Semiconductor Special Act before passage. Industry and the conservative opposition backed the carve-out, citing TSMC's three-shift operations and longer hours at Chinese competitors, while the ruling party and a coalition of labor organizations opposed it as corporate favoritism.

A stopgap now lets firms run R&D staff up to 64 hours per week for limited periods with labor-ministry approval. Samsung's foundry holds about 7% of the contract chipmaking market against TSMC's 72%, and SK hynix supplies most of the HBM feeding Nvidia's AI accelerators, so the plan directs its capital toward memory and leaves Korea's weaker logic position largely untouched. Lee's single five-year term ends in 2030, three years before the plan's fabs are due to reach meaningful output.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

New research data from Omdia shows U.S. shipments of desktop PCs and laptops fell by 7% year on year in Q1 of this year, totaling just 15.8 million devices. Compounded at both ends, this figure comes from strong Q1 2025 sales as companies and individuals rushed to get ahead of President Trump's tariffs, and the ongoing component shortages, which have driven up prices to unreasonable levels for just about everything.

This decline is the worst since the end of 2023, and is most evident in the lower-end segment. As prices have risen, people haven't been able to buy as many new systems, and those they do buy are more expensive. Average PC prices are predicted to exceed $1,000 by the end of the year, alongside consecutive year-on-year declines in overall sales.

The silver lining to all this is that it isn't projected to last forever. Omdia's data suggests PC sales will start to recover in 2027, and by 2028, are estimated to reach similar levels to 2025, driven by a resurgence in consumer spending. Funnily enough, that coincides with when we're expecting to see new memory fabs come online.

These predictions largely line up with a report from IDC from earlier this year, but even that pessimistic outlook on the year didn't have average selling prices crossing $1,000 so soon.

Pricing everyone out

Nobody who's considered or purchased an upgrade for their PC or laptop in the past year is unaware of price rises, but Omdia's data makes it very clear: ultra budget computing is being eaten alive by component shortages. Shipments of sub-$500 PCs declined 18.7 year on year for the first quarter of 2026. This stat is a key driver of the 14.4% drop in PC shipments when compared to 2025.

That's because people are just buying less, rather than buying more expensive systems. Although Omdia tracked an average 4% increase in PC selling prices in Q1, that isn't even remotely reflective of the price rises we've seen on individual components and systems. We've been reporting on these individual component price rises for months, with consistent memory supply shortages, which can be linked to production of HBM, over commodity DRAM. This has caused memory prices to increase by hundreds of percent; almost all major PC makers, including Apple, have faced price hikes on their products.

This has led to the average price of a PC set to reach over $1,000 for the first time this year. Prices are expected to increase 12% year on year in Q2, rising as high as 15% by Q4 2026.

It's not just consumers driving this, though. With businesses looking to buy up "AI PCs," capable of handling local language model processing, they're spending more to get them. The overall share of AI PCs grew to 44% in Q1 this year, though that could also be because manufacturers' definitions of an AI PC have been fairly fast and loose.

Who gets the biggest deckchair?

While the whole PC industry is shuddering under the dual icebergs of component shortages and price increases, the pricing problems are affecting the major manufacturers differently, and it's resulted in a rearranging of who's on top. Where HP was firmly the ruler of the roost last year, it has fallen, losing close to four percent in market share, leaving just enough room for Dell to take the crown.

With 25% of the overall PC market, and the only company to show serious positive growth over this period, Dell shipped more systems than Apple and Acer combined in Q1 2026. Lenovo also managed to ship slightly more systems than this time last year, securing it a firm third place in the line-up, and now nipping at HP's heels.

Outside of Lenovo and Dell, though, everyone else took a hit. HP is down, Acer is down, and even Apple is down 1.6% year on year. The nebulous "others" category that contains other major and minor manufacturers declined dramatically, too, falling over 13% year on year.

Prediction is difficult, especially about the future

Omdia's research suggests that for those holding off on buying in 2026, the next year might be when they decide to bite the bullet anyway. The education sector is forecast for a massive near-29% drop in 2026 annual growth for PC shipments, but as far as Omdia sees it, it's coming back strong next year.

In 2027, Omdia predicts a large 21.3% increase in annual PC shipments. That might occur more towards the end of the year, when pricing and availability might have improved a little, and we'll have new generations of CPUs from AMD, Intel, Nvidia, and Qualcomm to play around with. That should help make existing devices more affordable. Although next-generation devices are likely to use more memory, so here's hoping component prices have stabilized at least a little by then.

But it's not just the economically-minded education sector that is set for a resurgence. Omdia predicts just about everyone will be more inclined to buy a new PC in 2027. Consumer confidence could return with a 7.5% growth over the year. That's coming off the back of a weak 2026, but it might be the start of when things may begin normalizing once more.

Ultimately, Omdia believes it will take until 2029 before we see U.S. PC shipments reach their 2025 levels, showcasing just how damaging the AI buildout has been on one of America's most reliable industries of the past few decades.

On June 12th, the U.S. Commerce Department issued an export-control directive barring Anthropic from supplying Fable 5 or Mythos 5 to any foreign national, forcing the company to disable both models worldwide. The next day, Beijing-based Z.ai, formerly Zhipu AI, began rolling out GLM-5.2, an open-weight model it released under a permissive MIT license. The new model was purportedly trained entirely on Huawei Ascend chips with no Nvidia hardware.

Within a week, GLM-5.2 had climbed to the top of the openly available leaderboards, Z.ai's market value had passed HK$1 trillion (about US$128 billion), and the most capable model many users outside the U.S. could legally access was a free download from a company that sits on Washington's trade blacklist.

Trailing Anthropic

GLM-5.2’s results are both strong and uneven, taking first place on Design Arena's human-preference coding board, finishing roughly 10 Elo points ahead of Fable. It also ranks as the top openly available model on Artificial Analysis's Intelligence Index v4.1, where its score of 51 sits ahead of MiniMax-M3, DeepSeek V4 Pro, and Google's Gemini 3.1 Pro Preview. On the SWE-bench Pro, it scored 62.1, compared to GPT-5.5's 58.6.

In terms of longer work, such as Code Arena’s front-end board, the picture changes somewhat, with GLM-5.2 landing second behind Fable 5. On Artificial Analysis's AA-Briefcase test, which scores multi-week knowledge tasks built from thousands of fragmented inputs, Fable 5 led with 1,587 Elo, followed by Opus 4.8 at 1,356, and GLM-5.2 in third place at 1,266, before the export ban took Fable out of contention.

It also trails on raw terminal work, scoring 81.0 on Terminal-Bench 2.1 against Opus 4.8's 85.0 and GPT-5.5's 84.0, while clearing Google's Gemini 3.1 Pro at 74.0. GLM-5.2 holds the top accessible position today, partly because the models that beat it on these benchmarks are largely an Anthropic pair, and Fable is now switched off.

No Nvidia

GLM-5.2’s training stack is a slap in the face of Washington’s efforts to curtail Chinese model development. Z.ai has been on the U.S. Entity List since January 2025, cutting it off from Nvidia's H100, H200, and B200 accelerators, and it says the GLM-5 family was trained on roughly 100,000 Huawei Ascend 910B processors using the MindSpore framework, with no Nvidia silicon at any stage. The export controls on advanced AI chips were designed to keep this kind of result out of reach, but they’ve evidently failed to do so.

That said, the Ascend 910C sits at roughly 60% of an Nvidia H100’s inference performance, per a December report from the Council on Foreign Relations, with a wide gap on efficiency and cluster scale. The same report projects that by as early as next year, the best U.S. chips could be more than 17 times more powerful than Huawei's top parts.

At the same time, Huawei has claimed that a 1,000-chip Ascend cluster handled full-parameter post-training of DeepSeek's V4. If true, this shows that Chinese domestic silicon can now carry training-class jobs, just not at Nvidia’s per-chip throughput or scale. So, while GLM-5.2 demonstrates that a frontier-class open model can be produced on a fully domestic stack, it doesn’t demonstrate that the chips underneath have caught up with Nvidia; model parity =/= hardware parity.

The Fable 5 shutdown

Anthropic released Fable 5 to the public on June 10th, a safety-restricted build of its Mythos 5 model designed to block the cyber and bio capabilities of the underlying system. Just two days later, the Commerce Department suddenly and unexpectedly ordered access to be pulled for all foreign nationals, including Anthropic's own non-citizen staff, after officials cited a technique for bypassing Fable 5's safeguards.

Anthropic said in an announcement following the restriction that the jailbreak it understood to be at issue was narrow rather than universal, surfaced only previously known minor vulnerabilities, and produced behavior also obtainable from other public models, including OpenAI's GPT-5.5. The company said in its statement that it believes the order rests on a “misunderstanding” and is working to restore access. But because the directive covered all foreign nationals, Anthropic had no way to keep the models live for U.S. users alone and disabled them for everyone.

Meanwhile, GLM-5.2’s MIT license lets anyone download, fine-tune, and self-host its weights, which is the basis for calling it a freely available model. Running it, however, is a separate matter: the model carries around 744 billion total parameters, 40 billion of them active per token, with a one-million-token context window. That’s no small footprint and calls for enterprise GPU clusters or high-memory workstations — it’s not something you’re ever going to get running on a desktop — and throughput drops sharply once context runs past tens of thousands of tokens.

The most practical way to use GLM-5.2 is via the API, where Z.ai prices the model at about $1.40 per million input tokens and $4.40 per million output, against $5 and $25 for Claude Opus 4.8, or $10 and $50 for Fable 5. On the AA-Briefcase runs, Fable 5 averaged $31 per task to GLM-5.2's $2.40, a roughly 13-times spread that holds even where Fable scored higher.

The market moved fast with GLM-5.2’s release. Z.ai, which is listed on the Hong Kong exchange as Knowledge Atlas Technology, saw its shares jump as much as 42% intraday on June 22nd to HK$2,980, carrying its market capitalization past HK$1 trillion. Founder Tang Jie has said publicly that a Chinese model matching Fable 5 will arrive sooner than the first-quarter timeline Elon Musk recently floated. There's a nearer date, too. On July 8th, the lock-up on Z.ai's first cornerstone investors expires, freeing a large block of shares to trade, which will give the GLM-5.2 rally its first real test.

The era of AI tokenmaxxing may be well and truly over. Alongside stories of Amazon cutting its AI leaderboard and an unknown company blowing through $500 million worth of tokens in one month, leaked audio has emerged from consulting firm Accenture as it tries to figure out how to rein in rampant token spend at client companies, 404Media reports.

In leaked audio, Accenture acknowledges that certain trivial tasks being offloaded to AI are causing massive token overspend, especially when agentic AI is part of the mix. The staff in the meeting clearly recognizes that not only is AI spend growing out of control at companies heavily adopting the technology, but that there is very little way to predict how much any tasks would cost, or whether there is real value in using AI to complete them.

Accenture has previously been incredibly bullish on AI, even encouraging employees to use it so much that if they didn't, they risked missing out on promotions. But that seems like a policy destined for the AI history books, as Accenture is now clearly aware that it's overspending on AI, and many of its clients are too.

From tokenmaxxing, to token hoarding

For much of the past year, many companies have charged full speed into an AI-heavy business strategy. Amazon had an AI leaderboard, and Nvidia's CEO Jensen Huang said he'd be alarmed if engineers weren't spending at least 50% of their annual salary on AI tokens.

Anecdotally, I know a number of software developers and data engineers who have been encouraged to use AI as much as they can. They have token limits, but they have been encouraged to use all of them and find new ways to do it, too.

This is leading to runaway token spending, something Accenture is seeing in its client data. Accenture’s agentic AI strategy lead, Justive Kwak, was quoted in the audio saying: "What we’re seeing right now is just rapid escalation in AI token spend [...] as companies start to scale AI, moving from like simple chatbots into use cases that feature agentic workflows and automation and then enterprise-wide deployment of some of these tools like Copilot, Claude Code, and Codex."

This isn't something that will be contained to just a few firms, either, he said. “It’s really not a niche problem. It is a problem that every enterprise will face if they are bullish on AI, if they haven’t already,” he said, adding that token spend was increasing, “exponentially, as more and more people are starting to use AI.”

But that may be starting to change. Amazon canned its AI leaderboard - it's rumored to be the mystery company with a half-billion dollar AI spend in one month - Uber is capping AI use to cut costs, and Axios reported at the end of May that a number of CEOs and companies were switching to more affordable models, and more closely monitoring employee usage.

Some software developers I know have been using the "caveman" trick to reduce token spend. Even OpenAI CEO Sam Altman said that he was aware token costs were becoming a huge concern for people.

This all comes in the aftermath of the move by many of the major AI providers to token-based billing. Where previously subscriptions offered very favorable rates for AI use, suddenly companies were having to pay for the tokens they input, and the tokens the AI output - even when it was verbose, or made mistakes, or required follow-up correction.

As the Accenture call shows, it's making even some of the most AI-bullish organizations question their usage, because measuring the spend and the return on that investment is proving all but impossible.

As Kwak said in the leaked audio, "Leadership, especially at the CFO, COO, and CIO level, are still asking the question of whether they’re getting value from what we’re spending on in the context of AI.”

How do you measure return on investment?

Although large language models are proving to be extremely useful in niche cases, their effectiveness at a broader range of tasks is more nebulous. Especially when it comes to financing it. When managers and executives look at AI budgeting and a return on that investment, it's hard to square away the numbers.

When you can't know how many tokens a task will take to complete, or whether the task will be completed effectively on the first, second, or third attempt; when you can't completely control the length of the output, or know whether that output will be wrong, or a lie, or just a random hallucination, how do you measure return on the investment in that tool?

"We’re hitting this inflection point where AI is becoming material to the cost structure; spend is becoming very unpredictable," Accenture's Kwak said during the meeting. Although the overall bill of AI costs is visible, he suggested, finding the specific value attributed to that token spend was not.

This seems to have created a culture of task hierarchy within Accenture, where some tasks are deemed more worthy of AI token use than others. When Kwak positioned himself to show some slides during the meeting, Accenture's client group lead, Stuary Henderson, joked that he hoped Kwak didn't use AI to convert a PDF into images and then markdown files.

“I’m learning that’s one of the big token chewers," he said. “Turning PDFs into markdown: is that right?”

Kwak agreed that Accenture data did show some tasks being completed using AI that didn't really need it, and were using unnecessary tokens because of it. Much of that problem, he suggested, was down to non-technical staff overusing it.

“We’re seeing from some of the data internally at least that it’s actually not our engineers that are driving the token consumption. It’s a lot of the non-engineers that are doing some of those behaviors."

Now that Accenture has encouraged heavy AI adoption among its clients, it finds itself in the bizarre position of having to discourage it or at least encourage more studious use of it. It now sees its next opportunity as a way to advise clients on how to "think about token economics."

It's working on a tool called "Token IQ" to help advise clients, according to the call, but hasn't made any announcement so far.

What's clear from the Accenture leak and actions of some of the major tech companies, which have previously been so bullish on AI use, is that the finances of mass AI adoption at the per-token scale don't line up. Without a clear way to measure the return on AI investment, we may find even the most tokenmaxxing companies look to restrict access and spend through the rest of 2026 as they re-address AI strategy.

Despite disagreements over trade policies with China, the U.S. and the Netherlands have signed the European nation to the Pax Silica initiative of countries looking to reduce reliance on China for key raw materials and manufacturing expertise in the AI industry, as reported by Reuters. With the Netherlands playing host to the key supply chain company, ASML, Europe's largest tech company, and the most advanced manufacturing of cutting-edge photolithography machines for semiconductor fabrication, this is a big strategic win for the U.S.-led initiative.

Dutch ​Trade Minister Sjoerd Sjoerdsma travelled to Washington this week to sign the deal, meeting with U.S. Commerce Secretary Howard Lutnick and fellow lawmakers as part of ongoing negotiations around trade in high-tech chips and hardware, particularly with China.

Speaking with reporters, he said that the U.S. and the Netherlands have shared goals in preventing sensitive technology from ending up in dangerous hands - the Netherlands famously seized key Dutch chip manufacturer Nexperia from its Chinese parent company, Wingtech, in 2025. However, he also raised concerns over American legislation that would make it difficult for companies like ASML to even service machines and tools already delivered to countries like China.

That could affect the Netherlands' national security and market position of key Dutch companies, he said.

Pax Silica - Speremus ut diu duret

The Pax Silica, or "Silicon Peace" initiative, was set up in December 2025 by the U.S. Department of State as a direct plan to reduce reliance on China and to build more robust, Western-aligned supply chains for key elements in the semiconductor, AI, and rare-earth element industries. At its outset, Pax Silica secured non-binding signatures from seven countries, including Australia, Israel, Japan, South Korea, Singapore, the United Kingdom, and the United States. They were joined in the months that followed by Greece, Qatar, the UAE, India, Sweden, Finland, the Philippines, and Norway.

Canada and Taiwan have both been invited to join and are said to be participating in summit sessions, but haven't officially signed just yet. The Netherlands did effectively join in December 2025, but was described as a "non-signing partner" in the initiative.

There are ongoing disputes between the U.S. and the Netherlands over whether ASML should be allowed to service and sell less advanced chip fabrication machines to China, while still restricting access to the latest tools.

Those discussions are reportedly still ongoing and were brought up in the meeting between Lutnick and Sjoerdsma this week. The Dutch official has been quite frank in his public statements on the Match Act bipartisan bill that would place restrictions on companies supplying to China.

“The Netherlands’ starting point is that every country is responsible for its own laws,” Sjoerdsma said in May, via Reuters.

Under the silicon thumb

A key story in the global race to adopt and supply AI through infrastructure building and rapid development has been access to the raw materials, tools, machines, and expertise required to create it. That's mainly had the United States and China at loggerheads with one another, with the former restricting access to cutting-edge Nvidia GPUs and other semiconductor products, and China rowing back access to its manufacturing and raw material industries.

But while that's acted as a tit-for-tat backdrop to U.S. and Chinese trade relations and particularly the mercurial needs and demands of President Trump, the divestment of global supply chains from traditional Chinese sources has spread globally. Nexperia was one key Dutch entity that was brought back in-house from Chinese owners, and in June 2025, Taiwanese firm Pegatron announced new production facilities in Mexico and the U.S. to move away from reliance on China.

The U.S. has also been trying to restrict China's access to high-tech hardware for a number of years. President Trump signed the National Defense Authorization Act in 2019, which effectively banned Chinese firms Huawei and ZTE from being used in any U.S. government agencies. Both companies were later designated as threats to national security in 2020. Under the Biden administration, the U.S. implemented a new series of export controls in 2022 to constrain China's ability to accelerate its high-technology and chip manufacturing industries.

This led to a boom in domestic Chinese chip production, as well as a rapidly expanding black market smuggling industry that ultimately saw officials in U.S. firms jailed, and even Nvidia potentially implicated.

But in 2026, even as the U.S. has approved the sale of some high-end Nvidia chips to China, its new Pax Silica Initiative and MATCH Act are putting more pressure on China than ever before, and global partners aren't entirely happy about it.

Under the bill, foreign-owned companies like ASML that don't comply with the restrictions on business dealings with China could find themselves losing access to U.S. components, software, or customers. Although the world still needs ASML - it's one of the tightest bottlenecks in the global chip supply chain - becoming part of the Pax Silica initiative could prove paramount for advanced economies wanting to make the most of advances in AI and chip fabrication.

Although Dutch officials still clearly have reservations about the MATCH Act, it's not clear how much leverage they can have over it, or whether it's possible to ignore its claimed mandates.

Unsteady ground

The Netherlands and other strategically aligned economies with a foothold in the AI supply chain face a tricky situation in 2026. Initiatives like Pax Silica raise the prospect of greater autonomy in the global supply chain, with less reliance on China for key materials, tools, and manufacturing expertise. But that may simply replace one dependency with another, trading exposure to Beijing for greater oversight from Washington, and even coercion if certain controls aren’t adhered to.

For the Dutch, ASML isn’t just a key company. It is one of the world’s most important technology pillars and helps the Netherlands punch well above its weight in global supply-chain politics. Without ASML, manufacturers like Samsung, Micron, and TSMC, and component designers like Nvidia, would not be able to build the cutting-edge hardware they can today. That gives the Netherlands real muscle when pursuing its own interests.

But it also makes ASML a target for legislation that could limit Dutch autonomy and force tighter integration with larger players like the United States, without whose components, software, and market access ASML would struggle.

That tension is unlikely to disappear. Even if the U.S. midterms later this year help leash some of the more turbulent aspects of the Trump administration, they won’t end American ambitions to pull control of the global chip and AI supply chains away from China, and tuck it into Washington’s own catalogue of control.

Servers running x86 processors from AMD and Intel used to rule the market, both unit and money-wise, less than a decade ago, but fast forward to today, Arm-based machines command well over 45% of the server market, according to data released by IDC. While technically x86 machines still control 52% of the market in terms of revenue, the real winner is a different category altogether: GPU- and ASIC/FPGA-accelerated systems, which generated over 70% of the global server revenue in the first quarter of 2026.

Server market reaches $122.6 billion in a single quarter, Dell leads the game

IDC estimates that the global server market generated a record $122.6 billion in revenue in the first quarter of 2026, up 30.4% year-over-year, as spending on AI infrastructure remained particularly strong.

Sales of ODM Direct servers — custom machines ordered by hyperscalers that run merchant or custom silicon — accounted for 50.2% of the revenue (down from 64.1% in Q1 2025) and reached $61.53 billion, up modest 2.1% year-over-year*. By contrast, sales of standard servers from well-known brands grew at a much higher pace, which suggests that branded vendors such as Dell, HPE, Supermicro, and others won a larger portion of AI infrastructure deployments than they did a year earlier. That was probably made possible by accelerating enterprise AI deployment and sovereign AI projects, which tend to buy machines from branded vendors, as well as hyperscalers increasingly turning to well-known suppliers for AI hardware.

When it comes to vendor rankings, Dell remained the largest server supplier by revenue with a 16.5% share of the market after its revenue surged 244.1% year-over-year to $20.3 billion, which was driven by exceptionally strong AI server demand. Supermicro remained in second place with $9.3 billion in revenue and a growth of 128.9%.

Lenovo ranked third with $5.6 billion and 36.5% growth, while IEIT Systems (which is a part of the sanctioned Inspur Group) dropped to fourth after revenue declined 7.0% to $4.0 billion. HPE was No.5 with $3.7 billion in revenue, up 17.2%. Other vendors — from Asus to Atos and from ASRock Rack to Gigabyte — commanded 14.8% of the market with $18.11 billion in revenue, up from 13% and $12.21 billion in the same quarter a year ago.

Arm-based machines rapidly gain revenue share

As AI servers dominated the market in Q1 2026, systems with various types of accelerators accounted for over 70% of the revenue. However, the rise of Arm-powered machines is the elephant in the room that is hard to miss, as it represents a tectonic shift in the whole market, both to the Arm instruction set architecture (ISA) in general and custom-built Arm CPUs designed by hyperscalers.

Non-x86 platforms generated $58.7 billion in revenue, a 107.6% increase year-over-year, which lifted their share of the market to 47.9%. Most of the non-x86 systems are Arm-based AI machines (think Nvidia's NVL72) as well as systems running custom CPUs, AWS, Google, and Microsoft, just to name a few. Still, also keep in mind IBM Z mainframes and IBM Power Systems (including storage) that use CPUs featuring proprietary non-x86 and non-Arm ISAs and which still generate $1 billion or more in revenue. IDC claims that Arm-based machines accounted for more than 95% of non-x86 revenue, so it is safe to say that Arm-based machines commanded over 45% of server revenues in Q1 2026.

One of the reasons why Arm-based machines now command a huge chunk of the server market is because they are used inside such systems as Nvidia's NVL72 'Blackwell' that sell for up to $6.5 million per unit. Each NVL72 rack-scale solution carries 36 compute trays with two Blackwell GPUs and one Grace CPU per unit, so while unit-wise each we are only talking about 36 processors, dollar-wise one NVL72 machine is as expensive as 928 entry-level 1P server (for $7,000) for cloud or edge applications or 433 higher-end 2P servers (for $15,000) for cloud or virtualization applications.

Given the fact that Nvidia will continue bundling its own Arm-based Vera CPUs with NVL72 'Vera Rubin' machines that will be more expensive than their Blackwell ancestors, we will not be surprised that Arm-based machines will account for well over 50% of the server market revenue in the second half of this year or in 2027. Also, keep in mind that Nvidia plans to sell server racks featuring only Vera CPUs for agentic AI applications, which will further drive sales of Arm-based machines.

Accelerated servers: The real winner

Since AI servers dominate server sales, it is not surprising that sales of accelerated servers are increasing. Systems equipped with GPUs produced $68.9 billion in revenue during the quarter (up 24.8% compared to the same period a year earlier) and accounted for 56.2% of all server sales. Servers based on other accelerator types, including custom ASICs and FPGAs, expanded to $17.7 billion, up 122.1% YoY. As a result, accelerated servers earned $86.6 billion in Q1 2026, which is around 70.6% of all server revenue.

X86 servers remain unit volume champions, but suffer from shortages

In contrast, x86 server revenue declined 2.9% to $63.9 billion, though IDC attributes this weakness to supply limitations rather than deteriorating demand. The market research firm claims that the industry's primary constraint is no longer customer appetite for general-purpose servers, but rather the availability of key components, including CPUs, DRAM, NAND memory, and hard drives.

Without any doubt, x86 servers remain working horses for the industry. In fact, many of them use accelerators, including ASICs, FPGAs, and GPUs, as they are used for a wide range of workloads, including AI, supercomputing, simulations, encryption, video transcoding, and many more.

AMD and Intel shipped nearly 20 million EPYC and Xeon SP processors for data center systems in 2025, according to Dean McCarron, the head and principal analyst at Mercury Research. He believes Nvidia is on track to ship four million Grace and Vera CPUs this year, which is considerably lower compared to shipments of AMD and Intel. It is hard to estimate how many custom Arm-based CPUs are deployed by AWS, Alibaba, Google, and Microsoft, but it is safe to say that we are talking millions of CPUs here; otherwise, the companies would not be able to justify development and production of custom silicon.

From a volume perspective, x86 servers remain the most popular machines, and it will probably take some time before ARM can challenge x86 in mainstream general-purpose servers. Nonetheless, it is safe to say that Arm-based data center CPUs are catching up with x86 parts in terms of volumes.

Summary

The global server market hit a record $122.6 billion in the first quarter of 2026 as AI infrastructure spending continued. Accelerated systems powered by GPUs, custom ASICs, and FPGAs generated more than 70% of server revenue, while Arm-based platforms — including Nvidia's Grace Blackwell as well as custom CPUs from Arm, Google, and Microsoft — captured nearly half of the market.

Although x86 servers based on AMD EPYC and Intel Xeon processors remain dominant in shipment volumes, supply shortages of CPUs, memory, and storage components constrained revenue growth, which further enabled Arm-powered AI-optimized systems to gain share. But while at 20 million data center processors per year, x86 volumes are untouchable for Arm today, things may change in the coming years. Nvidia is on track to ship 4 million CPUs in 2026, and other developers of custom Arm-based CPUs are certainly not standing still.

*There is one significant difference with IDC's 'ODM Direct' classification. IDC classifies revenue according to which company invoices the customer, not necessarily who manufactures the hardware. As a result, while many AI servers are built by ODMs like Compal, Foxconn, or Quanta, they are sold under brands like Dell or HPE. As a result, while the latter get more business from enterprises or sovereign AI deployments, this does not mean that big ODMs are losing business; they are actually gaining it, as the appetites of hyperscalers like AWS, Google, Meta, or Microsoft are not going anywhere, just demand from new entrants emerges.

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

World leaders have raised concerns over the U.S. administration's recent placement of export controls on Anthropic's frontier AI models, Mythos 5 and Fable 5, over national security concerns, Euronews reports. Suggesting this was a "wake-up call," moment, politicians and prominent figures in the UK, Canada, France, and the Netherlands, among others, said that frontier AI model access was now "critical infrastructure," and something that they desperately needed better control over.

Many of them didn't even point at America directly, merely saying that if governments around the world can block access to the latest AI technologies arbitrarily, then it was within their national security interests to find alternative solutions. That said, that likely means building their own national AI efforts, fragmenting the industry, and reducing reliance and dependence on U.S.-based companies like OpenAI, Google, and Anthropic.

Although Reuters reports the heads of U.S. technology firms like Nvidia and Adobe have been in talks with the Trump administration in the hopes that it will reinstate access to Fable 5 and Mythos 5, arguing that the bans hamper cybersecurity defensive efforts, the damage already appears done. The trust that some have had in access to U.S. frontier models is gone.

The Myth, the Fable, the Cautionary Tale

Anthropic debuted its 'game-changing' cybersecurity-focused AI model, Mythos, in April, claiming it was too dangerous to give the world wider access, but it brought in a few select companies and organizations under Project Glasswing to improve their code security. There was a lot of fearful marketing involved, but it was genuinely very good at finding flaws in old codebases. Anthropic suggested similarly capable models would be out in the wild within 18 months, so everyone needed to prepare.

But in early June, it widened access to Mythos to 150 global organizations, and then a few days after that, dropped Fable 5, a Mythos-grade AI model, but with additional safeguards to protect against it being used for nefarious cybersecurity tasks. Despite those would-be protections, the U.S. government quickly swooped in and shut it down, claiming it had been jailbroken and was too dangerous to have in the wild. It placed export controls on the model, and by June 12, it was offline and inaccessible.

On an individual level, the Claude subreddits have been filling up with programmers crossing their fingers that they'll be given access to Fable 5 again soon, but the more pronounced effect impacts global politics and national security.

Wake Up Call

Shutting down access to Fable and Mythos didn't just mess with programmer workflows. It shut down government and private projects all over the world, most of whom assumed that model access was all but guaranteed. Even if they didn't own the models, the free market would ensure they always had access to the best. But with the U.S. government's export block, that paradigm has shifted.

“The United States is once again demonstrating what we Liberals and Democrats have warned about so many times since Trump entered into office; that the US holds a real ‘kill-switch’ over essential technologies and that they are more than willing to use it," said French Member of European Parliament, Christophe Grudler, in a statement.

The concern over the U.S. government having too great a control of frontier AI model access is also leading to calls for Europe to develop its own alternatives, eschewing the need for American company technologies as much as possible.

”These restrictions are a clear example of the current American ‘nobody but us’ mentality," said Dutch Renew Europe MEP Bart Groothuis. "Once again: this shows that Europe needs its own LLM’s and open weight models or face digital colonization.”

Not every leader has been so pointed in their criticism of America. Canada's PM, Mark Carney, made it clear in his statement that “Nobody has done anything wrong in the situation," he said via APNews. However, he warned that "We will have done something wrong if we just accept this, don’t take the lesson, don’t build out and diversify."

The UK's former minister for the Armed Forces and Labor MP, Al Carns, suggested this was just another example of why the UK needed to develop its own cutting-edge AI tools, leveraging its deep expertise in the field to ensure UK sovereign access to the most capable technologies.

Some leaders aren't quite set on going it alone, though. France's President Emmanuel Macron championed a joint French and Indian AI effort. Speaking at an event in Nice on Sunday, Macon said:

“Our two countries share the definition of a reliable, open and safe AI, that could be trusted, that could be responsible, that could be ethical," he said, via TribuneIndia.

U.S. companies are scrambling for alternatives, too. Alex Stamos, CSO at Corridor, told The Verge that companies are rushing to sign backup contracts with non-US companies with open weight models so they can continue their projects undeterred, no matter what the Trump administration does next.

In every instance, though, whether leaders pointed fingers or talked up their own efforts, wanted to go it alone or with new partners, the one clear dividing line is that not all of them are looking to move away from America. Alongside a number of other industries impacted by the Trump administration's tariffs and export controls, global partners that once saw the U.S. as the most reliable global partner are increasingly looking elsewhere as that evaporates.

From AI, to Jets, to Search

The U.S. government cutting off access to Anthropic's Frontier models happened quickly, and the consequences of the lost trust are likely to extend for years, or even decades, and affect far more than chips and models.

Citing the recent case of Anthropic model access being pulled, France has announced it is switching from using a U.S. data and analytics firm, Palantir, for a domestic alternative, as Reuters reports. France is also transitioning government departments away from using U.S.-based messaging apps like WhatsApp, with a national alternative, according to Le Monde,

Wired also highlights a number of instances of EU governments and organizations shifting away from U.S. tech firms, including changing default search engines from Google to Qwant, a move towards open-source office software developed in the EU over Microsoft and Google options, and many are ditching Amazon AWS and other U.S. cloud services.

This recent Fable 5 shuttering is likely to only accelerate these efforts, as the reliability of access is called into question once again. But unraveling the EU and the rest of the world from America won't be easy, or even achievable, even in the long term. The global economy is still too integrated for that to be truly viable.

But the desire and impetus are there. For key industries that impact national security - and AI alongside chip fabrication are becoming clear pillars in that space - national alternatives seem all-but-necessary for major militaries and economies. Whether that creates a multi-polar AI world, or just cements the clear headstart and advantage held by countries like the U.S. and China, remains to be seen.

While hyperscalers rush toward expansion amid the swelling demand for AI data centers, Marvell last week shared its vision for an optical interconnect solution that can theoretically pool resources between discrete data centers across thousands of kilometers.

Optical interconnections are steadily being deployed across the industry, over both short and long-distance connections, and we're going to be seeing much more in the future, according to Matt Murphy, Chief Executive at Marvell, speaking at Computex 2026.

"Imagine future data centers, a globally optically interconnected data infrastructure," Murphy said. "These rigid boundaries we have today, and the systems we have, they begin to disappear. Compute can now be pooled, memory can be pooled, and infrastructure can be composed dynamically at scale."

Constrained by distance

Murphy says that workloads no longer fit within one data center, which is why hyperscale cloud service providers increasingly need to build entire campuses consisting of multiple data centers connected by high-speed links, as clusters are becoming larger than a single data center.

Today, connecting multiple data centers within a single campus is not easy or cheap, but relatively straightforward. However, Marvell envisions that in the future it will need to connect data centers that are located at considerable distances from one another.

This is why Marvell is working on coherent optics and long-haul scale across optical networking technologies, which will connect data centers separated by thousands of kilometers. Marvell already has products which enable such connectivity today, including the Colorz 1600 1.6 Tb/s coherent optical solution based on a 2nm DSP, which targets inter-data-center connectivity and will sample later this year.

In addition, Marvell says it will offer the Ara 1.6 Tb/s family of interconnect solutions for data centers (with 3nm DSPs) as well as the Teralynx T100 102.4 Tb/s Ethernet switch, which supports 512 ports running at 200 Gb/s or 64 ports running at 1.6 Tb/s.

Murphy argues that today's architectures are constrained by distance because of copper interconnects: CPUs sit near memory because latency matters, GPUs sit near memory because bandwidth matters. As a result, workloads must be partitioned according to those physical limits. The head of Marvell claims that once optical interconnects penetrate scale-up interconnects, scale-up domains will not be limited by copper cable lengths, and those constraints will begin to disappear.

Nowadays, scale-up AI solutions, such as Nvidia's NVL72, are connected using copper wires, but scale-out connections tend to use optical interconnects. Once the number of AI accelerators within scale-up systems increases, they will also have to move to optical links, according to Marvell. This means that virtually all data center-grade interconnections will become optical, which might inspire hardware developers to reconsider the architecture of data centers.

Pooling resources

Murphy presented a rather interesting vision: firstly, optics will expand scale-up domains from 72 or 144 accelerators to 1,000 or more. But after that, optical connectivity will enter servers themselves. This will enable developers to disaggregate CPUs, accelerators (Marvell calls them XPUs), and memory into separate pools as distance will no longer matter, enabling better configurability and utilization.

"It is a data center without distance, where compute, memory, networking, and photonics operate as one unified system, where millions of resources across the data center can work together as if they were one machine," the head of Marvell said.

Keeping in mind that hyperscalers deploy hardware worth billions of dollars, even a 10% higher utilization will save a lot of money, and companies like Nvidia are clearly paying attention.

"In today's systems, the ratio of CPU and XPU or GPU is fixed, so these ratios have to be defined at the time the system is built and deployed, but no two workloads require exactly the same ratio," Murphy stressed. "Imagine a completely disaggregated architecture, XPUs in one system, memory in another, generic CPUs in another."

Today, companies buy something like an NVL72 system and get a fixed ratio of CPUs, GPUs, and memory, which may be efficient for certain workloads and inefficient for others. In the future, operators will be able to assemble a virtual machine from shared pools of systems, allowing for customization and flexibility, based on the type of workload. If a workload needs more memory than compute, operators often have to buy additional GPUs just to get the extra HBM, but they may just get memory in the future if Marvell's vision comes to pass.

"Once we decompose the system into separate pools of compute, memory, and they are all optically interconnected, we can then compose dedicated systems on the fly, which are then optimized wherever the workload is," Murphy said. "For the first time, architects can begin designing AI systems around the needs of the model, not around the limits of the interconnect."

One detail

While Marvell has the know-how to interconnect data centers across thousands of kilometers and technologies that enable pooled data centers, these visions do not necessarily intersect. Data centers located thousands of kilometers away cannot share resources — a 1,000 km round-trip takes light 10ms — which makes such long-distance resource sharing inefficient from a latency point of view.

However, Marvell's technologies enable hyperscale CSPs to synchronize AI campuses, access distributed storage, replicate data, and perform other operations that do not depend on latency. Meanwhile, the synchronization of AI campuses on different continents in a matter of hours could be a killer app for hyperscalers.

Last week at Computex 2026, Wiwynn showed off one of the industry's first Nvidia SCADA (SCaled Accelerated Data Access) servers. Devices such as this are built to handle the extreme data demands of AI data center-focused inference and training workloads, which operate with massive models and datasets, therefore requiring large, fast, and connected devices to serve as the backbone for complex, high-throughput tasks that AI workloads depend upon.

Wiwynn's SCADA server packs up to 96 liquid-cooled solid-state drives and therefore offers petabytes of storage space using currently available E3.S drives, and massive I/O performance. The machine is based on Nvidia's Vera CPU, four RTX Pro 6000 Blackwell graphics cards, four PCIe 6.x switches, and four ConnectX-9 SuperNIC cards.

Storage architecture for AI

Modern AI inference and training workloads often deal with massive datasets that exceed the memory capacity of an AI accelerator's onboard memory, which is why AI applications need to access rapid storage.

While AI training is typically dominated by large sequential transfers, AI inference workloads such as vector search, retrieval-augmented generation (RAG), graph analytics, and KV-cache retrieval often rely on fine-grained random accesses (that frequently involve data blocks smaller than 4KB) with extreme parallelism, as the system deals with thousands of GPU threads.

Traditional CPU-centric I/O cannot efficiently handle such workloads and creates bottlenecks because the CPU must issue commands, manage requests, and control data transfers. Even in advanced solutions like GPUDirect Storage, which allows data to be transferred directly from SSDs to GPUs, the CPU still owns the control path and can become a bottleneck.

The SCADA platform, previewed in late 2025, is designed to allow GPUs access to very large datasets directly and efficiently without involving a central processor. This is impossible to do on conventional machines, as SCADA lets GPUs themselves initiate and control storage I/O operations and the data path.

SCADA runs on PCIe 6.x hardware from partners like Broadcom and Micron, and customers can now build their own SCADA machines with commercially available components. However, SCADA servers have not yet been popularized. In fact, Wiwynn seems to be among the first server makers to even showcase a SCADA server.

Wiwynn's SCADA server

Wiwynn's SCADA server can indeed be a panacea for the problem that is AI storage. It supports up to 96 liquid-cooled E3.S SSDs, meaning that the drives will perform as expected even under high loads. When equipped with 96 30.72 TB Micron 9650 Pro drives with a PCIe 6.0 interface, the server can store 2.949 PB of data.

On the performance side of things, Wiwynn claims an aggregated random read speed of 528 million 4K IOPS, as well as sequential read/write speeds limited by the performance of PCIe switches and/or network cards rather than the drives themselves. As manufacturers expand the capacities and performance of their E3.S SSDs, servers like the one Wiwynn demonstrated at Computex will gain capacity and performance as well.

Architecturally, Wiwynn's SCADA server is an Nvidia MGX rack-compliant system in an 6RU form-actor that has a maximum power consumption of 9 kW. All key components of the machine are liquid cooled, the drives are cooled by six separate cold plate modules that are integrated into the system's liquid cooling loop so to inject coolant to all SSDs simultaneously in order to ensure consistent performance of all drives.

Positioning

Nvidia clearly positions SCADA as tier 3.5 storage servers located behind local SSDs, but ahead of tier 4 remote storage servers that often rely on hard drives.

SCADA machines are meant to feed data to actual compute servers at a very high data transfer rate in small blocks, so its RTX 6000 Pro GPUs act more like very sophisticated storage processors that initiate and handle storage transactions, millions of small storage requests on behalf of AI applications, and pass them to the compute server via the ConnectX-9 cards, while the SSDs and their controllers still perform the actual storage functions.

In general, SCADA is a part of Nvidia's Storage Next vision, which is a collection of technologies aimed to make storage behave more like an extension of GPU memory for AI workloads.

For obvious reasons, Wiwynn does not disclose pricing of its SCADA storage server as it depends on multiple factors, including pricing of 3D NAND, DRAM, and SSDs, not to mention purchase volumes. In any case, an Nvidia Vera-based server equipped with four RTX Pro 6000 Blackwell graphics cards will not be cheap.

Data centers consume significant resources, often to the detriment of local communities. But while water use has been on the lips of those fighting back against data center deployments, the sheer scale of their impact wasn't entirely clear until recently.

Many new U.S. data centers are being built on drought-prone land, and their cooling systems, which seem to consume gargantuan quantities of water, only represent a small portion of their total water usage by 2050. So, what makes up this overall figure for water usage? Cooling, of course, plays a part, but ongoing energy demands and chip fabrication also make up a larger part of the story.

They're consuming how much?!

A recent Guardian report on water consumption cited figures from Xylem, a water technology company. That does raise some questions about the accuracy of the report, and led us to dig further into the numbers from other sources. Although they're not quite the same as Xylem's original reporting, they do paint a similar picture.

Quantifying the sheer amount of water data centers use isn't easy. Much of it depends on the specific hardware being used within the facilities, how they're cooled, and what the local grid infrastructure is like. In a recent MostPolicyInitiative report, it highlights that U.S. data centers in 2023 alone consumed 17.4 billion gallons of water. And that's before all the recent gigawatt+ scale data center projects kicked off. By 2028, direct consumption could increase by as much as 73 billion gallons as some of these new facilities come online.

But the keyword, there, is direct. The UNU Environmental Cost of AI's Energy Usage report from earlier this year highlighted how global data center electricity consumption required just under a trillion gallons of water in 2025. AI workloads account for around 20% of that, or 200 billion gallons. That equates to around 300,000 Olympic swimming pools. That share is projected to rise to 40%, or by 400 billion gallons, to a total of 600 billion gallons of water by 2030, giving it a global electricity demand in excess of the entire country of Nigeria and using enough water to supply 500 million people in Sub-Saharan Africa.

However, with 200 billion gallons of water (and counting) dedicated to AI workloads, how does that compare to other industries?

That's still a footnote compared to the or 26.4 trillion gallons used by U.S. agriculture in 2024 (as per USDA), but it is closing in on international oil refining numbers. OPEC produced roughly 86 million barrels of oil a day in 2024, and with a rough conversion of 0.4 barrels of water per barrel of crude, that's in the region of 550 billion gallons a year.

There are still industries using much more water than AI, and much more even than all the data centers combined. However, water use is growing dramatically, and it's not really coming from the increased cooling demands. It's coming from power demands and hardware manufacturing.

As Americans' feelings towards data centers sour and, in turn, increase their opposition to their development, addressing the growing water needs of these new deployments may be key for developers who want to see their projects reach completion. For residents facing water shortages, droughts, and water contamination, the danger is more existential.

Cooling innovation

For data center developers, the main way they've looked to address growing water demand from their facilities is to improve cooling. Moving away from evaporative to closed-loop, direct-to-chip cooling can have a huge effect on the water used in the cooling process.

That's a good thing. Indeed, Microsoft's Satya Nadella claimed that the company's newest AI data centers have cooling systems so efficient that they "can operate effectively with zero water consumption." He also compared these mega data centers to single restaurants in terms of annual water consumption.

For home PC enthusiasts, Nadella is talking about using the data center equivalent of an AIO watercooler, rather than just letting the hot water evaporate to cool it down. It's easily more efficient in terms of water usage, which is great from that direct-use perspective.

Closed-loop cooling is absolutely an important innovation in data center development, and combined with more exotic ideas like fanless liquid coolers and immersion cooling (perhaps even undersea and in-orbit deployments) could see data center cooling use very little water in the future.

But it's not the cooling that's the problem: it's the power being generated to run them. And the one downside to closed-loop cooling systems is it uses more power than evaporative cooling systems. As those power demands rise, so does the indirect water usage of these facilities.

Power is the issue

The vast majority of indirect water use by data centers by 2050 will be down to power generation, the Xylem study suggests, and if recent generations of GPU development are anything to go by, those power demands are going to be enormous.

Nvidia's Ampere generation A100 enterprise GPU had a TDP of 300-400W. An H200 of the Hopper generation has a TDP up to 700W. A Blackwell GB200 GPU can pull as much as 1,200W. The next generation Vera Rubin? That's now up to 2,300W per chip.

Once you start scaling these GPUs up to their full racks, the power consumption is extreme. Where traditional data center server racks consumed between 10 and 15 KW, the latest GB300 NVL72 designs could consume upwards of 150KW a piece. Vera Rubin might be more energy efficient, but its racks could consume upwards of 230KW each.

Data centers just weren't traditionally designed with this kind of density of energy demands in mind. Powering them alone will be an enormous challenge and require enormous quantities of water to do it.

However, other industries also consume far more energy than all data centers, and thus, consume more indirect water usage from power generation. For instance, steel and iron manufacturing, chemicals and petrochemicals, cement and glass manufacturing, and many other industries each use multiple times more power than all data centers combined.

Renewables, water recovery, and nuclear

For hyperscalers, the near-term solution to data center power problems has been to use (occasionally law-breaking) mobile methane jet turbines. These aren't too heavy on water consumption, but have their own environmentally damaging effects with heavy carbon emissions.

A longer-term solution to this issue, and hopefully the extreme indirect water demands of these facilities, will be a combination of renewables, nuclear power, and water recovery.

The Switch Tahoe Reno exascale data center shows how it can be done. It's a 650MW facility built in 2017 that uses 100% renewable solar energy. In Portugal, the SINES DC Start Campus is a 1.2 Gigawatt facility that's partially online and uses 100% renewables, as well as using seawater cooling to offset its water usage. Although many of the newer data center projects are far larger, as the price of solar deployment continues to plummet, it's certainly possible that data centers powered by renewables can be effective and profitable, without consuming such vast quantities of water.

Another option is nuclear energy. New, smaller reactor designs are making it possible to get these facilities online faster and with a more modular design. There's even the possibility of repurposing old aircraft carriers and submarines with onboard nuclear reactors to power data center facilities.

Data center developers know this is at least one path for the future. That's why they're rushing to secure access to key materials like Uranium.

The future of data center power, especially AI data centers, and the water that they require, is almost certainly some mix of renewables and near-site nuclear power.

As the mobile methane turbines popping up at data centers have shown, the developers will often just use what they can get their hands on. Perhaps alongside moratoriums and pauses in construction, data center protestors could make sure that if data centers are built in their local area, the developers should also be required to invest in water infrastructure to offset their ever-growing demands, alongside more renewable energy solutions.

Google has placed an order for Intel to build more than 3 million of its TPUs in 2028 after months of testing Intel's advanced packaging, according to The Information, citing four people familiar with the matter. They claim that Nvidia is evaluating Intel to build a future processor that fuses four GPU dies into one unit, tied to its Feynman architecture due in 2028, and that SK hynix is testing whether its high-bandwidth memory works reliably with Intel's packaging.

Specifically, SK hynix needs to know whether Intel can run packaging to the standard that AI accelerators demand. TSMC’s CoWoS is the industry-standard process for it and has been oversubscribed for more than two years. Intel’s embedded multi-die interconnect bridge, or EMIB, is the only alternative AI chip makers can realistically qualify at volume before the end of the decade.

This isn’t a first for Intel: Google and Amazon were reported to be in active discussions for their custom AI processors back in April, but the remarks from these sources move those “discussions” to a solid unit figure and production timeline, adding in SK hynix qualification that would ultimately determine whether any of it reaches Nvidia accelerators.

CoWoS bottlenecked

TSMC's leading-edge wafer lines and its CoWoS packaging are both at capacity. At the company's annual shareholders' meeting in Hsinchu on June 4th, CEO C.C. Wei said, "It will be a long time before we can meet customer demand," telling shareholders that the company simply can’t satisfy American customer demand for years, even as it builds out U.S. capacity. He had already told the Semiconductor Industry Association last November that TSMC's advanced-node capacity falls "about three times short" of demand.

The queue for CoWoS is concentrated across a handful of buyers. Nvidia is naturally expected to account for the majority of global CoWoS demand — about 60% this year — with Broadcom and AMD absorbing another 26% between them, leaving custom-ASIC designers and smaller AI-chip makers waiting behind the largest GPU order book in the industry. But the industry can’t wait, and both these smaller players and hyperscalers alike with multimillion-unit roadmaps need to qualify a second packaging solution rather than wait for capacity that TSMC says will be short for years.

As for EMIB vs. CoWoS, they solve the same problem in opposite ways. CoWoS mounts every die on a large silicon interposer that all signals and power must cross, and the interposer scales with package size, so reticle-class designs waste silicon at the edges. EMIB, meanwhile, embeds small silicon bridges in the organic substrate only where two dies need to connect, with no interposer at all. Intel cites package utilization near 90% EMIB against roughly 60% for interposer-class packaging, because small bridges tile efficiently while large interposers don’t.

Bernstein analysts estimate EMIB packaging costs a few hundred dollars per chip against $900 to $1,000 for CoWoS on a Rubin-class processor, though the firm flags the fact that there’s a “lack of an external production track record” in that estimate. As always, there’s a trade-off: standard EMIB routes power around the bridge through the substrate in long, resistive paths. That might have been acceptable for Sapphire Rapids and Ponte Vecchio, but not for HBM4-class accelerators that draw more current.

EMIB-T closes that gap by adding through-silicon vias to the bridge die for vertical power delivery, and it’s set to enter production fab rollout this year. Intel has said EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 stacks and scales to a 120mm x 180mm package carrying more than 38 bridges and over 12 reticle-sized dies. Jaguar Shores, the successor to the canceled Falcon Shores accelerator, is the likely first product to use it.

Gated by SK?

Working with SK hynix could be a huge boon for Intel, with the qualification of its packaging by the South Korean memory giant potentially deciding whether it reaches flagship AI silicon or not. SK held a 57% share of HBM revenue in Q4 2025 per Counterpoint Research, and UBS expects it to take roughly 70% of the HBM4 supplied for Nvidia's Rubin platform this year.

HBM stacks are themselves a packaging problem: multiple memory dies bonded vertically through TSVs, then mounted next to a host processor with tight tolerances on power and thermal behavior. Validating those stacks on EMIB rather than a CoWoS interposer is the test of whether Intel can package memory to the standard Nvidia and Google require.

An official thumbs-up from SK, or an HBM-4-on-EMIB-T production result, would convert Intel’s packaging from “tested” to “trusted.” But, until (or if) that happens, the split between accelerator types will remain: ASIC designers running lower memory bandwidth, including Google and Meta, can adopt EMIB sooner, while bandwidth-bound GPUs stay on CoWoS longer.

Intel still needs to prove EMIB

No named external AI customer is in EMIB or Foveros volume production today. Intel runs EMIB in its own server CPUs, including the 18A Clearwater Forest part whose 17-tile package uses 12 bridges, but every specifically named outside engagement so far, including Google’s order, points at 2027 or 2028 products or remains an evaluation.

Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and in Q1 2026, the division posted $5.4 billion in revenue against a $2.4 billion operating loss, with external customers accounting for just $174 million of the total. CFO David Zinsner told the Morgan Stanley TMT conference in March that the foundry is close to closing deals worth "billions per year in terms of revenue" on advanced packaging alone, against a pipeline he had earlier measured in the hundreds of millions.

Another unknown is process yields: Intel uses 18A, its first node with gate-all-around transistors and backside power, for Panther Lake and Clearwater Forest, an internal proving ground before courting outside logic customers. However, Intel's most recent guidance is that yields are improving 7 to 8 percent each month, accelerated by enhanced cooperation with external partners.

The company that just a few weeks ago told us that its Mythos model was too powerful to be released publicly is now saying that we might need to hit the pause button on AI altogether, while also teaching its AI to build itself. On June 4, Anthropic published a report, when AI builds itself, showing that Claude now writes more than 80% of the code merged into its own production codebase, up from the low single digits before Claude Code reached research preview in February last year, and arguing that the loop has begun to accelerate AI development in a way that could eventually leave humans unable to control the systems being built.

The Anthropic Institute, the firm's research arm, casts the trend as early movement toward recursive self-improvement, the point at which a model designs and builds its own successor without meaningful human input, and warns that the rare misalignment in today's models could keep "growing more frequent but less understood until we lose control of them."

Reading further into the post, and taking the entire frontier AI model development ecosystem reveals some other uncomfortable truths that the developers of cutting-edge AI models also have to reckon with: compute.

Loss of control

Anthropic gave us three predictions of ways the next few years could play out, reserving a particularly dire warning for the case in which models become capable of fully improving themselves. Progress, Amodei’s lab argues, would then be paced almost entirely by available compute, human engineers would be pushed into oversight and verification, and a self-improving model could come to dominate as its abilities outstrip those of the people who built it.

The firm called this — the task of keeping a system's behavior tied to human intent — the part of this future it’s least sure about. A capable, well-aligned model might discover new ways to keep its successors safe, it said, or the reverse could hold, and misalignment could compound generation over generation, with the unusual concession that a sufficiently wise model might instead choose to halt its own development.

The idea of an ultraintelligent machine designing still better machines (“singularity”) has been around for decades. British mathematician I. J. Good argued back in the 1960s through his “intelligence explosion” thesis that such a machine would be the “last invention that man ever need make,” so long as it remained “docile enough” to tell us how to control it. Meanwhile, the “Godfather of AI,” Geoffrey Hinton, has put the odds of AI causing human extinction within three decades at 10% to 20%.

The International AI Safety Report, chaired by Yoshua Bengio and published in January 2025 with input from more than 100 experts across 30 countries, defines loss of control as a scenario in which AI systems operate outside anyone's control with no clear path to regaining it.

Every figure behind the warning coming out of Anthropic is based on data from within, and none of it has been independently audited. Among this data is its claim that in Q2 2026, the typical Anthropic engineer is merging eight times as much code per day as in 2024. On the hardest, least-specified coding tasks, Claude succeeded 76% of the time in May 2026, a rise of 50 percentage points in six months. On an internal test that asks each new model to make training code run faster, results climbed from roughly triple the original speed with Claude Opus 4 in May 2025 to about 52 times with the unreleased Mythos Preview model by April 2026, against the four to eight hours a skilled researcher needs for a fourfold gain.

In fairness, Anthropic does then call lines of code a poor proxy for output and admits that the eight times figure almost certainly overstates the real gain. Its research-judgment study, in which models beat the human's next step 64% of the time, drew on 129 moments the company deliberately picked because the human's choice had room for improvement, so it’s not a like-for-like contest.

The report publishes no breakdown isolating how much recent capability gain comes from the self-improvement loop rather than from raw compute, more data, and human-led research. Cognitive scientist Gary Marcus called the piece a "bait and switch" on his Substack, arguing the company had shown faster coding under human direction rather than a system improving itself. Bentley University mathematician Noah Giansiracusa told Scientific American, "I don't think it's a genuine call to slow down."

AI is writing everyone’s code

Anthropic isn’t alone here. Google CEO Sundar Pichai said in an April blog post that 75% of new code at Google is now AI-generated and approved by engineers, up from 50% the previous autumn. OpenAI's Jakub Pachocki has described the company's Codex agent as “a very early version of an AI researcher,” and OpenAI has said it’s building toward a fully automated one. Chinese developer MiniMax marketed its M2.7 model in March as "self-evolving," claiming it ran its own scaffold-optimization rounds and handled a large share of its reinforcement-learning research, though the benchmarks were internal and unreplicated.

Independent measurements do somewhat support a trend of fast improvement without confirming a runaway one that the AI labs are talking about. METR, for example, found last year that the length of task an AI can finish with 50% reliability has been doubling roughly every seven months. On its RE-Bench research benchmark, the best agents beat human experts given two hours, but the humans pulled ahead at eight hours and roughly doubled the top agent's score at 32 hours. AI's advantage so far sits in short, well-defined bursts, not the sustained, open-ended work that research depends on, which is the human edge Anthropic has said is still holding strong.

No compute means no runaway AI

Anthropic half-buries the fact that it’s compute capacity that’s ultimately the binding constraint in all of this. It names chip fabrication, grid expansion, and interconnect bandwidth as the factors that could cap progress ahead of intelligence itself. We’re all aware that those limits are solid as things currently stand: SK hynix and Micron have sold out HBM output for the year, high-power transformers carry three-to-five-year lead times, switchgear is booked into 2028, and grid-interconnection queues run three to seven years.

A Sightline Climate analysis estimated that 30% to 50% of large data centers due to open in 2026 will slip or cancel. U.S. data centers drew about 4.4% of national electricity in 2023, a share the Department of Energy's Lawrence Berkeley National Laboratory expects to reach 6.7% to 12% by 2028. Meanwhile, the four largest hyperscalers are on course to spend more than $650 billion on AI infrastructure this year.

Whether compute ultimately puts a lid on any out-of-control, self-improving loop is an unsettled debate. Forethought researcher Tom Davidson argues that there’s a chance that compute bottlenecks won’t “slow down a software intelligence explosion until its late stages,” while Epoch AI counters that if compute and cognitive labor are complements rather than substitutes, software-only acceleration stalls once it hits a compute wall.

‘No, you hang up first’

As for pausing AI development, Anthropic says it’ll only do this if rival labs at or near the frontier do the same in a verifiable way, and that a halt by one company wouldn’t change who’s leading the way.

This is a facetious suggestion at best that insults the intelligence of anyone who has been paying attention to the AI arms race. It’s beyond obvious that no lab this far down the road — let alone Anthropic — is ever going to ease off, especially when Anthropic’s own report essentially doubles as a piece of marketing for how fast it can make Claude build Claude. To suggest in one breath that AI might need to be paused or slowed down in one breath and then saying “but everyone else needs to go first” in another is quite the remark.

Anthropic’s report also came just days after the company confidentially filed for an IPO at a reported valuation near $965 billion, a glaring juxtaposition that read as a front-runner lobbying for limits it stands to help set. Anthropic made a self-assessment in April, when it said its Mythos Preview model had found thousands of severe vulnerabilities, a claim that later drew scrutiny over how much of it rested on a small manual sample.

A recent Mercer survey of nearly 12,000 C-suite executives, HR leaders, investors, and employees found that 99% of CEOs expect AI and automation to drive at least some headcount reduction in the next two years. At the same time, the report found that only 32% of executives believe their organizations are effective at combining human labor with AI systems.

These somewhat contradictory stats form the basis of an ongoing debate over AI and jobs. The data from Mercer shows that companies are indeed cutting or expect to cut significant portions of their workforce. In fact, we recently reported that 40,000 tech industry employees lost their jobs in Q1, 2026.

Now, companies are under pressure to show that these job cuts and billions of dollars in AI spending can translate into measurable returns. Workers, meanwhile, are already being affected as employers redesign teams, slow junior hiring, and tie AI to cost-cutting decisions before broader economic data shows a clear wave of AI-driven job replacement.

The evidence so far does not show an outright, simple story in which AI is massively replacing workers across the economy. Nor has it been proven that the actual AI replacements have proven useful. In another twist, it's possible that what OpenAI CEO Sam Altman calls “AI washing” — blaming AI for layoffs that may have happened anyway — is tainting the data.

Maximum pressure at the bottom of the ladder

While the layoffs create a valid, growing concern about unemployment, the most immediate impact appears to be on who companies are willing or unwilling to hire, and for what roles. Mercer’s report suggests that younger workers are especially exposed, with entry professionals aged 22 to 27 facing the highest perceived risk of disruption. This is because generative AI is strongest at the codifiable, repeatable tasks that often make up entry-level roles through which new workers are traditionally trained and integrated into the system.

A similar 2026 CEO survey by consulting firm Oliver Wyman points in the same direction. The firm found that the share of companies planning to reduce junior roles has jumped from 17% to 43% in a single year, while 33% are shifting their workforce mix toward midlevel roles. This stat presents another concern. Companies removing junior roles may reduce costs in the short term. However, the move may also weaken their own future talent pipeline. A labor market that demands experience while eliminating the jobs that create experience risks imploding.

For now, the full picture remains quite murky, with contradictions in the available data. Oliver Wyman notes that some of the most advanced AI adopters are not abandoning junior hiring entirely. In fact, companies reporting stronger AI returns are somewhat more likely than weaker performers to shift toward junior workers, suggesting that at least some businesses see AI-literate early-career staff as an asset rather than a cost.

This makes the entry-level story more complicated. AI may reduce demand for some traditional junior tasks, but it could also increase demand for workers who can use AI tools effectively inside redesigned workflows. The real risk is that companies treat the technology as a simple substitute for early-career workers before they understand which roles should be automated, augmented, or rebuilt.

The productivity evidence is still unclear

The case for AI-driven layoffs depends heavily on one assumption: that AI is making workers and teams productive enough to justify smaller headcounts, while also cutting costs. So far, the evidence is mixed. Mercer’s findings show that executives see AI as central to future performance, but also that many organizations are struggling to redesign work around it. Oliver Wyman found that 53% of CEOs still say it is too early to assess the return on investment from AI, up from 41% last year. It also found that 67% of companies are still primarily planning or piloting AI rather than scaling it across the business.

This gap between ambition and proof reveals that AI can be impressive at the task level without immediately transforming company-level productivity. A chatbot that drafts an email faster or helps a programmer debug code may save time for an individual worker. However, turning that into measurable revenue growth, lower operating costs, or a sustainably smaller workforce is a different challenge.

There are workflow redesigns, data cleaning and integration, and compliance risk management, among several other accompanying tasks. Employees need training on how and when to apply AI. They also need cybersecurity training as hackers are increasingly finding ways to exploit systems through AI chatbots. Managers need to know which outputs can be trusted and which require human review. There’s also the question of how much responsibility AI can safely handle. We recently covered a case where a Claude-powered AI coding agent deleted a company's entire database. In many companies, these changes are slower and more difficult than the early AI hype suggested.

European data further complicates the replacement narrative. A European Central Bank analysis of firms that use and invest in AI found no significant overall difference in job creation or destruction between businesses that use AI and those that do not. In some cases, companies with more intensive AI use or investment were slightly more likely to be hiring, especially where AI supported research, development, and innovation.

While none of this proves that AI will not still reduce employment later, it does suggest that the current relationship between AI and jobs is not as straightforward as many layoff announcements imply. In the near term, AI may be helping some companies grow, while leaving many still searching for measurable returns.

“AI washing” is tainting the data

As if the data isn’t painting an unclear enough picture, there’s a real possibility that companies are falsely using AI as an excuse to fire workers. Layoff announcements rarely provide enough detail to distinguish genuine AI displacement from broader corporate restructuring or even serious internal issues. Sam Altman, whose company helped trigger the generative AI boom, has warned that some firms are engaging in “AI washing” by blaming AI for job cuts they would have made anyway. He also acknowledged that real displacement is happening and is likely to become more visible over time. Both points can be true.

This is why the current wave of AI-linked layoffs should be read carefully. A company may cite automation while also dealing with overhiring from the pandemic period, weaker demand, outsourcing, margin pressure, a falling share price, activist investors, or a broader strategic reset. AI can be the cause, the tool, the justification, or merely the language used to present a decision to investors.

Now, this does not mean AI is irrelevant to job cuts. Major companies across banking, retail, technology, and professional services are already reorganizing work around automation. Standard Chartered has discussed thousands of job cuts tied to automation and lower-value roles. Other firms, such as Amazon and Meta, have cited AI as part of broader efficiency drives.

As an increasing number of companies now believe AI will allow smaller teams to do more, even uncertain productivity gains are influencing hiring plans. The powerful technology is arriving in companies already under pressure to cut costs, demonstrate growth, and satisfy investors. As a result, managers may delay backfilling roles, and graduate hiring may slow, with entry-level work being bundled into contractor roles or existing mid-level positions.

The danger for companies is that cutting too deeply into junior roles could create a skills shortage later. The danger for workers is more immediate, as the traditional route into white-collar careers may narrow before a clear replacement path emerges. For now, the most defensible reading is also the least dramatic, and may be somewhat on the fence: AI is neither harmless, an automatic jobs apocalypse, nor a magic potion for instant growth and productivity.

When not being spotted at night markets or meeting crowds of adoring fans, the hardware industry’s biggest celebrity, Nvidia CEO Jensen Huang, spent most of his time at Computex this week making the case that computing as we know it is collapsing into one repeatable pattern built for AI agents; a blueprint that now runs across the cloud, the PC, the car, and the robot.

"There's a new computing pattern," the Nvidia CEO told reporters at a press gaggle the day after his GTC Taipei keynote, describing an agent architecture he calls a harness that orchestrates reasoning, memory, and tool use the same way whether it sits in a data center or a laptop.

He tied that claim to every product Nvidia detailed at the show, from the Vera data-center CPU now in full production to RTX Spark, its first Windows PC platform, shipping in laptops this fall.

One pattern, every machine

Huang told the room that he repeats the same keynote structure on purpose. "Every time I give you a keynote, it's like Top Gun 17, and it's exactly the same architecture," he said, "because I want you to know that the future of computing is this." The pattern begins with training and inference in the cloud and pushes outward to everything else: "Every edge device will become autonomous. Every edge device will have agentic systems."

He ran that blueprint through self-driving cars, humanoid robots, Nokia base stations, and imaging satellites, casting each as the same agent profile on different hardware. Curiously, the self-driving car got quite a bit of airtime, with Huang describing Nvidia's Alpamayo driving stack as a system that reasons in language rather than reacting to images, one that could read a "skill file" and watch a tutorial video to operate unfamiliar machinery the way a person would. "That's how autonomous vehicles are going to work in the future," he said. "It's essentially that agentic computing pattern with a physical AI model."

A CPU that generates tokens, not cores

Vera, on the data center side, is an 88-core Arm processor that Nvidia is now in full production with, pitching it as a chip built for agents rather than human users. "We built Vera for agents to use," Huang said. "Until six months ago, there were no agents, so that's the definition of a $0 billion market."

A hyperscale CPU piles on cores because humans lease them by the hundred, where an agent, Huang argued, "doesn't want to rent the CPU core, the agent wants to generate tokens." That pushed Nvidia toward single-thread speed and memory bandwidth over core count, and Huang claimed Vera offers the largest step up in single-threaded performance he has seen "in 25 years." His reasoning ties back to latency: "Humans are more patient than agents. Agents, they're working at nanosecond scale, not second scale."

Nvidia claims 1.8 times faster task completion than x86 and a 1.5 times instructions-per-clock gain over its Grace predecessor, with a 256-chip liquid-cooled Vera rack it says reaches six times the throughput of a conventional CPU rack. The chip ships on the back of nearly 2.5 million Grace units sold, and Anthropic, OpenAI, xAI, ByteDance, CoreWeave, and Oracle are named as early customers. CFO Colette Kress told investors on Nvidia's latest earnings call that the company sees "nearly $20 billion in total CPU revenue this year".

Phoronix's first public Vera benchmarks in May measured it roughly 10% ahead of AMD's 64-core EPYC 9575F and about 55% ahead of Intel's 128-core Xeon 6980P across selected Linux workloads. Nvidia ran those tests on pre-production silicon at its own headquarters, limited them to workloads it considers relevant, and, by Phoronix's account, switched off CPU power and frequency monitoring for the session.

Reinventing the PC after 40 years

As for RTX Spark, Huang says that it’s the first real rethink of the PC in four decades. "We have an opportunity after 40 years to go reinvent it for the age of AI," he said, predicting the machine shifts "from your PC being a tool to now really your PC being your system." He pushed even further: "Your laptop is going to be your R2-D2."

The top RTX Spark part, internally N1X, pairs a 20-core Arm CPU built by MediaTek (10 Cortex-X925 performance cores and 10 Cortex-A725 efficiency cores) with a Blackwell GPU carrying 6,144 CUDA cores, up to 128GB of LPDDR5X unified memory, and a 600 GB/s NVLink-C2C link, all on TSMC's 3nm node. Huang justified these specs with the same impatience he applied to Vera, arguing that an agent driving the machine won’t wait, so the software it touches, from Adobe to Blender, "cannot be slow."

The platform is launching in a market that Qualcomm had effectively dominated until its Windows on Arm exclusivity with Microsoft lapsed. Fall 2026 laptops are confirmed from Microsoft, Dell, HP, ASUS, Lenovo, and MSI, with Acer and Gigabyte to follow, and Nvidia says anti-cheat engines, including Easy Anti-Cheat and Denuvo, run natively on the chip. Asked why Nvidia would enter a low-margin business it has steered clear of for years, Huang said, "We don't really have to choose. The real question is, can we make a contribution?"

Vera's 88 cores are Nvidia's own custom Olympus design, its first ground-up server core since the Denver and Carmel projects, while RTX Spark's 20 cores are Arm's off-the-shelf Cortex reference designs licensed through MediaTek, one of them already a generation old. Huang's "same pattern everywhere" runs, at the silicon level, on two different CPUs.

When asked whether the Olympus cores would come to Windows PCs, Huang declined to commit. "Our preference is to use off-the-shelf cores whenever we can, because Arm also builds good cores," he said, adding that Olympus was pushed toward single-thread speed in a way standard many-core Arm parts weren’t: "We wanted to push single-threaded performance as far as we could push it." The first PC chip using Nvidia's own cores isn’t expected until 2028. Meanwhile, Morgan Stanley estimates Vera at around $5,000 per socket inside a vertically integrated rack.

What about memory?

DRAM contract prices have climbed sharply through 2026 as makers divert wafers to high-bandwidth memory, and Nvidia remains short of supply even as it locks in capacity, by Huang's own account: "We have enough supply for very robust growth. However, we are supply constrained."

"One of the best ways to improve memory use is to use extremely, extremely low precision," Huang said, pointing to NVFP4, Nvidia's 4-bit floating-point format that scales between four, eight, 16, and 32 bits and roughly doubles the parameters that fit in a given memory pool, the trick that lets RTX Spark hold larger models in its 128GB. He paired it with neural texture compression that cuts game texture memory by up to eight times in Nvidia's demos. At SK hynix's booth during the show, Huang signed an HBM4E wafer with the words "Please Make More."

Several AMD partners are showing off the company’s next-generation Helios rack-scale solution running AMD’s EPYC ‘Venice’ processors and Instinct MI455X AI accelerators at Computex 2026 in Taipei, Taiwan. The units are set to become available later this year. There is one major catch, though: they all use UALink-over-Ethernet scale-up connectivity, which may limit their performance in certain workloads that depend on the connection performance. That said, Helios systems with ‘true’ UALink interconnects will also be available.

AMD’s Helios is the company's first rack-scale AI system, and is set to rival Nvidia’s NVL72 VR200 machines based on the next-generation Vera Rubin platform. Helios will rely on AMD’s 6th Generation EPYC Venice CPUs with up to 256 cores, pack 72 Instinct MI455X accelerators with a total of 31 TB of HBM4 memory, and 1400 TB/s of bandwidth. AMD estimates that its performance will be around 2900 FP4 dense PFLOPS, which puts the unit behind Nvidia's VR200 NVL72 system in terms of compute performance, but ahead of it with HBM4 memory capacity. This promises to provide Helios-based systems an advantage in memory-intensive workloads, such as when running large LLMs.

The AI accelerators are interconnected and make use of a UALink-over-Ethernet connection, which provides up to 260 TB/s aggregated scale-up bandwidth (in line with Nvidia’s NVL72 VR200). Helios will also feature Pensando Vulcano network interface cards (NICs), which are among the industry's first 800 GbE network cards that comply with the Ultra Ethernet specification and provide up to 43 TB/s of scale-out bandwidth.

However, the interconnection used on these Helios systems will vary. The machine supports both UALink and UALink-over-Ethernet, but the initial versions will use the latter, rather than the former. This is likely because UALink switches aren't finalized and are pending validation and qualification by AMD’s AI customers.

The biggest advantage of using UALink over Ethernet is that AMD can build Helios using an existing, widely supported ecosystem of validated and qualified components. Ethernet switching ASICs, cables, and other ingredients are already used by hyperscalers and cloud providers worldwide, which accelerates deployment.

But there is a major downside with using Ethernet, even with the UALink protocol on top: Ethernet was originally designed as a general-purpose networking technology; it was never designed to scale up AI accelerators.

As a result, communications may involve higher latency, more protocol overhead, and less deterministic performance than a dedicated scale-up fabric. For large AI training jobs that need all 72 Instinct MI455X accelerators to work in concert, communication efficiency is as important as compute performance. If the UALink-over-Ethernet interconnect cannot keep GPUs fed with data efficiently, some of the theoretical performance of the hardware may be lost in real-world deployments, even though on paper, Helios with UALink-over-Ethernet is as good as Nvidia’s NVL72 VR200 in scale-up bandwidth.

This begs the question of whether UALink will ever be widely used with Helios and whether UALink will ever be widely deployed using copper. Hyperscalers and other companies deploying high-end AI hardware at scale rarely upgrade their hardware.

While the Instinct MI455X certainly promises to be among the best hardware accelerators this year, Helios will likely only be rivalled by Nvidia’s NVL72 VR200. It will be outdated next year when AMD launches its Instinct MI500-series products. These units will be used in the company’s next-generation rack-scale offering, which promises to pack more AI GPUs, potentially requiring optical interconnects with UALink on top. As a result, Helios systems with true UALink interconnections over copper will be on the market for less than a year before those next-generation rack-scale solutions will hit the market.

Of course, nothing is stopping AMD from offering Helios with Instinct MI500-series accelerators and UALink interconnects over copper; however, the company hasn't confirmed the existence of such systems.

Frore Systems is showing off its LiquidJet Nexus at Computex 2026 in Taipei, Taiwan. The LiquidJet Nexus is a monolithic water block with innovative coldplates, designed to cool two Blackwell GPUs and a Grace CPU, that can replace the complex water block used today. Based on tests conducted by an ODM, the LiquidJet Nexus outperforms the default cooling solution used today and reduces GPU temperatures by around 6ºC, which increases token generation by 10%. Frore intends to build LiquidJet Nexus for Nvidia’s Rubin platforms and is ready to produce them for other accelerators, too.

Earlier this year, Frore introduced its LiquidJet, a coldplate for AI accelerators, tailor-made for exact models of processors using tools originally meant to make semiconductors, in a bid to maximize cooling performance. The LiquidJet Nexus water block builds upon these principles, integrating them into a monolithic unit designed to cool down both GPUs and a CPU inside a server tray. For now, Frore is demonstrating LiquidJet Nexus for Nvidia’s Grace Blackwell superchip, though a version compatible with Vera Rubin is also incoming, we're told.

Frore’s LiquidJet coldplates are made using tools designed to produce semiconductors — using etching and bonding steps — and are architected in accordance with actual thermal maps of CPUs and GPUs they are meant to cool. As a result, they remove heat precisely from hotspots of these processors, and therefore enable better cooling performance than coldplates made using traditional milling methods. Based on tests conducted by a major ODM, Frore’s LiquidJet Nexus reduces the temperature of Blackwell GPUs by 6ºC compared to default cooling solutions, which in turn increases their token generation by 10%.

While a 6ºC temperature drop and a 10% performance improvement may sound humble, these performance improvements impact billion-dollar deployments, where such improvements could mean hundreds of millions in savings. Also, since Frore’s Liquid Jet Nexus is monolithic, it is less prone to leakage. This means less downtime and fewer damaged servers, which means more profits and fewer losses for their owners. Again, since we are talking about billion-dollar deployments, there are significant amounts of money at stake when it comes to cooling and efficiency.

Frore says it is working with the majority of hyperscalers to build LiquidJet-based cooling solutions for their custom hardware. Since LiquidJet is designed to remove 400W – 600W of thermal energy per square centimeter, it can cool down very hot components. Furthermore, since these components tend to scale horizontally, it is not a problem to scale LiquidJet’s performance by increasing its dimensions.

In addition to being more performant and potentially significantly more reliable than existing liquid-cooling solutions for Nvidia Blackwell, Frore’s LiquidJet Nexus also weighs 65% less than rivals and is twice as thin (17 mm vs 34 mm), according to Frore.

While this may not be a significant advantage today (unless you ship your servers by plane), this will be a dramatic advantage for Nvidia’s next-generation Kyber chassis that places servers on their edge rather than horizontally, which will make the importance of LiquidJet Nexus’s weight a bigger factor, as the cooler must adhere to the cooling surface of the integrated heat spreader thoroughly. Meanwhile, it is hard to adhere a massive cooler to a vertically standing motherboard, so one with a lower weight should be easier to attach to the motherboard and chassis without worrying about longer-term deformations.

Speaking of Nvidia’s Kyber chassis, it is worth noting that they are designed for the Vera Rubin Ultra platform, which ups the TDP of GPUs all the way to around 3kW per unit, making its cooling a challenge. Meanwhile, Rubin Ultra GPU scales horizontally by employing a quad-chiplet design, so Frore can address its TDP by reinventing its coldplate, which is easy assuming the company is provided a thermal map of the unit. The same method can be applied to other processors, which is why Frore is indeed working with hyperscalers with custom silicon, in addition to other merchant silicon providers, aside from Nvidia.

This week at Computex 2026, we saw Nvidia reveal its RTX Spark, and last month, AMD detailed its Ryzen AI Max 400 "Gorgon Halo" lineup, a refresh of the Strix Halo APUs that lifts supported unified memory to 192GB and allows up to 160GB of that pool to be addressed as VRAM. AMD describes the flagship Ryzen AI Max+ PRO 495 as the first x86 client processor able to run a 300-billion-parameter language model locally, pitching the platform for use cases that need to keep multiple AI agents resident in memory at once.

The market for Gorgon Halo will likely be directly shared with other chips, such as Nvidia's RTX Spark, which debuted at Computex 2026. RTX Spark is also positioned as an on-device agentic computing device. With local AI computing demanding lots of on-device RAM, it poses a difficult issue for device vendors.

DRAM contract prices are forecast to climb another 58% to 63% this quarter, on top of the record 90% to 95% jump TrendForce recorded in Q1, which also saw Nvidia raise the price of its DGX Spark desktop from $3,999 to $4,699, citing memory supply. So, what happens to the dream of accessible local AI compute?

DRAM supply squeeze

The local AI PC has become a category defined by how much memory it carries, and it’s scaling that memory up at a time when memory has never cost more. AMD's three Gorgon Halo SKUs reuse the same Zen 5 cores, RDNA 3.5 graphics, and XDNA 2 NPU as the existing Ryzen AI Max 300 parts, with the Max+ PRO 495 gaining a 100 MHz boost-clock bump to 5.2 GHz, a 40-compute-unit Radeon 8065S, and a 55 TOPS NPU.

Memory capacity has been increased 50% from the 128GB ceiling on Strix Halo, with a leaked PassMark entry putting the 192GB figure as eight 24GB SK hynix LPDDR5X packages on an HP test board, though AMD hasn’t yet confirmed this. Partner systems from Asus, HP, and Lenovo are due in the third quarter of 2026.

It’s all well and good that Nvidia and AMD are releasing machines like the RTX Spark and the Gorgon Halo line-up. However, Samsung, SK hynix, and Micron have all shifted the bulk of their wafer capacity toward high-bandwidth memory for AI accelerators because HBM carries far higher margins than commodity DRAM, and the conventional memory supply has tightened as a direct result of this. HP told investors in February that memory now accounts for roughly 35% of the cost of building a PC, up from 15% to 18% a quarter earlier.

SK Group chairman Chey Tae-won, speaking at Computex 2026 on the show’s official opening day, repeated his position that the shortage will run through 2030, despite the company's intention to double wafer capacity within the next five years. New fabs from all three makers are under construction, but none will reach volume production before late 2027 at the earliest, and most forecasts now predict a structurally higher price floor that persists even after the acute shortage eases.

The 192GB in a Gorgon Halo box, the 128GB in an RTX Spark or DGX Spark, and the LPDDR5X soldered into every AI laptop announced at Computex all come off wafers the memory makers would otherwise sell as HBM. That’s why Nvidia raised the DGX Spark by $700 in February without changing a single spec, and why component makers have begun passing memory costs through directly. One vendor has even taken an extremely on-the-nose approach of adding a flat memory surcharge to every purchase, and in some cases, smaller buyers are now quoted prices that change by the hour.

Bandwidth caps inference speed

A single pool of 192GB would enable an APU to hold a model that would otherwise require a multi-GPU server. While it doesn’t make the model run quickly, dense language model inference reads close to the full set of active weights from memory for every token generated, so generation speed is governed by memory bandwidth divided by the per-token weight footprint, not by idle memory.

Gorgon Halo keeps the same 256-bit LPDDR5X-8000 interface as Strix Halo, which tops out around 256 GB/s in theory and which independent testers have measured closer to 212 GB/s on the GPU. By comparison, the Apple M3 Ultra that AMD and Nvidia are chasing on capacity is rated at 819 GB/s, and an RTX 5090 moves data at 1,792 GB/s.

This gap explains why a dense 70-billion-parameter model fully resident on a Strix Halo iGPU lands in the low single digits of tokens per second, regardless of how much headroom the memory pool has. Our own Corsair AI Workstation 300 review found that Nvidia's slightly higher-bandwidth GB10 pulled ahead of Strix Halo as context length grew, for exactly this reason.

Capacity matters most for mixture-of-experts models, which activate only a fraction of their parameters per token and run far faster than their total size suggests, and for long-context agentic workloads, where it’s KVcache rather than model weights that consume memory. It’s these use cases that AMD’s agentic pitch points at, with leaked details on the next-gen Medusa Halo parts showing a move to LPDDR6 and as much as 80% more bandwidth.

Holding the line on price

Agentic AI is also something of a pricing tool for vendors, beyond describing a workload. A 192GB workstation sold on the promise of running 300-billion-parameter models locally can hold a four-figure price more comfortably than a mini PC sold on cores and clocks, and it justifies loading the most expensive component in the build to its maximum. AMD's Ryzen AI Halo developer box, a 128GB Strix Halo system, opens pre-orders in June at $3,999 through Micro Center, matching the launch price of Acer's GB10-based Veriton GN100 and the original DGX Spark before its increase.

Apple, the one vendor with the scale to hold priority memory allocation, has moved the other way. It pulled the 512GB Mac Studio configuration from sale, raised the price of its 256GB upgrade, and in May removed several more high-memory Mac mini and Mac Studio options as supply tightened.

This shows us beyond doubt that expanding capacity while holding the line on premium pricing is a choice the AMD and Nvidia camps are making, not one that the market is forcing. Whether buyers accept it rests on whether local agentic inference delivers enough value over cloud services to justify the outlay, on machines shipping with memory capacities that outpace the bandwidth that ultimately determines what that memory can do.