ASML launched a Lego kit version of the TWINSCAN EXE:5000, the world’s first High-NA EUV machine, in December 2024. Since ASML only sells products like these to employees, the company canceled orders from non-employees, making the kit even more desirable for collectors. Current eBay listings show a Buy It Now price between $500 and $700, which is significantly higher than the $230 that the company asks for on the official website. However, X user @lithos_graphein shared a recreation of the kit available on Rebrickable, which added some tasteful modifications.

“A friend of mine fell in love with the ASML employee-exclusive Lego TWINSCAN EXE:5000 set and asked me to recreate it. While the original Lego version already looked impressive, I made some modifications to better capture the details of the real machine,” NightHawk11991 said in the description of the MOC (My Own Creation). “Using photos my friend took of the actual equipment, I designed this custom MOC to enhance its accuracy. I also added some interior details, including vacuum pumps, a laser emitter, reflectors, and more. Additionally, the silicon wafer tray can slide out for added functionality!”

The ASML TWINSCAN EXE:5000 MOC requires 152 unique parts and a total of 810 bricks. While this may not be the biggest build you can get from Lego or find on the Rebrickable MOC website, it’s still a rather significant build, with @lithos_graphein saying that it took them about a week to complete it. You can build and complete this project yourself, with PDF instructions available for free on the Rebrickable website. If you’re missing a Lego part to finish the build, you can also purchase it separately, although you might have a bit of a hard time looking for rarer parts included in the project.

@lithos_graphein is also the same one who was able to get their hands on a rare ASML Special Edition Monopoly board, which was released in 2007, after they traded an official ASML Lego kit for the board game. Company-commissioned merch like this is often given or offered to employees, meaning the average shopper wouldn’t be able to purchase it brand new unless they have a relative working in that company who buys it for them. Other semiconductor companies that have sold merch like this include TSMC and SK hynix, with resellers who were able to get their hands on company swag and sell it online for as much as $16,700.

Being unable to procure EUV litho tools from ASML, China must develop such systems locally, so from time to time we learn about an EUV-related 'breakthrough' in China that will turn into an actual EUV scanner over the following several years. This week, Chinese startup Langdao Silex demonstrated a prototype extreme ultraviolet (EUV) light source with over 15W of output power, 90% domestic components, and decent uptime. The company will need another three to five years to commercialize its technology, reports TrendForce, citing various sources. Yet, a light source alone does not make an EUV scanner.

An LPP EUV source from China

Langdao Silex, which was established in 2024 by Tsinghua University's Gas Discharge Plasma Laboratory alumni, demonstrated its EUV light source prototype at the 26^th China International Industry Fair in Shanghai, for obvious reasons, without lighting it up. Just like modern light sources from ASML, the company's low-power FlintNano LPP-OXXO system uses laser-produced plasma (LPP) technology that produces EUV radiation by bombarding tiny heated metal droplets with high-energy laser pulses to create extremely hot plasma. The system features a 1,000W driving laser (presumably a CO₂ one) with an operating frequency of 1 kHz – 20 kHz and conversion efficiency exceeding 2%. Its EUV output exceeds 15W (presumably measured at the plasma rather than at intermediate focus, as the company has not demonstrated a complete EUV collection system) while its brightness reaches 100 W/(mm²·sr). The source has an étendue of 1 × 10⁻³ mm²·sr and generates plasma with a diameter of 60 μm.

According to Langdao's specifications, the FlintNano LPP-OXXO can operate continuously for over 100 hours with plasma stability of 3% RMS and EUV output power stability of 5%. These characteristics make the system suitable for semiconductor exposure experiments, although its output remains insufficient for high-volume chip production. Meanwhile, the 'over 100 hours' availability is very impressive for a pre-production light source, though we must admit that there is no way to verify the claim.

Langdao is also developing the FlintMicro-LPP high-power EUV source, which has completed proof-of-principle validation, according to reports. However, Langdao has not disclosed its output power, conversion efficiency, or operating lifetime.

On paper, Langdao's EUV source is comparable in output to some of the earliest EUV sources developed by Western and Japanese equipment makers, albeit with a major caveat: Langdao seems to measure EUV power at the plasma rather than after the collector or at intermediate focus as ASML does. ASML's early EUV demonstration equipment used approximately 10W at intermediate focus DPP sources in 2007, while Cymer's LPP sources installed in early NXE:3100 systems delivered up to 11W during wafer exposure in 2012 (note that ASML's machines are source agnostic, so some NXE:3100 prototypes used DPP sources, while others used LPP sources). By 2013, Cymer demonstrated approximately 40W at intermediate focus over extended operating periods. Meanwhile, Japan's Gigaphoton targeted 25W with its first prototype in 2013 and demonstrated 43W in early 2014. By late 2014, Gigaphoton had achieved 118W during a 10-minute test. However, since these historical figures involve different measurement conditions and operating durations, direct comparisons are vastly inaccurate.

Not quite there

Langdao Silex has not demonstrated its EUV light source in action, so all we know about it comes from the company itself. As noted, 15W power looks comparable to early EUV sources developed by Philips Extreme UV (DPP) and Cymer (LPP). Meanwhile, early NXE:3400-series machines came with 125W – 150W at intermediate focus sources, which was far from enough for high-volume manufacturing (HVM).

Modern EUV lithography equipment comes with considerably more powerful sources. ASML introduced 250W-class EUV sources for commercial production in 2018 – 2019 and has since achieved substantially higher output levels. Increasing output requires more powerful CO₂ lasers, highly accurate tin-droplet generators, effective debris mitigation, durable collector mirrors, and considerably better long-term reliability.

Langdao claims that 90% of its prototype's components are domestically sourced and that most critical parts were developed in China. However, the company has not explained whether the localization figure reflects component count, value, or another metric. Furthermore, its representatives reportedly acknowledged that increasing EUV output and improving long-term operational stability are the targets to be achieved in a bid to commercialize the source.

Not an EUV scanner

Yet, even without complete EUV scanners, Langdao's source could support EUV photoresist development, mask inspection research, development of EUV collection and illumination optics, and eventually experimental exposure testing.

Developing a complete EUV lithography scanner will require further advances in EUV collection and illumination systems, high-precision multilayer mirrors, wafer and reticle stages, overlay accuracy, and system integration. Meanwhile, all of these devices require a separate supply chain that hardly exists in China today.

Therefore, even if Langdao successfully develops its EUV source and increases its output to levels suitable for high-volume manufacturing, this would not necessarily mean that China could manufacture its own EUV lithography machines any time soon. Moreover, while Langdao's progress is impressive, it took ASML/Cymer approximately six years to increase the output of its LPP EUV source from 11W to 125W – 150W at intermediate focus, so there is no way that Langdao's LPP source could be used for anything beyond development tools in the next three to five years.

Meanwhile, Langdao has not disclosed where its reported 15W of EUV output is measured. If this figure represents radiation generated at the plasma rather than power delivered at intermediate focus, the source's usable output would be considerably lower than 15W when measured according to industry-standard practices. That said, it does not look like China got significantly closer to building its own EUV lithography scanners with the current announcement.

The EU is currently in talks with China to lift restrictions the country imposed on Sindlhauser Materials GmbH, a German company in ASML’s supply chain, as the sanctions risk putting the company out of business. In return, the EU would remove restrictions it placed on one unnamed Chinese firm accused of aiding Russia in the war with Ukraine, according to an Oct. 14 Bloomberg report citing people familiar with the matter.

The deal was discussed during EU Commissioner for Trade and Economic Security Maroš Šefčovič’s visit to Beijing. The EU is expected to make the first move, with any delisting on its end requiring unanimous support from member states. Both sides also agreed to share more information and give advance warning on future export restrictions.

In July 2026, China put Sindlhauser, a German precision-manufacturing and advanced-coatings firm, on its export-control list, along with 13 other European companies, in apparent retaliation for the EU’s 21st Russia sanctions package, which sanctioned several Chinese firms accused of supplying Moscow with components that can be used to make weapons. Beijing’s official reason was the firms’ alleged dealings with Taiwan.

China’s selection of Sindlhauser is not random, as the company sits in ASML’s supply chain. According to Bloomberg, officials believe Beijing has spent the last year and a half gathering information on Western supply chains, and used the data to identify the seemingly obscure German firm as a pressure point on the world’s most important chipmaking-equipment company.

Sindlhauser relies almost entirely on Chinese rare earths and critical minerals. Therefore, the restrictions, which ban Chinese exporters from selling dual-use items to the firm, cut off its main source of input. They also prohibit foreign companies and individuals from passing on China-origin dual-use items to the firm, thus preventing Sindlhauser from simply sourcing the same materials through a third-party distributor.

After the listing, which initially sparked panic over the company’s survival, the German government and Bavaria’s state government stepped in, helping the company explore workarounds such as alternative suppliers and recycling existing materials. However, due to its heavy dependence on China, Sindlhauser now faces the risk of going out of business in the coming months if the sanctions remain.

EU officials in Brussels had been raising the case with Beijing for weeks, culminating in the delisting swap discussed during Šefčovič’s visit. The incident highlights China’s influence on several aspects of the global technology supply chain, including semiconductor manufacturing, which is critical to the AI boom. The country placed export restrictions on several rare earth metals, limiting their availability across the supply chain. Meanwhile, the West has been investing heavily in domestic supply chains to reduce reliance on China.

ASML this week reported record quarterly revenue of $13.06 billion (€11.66 billion) and profitability of nearly $5.79 billion (€5 billion) as demand for advanced semiconductor manufacturing equipment continues to accelerate and investments in AI infrastructure continue to increase. The company now expects demand for its lithography systems to exceed its production capacity in 2027 and 2028, despite plans to increase output substantially. Some clients are already interested in placing orders for equipment as far ahead as 2030, which makes ASML consider further capacity expansions beyond its previously announced intentions.

Record financial results

ASML reported third-quarter 2026 revenue of $13.06 billion USD (€11.66 billion), up 55% year-over-year and 25% sequentially. The company's gross margin reached a record 57.5%, up from 51.6% a year earlier, while operating income rose to $5.79 billion (€5.17 billion). Net income reached $5.56 billion USD (€4.96 billion) , although this figure includes approximately $570 million (€510 million) from the re-evaluation of the company's investment in Mistral AI.

During the quarter, ASML sold 121 lithography systems, including 113 new and eight refurbished machines, up from 91 systems in Q2 2026. The company generated $4.59 billion USD (€4.1 billion) from 17 EUV lithography systems and $4.82 billion USD (€4.3 billion) from 85 DUV (including 45 ArFi scanners) and 19 i-line litho tools. In addition, ASML recognized revenue from one High-NA EUV system in Q2. Of total equipment revenue, 54% came from logic chipmakers and 46% from memory manufacturers.

Taiwan accounted for 32% of ASML's equipment sales in Q3 2026, followed closely by South Korea at 31%. China represented another 23%, while the United States accounted for 13% and the rest of Asia contributed just 1%. Combined, Taiwan and South Korea generated 63% of ASML's equipment revenue, which reflects substantial investments in advanced logic and memory manufacturing capacity that by far exceed those in the U.S. and Japan.

ASML’s Installed Base Management business generated $3.68 billion (€3.29 billion), approximately $450 million (€400 million) above guidance, largely due to strong demand for productivity upgrades (more on this later), which contributed to the company’s record profitability.

For the fourth quarter, ASML expects revenue of $15.9 billion to $17.0 billion (€14.2 billion to €15.2 billion) and gross margin of approximately 57%. Full-year revenue should reach $49.3 billion to $50.4 billion (€44 billion to €45 billion), up approximately 36% YoY. The company projects EUV revenue should increase by more than 45% year-over-year, while memory-related equipment sales are expected to rise by approximately 75%, which indicates growing demand from DRAM producers.

Demand for litho tools spans to 2030

One of the biggest learnings from these results and accompanying statements is that semiconductor manufacturers are increasingly interested in securing lithography equipment years before they actually need it. According to ASML CEO Christophe Fouquet, customers expect demand for its products to exceed available supply through at least 2028, which encourages them to accelerate construction of new fabs as well as expand their existing capacity.

"Our leading-edge high-volume customers are sharing very good visibility as a result of the increasing number of long-term commitments they are securing with their customers," Fouquet said during the company's conference call with analysts and investors. "This extended visibility has led them to conclude that demand for their products will outpace supply through at least 2028. As a result, customers are accelerating capacity build-out plans and preparing for further expansion beyond 2028 in order to better meet the anticipated level of demand."

ASML is already receiving orders that are to be delivered in 2028, while some customers have expressed interest in equipment for 2029 and even 2030.

"As customers shift focus to their needs beyond 2027, our order momentum continues to build," Fouquet added. "We are increasingly receiving orders for 2028, and customers are also expressing interest in placing orders for 2029 and even 2030."

To address this demand, ASML plans to manufacture approximately 65 Low-NA EUV systems in 2026, up from 44 scanners shipped in 2025. Production of immersion DUV systems should remain approximately at last year's level, even though proveiously the company expected shipments of DUV tools to decline.

The company previously announced plans to increase production capacity for both Low-NA EUV and immersion DUV systems by 30% in 2027, followed by another potential 30% increase in 2028. Based on its 2026 EUV production target, this implies capacity for approximately 85 Low-NA EUV systems in 2027 and roughly 110 in 2028, assuming both increases materialize.

However, ASML now believes even this level of output will be insufficient and is investigating ways to expand its 2028 capacity beyond the previously planned 30% increase. However, the company has not disclosed revised production targets.

"Looking further ahead, we shared our intent last quarter to increase our capacity in 2027 by 30% for both Low NA EUV and DUV immersion systems, as well as to investigate adding a further 30% in 2028," explained Roger Dassen, Chief Financial Officer at ASML. "However, given the dynamics of this quarter, we now anticipate that our current planned levels of output in 2027 and 2028 will not fully meet the demand of our customers."

High-NA EUV adoption

Meanwhile, High-NA EUV adoption is progressing. Intel has already exposed more than one million wafers using High-NA systems and plans to start using High-NA EUV with its 14A process technology in 2028. Samsung plans to introduce High-NA EUV into high-volume manufacturing (HVM) in 2028 for DRAM and for logic later, while TSMC plans to use High-NA EUV scanners by 2030 – 2031. ASML says availability across its installed High-NA fleet is approaching 90%, which suggests that the tools are becoming mature enough for HVM deployment.

Interestingly, Samsung's planned 2028 introduction may create additional demand for High-NA equipment from memory manufacturers, as they will need to compete against their larger rival. However, ASML has not disclosed specific shipment targets for these tools.

New tools, more capacity

ASML also intends to increase semiconductor production capacity by introducing more productive lithography systems. Its upcoming Twinscan NXE:3800F, scheduled for introduction in early 2027, will process up to 260 wafers per hour, compared with 230 wafers per hour for the existing NXE:3800E. While this represents 'only' approximately 13% higher throughput, this translates to 21,600 extra EUV exposures per month without corresponding increases in cleanroom space. Three such tools per fab enable 90 additional EUV exposures per hour, 2,160 per day, or 64,800 per month. The company also plans to introduce a new critical-layer immersion DUV system capable of processing 330 wafers per hour.

Keep in mind that the actual fab capacity improvements depend on the number of lithography exposures required per wafer on a particular node, as well as the capabilities of other manufacturing equipment.

Another important element of ASML's strategy is its growing portfolio of productivity upgrade packages for existing EUV and DUV systems. Such upgrades enable chipmakers to increase wafer throughput without purchasing additional scanners, which can provide additional capacity considerably faster than procuring new tools or constructing new fabs.

Value-based pricing is a go

One of the controversial things that ASML discussed back in early Q2 was its value-based pricing, which many thought was a blanket price hike. This is not and CFO Roger Dassen this week confirmed that negotiations with major customers have been completed, although the financial benefits for ASML will not become visible immediately.

The company expects the first effects of higher pricing to appear during 2027, with the full impact becoming apparent in 2028 and beyond, which essentially means that the company is not setting new prices on its backlog, but generally setting new prices on new tools.

"We completed those conversations," said Dassen. "So that has been done with the key customers. The effect of that is not really visible in 2026. It will start to become visible partly in the course of 2027. The full impact of that you will start to see in 2028 and beyond."

This strategy could further improve ASML's already substantial gross margins, particularly as customers have no alternatives for advanced lithography equipment.

China remains important

Despite export restrictions that prevent Chinese chipmakers from acquiring EUV scanners and advanced DUV systems, China remains a substantial market for ASML. The company expects China to account for approximately 20% of its total revenue in 2026, which implies annual sales of roughly €8.8 billion to €9 billion based on current guidance.

Although China's share of ASML's business has declined from its levels in 2023 - 2025, the country's semiconductor manufacturers continue to invest in mature node capacity and equipment that remains available under existing export regulations. Meanwhile, it is impossible to predict what is going to happen if the U.S. lawmakers approve the MATCH Act.

Yet, ASML management emphasizes that its key growth opportunities lie with advanced logic and memory manufacturers, which are accelerating their investment in advanced lithography tools, including sophisticated DUV systems, Low-NA EUV machines, and High-NA EUV scanners.

The future of ASML

Thanks to gaining momentum in AI infrastructure investments, ASML reported record quarterly revenue of $13.06 billion (€11.7 billion) as demand for advanced lithography equipment continued to accelerate. The company expects demand to persist for years as its customers are interested in placing orders for tools to be delivered as far ahead as 2030. To meet growing demand, the company plans to expand production capacity beyond its previous targets for 2028. ASML also intends to introduce new EUV and DUV systems with higher productivity, offer productivity upgrades, and raise equipment prices to capitalize on unprecedented demand.

ASML has said that the unprecedented spending and investment brought about by the artificial intelligence (AI) boom is not slowing down at all, as customers are already lining up to place orders for its advanced chipmaking tools for 2029 and 2030, according to a Reuters report citing ASML's Q3 2026 earnings published today, October 14. ASML CEO Christophe Fouquet said that the company would struggle to meet the demand despite plans announced in July to raise capacity by 30% in 2027 and another 30% in 2028. The company also confirmed on Wednesday that it will raise prices starting in 2027, with the full effect showing in 2028.

The Dutch company's comments follow its Q3 2026 earnings report, which detailed a net profit of €4.96 billion on net sales of €11.7 billion. It projects Q4 sales of €14.2 billion to €15.2 billion ($15.9 billion to $17 billion), boosting its full-year sales projections from at least €43 billion to €44-45 billion. ASML's shares rose 2% on Wednesday, up almost 70% so far this year, with its €586 billion market valuation making it Europe's largest firm by market cap.

According to Reuters, there had been concerns that the AI investment boom was losing steam. However, positive projections from the largest manufacturer of the tools for making AI chips and advanced semiconductors signal that chipmakers will keep expanding, sustaining demand across the AI industry well into the foreseeable future. "There were concerns that the AI trade was running out of steam," Gordon Kerr, European macro strategist at KBRA, said. "Demand for chips remains strong, and infrastructure spending is likely to continue well into 2027."

ASML's customers include logic chip manufacturers such as Samsung, Intel, and TSMC, which manufactures chips for Nvidia, all of whom are heavily investing in increasing chip production. Memory chip makers SK Hynix and Micron ⁠have also announced expansion plans that involve ASML machines. Meanwhile, the company's CFO Roger Dassen said it is "still kicking the tires on the exact size of that (Terafab) opportunity," referring to Elon Musk's 100 million square feet semiconductor manufacturing facility that aims to output millions of logic and memory chips. Terafab will reportedly receive its first EUV chipmaking tool from ASML in mid-2027.

ASML's order book reflects a wave of spending across the AI industry. As of April this year, Google, Amazon, Microsoft, and Meta reportedly collectively planned to spend $725 billion on capex in 2026, up 77% from last year's record $410 billion. Since then, Alphabet has raised its 2026 capex guidance from $180–190 billion to $195–205 billion, Amazon from $200 billion to $220 billion, and Meta has raised the floor of its range from $125 billion to $130 billion, keeping its $145 billion ceiling. Some of the spending reflects rising chip prices, with Microsoft CFO Amy Hood attributing $25 billion of the company's record capex budget to higher prices for memory chips and other components. Still, analysts such as Gartner expect global AI spending to rise 49.5% in 2026 to $2.7 trillion and another 36.2% in 2027.

Elon Musk's Terafab will get its first EUV lithography tool in the middle of next year, reports Tim Culpan, citing sources with knowledge of the matter. But considering that the shell of the firm's development fab will not be completed until late 2027 and that tools will only begin to be moved in later that year, according to SemiAnalysis, the scanner will sit idle for some time.

Tesla broke ground on its research fab on the north campus of Giga Texas near Austin this past April. SemiAnalysis expects the building to be completed in 15 months and predicts it will take Tesla a further six months to install equipment and production tools, after which it will be able to start processing wafers, or rather experimenting with chip production to get the team prepared for completion of the Terafab volume fab phase 1.

Given how hard it is to get an ASML Twinscan NXE EUV lithography tool these days, storing it for several months before putting it to use may sound like an expensive slack period, but it's not the significant financial problem for Terafab that it would be for a traditional chipmaker.

The projected delivery of a conventional EUV lithography system to Terafab also indicates that while Elon Musk has praised free electron laser (FEL) light sources for lithography tools, the first-generation efforts of his semiconductor production company will rely on more traditional equipment. This is not particularly surprising, as Terafab is set to use Intel's 14A manufacturing technology. 14A will use not only existing Low-NA EUV scanners, but also next-generation High-NA EUV machines.

Using lithography systems with unconventional and largely untested light sources would require substantial modifications to the manufacturing process, extensive equipment qualification, and potentially changes to photomasks and photoresists, which would complicate the transfer of Intel’s 14A technology and delay Terafab's production ramp.

But usage of standard lithography equipment does not mean that Musk's company has no plans to use tools that are different from those used by Intel, though for now it is too early to make guesses about what Terafab engineers might change in terms of fab configuration.

SpaceX announced that it had selected Grimes County for Terafab in early August 2026. By now, there is evidence that work has progressed beyond clearing land, as drone footage published by Joe Tegtmeyer in mid-September showed foundation excavation and rebar cage installation at the northwestern part of the site. This suggests that contractors had begun structural construction by early September, although the precise purpose of the foundation is unknown.

Right now, SemiAnalysis reports that project Terafab Grimes phase 1 will be built in 20 months, equipped in 17 months, and ramped to volume in six months. Analysts project that the fab will begin operation in late 2029 and then ramped to volume by mid-2030.

An interesting note about Terafab's volume fab is that SpaceX reportedly ordered semiconductor manufacturing equipment in April 2026, several months before officially announcing the Grimes County location. This indicates that the company committed to its manufacturing plans well before the public groundbreaking. In addition, this makes the mid-2028 equipment installation forecast plausible, given the long lead times associated with advanced semiconductor manufacturing equipment.

Intel plans to begin risk production using its 14A (1.4nm-class) fabrication process in the second half of 2027 and initiate high-volume manufacturing (HVM) in the second half of 2028 if everything goes as planned. This puts Intel's ramp into HVM at least 1.5 years ahead of SpaceX’s Terafab Grimes Phase 1.

This means that while Terafab will get a proven advanced manufacturing technology, presumably with decent yields, it will not be the absolute best production node at the time, as TSMC intends to start volume production of chips using its A12 fabrication process in late 2029. A12 is a 1.2nm-class process with TSMC's second-generation nanosheet GAA transistors and backside power delivery. Intel will be close to unveiling its 14A-P node at the same time.

Nonetheless, since Terafab will likely exclusively serve SpaceX, Tesla, and xAI, a slightly less advanced node will not be a big problem for the company, as the potential cost increases incurred by using a more sophisticated manufacturing technology will be offset by using an in-house production facility.

Chinese chipmakers have accumulated an estimated 343 immersion DUV lithography chipmaking tools from 2012 to early 2026, many of which can be used to make chips using 7nm-class process technologies, according to a report from the Centre for Technology & Statecraft (CTS). The Washington-based group asserts that this equipment gives Chinese fabs considerable potential to produce sophisticated processors despite their inability to procure ASML's more advanced EUV systems. While the total number of ArFi tools owned by Chinese chipmakers seems plausible, some other estimates look questionable.

China has been particularly aggressive in procuring wafer fabrication equipment in recent years as the U.S. government has been busy imposing various curbs on its semiconductor industry. Since 2012, Chinese chipmakers, including logic and memory makers, have imported 343 immersion DUV lithography scanners from ASML, excluding imports to multinational fabs located within China.

The authors of the report claim that the existing export controls leave an important gap because lithography equipment originally acquired for less advanced process technologies can potentially be reassigned for more sophisticated process technologies, such as 7nm-class nodes (which the industry adopted in 2018 – 2019). This happens at a cost, but if no other options are available, Chinese chipmakers have no choice. They propose to prohibit exports of all immersion DUV systems to China and restrict replacement components and maintenance services for machines installed at advanced fabs, a proposal consistent with the bipartisan MATCH Act introduced in April.

CTS claims that 270 of these immersion DUV tools are ASML's Twinscan NXT:1980i scanners featuring a 38nm resolution and a 2.5nm matched-machine overlay capability crucial for multipatterning for 7nm-class nodes, which can be used to make chips using 7nm-class fabrication technologies. In addition, CTS claims that Chinese fabs own 22 NXT:2050i and six NXT:2000i systems. It is unclear how many of the 296 advanced immersion DUV scanners shipped to China are currently operational.

Dutch authorities introduced licensing requirements for exports of ASML's NXT:2000i and more capable immersion DUV scanners in September 2023, which effectively prevents their shipment to China. As a result, Chinese chipmakers had to opt for the least capable NXT:1980i. CTS now estimates that Chinese fabs purchased approximately 90 NXT:1980i scanners in 2024 and another 89 units in 2025, spending more than $13 billion during the two-year period. While the Netherlands expanded export controls to the NXT:1980i in September 2024, individual exports of this model can still receive approval. Furthermore, ASML can also potentially sell its NXT:1965Ci systems to clients in China, though we are not sure it has all the components needed for these outdated scanners.

ASML's own results reflect unusually high demand from China: the country represented 41% of its net system sales by shipment destination in 2024 and 33% in 2025. That share subsequently declined to 19% in Q1 2026 and 14% in Q2, which is something that ASML had warned about before.

One should keep in mind that the CTS numbers — ~90 NXT:1980i systems in 2024 and 89 in 2025 — cannot be independently reconstructed from ASML's published financial data. At most, ASML's disclosures provide a useful sanity check: China was indeed an exceptionally large destination during precisely those years, while ASML sold 129 and 131 ArFi systems globally in 2024 and 2025, respectively. If CTS' numbers are correct, then Chinese chipmakers bought the lion's share, 70% and 68%, of ASML's immersion DUV tools output in 2024 and 2025 despite export controls introduced in 2024. Meanwhile, the NXT:1980Di systems are readily available on the secondhand market.

*The source mentions the NXT:1980i machines, which probably include the original 1980Di and newer 1980Fi featuring higher productivity. We will use the 'NXT:1980i' name in this story for consistency, even though ASML has never produced a scanner named NXT:1980i.

As the world's only supplier of EUV lithography systems, ASML is Europe's largest company by market capitalization, currently valued at around $660 billion. But it earned almost nothing in Europe this year, down from 1% of total profits in 2025 and 5% in 2024. Why? European chipmakers bought no lithography equipment from ASML in 2026 — and the company is calling on EU authorities to help create demand for European chips.

"We are selling absolutely nothing in Europe," said Frank Heemskerk, executive vice president of public affairs at ASML, while speaking at a panel discussion from the Dutch political and cultural center De Balie. "Because Europe is not investing and because no chip factories are being built in Europe. That is genuinely worrying. […] [Our revenue share in Europe is 0%], it used to be 1%."

Indeed, Europe accounted for 1% of ASML's revenue share in 2025, 5% in 2024, 4% in 2023, and 2% in 2022, based on the company's presentations for investors. In the first two quarters of 2026, however, Europe accounted for 0% of ASML's revenue, according to ASML's earnings reports.

"There simply is no demand here for these kinds of highly specialized machines," Heemskerk said. "That is the problem. So apart from trying to attract investment with capital on the supply side, we should do much more to create demand. […] So, we at ASML are also making an enormous effort, and we are talking with Ursula von der Leyen in Europe, saying: 'try to harness the market power and dynamism that ultimately do exist in Europe in a number of areas.'"

So far, the European Union has been keen on subsidizing building new fabs in Europe (something that did not help to lure Intel in). But ASML is calling on European governments to help aggregate and guarantee demand for European-made chips — which will encourage major European chip consumers to source locally, giving semiconductor manufacturers an economic reason to build or expand fabs in Europe.

"We need to make sure that some of those buyers — the customers of our customers — start talking much more closely with European manufacturers again. In areas such as artificial intelligence for industry, for example, there are still plenty of opportunities that Europe can seize. But you have to organize this collectively."

New fabs are being built…

That said, the ASML EVP may be too pessimistic about Europe's semiconductor industry.

Intel runs its massive Fab 34 near Leixlip, Ireland, and recently announced plans to invest €5 billion in the facility to expand production of CPUs on Intel 4 and Intel 3 process technologies. While the new investment dwarfs Intel's plans to invest roughly €80 billion in its Magdeburg, Germany, fab complex, with two first fabs alone accounting for over €30 billion, it still represents Intel's commitment to its Ireland campus.

In addition, ESMC — which is backed by TSMC, Bosch, Infineon, and NXP — is building a brand-new fab near Dresden that will cost around €15 billion. The fab will be capable of producing chips using 12nm/16nm-class FinFET and 22nm/28nm planar transistor-based process technologies used in a wide range of automotive applications. The same nodes are also used for various consumer electronics and edge applications.

Infineon also opened its new €5 billion Smart Power Fab in Dresden in July 2026, which marked the largest single investment in the company's history and effectively doubled its manufacturing capacity at the site. The 300mm facility produces power semiconductors as well as analog and mixed-signal chips for automotive, industrial, renewable-energy, and AI data-center applications.

Last but not least, GlobalFoundries officially broke ground on the latest major expansion and upgrade of Fab 1 in Dresden this March to increase capacity for its specialty process technologies, including 22nm FD-SOI (22FDX), embedded non-volatile memory (eNVM), and the BCD (bipolar-CMOS-DMOS) node for power management ICs. To some degree, the upgrade was forced by headwinds that GlobalFoundries faced when building the €10.4 billion joint fab with STMicroelectronics in the Grenoble, France, region.

With numerous semiconductor fab projects in place in Europe, ASML will continue to sell its tools to companies in the EU for years to come; the semiconductor industry is far from dead in the bloc. Of course, the important detail is that all of these production facilities are built by multinational corporations (sometimes in collaboration with local companies) — but this is largely a global trend rather than a major issue.

…But there's a catch

Although the fab projects in Europe are large in terms of investment, they pale in comparison with those being built in Taiwan, South Korea, the U.S., and Japan, where tens or even hundreds of billions of dollars are being invested in new semiconductor production facilities.

What is perhaps more important from ASML's standpoint is that none of the ongoing fab projects in Europe are leading-edge fabs set to use EUV and eventually High-NA EUV lithography scanners. The tools that European fabs use today and that new facilities are set to use in the future are mature tools that cost considerably less than advanced EUV or immersion DUV scanners. This is perhaps a concern for ASML, as the company is naturally interested in selling its more sophisticated and expensive equipment.

Another concern is that even advanced silicon produced in Ireland or at ESMC is then shipped to other regions for packaging, meaning that European companies have largely lost their ability to produce sophisticated chips entirely in Europe. In turn, this means that, for now, there is hardly any strategic point for European authorities to create demand for chips that are 'Made in Europe' because they are either not assembled in Europe, not produced in Europe, or not developed in Europe. We have no idea whether this is eventually going to change, but there are currently no signs that it will.

One of the key challenges with the development of extreme ultraviolet (EUV) lithography scanners is building a powerful and reliable light source. ASML, which is the only company to manufacture EUV lithography tools, uses rather complicated laser-produced plasma (LPP) technology to generate EUV light. By contrast, numerous companies propose to use a free-electron laser (FEL), which relies on a particle accelerator, for EUV generation. While FEL has its advantages and is even endorsed by Elon Musk, ASML is unlikely to adopt it, according to JPMorgan.

"Given laser advances, ASML sees no reason to try new 'FEL' light source favored by Musk," reports Semi Doped, citing a JPMorgan note for clients.

Modern EUV lithography systems use laser-produced plasma light sources that fire powerful CO₂ laser pulses at tiny droplets of molten tin, around 30 microns in diameter, which turns them into ionized plasma with electron temperatures of several tens of electron volts that emits 13.5-nm EUV radiation. The light is then collected by a roughly 0.5-meter elliptical collector mirror coated with multiple layers of molybdenum and silicon, which selectively reflects as much 13.5-nm radiation as possible and directs it toward the intermediate focus at the entrance to the scanner.

Since virtually all materials absorb EUV radiation — even specialized multilayer mirrors absorb a substantial portion of it — the entire optical path must operate in vacuum and use reflective rather than conventional refractive optics, which is one reason why generating sufficient EUV source power remains challenging.

Despite major challenges, ASML has gradually increased the source power of its LPP light sources from around 250W to around 500W and plans to increase it to 1000W in the coming years. In addition, the company plans to almost double the number of generated tin droplets to 100,000 every second.

A free-electron laser (FEL) generates EUV light by accelerating electrons to nearly the speed of light and passing the electron beam through an undulator, a series of alternating magnets that force electrons to oscillate and emit radiation. Interaction between the electrons and their radiation causes them to form microscopic bunches and emit light with a 13.5-nm wavelength. This approach eliminates tin droplets and associated debris (that require usage of protective pellicles on photomasks) as well as potentially provides substantially higher EUV power than LPP sources. Furthermore, one FEL can potentially replace multiple LPP sources with a single FEL and a large EUV beam-distribution system.

Yet, there is a major tradeoff: instead of a relatively compact LPP, FEL requires a highly complex particle accelerator, an electron source, a long undulator, electron-beam control, radiation shielding, and an extremely complex distribution system featuring mirrors capable of handling and distributing very high EUV power without losing too much of it along the way. The whole machine must achieve semiconductor fab levels of availability, efficiency, and cost, something that took ASML and the rest of the industry years to achieve.

So, while there is a great enthusiasm surrounding FEL in China, the U.S., and Japan, it will likely take a decade, if not more, before FEL will be able to rival LPP in real semiconductor production facilities. The technology will likely devour billions of dollars in the meantime, so not all entities currently pursuing FEL will live that long.

For years, TSMC has tried to avoid making public comments about its plans to use EUV lithography with a 0.55 numerical aperture optics, or High-NA EUV, because the company's developers had a good idea how to keep advancing process technologies without using $400 million scanners. However, TSMC cannot rely on Low-NA EUV systems forever, so this week the company announced plans to use High-NA EUV starting from 2030.

TSMC did not formally reveal which fabrication technology will be the first to adopt High-NA EUV, though the year 2030 points to a few candidates. What TSMC did say is that it expects the number of layers processed using High-NA EUV to eventually increase as its fabrication technologies become more complex, driven by increasing complexity of transistor architectures, which is probably an implication for more sophisticated implementations of gate-all-around (GAA) transistors as well as complementary field-effect transistors (CFETs) later on.

TSMC plans to start using High-NA EUV lithography tools for high-volume manufacturing in 2030 using conventional 6×6-inch photomasks. The company then plans to build a pilot line that uses 6×12-inch photomasks in 2031 with the goal of bringing 6×12-inch High-NA lithography systems into advanced node production by 2033.

High-NA EUV lithography tools can achieve an 8nm single-exposure resolution, as opposed to a 13nm single-exposure resolution offered by today's Low-NA EUV litho systems. However, when used with conventional 6×6-inch photomasks, High-NA EUV scanners have only half the exposure field of their Low-NA counterparts, which creates challenges for manufacturing very large dies. As a result, chipmakers building massive AI accelerators must either stitch multiple exposure fields together or adopt multi-chiplet designs, two approaches that have their own other challenges, such as tool productivity and power consumption. To circumvent the 6×6-inch photomask limitations, TSMC is working with ASML to set the stage for 6×12-inch photomasks.

Changing the size of photomasks is not a trivial endeavor as it requires changing everything from EDA software to tools that produce and write masks as well as systems that handle them, which essentially means that the entire industry must work on this change. ASML seems to be optimistic about the transition as it is supported not only by Intel and TSMC, but also by Samsung.

"We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips," said Christophe Fouquet, president & CEO, ASML. "We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative."

Perhaps the biggest intrigue about TSMC's usage of High-NA EUV lithography is which process technology will be the first to use the new systems. Based on what we know about TSMC's roadmap, A10 or A11 (1/1.1nm-class) seems to be by far the strongest candidates to use High-NA EUV scanners for the most critical layers. TSMC's latest strategy separates its roadmap into annual client-oriented nodes (N2, N2P, N2X, A14, A13) and roughly biennial high-performance nodes (A16 in 2027, then A12 in 2029). The company has already confirmed that A12 and A13, due in 2029, will continue to rely on conventional EUV lithography.

Since A13 is an optical shrink of A14 that increases transistor density by only 6%, with performance and power improvements yet to be disclosed, its successor in 2030 will likely have to deliver considerably more substantial gains. It is therefore reasonable to expect A13’s successor — whether it is called A11 or A10 — to adopt more advanced lithography and/or TSMC's 3^rd Generation nanosheet GAA transistors to deliver significantly higher transistor density as well as meaningful performance and power improvements over its predecessor. Yet, we are of course speculating.

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.

One million High-NA wafers

Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.

Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.

Sticking to stitching

Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.

Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.

6×12 mask effort progressing

To avoid using stitching, the industry — led by Intel — plans to shift to larger 6×12 masks, which will enable a 26×33 mm full field in one exposure. While this looks easy on paper, make the mask twice as long, changing the mask represents an enormous ecosystem change.

Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.

It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.

Being the world's largest contract chipmaker has its advantages for TSMC when it comes to negotiations with suppliers, as it naturally buys far more than others. However, it also has its difficulties because its requirements are dramatically larger than those of other foundries, and when they grow further, it gets exceedingly hard to source what it needs. Especially when its requirements increase nearly 2X in less than a year.

TSMC has nearly doubled its projected requirements for semiconductor production equipment since the end of last year as the foundry expands manufacturing capacity to address surging demand from the AI sector, said Cliff Hou, TSMC's deputy co-chief operating officer, during a fireside chat at Semicon Taiwan, reports FocusTaiwan. The world's largest foundry admits that it cannot meet all demand from all customers, though it is trying to catch up, according to Bloomberg.

TSMC makes projections about the number of tools it needs to purchase over the following year as well as its spending. After making that assessment late last year, the company discovered that by the end of the first quarter, the requirement had increased to 1.5 times that projection, and by July it had climbed to 1.9 times the original estimate, which means that TSMC's equipment needs had almost doubled in about six months.

TSMC itself attributes its increased needs to the number of new fabs that it is building in Taiwan and the U.S., though it should be noted that in addition to brand-new fabs, the company is also upgrading existing ones, which also need new machinery.

Interestingly, tool count does not seem to be proportional to tool cost. While TSMC increased its 2026 capital expenditure (CapEx) budget significantly in the recent eight months, it increased nowhere near 90%. Back in January, it guided 2026 CapEx to be from $52 billion to $56 billion. By April, it moved its estimate towards the high end of the original guidance, but in July it officially increased it to the range between $60 billion and $64 billion, or by around 15% if we only consider midpoints.

How exactly TSMC makes assessments about the number of tools it needs to buy the following year is something that remains to be seen, but perhaps a more pressing question for the industry is how it plans to acquire that equipment considering shortages of wafer fab tools due to massive demand from virtually all chipmakers.

China's ability to produce lithography tools is comparable to that of market leader ASML sometime in 2004, an analyst with UBS wrote in a note to clients. The situation may change in the next two or five years when Chinese companies start producing immersion DUV lithography systems in mass quantities, and Chinese chipmakers begin to deploy them for production of actual chips. However, China's semiconductor industry will remain well behind Western industry. "They seem to be at a similar stage to ASML in 2004," wrote Francois-Xavier Bouvignies, an analyst with UBS, in a note for clients, reports Bloomberg.

For years, China's pursuit of semiconductor self-sufficiency stemmed from its ability to produce mainstream chips on trailing nodes using fairly advanced, though not the latest, tools from leading producers such as ASML, KLA, and Lam Research. In recent years, China found itself in a new reality in which it could no longer obtain the latest chipmaking tools and had to build them domestically. Although companies like ACM Research, AMEC, and Naura have developed world-class chemical wafer deposition, cleaning, etching, and oxidation/diffusion tools that are now mass-produced and used by Chinese chipmakers, none of the Chinese companies have managed to develop a competitive lithography machine that can be used to make chips on more or less modern nodes and initiate its mass production.

Photolithography is generally considered the most technologically complex and demanding individual process in advanced semiconductor manufacturing. Firstly, lithography systems themselves are extraordinarily complex and contain tens of thousands of individual components. Secondly, the required positional accuracy is extraordinary, as a modern lithography scanner needs excellent resolution, overlay, focus control, scanner-to-scanner matching, CD uniformity, and line edge roughness, just to name some of the requirements. Finally, a competitive litho system must guarantee predictable uptime, defect density, and performance. Perhaps the key thing here is that all of the required features must be achieved without compromises, as, for example, a machine with high resolution and ideal uniformity that can process one wafer per hour cannot be used for mass production.

Historically, over a dozen companies produced lithography tools. However, as they became more complex, only ASML, Canon, and Nikon survived, with ASML being the undisputed market leader and the only maker of EUV lithography scanners.

As China is essentially developing a parallel semiconductor ecosystem, there have been reports of multiple entities working on lithography systems, including Shanghai Micro Electronics Equipment (SMEE), AMIES (which seems to be a SMEE spin-off that includes Aishengna and Yuliangsheng units), SiCarrier (reportedly controlled by Huawei), and even Naura (which denies that it is developing litho tools). SMEE, which was established in 2002, is by far the most important established Chinese manufacturer of litho tools. Meanwhile, so far none of China-based makers of lithography have established mass production of immersion DUV scanners capable of producing chips at 45nm and below.

SMEE reportedly formally introduced its first immersion DUV lithography system called SSA/800-10W and capable of making chips on nodes down to 28nm back in 2023. However, there have been no evidence that SMEE has indeed started mass production of the SSA/800-10W and that it has been adopted by a single manufacturer for mass production of chips. While it is conceivable that not all chipmakers announce deployment of breakthrough tools, especially keeping in mind that Chinese vendors like SMEE have plenty of foreign suppliers, we would have seen at least some indirect evidence (starting from procurement/acceptance records as well as component orders all the way to job postings and scientific papers) that SMEE started shipments of the SSA/800-10W in 2023 – 2024 by now, assuming of course that there were any shipments.

Interestingly, but the reports about China-made immersion DUV scanners now mass-produced by Shanghai Aishengna Electronic Technology Group (a unit, or an affiliate of SMEE) re-emerged this July, again, without any evidence. This time around, the reports did not even mention targeted nodes or throughput capabilities. To make matters even more suspicious is the lack of reports about shipments of evaluation tools to chipmakers (like ASML does this with its High-NA EUV machines) as well as preliminary results of their process qualifications (like Intel does with ASML's High-NA EUV machines).

For a first-ever Chinese immersion scanner, it is reasonable to expect Chinese chipmakers to use it on engineering wafers, characterize it against ASML machines, develop recipes, identify drawbacks, and pass that information back to SMEE, something that should take about a year. Only once that first machine performs adequately does it make sense to order and qualify multiple SSA/800-10W units for mass production. In fact, such qualification will likely take another year for a single layer and more time for additional layers. To that end, an insertion of an all-new lithography scanner into an existing flow will take at least two years, but likely more. To that end, once SMEE (or its business units) and its customers figure out how the first Chinese immersion scanner should work, these scanners will still be far from mass deployment.

In any case, without any real indicators that Chinese makers of wafer fab tools can produce and ship immersion lithography scanners to customers, we can only state what the UBS analyst did: China's lithography industry is in a position where ASML was in the mid-2000s.

The only two places in the world that can build the optical columns inside ASML's lithography scanners -- a key part of semiconductor manufacturing -- are set for dramatic expansion, the manufacturer said on Friday.

Zeiss Semiconductor Manufacturing Technology has confirmed that it's adding around 25,000 square meters of production and production-adjacent space at Oberkochen in southern Germany, with staff moving into the first completed building this month, four years after the 2022 groundbreaking. The remaining buildings will be handed over in stages.

Oberkochen and Wetzlar are the only two places in the world where the optical columns can be built, and ASML's own annual report states that the number of systems it can produce is limited by Zeiss SMT's production capacity. ASML told investors earlier this month that it plans to lift Low-NA EUV output by roughly 30% in 2027.

ASML's 2025 annual report describes Carl Zeiss SMT as its sole supplier of lenses, mirrors, illuminators, collectors, and other critical optical components, held under an exclusive arrangement. If Zeiss couldn't sustain production over a prolonged period, the filing warns, ASML "would effectively cease to be able to conduct our business." Purchases from Zeiss SMT and its subsidiaries reached €4.41 billion in 2025, up from €3.95 billion in 2024 and €3.33 billion in 2023. (1 Euro = 1.14 USD)

CFO Roger Dassen said during ASML's July earnings call that it's close to fully booked on Low-NA EUV for 2027, is raising capacity by about 30% from roughly 65 systems this year, and is evaluating another 30% increase for 2028. He told reporters the same day that the company is compressing its scanner build cycle from around 22 weeks to 15 or 16. It's understood that ASML is planning Low-NA EUV machine price hikes, something which has reportedly upset TSMC.

High-NA projection optics contain more than 40,000 parts and weigh about 12 tons, roughly seven times the volume and weight of standard EUV optics. The illumination system adds another 25,000 parts and 6 tons. Individual High-NA mirrors weigh several hundred kilograms, around twice the size and 10 times the weight of current EUV mirrors, and Zeiss says they're machined for months before reaching the required figure. Verifying them requires a purpose-built vacuum chamber measuring 5 by 10 meters, made up of over 100,000 parts and weighing more than 150 tons. Intel became the first company to ship high-volume logic on 0.55 NA scanners this month. Adding floor space doesn't shorten any of those steps.

ASML held €1.91 billion in loans receivable from Zeiss SMT at the end of 2025, up from €1.44 billion a year earlier, alongside €1.19 billion in advance payments made to secure optical column deliveries. Two €1 billion facilities are in place, signed in September 2021 and September 2024, and ASML issued a further €444 million loan in July 2025 and a €212.5 million short-term loan in November. A May 2025 restatement of the company's framework agreement made the capex loans interest-free, with repayment expected over seven or 15 years and quarterly installments that vary with Zeiss SMT's revenue.

Zeiss SMT booked €5.055 billion in the fiscal year to September 30, 2025, up 23% and the largest of the Zeiss Group's four segments. It's also building a multifunction factory at Wetzlar, added 300 square meters of cleanroom at Rossdorf last fall, and opened an innovation center in Korea this month.

The Hague Centre for Strategic Studies has rated the Dutch semiconductor industry as being at very high risk of Chinese foreign interference in a recent report, placing it above the maritime and aerospace sectors, and citing years of espionage against ASML and NXP. Written by Benedetta Girardi and Hans Horan for the China Knowledge Network, a body funded by the Dutch Ministry of Foreign Affairs, the study calls for stricter vetting of personnel at sensitive chip sites and a public-private fund to swap out high-risk foreign hardware, including server motherboards and baseboard management controllers. Both authors expanded on the findings in interviews with Nikkei Asia last week.

The report sorts Beijing's methods into five categories: economic statecraft, digital and information operations, physical interference, legal pressure, and talent-based technological espionage. ASML said in 2023 that a former China-based employee stole data about its lithography tools from an internal product lifecycle management system, one of several insider theft cases at the company stretching back to 2015, and the Dutch military intelligence service MIVD named all three sectors as Chinese espionage targets in its 2024 annual report.

China restricted rare earth exports through 2025, and ASML's complex optical systems depend on those materials. The EU holds an anti-coercion instrument designed to counter economic blackmail by non-member states, but leaders treat it as a last resort. The tool was "created with China in mind," Benedetta Girardi, program coordinator of the HCSS Europe in the Indo-Pacific program, told Nikkei Asia.

Dutch anti-discrimination law prohibits screening policies that target only Chinese nationals, and the standard VOG background certificate doesn't account for an applicant's conduct or connections outside the EU. The report proposes a tiered system instead, whereby companies identify their "he Hague Centre for Strategic Studies has rated the Dutch semiconductor industry as being at very high risk of Chinese foreign interferencejewels" and apply deeper screening, weighing factors such as susceptibility to blackmail or bribery, to staff with direct access, while junior hires and contractors get lighter checks.

A proposed resilience fund, built with the EU and NATO, would pay to replace equipment such as server motherboards, BMCs, and large ship-to-shore cranes with European-made equivalents. The mechanism would sit alongside Project Beethoven, the €2.5 billion Dutch government effort to expand domestic semiconductor production capacity, and would include surge funding that unlocks during crises such as sanctions escalation or major cyber campaigns.

ASML denied a U.S. government concern in June that one of its EUV machines had reached China in breach of export controls, telling Tom's Hardware the claims were baseless and harmful to its reputation.

The Nexperia dispute, in which the Dutch government seized the chipmaker from its Chinese parent, and Beijing responded by blocking exports from its Guangdong site, played out while the report was being written. In a crisis such as a confrontation over Taiwan, the researchers assess that Chinese leverage over strategic industries would likely constrain Dutch policy choices and limit participation in allied responses.

ASML is reportedly considering increasing prices of its existing Low-NA EUV lithography tools. The potential price hikes have already upset TSMC, ASML's largest client, reports The Information. But can ASML rapidly raise the prices of the tools it sells to chipmakers? Price adjustments are not going to happen overnight, said Roger Dassen, CFO of ASML, said during the company's quarterly earnings call. But there is one thing to remember about ASML's price hikes: They are going to affect the entire semiconductor industry.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. […] Given the long order lead times that we have, that does not translate into pricing effects tomorrow."

ASML just reported record results for its second quarter of 2026, with total net sales of €9.326 billion ($10.67 billion) and net income of €2.918 billion ($3.338 billion). The company now expects net sales between €43 billion ($49.2 billion) and €45 billion ($51.5 billion) in 2026, a range that comfortably exceeds its own guidance and the expectations of industry analysts.

More complex, more expensive

ASML has generally increased the average selling price of EUV scanners over successive generations as they increase in complexity and productivity, so the idea of higher pricing of EUV tools is not particularly new. The company calls the concept of 'value-based pricing' and gradually increases its average selling price (ASP) based on the value that its tools provide to its operators.

Early ASML Twinscan NXE systems were commonly discussed in the roughly €100 million–€120 million ($115 million-$137 million) range, while later production models such as the NXE:3400C and NXE:3600D moved toward roughly €140 million–€170 million ($160 million-$195 million). The latest NXE:3800E is climbing even further. High-NA EXE systems represent another major step up, at more than €350 million ($400 million) per machine according to industry reports.

Meanwhile, both productivity and performance of ASML's Twinscan NXE systems have been steadily increasing: While the NXE:3400C and NXE:3600D can process 160 – 170 wafers per hour (WPH) and feature a matched machine overlay (MMO) of ≤ 1.1nm, the NXE:3800E and NXE:3800F increase productivity to 220 WPH and 260 WPH, respectively, while increasing MMO to 0.9nm. With the NXE:4200G and NXE:4200H (which will likely feature an all-new light source), we are looking at productivity beyond 300 WPH and MMO of ≤0.8nm - ≤0.7nm.

ASML makes no secret that more advanced EUV lithography tools carry a higher average selling price than their predecessors.

"You should also recognize that the tool mix that we are going to ship next year is a different tool mix from the tool mix that we shipped this year," Dassen said. "When it comes to EUV in particular, the tool mix that we are going to ship next year will be EXE: 3800E and EXE:3800F [tools], while this year it is a combination of EXE:3600D and EXE:3800E [systems]."

ASML's value-based pricing logic is essentially: if an upgraded Low-NA machine processes more wafers and therefore generates more economic value for a fab, ASML can capture part of that additional value through a higher system price. This is what ASML has been doing for some time. That said, the important nuance in Dassen's statement is that he appears to be discussing further price increases for Low-NA EUV tools.

ASML's EUV dominance

ASML is the only supplier of EUV lithography systems on the planet; every single chipmaker must comeq to the company to get one of these scanners, so the company sells these machines years in advance. This year, the company expects to have the capacity to build 65 EUV tools and intends to increase capacity by 30% next year to around 84 – 85 EUV systems. In 2028, ASML plans to produce 110 EUV scanners.

"For 2027, we are now close to being fully covered with orders for Low-NA EUV, and we are planning to increase our Low-NA EUV capacity by around 30%," Dassen said. "Looking ahead to 2028, we have already received a significant number of Low-NA EUV orders. Strong demand forecasts from our customers have led us to investigate a further 30% capacity increase for that year."

Given the strong demand for ASML's tools, the company is in a position to increase prices, at least according to the rules of the free market. As always, comments on pricing are made in opaque corporate language, so one can make a lot out of it, or nothing at all.

"Clearly, the environment that we live in today, with the [substantial] value that our products bring to customer, of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, it is not that easy for ASML to just hike prices overnight, and there are important things to note. When ASML gets an order, and that order enters the reported backlog (which totaled €38.8 billion as of late Q4 2025), it already carries a sales value (with a possibility of inflation adjustments), so there is necessarily an agreed or otherwise contractually determined price basis attached to it.

This makes Dassen's comments particularly interesting. If ASML is already close to fully booked for 2027 Low-NA EUV capacity and has received a significant number of Low-NA orders for 2028, then much of that capacity is already represented by customer orders with associated sales values. As a result, unless ASML can subsequently renegotiate the fixed price before delivery, it cannot hike prices on tools that it intends to ship in 2027 and part of 2028. This essentially means that ASML could only book new orders that it intends to ship in 2028 (presumably for the second half of the year) and onwards at higher prices. However, ASML has not confirmed this directly.

ASML's next-generation NXE:4200G is on track to arrive in 2029. That scanner is poised to be more expensive than the NXE:3800E/NXE:3800F anyway, so the company's Low-NA EUV ASPs will inevitably get a bump that year. Of course, ASML is set to continue shipping its EXE:3800-series after 2029. The big question is whether the company will adjust the prices of these units that will ship starting in 2028 or not.

We do not know the answer to this question, unfortunately. But during the conference call, ASML's financial chief implied that the company would like to get 'rewards' from its customers not only for improved productivity, but also for other improvements of its tools, which means that ASML will stick to its value-based pricing model, but may adjust the pricing for the EXE:3800 model.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. [But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out, which, put in another way, customers were paying for the productivity upgrade, and the value that we gave them for free was the value associated with, let us say, overlay improvement, imaging quality […]. In the current environment, with the value that we bring, we are also having conversations with customers on how we get rewarded for that additional value."

TSMC's backlash against the price hikes

As ASML will likely not be able to hike prices on EUV tools that have already been pre-ordered and which are set to be delivered in the course of the next two years, existing chipmakers like TSMC will not feel the effects of the price increase at least over the next 24 months. Of course, if ASML adjusts prices of its EXE:3800-series scanners due to ship in 2028 – 2028, nobody is going to be happy. And yet, TSMC seems to be so upset that the sentiment has made it to the press. There are several reasons behind the reported backlash, but the major one seems to be strategic.

For years, TSMC has said that ASML's High-NA EUV lithography tools were too expensive, and that the company's engineers can continue innovating using Low-NA EUV systems. Also, adopting all-new High-NA EUV scanners will not be an easy undertaking in general, as the transition also requires new photoresists, photomasks, pellicles, metrology equipment, design rules, computational lithography flows, and numerous other supporting technologies and process innovations.

TSMC's mid-term expansion strategy, as well as a leading-edge roadmap through 2030, has been built around extracting more performance and resolution from conventional Low-NA EUV scanners using techniques such as improved masks, computational lithography, and multi-patterning where necessary. If ASML proceeds with its price hikes for Low-NA EUV tools, this can seriously hit one of the key economic foundations of TSMC's strategy.

TSMC's intention to avoid the usage of High-NA EUV scanners until at least 10A-class (1nm) process technology has an important economic advantage. A High-NA EUV system costs more than €350 million, whereas Low-NA systems are substantially cheaper. As a result, TSMC can choose its own trade-off between additional process steps and buying much more expensive lithography equipment. In contrast, Intel, which is set to adopt High-NA EUV lithography for its 14A fabrication process, has much less flexibility: If a particular process technology is designed around High-NA EUV layers, these extremely expensive scanners, along with other ingredients, become part of the manufacturing flow and affect wafer pricing.

One of the reasons TSMC would like to extend usage of Low-NA EUV systems is that it already has the world's largest install base of these tools, as well as mature processes, established flows, and plenty of innovations that enable it to stay ahead of the competition. However, if ASML systematically ties productivity improvements of each new Low-NA EUV generation to higher prices, the cost advantage of staying with Low-NA EUV gradually narrows, which greatly undermines TSMC's strategy.

There are several other reasons for TSMC to be particularly unhappy with ASML. Firstly, TSMC needs an enormous number of tools for its upcoming fabs in Taiwan, the U.S., and Japan. All of the company's leading-edge process technologies through 2029 rely on Low-NA EUV production tools. Even a relatively modest percentage increase applied to dozens of Low-NA EUV scanners can add billions of dollars to the company's capital expenditure (CapEx).

Secondly, ASML is essentially arguing that it deserves a share of its customers' improved economics. From TSMC's perspective, potential price adjustments are very different from charging more because a new scanner is materially more expensive to manufacture. ASML is effectively saying: 'Your fabs are more profitable, and our tools are more productive, therefore we want a piece of that.'

Thirdly, pricing negotiated today determines pricing and TSMC's economy for years to come. Now that ASML is sold out for 2027 and a significant part of 2028, it is negotiating terms for the second half of 2028 and onwards. Accepting a substantial increase now will inevitably carry through to dozens or hundreds of future Low-NA EUV systems, which directly affects TSMC's economics.

As the semiconductor industry increasingly relies on ASML's EUV lithography tools both for logic and memory production, ASML is considering increasing prices of these systems as they deliver greater productivity and better value for its customers. However, with 2027 production nearly sold out and substantial 2028 orders already booked, meaningful increases may primarily affect systems delivered from late 2028 onward. Nonetheless, the idea has already angered TSMC, ASML's largest client, reports The Information.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. "Given the long order lead times that we have, that... doesn't translate into pricing effects tomorrow."

Value-based pricing set to persist… in a new way

ASML has long followed what it calls value-based pricing and gradually increased its quotes based on output, patterning costs, power consumption, and other benefits its new tools offer to clients.

Usually, this involved increasing prices once in a while. For example, if early Twinscan NXE Low-NA EUV systems cost roughly €100 million – €120 million ($115 million–$137 million), the more advanced are priced starting at €170 million ($195 million. It is still well below rumored quotes for High-NA EXE scanners that exceed €350 million ($400 million). At the same time, Low-NA productivity has risen from 160–170 wafers per hour (WPH) and ≤1.1nm matched-machine overlay to 220 WPH/260 WPH with NXE:3800E/NXE:3800F at 0.9nm. Future NXE:4200G/NXE:4200H systems are expected to exceed 300 WPH and improve overlay to ≤0.8nm–≤0.7nm.

"Clearly, the environment that we live in today, with the value that our products bring to customer — it's substantial— of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, later during the call, Dassen emphasized that ASML intends to maintain its value-based approach even in the current environment of high demand and limited supply in the semiconductor world. Yet, he stressed that from now on, ASML might want to charge for things beyond just productivity.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. "[But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out," he said, suggesting that ASML shares value with its clients.

No price hikes in the short term

ASML will be unable to hike prices of Low-NA EUV systems for another couple of years. Since orders that are in ASML's backlog already carry a sales value, subject to inflation adjustments, prices for much of the 2027 and early 2028 output may already be contractually determined. Unless existing contracts can be renegotiated, higher pricing could therefore primarily apply to 2028 shipments and beyond, or for new orders that somehow get squeezed in in 2027. The NXE:4200G, due in 2029, should naturally lift average selling prices anyway as it gets major performance improvements.

TSMC is upset

For TSMC, however, the issue is strategic. The foundry's leading-edge roadmap through 2030 relies on extending Low-NA EUV with better masks, computational lithography, and multipatterning. Until then, TSMC's strategy has always been avoiding High-NA EUV until at least its 10A-class (1 nm-class) technology. If ASML hikes prices of its future Low-NA EUV lithography systems, it will likely affect all of TSMC's plans for the next several years.

TSMC already operates the world's largest Low-NA EUV fleet and needs many more scanners for fabs in Taiwan, the U.S., and Japan as it executes its global expansion strategy. Consequently, even modest increases beyond TSMC's projections could add billions to capital spending, reduce the economic advantage of postponing High-NA, and ultimately raise its manufacturing costs. Moreover, accepting higher prices now could establish the baseline for dozens or hundreds of future systems, which will allow ASML to capture a larger share of the economic value created by increasingly productive lithography equipment.

Can this force TSMC to transition to High-NA EUV tools earlier than planned? Moving to High-NA EUV requires not only €350-million-plus scanners but also new resists, masks, pellicles, metrology, design rules, and computational lithography flows, which are likely not ready at TSMC.

Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Despite disagreements over trade policies with China, the U.S. and the Netherlands have signed the European nation to the Pax Silica initiative of countries looking to reduce reliance on China for key raw materials and manufacturing expertise in the AI industry, as reported by Reuters. With the Netherlands playing host to the key supply chain company, ASML, Europe's largest tech company, and the most advanced manufacturing of cutting-edge photolithography machines for semiconductor fabrication, this is a big strategic win for the U.S.-led initiative.

Dutch ​Trade Minister Sjoerd Sjoerdsma travelled to Washington this week to sign the deal, meeting with U.S. Commerce Secretary Howard Lutnick and fellow lawmakers as part of ongoing negotiations around trade in high-tech chips and hardware, particularly with China.

Speaking with reporters, he said that the U.S. and the Netherlands have shared goals in preventing sensitive technology from ending up in dangerous hands - the Netherlands famously seized key Dutch chip manufacturer Nexperia from its Chinese parent company, Wingtech, in 2025. However, he also raised concerns over American legislation that would make it difficult for companies like ASML to even service machines and tools already delivered to countries like China.

That could affect the Netherlands' national security and market position of key Dutch companies, he said.

Pax Silica - Speremus ut diu duret

The Pax Silica, or "Silicon Peace" initiative, was set up in December 2025 by the U.S. Department of State as a direct plan to reduce reliance on China and to build more robust, Western-aligned supply chains for key elements in the semiconductor, AI, and rare-earth element industries. At its outset, Pax Silica secured non-binding signatures from seven countries, including Australia, Israel, Japan, South Korea, Singapore, the United Kingdom, and the United States. They were joined in the months that followed by Greece, Qatar, the UAE, India, Sweden, Finland, the Philippines, and Norway.

Canada and Taiwan have both been invited to join and are said to be participating in summit sessions, but haven't officially signed just yet. The Netherlands did effectively join in December 2025, but was described as a "non-signing partner" in the initiative.

There are ongoing disputes between the U.S. and the Netherlands over whether ASML should be allowed to service and sell less advanced chip fabrication machines to China, while still restricting access to the latest tools.

Those discussions are reportedly still ongoing and were brought up in the meeting between Lutnick and Sjoerdsma this week. The Dutch official has been quite frank in his public statements on the Match Act bipartisan bill that would place restrictions on companies supplying to China.

“The Netherlands’ starting point is that every country is responsible for its own laws,” Sjoerdsma said in May, via Reuters.

Under the silicon thumb

A key story in the global race to adopt and supply AI through infrastructure building and rapid development has been access to the raw materials, tools, machines, and expertise required to create it. That's mainly had the United States and China at loggerheads with one another, with the former restricting access to cutting-edge Nvidia GPUs and other semiconductor products, and China rowing back access to its manufacturing and raw material industries.

But while that's acted as a tit-for-tat backdrop to U.S. and Chinese trade relations and particularly the mercurial needs and demands of President Trump, the divestment of global supply chains from traditional Chinese sources has spread globally. Nexperia was one key Dutch entity that was brought back in-house from Chinese owners, and in June 2025, Taiwanese firm Pegatron announced new production facilities in Mexico and the U.S. to move away from reliance on China.

The U.S. has also been trying to restrict China's access to high-tech hardware for a number of years. President Trump signed the National Defense Authorization Act in 2019, which effectively banned Chinese firms Huawei and ZTE from being used in any U.S. government agencies. Both companies were later designated as threats to national security in 2020. Under the Biden administration, the U.S. implemented a new series of export controls in 2022 to constrain China's ability to accelerate its high-technology and chip manufacturing industries.

This led to a boom in domestic Chinese chip production, as well as a rapidly expanding black market smuggling industry that ultimately saw officials in U.S. firms jailed, and even Nvidia potentially implicated.

But in 2026, even as the U.S. has approved the sale of some high-end Nvidia chips to China, its new Pax Silica Initiative and MATCH Act are putting more pressure on China than ever before, and global partners aren't entirely happy about it.

Under the bill, foreign-owned companies like ASML that don't comply with the restrictions on business dealings with China could find themselves losing access to U.S. components, software, or customers. Although the world still needs ASML - it's one of the tightest bottlenecks in the global chip supply chain - becoming part of the Pax Silica initiative could prove paramount for advanced economies wanting to make the most of advances in AI and chip fabrication.

Although Dutch officials still clearly have reservations about the MATCH Act, it's not clear how much leverage they can have over it, or whether it's possible to ignore its claimed mandates.

Unsteady ground

The Netherlands and other strategically aligned economies with a foothold in the AI supply chain face a tricky situation in 2026. Initiatives like Pax Silica raise the prospect of greater autonomy in the global supply chain, with less reliance on China for key materials, tools, and manufacturing expertise. But that may simply replace one dependency with another, trading exposure to Beijing for greater oversight from Washington, and even coercion if certain controls aren’t adhered to.

For the Dutch, ASML isn’t just a key company. It is one of the world’s most important technology pillars and helps the Netherlands punch well above its weight in global supply-chain politics. Without ASML, manufacturers like Samsung, Micron, and TSMC, and component designers like Nvidia, would not be able to build the cutting-edge hardware they can today. That gives the Netherlands real muscle when pursuing its own interests.

But it also makes ASML a target for legislation that could limit Dutch autonomy and force tighter integration with larger players like the United States, without whose components, software, and market access ASML would struggle.

That tension is unlikely to disappear. Even if the U.S. midterms later this year help leash some of the more turbulent aspects of the Trump administration, they won’t end American ambitions to pull control of the global chip and AI supply chains away from China, and tuck it into Washington’s own catalogue of control.

An interesting conversation on X has unearthed the existence of a rare ASML-focused Special Edition Monopoly board. Two chipmaking and engineering enthusiasts appear to have clinched a deal where one hands over an ASML Lego kit, a scale model of the world’s first High-NA EUV machine. In the no-cash deal, the other party will receive an ASML Special Edition Monopoly board. It appears that the deal is done, barring any regulatory hurdles and no one changing their minds, but it did pique our interest in the history of the board.

While we’ve seen and reported on the ASML chip tool Lego sets previously, this is the first time the firm’s special edition Monopoly set has blipped on our radar. It is possible this obscurity is due to this board game edition coming out way back in 2007, when the pioneering Dutch semiconductor company’s profile wasn’t quite as high as it is now. With the semiconductor segment becoming all the more important in recent years, driving the current AI boom, cutting-edge chip tool firms like ASML have risen to great prominence.

ASML’s special edition merchandise is also in high demand in the 2020s. Thankfully, we can learn a little more about the provenance of the headlining Monopoly board as it is featured in the board game’s Wiki. As previously mentioned, it was produced in 2007. Specifically, it was prepared for the Christmas period at the end of that year “as a gift to ASML employees and their families this holiday season.” From that ‘publisher’s description, it sounds like quite a few employees will have received one of these games, but it is still obviously an attractive collector’s item.

Sadly, the Wiki imagery doesn’t clearly show what the playing ‘tokens’ are (that’s Hasbro’s official term for the little metal playing pieces). The normal game has tokens like a boot, a dog, and a car, but we can’t quite make out the detail on this. Instead of streets and avenues, the ASML Monopoly board appears to have technologies and machines. Furthermore, the traditional stations are replaced by ASML campuses. Elsewhere on the board, special spaces include Corporate Tax and Press Release, where you must pick up a card. Regular Monopoly features such as Go, Water Works, Go To Jail, and the Electric Company remain.

Other non-consumer-facing semiconductor brands like TSMC and SK hynix have released successful sellout merchandise and memorabilia in recent years. Some items are easier for non-employees to get a hold of than others. For example, it is easy for anyone to find resellers of TSMC-related merchandise on Taiwan’s Shopee marketplace.

ASML has told Tom's Hardware that claims one of its extreme ultraviolet (EUV) lithography systems has ended up in China despite export restrictions is both inaccurate and damaging to its reputation. It follows a report that Commerce Secretary Howard Lutnick questions senior leadership, concerned that one of the machines had ended up in China in breach of export restrictions.

The company is refuting a recent report claiming the U.S. government believes that one of ASML's extreme ultraviolet (EUV) lithography systems may have somehow reached China despite export restrictions, according to Bloomberg, citing sources familiar with negotiations between the U.S. officials and ASML executives. ASML denies any wrongdoing and claims that it knows the location of every EUV tool it has ever built.

The issue reportedly emerged during meetings between U.S. Commerce Secretary Howard Lutnick and ASML executives. According to people familiar with the discussions cited by Bloomberg, Lutnick questioned whether an EUV system may have found its way into China. Such a development would represent a major breach of export controls because, under the Wassenaar Arrangement, ASML can not ship EUV lithography equipment to Chinese customers. In fact, the only EUV tool that China-based Semiconductor Manufacturing International Corp. (SMIC) has bought remains in the Netherlands. As a result, ASML calls the accusations 'unfounded' and 'damaging.'

"In recent years, ASML has refuted several unfounded rumors regarding non-compliance with export controls concerning China which were inaccurate and damaging to our reputation," a spokesperson for ASML told Tom's Hardware.

The U.S. government has not publicly produced evidence that a complete EUV scanner is operating in China. Yet, several senior administration officials told Bloomberg that they possess information indicating that ASML exported equipment associated with EUV systems, including specialized systems used to 'transport EUV machines.' Those officials declined to disclose any evidence, citing sensitivity concerns.

"ASML has never shipped an EUV machine to China, nor have we shipped to China any component, module or equipment specially designed to be used in an EUV machine," the spokesperson told us.

An ASML EUV scanner is made of 100,000 components and weighs 180 tons. It is transported only by air on multiple planes, and it would be impossible to intercept such a shipment without causing an international scandal. Meanwhile, given the complexity of the machine, it is impossible to build one using spare or scrap parts or reverse engineer it using its components, as we reported back in December.

Bloomberg claims that ASML has circulated an internal presentation titled 'No indication of any ASML EUV System in China,' which reportedly states there are 314 EUV systems currently operating worldwide and another 26 that have been retired. According to the document, none are located in China. The presentation further notes that EUV scanners continuously communicate with ASML, so the company can detect interruptions, abnormal activity, or connectivity issues. In addition, customers cannot simply dismantle, transport, and reinstall an EUV scanner without direct assistance from ASML due to specialized logistics and handling requirements.

ASML certainly understands concerns of the West regarding China, so claims it has never shipped an EUV tool to the People's Republic initially due to the Wassenaar Arrangement and then due to more recently imposed export controls.

"ASML regularly engages in transparent and open dialogue with government leaders globally," ASML told us. "We recognize the national security considerations behind export control regulations in the U.S. and the Netherlands. As a company, we are fully committed to abiding by all laws and regulations applicable to our business activities, including all applicable relevant export control regulations, and we have consistently adjusted our business to any development in export controls to comply to any new rules."

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

Chinese semiconductor start-up Prinano announced that it has successfully validated the mass production of photonic chips without using the industry-standard lithography equipment. According to an SCMP report, the company said in a WeChat post on Friday, June 5th, that it had made 8-inch optical chip wafers in collaboration with Shenzhen Litra Technology. The company said it achieved this while “completely avoiding” the need for deep-ultraviolet lithography (DUV), a significant breakthrough in China’s push to reduce its dependence on ASML lithography tools, which remain subject to export restrictions.

Instead of conventional optical lithography, Prinano said it used its PL-AS vacuum air-cushion nanoimprint lithography (NIL) system, which, according to the company, can reduce manufacturing costs to roughly one-tenth that of traditional DUV-based processes, while supporting wafer-level production of photonic chips.

Modern chips are typically produced using highly sophisticated DUV or more advanced EUV (extreme ultraviolet) systems that project circuit patterns onto silicon wafers using light. These machines contain some of the most complex optics ever built and can cost hundreds of millions of dollars. Nanoimprint lithography takes a very different approach. Rather than projecting patterns using light, it physically presses nanoscale structures into a specially prepared resist layer, basically stamping microscopic patterns directly onto the wafer surface. This process eliminates the need for many of the expensive optical systems required by conventional lithography equipment.

Nanoimprint lithography has long been viewed as a potential alternative to conventional optical lithography because of its potential for lower costs and extremely high pattern resolution. However, despite its promise, the technology has struggled to achieve widespread adoption in semiconductor manufacturing due to concerns about defect rates, template wear, throughput, and production yields, all of which become increasingly important in high-volume manufacturing environments.

Founded in 2017, Prinano has spent the past several years working to overcome those limitations by developing its own nanoimprint lithography ecosystem. The company took a significant step in 2025 when it announced the delivery of what it described as China's first semiconductor nanoimprint lithography system to a domestic customer, marking an early effort to commercialize the technology.

The company's latest announcement suggests it may have progressed beyond equipment development and pilot deployments. According to Prinano, its PL-AS vacuum air-cushion nanoimprint lithography platform incorporates wafer-level pressure control, customized double-layer imprinting materials, and proprietary process technologies capable of producing sub-10-nanometer features. The company now claims those developments have enabled the successful validation of wafer-scale photonic chip production on 8-inch wafers.

Importantly, Prinano is not attempting to replace the production of cutting-edge processors or AI accelerators. Instead, the company's announcement focuses on photonic chips, a category of semiconductors that manipulate light rather than electrical signals. These devices are widely used in fiber-optic communications, data center interconnects, sensing systems, and LiDAR technologies.

Photonic chips are considered particularly well suited to nanoimprint lithography because many of their critical structures, including waveguides, gratings, and ring resonators, consist of repeating nanoscale patterns that can be replicated efficiently through imprinting techniques. This characteristic makes them a more practical near-term application for NIL than advanced logic chips, where defect rates and alignment requirements are far more demanding.

Another noteworthy detail is the use of 8-inch wafers. While leading-edge processors are increasingly manufactured on larger 12-inch wafers, 8-inch wafers remain widely used across specialized sectors such as compound semiconductors and power electronics. Demonstrating production on full 8-inch wafers suggests the process has moved beyond laboratory-scale demonstrations and into a format more compatible with commercial manufacturing.

The development also highlights China's broader search for alternative semiconductor manufacturing pathways amid ongoing export restrictions. Access to advanced lithography equipment from ASML — required for EUV and DUV — has been increasingly constrained under US-led controls, prompting Chinese companies to explore alternative approaches ranging from advanced packaging technologies to new chip architectures and novel manufacturing methods. Huawei recently announced a new LogicFolding chip architecture that allows the company to develop high-performance processors without relying on restricted EUV lithography machines.

Significant questions remain about Prinano’s announcement. While the claims have been validated in mass production, the company did not disclose production volumes, yield rates, defect densities, customer shipment data, or independent third-party validation. These metrics are critical for determining whether a semiconductor manufacturing technology is commercially viable rather than merely technically feasible.

ASML has confirmed that a group of disgruntled workers is pushing back hard against an invitation for Elon Musk to address the equipment maker’s closed annual tech conference in Den Bosch this Thursday. According to Dutch publication Eindhovens Dagblad (via DutchNews), employees have been airing their grievances on the company’s internal comms platform, with several threatening to skip his appearance altogether because of his involvement in U.S. politics and what staff described as "Nazi sympathies."

If the invitation is accepted, Musk could join CEO Christophe Fouquet by video link to discuss AI, robotics, space exploration, and semiconductor production, with the conversation centered around Terafab, the SpaceX and Tesla chip venture whose proposed Texas fab can’t reach production without ASML's machines.

Backlash began to surface on Viva Engage, ASML’s internal employee platform, where workers have argued that giving the controversial tech leader a platform clashes with the company’s stated commitment to an inclusive culture. In particular, ASML staff have specifically highlighted Musk’s political activities around the Trump administration, general anti-European rhetoric, and what staff described as “Nazi sympathies.” In March, an Amsterdam court banned the Grok image-generation app due to its abusive “undressing” image generation capabilities.

ASML is the sole monopoly supplier of EUV lithography systems, the tools needed to pattern transistors at the leading edge; fabs targeting advanced nodes have no viable alternative.

Every major foundry and memory maker, including TSMC, Samsung, SK hynix, Micron, and Intel, already holds orders with the company. Terafab, by contrast, has no path to leading-edge production that bypasses ASML, and the company’s CEO said last month that Musk is "very serious" about the project, noting that ventures like Terafab and Starlink would strain equipment makers' capacity over the coming years.

ASML hasn’t addressed the internal revolt directly, saying only to employees via Viva Engage that it’s committed to a workplace where everyone feels respected and is free to express their opinion.

Musk announced Terafab in March as a SpaceX and Tesla joint venture with an initial $20 billion budget, targeting 2nm production and a terawatt of annual compute for AI, robotics, and orbital data centers. SpaceX has since filed a property tax abatement application in Grimes County, Texas, for a fab costing $55 billion in its initial phases and up to $119 billion if all expansions proceed, with Intel set to contribute its 14A process technology. Outside estimates run higher, with Bernstein analysts arguing the full terawatt project would require roughly 358 fabs and around $5 trillion.

“ASML regularly invites technology leaders from the industry to share their insights. The invitation to Elon Musk took place in the context of the Terafab project, which is highly relevant to the semiconductor industry,” the company said.

ASML closed Wednesday, June 3rd, as the most valuable company in European history, reaching a market cap of $668 billion and passing the $650 billion record Novo Nordisk set in June 2024. The Dutch firm, which is the sole supplier of the extreme ultraviolet (EUV) lithography machines that TSMC, Samsung, and Intel use to print leading-edge logic, rose after JPMorgan and Morgan Stanley published near-identical notes arguing it can manufacture far more machines than the market had assumed.

The two banks raised their price targets on the same day, JPMorgan to €1,900 from €1,515 and Morgan Stanley to €1,660 from €1,400, both keeping Overweight ratings. JPMorgan analyst Sandeep Deshpande argued that ASML can deliver more than 110 low-NA EUV systems without adding new building capacity, well above the roughly 90 units investors had previously cited as the maximum and above the company's own near-term output.

That output is mission-critical for the chip industry because EUV remains a severe chokepoint on advanced chip supply. Every wafer of leading-edge silicon used to train and run AI models passes through an ASML scanner at some stage, so more machines shipping translates directly into more capacity for the fabs downstream.

Morgan Stanley said its greater confidence in near-term shipments stemmed from comments at ASML's April annual general meeting, where the company outlined an expansion at the Brainport Industries Campus in Eindhoven, with construction set to begin in the third quarter of 2026. The bank cautioned that the campus "needs to be the start of a multi-phase build-out" to fully alleviate capacity concerns.

ASML’s record ironically sits below the bar set by the companies ASML supplies. Its market cap remains short of the trillion-dollar mark that several U.S. chip firms have cleared, and the stock's roughly 50% gain this year has trailed the broader semiconductor sector, which has run far hotter on AI demand. ASML had already passed SAP as Europe's largest listed company and is now worth more than the next two European firms, HSBC and Roche, combined.

And while the company holds a monopoly, its long-term dominance isn’t guaranteed; several efforts are currently taking aim at it. Substrate, a San Francisco startup backed by Peter Thiel's Founders Fund and the CIA-linked In-Q-Tel, has raised $100 million for a particle-accelerator X-ray lithography system that it claims can pattern 2nm-class features at roughly $10,000 per wafer against the $100,000 it models for leading-edge EUV. Canon is also shipping commercial nanoimprint tools, while Nikon has entered with a lower-end product, and China has touted a workaround to ASML's equipment.

None of these is likely to replace an EUV scanner in high-volume logic anytime soon, where ASML's tools run from roughly $235 million for a low-NA system to about $380 million for the High-NA EXE:5200B that Intel installed late last year for its 14A node.

Asked about rivals by TechCrunch last month, ASML CEO Christophe Fouquet said the gap between wanting the technology and having it remains vast, adding that "when you start from scratch, the challenge is enormous."

Nikon will try to win back lithography customers by selling argon fluoride (ArF) tools for less than market leader ASML, the company's new president and chief executive, Yasuhiro Ohmura, told Nikkei Asia in a recent interview. Ohmura, who took the role in April, said Nikon is talking to several large chipmakers in the U.S. and Asia about fresh ArF orders, with discussions "nearing purchase orders."

Nikon’s pitch to customers comes after a brutal stretch for the business: Nikon shipped 11 ArF systems in its fiscal year ending March 2024 and none across the first three quarters of its 2025 fiscal year, according to company figures reported by TrendForce, against ASML's grip on more than 80% of the lithography market.

Competing on price like this targets a segment of the market that ASML doesn’t outright dominate. While it holds an obvious monopoly position on extreme ultraviolet (EUV) systems used for the most advanced chipmaking processes, ArF immersion is a type of mature deep ultraviolet (DUV) work, and the majority of patterning steps, even on a 3nm chip, still run on it. ASML's advanced ArF immersion machines average around $82.5 million per unit, leaving room for a cheaper rival. Nikon walked away from EUV in 2008.

In February, Nikon said that it would launch a new ArF immersion platform in its 2028 fiscal year, fitted with a new lens and wafer stage, and built for compatibility with ASML's installed tools. "We manufacture many parts in-house, giving us an advantage in cost competition," Ohmura told Nikkei Asia.

Nikon and ASML are the only two companies that build ArF lithography equipment, and demand is climbing as the AI bubble strains tool supplies. ASML shipped 48 EUV and 131 immersion DUV systems in 2025 and closed the year with a €38.8 billion order backlog. Ohmura argues that chipmakers would rather buy from two suppliers than depend on one to keep a lid on equipment costs.

Whether price alone will pull customers back remains to be seen. Nikon's ArF market share has kept sliding since ASML pulled ahead through long-term R&D partnerships and exclusive handling of cutting-edge tools, and Intel, which once accounted for 80% of Nikon's ArF orders, has cut spending amid its own manufacturing troubles.

Nikon posted a net loss of 86 billion yen ($540 million) for the year ended March, its worst ever, dragged down by weak equipment orders and a struggling metal 3D printing unit. Ohmura says he plans to narrow Nikon's focus to cameras and chipmaking tools.

ASML CEO Christophe Fouquet said on Wednesday that he has spoken directly with Elon Musk about the TeraFab semiconductor project, telling Reuters that the SpaceX and Tesla founder is "very serious" about building one of the largest chip manufacturing operations ever attempted.

Fouquet, speaking at a tech event in Antwerp, Belgium, also warned that soaring AI demand will leave the global semiconductor industry short on capacity for the foreseeable future.

TeraFab, which Musk announced in March with an initial $20 billion investment, will aim to produce logic chips, memory, and advanced packaging under one roof in Texas. Intel joined the project in April and plans to contribute its 14A process technology, and SpaceX has since filed for a $55 billion semiconductor facility in Grimes County, Texas, with potential expansion costs reaching $119 billion.

Fouquet didn’t share details of his conversations with Musk but said that projects like TeraFab and Starlink would put pressure on equipment makers' capacity over the coming years.

ASML is the sole global supplier of EUV lithography systems, which are required to manufacture any chip at the leading edge. Any serious new entrant to advanced chipmaking, TeraFab included, would need to procure billions of dollars in ASML equipment. The company currently has orders from every major foundry and memory maker, including TSMC, Samsung, SK Hynix, Micron, and Intel.

Fouquet says that he expects the first logic chips produced with ASML's High NA EUV lithography systems to arrive within months. Intel is the earliest adoptee, having installed and completed acceptance testing of its Twinscan EXE:5200B at the D1X fab in Oregon late last year. The High NA tools use a 0.55 numerical aperture lens, enabling roughly 2.9 times the transistor density of current EUV systems in a single exposure.

Fouquet also confirmed that ASML is developing a second advanced packaging tool, expanding the company's product line beyond lithography. He described the segment as “a small leg” right now, but added that it will present new opportunities for ASML.

On export controls, Fouquet pushed back against the proposed MATCH Act, which U.S. lawmakers introduced last month to ban sales and servicing of ASML's DUV lithography tools to Chinese customers, among other things. He noted that the DUV immersion systems ASML currently sells to China are based on tech first introduced in 2015, placing them eight generations behind the leading edge. Further restrictions, he argued, would only speed up China's domestic efforts to develop competing tools.

"If I put you in a desert and tell you you're not going to have access to food anymore, how long does it take you to make your own garden?" Fouquet told Reuters. "It's a matter of survival."

ASML and Tata Electronics have signed a memorandum of understanding to deploy ASML's lithography equipment at India's first front-end semiconductor fab, a 300mm facility under construction in Dholera, Gujarat.

The deal was signed during Indian Prime Minister Narendra Modi's visit to the Netherlands, with Dutch Prime Minister Rob Jetten also present, and covers lithography tools, talent development, and supply chain support for a fab backed by $11 billion in total investment.

Taiwan's Powerchip Semiconductor Manufacturing Corporation (PSMC) is licensing the process technology for the Dholera fab, covering 28nm, 40nm, 55nm, 90nm, and 110nm nodes, according to the ASML press release. PSMC is also providing design and construction assistance under a definitive agreement finalized with Tata Electronics in 2024.

At full capacity, the plant is designed to produce 50,000 wafers per month for a chip portfolio that covers power management ICs, display drivers, microcontrollers, and high-performance computing logic for automotive, mobile, AI, and communications applications, according to the companies' joint statement.

"ASML's deep expertise in holistic lithography solutions will ensure the timely ramp of our fab in Dholera, create a resilient and trusted supply chain for our global customers, drive innovation, and develop talent locally," Randhir Thakur, CEO and MD of Tata Electronics, said in the press release.

It was reported last month that civil construction at the Dholera site has reached roughly 50% completion. The project required a major redesign late last year after soil testing found the ground too soft and saline for the original structural plan, though it was said at the time that the changes wouldn’t delay the project’s overall timeline, and trial production is still targeted for later this year.

India's government is covering 50% of the eligible project costs through the India Semiconductor Mission, according to a fiscal support agreement signed in March last year between Tata Electronics and the Indian government's ISM.

The Gujarat state government provides additional incentives, including subsidized land in the Dholera Special Investment Region, reduced power tariffs, and stamp duty exemptions. The Dholera site was formally designated a Special Economic Zone in April 2026.

This deal is the latest in a series of partnerships that Tata has assembled for the Dholera project. India joined the U.S.-led Pax Silica initiative back in February, a supply chain alliance spanning semiconductors, AI infrastructure, and critical minerals.

India currently has no front-end wafer fab capacity. While Micron does operate an assembly and test facility in Sanand, Gujarat, and several other packaging and testing projects are in development, the Dholera fab is the country's only commercial foundry project. ASML CEO Christophe Fouquet described India's semiconductor sector as presenting "many compelling opportunities" in the joint statement, adding that the company looks forward to contributing "technological expertise" and helping "nurture talent in India."

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

The Dutch company holds a 100% monopoly on EUV lithography and approximately 83% of the global lithography market overall, and its roadmap now spans four distinct generations of technology: DUV immersion systems that still handle the majority of layers on every advanced chip, low-NA EUV scanners that enabled the 5nm and 3nm era, High-NA EUV tools now entering early production at Intel and Samsung, and a Hyper-NA concept that remains in feasibility studies for the 2030s.

Each step up this ladder delivers finer resolution at exponentially higher cost and complexity, and just how aggressively the industry's largest chipmakers adopt each generation will determine the pace of transistor scaling for the next decade and beyond.

DUV immersion and low-NA EUV

ASML's DUV immersion systems are still the backbone of semiconductor manufacturing when it comes to volume production. The company sold 131 immersion DUV tools in 2025. Even a chip built on TSMC's 3nm node uses EUV on only a handful of critical layers; the majority of patterning steps still run on DUV immersion tools like the TWINSCAN NXT:2100i, which delivers 295 wafers per hour at 1.35 NA with 1.3nm overlay.

DUV single-exposure is also the standard in mature nodes powering automotive and industrial chips. While DUV multi-patterning can push down to 7nm and even 5nm, it comes at an enormous cost of up to 34 patterning steps at 7nm versus nine with EUV.

Chinese customers purchased an estimated 70% of ASML's DUV immersion systems in 2024, stockpiling ahead of tightening Dutch export restrictions that now cover the NXT:1970i and newer models. SMIC demonstrated 7nm production using DUV multi-patterning for Huawei's Kirin 9000S, according to TechInsights. But the process requires significantly longer cycle times than EUV-based production, and questions exist around whether yields are sufficient for volume commercialization.

On the EUV side, ASML's low-NA systems operate at 0.33 numerical aperture with 13.5nm wavelength light, achieving 13nm single-exposure resolution. The TWINSCAN NXE:3600D, introduced around 2021, delivers 160 wafers per hour with 1.1nm matched-machine overlay. Its successor, the NXE:3800E, began shipping in March 2024 and pushes throughput to 195 wafers per hour, upgradable to 230 — following ASML's recently updated roadmap — while tightening overlay below 1.1nm. Each NXE:3800E costs roughly $180 million. It shares its bottom module, including wafer handler and faster stage mechanics, with the High-NA EXE platform, a decision that reduces ASML's manufacturing complexity and provides fabs with a degree of serviceability continuity when they upgrade.

ASML's roadmap extends low-NA further, with the NXE:3800F expected around 2027. It targets a ≤0.9nm overlay and over 260 wafers per hour. A subsequent NXE:4200G targets a ≤0.8nm overlay and over 300 wafers per hour, with an NXE:4200H beyond that at a ≤0.7nm and 330 wafers per hour. Further out, ASML has disclosed a High Productivity platform, the NXE:4600, targeting 400 wafers per hour or more.

TSMC has confirmed that it will not use high-NA EUV for its A16 (1.6nm) or A14 (1.4nm) nodes, instead relying on low-NA with multi-patterning. Kevin Zhang, TSMC's Deputy Co-COO and Senior Vice President of Business Development, said at the company's European Technology Symposium last May that TSMC would adopt high-NA "whenever we see high-NA will provide meaningful, measurable benefit," adding that the technology team continues to extend the life of current EUV.

Computational lithography is one reason low-NA can stretch further, with ASML's Brion subsidiary developing inverse lithography technology and curvilinear mask optimization software that computationally corrects for optical distortion beyond specification, effectively squeezing better resolution from existing 0.33 NA optics without hardware changes.

TSMC has been a major user of these techniques, and their continued advancement narrows the gap between low-NA double patterning and High-NA single exposure. ASML's installed base management business, which services and upgrades the global fleet of lithography tools, reached €8.2 billion in revenue in 2025, up 26% year-over-year. That recurring revenue stream grows with every tool shipped and is increasingly important as fabs push older systems to higher utilization rates.

High-NA EUV

The jump to 0.55 numerical aperture with high-NA is the largest optical leap in EUV's history, shrinking minimum resolution from 13nm, which itself was down from 30nm with DUV, to 8nm and enabling approximately 2.9 times higher transistor density in a single exposure. ASML's first High-NA tool, the EXE:5000, shipped to Intel in December 2023 as a development platform.

Each unit of the production-capable EXE:5200B weighs in at 150,000 kilograms, requires 250 shipping crates, and takes six months and 250 engineers to assemble on-site, says Intel. Priced at approximately $380 million, the EXE:5200B delivers 175 wafers per hour at 50 mJ/cm² dose with 0.7nm overlay. ASML told Reuters in early 2024 that it had taken 10 to 20 orders by that point and planned to deliver 20 annually by 2028.

Intel announced that it had completed acceptance testing of its EXE:5200B in December 2025 at its Hillsboro D1X fab and that the tool will be used for the development of Intel's 14A fabrication process. 14A is expected to be the first production node to rely on High-NA for its most critical layers, with risk production targeted for 2027.

In September, SK hynix became the first memory manufacturer to install a commercial High-NA system at its M16 fab in Icheon, South Korea. Samsung, meanwhile, received its first EXE:5200B in October, with a second unit due in the first half of 2026 for its 1.4nm foundry node. Imec, the Belgian research institute, secured an EXE:5200 last month with a Q4 2026 qualification target for sub-2nm process development.

ASML's near-term High-NA roadmap includes the EXE:5200C, targeting 190 wafers per hour without stitching and 160 with stitching at sub-0.8nm overlay, followed by the EXE:5200D at 195/175 wafers per hour and eventually the EXE:5400E at 210/180 wafers per hour with sub-0.7nm overlay. A High Productivity variant, the EXE:5600, targets 250 wafers per hour or more.

Analysts from SemiAnalysis believe TSMC won’t adopt High-NA EUV until its 1nm-class A10 node, which would place volume deployment around 2029 to 2030, because existing low-NA EUV systems can match High-NA's 8nm resolution using double patterning, and SemiAnalysis estimates that approach may still cost less than High-NA single patterning. High-NA tools also require substantial changes to existing fab buildings to accommodate their size.

Hyper-NA and pellicles

ASML placed Hyper-NA on its official roadmap for the first time at imec's ITF World in May 2024, with former CTO Martin van den Brink commenting a few months prior that an NA above 0.7 "is certainly an opportunity that will become more visible from around 2030." The primary target is 0.75 NA, with 0.85 NA also under investigation. Zeiss has begun preliminary lens designs. Estimated tool cost: roughly $720 million per system, according to TrendForce.

At 0.75 NA, however, polarization effects begin destroying imaging contrast because one polarization orientation effectively cancels light at extreme incidence angles, thereby necessitating the use of polarizers that block photons and reduce efficiency. Depth of focus shrinks further, and resists must be made even thinner than the sub-30nm films used for high-NA, worsening etch selectivity and stochastic defects from photon shot noise. On top of all that, an electron blur of approximately 2nm may impose a solid resolution barrier regardless of optical improvements.

Pellicle development is another bottleneck. These ultra-thin membranes protect masks from particle contamination during exposure but must transmit EUV light efficiently at rising source power levels. ASML's current composite silicon-based pellicle achieves over 90% transmission at 380 W source power, but for future systems running at 600 W to 1,000 W, carbon nanotube pellicles are the next-gen technology, achieving up to 97% transmission while withstanding temperatures above 1,500 C. Mitsui Chemicals is building dedicated CNT pellicle production capacity targeting 5,000 sheets per year and commercialization aimed for this year.

Export controls and Canon NIL

EUV systems have never been sold to China, blocked since 2019 under U.S. pressure despite existing orders from Chinese customers. In addition, Dutch export controls, effective since late 2023, required licenses for advanced DUV immersion systems (NXT:2000i and newer), and by September 2024, the restrictions expanded to include the NXT:1970i and NXT:1980i.

Servicing restrictions also prohibit ASML from improving overlay accuracy or increasing throughput by more than 1% on installed Chinese systems. China represented 49% of ASML's revenue at the peak of stockpiling in Q2 2024, falling to roughly 36% for full-year 2024. ASML's management guided China to approximately 20% of revenue in 2025 and 2026, which has seen South Korea and Taiwan emerge as the primary growth markets, with SK hynix alone placing a record $7.9 billion EUV order last month covering roughly 30 systems over two years.

Canon's FPA-1200NZ2C nanoimprint lithography system, announced in October 2023, represents the only credible alternative patterning approach. At roughly $15 to $20 million per system with 90% lower power consumption than EUV, it uses direct mechanical pattern transfer rather than optical exposure. Canon delivered the first commercial unit to the Texas Institute for Electronics in September 2024, and its current specs show some significant limitations: 80 to 100 wafers per hour (versus 195+ for low-NA EUV), 14nm minimum linewidth, and 2.4 to 3.2nm overlay (versus sub-1.1nm for EUV).

Japan's Dai Nippon Printing (DNP) is targeting 2027 mass production of 1.4nm-class nanoimprint templates, but no major foundry has committed to NIL for high-volume logic manufacturing. The technology's likely niche remains repetitive memory patterns, particularly high-layer-count 3D NAND, where its cost advantage could outweigh the throughput and overlay penalties. Defect density from direct physical contact between template and resist remains the fundamental barrier to logic adoption, where a single misplaced particle can kill an entire die.

ASML revenues continue climbing

ASML's 2025 results reflect the sheer scale of its roadmap, with €32.7 billion in revenue (up 16% year-over-year), 52.8% gross margin, and €9.6 billion net income. EUV became the leading source of system revenue at 48%, or €11.6 billion, up 39% from 2024. Net bookings surged 48% to €28 billion, with Q4 2025 alone delivering a record €13.2 billion in orders. The company recognized revenue on two High-NA systems during the year.

ASML's Q1 2026 results, published April 15, show €8.8 billion in total net sales at 53% gross margin, with €2.8 billion net income. The company shipped 16 EUV and 17 immersion DUV systems in the quarter, with South Korea accounting for 45% of system sales by region and China at 19%. ASML raised its full-year 2026 revenue guidance to €36 to €40 billion, with 51% to 53% gross margins

Each NA increase delivers diminishing resolution gains at exponentially rising cost and complexity. The most likely trajectory is not a clean generational handoff but an extended coexistence: low-NA handling the bulk of EUV layers well into the 2030s, High-NA reserved for the most critical pitches at sub-2nm nodes, and Hyper-NA arriving as a targeted tool for the most extreme features, subject to workarounds for the bottlenecks we’ve discussed above.

U.S. lawmakers have revised the MATCH Act to narrow its scope after industry pushback and removed one of the most sweeping provisions that prohibited sales of cryogenic etching tools to chipmakers in the countries of concern (most notably China), reports Reuters. Yet Chinese chipmakers were not allowed to obtain these tools anyway due to existing export controls, which makes the alterations somewhat cosmetic.

The updated version of the bill eliminates a nationwide restriction on cryogenic etch equipment produced by companies such as Lam Research and Tokyo Electron, according to Reuters, which claims it has seen the revised copy of the document (which does not appear to be available on official websites). In addition, the report claims that many of the restrictions proposed in the early April version of the bill have been removed, but does not elaborate. This provision had raised concerns across the semiconductor equipment industry due to its wide reach and potential impact on global trade.

The original draft explicitly included cryogenic etching equipment as a separate type of etching equipment requiring specific export controls. Cryogenic etching tools are designed for high-aspect-ratio, extremely smooth silicon etching, where sidewall roughness must be minimized. Such tools are used primarily in front-end semiconductor fabrication to create high-precision silicon features, such as advanced transistor structures (e.g., FinFET/GAA) and specialized MEMS. In addition, they are also used in R&D environments where ultra-smooth, high-aspect-ratio silicon etching is required.

The current U.S. export controls require an export license to ship tools used to build logic chips on 14nm/16nm-class process technologies that use FinFET transistors, so cryogenic etching tools have been covered by American export rules since 2021. The existing export controls curbed sales of advanced tools to select fabs, potentially allowing Chinese chipmakers to obtain such tools for their outdated fabs. The MATCH Act proposes to curb shipments of such equipment to actual companies (thus, plugging the loophole that allowed adversaries to circumvent existing rules), so the blanket ban on selling cryogenic etching tools to countries of concern was excessive.

Reuters reports that the latest version of the bill upholds restrictions on sales of advanced wafer fabrication equipment by U.S. and foreign companies to certain Chinese semiconductor manufacturers, including ChangXin Memory Technologies (CXMT), Yangtze Memory Technologies (YMTC), and Semiconductor Manufacturing International Corporation (SMIC). The bill also maintains requirements for licenses to service equipment at covered facilities. However, the updated version no longer applies a blanket presumption that such licenses will be denied, which should ease one of the more contentious elements for ASML and Tokyo Electron.

A bipartisan group of U.S. senators has proposed a new law that would impose an almost blanked ban on exports of advanced wafer fabrication equipment (WFE) to select entities in adversary nations, a rule that would complement the existing fab-based bans. If imposed, leading China-based chipmakers like CXMT, Hua Hong, SMIC, and YMTC would lose the ability to procure advanced tools for outdated fabs and use them to advance their leading-edge facilities.

"Certain entities, including [CXMT, Hua Hong/HLMC, Huawei, SMIC, and YMTC] are engaged in efforts to produce advanced-node integrated circuits that are especially crucial for the Military-Civil Fusion efforts of the People’s Republic of China and warrant comprehensive export controls to prevent those companies from accessing items made with [U.S.] technologies," the proposal reads.

The U.S. government restricted sales of advanced wafer fabrication equipment to potential foes like China back in late 2021. Under these restrictions American companies and eventually companies from allied nations, including the Netherlands and Japan, must obtain an export license from the U.S. government to ship WFE capable of 14nm process technologies for logic, 18nm-class DRAM fabrication processes, and 128-layer or more NAND if they ship to China-based entities. The new proposal does not introduce anything new in terms of curbs. What it does is change how shipments of tools are permitted.

Today export controls regulate shipments to exact fabs that may or may not be blacklisted by the U.S. government, not entities that own these fabs. To that end, WFE makers can ship advanced machines, such as the ASML Twinscan NXT:1950i/1980Di (which can be upgraded to the sanctioned 5nm-capable NXT:2000i) to companies like SMIC as long as the latter does not use these tools for advanced process technologies. However, controlling how these tools are used is extremely complicated as Chinese chipmakers and authorities do not really endorse such audits. Meanwhile, these advanced tools are indeed used to make chips using 7nm-class process technologies, such as SMIC's N+1 and N+2.

The newly proposed MATCH Act shifts export controls from fab-based controls to a hybrid model that is company-based (and affiliation-based), though fab-level triggers will remain in place. As a result, companies like SMIC will not be able to buy advanced tools for fabs that use trailing nodes and then redirect them to their fabs capable of 7nm-class technologies.

In addition, the MATCH Act is designed to force global alignment on semiconductor equipment export controls. At first, the U.S. will pursue coordination with allied supplier countries such as the Netherlands, Japan, South Korea, and Taiwan. If that effort fails, then the U.S. will expand restrictions extraterritorially to cover foreign-made tools that contain more than 0% of American technology, or require servicing that relies on American technologies. The end goal is to close loopholes that enable adversaries to circumvent existing controls.

An avid reader who has been following U.S. restrictions on advanced fab tools will ask whether it will be possible for restricted China-based entities to get sophisticated WFE from various intermediaries that are not restricted. As far as we can tell, while intermediary entities can in theory acquire semiconductor manufacturing equipment and divert it illegally, the MATCH Act is explicitly structured to prevent circumvention via intermediaries as export controls attach not only to the initial transaction, but also to end-use, end-user, reexport, and servicing. Therefore, routing semiconductor equipment through a third-party entity would not bypass restrictions, but will instead expose all parties involved, which essentially means losing access to advanced WFE in the future and servicing of existing tools, which in turn will render these machines useless over time.

While the bill cannot eliminate small-scale leakage of advanced systems, one-off tool diversion, or black market activity, it is designed to eliminate reliable supply chains currently used by Chinese entities to get advanced fabrication equipment to build up and maintain world-class fabs.

Last but not least, the MATCH Act introduces the 75% threshold that serves as a built-in calibration mechanism that limits controls to genuine technological chokepoints that countries of concern (i.e., China) cannot produce themselves. For example, if China can meet 75% of its demand for certain tools (e.g., etching or deposition tools), then the U.S. government no longer restricts shipments of appropriate tools to China. Under the newly proposed bill, restrictions are applied where they retain strategic leverage and can be relaxed if domestic alternatives reach sufficient scale. This seems to be important for American companies that sell etching and deposition tools. For now, they maintain lead over Chinese makers like AMEC or Naura, but the latter already offers world-class tools, so once they reach scale, American companies like Applied Materials will lose strategic positions on the Chinese market, at which point the U.S. government will cease regulating their shipments to customers in the PRC.

SK hynix disclosed in a regulatory filing on Tuesday that it will purchase 11.9 trillion won ($7.9 billion) worth of EUV lithography equipment from ASML by the end of 2027, as reported by Bloomberg. The deal is the largest single EUV order ever publicly disclosed by an ASML customer, and it runs through December 2027. SK hynix said the tools are intended for mass production of next-gen products as the company races to expand capacity for AI-driven memory demand.

Bernstein analyst David Dao estimates that the order covers approximately 30 new EUV machines over two years, slightly above his prior forecast of 26. The scanners will be deployed across two facilities: SK hynix's M15X plant in Cheongju, which is focused on producing HBM chips, and the new Yongin Semiconductor Cluster, which will handle advanced DRAM. Ryu Young-ho, a senior analyst at NH Investment & Securities, told Reuters that the equipment is expected to serve both HBM and advanced DRAM production.

SK hynix accelerated the Yongin timeline earlier this year, moving the first cleanroom opening from May to February 2027. The company committed a total of 31 trillion won ($21.5 billion) to the Yongin Phase 1 fab, which will eventually house two building shells and six cleanrooms. M15X, meanwhile, began deploying wafers in February after its first clean room opened in October of last year.

ING analyst Marc Hesselink noted in a client note that the order contains a "pull-in element" designed to lock down ASML equipment supply ahead of competitors. SK hynix is likely to increase spending on the less advanced DUV lithography machines separately, where lead times are shorter at three to six months, Hesselink added.

ASML, which announced plans to cut some 1,700 managerial roles back in January, reported a €38.8 billion order backlog at the end of 2025. Samsung and TSMC are also major buyers of EUV equipment, and all three major memory makers are expanding capacity as AI infrastructure buildout continues to strain global DRAM and HBM supply.

SK hynix currently holds more than 60% of the global HBM market and is a primary supplier to Nvidia, but Samsung is ramping its own EUV-based HBM production aggressively. SK hynix announced a separate $13 billion advanced packaging facility in Cheongju earlier this year to handle the downstream assembly of HBM chips produced at M15X.

Arena has announced its first book, which is simply called Silicon. Best known for its magazine, which celebrates American ingenuity in business, technology, and civilization, Arena’s stylish and premium “coffee table book like no other” is up for pre-order now. Silicon is priced at $99, including tax and free shipping in the U.S. and Canada. Expect it to make a five-pound impression on your doormat in May.

Silicon is described by Arena, not as a dense scientific technical work, but as “an art book and anthology.” In other words, it isn’t only for semiconductor wizards like Anton Shilov. I think it will also appeal to pea-brained folk like myself, or anyone else who appreciates the visual appeal of technology, enhanced by the book’s great presentation and print quality.

On the topic of physical quality, Arena boasts that Silicon has a “special foil stamped cover, a genuine thread binding, and 384 pages of European archival paper.” The shimmering light-diffracting cover particularly hits the coffee table segment right in the bullseye.

As an anthology, readers get 10 independent chapters to absorb. The prose is liberally punctuated with “hundreds of full-page photographs of computer chips from the last 50 years,” explains the pre-order website. So, you can dip into Silicon willy-nilly for any of the 10 self-contained segments. Might we suggest some matching bookmarks?

The first chapter is called Teaching Sand to Think and was penned by Dylan Patel & Jeff Koch. You may have seen Patel mentioned on Tom’s Hardware from time to time, due to the SemiAnalysis semiconductor industry insights and reports he often shares. Other chapters cover subjects such as Moore’s Law, ASML’s Throne, the Nvidia Factor, and more.

The animated GIF in Arena’s social media posts promoting Silicon, as well as the product page’s visual carousel, provide a decent preview of leafing through this weighty tome. Its looks like it could be an essential read to discover silicon, "the element that built modernity." Furthermore, it will provide perspective to “the world of transistors, chips, and the greatest technology revolution of all time,” reckons Arena.

Employees at ASML still don't know whether they will lose their jobs, some seven weeks after the Dutch chip equipment maker announced plans to cut 1,700 management roles alongside record full-year revenue of €32.7 billion. The cuts target management positions in ASML's technology and IT departments, with 1,400 roles going in the Netherlands and 300 in the United States, representing roughly 4% of the company's global workforce.

The prolonged uncertainty is generating internal unrest, according to an ASML spokesperson who spoke to Dutch broadcaster Omroep Brabant. "People simply don't know where they stand. ‘What does this mean for me?’ they ask," the spokesperson said. "We can't answer that question on an individual level right now. It's a very difficult situation for everyone, and it's causing unrest, and we completely understand that."

According to trade unions familiar with the matter, ASML said it hopes to finalize the terms of the reorganization by April 1, with some of the affected management employees potentially offered new engineering positions as an alternative to redundancy. "We will do everything we can to keep that number as low as possible," the spokesperson said. "But it will never be completely zero."

Both of the main unions involved have rejected the April 1 target as unworkable. FNV negotiator Peter Reniers called the timeline "unrealistic," arguing ASML should instead identify where displaced employees can be redeployed internally before pushing toward a formal agreement. "There's no need to do this abruptly now," Reniers told the broadcaster.

Meanwhile, CNV negotiator Rémy Biesmans said he doesn’t expect a deal in the next three weeks either, describing the situation as a choice between resolving things quickly at the risk of getting the terms wrong, or taking longer to reach an outcome that actually protects workers. "Our goal remains to avoid forced layoffs," he said.

Cuts and expansion plans run in tandem

The unions have also questioned the logic of the cuts despite expansion plans. Eindhoven's city council approved a zoning plan amendment on March 11 that allows ASML to begin construction of a second campus at the Brainport Industries Campus near Eindhoven Airport, a site intended to accommodate 20,000 new employees. That’s nearly double the company's current Dutch headcount of around 23,000, and the first 5,000 workers are expected to move in by early 2028.

The company reported a net profit of €9.6 billion for 2025 and has guided for revenue of €34 to €39 billion for 2026, with Q4 2025 orders alone coming in at €13.2 billion, which was more than double analyst expectations. China's share of revenue, meanwhile, is projected to fall from 33% in 2025 to around 20% in 2026 as U.S. export controls continue to restrict sales of EUV equipment to Chinese manufacturers.

ASML this week reaffirmed that it is on track to release a Twinscan NXE extreme ultraviolet lithography system that features a 1000W EUV power source and can process up to 330 wafers per hour. The system, projected for sometime in 2030 or beyond, offers 50% more power than the current best EUV tool, the NXE:3800E. Such machines will greatly increase productivity and decrease costs per wafer for chipmakers, but to make them possible, ASML has had to achieve several breakthroughs.

"What was achieved — one kilowatt — is pretty amazing," Michael Purvis, ASML's lead technologist for its EUV source light, told Reuters. "We see a reasonably clear path toward 1,500 watts, and no fundamental reason why we couldn't get to 2,000 watts."

However, to get to a 1000W-class EUV source in the 2030s, ASML must develop a new three-pulse EUV light generation method that it disclosed in late 2024. The new method involves a 1μm pre-pulse that flattens the droplets, followed by a 1μm rarefaction pre-pulse that rarefies them, after which the main 10μm CO2 laser pulse turns them into EUV plasma. Previously, ASML filed a patent application for an EUV light source producing three laser pulses, according to Asianometry. For now, this three-pulse source is not a part of any shipping machine, though expect it to end up in a Twinscan NXE:4000-series scanners due later this decade.

Yet, the actual 1000W EUV radiation source will also be equipped with a new tin droplet that will almost double the number of tin droplets to 100,000 every second. This unit is also currently under development, and it will take years before it is commercialized, according to an ASML spokesperson speaking with Tom's Hardware.

Building a new laser system that comprises of a CO2 laser with a 10μm wavelength for the main pulse and two non-CO2 lasers for with ~1μm wavelength for pre-pulses and a new tin droplet generator that doubles performance as well as a new tin droplet generator with twofold performance sounds easy on paper, both these devices as well as devices that accompany them to make their work possible represent numerous major technological breakthroughs.

Increasing the number of tin droplets automatically means increasing the amount of debris that can end up on a wafer (or rather a pellicle), so they must be promptly removed, which means an all-new debris collector. While producing 1000W of EUV radiation is hard, transferring it onto a wafer is even harder, so ASML had to invent all-new high transmission projection optics, which are meant to scale all the way to over 450 wafers per hour, or toward something like 1500W. Also, increased productivity and higher performance light sources require new wafer and reticle stages, which will also be upgraded in systems featuring a 1000W light source. Last but not least, a 1000W EUV light source also calls for new resists and pellicles, so in addition to ASML itself, the whole industry needs to prep for the arrival of the company's tools featuring its latest innovations.

ASML has long planned to increase the productivity of its EUV lithography scanners to 330 wafers per hour by around 2030, a productivity level tied to a 1000W light source. Therefore, the announcement made this week outlines the technology the company invented to achieve that roadmap goal.

ASML is yet to integrate its 1000W EUV light source into its Low-NA EUV and High-NA EUV roadmaps. The company's next-generation Low-NA Twinscan NXE:4000F litho system with a production capacity of over 250 WpH and a matched machine overlay (MMO) performance of 0.8 nm for 1.x-nm-class nodes is due in 2027, followed by the NXE:4200G with productivity of over 280 WpH in 2029. On the High-NA EUV front, ASML preps the Twinscan EXE:5200C with an over 185 WpH output and a <0.9nm MMO performance next year, followed by the EXE:5400D with productivity of over 195 wafers per hour in 2029.

A group of U.S. lawmakers this week sent a letter to the U.S. State and Commerce Departments calling to reinforce restrictions on wafer fab equipment (WFE) exported to China. The group calls to restrict the sale of virtually all chipmaking tools to China. With the exception of those that can be manufactured domestically in the People's Republic of China (PRC). In addition, the group demands the U.S. to work with allied nations and ensure that they implement similar export policies, thus banning sales of all advanced chipmaking tools to the PRC.

The group led by House Select Committee on China Chairman John Moolenaar and House Foreign Affairs Committee Chairman Brian Mast sent the letter to Secretary of State Marco Rubio and Secretary of Commerce Howard Lutnick demanding to impose more robust curbs on exports of semiconductor production tools to China and use diplomacy to make allied nations follow. Right now, American companies need an export license to ship WFE tools to China-based entities. These tools that can be used to make logic chips on 14nm/16nm manufacturing technologies, produce DRAM on 18nm-class half-pitch fabrication process, and fabricate 3D NAND with 128 or more layers. At the same time, American companies can obtain an export license and supply these very tools to entities that formally do not produce the aforementioned semiconductors. The new set of rules proposed by the group prohibit to sell any WFE to China-based entities except tools that can be manufactured locally in China.

The lawmakers argue that existing controls remain incomplete as certain foreign-produced 'chokepoint tools' (i.e., advanced lithography systems by ASML and sophisticated etching and deposition tools by Tokyo Electron) are restricted only when destined for specific Chinese entities rather than being subject to broad country-level limitations.

They note that once equipment enters China, enforcement becomes difficult because verification visits require approval from Chinese authorities, which can take weeks or months to arrange, and are conducted under supervision. As a result, Chinese companies like SMIC can continue develop their process technologies using advanced manufacturing tools, whereas various entities funded by Huawei or even the federal government can reverse engineer these machines to build similar systems locally.

Reverse engineering of existing tools and subcomponents is another point of concern raised by the lawmakers. Despite the efforts of the U.S. government, Chinese companies retain access to the subcomponents of chipmaking equipment, which not only enables them to fix existing tools, but also reverse engineer these parts. Without tighter export controls on spare parts, China could eventually replace foreign equipment with locally developed alternatives, lawmakers believe.

"We urge the Administration to press allies to implement countrywide controls on key chokepoint semiconductor manufacturing equipment and subcomponents: that is, all equipment and subcomponents that China cannot produce indigenously," the letter reads. "This engagement should include clear and reasonable deadlines, after which the United States should be prepared to act to close remaining gaps itself if necessary, including by prohibiting the use of U.S.-origin components in the production of chokepoint tools destined to China."

The letter also mentions servicing of WFE as a potential area for even tighter regulation as now these rules adhere to export control rules, which means that certain restricted advanced systems can still be serviced as long as they are installed at an approved buyer. As these systems require ongoing maintenance and technical support to remain operational, limiting servicing could be a way to reduce practical lifespan of already installed equipment.

"The window to secure America's semiconductor advantage is narrowing," the letter concludes. "We request a briefing within the next month on the Administration's strategy for securing allied cooperation on countrywide controls on chokepoint semiconductor manufacturing equipment and components and the timeline for achieving this goal. We stand ready to work with you on a bipartisan basis to ensure our export control regime and the alliances that support it are equal to this challenge."

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

Despite the massive AI infrastructure build-out and a bumper earnings call on Tuesday, ASML, the only company in the world that manufactures the tools that make the cutting-edge chips that are currently in high demand, announced that it plans to lay off some of its employees. According to the company’s announcement, it’s streamlining its Technology and IT & Data organizations, with the former moving “from a project/matrix setup to one where most of our engineers will be dedicated to a specific product and module.” This reorganization is meant to simplify processes and decision-making throughout the company.

“As a result of these proposed changes, some roles — mainly at the leadership level — may no longer be required,” ASML said in its press release. “At the same time, to retain our engineering capability, we will create new engineering jobs to strengthen existing technology projects and embark on new ones to support our own and our customers’ growth plans. While this will allow some of our impacted colleagues to move to new roles, we have to acknowledge that some will leave ASML as a result.” This isn’t just a minor trim for the two departments, too. Even though ASML still plans on creating roles in Manufacturing, Customer Support, and Sales, it expects to reduce its headcount by 1,700 positions, mostly affecting the Netherlands and the United States.

ASML has a practical monopoly on chipmaking tools, and it stands to benefit from the continuing growth of the semiconductor industry. Despite that, it seems that it wants to maintain a lean and efficient workforce, even as it’s growing its headcount and footprint with its Eindhoven expansion expected to be online by 2028. “As our FY 2025 financial results demonstrate, we are choosing to make these changes at a moment of strength for the company,” the company stated. “Improving our processes and systems will allow us to innovate more and innovate better, generating further responsible growth for ASML and our stakeholders.”

This is one of the first major announcements of layoffs in the tech industry for 2026, which has been hit with over 100,000 job cuts in just the first half of last year. Intel took the lead with the layoffs, prompted by the financial disaster that first came to light in 2024, with Microsoft and Meta following closely behind. However, these job losses aren’t caused by a contraction of the tech industry — instead, it’s driven by industry shifts, with AI and automation taking over many entry-level positions. ASML’s announcement, though, is different, with many of the affected personnel expected to be from leadership positions — mostly middle managers and up.

China has quietly introduced a rule under which chipmakers must use at least 50% domestically produced equipment when adding new semiconductor manufacturing capacity, reports Reuters. The move could potentially reshape procurement decisions, accelerate local tool adoption, and squeeze foreign suppliers out of the Chinese market.

However, there are a number of catches with this requirement: firstly, authorities grant waivers for advanced fabs; secondly, Chinese industry cannot produce enough litho systems, if the numbers via Reuters are accurate.

The rule is not published in any formal regulation, but in recent months, companies seeking government approval to build or expand fabs have been instructed to prove that at least half of their equipment spending is directed to Chinese suppliers. Applications that fail to meet the threshold are typically rejected, according to people familiar with the process. In fact, officials told applicants that 50% is a baseline rather than a target as the long-term objective is to exclusively use domestic wafer fab tools.

However, regulators allow case-by-case flexibility when domestic alternatives are constrained, which is perhaps the main catch about the rule. The requirement is applied most strictly to production lines used to make chips via mature process technologies, whereas advanced nodes receive temporary exemptions due to gaps in local tool availability, particularly when it comes to lithography equipment.

Speaking of lithography tools, state-linked chipmakers placed 421 orders for domestically produced lithography machines and their components this year at combined value of about ¥850 million ($121.3 million), according to Reuters. While the number 421 looks substantial, it includes both new systems and spare parts, which does not give an idea how many new tools were actually ordered.

To put the value into context, ASML's dry ArF tools used to produce chips on mature nodes cost around $27.9 million per unit on average (based on the company's Q4 FY2024 results), whereas KrF systems cost around $14.46 million per unit. By contrast, ASML's latest immersion DUV (ArF) lithography scanners used to make chips on advances process technologies cost $82.5 million per unit on average. With Chinese-made litho tools we do not usually talk about immersion lithography, but rather about dry ArF or KrF machines (China's best demonstrated tools are 28nm-capable, but these do not seem to be in mass production now). That said, the combined value shows that the Chinese industry can only produce rather cheap litho systems for outdated process technologies and even they are hardly made in significant quantities.

$121.3 million is approximately eight ASML KrF litho machines. Even if Chinese manufacturers have managed to cut costs of these mature tools by half (which is probably impossible), it means that they could only produce 16 of such tools in 2025. By contrast, ASML built 152 KrF steppers, 65 i-line tools, 28 ArF dry scanners, 129 ArF scanners, and 44 EUV scanners in 2024.

A report this week claimed that a covert laboratory in China had managed to reverse-engineer an extreme ultraviolet (EUV) lithography scanner, one of the most complex machines on Earth, shocking many industry observers. However, China's 'Frankenstein' EUV chipmaking tool is known to be cobbled together from many disparate parts and not fit for manufacturing of any sort. In fact, the experiment hasn't even produced a single chip.

When you have been around long enough in the tech industry, one thing that you learn is that all the breakthroughs that happen around are a result of years, if not decades, of hard work of multiple teams. Then, bringing these breakthroughs to mass production takes another five to 10 years, depending on the involvement of big companies like Intel, which are well-suited to translate scientific innovations into production as quickly as possible. Here's why China's experimental EUV machine is still many years away from producing even a single chip.

Can you steal a blueprint for an EUV tool?

The report about a reverse-engineered EUV lithography machine that produces EUV radiation using the same CO2 laser-produced plasma (LPP) method that ASML uses reminded me of a scene in Christopher Nolan's movie 'Oppenheimer', when Lewis Strauss implies that the blueprints of the American nuclear bomb were stolen based on the fact that Russians have used a plutonium implosion device, like the one built in Los Alamos.

Indeed, blueprints and detailed scientific information from the U.S. Manhattan Project were stolen by Soviet spies. But while in the case of the atomic bomb, there were actual blueprints and detailed scientific information in Los Alamos, so seven convicted Russian spies had somewhere to steal from, there is no single detailed blueprint of an EUV scanner, according to a source with knowledge of the matter.

This may be correct, as the current Twinscan NXE platform is a product developed worldwide by a constellation of partners. While there is no doubt that China has a widespread spy network, stealing blueprints from multiple ASML facilities worldwide is difficult. What's even more challenging is stealing blueprints of parts from thousands of ASML suppliers worldwide, then assembling a functioning EUV lithography tool.

To add some context, Cymer — the inventor of ASML’s EUV LPP-based light source — is an American company (subject to all imaginable export controls) that ASML acquired in 2012. Cymer is now an internal part of the ASML supply chain. It provides the complete EUV light-generation subsystem, including the LPP source (which generates 13.5-nm radiation), a high-performance CO2 laser system, tin-droplet generation with a targeting unit, a debris-mitigation unit, and the EUV radiation collector. The hardware itself is precious, but so are the associated proprietary firmware, control software, and diagnostic tools required to continuously deliver stable, high-performance EUV radiation to the scanner for high-volume manufacturing (HVM).

Even then, Cymer's EUV source relies on a high-end ultra-precise mirror, coated with multilayer molybdenum-silicon (Mo/Si) stacks developed and made by Carl Zeiss in Germany. Since EUV radiation can be absorbed by almost anything, it also requires specialized mirrors from Carl Zeiss.

Without illuminator optics (which shape and uniform the beam using faceted mirrors) and projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors), the EUV source itself is useless in isolation. Even if one can steal blueprints of Carl Zeiss optics, replicating them is hard, if not impossible, because it requires utmost precision, and for now, Carl Zeiss is the only company in the world that can produce such precise optics hardware.

Can you steal an entire high-tech supply chain?

Beyond optics, ASML relies on thousands of suppliers across the United States, Japan, and Europe to deliver critical subsystems, which it then integrates into a single machine.

In the U.S., ASML’s Cymer division develops the laser-produced plasma light source, as mentioned above. Japanese companies supply ultra-precision mechanical components, sensors, and materials, including EUV photoresists, while European firms provide vacuum systems, precision structures, and specialty materials. Each supplier owns proprietary process technology that ASML itself does not fully control, which highlights that EUV lithography is ultimately sustained not by one company, but by an ecosystem whose collective intellectual property and integration experience form one of the deepest and most crucial technological chains in the semiconductor industry.

ASML's key ability is to orchestrate this ecosystem and integrate tens of thousands of externally developed parts with its own hardware and software into a machine that operates at nanometer-scale tolerances in high-volume manufacturing. Therefore, replicating an EUV lithography tool requires far more than copying a scanner's design (which is impossible as there is no single blueprint of an EUV machine and the company does its best to keep knowledge of its engineers the unit compartmentalized): it demands recreating an entire global supplier network, the co-development culture that binds it together through groups such as imec (which no longer works with Chinese clients), and the decades of trial-and-error that transformed fragile subsystems into a tool that is widely used for high-volume chipmaking.

Can you even DIY a lithography tool?

Considering the versatility of ASML's scanner design, as well as its omnipresence throughout the industry, there are numerous loopholes in obtaining certain parts of the machinery. Banks or chipmakers usually auction off older lithography equipment, and spare parts for advanced tools can be found on open markets (even eBay yields results for spares).

There is an additional rumor claiming that China intercepted a Cymer EUV radiation source while it was in transit, recorded the part numbers, then obtained them from various sellers or acquired refurbished scrap parts, and assembled a machine in a covert lab. Because not all parts can be acquired on the open market and their condition is unknown, this Frankenstein EUV tool does not work, according to Reuters.

Yet, because ASML's tools are designed to be easily serviced or upgraded in the field and spares appear readily available, Chinese chipmakers — such as SMIC — have managed to upgrade some of their existing tools using components obtained from third parties. For example, they have obtained stage and overlay performance data for the Twinscan NXT DUV lithography tools to make them more suitable for producing chips at advanced nodes, such as 7nm-class process technologies. It goes without saying that such Frankensteined upgrades and tools may not meet all of ASML's stringent standards for quality and reliability. If they increase SMIC's output of advanced wafers by 10%, such modifications may be worth the risk.

The modular nature of ASML's Twiscan platforms simplifies production and upgrade processes. Still, it also means that many of those components can be purchased by unauthorized buyers, such as China-based chipmakers sanctioned by American and European governments. In theory, this means that a Chinese chipmaker could DIY their advanced lithography tools from ASML using components available openly or refurbished in-house, which would, of course, take an incredible amount of time and effort, but would still get them the necessary hardware. However, even obtaining the hardware itself does not guarantee that it functions as intended, as ASML's tools are controlled by proprietary software and firmware that are not publicly available. As a result, even if Chinese specialists obtain the hardware, they will not be able to fully reverse-engineer it to meet ASML's standards.

All in all, it is not surprising that while Chinese scientists have managed to lay their hands on some of the components of ASML's EUV scanner, they have struggled to replicate the tool itself, as they lack a supply chain to produce high-tech parts. They also lack software and firmware that control these components, and therefore, a deep understanding of how they function when working in concert.

IMEC has successfully demonstrated the full wafer-scale fabrication of nanopores using ASML’s state-of-the-art extreme ultraviolet (EUV) machines. Described by ASML’s Product Communications Manager as an “unexpectedly awesome biomedical application” of his firm's machinery, this could be an important advance due to the molecular sensing possibilities nanopores open up.

The qualities of nanopores are of great interest in biomedicine. As you might have determined from the etymology, nanopores are essentially tiny holes, just a few nanometers wide. In more relatable language, perhaps, these pores have diameters that make them roughly 10,000 times finer than a human hair.

What is the use of such tiny perforations?

Nanopores can be used by biomedical sensors due to the way molecules interact with them. The science behind their use in detection is:

• An ionic current flowing through the nanopores is measured,
• As molecules pass through, they create modulations giving away their size, structure, charge, and interactions,
• Different molecules can thus be detected from their distinct electrical signatures, with high sensitivity.

In this way, these EUV fabricated nanopores can act like molecular checkpoints for biomedical sensing. They can detect and determine individual molecules like a virus, protein, or DNA etc. That’s a great feature for accurate molecule identification and analysis. Furthermore, adjusting the solid state nanopore size can also be useful for filtration and molecular data storage applications, indicates IMEC.

Why use EUV machinery?

Current nanopore production methods are claimed to be slow, limited to the lab, and expensive. IMEC’s paper describes how it successfully fabricated “highly uniform nanopores with diameters down to ~10nm across full 300mm wafers.” This breakthrough – encompassing mass production, precision, and reproducibility - should put an end to the delays in adoption of nanopore-based sensors.

While we applaud the research, and the idea of making precision nanopores more accessible to medical equipment makers, we also understand that ASML EUV equipment isn’t that easy to acquire. Such is the demand for this high-tech machinery by the booming semiconductor industry, we hope there remains some chance for biomedical production runs like nanopore production.

However, we are slightly reassured by the researchers highlighting that this is a step towards “cost-effective (mass) production,” as surely they will have assessed the costs of getting a 300mm wafer full of nanopores produced at this time.

Edit 12/22/2025 4:15am PT: Corrected ASML employee's title.

A secret laboratory in China has quietly assembled a prototype extreme ultraviolet (EUV) lithography system and is now testing it stealthily, which means that the country may be close to replicating the most advanced technology that currently exists on Earth, reports Reuters.

The tool was reportedly developed by reverse engineering existing scanners from ASML and is said to be on-track to make prototype chips in 2028. If the information is correct, then Chinese scientists have made numerous breakthroughs across multiple disciplines in just a few years instead of decades, a scenario that appears extremely unlikely. Further analysis of the report indicates that China's laboratory is far from completing the tool, meaning that the country is years away from making chips using EUV lithography.

China's alleged EUV scanner

The system was reportedly completed in early 2025 inside a highly secured facility in Shenzhen and occupies nearly an entire factory floor. The Chinese machine reportedly generates EUV light with a wavelength of 13.5nm using the same laser-produced plasma (LPP) method as ASML Twinscan NXE machines, not the particle accelerator-based steady-state microbunching (SSMB) method designed at Tsinghua University or discharge-produced plasma (DPP) technology developed at Harbin Institute of Technology (HIT), which might prove the point that the system was reverse-engineered or at least contains a substantial amount of technologies pioneered by ASML.

ASML's laser-produced plasma (LPP) method uses tiny molten tin droplets, roughly 25–30 microns in diameter, which are injected into a vacuum chamber at a rate of about 50,000 droplets per second. Then, a high-power CO₂ laser first fires a low-intensity pre-pulse at each droplet, flattening it into a disk-like shape, followed by a more powerful main pulse that vaporizes the flattened tin and creates a superheated plasma with temperatures exceeding 200,000°C. This plasma emits isotropic EUV light, which is then collected by a large multilayer collector mirror and directed into the lithography system's reflective optics for patterning silicon wafers. This process repeats tens of thousands of times per second.

The machine is reportedly larger than the original, but it is operational in the sense that it can generate EUV radiation. However, it has not progressed to make usable chips as it still struggles to replicate 'the precision optical systems' features by Twinscan NXE systems. Furthermore, there is no word about power of the EUV light source, a crucial parameter that defines whether a tool can or cannot be used for volume production.

Not operational, for now

The report clearly states that the Chinese EUV scanner cannot currently be used to make chips, but the Chinese government reportedly wants the first chip prototypes to emerge in 2028, two or three years down the road. However, a more realistic target is 2030, four or five years from now, which is a long time. Meanwhile, from the report, it is not completely clear what stage the Chinese team is at today.

The report does not disclose which specific components of the optical system are the primary bottlenecks, as the article groups them rather generally. In particular, it is uncertain if the alleged EUV tool struggles to replicate the ultra-precise collector mirror system coated with multilayer molybdenum-silicon (Mo/Si) stacks, illuminator optics (which shapes and uniforms the beam using faceted mirrors), or projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors). ASML outsources the development and production of these components to Carl Zeiss from Germany. If the developers failed to replicate the collector itself, then the rest of the machine can hardly be called an EUV lithography system, as technically, the only thing they have is some kind of light source that they have yet to learn how to use. Yet, even if the developers cannot replicate illuminator optics or projection optics (suggesting that the collector itself is there), it still means they do not have even a poorly working EUV lithography tool, but rather a set of certain components.

When talking about advanced lithography equipment, we must keep in mind that such tools rely on seamless integration of sophisticated light sources, advanced optics, ultra-precise mechanical engineering, complex control software, and specialized materials, all of which must function reliably within nanometer-scale tolerances demanded by modern chip manufacturing. The story has no word about the state of the mechanical systems of the alleged tool: we know nothing about the wafer stocker system, wafer stages, or reticle stages, all of which are crucial for operation and yields.

To put China's EUV efforts into perspective, the secret lab is not even close to building an alpha tool. For now, what the Chinese lab has cannot even put the light on a wafer, save for printing lines and spaces, something ASML's tool could do in 2006, about 11 years before the company shipped its first Twinscan NXE:3400B system meant for high-volume manufacturing. Of course, reverse engineering certain components can give Chinese engineers a speed boost, but it remains to be seen how significant this one is going to be.

Reverse engineering an ASML Twinscan NXE?

According to Reuters's sources familiar with the effort, the Chinese EUV tool was 'developed' by a team that includes former engineers from ASML and recent university graduates, who allegedly reverse-engineered the company's EUV machines. The secret lab was so stealthy that its employees were given fake IDs to avoid detection of their concentration in one place by foreign spies.

Yet, it is unclear how any engineers from China could reverse engineer an EUV lithography scanner, as the Dutch company has never supplied one to China and hardly taught personnel from China how to service its EUV systems that are not allowed to be shipped to the People's Republic.

Reverse engineering a machine that contains over 100,000 parts is a hard task that takes hundreds of engineers with knowledge of the matter, which is why the secret entity led by the Government of China hired not only former engineers from ASML China, but also former employees of the Dutch company from elsewhere, presumably from Europe, Taiwan, and the U.S. For example, Lin Nan, formerly responsible for EUV light source technology at ASML, now leads a team at the Chinese Academy of Sciences’ Shanghai Institute of Optics that has filed eight EUV-related patents in just 18 months. Yet, this may mean that he uses his experience and knowledge rather than trying to replicate what he did at ASML or reverse engineer what he did at ASML due to the absence of an EUV scanner in his lab.

“It makes sense that companies would want to replicate our technology, but doing so is no small feat,” a statement by ASML published by Reuters reads.

The report says that around 100 recent university graduates are tasked with reverse-engineering parts from EUV and DUV lithography tools, with each workplace monitored by a dedicated camera that records the disassembly and reassembly process, an important part of the whole China's lithography program, according to the report. Employees who successfully put components back together receive bonuses. Yet again, a Twinscan NXE tool is a mechanism consisting of over 100,000 parts working together, not just a sum of all parts.

To sum up, China has reportedly built a secret prototype EUV lithography system and begun testing it, which suggests that the country may be closer to reproducing the most advanced chipmaking technology in existence than previously believed. However, details provided by the report indicate that China is still years — if not a decade — away from making chips using EUV lithography.

The machine can generate 13.5-nm EUV light using the same laser-produced plasma (LPP) method employed by ASML, which may demonstrate extensive reverse engineering of Western technology rather than the use of alternative domestic approaches. However, the tool is significantly larger than commercial systems available today, it cannot produce usable chips, and appears to struggle with other elements of EUV lithography, particularly ultra-precise optics supplied to ASML by Carl Zeiss. In fact, details about the system like light source power, optical subsystem maturity, and the state of critical mechanical components remain unclear.

While China expects first prototype EUV chips to emerge in 2028, Reuters's sources suggest 2030 is more realistic. Yet, the whole effort relies heavily on recruiting former ASML engineers and reverse engineering parts from existing EUV and DUV tools, which are not only hard to develop, but are extremely hard to make. Meanwhile, there is no word whether the current team responsible for disassembling and reassembling components can actually make an ultra-complex machine consisting of over 100,000 parts work flawlessly to produce semiconductors in high volumes.

Intel announced that it had installed ASML's Twinscan EXE:5200B, the industry's first High-NA lithography tool with 0.55 numerical aperture projection optics made for commercial chip production. The tool has passed acceptance testing and will be used for development of Intel's 14A fabrication process, which will be the world's first node to rely on High-NA EUV scanners for its most critical layers. The achievement indicates that High-NA EUV lithography is moving beyond early experimentation toward high-volume manufacturing (HVM).

ASML's Twinscan EXE:5200B builds on the 1st Generation EXE:5000 platform that Intel received in 2023 for its Oregon R&D fab. The new tool can 'print' chips with an 8nm resolution, enabling scaling beyond which is currently possible with Low-NA EUV tools that offer a 13nm resolution without using multi-patterning. Unlike the EXE:5000, the EXE:5200B is capable of processing 175 wafers per hour at a 50 mJ/cm² dose (up from 185 wafers per hour at at a 20 mJ/cm² dose) and achieves overlay accuracy of 0.7 nanometers, a critical parameter as feature dimensions continue to shrink.

To boost performance, the scanner integrates a higher-power EUV light source to enable faster wafer exposures at a 50 mJ/cm² dose. This in turn supports workable resist/process windows with strong image contrast while minimizing line-edge roughness (LER) and line-width roughness (LWR), which tend to be challenging with modern production nodes.

ASML and Intel did not limit their work to the optics and light source. They also reworked the wafer stocker system, which is responsible for how wafers are stored, queued, and moved in and out of the scanner. For next-generation tools, this component of the system has a direct impact on both productivity and patterning accuracy.

The updated stocker design improves lot flow and wafer handling to make sure that wafers arrive at the exposure stage in a more predictable state. At the same time, it provides tighter thermal control, keeping wafers and carriers at stable temperatures before and after exposure, an important factor as even tiny temperature variations can cause wafer expansion or contraction, leading to overlay errors, which in turn leads to an increase in defects and decrease of yields.

In addition, by reducing thermal and mechanical variation, the new architecture helps to minimize drift over long runs, thus enabling the scanner to maintain stable behavior and reducing the necessity for frequent recalibration. This stability will be particularly important for multi-pass and multi-exposure patterning, which will be inevitably used in the coming years for sub-1nm process technologies.

One of EXE:5200B's parameters that is hard to overestimate is its overlay performance of 0.7 nm, which was achieved by advancements of stage control, sensor calibration, and environmental isolation. Overlay performance is crucially important for next-generation process technologies as even tiny alignment errors can translate into yield losses.

It is necessary to note that ASML's Twinscan EXE:5200B is not just another EUV scanner in Intel's fab, but rather a foundation that is expected to enable Intel to regain its leadership in the semiconductor industry.

To use the new lithography tool, Intel is conducting parallel work on masks, etch processes, resolution enhancement techniques, and metrology that must be co-optimized to extract the maximum value from High-NA EUV patterning.

Intel says that its High-NA tools will enable more flexible design rules, reduce the number of patterning steps, lower mask counts, shorter cycle time, and increased yields thanks to lack of multipatterning with 14A and more advanced process technologies. Meanwhile, as Intel learns how to use High-NA EUV tools and gains valuable HVM experience, it will be able to insert High-NA EUV multi-patterning when it needs to in the sub-1nm era without significant effect on yields.

Dutch company ASML — famously the sole producer of the latest photolithography machines for fabricating cutting-edge chips — is under fire for selling hardware to a Chinese defense firm with ties to the ruling party.

Although ASML claims that the technology it sold to Chinese chip manufacturers was old and not able to "produce state-of-the-art chips," as reported by Nos,analysts have still raised concerns over its dealings with a firm developing quantum technologies, which could have implications for military technology development and deployment.

The Dutch government has long been aware of the risks posed by China's access to chip design software and manufacturing hardware. That's partly why there's been such fallout recently around Chinese involvement with Dutch chip firm, Nexperia. But Dutch firm ASML may have had far greater dealings with Chinese businesses, and it's raising more than a few red flags.

Nos claims that the business that purchased the ASML chip manufacturing component was a division of China Electronics Technology Group Corporation (CETC), a Chinese state-owned company that is a key component in the country's military industrial complex, producing key equipment for rocket systems and drones. It has also reportedly worked on the Chinese space program and fabricates chips for military use.

Nos has also accused ASML of supplying a deep lithography system (DUV) in its entirety to the Shenzhen International Quantum Academy. This is arguably more notable, as the Dutch Military Intelligence and Security Service has explicitly warned against China's development of quantum technologies.

Although ASML's DUV machines are older designs that produce chips in resolutions of around 38nm (the latest dual-stage extreme ultraviolet (EUV) systems can manage 8nm), analysts are still concerned about the direct provision of such systems, considering the concerns over Chinese technological development.

ASML has said it won't comment directly on sales to customers, but has suggested that what it has transferred to China is not cutting-edge, describing it as "old technology that can't be used to produce state-of-the-art chips." It added: "It is impossible for suppliers, such as ASML, to assess if a chip manufacturer in China should, or should not, be subject to export controls. National security is the responsibility of governments."

Indeed, it highlights that the designs it has sold to Chinese companies are not subject to export controls. This was confirmed when Nos spoke to the Dutch Ministry of Foreign Affairs.

"Not all high-tech goods are, by definition, sensitive and subject to authorization under the export controls policy," it said in a statement. "This is also the case for parts of lithography machines. Lithography machines contain a great deal of parts, technology, and software. All those parts are needed for a machine to work, but not all parts play a crucial/strategic role."

That said, Nos claims to have spoken to industry experts who suggest the parts sold to Chinese companies were, in fact, essential for the operation of certain fabrication machinery and should be considered for export controls.

"The problem is that the Dutch government does not have any control over this export of parts", says Judith Huismans, China expert for RAND Europa and former head researcher for Datenna. She suggested governments should consider export controls for parts, too: "That way, you are not saying that ASML can no longer export anything to China, but it will give the government more control and tools."

According to a new report, ASML reportedly offered to provide the United States with information about its Chinese customers. The offer came after it was caught selling more machines that went against an agreement stopping the sales of extreme ultraviolet light (EUV) and deep ultraviolet light (DUV) lithography machines to China.

According to NL Times, the Netherlands and the U.S. agreed in January 2023 that the former would stop selling and exporting its DUV lithography machines (with EUV machines already banned) to the U.S. rival starting in September 2023, with the ban taking full effect by January 2024. In the meantime, there was a gentleman’s agreement between the two nations that ASML would only ship a limited number of DUV machines that it was contractually obligated to deliver, and stop further sales of these devices.

However, the book De belangrijkste machine ter wereld, which translates to “The most important machine in the world” [machine translation] and was written by former Bloomberg journalists Diederik Baazil and Cagan Koc, says that ASML CEO Peter Wennink allegedly sold more machines than agreed in the intervening period, breaking the pact between the two nations. Former Dutch Prime Minister Mark Rutte told Wennink that his company “was venturing into dangerous territory” and that the Netherlands government felt misled and humiliated. He also said that Washington demanded they regain its trust, and that it was in the company’s best interest to do so.

Aside from restricting the sale of its equipment, the U.S. also sought to block ASML from servicing machines already deployed in China. However, instead of an outright ban, the ASML CEO suggested that the company be allowed to continue its services to its Chinese clients while also making its engineers report on the developments within these companies.

ASML’s employees have unique opportunities because its people have regular access to China’s fabs and also frequently work with Chinese engineers, allowing them to have unique insight into what’s actually going on behind the scenes. “ASML could be Washington’s eyes and ears in China,” the book said, quoting a senior U.S. government official. Of course, ASML denied making this offer, with its spokesperson telling NL Times that it was an inaccurate portrayal from the two authors.

Many are often wary of governments, whether it be Eastern or Western, taking advantage of and coercing companies into revealing data and information about their customers. But, if this account is true, this is the other way around and could prove damaging to ASML. After all, even though the company produces some of the most advanced lithography machines in the world, it must still maintain a reputation that it can be trusted — otherwise, its customers might be forced to look for alternatives because of the fear that their secrets will be revealed, whether to public entities or private institutions. Besides, any company offering customer data to anyone, even a state, is likely breaking several data privacy laws and is also betraying public trust.

This is likely one of the reasons why the U.S. government is wary of the dominance of Chinese companies within its borders. Beijing passed its National Intelligence Law in 2017, which requires all institutions and individuals to cooperate with Chinese intelligence agencies. Although there are other reasons, this law is probably one factor that Washington considered leading to the 2019 Huawei ban, with other giants like drone-maker DJI and networking hardware manufacturer TP-Link also facing potential sanctions.

Lowering defect densities and increasing yields are the key challenges for chipmakers and chip designers who use hundreds of methods for both tasks. This is because semiconductor fabrication technologies involve thousands of steps, and each can affect defect rates and yields. A recent discovery by researchers at Chinese universities has revealed how resists behave during development and how the post-exposure bake (PEB) step can reduce defect density by up to 99% in some cases, according to a paper published in Nature. However, despite these bold claims, the study has dubious practical use.

Researchers from Peking University and Tsinghua University have managed to visualize how photoresist molecules dissolve, migrate, and entangle within developer liquid during the pattern-forming (development) step. To do so, the team used cryogenic electron tomography (cryo-ET) to reconstruct the true 3D structure of photoresist polymers in their hydrated state at sub-5nm resolution.

The study revealed that most photoresist molecules accumulate in clusters at the gas–liquid interface rather than being evenly distributed in solution, which generates defects. The scientists claim that a slight increase in post-exposure bake (PEB) temperature — from 95°C to 105°C in their case — and maintaining a continuous developer layer prevented these clusters, cutting defect density on 300mm wafers by over 99% using existing resists and DUV equipment.

However, it is worth noting that chipmakers carefully select PEB temperatures for each process technology to achieve the best possible results, which limits the practical implications of the research.

To make it easier to understand what was discovered, here's a sequence of steps within a lithography step.

1. Coating: The wafer is spin-coated with photoresist.
2. Exposure: Ultraviolet (UV) or Extreme Ultraviolet (EUV) light passes through a mask to selectively expose regions of the resist.
3. Post-Exposure Bake (PEB): The exposed resist is gently heated to activate the acid-catalyzed chemical reactions that change solubility.
4. Development: The wafer is rinsed with a developer solution (often TMAH in water for DUV), which dissolves the exposed or unexposed parts of the resist, depending on the resist type, to create a thin liquid film of developer and form the patterns. This step was the focus of the research.
5. Rinse and Dry: The remaining pattern is cleaned and dried for subsequent processing.

The study in the development phase discovered that these photoresist molecules form weak, reversible entanglements that lead to microscopic clusters, which turn out to be the hidden source of pattern defects seen on processed semiconductor wafers.

A hidden process

In immersion and EUV lithography, the developer's liquid film dissolves light-exposed regions of the resist, transferring the pattern to the wafer. While the process is well known across the industry, until now there was no clear understanding of the microscopic behavior of chemically amplified resists (CARs) during pattern development, as existing methods such as scanning electron microscopy (SEM) could only observe dried residues or indirect effects. As a result, process engineers usually rely on trial-and-error tuning of resist chemistry and developer composition, since nobody has observed the real-time behavior of photoresists during development.

Instead of using SEM or atomic-force microscopy, the researchers used a cryo-electron tomography tool — usually used in structural biology to study cells, protein complexes, or viruses in frozen states — to visualize the behavior of photoresists inside a developer liquid at nanometer resolution. To do so, they had to go to great lengths in sample preparation, vitrification speed (the cooling rate at which a liquid changes state without crystallizing), and electron-beam control.

For their research, the scientists used a poly(methacrylate)-based CAR, which is widely used in 193nm immersion and 13.5nm EUV lithography.

An observation

Cryo-ET imaging revealed that the CAR polymers — frozen in their natural liquid state — were preserved as flexible, thread-like chains with random coiled shapes. Analysis of the polymer density revealed that the concentration decreased sharply with depth: in 25nm– 100 nm-thick films, about 80% of the polymer mass accumulated near the gas–liquid interface. Hence, contrary to long-standing assumptions, the resist polymers were not evenly dispersed in the developer but were concentrated at the film surface, where they later formed clusters that caused pattern defects. The same pattern was observed with other resists (e.g., designed for 248nm and 365nm exposures) demonstrated the same pattern, but this was never a problem until recently. Control samples with only the developer showed no surface signal, confirming that the effect came from the polymers themselves.

Further 3D reconstructions (combination of hundreds of low-dose electron images taken at different tilt angles) showed that inside the film, 12nm-long polymer chains stayed mostly separate, while near the surface they gathered into 30 – 40nm clusters, dimensions well above the sizes of killer defects in modern technologies.

However, these clusters are reversible by heat and are not observed in real life. In fact, killer defects in modern nodes are an order of magnitude smaller, which implies that the clusters of CAR molecules are already mitigated by leading chipmakers in their cutting-edge nodes.

Furthermore, while increasing post-exposure bake (PEB) temperature from 95°C to 105°C disrupts the cohesive interactions and helps to get rid of some defects with certain manufacturing technologies, this is an absolute yield killer for modern fabrication processes that rely on EUV lithography.

Good for DUV, catastrophic for EUV

In Deep Ultraviolet (DUV, 193nm immersion) lithography, a PEB at around 105°C is well within the normal operating range for CARs based on poly(methacrylate). These resists form features roughly 20 nm – 40 nm wide, and their photoacid diffusion lengths (about 10 nm – 20 nm) remain small enough relative to those features to preserve resolution. At 105°C, the additional thermal energy slightly increases polymer mobility and acid diffusion, enabling more complete chemical reaction and smoother dissolution during development, which helps reduce residues and improve pattern uniformity, thus reducing defects and maintaining yields. However, in some cases a a PEB at around 105°C increases line-edge roughness (LER) and line-width roughness (LWR), which leads to degradation of critical dimension uniformity (CDU), which means that it should not be used for critical layers.

However, in EUV (13.5 nm) lithography, the situation is completely different. EUV resists are typically baked at 80°C–95°C to carefully balance acid mobility and reaction completion, maintaining critical-dimension control. EUV CARs must define features as small as 13nm, so even a few nanometers of acid spread can destroy pattern fidelity. Raising the PEB temperature to 105°C would greatly accelerate acid diffusion, broaden the reaction zone, and significantly increase LER/LWR, thereby blurring the fine features defined by the EUV exposure and potentially creating defects. It also increases stochastic variation by over-reacting CAR polymer chains unevenly, which leads to other defects.

The lowdown

While the study offers valuable microscopic insight into how photoresist polymers behave in developer films, its practical impact on semiconductor manufacturing is limited, to put things mildly. Increasing the PEB to 105°C is already within the normal safe range for DUV lithography and therefore not a breakthrough, which is why we do not see 30nm–40nm defects with modern DUV-based nodes. Meanwhile, the same temperature adjustment is unsuitable for EUV processes, as such temperatures can severely degrade resolution and yield.

As a result, the work is scientifically impressive, as it confirms mechanisms that chipmakers have long managed empirically. However, it offers no new solutions applicable to advanced nodes. Then again, if scientists from Intel, Samsung, or TSMC use cryo-ET as well, they might come up with something that leads to an actual breakthrough.

This free-to-access article was made possible by Tom's Hardware Premium, where you can find in-depth news analysis, features, and access to Bench. Subscribe now from just $7 per month for a limited time.

American startup Substrate is developing a new X-ray lithography (XRL) system, powered by a particle accelerator-based light source, that promises superior performance and cost efficiency compared to standard EUV lithography, aiming to achieve resolutions equivalent to ASML's 2nm-class processes. The firm also claims it can advance beyond that. Substrate also claims that its efforts will be cheaper to produce than the competition's and will offer finer resolutions before 2030, as the company detailed on its website.

However, the tool that Substrate is developing does not appear to be compatible with existing equipment and production flows, so the company will have to reinvent the whole supply chain to be successful. However, Substrate does not plan to sell its tool, but to build its own fab and provide foundry services.

Expensive tools = expensive chips

As integrated circuit features are getting smaller, chipmakers are using increasingly intricate lithography tools that now cost around $235 million for an ASML NXE:3800E Low-NA EUV scanner or around $380 million for an ASML EXE:5200B High-NA EUV scanner. As a result, fabs are becoming increasingly expensive to build, and chips are becoming more expensive to produce.

Substrate models that a leading-edge fab will cost around $50 billion by 2030, leaving semiconductor production to a handful of companies with very deep pockets. Furthermore, such fab expenditures are expected to increase the cost of a 300-mm wafer, which it claims could balloon to $100,000 when using leading-edge fabrication processes. This will make the development and production of advanced chips prohibitively expensive for small companies. Substrate intends to change that and reduce wafer pricing to just $10,000 by 2030.

"At Substrate, we have a pathway to reduce the cost of leading-edge silicon by an order of magnitude compared to the current cost-scaling path we are on," a statement by the company reads. "By the end of the decade, Substrate will produce wafers closer to $10,000, not $100,000."

Note that Substrate is by no means the only company exploring particle accelerators as light sources for EUV or beyond-EUV lithography. In the U.S. alone, two companies — Inversion Semiconductor and xLight — as well as researchers at Johns Hopkins University, have revealed that they are working on lithography systems harnessing particle accelerators over the past 12 months. Chinese scientists and Japanese researchers are also testing particle accelerators for semiconductor production.

Substrate's X-ray lithography

Substrate is developing a new type of lithography system that uses a particle accelerator to produce short-wavelength X-ray radiation (or light) for chipmaking. The goal is to replace ASML's expensive EUV lithography scanners with compact, low-cost machines capable of printing transistor patterns at a 2nm-class process technology (or even more advanced, the company claims). The firm claims the machine should reduce chip production costs by 10 times by the end of the decade.

At the core of Substrate’s technology is a custom particle accelerator which propels electrons (produced by an unknown emitter) to near the speed of light using radio-frequency cavities. As these electrons pass through sporadic magnetic fields, they gain kinetic energy, accelerating to speeds very close to the speed of light (a relativistic speed), which allows them to produce special types of light when manipulated. These fast-moving electrons fly through a series of magnets that flip back and forth, wiggling the electrons and causing them to release their energy and produce coherent bursts of intense X-ray light (or radiation).

That light is 'billions of times brighter than the sun,' likely producing pulses intense enough to achieve the desired resolution and dose. The X-ray pulses are then focused by 'a succession of perfectly polished optics' to project a photomask onto a photoresist-coated silicon wafer. Note that Substrate never mentions reticle and resist in its official description, only claiming that 'bright pulses of light' are collimated and transported 'all the way to the silicon wafer,' which implies maskless direct-write lithography, which is good enough for research purposes, but orders of magnitude too slow for the mass production of chips. However, this remains speculation on our part.

In fact, Substrate's description of its technologies is very brief and lacks detail (perhaps for competitive reasons), making it difficult to analyze. However, since the company mentions X-ray, we are dealing with electromagnetic radiation with wavelengths ranging from 0.01nm to 10nm and energies from about 100 eV to 100 keV. The shorter the wavelength, the finer the structure that can the printed with improved accuracy, but the harder the light is to manage and work with.

Given Substrate's achievements so far, we are likely dealing with soft X-rays (wavelengths of 1-10 nm, lower energy) rather than hard X-rays (wavelengths of 0.1-1nm, higher energy).

Since short-wavelength light (including EUV and X-rays) is strongly absorbed by most materials, managing it requires a set of perfectly polished mirrors that reflect light at grazing angles (to avoid absorption), ultra-precise alignment, and vacuum environments. Also, X-ray lithography requires all-new resists that can handle high-energy photons without damage or blur.

Achievements so far

2nm-like CD and T2P spacing

To prove that its XRL method works, Substrate has shown off images of a random logic contact array with 12nm critical dimensions (CD) and 13nm tip-to-tip (T2T) spacing printed with high pattern fidelity, as well as random vias with a 30nm center-to-center pitch, possessing superb pattern quality and critical dimension uniformity. If such metrics could be achieved for mass production today, this would largely revolutionize the lithography industry, as it would enable scaling across both axis at 2nm-class nodes (and lower) without using multi-patterning.

Modern EUV scanners with 0.33 NA optics can achieve critical dimensions of 13nm–16nm in high-volume manufacturing, which is sufficient to print a 26nm minimum metal pitch (good enough for 2nm or 3nm-class process technologies) and a 25nm T2T interconnect space with a single exposure.

Such disproportions emerge because chipmakers tend to optimize resolution in the Y direction (CD) to get the tightest metal-pitch line-space pattern, but at the cost of resolution in the X direction, which means that T2T prints poorly or inconsistently, leading to bridging defects, stochastic defects, yield loss, complicated design rules, and slower scaling. To mitigate this and avoid blurred or inconsistent line ends at tip-to-tip spacing, Intel applies pattern-shaping tools in the X-direction with its 18A fabrication technology, but this complicates the overall production flow and does not fundamentally solve the issue.

Substrate's tool (assuming these are real lab results, not a simulation) can already outperform existing Low-NA EUV scanners in terms of achievable CDs with single-resolution patterning, and it leaves them behind dramatically when it comes to T2T spacing printed with high fidelity. This means that Substrate's X-ray lithography tool could possibly replace costly EUV multi-patterning used for sophisticated 3nm and 2nm-class process technologies or pattern shaping used for Intel 18A.

Our friends at SemiAnalysis have managed to get more performance claims from Substrate, which look even more impressive. The company claims it has achieved overlay accuracy of under 1.6nm, full wafer critical-dimension uniformity (CDU) of 0.25 nm, line edge roughness (LER) of under 1nm, and local critical dimension uniformity (LCDU) below 1.5 nm.

If accurate, this performance would match or surpass ASML's Twinscan NXE:3800E in uniformity, though its overlay precision is slightly worse than the 0.9nm machine-matched overlay standard in the latest EUV scanners. Also, the line-width uniformity of contacts on an image provided by Substrate is rather poor.

Assuming the results presented by Substrate are real and achieved in a lab environment, this means the company has solved three critical challenges with X-ray lithography. First, build a light source featuring an electron gun and a particle accelerator; second, create a grazing-incidence mirror system to reflect and focus X-rays at very shallow angles; and make the whole thing compact enough to fit into a lab.

Future challenges

However, Substrate still has a lot of work to do, turning its X-ray lithography technology from a lab success into a viable production tool. Substrate must prove that its X-ray lithography system can maintain beam stability, optical precision, resist compatibility, overlay accuracy, and commercial throughput simultaneously, something no X-ray platform has ever achieved.

Existing photoresists are incompatible with X-ray radiation, as they are optimized for EUV radiation with considerably lower photon energy. So, Substrate will have to invent a proper resist and then produce it at volume. The company will also have to develop photomasks that can sustain X-ray radiation. Grazing-incidence mirrors for X-rays are also not in mass production, and it is unknown whether they can be mass-produced cheaply and reliably by existing producers like Zeiss.

Substrate will also have to ensure that X-rays do not damage the underlying transistors or introduce stochastic defects. Achieving overlay accuracy below 1nm (to match ASML's production-level alignment precision) remains another challenge for the company. This is perhaps because the company still has to address issues such as wafer handling, stage repeatability, and other factors related to high-precision mechanics, which ASML has taken decades to solve.

Beyond that, the tool must reach commercial throughput and consistent yield, something that took years for ASML's EUV tools. In fact, ASML's EUV journey timeline is quite exemplary: it has taken the industry 12 years to evolve from an alpha demo tool (2006) to mass production (2018), and about seven years to go from the first pre-production system (2010) to a mass-production-capable scanner.

A new paradigm

Speaking of mass-production-capable X-ray lithography tools, it is important to note that Substrate has no intention of selling them to third parties such as Intel or TSMC. Instead, Substrate plans to build its own fabs in the U.S. (a move that could give the company geopolitical importance in the eyes of the U.S. government), install additional tools, and offer foundry services, thus challenging existing chip contract manufacturers.

However, this strategy adds complexity and cost. Constructing even a single high-end semiconductor fabrication plant would require tens of billions of dollars in investment and a large ecosystem of suppliers and service infrastructure, which currently does not exist for X-ray lithography production.

Substrate would also need to integrate its XRL litho machines with hundreds of other tools in the fab, or persuade its suppliers (such as Applied Materials, KLA, Lam Research, etc.) to help it do so, which likely involves further investments from the company, making its first fab particularly expensive.

Also, running both a toolmaking activity and a chip foundry would stretch Substrate's technical and financial resources, which would make it particularly hard to achieve its promised per-wafer price of $10,000 by the end of the decade, as its investors will likely demand returns after pouring tens of billions of dollars into the company.

However, if Substrate succeeds in both roles, it could shift the balance of the semiconductor supply chain back to the U.S., as the company will likely outpace ASML's tools in terms of resolution and performance, and TSMC in terms of design cycle time and potentially volume.

To get more insightful news analysis, Subscribe to Tom's Hardware Premium from just $7 per month for a limited time.

Last week, ASML introduced the Twinscan XT:260 lithography scanner, the industry's first scanner that has been designed from the ground up for advanced 3D packaging, marking a new era in fab tools.

Advanced packaging technologies like TSMC's Chip-on-Wafer-on-Substrate (CoWoS) are crucially important to achieve the performance scaling necessary to develop artificial intelligence and to evolve supercomputers.

Advanced packaging relies on deposition, etching, lithography, and metrology/inspection tools to make sophisticated chips. But while using these front-end tools is efficient for many steps, they are overengineered for some, and insufficient for others.

"In line with our plans to support our customers in the 3D integration space, we shipped ASML’s first product serving Advanced Packaging, the Twinscan XT:260, an i-line scanner offering up to 4x productivity compared to existing solutions.", ASML posted in its Q3 2025 financial results.

The Twinscan XT:260

ASML's Twinscan XT:260 is an i-line (365 nm) step-and-scan lithography system that processes 300-mm wafers and weds the precision of previous-generation front-end lithography tools with the productivity and flexibility of back-end tools. TSMC claims this provides four times higher productivity compared to 'competing steppers' used for advanced packaging technologies, such as Canon's FPA-5520iV. ASML never named the exact competing product, but Canon's FPA-5520iV is a good bet.

The key advantage of the tool compared to some of the existing machines used for advanced packaging is that it supports a high-dose exposures (340 mJ is mentioned, though it is usually tunable) and a 52 mm × 66 mm image field, enabling the tool to process up to 3,432 mm^2 interposers (4X EUV reticle size) without field stitching, which reduces complexity and speeds up the production cycle. For the sake of truth, it should be noted that Canon’s FPA-5520iV LF2 Option supports a 52 mm × 68 mm image field, but this is a stepper, not a scanner.

The system delivers 400 nm resolution, a 35 nm overlay, and offers a large depth of focus (11 µm at 1 µm CD) to enable accurate patterning for redistribution layers (RDLs) through-silicon vias (TSVs), and hybrid bonding structures used by modern packaging methods to integrate multi-chiplet designs. The unit also boasts 775 µm through-silicon alignment capabilities to make it particularly suited for bonded or non-planar wafers, which are common in 3D stacking.

The Twinscan XT:260 relies on ASML's dual-stage platform, so it can expose one wafer while simultaneously aligning the next, which significantly increases its performance. Speaking of performance, the machine can process up to 270 wafers per hour (at a 340 mJ dose) and handle thick (0.775 mm – 1.7 mm) or warped (1 mm) wafers.

With a 400 nm resolution, 35 nm overlay, and the ability to handle thick or warped wafers (up to 1.7 mm), the XT:260 is optimized for technologies Intel's Foveros, TSMC's CoWoS and System-on-Integrated-Chips (SoIC), as well as other high-density die-stacking or interposer technologies which require precise alignment through silicon.

The Twinscan XT:260 is positioned below the Twinscan XT:400M, the company's most basic i-line scanner used for chipmaking on mature nodes, but which may be an overkill for chip packaging on advanced nodes for now. Keep in mind that there are plenty of ASML's PAS 5500 i-line steppers that are used for 'more-than-Moore' applications, which is the company's convoluted way of pointing towards advanced packaging.

Compared with Canon's FPA-5520iV and the long-standing PAS 5500 i-line steppers, which have been widely used for CoWoS and fan-out packaging, the XT:260 represents a major leap in both productivity and precision. While the aforementioned tools rely on step-and-repeat exposure with limited throughput and field size (PAS 5500 only), the XT:260 introduces a scanner architecture with continuous wafer movement, advanced alignment optics, and automation suitable for high-volume 3D integration, which will be particularly important given that demand for advanced packaging is increasing.

The big picture

ASML's Twinscan XT:260 is the industry's first lithography scanner designed specifically for advanced packaging. It's not the only lithography scanner aimed at advanced packaging, though. The semiconductor industry has a choice: Use new tools like the Twinscan XT:260, or repurpose existing tools designed for front-end chip manufacturing for advanced packaging. If ASML's estimations are correct, using this specific tool will be technically beneficial, but may come at significant expense.

Previous-generation front-end lithography, etch, and deposition tools offer sub-micron precision, but need ultra-clean processing environments that ensure tight overlay and defect control. This is because they produce thousands of interconnects linking chiplets and HBM stacks in 2.5D, and eventually 3D System-in-Packages (SiPs).

However, these front-end tools are far more expensive — both in terms of price, performance, and total cost of ownership — than what is typically required for back-end packaging steps. Hence, using them in packaging lines drives up cost and limits output. One advantage of using them is that developers, process control engineers, and technicians at Intel and TSMC are familiar with those tools, which almost certainly guarantees good yields and fast ramp-ups. However, it comes at a high cost and a relatively long production cycle.

With tools like ASML's Twinscan XT:260, wafer-level stages that demand extreme precision — TSV formation, RDL patterning, and hybrid bonding — will get faster and therefore cheaper. This will set the stage for the broader adoption of advanced packaging technologies in several years. It'll likely take some time for chipmakers like Intel, Samsung, and TSMC, or OSAT companies like ASE, Amkor, and JCET, to integrate the lithography system into their process technologies and flows.

There are a lot more tools to be designed specifically for advanced packaging. Advanced packaging techniques still rely on 'classic' back-end tools for underfill, molding, ball attach, and many other operations. This hybrid flow balances cost with accuracy: front-end-grade tools where micron (or even nanometer) alignment matters.

As advanced packaging facilities use front-end tools (with appropriate costs), the boundary between foundries and OSATs is blurring. TSMC's CoWoS and SoIC facilities are filled with wafer fab equipment from ASML, Applied Materials, Canon, KLA, Lam Research, and Tokyo Electron, and usually cost north of $3 billion, the cost of a chip fab in the early 2010s. This is going to continue as more WFE makers set to produce tools specifically tailored for advanced packaging in the coming years and quarters.

The chief financial officer of ASML has told Bloomberg that the lithography giant is well prepared for China's export controls regime on rare earth elements and technologies for their mining and refining. The company has long lead times for its advanced tools, so it has plenty of raw materials in stock to support short-term demand from its clients. What happens after the company's reserves deplete is something unclear, though.

"We have long lead times, and therefore, also in our supply chain, we make sure that we have the materials in that we that we need for the next couple of months," said Roger Dassen, CFO of ASML, in a conversation with Bloomberg.

Under the new export control rules China imposed last week, companies have to get an export license to ship such rare earth materials as holmium, thulium, or ytterbium, or products based on these materials, from China's Ministry of Commerce. Furthermore, China imposed its export controls beyond its own borders on products containing rare earth materials originating from China if their value content within that product is more than 0.1% starting December 1, 2025.

This decision of the Chinese government could essentially stop all the supplies of all rare earth materials and products containing them across the world, something that could harm ASML, which uses a number of them inside its DUV and EUV lithography systems, metrology tools, and inspection tools.

However, Dassen downplayed the possibility of halting production after December 1, saying that the company's supply planning and long production cycles give it enough flexibility to absorb temporary disruptions. Meanwhile, the company now has over a month to buy rare earth materials or components containing them before the new export controls regime is enacted.

Speaking of China, ASML re-emphasized that it expects demand from its customers in the People's Republic to drop in 2026 due to the revocation of fast-track VEU license exemptions for Micron, Samsung, SK hynix, and TSMC, as well as softening demand from local chipmakers.

"When we look at China, we believe that the demand of our Chinese customers is going to be significantly lower in 2026 than it has been in 2024 and 2025 when we had very strong business there," said Christophe Fouquet, chief executive of ASML, during the company's earnings call with investors and analysts.

When Dutch officials revoked ASML’s license to export Twinscan NXT:2050i and NXT:2100i extreme ultraviolet (EUV) lithography systems to China under U.S. pressure, it closed the door to the only machines capable of producing sub-7nm chips at scale.

That single policy decision has defined what some analysts are calling the semiconductor cold war, where SMIC and its peers cannot buy the equipment needed for modern AI accelerators, and every shipment of advanced tools is now scrutinized as if it were a weapons transfer.

What the blockade hasn’t done is stop China’s fabs. Instead, it has forced an awkward reliance on older deep ultraviolet (DUV) machines (via TrendForce) and sparked a parallel race to design local replacements. It’s a strategy of necessity, one that accepts higher costs and lower yields in exchange for continuity and independence.

Sanctions and the scramble for workarounds

EUV machines are some of the most complex industrial systems in existence. Packed with thousands of U.S.-origin components and priced at hundreds of millions of dollars a piece, they are the foundation of every 5nm and 3nm chip shipping, or planning to ship in the future. China has none, and the U.S. has made sure of that.

Successive rounds of sanctions since 2022 have blocked not just EUV exports, but also the most advanced immersion DUV systems, including ASML’s Twinscan NXT:1970i and NXT:1980i. The Netherlands and Japan joined those restrictions, and even service contracts for ASML machines installed in China are being scrutinized. ASML itself has admitted that a China-based employee stole proprietary EUV data, highlighting how valuable the technology has become.

The policy has pushed chip procurement into murky territory. Grey-market Nvidia GPUs continue to flood in through Hong Kong and Singapore despite being explicitly banned, with seizures measured in the hundreds of millions of dollars. But smuggling a workstation card is one thing; sneaking in a 180-ton lithography scanner is another. On that front, Washington’s chokehold on export controls has held up.

The DUV fallback plan

Deep ultraviolet lithography predates EUV by decades. Using 193nm argon-fluoride lasers, immersion DUV systems comfortably support 28nm nodes, with yields and costs increasing dramatically as nodes shrink further. With multi-patterning (exposing the same wafer multiple times with different masks) they can be stretched down to 7nm-class geometries. Intel’s disastrous 10nm rollout proved how costly and yield-sensitive that approach can be, but it remains the only path available to Chinese fabs.

SMIC’s Kirin 9000-class parts, built for Huawei, already demonstrate the limits of this strategy. It’s widely believed that they were fabricated with DUV and heavy use of multiple patterning. The chips work, but at lower volume and efficiency than anything coming out of Taiwan or South Korea.

For now, Chinese fabs are leaning on their existing ASML DUV fleets. Nearly half of ASML’s second-quarter equipment tooling shipments in 2024 went to China, despite the political pressure in Washington. Those sales are a reminder of just how dependent Beijing still is on imported tools. But the window is closing, and the focus is shifting.

Shanghai Micro Electronics Equipment announced in 2023 that it had built a 28nm immersion scanner, the SSA800-10W. It’s crude compared to ASML’s Twinscan line, but it represents the first domestically developed immersion tool, and critically, it was designed without U.S. intellectual property. According to a TrendForce report, SMIC is testing a prototype from Yuliangsheng, a Huawei-linked affiliate of SiCarrier, which also rated for 28nm, but with ambitions to scale toward 7nm with multi-patterning.

A fully domestic DUV scanner, even if mired in yield problems, would insulate Chinese foundries from future Western policy decisions. Let’s not forget that China has previously made it clear that strategic self-sufficiency matters more than perfect parity with TSMC or Samsung.

China is playing the long game