Despite disagreements over trade policies with China, the U.S. and the Netherlands have signed the European nation to the Pax Silica initiative of countries looking to reduce reliance on China for key raw materials and manufacturing expertise in the AI industry, as reported by Reuters. With the Netherlands playing host to the key supply chain company, ASML, Europe's largest tech company, and the most advanced manufacturing of cutting-edge photolithography machines for semiconductor fabrication, this is a big strategic win for the U.S.-led initiative.

Dutch ​Trade Minister Sjoerd Sjoerdsma travelled to Washington this week to sign the deal, meeting with U.S. Commerce Secretary Howard Lutnick and fellow lawmakers as part of ongoing negotiations around trade in high-tech chips and hardware, particularly with China.

Speaking with reporters, he said that the U.S. and the Netherlands have shared goals in preventing sensitive technology from ending up in dangerous hands - the Netherlands famously seized key Dutch chip manufacturer Nexperia from its Chinese parent company, Wingtech, in 2025. However, he also raised concerns over American legislation that would make it difficult for companies like ASML to even service machines and tools already delivered to countries like China.

That could affect the Netherlands' national security and market position of key Dutch companies, he said.

Pax Silica - Speremus ut diu duret

The Pax Silica, or "Silicon Peace" initiative, was set up in December 2025 by the U.S. Department of State as a direct plan to reduce reliance on China and to build more robust, Western-aligned supply chains for key elements in the semiconductor, AI, and rare-earth element industries. At its outset, Pax Silica secured non-binding signatures from seven countries, including Australia, Israel, Japan, South Korea, Singapore, the United Kingdom, and the United States. They were joined in the months that followed by Greece, Qatar, the UAE, India, Sweden, Finland, the Philippines, and Norway.

Canada and Taiwan have both been invited to join and are said to be participating in summit sessions, but haven't officially signed just yet. The Netherlands did effectively join in December 2025, but was described as a "non-signing partner" in the initiative.

There are ongoing disputes between the U.S. and the Netherlands over whether ASML should be allowed to service and sell less advanced chip fabrication machines to China, while still restricting access to the latest tools.

Those discussions are reportedly still ongoing and were brought up in the meeting between Lutnick and Sjoerdsma this week. The Dutch official has been quite frank in his public statements on the Match Act bipartisan bill that would place restrictions on companies supplying to China.

“The Netherlands’ starting point is that every country is responsible for its own laws,” Sjoerdsma said in May, via Reuters.

Under the silicon thumb

A key story in the global race to adopt and supply AI through infrastructure building and rapid development has been access to the raw materials, tools, machines, and expertise required to create it. That's mainly had the United States and China at loggerheads with one another, with the former restricting access to cutting-edge Nvidia GPUs and other semiconductor products, and China rowing back access to its manufacturing and raw material industries.

But while that's acted as a tit-for-tat backdrop to U.S. and Chinese trade relations and particularly the mercurial needs and demands of President Trump, the divestment of global supply chains from traditional Chinese sources has spread globally. Nexperia was one key Dutch entity that was brought back in-house from Chinese owners, and in June 2025, Taiwanese firm Pegatron announced new production facilities in Mexico and the U.S. to move away from reliance on China.

The U.S. has also been trying to restrict China's access to high-tech hardware for a number of years. President Trump signed the National Defense Authorization Act in 2019, which effectively banned Chinese firms Huawei and ZTE from being used in any U.S. government agencies. Both companies were later designated as threats to national security in 2020. Under the Biden administration, the U.S. implemented a new series of export controls in 2022 to constrain China's ability to accelerate its high-technology and chip manufacturing industries.

This led to a boom in domestic Chinese chip production, as well as a rapidly expanding black market smuggling industry that ultimately saw officials in U.S. firms jailed, and even Nvidia potentially implicated.

But in 2026, even as the U.S. has approved the sale of some high-end Nvidia chips to China, its new Pax Silica Initiative and MATCH Act are putting more pressure on China than ever before, and global partners aren't entirely happy about it.

Under the bill, foreign-owned companies like ASML that don't comply with the restrictions on business dealings with China could find themselves losing access to U.S. components, software, or customers. Although the world still needs ASML - it's one of the tightest bottlenecks in the global chip supply chain - becoming part of the Pax Silica initiative could prove paramount for advanced economies wanting to make the most of advances in AI and chip fabrication.

Although Dutch officials still clearly have reservations about the MATCH Act, it's not clear how much leverage they can have over it, or whether it's possible to ignore its claimed mandates.

Unsteady ground

The Netherlands and other strategically aligned economies with a foothold in the AI supply chain face a tricky situation in 2026. Initiatives like Pax Silica raise the prospect of greater autonomy in the global supply chain, with less reliance on China for key materials, tools, and manufacturing expertise. But that may simply replace one dependency with another, trading exposure to Beijing for greater oversight from Washington, and even coercion if certain controls aren’t adhered to.

For the Dutch, ASML isn’t just a key company. It is one of the world’s most important technology pillars and helps the Netherlands punch well above its weight in global supply-chain politics. Without ASML, manufacturers like Samsung, Micron, and TSMC, and component designers like Nvidia, would not be able to build the cutting-edge hardware they can today. That gives the Netherlands real muscle when pursuing its own interests.

But it also makes ASML a target for legislation that could limit Dutch autonomy and force tighter integration with larger players like the United States, without whose components, software, and market access ASML would struggle.

That tension is unlikely to disappear. Even if the U.S. midterms later this year help leash some of the more turbulent aspects of the Trump administration, they won’t end American ambitions to pull control of the global chip and AI supply chains away from China, and tuck it into Washington’s own catalogue of control.

An interesting conversation on X has unearthed the existence of a rare ASML-focused Special Edition Monopoly board. Two chipmaking and engineering enthusiasts appear to have clinched a deal where one hands over an ASML Lego kit, a scale model of the world’s first High-NA EUV machine. In the no-cash deal, the other party will receive an ASML Special Edition Monopoly board. It appears that the deal is done, barring any regulatory hurdles and no one changing their minds, but it did pique our interest in the history of the board.

While we’ve seen and reported on the ASML chip tool Lego sets previously, this is the first time the firm’s special edition Monopoly set has blipped on our radar. It is possible this obscurity is due to this board game edition coming out way back in 2007, when the pioneering Dutch semiconductor company’s profile wasn’t quite as high as it is now. With the semiconductor segment becoming all the more important in recent years, driving the current AI boom, cutting-edge chip tool firms like ASML have risen to great prominence.

ASML’s special edition merchandise is also in high demand in the 2020s. Thankfully, we can learn a little more about the provenance of the headlining Monopoly board as it is featured in the board game’s Wiki. As previously mentioned, it was produced in 2007. Specifically, it was prepared for the Christmas period at the end of that year “as a gift to ASML employees and their families this holiday season.” From that ‘publisher’s description, it sounds like quite a few employees will have received one of these games, but it is still obviously an attractive collector’s item.

Sadly, the Wiki imagery doesn’t clearly show what the playing ‘tokens’ are (that’s Hasbro’s official term for the little metal playing pieces). The normal game has tokens like a boot, a dog, and a car, but we can’t quite make out the detail on this. Instead of streets and avenues, the ASML Monopoly board appears to have technologies and machines. Furthermore, the traditional stations are replaced by ASML campuses. Elsewhere on the board, special spaces include Corporate Tax and Press Release, where you must pick up a card. Regular Monopoly features such as Go, Water Works, Go To Jail, and the Electric Company remain.

Other non-consumer-facing semiconductor brands like TSMC and SK hynix have released successful sellout merchandise and memorabilia in recent years. Some items are easier for non-employees to get a hold of than others. For example, it is easy for anyone to find resellers of TSMC-related merchandise on Taiwan’s Shopee marketplace.

ASML has told Tom's Hardware that claims one of its extreme ultraviolet (EUV) lithography systems has ended up in China despite export restrictions is both inaccurate and damaging to its reputation. It follows a report that Commerce Secretary Howard Lutnick questions senior leadership, concerned that one of the machines had ended up in China in breach of export restrictions.

The company is refuting a recent report claiming the U.S. government believes that one of ASML's extreme ultraviolet (EUV) lithography systems may have somehow reached China despite export restrictions, according to Bloomberg, citing sources familiar with negotiations between the U.S. officials and ASML executives. ASML denies any wrongdoing and claims that it knows the location of every EUV tool it has ever built.

The issue reportedly emerged during meetings between U.S. Commerce Secretary Howard Lutnick and ASML executives. According to people familiar with the discussions cited by Bloomberg, Lutnick questioned whether an EUV system may have found its way into China. Such a development would represent a major breach of export controls because, under the Wassenaar Arrangement, ASML can not ship EUV lithography equipment to Chinese customers. In fact, the only EUV tool that China-based Semiconductor Manufacturing International Corp. (SMIC) has bought remains in the Netherlands. As a result, ASML calls the accusations 'unfounded' and 'damaging.'

"In recent years, ASML has refuted several unfounded rumors regarding non-compliance with export controls concerning China which were inaccurate and damaging to our reputation," a spokesperson for ASML told Tom's Hardware.

The U.S. government has not publicly produced evidence that a complete EUV scanner is operating in China. Yet, several senior administration officials told Bloomberg that they possess information indicating that ASML exported equipment associated with EUV systems, including specialized systems used to 'transport EUV machines.' Those officials declined to disclose any evidence, citing sensitivity concerns.

"ASML has never shipped an EUV machine to China, nor have we shipped to China any component, module or equipment specially designed to be used in an EUV machine," the spokesperson told us.

An ASML EUV scanner is made of 100,000 components and weighs 180 tons. It is transported only by air on multiple planes, and it would be impossible to intercept such a shipment without causing an international scandal. Meanwhile, given the complexity of the machine, it is impossible to build one using spare or scrap parts or reverse engineer it using its components, as we reported back in December.

Bloomberg claims that ASML has circulated an internal presentation titled 'No indication of any ASML EUV System in China,' which reportedly states there are 314 EUV systems currently operating worldwide and another 26 that have been retired. According to the document, none are located in China. The presentation further notes that EUV scanners continuously communicate with ASML, so the company can detect interruptions, abnormal activity, or connectivity issues. In addition, customers cannot simply dismantle, transport, and reinstall an EUV scanner without direct assistance from ASML due to specialized logistics and handling requirements.

ASML certainly understands concerns of the West regarding China, so claims it has never shipped an EUV tool to the People's Republic initially due to the Wassenaar Arrangement and then due to more recently imposed export controls.

"ASML regularly engages in transparent and open dialogue with government leaders globally," ASML told us. "We recognize the national security considerations behind export control regulations in the U.S. and the Netherlands. As a company, we are fully committed to abiding by all laws and regulations applicable to our business activities, including all applicable relevant export control regulations, and we have consistently adjusted our business to any development in export controls to comply to any new rules."

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

Chinese semiconductor start-up Prinano announced that it has successfully validated the mass production of photonic chips without using the industry-standard lithography equipment. According to an SCMP report, the company said in a WeChat post on Friday, June 5th, that it had made 8-inch optical chip wafers in collaboration with Shenzhen Litra Technology. The company said it achieved this while “completely avoiding” the need for deep-ultraviolet lithography (DUV), a significant breakthrough in China’s push to reduce its dependence on ASML lithography tools, which remain subject to export restrictions.

Instead of conventional optical lithography, Prinano said it used its PL-AS vacuum air-cushion nanoimprint lithography (NIL) system, which, according to the company, can reduce manufacturing costs to roughly one-tenth that of traditional DUV-based processes, while supporting wafer-level production of photonic chips.

Modern chips are typically produced using highly sophisticated DUV or more advanced EUV (extreme ultraviolet) systems that project circuit patterns onto silicon wafers using light. These machines contain some of the most complex optics ever built and can cost hundreds of millions of dollars. Nanoimprint lithography takes a very different approach. Rather than projecting patterns using light, it physically presses nanoscale structures into a specially prepared resist layer, basically stamping microscopic patterns directly onto the wafer surface. This process eliminates the need for many of the expensive optical systems required by conventional lithography equipment.

Nanoimprint lithography has long been viewed as a potential alternative to conventional optical lithography because of its potential for lower costs and extremely high pattern resolution. However, despite its promise, the technology has struggled to achieve widespread adoption in semiconductor manufacturing due to concerns about defect rates, template wear, throughput, and production yields, all of which become increasingly important in high-volume manufacturing environments.

Founded in 2017, Prinano has spent the past several years working to overcome those limitations by developing its own nanoimprint lithography ecosystem. The company took a significant step in 2025 when it announced the delivery of what it described as China's first semiconductor nanoimprint lithography system to a domestic customer, marking an early effort to commercialize the technology.

The company's latest announcement suggests it may have progressed beyond equipment development and pilot deployments. According to Prinano, its PL-AS vacuum air-cushion nanoimprint lithography platform incorporates wafer-level pressure control, customized double-layer imprinting materials, and proprietary process technologies capable of producing sub-10-nanometer features. The company now claims those developments have enabled the successful validation of wafer-scale photonic chip production on 8-inch wafers.

Importantly, Prinano is not attempting to replace the production of cutting-edge processors or AI accelerators. Instead, the company's announcement focuses on photonic chips, a category of semiconductors that manipulate light rather than electrical signals. These devices are widely used in fiber-optic communications, data center interconnects, sensing systems, and LiDAR technologies.

Photonic chips are considered particularly well suited to nanoimprint lithography because many of their critical structures, including waveguides, gratings, and ring resonators, consist of repeating nanoscale patterns that can be replicated efficiently through imprinting techniques. This characteristic makes them a more practical near-term application for NIL than advanced logic chips, where defect rates and alignment requirements are far more demanding.

Another noteworthy detail is the use of 8-inch wafers. While leading-edge processors are increasingly manufactured on larger 12-inch wafers, 8-inch wafers remain widely used across specialized sectors such as compound semiconductors and power electronics. Demonstrating production on full 8-inch wafers suggests the process has moved beyond laboratory-scale demonstrations and into a format more compatible with commercial manufacturing.

The development also highlights China's broader search for alternative semiconductor manufacturing pathways amid ongoing export restrictions. Access to advanced lithography equipment from ASML — required for EUV and DUV — has been increasingly constrained under US-led controls, prompting Chinese companies to explore alternative approaches ranging from advanced packaging technologies to new chip architectures and novel manufacturing methods. Huawei recently announced a new LogicFolding chip architecture that allows the company to develop high-performance processors without relying on restricted EUV lithography machines.

Significant questions remain about Prinano’s announcement. While the claims have been validated in mass production, the company did not disclose production volumes, yield rates, defect densities, customer shipment data, or independent third-party validation. These metrics are critical for determining whether a semiconductor manufacturing technology is commercially viable rather than merely technically feasible.

ASML has confirmed that a group of disgruntled workers is pushing back hard against an invitation for Elon Musk to address the equipment maker’s closed annual tech conference in Den Bosch this Thursday. According to Dutch publication Eindhovens Dagblad (via DutchNews), employees have been airing their grievances on the company’s internal comms platform, with several threatening to skip his appearance altogether because of his involvement in U.S. politics and what staff described as "Nazi sympathies."

If the invitation is accepted, Musk could join CEO Christophe Fouquet by video link to discuss AI, robotics, space exploration, and semiconductor production, with the conversation centered around Terafab, the SpaceX and Tesla chip venture whose proposed Texas fab can’t reach production without ASML's machines.

Backlash began to surface on Viva Engage, ASML’s internal employee platform, where workers have argued that giving the controversial tech leader a platform clashes with the company’s stated commitment to an inclusive culture. In particular, ASML staff have specifically highlighted Musk’s political activities around the Trump administration, general anti-European rhetoric, and what staff described as “Nazi sympathies.” In March, an Amsterdam court banned the Grok image-generation app due to its abusive “undressing” image generation capabilities.

ASML is the sole monopoly supplier of EUV lithography systems, the tools needed to pattern transistors at the leading edge; fabs targeting advanced nodes have no viable alternative.

Every major foundry and memory maker, including TSMC, Samsung, SK hynix, Micron, and Intel, already holds orders with the company. Terafab, by contrast, has no path to leading-edge production that bypasses ASML, and the company’s CEO said last month that Musk is "very serious" about the project, noting that ventures like Terafab and Starlink would strain equipment makers' capacity over the coming years.

ASML hasn’t addressed the internal revolt directly, saying only to employees via Viva Engage that it’s committed to a workplace where everyone feels respected and is free to express their opinion.

Musk announced Terafab in March as a SpaceX and Tesla joint venture with an initial $20 billion budget, targeting 2nm production and a terawatt of annual compute for AI, robotics, and orbital data centers. SpaceX has since filed a property tax abatement application in Grimes County, Texas, for a fab costing $55 billion in its initial phases and up to $119 billion if all expansions proceed, with Intel set to contribute its 14A process technology. Outside estimates run higher, with Bernstein analysts arguing the full terawatt project would require roughly 358 fabs and around $5 trillion.

“ASML regularly invites technology leaders from the industry to share their insights. The invitation to Elon Musk took place in the context of the Terafab project, which is highly relevant to the semiconductor industry,” the company said.

ASML closed Wednesday, June 3rd, as the most valuable company in European history, reaching a market cap of $668 billion and passing the $650 billion record Novo Nordisk set in June 2024. The Dutch firm, which is the sole supplier of the extreme ultraviolet (EUV) lithography machines that TSMC, Samsung, and Intel use to print leading-edge logic, rose after JPMorgan and Morgan Stanley published near-identical notes arguing it can manufacture far more machines than the market had assumed.

The two banks raised their price targets on the same day, JPMorgan to €1,900 from €1,515 and Morgan Stanley to €1,660 from €1,400, both keeping Overweight ratings. JPMorgan analyst Sandeep Deshpande argued that ASML can deliver more than 110 low-NA EUV systems without adding new building capacity, well above the roughly 90 units investors had previously cited as the maximum and above the company's own near-term output.

That output is mission-critical for the chip industry because EUV remains a severe chokepoint on advanced chip supply. Every wafer of leading-edge silicon used to train and run AI models passes through an ASML scanner at some stage, so more machines shipping translates directly into more capacity for the fabs downstream.

Morgan Stanley said its greater confidence in near-term shipments stemmed from comments at ASML's April annual general meeting, where the company outlined an expansion at the Brainport Industries Campus in Eindhoven, with construction set to begin in the third quarter of 2026. The bank cautioned that the campus "needs to be the start of a multi-phase build-out" to fully alleviate capacity concerns.

ASML’s record ironically sits below the bar set by the companies ASML supplies. Its market cap remains short of the trillion-dollar mark that several U.S. chip firms have cleared, and the stock's roughly 50% gain this year has trailed the broader semiconductor sector, which has run far hotter on AI demand. ASML had already passed SAP as Europe's largest listed company and is now worth more than the next two European firms, HSBC and Roche, combined.

And while the company holds a monopoly, its long-term dominance isn’t guaranteed; several efforts are currently taking aim at it. Substrate, a San Francisco startup backed by Peter Thiel's Founders Fund and the CIA-linked In-Q-Tel, has raised $100 million for a particle-accelerator X-ray lithography system that it claims can pattern 2nm-class features at roughly $10,000 per wafer against the $100,000 it models for leading-edge EUV. Canon is also shipping commercial nanoimprint tools, while Nikon has entered with a lower-end product, and China has touted a workaround to ASML's equipment.

None of these is likely to replace an EUV scanner in high-volume logic anytime soon, where ASML's tools run from roughly $235 million for a low-NA system to about $380 million for the High-NA EXE:5200B that Intel installed late last year for its 14A node.

Asked about rivals by TechCrunch last month, ASML CEO Christophe Fouquet said the gap between wanting the technology and having it remains vast, adding that "when you start from scratch, the challenge is enormous."

Nikon will try to win back lithography customers by selling argon fluoride (ArF) tools for less than market leader ASML, the company's new president and chief executive, Yasuhiro Ohmura, told Nikkei Asia in a recent interview. Ohmura, who took the role in April, said Nikon is talking to several large chipmakers in the U.S. and Asia about fresh ArF orders, with discussions "nearing purchase orders."

Nikon’s pitch to customers comes after a brutal stretch for the business: Nikon shipped 11 ArF systems in its fiscal year ending March 2024 and none across the first three quarters of its 2025 fiscal year, according to company figures reported by TrendForce, against ASML's grip on more than 80% of the lithography market.

Competing on price like this targets a segment of the market that ASML doesn’t outright dominate. While it holds an obvious monopoly position on extreme ultraviolet (EUV) systems used for the most advanced chipmaking processes, ArF immersion is a type of mature deep ultraviolet (DUV) work, and the majority of patterning steps, even on a 3nm chip, still run on it. ASML's advanced ArF immersion machines average around $82.5 million per unit, leaving room for a cheaper rival. Nikon walked away from EUV in 2008.

In February, Nikon said that it would launch a new ArF immersion platform in its 2028 fiscal year, fitted with a new lens and wafer stage, and built for compatibility with ASML's installed tools. "We manufacture many parts in-house, giving us an advantage in cost competition," Ohmura told Nikkei Asia.

Nikon and ASML are the only two companies that build ArF lithography equipment, and demand is climbing as the AI bubble strains tool supplies. ASML shipped 48 EUV and 131 immersion DUV systems in 2025 and closed the year with a €38.8 billion order backlog. Ohmura argues that chipmakers would rather buy from two suppliers than depend on one to keep a lid on equipment costs.

Whether price alone will pull customers back remains to be seen. Nikon's ArF market share has kept sliding since ASML pulled ahead through long-term R&D partnerships and exclusive handling of cutting-edge tools, and Intel, which once accounted for 80% of Nikon's ArF orders, has cut spending amid its own manufacturing troubles.

Nikon posted a net loss of 86 billion yen ($540 million) for the year ended March, its worst ever, dragged down by weak equipment orders and a struggling metal 3D printing unit. Ohmura says he plans to narrow Nikon's focus to cameras and chipmaking tools.

ASML CEO Christophe Fouquet said on Wednesday that he has spoken directly with Elon Musk about the TeraFab semiconductor project, telling Reuters that the SpaceX and Tesla founder is "very serious" about building one of the largest chip manufacturing operations ever attempted.

Fouquet, speaking at a tech event in Antwerp, Belgium, also warned that soaring AI demand will leave the global semiconductor industry short on capacity for the foreseeable future.

TeraFab, which Musk announced in March with an initial $20 billion investment, will aim to produce logic chips, memory, and advanced packaging under one roof in Texas. Intel joined the project in April and plans to contribute its 14A process technology, and SpaceX has since filed for a $55 billion semiconductor facility in Grimes County, Texas, with potential expansion costs reaching $119 billion.

Fouquet didn’t share details of his conversations with Musk but said that projects like TeraFab and Starlink would put pressure on equipment makers' capacity over the coming years.

ASML is the sole global supplier of EUV lithography systems, which are required to manufacture any chip at the leading edge. Any serious new entrant to advanced chipmaking, TeraFab included, would need to procure billions of dollars in ASML equipment. The company currently has orders from every major foundry and memory maker, including TSMC, Samsung, SK Hynix, Micron, and Intel.

Fouquet says that he expects the first logic chips produced with ASML's High NA EUV lithography systems to arrive within months. Intel is the earliest adoptee, having installed and completed acceptance testing of its Twinscan EXE:5200B at the D1X fab in Oregon late last year. The High NA tools use a 0.55 numerical aperture lens, enabling roughly 2.9 times the transistor density of current EUV systems in a single exposure.

Fouquet also confirmed that ASML is developing a second advanced packaging tool, expanding the company's product line beyond lithography. He described the segment as “a small leg” right now, but added that it will present new opportunities for ASML.

On export controls, Fouquet pushed back against the proposed MATCH Act, which U.S. lawmakers introduced last month to ban sales and servicing of ASML's DUV lithography tools to Chinese customers, among other things. He noted that the DUV immersion systems ASML currently sells to China are based on tech first introduced in 2015, placing them eight generations behind the leading edge. Further restrictions, he argued, would only speed up China's domestic efforts to develop competing tools.

"If I put you in a desert and tell you you're not going to have access to food anymore, how long does it take you to make your own garden?" Fouquet told Reuters. "It's a matter of survival."

ASML and Tata Electronics have signed a memorandum of understanding to deploy ASML's lithography equipment at India's first front-end semiconductor fab, a 300mm facility under construction in Dholera, Gujarat.

The deal was signed during Indian Prime Minister Narendra Modi's visit to the Netherlands, with Dutch Prime Minister Rob Jetten also present, and covers lithography tools, talent development, and supply chain support for a fab backed by $11 billion in total investment.

Taiwan's Powerchip Semiconductor Manufacturing Corporation (PSMC) is licensing the process technology for the Dholera fab, covering 28nm, 40nm, 55nm, 90nm, and 110nm nodes, according to the ASML press release. PSMC is also providing design and construction assistance under a definitive agreement finalized with Tata Electronics in 2024.

At full capacity, the plant is designed to produce 50,000 wafers per month for a chip portfolio that covers power management ICs, display drivers, microcontrollers, and high-performance computing logic for automotive, mobile, AI, and communications applications, according to the companies' joint statement.

"ASML's deep expertise in holistic lithography solutions will ensure the timely ramp of our fab in Dholera, create a resilient and trusted supply chain for our global customers, drive innovation, and develop talent locally," Randhir Thakur, CEO and MD of Tata Electronics, said in the press release.

It was reported last month that civil construction at the Dholera site has reached roughly 50% completion. The project required a major redesign late last year after soil testing found the ground too soft and saline for the original structural plan, though it was said at the time that the changes wouldn’t delay the project’s overall timeline, and trial production is still targeted for later this year.

India's government is covering 50% of the eligible project costs through the India Semiconductor Mission, according to a fiscal support agreement signed in March last year between Tata Electronics and the Indian government's ISM.

The Gujarat state government provides additional incentives, including subsidized land in the Dholera Special Investment Region, reduced power tariffs, and stamp duty exemptions. The Dholera site was formally designated a Special Economic Zone in April 2026.

This deal is the latest in a series of partnerships that Tata has assembled for the Dholera project. India joined the U.S.-led Pax Silica initiative back in February, a supply chain alliance spanning semiconductors, AI infrastructure, and critical minerals.

India currently has no front-end wafer fab capacity. While Micron does operate an assembly and test facility in Sanand, Gujarat, and several other packaging and testing projects are in development, the Dholera fab is the country's only commercial foundry project. ASML CEO Christophe Fouquet described India's semiconductor sector as presenting "many compelling opportunities" in the joint statement, adding that the company looks forward to contributing "technological expertise" and helping "nurture talent in India."

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

The Dutch company holds a 100% monopoly on EUV lithography and approximately 83% of the global lithography market overall, and its roadmap now spans four distinct generations of technology: DUV immersion systems that still handle the majority of layers on every advanced chip, low-NA EUV scanners that enabled the 5nm and 3nm era, High-NA EUV tools now entering early production at Intel and Samsung, and a Hyper-NA concept that remains in feasibility studies for the 2030s.

Each step up this ladder delivers finer resolution at exponentially higher cost and complexity, and just how aggressively the industry's largest chipmakers adopt each generation will determine the pace of transistor scaling for the next decade and beyond.

DUV immersion and low-NA EUV

ASML's DUV immersion systems are still the backbone of semiconductor manufacturing when it comes to volume production. The company sold 131 immersion DUV tools in 2025. Even a chip built on TSMC's 3nm node uses EUV on only a handful of critical layers; the majority of patterning steps still run on DUV immersion tools like the TWINSCAN NXT:2100i, which delivers 295 wafers per hour at 1.35 NA with 1.3nm overlay.

DUV single-exposure is also the standard in mature nodes powering automotive and industrial chips. While DUV multi-patterning can push down to 7nm and even 5nm, it comes at an enormous cost of up to 34 patterning steps at 7nm versus nine with EUV.

Chinese customers purchased an estimated 70% of ASML's DUV immersion systems in 2024, stockpiling ahead of tightening Dutch export restrictions that now cover the NXT:1970i and newer models. SMIC demonstrated 7nm production using DUV multi-patterning for Huawei's Kirin 9000S, according to TechInsights. But the process requires significantly longer cycle times than EUV-based production, and questions exist around whether yields are sufficient for volume commercialization.

On the EUV side, ASML's low-NA systems operate at 0.33 numerical aperture with 13.5nm wavelength light, achieving 13nm single-exposure resolution. The TWINSCAN NXE:3600D, introduced around 2021, delivers 160 wafers per hour with 1.1nm matched-machine overlay. Its successor, the NXE:3800E, began shipping in March 2024 and pushes throughput to 195 wafers per hour, upgradable to 230 — following ASML's recently updated roadmap — while tightening overlay below 1.1nm. Each NXE:3800E costs roughly $180 million. It shares its bottom module, including wafer handler and faster stage mechanics, with the High-NA EXE platform, a decision that reduces ASML's manufacturing complexity and provides fabs with a degree of serviceability continuity when they upgrade.

ASML's roadmap extends low-NA further, with the NXE:3800F expected around 2027. It targets a ≤0.9nm overlay and over 260 wafers per hour. A subsequent NXE:4200G targets a ≤0.8nm overlay and over 300 wafers per hour, with an NXE:4200H beyond that at a ≤0.7nm and 330 wafers per hour. Further out, ASML has disclosed a High Productivity platform, the NXE:4600, targeting 400 wafers per hour or more.

TSMC has confirmed that it will not use high-NA EUV for its A16 (1.6nm) or A14 (1.4nm) nodes, instead relying on low-NA with multi-patterning. Kevin Zhang, TSMC's Deputy Co-COO and Senior Vice President of Business Development, said at the company's European Technology Symposium last May that TSMC would adopt high-NA "whenever we see high-NA will provide meaningful, measurable benefit," adding that the technology team continues to extend the life of current EUV.

Computational lithography is one reason low-NA can stretch further, with ASML's Brion subsidiary developing inverse lithography technology and curvilinear mask optimization software that computationally corrects for optical distortion beyond specification, effectively squeezing better resolution from existing 0.33 NA optics without hardware changes.

TSMC has been a major user of these techniques, and their continued advancement narrows the gap between low-NA double patterning and High-NA single exposure. ASML's installed base management business, which services and upgrades the global fleet of lithography tools, reached €8.2 billion in revenue in 2025, up 26% year-over-year. That recurring revenue stream grows with every tool shipped and is increasingly important as fabs push older systems to higher utilization rates.

High-NA EUV

The jump to 0.55 numerical aperture with high-NA is the largest optical leap in EUV's history, shrinking minimum resolution from 13nm, which itself was down from 30nm with DUV, to 8nm and enabling approximately 2.9 times higher transistor density in a single exposure. ASML's first High-NA tool, the EXE:5000, shipped to Intel in December 2023 as a development platform.

Each unit of the production-capable EXE:5200B weighs in at 150,000 kilograms, requires 250 shipping crates, and takes six months and 250 engineers to assemble on-site, says Intel. Priced at approximately $380 million, the EXE:5200B delivers 175 wafers per hour at 50 mJ/cm² dose with 0.7nm overlay. ASML told Reuters in early 2024 that it had taken 10 to 20 orders by that point and planned to deliver 20 annually by 2028.

Intel announced that it had completed acceptance testing of its EXE:5200B in December 2025 at its Hillsboro D1X fab and that the tool will be used for the development of Intel's 14A fabrication process. 14A is expected to be the first production node to rely on High-NA for its most critical layers, with risk production targeted for 2027.

In September, SK hynix became the first memory manufacturer to install a commercial High-NA system at its M16 fab in Icheon, South Korea. Samsung, meanwhile, received its first EXE:5200B in October, with a second unit due in the first half of 2026 for its 1.4nm foundry node. Imec, the Belgian research institute, secured an EXE:5200 last month with a Q4 2026 qualification target for sub-2nm process development.

ASML's near-term High-NA roadmap includes the EXE:5200C, targeting 190 wafers per hour without stitching and 160 with stitching at sub-0.8nm overlay, followed by the EXE:5200D at 195/175 wafers per hour and eventually the EXE:5400E at 210/180 wafers per hour with sub-0.7nm overlay. A High Productivity variant, the EXE:5600, targets 250 wafers per hour or more.

Analysts from SemiAnalysis believe TSMC won’t adopt High-NA EUV until its 1nm-class A10 node, which would place volume deployment around 2029 to 2030, because existing low-NA EUV systems can match High-NA's 8nm resolution using double patterning, and SemiAnalysis estimates that approach may still cost less than High-NA single patterning. High-NA tools also require substantial changes to existing fab buildings to accommodate their size.

Hyper-NA and pellicles

ASML placed Hyper-NA on its official roadmap for the first time at imec's ITF World in May 2024, with former CTO Martin van den Brink commenting a few months prior that an NA above 0.7 "is certainly an opportunity that will become more visible from around 2030." The primary target is 0.75 NA, with 0.85 NA also under investigation. Zeiss has begun preliminary lens designs. Estimated tool cost: roughly $720 million per system, according to TrendForce.

At 0.75 NA, however, polarization effects begin destroying imaging contrast because one polarization orientation effectively cancels light at extreme incidence angles, thereby necessitating the use of polarizers that block photons and reduce efficiency. Depth of focus shrinks further, and resists must be made even thinner than the sub-30nm films used for high-NA, worsening etch selectivity and stochastic defects from photon shot noise. On top of all that, an electron blur of approximately 2nm may impose a solid resolution barrier regardless of optical improvements.

Pellicle development is another bottleneck. These ultra-thin membranes protect masks from particle contamination during exposure but must transmit EUV light efficiently at rising source power levels. ASML's current composite silicon-based pellicle achieves over 90% transmission at 380 W source power, but for future systems running at 600 W to 1,000 W, carbon nanotube pellicles are the next-gen technology, achieving up to 97% transmission while withstanding temperatures above 1,500 C. Mitsui Chemicals is building dedicated CNT pellicle production capacity targeting 5,000 sheets per year and commercialization aimed for this year.

Export controls and Canon NIL

EUV systems have never been sold to China, blocked since 2019 under U.S. pressure despite existing orders from Chinese customers. In addition, Dutch export controls, effective since late 2023, required licenses for advanced DUV immersion systems (NXT:2000i and newer), and by September 2024, the restrictions expanded to include the NXT:1970i and NXT:1980i.

Servicing restrictions also prohibit ASML from improving overlay accuracy or increasing throughput by more than 1% on installed Chinese systems. China represented 49% of ASML's revenue at the peak of stockpiling in Q2 2024, falling to roughly 36% for full-year 2024. ASML's management guided China to approximately 20% of revenue in 2025 and 2026, which has seen South Korea and Taiwan emerge as the primary growth markets, with SK hynix alone placing a record $7.9 billion EUV order last month covering roughly 30 systems over two years.

Canon's FPA-1200NZ2C nanoimprint lithography system, announced in October 2023, represents the only credible alternative patterning approach. At roughly $15 to $20 million per system with 90% lower power consumption than EUV, it uses direct mechanical pattern transfer rather than optical exposure. Canon delivered the first commercial unit to the Texas Institute for Electronics in September 2024, and its current specs show some significant limitations: 80 to 100 wafers per hour (versus 195+ for low-NA EUV), 14nm minimum linewidth, and 2.4 to 3.2nm overlay (versus sub-1.1nm for EUV).

Japan's Dai Nippon Printing (DNP) is targeting 2027 mass production of 1.4nm-class nanoimprint templates, but no major foundry has committed to NIL for high-volume logic manufacturing. The technology's likely niche remains repetitive memory patterns, particularly high-layer-count 3D NAND, where its cost advantage could outweigh the throughput and overlay penalties. Defect density from direct physical contact between template and resist remains the fundamental barrier to logic adoption, where a single misplaced particle can kill an entire die.

ASML revenues continue climbing

ASML's 2025 results reflect the sheer scale of its roadmap, with €32.7 billion in revenue (up 16% year-over-year), 52.8% gross margin, and €9.6 billion net income. EUV became the leading source of system revenue at 48%, or €11.6 billion, up 39% from 2024. Net bookings surged 48% to €28 billion, with Q4 2025 alone delivering a record €13.2 billion in orders. The company recognized revenue on two High-NA systems during the year.

ASML's Q1 2026 results, published April 15, show €8.8 billion in total net sales at 53% gross margin, with €2.8 billion net income. The company shipped 16 EUV and 17 immersion DUV systems in the quarter, with South Korea accounting for 45% of system sales by region and China at 19%. ASML raised its full-year 2026 revenue guidance to €36 to €40 billion, with 51% to 53% gross margins

Each NA increase delivers diminishing resolution gains at exponentially rising cost and complexity. The most likely trajectory is not a clean generational handoff but an extended coexistence: low-NA handling the bulk of EUV layers well into the 2030s, High-NA reserved for the most critical pitches at sub-2nm nodes, and Hyper-NA arriving as a targeted tool for the most extreme features, subject to workarounds for the bottlenecks we’ve discussed above.

U.S. lawmakers have revised the MATCH Act to narrow its scope after industry pushback and removed one of the most sweeping provisions that prohibited sales of cryogenic etching tools to chipmakers in the countries of concern (most notably China), reports Reuters. Yet Chinese chipmakers were not allowed to obtain these tools anyway due to existing export controls, which makes the alterations somewhat cosmetic.

The updated version of the bill eliminates a nationwide restriction on cryogenic etch equipment produced by companies such as Lam Research and Tokyo Electron, according to Reuters, which claims it has seen the revised copy of the document (which does not appear to be available on official websites). In addition, the report claims that many of the restrictions proposed in the early April version of the bill have been removed, but does not elaborate. This provision had raised concerns across the semiconductor equipment industry due to its wide reach and potential impact on global trade.

The original draft explicitly included cryogenic etching equipment as a separate type of etching equipment requiring specific export controls. Cryogenic etching tools are designed for high-aspect-ratio, extremely smooth silicon etching, where sidewall roughness must be minimized. Such tools are used primarily in front-end semiconductor fabrication to create high-precision silicon features, such as advanced transistor structures (e.g., FinFET/GAA) and specialized MEMS. In addition, they are also used in R&D environments where ultra-smooth, high-aspect-ratio silicon etching is required.

The current U.S. export controls require an export license to ship tools used to build logic chips on 14nm/16nm-class process technologies that use FinFET transistors, so cryogenic etching tools have been covered by American export rules since 2021. The existing export controls curbed sales of advanced tools to select fabs, potentially allowing Chinese chipmakers to obtain such tools for their outdated fabs. The MATCH Act proposes to curb shipments of such equipment to actual companies (thus, plugging the loophole that allowed adversaries to circumvent existing rules), so the blanket ban on selling cryogenic etching tools to countries of concern was excessive.

Reuters reports that the latest version of the bill upholds restrictions on sales of advanced wafer fabrication equipment by U.S. and foreign companies to certain Chinese semiconductor manufacturers, including ChangXin Memory Technologies (CXMT), Yangtze Memory Technologies (YMTC), and Semiconductor Manufacturing International Corporation (SMIC). The bill also maintains requirements for licenses to service equipment at covered facilities. However, the updated version no longer applies a blanket presumption that such licenses will be denied, which should ease one of the more contentious elements for ASML and Tokyo Electron.

A bipartisan group of U.S. senators has proposed a new law that would impose an almost blanked ban on exports of advanced wafer fabrication equipment (WFE) to select entities in adversary nations, a rule that would complement the existing fab-based bans. If imposed, leading China-based chipmakers like CXMT, Hua Hong, SMIC, and YMTC would lose the ability to procure advanced tools for outdated fabs and use them to advance their leading-edge facilities.

"Certain entities, including [CXMT, Hua Hong/HLMC, Huawei, SMIC, and YMTC] are engaged in efforts to produce advanced-node integrated circuits that are especially crucial for the Military-Civil Fusion efforts of the People’s Republic of China and warrant comprehensive export controls to prevent those companies from accessing items made with [U.S.] technologies," the proposal reads.

The U.S. government restricted sales of advanced wafer fabrication equipment to potential foes like China back in late 2021. Under these restrictions American companies and eventually companies from allied nations, including the Netherlands and Japan, must obtain an export license from the U.S. government to ship WFE capable of 14nm process technologies for logic, 18nm-class DRAM fabrication processes, and 128-layer or more NAND if they ship to China-based entities. The new proposal does not introduce anything new in terms of curbs. What it does is change how shipments of tools are permitted.

Today export controls regulate shipments to exact fabs that may or may not be blacklisted by the U.S. government, not entities that own these fabs. To that end, WFE makers can ship advanced machines, such as the ASML Twinscan NXT:1950i/1980Di (which can be upgraded to the sanctioned 5nm-capable NXT:2000i) to companies like SMIC as long as the latter does not use these tools for advanced process technologies. However, controlling how these tools are used is extremely complicated as Chinese chipmakers and authorities do not really endorse such audits. Meanwhile, these advanced tools are indeed used to make chips using 7nm-class process technologies, such as SMIC's N+1 and N+2.

The newly proposed MATCH Act shifts export controls from fab-based controls to a hybrid model that is company-based (and affiliation-based), though fab-level triggers will remain in place. As a result, companies like SMIC will not be able to buy advanced tools for fabs that use trailing nodes and then redirect them to their fabs capable of 7nm-class technologies.

In addition, the MATCH Act is designed to force global alignment on semiconductor equipment export controls. At first, the U.S. will pursue coordination with allied supplier countries such as the Netherlands, Japan, South Korea, and Taiwan. If that effort fails, then the U.S. will expand restrictions extraterritorially to cover foreign-made tools that contain more than 0% of American technology, or require servicing that relies on American technologies. The end goal is to close loopholes that enable adversaries to circumvent existing controls.

An avid reader who has been following U.S. restrictions on advanced fab tools will ask whether it will be possible for restricted China-based entities to get sophisticated WFE from various intermediaries that are not restricted. As far as we can tell, while intermediary entities can in theory acquire semiconductor manufacturing equipment and divert it illegally, the MATCH Act is explicitly structured to prevent circumvention via intermediaries as export controls attach not only to the initial transaction, but also to end-use, end-user, reexport, and servicing. Therefore, routing semiconductor equipment through a third-party entity would not bypass restrictions, but will instead expose all parties involved, which essentially means losing access to advanced WFE in the future and servicing of existing tools, which in turn will render these machines useless over time.

While the bill cannot eliminate small-scale leakage of advanced systems, one-off tool diversion, or black market activity, it is designed to eliminate reliable supply chains currently used by Chinese entities to get advanced fabrication equipment to build up and maintain world-class fabs.

Last but not least, the MATCH Act introduces the 75% threshold that serves as a built-in calibration mechanism that limits controls to genuine technological chokepoints that countries of concern (i.e., China) cannot produce themselves. For example, if China can meet 75% of its demand for certain tools (e.g., etching or deposition tools), then the U.S. government no longer restricts shipments of appropriate tools to China. Under the newly proposed bill, restrictions are applied where they retain strategic leverage and can be relaxed if domestic alternatives reach sufficient scale. This seems to be important for American companies that sell etching and deposition tools. For now, they maintain lead over Chinese makers like AMEC or Naura, but the latter already offers world-class tools, so once they reach scale, American companies like Applied Materials will lose strategic positions on the Chinese market, at which point the U.S. government will cease regulating their shipments to customers in the PRC.

SK hynix disclosed in a regulatory filing on Tuesday that it will purchase 11.9 trillion won ($7.9 billion) worth of EUV lithography equipment from ASML by the end of 2027, as reported by Bloomberg. The deal is the largest single EUV order ever publicly disclosed by an ASML customer, and it runs through December 2027. SK hynix said the tools are intended for mass production of next-gen products as the company races to expand capacity for AI-driven memory demand.

Bernstein analyst David Dao estimates that the order covers approximately 30 new EUV machines over two years, slightly above his prior forecast of 26. The scanners will be deployed across two facilities: SK hynix's M15X plant in Cheongju, which is focused on producing HBM chips, and the new Yongin Semiconductor Cluster, which will handle advanced DRAM. Ryu Young-ho, a senior analyst at NH Investment & Securities, told Reuters that the equipment is expected to serve both HBM and advanced DRAM production.

SK hynix accelerated the Yongin timeline earlier this year, moving the first cleanroom opening from May to February 2027. The company committed a total of 31 trillion won ($21.5 billion) to the Yongin Phase 1 fab, which will eventually house two building shells and six cleanrooms. M15X, meanwhile, began deploying wafers in February after its first clean room opened in October of last year.

ING analyst Marc Hesselink noted in a client note that the order contains a "pull-in element" designed to lock down ASML equipment supply ahead of competitors. SK hynix is likely to increase spending on the less advanced DUV lithography machines separately, where lead times are shorter at three to six months, Hesselink added.

ASML, which announced plans to cut some 1,700 managerial roles back in January, reported a €38.8 billion order backlog at the end of 2025. Samsung and TSMC are also major buyers of EUV equipment, and all three major memory makers are expanding capacity as AI infrastructure buildout continues to strain global DRAM and HBM supply.

SK hynix currently holds more than 60% of the global HBM market and is a primary supplier to Nvidia, but Samsung is ramping its own EUV-based HBM production aggressively. SK hynix announced a separate $13 billion advanced packaging facility in Cheongju earlier this year to handle the downstream assembly of HBM chips produced at M15X.

Arena has announced its first book, which is simply called Silicon. Best known for its magazine, which celebrates American ingenuity in business, technology, and civilization, Arena’s stylish and premium “coffee table book like no other” is up for pre-order now. Silicon is priced at $99, including tax and free shipping in the U.S. and Canada. Expect it to make a five-pound impression on your doormat in May.

Silicon is described by Arena, not as a dense scientific technical work, but as “an art book and anthology.” In other words, it isn’t only for semiconductor wizards like Anton Shilov. I think it will also appeal to pea-brained folk like myself, or anyone else who appreciates the visual appeal of technology, enhanced by the book’s great presentation and print quality.

On the topic of physical quality, Arena boasts that Silicon has a “special foil stamped cover, a genuine thread binding, and 384 pages of European archival paper.” The shimmering light-diffracting cover particularly hits the coffee table segment right in the bullseye.

As an anthology, readers get 10 independent chapters to absorb. The prose is liberally punctuated with “hundreds of full-page photographs of computer chips from the last 50 years,” explains the pre-order website. So, you can dip into Silicon willy-nilly for any of the 10 self-contained segments. Might we suggest some matching bookmarks?

The first chapter is called Teaching Sand to Think and was penned by Dylan Patel & Jeff Koch. You may have seen Patel mentioned on Tom’s Hardware from time to time, due to the SemiAnalysis semiconductor industry insights and reports he often shares. Other chapters cover subjects such as Moore’s Law, ASML’s Throne, the Nvidia Factor, and more.

The animated GIF in Arena’s social media posts promoting Silicon, as well as the product page’s visual carousel, provide a decent preview of leafing through this weighty tome. Its looks like it could be an essential read to discover silicon, "the element that built modernity." Furthermore, it will provide perspective to “the world of transistors, chips, and the greatest technology revolution of all time,” reckons Arena.

Employees at ASML still don't know whether they will lose their jobs, some seven weeks after the Dutch chip equipment maker announced plans to cut 1,700 management roles alongside record full-year revenue of €32.7 billion. The cuts target management positions in ASML's technology and IT departments, with 1,400 roles going in the Netherlands and 300 in the United States, representing roughly 4% of the company's global workforce.

The prolonged uncertainty is generating internal unrest, according to an ASML spokesperson who spoke to Dutch broadcaster Omroep Brabant. "People simply don't know where they stand. ‘What does this mean for me?’ they ask," the spokesperson said. "We can't answer that question on an individual level right now. It's a very difficult situation for everyone, and it's causing unrest, and we completely understand that."

According to trade unions familiar with the matter, ASML said it hopes to finalize the terms of the reorganization by April 1, with some of the affected management employees potentially offered new engineering positions as an alternative to redundancy. "We will do everything we can to keep that number as low as possible," the spokesperson said. "But it will never be completely zero."

Both of the main unions involved have rejected the April 1 target as unworkable. FNV negotiator Peter Reniers called the timeline "unrealistic," arguing ASML should instead identify where displaced employees can be redeployed internally before pushing toward a formal agreement. "There's no need to do this abruptly now," Reniers told the broadcaster.

Meanwhile, CNV negotiator Rémy Biesmans said he doesn’t expect a deal in the next three weeks either, describing the situation as a choice between resolving things quickly at the risk of getting the terms wrong, or taking longer to reach an outcome that actually protects workers. "Our goal remains to avoid forced layoffs," he said.

Cuts and expansion plans run in tandem

The unions have also questioned the logic of the cuts despite expansion plans. Eindhoven's city council approved a zoning plan amendment on March 11 that allows ASML to begin construction of a second campus at the Brainport Industries Campus near Eindhoven Airport, a site intended to accommodate 20,000 new employees. That’s nearly double the company's current Dutch headcount of around 23,000, and the first 5,000 workers are expected to move in by early 2028.

The company reported a net profit of €9.6 billion for 2025 and has guided for revenue of €34 to €39 billion for 2026, with Q4 2025 orders alone coming in at €13.2 billion, which was more than double analyst expectations. China's share of revenue, meanwhile, is projected to fall from 33% in 2025 to around 20% in 2026 as U.S. export controls continue to restrict sales of EUV equipment to Chinese manufacturers.

ASML this week reaffirmed that it is on track to release a Twinscan NXE extreme ultraviolet lithography system that features a 1000W EUV power source and can process up to 330 wafers per hour. The system, projected for sometime in 2030 or beyond, offers 50% more power than the current best EUV tool, the NXE:3800E. Such machines will greatly increase productivity and decrease costs per wafer for chipmakers, but to make them possible, ASML has had to achieve several breakthroughs.

"What was achieved — one kilowatt — is pretty amazing," Michael Purvis, ASML's lead technologist for its EUV source light, told Reuters. "We see a reasonably clear path toward 1,500 watts, and no fundamental reason why we couldn't get to 2,000 watts."

However, to get to a 1000W-class EUV source in the 2030s, ASML must develop a new three-pulse EUV light generation method that it disclosed in late 2024. The new method involves a 1μm pre-pulse that flattens the droplets, followed by a 1μm rarefaction pre-pulse that rarefies them, after which the main 10μm CO2 laser pulse turns them into EUV plasma. Previously, ASML filed a patent application for an EUV light source producing three laser pulses, according to Asianometry. For now, this three-pulse source is not a part of any shipping machine, though expect it to end up in a Twinscan NXE:4000-series scanners due later this decade.

Yet, the actual 1000W EUV radiation source will also be equipped with a new tin droplet that will almost double the number of tin droplets to 100,000 every second. This unit is also currently under development, and it will take years before it is commercialized, according to an ASML spokesperson speaking with Tom's Hardware.

Building a new laser system that comprises of a CO2 laser with a 10μm wavelength for the main pulse and two non-CO2 lasers for with ~1μm wavelength for pre-pulses and a new tin droplet generator that doubles performance as well as a new tin droplet generator with twofold performance sounds easy on paper, both these devices as well as devices that accompany them to make their work possible represent numerous major technological breakthroughs.

Increasing the number of tin droplets automatically means increasing the amount of debris that can end up on a wafer (or rather a pellicle), so they must be promptly removed, which means an all-new debris collector. While producing 1000W of EUV radiation is hard, transferring it onto a wafer is even harder, so ASML had to invent all-new high transmission projection optics, which are meant to scale all the way to over 450 wafers per hour, or toward something like 1500W. Also, increased productivity and higher performance light sources require new wafer and reticle stages, which will also be upgraded in systems featuring a 1000W light source. Last but not least, a 1000W EUV light source also calls for new resists and pellicles, so in addition to ASML itself, the whole industry needs to prep for the arrival of the company's tools featuring its latest innovations.

ASML has long planned to increase the productivity of its EUV lithography scanners to 330 wafers per hour by around 2030, a productivity level tied to a 1000W light source. Therefore, the announcement made this week outlines the technology the company invented to achieve that roadmap goal.

ASML is yet to integrate its 1000W EUV light source into its Low-NA EUV and High-NA EUV roadmaps. The company's next-generation Low-NA Twinscan NXE:4000F litho system with a production capacity of over 250 WpH and a matched machine overlay (MMO) performance of 0.8 nm for 1.x-nm-class nodes is due in 2027, followed by the NXE:4200G with productivity of over 280 WpH in 2029. On the High-NA EUV front, ASML preps the Twinscan EXE:5200C with an over 185 WpH output and a <0.9nm MMO performance next year, followed by the EXE:5400D with productivity of over 195 wafers per hour in 2029.

A group of U.S. lawmakers this week sent a letter to the U.S. State and Commerce Departments calling to reinforce restrictions on wafer fab equipment (WFE) exported to China. The group calls to restrict the sale of virtually all chipmaking tools to China. With the exception of those that can be manufactured domestically in the People's Republic of China (PRC). In addition, the group demands the U.S. to work with allied nations and ensure that they implement similar export policies, thus banning sales of all advanced chipmaking tools to the PRC.

The group led by House Select Committee on China Chairman John Moolenaar and House Foreign Affairs Committee Chairman Brian Mast sent the letter to Secretary of State Marco Rubio and Secretary of Commerce Howard Lutnick demanding to impose more robust curbs on exports of semiconductor production tools to China and use diplomacy to make allied nations follow. Right now, American companies need an export license to ship WFE tools to China-based entities. These tools that can be used to make logic chips on 14nm/16nm manufacturing technologies, produce DRAM on 18nm-class half-pitch fabrication process, and fabricate 3D NAND with 128 or more layers. At the same time, American companies can obtain an export license and supply these very tools to entities that formally do not produce the aforementioned semiconductors. The new set of rules proposed by the group prohibit to sell any WFE to China-based entities except tools that can be manufactured locally in China.

The lawmakers argue that existing controls remain incomplete as certain foreign-produced 'chokepoint tools' (i.e., advanced lithography systems by ASML and sophisticated etching and deposition tools by Tokyo Electron) are restricted only when destined for specific Chinese entities rather than being subject to broad country-level limitations.

They note that once equipment enters China, enforcement becomes difficult because verification visits require approval from Chinese authorities, which can take weeks or months to arrange, and are conducted under supervision. As a result, Chinese companies like SMIC can continue develop their process technologies using advanced manufacturing tools, whereas various entities funded by Huawei or even the federal government can reverse engineer these machines to build similar systems locally.

Reverse engineering of existing tools and subcomponents is another point of concern raised by the lawmakers. Despite the efforts of the U.S. government, Chinese companies retain access to the subcomponents of chipmaking equipment, which not only enables them to fix existing tools, but also reverse engineer these parts. Without tighter export controls on spare parts, China could eventually replace foreign equipment with locally developed alternatives, lawmakers believe.

"We urge the Administration to press allies to implement countrywide controls on key chokepoint semiconductor manufacturing equipment and subcomponents: that is, all equipment and subcomponents that China cannot produce indigenously," the letter reads. "This engagement should include clear and reasonable deadlines, after which the United States should be prepared to act to close remaining gaps itself if necessary, including by prohibiting the use of U.S.-origin components in the production of chokepoint tools destined to China."

The letter also mentions servicing of WFE as a potential area for even tighter regulation as now these rules adhere to export control rules, which means that certain restricted advanced systems can still be serviced as long as they are installed at an approved buyer. As these systems require ongoing maintenance and technical support to remain operational, limiting servicing could be a way to reduce practical lifespan of already installed equipment.

"The window to secure America's semiconductor advantage is narrowing," the letter concludes. "We request a briefing within the next month on the Administration's strategy for securing allied cooperation on countrywide controls on chokepoint semiconductor manufacturing equipment and components and the timeline for achieving this goal. We stand ready to work with you on a bipartisan basis to ensure our export control regime and the alliances that support it are equal to this challenge."

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

Despite the massive AI infrastructure build-out and a bumper earnings call on Tuesday, ASML, the only company in the world that manufactures the tools that make the cutting-edge chips that are currently in high demand, announced that it plans to lay off some of its employees. According to the company’s announcement, it’s streamlining its Technology and IT & Data organizations, with the former moving “from a project/matrix setup to one where most of our engineers will be dedicated to a specific product and module.” This reorganization is meant to simplify processes and decision-making throughout the company.

“As a result of these proposed changes, some roles — mainly at the leadership level — may no longer be required,” ASML said in its press release. “At the same time, to retain our engineering capability, we will create new engineering jobs to strengthen existing technology projects and embark on new ones to support our own and our customers’ growth plans. While this will allow some of our impacted colleagues to move to new roles, we have to acknowledge that some will leave ASML as a result.” This isn’t just a minor trim for the two departments, too. Even though ASML still plans on creating roles in Manufacturing, Customer Support, and Sales, it expects to reduce its headcount by 1,700 positions, mostly affecting the Netherlands and the United States.

ASML has a practical monopoly on chipmaking tools, and it stands to benefit from the continuing growth of the semiconductor industry. Despite that, it seems that it wants to maintain a lean and efficient workforce, even as it’s growing its headcount and footprint with its Eindhoven expansion expected to be online by 2028. “As our FY 2025 financial results demonstrate, we are choosing to make these changes at a moment of strength for the company,” the company stated. “Improving our processes and systems will allow us to innovate more and innovate better, generating further responsible growth for ASML and our stakeholders.”

This is one of the first major announcements of layoffs in the tech industry for 2026, which has been hit with over 100,000 job cuts in just the first half of last year. Intel took the lead with the layoffs, prompted by the financial disaster that first came to light in 2024, with Microsoft and Meta following closely behind. However, these job losses aren’t caused by a contraction of the tech industry — instead, it’s driven by industry shifts, with AI and automation taking over many entry-level positions. ASML’s announcement, though, is different, with many of the affected personnel expected to be from leadership positions — mostly middle managers and up.

China has quietly introduced a rule under which chipmakers must use at least 50% domestically produced equipment when adding new semiconductor manufacturing capacity, reports Reuters. The move could potentially reshape procurement decisions, accelerate local tool adoption, and squeeze foreign suppliers out of the Chinese market.

However, there are a number of catches with this requirement: firstly, authorities grant waivers for advanced fabs; secondly, Chinese industry cannot produce enough litho systems, if the numbers via Reuters are accurate.

The rule is not published in any formal regulation, but in recent months, companies seeking government approval to build or expand fabs have been instructed to prove that at least half of their equipment spending is directed to Chinese suppliers. Applications that fail to meet the threshold are typically rejected, according to people familiar with the process. In fact, officials told applicants that 50% is a baseline rather than a target as the long-term objective is to exclusively use domestic wafer fab tools.

However, regulators allow case-by-case flexibility when domestic alternatives are constrained, which is perhaps the main catch about the rule. The requirement is applied most strictly to production lines used to make chips via mature process technologies, whereas advanced nodes receive temporary exemptions due to gaps in local tool availability, particularly when it comes to lithography equipment.

Speaking of lithography tools, state-linked chipmakers placed 421 orders for domestically produced lithography machines and their components this year at combined value of about ¥850 million ($121.3 million), according to Reuters. While the number 421 looks substantial, it includes both new systems and spare parts, which does not give an idea how many new tools were actually ordered.

To put the value into context, ASML's dry ArF tools used to produce chips on mature nodes cost around $27.9 million per unit on average (based on the company's Q4 FY2024 results), whereas KrF systems cost around $14.46 million per unit. By contrast, ASML's latest immersion DUV (ArF) lithography scanners used to make chips on advances process technologies cost $82.5 million per unit on average. With Chinese-made litho tools we do not usually talk about immersion lithography, but rather about dry ArF or KrF machines (China's best demonstrated tools are 28nm-capable, but these do not seem to be in mass production now). That said, the combined value shows that the Chinese industry can only produce rather cheap litho systems for outdated process technologies and even they are hardly made in significant quantities.

$121.3 million is approximately eight ASML KrF litho machines. Even if Chinese manufacturers have managed to cut costs of these mature tools by half (which is probably impossible), it means that they could only produce 16 of such tools in 2025. By contrast, ASML built 152 KrF steppers, 65 i-line tools, 28 ArF dry scanners, 129 ArF scanners, and 44 EUV scanners in 2024.

A report this week claimed that a covert laboratory in China had managed to reverse-engineer an extreme ultraviolet (EUV) lithography scanner, one of the most complex machines on Earth, shocking many industry observers. However, China's 'Frankenstein' EUV chipmaking tool is known to be cobbled together from many disparate parts and not fit for manufacturing of any sort. In fact, the experiment hasn't even produced a single chip.

When you have been around long enough in the tech industry, one thing that you learn is that all the breakthroughs that happen around are a result of years, if not decades, of hard work of multiple teams. Then, bringing these breakthroughs to mass production takes another five to 10 years, depending on the involvement of big companies like Intel, which are well-suited to translate scientific innovations into production as quickly as possible. Here's why China's experimental EUV machine is still many years away from producing even a single chip.

Can you steal a blueprint for an EUV tool?

The report about a reverse-engineered EUV lithography machine that produces EUV radiation using the same CO2 laser-produced plasma (LPP) method that ASML uses reminded me of a scene in Christopher Nolan's movie 'Oppenheimer', when Lewis Strauss implies that the blueprints of the American nuclear bomb were stolen based on the fact that Russians have used a plutonium implosion device, like the one built in Los Alamos.

Indeed, blueprints and detailed scientific information from the U.S. Manhattan Project were stolen by Soviet spies. But while in the case of the atomic bomb, there were actual blueprints and detailed scientific information in Los Alamos, so seven convicted Russian spies had somewhere to steal from, there is no single detailed blueprint of an EUV scanner, according to a source with knowledge of the matter.

This may be correct, as the current Twinscan NXE platform is a product developed worldwide by a constellation of partners. While there is no doubt that China has a widespread spy network, stealing blueprints from multiple ASML facilities worldwide is difficult. What's even more challenging is stealing blueprints of parts from thousands of ASML suppliers worldwide, then assembling a functioning EUV lithography tool.

To add some context, Cymer — the inventor of ASML’s EUV LPP-based light source — is an American company (subject to all imaginable export controls) that ASML acquired in 2012. Cymer is now an internal part of the ASML supply chain. It provides the complete EUV light-generation subsystem, including the LPP source (which generates 13.5-nm radiation), a high-performance CO2 laser system, tin-droplet generation with a targeting unit, a debris-mitigation unit, and the EUV radiation collector. The hardware itself is precious, but so are the associated proprietary firmware, control software, and diagnostic tools required to continuously deliver stable, high-performance EUV radiation to the scanner for high-volume manufacturing (HVM).

Even then, Cymer's EUV source relies on a high-end ultra-precise mirror, coated with multilayer molybdenum-silicon (Mo/Si) stacks developed and made by Carl Zeiss in Germany. Since EUV radiation can be absorbed by almost anything, it also requires specialized mirrors from Carl Zeiss.

Without illuminator optics (which shape and uniform the beam using faceted mirrors) and projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors), the EUV source itself is useless in isolation. Even if one can steal blueprints of Carl Zeiss optics, replicating them is hard, if not impossible, because it requires utmost precision, and for now, Carl Zeiss is the only company in the world that can produce such precise optics hardware.

Can you steal an entire high-tech supply chain?

Beyond optics, ASML relies on thousands of suppliers across the United States, Japan, and Europe to deliver critical subsystems, which it then integrates into a single machine.

In the U.S., ASML’s Cymer division develops the laser-produced plasma light source, as mentioned above. Japanese companies supply ultra-precision mechanical components, sensors, and materials, including EUV photoresists, while European firms provide vacuum systems, precision structures, and specialty materials. Each supplier owns proprietary process technology that ASML itself does not fully control, which highlights that EUV lithography is ultimately sustained not by one company, but by an ecosystem whose collective intellectual property and integration experience form one of the deepest and most crucial technological chains in the semiconductor industry.

ASML's key ability is to orchestrate this ecosystem and integrate tens of thousands of externally developed parts with its own hardware and software into a machine that operates at nanometer-scale tolerances in high-volume manufacturing. Therefore, replicating an EUV lithography tool requires far more than copying a scanner's design (which is impossible as there is no single blueprint of an EUV machine and the company does its best to keep knowledge of its engineers the unit compartmentalized): it demands recreating an entire global supplier network, the co-development culture that binds it together through groups such as imec (which no longer works with Chinese clients), and the decades of trial-and-error that transformed fragile subsystems into a tool that is widely used for high-volume chipmaking.

Can you even DIY a lithography tool?

Considering the versatility of ASML's scanner design, as well as its omnipresence throughout the industry, there are numerous loopholes in obtaining certain parts of the machinery. Banks or chipmakers usually auction off older lithography equipment, and spare parts for advanced tools can be found on open markets (even eBay yields results for spares).

There is an additional rumor claiming that China intercepted a Cymer EUV radiation source while it was in transit, recorded the part numbers, then obtained them from various sellers or acquired refurbished scrap parts, and assembled a machine in a covert lab. Because not all parts can be acquired on the open market and their condition is unknown, this Frankenstein EUV tool does not work, according to Reuters.

Yet, because ASML's tools are designed to be easily serviced or upgraded in the field and spares appear readily available, Chinese chipmakers — such as SMIC — have managed to upgrade some of their existing tools using components obtained from third parties. For example, they have obtained stage and overlay performance data for the Twinscan NXT DUV lithography tools to make them more suitable for producing chips at advanced nodes, such as 7nm-class process technologies. It goes without saying that such Frankensteined upgrades and tools may not meet all of ASML's stringent standards for quality and reliability. If they increase SMIC's output of advanced wafers by 10%, such modifications may be worth the risk.

The modular nature of ASML's Twiscan platforms simplifies production and upgrade processes. Still, it also means that many of those components can be purchased by unauthorized buyers, such as China-based chipmakers sanctioned by American and European governments. In theory, this means that a Chinese chipmaker could DIY their advanced lithography tools from ASML using components available openly or refurbished in-house, which would, of course, take an incredible amount of time and effort, but would still get them the necessary hardware. However, even obtaining the hardware itself does not guarantee that it functions as intended, as ASML's tools are controlled by proprietary software and firmware that are not publicly available. As a result, even if Chinese specialists obtain the hardware, they will not be able to fully reverse-engineer it to meet ASML's standards.

All in all, it is not surprising that while Chinese scientists have managed to lay their hands on some of the components of ASML's EUV scanner, they have struggled to replicate the tool itself, as they lack a supply chain to produce high-tech parts. They also lack software and firmware that control these components, and therefore, a deep understanding of how they function when working in concert.

IMEC has successfully demonstrated the full wafer-scale fabrication of nanopores using ASML’s state-of-the-art extreme ultraviolet (EUV) machines. Described by ASML’s Product Communications Manager as an “unexpectedly awesome biomedical application” of his firm's machinery, this could be an important advance due to the molecular sensing possibilities nanopores open up.

The qualities of nanopores are of great interest in biomedicine. As you might have determined from the etymology, nanopores are essentially tiny holes, just a few nanometers wide. In more relatable language, perhaps, these pores have diameters that make them roughly 10,000 times finer than a human hair.

What is the use of such tiny perforations?

Nanopores can be used by biomedical sensors due to the way molecules interact with them. The science behind their use in detection is:

• An ionic current flowing through the nanopores is measured,
• As molecules pass through, they create modulations giving away their size, structure, charge, and interactions,
• Different molecules can thus be detected from their distinct electrical signatures, with high sensitivity.

In this way, these EUV fabricated nanopores can act like molecular checkpoints for biomedical sensing. They can detect and determine individual molecules like a virus, protein, or DNA etc. That’s a great feature for accurate molecule identification and analysis. Furthermore, adjusting the solid state nanopore size can also be useful for filtration and molecular data storage applications, indicates IMEC.

Why use EUV machinery?

Current nanopore production methods are claimed to be slow, limited to the lab, and expensive. IMEC’s paper describes how it successfully fabricated “highly uniform nanopores with diameters down to ~10nm across full 300mm wafers.” This breakthrough – encompassing mass production, precision, and reproducibility - should put an end to the delays in adoption of nanopore-based sensors.

While we applaud the research, and the idea of making precision nanopores more accessible to medical equipment makers, we also understand that ASML EUV equipment isn’t that easy to acquire. Such is the demand for this high-tech machinery by the booming semiconductor industry, we hope there remains some chance for biomedical production runs like nanopore production.

However, we are slightly reassured by the researchers highlighting that this is a step towards “cost-effective (mass) production,” as surely they will have assessed the costs of getting a 300mm wafer full of nanopores produced at this time.

Edit 12/22/2025 4:15am PT: Corrected ASML employee's title.

A secret laboratory in China has quietly assembled a prototype extreme ultraviolet (EUV) lithography system and is now testing it stealthily, which means that the country may be close to replicating the most advanced technology that currently exists on Earth, reports Reuters.

The tool was reportedly developed by reverse engineering existing scanners from ASML and is said to be on-track to make prototype chips in 2028. If the information is correct, then Chinese scientists have made numerous breakthroughs across multiple disciplines in just a few years instead of decades, a scenario that appears extremely unlikely. Further analysis of the report indicates that China's laboratory is far from completing the tool, meaning that the country is years away from making chips using EUV lithography.

China's alleged EUV scanner

The system was reportedly completed in early 2025 inside a highly secured facility in Shenzhen and occupies nearly an entire factory floor. The Chinese machine reportedly generates EUV light with a wavelength of 13.5nm using the same laser-produced plasma (LPP) method as ASML Twinscan NXE machines, not the particle accelerator-based steady-state microbunching (SSMB) method designed at Tsinghua University or discharge-produced plasma (DPP) technology developed at Harbin Institute of Technology (HIT), which might prove the point that the system was reverse-engineered or at least contains a substantial amount of technologies pioneered by ASML.

ASML's laser-produced plasma (LPP) method uses tiny molten tin droplets, roughly 25–30 microns in diameter, which are injected into a vacuum chamber at a rate of about 50,000 droplets per second. Then, a high-power CO₂ laser first fires a low-intensity pre-pulse at each droplet, flattening it into a disk-like shape, followed by a more powerful main pulse that vaporizes the flattened tin and creates a superheated plasma with temperatures exceeding 200,000°C. This plasma emits isotropic EUV light, which is then collected by a large multilayer collector mirror and directed into the lithography system's reflective optics for patterning silicon wafers. This process repeats tens of thousands of times per second.

The machine is reportedly larger than the original, but it is operational in the sense that it can generate EUV radiation. However, it has not progressed to make usable chips as it still struggles to replicate 'the precision optical systems' features by Twinscan NXE systems. Furthermore, there is no word about power of the EUV light source, a crucial parameter that defines whether a tool can or cannot be used for volume production.

Not operational, for now

The report clearly states that the Chinese EUV scanner cannot currently be used to make chips, but the Chinese government reportedly wants the first chip prototypes to emerge in 2028, two or three years down the road. However, a more realistic target is 2030, four or five years from now, which is a long time. Meanwhile, from the report, it is not completely clear what stage the Chinese team is at today.

The report does not disclose which specific components of the optical system are the primary bottlenecks, as the article groups them rather generally. In particular, it is uncertain if the alleged EUV tool struggles to replicate the ultra-precise collector mirror system coated with multilayer molybdenum-silicon (Mo/Si) stacks, illuminator optics (which shapes and uniforms the beam using faceted mirrors), or projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors). ASML outsources the development and production of these components to Carl Zeiss from Germany. If the developers failed to replicate the collector itself, then the rest of the machine can hardly be called an EUV lithography system, as technically, the only thing they have is some kind of light source that they have yet to learn how to use. Yet, even if the developers cannot replicate illuminator optics or projection optics (suggesting that the collector itself is there), it still means they do not have even a poorly working EUV lithography tool, but rather a set of certain components.

When talking about advanced lithography equipment, we must keep in mind that such tools rely on seamless integration of sophisticated light sources, advanced optics, ultra-precise mechanical engineering, complex control software, and specialized materials, all of which must function reliably within nanometer-scale tolerances demanded by modern chip manufacturing. The story has no word about the state of the mechanical systems of the alleged tool: we know nothing about the wafer stocker system, wafer stages, or reticle stages, all of which are crucial for operation and yields.

To put China's EUV efforts into perspective, the secret lab is not even close to building an alpha tool. For now, what the Chinese lab has cannot even put the light on a wafer, save for printing lines and spaces, something ASML's tool could do in 2006, about 11 years before the company shipped its first Twinscan NXE:3400B system meant for high-volume manufacturing. Of course, reverse engineering certain components can give Chinese engineers a speed boost, but it remains to be seen how significant this one is going to be.

Reverse engineering an ASML Twinscan NXE?

According to Reuters's sources familiar with the effort, the Chinese EUV tool was 'developed' by a team that includes former engineers from ASML and recent university graduates, who allegedly reverse-engineered the company's EUV machines. The secret lab was so stealthy that its employees were given fake IDs to avoid detection of their concentration in one place by foreign spies.

Yet, it is unclear how any engineers from China could reverse engineer an EUV lithography scanner, as the Dutch company has never supplied one to China and hardly taught personnel from China how to service its EUV systems that are not allowed to be shipped to the People's Republic.

Reverse engineering a machine that contains over 100,000 parts is a hard task that takes hundreds of engineers with knowledge of the matter, which is why the secret entity led by the Government of China hired not only former engineers from ASML China, but also former employees of the Dutch company from elsewhere, presumably from Europe, Taiwan, and the U.S. For example, Lin Nan, formerly responsible for EUV light source technology at ASML, now leads a team at the Chinese Academy of Sciences’ Shanghai Institute of Optics that has filed eight EUV-related patents in just 18 months. Yet, this may mean that he uses his experience and knowledge rather than trying to replicate what he did at ASML or reverse engineer what he did at ASML due to the absence of an EUV scanner in his lab.

“It makes sense that companies would want to replicate our technology, but doing so is no small feat,” a statement by ASML published by Reuters reads.

The report says that around 100 recent university graduates are tasked with reverse-engineering parts from EUV and DUV lithography tools, with each workplace monitored by a dedicated camera that records the disassembly and reassembly process, an important part of the whole China's lithography program, according to the report. Employees who successfully put components back together receive bonuses. Yet again, a Twinscan NXE tool is a mechanism consisting of over 100,000 parts working together, not just a sum of all parts.

To sum up, China has reportedly built a secret prototype EUV lithography system and begun testing it, which suggests that the country may be closer to reproducing the most advanced chipmaking technology in existence than previously believed. However, details provided by the report indicate that China is still years — if not a decade — away from making chips using EUV lithography.

The machine can generate 13.5-nm EUV light using the same laser-produced plasma (LPP) method employed by ASML, which may demonstrate extensive reverse engineering of Western technology rather than the use of alternative domestic approaches. However, the tool is significantly larger than commercial systems available today, it cannot produce usable chips, and appears to struggle with other elements of EUV lithography, particularly ultra-precise optics supplied to ASML by Carl Zeiss. In fact, details about the system like light source power, optical subsystem maturity, and the state of critical mechanical components remain unclear.

While China expects first prototype EUV chips to emerge in 2028, Reuters's sources suggest 2030 is more realistic. Yet, the whole effort relies heavily on recruiting former ASML engineers and reverse engineering parts from existing EUV and DUV tools, which are not only hard to develop, but are extremely hard to make. Meanwhile, there is no word whether the current team responsible for disassembling and reassembling components can actually make an ultra-complex machine consisting of over 100,000 parts work flawlessly to produce semiconductors in high volumes.

Intel announced that it had installed ASML's Twinscan EXE:5200B, the industry's first High-NA lithography tool with 0.55 numerical aperture projection optics made for commercial chip production. The tool has passed acceptance testing and will be used for development of Intel's 14A fabrication process, which will be the world's first node to rely on High-NA EUV scanners for its most critical layers. The achievement indicates that High-NA EUV lithography is moving beyond early experimentation toward high-volume manufacturing (HVM).

ASML's Twinscan EXE:5200B builds on the 1st Generation EXE:5000 platform that Intel received in 2023 for its Oregon R&D fab. The new tool can 'print' chips with an 8nm resolution, enabling scaling beyond which is currently possible with Low-NA EUV tools that offer a 13nm resolution without using multi-patterning. Unlike the EXE:5000, the EXE:5200B is capable of processing 175 wafers per hour at a 50 mJ/cm² dose (up from 185 wafers per hour at at a 20 mJ/cm² dose) and achieves overlay accuracy of 0.7 nanometers, a critical parameter as feature dimensions continue to shrink.

To boost performance, the scanner integrates a higher-power EUV light source to enable faster wafer exposures at a 50 mJ/cm² dose. This in turn supports workable resist/process windows with strong image contrast while minimizing line-edge roughness (LER) and line-width roughness (LWR), which tend to be challenging with modern production nodes.

ASML and Intel did not limit their work to the optics and light source. They also reworked the wafer stocker system, which is responsible for how wafers are stored, queued, and moved in and out of the scanner. For next-generation tools, this component of the system has a direct impact on both productivity and patterning accuracy.

The updated stocker design improves lot flow and wafer handling to make sure that wafers arrive at the exposure stage in a more predictable state. At the same time, it provides tighter thermal control, keeping wafers and carriers at stable temperatures before and after exposure, an important factor as even tiny temperature variations can cause wafer expansion or contraction, leading to overlay errors, which in turn leads to an increase in defects and decrease of yields.

In addition, by reducing thermal and mechanical variation, the new architecture helps to minimize drift over long runs, thus enabling the scanner to maintain stable behavior and reducing the necessity for frequent recalibration. This stability will be particularly important for multi-pass and multi-exposure patterning, which will be inevitably used in the coming years for sub-1nm process technologies.

One of EXE:5200B's parameters that is hard to overestimate is its overlay performance of 0.7 nm, which was achieved by advancements of stage control, sensor calibration, and environmental isolation. Overlay performance is crucially important for next-generation process technologies as even tiny alignment errors can translate into yield losses.

It is necessary to note that ASML's Twinscan EXE:5200B is not just another EUV scanner in Intel's fab, but rather a foundation that is expected to enable Intel to regain its leadership in the semiconductor industry.

To use the new lithography tool, Intel is conducting parallel work on masks, etch processes, resolution enhancement techniques, and metrology that must be co-optimized to extract the maximum value from High-NA EUV patterning.

Intel says that its High-NA tools will enable more flexible design rules, reduce the number of patterning steps, lower mask counts, shorter cycle time, and increased yields thanks to lack of multipatterning with 14A and more advanced process technologies. Meanwhile, as Intel learns how to use High-NA EUV tools and gains valuable HVM experience, it will be able to insert High-NA EUV multi-patterning when it needs to in the sub-1nm era without significant effect on yields.

Dutch company ASML — famously the sole producer of the latest photolithography machines for fabricating cutting-edge chips — is under fire for selling hardware to a Chinese defense firm with ties to the ruling party.

Although ASML claims that the technology it sold to Chinese chip manufacturers was old and not able to "produce state-of-the-art chips," as reported by Nos,analysts have still raised concerns over its dealings with a firm developing quantum technologies, which could have implications for military technology development and deployment.

The Dutch government has long been aware of the risks posed by China's access to chip design software and manufacturing hardware. That's partly why there's been such fallout recently around Chinese involvement with Dutch chip firm, Nexperia. But Dutch firm ASML may have had far greater dealings with Chinese businesses, and it's raising more than a few red flags.

Nos claims that the business that purchased the ASML chip manufacturing component was a division of China Electronics Technology Group Corporation (CETC), a Chinese state-owned company that is a key component in the country's military industrial complex, producing key equipment for rocket systems and drones. It has also reportedly worked on the Chinese space program and fabricates chips for military use.

Nos has also accused ASML of supplying a deep lithography system (DUV) in its entirety to the Shenzhen International Quantum Academy. This is arguably more notable, as the Dutch Military Intelligence and Security Service has explicitly warned against China's development of quantum technologies.

Although ASML's DUV machines are older designs that produce chips in resolutions of around 38nm (the latest dual-stage extreme ultraviolet (EUV) systems can manage 8nm), analysts are still concerned about the direct provision of such systems, considering the concerns over Chinese technological development.

ASML has said it won't comment directly on sales to customers, but has suggested that what it has transferred to China is not cutting-edge, describing it as "old technology that can't be used to produce state-of-the-art chips." It added: "It is impossible for suppliers, such as ASML, to assess if a chip manufacturer in China should, or should not, be subject to export controls. National security is the responsibility of governments."

Indeed, it highlights that the designs it has sold to Chinese companies are not subject to export controls. This was confirmed when Nos spoke to the Dutch Ministry of Foreign Affairs.

"Not all high-tech goods are, by definition, sensitive and subject to authorization under the export controls policy," it said in a statement. "This is also the case for parts of lithography machines. Lithography machines contain a great deal of parts, technology, and software. All those parts are needed for a machine to work, but not all parts play a crucial/strategic role."

That said, Nos claims to have spoken to industry experts who suggest the parts sold to Chinese companies were, in fact, essential for the operation of certain fabrication machinery and should be considered for export controls.

"The problem is that the Dutch government does not have any control over this export of parts", says Judith Huismans, China expert for RAND Europa and former head researcher for Datenna. She suggested governments should consider export controls for parts, too: "That way, you are not saying that ASML can no longer export anything to China, but it will give the government more control and tools."

According to a new report, ASML reportedly offered to provide the United States with information about its Chinese customers. The offer came after it was caught selling more machines that went against an agreement stopping the sales of extreme ultraviolet light (EUV) and deep ultraviolet light (DUV) lithography machines to China.

According to NL Times, the Netherlands and the U.S. agreed in January 2023 that the former would stop selling and exporting its DUV lithography machines (with EUV machines already banned) to the U.S. rival starting in September 2023, with the ban taking full effect by January 2024. In the meantime, there was a gentleman’s agreement between the two nations that ASML would only ship a limited number of DUV machines that it was contractually obligated to deliver, and stop further sales of these devices.

However, the book De belangrijkste machine ter wereld, which translates to “The most important machine in the world” [machine translation] and was written by former Bloomberg journalists Diederik Baazil and Cagan Koc, says that ASML CEO Peter Wennink allegedly sold more machines than agreed in the intervening period, breaking the pact between the two nations. Former Dutch Prime Minister Mark Rutte told Wennink that his company “was venturing into dangerous territory” and that the Netherlands government felt misled and humiliated. He also said that Washington demanded they regain its trust, and that it was in the company’s best interest to do so.

Aside from restricting the sale of its equipment, the U.S. also sought to block ASML from servicing machines already deployed in China. However, instead of an outright ban, the ASML CEO suggested that the company be allowed to continue its services to its Chinese clients while also making its engineers report on the developments within these companies.

ASML’s employees have unique opportunities because its people have regular access to China’s fabs and also frequently work with Chinese engineers, allowing them to have unique insight into what’s actually going on behind the scenes. “ASML could be Washington’s eyes and ears in China,” the book said, quoting a senior U.S. government official. Of course, ASML denied making this offer, with its spokesperson telling NL Times that it was an inaccurate portrayal from the two authors.

Many are often wary of governments, whether it be Eastern or Western, taking advantage of and coercing companies into revealing data and information about their customers. But, if this account is true, this is the other way around and could prove damaging to ASML. After all, even though the company produces some of the most advanced lithography machines in the world, it must still maintain a reputation that it can be trusted — otherwise, its customers might be forced to look for alternatives because of the fear that their secrets will be revealed, whether to public entities or private institutions. Besides, any company offering customer data to anyone, even a state, is likely breaking several data privacy laws and is also betraying public trust.

This is likely one of the reasons why the U.S. government is wary of the dominance of Chinese companies within its borders. Beijing passed its National Intelligence Law in 2017, which requires all institutions and individuals to cooperate with Chinese intelligence agencies. Although there are other reasons, this law is probably one factor that Washington considered leading to the 2019 Huawei ban, with other giants like drone-maker DJI and networking hardware manufacturer TP-Link also facing potential sanctions.

Lowering defect densities and increasing yields are the key challenges for chipmakers and chip designers who use hundreds of methods for both tasks. This is because semiconductor fabrication technologies involve thousands of steps, and each can affect defect rates and yields. A recent discovery by researchers at Chinese universities has revealed how resists behave during development and how the post-exposure bake (PEB) step can reduce defect density by up to 99% in some cases, according to a paper published in Nature. However, despite these bold claims, the study has dubious practical use.

Researchers from Peking University and Tsinghua University have managed to visualize how photoresist molecules dissolve, migrate, and entangle within developer liquid during the pattern-forming (development) step. To do so, the team used cryogenic electron tomography (cryo-ET) to reconstruct the true 3D structure of photoresist polymers in their hydrated state at sub-5nm resolution.

The study revealed that most photoresist molecules accumulate in clusters at the gas–liquid interface rather than being evenly distributed in solution, which generates defects. The scientists claim that a slight increase in post-exposure bake (PEB) temperature — from 95°C to 105°C in their case — and maintaining a continuous developer layer prevented these clusters, cutting defect density on 300mm wafers by over 99% using existing resists and DUV equipment.

However, it is worth noting that chipmakers carefully select PEB temperatures for each process technology to achieve the best possible results, which limits the practical implications of the research.

To make it easier to understand what was discovered, here's a sequence of steps within a lithography step.

1. Coating: The wafer is spin-coated with photoresist.
2. Exposure: Ultraviolet (UV) or Extreme Ultraviolet (EUV) light passes through a mask to selectively expose regions of the resist.
3. Post-Exposure Bake (PEB): The exposed resist is gently heated to activate the acid-catalyzed chemical reactions that change solubility.
4. Development: The wafer is rinsed with a developer solution (often TMAH in water for DUV), which dissolves the exposed or unexposed parts of the resist, depending on the resist type, to create a thin liquid film of developer and form the patterns. This step was the focus of the research.
5. Rinse and Dry: The remaining pattern is cleaned and dried for subsequent processing.

The study in the development phase discovered that these photoresist molecules form weak, reversible entanglements that lead to microscopic clusters, which turn out to be the hidden source of pattern defects seen on processed semiconductor wafers.

A hidden process

In immersion and EUV lithography, the developer's liquid film dissolves light-exposed regions of the resist, transferring the pattern to the wafer. While the process is well known across the industry, until now there was no clear understanding of the microscopic behavior of chemically amplified resists (CARs) during pattern development, as existing methods such as scanning electron microscopy (SEM) could only observe dried residues or indirect effects. As a result, process engineers usually rely on trial-and-error tuning of resist chemistry and developer composition, since nobody has observed the real-time behavior of photoresists during development.

Instead of using SEM or atomic-force microscopy, the researchers used a cryo-electron tomography tool — usually used in structural biology to study cells, protein complexes, or viruses in frozen states — to visualize the behavior of photoresists inside a developer liquid at nanometer resolution. To do so, they had to go to great lengths in sample preparation, vitrification speed (the cooling rate at which a liquid changes state without crystallizing), and electron-beam control.

For their research, the scientists used a poly(methacrylate)-based CAR, which is widely used in 193nm immersion and 13.5nm EUV lithography.

An observation

Cryo-ET imaging revealed that the CAR polymers — frozen in their natural liquid state — were preserved as flexible, thread-like chains with random coiled shapes. Analysis of the polymer density revealed that the concentration decreased sharply with depth: in 25nm– 100 nm-thick films, about 80% of the polymer mass accumulated near the gas–liquid interface. Hence, contrary to long-standing assumptions, the resist polymers were not evenly dispersed in the developer but were concentrated at the film surface, where they later formed clusters that caused pattern defects. The same pattern was observed with other resists (e.g., designed for 248nm and 365nm exposures) demonstrated the same pattern, but this was never a problem until recently. Control samples with only the developer showed no surface signal, confirming that the effect came from the polymers themselves.

Further 3D reconstructions (combination of hundreds of low-dose electron images taken at different tilt angles) showed that inside the film, 12nm-long polymer chains stayed mostly separate, while near the surface they gathered into 30 – 40nm clusters, dimensions well above the sizes of killer defects in modern technologies.

However, these clusters are reversible by heat and are not observed in real life. In fact, killer defects in modern nodes are an order of magnitude smaller, which implies that the clusters of CAR molecules are already mitigated by leading chipmakers in their cutting-edge nodes.

Furthermore, while increasing post-exposure bake (PEB) temperature from 95°C to 105°C disrupts the cohesive interactions and helps to get rid of some defects with certain manufacturing technologies, this is an absolute yield killer for modern fabrication processes that rely on EUV lithography.

Good for DUV, catastrophic for EUV

In Deep Ultraviolet (DUV, 193nm immersion) lithography, a PEB at around 105°C is well within the normal operating range for CARs based on poly(methacrylate). These resists form features roughly 20 nm – 40 nm wide, and their photoacid diffusion lengths (about 10 nm – 20 nm) remain small enough relative to those features to preserve resolution. At 105°C, the additional thermal energy slightly increases polymer mobility and acid diffusion, enabling more complete chemical reaction and smoother dissolution during development, which helps reduce residues and improve pattern uniformity, thus reducing defects and maintaining yields. However, in some cases a a PEB at around 105°C increases line-edge roughness (LER) and line-width roughness (LWR), which leads to degradation of critical dimension uniformity (CDU), which means that it should not be used for critical layers.

However, in EUV (13.5 nm) lithography, the situation is completely different. EUV resists are typically baked at 80°C–95°C to carefully balance acid mobility and reaction completion, maintaining critical-dimension control. EUV CARs must define features as small as 13nm, so even a few nanometers of acid spread can destroy pattern fidelity. Raising the PEB temperature to 105°C would greatly accelerate acid diffusion, broaden the reaction zone, and significantly increase LER/LWR, thereby blurring the fine features defined by the EUV exposure and potentially creating defects. It also increases stochastic variation by over-reacting CAR polymer chains unevenly, which leads to other defects.

The lowdown

While the study offers valuable microscopic insight into how photoresist polymers behave in developer films, its practical impact on semiconductor manufacturing is limited, to put things mildly. Increasing the PEB to 105°C is already within the normal safe range for DUV lithography and therefore not a breakthrough, which is why we do not see 30nm–40nm defects with modern DUV-based nodes. Meanwhile, the same temperature adjustment is unsuitable for EUV processes, as such temperatures can severely degrade resolution and yield.

As a result, the work is scientifically impressive, as it confirms mechanisms that chipmakers have long managed empirically. However, it offers no new solutions applicable to advanced nodes. Then again, if scientists from Intel, Samsung, or TSMC use cryo-ET as well, they might come up with something that leads to an actual breakthrough.

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American startup Substrate is developing a new X-ray lithography (XRL) system, powered by a particle accelerator-based light source, that promises superior performance and cost efficiency compared to standard EUV lithography, aiming to achieve resolutions equivalent to ASML's 2nm-class processes. The firm also claims it can advance beyond that. Substrate also claims that its efforts will be cheaper to produce than the competition's and will offer finer resolutions before 2030, as the company detailed on its website.

However, the tool that Substrate is developing does not appear to be compatible with existing equipment and production flows, so the company will have to reinvent the whole supply chain to be successful. However, Substrate does not plan to sell its tool, but to build its own fab and provide foundry services.

Expensive tools = expensive chips

As integrated circuit features are getting smaller, chipmakers are using increasingly intricate lithography tools that now cost around $235 million for an ASML NXE:3800E Low-NA EUV scanner or around $380 million for an ASML EXE:5200B High-NA EUV scanner. As a result, fabs are becoming increasingly expensive to build, and chips are becoming more expensive to produce.

Substrate models that a leading-edge fab will cost around $50 billion by 2030, leaving semiconductor production to a handful of companies with very deep pockets. Furthermore, such fab expenditures are expected to increase the cost of a 300-mm wafer, which it claims could balloon to $100,000 when using leading-edge fabrication processes. This will make the development and production of advanced chips prohibitively expensive for small companies. Substrate intends to change that and reduce wafer pricing to just $10,000 by 2030.

"At Substrate, we have a pathway to reduce the cost of leading-edge silicon by an order of magnitude compared to the current cost-scaling path we are on," a statement by the company reads. "By the end of the decade, Substrate will produce wafers closer to $10,000, not $100,000."

Note that Substrate is by no means the only company exploring particle accelerators as light sources for EUV or beyond-EUV lithography. In the U.S. alone, two companies — Inversion Semiconductor and xLight — as well as researchers at Johns Hopkins University, have revealed that they are working on lithography systems harnessing particle accelerators over the past 12 months. Chinese scientists and Japanese researchers are also testing particle accelerators for semiconductor production.

Substrate's X-ray lithography

Substrate is developing a new type of lithography system that uses a particle accelerator to produce short-wavelength X-ray radiation (or light) for chipmaking. The goal is to replace ASML's expensive EUV lithography scanners with compact, low-cost machines capable of printing transistor patterns at a 2nm-class process technology (or even more advanced, the company claims). The firm claims the machine should reduce chip production costs by 10 times by the end of the decade.

At the core of Substrate’s technology is a custom particle accelerator which propels electrons (produced by an unknown emitter) to near the speed of light using radio-frequency cavities. As these electrons pass through sporadic magnetic fields, they gain kinetic energy, accelerating to speeds very close to the speed of light (a relativistic speed), which allows them to produce special types of light when manipulated. These fast-moving electrons fly through a series of magnets that flip back and forth, wiggling the electrons and causing them to release their energy and produce coherent bursts of intense X-ray light (or radiation).

That light is 'billions of times brighter than the sun,' likely producing pulses intense enough to achieve the desired resolution and dose. The X-ray pulses are then focused by 'a succession of perfectly polished optics' to project a photomask onto a photoresist-coated silicon wafer. Note that Substrate never mentions reticle and resist in its official description, only claiming that 'bright pulses of light' are collimated and transported 'all the way to the silicon wafer,' which implies maskless direct-write lithography, which is good enough for research purposes, but orders of magnitude too slow for the mass production of chips. However, this remains speculation on our part.

In fact, Substrate's description of its technologies is very brief and lacks detail (perhaps for competitive reasons), making it difficult to analyze. However, since the company mentions X-ray, we are dealing with electromagnetic radiation with wavelengths ranging from 0.01nm to 10nm and energies from about 100 eV to 100 keV. The shorter the wavelength, the finer the structure that can the printed with improved accuracy, but the harder the light is to manage and work with.

Given Substrate's achievements so far, we are likely dealing with soft X-rays (wavelengths of 1-10 nm, lower energy) rather than hard X-rays (wavelengths of 0.1-1nm, higher energy).

Since short-wavelength light (including EUV and X-rays) is strongly absorbed by most materials, managing it requires a set of perfectly polished mirrors that reflect light at grazing angles (to avoid absorption), ultra-precise alignment, and vacuum environments. Also, X-ray lithography requires all-new resists that can handle high-energy photons without damage or blur.

Achievements so far

2nm-like CD and T2P spacing

To prove that its XRL method works, Substrate has shown off images of a random logic contact array with 12nm critical dimensions (CD) and 13nm tip-to-tip (T2T) spacing printed with high pattern fidelity, as well as random vias with a 30nm center-to-center pitch, possessing superb pattern quality and critical dimension uniformity. If such metrics could be achieved for mass production today, this would largely revolutionize the lithography industry, as it would enable scaling across both axis at 2nm-class nodes (and lower) without using multi-patterning.

Modern EUV scanners with 0.33 NA optics can achieve critical dimensions of 13nm–16nm in high-volume manufacturing, which is sufficient to print a 26nm minimum metal pitch (good enough for 2nm or 3nm-class process technologies) and a 25nm T2T interconnect space with a single exposure.

Such disproportions emerge because chipmakers tend to optimize resolution in the Y direction (CD) to get the tightest metal-pitch line-space pattern, but at the cost of resolution in the X direction, which means that T2T prints poorly or inconsistently, leading to bridging defects, stochastic defects, yield loss, complicated design rules, and slower scaling. To mitigate this and avoid blurred or inconsistent line ends at tip-to-tip spacing, Intel applies pattern-shaping tools in the X-direction with its 18A fabrication technology, but this complicates the overall production flow and does not fundamentally solve the issue.

Substrate's tool (assuming these are real lab results, not a simulation) can already outperform existing Low-NA EUV scanners in terms of achievable CDs with single-resolution patterning, and it leaves them behind dramatically when it comes to T2T spacing printed with high fidelity. This means that Substrate's X-ray lithography tool could possibly replace costly EUV multi-patterning used for sophisticated 3nm and 2nm-class process technologies or pattern shaping used for Intel 18A.

Our friends at SemiAnalysis have managed to get more performance claims from Substrate, which look even more impressive. The company claims it has achieved overlay accuracy of under 1.6nm, full wafer critical-dimension uniformity (CDU) of 0.25 nm, line edge roughness (LER) of under 1nm, and local critical dimension uniformity (LCDU) below 1.5 nm.

If accurate, this performance would match or surpass ASML's Twinscan NXE:3800E in uniformity, though its overlay precision is slightly worse than the 0.9nm machine-matched overlay standard in the latest EUV scanners. Also, the line-width uniformity of contacts on an image provided by Substrate is rather poor.

Assuming the results presented by Substrate are real and achieved in a lab environment, this means the company has solved three critical challenges with X-ray lithography. First, build a light source featuring an electron gun and a particle accelerator; second, create a grazing-incidence mirror system to reflect and focus X-rays at very shallow angles; and make the whole thing compact enough to fit into a lab.

Future challenges

However, Substrate still has a lot of work to do, turning its X-ray lithography technology from a lab success into a viable production tool. Substrate must prove that its X-ray lithography system can maintain beam stability, optical precision, resist compatibility, overlay accuracy, and commercial throughput simultaneously, something no X-ray platform has ever achieved.

Existing photoresists are incompatible with X-ray radiation, as they are optimized for EUV radiation with considerably lower photon energy. So, Substrate will have to invent a proper resist and then produce it at volume. The company will also have to develop photomasks that can sustain X-ray radiation. Grazing-incidence mirrors for X-rays are also not in mass production, and it is unknown whether they can be mass-produced cheaply and reliably by existing producers like Zeiss.

Substrate will also have to ensure that X-rays do not damage the underlying transistors or introduce stochastic defects. Achieving overlay accuracy below 1nm (to match ASML's production-level alignment precision) remains another challenge for the company. This is perhaps because the company still has to address issues such as wafer handling, stage repeatability, and other factors related to high-precision mechanics, which ASML has taken decades to solve.

Beyond that, the tool must reach commercial throughput and consistent yield, something that took years for ASML's EUV tools. In fact, ASML's EUV journey timeline is quite exemplary: it has taken the industry 12 years to evolve from an alpha demo tool (2006) to mass production (2018), and about seven years to go from the first pre-production system (2010) to a mass-production-capable scanner.

A new paradigm

Speaking of mass-production-capable X-ray lithography tools, it is important to note that Substrate has no intention of selling them to third parties such as Intel or TSMC. Instead, Substrate plans to build its own fabs in the U.S. (a move that could give the company geopolitical importance in the eyes of the U.S. government), install additional tools, and offer foundry services, thus challenging existing chip contract manufacturers.

However, this strategy adds complexity and cost. Constructing even a single high-end semiconductor fabrication plant would require tens of billions of dollars in investment and a large ecosystem of suppliers and service infrastructure, which currently does not exist for X-ray lithography production.

Substrate would also need to integrate its XRL litho machines with hundreds of other tools in the fab, or persuade its suppliers (such as Applied Materials, KLA, Lam Research, etc.) to help it do so, which likely involves further investments from the company, making its first fab particularly expensive.

Also, running both a toolmaking activity and a chip foundry would stretch Substrate's technical and financial resources, which would make it particularly hard to achieve its promised per-wafer price of $10,000 by the end of the decade, as its investors will likely demand returns after pouring tens of billions of dollars into the company.

However, if Substrate succeeds in both roles, it could shift the balance of the semiconductor supply chain back to the U.S., as the company will likely outpace ASML's tools in terms of resolution and performance, and TSMC in terms of design cycle time and potentially volume.

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Last week, ASML introduced the Twinscan XT:260 lithography scanner, the industry's first scanner that has been designed from the ground up for advanced 3D packaging, marking a new era in fab tools.

Advanced packaging technologies like TSMC's Chip-on-Wafer-on-Substrate (CoWoS) are crucially important to achieve the performance scaling necessary to develop artificial intelligence and to evolve supercomputers.

Advanced packaging relies on deposition, etching, lithography, and metrology/inspection tools to make sophisticated chips. But while using these front-end tools is efficient for many steps, they are overengineered for some, and insufficient for others.

"In line with our plans to support our customers in the 3D integration space, we shipped ASML’s first product serving Advanced Packaging, the Twinscan XT:260, an i-line scanner offering up to 4x productivity compared to existing solutions.", ASML posted in its Q3 2025 financial results.

The Twinscan XT:260

ASML's Twinscan XT:260 is an i-line (365 nm) step-and-scan lithography system that processes 300-mm wafers and weds the precision of previous-generation front-end lithography tools with the productivity and flexibility of back-end tools. TSMC claims this provides four times higher productivity compared to 'competing steppers' used for advanced packaging technologies, such as Canon's FPA-5520iV. ASML never named the exact competing product, but Canon's FPA-5520iV is a good bet.

The key advantage of the tool compared to some of the existing machines used for advanced packaging is that it supports a high-dose exposures (340 mJ is mentioned, though it is usually tunable) and a 52 mm × 66 mm image field, enabling the tool to process up to 3,432 mm^2 interposers (4X EUV reticle size) without field stitching, which reduces complexity and speeds up the production cycle. For the sake of truth, it should be noted that Canon’s FPA-5520iV LF2 Option supports a 52 mm × 68 mm image field, but this is a stepper, not a scanner.

The system delivers 400 nm resolution, a 35 nm overlay, and offers a large depth of focus (11 µm at 1 µm CD) to enable accurate patterning for redistribution layers (RDLs) through-silicon vias (TSVs), and hybrid bonding structures used by modern packaging methods to integrate multi-chiplet designs. The unit also boasts 775 µm through-silicon alignment capabilities to make it particularly suited for bonded or non-planar wafers, which are common in 3D stacking.

The Twinscan XT:260 relies on ASML's dual-stage platform, so it can expose one wafer while simultaneously aligning the next, which significantly increases its performance. Speaking of performance, the machine can process up to 270 wafers per hour (at a 340 mJ dose) and handle thick (0.775 mm – 1.7 mm) or warped (1 mm) wafers.

With a 400 nm resolution, 35 nm overlay, and the ability to handle thick or warped wafers (up to 1.7 mm), the XT:260 is optimized for technologies Intel's Foveros, TSMC's CoWoS and System-on-Integrated-Chips (SoIC), as well as other high-density die-stacking or interposer technologies which require precise alignment through silicon.

The Twinscan XT:260 is positioned below the Twinscan XT:400M, the company's most basic i-line scanner used for chipmaking on mature nodes, but which may be an overkill for chip packaging on advanced nodes for now. Keep in mind that there are plenty of ASML's PAS 5500 i-line steppers that are used for 'more-than-Moore' applications, which is the company's convoluted way of pointing towards advanced packaging.

Compared with Canon's FPA-5520iV and the long-standing PAS 5500 i-line steppers, which have been widely used for CoWoS and fan-out packaging, the XT:260 represents a major leap in both productivity and precision. While the aforementioned tools rely on step-and-repeat exposure with limited throughput and field size (PAS 5500 only), the XT:260 introduces a scanner architecture with continuous wafer movement, advanced alignment optics, and automation suitable for high-volume 3D integration, which will be particularly important given that demand for advanced packaging is increasing.

The big picture

ASML's Twinscan XT:260 is the industry's first lithography scanner designed specifically for advanced packaging. It's not the only lithography scanner aimed at advanced packaging, though. The semiconductor industry has a choice: Use new tools like the Twinscan XT:260, or repurpose existing tools designed for front-end chip manufacturing for advanced packaging. If ASML's estimations are correct, using this specific tool will be technically beneficial, but may come at significant expense.

Previous-generation front-end lithography, etch, and deposition tools offer sub-micron precision, but need ultra-clean processing environments that ensure tight overlay and defect control. This is because they produce thousands of interconnects linking chiplets and HBM stacks in 2.5D, and eventually 3D System-in-Packages (SiPs).

However, these front-end tools are far more expensive — both in terms of price, performance, and total cost of ownership — than what is typically required for back-end packaging steps. Hence, using them in packaging lines drives up cost and limits output. One advantage of using them is that developers, process control engineers, and technicians at Intel and TSMC are familiar with those tools, which almost certainly guarantees good yields and fast ramp-ups. However, it comes at a high cost and a relatively long production cycle.

With tools like ASML's Twinscan XT:260, wafer-level stages that demand extreme precision — TSV formation, RDL patterning, and hybrid bonding — will get faster and therefore cheaper. This will set the stage for the broader adoption of advanced packaging technologies in several years. It'll likely take some time for chipmakers like Intel, Samsung, and TSMC, or OSAT companies like ASE, Amkor, and JCET, to integrate the lithography system into their process technologies and flows.

There are a lot more tools to be designed specifically for advanced packaging. Advanced packaging techniques still rely on 'classic' back-end tools for underfill, molding, ball attach, and many other operations. This hybrid flow balances cost with accuracy: front-end-grade tools where micron (or even nanometer) alignment matters.

As advanced packaging facilities use front-end tools (with appropriate costs), the boundary between foundries and OSATs is blurring. TSMC's CoWoS and SoIC facilities are filled with wafer fab equipment from ASML, Applied Materials, Canon, KLA, Lam Research, and Tokyo Electron, and usually cost north of $3 billion, the cost of a chip fab in the early 2010s. This is going to continue as more WFE makers set to produce tools specifically tailored for advanced packaging in the coming years and quarters.

The chief financial officer of ASML has told Bloomberg that the lithography giant is well prepared for China's export controls regime on rare earth elements and technologies for their mining and refining. The company has long lead times for its advanced tools, so it has plenty of raw materials in stock to support short-term demand from its clients. What happens after the company's reserves deplete is something unclear, though.

"We have long lead times, and therefore, also in our supply chain, we make sure that we have the materials in that we that we need for the next couple of months," said Roger Dassen, CFO of ASML, in a conversation with Bloomberg.

Under the new export control rules China imposed last week, companies have to get an export license to ship such rare earth materials as holmium, thulium, or ytterbium, or products based on these materials, from China's Ministry of Commerce. Furthermore, China imposed its export controls beyond its own borders on products containing rare earth materials originating from China if their value content within that product is more than 0.1% starting December 1, 2025.

This decision of the Chinese government could essentially stop all the supplies of all rare earth materials and products containing them across the world, something that could harm ASML, which uses a number of them inside its DUV and EUV lithography systems, metrology tools, and inspection tools.

However, Dassen downplayed the possibility of halting production after December 1, saying that the company's supply planning and long production cycles give it enough flexibility to absorb temporary disruptions. Meanwhile, the company now has over a month to buy rare earth materials or components containing them before the new export controls regime is enacted.

Speaking of China, ASML re-emphasized that it expects demand from its customers in the People's Republic to drop in 2026 due to the revocation of fast-track VEU license exemptions for Micron, Samsung, SK hynix, and TSMC, as well as softening demand from local chipmakers.

"When we look at China, we believe that the demand of our Chinese customers is going to be significantly lower in 2026 than it has been in 2024 and 2025 when we had very strong business there," said Christophe Fouquet, chief executive of ASML, during the company's earnings call with investors and analysts.

When Dutch officials revoked ASML’s license to export Twinscan NXT:2050i and NXT:2100i extreme ultraviolet (EUV) lithography systems to China under U.S. pressure, it closed the door to the only machines capable of producing sub-7nm chips at scale.

That single policy decision has defined what some analysts are calling the semiconductor cold war, where SMIC and its peers cannot buy the equipment needed for modern AI accelerators, and every shipment of advanced tools is now scrutinized as if it were a weapons transfer.

What the blockade hasn’t done is stop China’s fabs. Instead, it has forced an awkward reliance on older deep ultraviolet (DUV) machines (via TrendForce) and sparked a parallel race to design local replacements. It’s a strategy of necessity, one that accepts higher costs and lower yields in exchange for continuity and independence.

Sanctions and the scramble for workarounds

EUV machines are some of the most complex industrial systems in existence. Packed with thousands of U.S.-origin components and priced at hundreds of millions of dollars a piece, they are the foundation of every 5nm and 3nm chip shipping, or planning to ship in the future. China has none, and the U.S. has made sure of that.

Successive rounds of sanctions since 2022 have blocked not just EUV exports, but also the most advanced immersion DUV systems, including ASML’s Twinscan NXT:1970i and NXT:1980i. The Netherlands and Japan joined those restrictions, and even service contracts for ASML machines installed in China are being scrutinized. ASML itself has admitted that a China-based employee stole proprietary EUV data, highlighting how valuable the technology has become.

The policy has pushed chip procurement into murky territory. Grey-market Nvidia GPUs continue to flood in through Hong Kong and Singapore despite being explicitly banned, with seizures measured in the hundreds of millions of dollars. But smuggling a workstation card is one thing; sneaking in a 180-ton lithography scanner is another. On that front, Washington’s chokehold on export controls has held up.

The DUV fallback plan

Deep ultraviolet lithography predates EUV by decades. Using 193nm argon-fluoride lasers, immersion DUV systems comfortably support 28nm nodes, with yields and costs increasing dramatically as nodes shrink further. With multi-patterning (exposing the same wafer multiple times with different masks) they can be stretched down to 7nm-class geometries. Intel’s disastrous 10nm rollout proved how costly and yield-sensitive that approach can be, but it remains the only path available to Chinese fabs.

SMIC’s Kirin 9000-class parts, built for Huawei, already demonstrate the limits of this strategy. It’s widely believed that they were fabricated with DUV and heavy use of multiple patterning. The chips work, but at lower volume and efficiency than anything coming out of Taiwan or South Korea.

For now, Chinese fabs are leaning on their existing ASML DUV fleets. Nearly half of ASML’s second-quarter equipment tooling shipments in 2024 went to China, despite the political pressure in Washington. Those sales are a reminder of just how dependent Beijing still is on imported tools. But the window is closing, and the focus is shifting.

Shanghai Micro Electronics Equipment announced in 2023 that it had built a 28nm immersion scanner, the SSA800-10W. It’s crude compared to ASML’s Twinscan line, but it represents the first domestically developed immersion tool, and critically, it was designed without U.S. intellectual property. According to a TrendForce report, SMIC is testing a prototype from Yuliangsheng, a Huawei-linked affiliate of SiCarrier, which also rated for 28nm, but with ambitions to scale toward 7nm with multi-patterning.

A fully domestic DUV scanner, even if mired in yield problems, would insulate Chinese foundries from future Western policy decisions. Let’s not forget that China has previously made it clear that strategic self-sufficiency matters more than perfect parity with TSMC or Samsung.

China is playing the long game

TSMC is by far the largest operator of ASML's EUV lithography tools in the industry, with a second-to-none supply chain of both hardware and raw materials. The company's requirements for EUV pellicles (a thin membrane that protects the photomask, which acts as a stencil for chip patterns) have gotten incredibly high. The requirements are so extreme that TSMC intends to retrofit one of its 200-mm fabs to produce proprietary EUV pellicles exclusively, according to DigiTimes.

However, TSMC's proprietary pellicles, which outperform ASML's own offering, are just the tip of the iceberg, as TSMC pushes efforts to improve the efficiency of its fabs and ASML's EUV lithography tools.

When TSMC first deployed EUV in 2019 on its N7+ process for Huawei's HiSilicon Kirin 9000-series processors for smartphones, it already controlled 42% of the global install base of EUV lithography machines, despite TSMC not being the first foundry to formally announce the use of EUV tools.

By 2020, as ASML accelerated shipments and introduced its N5 process technology, which uses EUV for several layers, TSMC captured 50% market share of all EUV machines; this increased to 56% in mid-2024, with 130 machines to its name. Now, TSMC likely controls around 200 EUV machines globally, across many of its fabs.

While the number of EUV systems increased at TSMC by over 10 times compared to 2019, the number of wafers the company processes increased by over 30 times over six years, which indicates that TSMC did an incredible job to reduce downtime and service time, while increasing the throughput of its EUV scanners, which ultimately leads to higher productivity.

Tool productivity

TSMC said at its Technology Symposium in mid-2024 that it had doubled the wafer output per EUV tool per day since 2019 by fine-tuning both the exposure dose and the photoresist materials used in its lithography process. But, to define how TSMC has managed such efficiency, we speculate how the company may have achieved this.

On the exposure side, TSMC refined dose-to-size and dose-to-clear thresholds to reduce scanner dwell time per exposure field, while preserving critical dimension (CD) uniformity and ensuring line-edge roughness (LER) according to spec, which enables faster patterning without compromising yield in EUV lithography.

Typically, lowering these doses reduces the scanner's dwell time per field, enabling more wafers to be processed each day. However, this must be carefully balanced to maintain pattern fidelity, including CD control and LER. TSMC has succeeded, at least if we decoded its description correctly. Since TSMC has not disclosed the exact details, this is speculation, based on publicly available information.

On the materials side, TSMC upgraded its photoresist systems, possibly adopting high-sensitivity chemically amplified resists (CARs) and potentially incorporating metal-oxide resists (MORs) to improve absorption at 13.5 nm wavelength. These materials can enable lower exposure doses without degrading resolution. However, the company has yet to disclose which materials were used and exactly how they may have been implemented.

In parallel, TSMC also improved scanner utilization efficiency by deploying predictive maintenance models, optimizing job scheduling, servicing tools in advance, enhancing vibration control, and improving cooling performance. These changes reduced unplanned downtime and increased daily tool availability, enabling each EUV system to process more wafers in a stable environment.

Particular Pellicles

One of the most important advances has been in pellicle technology. These thin membranes protect EUV photomasks (reticles) from contamination, but have long been a bottleneck due to durability and defect issues. ASML itself developed two generations of its reticles, but it appears as though TSMC has managed to outpace them.

Back in mid-2024, TSMC reported dramatic improvements of its in-house developed EUV pellicle performance, including a four times longer lifespan, four and a half times more wafer output per pellicle, and an 80x reduction in defects. This likely points to TSMC's full-stack engineering approach that spans materials, mechanics, and fab integration.

On the materials side, TSMC may have adopted advanced pellicle films such as ultra-thin silicon-based membranes (e.g., SiNx, ZrSi₂) or hybrid multilayers with optimized EUV transmittance, thermal stability, and mechanical strength. These materials withstand EUV radiation, minimize thermal deformation, and reduce outgassing. To further suppress particle adhesion and resist contamination-induced failures, TSMC likely treated the surface with anti-reflective coatings or plasma passivation; however, this is speculation and not officially confirmed.

There are additional ways to improve the lifespan of pellicles and reduce defects. For example, tighter cleanroom protocols would reduce the chance of particle transfer onto pellicles or reticles. However, TSMC has yet to disclose these methods.

Photomasks

In addition to pellicles that protect photomasks, TSMC is also refining the photomasks themselves. To meet the A14 node's lithography demands, TSMC improved mask accuracy and defect control to reduce defect density, boost yield, and ultimately increase throughput.

TSMC claims that its engineers had improved CD uniformity, pattern fidelity, and overlay precision for curvilinear features by modifying EUV mask blanks, increasing the resolution of multi-beam writers, and optimizing mask fabrication processes. These steps ensured a more consistent pattern transfer and better alignment across layers.

Defect control was a major focus, too. TSMC strengthened its pellicle inspection, reticle cleanliness, and developer rinse chemistry to suppress defects like bridging and pattern collapse. TSMC deployed advanced e-beam inspection techniques to detect sub-visible membrane defects and degradation early, enabling predictive maintenance and proactive replacement before catastrophic failures, which improves yields and lowers performance variability.

In the future, TSMC plans to develop next-generation blank materials and new process flows to support future EUV requirements.

Planarization

Improving photomasks and pellicles are not the only ways to lower defect density, increase yields, and reduce performance variability, particularly for 2nm and sub-2nm-class process technologies, according to TSMC. The company is working to improve polarization for its A16 and A14 fabrication processes.

Planarization is crucial in advanced EUV lithography because it ensures a uniformly flat wafer surface, which is critical for maintaining focus and pattern fidelity at sub-2nm nodes like TSMC's A16 and A14. EUV systems have an extremely shallow depth of focus, which is why any topographical variation could be a source of defocus, CD variation, or LER. Uneven surfaces also lead to non-uniform resist thickness, which affects dose absorption and etch uniformity. Also, overlay errors increase if subsequent layers are patterned on non-planar foundations.

TSMC likely improves this through advanced chemical mechanical planarization (CMP), optimizing slurry chemistry, pressure profiles, and endpoint detection to achieve tight within-wafer and wafer-to-wafer planarity control.

Energy efficiency

EUV scanners are known for heavy energy use, and here too TSMC has made progress. It says it reduced power consumption of EUV tools by 24% 'through innovative energy saving techniques.' The company's future target is a 1.5 times improvement in energy efficiency per wafer by 2030.

Reduction in EUV scanner power consumption was likely achieved through a combination of hardware-level and system-level optimizations, though which optimizations were made has not been disclosed. For example, TSMC could enhance the laser-to-EUV conversion efficiency, where a significant amount of energy is lost. Another key area is thermal management. TSMC likely refined liquid cooling systems, optimized coolant flow rates, and improved heat exchanger design to lower auxiliary power consumption while maintaining thermal stability.

On the system side of things, firmware and scheduler optimizations may have reduced idle-state energy use and improved synchronization between subsystems, reducing power draw during non-exposure operations. Predictive maintenance and better utilization analytics would help avoid performance degradation from inaccurate positioning, synchronization, or overheating, which prevents inefficient tool operation.

TSMC's position strengthens

China's attempt to build a self-sufficient semiconductor industry has been instrumental in creating numerous companies, such as Huawei's HiSilicon, SMIC, and YMTC, that develop and manufacture world-class chips. However, while there are China-based firms that produce chipmaking tools, they cannot replace equipment made by American or European companies for advanced process technologies. Some, like Goldman Sachs, believe that China's chipmaking capability is about 20 years behind ASML, but there are signs that the situation may be more optimistic. But can China indeed unbind itself from the leading suppliers of chipmaking tools?

World-class memory and logic on Western tools

Although China-based chipmakers like CXMT, HuaHong, SMIC, and YMTC can produce logic (down to 7nm-class) and memory chips that are competitive on the global market, these companies rely on electronic design automation (EDA) and simulation software for chip design as well as production tools made in Europe, Japan, and the U.S., which makes them vulnerable to export controls from Western nations.

Domestically manufactured equipment accounts for just 15% to 30% of the total tools deployed in Chinese semiconductor fabs (according to AMEC estimates), which means that 70% to 85% of the tools they use are procured from American, European, Japanese, or South Korean companies.

To that end, it is crucial for the People's Republic's semiconductor industry to build its own EDA tools, ecosystem, and wafer fab equipment (WFE) supply chains, which the central government fully understands.

Last year, China began assembling the third installment of its Big Fund with the aim of funding companies producing ultra-pure chemistry or silicon wafers, as well as firms that develop and build chipmaking tools. However, this year it expanded the goal of the $50-billion Big Fund III to EDA and simulation tools. There are multiple ways for China to utilize this money to build advanced fab tools, but this will take time —a valuable asset, given the restrictions imposed on the country's semiconductor sector by the U.S. government.

Strong offerings for everything, but lithography

Every semiconductor production facility uses hundreds or thousands of tools, but they can be divided into several groups that perform different steps, including deposition (CVD, ALD, PVD), lithography (including tracking tools and lithography scanners), etching, ion implantation, annealing, cleaning, metrology, and inspection.

China has dozens of companies developing and producing wafer fab equipment for a variety of steps of the front-end production flow (actual semiconductor manufacturing), as well as companies making tools for back-end production (chip packaging).

It is simultaneously good and bad that China has so many WFE companies: on the one hand, there is competition both in terms of products and in terms of ideas, but on the other hand, small companies can't compete against industry giants like Applied Materials or Tokyo Electron. Still, there are quite big firms as well. Perhaps the best-known companies are ACM Research (equipment for cleaning, polishing, electrochemical plating, and plasma-enhanced CVD), Advanced Micro‑Fabrication Equipment (AMEC, deposition tools), Hwatsing Technology (chemical mechanical planarization/polishing), Kingsemi (spin-coating and developing tools), Naura Technology (etching, annealing, etc.), Shanghai Micro Electronics Equipment (SMEE, lithography tools, metrology, inspection tools), Piotech (deposition tools), and YuweiTek (optical inspection and metrology).

SiCarrier is a rising star in China's semiconductor equipment landscape. The company presented a catalog of dozens of fab tools at Semicon China this year and is believed to be developing a full stack of wafer fab equipment from deposition and lithography all the way to annealing and inspection. The main investor of SiCarrier is Shenzhen Major Investment Group, a government-backed fund supporting other semiconductor ventures associated with Huawei, which is why many observers think that SiCarrier is essentially a chipmaking tool arm of Huawei.

For now, Chinese companies have strong local offerings in etching, deposition, cleaning, CMP, and coating/developing, especially for mature and legacy process technologies (e.g., 28 nm and above). In fact, AMEC's tools can be used for the production of chips on 5nm-class nodes, according to the company. However, there is a caveat: many of the WFE equipment made in China uses components from Western companies, which are either subject to export controls already or will become so shortly. What is no less important is that lithography remains the most critical choke point for the People's Republic.

20 years behind?

Designing lithography tools is extremely challenging, as they sit at the intersection of optics, precision engineering, control systems, and materials science, all operating at nanometer-level tolerances in modern fabrication technologies.

SMEE, China's most advanced maker of litho tools, is significantly behind global leaders like ASML or Nikon. The company formally introduced its 28nm-capable immersion ArF DUV SSA/800-10W litho machine in late 2023, but it still does not list it on its website, and it is unclear whether it has shipped any production tools to actual chipmakers, such as HuaHong or SMIC, which have vast 28nm-class capacities. According to SMEE's website, the best lithography systems it has are the SSA600-series dry scanners, capable of 90nm, 110nm, and 280nm process technologies, which are from the early to mid-2000s.

SiCarrier is also developing lithography machines capable of 28nm-class production nodes (according to a Nikkei report), but the catalog from Semicon did not include any lithography tools, perhaps to keep its lithography developments a secret from the U.S. government, as they heavily rely on components made outside of China.

Keeping in mind that both SMEE and SiCarrier have so far developed lithography systems capable of producing chips on a 28nm-class process technologies, it is safe to say that both companies have managed to build immersion DUV scanners, which is a major milestone. ASML has 5nm-capable immersion DUV machines, which pretty much shows the immense capability of this technology.

However, as the best thing listed on SMEE's website is its dry SSA600-series litho system, comparable to ASML's machines from the early 2000s, analysts from Goldman Sachs have every right to say that SMEE is 20 years behind ASML. But can SMEE and/or SiCarrier leapfrog from a 28nm-capable machine that they cannot ship in volume, to something more advanced? Let's theorize.

Immersion DUV lithography is hard

Modern ArF immersion DUV lithography tools are incredibly difficult to design because they must enable a resolution sufficient for 5nm-class (and possibly beyond that) process technologies using 193 nm-wavelength light, which is far beyond the natural resolution limit of that wavelength.

To overcome this, immersion DUV scanners rely on high numerical aperture (NA) lenses made from ultra-pure calcium fluoride (CaF₂), polished to sub-nanometer surface roughness. ASML claims that only a few companies worldwide have the capability to manufacture optics of this precision, and its advanced tools almost exclusively use optics from Zeiss. Chinese companies do not have access to Zeiss's optics.

Additionally, ArF immersion scanners incorporate a thin layer of high-purity water between the lens and the wafer to enhance resolution. This requires maintaining a 1 mm fluid layer flowing at speeds of up to 1 m/s with no bubbles, turbulence, or contamination, which demands precision control over fluid dynamics and thermal stability.

Mechanical components must match optical precision: the wafer and reticle stages move at high speed but must maintain sub-nanometer accuracy using air bearings or magnetic levitation and have feedback systems that operate at microsecond latency to correct any drift or vibration. Software and sensors must act with a nanometer overlay error, as any deviation in alignment, stage motion, or temperature can destroy the pattern.

Not all mechanical components that ASML uses in its lithography, metrology, or inspection machines are built by the company; many are produced by third parties, so other companies can procure and use them as well (which is how Chinese companies obtain loads of components for their WFE). However, replicating ASML's software and firmware is as challenging as assembling a high-precision machine.

Chinese firms like SMEE, attempting to develop similar immersion DUV systems (like the SSA/800‑10W), must not only replicate the success in the face of extreme engineering challenges, but also replace or recreate every banned or restricted component from scratch. This is why even reaching 28nm-class capability is considered a major milestone.

However, moving to 16nm or 7nm is not a linear progression for ASML or SMEE, so it does not get meaningfully easier. In fact, the jump from 28nm to 7nm lithography involves entirely new classes of technology, control, and precision, with exponentially higher complexity and capital intensity. Technologies involved in ASML's latest DUV scanners are protected by various export controls (which prohibit shipping technologies enabling Chinese entities to make 16nm-class (and below) logic chips to China), so essentially, SMEE cannot get any help from the outside world.

ASML's 28 nm-class DUV capability (via Twinscan XT:1930i/1950i) was mature around 2010, whereas its DUV-based 5 nm-class capability using self-aligned quadruple patterning (SAQP), complex optical proximity correction (OPC), new masks, and new resists (among other things, of course), was commercially supported by 2020 with the Twinscan NXT:2000i. Nikon began sales of its 7nm-capable NSR-S636E in early 2024.

SMEE yet has to achieve maturity with its SSA/800-10W and produce it in high volume before attempting to move towards 16nm and 7nm. Considering that virtually no newly built fabs in China target 28nm technologies and below, it is unlikely that SMEE is close to volume production of its SSA/800-10W. As a result, SMEE is probably over 10 years behind ASML's NXT 2000i, and well over 15 years behind ASML's contemporary EUV tools (we are not going to touch upon EUV in this article because it is a completely different branch of technology development that requires plenty of innovations that took 20+ years).

No domestic tools for advanced nodes in the next 10 or more years

There is no way that SMEE or SiCarrier can make semiconductor breakthroughs faster than ASML did, so you shouldn't expect either company to come up with a 7nm or 5nm immersion DUV scanner in less than 10 years. While industry espionage and reverse engineering of tools that Chinese companies already have can speed up some developments, replicating ASML's Twinscan NXT:2000i is impossible not only because it has 100,000+ bleeding-edge parts, but also because the process will require replication of the entire ecosystems behind this machine.

As there are no shortcuts that can lead to NXT:2000i-class machines, SMEE and SiCarrier have to invest billions in internal R&D, master their optical and precision mechanic capabilities, work closer with third parties to develop new classes of raw materials and parts, and cooperate with fabs to take into account their developments.

In short, while China's semiconductor industry may achieve self-sufficiency with mature nodes in the coming years and perhaps even produce world-class tools for deposition, etching, ion implantation, annealing, and cleaning, there is no way that Chinese companies can catch up with ASML or Nikon in lithography any time soon. To that end, China will have to rely on advanced lithography tools for 7nm or 5nm-class technologies made in Europe or Japan for the next 10 years at least.

Prinano Technology, a China-based developer of nanoimprint tools, has delivered its first semiconductor-grade step-and-repeat nanoimprint lithography system to a Chinese customer that is focused on specialty process technologies. Instead of using traditional light-based lithography techniques, this type of chipmaking tool 'stamps' a chip design onto the wafer with a quartz mold that's imprinted with the circuit design. 

Prinano's PL-SR-series machine is the first nanoimprint lithography tool (NIL) developed in China and set to be used for actual chip production once it passes all necessary tests at Prinano's client. Prinano is the second company in the world to deliver an actual nanoimprint lithography tool to a customer after Canon.

China's NIL tool seems to work

Prinano's PL-SR step-and-repeat nanoimprint lithography tool patterns wafers by physically pressing a rigid quartz mold engraved with nanoscale circuit designs into a thin layer of liquid resist deposited on the wafer surface. Instead of using light and projection optics like photolithography, the PL-SR directly replicates the mold's features at full scale. It applies the resist using a high-precision inkjet system that dynamically adjusts droplet volume for different pattern densities to ensure a thin, uniform residual layer (under 10nm, with less than 2nm variation). 

Prinano's PL-SR system processes 300mm wafers and achieves less than 10nm linewidth capability. During operation, the system aligns the mold and wafer to presumably sub-10nm precision, makes full contact without a vacuum, and imprints each field sequentially (which is why it is called a 'step-and-repeat' system), stitching them together to cover the full 300mm wafer. 

The machine features a proprietary template profile control mechanism — an important innovation for NIL — that promises to compensate for curvature mismatches between the rigid quartz mold and silicon wafer to enable transfer of features with aspect ratios over 7:1 without any distortions to maximize yields and reduce performance variations. After imprinting, the resist pattern is cured and later etched to form the final circuit structures.

With good results

While we cannot directly compare the NIL lithography machine with EUV tools, its linewidth capability can be compared to the resolution enabled by EUV scanners. Modern EUV systems with 0.33 NA optics operate at a 13.5nm wavelength and typically achieve 13nm minimum half-pitch in a single exposure, which is good enough to print a 26nm minimum metal pitch with a single exposure patterning. 

To achieve resolutions below 10nm (e.g., printing 3nm-class process technology features at 21nm – 24nm), EUV tools necessitate multiple patterning steps, thereby adding cost and complexity. NIL's single-step reproduction of sub-10 nm lines is potentially simpler than EUV’s multipatterning for the same size, but only if the quartz mold can be manufactured with matching accuracy and defects can be kept low. 

As for <10nm residual layer thickness with less than a 2nm variation, EUV lithography (EUVL) scanners do not create a 'residual layer' in the same sense as nanoimprint lithography systems, but it makes sense to compare these dimensions to EUV's critical dimensions uniformity (CDU). Modern EUVL tools achieve CDUs within 1nm – 2nm across the wafer, so in this sense, NIL and EUVL systems are similar. 

Prinano does not disclose overlay performance of its NIL tools, but its whitepaper about the tool says that the 'industry requires' overlay accuracy 'below 10 nm, and even approach the 1nm level' in the future. The latest ASML Twinscan NXE:3800E can achieve overlay performance in the range of 1.5nm – 2.0nm for high-volume manufacturing, depending on process conditions. Considering that Prinano does not directly disclose its overlay accuracy, we can only speculate that its target for now is between 1nm and 10nm.

But not for high-volume output

But competitive resolution is only one part of the equation. One thing to keep in mind is that NIL step-and-repeat imprinting is inherently slower than EUV or DUV projection lithography because each wafer field must be physically contacted, imprinted, cured, and separated before moving to the next. This mechanical cycle limits wafer-per-hour rates to the tens for fine features, whereas modern EUV tools can process around 200 wafers per hour. The slower pace makes NIL less suited for high-volume, leading-edge logic or memory production, even if its resolution is competitive.

And not for logic (at least for now)

The U.S. and China are locked in an unprecedented race over semiconductor technology, driven by national security concerns, economic competitiveness, and the belief that control of advanced chips will determine global leadership in the decades ahead. Chips are the foundation of everything from smartphones and data centers to fighter jets and the energy grid, as well as powering the AI tech both Washington and Beijing see as critical for future military and economic power.

The rivalry has intensified in recent months as both sides have recognised vulnerabilities in their supply chains. The U.S., home to most chip design and high-end equipment companies, grew wary of depending on global manufacturing concentrated in East Asia – especially as China poured hundreds of billions into building its own chip industry, and constantly threatens invasion of Taiwan, where over 60% of global semiconductor production and more than 90% of the most advanced chips (below 7nm) passes through.

China, in turn, saw its reliance on foreign (often American or U.S.-allied) technology as a strategic weakness, especially after repeated sanctions blocked its access to the most advanced chips and manufacturing equipment. This escalating contest has led to historic subsidies, new export controls, technical bans, and a scramble to onshore production. We reached out and interviewed multiple industry analysts to get a further understanding of how this dynamic could impact the industry.

Both powers go head-to-head

The two countries are engaged in an arms race to see who can stand up their own chip development first, which has resulted in a global divide between major superpowers. While neither side can yet claim decisive victory, their race is already reshaping trade, geopolitics, and the global tech landscape.

“We're definitely seeing more bifurcation in the chip industry, as China pours money into building a self-sufficient supply chain,” says Chris Miller, professor at Tufts University and the author of Chip War: The Fight for the World’s Most Critical Technology.

It’s an assessment that William Matthews, senior research fellow for China and the world in the Asia-Pacific Programme at Chatham House, agrees with. "I think the long-term trend will be toward bifurcation as China catches up. Beijing is clear about its desire for independent technological capability across the board - I'm not sure we're on the 'brink' of this, but that does seem to be the direction of travel."

But both believe the rupture hasn’t yet arrived. Each country remains dependent on the other – at least for now. “China is still reliant on importing chipmaking tools and materials, especially for high-end production,” explains Miller. China relies on imported lithography equipment, particularly EUV machines from ASML, which are restricted by U.S.-led export controls.

It also depends on foreign EDA software and ultra-pure materials essential for leading-edge chips. These tools and technologies are extraordinarily complex, protected by IP, and take decades to master – areas where domestic alternatives are still underdeveloped. As a result, China cannot yet manufacture chips at the most advanced process nodes ( 5nm or below) at scale or efficiency. “I think the export control has been effective in controlling China’s access to advanced chipmaking from TSMC, Samsung, and Intel and advanced chipmaking tools from ASML,” says Ray Wang, research director for semiconductors, supply chain and emerging tech at The Futurum Group.

It's an approach that some of the U.S. president’s most senior advisors have given full-throated support to. “Restricting the sale of EUV lithography equipment to China is the single most important export control we have,” David Sacks, the administration’s AI and crypto czar, posted on social media in May.

And beyond those struggles, the reality is that China is still a chip importer of its own. “It is also still importing large volumes of high-end chips because of their struggles to ramp up production capacity,” says Miller.

Can China survive through tariffs and export controls?

As of 2024, China's monthly chip production capacity reached around 8.85 million wafers, with most output coming from mature-node fabs (28nm and above). This figure is forecast to rise to 10.1 million wafers per month by the end of 2025, largely driven by government funding and 18 new fabs under development. But that’s changing. Market research and tech consulting firm Yole Group predicts that China will hold 30% of the world’s global foundry production capacity by 2030, making it the world’s largest hub of semiconductor production. In 2024 alone, it bought 40% of all wafer fabrication equipment worldwide – recognising it needed to step up its production.

However, when that does happen, and China manages to ramp up production, there will be significant changes for us all. “It will have global implications – and be yet another example of China successfully innovating and catching up under pressure from the U.S., while also exploiting a market for its own technology abroad, especially across the Global South,” says Matthews. “I suspect we will see a pattern which is now quite familiar, of growing Chinese indigenous capability leading to deeper separation of ecosystems as the U.S. responds by attempting to restrict China further.”

That’s concerning experts who are studying the area. “With U.S.–China tensions rising and technological competition intensifying, a deeper decoupling of the semiconductor supply chain now looks inevitable,” says Wang, “spanning chip design, manufacturing, equipment, and other critical segments. If U.S.–China tensions persist – or deteriorate further – the global semiconductor supply chain could ultimately and completely split into two parallel ecosystems, which is occurring in front of our eyes.”

There are already signs of that happening. Washington is choking China’s access to the tools used to design and make advanced chips. A May order from the US Commerce Department revoked existing licences for shipping electronic-design-automation (EDA) software and critical chemicals to Chinese customers, forcing vendors such as Cadence (which was fined $140 million for exporting design tools to China) and Synopsys to apply for case-by-case permits.

In return, China had initially refused to approve, but then backed down on, a merger of Synopsys and Ansys, two of the largest providers of EDA software, which is essential for designing the architecture and logic of semiconductors before they are manufactured, in the world. These tools enable simulation, verification, and layout of complex chip designs, making them critical to advanced semiconductor R&D and production.

Homegrown chips

China is responding to the threat of being squeezed out of the supply chain by backing its own homegrown production arms to the hilt. They’re putting the full force of Chinese finance and regulation behind the plans. Big Fund III, a third-phase, state-backed war chest, aims to deploy ¥344 billion ($48 billion) into the country’s weakest links of lithography and design software. The fund plans longer holding periods and aggressive consolidation to accelerate breakthroughs, according to people familiar with its mandate.

Alongside that, Chinese leadership is also putting the power of the state to work in favour of the AI sector. The forthcoming 15th Five-Year Plan (2026-30) will have AI development at its core. Early drafts flagged by Chinese state media put semiconductor equipment self-reliance near the top of national priorities, alongside the “AI Plus” push to embed artificial intelligence across every sector of the economy.

Despite those hints at the future direction, exact details are difficult to discern. “It's hard to interpret exactly how China's industrial policy is evolving because so much of its industrial policy spending happens at the provincial level and local level, as well as various public-private funds,” says Miller. “Still, it does seem like the new iteration of the Big Fund is focusing more on EDA and chipmaking equipment. However, these are very challenging segments to enter, and it will take years for China to produce cutting-edge capabilities in these spheres.”

While China's chipmaking ambitions are indeed large, it has not been entirely successful in its efforts thus far, with a large number of projects and fabs entirely collapsing, despite lofty claims.

Global implications

What the ongoing feud between the U.S. and China means for the rest of the world and Europe is particularly vexing for experts. “That is a risk for Europe – again, following a pattern seen in other technologies from EVs to robotics,” says Matthews. The problem is that “Europe has been consistently late in waking up to China's capability and challenge to the U.S.,” he explains.

In response, Europe ought to try and carve out niches in order to maintain competitiveness. “But that means massive focused investment and a strategy more like China’s,” Matthews says. “The question would be whether Europe has the political will to pursue that over the long term.” Matthews argues there is a strong case for Europe to pursue chip production even if it lags behind the U.S. and China in order to strengthen its own autonomy and resilience – as it has in other areas, including its tech stack, with the development of proprietary versions of Google Docs and Microsoft Office – “but again, that needs to be accompanied by a real mindset shift on industrial policy and a plan to engage countries in the Global South as customers,” Matthews explains. “The challenge will be catching up with China on these two counts.”

Still, given the EU’s recent history in making sure it’s in control of its own supply chain and regulation, and not at the whims of the United States, it seems likely. “Europe is probably going to consider a second EU Chips Act to build its semiconductor capabilities, which will probably focus on some of these unique chipmaking capabilities, as well as its niches in materials and equipment,” says Miller.

At the same time, Europe will have to compete in the global market for expertise and manufacturing tools. And the U.S. is making sure it’s as competitive as possible to head off China.

Five years ago, Washington wagered that a 25% investment tax credit would be enough to lure chipmakers home. It worked – up to a point. But a June Senate draft lifted the subsidy to 30%, and President Donald Trump’s “One Big Beautiful Bill,” signed in July, took it to 35% for fabs breaking ground before 2026, with sweeteners for AI-specific capacity. Industry has responded in kind: in March, before the Big Beautiful Bill was passed, Taiwan Semiconductor Manufacturing Co. (TSMC), one of the world’s biggest names in the sector, lifted its financial commitment to onshore chip manufacturing capacity in Arizona from $65 billion to $165 billion, cementing the single largest foreign-direct investment in U.S. history.

“AI is reshaping our daily lives and semiconductor technology is the foundation for new capabilities and applications," said TSMC Chairman and CEO C.C. Wei in a statement. “With the success of our first fab in Arizona, along with needed government support and strong customer partnerships, we intend to expand our U.S. semiconductor manufacturing investment by an additional $100 billion, bringing our total planned investment to $165 billion.”

“It's clear to me that TSMC in Arizona has been quite successful despite the early hurdles, and its P1 – the first fab in Arizona – is in fact in operation,” says Wang. The P1 facility is expected to produce up to 30,000 wafers per month using 4nm and 5nm process technology, primarily for high-performance computing clients like Apple and Nvidia. “I expect its P2 and P3 will have [an] easier learning curve, and construction-to-operation process should be smoother.”

As for other investment from Texas Instruments, which announced a $60 billion U.S.-focused tech pledge in June that it said would create 60,000 jobs, and Micron, which has committed up to $100 billion to build the largest semiconductor fabrication facility in the U.S. in New York, focusing on memory chip production, with initial construction starting in the late 2020s, it’s “too early to say,” reckons Wang.

The two countries are caught up in a delicate dance to try and one-up each other, while ensuring they keep access to the things on which they are reliant on one another for. In mid-July, the United States loosened its restrictions on the export of Nvidia’s H20 chips, seemingly in exchange for China reallowing the export of rare earths that are vital in other chips’ manufacturing. Until one side or the other can fully onshore all the required production processes, there’s an awkward quid pro quo going on.

After that point, all bets are off.

An ex-ASML employee has been sentenced to three years' imprisonment for sharing company secrets with a contact in Russia. According to a post on the Netherlands' judiciary website, De Rechtspraak (machine translation), the defendant copied information from ASML and NXP computer systems for his contact and accessed information specifically for this purpose. However, the sentence was reduced in length, from the four years sought by the prosecution, as there was no proof that the man acted for financial gain.

The importance of ASML to the world’s semiconductor industry cannot be overstated. This Dutch tech company makes the most advanced lithography machines available, crucial to the likes of TSMC, Samsung, and Intel in striving for chip production at the finest scales – and reaping the density, performance, and efficiency advantages of advanced processes.

Russia is a relative tech minnow in the context of ASML’s pedigree, so it would naturally be interested in gaining access to some of the proprietary knowledge and technologies that are kept from the public domain. The unnamed ex-employee is said to have copied confidential files from both ASML and NXP over a period spanning several years.

We aren’t told the full extent of the intellectual property theft in the source report. It is indicated that specifics shared by the accused/imprisoned man were largely to do with designing microchip production lines.

Investigators found a “large amount of files from ASML and NXP, which were found on various data carriers at his home.” It was judged to be implausible that the ex-employee needed these files for his work, and many of the files were beyond the scope of the activities for which he was employed.

The ex-employee was also accused of ‘computer trespassing’ on systems with the sole purpose of providing technical assistance to his Russian contact. The defendant is claimed to have stated (machine translated) that “I had kept files from ASML for my own use... Whether those files were allowed to go to Russia? I did not ask myself that.” Later admitting, “Yes, I gave advice.”

Information 'of great value' to Russia

ASML, maker of the world's most advanced chipmaking tools, and the Van Gogh museum have collaborated on the design of a 3D scanner to capture and create digital twins of the masterpieces of the Netherlands’ most famous artist. Vincent van Gogh’s artistic brushwork was characteristic for its ‘Impasto’ style, where paint can be applied in a very thick and textured style. Thus, the ‘Impasto Project’ was born, with ASML and the museum creators developing a 3D scanner that can capture exceptional levels of artistic detail in approximately 100 gigabytes of data per painting.

The curators of the Van Gogh Museum had a dream project, where they could create something akin to the ‘Google Maps for paintings.’ They thought it was worth striking up a conversation with local tech titan ASML and got lucky, as the leading chip toolmaker develops technologies that are perhaps surprisingly applicable to the detailed 3D scanning of paintings.

When ASML was initially approached in 2017, the partnership might have sounded unusual. However, both van Gogh and ASML are Dutch icons, with their roots in the province of North Brabant. Moreover, “at ASML we don't just make chip machines,” explained (machine translation) Head of Research Metrology at ASML, Maarten Voncken. “We also make equipment to measure how accurate those machines are.” This technology turned out to be surprisingly applicable for 3D scanning paintings.

As mentioned above, the pilot program began in 2017 and, after a promising start, the collaboration was extended in 2019. Work has continued apace, and the partners will now collaborate on the Impasto Project until at least 2028.

How the scanner works

The Impasto Project hardware is essentially a small, shoebox-sized scanner guided by a framed system with rails. This imaging process takes photos of dozens of segments of each painting. Each specific area photo is taken four times with the camera at slightly different angles.

This varied data representing the same image segment allows the custom software to calculate the varied thickness of the paint from shadows that are cast. As we mentioned in the intro, a finished 3D image scan of a painting is approximately 100 GB.

ASML measuring equipment is accurate to the nanometer level, so this 3D scanning tool operates at a scale approximately 100,000 times larger. Nevertheless, significant customization of the hardware and software was required to meet the requirements of the museum's curators.

In addition to the digital twin plans, the scanner can also be used to automate the process of inspecting paintings before and after they are lent to other institutions. Thanks to this new tool, curators can check the effects of handling, temperature, and moisture changes when paintings are loaned. Observations will likely be used to improve the handling and transport of these treasured works.

Giving back

Interestingly, ASML is nonchalant about the investment in non-core areas, such as the Impasto Project. It shrugs off the cost of the project at ‘a few million a year.’ It also revealed that around 10 to 15 ASML staffers work on this project. We aren’t familiar with Dutch business practices, but this project seems to be part of a wider commitment to ‘give back’ to the region. Currently, ASML invests around $100 million in local employment projects as part of its ‘social budget.’ ASML also sponsors a gallery at the museum.

With the ASML collaboration established and 3D scanning becoming routine, visitors to the Van Gogh Museum can now visit a new science center within the museum. Here, they will find the 3D scanning equipment on display, among other technical art curation-related things.

Outside interest

Creating a powerful, reliable, and manufacturable light source for modern chipmakers is one of the most complex challenges in today's industry. Among all makers of litho systems, only ASML has successfully created EUV light to print the smallest chip features — but one startup has a radical new idea to change the status quo.

Inversion Semiconductor, a San Francisco startup backed by venture capital firm Y Combinator, plans to develop a light source based on a compact particle accelerator, which it claims would be 33 times more powerful than ASML's existing technology and could pave the way for producing finer chip features.

At the heart of Inversion's tech is a 'tabletop' particle accelerator that is 1,000x smaller than traditional particle accelerators and yet can deliver output power of up to 10 kW. Despite its tiny dimensions, Inversion claims that its light source, leveraging the laser wakefield acceleration (LWFA) method, can either speed up chipmaking 15 fold (assuming one 10 kW light source powers one lithography system) or power multiple chipmaking tools simultaneously, thereby cutting costs.

There are major challenges for the budding startup, however, as this specific type of accelerator requires petawatt-class lasers, which are both costly and power hungry. Additionally, unless Inversion Semiconductor collaborates with ASML (or perhaps other manufacturers of lithography machines), it would need to develop its own lithography systems and create a new ecosystem for its scanners, a time-consuming and expensive endeavor.

Given that Inversion Semiconductor has no experience building high-volume, 24/7 fab tools, the company's ambitions are lofty, and there's no guarantee it will fulfill the promise it's making on paper.

10 times more power-hungry than ASML

Inversion Semiconductor was founded in 2024 by Rohan Karthik (CEO) and Daniel Vega (CTO), both of whom hold master's degrees in mechanical engineering and applied physics. The company is backed by Y Combinator. Inversion's goal is to develop a compact, high-performance light source based on a particle accelerator that would offer an output power of 10 kW, which is 10 times more powerful than what ASML plans to achieve over the next decade.

This particle accelerator could produce lasers with wavelengths between 20nm and 6.7nm, including 13.5nm light used by ASML for both Low-NA EUV and High-NA EUV lithography tools today.

Light with a sub-10nm wavelength is called a soft X-ray, which is not currently used for chip production due to its high absorption rates by most materials. So, while sub-10nm wavelengths are not currently used in chip production, it might prove to be a promising field for research in the long-term future.

Inversion's ambitions do not end with the development of just a light source, but span all the way to building complete lithography tools to compete against ASML directly.

Using particle accelerators as light sources for lithography tools is a widely discussed and researched topic in the industry, but Inversion Semiconductor plans to use what it calls 'tabletop particle accelerators' that can accelerate electrons to extremely high energies over centimeters, rather than kilometers, as seen in accelerators such as the Large Hadron Collider used by CERN.

Riding on the wakefield waves

Immersion intends to use accelerators relying on the laser wakefield acceleration (LWFA) technique, which is significantly different compared to methods used by ASML and CERN. LWFA uses powerful, ultra-short (femtosecond-scale) laser pulses interacting with plasma, consisting of free electrons and positively charged ions.

When an intense laser pulse travels through plasma, it creates strong electric fields by pushing electrons aside and generating plasma waves, or 'wakefields' behind it. Electrons can become trapped and accelerated rapidly within these waves, gaining substantial energy in a very short distance as they rush back to their original position. The plasma wave accelerates electrons in fields that are 100 – 1000 times stronger than those found in a conventional accelerator, according to the Imperial College London.

The accelerated electrons can then be used for various practical applications, including compact X-ray sources and semiconductor lithography, just to name a few. Unlike traditional EUV sources, the LWFA method generates radiation that is coherent, monochromatic, and precisely tuneable, enabling wavelengths shorter than 13.5 nm (e.g., 6.7 nm target, which is far from industrial deployment), which could be instrumental for next-generation lithography systems.

The LWFA mechanism accelerates electrons to energies reaching multiple giga-electron volts (GeV) over distances as short as a few centimeters, thus miniaturizing high-energy electron acceleration systems dramatically, from large facilities down to tabletop-sized devices, which could spark further innovation for the semiconductor industry.

Immersion Semiconductor's immediate goals

Immersion Semiconductor's progress to date includes setting up a small laser laboratory within the Y Combinator offices to develop new laser stabilization techniques, and building initial LWFA prototypes capable of producing short-wavelength radiation. They have also partnered with the Lawrence Berkeley National Laboratory and the BELLA Center to collaborate on the BELLA-LUX project, focusing on refining laser stability and improving the generation of suitable light for semiconductor use.

The company's immediate goal is to develop Starlight: a high-power, tunable light source capable of producing 1 kW of soft X-ray light in the 20 nm to 6 nm wavelength range. If successful, the device could find use in applications like industrial X-ray imaging and semiconductor mask inspection. Companies such as Tesla and Applied Materials have expressed interest in these early-stage developments, according to Immersion Semiconductor.

In parallel, the company is working on advanced mirror systems to reflect and focus the generated EUV light (i.e. higher than 10nm), which are necessary to direct the light precisely for wafer patterning. The first lithography system based on this technology — designated LITH-0 — will be powered by Starlight, with the goal of demonstrating practical silicon wafer patterning capabilities. However, no-one knows when Inversion Semiconductor's LITH-0 will be complete, and fully-functional.

Are there any Caveats? Many!

On paper, Inversion Lithography's plans seem sound and the LWFA method of generating EUV radiation (or light) seems almost perfect. However, there are many caveats.

First up, an LWFA accelerator chamber may be small, but it requires a petawatt-class, ultrafast laser systems which are extremely complex, large, and expensive. Cooling and maintaining such lasers for reliable, non-stop fab operation is something that nobody has tried. It is also unclear whether Immersion Semiconductor's setup can fire those lasers at a consistent repetition rate per second.

Secondly, even researchers from the John Adams Institute for Accelerator Science at Imperial College London admit that LWFA produces electron beams with large energy spread (variation in electron energies) and beam divergence (wider spread of trajectories) at beyond 1 GeV.

For lithography, the generated light must be highly stable in wavelength, direction, and coherence to achieve precise and repeatable patterning. Instability translates into poor resolution leading to performance variability and yield loss.

Thirdly, while today LWFA-based tools featuring a laser with 13.5nm light source can use mirrors and optics developed for ASML's Low-NA and High-NA EUV tools, should they move to shorter wavelengths, they are poised to use new mirrors and optics. This will be a problem, of course, if Inversion Lithography actually decides to develop its own lithography systems, but, this means it will have to develop a whole new ecosystem.

A more realistic variant could be making its LWFA-based source compatible with existing tools from ASML. However, there is a problem too. Integrating an LWFA light source with existing EUV lithography scanners would be complex as it would require developing new beam shaping, focusing, and metrology systems, just to name a few challenges. While ASML has solved all the challenges associated with its Cymer light sources, we can only wonder whether the company is interested in making its tools work with a third-party tool. As for other makers of litho machines — Canon and Nikon — they have not managed to go beyond KrF and ArF lasers and tools, respectively, so chances that they will manage to build EUV (or beyond EUV) scanners are low. Also, keeping in mind that we are talking about an at least 1 kW light source, the industry will also need new resists, pellicles, and other expendables to make everything work.

Perhaps the biggest challenge for Inversion Lithography is that it does not have any experience in production of rapidly-serviceable mass-produced tools that are engineered for fabs operating 24/7 and are highly compatible with other production equipment in the building.

Summary

Inversion Lithography aims to develop a compact, LWFA-based light source that 10 times more powerful than ASML's current EUV light sources while also targeting even shorter wavelenghts. Inversion says that its light sources will be tunable and will create coherent radiation for finer semiconductor patterning. Eventually the company aims to build a light source with a 10 kW performance (10 times more powerful compared to what ASML plans over the next decade), it can either greatly speed up production of chips (by 15 times, the company claims), or power multiple lithography systems with one light source, thus cutting down costs.

However, there are major challenges as an LWFA-based accelerator require a petawatt-class laser, which consumes a lot of power and is expensive. Also, unless Inversion teams up with ASML (an unlikely scenario) or other makers of litho tools like Canon and Nikon (also unlikely) and develops its own scanners, it will have to develop an all-new ecosystem for its machines, which is timely and extremely costly. Also, if the company goes down this path, it will have to gain experience in creating and maintaining high-volume production 24/7 fab tools.

ASML appears to have accelerated its ambitious expansion plans. The Netherlands-based undisputed leader in the design and provision of advanced chip-making equipment now signals it will have employees moved into its new Brainport Industries Campus, near Eindhoven, by 2028. The update was shared in a presentation of a preliminary draft urban development plan alongside officials from the municipality of Eindhoven, reports Tweakers.net and mainstream Dutch news media like ED (we used machine translations).

The Brainport Industries Campus expansion plans were first made public about a year ago. At that time, the company discussed the expansion coming into being "around or after 2030," according to the Dutch sources. Yesterday, during the presentation, attendees were told about the first of the additional 20,000 employees settling into their new roles in three years - which would make it 2028.

ASML's new campus plans are rather impressive and have even been called "un-Dutchly large," by some. The expanded campus will add 357,000 square meters or more to ASML's footprint. That's approximately as big as 50 football fields. ASML has located the new campus between Eindhoven Airport and the A2 motorway – and the site will even be intersected by the Ekkersrijt river.

Details shared yesterday suggest that the new campus area will include two parking garages, plus slots for 4,200 bicycles. The municipality won't make a dedicated motorway (freeway) exit for the facility, however, two major roads will be redesigned to address the expected traffic flow, as will a dedicated bus lane for commuters.

The Dutch government released €1.7 billion last year to help facilitate this project, which is obviously going to be important for the region, and the nation in general. Though things appear to be being slipstreamed, some important hurdles remain. For example, the Dutch power grid is already creaking under current demands, and there is also said to be a 'nitrogen storage problem.' The question of land acquisition also remains, and though Philips owns 80% of the designated area, that leaves 20% open to deals and legal wrangling. Last but not least, now the plans are public, environmental associations, nearly municipalities, and other parties can respond.

Addressing EUV machine demand

Intel has made significant strides in implementing High-NA EUV lithography by installing two High-NA litho machines, developing custom reticles as well as all-new optical proximity correction, and processing 30,000 wafers. However, major hurdles remain: the $380 million – $400 million tool cost and potential necessity to overhaul photomask supply chain limits economic viability of the technology. Furthermore, a single High-NA EUV exposure costs 2.5 times more than a single Low-NA EUV exposure, which raises further questions about economic feasibility over the next few years, reports SemiAnalysis.

Puzzling economics

ASML's Twinscan EXE:5000 weighs 150 tons and is priced around $380 million – $400 million, roughly double that of its Low-NA Twinscan NXE predecessors. At the SPIE conference earlier this year IBM presented simulation data comparing different approaches to patterning. It showed that replacing three or four Low-NA masks with one High-NA exposure could yield cost savings. For example, IBM estimated a four-mask self-aligned double patterning flow is 1.7 to 2.1 times more expensive than a single High-NA exposure. But when only two Low-NA passes are replaced, High-NA becomes more expensive by 2.5 times, which means that High-NA is only cost-efficient when it can eliminate three or more exposures.

This does not mean that the industry will not need High-NA tools. It means that the industry will have tangible benefits of using High-NA EUV lithography when it needs triple or quadruple patterning with Low-NA EUV scanners, which will depend on process technologies that the industry adopts and aggressiveness of process scaling going forward.

According to Intel, this may happen sooner rather than later. The company showed imaging results, made economic comparisons, and discussed patterning alternatives, and ecosystem readiness, painting a detailed picture of where High-NA EUV stands in 2025 at the SPIE Advanced Lithography conference earlier this year.

The imaging results included key device layers such as metal and contact levels. In the case of metal layers, Intel used one High-NA exposure to replace a previous scheme requiring three separate Low-NA exposures and around 30 total process steps. This simplification could reduce cost and defectivity for complex interconnect structures. In contact holes, yield from early High-NA tests matched that of established multi-patterning flows, despite the initial masks being early-stage test versions. These outcomes suggest High-NA EUV lithography is technically viable for some of the most challenging layers at upcoming nodes.

Intel itself is expected to selectively implement High-NA EUV lithography for a few layers within its Intel 14A (1.4nm-class) process technology, though ecosystem readiness could impact the company's plans. For Intel, the good news is that it is at the helm of that ecosystem development and will therefore have a lead over rivals.

Parallel development

By acquiring and installing two ASML Twinscan EXE:5000 lithography tools ahead of competitors, Intel is ahead of the industry in gathering process data and proving viability for high-volume manufacturing. Intel did everything it could to get its High-NA EUV scanners as early as possible. It received the first Twinscan EXE:5000 machine over a year ago and skipped ASML's typical factory tool qualification, which includes assembly of the tool at an ASML facility — opting instead for assembly and startup at its own D1D fab near Hillsboro, Oregon. This early decision gave Intel a head start in validating the system and building process readiness. To support its development efforts, Intel exposed over 30,000 wafers across both High-NA tools, making it the most experienced user of this new platform.

But getting a new scanner and assembling it are only some of the challenges associated with making it work properly. In addition, Intel needed to develop process technology itself, photomasks, resists, and optical proximity correction (OPC) software enhancement techniques. Normally, since all these things are co-dependent, they are developed serially. However, Intel adopted a parallel development strategy to meet the tight timeline for its 14A (1.4nm-class) node, which is expected to be production ready in 2026. The company shared details how it managed to do so at this year's SPIE Advanced Lithography conference.

Intel began to develop OPC well before it got its High-NA EUV tool running. The company used simulations and exposures on conventional EUV tools to extrapolate and fine-tune models intended for High-NA EUV. This strategy bypassed the usual delay in mask preparation and enabled immediate pilot line operation once the High-NA scanners were up. Results exceeded expectations: source power reached 110% of target (a first for an ASML scanner at launch) and overlay alignment measured at 0.6nm, which is comparable (yet, not as precise) to mature Low-NA systems.

By now, Intel has made significant strides in developing production ready photomasks, resists, OCP, and other elements of High-NA EUV production flow. However, it looks like the obstacles associated with adoption of High-NA EUV tools by the industry are not only engineering challenges, but also economic hurdles associated both with infrastructure development and usage scenarios.

Not yet ready for prime time

One of the challenges with High-NA EUV lithography is the two times smaller exposure field compared to Low-NA EUV lithography due to higher numerical aperture of projection optics: 26 mm × 16.5 mm vs. 26 mm × 33 mm.

This is a major challenge for large chips like GPUs and CPUs, which often exceed the 13×26 mm limit of a single High-NA exposure. Therefore, to pattern these dies, two or more overlapping exposures (stitched fields) must be used (an alternative is to use a multi-chiplet designs). This introduces alignment complexity, risks of overlay errors, and yield loss in the stitched regions. Also, with fewer chips fit per exposure field, more passes per wafer are required, which reduces the wafer-per-hour rate and increases cost per wafer.

ASML proposes to use accelerated stages (i.e., accelerate how the wafer moves under the photomask) to compensate for higher number of exposures. However, Intel has long proposed to use a larger 6×12-inch photomask instead of industry-standard 6×6-inch photomask. A larger photomask solves the half-field problem by doubling the reticle area, allowing it to hold two adjacent half-field images side by side. When used with appropriately configured High-NA optics, this enables the system to expose a full 26 mm × 33 mm field in one scan pass, restoring the field size to that of Low-NA tools. This obviously eliminates the need for stitching and all the challenges associated with it.

However, the shift to larger photomasks would require a complete overhaul of the mask supply chain, from blank preparation and e-beam writing to handling and fab integration. ASML acknowledged that internal studies on larger masks are in progress but has not committed to bringing the capability to market. The change would disrupt the company's platform unification strategy for Low-NA, High-NA, and eventually Hyper-NA tools and potentially reduce sales of higher-end tools.

In photoresist development, metal-oxide resists are gaining ground as the preferred option for High-NA, according to the Intel's presentation at SPIE. These materials provide better performance in terms of resolution, line-edge roughness, and dose sensitivity, especially important given the thinner films required by the thin depth-of-focus associated with High-NA optics. Traditional chemically amplified resists struggle with etch resistance at the thicknesses now needed, while metal-oxide formulations retain sufficient durability during pattern transfer. Most SPIE 2025 data shared for High-NA tools used metal-oxide resists rather than legacy organics, according to SemiAnalysis.

The method of applying and developing photoresist is another point of industry concern. Tokyo Electron currently dominates the standard wet process with spin-on coating and wet development in its track tools. Lam Research is attempting to gain share by promoting a dry deposition and dry development approach, done in its proprietary tools.

Conclusion

Scientists at the University of Massachusetts Amherst have introduced a novel method for aligning layers in chips using lasers and metalenses. The new technique is claimed to achieve accuracy down to the atomic scale, reports SciTechDaily. This advancement could be critical for next generation process technologies as well as integration of multi-chiplet 3D designs.

Overlay accuracy — precise alignment of one layer of a chip with the underlying layer — is one of the most critical capabilities of today's chipmaking tools as each wafer with logic chips requires over 4,000 manufacturing steps performed by different machines. Contemporary chipmaking tools perform overlay operations primarily using advanced optical metrology, alignment marks, and closed-loop control systems integrated into photolithography systems.

However, existing methods face limitations such as the inability to simultaneously focus on widely spaced layers and a resolution limit of about 2 – 2.5nm. These issues introduce potential inaccuracies during refocusing and positioning, which could be problematic for both for next-gen production nodes and vertically stacked multi-chiplet designs in the future.

The method proposed by the UMass Amherst team involves placing specially designed concentric metalenses on chip surfaces. When illuminated with a laser, these lenses generate holographic interference patterns. By analyzing these patterns, researchers can determine how much two chip layers are misaligned, including the direction and precise amount of displacement across all three spatial axes.

Their technique can detect lateral misalignments as small as 0.017nm and vertical deviations down to 0.134nm. This surpasses their original goal of 100nm precision and exceeds what optical microscopes can resolve. Furthermore, they believe that the method could lower manufacturing costs by simplifying one of the most complex steps in chip production and 3D chip integration. Unfortunately, it is unclear whether the setup can be integrated with existing lithography tools, bonding tools, and though silicon vias formation tools. If not, the technology will hardly gain grounds in the semiconductor industry.

This laser hologram technology has implications beyond chip manufacturing. A similar setup — a basic laser source and a camera — can be adapted to measure physical movements. For instance, a shift in a surface due to pressure or vibration can be translated into an optical signal. This opens opportunities in applications like environmental sensing, industrial monitoring, and biomedical diagnostics.

Donald Trump introduced a sweeping set of import taxes on Wednesday that targeted nearly all U.S. trading partners — but offered a notable exemption for the high-tech industry.

The tariffs include a flat 10% fee on all incoming goods beginning April 5, followed by higher, customized rates for about 60 countries starting April 9. However, numerous items, including computer chips, copper, medicine, and lumber, will be excluded from the new import fees. Initial reports indicate the administration has said tariffs for semiconductors could come at a later date.

There is a catch with the exceptions. A senior official from the White House told a Reuters correspondent that the Trump administration is preparing separate tariffs for industries like semiconductors, drugs, and critical minerals. On the one hand, this means that these items will remain outside the scope of the current tariff framework (i.e., no 32% tariff on Taiwanese chips for now); on the other hand, it remains to be seen how high those import taxes will be.

Initially excluding semiconductors from the sweeping import taxes enables American companies to buy chips made in Taiwan without any curbs — good news for AMD, Broadcom, Nvidia, and Qualcomm, as the majority of their chips are produced in Taiwan. Also, the exemption of semiconductors applies to chips produced in Europe, Japan, and South Korea, which is again good news for automotive and consumer electronics industries in the U.S. as both use loads of chips.

The exclusion also concerns chips made in China, however, including those made by companies controlled by the state and at fabs sanctioned by the U.S. For now, China's semiconductor industry can rejoice, unlike the American semiconductor industry, which will now have to pay 20% extra for European and 24% extra for Japanese tools they import to their fabs in the U.S.

While 20% to 24% does not sound like a lot compared to the over 50% tariff set on China-originated goods, we are talking about very expensive equipment. ASML's lithography tools cost a significant amount of money: a Low-NA EUV litho machine costs around $200 million, whereas a High-NA EUV litho system is projected to cost $380 million even without extra taxes. With Trump's tariffs, these tools will cost $240 million and $456 million, respectively, disrupting all the capital expenditure plans for companies building advanced semiconductor production facilities in the U.S., including Intel, TSMC, and Samsung Foundry.

Those who use mature process technologies — such as GlobalFoundries and Texas Instruments — will also have to pay extra for their tools. Ultimately, this will make chips produced in the U.S. more expensive.

The highest adjusted rate goes to Vietnam at 46%, followed by Cambodia at 49%, Taiwan at 32%, and China at 34%, which on top of a previous 20% duty, brings China's total to 54%. Other countries affected include the European Union at 20%, Japan at 24%, South Korea at 25%, and India at 26%. The tariffs look massive and, in the case of China, even prohibitive.

While the punitive tariffs set on the majority of goods made in China were something to be expected, the massive import taxes on products from countries like India (32%), Taiwan (32%), Thailand (36%), Vietnam (46%), and other countries in the region will clearly hit the high-tech industry supply chain as large PC makers have moved their production away from China to these countries to avoid tariffs from the U.S. administration.

It seems manufacturers cannot actually avoid these tariffs, so expect products like PCs, smartphones, TVs, and other high-tech items to get more expensive in the U.S. and profitability of American companies to get lower.

However, some goods and countries (such as those already under heavy sanctions) are excluded. These exemptions include semiconductors, copper, drugs, lumber, specific minerals that the U.S. does not produce domestically, precious metals, energy resources, steel, aluminum, and vehicle-related goods already taxed under existing rules, and products covered under national security provisions.

A 43-year-old Russian engineer is accused of secretly supplying sensitive technical information from ASML, NXP, and TSMC to Russia, allegedly to assist in building a 28nm-capable fab there, reports Dutch newspaper NRC.

The engineer, identified in court documents only as German A., illicitly earned about €40,000 and now faces 18 to 32 months in prison. Though German A. alone could not steal full designs for a semiconductor, a coordinated group could potentially assist semiconductor production in Russia.

Hundreds of confidential documents stolen

German A. is accused of supplying Russia with confidential technical materials from ASML, GlobalFoundries, NXP, TSMC, and GlobalFoundries, including semiconductor production manuals and various chipmaking machines. The investigators reportedly found that he obtained 105 internal documents from ASML and 88 files related to TSMC.

The materials did not contain complete blueprints for building wafer fabrication equipment or something more significant (e.g., a fab itself or how to design a process technology). Still, they were labeled confidential and could support the setup of a basic semiconductor line capable of producing chips at 28nm-class process technology, which is good enough for military applications.

Investigators believe he shared this data via cloud storage and messaging apps and handed over a USB stick in Moscow, allegedly earning around €40,000 in the process.

German A. is reportedly also linked to an attempt to acquire a chemical vapor deposition tool, possibly as part of efforts to equip a future chip facility in Russia. However, according to the report, the tool was first redirected to Israel and then never delivered.

In August 2024, German A. was taken into custody following a report from the national intelligence agency. A month later, ASML and NXP were officially informed of the espionage suspicion. His case is now being handled in court, and authorities suspect ties to Russian intelligence. Both firms are involved in the investigation and have filed complaints against the former employee.

While German A. could not possibly steal blueprints of all tools necessary to build a fully functioning semiconductor production facility in Russia, a network of such spies could potentially do the job and revive semiconductor production in the hostile nation.

A long career

Before his arrest in 2024, German A had a long career in the semiconductor development and production industry. In 2008 and 2009, he interned at Imec, a research center in Belgium. After that, he joined the Greek research institute NCSR and later started to work at Fab 1, a Dresden facility of GlobalFoundries.

In 2015, he joined a Dutch start-up called Mapper, which developed a maskless lithography technology based on massively parallel e-beam writing using 10,000 – 13,000 e-beams. Mapper received financial backing from Rusnano, a state-controller high-tech investor, in 2012 and built a small site in Russia to manufacture MEMS (micro-electromechanical systems).

When Mapper went bankrupt in late 2018, ASML absorbed its assets and personnel under pressure from the Dutch and U.S. governments to protect the technology. German A. was among over 100 engineers who moved to ASML, where he operated machines for producing electro-optical components. For now, ASML's employees describe German A. as a 'not high flyer,' whereas others claim he was a committed but introverted technician who had difficulty communicating.

However, according to NRC, German A.'s name appears on four patent filings associated with ASML, the latest of which was published just a month ago. These documents list several inventors, and it is unclear whether German A. played a significant role in those innovations.

A review of his digital activity shows that he accessed restricted files on two days in December 2020, even though he had no need for them. At the time, the company's internal security systems did not raise any alerts. Experts asked by NRC believe the leaked data includes presentations and manuals but not the core plans needed to construct chip machines or an entire plant. His contract ended in 2021 when ASML outsourced his work.

After ASML, German A. used recruitment agencies to look for work in research roles but was unsuccessful. In January 2022, during the pandemic, he joined NXP in Nijmegen on a temporary contract as a process technician. In May of that year, he contacted a company in Nijmegen to request a quote for a used chemical vapor deposition tool from ASM International. Initially, the equipment was supposed to be shipped to Germany, but he later changed the destination to Israel. The item was never delivered. This is now seen as an attempt to gather parts for a new facility.

Statements from his former spouse reveal that by late 2023, he was in touch with Russian researchers about building a fab in Russia capable of producing chips using a 28nm technology. Back then, Russian entities were blacklisted and could not get advanced chips from prominent suppliers, whether distributors or foundries.

That same year, he held a one-year position at TU Delft but remained isolated, and investigators found no signs of theft there.

Not first time

Both ASML and NXP experienced breaches involving unauthorized access in the past. In late 2023, it was revealed that a cyber group linked to China had been covertly operating within NXP's systems for an extended period. ASML also battles frequent cyberattacks and insider threats: in early 2022, a former Chinese employee stole confidential data. Although that employee, just like German A., lacked access to complete designs needed to construct a fab tool or equip a fab, a broader network of similar operatives could realistically piece together enough to boost the semiconductor industries of China and Russia.

In response, both companies have strengthened their digital defenses: internal systems now limit access between departments and employee activity is tracked for unusual behavior.

Chinese chipmakers have been gradually shifting some of their production to tools made in China in a bid to support the local wafer fab equipment ecosystem and reduce reliance on tools produced abroad. China already has several well-known manufacturers of chipmaking tools that specialize in one or two types of equipment, which set sales records in 2024. However, there is a little-known Huawei-linked company, Si Carrier Technologies, that has revealed it has almost all types of wafer processing tools in its catalog published at Semicon China and re-published by Zhininren. 

SiCarrier Technologies is a startup widely discussed at this year’s Semicon China, but is little known outside of the People’s Republic. The company is closely linked to Huawei and was founded four years ago in Shenzhen to develop world-class fab tools that would compete against front-end chip production equipment made by market leaders ASML, Applied Materials, KLA, and Lam Research, according to Nikkei. SiCarrier's main investor is Shenzhen Major Investment Group, a government-backed fund supporting other chip ventures connected to Huawei, including PengXinWei Integrated Circuit Manufacturing and SwaySure Technology. 

SiCarrier currently operates R&D centers in Shanghai, Beijing, Xi’an, Wuhan, Chengdu, Hangzhou, and overseas. Its end-to-end development chain covers materials, components, and full systems. To support rapid development, the company aggressively recruits senior engineers from top global companies like ASML and Applied Materials. 

The SiCarrier catalog presented at Semicon China includes a wide range of semiconductor manufacturing equipment, metrology tools, and inspection systems. The catalog does not include any lithography tools (possibly to keep its lithography advancements a secret), but Nikkei reports that the company already has litho tools capable of processing 300-mm wafers on 28nm process technologies and older. Even without lithography machines, the company lists dozens of tools that can perform the vast majority of steps in the front-end semiconductor production flow. The company also has metrology, inspection, and testing tools. 

On the process side, the catalog includes tools used for atomic layer deposition (ALD) for dielectrics and metal gates, chemical vapor deposition (CVD), physical vapor deposition (PVD) blanket film deposition and metal contact deposition, epitaxy, etching, and annealing. The catalog does not explicitly characterize tools and their capabilities in terms of actual fabrication processes, but it does frequently refer to ‘advanced process nodes’ as well as ‘future advanced nodes.’ 

On the metrology and inspection front, the catalog includes tools for the optical inspection of both patterned and unpatterned wafers, atomic force microscopy for morphology inspection at nanoscale resolution, and advanced measurement systems for thin film thickness, element composition, and crystallinity. 

Finally, SiCarrier also has various testing machines, including wafer electrical performance tests, known-good die tests, and functional tests. However, these tools are currently aimed mostly at power semiconductors. 

For now, it is unclear whether all of the tools that SiCarrier lists can be ordered and acquired. It is also unclear whether these machines are compatible with existing production flows that rely on machines from ASML, Applied, KLA, Lam, TEL, and others. 

However, Nikkei claims that SiCarrier has partnered closely with Huawei, which has assembled a large internal team focused on semiconductor manufacturing and equipment, and that they are working to improve process implementation and identify technical challenges across production lines. This could mean that SiCarrier and Huawei intend to build tools for a ‘proprietary’ production flow involving exclusively Chinese tools. If this is the case, it could take years before the first fab with such a flow comes online. Nonetheless, given SiCarrier’s pace so far, it could well impress the industry.