OpenAI and Broadcom have introduced Jalapeño, a custom-built inference processor designed specifically for modern large language models and future agentic AI workloads, which is designed to deliver performance per watt they claim is higher than today's leading-edge hardware. OpenAI considers its hardware project a strategic one and envisions Jalapeño to be the first generation of its inference hardware.

Not another AI accelerator

OpenAI stresses that Jalapeño is a purpose-built inference ASIC and not a repurposed training accelerator or a general-purpose AI processor. OpenAI says the architecture of Jalapeño was designed based on its understanding of LLM behavior and is meant to address practical bottlenecks that matter for inference at scale, including costly data movement, balance between compute and memory resources, networking efficiency, and overall behavior. OpenAI also states that the design of the processor is meant to wed high throughput with low latency (which is why it uses a huge compute chiplet and HBM memory and not cheaper types of DRAM like many other inference accelerators), which will be particularly handy for reasoning and agentic workloads.

In addition, OpenAI and Broadcom claim the processor is built to deliver higher effective utilization than conventional AI accelerators and deliver performance that is close to the theoretical maximum, which means very high efficiency both in terms of costs and in terms of power. Meanwhile, the companies did not disclose performance targets for their Jalapeño ASIC, so these claims should be taken with a grain of salt.

Engineering samples are already operating in the lab at target clock speed and power (though Broadcom and OpenAI do not disclose details about this, either), and OpenAI says it is running machine learning workloads, such as GPT-5.3-Codex-Spark.

The two companies also claim that early internal testing indicates that Jalapeño's performance-per-watt is substantially better than 'current state-of-the-art hardware,' although no hard numbers, benchmarks, memory configuration, or other details are disclosed, so again, we will have to take the claims with a grain of salt. In addition, one must bear in mind that while Jalapeño can purportedly beat existing AMD's Instinct MI350-series and Nvidia's Blackwell-based accelerators, it remains to be seen how competitive it will be against AMD's Instinct MI400-series and Nvidia's Rubin-based offerings.

"Jalapeño was designed from the ground up for LLM inference using detailed insights from our close collaboration with OpenAI researchers," said Richard Ho, who leads OpenAI's hardware program. "We optimized the architecture around the kernels, memory movement, networking, and serving patterns that matter most for frontier AI models. Based on early testing, Jalapeño will efficiently execute our most important workloads close to the hardware’s theoretical limits."

A massive chip with six HBM modules

While Broadcom and OpenAI did not disclose specifications of Jalapeño, they did show its wafer and packaging, so we can do a brief analysis. The package appears to contain one large compute chiplet surrounded by six HBM modules and another chiplet that likely packs input/output interfaces and is surrounded by two structural dummy dies.

The wafer image does look like a Broadcom-style systolic-array-heavy accelerator, in the sense that it shows a very regular, repeated, columnar floorplan with what looks like replicated compute regions and fixed infrastructure macros. Yet, keep in mind that we are speculating, and the image is not clean enough to say that this is definitely Broadcom's standard TPU-like systolic array template with some perks from OpenAI,

From the image alone, it is impossible to tell whether Jalapeño uses a true 2D systolic array, a set of 1D/2D matrix engines, a collection of vector or tensor tiles, or some other inference datapath. All we can say is that the die has a highly repetitive floorplan consistent with several kinds of tiled AI accelerator architectures.

What we can tell from the image is the approximate die size of Jalapeño's compute chiplet based on the size of HBM3/4 packages (10.975 mm × 10.975 mm) that surround it. From what we can tell, the chiplet measures 25.46 mm (width) × 33 mm (height), which means that its die size is around 840 mm², which is very close to the reticle size of EUV lithography systems (858 mm²). Given that the quality of the shot is poor, the die size we estimate cannot be 100% accurate, but we suspect it is close enough.

The die size of Jalapeño's compute chiplet implies that it packs quite a lot of compute oomph, though, of course, we cannot make performance estimates based on this metric. Yet, it is safe to say that Jalapeño's compute die is considerably bigger than compute dies of other inference accelerators on the market and more resembles processors for AI training. Speaking of processors for AI training, we increasingly see multi-chiplet designs for these workloads as companies like AMD and Nvidia want to pack as much performance as possible. Meanwhile, the fact that OpenAI and Broadcom chose to go with a large compute chiplet possibly indicates that they wanted to reduce latencies by as much as possible.

Designed in nine months

The companies say the chip reached tape-out in just nine months and is slated for deployment beginning in late 2026, which represents an extremely fast turnaround time in ASIC design. It is unclear whether Broadcom and OpenAI extensively used artificial intelligence to define and then develop Jalapeño, though the companies admitted that they used OpenAI's models to speed up parts of the chip's design and optimization work. Typically, it takes 1.5 – 2 years to design an ASIC from scratch, so AI can shrink the development cycle. Another means to accelerate the design cycle is Broadcom's extensive reuse of its logic across different custom designs to deliver new chips faster than other companies.

It is noteworthy that, according to the announcement, Jalapeño is designed to support not only OpenAI's own workloads but also present and future LLMs across the industry, which potentially lets OpenAI sell its hardware to third parties, assuming that it can get enough supply from Broadcom and TSMC. Meanwhile, the chief executive of Broadcom indicates that Jalapeño will be deployed at gigawatt-scale data centers with Microsoft and other partners starting this year, though it is unclear whether the processor will be used exclusively for OpenAI workloads or will be available for other tenants as well.

"Our collaboration with OpenAI represents a fundamental commitment to scaling the physical infrastructure required for the next decade of AI," said Hock Tan, President and CEO, Broadcom. "This is just the beginning of a multi-generation roadmap. By co-developing our industry-leading silicon directly with OpenAI, we are enabling the deployment of gigawatt-scale data centers with Microsoft and other partners beginning in 2026."

Broadcom and Meta this week announced the extension of their relationship with a long-term agreement under which Broadcom will supply Meta multiple generations of custom-designed Meta Training and Inference Accelerator (MTIA) hardware through 2029. The package includes supplying hundreds of thousands of AI processors. The deal is significant enough for Hock Tan, chief exec of Broadcom, to leave Meta's board of directors, ostensibly to avoid a conflict of interest.

Under the terms of the deal, Broadcom will supply Meta multiple generations of custom-designed AI accelerators for training and inference that will be built around Broadcom's foundational XPU platform, which enables to combine custom differentiating silicon with standard logic, memory, and high-speed I/O to greatly improve efficiency and lower the cost of such bespoke processors. The companies are tight-lipped about the exact volumes of hardware to be supplied, though they say that it will consume multiple gigawatts of power, with initial commitments exceeding 1 GW of compute capacity. In addition, Broadcom will supply Meta Ethernet networking solutions for scale-up, scale-out, and scale-across requirements.

It is necessary to note that Broadcom participates in Microsoft, Meta, and OpenAI-led multi-source agreements for unified optical compute interconnects for scale-up interconnects. To that end, Broadcom will likely supply Meta custom AI accelerators with optical scale-up interconnects over time.

"Meta is partnering with Broadcom across chip design, packaging, and networking to build out the massive computing foundation we need to deliver personal superintelligence to billions of people," said Meta founder and CEO Mark Zuckerberg. "As we roll out more than 1GW of our custom silicon to start and then multiple gigawatts over time, this partnership will give us greater performance and efficiency for everything we are building."

One of the interesting implications of the deal is that MTIA accelerators use modified RISC-V-based cores from Andes Technology for scheduling and orchestration, as well as some basic processors. While compute blocks (tensor engines, vector engines, systolic arrays, etc.) are not RISC-V-based, the scale of the deal will likely benefit both Andes Technology and the RISC-V ISA ecosystem in general.

Hock Tan will step down from Meta's board of directors and move into an advisory role, likely in a bid to avoid a conflict of interest as he remains chief executive of Broadcom. Nonetheless, in his new role, he will guide Meta's custom silicon roadmap and influence its future infrastructure investments.

"We are pleased to expand our strategic collaboration with Meta as they pioneer the next frontier of artificial intelligence," said Hock Tan, President and CEO, Broadcom. "This initial MTIA deployment is just the beginning of a sustained, multi-generation roadmap to serve the trajectory of massive growth over the next few years highlighting Broadcom’s unmatched leadership in AI networking and the power of our foundational XPU custom accelerator platform."

Broadcom disclosed in a securities filing on Monday that it’ll supply Anthropic with roughly 3.5 gigawatts of Google TPU capacity starting in 2027, and separately committed to designing and supplying future generations of Google's TPUs through 2031.

This new Anthropic capacity is in addition to the 1 GW already coming online in 2026 under the Google Cloud agreement announced last October, and the filing states that Anthropic's use of the expanded capacity is contingent on its continued commercial performance.

The Monday filing covers two linked arrangements. The first is a supply assurance agreement under which Broadcom will provide networking and other components for Google's next-generation AI racks through 2031. The second is the expanded three-way collaboration with Anthropic, which routes Google-designed TPUs to the AI company via Broadcom as part of the multi-gigawatt commitment Anthropic has made for next-generation TPU-based compute. The vast majority of the new infrastructure will be located in the United States, extending the $50 billion American AI infrastructure commitment Anthropic made in November 2025.

Anthropic said in a blog post that its annualized revenue run rate has now passed $30 billion, up from around $9 billion at the end of 2025, and that more than 1,000 business customers are spending over $1 million a year on its services, double the figure from February.

"This groundbreaking partnership with Google and Broadcom is a continuation of our disciplined approach to scaling infrastructure: we are building the capacity necessary to serve the exponential growth we have seen in our customer base," Krishna Rao, Anthropic's chief financial officer, said in the blog post. Amazon Web Services remains Anthropic's primary cloud and training partner under Project Rainier, the Trainium 2-based supercluster in Indiana, and the new Google-Broadcom capacity sits alongside that arrangement rather than replacing it.

Google, of course, owns both the TPU architecture and software stack, with Broadcom acting as the silicon implementation partner, converting Google's architecture into a manufacturable ASIC layout while supplying high-speed SerDes, power management, and packaging. TSMC handles fabrication.

The same division of labor underpins Broadcom's separate $10 billion custom silicon program with OpenAI, announced as a 10 GW co-development effort last October, which makes Broadcom the implementation layer for two of the three largest U.S. frontier model developers. Analysts at Mizuho, led by Vijay Rakesh, estimated that Broadcom would record $21 billion in AI revenue from Anthropic in 2026 and $42 billion in 2027, figures Mizuho published in a note following Broadcom's March earnings call, though the SEC filing didn’t contain any specific amounts.

Both Anthropic and OpenAI continue to draw heavily on Nvidia GPUs through cloud providers including AWS, Google Cloud, and Microsoft Azure, and OpenAI has separately committed to 6GW of AMD GPU capacity, with the first gigawatt expected in the second half of this year.

As AI clusters grow larger, they begin to use optical interconnects for scale-out connectivity. However, the day when they require optical interconnects for scale-up connectivity may be approaching soon. To prep for that day, hyperscalers Microsoft, Meta, and OpenAI teamed up with hardware designers AMD, Broadcom, and Nvidia to develop a protocol-agnostic scale-up interconnection technology for AI clusters.

To do so, the group of companies this week established the Optical Compute Interconnect (OCI) Multi-Source Agreement (MSA) group to define an open optical connectivity specification for scale-up interconnections used inside large AI systems and racks to enable hyperscalers to use optical cables instead of copper to connect more accelerators at high speed and predictable power. In practice, this means the consortium will develop a common optical physical layer (PHY) and unified components to support various protocols, such as UALink for AMD and Broadcom, and NVLink for Nvidia.

The OCI connectivity technology for short-reach optical links used in AI racks and scale-up clusters will define a common PHY based on NRZ signaling and wavelength-division multiplexing (WDM), starting at four wavelengths × 50 Gb/s (200 Gb/s per direction) and scaling all the way to 800 Gb/s per fiber. Over time, the roadmap is expected to expand both wavelength counts and signaling rates, targeting 3.2 Tb/s per fiber and beyond as the ecosystem evolves. The technology will support pluggable optical modules, on-board optics, and co-packaged optics (CPO) integrated directly with compute silicon.

"The growing need for optical scale-up interconnect to support large AI systems later this decade is clear," said Brian Amick, Senior Vice President, Technology & Engineering at AMD. "AMD is a founding member and strong supporter of the OCI MSA as it establishes an open specification for the industry to foster a robust, multi-vendor optical scale-up interconnect ecosystem."

The common optical layer will enable different processors and interconnect protocols to operate over the same fiber infrastructure and switches from different suppliers, ensuring flexibility for hyperscalers while retaining the competitive advantages of the protocols used by developers of AI accelerators, AI GPUs, XPUs, and other processors. In addition, the standardized OCI roadmap is meant to simplify system integration, reduce development risk, and shorten deployment cycles for new generations of AI hardware.

"Broadcom is proud to draw upon our multi-generational CPO platform and industry partnerships to drive the OCI specification forward," said Near Margalit, Vice President & General Manager, Optical Systems Division at Broadcom. "The OCI-MSA allows for seamless integration with existing electrical SerDes-based ASICs while providing a clear path to direct ASIC integration, ensuring the ecosystem remains flexible and high-performing."

While the OCI MSA group is headed by AMD, Broadcom, and Microsoft, which are known supporters of open industry standards, this is clearly not a traditional standard body like the Ultra Ethernet Consortium or UALink Consortium, which will have an impact on how the technology is developed.

Firstly, the OCI MSA is hyperscaler-driven rather than vendor-driven. The arrangement is unlike most industry consortia, which are organized and led by independent hardware vendors (IHVs), IP companies, and networking suppliers.

Secondly, OCI targets a very specific architectural layer of AI systems — short-reach links that connect accelerators and switches within a scale-up domain. By contrast, traditional hardware development groups tend to standardize on a vertically integrated set of technologies to be widely adopted across a market or markets.

Thirdly, as the organization is a Multi-Source Agreement (MSA) group, it will, by definition, be faster than a typical industry standard setting body. MSAs are meant to enable select companies to align on electrical/optical interfaces and build interoperable products quickly, without the lengthy consensus processes typical of classic organizations like JEDEC or the Ultra Ethernet Consortium (which are designed to unite tens or hundreds of companies and support an entire industry). The OCI MSA — at least for now — will enable AMD, Broadcom, and Nvidia to build interoperable short-reach interconnections for Microsoft, Meta, and OpenAI.

"Nvidia is a founding member of the OCI MSA to establish a common optical standard across global AI infrastructures," said Gilad Shainer, Senior Vice President of Networking at Nvidia. "By equipping best-in-class compute with state-of-the-art optics, the OCI MSA can deliver the scale and performance required by the next era of super-intelligence."

UALink (short for Ultra Accelerator Link) is an upcoming interconnect technology designed to enable high-speed, low-latency communication between AI accelerators (ASICs, GPUs, FPGAs, NPUs, XPUs) and other compute devices across a scale-up logical domain. Many see it as an important path forward for the future of AI data centers due to its planned performance, cost, and power efficiency advantages, not to mention that, as an open standard, it will reduce vendor lock-in.

In 2025, the UALink Consortium published revision 1.0 of the UALink specification, marking a point after which hardware designers can officially implement the technology into their AI/HPC accelerators and switch ASICs required to build AI pods with up to 1,024 accelerators. But while UALink technology is widely supported by the industry, and its specification that defines accelerator-to-accelerator comms is available now, its broad adoption is several years away.

What is UALink?

UALink would enable programmers to treat multiple accelerators like a single processor, with a large memory pool (or at least enable parallelism with minimal effort from developers) and to greatly simplify network communications between processors.

UALink was designed as a competing technology for Nvidia's proprietary NVLink interconnect that is supported by a broad range of industry players, including AMD, Arm, AWS, Broadcom, Cadence, Intel, Google, Marvell, Meta, Microsoft, and Synosys, just to name a few.

The UALink 200G 1.0 specification is designed to support up to 1,024 accelerators per domain (or pod) at a speed of 212.5 GT/s, enabling direct memory access between accelerators using simple load/store and atomic operations, and thus behaves as a single system. UALink is built around a lightweight layered protocol stack that includes a Protocol Layer (UPLI), Transaction Layer (TL), Data Link Layer (DL), and Physical Layer (PL).

At the physical layer, UALink reuses standard Ethernet PHY signaling (such as 100GBASE-KR1, 200GBASE-KR2, and 800GBASE-KR4) to simplify implementation, but introduces custom framing, forward error correction (FEC), and latency optimizations. Each serial lane runs at 212.5 GT/s, delivering an effective 200 GT/s of data per lane after FEC overhead. Meanwhile, configurations of x1, x2, or x4 links are supported, to enable up to 800 GT/s of bandwidth per direction per link. The DL layer formats traffic into 640-byte FLITs with CRC and segment headers, while the TL layer compresses request and response messages into 4–16 byte payloads to cut latencies and keep die area in check.

According to developers of UALink, the protocol ensures deterministic latency below 1 µs and achieves up to 93% effective bandwidth utilization, which is very high. UALink does not replace Ethernet, PCIe, or CXL, but is designed to coexist with these technologies within system nodes, serving solely for peer-to-peer traffic between accelerators.

When it comes to system architecture, it is centered around UALink Switches (ULS) that enable point-to-point accelerator communication within and across racks. These switches must support lossless delivery, non-blocking fabric behavior, and virtual pod isolation. Each accelerator is assigned a 10-bit routing ID (thus the limitation of 1,024 accelerators per pod), and switches maintain per-port routing tables to support scale-up topologies. The standard includes fault containment, error detection, and isolation mechanisms that limit failures to a single virtual pod without impacting others in the 'large' scale-up pod.

While UALink version 1.0 is here, the technology is still a work in progress as future versions are expected to add memory coherency (already supported by NVLink) and virtualization features.

Why UALink?

Today, Nvidia's NVLink allows the company and its partners to build pods with up to 576 GPUs (GPU packages), enabling scale-up world sizes that feature both high bandwidth and low latency. In contrast, the scale-up world size of AMD's Instinct MI300-series accelerators (or Nvidia's H100 GPUs) is limited to eight GPUs per box, as connectivity outside of the box is enabled by Ethernet.

Ethernet, even at 400G/800G with RDMA (RoCE), is fundamentally optimized for packet-based, scale-out communication, not the low-latency, memory-semantic, load/store operations required for scale-up AI accelerator interconnects. By contrast, UALink provides direct memory access between accelerators, supports atomics, and preserves ordering semantics across endpoints. Even with various optimizations, Ethernet introduces higher round-trip latency (~2 µs+) and software stack overhead, something that limits Ethernet even for modern data centers. By contrast, UALink targets <1 µs round-trip latency, supports lossless flow control, and operates with fixed-size FLITs and ID-based routing.

Even high-end Ethernet switches like Broadcom's Tomahawk Ultra require NICs to translate load/store commands into RDMA commands, which adds latency and complexity that UALink bypasses by supporting native hardware messaging.

Building the UALink ecosystem

As the UALink Consortium includes over 90 members, it is reasonable to assume that there are dozens of companies currently working on various AI and HPC accelerators with UALink support. In addition, connectivity companies are working on switches. Finally, Synopsys has been offering UALink IP and PHY for about a year now, which greatly simplifies the implementation of the technology.

Integrating ready IP and PHY from vendors like Synopsys or Cadence into an AI accelerator or system-on-chip typically takes 12 to 24 months, depending on the complexity of the chip, project maturity, and some other development-specific factors. Therefore, processors with UALink could be months or quarters away. Synopsys says that the interest in the technology is significant.

"UALink is a truly open standard that is attracting significant interest from both accelerator and switch companies," Priyank Shukla, Director of Product Management for HPC IP at Synopsys, told Tom's Hardware. "We have successfully delivered our Synopsys UALink 200G IP solution, which includes both controller and PHY IP, to customers in the switch and accelerator markets."

Among the companies that have already confirmed development of processors with UALink are AMD (Instinct MI400, MI500-series) and Marvell (as an option for custom silicon aimed at hyperscalers), though expect the technology to be supported by others shortly. However, the deployment of UALink switches across the MI400 series is dependent on how quickly we can see UALink switching silicon in 2026. In the absence of such switches, the MI400 series may be forced to use UALink-over-Ethernet, which is a less-than-ideal use case.

In fact, it looks like the availability of switches could be the main factor that slows down the adoption of UALink technology.

Astera Labs is currently developing smart fabric switches, signal conditioners, controllers, and more. The company expects to deliver its first UALink solutions in 2026 to solve scale-up connectivity challenges, but it has not disclosed what comes next. It also observes that the interest in the technology is significant.

"While I cannot speak to specific product timelines, what I can tell you is that the UALink ecosystem momentum has exceeded our expectations since releasing the 1.0 specification in April," Chris Petersen, Fellow of Technology and Solution Architecture at Astera Labs, told Tom's Hardware. "Our customers — particularly hyperscalers — consistently tell us three things drive their infrastructure decisions: they need open standards with multi-vendor support, they're focused on total cost of ownership, and they need faster time-to-market to deploy the compute scale that cutting-edge AI applications demand."

Unlike Astera Labs, Broadcom — which develops custom AI processors for its clients as well as various communications hardware for data centers — seems a little more restrained, even though it is a founding member of the UALink Promoters Group. The company cannot talk about whether it is building UALink-supporting accelerators for its customers, and it positions its Tomahawk Ultra Ethernet solutions for scale-up connectivity of AI accelerators.

"We can say that we see tremendous momentum behind using Ethernet for scale-up," a spokesperson for Broadcom told us. "Tomahawk Ultra was purpose-built for Ethernet-based AI scale-up and is available today."

Is there a roadblock?

Although the UALink 1.0 specification is ready and can be used to build switching hardware, the technology is missing several things, including the 128G DL/PL specification (was expected in July 2025, but there is no word whether it has been finalized), In-Network Collectives (INC, was expected December 2025) hardware acceleration of collective operations, and a 128G/200G UCIe PHY chiplet specification.

None of these features is mandatory for building switching hardware, so building a spec-compliant switch ASIC under the UALink 1.0 is possible. However, the 128G DL/PL specification will be important for next-gen, mixed-rate, or forward-compatible switch designs that support a slower data transfer rate. Meanwhile, INC is required to support large-scale training efficiently and interoperate with future hardware. Without INC, collective operations must be executed in software or via network cards, which adds latency and hinders the advantages of UALink.

"The UALink Consortium is actively working on additional specifications,s including management, UCIe IO chiplet integration, and In-Network Collectives that will further enhance the ecosystem to meet these demands," said Petersen. "With 85+ member companies driving this expanding specification roadmap, UALink is responding to a real market urgency for scale-up solutions that can keep pace with AI's exponential growth."

Perhaps some of the companies that currently work on UALink-supporting hardware do not want to commit to a particular roadmap before all the features are supported by the specification. However, the importance of INC may not be that significant.

"INC is not commonly deployed across all applications, and we also see many of today's solutions that could use INC are deployed without INC enabled," Ahmad Danesh, Associate Vice President of product management at Astera Labs, told Tom's Hardware. "The UALink Consortium BoD considered this when defining UALink 1.0, and the early adopters see a higher priority on delivering higher performance and lower TCO through UALink's purpose-built memory-semantic protocol. The lack of INC specification in UALink 1.0 is not expected to affect launch schedules of UALink hardware, but the consortium continues to advance the specification and actively works on INC to deliver even more value with UALink."

Adoption will take time

UALink is a promising and open interconnect standard designed to enable high-speed, low-latency communication between AI accelerators that has gained support from over 90 companies.

However, while AMD and Marvell have confirmed UALink-based processor development and Synopsys already offers controller and PHY IP, full-scale deployment will take time due to integration cycles and the current lack of UALink-compliant switches.

Although future enhancements like In-Network Collectives (INC) and the 128G PHY spec are not required to build compliant hardware, their absence may delay broader commitments, as some companies may wait for these features to be finalized before locking development of their UALink hardware and releasing it to market. Nonetheless, Astera Labs expects the first products supporting UALink to hit the market at some point this year.

Today at CES, Broadcom is expanding the family with two new dual-band Wi-Fi 8 chips that combine 2.4 GHz and 5 GHz radios into a single chip. The BCM6714 is the lower-end offering, with a 3x4 arrangement. That means it supports three spatial streams on the 2.4 GHz band and four on the 5 GHz band. The BCM6719 ups the ante by delivering four spatial streams across both bands.

And with that news, I can already see the collective eyerolls of the enthusiast community. When Wi-Fi 7 launched, the first devices to hit the market were more expensive tri-band solutions that supported the 2.4 GHz, 5 GHz, and 6 GHz bands. Later, more affordable networking products arrived, supporting only the 2.4 GHz and 5 GHz bands. While this allowed manufacturers to hit a lower price point, it also created confusion in the marketplace – just because a router was labeled Wi-Fi 7 didn't mean it supported the full feature set. That confusion will live on for another generation.

These two new entry-level chips join the BCM6718, which Broadcom announced last year, one of its first Wi-Fi 8 (802.11bn) compliant chips aimed at the consumer/residential wireless market. It's a 4-stream tri-band Wi-Fi (2.4 GHz, 5 GHz, and 6 GHz).

But that's not all; Broadcom also announced the BCM4918 Wi-Fi 8 APU, which is compatible with the BCM6714, BCM6719, and BCM6718. This system-on-chip is designed for high-performance computing and AI acceleration. Not only does it include an onboard neural engine for on-device AI/ML inference and acceleration, but it also features dedicated network engines to handle wireless and wired traffic, bypassing the CPU. It supports multi-gigabit Ethernet for powering your high-flying wired network. The chip also enabled Edge-AI processing and real-time network optimization.

Broadcom says it is already sampling the BCM6714 and BCM6719 to its "early access customers," pointing to general availability in consumer-grade networking products by the end of 2026, a similar timeline to MediaTek's. This seems doable, as we've already seen prototype Wi-Fi 8 hardware this week at CES, and Asus even told us that its first-generation Wi-Fi 8 products will launch later this year, with second-generation hardware coming in 2027.

Wi-Fi 8 is designed to improve reliability and lower latency rather than deliver a massive uplift in theoretical speeds (as had been the case with previous Wi-Fi iterations). Instead of obscene theoretical speeds that consumers likely won't see in the real world, the IEEE says that Wi-Fi 8 will deliver up to a 25 percent improvement in real-world speeds while reducing latency. Asus specifically highlighted improvements to mid-range throughput and showcased a 10 percent uplift in throughput over its fastest Wi-Fi 7 router with early prototypes.

A growing body of forecasts from AMD, Nvidia, Broadcom, and major research firms now points toward a semiconductor market that passes the trillion-dollar threshold before the decade closes, driven by an AI infrastructure buildout several times larger than any previous expansion in the industry’s history.

New analysis from Creative Strategies is calling this shift a "giga cycle," arguing that the unprecedented scale of AI demand is restructuring the economics of compute, memory, networking, and storage simultaneously. Global semiconductor revenue was roughly $650 billion in 2024, yet multiple outlooks now place the trillion-dollar mark in 2028 or 2029. AI is responsible for most of that upward revision.

AMD CEO Lisa Su recently lifted the company’s own long-term expectations, describing the AI hardware market as a $1 trillion opportunity by 2030 while projecting 35% compound annual growth for AMD overall and around 60% for its data-center business. She also spoke out against AI bubble talks that have dominated in recent months.

Meanwhile, Nvidia has set even broader expectations, describing the coming five years as a $3 trillion to $4 trillion AI infrastructure opportunity during the company’s Q2 2026 earnings call. This figure is based on system-level deployments across hyperscalers, sovereign AI projects, and enterprise clusters.

The broader implication is that every major category of silicon is expanding at once. Creative Strategies expects data-processing silicon to exceed half of total semiconductor revenue by 2026. AI accelerators, which accounted for under $100 billion in 2024, are projected to reach the $300 billion to $350 billion range by 2029 or 2030. That growth pushes system spending sharply higher. The AI server market is forecast to climb from about $140 billion in 2024 to as much as $850 billion by 2030, a trajectory that will reshape chip demand even before accounting for custom silicon.

This environment has elevated ASIC development to a central role in hyperscaler roadmaps. Broadcom expects its custom-silicon business to exceed $100 billion by decade’s end. The company has already disclosed a $10 billion AI infrastructure order from a customer thought to be OpenAI.

Memory and packaging remain the tightest constraints. HBM revenue is forecast to grow from roughly $16 billion in 2024 to more than $100 billion by 2030. Each HBM generation consumes a larger share of wafer supply than conventional DRAM, pushing the broader memory market upward as AI clusters scale. Advanced packaging faces similar pressure as CoWoS capacity is projected to expand by more than 60% from the end of 2025 to the end of 2026.

"The defining characteristic of the semiconductor giga cycle is that the market expansion is large enough to create greenfield opportunities across every segment of the value chain," says Creative Strategies, presenting the combined effect as a moment where every segment is growing in unison rather than a cycle concentrated in any particular area.

OpenAI is reportedly working with SoftBank-owned Arm on a new CPU to complement the custom AI accelerator it is co-developing with Broadcom. The collaboration, first reported by The Information, would see Arm design a server-class CPU that anchors OpenAI’s next-generation AI racks, potentially representing one of Arm’s biggest steps into the data center market to date.

The chip in question is OpenAI’s in-house AI accelerator, part of plans announced on October 13 to deploy custom AI accelerators and rack systems in collaboration with Broadcom. The SoC, specialized for inference workloads, is expected to enter production in late 2026 and scale up to support roughly 10 gigawatts of compute capacity between 2026 and 2029. The Broadcom accelerator, said to be fabricated by TSMC, has been in development for roughly 18 months.

According to The Information, Arm’s new role goes well beyond supplying architectural blueprints. The company has recently started designing and manufacturing its own CPUs rather than just licensing cores to partners, and sees the OpenAI contract as a chance to expand its server ambitions. People familiar with the discussions told the outlet that OpenAI could use the Arm-designed CPU not only with its Broadcom chip, but also with systems from Nvidia and AMD.

The potential revenue from OpenAI’s CPU program could reach into the billions, the report also said, representing a major windfall for SoftBank, which owns nearly 90% of Arm and has borrowed heavily against its stake. SoftBank has also pledged to invest tens of billions of dollars into OpenAI’s data center build-out and to buy AI technology from the startup to help accelerate Arm’s own chip development cycle.

Together with earlier agreements with Nvidia and AMD, OpenAI says its chip programs now total as much as 26GW of planned data center capacity. If successful, OpenAI’s custom chip deployments could reach a total installed base that analysts estimate could cost more than $1 trillion in construction and equipment in tandem with its Nvidia and AMD purchases.

The OpenAI–Broadcom chip could also give the ChatGPT developer more leverage in pricing talks with Nvidia, whose H100 and forthcoming Blackwell GPUs still dominate the AI training market. If Broadcom and TSMC can scale production, OpenAI’s inference chips may offer a partial hedge against the tight GPU supply that has constrained AI labs for much of the past year.

OpenAI has signed a multi-year deal with Broadcom to co-develop and deploy 10 gigawatts of custom AI accelerators and rack systems, the companies announced on October 13. OpenAI will handle accelerator and system design, while Broadcom leads development and roll-out starting in the second half of 2026. Full deployment is targeted by the end of 2029.

The agreement forms part of an ongoing, aggressive hardware push by OpenAI. Unlike with its current reliance on Nvidia GPUs, the new systems will be based on in-house accelerators paired with Broadcom’s networking and hardware IP. The deal could mark a shift away from traditional GPU-centric clusters in favor of tightly integrated silicon tailored to OpenAI’s training and inference workloads.

The two companies have already been working together for over 18 months, and this formal agreement builds on that collaboration. Few technical details have been disclosed, but the joint announcement confirms that the systems will use Ethernet-based networking, suggesting a data-center architecture designed for scalability and vendor neutrality. OpenAI says deployments will be phased over several years, with the first racks going online in the second half of 2026.

The new agreement adds to OpenAI’s existing partnerships with Nvidia and AMD, bringing the company’s total hardware commitments to an estimated 26 gigawatts, including roughly 10 gigawatts of Nvidia infrastructure and an undisclosed slice of AMD’s upcoming MI series.

Interestingly, OpenAI is not believed to be Broadcom’s still-unknown $10 billion customer. Speaking with CNBC, Broadcom semiconductor president Charlie Kawwas appeared alongside OpenAI’s Greg Brockman and joked, “I would love to take a $10 billion [purchase order] from my good friend Greg,” he said, adding, “He has not given me that PO yet.” WSJ reports that the deal is worth "multiple billions of dollars."

OpenAI stands to gain a deep bench in ASIC design and proven supply chain maturity from Broadcom. The company already produces custom AI silicon for hyperscale customers, including Google’s TPU infrastructure. By leveraging Broadcom’s Ethernet and chiplet IP, OpenAI gets a path to differentiated hardware without building a silicon team from scratch.

Meanwhile, for Nvidia, the deal adds to a growing list of partial defections among major AI customers exploring in-house silicon. Amazon, Google, Meta, and Microsoft are all now pursuing custom accelerators. What remains to be seen is how well these bespoke solutions perform at scale, and whether vendors like Broadcom can match the ecosystem maturity of CUDA.

Neither company has disclosed foundry partners, packaging flows, or memory choices for the upcoming accelerators. Those decisions will shape delivery timelines just as much as wafer capacity. With deployment still a year out, the clock is ticking.

OpenAI's long-rumored $10 billion partnership with Broadcom is already showing cracks. The company is widely understood to be developing a custom chip designed specifically for OpenAI's inference workloads, but according to individuals familiar with the matter, the project has "hit snags": OpenAI wanted more power, sooner, than Broadcom could deliver, and an internal push to roll the chip out in Q2 2026 has already slipped to Q3 at the earliest, according to a report from The Information.

The project, which has been kept deliberately quiet, is set to have manufacturing run through TSMC. Once live, the chip could handle inference jobs across OpenAI’s growing fleet of data centers, cutting its exposure to GPU bottlenecks and potentially lowering costs.

However, even as OpenAI lays the groundwork for its own silicon, it’s doubling down with Nvidia. A recent infrastructure agreement between the two companies, potentially worth more than $100 billion, would see Nvidia supply GPUs for the next wave of OpenAI-hosted AI clusters. Nvidia’s CEO Jensen Huang recently said that OpenAI “is likely going to be the next multi-trillion-dollar hyperscaler company,” with OpenAI remaining a cornerstone customer for Nvidia’s highest-end systems.

This, then, highlights the same paradoxical situation we’ve seen time and time again with AI. Amazon, Google, Microsoft, Meta, and now OpenAI are all building their own chips to reduce their reliance on Nvidia, while simultaneously relying on Nvidia more than ever.

A hedge with no clear endgame

Broadcom executives first confirmed what is believed to be the OpenAI deal late last year, saying that a large AI customer had booked billions in long-term orders. Reports quickly tied the deal to OpenAI, which has been growing a small, specialized in-house silicon team since at least mid-2023. The chip is understood to be designed for internal inference tasks and is not intended for commercial release. Broadcom handles the physical design, with TSMC expected to fabricate the chips.

This deal made OpenAI the latest entrant in a long line of hyperscalers trying to build their own chips. Amazon has its Trainium and Inferentia platforms. Google is now on its fifth-generation TPU. Microsoft is working on its Maia accelerators. Each was billed as a shift away from GPU dependency. Each still runs major workloads on Nvidia silicon.

OpenAI doesn’t shy away from this fact. Its GPT-4 model was trained on Nvidia H100s, and its hosting partners — including CoreWeave and Microsoft — continue to deploy Nvidia hardware at scale. The new custom chip effort might eventually take over some inference jobs, but there’s no evidence it will replace H100 or Blackwell-class GPUs for training. And even if the silicon performs well, it won’t come bundled with Nvidia’s competitive software stack.

There’s no matching CUDA

This is the piece challengers still can’t match. Nvidia’s CUDA platform remains the default target for nearly every AI framework in use today. From PyTorch and TensorFlow to popular model compilers and quantization toolkits, most of the AI software stack is optimized for Nvidia’s architecture. Migrating off it means rewriting core libraries, retraining engineers, and adapting models to new hardware, which, ultimately, is a cost few companies are willing to absorb.

OpenAI, like others, is unlikely to abandon CUDA without a compelling reason. Broadcom doesn’t offer its own software ecosystem, which means OpenAI’s team would need to build its own toolchain or adopt one of the open standards still struggling to reach parity. In the meantime, the easiest, fastest way to build and run large-scale models is still with Nvidia’s chips and software.

Jensen Huang knows this. Holding an iron grip over the industry, he’s reportedly given a heads-up by the likes of Amazon and Google before they announce a new chip that might compete with Nvidia’s. All this is done on the down low and, according to reports, has become something of an unwritten rule. It’s not required, but it happens, and it shows the degree to which Nvidia still commands power among its customers, even those building chips to hedge against Nvidia.

It’s not difficult to understand why this is the case. Nvidia is pouring billions into partnerships, infrastructure, and component sourcing. It recently agreed to buy up to $6.3 billion in unused GPU capacity from CoreWeave, invested nearly $1 billion to license Enfabrica’s networking tech, and paid Intel $5 billion as part of a joint development pact. It even agreed to support OpenAI’s next generation of GPU data centers despite OpenAI’s clear intent to use its own chips at some point.

Supply chain headwinds

When Intel introduced its IDM 2.0 strategy in 2021, a substantial part of the plan was to build custom x86 processors for clients and then produce them at Intel Foundry. However, the company has never assigned an executive to manage its custom silicon business, and the only major design wins were for custom Xeon CPUs used by Amazon Web Services. However, this month, Intel made two important steps that make it a de facto contract chip designer: it appointed an executive to lead its custom silicon business and signed a multi-year contract to build custom Xeon CPUs for Nvidia's AI platforms.

The current state of Intel's custom CPU business

Intel has been offering semi-custom Xeon processors to various customers for over a decade. These CPUs typically serve hyperscalers or large AI/data center customers who require performance or efficiency enhancements optimized for their specific workloads. These Xeon processors are tweaked from standard off‑the‑shelf Xeon SKUs with different frequency bins, power envelopes, packaging, microcode, feature sets, or even special-purpose accelerators designed for certain workloads.

When Intel discussed custom x86 processors in 2021, it mentioned customizable cores, custom IP, and customized Intel IP, which is far more impressive than its semi-custom offerings. However, the only custom products that Intel developed for a large client and disclosed publicly are the aforementioned Xeon CPUs for Amazon Web Services.

Intel has never revealed the degree of customization on the IP level with these products, though we know from AWS that its custom Xeon 6 CPU has an unknown number of cores, a 3.90 GHz all-core turbo frequency (up from 3.20 GHz for the off-the-shelf Xeon 6952P model), and faster DDR5-7200 memory support (up from DDR5-6400). However, such a level of customization is not something we usually expect from a bespoke CPU in a world where hyperscalers run dozens of highly customized models for their in-house processors inside data centers.

This is something that must change if Intel truly plans to serve a crowded market, with names like Alchip, Alphawave, AMD, Andes, Broadcom, GUC, Marvell, MediaTek, and Sondrel. This month, Intel appointed Srini Iyengar to lead its Central Engineering Group, enabling the company to build a custom silicon business serving a broad range of external customers. That job is not going to be easy, but Iyengar has the appropriate experience to do it.

Srini Iyengar has spent over two decades at Intel, with the latter half of his career focused on custom silicon architecture for infrastructure platforms. As a Principal Engineer, he has played a key role in architecting Arm-based Infrastructure Processing Unit (IPU) SoCs, defining product features to optimize performance, power, and area (PPA), and collaborating across IP vendors, verification, firmware, and manufacturing teams to deliver tailored solutions. Previously, he led the architectural development of special-purpose accelerator subsystems for server CPUs.

In addition, Intel this month disclosed its custom silicon unit's biggest win so far: a multi-year contract with Nvidia, under which it will develop and build bespoke Xeon CPUs for Nvidia's AI infrastructure. Given that Nvidia controls the lion's share of the AI hardware market, this is a significant contract both in terms of volume and in terms of Intel's public image.

Custom silicon is on the rise

When mentioning custom silicon in the context of Intel, we primarily refer to consumer and data center processors, as these are the areas where Intel excels. However, the semiconductor industry is witnessing a sharp rise in demand for bespoke application-specific processors across virtually all verticals, including AI, automotive, cloud, consumer, data centers, and consumer electronics.

Around a decade ago, only large companies could afford to develop their own custom chips, but with maturing contract chip development services, IP ecosystems, foundry yields, and a changing competitive landscape, the interest in bespoke chips is stronger than ever.

Apple's early lead in custom processors for smartphones set the tone for the consumer electronics industry, showing how proprietary silicon can deliver performance, efficiency, and product differentiation. In 2025, Google, Huawei, and Xiaomi have also developed their own smartphone SoCs.

In the data center, hyperscalers like Amazon and Google have become major drivers of custom silicon. AWS has its own Trainium accelerators for AI training, Inferentia accelerators for AI inference, and Graviton CPUs for general-purpose compute. Google produces its own chips for AI (TPUs), video (VCUs), and its own application processors for smartphones. These companies benefit from integrating hardware and software stacks, enabling better efficiency and lower costs at scale. The trend extends to other hyperscalers, including Alibaba, Baidu, Meta, Microsoft, and OpenAI.

Automotive manufacturers are also investing in their own processors (motivated by Tesla's early lead) as they shift to software-defined vehicles (SDVs). These companies are set to use multiple high-end SoCs across a vehicle, with the main Advanced Driver-Assistance System (ADAS) SoC likely using multiple chiplets. These companies are not only interested in reliability, performance, and features, but also in the long-term availability.

Advanced AI-assisted EDA tools from Cadence, Synopsys, and Siemens AI as well as simulation tools from Ansys (now part of Synopsys), greatly streamline the development of custom processors, which lowers the barrier for companies that intend to establish their own chip design division. If the return on investment looks compelling, unit costs are reduced significantly, or the total cost of ownership is lowered several times, or performance improvements are dramatic, then companies will at least consider starting an in-house chip design initiative.

However, development of chips is always a risk, both in terms of money and time-to-market. This is especially true for companies starting from scratch or lacking in-house expertise. Also, far not all companies that can benefit from custom silicon can afford an internal chip division. Finally, there are companies not willing to afford an internal chip design department for many reasons. This is where contract design-to-order service companies come into play.

What do customers want?

Companies that want the benefits of custom silicon, without the complexity of managing specifics like IP licensing, verification, or tape-out, have a very specific set of requirements for a contract chip designer, as it essentially becomes a strategic partner, not just a service provider.

One of the biggest priorities for interested companies is the experience of their partner. Customers seek design firms with a proven track record of delivering complex SoCs or ASICs, ideally in their industry domain. This includes not only silicon delivery but also successful tape-outs on advanced nodes, system-level architectural understanding, and familiarity with key verticals such as automotive, AI/ML, client PCs, and networking.

Secondly, customers expect access to a comprehensive IP portfolio. Most firms do not want to source and license every IP block individually; therefore, contract designers must provide or integrate essential IP blocks, such as PCIe, DDR, SerDes, Ethernet, USB, and security. Many customers also require the ability to integrate their own custom IP or differentiate through co-developed blocks. Therefore, the chip designer must have licensing flexibility, reuse rights, and expertise in deep IP integration.

Thirdly, clients demand a mature and automated design flow. Faster tape-outs and fewer silicon bugs are critical to stay on schedule and within budget. This also means the designer should handle validation, testbench creation, simulation, and signoff with minimal supervision.

Next, clients also value pre-existing relationships with foundries and Outsourced Semiconductor Assembly Tests (OSATs), which ensure that the designed processor will enter mass production and will ramp up to target volumes at predictable costs. Long-term support — including yield increase, silicon validation, firmware tuning, and product lifecycle management — is often a crucial factor.

Lastly, some clients prefer a full turnkey model, while others opt for joint development with an eventual handoff. Normally, a contract chip designer should support both and ensure strong IP protection, data security, and clear ownership terms.

What Intel can and cannot offer

Intel today can offer several — but not all — of the elements that customers expect from a contract chip designer. While the company is taking serious steps toward building a competitive custom silicon business, it still lags behind established ASIC players in a number of key areas.

Intel has decades of experience designing some of the world's most complex processors, including consumer CPUs for a wide range of PCs, Xeon processors for data centers, GPUs, FPGAs (via Altera), and even AI accelerators. The company clearly understands power, performance, and area (PPA) tradeoffs at scale.

For customers that require high-performance x86-based compute or custom server-class silicon, Intel's architectural know-how is likely second to none. Additionally, in recent years, Intel has gained experience in integrating chiplets made on different nodes from various foundries, a feat no one else in the industry has yet achieved in volume.

However, unlike Alchip, Andes, GUC, Marvell, or MediaTek, Intel does not have a proven track record of integrating Arm, RISC-V, or 3rd-party cores into customer designs.

Intel owns a wide range of IP, including x86 cores, GPUs (and supporting hardware like media engines, display engines, display controllers, audio codecs, etc.), AI accelerators, security engines, special-purpose accelerators (primarily for data centers), and high-speed I/O controllers and PHY (e.g., DDR, HBM, Ethernet, PCIe, Thunderbolt, UPI, USB, etc.). For customers looking to build a product around x86 and reuse trusted Intel IP blocks, the company can provide a strong starting point — particularly for data center and perhaps even for AI accelerators.

However, Intel's IP for its own 18A process technologies is relatively limited (for now), so it will have to license IPs from third parties like Synopsys, which is not a big problem, but adds complexity. While Intel has proven IPs for TSMC's process technologies, these are mostly focused on consumer solutions, not on data center solutions, which will again mean reliance on third-party IPs.

With Intel Foundry and packaging capabilities like EMIB, Foveros, and 3D chiplets, Intel can offer not only custom chip design but also manufacturing and advanced integration options. This is a strong differentiator versus design-only houses that rely on external foundries and OSATs. For chiplet-based SoCs or heterogeneous designs, Intel has a compelling packaging roadmap. Intel also has a good relationship with TSMC.

There might be a perception issue, though. Intel may favor its own IP, packaging, or node choices, which could limit design freedom. Some customers may prefer a neutral, foundry-agnostic partner that will deliver their GDSII file to TSMC.

Finally, Intel's traditional business model is focused on low-mix/high-volume chip development and production. A contract manufacturer is focused on agile development, tape-out, and low-volume production, and we have no idea how ready Intel's teams are for such work.

The first step

Broadcom this week announced that it had signed an agreement to supply $10 billion worth of AI data center hardware to an undisclosed customer. The hardware includes custom-designed AI accelerators tailored for workloads specific to the client, as well as other gear from the company. It is widely rumored that the customer in OpenAI, which reportedly intends to use the AI processors for inference workloads, and the sheer scale of the order could amount to several million AI processors. 

As always, Broadcom isn't tipping its hat on the mystery customer. "Last quarter, one of these prospects released production orders to Broadcom, and we have accordingly characterized them as a qualified customer for XPUs and, in fact, have secured over $10 billion of orders of AI racks based on our XPUs," said Hock Tan, President and CEO of Broadcom, during the company's earnings conference call. 

Hardware is ready

While the $10 billion number is a big deal, there is a lot more in the announcement. Broadcom stated the customer is now 'qualified,' confirming that the chip and possibly the associated platform passed customer validation. That means that whoever this client is, they are happy with the functionality and performance (and so the design has been locked). Meanwhile, the phrase 'released production orders' means the customer moved from evaluation or prototyping to full-scale commercial procurement, though Broadcom will recognize revenue at a later point, possibly once the hardware is delivered or deployed. 

Broadcom does not reveal the names of its customers, but it said it would deliver 'racks based on its XPUs' in Q3 2026, which ends in early August 2025. Although the company calls its products 'racks,' these are not racks supplied by companies like Dell. What Broadcom intends to deliver to its undisclosed client is custom AI accelerators (XPUs) and networking chips, along with reference AI rack platforms that integrate these components. These are not full systems, but building blocks for large customers to assemble their own AI infrastructure at scale. 

On time for 2026 deployment

Assuming that Broadcom delivers its hardware to the undisclosed client in June or July, 2026, that client will be able to able to deploy them in a few months (i.e., in Fall, 2026), depending on various factors. Such a timeframe aligns with reports suggesting that OpenAI’s first deployment of its custom AI processors, developed in collaboration with Broadcom, was expected between late 2026 and early 2027.

OpenAI’s custom AI processor is expected to utilize a systolic array architecture — a grid of identical processing elements (PEs) optimized for matrix and/or vector operations, arranged in rows and columns — a design similar to that of other AI accelerators. The chip will reportedly feature HBM memory, though it is unclear whether it will adopt HBM3E or HBM4, and is likely to be manufactured on TSMC’s N3-series (3nm-class) process technology.

A massive deal

Amid a fierce trade war with the US, China's General Administration of Customs has changed its rules of how the origin of imported chips must be classified, now deeming that the wafer fabrication location should be counted as the origin of chips shipped to the country. This rule exempts products from AMD, Nvidia, Qualcomm, Intel, and other chipmakers who outsource wafer fabrication to Taiwanese companies from the punitive 125% tariff China now imposes on products from the U.S. However, this badly hurts Intel, Global Foundries, Texas Instruments, and chip designers who produce chips in America.

Today, the China Semiconductor Industry Association published an urgent notice regarding the rules for determining the 'country of origin' of semiconductor products shipped to China. As it turns out, the location where the wafer was processed is deemed the 'country of origin,' no matter where the chip was developed or packaged, according to a CSIA document published in WeChat and republished by various analysts. The rule applies to both packaged and unpackaged semiconductors.

Because China deems Taiwan its own territory, chips fabricated by TSMC, Micron, UMC, Vanguard, and other chipmakers in Taiwan will be exempt from punitive 125% import duties imposed on products from then U.S. even though virtually all contemporary chips from companies like AMD, Broadcom, Intel, Nvidia, Micron, and Qualcomm are developed in America and are sold by U.S.-based company.

By applying this rule, the Chinese government kills two birds with one stone.

On the one hand, it allows chipmakers to ship their products to China without any restrictions or punitive tariffs, which enables China-based fabs to continue making actual products based on those chips, thus keeping Chinese facilities busy. As an added bonus, China shows American companies that it considers Taiwan its own territory and actually means it by not imposing any punitive import duties.

On the other hand, it punishes American chipmakers and chip designers that produce their ICs in the U.S., which includes companies that outsource to GlobalFoundries' Fab 8 in New York as well as Texas Instruments, which builds its chips in Texas.

As an added bonus, the Chinese government helps TSMC, UMC, Vanguard, and China-based foundries to potentially land new customers. This has implications, too. Many products made in China use chips from American companies produced in America by companies like Analog Devices, GlobalFoundries, NXP, or ON Semiconductor, or fabbed by contract chipmakers in the U.S., such as Intel or GlobalFoundries. Consequently, companies that use chips from the U.S. will now have to find alternatives, which takes time and costs money. For some, this may be the end of the line.

One thing to note is the stark contrast between how Chinese customs treat semiconductor products and how American customs treat chips in terms of 'country of origin.' The U.S. determines the 'country of origin' by the location of the last substantial transformation, where the product undergoes a major change. For example, a memory IC developed in the U.S., fabbed in Japan, but packaged in China is considered a Chinese product subject to punitive tariffs, according to the current laws. The same applies to logic chips designed in the USA but fabbed in Taiwan and packaged in China by subsidiaries of Taiwanese OSAT giants. By contrast, China's customs determine the 'country of origin' by the location of the actual wafer fabrication facility.

Jensen Huang, chief executive of Nvidia, stated that his company had not been approached to participate in a group effort to acquire a stake in a company that would operate Intel's foundry unit. He dismissed claims that Nvidia was working with industry peers and TSMC on such a deal at a press conference at GTC, reports Reuters. 

Separately, Paul Liu, a TSMC board member and the head of Taiwan's National Development Council, denied claims that the company is considering purchasing Intel's struggling foundry unit, reports DigiTimes.

"Nobody has invited us to a consortium," Huang said, according to Reuters. "Nobody invited me. Maybe other people are involved, but I do not know. There might be a party. I was not invited." 

While speaking to Taiwan's Legislative Yuan Economic Committee on March 19, Paul Liu stated that the acquisition of Intel Foundry has never been discussed at the board level and compared it to mixing two incompatible substances, something that one in the semiconductor industry can consider both figuratively as Intel and TSMC have vastly different corporate cultures and literally as the two companies use different chemical substances for manufacturing. As a result, industry experts believe such an acquisition would be more harmful than beneficial to TSMC.

Liu explained that stabilizing the company's most advanced production technologies already takes between 18 and 24 months. Exporting such a node to the the U.S. would add another year, making American operations three years behind those in Taiwan, according to Liu. He also addressed concerns about a possible second Trump presidency leading to a shift of Taiwan's semiconductor industry to the U.S., urging lawmakers to see the U.S. as a partner (which accounts for the lion's share of TSMC's revenue) rather than a competitor.

Earlier this year there were rumors that the U.S. government pushed TSMC to take over Intel Foundry and operate it. The plan involves Intel spinning off its Intel Foundry unit, which makes chips for itself and external clients. TSMC would acquire less than half of the new entity, while the remaining shares would go to industry partners. The list of industry partners included AMD, Broadcom, Nvidia, and Qualcomm, according to Reuters. However, speaking at the conference, Huang denied any involvement in discussions about a potential consortium to take control of Intel's fabs. 

For Nvidia, which produces billions of dollars worth wafers every year, a dual sourcing supply strategy could make sense. However, designing large AI/HPC GPUs for different process technologies used by Intel and TSMC would significantly affect Nvidia's costs. Investing in a fab joint venture would also be odd for the company, which started as — and remains — a fabless chip designer.

The talks reportedly started before TSMC's March 3 announcement of its $100 billion U.S. investment. This plan includes five additional Fab 21 modules, two advanced packaging facilities, and a research center. However, according to Reuters' own report, the conversations about the fab joint venture continued after the announcement as TSMC was seeking agreements with major fabless chip design companies. As a result, Taiwanese lawmakers raised concerns following such media reports and pressured Liu for clarifications.

The global semiconductor industry saw explosive growth in 2024, mainly driven by sales of processors for AI applications, according to TrendForce. The Top 10 largest fabless chip developers earned nearly a quarter of a trillion dollars last year; roughly half of that sum came from Nvidia.

The largest fabless chip designers generated $249.8 billion in revenue, up 49% from the previous year. The growth boomed due to skyrocketing demand for AI GPUs, ASICs, adjacent chips (e.g., network processors, DPUs), datacenter CPUs, and recovered demand for client PCs. Market consolidation also intensified, with the Top 5 firms now accounting for over 90% of the revenue among the Top 10.

Nvidia was at the forefront of the industry and extended its dominance, posting $124.3 billion in revenue (a 125% increase from 2023) and capturing 50% of the revenue share. Hopper-based H100, H20, and H200 GPUs drove the company’s revenue increase, as Blackwell-based B200/GB200/B100 only emerged in the fourth quarter. As demand for Blackwell parts — which are believed to be more expensive than Hopper GPUs — increases this year, they will likely enable an even higher revenue for the green company this year.

Qualcomm ranked second, earning $34.86 billion, a 13% year-over-year increase. The company’s growth came from smartphones, the automotive sector, and PCs, a new source of the company’s revenue. The company secured a legal victory against Arm, and there are no risks that the latter will withdraw its licenses. The company also confirmed its interest in datacenter CPUs, though its entry into this market is likely a few years down the road.

Broadcom held third place, with its semiconductor unit bringing in $30.64 billion, up 8% from the previous year. AI-related products accounted for more than 30% of its semiconductor revenue. Despite a mid-year slump, demand for wireless communication, broadband, and server storage will drive the company’s growth in 2025.

AMD followed in fourth, increasing revenue by 14% to $25.79 billion. Its server business surged by 94%, boosting its position in datacenters and the cloud. Strategic partnerships with Dell, Google, and Microsoft are expected to help sustain its momentum, according to TrendForce.

MediaTek secured the fifth spot, with $16.52 billion in revenue, marking a 19% annual increase. The company’s success was driven by mainstream 5G smartphones, power management chips, and AI-related products. Its collaboration with Nvidia on Project Digits positions it for further expansion in 2025 as AI integration in mobile devices increases.

Marvell was the sixth largest fabless chip designer, with 5.637 billion in revenue, up 2% from the previous year. Realtek moved to seventh place with $3.53 billion (16% YoY growth), benefiting from a recovery in PC and automotive-related sales. Meanwhile, Novatek dropped to eighth, with revenue declining 10% to $3.2 billion.

Will Semiconductor and MPS closed the top ten, each showing 21% revenue growth, reaching $3.05 billion and $2.2 billion, respectively. Will Semiconductor benefited from high-end CMOS image sensors in Android phones and autonomous vehicles, while MPS saw success as its power management chips entered the AI server supply chain.

TrendForce expects AI to drive growth in various sectors, from datacenters to personal devices, in 2025.

Although TSMC has committed to invest an additional $100 billion in its own Fab 21 campus in the U.S., a potential joint venture to run Intel's manufacturing capacity is still in the works, according to Reuters, citing four sources. TSMC would reportedly not own more than 50% of the proposed joint venture. A venture that would see leading American fabless chip designers — AMD, Broadcom, Nvidia, and Qualcomm — get stakes in the joint venture, which will be operated by TSMC.

The initiative emerged following a request from President Trump's administration, aiming to bolster Intel while ensuring continued American control. Under the terms of the proposed scheme, Intel will have to spin off its Intel Foundry (IF) division that produces chips for Intel and third-party customers, and then TSMC, the world's largest contract chipmaker, buys less than 50% of IF, leaving the rest to partners. TSMC reportedly initiated discussions with AMD, Broadcom, Nvidia, and Qualcomm, but the talks remain preliminary and sensitive, according to four anonymous sources familiar with these discussions. It is also noteworthy that TSMC has not pitched its main client, Apple, to invest in the JV.

The idea of such a collaboration aligns strategically with President Trump's goal to revive domestic advanced manufacturing, and reviving Intel is one of the administration's priorities. However, it is unclear whether splitting the company and handing its parts to TSMC helps with competition between foundries.

According to Reuters' sources, TSMC approached potential partners about the joint venture prior to its March 3 announcement of plans to invest an additional $100 billion in its U.S. manufacturing capacities, which includes the construction of five new Fab 21 modules over the next several years, building two advanced packaging facilities, and an R&D center. Discussions regarding the joint venture involving Intel's foundry division have continued since then, according to the three sources, with TSMC aiming to secure partnerships with multiple chip design companies.

Technical, operational, and business complexities present significant hurdles for the potential joint venture.

• According to an Intel filing with the SEC, Intel's manufacturing and real estate assets cost around $108 billion, so interested parties will have to invest tens of billions of dollars to get a sizeable stake in Intel Foundry.
• TSMC is unlikely to be interested in owning a 50% stake in a JV that uses its own process technologies and competes against the Taiwan foundry.
• Transferring TSMC's production nodes to Intel's advanced fabs with EUV tools is hard, if possible at all, as Intel and TSMC operate vastly different manufacturing processes, employing distinct equipment configurations and chemical substances at their respective fabs.
• Intel has fabs that can only produce chips using its own process technologies. These fabs — which cost tens of billions of dollars — will continue to serve Intel for a while, but they present little value for outside investors.
• It is unclear how operating a JV aligns with TSMC's own manufacturing operations in the U.S.

The news had immediate market implications. Intel's stock price rose more than 7% in pre-market U.S. trading following reports of this potential partnership, according to Reuters. However, it is unclear whether the aforementioned fabless semiconductor developers are interested in getting into manufacturing. All of them chose to be fabless because they did not want to get into a complex capital-intensive business, and it is unclear what could drive their interest towards putting tens of billions of dollars in a JV considering the fact that they already have pre-booked capacity at TSMC.

Nvidia and Broadcom are both testing chips using Intel's new 18A manufacturing process, reports sources to Reuters, indicating that these well-known projects continue. Intel's 18A process is the company's first fabrication technology to rely on gate-all-around RibbonFET transistors and a backside power delivery network named PowerVia. The Intel 18A process is broadly comparable to TSMC's N2 node. However, 18A is thought to be faster, while N2 is a denser chip.

Reuters sources suggest that both Nvidia and Broadcom's tests are not being conducted on complete chip designs, but the companies want to understand how 18A works in both behavior and performance. It's common to test processors before committing to purchasing them outright.

This isn't entirely new information, as there have been reports that Broadcom had been testing 18A since as early as September 2024. Back then, it was claimed that Broadcom's tests using 18A did not meet expectations, but that was not confirmed, with Broadcom merely saying the tests were ongoing.

Nvidia CEO Jensen Huang has claimed as far back as 2022 that Nvidia would consider using Intel-fabricated chips, and noted the company had test chips under active testing in 2023. In 2024, Tom's Hardware quizzed Intel Foundry Services chief Stu Pann about the company's RAMP-C project, in which Nvidia is a formal partner. This program gives companies federal funding to build test chips on Intel's 18A process node for military applications.

Intel recently launched a dedicated website to advertise its 18A process, and consumer Panther Lake processors are set to enter mass production in mid-2025.

An Intel spokesperson told Reuters: "We don't comment on specific customers but continue to see strong interest and engagement on Intel 18A across our ecosystem."

While Intel's 18A process is reportedly garnering interest from big-name clients, Reuters claims to have reviewed supplier documents that indicate a problem with some unnamed third-party IP providers. Reuters claims this situation is causing "potential further delays in Intel's ability to deliver chips for some contract manufacturing customers" that could stretch the launch times for small and mid-size customers to mid-2026. Intel responded that it remains on track to begin fabricating chips in the second half of this year.

This is happening on the backdrop of a particularly difficult period for Intel, as the company lost $1.6 billion in 2024 and continues to struggle in its data center and foundry divisions. Former CEO Pat Gelsinger was ousted in December 2024, despite being one of the key people to lead Intel toward developing 18A, a product that could theoretically compete with TSMC's dominance.

Former Intel CEO Craig Barrett said on the matter: "In my opinion, a far better move might be to fire the Intel board and rehire Pat Gelsinger to finish the job he has aptly handled over the past few years.”

While Broadcom and Nvidia are likely to be testing 18A chips, Intel is in a position where it needs to lock down big clients for its next process node. Intel isn't expecting a quick pathway to profitability with its Foundry, as the company doesn't predict it will break even until 2027.

Ex-Intel lead silicon engineer Jim Keller says Intel may not make as much money as it used to earn historically, but selling the company or some of its businesses is not a way to unlock shareholder value, but rather a fire sale of a company that has high chances to prosper. Jim Keller, a legendary chip designer and now the chief executive officer of Tenstorrent, a promising AI processor developer, took to Twitter to express his views on the latest news of a potential split or sale of Intel. 

"You build value by having a great goal and a team that loves working to the goal," Keller wrote in an X post. "Intel built the fastest CPUs on the best process [technologies]. This [Handling Intel's businesses to third parties] is not unlocking shareholder value, it is a fire sale. It makes me sad."

"[…] I think a great Intel is worth $1 trillion. Seems a little careless to throw it away," he added later.  

The latest rumors indicate that Broadcom could be interested in taking over Intel's products business, whereas the Intel Foundry unit could form a joint venture with TSMC or even with a conglomerate involving TSMC, Broadcom, Qualcomm, and other companies that would inject money into a new independent chipmaker. 

One commenter in the thread suggested that a better outcome for Intel would be to become a private company with the help of American investors, fire the current board of directors, and then take the time to reinvent Intel. 

"It would be hard but doable," Keller wrote in another post. "Humans are amazing when they have a great goal and a team they believe in." 

The current U.S. government will unlikely support Intel's fabs being run by TSMC or other foreign entities, even though the Trump administration encourages domestic manufacturing. However, if Intel gives up its own manufacturing, it will not only cease to be an integrated device manufacturer (IDM) but also lose one of its strong points: complete control over products and their manufacturing. Also, it's unlikely that TSMC and other potential investors will be tremendously interested in investing in Intel Foundry, which bleeds money as it has yet to land orders from major companies. 

However, companies with deep pockets, such as Broadcom, could take over Intel's products division to gain CPU capability and world-class product design teams. However, a change of Intel ownership automatically terminates the company's broad cross-licensing agreement with AMD. This means the new entity could lose access to innovations developed by AMD and shared between companies as part of their broad cross-license agreement unless a new agreement is inked.

Intel has faced severe financial and execution woes over the past couple of years, leading to all types of speculation about the future of the company, with the most recent rumors pointing to Broadcom's interest in taking over Intel's product business, as well as an alleged U.S. government intention to make TSMC run Intel Foundry manufacturing operations in a joint venture between Intel and the Taiwanese contract chipmaker. But there is an obstacle that many people overlook: the broad cross-licensing agreement between Intel and AMD, as observed by Digits-to-Dollars. 

AMD and Intel have a broad cross-licensing agreement (in fact, multiple agreements, with the most recent signed in 2009) that allows both companies to use each other's patents while preventing lawsuits over possible infringements. This covers their entire portfolios, including CPUs, GPUs, and other innovations. AMD can produce x86-based processors with Intel's instruction set extensions, while Intel can incorporate AMD's innovations into its own CPUs. 

However, neither can develop processors that work with the other's sockets or motherboards., and the agreement has strict conditions for termination. If either company merges, is acquired, or enters a joint venture that alters ownership, the deal ends immediately. In the event of one of these triggers, the two companies must negotiate a new licensing arrangement. 

Although some market observers tie the AMD and Intel cross-licensing agreement directly to the 1976 agreement concerning the x86 instruction set architecture (ISA), this is not the case. The agreements include a variety of extensions to x86 (such as SSE and AVX) as well as other innovations that are inseparable parts of today's CPUs. While it is possible to build an x86 CPU without AVX, SSE, or other extensions, such processors will not be able to compete against modern counterparts. Thus, losing the license could be devastating to both AMD and Intel. 

In addition to the x86 ISA and extensions, the broad cross-licensing agreement between the two companies covers other technologies, including GPUs, DPUs, and FPGAs. Therefore, if the agreement were terminated, it would affect virtually all of AMD and Intel’s products, necessitating a renegotiation of the cross-licensing agreement. 

Companies in the high-tech industry tend to sign broad cross-licensing agreements, but a big question is whether AMD is actually interested in signing such an agreement with Broadcom. Historically, Broadcom was primarily known for networking solutions and wireless technologies, but today the company is a major player in the storage, cybersecurity, and infrastructure software markets. Perhaps more importantly, it has emerged as a leading developer of custom AI processors, collaborating with virtually all major cloud service providers and hyperscalers. Acquiring CPU capabilities would make Broadcom a formidable competitor for AMD. At present, Broadcom, armed with both CPUs and AI processors, poses a greater competitive threat to AMD than Intel, the latter of which lacks a clear AI strategy. 

While Digits-to-Dollars suggests that AMD could ask Broadcom to help counter Nvidia’s dominance in the AI market by creating "AMD-friendly" networking interfaces and connectivity solutions, Broadcom’s priority appears to be strengthening its position in the data center market, where it currently lacks CPUs. Once the company acquires a general-purpose data center processor business — further strengthened by Intel's large client PC processor volumes — it will likely focus on developing its own AI data center platform consisting of CPUs and ASICs, rather than assisting AMD in competing with Nvidia. Of course, an industry-standard platform centered around open standards like Ultra Ethernet could make life easier for both AMD and Broadcom in their fight against Nvidia. However, competing with Broadcom will be more challenging for AMD than competing with Intel.

Intel is facing potential acquisition bids from TSMC (Taiwan Semiconductor Manufacturing Company) and Broadcom, according to sources cited by The Wall Street Journal. The two major tech companies are exploring deals that could effectively split Intel's operations, with Broadcom reportedly eyeing Intel’s chip design and marketing divisions, while TSMC is assessing the possibility of taking over its chip manufacturing plants.

Broadcom has engaged in informal discussions with advisors about a potential bid, though it is likely to proceed only if it secures a partner to handle Intel’s manufacturing segment. This approach aligns with Broadcom’s ongoing strategy of expanding its business through targeted acquisitions. Meanwhile, TSMC, the world's largest contract chip maker, is reportedly considering forming an investor consortium to acquire Intel’s fabrication plants, which would further strengthen its position in the global semiconductor market. All discussions remain preliminary, and no formal offers have been made.

Intel has been struggling to regain its foothold in chip manufacturing amid increasing competition from TSMC and others. Pat Gelsinger, the company’s previous CEO, was ousted in December after a series of setbacks including delays in manufacturing plans, a decline in AI chip market share, and a reliance on government subsidies to fund factory expansions. Intel’s financial struggles, including $7 billion in losses from its chipmaking segment in 2023 and a 60% decline in share price, have made it an acquisition target.

Any potential deal faces a major roadblock, however: U.S. government opposition. The Trump administration has voiced strong concerns over the possibility of a foreign company operating Intel’s U.S.-based chip fabs. A White House official recently stated that while foreign investment is generally encouraged, Intel’s domestic manufacturing capabilities are seen as strategically important, making it unlikely that a takeover by TSMC would receive government approval.

This stance complicates any potential deal, especially as the U.S. government has been actively subsidizing domestic semiconductor production to reduce reliance on foreign chip makers. If Broadcom and TSMC move forward with their plans, they may need to navigate regulatory hurdles and find domestic partners to satisfy national security concerns.

A breakup of Intel would mark a shift toward specialization, with companies focusing on either chip design or manufacturing. Whether these acquisition talks gain momentum or stall due to political and economic factors remains to be seen.

OpenAI expects to finalize its first custom AI processor design in the coming months and send it to TSMC for production, aiming for large-scale manufacturing by 2026, reports Reuters. OpenAI follows its rivals from Google, Meta, and Microsoft, so to remain competitive in terms of costs, it needs its own custom processors earlier rather than later.

The custom silicon OpenAI will create for AI processors is expected to feature a so-called systolic array design, a grid of identical processing elements (PEs that perform matrix or vector computations) that are arranged in rows and columns and connected in such a way that data 'pulses' through the array in a pipeline-like fashion. The processor is said to use HBM memory, though it is unclear whether OpenAI plans to use HBM3E or HBM4. As for process technology, OpenAI reportedly aims at TSMC's proven N3-series (3nm-class) fabrication process.

OpenAI is reportedly working with Broadcom on its custom processor for AI workloads project. Typically, companies that work with Broadcom on custom processors develop key differentiating intellectual property (IP) in-house (or at least define it with Broadcom), and then Broadcom adds the remaining parts such as general-purpose CPU cores, memory, and I/O controllers and physical interfaces, as well as assembling the final design.

On the OpenAI side, the effort is led by Richard Ho, who previously worked on Google's TPUs. Ho's team reportedly doubled to 40 engineers recently, but it is still considerably smaller than those at Amazon Web Services or Google. Expanding the initiative to match the scale of Google or Amazon would require hiring hundreds more engineers. That said, it is reasonable to expect OpenAI's in-house contribution to the design to be relatively small.

Internally, OpenAI sees its custom processor as a way to improve its bargaining power with existing suppliers, mainly Nvidia. However, if successful, the company intends to refine and upgrade its custom silicon over time, expanding functionality with each iteration. The first version is expected to be produced in small quantities, primarily for running inference workloads on AI models rather than training them.

Developing a high-performance AI processor is an expensive undertaking. Industry estimates suggest a single model could cost hundreds of millions of dollars, and supporting infrastructure, including necessary hardware and software, could double that amount. However, when more than one processor is developed per platform, those costs per processor typically drop.

Historically, even companies like AWS, Google, Meta, and Microsoft have struggled to create competitive in-house processors that could beat Nvidia's GPUs in terms of performance. However, they have managed to build much cheaper processors with higher energy efficiency tailored for their workloads, which enables them to more than offset development costs. Also, these custom processors make running AI models cheaper for their cloud customers, which is good for the market.

The demand for AI chips continues to surge as Big Tech companies need vast quantities of processors to train and then run their increasingly sophisticated models. Meta has allocated $60 billion for AI infrastructure this year, while Microsoft plans to invest $80 billion in 2025. OpenAI has not formally announced its 2025 spending plan — which is not surprising as it is not a public company — but, likely, it will also spend tens of billions of dollars on hardware, software, and infrastructure this year.

If OpenAI manages to tape out its first custom processor in the coming months, then it will be able to mass produce it sometime a year after that, in mid-2026. If it is lucky, it will begin deployment in the second half of 2026.

DeepSeek, a China-based startup, unveiled an AI assistant last week that is 20 to 50 times cheaper to train and operate than OpenAI's models. This triggered a massive selloff of tech stocks that had been driven by the rise of AI. The selloff wiped nearly $600 billion from Nvidia’s market value as investors believed that demand for its processors would decrease. However, ex-Intel CEO Pat Gelsinger argues that compute performance is never enough and that high demand for processors from tech giants will remain.

The reaction to DeepSeek's breakthrough has overlooked three critical lessons from five decades of computing, according to Gelsinger's post over at LinkedIn. First, lowering the cost of computing resources expands the market, not contracts it. Just as cheaper technologies like PCs and mobile devices drove explosive growth, making AI more affordable will integrate it into more applications and will trigger broader adoption.

"The market reaction is wrong, lowering the cost of AI will expand the market," Gelsinger wrote. "Today I am an Nvidia and AI stock buyer and happy to benefit from lower prices."

Second, engineering thrives under constraints, Gelsinger notes. DeepSeek’s team faced export restrictions and limited resources but created a world-class solution at a fraction of the usual cost. This ingenuity resonates with insights from computer science pioneers, who often state that they achieved their best work under significant limitations.

Third, openness fosters innovation, Gelsinger contends. The shift toward proprietary AI models stifles transparency and collaboration. Open ecosystems, as proven by Linux, Wi-Fi, and USB, consistently lead to better outcomes by encouraging scrutiny, ethical introspection, and broader adoption. DeepSeek’s open approach offers a much-needed reminder of the importance of shared innovation in AI.

“Open wins every time it is given a proper shot,” Gelsinger wrote. “AI is much too important for our future to allow a closed ecosystem to ever emerge as the one and only in this space.”

Gelsinger is not alone in his assessment that the market reaction is wrong; other market observers believe that the reaction was exaggerated. AMD, Broadcom, Intel, and Nvidia remain essential for building AI data centers and training large AI models.

"The real money in AI is providing the chips for the data centers from the likes of Nvidia, AMD, and Broadcom," Daniel Morgan, senior portfolio manager at Synovus Trust Company, told Reuters. "Overall, I view the AI tech selloff today as an opportunity to add high-quality tech shares on weakness."

DeepSeek’s model can be used locally on PCs and even smartphones, which is its fundamental advantage over ChatGPT's o1 and o4 models that reside on the cloud. However, training the model still requires advanced data center-grade hardware. Although DeepSeek reduces requirements for training hardware, companies like Anthropic and OpenAI could increase the number of parameters for their models while still consuming their vast computing resources.

To that end, demand for advanced processors in large-scale computing environments is expected to persist. Also, it is unclear how much resources — both computational and financial — DeepSeek consumed while prepping to train its model and developing all the optimizations to reduce requirements for the training cluster. Thus, the implications of DeepSeek’s breakthrough on the hardware market remain to be determined. 

As a result, experts suggest that the selloff could present a buying opportunity for long-term investors in tech stocks like AMD, Broadcom, Intel, and Nvidia.

Several trade organizations including the Semiconductor Industry Association (SIA) and Semiconductor Equipment Materials International, have written a letter to outgoing U.S. President Joe Biden, raising concerns about new U.S. export controls, reports Reuters. The organizations, which represent chip developers, as well as producers of chipmaking tools, criticized the lack of industry consultation regarding regulations restricting the global use of American processors for AI. 

The letter comes after the Biden administration introduced a three-tier licensing system for U.S. made AI processors (such as Nvidia's H100 or B200 GPUs), requiring most countries to obtain licenses. High-bandwidth memory (HBM), essential for AI GPUs and ASICs, is also set to face stricter export restrictions, especially for sales to China. These changes could have significant impact on U.S. companies like AMD, Broadcom, Intel, Nvidia, and Micron, as well as the global semiconductor market. Nvidia has heavily condemned the decision.

The trade organizations warned that these new restrictions could harm U.S. companies and shift market share to international competitors. The groups stressed the absence of meaningful consultation and public feedback on these economically significant policies. The trade groups urged the administration to reconsider the rules, emphasizing their long-term implications. 

Sales to China represents a significant figure for AMD, Intel, and Nvidia. Under the new export rules, these companies will be unable to sell almost any of their AI processors to Tier 3 countries — such as Belarus, China, Iran, Macau, Russia, and other arms-embargoed nations — which will severely harm their sales. Yet, China already has its own AI processors, such as Huawei's Ascend 900 series that may be slower than Nvidia's H20 HGX, but could be good enough to build a high-performance cluster for AI training. Since China could potentially sell these processors to other restricted countries, this will harm Nvidia's dominance on the AI market. Also, given the restrictions, some Tier 2 countries may reinforce their efforts to produce sovereign processors for AI and HPC based on open-source technologies, such as RISC-V, which will harm dominance of all American companies, such as AMD, Intel, and Nvidia. 

Additionally, the upcoming regulations might reverse a prior interpretation that benefited American producers of wafer fabrication tools, such as Applied Materials, KLA, and Lam Research. All of these companies generated billions selling their equipment to Chinese makers of 3D NAND, DRAM, and logic. The potential reversal could significantly impact its earnings. 

Neither the trade groups nor Lam Research responded to inquiries for comment, according to Reuters.

Intel's market capitalization dropped from around $198 billion in early 2024 to around $87 billion today, which makes the company an interesting acquisition target. Broadcom is certainly one of the companies that is known for making large acquisitions, and given its current focus on custom datacenter processors for AI, it could potentially be interested in taking over. However, its chief executive played down such a possibility citing a lack of Interest from Intel. 

"[Broadcom has] not been asked [to take over Intel]," said Hock Tan, chief executive of Broadcom, in an interview with the Financial Times. "I can only make a deal if it is actionable. Actionability means someone comes and asks me. Ever since Qualcomm, I learned one thing: no hostile offers." 

Back in 2018, Broadcom's $142 billion attempt to acquire rival chipmaker Qualcomm through a hostile takeover was stopped by then-President Donald Trump in a rare and extraordinary move. 

Earlier this year, we reported that Qualcomm was potentially interested in acquiring Intel, although it ultimately turned out that other reports said the company lost interest in buying Intel with all of its product divisions and manufacturing operations. 

Just like a merger with Qualcomm, an Intel merger with Broadcom could align with industry megatrends. Broadcom enjoys growing demand for AI processors it designs for clients like Google as well as connectivity solutions in data centers. By contrast, Intel's processors power the vast majority of servers as well as client PCs. Broadcom lacks presence in PCs and does not supply server CPUs. 

Intel's strength is, of course, its production scale and dominance in client computers. However, Intel is currently struggling to keep its process technologies competitive with TSMC and its processor products competitive with rival AMD. As a result, the appeal of the company is not particularly high at this point, especially because Broadcom has to integrate VMware, a company it acquired for $61 billion in 2022. 

Additionally, Broadcom is busy with its bespoke processor business for major high-tech companies, including ByteDance, Google, Meta, and reportedly Apple and OpenAI, which are seeking alternatives to Nvidia's processors. 

Tan described the ongoing investment frenzy in Silicon Valley, where tech giants are rapidly planning AI infrastructure projects for the next three to five years. These firms are constructing massive data centers, such as xAI's Memphis facility with 100,000 Nvidia GPUs and Colossus with up to one million Nvidia GPUs, to handle the computing needs of their ambitious AI programs. 

Tan has predicted that AI projects for Broadcom's clients could require clusters with up to one million processors as demand for computing power to train and run advanced AI systems continues to grow. He emphasized that the scaling principle—more data and processing yielding smarter AI—is driving these investments, despite uncertainty about when or if artificial general intelligence (AGI) will be achieved.

Broadcom has introduced its 3.5D eXtreme Dimension System in Package (3.5D XDSiP) platform for ultra-high-performance processors for AI and HPC workloads. The new platform relies on TSMC's CoWoS and other advanced packaging technologies. It enables chip designers to build system-in-packages (SiPs) of 3D-stacked logic, network and I/O chiplets, and HBM memory stacks. The platform allows for SiPs with up to 6000mm² of 3D-stacked silicon with 12 HBM modules. The first 3.5D XDSiP products are set to arrive in 2026.

Broadcom's 3.5D XDSiP uses TSMC's CoWoS-L packaging technology that offers a maximum interposer size of approximately 5.5 times that of a reticle (about 858 mm^2), or 4719 mm^2 for compute chiplets, I/O chiplets, and up to 12 HBM3/HBM4 packages. To maximize performance, Broadcom suggests disintegrating the design of compute chiplets and stacking one logic chiplet on top of another in a face-to-face (F2F) manner using hybrid copper bonding (HCB).

This face-to-face (F2F) stacking approach that directly connects the upper metal layers of the top and bottom silicon dies using bumpless hybrid copper bonding is the key benefit of Broadcom's 3D XDSiP platform compared to the face-to-back approach that relies on through silicon vias (TSVs). The F2F approach enables up to 7 times more signal connections and shorter signal routing, reduces power consumption in die-to-die interfaces by 90%, minimizes latency within the 3D stack, and provides additional flexibility for design teams to disaggregate ASIC architecture between top and bottom dies (which is a result of denser connections and lower latencies), according to Broadcom.

"In close collaboration with our customers, we have created a 3.5D XDSiP platform on top of the technology and tools from TSMC and EDA partners," said Frank Ostojic, Senior Vice President and General Manager, ASIC Products Division, Broadcom. "By stacking chip components vertically, Broadcom's 3.5D platform enables chip designers to pair the right fabrication processes for each component while shrinking the interposer and package size, leading to significant improvements in performance, efficiency, and cost."

The company's press release does not mention TSMC's 3D stacking packaging methods. However, 3.5D XDSiP's F2F HCB is likely a proprietary implementation of TSMC's bumpless SoIC-X stacking technology, albeit with Broadcom's proprietary design and automation flow (which is something indirectly confirmed by Kevin Zhang from TSMC). Since the platform uses both 2.5D integration and 3D stacking, Broadcom calls it '3.5D.'

"TSMC and Broadcom have collaborated closely over the past several years to bring together TSMC's most advanced logic processes and 3D chip stacking technologies with Broadcom's design expertise," said Dr. Kevin Zhang, Senior Vice President of Business Development & Global Sales and Deputy Co-COO, TSMC.

Broadcom is set to use its 3.5D eXtreme Dimension System in Package platform for custom AI/HPC processors and ASICs it designs for companies like Google, Meta, and OpenAI, which have infinite demands for performance. As part of the platform, Broadcom will offer a broad set of IPs, including HBM PHY, PCIe, and GbE; full-solution chiplets; and even silicon photonics, which enables its clients to focus on the essential part of their processors: processing unit architecture.

Broadcom's lead 3.5D XDSiP product combines four compute dies made on TSMC's leading-edge process technology (N2), one I/O die, and six HBM modules.

Broadcom currently has five products under development using its 3.5D technology, including several products for the growing AI sector from its major customers and one — the Fujitsu Monaka processor that will use the Arm ISA and TSMC's 2nm-class process technology — aimed at both AI and HPC spaces. Shipments of 3.5D XDSiP products will start in February 2026.

"With over a decade-long partnership, Fujitsu and Broadcom have successfully brought multiple generations of high-performance computing ASICs to the market," said Naoki Shinjo, SVP and Head of Advanced Technology Development at Fujitsu. "Broadcom's latest 3.5D platform enables Fujitsu's next-generation 2-nanometer Arm-based processor, Fujitsu-Monaka, to achieve high performance, low power consumption and lower cost."

Ukrainian researchers have uncovered Western-made components in North Korean missiles used by Russia in its war against Ukraine. These components, which include microcontrollers, came from at least nine Western companies despite strict sanctions. This discovery highlights weaknesses in enforcing export controls and raises concerns about the continued flow of technology to North Korea and Russia, reports Bloomberg.

The list of implicated companies includes U.S.-based Analog Devices and Broadcom, Dutch NXP Semiconductors, Swiss company TRACO Electronic AG, and British XP Power. These parts were manufactured as recently as last year, demonstrating that components are still being smuggled to North Korea and eventually to Russia despite years of sanctions.

The missile analyzed was a North Korean KN-23/24, shot down over Ukraine's Poltava Region on September 7. Inside, researchers found crucial chips used for navigation and communication, all of which should have been restricted by export laws. This discovery underscores the ongoing problem of Russia and North Korea accessing advanced Western technology for military purposes, despite increasingly tough sanctions aimed at stopping these transfers.

Several companies implicated in the above denied knowingly selling their products to North Korea. American firms told Bloomberg that they were working with authorities to strengthen compliance measures and to prevent any illegal diversion of their products. Broadcom, in particular, mentioned that many of its components are commonly counterfeited, implying that some Broadcom-branded chips that were discovered weren't genuine while others may have reached North Korea through illicit means.

Russia's ability to continue obtaining these components is worrying, as they are crucial for building missiles that have been used in attacks on Ukraine's civilian infrastructure, businesses, and energy networks.

The broader concern is the growing partnership between North Korea, Russia, Iran, and possibly other sanctioned countries. This collaboration appears to extend beyond just the supply of parts, with these countries potentially exchanging engineers and technological expertise to bolster their military capabilities. This growing alignment between sanctioned nations threatens to further undermine global security efforts.

AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft have joined forces to develop Ultra Accelerator Link (UALink), a new industry standard to enable high-speed, low-latency interconnection for datacenter grade AI and HPC accelerators. UALink will allow for interconnecting up to 1,024 accelerators within one pod, which would be a major achievement. The UALink technology will essentially compete against Nvidia's NVLink, so the green company is not participating in its development.

The UALink initiative is designed to create an open standard for AI accelerators to communicate more efficiently. The first UALink specification, version 1.0, will enable the connection of up to 1,024 accelerators within an AI computing pod in a reliable, scalable, low-latency network. This specification allows for direct data transfers between the memory attached to accelerators, such as AMD's Instinct GPUs or specialized processors like Intel's Gaudi, enhancing performance and efficiency in AI compute. 

"The work being done by the companies in UALink to create an open, high performance and scalable accelerator fabric is critical for the future of AI," writes Forrest Norrod, executive vice president and general manager, Data Center Solutions Group at AMD in the press release. "Together, we bring extensive experience in creating large scale AI and high-performance computing solutions that are based on open-standards, efficiency and robust ecosystem support. AMD is committed to contributing our expertise, technologies and capabilities to the group as well as other open industry efforts to advance all aspects of AI technology and solidify an open AI ecosystem." 

AMD, Broadcom, Google, Intel, Meta, and Microsoft all develop their own AI accelerators (well, Broadcom designs them for Google), Cisco produces networking chips for AI, while HPE builds servers. These companies are interested in standardizing as much infrastructure for their chips as possible, which is why they are teaming up for this the UALink Consortium. Since Nvidia has its own infrastructure, it is naturally not interested in co-developing UALink.

By standardizing the interconnect for AI and HPC accelerators, it will be easier for system OEMs, IT professionals, and system integrators to integrate and scale AI systems in datacenters. The standard aims to promote an open ecosystem and facilitate the development of large-scale AI and HPC solutions.

"UALink is an important milestone for the advancement of Artificial Intelligence computing," said Sachin Katti, SVP & GM, Network and Edge Group, Intel. "Intel is proud to co-lead this new technology and bring our expertise in creating an open, dynamic AI ecosystem. As a founding member of this new consortium, we look forward to a new wave of industry innovation and customer value delivered though the UALink standard. This initiative extends Intel’s commitment to AI connectivity innovation that includes leadership roles in the Ultra Ethernet Consortium and other standards bodies." 

The UALink Consortium will be established to oversee the development and implementation of the UALink standard. The consortium is expected to be incorporated by the third quarter of 2024, aligning with the release of the 1.0 specification. Companies that join the consortium will have access to the specification and can contribute to its ongoing development.

Driven by unprecedented demand for its H100 processor used for AI and HPC applications, Nvidia more than doubled its revenue in the calendar year2023 and became the world's largest fabless chip developer by revenue last year. The company did much better than the remaining nine companies in the top 10 and was among only four developers that posted revenue increases last year, reports TrendForce.

Revenue of the top 10 fabless chip design firms rose to approximately $167.6 billion, a 12% increase from the previous year, largely due to gargantuan contributions from Nvidia, which recorded a stellar 105% growth and earned $55.268 billion and reportedly captured over 80% of the AI accelerator market. TrendForce believes that Nvidia's ongoing dominance is set to strengthen in 2024 as the company is on track to release its Hopper-based H200 GPU and Blackwell-based B100, B200, and GB200 products.

Broadcom also saw positive growth: its 2023 revenue reached $28.445 billion, a 7% increase. This was partially fueled by the AI chip sector, which now accounts for nearly 15% of its semiconductor solutions, according to TrendForce.

Conversely, AMD faced a slight setback, with revenue dropping 4% to $22.68 billion, primarily due to reduced demand in the PC sector. However, growth in its data center and embedded businesses provided some offset, spurred by the company's acquisition of Xilinx.

On the other hand, Qualcomm and MediaTek — two major developers of application processors for smartphones — experienced declines due to a slump in the handset market. Qualcomm's revenue fell by 16% to $30.913 billion, impacted by poor performance in the handheld device and IoT sectors amidst low shipment volumes in China. Similarly, MediaTek saw a 25% reduction in its revenue to $13.888 billion, suffering losses across its smartphone, power management IC, and smart edge divisions. 

Looking ahead, the IC design industry is poised for further expansion in 2024, driven by demand for AI processors. The proliferation of AI is anticipated to extend into personal computing devices, such as PCs and smartphones. This shift is expected to fuel continued revenue growth across the sector.

Notably, the rankings among the top ten companies saw some shifts. MPS made its way onto the list with a 4% increase in revenue, reaching $1.821 billion, thanks to its strong performance in automotive and enterprise data sectors. In contrast, Realtek experienced a 19% decline in revenue to $3.053 billion, leading to a drop in its ranking due to faltering PC sales and halted projects in China. However, prospects for recovery are on the horizon for Realtek with the rise of Wi-Fi7 and renewed telecom tenders expected to drive the company's sales.

Broadcom has demonstrated that it is perhaps the world's largest processor. But for what application? When we visited TSMC's events, we were always shown a deck of multi-chiplet processors that use the company's chip-on-wafer-on-substrate (CoWoS) packaging technology and feature near the reticle limit (858mm^2, 26 mm by 33 mm) compute chiplets. We cannot take photos of the deck, but there are certainly processors that grab attention. One of those devices comes from Broadcom, and it has been shown at the company's recent investor events.

For most observers, Broadcom is a networking and telecommunications giant, but the company also has a significant custom chip design business. For those unfamiliar with this unit of Broadcom, Google is one of the company's most prominent clients in terms of contract chip design.

However, just like TSMC, Broadcom does not announce its clients. For those who want to rekindle its short-term innovations, Broadcom has a list of them in its recent press release. What it does to impress is demonstrate its vast accomplishments to its investors. These are indeed vast, as observed by our friend and colleague Patrick Moorhead of Moor's strategies market analysis company.

"Here is another fun one," Patrick Moorhead wrote in an X post. "The guy who is smiling Frank Ostojic [who] runs Broadcom's custom silicon group. He should be smiling as he announced that he has a third XPU design from a large 'consumer AI company.'

Broadcom officially brands those chips as XPUs so as not to disclose their applications. Meanwhile, the use of high-bandwidth memory pretty much shows its target usage, which might well be artificial intelligence or hardcore AI-infused network switching.

"To the right is a close up of the XPU," Moorhead added. "You can see the two compute units on the center and all the HBM to the left and right. A full up custom SoC with lots and lots of compute, HBM, very high speed intra chip connectivity and, as you would expect, the highest performance external networking."

Developing a chiplet of this scale (i.e., near the reticle size) is already an achievement. Yielding it to a proper level is another dimension of achievement, and it looks like Broadcom's foundry partner, most likely TSMC, has accomplished it as well. Now, it is time for software to catch up and use this processor's might.

Intel showcased its Gaudi3 Processor for artificial intelligence (AI) workloads alongside the formal introduction of its 14th-Gen Core Ultra "Meteor Lake" processors and 5th-Gen Xeon Scalable CPUs for datacenters. The accelerator is set to arrive in 2024 and will offer a significant performance bump compared to its predecessor, the Gaudi2.

Intel CEO Gelsinger discussed the upcoming release of Intel's Gaudi3, which is scheduled for next year, and showed off the new AI accelerator aimed at deep learning and large-scale generative AI models for the first time. The new unit looks like a huge module (OAM, we presume) with a massive ASIC and multiple HBM3 (or HBM3E) memory stacks on it. The ASIC package looks significantly larger than the Gaudi2, so we presume that it is equipped with eight HBM3E stacks on it (rather then with six in case of Gaudi2). Based on a slide Intel presented at SC23, Gaudi3 is not a monolithic processor, but rather a dual-chiplet design that fuses together two processors.

In addition, Intel announced that the Gaudi3 will offer four times higher BF16 performance, two times faster networking performance, and 1.5X higher bandwidth compared to Gaudi2.

"Our Gaudi roadmap remains on track with Gaudi3 out of the fab, now in packaging and expected to launch next year," said Pat Gelsinger, CEO of Intel, at the company's latest conference call (via SeekingAlpha). In 2025, Falcon Shores brings our GPU and Gaudi capabilities into a single product."

Intel's Habana Gaudi2 already is a quite promising product, with 24 fully programmable Tensor Processor Cores (TPCs) and 96GB of HBM2E memory, capable of challenging Nvidia's H100 GPU for AI and HPC. Intel's Habana Gaudi3, which is expected to hit the market in 2024, will offer significantly improved performance ove its predecessor, Gelsinger said earlier this year.

Intel said the Gaudi line-up has experienced significant growth — attributed to its proven performance and competitive TCO, as well as its reasonable pricing. The company is confident that the rising demand for generative AI hardware will position Intel to secure a more substantial share of the accelerator market in 2024, primarily through its range of AI accelerators, which will be spearheaded by Gaudi.

"We are pleased with the customer momentum we are seeing from our accelerator portfolio and Gaudi in particular, and we have nearly doubled our pipeline over the last 90 days," said Gelsinger on the call.

Nvidia this year became the world's most valuable semiconductor company with a value of over $1 trillion. The company earns more money than Intel and other tech giants, and yet Jensen Huang's management style is quite unconventional, as it turns out, with no long-term planning and 40 direct reports, among other interesting tidbits. Nvidia CEO Jensen Huang outlined his management philosophy in an interview with Joel Hellermark conducted earlier this year (and recently noticed by analyst Dan Hockenmaier), giving a unique insight into the radically different way that Huang manages his company.  

40 Direct Reports, No 1:1 Meetings

Huang avoids typical hierarchical communication and maintains a flat organizational structure, with as many as 40 direct reports. Meanwhile, he avoids 1:1 meetings, preferring group discussions that ensure everyone is on the same level, starting right from the top. Huang places a strong emphasis on continuous learning and staying updated with the latest trends and innovations in the industry. One of the ways he does this is by surrounding himself with knowledgeable individuals who are willing to share their expertise.

Meetings at Nvidia are not restricted by rank or position. Everyone, from VPs to entry-level employees, has access to all information and can join any meeting, according to Huang. Huang's philosophy revolves around the idea that if there's a strategic direction or decision to be made, why limit the information to a select few?  

"If there is a strategic direction, why do you tell one person," Huang asked rhetorically. "You tell everybody, and so after, we are swimming in the soup of strategizing and how to formulate the path to the future. When the time comes, I will send it out to everybody at the same time, or I will tell everybody at the same time, and people will give me feedback, and we will refine it."

Share Strategic Directions, No Solid Plans

By sharing the strategic direction of the company with everyone, Huang says he opens the door for feedback from various perspectives. This collective approach is designed to harness the intelligence and expertise of the entire organization, leading to refined and well-thought-out strategies.

When it comes to strategies, Nvidia certainly follows its own path. In terms of planning, Huang believes that rigid long-term plans can sometimes be restrictive. Therefore, he doesn't set long-term or short-term plans. Instead, the company adopts a flexible approach, constantly re-evaluating its strategies based on the ever-evolving business and market conditions, according to Huang. This is particularly crucial given the rapid advancements in the field of AI, where adaptability can be a significant advantage.

"We don't do a periodic planning system," said Huang. "The reason for that is because the world is a living, breathing thing. So, we just plan continuously; there is no five-year plan, there is no one-year plan, there is no plan — there is just what we are doing."

To speed up the decision-making process and stay up-to-date with realities, Huang gave up usual status reports. He feels that by the time status updates reach him, they often lose their "ground truth" (original essence and authenticity). To counteract this, he encourages any employee to email him their immediate 'top five things' on their mind. Every morning, he dedicates time to reading around 100 of these emails, ensuring he is in touch with the ground realities of his company.

Think Outside the Box, Leave Commodity Markets

Huang says the core mission of Nvidia is to tackle challenges that are on the edge of what's currently possible, pushing the envelope of what conventional computers can achieve rather than solving regular computing problems. In fact, Huang believes in walking away from businesses or sectors that have become commoditized, which is why Nvidia left the smartphone and tablet SoC market a few years ago. Huang feels this approach drives technological advancements and sets Nvidia apart from rivals. 

However, making decisions that deviate from the norm or established playbooks can be challenging. Instead of following established practices, Huang suggests breaking down problems into their fundamental truths and building solutions from there, saying this approach encourages innovative thinking and often leads to groundbreaking solutions that traditional methods might overlook. Another way Huang says he deviates from established practices is by trusting his intuition to 'make the right decisions at the right time.'

Huang describes Nvidia's organizational structure as having three primary objectives: attracting the best talent in the industry, operating with a lean and efficient team, and ensuring that information flows swiftly and effectively throughout the company.

The merits of different management styles often come with many tradeoffs, and we don't get to see that side of the picture in the one-sided description. However, it is clear that Huang's unique style is designed to retain much of the flexibility you would see with a start-up, as opposed to the rigid hierarchical organizations at large incumbents that often become mired down in internal bureaucracy and then begin to stagnate. Nvidia is experiencing rapid growth now as it has essentially cornered many aspects of the explosive GPU market, but how this streamlined management style will work as the company becomes larger remains a question, along with whether or not a successor could succeed in replicating the approach.

TSMC has reportedly tapped two industry heavyweights to explore silicon photonics, according to UDN.com. This move addresses the rising demand for enhanced data transmission speeds, especially with the proliferation of AI technologies and large language models that run on multiple machines. 

Reports indicate that TSMC has assembled a dedicated R&D team of approximately 200 experts, focusing on harnessing silicon photonics's power for future chips. Speculation suggests that TSMC is in talks with major players like Broadcom and Nvidia to co-develop applications centered on the technology. This collaboration aims to produce next-generation chips with silicon photonics, and substantial orders are expected as early as the second half of 2024.

While TSMC has not confirmed the rumors (which have been ongoing for at least a year), the company is optimistic about silicon photonics technology. 

"If we can provide a good silicon photonics integration system ... we can address both critical issues of energy efficiency and computing power [performance] for AI," said Douglas Yu, TSMC VP of pathfinding for system integration, reports Nikkei. "This is going to be a new paradigm shift. We may be at the beginning of a new era."

The SEMICON Taiwan 2023 international semiconductor equipment exhibition recently highlighted silicon photonics by hosting the Silicon Photonics Global Summit, underscoring its growing importance in the industry. Virtually all prominent chip designers, including Intel, are exploring silicon photonics. The collective interest from these giants indicates that the market for the technology could experience a surge starting from 2024 and onwards.

In the wake of the rapid expansion of AI and HPC, there is a growing need for faster datacenter interconnections. Traditional technologies are struggling to keep pace, prompting the industry to turn to other solutions and silicon photonics, which transforms electrical signals into light signals, has emerged as a promising answer that can dramatically speed up chip-to-chip and machine-to-machine interconnections. 

However, the journey is not without challenges. As data transmission rates climb, power consumption and heat management become more critical. The industry's proposed solution involves integrating silicon photonics components with specialized chips using Co-Packaged Optics (CPO) technology. This approach is already gaining traction, with tech leaders like Microsoft and Meta considering its adoption for their next-gen network infrastructures. 

Intel recently held a launch event for a new China-specific version of its Gaudi 2 processor for artificial intelligence (AI) workloads, and this new version is compliant with the latest US sanctions on China-bound AI and GPU processors. The new version cuts down the card's scale-up interconnect, which somewhat limits the performance of AI servers on its base. To some degree, this will help with the massive shortages of AI GPUs, such as Nvidia's A100 and H100, as well as the cut-down A800 versions that Nvidia has also created specifically for its China customers.

Intel has two Gaudi 2 versions that come in the 600W OCP model form factor. The regular version, called Gaudi 2 HL-225H, has 24 x 100Gbps RDMA (RoCE v2) interconnects, whereas the cut-down version of the product, called Gaudi 2 HL-225B, has 21 x 100Gbps RDMA (RoCE v2) scale-up interconnects. The reduced number of scale-up interfaces reduces the performance of AI servers based on this version of Gaudi 2, but keeping in mind the huge demand for AI capabilities in China, it will likely be popular regardless.

Intel describes the Gaudi 2 accelerator's version for the Chinese market as 'The HLB-225B Processor complies with US BIS regulations' for supercomputers and semiconductors.

While the availability of Intel's Habana Gaudi 2 in China will ease shortages of GPU servers, it should be noted that it isn't likely that applications that already use Nvidia's GPUs will be ported to Gaudi. Therefore, Nvidia's existing customers will have to keep buying from Nvidia.

"On July 11, Intel held an event for customers, partners and local media in the China market," an Intel spokesperson said. "As part of the event program, Intel provided attendees with updates on our AI strategy, our unique portfolio of AI products and announced the availability of Gaudi2 for customers in China. The availability of Gaudi2 in China continues Intel’s nearly 40-year history of delivering innovative yet legally-compliant products to this key growth market."

According to DigiTimes, TSMC is accelerating orders with backend equipment suppliers as it starts an expansion plan for its chip-on-wafer-on-substrate (CoWoS) packaging capacity. The shortage of compute GPUs for artificial intelligence and high-performance computing, which Nvidia largely dominates, is mainly attributed to TSMC's limited CoWoS packaging production capabilities.

Reports suggest that TSMC has plans to increase its current CoWoS capacity from 8,000 wafers per month to 11,000 wafers per month by the end of 2023 and then to around 14,500 – 16,600 wafers by the end of 2024. Previously Nvidia was rumored to increase its CoWoS capacity to 20,000 wafers per month by the end of 2024. Remember that the information comes from unofficial sources and may be inaccurate. 

Major tech giants like Nvidia, Amazon, Broadcom, Cisco, and Xilinx have all boosted their demand for TSMC's advanced CoWoS packaging and are consuming every wafer they can get. As a result, TSMC has been forced to renew orders for necessary equipment and materials, according to DigiTimes. The production of AI servers has significantly risen, fueling the already intense demand for these advanced packaging services. 

Nvidia has already booked 40% of TSMC's available CoWoS capacity for the coming year. However, due to the severe shortage, Nvidia has started exploring options with its secondary supplier, placing orders with Amkor Technology and United Microelectronics (UMC), although these orders are relatively small, the report claims. 

To cater to its increased CoWoS packaging needs, TSMC is partnering with multiple suppliers from around the globe, including U.S.-based Rudolph Technologies, Japan's Disco, and Germany's SUSS MicroTec, along with Taiwanese experts Grand Process Technology (GPTC) and Scientech. The suppliers are under pressure to provide almost 30 sets of relevant tools by mid-2024. 

TSMC has also begun implementing strategic changes, such as redistributing some of its InFO production capacity from its northern Taiwan site in Longtan to its Southern Taiwan Science Park (STSP). It's also fast-tracking the expansion of the Longtan site. Furthermore, TSMC is increasing its in-house CoWoS production while outsourcing part of its oS manufacturing to other assembly and test (OSAT) companies. For instance, Siliconware Precision Industries (SPIL) has been one of the beneficiaries of this outsourcing initiative.

TSMC opened its Advanced Backend Fab 6 facility last week. It is set to expand its advanced packaging capacity for its frontend 3D stacking SoIC (CoW, WoW) technologies and backend 3D packaging methods (InFO, CoWoS). For now, the fab is ready for SoIC. The Advanced Backend Fab 6 can process around one million 300-mm wafers per year and carry out over 10 million hours of testing annually, with cleanroom space that is larger than the combined cleanroom spaces of all other TSMC advanced packaging facilities.

Among the most impressive features of the Advanced Backend Fab 6 is the extensive five-in-one intelligent automated material handling system. The system controls the production flow and detects defects instantly, increasing yield. This is crucial for complex multi-chiplet assemblies like AMD's MI300, as packaging defects immediately render all chiplets unusable, leading to significant losses. With data processing capabilities 500 times faster than average, the facility can maintain comprehensive production records and track every die it processes.

Nvidia uses CoWoS for its highly successful A100, A30, A800, H100, and H800 compute GPUs. AMD's Instinct MI100, Instinct MI200/MI200/MI250X, and the upcoming Instinct MI300 also use CoWoS.

Intel has proclaimed that “the Wi-Fi future is here” after successfully demonstrating Wi-Fi 7 technology with partner Broadcom. In the over-the-air demos, a Wi-Fi 7 connection between an Intel Core-powered laptop and a Broadcom access point achieved a steady 5 Gbps transfer speed. This is a worthwhile upgrade versus Wi-Fi 6, which maxes out at 1 Gbps.

As the Intel news blog highlights, industry collaboration is essential to ensure the widespread adoption of Wi-Fi 7 and its practical benefits. Having one Wi-Fi 7 in one category of devices but no other is pretty useless.

Broadcom chimed in to assert that “the ecosystem is ready.” It highlighted the value of Wi-Fi 7 goes beyond simple speed increases to deliver greater network capacity and the benefits of much lower latencies. The reduced latencies will be invaluable for immersive experiences over Wi-Fi, with the most obvious applications being online gaming and reduced latency wireless VR headsets. For media streamers, it also opens up the eye-popping possibility of UHD 16K streaming (or more people on the network streaming 4K or 8K videos). Last but not least, the newest Wi-Fi standard could help reduce wireless network traffic jams in busy homes and offices.

The underlying technologies behind Wi-Fi 7 include wider 320 MHz channels in unlicensed 6GHz spectrum and higher order 4K QAM data modulation. Intel’s blog also outlined the importance of multi-link operation and improved channel utilization efficiency.

Video: demo compares Wi-Fi 6 on the 5 GHz band, vs. Wi-Fi 6E on the 6 GHz band, vs. Wi-Fi 7 on the 6 GHz band.

These are still early days for Wi-Fi 7, as it isn’t expected to be certified until next year, with products bearing the Wi-Fi 7 logo perhaps not appearing until H2 2023. However, last month an Intel exec was quoted as saying Wi-Fi 7 will start to be “installed in PC products such as laptops by 2024.” As one (code)name is never enough, Wi-Fi 7 devices will also be referenced as featuring the “Wi-Fi 802.11be” connectivity protocol.

A positive from the lengthy sounding rollout timescale is that Wi-Fi 7 speeds could be further enhanced in the interim. Hopefully, Wi-Fi 7 will catch on quickly, inspired by the attractive transfer speeds and latency benefits. It will also be welcomed if Wi-Fi 7 device rollout isn’t hampered by the component shortage problems, which slowed Wi-Fi 6E device availability.

In the first quarter of 2022, the Top 10 fabless chip designers increased their cumulative sales to $39.43 billion, or by a whopping 44% year-over-year, according to TrendForce. Qualcomm and Nvidia continued to remain on top of the list, but AMD — now in the fourth place — is slowly but surely increasing its sales and has all chances to become the third largest fabless chip designer in the coming quarters.

Being the world's leading supplier of smartphone SoCs and RF modules, Qualcomm enjoyed the natural growth of these businesses in Q1 2022. In addition, the company experienced growth in its automotive and IoT sales, so Qualcomm's earnings for the first quarter totaled $9.548 billion (excluding its licensing business), up 52% from the same quarter a year ago.

Nvidia continued to benefit from the growing demand for discrete graphics processing units for client PCs and datacenter GPUs for AI and high-performance computing applications. Hence, its revenue for Q1 reached $7.904 billion, up 53% annually. By contrast, Broadcom was not that lucky, so its sales 'only' increased by 26% YoY to $6.11 billion.

AMD replaced MediaTek from the No.4 spot in Q1 mainly because it added Xilinx sales to its revenues. Still, AMD's CPU and GPU sales significantly increased in the first quarter due to strong demand for high-performance processors and graphics cards. As a result, AMD's earnings exceeded $5.887 billion in Q1 2022, up 71% from the same quarter last year. Once the company adds Pensando to its results and ramps up production of CPUs, GPUs, and console SoCs due to seasonality later this year, it will probably outpace Broadcom in terms of earnings. It will become one of the world's Top 3 fabless designers of chips, a landmark event for a company that almost went bankrupt about half of a decade ago. Of course, it remains to be seen how smooth integration of Pensando and Xilinx will proceed, but for now, the sky is blue for AMD. 

While MediaTek switched its place with AMD, its Q1 revenue grew a healthy 32% year-over-year to $5.007 billion. The company continues to address all kinds of smartphones and tablets with its mobile SoCs. As its portfolio expands and the performance of application processors increases, the company can charge more significant premiums for its products. 

Marvell was another company in Q1 2022 to demonstrate an over 70% revenue growth year-over-year (to $1.412 billion) mainly due to its acquisition of Innovium, a cloud and edge data center networking solutions designer, in October 2021. Meanwhile, Marvell was not the only company to improve its business results by adopting an M&A strategy. For example, Cirrus Logic (No.10) took over Lion Semiconductor to boost its mixed-signal business in mid-2021, so its Q1 2022 sales reached $490 million, up 67% year-over-year. 

Demand for different chips continues to remain strong, particularly in 5G, automotive, AI, high-performance computing, and edge computing spaces. But the geopolitical and macroeconomic situation may pose challenges even for the seemingly resilient semiconductor market. As a result, it will be fascinating to watch how the leading chip companies will address these challenges in the coming quarters.

Rumors have swirled for the past week that Broadcom was in talks to purchase VMware. Today, the chip maker confirmed its intentions by announcing that it will acquire VMware for $61 billion in cash and stock. 

This Broadcom-VMware tie-up would be among the largest ever in the tech industry. Dell bought EMC for $67 billion back in 2015. Earlier this year, Microsoft made a $68.7 billion deal to purchase gaming giant Activision Blizzard. The deal values VMware at $142.50 per share, representing a 44 percent premium compared to the closing price on May 20th (the last trading day before news of the impending deal was first reported). 

Broadcom's chips touch nearly every facet of everyday computing. The company produces chips at the heart of storage and wired networking devices. Broadcom is also a critical player in the wireless industry, making Wi-Fi and Bluetooth chips used in PCs and mobile devices. It is also deeply embedded in industries that you might not think of, like the automotive sector, which has grown increasingly reliant on advanced chips to power infotainment, autonomous driving and battery management systems (in electric vehicles). Broadcom also has a broad enterprise hardware and software portfolio, the latter of which is why the VMware deal is crucial to the company's future growth. 

VMware specializes in virtualization and cloud computing, which is an incredibly hot market segment in the enterprise world. VMware offers virtualized software solutions supported across all major desktop operating systems (Windows, Linux, macOS) and enterprise software solutions for server hardware platforms. Dell spun off VMware, which it acquired in 2015 as part of its EMC transaction, just over a year ago.  

"Building upon our proven track record of successful M&A, this transaction combines our leading semiconductor and infrastructure software businesses with an iconic pioneer and innovator in enterprise software as we reimagine what we can deliver to customers as a leading infrastructure technology company," said Hock Tan, President and CEO for Broadcom. "We look forward to VMware's talented team joining Broadcom, further cultivating a shared culture of innovation and driving even greater value for our combined stakeholders, including both sets of shareholders." 

For his part, VMware CEO Raghu Raghuram added, "Combining our assets and talented team with Broadcom's existing enterprise software portfolio, all housed under the VMware brand, creates a remarkable enterprise software player." 

Broadcom expects that the VMware deal with pass regulatory muster (along with approval from shareholders) and should be completed during its fiscal year 2023.

Taiwan Semiconductor Manufacturing Corp. is set to start high volume production of chips using its N2 (2 nm-class) process technology in late 2025 and deliver the first batch of these chips in early 2026. According to two media reports and sources within the financial community, the first customers to adopt N2 will be Apple and Intel.

Apple and Intel First to Use TSMC's N2

Apple has been TSMC's largest customer by revenue contribution for about a decade, so it is not surprising that it will also be an alpha customer for N2. As for Intel, the company intends to use TSMC's services to make graphics processing units (GPUs) and various SoCs, two types of applications that benefit from leading-edge nodes. So, it is not surprising that Intel will also be one of the early adopters of N2, according to reports by DigiTimes and UDN. Furthermore, given Intel's volumes, it will quickly become one of the foundry's primary customers. 

Since the first batch of N2 chips should be delivered in early 2026, it is unclear which of Apple's system-on-chips (SoCs) will use it then. Meanwhile, analysts from China Renaissance Securities speculate that Intel will use TSMC's N2 for the graphics tile in its codenamed Lunar Lake processor.  

"We also see more clarity around TSMC's N2 expansion schedule in Fab 20 (Hsinchu)," Sze Ho Ng, an analyst with China Renaissance Securities, wrote in a note for clients. "Tool move-in is expected to start by end-2022, based on company plans, ahead of risk production in late 2024E with Intel (client PC Lunar Lake's graphic 'tiles', while the CPU 'tiles' are fabbed using Intel’s 18A) and Apple being the anchor customers for dedicated capacity support." 

The usage scenario of N2 for Lunar Lake is speculation at this point. However, Intel's own slide that describes graphics tiles of Meteor Lake, Arrow Lake, and Lunar Lake processors clearly indicates that the latter's GPU will be made externally using a technology that is more advanced than N3.

AMD, Nvidia, MediaTek to Use N3, N2

AMD, Broadcom, Nvidia, and MediaTek have formally confirmed that they will use various nodes from TSMC's N5 family (N5, N5P, N4, N4P, N4X). MediaTek has already formally introduced its N5-based Dimensity 8000/8100 application processors and N4-based Dimensity 9000 SoC, whereas Nvidia will use a custom 4N fabrication process for its Hopper and presumably Ada Lovelace GPUs. AMD's Genoa and Raphael processors will also be made using a 5 nm technology. 

According to the DigiTimes report, all of these companies are currently in talks with TSMC over allocation for N3-capable capacities starting late 2023 or sometime in 2024. In addition, these companies are also expected to start talks regarding N2-capable allocations next year, though they will certainly adopt N2 significantly later than Apple and Intel.

N2: Coming in 2026

TSMC's N2 will be the foundry's first technology to adopt gate-all-around field-effect transistors (GAAFET), years after Samsung's 3GAE (2023) and over a year after Intel 20A (2024). So far, the world's largest contract maker of chips has not disclosed what to expect from N2 in terms of power, performance, and area/transistor density improvements over N3. However, considering the fact that this will be a brand-new node, it is reasonable to expect tangible advantages over its predecessors. The new fabrication process will continue to rely on proven extreme ultraviolet (EUV) lithography scanners with a 0.33 numerical aperture. By contrast, Intel's 18A is set to use innovative ASML's Twinscan EXE EUV scanners with High-NA (0.55NA).

The Broadcom SoC in the Raspberry Pi 4 Model B has been quietly updated to match the one in the Raspberry Pi 400, according to St Louis-based app developer (and more importantly, Pi Cast guest) Jeff Geerling.

Geerling noticed the change after buying a new Raspberry Pi 4, an 8GB model, to replace a broken board, and spotting that one character in the model number on one of its chips had changed. The BCM2711 is the SoC (System on Chip), the whole brain of the Raspberry Pi housing its CPU, GPU, and the PCIe link that connects the USB ports. Previously, its model number has ended in B0T, but Geerling’s new baby has a model number ending C0T, matching that used in the Raspberry Pi 400’s SoC.

It makes sense for Raspberry Pi to have done this, as it cuts down on the different chips they have to order and handle, and we can probably expect the new model to trickle down throughout the range — indeed, Geerling presents some evidence that this is already happening. The difference between the two models, however, is somewhat fine-grained. Extremely so, in fact. Highly granular, you might say.

It’s basically nothing. There are two main fixes related to RAM addressing, allowing the PCIe and EMMC2 buses to access more memory than they could before (hence why the new chip has appeared on the Pi 4 with the most RAM) and some ‘power gating improvements.’

The Pi 400 runs at 1.8GHz, compared to the Pi 4 Model B’s 1.5GHz, so the new chip may open up better overclocking potential, given sufficient cooling. Otherwise, unless you’re working on something that needs to access 8GB of RAM over EMMC2, it’s unlikely you will notice any difference. 

NortonLifeLock and Avast ave announced a merger, whereby Norton will be purchasing the full amount of available Avast shares so as to incorporate it into its cybersecurity business. The deal, reported via The Verge, worth upwards of $8 billion, will leave the resulting cyber-security giant with a total of around 500 million customers. 

Vincent Pilette, NortonLifeLock CEO, extoled the virtues of this merger, saying that "With this combination, we can strengthen our cyber safety platform and (...) will also have the ability to further accelerate innovation to transform cyber safety.” Avast CEO Ondřej Vlček, on the other hand, added that "At a time when global cyber threats are growing, yet cyber safety penetration remains very low, together with NortonLifeLock, we will be able to accelerate our shared vision of providing holistic cyber protection for consumers around the globe.”

Cyber-security concerns have been increasing at a breakneck pace alongside the pervasiveness of blockchain and cryptocurrency technologies, which add on to the already valuable data that consumers and companies hold in their machines. And it will only increase in wake of ever more sophisticated threats - legions of malware-infected PCs running botnets, ransomware attacks that hold companies hostage, attacks on critical services infrastructure - these are just some of the different attack vectors that the cyber-security community has to tackle when designing their solutions. The merger aims to unite both companies' expertise in their respective fields, with the resulting company looking to be the perfect solution for both privacy-minded consumers (one of Avast's stronger characteristics) and NortonLifeLock's focus on identity security.

Avast has already established itself as an important player in the cyber-security space since its creation in 2010, with its success leading to the acquisition of another cyber-security company, AVG, back in 2016. NortonLifeLock, however, represents the consumer-geared remains of the Symantec cyber-security empire (first established in 1991), which saw its enterprise security solutions sold to Broadcom in 2019.

Nvidia is making friends. Broadcom, MediaTek, and Marvell have all reportedly signaled their approval of the company's $40 billion acquisition of Arm as regulators around the world consider the effect it might have on the global electronics industry.

Higher-profile Arm licensees like Google, Microsoft, and Qualcomm have publicly objected to Nvidia's proposed acquisition of the company, and it wouldn't be surprising if other Arm licensees have complained about the deal in secret.

UK regulators have also raised concerns about the Arm acquisition. The European Commission and the FTC have reportedly contacted Nvidia about the deal, too, even though it hasn't formally requested their approval. These concerns—along with a late request for approval from Chinese regulators—are likely to delay any verdicts.

But now it seems Nvidia has a few allies. The Sunday Times reported that Arm licensees Broadcom, MediaTek, and Marvell have lent their support to Nvidia, as UK regulators prepare to reach a decision regarding the proposed acquisition.

The companies don't appear to have been particularly vocal about their support; we couldn't find any explanations of their stances on the acquisition on their respective websites. Still, even quiet support from these chip makers could prove valuable to Nvidia.

The UK Competition and Markets Authority has until July 31 to prepare a report on the potential national security and competitive impacts of Nvidia acquiring Arm. The UK Secretary of State will use that report to inform their decision about the deal.

Two weeks ago a report surfaced detailing Nvidia's apparent interest in acquiring Arm. Now, it looks like negotiations are already well underway, as reported by Bloomberg. 

According to the publication, which cited "people familiar with the matter," Nvidia is Arm's only potential buyer right now. The companies are reportedly in "advanced talks" and considering a transaction of stock and cash, though no price has been set yet. Arm was valued at $32 billion back when SoftBank acquired the company in 2016. Nvidia would be able to afford this transaction thanks to increases in its stock price over the past year.

In four years under SoftBank's direction, Arm's annual revenue has only increased from $1.2 billion to $1.9 billion, as reported by the Financial Times. Under a new roof, such as Nvidia's, there is a chance that Arm could meet higher expectations. Nvidia's revenue has tripled in that same timeframe.

However, there are concerns to be had with Nvidia acquiring Arm. The transaction would have to be subject to tough antitrust investigations, as Arm is a fundamental player in much of the technology industry. Arm licenses its architectures to clients such as Qualcomm, Apple, Broadcom and even Nvidia itself from time to time. Placing this licensor in the hands of Nvidia would give the graphics card maker a lot of power in the market.

One of the important developments to note in this process is that Apple is currently transitioning its Mac systems to its own silicon design, which will feature an Arm architecture. 

Whether the deal will go through is unknown, but we do know that if it happens, it could fundamentally change the technology landscape as we know it.

Earlier this year, the Raspberry Pi Foundation hooked up with Igalia to start development on an open-sourced Vulkan graphics driver for the Raspberry Pi. However, Martin Thomas, an engineer at Nvidia, beat them to the punch.

Thomas announced yesterday via his personal Twitter that his RPi-VK-Driver is ready for primetime. The talented engineer had been working on the Vulkan driver in his spare time for more than two years. 

Technically, Thomas' iteration isn't a Vulkan driver per se because it doesn't comply with the official standards established by The Khronos Group. Nonetheless, the resourceful developer produced a driver that adheres to the Vulkan parameters as much as possible, and as close as the hardware would permit it. There's just one limitation with the RPi-VK-Driver though. Unlike the official Vulkan driver that's still in the works, Thomas' version is only compatible with the Broadcom VideoCore IV GPU that's found inside the Raspberry Pi 1, 2, 3 and Zero devices.

Thomas showed off the power of his RPi-VK-Driver with a Raspberry Pi 3 Model B+ and Quake III Arena. The Broadcom VideoCore IV GPU, which is clocked at 250 MHz, runs the title at over 100 FPS on the 1,280 x 720 resolution. Thomas estimated that the Raspberry Pi 3 Model B will likely deliver around 70 FPS at a 1,920 x 1,080 resolution due to the hardware limitation.

In comparison to the OpenGL drivers, Thomas affirms that his RPi-VK-Driver offers improved memory management, and it's better at handling multi-threaded command submissions. The driver's other attributes include MSAA (multisample anti-aliasing) support, low level assembly shaders and performance counters.

The integrated circuit (IC) market, which was led last year by Nvidia, Qualcomm and Broadcom, is "unlikely to return to growth in 2020" due to the "combined influence of the U.S. Entity List and the COVID-19 pandemic," TrendForce said today. This is despite the slight improvements some companies saw in the fourth quarter of 2019.

The research firm said the industry's revenues were down 4.4% year-over-year for 2019. It attributed much of that decline on Broadcom, Qualcomm and Nvidia because they all suffered from decreased revenues despite being market leaders.

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• The best graphics cards for gaming
• AMD Ryzen Embedded appears in tiny Raspberry Pi-sized computer

Broadcom and Qualcomm's revenues dropped after Huawei was added to the Entity List by the U.S. Department of Commerce, according to TrendForce, which means they're unlikely to see much improvement in 2020 unless export restrictions change.

TrendForce said that Nvidia's problems resulted from "excessive stock of gaming graphics cards in the first three quarters of 2019." Things improved in Q4 but not enough for Nvidia's year-over-year revenues to fully recover.

Here's what TrendForce said about COVID-19's potential effect on the industry:

"The COVID-19 pandemic is now a global threat, which will certainly affect the public's purchasing demand for consumer electronics. [...] Given that the pandemic has already exerted its influence over the IC design industry in 1H20, the overall industry is unlikely to recover in 2020."

That's in line with previous reports indicating that COVID-19 led to reduced demand for motherboards and graphics cards in China earlier this year, as well as a report today that coronavirus is hitting motherboard and GPU shipments. Now that the virus has gone global, it wouldn't be surprising if we saw similar declines elsewhere.

Companies were essentially hit with the one-two punch of U.S. export restrictions and a global pandemic that can disrupt their supply chains and reduce demand for their products. Here's to hoping that 2021 will be a little bit easier to manage.

If you've ever wanted to buy a chip factory, now's your chance! The chip fab that used to belong to SK Hynix up until 2015 but shut down in 2008 is up for auction with a starting bid of $1.5 million, as reported by Oregon Live Tuesday. 

The fab is at 1830 Willow Creek Circle in Eugene, Oregon and has a floor space of 1.2 million square feet. it has a huge amount of excess land available for further expansion and comes with one clean room, which could be helpful, for example, for the pharmaceutical industry, of 122,000 square feet.

The property also has a lot of power access with two 42MW substations for 84MW of power, has access to high-speed internet, as well as a water discharge capacity of 1.2 million gallons per day. The property even comes with some of the old infrastructure for 200mm wafer manufacturing, according to the listing.

Eugene Technology Center's History

SK Hynix initially opened the factory in 1998 with a $1.5 billion investment. A decade later, SK Hynix closed the factory with roughly 1,400 losing jobs, according to the Oregon publication 

After this, the fab remained unused for years until 2015, when Avago, now known as Broadcom, bought the fab for $21 million. However, Avago changed its tune about re-opening the fab the next year.

Following that, Corning (the company that makes the Gorilla Glass in your phone), bought the factory for $13.4 million but did not end up using it for anything. 

Fast forward three years to today, and the factory is once again for sale, this time with the auction opening at just $1.5 million. If you want in, you'll have to pay a $25,000 participation deposit to cast your bid from March 23 through March 25, 2020.

TSMC announced a partnership with Broadcom to introduce an enhanced Chip-on-Wafer-on-Substrate (CoWoS) platform, a 2.5D integrated circuit (2.5D IC) through-silicon via (TSV) interposer-based packaging technology, that supports the industry’s first and largest full 2x reticle size interposer.

The next generation CoWoS interposer has an area of approximately 1,700mm2 and can be used to boost computing power for high-performance computing (HPC) systems. The technology will also be ready to support TSMC’s next-generation 5nm process node.

The new CoWoS generation can accommodate multiple logic system-on-a-chip (SoC) dies and up to six cubes of high-bandwidth memory (HBM) supporting up to 96GB of memory. The new CoWoS technology also provides 2.7 terabytes per second (TB/s) bandwidth, which is 2.7x higher than TSMC’s previous CoWoS technology that it launched in 2016. 

TSMC also says the interposer provides 2.2X more memory bandwidth than any other competing technology. According to WikiChip, Intel’s cancelled Spring Crest had a memory bandwidth of 1.23 TB/s, while NEC’s Aurora peaks at 2.2 TB/s. 

The support for the larger memory bandwidth comes from Samsung’s “Flashbolt” HBM2E dies. These dies have twice the density (16 gigabits) per die compared to competing solutions and support up to 3.2 GT/s. That results in a bandwidth of 2.46 TB/s for six stacks.

The higher memory capacity and bandwidth makes it suited for memory-intensive applications such as deep learning, 5G networking workloads, power-efficient data centers, and so on. The new technology offers additional space and increased flexibility and yield for complex ASIC designs. 

TSMC has been previewing interposer technology with up to 3x the reticle size (2500 mm2) or even larger, but there’s no word on when we can expect this technology to arrive. 

ESET researchers today revealed a vulnerability called Kr00k that hackers can exploit to snoop on the Wi-Fi traffic of devices using chips made by Broadcom and Cypress. How many devices might that be? Well, according to the researchers, billions of devices were affected by Kr00k before manufacturers started releasing patches.

These Wi-Fi chips are found in many popular devices. Amazon uses them in its Kindle and Echo products; Apple uses them in various iPad, iPhone and MacBook models; Google uses them in its Nexus products; Samsung relies on them for its Galaxy smartphones and they're also found in the Raspberry Pi 3, as well as Wi-Fi routers.

The ESET researchers said they didn't find any evidence of Kr00k in Wi-Fi chips made by Qualcomm, Realtek, Ralink or MediaTek. This suggests the problem was limited to chips made by Broadcom, which acquired Cypress in 2016, but ESET said they weren't able to test every Wi-Fi chip to confirm that.

"Wi-Fi access points and routers are also affected by Kr00k," the ESET researchers said, "making even environments with patched client devices vulnerable. All-in-all, before patching there were more than a billion affected devices." People were effectively made vulnerable twice: once via their devices and once via access points.

Addressing the vulnerability also required a two-tiered approach. Broadcom had to develop its own patch to release to manufacturers, which then had to release patches for their own products afterwards. And then, of course, people had to actually install the patches before their devices would actually be protected.

That leaves a lot of points of failure. Broadcom released patches to manufacturers, according to the ESET researchers, but it's not clear that every manufacturer has released patches for all of their affected products. Even if they have, there's no guarantee that all of the affected devices will receive those critical patches.

What Should You Do? 

So where does that leave everyone? ESET's researchers said consumers should check with manufacturers to see if a patch is available for their products. It also said that it's working with the Wi-Fi Alliance, "which is developing additional tools that might help organizations identify vulnerable devices in their infrastructure."

CES 2020 is winding down. The event officially ends tomorrow, many companies have already held their press conferences and we've officially worn down the soles of our shoes walking all over the show floor and the Las Vegas Strip. But the show must go on, as Freddie Mercury sang, and so we've collected everything we covered on Thursday.

If you only want to see the best of what CES 2020 had to offer, however, look no further than the Tom's Hardware CES 2020 Awards. We awarded everything from "Best Robot" to "Best Lighting," so odds are good that you'll find something to covet among our picks for the most interesting things found at this crazy show.

You can also find our previous coverage here:

• CES 2020: Everything From Day Zero
• CES 2020: Everything From Day One
• CES 2020: Everything From Day Two

The Latest Components, Led by Intel's Xe Graphics

• Intel Unveils Xe DG1 Mobile Graphics in Discrete Graphics Card for Developers
• Intel's New Core i9-10900K, Could Pull 300W of Power
• Cooler Master Intros World-First 850 W SFX Power Supply
• Gigabyte Unveils Trio Of Non-Auros Branded Gaming Monitors at CES
• Phanteks Shows off Light-show Case at CES 2020
• Samsung’s New T7 Touch External SSD Sports Built-in Fingerprint Reader, Twice the Performance
• Silverstone Shows off New Case Lineups at CES 2020

Accessories, Autonomous Vehicles and All the Rest

• I Drove Razer's Massive Esports Racing Machine
• Aukey's New Laptop Chargers Could Be Smallest Ever
• Lian Li Ups its RGB Cable Game With the Strimer Plus at CES 2020
• Broadcom Prepares for Wi-Fi 6E With a Series of New Chipsets
• Mobileye Finds New Partners to Bring MaaS to South Korea, L2+ to China
• Qualcomm Enters Autonomous Vehicle Market with 700 TOPS Snapdragon Ride
• Pico's VR Glasses May Be the Slickest VR Headset Ever
• Riotoro Shocks CES by Expanding Into Gaming Monitor and Earbuds Market
• FTC Chair: Multiple Antitrust Investigations Will End in 2020

Remember: Our coverage won't stop just because CES 2020 is coming to an end. We're going to be wandering the show tomorrow, too, and will likely be writing about the devices we saw in Las Vegas even after we've all flown back home. (Assuming we manage to get our hands on all of the caffeine, that is.)

You can find all our CES 2020 coverage in one place by bookmarking this page. And you can also follow along on Twitter and Facebook, too.

Broadcom announced a series of chipsets for the new Wi-Fi 6E extension of 802.11ax that introduces Wi-Fi for the 6GHz band, and claims it is the industry's most comprehensive Wi-Fi 6E portfolio.

Broadcom announced four chipsets for residential applications and four for the enterprise. The most powerful chips have support for 4x4 dual-band Wi-Fi with 160MHz channel support. There are also two 3x3 tri-band SKUs with 80MHz channels and a 2x2 SKU with Arm processor. The 6GHz band allows for a maximum of 1.2GHz channel bandwidth, which could be through seven 160MHz channels.

Greg Fischer, senior vice president and general manager of the Broadband Carrier Access Products Division at Broadcom, said this about the chipsets in a statement:

"As momentum accelerates around availability of 6 GHz, Broadcom is excited to be on the forefront of Wi-Fi technology paving the way for ecosystem adoption of Wi-Fi 6E. With the industry's broadest portfolio of Wi-Fi 6E silicon, we will enable our customers to build a variety of products that unlock the tremendous potential of 6 GHz spectrum. This announcement demonstrates Broadcom’s continued leadership and unwavering commitment in driving the next Wi-Fi evolution for enterprise and residential WLAN as well as mobile devices."

Broadcom said it has already started sampling the chips. Wi-Fi 6E on 6GHz was announced last week and allows for 1.4Gbps at 7m with low latency.

Broadcom has started shipping its Tomahawk 4 switch to major cloud providers such as Alibaba and Microsoft. The chip packs 31 billion transistors on TSMC’s 7nm process and has 64 ports of 400GbE switching.

Two years after sampling its 12.8Tbps Tomahawk 3 silicon on TSMC’s 16FF+, segment leader Broadcom has now started shipping Tomahawk 4, the industry’s first switch capable of 25.6Tbps. Early adopters include Alibaba Cloud, Google Cloud, Microsoft, Tencent and Uber.

The 25.6Tbps throughput is achieved by packing 512 instances of 50G PAM4 SerDes. The monolithic 31 billion transistor chip is built on TSMC’s 7nm process. Broadcom says it remains committed to doubling the throughput of its switching silicon every two years.

As such, Tomahawk 4 has support for up to 64 ports of 400GbE switching or 256 ports of 100GbE, the highest radix of 100GbE solutions. According to Broadcom, it has a 75% lower power and cost than competitors. It also has some new features such as advanced load balancing mechanisms. Broadcom is also opening up its switch API as open source software with the introduction of Broadcom Open Network Switch APIs (OpenNSA).

Intel this year entered the switching market with the acquisition of startup Barefoot Networks, whose 7nm Tofino2 with chiplet architecture is capable of 12.8Tbps, while it stopped development of its Omni-Path fabric, launched its first 100Gbps Ethernet controllers and is moving to 400Gbps silicon photonics.

The Next Platform has a deep dive on Tomahawk 4.