Preliminary specifications of Nvidia's GeForce RTX 5080 and GeForce RTX 5090 graphics cards have been published by @kopite7kimi, a reputable hardware leaker who tends to have access to accurate information about Nvidia's upcoming products. If the specifications are correct, then Nvidia's forthcoming GeForce RTX 5090 will be a monster with a 600W total graphics power rating (TGP). Many of these specs line up with previous leaks, just with a bit more detail in some areas. You can see our Nvidia Blackwell RTX 50-series GPUs guide for more details.

Nvidia's GeForce RTX 5090 — the flagship Blackwell GPU for desktop PCs — is expected to be based on the GB202 graphics processor with 21,760 CUDA cores, mated with 32GB of GDDR7 memory using a 512-bit interface. That massive number of FP32 cores will consume enormous amount of power, up to 600W if the leak is accurate. The card will certainly rank among the best graphics cards when it's released, even if the final specifications end up being slightly less impressive. Just don't ask about pricing...

By contrast, Nvidia's GeForce RTX 5080 is said to be powered by the GB203 GPU and will feature 10,752 CUDA cores, which is roughly half of the range-topping offering. RTX 5080 graphics cards are now projected to come with 16GB of GDDR7 memory with a 256-bit interface, with a TGP rating of 400W. With a decent bandwidth uplift enabled by GDDR7, the RTX 5080 should significantly outperform its predecessor in high resolutions and should be a potent graphics card.  

Preliminary specifications of Nvidia's GeForce RTX 5000-series graphics cards

While the potentially massive performance of the GeForce RTX 5090 certainly draws attention, another thing that strikes the eye is the huge performance gulf between the flagship RTX 5090 and its smaller RTX 5080 sibling. It's almost exactly half of the range-topping graphics processor in terms of the number of stream processors and memory interfaces. The TGP will be two-thirds of the top-tier card, so clocks might be higher to try to narrow the gap, but this represents an even bigger difference than with the 40-series GPUs.

That potential performance disparity looks strange to say the least, and suggests Nvidia may want to try and create a new tier of performance — or perhaps limit the appeal of certain consumer cards as AI compute alternatives. The RTX 4090 on paper offers 68% more GPU cores, 50% more VRAM, 41% more memory bandwidth, and 13% more L2 cache than the RTX 4080. In practice, CPU limits hold the 4090 back at lower settings, but at 4K ultra it ended up being about 35% faster than the second tier 40-series GPU — and the RTX 3090 was only about 15% faster than the RTX 3080. But these specs, if correct, suggest the 5090 could be up to twice the performance of the 4080.

While we can't say for certain why Nvidia decided to build its next-generation lineup this way, one of the technical explanations could be that Nvidia's GB202 processor may consist of two GB203 dies. Using a multi-chiplet design for Blackwell GPUs has been rumored for a while and the GB100/GB200 datacenter GPUs indeed adopt this architecture. However, using CoWoS-L packaging to enable the high-speed (~10 TB/s) interconnect between dies for a consumer-grade product seems like a very expensive idea.

An alternative to building a multi-chiplet GPU would be to build a monolithic graphics processor with over 21,760 CUDA cores at TSMC's 4nm-class process technology, which would result in a circa 650 mm^2 die. Such a design is hard to yield because of the large die size, which is why redundancies are usually present — the 4090's AD102 chip for example has a maximum of 144 Streaming Multiprocessors (SMs), but only 128 are enabled. So it's not impossible for Nvidia to go that route if it wants to. A monolithic chip would also be very expensive, however, and it would be weird to have such a huge gap between the RTX 5080 and RTX 5090. Other GPUs could try to plug the holes, though, and we could eventually see lower tier parts that might have something like 18,000 functional CUDA cores.

What we do know is that Nvidia uses the same chips for a variety of products: desktop, mobile, professional, and data center GPUs are all based on the same silicon designs. With AI being such a hot item right now, Nvidia might be creating a massive data center part as the first priority, and then productizing it as a consumer offering as well. If that's the case, don't be surprised if pricing ends up being quite a bit higher than the already exorbitantly priced RTX 4090 — and we could even see AI variants arrive before the consumer models.

For now, all the information we have about Blackwell-based graphics cards for client PCs is strictly unofficial. Apply the usual skepticism and know that, until Nvidia says something directly, things can and likely will change. There are still conflicting rumors on the release date as well, with some saying the RTX 50-series won't arrive until early 2025. If correct, that gives ample time for continued tweaking ahead of the launch. Until the official announcement, we can expect the rumor mill to stay busy churning out various theories and specifications.

It seems that gamers still hoping to get into the RTX 40-series bandwagon will have to be content with the RTX 4090 GPU as the halo product of this generation. That's according to the typically thrustworthy leaker Kopite7kimi, who reported via Twitter that internal Nvidia plans to launch a refreshed flagship — let's call it the RTX 4090 Ti — have been canceled.

The rumor comes as the one-year anniversary of the RTX 4090's announcement (originally in September 2022) is fast approaching. Through recent years, Nvidia has been building out its product stack with mid-generation refreshes that not only add the "Ti" moniker, but also offer performance step-ups to better round-out the company's lineup against AMD's comparable competition. Nvidia has already launched some Ti models (namely the RTX 4060 Ti and the RTX 4070 Ti), but that strategy doesn't seem to be happening on the upper ladders of Nvidia's product stack anymore.

There may be a few reasons for this. The main reason likely has to do with competition (or the lack thereof). Once again, AMD decided not to go after the performance crown; the RX 7900 XTX, while a great card that's frequently at the top of our list of the best graphics cards, is more of a direct competitor to the RTX 4080. Nvidia still has the halo product and the brownie points that brings, so why spend more money in bringing yet another SKU to market?

Of course, there's an argument that NVIDIA must be sitting on at least some number of fully-functioning AD-102 chips, but those bring less of a profit than a comparable professional accelerator (such as the Nvidia L40 or others). There's also the question of power consumption, and with the 16-pin meltdown controversy still not fully put to bed, the potential for issues with a 600W RTX 4090 Ti certainly exist.

There's also the fact that sales of graphics cards and PC components are slumping badly right now. With the previous generation RTX 30-series cards, Nvidia introduced the RTX 3080 Ti and RTX 3070 Ti less than a year after the initial launch, with an RTX 3090 Ti arriving in April 2022. The first two were commercially successful, due to the unprecedented demand. The last? Not so much. If Nvidia doesn't do a mid-cycle refresh for the RTX 40-series, that speaks volumes about how many cards are sitting on shelves.

Kopite7kimi added that while plans for Ti versions of Nvidia's top-performing cards are out of the deck, there's still a plan to optimize production silicon by introducing further products onto the stack. According to the leaker, though, these are being geared more toward the Chinese market and should fit in Nvidia's lineup as variations of the RTX 4060 and 4070 based on the AD103 and AD106 chips. If this pans out, it seems both AMD and Nvidia are willing to make specific GPUs to cater to the (admittedly immense) Chinese market.

As an added bonus, Kopite7kimi also mentioned that multiple industry sources have confirmed that the next-generation Nvidia flagship (let's call it the RTX 5090) will feature a 512-bit memory interface. If true, this marks the first time since the GTX 280 and GTX 285 days — all the way back in 2008/2009! — that Nvidia has used a 512-bit bus width.

Of course, that doesn't include dual-GPU cards, like the Titan Z with a 2 x 384-bit bus.  Or there was also the GTX 295 with a dual 448-bit interface. The last mainstream consumer GPU with a 512-bit bus (not counting HBM/HBM2 solutions) were AMD's R9 390/390X (which were basically tuned variants of the earlier R9 290/290X). Regardless, most graphics cards on the market instead use a simpler, and less expensive, 256-bit bus. Top models may go as wide as a 384-bit interface, which is still enough to offer bandwidth of around 1 TB/s mark when paired with the appropriate VRAM tech (GDDR6X or GDDR6).

Companies usually prefer to add memory bandwidth by adopting newer (and faster) memory tech rather than by increasing the bus depth, due to the lower developmental and manufacturing costs incurred. And with Nvidia being expected to introduce its RTX 5000 series by 2025, it's theoretically possible that the company might be looking to pair its next product family with GDDR7 memory.

At a maximum throughput of 32 Gbps, a 512-bit bus width would translate into 2 TB/s throughput — double that of the RTX 4090. Considering how even $1,500 cards are nowadays insufficient to run the latest games at full settings and native resolution (looking at you, Remnant II), there may be something to that idea. With 2GB memory chips, a 512-bit interface would also translate to 32GB of VRAM total on such a GPU, or potentially even 64GB and 128GB professional versions with 4GB chips.

Again, everything we're saying here stems from Kopite7kimi's tweets. While they're generally correct, this isn't the same as an official confirmation. Product roadmaps can and will change. Maybe Nvidia will ultimately decide to launch a new Titan RTX based on AD102, maybe it won't. So do your best "salt bae" impersonation with regards to the RTX 4090 Ti and future RTX 5090 rumors.

Tokyo Institute of Technology researchers have outlined their new BBCube hybrid 3D memory. BBCube 3D is short for 'Bumpless Build Cube 3D'. It is claimed that this new type of memory could pave the way to faster and more efficient computing by improving the bandwidth between processing units (or PUs, such as GPUs and CPUs) and memory chips. Specific claims for the technology are that it offers 30x bandwidth of DDR5 or 4X the bandwidth of HBM2E. Importantly, it also delivers impressive efficiencies by cutting bit access energy to one-twentieth of DDR5 memory, and a fifth of that used with HBM2E.

BBCube 3D's stacked architecture "has achieved the highest attainable performance in the whole world," boasts the official Tokyo Tech news blog. Before explaining how BBCube 3D memory is designed, the researchers outline the problem facing designers using currently available memory tech like DDR5 or HBM2E. They assert that desirable higher bandwidth currently comes at the expense of one or both of expensive wider buses, or power-intensive data rate boosts.

So, how does BBCube 3D improve the integration between PUs and dynamic random access memory (DRAM)? The diagram above gives a basic overview of the BBCube 3D design. You can see that the Pus sit atop their caches on top of the memory stacks. These are all housed on a silicon interposer foundation.

It is further explained that "the lack of typical solder microbumps, and the use of TSVs in place of longer wires, together contribute to low parasitic capacitance and low resistance." The structure creates connections between PUs and DRAMs in three dimensions, making extensive use of the aforementioned through-silicon vias (TSVs).

Tokyo Tech's claimed performance for BBCube 3D would make it highly attractive to computing designs thanks to a compelling combination of performance and reduced energy use. Another desirable quality of the design, stemming from the power efficiency, is said to be its reduced "thermal management and power supply issues," which can be precipitated by some 3D semiconductor designs.

There currently appear to be no plans in place for BBCube 3D commercialization, so let us join with the scientists at the Tokyo Institute of Technology in hoping that this new technology "paves the way to faster and more efficient computing."

Japanese tech site PC Watch has managed to get its hands on a Moore Threads MTT S80 graphics card. This card uses a GPU that, despite some obfuscation deployed by Moore Threads management, appears to use the Imagination Technologies PowerVR architecture. This isn't going to make the list of the best graphics cards, not even if we roll back the clock to 2015, but it's good to start to see cards like this tested outside of China in benchmarks and games we're familiar with.

Though we're pretty sure that the PowerVR architecture is behind the card, PC Watch reported from Moore Threads verbatim regarding the specs of the MTT S80. So, the card uses the Chunxaio architecture, employing 4096 MUSA cores. Other specs include the GPU's clock speed of 1.8 GHz, and its peak performance of 14.2 TFLOPS. There's a generous 16GB of GDDR6 14 Gbps memory onboard the sample tested by PC Watch, and that connects to the GPU via a 256-bit bus for 448 GB/s bandwidth.

The MTT S80 is relatively power hungry, with a TGP (total graphics power) of 255W. That's probably why it includes a triple fan design. Also interesting is that the card uses a PCI Express Gen5 x16 connector. These raw specs don't tell the full story, of course, and driver support could still be a major factor in performance. But let's see what PC Watch found in its testing.

Before we look at the benchmarks and gaming tests, please note that PC Watch found there were lots of current games that wouldn't run on the MTT S80 - even using a supported motherboard, OS and CPU. DX12 and Vulkan games were insurmountable hurdles for this card, but some DX11 titles could run with varying degrees of success. Modern benchmarks faced a similar issue, with the most current version of 3DMark stable and usable being 3DMark 06.

Above you can see that the MTT S80 fares very badly when put up against even modest competition like Nvidia's GeForce GTX 1050 Ti, a budget GPU that debuted in 2016. On paper, the GTX 1050 Ti is woefully outmatched — it offers up 2.1 teraflops of compute, has 4GB of GDDR5 memory, and 112 GB/s of bandwidth with a 75W TGP. Even with such weak competition, the Moore Threads graphics card falls flat.

The MTT S80 fared best in DX9 graphics comparisons. It was still significantly behind the GTX 1050 Ti but not completely trounced. Or... well, it was completely trounced, but the average performance lead in the DX9 tests was 'only' 86% — so not quite double the performance.

Things were much worse for the MTT S80 when PC Watch looked at a selection of DX11 games. Besides some rendering errors, performance was very poor and some games effectively failed to work at all with single digit fps. Even if we discount Asetto Corsa where the Nvidia GPU was 90 times faster, the average lead in the DX11 games was still 188%, nearly triple the performance. One percent lows were also frightful on the MTT S80.

Poor performance and compatibility isn't the end of the sorry tale of the Moore Threads graphics card, unfortunately. As it stands, the card sucks up a lot of watts for very little. The MTT S80 on average consumed 142W, while the GTX 1050 Ti averaged just 60W.

In terms of performance per watt, even discounting Asetto Corsa (again), the MTT S80 managed just 0.33 fps/W while the GTX 1050 Ti averaged 1.86 fps/W. That makes the old Pascal GPU over five times as efficient.

There's a clear disconnect between the raw specs of the MTT S80 and its real-world results. On paper, the MTT S80 has four times as much memory, four times the memory bandwidth, and nearly seven times the raw FP32 compute. It's nowhere near reaching that theoretical level of performance.

PC Watch seems to think that the Moore Threads graphics card's major issue is with drivers, so it has some hope that things will continue to improve over the coming months. For now, the MTT S80 is not for gamers, curious developers, or graphics card collectors.

Back in February we reported on Korean TechTuber BullsLab Jay's video featuring the same MTT S80 graphics card. At that time, gaming tests were restricted to DX9 titles due to platform / driver immaturity. The fact that the MTT S80 can now at least try to run some DX11 games shows progress with the drivers, but there's still a long way to go. DirectX 12 and Vulkan games are also not currently supported.

YouTuber VswitchZero was a little disappointed after getting his hands on a servicable old 486 DX66 and firing up Doom. Wearing the rose-tinted spectacles of PC gaming nostalgia, one might expect one of the fastest pre-Pentium systems to offer quick and slick Doom thrills, but VswitchZero lamented that Doom ran “very choppy, and [it was] not a lot of fun to play.” The issues were largely caused by the PC’s ISA bus graphics, so the YouTuber decided to work on a project to overclock the ISA bus to the max... resulting in a successful overclock of 212% recorded.

VswitchZero’s ISA hijinks were partly inspired by the acquisition of a 1992 vintage DEC Digital system with ISA slots only, as mentioned above. Further inspiration came from a YouTube channel called CPU Galaxy, which ran an ISA Doom 25 FPS challenge for subscribers. The name of the challenge provides a hint at the low frame rates pioneering PC 3D gamers had to suffer.

For some background to ISA bus overclocking, the bus speed of this old 16-bit interface was usually ~8 MHz. The ISA clock was typically derived from a divider of the front side bus speed. For example, with a CPU running at 33 MHz, a divider of a quarter was used, so the ISA bus would run at 8.25 MHz. However, some motherboards had an independent clock generator crystal. Whichever way your motherboard was configured, adjusting the divider could provide some interesting ISA overclocking opportunities. For contemporaneous graphics cards, which would potentially saturate the 16-bit 8 MHz ISA bus, some decent gains could be attained using this overclocking method.

VswitchZero’s video shows us the old ISA system he put together for his overclocking feat. The YouTuber talks us through the ‘rules’ of the ISA Doom 25 FPS challenge and his choices for motherboard, CPU, RAM, storage, and video card. These choices are important, as some parts are more flexible or malleable to the overclocker’s will, while others will quickly become unhappy with any ISA overclocking — impacting performance and stability.

The system motherboard chosen was an Asus model with SIS chipset, which offers some decent tweakability. Interestingly, the CPU used was an Evergreen upgrade socket AMD 5x86 chip which was praised for its performance, multiplier, and bus frequency flexibility. The ISA graphics card selected was the ATI Mach 32, which apparently was a sweet spot choice for ISA systems and overclocking.

Initial overclock testing with the ISA bus pushed to 11 MHz fell flat, as a BIOS bug meant the divider setting change didn’t result in a faster bus speed. A BIOS update (which was rather laborious and required specialized hardware) did the job. Most importantly, the Doom benchmark showed that an average 21.9 fps was achieved with the 11 MHz ISA bus. VswitchZero was relaxed about still being some distance from beating 25 fps, as there remained optimizations for front side bus (FSB overclocking), CPU overclocking, and other ISA dividers to test.

Configuring a 50 MHz FSB, and 3x multiplier, resulting in a 150 MHz CPU clock had a larger impact. Memory timings and wait states could stay at the lowest values possible, with only the cache read state needing some reduction. With these settings and a 12.5 ISA bus speed, Doom ran stably at 25.1 fps. The YouTuber had cracked the 25 fps milestone.

Next, applying a divider to run the ISA bus at 16.67 MHz worked out without any glitches or other side-effects. Doom could run at 30.4 fps given these settings.

Moving up to an amazing ISA bus speed of 25 MHz, the system remained stable, and VswitchZero says the system could rival VESA Local Bus systems in benchmarks. As for Doom, it managed a flawless run at 35.7 fps. This was quite a feat, considering it started at less than 20 fps.

At the end of the main testing spree, VswitchZero decided to assess some different components, including other ISA graphics cards. You can see the further testing and follow the discussion of the different parts in the video embedded above.

Whether you're looking for the best RAM for gaming to upgrade a PC that struggles with today’s titles or building a new PC from scratch, the most suitable RAM kit for your budget depends on the platform you choose and the workloads you plan to run.

The tricky part is figuring out whether faster memory improves your system’s performance. For instance, if you’re using an Intel system with the best graphics cards, most programs won’t respond significantly to faster or slower memory. However, certain workloads, such as specific games and software, benefit from higher data rates. For example, file compression programs favor fast memory. Check out our RAM benchmark hierarchy and a ranking of the best RAM.

AMD’s Zen-based processors benefit more from higher memory frequencies, which you can read about here. Increased memory speeds on AMD Ryzen- and Threadripper-based systems often lead to real-world performance gains. In gaming, this results in higher frame rates at common resolutions, such as 1080p (1920x1080), and smoother gameplay at higher resolutions. However, the number of extra frames gained with faster RAM can vary greatly depending on the game.

Lastly, memory speed greatly affects gaming performance with integrated graphics, whether using an Intel or AMD processor (you can see how they compare in our CPU Benchmark Hierarchy). The graphics engine built into most of the best CPUs for gaming typically lacks dedicated memory, unlike discrete graphics cards, so faster RAM can also improve performance. However, if you have to pay a premium for the fastest RAM to get playable frame rates, investing in slower system memory and a discrete graphics card is a smarter choice.

In short, the best RAM is usually the fastest, especially if you’re gaming without a dedicated graphics card, using an AMD Ryzen system, and sometimes with Intel chips in specific cases. If you're looking for the best plug-and-play compatibility, DDR5-5600 works directly with AMD Ryzen 9000 (Granite Ridge) and Ryzen 9000 X3D processors. At the same time, DDR5-6400 CUDIMMs are compatible with Intel Core Ultra 200S (Arrow Lake) processors.

The global memory market is currently experiencing a significant shortage driven by the explosive growth in artificial intelligence and data center expansion. Some memory kits have doubled and even tripled in price. Despite these market fluctuations, our recommendations remain valid for both DDR5 and DDR4 platforms. While it would be unrealistic to expect these memory kits to maintain the exact pricing we observed during our original testing and review period, the value proposition of each kit holds. If you find any of our recommended memory kits at a competitive price, we strongly encourage you to act quickly. Memory deals are hard to come by, and they sell out within hours, or even minutes, of being listed.

Prime Day Exceptional RAM deal

Here is a standout budget RAM deal from the Prime Day event, which is currently taking place. See our best overall picks below.

Best RAM For Gaming You Can Buy Today

Best Performance 32GB DDR5 Kit

It's hard to find reasons not to like the Trident Z5 Neo RGB DDR5-6000 C30. The memory kit functions flawlessly out of the box and delivers solid performance. That alone is enough to win over the majority of buyers. Looks, as usual, are subjective, but you can't dispute the Trident Z5 Neo RGB's premium exterior. Like its competition, G.Skill utilizes SK hynix M-die ICS for the memory kit, so some headroom remains for tweaking in memory modules.

DDR5 pricing still fluctuates, but current DDR5-6000 C30 memory kits are available starting at $97.97. When you consider that, the Trident Z5 Neo RGB DDR5-6000 C30's $117.99 price tag suddenly doesn't look so bad. The Trident Z5 Neo RGB DDR5-6000 C30 has proven to be a formidable memory kit for AMD and Intel platforms. There will ultimately be faster memory kits down the road, but in the meantime, the Trident Z5 Neo RGB DDR5-6000 C30 is as good as it gets.

Read: G.Skill Trident Z5 RGB DDR5-6000 C30 review

Best 32GB DDR5 Kit

Best 192GB DDR5 Kit

While not focused on speed, the Vengeance DDR5-5200 C38 is the kind of memory kit that satisfies users who need a lot of memory for their work. This use case includes professionals like content creators, software developers, and data scientists—just to name a few. Current AMD and Intel processors support DDR5-3600 and DDR5-4400, respectively, in a four-DIMM setup. Therefore, DDR5-5200 is technically overclocked, so your results may vary depending on your processor and motherboard.

Corsair currently sells the Vengeance DDR5-5200 C38 for $649.99. The company also offers a more eye-catching version with RGB that adds a $10 premium. It's clear that the memory kit costs a lot, but it's a valuable asset if you need plenty of memory for your work.

Read: Corsair Vengeance DDR5-5200 C38 review

Best 96GB DDR5 Kit

The Trident Z5 RGB DDR5-6400 C32 is a fast-performing memory with generous capacity for professional users. Occupying just two memory slots, the memory kit is the ideal solution for compact workstations and enthusiast small-form-factor builds based around mini-ITX motherboards or simply conventional ATX motherboards that can only house two DIMMs.

G.Skill sells the memory kit for $339.99, a reasonable price for a 96GB memory kit of this caliber. Cheaper options are available on the current market, but they typically run at lower frequencies and don't deliver the same level of performance as the Trident Z5 RGB DDR5-6400 C32.

Read: G.Skill Trident Z5 RGB DDR5-6400 C32 review

Best 32GB DDR5-4800 Kit

The Samsung DDR5-4800 C40 memory kit targets consumers who want to stick to the JEDEC baseline speed. The memory modules don't look pretty but have shown excellent overclocking headroom. There's a good potential to hit breakneck speeds with tight timings. The B-die ICs will help you push the memory modules. Our sample got to DDR5-5800 C36 easily. However, there is no guarantee overclock, so this memory kit belongs to the high-risk, high-reward category.

The memory modules sell for $54.50. That's the consumer pricing, of course, not the IC pricing. As a result, a two-DIMM configuration will set you back $109, so it's not a bad price if you want to run JEDEC speeds. The Samsung DDR5-4800 C40 memory kit can be your ticket into the B-die overclocking world.

Read: Samsung DDR5-4800 C40 review

Best 16GB Kit For Ryzen Owners

TeamGroup did a great job with the Xtreem ARGB DDR4-3600 C14 memory kit -- It certainly ticks all the right boxes. The memory kit looks fantastic and performs equally well when lit up or powered down. The Xtreem ARGB is the fastest DDR4-3600 C14 memory kit we've tested.

The memory market only has a handful of DDR4-3600 C14 memory kits at the 16GB (2x8GB) capacity. The Xtreem ARGB is the least expensive, at $169.99. So, our only gripe is its availability. Unfortunately, Newegg is the only retailer that lists the memory kit, so finding it could be challenging.

Read: TeamGroup T-Force Xtreem ARGB DDR4-3600 review

Best High-Speed 16GB Kit

For those with a board that can handle its top speed and games or workloads that can take advantage of it, Patriot’s Viper Steel DDR4-4400 16GB kit is an excellent high-performance option that also skips RGB.

Keeping the kit simple has allowed Patriot to equip the Viper Steel with enhanced timings that dramatically boost the performance of specific programs, including some games. The Viper Steel DDR4-4400 excels in a market filled with gaming rigs and builds focused on singular tasks.

Read: Patriot Viper Steel DDR4-4000 review

Best High-Speed RGB 16GB Kit

Patriot bucks the trend of pairing cosmetic features with mainstream DRAM ICs instead of pushing data rates up to 4,133 megahertz (MHz) on its Viper RGB. As a result, this DDR4-3600 kit is only $10 more than the white-LED version and several dollars cheaper than competing products with similar latency. That makes it a great value at this speed, though slower kits have more significant pricing advantages.

The fastest DDR4-3600 kit we’ve tested, Patriot’s Viper RGB DDR4-3600 kit, provides excellent value to buyers who want to go (overclocking capability) and show (RGB LEDs).

Read: Patriot Viper RGB DDR4-3600 review

Best Overclocker Value 16GB Kit

It may not have fancy software-controlled RGB lights, and faster kits are available for higher prices, as are budget-priced kits that cost less. But for many who don’t want or need their memory to glow like a rainbow, Patriot’s Viper 4 DDR4-3400 C16 16GB (PV416G340C6K) sits in a sweet spot of price and performance.

The kit includes two 8GB modules rated with XMP values of DDR4-3400 CAS 16-18-18-36. Those last three numbers aren’t great, but DDR3 lovers must remember that 16 cycles at a 3400 MHz data rate have the same latency time as eight cycles at 1700 MHz. So this kit has an excellent DRAM overclocking value and provides some stylish red heatsinks to ensure your memory looks good enough to show off in your windowed case.

Read: Patriot Viper 4 DDR4-3400 review

Best 32GB RGB Kit

Builders who prioritize aesthetics face a tough choice between the best-looking and best-performance parts. Corsair offers a bit of both in its Vengeance RGB DDR4-3200 kit, providing four 8GB DIMMs (32GB total) at CAS 16 timings for a reasonably moderate price, given recent market trends. And this kit isn’t all about looks; it has the goods where benchmarks are concerned, too.

Superb performance and moderate pricing earn the Vengeance RGB Pro DDR4-3200 our Editor’s Choice Award for RGB-equipped memory, though its pastel colors might be off-putting to a few builders.

Corsair’s kit beat our previous favorite, the HyperX Predator RGB, in overall performance at every speed, barring the DDR4-4000 setting it didn’t reach. Corsair also provides a better-performing XMP value and a lower price than the competition, making the Vengeance RGB Pro the uncompromised winner and an excellent addition to your next RGB build.

Read: Corsair Vengeance RGB Pro DDR4-3200 review

Best Two-DIMM 32GB Kit

Buyers in the performance PC market have only two excuses for stopping at DDR4-3200: Either they’re trying to save money or coax good performance from a system that can’t go much farther.

For those in either category, but the former in particular, Patriot Patriot’s 32GB Viper Steel 3200 kit outshines the competition in terms of pricing price, beating its closest competition by approximately 18%. That’s without any performance penalties beyond having the exact mid-market timings as its competitors.

Even though the Patriot Viper Steel’s performance victories are less than 1% overall, its low price puts it well ahead of even the least-expensive competitor in our basic performance-to-price comparison. As a result, value seekers within the performance PC market have just found their new champion.

Read: Patriot Viper Steel DDR4-3200 review

Best Two-DIMM 64GB Kit

The Viper Steel DDR4-3600 C18 is a terrific memory kit for content creators or professionals who don't have the luxury of many DDR4 memory slots. Performance isn't a problem because the memory kit excels at everything you throw at it.

Patriot practically binned these modules to the max, so overclocking headroom is almost non-existent, even if you're willing to go wild on the voltage. However, running the Viper Steel at the advertised frequency should be sufficient in most scenarios.

Patriot prices the Viper Steel DDR4-3600 C18 64GB memory kit very attractively. At $239.99, the memory kit is neither cheap nor expensive. Viper Steel finds itself right in the middle of the competition. Given that it stands tall in terms of performance, this kit is easy to recommend for those needing speed and density in a dual-DIMM scenario.

Read: Patriot Viper Steel DDR4-3600 C18 2x32GB review

Best High-Speed 32GB Kit for Manual Tuning

It's easy to write G.Skill's Trident Z Neo DDR4-3600 C16 kit off if you don't look beyond the published specifications. However, during our review, the RAM kit proved its performance and value in different workloads.

The real value is hidden below the heat spreader—the memory modules use Samsung B-die ICs. With patience and time, you can optimize the timings for better performance. As always, your overclocking mileage will vary, but we got our sample down to CL13.

The Trident Z Neo memory modules come with XMP timings of 16-16-16-36, which aren't the worst in the memory world. However, with the DRAM voltage set to 1.45V, we tightened the timings to 13-14-14-35 before the kit became unstable.

Read: G.Skill Trident Z Neo DDR4-3600 C16 2x16GB review

Best 16GB Kit for H370 and B360

Intel’s H370 and B360 chipsets instruct its Core i5 (and above) processors to lock out any memory settings above DDR4-2666, which is particularly unfortunate in a market that’s moved way past that setting. DDR4-3200 is now mainstream within the enthusiast PC market and is often treated as such by the memory sellers that cater to enthusiasts and gamers. Thus, the best way to get a top-performing brand-new DDR4-2666 kit would be to dial the way-back machine to 2016 and get the high-performing equipment from that time. Barring that, Corsair has a workaround.

Corsair’s easy workaround for the performance problem of Intel’s DDR4-2666 limit was to use older, low-density chips to populate its 8GB DIMMs with two ranks rather than the single rank of its competitors. The best part is that they did this without a significant price increase. We recommend it for anyone whose XMP-compatible platform has a maximum DDR4-2666 data rate, including most retail boxed H370 and B360 motherboards.

Read: Corsair Vengeance LPX DDR4-2666 review

Quick RAM Shopping Tips 2026

Savings on the Best RAM

Whether you're buying DIMMs that made our list of the best RAM or not, you may find savings by checking out our lists of Newegg promo and Corsair coupon codes.

Kioxia and its research and manufacturing partner Western Digital plan to reveal their innovations that will enable higher-capacity and higher-performance 3D NAND memory devices at the upcoming 2023 Symposium on VLSI Technology and Circuits. Engineers from the two companies are looking to enable 8-plane 3D NAND devices as well as 3D NAND ICs with over 300 word-lines, reports eeNewsEurope.

Eight-Plane 3D NAND: Up to 205 MB/s

As 3D NAND devices increase the number of word-lines, shrink dimensions of NAND cells, and amplify the capacity of memory ICs, it becomes crucial to increase their read/write performance. Actual devices like the best SSDs, laptops, and smartphones tend to use fewer chips for a given capacity, but end users expect their new devices to be faster than their old ones.

One of the ways to improve performance of a 3D NAND IC is to increase the number of planes and enhance its internal parallelism. Kioxia will present a paper (C2-1) covering an eight-plane 1Tb 3D TLC NAND device with over 210 active layers and a 3.2 GT/s interface. The IC closely resembles Kioxia's/Western Digital's 218-layer 1Tb 3D TLC NAND device with a 17Gb/mm^2 density and a 3.2 GT/s I/O bus introduced in late March, but this one features eight planes instead of four and is said to offer 205 MB/s program throughput as well as a read latency of 40  μs. That latter spec is significantly better than the 56 μs offered by Kioxia's 128-layer 3D NAND.

The new paper reveals that Kioxia's 1Tb 3D TLC NAND device achieved its 3.2 GT/s interface speed by reducing the data query area in the X direction to 41%, allowing faster data transfer between memory and host. However, this new design can lead to wiring congestion, which Kioxia mitigated by introducing hybrid row address decoders (X-DEC). X-DECs help manage increased wiring density effectively, minimizing the degradation in read latency that could result from congestion.

Kioxia also implemented a one-pulse-two-strobe technique that allows for two memory cells to be sensed within a single pulse, reducing overall sensing time by 18% and increasing program throughput to 205 MB/s. The device's novel eight-plane architecture, one-pulse-two-strobe method, and 3.2 GT/s I/O allow for a read latency of 40 μs and a program throughput of 205 MB/s.

It's likely that the 1Tb 3D TLC NAND device already implements hybrid row address decoders and the one-pulse-two-strobe technique for its speedy interface, and these technologies will likely be widely used in the future. However, implementing an eight-plane architecture increases the complexity of both the 3D NAND IC and supporting memory controller, leading to higher development and manufacturing costs as well as longer time-to-market. Additionally, if the host controller cannot properly manage an eight-plane device, the actual performance of the IC may decrease.

>300-Layer 3D NAND

Besides investigating eight-plane 3D NAND IC device structures, Kioxia and Western Digital are also collaborating to develop 3D NAND devices with over 300 active word layers, which would enhance vertical channel length and boost the channel's crystalline quality.

To achieve this, the companies plan to employ Metal Induced Lateral Crystallization (MILC) techniques, as stated in the T7-1 paper. By utilizing MILC, developers were able to create single-crystallized 14-micron-long 'macaroni-like' silicon (Si) channels inside vertical memory holes, although for a 112-layer prototype device.

This experimental 3D NAND IC is also reported to leverage a cutting-edge nickel gettering method for eliminating impurities and flaws from the silicon material, thus enhancing cell array performance. As a result, read noise is reduced by a minimum of 40%, and channel conductance is increased tenfold, all without sacrificing cell reliability.

>400-Layer 3D NAND

Currently, techniques like string stacking allow for the construction of 3D NAND with hundreds of active layers, but they are time-intensive. As a result, device manufacturers and wafer fab equipment producers are developing methods to increase the layer count by etching longer (deeper) vertical channels.

Tokyo Electron, an etching tools manufacturer, is set to present a paper (T3-2) detailing a method for rapidly drilling more than 10-micron (10 μm) vertical channels for 400-layer 3D NAND nodes without excessive energy consumption or the use of toxic substances.

According to Tokyo Electron, its High-Aspect-Ratio (HAR) dielectric etching technology employs a cryogenic wafer stage and new gas chemistry to create 10-micron-high channels with an "excellent" etching profile in just 33 minutes and with an 84% reduced carbon footprint.

Intel surprisingly posted a product change notice on January 6 that it had decided to discontinue its important Virtual Raid on CPU (VROC) technology that is popular with its data center Xeon chips, including the fourth-gen Xeon models that launched last week. The feature is also present on some of Intel's consumer-focused Core models. Last week we reached out to Intel for details about the unexpected change, and today we're told the notice was posted prematurely.

“The PCN was prematurely posted while the decision was under evaluation. After discussing with the ecosystem and customers we realize there is significant demand for this product and intend to continue to support it.” — Intel Spokesperson to Tom's Hardware.

The VROC functionality is activated via different types of physical RAID keys that plug into the motherboard, each enabling a different level of RAID support. The keys cost between $100 for basic functionality to $250 for the full-featured model. Intel also offered these keys for consumer systems for some time, but they didn't gain much traction. 

Surprisingly, Intel originally posted January 23, 2023, as the last order date for the products. That's a mere 17 days after the initial posting that announced that "all support for VROC (Virtual Raid on CPU) software will be discontinued." Now we've learned that won't be the case.

This isn't the first time the company has issued a product notice in error — with a product stack as broad as Intel's, mistakes are bound to happen. Much like when the company put out a notice that its consumer chips were dying from a bus degradation issue, but later moonwalked the statement back to say the notice was in error.

The VROC feature debuted in 2017 to simplify and reduce the cost of high-performance storage arrays, and it has enjoyed broad uptake in enterprise applications. The feature brings NVMe RAID functionality on-die to the CPU for SSD storage devices, thus providing many of the performance, redundancy, bootability, manageability, and serviceability benefits that were previously only accessible with an additional device, like a RAID card or HBA. Thus, VROC gives users a host of high-performance storage features without the added cost, power consumption, heat, and complexity of another component, like a RAID card or HBA, in the chassis — not to mention extra cabling.

Pat Gelsinger's shift to focusing on the company's core competency — logic chips — has seen the company stepping away from several of its 'adjacencies,' like its storage business. It's unclear if the uncertainty that formed around the VROC tech stems from Intel's sale of its storage business to SK hynix, which also contributed to the company ceasing further development of its Optane-based products as it sells off its remaining inventory. Intel designed its VROC software to also work in tandem with its own storage products, so it's possible that the groups responsible for this software were within the storage organization that is headed to SK hynix as part of the sale.

In either case, users and OEMs alike have nothing to worry about, as Intel has decided to continue supporting the VROC feature. As such, the company has removed the original cancellation notice.

Every PC owner needs at least one USB hub to add ports, put connections within easy reach, or supply more power for charging / operation than your computer delivers on its own. One glance at the USB hub listings on Amazon will tell you that the market is full of choices, from tiny portable hubs that you can stash in a small pocket of your bag to large, powered hubs you'll want to keep on your desk.

Though there are plenty of choices, not all of them rank as the best USB hubs, and not all will meet your needs. To help you choose, we've tested more than dozens of models with different capabilities and listed the very best USB hubs on this page. We've also got some tips for picking the right type of USB hub, which you'll find below our product picks.

To find the best USB hub for your needs, consider the following:

Best USB Hubs You Can Buy Today

Best Desktop USB Hub

Getting a desktop USB hub like the Sabrent HB-B7C3 will change your tech life, both because of the amount of ports it has and because you can turn each one on and off. Sabrent's powered hub has a whopping ten USB Type-A ports, seven of which can do data transfer with the remaining three serving as changing ports only, capable of delivering more wattage to juice your phone, headset or tablet.

Each USB port has its own dedicated power button and, unlike with some competitors we tested, Sabrent's port buttons depress quickly, and have solid mechanical switches that make a pleasant clicky noise and stay in the up or down position. There's also a cool-looking blue status light to let you know whether a port is on or off.

I have been using the Sabrent HB-BUP7, the nearly-identical 7-port sibling to the HB-B7C3, as my daily driver for more than a year, and having these buttons is a real game changer. Changing default audio devices in Windows is a royal pain, requiring one to go into the control panel to, for example, make sound come out of your headset instead of your speakers. But with the power switches, I just turn off my USB speaker and turn on the wireless headphone dongle, or vice versa.

Anyone who works with microcontrollers such as the Raspberry Pi Pico or any Arduino board knows that most of these devices don't have on / off switches or even reset buttons. So, if you change code and need to restart them or you just want to power them off, you often need to yank the plug in and out, a huge hassle that could damage your gear. But with the Sabrent HB-B7C3, you can just toggle power on whatever port your microcontroller is plugged into.

The build quality on Sabrent's 10-port USB hub is the best we've seen on any hub we've tested. The clean lines, compact shape and tasteful lights and buttons make this look like a truly premium product. Having seven different data ports means that you can have all of your peripherals plugged in – your mouse, keyboard, webcam, microphone, 2FA key, speakers and headphones – and still have a port or two to spare.

The hub is powered by a massive 60-watt power adapter that looks like a laptop brick (we wish it were smaller). Sabrent boasts that the 3 charging ports deliver 2.4 amps of power while the data ports max out at 0.9 amps. As we found out when we we plugged our power load tester into the ports, both the charging and data ports are capable of delivering as much as 3.8 or 4.9 amps but only if you drop the voltage down to 4.05 volts (on all USB chargers, the volts go down if you request too many amps).

At 4.8 volts, which is around the minimum voltage most USB devices will tolerate, we got 1.25 and 1.32 amps from the charging and data ports, respectively. When I plugged my Android phone in to charge, a real-world situation because a device will negotiate the best combination of volts and amps, the charging ports sent 4.78 volts at 1.35 amps while the data ports gave the same amount of volts, but just 0.35 amps. To make a long story short, you'll get 6.4 watts from the charging ports, which is decent but not the 15-watts that fast phone chargers provide. All three charging ports should be able to deliver this at once.

All of the HB-B7C3's data ports operate at 5 Gbps and, in our tests, there was no drop off in speed from transferring data from our external SSD through the hub (versus directly connected to the PC). The 2-foot detachable upstream cable is helpful but we need an extension cable to reach all the way to the back of our desktop PC.

At $44 at press time, the Sabrent HB-B7C3 doesn't come cheap, but it's definitely worth the price. If you don't need the charging ports, you can save a little cash and desk space with the 7-port, Sabrent HB-BUP7 ($38 at press time), which also has a smaller power adapter. You can also splurge for the Sabrent HB-BU10 ($60 at press time), which has 10 data ports and no charging ports.

Best Premium USB Hub for MacBooks and Ultrabooks

All MacBooks and many of the best Ultrabooks come with only USB-C ports, and just a couple of them. That’s why there are so many portable USB hubs that connect to a computer via a built-in USB-C cable and then provide a few Type-A ports, along with some extra goodies such as an HDMI out or a card reader. Plugable's 9-in-1 USB-C Hub fixes that, by adding 4K HDMI, 140W pass-through charging, Gigabit Ethernet, four USB-data ports, and both SD and microSD card readers.

The pass-though charging port means, so long as you provide your own USB-C charger, you can power your laptop and other devices though the hub with one cable – a handy feature when you're on the go and don't have a lot of desk space. Similarly, the Pluggable hub's narrow design with the ports all on one side helps save space while keeping things tidy. And its metal shell feels like it can hold up to life on the road, frequently being tossed in a bag as you rush to your gate.

On our testing, copying a 50 GB test folder, we saw 621 MBps write speeds and read speeds of 830 MBps. Just keep in mind that file transfers will be slower if you have multiple bandwidth-heavy devices connected to the hub, as the upstream port is 10 Gbps. If you're frequently moving large files across storage devices and speed is important, you'll want a dock with a Thunderbolt 4 or USB4 upstream port for more bandwidth.

While the Plugable 9-in-1 hub delivers most of the ports you're likely to need without stepping up to something larger and pricier (typically a proper dock), its single 10 Gbps USB-C data port may be limiting as more and more modern devices connect over the newer interface. I'd love to see another USB-C data port here, because the second Type-C port on this hub is strictly for power passthrough.

Best USB Hub for iPads

Sometimes you just need a few extra USB Type-A ports on your laptop or desktop and you don’t want something that takes up a lot of space in your bag or on your table. At just 0.39 inches thick and 3.68 inches long, Anker’s 4-port Ultra Slim is very discrete. The hub has a built-in, 2-foot cable that’s long enough for any portable use, though you may want to use the attached hook and loop cable tie to keep it from getting tangled.

The Anker 4-Port Ultra Slim, as its name suggests, has four USB 3.x Type-A outputs and a single built-in Type-A upstream cable. As with every other hub on this list, we tested the Ultra Slim and found that it did not have any effect on transfer rates, providing our external SSD the same read and write speeds it got when connected directly to our laptop.

Though it has a very reasonable price ($12.99 at press time), Anker’s hub seems to have very solid build quality compared to some competitors, with a hard matte black plastic shell that shows no obvious seams and an attractive blue power light, though the casing got a little scratched as we carried it around. The Anker hub’s premium design stands in stark contrast to another cheap hub we tested, the Atolla USB 3.0 Hub Splitter, which has a glossy plastic shell with a line down the middle where two pieces of plastic were clearly glued or snapped together (and I fear could come apart some day).

Best USB-C Hub, Best Affordable USB Hub for MacBooks

Sabrent's HB-U3CR looks like it was built for MacBooks, thanks to a gunmetal gray aluminum chassis and a stylish, slanted design that will prop it up at an insertion-friendly angle on any table. However, it's an equally strong choice for use with a PC laptop that has USB-C ports and needs a few USB Type-A connections.

The HB-U3CR's small size and built-in cable make it easy to throw into your laptop bag, but a magnetic sticker that comes with it allows you to set up a permanent spot on your desk where you can attach and detach it, without fear of it falling over when you tug on the wire. It has three USB Type-A 3.x (5 Gbps) ports and a card reader that supports both microSD and SD cards, a boon for folks who are either using a digital camera or working with Raspberry Pis (which use microSD cards as their boot drives).

On our tests, the Sabrent HUB-U3 did not introduce any lag into file transfers, which means it won't hurt your performance. However, like most USB hubs on the market, it is limited to 5 Gbps, so that’s the top speed even if you connect it to a thunderbolt port and 10 Gbps USB peripheral. The 2-foot, built-in USB cord is about standard for a portable hub, but could be too short if you plan to use it with a desktop PC that you keep on the floor or far from your peripherals.

Best 10 Gbps, Type-A USB Hub

If you're using an external storage device – perhaps an NVMe drive you've put in one of the best SSD enclosures – you’d benefit a great deal from using a hub that supports 10 Gbps connections – alternatively known as USB 3.1 Gen 2 or USB 3.2 Gen 2. Unfortunately, very few USB hubs actually support these higher speeds and even fewer still support the 10 Gbps speed when it comes from a Type-A, rather than a Type-C, port.

The Inatek HB2025AL gives you four USB Type-A 10 Gbps output ports and one upstream Type-A 10 Gbps connector that's on a built-in cable. Considering that few laptops have USB Type-A ports that support 10 Gbps and few desktops have 10 Gbps Type-A ports on the front panel, you're probably going to be plugging this into the back of your motherboard. The model we tested was actually the HB2025A, which has a 1.6-foot cable, but we're recommending you spend an extra dollar or two to get the HB2025AL which has a 3.3-foot cable instead. Even 3.3 feet could be short if you're working with a desktop that’s on the floor.

You can also get other versions of Inatek's USB hub, the HB2025 for example, that connect to your computer via USB-C, which is a more common interface for 10 Gbps connections, particularly on laptops. We really wish one of these hubs had a mix of USB-C and USB Type-A downstream ports, but they are all Type-A downstream.

No matter what version of Inatek's hub you choose, the 10 Gbps connection is very welcome if you're working with external drives. Our test laptop did not have a USB Type-A 10 Gbps port so we connected the hub to a port on the back of our desktop and got read-and-write transfer rates of 684.7 and 492 MBps on our DiskBench 25GB test. By way of comparison, we got rates of 358.1 and 274.8 MBps when connected to a standard 5 Gbps port on our laptop, so the 10 Gbps speed makes quite a bit of difference.

Best USB-C expansion hub

While many new devices have shifted to using USB-C over the older USB-A standard for connectivity, the USB-C port count hasn't exactly kept up, whether you're using a laptop with a couple of the oval connectors or a desktop, which at most likely has two around back, plus one on the front panel. The Mokin 5-IN-1 10 Gbps USB-C to USB-C Hub solves the USB-C scarcity issue by turning one of those ports into four – or technically five.

The slim metal-wrapped hub has four USB-C ports running down one side, all running at up to 10 GBps. One of the ports is labeled for monitors and supports 4K, 60 Hz via DisplayPort over USB-C. A fifth USB-C port lives on the end of the hub, supporting up to 100W of power delivery (if you bring your own charger). This lets you push up to 85W to your laptop, while the rest is used to juice devices plugged into the hub.

As with all multi-port 10 Gbps hubs, your bandwidth is going to be limited by the upstream capabilities. So don't expect to connect multiple fast storage devices and expect them all to run at full speed. But if you need more USB-C ports to connect peripheral dongles or other accessories, the Mokin hub is a great option to ease your USB-C port anxiety, without spending a lot of money. It's often on sale for less than $30.

Just know that you'll need to connect to a power source via the port on the end for higher-drain devices. This hub often disconnected when plugged into my desktop's front-panel USB-C port and running an external SSD. But when connected to the ports on the back of my PC or to a USB PD power source, I had no issues with the hub not performing as expected. I saw write speeds using a 50GB test folder of 689 MBps and read speeds of 612 MBps – this isn't the fastest 10 Gbps hub, but beyond benchmarks, it's speedy enough for mainstream tasks.

Best Cheap Power-Switching USB Hub

This is a budget-friendly alternative to Sabrent’s HB series of USB hubs as it has 7 USB 3.0 data ports you can turn on and off, along with one dedicated charging port, and costs a lot less ($21 at press time). However, Atolla definitely cut some corners to get it to this price.

The chassis looks kind of ugly with a cheap-looking shiny plastic that’s a fingerprint magnet. The power toggle buttons for each port are soft and require you to hold them down for a second or two to change their state, which is a step down from the clicky buttons on Sabrent’s hubs. Also, the USB cable is built-in, so you can’t replace it with a longer one.

Similar to the Sabrent HB-U3CR, the Atolla delivered 1.2 amps at 4.8 volts on our power test and it charged our phone at 4.78 volts and 1.35 watts. The Atolla hub also offered similar performance to other hubs; we detected no slowdowns when copying files with our test SSD.

How We Test USB Hubs

When it comes to USB hubs, most of the time, the specs don’t lie. If you see a hub that has USB 3.x (USB 3.0 or USB 3.2 Gen 1) ports, those ports should operate at the same exact speed as connecting a device directly to a USB 3 port on your computer. To find out if any of the hubs we tested created a data bottleneck, we hooked up a 10 Gbps external SSD to the hub, which we connected to a laptop. We then used DiskBench to copy a 25GB folder both to and from the disk and compared the numbers to those we got when connecting the disk directly to the laptop.

In all cases but one, there was no change in performance from using a hub. Using the 5 Gbps interface on most USB hubs and on our laptop, we got read transfer rates of 355 to 360 MBps and write transfer rates of 273 to 285 MBps. The exact numbers could vary from one run to the next so there is no point in listing the results from each hub — they are all within the margin of error of each other. Only one hub, the Sabrent HB-UMP3, showed a slowdown in its write speed, dropping down to 179.5 MBps, about a 35 percent reduction in speed.

We also did power testing on every powered USB hub. To see just how much electricity the ports could deliver, we connected a load tester to the hub and tried to dial up as many amps as we could. As we dial up amps on any device, the voltage drops, so a 5 volt USB port could drop down to 4 volts or less as we increase the load, but typical USB devices need close to 5 volts – 4.7 or 4.8 volts is usually enough – so we tested how many amps we could get at 4.8 volts and at the, likely unacceptable, rate of 4.05 volts.

We also connected an Android phone to the ports and recorded how many volts and amps it received. The phone charging test was probably the most realistic, as it showed what kind of volts and amps a real device would negotiate with the hub.

Other USB Hubs We Tested

Not every USB Hub is one of the best USB hubs you can buy. We tested a number of other models that are worth considering, but not necessarily at the head of the class.

• Sabrent HB-BUP7 (7 ports, powered)
  We love this hub and it’s my personal daily driver. This is the 7-port version of the 10-port Sabrent HB-U3CR we recommend and, for some folks, a better choice because it’s more compact. However, at press time, it was only $6 cheaper than the 10-port model with charging ports, so the HB-U3CR gets the nod for giving you three charging ports for only a little more cash.
• Sabrent HB-U3CR
  This is the 4-port version of Sabrent’s awesome line of power-switch enabled, powered USB hubs. It’s dirt cheap at just $16, but it’s the only USB hub we tested that actually bottlenecked performance, cutting about 35 percent off the write speed of our external SSD. We also don’t like the layout of the ports on this as well as on its larger siblings. However, if you’re not overly concerned with performance, this is a good buy.
• JoyReken FlyingVHUB
  This is a standard, bus-powered 4-port USB Type-A 3.0 hub with a built-in USB Type-A upstream cable. The main twist here is that the hub is pyramid shaped and has a little RGB light in the shape of a V in the middle. You can change the color pattern a little by hitting a button, and there's a USB-C port on the back that appears to do nothing (it gave power to a device, but didn't send data).
• Ugreen USB-C 4-port Hub
  At $14.99 (and on sale at press time), this a solid choice for MacBook owners or anyone who needs a cheap, portable hub that has a USB-C upstream connector and four down-stream Type-A ports. It even has a USB-C power pass-through you can use for charging your laptop.
• Atolla USB 3.0 Hub Splitter
  Available for less than $10 at press time, this portable USB hub is a good value with an interesting twist. The Atolla has a single, built-in Type-A cable to connect to your laptop, along with four Type-A USB 3.x ports for output. Each of its four downstream ports has an on / off switch, which is something we love on powered, desktop hubs but is less necessary on a portable hub where you're not leaving things plugged in for long periods. The 6-inch, built-in upstream cable is too short for a lot of people.

Discounts on the Best USB Hubs

Whether you're shopping for one of the best gaming laptops or another model that didn't quite make our list, you may find some savings by checking out our lists of Dell coupon codes, HP coupon codes, Lenovo coupon codes, Razer promo codes or Newegg promo codes.

Tom's Hardware USB Hub Coverage

Best Flash Drives | Best External SSDs | External SSD reviews | USB 2.0 Turns 25 | All USB news | Best Gaming Keyboards | Best Budget Mechanical Keyboards | Best Wireless Mouse | Best Gaming Mice | Best Peripheral Deals

AMD representatives made an unexpected reveal today on the company's Meet the Experts webinar: AMD is working to bring CXL memory technology to its consumer CPUs over the next three to five years. This would bring persistent memory devices, like SSDs, onto the memory bus to improve performance. Compute eXpress Link (CXL) enables improved performance, lower latency, and memory expansion capabilities by bringing remote memory devices into the same pool with system DRAM. Think of it as enabling you to expand your memory by plugging in an SSD or more memory onto a device that slots into your PCIe or M.2 port.

Unlike Optane, which Intel is killing off due to poor adoption, CXL already enjoys broad industry support through an open protocol and can support many types of memories. In fact, AMD and Intel, among many others, are working together on the new specification.

The Meet the Experts show covered a diverse range of topics, including AMD's AM5 platform, DDR5 memory, and PCIe 5.0 SSDs. The host then opened the floor to questions. In response to the question of why storage devices aren't connected to the memory bus, AMD's Senior Developer Manager Leah Schoeb explained that persistent memories (like SSDs) and memory currently communicate with different protocols, preventing communication. 

"[...]It's not that in the future, we won't be bridging that communication. That's something that we're looking at with technologies such as CXL. So you'll find over the next, you know, three to five years, you'll see it first in the server area, but you'll find moving down into the client [consumer] area, ways that we can make sure that memory and storage can communicate on the same bus through CXL."

The host asked Phison's Senior Manager of Technical Marketing, Chris Ramseyer, if the company had any more to add to the topic.

"Well, to be honest, I'm on calls about this. Some of those are with Leah. I'm not sure how much I can really give out. We haven't announced anything in this area. But I can say that there is progress being made. And, again, this will be another ecosystem-type project, where it's not just going to be Phison and not just AMD putting this together. We're all going to have to work together to do this, and these collaborations have really advanced PCs over the last few years[...]," he commented.

As a reminder, the CXL spec is an open industry standard that provides a cache coherent interconnect between CPUs and accelerators, like GPUs, smart I/O devices, DPUs, and various flavors of DDR4/DDR5 and persistent memories. The interconnect allows the CPU to work on the same memory regions as the connected devices, thus improving performance and power efficiency while reducing software complexity and data movement.

However, the protocol requires dedicated silicon in both the host CPU and the connected device to function, like memory, persistent memory, GPU, or other accelerators. That requires the feature to be baked into the chip, and as with any new technology, CXL will take some time to mature.

The first CXL-capable processors are right around the corner, though: Intel's Sapphire Rapids and AMD's EPYC Genoa will come with early revisions of the specification built around the PCIe 5.0 interface. New revisions of the CXL spec still under development will support PCIe 6.0 and more sophisticated capabilities, like memory sharing and pooling. AMD will reveal its EPYC Genoa server chips in a live stream on November 10, while Sapphire Rapids is expected to arrive early next year, so CXL technology is on the cusp of real-world use.

AMD's disclosure today doesn't give us a specific date or chip generation for CXL support in consumer CPUs, but the three-to-five-year window mentioned suggests we could see it well after PCIe 6.0 devices, which debut in the 2024 timeframe.

Manli has introduced the industry's first Nvidia GeForce RTX 3060 graphics card with only 8GB of memory. The new board has the same compute performance as fully-fledged GeForce RTX 3060 12GB product, but it cuts down the memory capacity and bus width, which in turn reduces memory bandwidth. All of those changes should have a tangible effect on performance.

Manli's GeForce RTX 3060 8GB GDDR6 graphics card (via VideoCardz) presumably uses the same GA106 graphics processing unit as the 12GB card. It comes with 3584 CUDA cores with a 1777 MHz boost clock, the same clocks as the reference RTX 3060 12GB.

Unlike the typical GeForce RTX 3060 12GB board that features a 192-bit memory bus with 360 GB/s peak memory bandwidth, the GeForce RTX 3060 8GB only features a 128-bit memory interface. That likewise cuts the peak memory by 33%, down to just 240 GB/s. In cases where memory bandwidth matters, the new board will end up being significantly slower than the existing GeForce RTX 3060 with 12GB of GDDR6 memory.

Other than the narrower memory bus, the GeForce RTX 3060 8GB has the same specs as the 12GB card. It comes with a 170W TBP (Total Board Power) rating, a dual-slot cooling system, and four display outputs (three DisplayPort 1.4, one HDMI 2.0).

Neither Manli nor Nvidia have given an MSRP on the new RTX 3060 8GB model, though since it should land between the GeForce RTX 3050 8GB ($249) and GeForce RTX 3060 12GB ($329), it will likely be priced accordingly. We expect other graphics card vendors will follow Manli shortly with their own variants of the RTX 3060 8GB.

The impetus behind the card appears to be a desire to offer something between the rather anemic GeForce RTX 3050 and the existing RTX 3060 12GB. The 3050 gets pummeled by AMD's RX 6600 as well as Intel's Arc A750, both in price as well as performance. However, while trimming the memory capacity may reduce the price relative to the 12GB card, it will also drop performance.

Our best guess is that Nvidia probably has loads of GA106 graphics processors, some of which may not have three fully functional 64-bit GDDR6 controllers but which still have nearly all of the potential 30 Streaming Multiprocessors (SMs) available. This looks like a way to try and bump up the price relative to the 3050 while providing a modest boost to performance.

Nvidia's goal will be to use any and all opportunities to sell off as many Ampere GPUs as it can in the next several months in a bid to clear the road for its next-generation GPUs based on the Ada Lovelace architecture. We can't help but think it would find more success if it cut prices, rather than trying to fill the gap between the existing 3050 8GB and 3060 12GB cards.

Micron has quietly started volume production of GDDR6X memory chips featuring a 24 GT/s data transfer rate. The new memory devices are expected to be used by some of Nvidia's upcoming high-end GeForce RTX 40-series graphics cards based on the Ada Lovelace architecture. 

Micron's new 24 GT/s GDDR6X chips have a capacity of 16Gb (2GB) and can be used to build graphics cards with loads of memory onboard (via @Harukaze5719). It is expected that these ICs will be used for Nvidia's GeForce RTX 4090 graphics card, carrying 24GB of GDDR6X memory connected to the GPU using a 384-bit memory bus (and therefore offering a peak memory bandwidth of 1.152 TBps, assuming that Nvidia will use memory at its highest rated speed). Other products from the lineup are rumored to use slower GDDR6X devices with an up to 21 GT/s data transfer rate. 

In addition, the 24 GT/s GDDR6X memory chips are projected to be used by Nvidia's next-generation flagship graphics board currently known as The Beast (sometimes referred to as the GeForce RTX 4090 Ti), which will carry 48GB of memory on both sides of the card (and will likely be the best graphics card available in terms of raw performance in the coming months).  

Nvidia is rumored to formally introduce its GeForce RTX 40-series 'Ada Lovelace' products this fall. Therefore, it is about time for Micron to kick off volume production of its next-generation GDDR6X memory chips with an up to 24 GT/s data transfer rate. 

Neither Nvidia nor Micron have officially commented about usage scenarios of 24 GT/s GDDR6X memory chips, so take unofficial information about Nvidia's GeForce RTX 40-series lineup with a grain of salt. Meanwhile, Micron is certainly starting production on this memory that will be used by one of its clients. At present, the only company to support GDDR6X is Nvidia. 

It is noteworthy that Samsung has been sampling its 24 GT/s GDDR6 (not GDDR6X) memory chips since December, 2021. So Micron has some speedy competition. 

A PC bus, also referred to as "the bus," is the path on the PC's motherboard to transfer data to and from the CPU and other PC components or PCs. This includes communication between software. For example, a PCIe (peripheral component interconnect express) expansion card, such as a graphics card (aka GPU aka video card), will send data to and from the PCIe bus. 

There are numerous types of buses to accommodate different technologies. Below is a list of standard computer buses:

• eSATA (External SerialATA) - for transferring data between external hard drives and disk drives
• PCIe - for accessing PCIe expansion cards and certain M.2 SSDs 
• SATA (Serial ATA) - for accessing internal storage drives. Slower than PCIe 
• Thunderbolt - for accessing peripherals
• USB - for accessing peripherals

This article is part of the Tom's Hardware Glossary.

Further reading:

• Dissecting the Modern Motherboard: Connectors, Ports & Chipsets Explained
• How to Buy the Right CPU
• Best Gaming CPUs
• Best (Non-Gaming) Performance CPUs

Now is a good time to be in the market for a small-form-factor PC, it seems, as Zotac is at it again. Once again via the redoubtable Liliputing, news reaches us of the ZBOX QTG7A4500, a tiny pro workstation just 8 inches square that houses an
Nvidia RTX A4500 GPU with 16GB of GDDR6 memory and an eight-core i7.

That CPU is the i7-11800H, which pulls 45W and chews through 16 threads. Aimed at video editors and rendering enthusiasts rather than gamers, thanks to the presence of that A-series GPU, it’s good for pushing four displays thanks to the combination of two HDMI 2.1 and two DisplayPort 1.4a outputs. The GPU is an Ampere model, combining 56 second-generation RT Cores, 224 third-generation Tensor Cores, and 7,168 CUDA cores. It usually ships with 20 GB of graphics memory, connected via a 320-bit bus, but you’re only losing 4GB in this configuration.

RAM goes in two SODIMM slots that can support up to 64GB of DDR4-3200, and there's a PCIe 4.0 x4 M.2 socket, plus a PCIe 3.0 x4 slot for fast storage or Optane memory. The front of the unit boasts a single Thunderbolt 4 port, while every other USB port, front and back, is of the Type-A USB 3.1 Gen 2 sort. There are two Ethernet sockets, one Gigabit and the other 2.5Gbps, and you get an SD card slot, too. There's also Wi-Fi 6 and Bluetooth 5, with two antennas screwing into ports on the back of the case, and power comes from an external brick.

Performance should be high with specs like those, so we hope the cooling will be up to it. A fan and heatsink are specified, but the only illustration shows a duct designed to evacuate the hot air out of the side of the case. There are vents on every side apart from the front, but it might be a good idea not to box the QTG7A4500 in too tightly. We'd have loved to see a 12th-gen chip in there, as SFF designs benefit from the mix of power and efficiency cores, but the 11th-gen is a proven design that should rip through the kind of work this PC is aimed at.

There are no details about the release date or pricing at the time of writing, but a previous-generation ZBOX with an RTX 3070 is selling for just over $2,100 on Amazon.

The Intel 8086, from 1978, is a little lacking in horsepower by today’s standards, being a 16-bit chip running at up to 10 MHz. That hasn’t stopped Canada based engineer Robin Grosset, however, who’s found a way to attach one to a Raspberry Pi.

Formerly of IBM, and now CTO of AI firm MindBridge, Grosset knows his way around a chip or two. The Raspberry Pi 4 acts as a data bus, toggling the clock, dealing with the CPU’s requests, and providing read and write to memory and the I/O, allowing the 8086 chip to run MS-DOS. The chip receives power from the 3.3V pin on the Pi’s GPIO array - which it’s connected to directly - meaning not all 8086 processors will work, as the different models require anything from 3V to 7V. 

The chip in question is actually a clone, the NEC V30, pin compatible with the original Intel 8086 and used in the Psion Series 3 PDA from 1991 and the Wonderswan games console. The code also works with the Intel 8088, a variant of the 8086 with an 8-bit data bus. At the moment, the 8086 is only running at around 0.3MHz, slow even by 1978 standards, but its memory and disk drives are fast as they’re provided by the Pi. 

"This is a work in progress and just a bit of fun,” Grosset told us. “The original project was created by Elijah Miller. I got interested in it because it's a CPU connected directly to the Raspberry Pi header, which I thought was pretty crazy. This is made possible with no other supporting interface chips, just direct wiring links."

Grosset has also been working on a Raspberry Pi Zero 2 W powered "pi6502" which was made while waiting on parts for his 8086 build. “While I was waiting for my 8086 CPUs to arrive I tested out a 6502 CPU, and with some tweaks was able to achieve 2.6Mhz. That code is here and implements a really fast Apple 1,” he continues.

“For me this is interesting because you have to figure out the bus timing of the CPU chips, and you get to understand what the processor is doing at a very detailed level. The challenge to get this to a run at full speed is in both timing issues of the CPU, and also creating really efficient code to run the GPIOs.”

Grosset’s code for the 8086 HAT, including the C library he wrote for interfacing, is all available on GitHub, should you have an 8086 of your own and a hankering for MS-DOS. There are alternatives, however.

We’re big fans of the Raspberry Pi Compute Module 4 (CM4). The inclusion of a PCIe slot opened up a world of possibilities (which Jeff Geerling is exploring) but what if you want say, four PCIe slots? Happily, Waveshare has decided to do something about this as it releases the PCIe-Packet-Switch-4P, brought to our attention by CNX-Software, that uses an ASMedia ASM1184e PCIe switch to connect four devices to the CM4’s single-lane PCIe Gen 2 interface.

Admittedly, that’s not going to get you to typical GPU speeds, and may be further limited, as the Chinese-language wiki that accompanies the board states the bandwidth is 500Mbps, which seems to be missing a zero and may be a mistake.

The IO carrier board measures just 3.2in x 1.5 inches (82 x 39mm) and needs a 12v power supply. This can come via the PCIe bus, or through a DC jack. If no 12v can be found, a 5v supply can be substituted, but the board comes with warnings that this will flow back to the 12v rail, and precautions need to be taken to ensure the correct functioning of the board under these conditions. The documentation has no elaboration on how to do this but we can see what looks like a "floppy drive" power connector which supports 12v and 5v on the underside of the board.

The PCIe-Packet-Switch-4P is an add-on board that connects to a Compute Module 4 IO carrier board that already has a single Mini PCIe slot exposed. The board slots into the Mini PCIe slot, held in place with brass standoffs. It is also compatible with other Mini PCIe enabled carrier boards such as that on Waveguide’s own CM4 carrier board, which adds HDMI, Ethernet, USB ports, GPIO and three ribbon cable connectors.

Cards that work with Raspberry Pi over PCIe include USB 3 controllers, SSDs, SATA interfaces, Ethernet controllers, and even Creative’s Sound Blaster X-Fi Xtreme sound card. Pi tinkerer and friend of the Tom’s Hardware Pi Cast, Jeff Geerling, keeps a list of cards he’s tested at his site.

The Waveshare PCIe-Packet-Switch-4P currently sells in China for around $23. It isn’t currently available on the Waveshare English Store, but we’re hopeful it will make it to eager Raspberry Pi fans across the world.

Collectors of rare PC hardware have just missed out on the chance to own a little piece of history: a prototype Intel GPU claiming to be the only working Larabee board in the world. It sold on eBay France for a mere €4,650 ($5,234) and even came in a snazzy case.

Apparently fully working, a screenshot shows the BIOS startup, but without drivers, the Larrabee GPU is marked as an Intel engineering sample for internal use only. Exactly which truck it fell off to end up in the hands of the seller remains unknown, though we have no reason to doubt the bonafides of the vendor, who has a 100% feedback rating.

Larrabee was Intel's 2008-vintage attempt to make a GPU, or rather a GPGPU, separately from the project that led to Iris Pro. Rather than following in the footsteps of Nvidia and ATi, Larrabee used the X86 instruction set with special extensions, and the GPU functioned more like a hybrid of a CPU and GPU. In addition, it did a lot of its work in software rather than using specialized graphics hardware, using a tile-based rendering approach. The idea was to make a board that could accelerate more diverse workloads than 'just' games and achieve graphics effects that GPUs at the time couldn't manage, such as real-time ray-tracing and irregular shadow mapping.

Larrabee's processor was derived from Pentium designs, fitting 32 (or 24 in a cut-down version to use defective chips) in-order cores, each with four-way multithreading, onto a single chip. Each core had a 512-bit vector processing unit and used a 1,024bit (512bit bi-directional) bus to communicate with memory. It was speculated that 25 cores were enough to run Gears of War, an Xbox 360 game, without antialiasing.

Larrabee was general-purpose enough that, theoretically, the GPU could have run its own operating system. However, its graphics performance was poor compared to competing products, and the project was shelved as a GPU in 2009. Its GPGPU approach, however, is echoed today in things like Nvidia's CUDA, which opens up the power of the GPU's parallel processing to other applications.

The Larrabee technology passed to Intel's supercomputing division, which eventually built an accelerator card for high-performance computing released as Knights Corner, and the Xeon Phi co-processors, in 2012. They hung around until 2019 and were used in supercomputers, including Cori at the National Energy Research Scientific Computing Center, and China's Tianhe-2, which topped the list of the world's fastest supercomputers from June 2013 until November 2015.

Zotac today updated its ZBOX Mini PC. The new offering, the ZBOX Magnus, maintains the Small Form Factor (SFF) design philosophy of previous ZBOX products. Zotac is positioning the ZBOX Magnus for users aiming to tackle demanding creative workloads - but who also enjoy the latest AAA-games.

The ZBOX Maguns' small, 2.54 litre footprint, is sized at just 210mm (8.27in) length; 203mm (7.99in) width; and 62.2mm (2.45in) height. According to the company, "an improved and powerful cooling solution is backed by a full honeycomb ventilation on top, striking the perfect balance between power and thermals in the most compact form factor."

Inside that small footprint and bespoke cooling solution, the ZOTAC ZBOX Magnus (EN173080C) manages to cram in an Intel Core i7-11800H processor (8-core, 2.3 GHz, up to 4.6 GHz Turbo, 45 W TDP) with an Nvidia GeForce RTX 3080 mobile graphics card (packing a GA-104 chip with 6,144 CUDA cores and 16 GB of GDDR6 VRAM over a 256-bit bus, 150 W TDP). Obviously the mobility RTX 3080 brings lesser performance than a full, 8,704 CUDA-enabled RTX 3080 would. But in such a small enclosure, the added heat would likely turn into a problem relatively quickly, which is likely the reason why ZOTAC didn't opt for that GPU instead.

The Zotac ZBOX Magnus is available in either a barebones or Windows-ready model. The barebones option leaves the OS, memory and storage up to the user, while the non-barebones Windows (10 or 11) prebuilt can be configured with up to 64 GB of DDR4 memory across its two (2) DDR4-3200/2933 SO-DIMM slots. Storage expansions include a single 2,5" SATA 3 HDD/SSD bay and a pair of M.2 (2230/2242/2280) SSD slots, compatible with NVMe, SATA, or Intel Optane technologies.

When it comes to ports and connectors, the ZBOX offers a number of these in both its front panel:

•  3-in-1 card reader (SD/SDHC/SDXC) 
• Microphone input 
• 1 x Thunderbolt 4 
• 1 x USB 3.1 Gen 2 port 
• Power button and power LED 
• Wi-Fi LED, Hard drive LED

While the back panel also features a number of ports:

• 4 x USB 3.1 Gen 2 ports
• 1 x 10/100/1000 Ethernet
• 1 x Killer 10/100/1000/2500 Ethernet
• Dual Wi-Fi antenna connector

Only the Barebones version of the ZBOZ Magnus if for now listed on Zotac's website. No information on pricing or availability window for either products was made available at time of writing.

Giving an old system new life by installing more memory or a new storage device is one thing. But plugging a modern solid-state drive into an archaic 20-year-old Power Mac G4 requires a lot of hardware and software hacking, with the end result being questionably useful at best. Because clearly, a modern PCIe NVMe SSD that delivers gigabytes of throughput per second isn't going to deliver its best while running over a PCI bus with 133 MBps of bandwidth.  

Apple originally released its PowerMac G4 in 1999 and then launched its upgraded iterations till 2002. In other words, this desktop is outdated, to put it mildly. In addition to the ancient CPU and GPU, it lacks almost all modern interfaces. So it's nearly impossible to use any modern component with it without complications. But that didn't deter Pierre Dandumont from Journaldulapin.com. 

So what does Apple's early 2000s Power Mac G4 have to work with in terms of an interface? PCI. Not PCI Express, mind you, but a PCI slot that can be used to install various add-in-cards, such as graphics boards (yes, since the system is based on a Power processor, it lacks AGP as well). Meanwhile, there are PCI-to-PCIe adapter boards that let you install PCIe hardware into PCI slots, though with some caveats. 

Just plugging things in is not enough to make PCIe hardware work with a Power Mac G4. That system for obvious reasons does not support the NVMe protocol used by modern speedy SSDs. But it appears to support the AHCI protocol used by modern hard drives, some PCIe SSDs, and all SATA SSDs. The Power Mac G4 shipped with SCSI or Parallel ATA HDDs, and it looks like Apple used PATA controllers that support AHCI, but we are speculating here. This AHCI support enables the use of PCIe SSDs that use this protocol, such as Samsung's SM951. 

Yet even picking up the right SSD is not enough to make a relatively new drive work in a Power Mac G4 PC that's roughly 20 years old. In a bid to make the drive bootable, a different BIOS (or Open Firmware in this case) is needed and an appropriate version of Mac OS X is required, which Journaldulapin.com explains how to install. 

After all that, there will still be performance limitations, such as the 133 MB/s bandwidth supported by a 32-bit 33 MHz PCI bus (keep in mind that we are talking about a half-duplex interface here), but this is to be expected. 

A legitimate question about installing a new SSD into a system with such a performance-capping interface is whether it would be far easier and faster to just plug in an external SSD using a USB connection. And it is certainly easier to plug in a USB drive, but Apple's Power Mac G4 only features two USB 1.1 ports, which means a 12 Mb/s data rate (1.5 MB/s), an order of magnitude slower compared to what a 32-bit 33 MHz PCI interface provides.

Of course, using a FireWire 400 (around 50 MB/s) connection would have been faster, but connecting a modern SSD over a FireWire interface to a 20-year-old PC would probably have been even trickier than using a PCI slot. 

Then again much, like many of the best Raspberry Pi projects, installing a new component in an outdated Power Mac G4 is a lot less about convenience or improved performance as it is about fun and figuring out what's possible. From that perspective, this endeavor was clearly a success. 

Intel formally confirmed that select 4th Generation Xeon Scalable 'Sapphire Rapids' processors will feature on-package HBM memory late last year, but the company has never demonstrated an actual CPU equipped with HBM or revealed its DRAM configuration. At the International Symposium on Microelectronics hosted by IMAPS earlier this week, the company finally showcased the processor with HBM and confirmed its multi-chiplet design.

While Intel confirmed on numerous occasions that Sapphire Rapids processors will support HBM (presumably HBM2E) and DDR5 memory and will be able to use HBM either with or without main DDR5 memory, it never showcased an actual HBM-equipped CPU, until this week (thanks to the picture published by Tom Wassick/@wassickt).

As it turns out, each of four Sapphire Rapids chiplets has two HBM memory stacks that use two 1024-bit interfaces (i.e., a 2048-bit memory bus). Formally, JEDEC’s HBM2E specification tops at a 3.2 GT/s data transfer rate, but last year SK Hynix started to mass-produce 16GB 1024-pin known-good stacked dies (KGSDs) rated for a 3.6 GT/s operation. 

If Intel opts to use such KGSDs, HBM2E memory will provide Sapphire Rapids CPU a whopping 3.68 TB/s peak memory bandwidth (or 921.6 GB/s per die), but only for 128GB of memory.  By contrast, SPR's eight DDR5-4800 memory channels supporting one module per channel and offering 307.2 GB/s will support at least 4TB of memory using Samsung's recently announced 512GB DDR5 RDIMM modules.

It is also noteworthy the HBM-equipped Sapphire Rapids comes in a large BGA form-factor and will be soldered directly to the motherboard. This is not particularly surprising as Intel's LGA4677 form-factor is pretty narrow and the CPU does not have enough space on its package for HBM stacks. 

Furthermore, processors that require a very high-performance memory subsystem like HBM tend to feature loads of cores that work at high clocks and feature a very high TDP. Keeping in mind that HBM stacks are also power-hungry, it may not be easy to develop a socket that would feed an HBM-equipped beast. Therefore, it looks like HBM-equipped SPRs will only be offered to select clients (just like Intel's Xeon Scalable 9200 CPUs with up to 56 cores) and will mostly be aimed at supercomputers. 

Another thing to note is that the shape of the SPR chiplets on the image are rectangular rather than square (as on early images of Sapphire Rapids in LGA4677 packaging). The author of the image said that it comes from an Intel chart "given by an Intel employee and labeled SPR, and verbally noted as Sapphire Rapids." That said, it looks like HBM-supporting Sapphire Rapids CPU might have a different chiplet configuration than regular SPR processors (at the end of the day, regular Xeon Scalable CPUs do not need an HBM interface that takes die space).

Intel's Sapphire Rapids processors will feature a host of new technologies, including PCIe Gen 5 support with CXL 1.1 protocol for accelerators on top, a hybrid memory subsystem supporting DDR5 and HBM, Intel’s Advanced Matrix Extensions (AMX) as well as AVX512_BF16 and AVX512_VP2INTERSECT instructions designed for datacenter and supercomputer workloads, and Intel's Data Streaming Accelerator (DSA) technology, just to name a few.

Earlier this year we learned that Intel's Sapphire Rapids uses a a multi-chip package with EMIB interconnects between the die, unlike its predecessors that are monolithic. While the number of cores is something that depends on yield and power (some reports indicate that SPR will feature up to 56 active cores, but the actual chiplets may carry as many as 80 cores), it is evident that the 4th Generation Xeon Scalable will be the first to use Intel's latest packaging technologies and design paradigm.

If you believe the chatter around the water cooler, Intel's upcoming Alder Lake lineup of processors is coming our way as soon as October. And, of course, a processor needs to find a home in a motherboard. Intel's Z690 will be the top-end chipset for 12th Generation Core processors codenamed Alder Lake, and according to a report by Performance Computing Inquisitor, the new boards will come with cutting-edge memory and PCIe connectivity. As with all leaked information, even though these details do line up with what's generally known about the Alder lake processors, do take these new bits with a grain of salt. 

For starters, the leaked information claims the Z690 chipset supports both DDR4 and DDR5 DRAM. That means that it is up to the motherboard maker to choose which memory it decides to support on the motherboard, and it will ultimately result in mixed motherboard offerings from board partners like Asus, MSI, and Gigabyte, among others. In addition to the mixed memory support, the Z690 chipset has Gear 2 or Gear 4 modes for DDR5. This allows the memory controller to run at half or quarter speed, respectively, depending on the data rate, to boost overall throughput. 

The CPU outputs 16 Gen5 PCIe lanes, while the chipset provides up to 12 PCIe Gen4 lanes and up to 16 PCIe Gen3 lanes. This setup purportedly allows for higher-end SSDs to be attached, while also keeping GPUs on the newer PCIe bus standards.

Intel has decided to upgrade its Direct Media Interface (DMI) connection, which now uses 8 PCIe Gen4 lanes for communication between the processor and chipset, as pictured in the diagram above. It is worth pointing out that the chipset supports solid USB connectivity with up to four USB 3.2 2×2 (20Gb/s) ports. And for WiFi, there are CNVio modules that support Intel Wi-Fi 6E, and possibly even Wi-Fi 7. However, the latter is less likely in the near term.

As a general reminder, all of the aforementioned information should be taken with a grain of salt. Until Intel discloses further details, the specifications are uncertain and will remain that way until the launch later this year. 

True next-gen 3D chip stacking may be right around the corner, as researches from the Institute of Microeletronics (IME) have just achieved a technology breakthrough that enables up to four semiconductor layers to be stacked. This enables up to 50% savings compared to traditional 2D fabrication techniques, and the technique will likely be used in the best CPUs and best graphics cards of the future.

This achievement is a step-up from the AMD-announced, TSMC-enabled SRAM stacking that's bound to grace our computers by the end of this year, as that particular process currently only enables two dies (in AMD's case, a Zen 3 CCX on layer one and 96MB of SRAM cache on layer two) to be bonded together. The IME researchers have shown a process where they successfully bonded four separate silicon layers via TSVs (Through-Silicon-Vias), the information highways allowing communication between the different dies. 

TSVs and the active wafer stacking they enable are hailed as one of the most important technological breakthroughs for sustaining (and perhaps even improving upon) Moore's Law, since they allow for wider information buses that need not operate at extremely high frequencies to achieve performance goals. This, in turn, enables denser designs, since some components that were previously arranged horizontally can now be vertically stacked. It also allows for higher power efficiency, more efficient heat dissipation, and even offers improvements do yields. That last is because different components that go into a CPU, for instance, can now be manufactured in different wafers instead of the old, monolithic approach, automatically increasing resilience to manufacturing defects.

The manufacturing approach implemented by IME was achieved "...by combining Face-to-Face and Back-to-Back wafer bonding with onestep TSV after stacking." This means that the first, base layer has its "face" towards the second layer, which is also facing it; and the second layer has its "back" towards the third layer's back, which in turn faces the fourth layer's face. After these layers were bonded, IME then proceeded to "punch" them by etching along specifically-designed pathways that finally become the TSVs through which data flows.

If you're thinking that increased verticality should wreak havoc with temperature dissipation despite efficiency gains, you're right. That's why (currently) exotic, direct-to-die cooling technologies are being developed as we speak. Data cubes will soon become more than just science fiction.

Electronics is a world of protocols, technologies and connections. From the humble jumper wire, the most basic of connections where individual wires are used to connect the GPIO to a device, to specialist connectors often polarized or keyed for use with a specific interface. If you are new to electronics then wiring up your first circuit may seem daunting.

Companies such as Adafruit, Seeed and SparkFun have come up with their own solutions to this problem. Each solution is a system that has polarized connectors that make connecting compatible projects easier, with no soldering required. Using these connectors makes constructing electronics projects as easy as building with Lego. But what exactly is the difference between Adafruit’s Stemma / Stemma QT, SparkFun’s Qwiic and Seed’s Grove connectors? Read on to find out.

What are Stemma and Stemma QT?

Adafruit’s Stemma connector arrived in 2018 and essentially it is three or four pin JST PH with 2.00 mm pitch, a connector which is keyed so that it cannot be inserted incorrectly. Stemma is seen on larger boards such as PyPortal which has plenty of space for multiple three and four pin connectors.

There are two forms of Stemma connectors, a three or four pin connector. The three pin connector is used for Pulse Width Modulation, Analog and Digital IO. Using this connector we can control Neopixels, read analog sensors and use digital IO devices such as LEDs and buttons. The four-pin connector is for I2C (Inter-Integrated Circuit) components, enabling the use of multiple sensors / devices on a single bus thanks to devices having an address which can be read from / written to.

Stemma is a great connector, but for smaller boards, such as Adafruit’s QT Py RP2040 we need something smaller and that is where Stemma QT (‘cutie’) comes in. Stemma QT is a smaller version of the four pin Stemma format, roughly half the size of Stemma, with a 1.0 mm pitch. Stemma QT is only for use with I2C components. Analog, PWM and digital IO connections are made via the traditional GPIO.

The pin order for QT is designed to match the pin order for SparkFun’s Qwiic enabling the use of Qwiic add-ons with Stemma QT boards and for the reverse to also be true.

Examples of Stemma QT boards are Adafruit’s MPR121 capacitive touch sensor, SGP40 air quality sensor, aBME680 temperature / humidity / pressure sensor and AMG8833 IR thermal camera.

What is Qwiic?

SparkFun’s Qwiic Connect System was released in 2017 and is for use with I2C components. It is compatible with Adafruit’s Stemma and Stemma QT as Qwiic uses the same pin ordering. Qwicc, like Stemma, uses the I2C protocol and enables components to be daisy chained together.

Qwiic connectors can be found on many of SparkFun’s boards such as the MicroMod ATP carrier board which uses an M.2 slot, the MicroMod standard, for interchangeable processor boards such as the ESP32, Artemis and the new RP2040. There are also adapters for using Qwiic components on the Raspberry Pi via a HAT and pHAT and for the Arduino range of boards.

With SparkFun’s Qwiic connector we can easily connect sensors such as the HC-SR04 ultrasonic sensor, soil moisture sensor and even a NEO-M9N GPS breakout.

What is Seeed Studio’s Grove Connector?

Seeed Studio’s Grove connector is a proprietary connector for its range of boards and boards made in partnership with Arduino. The Grove connector is a 4-pin cable which can be used with analog, PWM, digital IO and I2C.

Grove is compatible with Stemma components, but only for I2C devices as analog, PWM and digital IO are not compatible. If you are unsure, just take a look at the component. If it has SDA / SCL pins, then it is an I2C device.

If you have never used Grove connections before, then the Grove Beginner Kit is worth your investment. In the kit we get an OLED screen, DHT11 temperature sensor, microphone, light sensor and a bonus Arduino compatible board.

Connector Comparison

Which Connector is Right For You?

The answer is based on what boards you already have and what you want to achieve. If you have Adafruit’s boards, then you will most likely have some form of Stemma / Stemma QT connector and so the entire range of add-ons is available to you. You will also have access to SparkFun’s Qwiic range of add ons which opens up a plethora of options for your projects. This is also true if you have any of SparkFun’s boards with Qwiic connectors. 

Seeed’s Grove connectors work with Arduino, Raspberry Pi and now the Raspberry Pi Pico. So buying one set of Grove components is good value for those that wish to use them across multiple platforms.

Ultimately the choice is yours. What projects you wish to build will dictate the choices that you make. But no matter what choice you make, all of these connectors make electronics a breeze and give you the confidence to learn new skills without worrying about your wiring.

A member of ServeTheHome forums has published what he claims to be the first photos of Intel's Xeon Scalable 'Sapphire Rapids' processor. If the images are legitimate, they may shed some light on the design of the CPU and may indicate that it does not use a large monolithic die, but actually carries two dies. 

The photos depict an LGA processor with a metallic heat spreader carrying an 'Intel Confidential' mark, which indicates that this is a pre-production chip meant for testing and evaluation. Another engraving indicates a rather moderate 2.0 GHz frequency of the CPU which is something to be expected from an early sample. Also, since the processor is a pre-production sample, it has a four-character stepping: QTQ2. Since the device does not look like an existing Intel processor, it could well be a sample of Intel's upcoming Sapphire Rapids.

The front side of the alleged Sapphire Rapids processor reveals a rather intriguing detail. The heat spreader of the CPU has two bulges of about the same size. Intel's contemporary CPU heat spreaders do feature a number of convexities, but there is always one main 'bump' above the main die. Two bulges may indicate that Intel uses two processor dies for Sapphire Rapids instead of one monolithic die.

The back side of the CPU looks typical for Intel's latest server processors with its land grid array split into two domains. Meanwhile, there are two identical sets of capacitors in the middle of the package, which supports the theory that Intel's Sapphire Rapids is indeed a multi-chip-module (MCM) carrying two dies interconnected using one of Intel's latest technologies (e.g., EMIB). By contrast, Intel's monolithic dies have one set of capacitors on the back of their packaging. 

Using an MCM — or chiplet — design has a number of advantages when it comes to development and manufacturing. For obvious reasons, it is easier to design, emulate, and debug smaller chips. It is also easier to hit decent clocks and yield levels with smaller dies. On the other hand, large monolithic dies work more efficiently as internal interconnections are always faster than off-chip interconnects. 

As a rule, Intel does not comment on leaked information about its unreleased products, so do not expect the company to confirm or deny any facts about its Sapphire Rapids processor beyond what is has already been revealed.

So far, Intel has publicly confirmed that its Sapphire Rapids processors will use the Golden Cove microarchitecture that supports Intel’s Advanced Matrix Extensions (AMX) as well as AVX512_BF16 and AVX512_VP2INTERSECT instructions that are particularly well suited for datacenter and supercomputer workloads. 

In addition to microarchitectural innovations, the new CPU will feature a DDR5 memory controller (enhanced with Intel’s Data Streaming Accelerator, DSA), the PCIe 5.0 bus with a 32 GT/s data transfer rate that is enriched with the CXL 1.1 protocol to optimize CPU-to-device (for accelerators) as well as CPU-to-memory (for memory expansion and storage devices) interconnects. Intel will produce Sapphire Rapids using its 10 nm Enhanced SuperFin technology.

In an update to analysts and investors, Intel has revealed some additional details about its ongoing projects, namely the Alder Laker hybrid processor for client PCs as well as the Sapphire Rapids CPUs for servers. Apparently, Alder Lake is sampling to PC makers, whereas Sapphire Rapids is about to.  

"We are now sampling our 2021 client CPU Alder Lake, and we'll be sampling our 2021 data center CPU, Sapphire Rapids later in the fourth quarter," said Bob Swan, CEO of Intel, during the company's earnings call with analysts and investors. "Both will deliver significant capabilities enabled by our six pillars of innovation including our [10nm] Enhanced SuperFin technology."

Hybrid x86: Intel's Alder Lake is Sampling

Being a rather mysterious processor in Intel's roadmap, Alder Lake promises to bring the concept of heterogeneous multi-core to x86 processors for client PCs. High-end versions of Alder Lake CPUs for desktops are expected to have up to 16 cores. Back in August Intel indeed said that Alder Lake belongs to 'performance' segment of CPUs.  

"We are advancing our hybrid architecture significantly with the focus on performance," said Raja Koduri, chief architect at Intel. "We are working on next generation hardware, guided scheduler, optimize for performance and leveraging all close seamlessly. Alder Lake will not only be great for performance, but it will also be our best performance per Watt architecture." 

Intel plans to use its 4th generation 10 nm process technology — called 10 nm Enhanced SuperFin — to make Alder Lake processors. The process technology was originally designed for datacenter products in mind, which typically means enhancements to power delivery, MEOL and BEOL in semiconductor production terms. Power delivery is crucial for hybrid processors, such as those that use Arm's Big.Little architecture.

Sapphire Rapids Samples in Q4

Releasing first samples of Sapphire Rapids to customers in Q4 2020 is meant to enable them to launch servers based on these CPUs sometimes in late 2021 or early 2021. Intel is supposed to start volume production of its Sapphire Rapids processors by early 2022 because the company has at least one SPR-based supercomputer contract — the Crossroads — that is set to be delivered by the time.  

But if Intel launches Sapphire Rapids in early 2022, this leaves the company’s 3rd generation Xeon Scalable ‘Ice Lake-SP’ processor about a year of active life on the market. Meanwhile, the two platforms are completely incompatible and it will take Intel’s server partners quite an effort to transit to it. In addition to processor innovations, the new platform will support DDR5 memory, the PCIe 5.0 bus with a 32 GT/s data transfer rate that is enhanced with CXL 1.1 protocol to optimize CPU-to-device (for accelerators) as well as CPU-to-memory (for memory expansion and storage devices) interconnects.  

Just like Alder Lake CPUs and Xe-HP GPUs, Sapphire Rapids will be made using Intel's 10nm Enhanced SuperFin process technology.

Intel made a dizzying array of announcements at its Architecture Day 2020 (full breakdown here). Still, its disclosures around its new Tiger Lake architecture with Willow Cove cores and its accompanying Xe LP graphics are arguably the most interesting, particularly because they will come in new laptops by the end of 2020 to fend off AMD's Ryzen Mobile processors. That's a desperately needed counter for Intel as AMD continues to make inroads in the high-performance notebook market while it simultaneously chomps away market share on the low end.

And Tiger Lake looks like a worthy adversary, at least from afar. Intel's announcements don't cover the specs for actual shipping silicon, but the architectural design certainly looks promising: The new Tiger Lake chips come with a revamped 10nm SuperFin transistor technology, higher frequencies than Ice Lake, a rebalanced cache hierarchy to improve performance, dual ring bus fabric, new security enhancements, support for LPDDR5-5400 in the future (LP4x-4267 for now), and the PCIe 4.0 interface, and Xe LP (Low Power) graphics, among many other improvements.

Don't be fooled by the "Low Power" in the Xe graphics branding, though. The Xe LP graphics engine promises up to twice the performance of the previous-gen Gen11, addressing a key sore point in Intel's lineup compared to AMD's capable 7nm "Renoir" Ryzen Mobile processors with Vega graphics. Intel's Xe LP comes with a significantly revamped architecture that merits its own further inspection, which we have in our Intel Drops XE LP Graphics Specs deep dive. The net-net is that the engine comes with up to 96 execution units (EU) and 'significant' performance-per-watt efficiency improvements over the previous Gen11 graphics, which implies twice the performance at lower power compared to Intel's Ice Lake.

Much like the Tiger Lake CPU cores, a big part of Xe LP's performance improvement comes courtesy of Intel's 10nm SuperFin transistors. First, it's important to know that after four "+" revisions to its 14nm node (each + represented an improvement to the node), Intel has finally decided to discard the "+" branding. Due to rampant industry confusion about the naming scheme, including confusion among Intel's own teams, the company will now assign a new unique name to each process node. "10nm SuperFin" marks the first outing for its new terminology, but Intel says the node is the equivalent of a 10nm+ revision.

The 10nm SuperFin transistors have what Intel calls breakthrough technology that includes a new thin barrier that reduces interconnect resistance by 30%, improved gate pitch so the transistor can drive higher current, and enhanced source/drain elements that lower resistance and improve strain. Intel also added a Super MIM capacitor that drives a 5X increase in capacitance, which helps reduce vDroop.

The new 10nm SuperFin transistors merit their own piece with deeper analysis, which you can find here, but the key takeaway is that Intel says they deliver the same amount of performance uplift that the company would normally expect from a whole series of intra-node "+" revisions, but with just one iteration. In fact, Intel claims these transistors mark the largest single intra-node improvement in the company's history. The changes don't impact density, but have a big impact on performance.

With those process improvements at hand, Intel turned its eye to the Willow Cove microarchitecture found in the Tiger Lake chips. Intel says that instead of making drastic microarchitectural changes that would improve instruction per cycle (IPC) throughput, it instead focused on tuning the circuits of the existing Sunny Cove architecture to run at higher clock speeds. As a reminder, Intel designed the Sunny Cove architecture with a "deeper, wider, smarter" ethos that yielded up to a 15% to 18% IPC performance improvement over the Skylake architecture. 

However, while Intel says it did gain "some" IPC improvement for Willow Cove, it says the lion's share of performance improvement comes from tuning for higher clock speeds at lower power. That should improve per-core performance while preserving battery life in the 10-30W notebooks these chips are destined for (at least for now, we might see 45W and perhaps higher models in the future). 

Overall, much of Tiger Lake's improved performance comes courtesy of the larger dynamic frequency range of the 10nm SuperFin transistors. The new transistors offer higher clock speeds at any given voltage, and can operate at a lower voltage at any given frequency. The transistors also have a greater dynamic range from the Vmin to Vmax (minimum/maximum voltage), and Vmax extends further than found with the original 10nm transistors. By tuning the architecture to exploit the full dynamic range of the transistors, Intel claims Tiger Lake offers both higher maximum frequencies in thermally-unconstrained use and is faster and more efficient in TDP-limited environments. Intel says the culmination of the tuning imparts a greater-than-generational performance improvement over the Sunny Cove cores present in Ice Lake. 

Web browsers represent one of the quintessential examples of a lightly-threaded workload that's highly dependent on per-core performance. Intel demoed Tiger Lake running the WebXPRT3 benchmark at both higher frequencies and lower power than the Sunny Cove cores found in the previous-gen Ice Lake chips. Intel confirmed that these measurements only include the single highest-boosting core in the system. That means it's possible that some of the uplift, which Intel says occurred at the same power, comes from some of the other power-saving measures that should allow better power balancing, as we'll outline below.

Intel has steadily changed its cache topology with its last few architectural upgrades, and yet another 'rebalancing' effort finds the company altering the Sunny Cove design as it moves to Willow Cove. Sunny Cove featured a somewhat drastic L1-D cache improvement from 32KB to 48 KB per core, along with a doubling of L2 cache to 512KB per core. However, Sunny Cove retained the same 2MB-per-core inclusive L3 cache scheme found on Skylake. Intel bumped that up by 50% to 4MB for Willow Cove and changed the cache from inclusive to non-inclusive. The larger L3 cache can hold more working sets to improve the cache hit ratio, but Intel hasn't elaborated on whether or not the larger non-inclusive cache will also contain all, or portions, of data stored in the L2 cache. The net effect is an increase to 12MB~24MB of L3 cache per chip, depending on the product (based on core counts).

Intel also beefed up the memory subsystem with deeper queues to improve scheduling efficiency and a second memory controller with support for DDR4-3200 and LPDDR4-4267 for now. However, the chipmaker made architectural provisions to support up to LPDDR5-5400 in the future. Sunny Cove has the same 128-bit memory bus width as Ice Lake, but Intel went from a 32b-wide quad-channel DDR4 controller to a 16b-wide octo-channel controller. The chip supports up to ~86 GB/s of memory bandwidth, a doubling over Ice Lake. That will certainly come in handy to feed the Xe LP Graphics engine.

With the move to more robust caches and faster memory, it's only natural that the on-chip fabrics have to improve in lockstep. Intel moved to the dual ring bus microarchitecture, though this varies significantly from the older dual ring busses found on high core-count Skylake-X dies of yore. Those dual ring busses served two distinct sets of cores with latency-incurring switches in-between to enable hops between the rings, with each stop on each ring only serving one core or element. In this design, each stop serves both bi-directional rings, meaning Willow Cove's dual ring bus is essentially two ring busses wrapped within one another. This approach doubles the coherent fabric's bandwidth, which is usually twice the memory bandwidth (172GB/s in this case). Interestingly, Intel has moved higher core-count chips to a mesh architecture due to its improved bandwidth, but chose to use a dual ring bus technique with Willow Cove.

Intel also sprinkled in a few new security features, like support for Total Memory Encryption (TME) using XTS/AES encryption/decryption algorithms to protect data held in memory. Control-Flow Enforcement Technology (CET) adds protection against some control-flow hijacking malware.

As part of the reworked memory and fabric subsystems, Intel also added in autonomous dynamic voltage/frequency scaling (DVFS) for the coherent fabric and memory subsystem, allowing them to modulate power consumption based upon usage. Other power enhancements include deeper package C-states that can turn off/reduce all the various clocks in the CPU, including newly power-gated subsystems like the fabric, PCIe, Type-C, and thermal sensors. Intel also lowered fixed rail voltages where possible and made unspecified changes to increase FIVR efficiency at lower load levels.

Intel reworked its High-vT devices, which are low-power low-performance transistors commonly used for I/O devices, like PCIe, Type-C interfaces, imaging, and the like. Intel made these devices more efficient by improving leakage, which then allows a lower operating voltage. That improvement also returns more power to the SoC for processing functions on either the CPU or GPU cores.

Unlike AMD's desktop Ryzen chips, the Ryzen 4000 "Renoir" Mobile APUs only support the PCIe 3.0 interface. That means that Intel finally has a connectivity advantage over Zen 2-based chips with its PCIe 4.0 connectivity in Tiger Lake, which offers twice the throughput of PCIe 3.0. Intel has also finally added support for a direct-attached PCIe storage device to the CPU. That means the chip features an unspecified number of lanes (varies by SKU) connected from the M.2 port directly to the CPU (the company says these lanes can also be used for GPUs).

In the past, Intel connected PCIe storage devices through the PCH, but it says the new direct-to-CPU PCIe 4.0 connection reduces storage latency by 100ns. Now, that sounds impressive if you measure in nanoseconds, but storage performance is measured in milliseconds. That means we're looking at a 0.00009ms improvement to latency, which is hardly meaningful. For reference, Intel's Optane SSD is the fastest SSD on the market (by far), and it has 0.014ms of latency. That means Intel's 100ns claim is meaningless in terms of storage performance (normal flash-based SSDs average between 0.1 and 0.06ms of latency). 

At least we get some meaningful improvements on the display side of the equation. Intel infused a 64-byte direct data path from the memory to the display so it can cut through the layers of arbitration in the chip fabric to ensure a solid QoS. That yields up to a 64GB/s isochronous low-latency pipe from the memory to the graphics, albeit with throughput varying by SKU. We're looking at support for AV1 decode, up to four display pipelines, 8K UHD and Ultra Wide, 12-bit BT2020 color, and 360Hz and Adaptive Sync, among others listed in the album above. Tiger Lake also supports up to six 4K90 sensors (support starts at 4K30) and can process still images up to 42 megapixels, an increase over the prior 27MP limitation with Ice Lake.

Intel touts its 'new' support for integrated Thunderbolt 4 and USB 4, but these aren't really 'new' protocols. In short, with speeds up to 40Gb/s, Thunderbolt 4 maintains the same maximum speed rating as its predecessor (TB3) and doesn't enable new features. Instead, in order to qualify for certification, vendors must enable all of the high-end features that used to be optional, like the ability to hit the 40Gb/s data throughput requirements and support two 4K displays or one 8K display. This approach does simplify the confusing branding surrounding Thunderbolt 3, but from a hardware standpoint, the speeds and feeds remain the same. 

Intel designed a new dual-sided Thunderbolt 3 controller architecture for Ice Lake that provides up to 4 ports, two on each side of the laptop, with each port connected to a x4 PCIe 3.0 root complex on the chip. The integrated controller brought the features enabled by Titan Ridge, a secondary chip that enabled Thunderbolt 3 connections via connections to the CPU and PCH, onto the Ice Lake die. This implementation uses eight PCIe lanes operating at 20 GT/s, a reduction from the 17 lanes on Titan Ridge that ran at 8 GT/s, thus reducing the power consumption, complexity, and componentry associated with the Thunderbolt interface. Vendors still need to add re-timers and power control circuitry, but overall, this implementation significantly simplifies the design. Intel hasn't shared many fine-grained details on the new connection, but it will be interesting to see if the company leverages the faster PCIe 4.0 standard to reduce the lane count. 

Intel carries over support for AI-boosting VNNI instructions (aka DL Boost - INT8/INT16) that leverage AVX-512 to boost the performance of convolutional neural networks. The Gaussian and Neural Accelerator (GNA) returns, but this time with a new 2.0 revision. This SoC-integrated AI accelerator block is used for processing all sorts of low-power voice-based applications, like translation and transcription, using low-power inferencing. Intel claims that this offload engine can reduce CPU utilization by 20% during these types of operations, but at a much lower power consumption of 1 gigaop-per-mW, with a max of 38 gigaops of performance. 

That's Tiger Lake and Willow Cove in a nutshell, at least for now. Today's disclosures only cover the architectural bits of the design, so we still don't have a list of processors that will come to market, or their respective specs. We expect those details to come to light in the coming months as we move closer to launch, but the early signs look promising for Intel. Tiger Lake could serve to be a much-needed parry to AMD's Ryzen Mobile assault, which has found Intel's rival slowly chipping away market share in the mobility market. As always, the proof is in the silicon, and we can't wait for Tiger Lake to hit our labs. 

EDIT, 15/03/2020, 3:00pm PT: MSI is the manufacturer behind the MS-98L9 V2.0. German retailer Spectra is one of the few to list the motherboard on its website. We have amended the text below to accurately reflect the situation:

As discovered by German publication HardwareLuxx, MSI has created a rather peculiar LGA1151-based motherboard for consumers that are still using archaic hardware. The MS-98L9 V2.0 apparently resurrects the defunct PCI interface, among other fascinating relics.

Maintaining the old-time look, the MS-98L9 V2.0 comes with a green PCB that adheres to the standard ATX form factor. The motherboard has a LGA1151 socket, and it's based on the Intel H110 chipset. This means that it can accommodate Intel processors up to the 7th Generation Kaby Lake chips that have enjoyed retirement since October 2019. Don't let the feeble power delivery subsystem fool you, though. MSI states the MS-98L9 V2.0 can handle Kaby Lake parts up to 95W without a sweat.

The MS-98L9 V2.0 comes with two DDR4 memory slots and supports dual-channel memory kits up to DDR4-2400 for a maximum capacity of 32GB. The motherboard only has four SATA III ports, but lacks an M.2 port, meaning you're out of luck when it comes to high-speed solid-state storage options unless you use one of the PCIe slots. 

The MS-98L9 V2.0's expansion configuration is one of the more interesting parts of the motherboard. It has one conventional PCIe x16 slot, one PCIe x16 slot wired at x4 and five vintage white PCI slots. At this point, we're suprised that MSI didn't throw an AGP slot into the mix as well. However, the motherboard manufacturer does include an ISA (Industry Standard Architecture) slot that dates way back to the 1980's.

The list of internal headers on the MS-98L9 V2.0 includes two USB 2.0 headers, one GPIO (general-purpose input/output) header, four COM headers, one SMBus (System Management Bus) header and one TPM (Trusted Platform Module) header. The motherboard depends on the Realtek ALC887-VD2-CG codec for audio and the Fintek F81866AD-I controller for I/O.

The MS-98L9 V2.0 can support up to two displays. The VGA port handles resolutions up to 1920 x 1200 at 60Hz and the HDMI port can output resolutions up to 4096 x 2160 at 24Hz. The motherboard provides two Gigabit Ethernet ports. One is based on Intel's I219-LM controller while the other is based relies on the I211-AT controller.

In addition to the aforementioned interfaces, the motherboard's rear panel also holds two USB 2.0 ports, one PS/2 combo port, two COM ports, four USB 3.0 ports and three 3.5mm audio jacks.

Spectra doesn't list a price for the MS-98L9 V2.0. If you're interested in the motherboard, you'll have to request a quote directly from the company.

There’s a new top dog when it comes to the X265 benchmark. This week, overclocker Christopher “Mythical Tech” Adkins used an Intel Celeron G470-powered system to set new world records for the single-core benchmark at both 4K and 1080p.  

The X265 benchmark is mutlithreaded and based on the x265 encoder that measures frames rendered per second by a CPU. Adkins hit 0.619 frames per second (fps) for the 4K record and 2.568 fps for the 1080p record with the Celeron running at a clock speed of 2.224 GHz.

“X265 is notoriously hard on the CPU and has been known to kill lots of chips,” Adkins told Tom’s Hardware. 

Despite its lower clock speed compared to other and newer CPUs (the chip came out in 2013), Adkins selected the G470 because it's the most recent single-core CPU with Hyper-Threading on a consumer CPU socket that he knows of with the Intel SSE4.1 and Intel SSE4.2 instruction sets, the instruction sets the benchmark's developer said are required to run the benchmark optimally. The benchmark was developed on the Sandy Bridge-E platform, and the newer AVX instruction set is said to have no performance impact (although AVX2 on Haswell would).   

But it wasn’t just about picking the right CPU. Adkins also spent around eight hours binning about 140 CPUs with the help of friends, searching for a high front-side bus (FSB) speed, which lets the processor communicate with devices connected to the chipset, a good integrated memory controller and a low enough cold bug, the point at which the temperature’s too low for the system to operate, on his cascade phase-change cooling system. 

RAM choice was the second most important component decision, and Adkins went with the Corsair Dominator GT DDR3-4096 (2x 2GB), which uses Elpida Hyper integrated circuits (ICs).

“Another IC that people use is PSC, but my particular CPU did not play well with any of my [RAM] kits of PSC, so I went with my kit of Hypers,” Adkins explained. 

Adkins chose the other components based on what could fit his college student budget. In fact, the Asus Maximus IV Extreme-Z motherboard had two dead PCIe slots and cost the overclocker just $25. Meanwhile, a GT 710 graphics card earned its spot for its small size and lower power draw. Adkins also used a 450W EVGA power supply. 

Of course, it isn’t overclocking if you’re not cooling. This record-breaking system relied on cascade phase change cooling, which sends gas through a cooling and condensing stage via two compressors.

“Most people choose to use a single-stage on Sandy Bridge (CPU microarchitecture), but I don't have one, so I had to hope my CPU did not cold bug at anything under -105 degrees Celsius,” Adkins said. 

Adkins seemingly has the making of a successful professional overclocker, breaking Albrecht  “Leeghoofd” Mesotten’s previous 4K, single-core record of 0.617 fps and 1080p record of 2.557 fps with his first time touching a Sandy Bridge-based processor or X265. His schedule also allowed only 24 hours to get the job done. This included 8 hours of binning and two hours getting the ISO for Windows 7, an overclocking favorite, downloaded, installed and stripped. 

“I fired up the cascade and booted into the OS at 110.5 FSB, which was what the record at the time done by Leeghoofd was set with. I compared my result to his to see how far behind I was with efficiency. After checking to see what FSB I would need, I set it to 111 and started to run it and initially got a score of 0.617 [fps], which was tied for first, but I knew it was capable of more,” Adkins recalled.

“So I restarted and went up to 111.2 [FBS], which is what allowed me to get the score of 0.619 that took first place [in 4K].”

Adkins didn’t have to change any settings to then break the 1080p benchmark because the system was limited by FSB, not CPU core speed or memory. The 4K benchmark was harder to break than the 1080p counterpart, Adkins said, because of how long each run took.

“In total, the cascade was running for 11 hours straight, which caused my room to get above 90 degrees Fahrenheit, and 11 hours of sitting next to the noise a cascade makes is not too fun,” Adkins said. “But overall it was mostly down to just being lucky with being able to bin so many CPUs to take the record.”

Update 9/13/2019 13:32pm PT:

After an extended period of back and forth with Intel, we have confirmed that the existing B-1 stepping chips do suffer from the LPC bus degradation issue, which is rectified via a firmware update. This issue is classified as Errata APL47, as listed here (PDF). When the B-1 Stepping is used in accordance to the published specifications and design guidelines, it meets PC Client and IOT usage requirements.

The new F-1 stepping products have the LPC bus degradation issue fixed in the silicon and will be available for order for 15 years.

We've amended the article below to include the new information and a portion of the errata/fix description. 

Original Article, 9/11/2019 2:40pm PT:

Regrettable errors happen all the time in life, but we rarely see one of this proportion from the world's leading semiconductor producer. We reported this week on an Intel PCN (Product Change Notice) posted to its QDMS website that stated the Apollo Lake chips suffered from LPC bus degradation issues that have been tied to previous Intel chip recalls, but we noticed that Intel pulled the PCN from the company's website on the following day. Below you can see the original PCN that called out the LPC bug specifically as the reason for a stepping change to the processors.

We've never seen a PCN pulled from Intel's site, so we followed up with the company to investigate. Intel tells us it posted the PCN in error, and the new version has no reference to an LPC bus degradation issue.

Here you can see the new PCN (PDF) posted to Intel's site this morning. The new PCN clarifies the stepping change, with an obvious emphasis on assuring the chips are in fact reliable. But it doesn't answer the question of why the change is being made.

Intel's original LPC bus degradation issue with the Atom C2000 series had enough of an impact that the company had to create a reserve fund to cover the costs associated with replacing the processors, so it certainly wants to make it known that the issue doesn't impact all parts. Intel also provided us with this statement in regards to the change:

There are no changes to the B-1 Stepping of the Intel® Celeron® N3350, J3355, J3455 Processors and Intel Pentium N4200 Processor as they meet all Intel quality goals for PC Usage and will continue to be available. The F-1 Apollo Lake Intel Celeron N3350, J3355, J3455 Processors and Intel Pentium N4200 Processor meet all Intel quality goals for PC Usage. With IOTG's operational decision to converge onto a single package for all of the IOTG Apollo Lake Processors, the F-1 stepping Celeron N3350, J3355, J3455 Processors and Pentium N4200 Processor has a slight increase in Z height compared to the B-1 Stepping.

You'll also notice that this statement calls out that the chips meet Intel's "quality goals for PC usage," but doesn't mention long life product availability. 

As noted above, after extensive back and forth with Intel, the company confirmed that the changes do stem from the LPC bus degradation errata. The existing B-1 stepping chips suffer from the LPC bus degradation issue, which is rectified via a firmware update.

This issue is classified as Errata APL47, as listed here (PDF). When the B-1 Stepping is used in accordance to the published specifications and design guidelines, it meets PC Client and IOT usage requirements.

The new F-1 stepping products have the LPC bus degradation issue fixed in the silicon and will be available for order for 15 years.

AMD's Vega 56 may be a last-gen flagship, but you can pick one up for the lowest price we've seen at retail today. Newegg has listed MSI's Radeon RX Vega 56 Air Boost 8G OC for $299.99 with promo code "VGASAV33S" and a $20 rebate, as it counters Amazon's Prime Day dealstravaganza. That's a total savings of $79.

The Vega 56 comes armed with 56 Compute Units fed by 8GB of HBM2 memory communicating across a 2049-bit bus. Vega 56 serves up 1156 / 1471 MHz base/boost clock speeds, but MSI bumps that up to 1181 / 1520 MHz. Meanwhile, 410 GB/s of memory bandwidth feeds the beast.

• MSI Radeon RX Vega 56 for $229.99 (reg $309)

You feed the card power through two 8-pin connectors, and three DisplayPort and a single HDMI port offer plenty of connectivity options.

We put the Vega 56 through its paces last year, finding that it excelled in 1440p gaming, but that did come at the cost of higher power consumption and thermal output. You can see the full rundown in our AMD Radeon RX Vega 56 8GB Review.

For more savings, check out our list of best Amazon Prime Day deals and best PC hardware deals overall as well as dedicated lists of current sales on SSDs, CPUs, GPUs, gaming laptops and Raspberry Pi stuff.

Are you ready to upgrade your old gaming rig? Newegg has this awesome Ryzen 5 3600X and Sapphire Radeon RX 5700 bundle for $559.89, which saves you up to $40 as opposed to buying each part individually.

• Get the Ryzen 5 3600X and Sapphire Radeon RX 5700 bundle for $559.89.

The Ryzen 5 3600X is part of AMD's Zen 2 army that recently invaded the processor market. The processor has formidable attributes that include six cores, 12 threads and up to 32MB of L3 cache. The chip runs with a 3.8 GHz base clock and 4.4 GHz boost clock. The Ryzen 5 3600X supports DDR4-3200 memory modules and the new PCIe 4.0 inferface out of the box. The Wraith Spire CPU cooler is included with the Ryzen 5 3600X so you don't have to spend extra for a cooling solution.

The Sapphire Radeon RX 5700 is a Navi-powered graphics card that's based on AMD's pristine RDNA (Radeon DNA) architecture. It comes with 2,304 Stream Processors that operate with a 1,465 MHz base clock, 1,625 MHz game clock and a boost clock that tops out at 1,725 MHz. The graphics card also has 8GB of GDDR6 memory running at 14 Gbps across a 256-bit memory bus for a maximum memory bandwidth of 448 GB/s.

The Radeon RX 5700 has a TBP (Typical Board Power) off 180W and draws power from one eight-pin PCIe connector and one six-pin PCIe connector. It's recommended that your system has at least a 600W power supply.

Should You Buy This Bundle?

As usual, we highly recommend you check out our in-depth Radeon RX 5700 review before opening your wallet. For more help picking the best graphics card for you, there's our graphics card buying guide, the AMD and Nvidia GPU hierarchy and our breakdown of the best graphics cards we've tested.

You can also review our CPU buying guide for help. To see where the Ryzen 5 3600X ranks among others currently available, including from rival Intel, check out our CPU hierarchy page. And for other CPUs we love, see our favorite gaming CPUs and favorite CPUs for productivity performance. 

Double Data Rate 5 (DDR5) is the next-generation standard for random-access memory (RAM). The new specification promises to bring chips that have much higher performance than the existing DDR4 modules, as well as lower power consumption. But what does that mean for desktop PCs? Let's take a look at what we know so far.

Why We Need DDR5 RAM

With the launch of AMD’s first-generation Ryzen processors, a new Core War began. AMD delivered quad-core/eight-thread processors at mid-range and eight-core/16-threads CPUs at the high-end for mainstream PC consumers, which was just about double what Intel had been offering for years in those ranges.

With the third-generation Ryzen processors, AMD has increased the core count by another 50%, pushing six-core chips at mid-range and 12-cores at the high-end. Intel has also been forced to respond with an increase in the number of cores for its own processors, although Intel hasn’t been nearly as aggressive as AMD.

In less than three years we went from four cores being just about the highest number most gamers or regular PC users could expect in their computers to three times as many. What all of this means is that we’re going need to drastically increase our memory bandwidth per core, too, if our PCs are going to keep up with AMD and Intel’s core war.

As we can see from Micron’s chart above, bandwidth per core has remained relatively stable since the early 2000s. However, bandwidth per core has started to decline since last year.

DDR5 Performance

DDR5 designs promise to arrive on the market with double the density as well as double the performance of the first-generation DDR4 modules. 

Image Credits: David Schor / WikiChip

DDR5-3200 RAM will see an increase of 1.36x in bandwidth compared to DDR4-3200. However, DRAM chips are expected to ship with a bandwidth of 4800MT/s, or 1.87x that of DDR4-3200 RAM. The official upper limit for the DDR5 RAM standard is 6400MT/s, but some designs may be able to push that further through overclocking.

SK Hynix has been working on DDR5 modules that can deliver 16Gb (2GB) capacity per chip. The company lowered voltage from 1.2V to 1.1V, which combined with the usage of its 1Ynm process, reduced power consumption compared to the company’s DDR4 modules. The module offers up to 6.4Gb/s of throughput for each pin.

Other benefits of DDR5 RAM include two independent 40-bit channels per module, improved command bus efficiency, improved refresh schemes and an increased bank group for additional performance.

Features Enabling High-Bandwidth DDR5 RAM

According to Micron, DDR5 will use a completely overhauled architecture compared to DDR4, with a focus on increasing bandwidth. A number of key features enable this increase in bandwidth. The most important is that DDR5 can increase the data rates from 3,200 MTps to 6,400 MTps. This data rate increase alone should more than keep up with potential future processors with even more cores.

The new DDR5 RAM standard also includes other new protocol features that are not related to the data rate transfers, but can still increase overall bandwidth. For instance, DDR5 DIMMs will support two 40-bit (32-bit + ECC) independent channels.

The new default burst length of 16 (BL16) in DDR5 RAM allows a single burst to access 64B of data, which is the typical CPU cache line size, using only one of the two independent channels or half the DIMM. This feature should provide a significant improvement in concurrency and effectively move us from the 8-channel memory systems we know today to a 16-channel system.

DDR5 also doubles the number of bank groups (BGs) compared to DDR4, while keeping the number of banks per BG the same. This means that the total number of banks will be double that of DDR4. This helps controllers avoid performance degradation associated with sequential memory accesses within the same bank. All of these features and more point to how significant of an upgrade DDR5 will be compared to DDR4.

First DDR5 Products to Ship In 2019

In March 2017, JEDEC, the group developing the DDR standard as well as other memory and storage standards, announced that it would release the DDR5 specification in 2018. In November 2018, SK Hynix announced the world’s first DDR5-compliant RAM module, which the company initially said would arrive in 2020.

However, since then SK Hynix has said that it will release a DDR5 module by the end of 2019. Samsung and Micron have also previously said they would release DDR5 memory modules, but those may not be fully standard-compliant.

SK Hynix predicted that DDR5 module sales would represent 25% of the RAM market in 2020 and 44% in 2021. The adoption of DDR5 RAM may be even faster in the mobile and data center markets. Smartphone makers (including Samsung) will want to outclass the competition with faster DDR5 LPDRAM, while data center customers will be seeking to satisfy their ever-increasing bandwidth needs. Meanwhile, we're still waiting for word on a firm arrival date for DDR5 for desktop PC, but this will likely hinge on AMD and Intel offering support on mainstream motherboards. Unfortunately, there have been no signs of DDR5 enablement from either company yet. 

MORE: Best RAM

Positive Technologies, a vulnerability assessment, compliance management and threat analysis solutions company, announced this week that it's discovered yet another undocumented feature in Intel’s chipsets, after previously stumbling upon an undocumented mode developed by Intel specifically for the NSA. The feature, Intel Visualization of Internal Signals Architecture (VISA), could allow attackers to gain the lowest-levels of access to Intel CPUs and any data being processed by those CPUs.

Intel VISA Unveiled

Intel VISA is a “full-fledged logic signal analyzer“ that is found in the PCH (Platform Controller Hub) microchips on modern Intel motherboards and CPUs. The feature normally allows manufacturers to test and debug the chips on the manufacturing line.

VISA can be used to monitor electronic signals sent from internal buses and peripherals to the PCH. Similarly, a malicious actor could use the feature to intercept all of the data passing through the same channels.

Positive Technologies expert Maxim Goryachy said in a statement: "We found out that it is possible to access Intel VISA on ordinary motherboards, with no specific equipment needed. With the help of VISA, we managed to partially reconstruct the internal architecture of the PCH microchip."

Intel Kept VISA Secret from the Public

According to the researchers, this feature has not been publicly disclosed by Intel, which would only tell others about it under a non-disclosure agreement (NDA).

The good news is that the feature is disabled by default (unlike Intel ME, which is enabled by default on most Intel-based machines), so attackers can’t exploit VISA without first finding a way to enable it.

The bad news is that the Positive Technologies researchers found a way to disable VISA using an older Intel ME vulnerability. Intel released a firmware patch that fixes that vulnerability back in 2017, but unless your laptop maker or motherboard maker has sent your the updated firmware and you updated your system with it, your PC will remain vulnerable. This bug can’t be fixed through operating system updates.

The silver lining is that if an attacker can exploit your system through the existing Intel ME vulnerability, then there they can’t do much worse by also gaining access to VISA. However, if in the future attackers find another way to enable VISA, even on systems with patched Intel ME firmware, that could indeed expose PC users to new dangers.

The researchers said that they have found three other ways to enable VISA themselves, which they will reveal in a presentation slide on the Black Hat site in a few days. The researchers already presented this information at the Black Hat Asia 2019 cybersecurity conference, which started on March 26 and ends today.

Another question that remains is how many other undocumented modes/features that give low-level access to a user's system are there in Intel's CPUs? Intel may try to keep them secret from the public primarily so that bad actors don't learn about them either, but security through obscurity usually doesn't work. Sophisticated attackers with enough resources can learn about those secret features on their own, just as the Positive Technologies researchers did.

Intel Begins with The 4004

The first microprocessor sold by Intel was the four-bit 4004 in 1971. It was designed to work in conjunction with three other microchips, the 4001 ROM, 4002 RAM, and the 4003 Shift Register. Whereas the 4004 itself performed calculations, those other components were critical to making the processor function. The 4004 was mostly used inside of calculators and similar devices, and it was not meant for use inside of computers. Its max clock speed was 740 kHz.

The 4004 was followed by a similar processor known as the 4040, which was essentially an improved variation of the 4004 with an extended instruction set and higher performance.

MORE: Best CPUs

MORE: Intel & AMD Processor Hierarchy

MORE: All CPU Content

8008 And 8080

The 4004 made a name for Intel in the microprocessor business, and to capitalize on the situation, Intel introduced a new line of eight-bit processors. The 8008 came first in 1972, followed by the 8080 in 1974 and the 8085 in 1975. Although the 8008 was the first eight-bit processor produced by Intel, it is not as notable as its predecessor or its successor, the 8080. It was faster than the 4004 thanks to its ability to process data in eight-bit chunks, but it was clocked rather conservatively between 200 and 800 kHz, and the 8008's performance simply didn't attract many system developers. The 8008 used 10-micrometer transistor technology.

Intel's 8080 was far more successful. It expanded on the design of the 8008 by adding new instructions and transitioning to six-micrometer transistors. This allowed Intel to more than double the clock rates, and the highest-performance 8080 chips in 1974 came running at 2 MHz. The 8080 was used in countless devices, which lead to several software developers, such as the recently formed Microsoft, to focus on software for Intel's processors.

Eventually when the 8086 was released, it was made source compatible with the 8080 to maintain backwards compatibility with this software. As a result, the 8080s and key hardware elements have been present inside of all x86-based processor ever produced, and 8080 software can technically still run on any x86 processor.

The 8085 was essentially a less expensive and higher-clocked variant of the 8080, which was highly successful as well though less influential.

8086: The Beginning Of x86

Intel's first 16-bit processor was the 8086, which helped to boost performance considerably compared to earlier designs. Not only was it clocked higher than the budget-oriented 8088, but it also employed a 16-bit external data bus and a longer six-byte prefetch queue. It was also able to run 16-bit tasks (though most software at this time was designed for eight-bit processors). The address bus was extended to 20-bit, which enabled the 8086 to access up to 1MB of memory and therefore increase performance.

The 8086 also became the first x86 processor, and it used the first revision of the x86 ISA, which nearly all of the processors created by AMD or Intel since the introduction of the 8086 have been based on.

Intel also produced the 8088 around the same time. This processor was based on the 8086, but with half as many data lines and a four-byte prefetch queue. This caused a loss of balance, as the narrower bus cut into instruction fetch rate, forcing Intel's execution unit to idle much of the time. It still had access to up to 1MB of RAM and ran at higher frequencies than previous processors; however, it was quite a bit slower than the 8086.

80186 And 80188

Intel followed up the 8086 with several other processors, all of which used a similar 16-bit architecture. The first was 80186, aimed at embedded applications. To facilitate this, Intel integrated several pieces of hardware typically found on the motherboard into the CPU, including the clock generator, interrupt controller, and timer. As a side effect, certain instructions ran notably faster on 80186 than 8086, even at the same clock rate. But of course, Intel naturally pushed the CPU's frequency up over time to further improve performance.

The budget-oriented 80188 similarly contained several pieces of hardware integrated into the processor. But like the 8088, its data bus was cut in half.

80286: More Memory, More Performance

The 80286 was released the same year as the 80186 and had nearly identical features, but it extended the address bus to 24-bit, which enabled the processor to access up to 16MB of memory.

iAPX 432

The iAPX 432 was an early attempt by Intel to diverge from its x86 portfolio in favor of an entirely different design. Intel expected iAPX 432 to be several times faster than its other offerings. The processor ultimately failed, however, due to some major design flaws. Although x86 processors are relatively complex, the iAPx 432 took CISC to a whole new level of complexity. The hardware design was rather large, which forced Intel to craft it out of two separate dies. The processor was also quite data hungry and failed to perform well without extremely high amounts of bandwidth. The iAPX 432 managed to outperform the 8080 and 8086, but it was quickly outpaced by newer x86 products, and eventually it was abandoned.

i960: Intel's First RISC

Intel created its first RISC processor in 1984. It was not designed as a direct competitor to the company's x86 processors because it was intended as a secure embedded solution. Internally, it was a 32-bit superscalar architecture that used Berkeley RISC design concepts. The first i960 processors were clocked relatively low, with the slowest model running at 10 MHz, but over the years it was improved and transitioned to smaller fabs that enabled it to hit up to 100 MHz. It also supported 4GB of protected memory.

The i960 was widely used inside of military systems as well as in business systems.

80386: x86 Turns 32-bit

Intel's first 32-bit x86 processor was the 80386, released in 1985. One key advantage that this processor had was its 32-bit address bus that allowed it to support up to 4GB of system memory. Although this was far more than anyone was using at the time, RAM limitations often hurt the performance of prior x86 and competing processors. Unlike modern CPUs, at the time the 80386 was released, more RAM almost always translated into a performance increase. Intel also implemented several architectural enhancements that helped push performance up above the 80286, even when both systems used the same amount of RAM. It also supported virtual mode processing, which increased multi-tasking support.

To segment its product line-up with a more budget-friendly offering, Intel also introduced the 80386SX. This processor was almost identical to the 80386; it still employed a 32-bit architecture, but half of its data bus was cut to 16 bits for cost-saving purposes.

i860

In 1989, Intel made another attempt to move away from its x86 processors. It created a new RISC CPU known as the i860. Unlike the earlier i960, this CPU was designed to be a high-performance model to compete in the desktop market, but the design proved problematic. Its most significant flaw was that the processor's performance relied entirely on the compiler to place instructions in the order they would need to be executed when the software was first created. This helped Intel keep the die size and overall complexity of the i860 down, but it was nearly impossible to correctly list every instruction from beginning to end when compiling the program. This caused the CPU to constantly stall while it attempted to work around the problem.

80486: Integrating The FPU

Intel's 80486 was another significant step up in terms of performance. The key to its success was tighter integration of components into the CPU. The 80486 was the first x86 CPU to contain L1 cache. Early 80486 models came with 8KB on-die, and were etched on a 1000nm process. But as the design transitioned to 600nm, the L1 cache size doubled to 16KB.

Intel also incorporated the FPU into the CPU, which up to that point had been a separate functional processing unit. By moving these pieces of hardware into the host processor, latency between them dropped sharply. The 80486 also used a faster FSB interface to increase bandwidth, and the core had various other tweaks to push up IPC. These changes increased the 80486's performance significantly, and high-end models were multiple times faster than the older 80386.

The first 80486 processors reached 50 MHz, and later models that used the improved 600nm process went as high as 100 MHz. To target budget-oriented users, Intel also released a version of the 80486 known as the 80486SX, which had the FPU disabled.

P5: The First Pentium

The Pentium emerged in 1993 as the first Intel x86 processor that didn't follow the 80x86 number system. Internally, the Pentium used the P5 architecture, which was Intel's first x86 superscalar design. Although the Pentium was generally faster than the 80486 in every way, its most prominent feature was a substantially improved FPU. The original Pentium's FPU was more than ten times faster than the 80486's aging unit. This became an even more significant feature in later years when Intel released the Pentium MMX. This processor was architecturally the same as the original Pentium, but featured support for Intel's new MMX SIMD instruction set that could drastically boost performance.

Intel also increased the L1 cache size on its Pentium processors relative to the 80486. Initial Pentiums contained 16KB, while the Pentium MMX moved up to 32KB. Naturally, these processors also ran at higher clock rates. The first Pentium processors used 800nm transistors and could hit just 60 MHz, but subsequent revisions transitioned to Intel's 250nm process and pushed frequencies up to 300 MHz.

P6: The Pentium Pro

Intel planned to quickly follow the Pentium up with the Pentium Pro based on its P6 architecture, but ran into technical difficulties. The Pentium Pro was considerably faster than the Pentium in 32-bit operations thanks to its Out-of-Order (OoO) design. It featured a significantly redesigned internal architecture that decoded instructions into micro-ops, which were then executed on general-purpose execution units. It also used a significantly extended 14-stage pipeline owing to the additional decoding hardware.

As the first Pentium Pro processors were targeted at the server market, Intel extended the address bus again to 36-bit and added its PAE technology that allowed it to support up to 64GB of RAM. This was far more than average users needed, but being able to support greater amounts of RAM was key to Intel's server customers.

The processor's cache system was reworked as well. The L1 cache was limited to two segmented 8KB caches, one for instructions and one for data. To make up for the 16KB deficit compared to the Pentium MMX, Intel placed between 256KB and 1MB of L2 cache on a separate chip attached to the CPU package. It connected to the CPU using a back-side-bus (BSB).

Intel initially planned to push the Pentium Pro out to consumers as well, but ultimately limited it as a server product. The Pentium Pro featured several revolutionary features, but it struggled against the Pentium and Pentium MMX in terms of performance. Both of the older Pentium parts were significantly faster at 16-bit operations, and 16-bit software was still heavily used back then. The processor also lacked support for the MMX instruction set, which resulted in the Pentium MMX outperforming the Pentium Pro in MMX-optimized software.

The Pentium Pro may have stood a chance in the consumer market, but it was also fairly expensive to produce due to the separate chip containing L2 cache. The fastest Pentium Pro processor ran at 200 MHz, and it was crafted with transistors ranging between 500 and 350nm.

P6: Pentium II

Intel didn't give up on the P6 architecture, but instead waited until 1997 when it released the Pentium II. The Pentium II managed to overcome nearly all of the negative aspects of the Pentium Pro. Its underlying architecture was similar to the Pentium Pro, and it continued to use a 14-stage pipeline with several enhancements to the core to improve IPC. The L1 grew to 16KB data + 16KB instruction caches.

Intel also moved to more affordable cache chips attached to a larger silicon package to reduce production costs. This was an effective way of making the Pentium II less expensive, but these memory modules were unable to operate at the CPU's full speed. Instead, the L2 cache ran at half-frequency, and on these early processors that was sufficient to increase performance.

Intel also added support for the MMX instruction set. The CPU cores used inside of the Pentium II, code-named "Klamath" and "Deschutes," were also sold as Xeon and Pentium II Overdrive products for servers. The highest-performance models contained 512KB of L2 cache and ran at 450 MHz.

P6: Pentium III And The Race To 1 GHz

Intel planned to follow up the Pentium II with a processor based on its Netburst architecture, but it wasn't quite ready. Instead, Intel pushed the P6 architecture out again as the Pentium III.

The first of these processors, code-named "Katmai," was rather similar to the Pentium II in that it used a slotted cartridge containing lower-quality L2 cache at half of the CPU's speed. The underlying architecture incorporated other significant changes, as several parts of the 14-stage pipeline were fused together, shortening it to 10 stages. Thanks to the updated pipeline and an increase in clock speed, the first of the Pentium III processors typically outperformed their Pentium II counterparts by a small margin.

Katmai was produced using 250nm transistors. However, following the move to a 180nm fabrication process, Intel was able to boost the Pentium III's performance significantly. This updated implementation, code-named "Coppermine," moved the L2 cache into the CPU and reduced its capacity by half (down to 256KB). But because it was able to run at the processor's frequency, performance still shot up.

Coppermine was Intel's competitor to AMD's Athlon in the race to break 1 GHz, which it succeeded in doing. Intel attempted to produce a 1.13 GHz model, but it was ultimately recalled after investigation from Dr. Tom Pabst of Tom's Hardware discovered that it was unstable. This left the 1 GHz model the fastest Coppermine-based Pentium III.

The last of Pentium III cores was named "Tualatin." It moved to a 130nm process that facilitated clock rates as high as 1.4GHz. It also increased the L2 cache back to 512KB, which helped improve performance somewhat.

P5 And P6: Celeron And Xeon

Around the release of the Pentium II, Intel also introduced its Celeron and Xeon product lines. These products used the same core as the Pentium II or Pentium III, but with varying amounts of cache. The first Celeron-branded processors based on the Pentium II had no L2 cache at all, which resulted in horrible performance. Later models based on the Pentium III had half of the L2 cache disabled compared to their Pentium III counterparts. This resulted in Celeron processors that used the Coppermine core containing just 128KB of L2 cache; later models based on Tualatin increased this to 256KB.

These half-cache derivatives became known as the Coppermine-128 and the Tualatin-256. Intel sold them at clock speeds comparable to the Pentium III, which allowed them to perform well and made them highly competitive against AMD's Duron processors. Microsoft used one of the Coppermine-128 Celeron processors clocked at 733 MHz as the CPU inside of its Xbox gaming console.

The first Xeon processors were similar, but they contained more L2 cache. The Pentium II-based Xeon processors contained at least 512KB, the same as Pentium II CPUs, whereas higher-end models could have up to 2MB.

MORE: Best CPUs
MORE: Best CPU Cooling
MORE: Intel & AMD Processor Hierarchy
MORE: All CPU Content

Netburst: Introduction

Before discussing Intel's Netburst architecture and the Pentium 4, it is important to examine the idea behind its deep pipeline, which describes the process whereby instructions move through a core. Pipeline stages often perform multiple tasks, but sometimes they're devoted to single functions. By either adding new hardware or splitting one stage into multiple stages, the execution pipeline can be extended. The processor pipeline can also be shrunk by removing hardware or by combining the components in multiple stages down into a single stage.

The length or depth of the pipeline has a direct impact on latency, IPC, clock speed and the architecture's throughput requirements. Longer pipelines typically require higher amounts of bandwidth, but if the pipeline is kept adequately fed with data, then each stage in the pipeline stays busy. Processors that have longer pipelines typically are able to run at higher clock rates as well.

The trade-off is significantly higher latency inside of the processor, as data flowing through it must stop at each stage for a certain number of clock cycles. Processors using a long pipeline tend to have lower IPC as well, which is why they rely on significantly higher frequencies to increase performance. Over the years, processors implementing both philosophies have proven successful. Neither approach is necessarily flawed.

Netburst: Pentium 4 Willamette And Northwood

In 2000, Intel's Netburst architecture was finally ready, and it was pushed into production as the Pentium 4. The combination would carry Intel's top-end CPUs for the next six years. The first implementation was named "Willamette," which carried Netburst and the Pentium 4 through the first two years of its life. This was a troubled time for Intel, however, and the chip struggled to outperform the Pentium III. Netburst enabled significantly higher frequencies, and Willamette managed to hit 2 GHz, but the Pentium III at 1.4 GHz was still faster in some tasks. AMD's Athlon processors enjoyed a healthy performance lead during this period.

The problem with Willamette was that Intel stretched the pipeline out to 20 stages and planned to hit even higher clock rates beyond 2 GHz, but due to power consumption and heat issues, it was unable to reach those goals. The situation improved with Intel's 130nm design known as "Northwood," which scaled up to 3.2 GHz and doubled the L2 cache from 256KB to 512KB. Netburst's power consumption and heat issues persisted. However, Northwood nevertheless performed significantly better and was highly competitive against AMD.

On high-end models, Intel also introduced its Hyper-Threading technology to improve resource utilization in environments that emphasized multitasking. Hyper-Threading wasn't as beneficial on Northwood as it is on present-day Core i7 processors, but it did push performance up by a few percentage points.

Willamette and Northwood were released inside of Celeron- and Xeon-branded CPUs as well. As with the previous generation of Celeron- and Xeon-based products, Intel raised or lowered the L2 cache size in order to distinguish their performance.

P6: Pentium-M

As Netburst was designed as a high-performance architecture that was fairly power hungry, it didn't translate well to mobile systems. Instead, in 2003 Intel created its first architecture designed exclusively for notebooks. The Pentium-M was based on the P6 architecture, but with a longer 12-14 stage pipeline. This was also Intel's first variable-length pipeline, which meant that instructions could be executed after moving through just 12 stages if the information required for the instruction was already loaded into cache. If not, it had to go through two additional stages to load the data.

The first of these processors was crafted with 130nm transistors and contained a 1MB L2 cache. It managed to hit 1.8 GHz while consuming just 24.5W of power. A later revision known as "Dothan" was released in 2004 and transitioned to 90nm transistors. This enabled Intel to increase the L2 cache to 2MB and, combined with a number of core enhancements, provide a decent IPC throughput improvement. The CPU also scaled up to 2.27 GHz with a slight increase of power to 27W.

The Pentium-M architecture would eventually be used inside of the Stealey A100 mobile CPUs before being replaced by Intel's line of Atom processors.

Netburst: Prescott

Northwood carried the Netburst architecture from 2002 until 2004, after which Intel launched Prescott with numerous enhancements. It used a 90nm fabrication process that enabled Intel to increase the L2 cache to 1MB. Intel also introduced the new LGA 775 interface that featured support for DDR2 memory and a faster quad-pumped FSB than the first Northwood-based CPUs. These changes resulted in Prescott having significantly more bandwidth than Northwood, which was vital to increasing Netburst's performance. Prescott was also Intel's first 64-bit x86 processor, allowing it to access more RAM and operate on 64 bits at a time.

Prescott was supposed to be the crown jewel in Intel's family of Netburst-based processors, but instead it was a fiasco. Intel again extended its execution pipeline, this time to 31 stages. The company hoped to increase clock rates enough to offset the longer pipe, but it was only able to hit 3.8 GHz. Prescott simply ran too hot and consumed too much power. Intel expected the move to 90nm to alleviate this issue, but the increased transistor density made cooling more difficult. As it was not able to hit higher frequencies, Prescott's evolutionary changes hurt overall performance.

Even with all of the enhancements and extra cache, Prescott was, at best, on par with Northwood at any given clock rate. Around the same time, AMD's K8 processors were also moving to smaller transistors that enabled them to hit higher frequencies. For this brief time period, AMD dominated the desktop CPU market.

Netburst: Pentium D

In 2005, the race was on to produce the first consumer-oriented dual-core processor. AMD had already announced its dual-core Athlon 64, but it wasn't available yet. Intel rushed to beat AMD by using a multi-core module (MCM) that contained two Prescott dies. The company christened its dual-core processor the Pentium D, and the first model was code-named "Smithfield."

The Pentium D launched to criticism, however, as it faced the same issues that plagued Prescott. The heat and power of two Netburst-based dies limited clock rates to 3.2 GHz at most. And because the architecture was bandwidth-limited, Smithfield's IPC suffered as throughput was split between two cores. The implementation wasn't particularly elegant either; AMD's dual-core CPU constructed from one die was considered superior.

Smithfield was followed by Presler, which moved to 65nm transistor technology. It contained two Ceder Mill dies on an MCM. This helped reduce the processor's heat and power consumption, and let Intel raise its clock rate to 3.8 GHz.

There are two key steppings of Presler. The first one had a higher 125W TDP, whereas the later model dropped down to 95W. Thanks to the smaller die size, Intel was able to double the L2 cache as well, so each die had 2MB. A few enthusiast models also featured Hyper-Threading, allowing the CPU to address four threads simultaneously.

All Pentium D processors supported 64-bit software and could take advantage of more than 4GB of RAM.

Core: Core 2 Duo

Intel eventually gave up on its Netburst architecture and instead put its support behind the P6 and Pentium-M design. The company realized that P6 was still viable, and capable of being both efficient and providing excellent performance. It reworked the architecture into its Core design. Like the Pentium-M, it used a 12 to 14 stage pipeline that was significantly shorter than Prescott's 31-stage implementation.

Core proved to be highly scalable, and Intel was able to push it into service on mobile systems with TDPs as low as 5W and high-end servers with 130W ceilings. Intel mostly sold it as "Core 2 Duo" or "Core 2 Quad" products, but Core was also used inside of Core Solo-, Celeron-, Pentium- and Xeon-branded CPUs. The dies used were built using two CPU cores, and quad-core designs used two dual-core dies on an MCM. Single-core versions, meanwhile, had one core disabled. L2 cache size ranged from 512KB up to 12MB.

With the improvements made to the Core architecture, Intel could again compete against AMD. The PC market entered a golden age filled with extremely competitive high-performance processors that are still viable to this day.

Bonnell: Silverthorne And Diamondville

The Core 2 architecture hit a wide range of devices, but Intel needed to produce something less expensive for the ultra-low-budget and portable markets. This led to the creation of Intel's Atom, which used a 26mm² die, less than one-fourth the size of the first Core 2 dies.

Intel didn't design Atom's Bonnell architecture completely from scratch, but instead went back to the Pentium's P5 foundation. That was largely because P5 was Intel's last in-order execution design. OoO execution, though highly beneficial to performance, also consumes quite a bit of power and takes up a large amount of die space. For Intel to meet its goals, OoO simply wasn't practical at the time.

The first Atom die, code named "Silverthorne," had a TDP of 3W. This enabled it to go places that Core 2 could not. Silverthorne's IPC was lackluster, but it was able to run at up to 2.13 GHz. It also contained 512KB of L2 cache. The decent frequency and L2 cache did little to make up for the low IPC, but Silverthorne still enabled an entry-level experience at a relatively low price.

Silverthorne was succeeded by Diamondville, which reduced the frequency to 1.67 GHz but enabled 64-bit support, which improved performance in 64-bit apps.

Nehalem: The First Core i7

With the processor market in a highly competitive state, Intel couldn't afford to sit still for long. So, it reworked the Core architecture to create Nehalem, which adds numerous enhancements. The cache controller was redesigned, and the L2 cache dropped to 256KB per core. This did not hurt performance though, as Intel instead added between 4-12MB of L3 cache shared between all of the cores. CPUs based on Nehalem included between one and four cores, and the family was built using 45nm technology.

Intel significantly reworked connections between the CPU and rest of the system as well. The ancient FSB that had been in use since the 1980s was finally put to rest, and it was replaced by Intel's QuickPath Interconnect (QPI) on high-end systems and by DMI everywhere else. This allowed Intel to move its memory controller (which was updated to support DDR3) and PCIe controller into the CPU. These changes significantly increased bandwidth while latency plummeted.

Once again, Intel extended the processor pipeline, this time to 20-24 stages. Clock rates did not increase, however, and Nehalem ran at comparable frequencies to Core. Nehalem also was Intel's first processor to implement Turbo Boost. Although the fastest Nehalem processor's base clock topped out at 3.33 GHz, it could operate at 3.6 GHz for short periods thanks to this new technology.

The last major advantage that Nehalem had over the Core architecture was that it marked the return of Hyper-Threading technology. Thanks to this and numerous other enhancements, Nehalem was able to perform up to twice as fast as Core 2 processors in heavily-threaded workloads. Intel sold Nehalem CPUs under the Celeron, Pentium, Core i3, Core i5, Core i7, and Xeon brands.

Bonnell: Pineview And Cedarview

In 2009, Intel released two new Atom-branded dies based on the Bonnell architecture. The first was known as "Pineview," which continued to use a 45nm fabrication process. It featured better performance than Diamondville by integrating a number of components traditionally found inside of the motherboard chipset, including graphics and the memory controller. This had the effect of reducing power consumption and lowering heat dissipation. Dual-core models were also available using two Pineview cores on an MCM.

Westmere: Graphics In The CPU

Intel created a 32nm die shrink of Nehalem that was code-named "Westmere." Its underlying architecture changed little, but Intel took advantage of the reduced die size to place additional components inside of the CPU. Instead of just four execution cores, Westmere contained up to 10. It could also have as much as 30MB of shared L3 cache.

The HD Graphics implementation in mainstream Westmere-based Core i3, i5, and i7 processors was similar to Intel's GMA 4500, except it had two additional EUs. Clock rates stayed about the same, ranging between 166 MHz in low-power mobile systems and 900 MHz on higher-end desktop SKUs. Although the 32nm CPU die and 45nm GMCH weren't fully integrated into a single piece of silicon, both components were placed onto the CPU package. This had the effect of reducing latency between the memory controller inside of the GMCH and the CPU. API support didn't significantly change between the GMA and HD Graphics implementations, though overall performance increased by over 50 percent.

Related: Evolution of Intel Graphics: i740 To Iris Pro

Sandy Bridge

With Sandy Bridge, Intel made its most significant leap in performance, the most in seven years. The execution pipeline was shortened into 14-19 stages. Sandy Bridge implemented a micro-op cache capable of holding up to 1500 decoded micro-ops that enabled instructions to bypass five stages if the micro-op required was already cached. If not, the instruction would have to run the full 19 stages.

The processor also featured several other improvements, including support for higher-performance DDR3. More components were integrated into the CPU as well. Instead of two separate dies on the CPU package (as on Westmere), everything moved into one die. The various subsystems were connected internally by a ring bus that enabled extremely high-bandwidth transactions.

Intel again updated its integrated graphics engine. Instead of a single HD Graphics implementation pushed into all CPU models, the company created three different versions. The top-end variant was the HD Graphics 3000 with 12 EUs that was could be clocked up to 1.35 GHz. It also contained extras like Intel's Quick Sync transcoding engine. The mid-range HD Graphics 2000 variant possessed the same features, except it dropped down to six EUs. The lowest-end HD Graphics model also had six EUs, but with the value-added features.

Bonnell: Cedarview

In 2011, Intel created another new Atom die based on the same Bonnell architecture used inside of Pineview. Again, there were minor core enhancements to improve IPC, but in reality little changed between the two. Cedarview's key advantage was a move to 32nm transistors that enabled frequencies up to 2.13 GHz at lower power. It was also able to support higher-clocked RAM thanks to an improved DDR3 memory controller.

Ivy Bridge

Intel followed Sandy Bridge with its Ivy Bridge processors, a "Tick+" in the company's "Tick-Tock" product design cadence. Ivy Bridge's IPC was only slightly better than Sandy Bridge's, but it brought with it other key advantages that outshined its predecessor.

Ivy Bridge's greatest advantage was its energy efficiency. The architecture was crafted with 22nm three-dimensional FinFET transistors that sharply reduced the CPU's power consumption. Whereas mainstream Sandy Bridge-based Core i7 processors typically came with a 95W TDP, the equivalent Ivy Bridge-based chips were rated at 77W. This was particularly important in mobile systems, and it allowed Intel to release a quad-core mobile Ivy Bridge CPU with a low 35W TDP. Prior to this, all of Intel's quad-core mobile CPUs came with at least a 45W TDP.

Intel took advantage of the reduced die size to also enlarge the iGPU. Ivy Bridge's highest-end graphics engine, HD Graphics 4000, packed in 16 EUs. The graphics architecture was also significantly reworked to improve the performance of each EU. With these changes, HD Graphics 4000 typically performed 200 percent better than its predecessor.

Haswell

Like a metronome, Intel pushed out its Haswell architecture just one year after Ivy Bridge. Haswell was once again more of an evolutionary step than a revolutionary one. The AMD processors competing against Sandy and Ivy Bridge weren't fast enough to do battle at the high end, so Intel wasn't pressured to increase performance too much. Haswell was approximately just 10 percent faster than Ivy Bridge overall.

Similar to Ivy Bridge, Haswell's most attractive features were its energy efficiency and iGPU. Haswell integrated the voltage regulation hardware into the processor, which enabled the CPU to keep a better handle on power consumption. The voltage regulator caused the CPU to produce more heat, but the Haswell platform as a whole became more efficient.

To combat AMD's APUs, Intel placed as many as 40 EUs inside of its top-end Haswell iGPU. The company also sought to increase the available bandwidth its fastest graphics engine had access to by equipping it with a 128MB L4 eDRAM cache, which drastically improved performance.

Bonnell: Silvermont

In 2014, Intel significantly reworked the Bonnell architecture to create Silvermont. One of the most significant changes was a switch to an OoO design. Another was the elimination of Hyper-Threading.

When the Bonnell architecture debuted, many felt that OoO occupied too much die space and was too power-hungry for an Atom CPU. By 2014, however, transistors had shrunk to such a small size and enjoyed reduced power consumption significantly enough that Intel could enable an OoO design on Atom. Intel also reworked the pipeline in Silvermont to minimize the impact of a cache miss. These changes, combined with a number of other improvements, resulted in a 50 percent increase in IPC compared to Cedarview.

To further boost Silvermont's performance, Intel created SKUs containing up to four CPU cores. It also switched to an iGPU based on the same graphics architecture in its Ivy Bridge processors. There were only four EUs in Silvermont's iGPU, but it nonetheless was capable of providing 1080p video playback, and it could run older games that weren't especially taxing. All aspects of the chipset were integrated into the Silvermont CPU as well, but this was more to reduce the system power consumption than anything.

The Silvermont die was used in Bay Trail-based products. The platform's TDP ranges between 2 and 6.5W, and the clock rate ranges between 1.04 and 2.64 GHz.

Broadwell

Intel's next processor architecture was known as Broadwell. Designed for mobile systems, it was released in late 2014 and used 14nm transistors. The first Broadwell-based product was called the Core M, and it was a dual-core Hyper-Threaded processor that operated with a 3-6W TDP.

Other mobile Broadwell processors dribbled out over time, but on the desktop side of the market, Broadwell never really showed up. A few desktop-oriented models were released in mid-2015. However, their reception was tepid. The highest-end SKU, however, contains the fastest integrated GPU Intel has ever added to a socketed CPU. It contains six subslices with eight EUs each, adding up to a total of 48. The GPU also has access to a 128MB L4 eDRAM cache, which helps to resolve the bandwidth challenges on-die graphics engines typically face. In gaming tests, it outperformed AMD's fastest APU and proved to be more than capable of providing playable frame rates in modern games.

Bonnell: Airmont

With its 14nm fab up and running, Intel did not hesitate to push out a new Atom chip built from these transistors. This CPU die was essentially a shrink of Silvermont, and Intel named it "Airmont." It did not improve IPC, but thanks to the die shrink it still managed to somewhat outperform its predecessor. After all, the move to 14nm transistors reduced heat dissipation, allowing the CPU to maintain its Turbo Boost frequency for longer periods of time.

Airmont's iGPU was significantly improved over Silvermont. The die itself contains 24 EUs, but products based on Airmont use between 12 to 16. None of the models based on Airmont currently all 24 EUs, and we are unlikely to see one in the future. These extra eight EUs exist to improve yields of Airmont, as a larger portion of the chip can be defective and still be salvageable. The graphics architecture was also updated to Intel's eight-gen Broadwell, improving the EUs' performance.

Airmont products were sold under the "Cherry Trail" and "Braswell" code names. The fastest Airmont-based Atom CPU is the N3700, which contains four CPU cores clocked at 1.6 GHz with a Turbo Boost frequency of 2.4 GHz. It also has a dual-channel DDR3L memory controller and 16 EUs clocked at up to 700 MHz.

Skylake

In 2015, not long after Broadwell first showed up on desktop systems, Intel replaced Broadwell with its Skylake architecture. Although Skylake-based CPUs were Intel's fastest to date, the platform changes accompanying Skylake were arguably more important.

Skylake was the first consumer-oriented CPU to use DDR4 memory, which is more energy-efficient than DDR3 and capable of enabling greater throughput. The Skylake platform also contained a number of improvements, such as a new DMI interface, an upgraded PCIe controller, and support for a much wider array of connectivity devices.

Naturally, Skylake included a better on-die GPU as well. The highest-end model was known as Iris Pro Graphics 580, and it was deployed to certain Skylake-R CPUs. The Iris Pro Graphics 580 engine featured 72 EUs and came paired with 128MB of L4 eDRAM. Most other Skylake-based chips included HD Graphics with 24 EUs, based on a design similar to Broadwell's.

Kaby Lake

Starting with Skylake and Kaby Lake, Intel ended its tick-tock development cadence in favor of a tick-tock-tock schedule. It was also referred to as the process-architecture-optimize cadence. This extended the amount of time Intel spent on a single fabrication process before it developed a new one. It also extended the amount of time between major architectural changes.

Kaby Lake, therefore, was essentially an optimized variation of Intel’s Skylake architecture. Although still 14nm, Intel utilized a process it called 14nm+ that had various tweaks to improve energy efficiency and performance. The architecture itself hardly changed at all, but it did facilitate DDR4-2400 memory support.

Kaby Lake also employed an HD Graphics 630 engine featuring improved codecs for encoding and decoding, extending support for 4K video playback.

Coffee Lake

With Coffee Lake, Intel increased the number of cores in its Core i3, i5, and i7 processors by two. This marked the largest increase in core count for Intel since the introduction of the Core 2 Quad in 2006.

Core i5s now have six cores without Hyper-Threading. Coffee Lake-based Core i7s also have six cores, but with Hyper-Threading. The underlying architecture does not change from Kaby Lake. However, with more cores to share the work, performance increases markedly in threaded applications.

Coffee Lake-based Core i3 processors lack Hyper-Threading, but thanks to the increase from two to four CPU cores, the Core i3 processor family has never wielded more power. In essence, Coffee Lake Core i3 CPUs are every bit as powerful as Kaby Lake Core i5s, and potentially faster than Skylake Core i5s.

Whiskey Lake and Amber Lake

Intel's delayed 10nm process has slowed progress on the smaller Cannon Lake processors, so the company developed the 14nm++ Whiskey Lake and 14nm+ Amber Lake processors for laptops, to fill the gap between generations.

The new 15-watt U-Series Whiskey Lake models slot into the same Eighth Generation Core “Kaby Lake-R” product stack as previous-generation mobile chips, and have the same numbers of cores and threads as the chips they’ll be replacing. And the 5-watt Amber Lake models replace the seventh-gen Y-series chips found primarily in fanless laptops and convertibles. One of the primary new features for Whiskey Lake is the addition of the first hardware-based fixes for Meltdown and L1TF to appear on consumer-focused CPUs.

The Whiskey Lake and Amber Lake processors all feature the same underlying Kaby Lake microarchitecture as previous-generation CPUs, with a few optimizations. Primarily, single-core boost frequencies get a big bump over previous parts (up to 4.6GHz with the Core i7-8565U). But of course, exactly how long your CPU will stay at that top speed depends largely on the device’s cooling abilities.

MORE: Best CPUs

MORE: Intel & AMD Processor Hierarchy

MORE: All CPU Content

As the release date for Microsoft’s Xbox One X console approaches, the company is opening up about the details of the Xbox One X—the new top of the Xbox One product stack. Today at the Hot Chips conference, the company released schematics and details about the internal workings of the SoC that is set to power the upcoming 4K-ready gaming console.

We already knew much of what the company discussed at the Hot Chips presentation, including the core count; clock speed; and bandwidth specifications of the CPU, GPU, and memory used in the system, but now we know how the components interact with each other.

Microsoft first revealed the Xbox One X, then known only as Project Scorpio, during the company’s E3 2016 conference. In what appeared to be a direct response to Sony’s PlayStation 4 Pro console, Microsoft announced that the next iteration of Xbox One console would boast 6TFlops of floating point performance, which would enable it to support native 4K gaming and virtual reality. The company said that the console would be available before the end of 2017.

In April, Microsoft released some of the basic hardware specs for project Scorpio, revealing that the console would feature an AMD SoC with eight CPU cores and 40 GPU compute units paired with 12GB of GDDR5 memory that provides 326GB/s of memory bandwidth. Microsoft also revealed that the console would include a 4K UHD Blu-ray player and a 1TB 2.5” storage drive.

Then, at Microsoft’s E3 2017 press conference, we learned that the device would be known as the Xbox One X and that it would boast a 384-bit memory bus (up from 256-bit). Microsoft also revealed that the new console wouldn’t include the 32MB of embedded eSRAM cache memory that current Xbox One and Xbox One S consoles offer, although it didn’t explain why.

Scropio: More Than Just A Codename

When Microsoft first announced the Xbox One X, it referred to the console by its internal code name, Project Scorpio. The company walked back the Scorpio moniker somewhat when it announced the official console name, but the company didn’t let go of the "Scorpio" title altogether. At the Gamescom conference in Germany, Microsoft revealed the Xbox One X Project Scorpio limited edition console, which includes the name Project Scorpio emblazoned across the front. But as it turns out, all Xbox One X consoles have a little bit of Scorpio in them. Microsoft called the system-on-chip (SoC) that powers the new console the Scorpio Engine.

The Scorpio Engine is a monster of an SoC developed by AMD, featuring a 359mm2 die with seven billion transistors built on TSMC’s 16nm FinFETT+ technology. The GPU compute units (the yellow section of the layout) consume most of the large die’s surface area. The Scorpio Engine’s GPU components include four shader arrays that each offer 11 compute units. Microsoft said that one compute unit per shader array is left inactive to compensate for yield problems that may occur.

The right side of the SoC die features the two four-core 2.3GHz CPU clusters (represented in dark green on the diagram). A pair of cache controllers flanks each CPU cluster. Twelve GDDR5 memory controllers line the top, bottom, and right edges of the SoC. The retail Xbox One X features 12GB of memory. Developer kits offer 2GB per channel for a total of 24GB system memory.

Microsoft said that the Xbox One X’s peak theoretical memory bandwidth is 326GB/s, which is nearly five times that of the Xbox One and Xbox One S. The company said that in testing, it managed to address 285GB/s of the available 326GB/s, but most games won’t use that much. The company noted that the extremely high memory bandwidth allowed it to do away with the 32MB eSRAM cache found in the older Xbox One models.

When Microsoft announced Project Scorpio, the company boasted that the new console would be the first to deliver 6Tflops of 32-bit floating point performance. During the Hot Chips presentation, the company said that it managed to squeeze out “just a hair more than 6Tflops." Each of the 40 compute units can perform 128 floating point operations second. Multiplied by the 1,172MHz core clock, that's a total of 6,000,640 Flops.

Microsoft said it put a lot of effort into optimizing the GPU performance. The Scorpio Engine SoC features firmware and “special hardware” to “integrate support for DX12” and maximize the performance of games that take advantage of Microsoft’s API. The Xbox One X’s performance optimizations extend to the CPU, as well.

The new console features an eight-core Jaguar-derived CPU like the one found in the Xbox One S console, but it operates 31% faster than the previous version. Microsoft said that most of the CPU performance optimizations revolve around memory latency improvements of the main memory controllers (up to 20%). The company attributes the improvement to tripling the available memory channels and increasing the number of main memory banks by a multiple of six. It also credits the rearrangement and enlargement of the TLB cache, and the introduction of a redesigned and larger Page Descriptor Cache, which “caches information about nesting page translations” and improves performance by “up to 4.3%.”

The Xbox One X features a single-chip southbridge design, which provides the reference clock for all the components in the system. The Scorpio Engine SoC interacts directly with the memory, the video outputs, the Ethernet network controller, and the south bridge. The southbridge communicates with the other components in the system, including the USB 3.0 controller, the infrared communication ports, the WiFi adapters for the network and the game controllers, the Blu-ray player, the hard drive, and the flash memory.

Audio and Video Improvements

Microsoft is touting the Xbox One X as a premium 4K gaming and entertainment system for the living room. In addition to offering 4K resolution gameplay, the console also boasts improved video decoding compared to the older Xbox One consoles. The Xbox One X supports 4K 60Hz HEVC (H.265), VP9, and AVC (H.264) video formats. It also offers 10-bit high dynamic range (HDR) HEVC and VP9 playback. The Xbox One X also supports 4K 60Hz HEVC video encoding for DVR capture and game streaming. 

The Xbox One X features support for 4K, 64-bit display output over the DP 1.2a / HDMI 2.0b protocol. The HDMI port also supports HDCP 2.2 and two-steam MST, which opens the doors for additional display support—a necessary feature if Microsoft ever jumps into VR on the Xbox One X. The upcoming console also includes eight custom audio processors that support spatial surround sound audio, which would also play a big role in VR support. Microsoft said a new firmware update would add spatial surround support to the Xbox One S, too.

Pre-Order Now

Microsoft is about to shake up the console gaming world with the most powerful game console ever built. The Xbox One X is now available for pre-order for a whopping $499, and the first shipments will land in the hands of eager gamers on November 7.

Intel's Akhilesh Kumar, the Skylake-SP CPU architect, penned a blog post today announcing the company's new on-chip mesh architecture for its Xeon Scalable Processor platform.

Intel's Scalable Processor platform is the company's re-branding of its venerable Xeon processor lineup, and due to the company's continued use of optimized server processor die for its HEDT (High-End Desktop) lineup for enthusiasts and workstations, the new architecture has wormed its way into the forthcoming Skylake-X family.

Intel's new mesh topology goes head-to-head with AMD's Infinity Fabric, which resides in its Ryzen, ThreadRipper, and EPYC processors. Let's compare the two designs.

The Ring Bus Era

CPUs are all about processing data, which requires data movement. Bits representing 1s and 0s speed through the internals of the processor on nanometer-scale pathways that move on the order of billions of cycles per second. Moving data between the key elements, such as cores, memory, and I/O controllers, is one of the most daunting challenges involved with processor design.

Efficient data movement has a tremendous impact on performance, but all data movement also requires power for transit, so smooth and effective transmission is a key component to ensuring a low power envelope. This also helps constrain thermal output. Optimized interconnects, in turn, allow architects to dedicate more of the power budget to other useful pursuits, such as data processing. Several techniques have been employed over the years for intra-processor communication, but Intel's ring bus implementation has served as a cornerstone of the company's designs for the last several generations.

Intel's ring bus, shown above on the Broadwell LCC (Low Core Count) die, connects the various components with a bi-directional bus (in red). The LCC dies employ a single ring that propels data at a one-cycle-per-hop rate (among contiguous cores). For instance, moving data from one core to its closest neighbor requires one cycle. Moving data to more distant cores requires more cycles, thus increasing the latency associated with data transit. It can take up to 12 cycles to reach the most distant core, so the ability to move data in either direction (bi-directional) allows the processor to route it along the shortest path possible. Caches accompany each separate core on the die, so increased latency also impacts cache performance.

The larger HCC (High Core Count) die exposes one of the problems with this approach. To increase the cores and cache, the HCC die employs dual ring buses. Communication between the two rings has to flow through a buffered switch (seen between the two rings at the top and bottom). Traversing the switch imposes a five-cycle penalty, and that is before the data has to continue through more hops to its destination. This increased latency limits scalability. The intra-processor communication takes longer as core counts increase, impacting performance, and increasing the frequency to defray the performance loss requires higher voltage, thus impacting power consumption and thermal dynamics. Remember, processors can reach boost frequencies for longer periods of time based upon the internal thermal budget, so increased voltage can also negatively affect performance.

Exposing The Mesh

Intel's new mesh architecture made its debut on the company's Knights Landing products, but the move to the more mainstream server SKUs and high-end desktop models is designed to bring about new levels of interconnect efficiency for those markets. Aside from the interconnect, a few key attributes pop out. Intel has moved the DDR4 controllers to the left and the right sides of the die--similar to the Knights Landing design--whereas the company has typically positioned them at the bottom for ring bus designs. We'll examine that shortly.

Intel aligned its new mesh topology into a grid of rows and columns that connect the cores and caches, along with the memory and I/O controllers. Notably, there are no buffered switches between disparate rings--it's simply a large mesh, so it eliminates one of the major traffic checkpoints for high core count dies entirely. The switch connections at each intersection of the grid allow for more direct communication between the components, thus providing faster pathways through intelligent scheduling. There also appears to be a circular design to the intersections, which likely allows for more optimized data path scheduling.

The ability to 'stair-step' data through the cores allows for much more complex, but efficient, routing among the elements. Intel also indicates that the new ring has increased bandwidth, which helps speed data traffic among the cores and the caches that feed them. The mesh is also responsible for traffic to and from main memory, so it has an impact on RAM throughput and latency as well.

Data also flows in from the PCIe controllers at the top of the die, along with the two inter-socket links. The inter-socket links manage data flow between processors in 2+ socket server configurations. In the past, Intel has employed its QPI (QuickPath Interconnect) for cross-socket communication, but it's rumored to employ a new UPI interconnect for Skylake server CPUs (Purley).  Intel hasn't specified the exact frequency of the new mesh, but has indicated that it has a lower frequency and voltage than the ring bus design, though it still delivers high bandwidth and low latency. That alone is an important achievement.

The modular and distributed design should allow Intel to add more cores to its die without imposing crushing performance and power consumption penalties. The mesh design also reduces latency variability when requesting data from far-flung LLC banks, which allows software to treat it as one large unified last-level cache.

So What About Skylake-X?

Intel released a die shot of its HCC (High Core Count) die that it employs for the Skylake-X processors. Again, Intel uses the same architecture for its Xeon lineup and for the enthusiast-class parts, so Skylake-X employs the same mesh interconnect topology.

We can clearly see the relocated DDR4 controllers on the right and left of the die (second row down on both sides), so while it appears the die has 20 cores, it 'only' features 18. This happens to be the maximum core count of Intel's new Skylake-X lineup.

Intel's mesh diagram indicates that it aligns the mesh intersections at the right side of each core, but the die shot implies otherwise. If we examine the cores on the far left column, we can see a distinct area of the core in the upper right corners, which the block diagram implies is the rough location of the interconnect. However, examining the adjacent column of cores indicates that the cores are mirror images of each other. This implies that instead of the mesh pathways running along the right side of each core, they might run on the left side of each mirrored column. This would have an impact on the distance between every other column of cores, which would translate as more cycles required for horizontal data traversal. For instance, it likely requires one hop/cycle to move data vertically to the next core, but moving horizontally from the second column to the third column will likely require more cycles. We'll have to wait for more detail.

In either case, the mesh architecture has a tremendous scalability advantage over its predecessor, and considering that Intel used the ring bus for several generations, we can expect the company to use the mesh for the foreseeable future. That should allow Intel to increase core counts without adverse performance penalties.

So What's AMD Up To?

No conversation about an Intel architecture is complete without a comparison to AMD's latest design. AMD also developed a new Infinity Fabric interconnect, which is an optimized version of HyperTransport, for its Zen microarchitecture. Fortunately, we know much more about AMD's interconnect.

AMD's Zen-based processors take a different path to processor design. The Zen microarchitecture employs a four-core CCX (CPU Complex) building block. AMD adorns each CCX with a 16-way associative 8MB L3 cache split into four slices; each core in the CCX accesses this L3 with the same average latency. Two CCXes come together to create an eight-core Ryzen 7 die (the large orange blocks in the image above), and they communicate via AMD’s Infinity Fabric interconnect. The CCXes share the same memory controller. This is basically two quad-core CPUs talking to each other over the Infinity Fabric pathway. The Infinity Fabric is a 256-bit bi-directional crossbar that also handles northbridge and PCIe traffic.

Although each core in a four-core CCX can access the local cache with the same average latency, trips to fetch data in adjacent CCXes incurs a latency penalty due to the trip across the Infinity Fabric. Communication between threads on cores located in disparate CCXes also suffers. AMD's design held a scalability advantage over Intel's ring bus architecture -- the company can simply infuse more CCXes onto the package to increase the core count. In fact, the 16C/32T ThreadRipper processors employ four CCXes. Due to the latency penalty for cross-CCX traffic, this could result in variability for some traffic. We expect the Intel marketing machine to push the new mesh architecture as an advantage over the Infinity Fabric, but it's notable that software optimization can defray many of the penalties associated with the Infinity Fabric.

We measured AMD's Infinity Fabric latency in our AMD Ryzen 5 1600X CPU Review and found that the speed of the fabric is tied to memory frequency, so faster memory data rates results in lower latency. This has a significant impact on Ryzen's gaming performance. We also measured Intel's ring bus latency with faster memory frequencies but found that it remains largely unaffected. It will certainly be interesting to test latency with the Skylake-X products to determine if the new mesh has distinctive characteristics.

The Wars Rage On

The return of a competitive CPU market has both Intel and AMD touting their latest architectural advantages, and both the mesh and AMD's Infinity Fabric will likely power the respective company's designs for the next several product generations, albeit with optimizations along the way. For instance, Intel's ring bus debuted back with Nehalem in 2007, and AMD's HyperTransport also served as an interconnect architecture that spanned multiple products.

Each architecture will have its strengths and weaknesses, and the only way to quantify performance advantages is to test the silicon. We're eager to get our hands on the new Skylake-X models to see if the new mesh topology offers tangible performance benefits. Stay tuned.

SK Hynix is displaying its next generation GDDR6 memory modules at Nvidia's GTC event in San Jose, California. According to the memory maker, GDDR6 operates with an I/O data rate of 16Gbps and a theoretical bandwidth of 768GB/s when paired with a 384-bit I/O bus. This new memory standard allows for twice the bandwidth per pin as GDDR5 and delivers 10% lower power consumption. It is expected to power Nvidia's upcoming Volta GPU architecture.

SK Hynix is the world’s second-largest memory chipmaker and world’s fifth largest semiconductor company. Just a few short weeks ago, senior vice president Jonghoon Oh, the Head of SK Hynix's DRAM Product Development Division said in a press release:

“With the introduction of this industry’s fastest GDDR6, SK Hynix will actively respond to high quality, high-performance graphics memory solutions market. The Company would help our clients enhance their performance of high-end graphics cards,” he added.

According to SK Hynix, the company has been collaborating with “a core graphics chipset client” to mass produce the GDDR6 for the upcoming market demands.

Putting these numbers into perspective, standard GDDR5 offers 8 Gbps of throughput, GDDR5X memory offers up to 12 Gbps, and GDDR6 offers speeds up to 16 Gbps. Here's a comparison list of GDDR5 versus GDDR6:

AMD Is Born

From its conception in 1969, AMD focused on producing microprocessors and similar computer components. Initially, it merely licensed processor designs from other companies like Fairchild Semiconductor. Although it started producing other PC components developed entirely in-house early on as well, AMD wouldn't produce a processor it designed itself for several years.

MORE: Best CPUs
MORE: Best CPU Cooling
MORE: Intel & AMD Processor Hierarchy
MORE: All CPU Content

AM9080 And AM2900

In 1975, AMD created its first two non-licensed processor products. Technically, its AM2900 wasn't a processor; rather, it was a series of components used to build a 4-bit modular processor. It also produced the AM9080, which was a reverse-engineered clone of Intel's 8080 8-bit microprocessor.

The IBM Agreement

AMD's entry into the x86 processor market began in the early 1980s following an agreement between IBM and Intel. At the time, IBM was one of the largest computer manufacturers in the world and quite possibly the single largest producer of computer products. IBM was deliberating on several different processor designs to use in its upcoming products when it entered into negotiations with Intel. If Intel won the contract, it would secure a massive order for the company's processors for use inside of IBM-compatible PCs.

IBM was concerned, however, that the sheer number of processors that it needed would exceed the production capabilities of any single manufacturer, so it required Intel to license its technology to third-party manufacturers to ensure sufficient total volume. Intel, not wanting to lose the contract with IBM to a competitor, agreed to IBM's terms in 1981.

Following the agreement, AMD began producing licensed identical clones of Intel's 8086 processors in 1982.

AM29000 32-Bit RISC Processors

Throughout the 1980s and into the 1990s, AMD also produced a line of 32-bit RISC processors known as the AM29000 series. These processors were essentially the next generation of its earlier AM2900 products, however, and they were targeted more at the embedded market than high-performance computers. AMD designed the AM29000 using a variation of the Berkeley RISC architecture. Eventually, AMD discontinued work on the AM29000 series to focus on its x86 processor line.

AMD AM286

AMD's second x86 processor was the AM286, a licensed clone of Intel's 80286. Although the chip was architecturally identical, it had one advantage over its Intel counterpart: higher clock speeds. Where Intel capped the 80286 at 12.5 MHz, AMD pushed the AM286 as high as 20 MHz.

AMD AM286

AMD AM386: Legal Battles With Intel

In 1985, Intel released its first 32-bit x86 processor design, the 80386. AMD planned to release its variation, the AM386, not long after, but Intel held it up in court. Intel claimed that its cross-licensing agreement permitted AMD to produce copies of only the 80286 and older processor designs, but AMD argued that the contract permitted it to create clones of the 80386 and future x86 derivatives, as well. After years of legal battles, the courts sided with AMD, and the company was able to release its AM386 in 1991.

Although the AM386 is an 80386 clone, AMD released AM386 processors with clock speeds up to 40 MHz, whereas Intel's 80386 tapped out at 33 MHz. This gave AMD a performance advantage, and as it used the same socket and platform as the 80386, it gave customers an upgrade path to their aging systems.

AMD AM386

AM486 And AMD 5x86: The Final Clone

The last processor designed by Intel that AMD produced was the AM486 (80486), and it was released in 1994. Due to ongoing legal disputes between Intel and AMD, some versions of the AM486 use Intel microcode whereas others use microcode developed in-house by AMD. AMD followed a similar strategy with its AM486 as it did with the AM386, by pushing clock speed considerably higher than Intel. Although Intel's fastest 80486 processors were capped at 100 MHz, AMD went as high as 120 MHz on the AM486.

Not long after, in 1995, AMD also released its AMD 5x86. This processor used the same architecture as the AM486 and 80486, but it pushed the clock speed even higher. Retail models ran at 133 MHz, and OEMs had access to an even faster 150 MHz version.

Other notable changes in this line of processors was the addition of L1 cache, which helped to increase performance compared to the older 80386/AM386 CPUs. It also moved the FPU into the same package as the CPU, which also significantly improved performance. Prior to this, all FPUs were sold as separate hardware units and connected to the CPU through the motherboard.

Following the release of Intel's first Pentium processor around the same time also lead AMD and other competing CPU designers to introduce the PR or "Pentium Rating" system. This gave companies a simple way to advertise their products against each other and against Intel's Pentium. An example of this is the AMD 5x86 PR 75, which was advertised as having equivalent performance to a 75 MHz Pentium CPU.

AM486 And AMD 5x86

K5: AMD's First x86 Processor

In 1996, AMD released its first x86 processor designed entirely in-house. The fifth-generation x86 K5 processor used an innovative design that combined the execution hardware from AMD's discontinued AM29000 RISC processors with an x86 front end. Because the execution back-end hardware was based on a RISC design, instructions were decoded into micro-instructions that could be fed into one of five integer execution units or an integrated FPU.

AMD implemented an out-of-order speculative execution design as well, which helped to boost performance. The overall design was fairly complex, however, which limited AMD's ability to push up the clock speed, and the K5 was not able to surpass Intel's Pentium in terms of performance. It was considered relatively efficient, however, and AMD advertised 100 MHz K5 processors with a PR133 rating, meaning that AMD considered it to have equivalent performance to a 133 MHz Pentium.

AMD K5

K6: AMD's NexGen Processor

Instead of developing a new architecture to succeed the K5, AMD opted to purchase NexGen, a competing manufacturer of processors, and use its upcoming Nx686 design for the K6. Although the design was completely different than the K5, it was somewhat similar at a high level.

For example, like the K5, the K6 also used an x86 front-end to decode instructions into micro-operations that were then executed on internally RISC-like hardware. The K6 was released in 1997, and it was compatible with Socket 7 motherboards; clock-for-clock, it matched the performance of Intel's Pentium II, while also being considerably less expensive. It also included the important MMX SIMD instruction set.

The Pentium II did have one major advantage in that its FPU performance was better than the K6.

AMD K6

AMD K6-II

AMD's next processor was the K6-II. It was essentially an extended version of the K6 that could use a faster 100 MHz FSB, higher clock speeds, and new SIMD instructions. AMD introduced its 3DNow! SIMD instruction set as a competitor to Intel's MMX. Similar to AMD's older processors, the K6-II gave customers a clear upgrade path from the aging Pentium MMX processors, and as a result they were highly successful.

AMD K6-II

AMD K6-III: Integration Of L2 Cache

In 1999, AMD released its third-generation K6 processor, the K6-III. It was architecturally similar to the K6 and K6-II, but AMD added 256 KB of L2 cache on the CPU die. Prior to this, L2 was placed on the motherboard and accessed over the FSB, but the tighter integration significantly reduced latency and increased bandwidth. The K6-III was relatively expensive, however, and AMD quickly replaced it with the Athlon processor.

AMD K6-III

AMD K6-II+ And K6-III+

The last processors released by AMD in the K6 product line were the K6-II+ and K6-III+, which were targeted at the mobile market. These processors were similar to the K6-III in that they incorporated on-die L2 cache. The K6-II+ had 128 KB of L2, whereas the K6-III+ had 256 KB. Thanks to the use of AMD's 180 nm fab technology, these processors were relatively energy efficient.

AMD K6-II+ And K6-III+

AMD K7 And K75: The Birth Of Athlon

In 1999, AMD released its seventh-generation processor, the Athlon. It used a new architecture that increased IPC considerably and allowed AMD to push the clock rates up to 1 GHz. The FPU inside of AMD's previous processors had lagged behind competing Intel products, so improving the FPU was one of the primary objectives of the design team. This lead to the Athlon being equipped with an exceedingly powerful triple-issue out-of-order FPU that surpassed Intel's competing processors.

The first processor models placed the CPU core on a large silicon card. Instead of using on-die L2 cache, AMD used separate RAM chips soldered onto the same package as the CPU. This enabled AMD to install larger amounts of L2, but the cache ran at lower clock speeds.

Licensing DEC's EV6 FSB technology allowed AMD to design its own chipsets, leading to the first all-AMD platforms. Unfortunately, those first motherboards fell short of what Intel's competing 440BX could do. The EV6 FSB also made the Athlon compatible with new DDR RAM, which featured greater bandwidth and performance compared to traditional SDRAM.

AMD K7 And K75

AMD K7: Athlon Thunderbird

Not long after the release of AMD's Athlon on Slot A and Intel's Pentium II and III for Slot 1, the industry realized that the lackluster performance of the L2 cache was hampering CPU performance. To overcome this issue, AMD reverted back to a traditional processor package with its Athlon Thunderbird, which contained L2 cache integrated directly onto the CPU die. Although the L2 cache size was cut in half, it ran at the same speed as the CPU, drastically improving performance.

Thanks to a maturing 180 nm process and higher yields, AMD also took this opportunity to boost the clock speed of its CPUs by 400 MHz.

AMD Athlon Thunderbird

K7: AMD Duron

To target the entry-level segment and to make use of its lower yield chips, AMD introduced the Duron product line. These processors used the same architecture but generally ran at lower clock speeds. AMD also disabled all but 64 KB of the L2 cache on these processors, which reduced performance, but the Duron still was quite competitive against Intel's Celeron products.

AMD Duron

AMD K7: Athlon Palomino/XP

In 2001, AMD improved the Athlon again with the Palomino/XP. Little changed between the Thunderbird and the Palomino/XP, but the ever-maturing 180 nm process enabled AMD to push clock speeds up another 333 MHz. It also added support for the SSE SIMD instruction set. Microsoft's Windows XP launched around the same time, so AMD added "XP" to the Palomino code name to help advertise it towards users of the new operating system.

Versions of the Athlon Palomino/XP were also sold under the name "Athlon MP" for servers and "Athlon 4" or "Athlon XP Mobile" for laptop computers.

AMD Athlon Palomino/XP

AMD K7: Athlon Thoroughbred And Barton

In 2002, AMD rolled out the Athlon Thoroughbred, which was produced on a new 130nm process. This helped lower power consumption push frequencies over 2 GHz. As the process matured, AMD introduced the Barton a year later. Barton brought a modest clock rate increase, and it also doubled the size of the L2 cache and added support for 200 MHz FSB and 400 MHz DDR RAM.

AMD Athlon Thoroughbred and Barton

AMD K7: Athlon Thorton And Duron

Alongside Barton, AMD released two lower-end processors, the Athlon Thorton and a new Duron. Both processors used the same die as Barton but with part of the L2 cache disabled.

Thorton had 256 KB of L2 cache. similar to older Athlon processors, and it ran at slightly lower clock speeds than Barton. Thanks to the new 130nm fab technology, it was also more energy efficient than the older Athlon CPUs. The new Duron chip was limited to 64 KB of L2 cache, just like the previous Duron processors, but it was available at clock speeds up to 1.8 GHz, making the high-end models considerably faster than their predecessors.

AMD Athlon Thorton and Duron

AMD Geode: The APU Predecessor

AMD purchased the Geode processor line in 2003 from National Semiconductor to extend its low-end product offerings. The Geodes actually had roots in another company called Cyrix, which created the MediaGX product line in the late 1990s as a single-chip solution containing a general-purpose processor, sound chip, graphics accelerator and all of the hardware typically inside of a motherboard's chipset. When Cyrix went out of business, National Semiconductor picked up the MediaGX and transformed it into the Geode.

AMD launched two processors under the "Geode" name. At the extreme low-end was the Geode GX series, which was identical to the products sold by National Semiconductor. As a somewhat higher-performance solution, AMD also introduced the LX series, which contained several enhancements including the transition to AMD's K7 Athlon architecture for the CPU. These products were highly efficient and were used in several inexpensive and thin-client devices.

AMD Geode

AMD K7: First Sempron

AMD released its first Sempron-branded products in 2004. Initially, they slid in between the high-end Athlon Barton processors and the low-end Duron, filling roughly the same space as the Athlon Thorton. The first few models used either Thorton or Thoroughbred cores with the full 256 KB of L2 cache. These chips were capped at slightly lower clock speeds, with the fastest SKUs clocked at 2 GHz.

Just a few months after Sempron was introduced, AMD released a new version based on the Barton core with the full 512 KB of L2 cache and a higher 2.2 GHz clock speed.

AMD Sempron

AMD K8: Athlon 64!

In 2003, AMD shocked the world by introducing the first consumer-oriented 64-bit x86 processor. Codenamed "K8," these processors were essentially heavily modified variations of the K7. By moving to a 64-bit design, AMD was able to extend the memory support to a theoretical 1 TB.

Although that was more RAM than any K8 system would ever use, PCs were no longer limited to 4 GB of memory, and systems with 8 GB of RAM began showing up on the market. AMD also moved the memory controller from its chipset and integrated it into the CPU die. This drastically reduced memory latency and pushed performance up considerably over the K7. With the memory controller inside of the CPU die, this effectively removed the FSB from the system. Instead, AMD introduced its HyperTransport technology, which was capable of significantly greater bandwidth than the older FSB connection.

AMD sold the initial batch of K8 chips under the brand names "Athlon 64" for consumers (Clawhammer and Newcastle), "Athlon 64 FX" (Sledgehammer and Clawhammer) for enthusiasts and "Opteron" for servers (Sledgehammer).

AMD Athlon 64 Sledgehammer, Clawhammer and Newcastle

AMD K8: Gradual Improvement

In 2004, AMD introduced its new 90nm transistor process, which enabled the company to increase the performance of its Athlon 64 processors while also reducing power consumption. AMD produced a total of four 90nm Athlon 64 chips to cover the desktop market.

Venice became the last Athlon 64 processor released for AMD's Socket 754, and it also was the highest-performing chip available on that platform. AMD's San Diego ran at similar clock speeds, but was targeted at the Socket 939 platform and had a larger 1 MB L2 cache.

To target more efficient systems, AMD introduced the Winchester core around the same time, which had a lower TDP of 67 W. It was the most energy efficient Athlon 64 processor for several years until the release of the 62 W TDP Orleans in 2006 and the 65nm 45 W Lima in 2007.

AMD Athlon 64 Winchester, Venice, San Diego, Orleans and Lima

AMD K8: Sempron

Alongside the K8 Athlon processors, AMD also updated its Sempron product line with the new K8 architecture. Just like the first Sempron products, these CPUs typically had less cache and lower clock speeds than their Athlon counterparts.

AMD K8 Sempron

AMD K8: Athlon 64 X2

Just as it did two years prior, AMD pulled another shocker in 2005 with the introduction of a consumer-oriented dual-core processor based on the K8 architecture. Although the two processors were incapable of working on the same thread simultaneously, the second CPU core could handle other tasks and increase multitasking performance.

AMD produced a total of six CPU configurations in the Athlon 64 X2 product line, but the first five are all relatively similar to each other, varying only in L2 cache size and clock rate. The sixth Athlon 64 X2 design was the fastest in the series and the most energy efficient, owing to the move to 65nm transistor technology.

AMD Athlon 64 X2

AMD K8: Turion And Turion X2

AMD introduced a new mobile product line called "Turion" in 2005. These processors used the same architecture as AMD's desktop product, but thanks to careful core binning, they were able to operate with less power. AMD introduced dual-core variants as well, dubbed "Turion X2." 

AMD K8 Turion and Turion X2

AMD K10: Quad-Core Phenom

AMD's next architecture, K10, was a rather ambitious design. It is closely related to the K8, but it had several enhancements to the core and associated cache and memory controller. IPC was improved compared to K8, but K10's greatest advantage was its quad-core design that enabled it to run laps around the K8 dual-core CPUs in heavily-threaded applications.

Unfortunately, the K10 ran into problems early on. The first K10 processors were based on the Barcelona configuration and sold as Opteron server processors. But a flaw in Barcelona (known as the TLB bug) could cause the CPU to lock up. AMD was able to release a software patch to keep the TLB bug at bay. However, it imposed a sizable performance hit. Owing to the power requirements to run multiple CPU cores simultaneously, the K10 Phenom processors also struggled to run at higher clock speeds. The fastest quad-core model was limited to 2.6 GHz, whereas dual-core K10 processors sold under the Athlon brand name manged to reach just 2.8 GHz.

It should be noted that all first-generation K10 processors used the Agena die with part of the core disabled. Toliman, the triple-core variant, is actually the Agena die with one core disabled. The dual-core die was codenamed "Kuma," which is an Agena die with two cores disabled. Barcelona is identical to the Agena die as well, except that AMD fixed the TLB bug on Agena before releasing them to retailers. They were sold under the "Phenom," "Opteron" and "Athlon" product lines.

AMD Phenom

AMD K10: Phenom II

AMD managed to overcome the Phenom's shortcomings in the Phenom II. By transitioning to a 45nm process, power consumption dropped considerably, as did the amount of heat generated by the CPU, which enabled AMD to increase clock speed. Quad-core Phenom II processors based on the first Phenom II core, Deneb, managed to hit clock rates as high as 3.7 GHz. Because the die was significantly smaller than Agena, AMD was also able to triple the L3 cache size. Finally, Deneb transitioned to a DDR3 memory controller, but maintained backward compatibility with DDR2.

AMD Phenom II X4

AMD K10: Phenom II X2 and X3

Similar to the first-generation Phenom processors, AMD recycled its semi-defective quad-core CPU die as triple- and dual-core dies. These processors kept the full 6 MB of L3 cache, but they typically ran at lower clock speeds. They were popular among enthusiasts, since it was sometimes possible to reactivate the disabled cores.

AMD Phenom II X2 and X3

AMD K10: Athlon II

AMD also released a series of low-end K10 processors branded Athlon II. To keep production costs low, these processors used CPU dies without L3 cache. The quad-core die was code-named Propus, and the dual-core was called Regor. A triple-core model called Rana used defective Propus dies with a single core disabled.

AMD also used Deneb cores, but with the L3 cache disabled. This hurt performance, but with several CPU cores and clock speeds around 3 GHz, they still offered a reasonable experience.

Because L3 cache increased power consumption of the CPU as a whole, AMD also sold several Propus and Regor dies as mobile Phenom II and Athlon II processors.

AMD Athlon II

AMD K10: Sempron

AMD extended its Sempron line again to serve as the absolute lowest-performance product in the K10 line. The K10 Semprons used the single-core Sargas die, which was harvested from defective Regor cores. The second core could sometimes be activated on these CPUs.

AMD Phenom II X2 and X3

AMD Athlon II X2, Sempron

AMD K10: Phenom II X6

In 2010, AMD stepped up its K10 product offerings again by introducing the Thuban and Zosma CPU dies. Thuban had a total of six CPU cores, and AMD used it in processors clocked as high as 3.3 GHz. AMD also introduced its Turbo Core technology with Thuban, which allowed the CPU to push its clock rate up to 3.7 GHz depending on the workload. This enabled Thuban to surpass Deneb in multitasking performance while also matching it in single-threaded performance.

Zosma dies were harvested from partially defective Thuban cores, making them similar to Deneb, but with Turbo Core technology. Thanks to a matured 45nm process, Zosma and Thuban were also more energy efficient than Deneb.

AMD Phenom II X6 and Zosma Phenom II X4

AMD K10: Fusion/Llano

AMD's Fusion project came to fruition in July 2011, when the company released its first APUs, code-named "Llano." The design combined a large number of AMD's Radeon Stream Processors based on the TeraScale 2 architecture with the company's K10 CPU cores. The underlying concept was similar to AMD's Geode line, which hadn't been updated in years. But where the Geode was designed as a low-power/performance solution, Llano was meant to be a higher-performance product.

It was never meant to compete in the high-end, but the idea was to create a SKU that could give reasonable CPU and graphics performance all in one. Llano suffered from a lack of L3 cache, and the iGPU was far too slow to keep most gamers happy, but for casual gamers that didn't mind lower graphics settings, it performed well enough.

AMD Llano

AMD Bobcat

To be more competitive with Intel's Atom and ARM's low-power microprocessors, AMD introduced its Bobcat architecture in 2011. Since Bobcat was designed to be efficient, it ran at fairly low clock speeds; the highest-performing model reached 1.75 GHz. Bobcat is technically an APU, and it contains an iGPU with 80 Stream Processors based on the TeraScale 2 architecture. The iGPU is clocked rather conservatively as well in order to keep power consumption low.

AMD Bobcat

AMD Bulldozer: Zambezi

In October 2011, AMD introduced the successor to its K10 architecture, code-named "Bulldozer." With Bulldozer, AMD attempted to use high core count and clock speed to outperform Intel's recently-released Sandy Bridge. The cost of this clock rate-focused design, however, was a marked drop in IPC compared to the K10 architecture, and the design has been plagued with problems. The first Bulldozer chip, code-named Zambezi, was not able to cleanly out-perform Thuban Phenom II X6 CPUs, let alone beat Sandy Bridge. Part of the problem came from the use of a Multi-Core Module (MCM) that contains two integer cores and one FPU. As the two integer execution units have to share the FPU, this can lead to stalls in the pipeline.

The design has also been criticized for being power-hungry and running too hot, though that stems from direct comparisons between Bulldozer and Sandy Bridge.

AMD Bulldozer Zambezi

AMD Piledriver: Trinity And Richland

A year after Bulldozer debuted, AMD released a revised architecture known as Piledriver. Piledriver was initially released with Trinity, the company's second-gen APU. It saw clock speed increase by about 10 percent, and that, in conjunction with architectural enhancements, pushed performance up by roughly 15 percent without increasing power consumption.

On the iGPU side, Trinity moved to the TeraScale 3 architecture used inside of AMD's Radeon HD 6900-series GPUs. This helped to increase graphics performance over Llano.

Richland, in turn, was a slightly improved Piledriver part. It performed just slightly better than Trinity due to higher clock speeds. It also managed to reduce power consumption and heat somewhat. The performance gap between mobile Trinity APUs and mobile Richland APUs was greater than on the desktop, owing to the improved thermals and power consumption.

AMD Trinity And Richland APUs

AMD Piledriver: Vishera

AMD also applied its Piledriver architecture to the FX family, displacing Zambezi in favor of Vishera.

AMD Bulldozer Vishera

AMD Steamroller: A GCN APU

In 2014, AMD updated its APU line again with the new Steamroller architecture. AMD shifted to a new 28nm process that favored chip density over clock speeds in order to be more compatible with its graphics technology. The CPU demonstrated a reasonable increase in IPC over its predecessor, thanks in part to a larger L1 cache and additional internal registers. It wasn't able to hit the same clock speeds as Richland though, so overall performance didn't increase much.

The graphics side of the APU improved drastically, however, owing to the new transistor technology, an increase in shader count, and a move to AMD's GCN GPU architecture. The APU featured a number of other enhancements, such as being the first HSA-compatible APU, the addition of AMD's TrueAudio DSP technology and support for PCIe 3.0.

The first Steamroller APUs use a configuration known as Kaveri. The APU line was later refreshed with Godavari, which benefits mostly from higher clock speeds.

AMD Jaguar

AMD introduced its Jaguar architecture in 2014 to replace the aging Bobcat core. Jaguar increased the CPU core count to four and moved to a faster GCN-based graphics processor with 128 shaders. IPC shot up by roughly 15 percent as well, alongside a boost in clock speed. Overall, Jaguar is significantly faster than Bobcat in every way.

The Jaguar architecture in also used inside of the Xbox One and Playstation 4. The models inside of these game consoles have significantly higher core counts on both the CPU and iGPU, however, and Jaguar-based products available in other devices are considerably slower.

AMD Jaguar

Excavator: The End Of Bulldozer

The last architecture that AMD plans to produce based on Bulldozer is known as Excavator, which is used inside of AMD Carrizo-based APUs. Relatively few of these products have been released thus far, so we can't be sure what the clock speed limit will be on these parts. Carrizo is designed to have significantly higher transistor density (than prior Bulldozer-based processors), which helps to reduce the die area and lower power consumption. AMD reworked the cache inside of Excavator, too.

The processor has less L2 cache, but twice as much L1 cache when compared to Steamroller. Because the L1 cache is several times faster than the L2 cache, this helps to boost IPC performance. The branch prediction target buffer was increased by 50 percent as well, to 768 KB, which further helps to improve performance. The graphics processor also gained 512 KB of dedicated L2 cache to increase graphics processing power. Rearranging the cache on the APU also helped to lower the power consumption, as cache tends to be fairly power hungry, and this new configuration has less overall cache on die.

AMD Excavator

Ryzen: AMD Reborn

AMD lost ground to Intel in essentially every area of the CPU market during the Bulldozer years. The company lost significant financial resources and had to sell its silicon fabs. With an uphill battle to remain in the processor market, AMD put its hopes on Ryzen.

The top end Ryzen processor, Ryzen 7 1800X, has eight CPU cores clocked at 3.6 GHz. The CPU can also accelerate up to 4.1 GHz in certain work loads. The eight cores are organized into two partitions. Each partition has 8MB of L3 cache, and each core has a dedicated 512KB L2 cache, a 64KB L1 instruction cache, and a 64KB L1 data cache. This gives the Ryzen 7 1800X a total of 16MB of L3, 4MB of L2, and 1MB of L1 cache.

In Ryzen, AMD implemented its first micro-op cache, which can store recently used instructions, improving performance and reducing pipeline stalls. Ryzen processors also support Hyper-Threading, which allows cores to handle two threads simultaneously. The company's processor debuts alongside the new AM4 socket, adding support for DDR4 RAM.

Ryzen 7 was closely followed up by its Ryzen 5 processors, which are created from semi-defective Ryzen 7 cores. Ryzen 5 is available in quad- and hexa-core variants and at similar clock speeds to Ryzen 7.

AMD Ryzen

MORE: Best CPUs
MORE: Best CPU Cooling
MORE: Intel & AMD Processor Hierarchy
MORE: All CPU Content

Google revealed more details about the performance of its Tensor Processing Unit (TPU), the company’s first machine learning chip. According to some benchmarks Google performed on its TPU, Haswell server CPUs, and Nvidia Tesla K80, the TPU chip came up 15-30x faster and up to 80x more efficient than those other chips.

How The TPU Was Born

Back in 2006, Google’s engineers discussed deploying GPUs, field-programmable gate arrays (FPGAs), and custom application specific integrated circuits (ASICs) in their data centers for machine learning applications. However, at the time, they concluded that their machine learning applications didn’t require enough computation to warrant developing ASICs.

This changed in 2013, when the engineers realized that the company’s use of deep neural networks (DNNs) was exploding, and that it would soon need to double its data centers if the growth in usage of DNNs continued.

Google’s engineers then decided to prioritize building a custom ASIC for inference, which is running neural networks that have already been trained on off-the-shelf GPUs. They called this ASIC a “Tensor Processing Unit” (TPU) because it’s tailored for Google’s open source TensorFlow machine learning software library.

How The TPU Is Built

Because Google was in a rush to deploy the TPU, the company didn’t integrate it tightly to CPUs and instead connected the TPU to the processors via the PCIe I/O bus. This allowed the TPU to plug into servers just as a GPU does. However, the host server has to send the instructions to the TPU rather than the TPU fetching the instructions itself, which means it’s closer in spirit to a floating-point unit co-processor than a GPU. This was also done to simplify design and debugging.

Although it’s a custom ASIC, a type of chip typically designed to run a limited set of instructions, Google said that it has some of the flexibility of an FPGA. This means it can be programmed to handle multiple types of neural networks. Therefore, even if Google’s future needs will require different types of machine learning algorithms, the TPUs should be flexible enough to adapt.

Plus, given the performance advantage the TPUs seem to offer over CPUs and GPUs, the company will likely continue to build new generations adapted for whatever machine learning technology is most advanced at the time.

TPU Performance Metrics

Google’s engineers said in a paper about the TPU that the most important metric it considers when buying chips for its data servers is not the peak performance of a chip, but the cost-performance metric - or, more specifically, the total cost of ownership (TCO). TCO is correlated with power use, as the more power a chip uses, the more its TCO rises over its lifetime.

Google used two performance/Watt metrics to compare the power draw of the TPU to that of the Haswell CPU and the K80 GPU. One is the total-performance/Watt metric, which includes the power used by the host server CPU when combined with either a K80 GPU or a TPU. The other is the incremental-performance/Watt, which only refers to the power used by the K80 GPU or the TPU.

A system that includes a Haswell server chip and an Nvidia K80 GPU has 1.2-2.1x the total-performance/Watt of the Haswell CPU alone, while an K80 GPU has an incremental-performance/Watt of 1.7-2.9x compared to a Haswell CPU.

At the same time, a Haswell/TPU server has 17-34x better total-performance/Watt compared to a Haswell CPU, and a relative incremental-performance/Watt of 41-83x for the TPU alone. That also means the TPU has 25-29x the performance/Watt of a K80 GPU.

Google also claimed that its TPU can achieve 15-30x inference performance compared to the K80 GPU and the Haswell CPU.

What To Expect From Future TPU Chips

The TPU was manufactured on a 28nm planar process and has been in use since 2015. If a next-generation TPU is made on a 14nm process, it could see a 2x improvement in performance/Watt just from that jump alone, as we’ve already seen from AMD and Nvidia’s 14/16nm GPUs.

Google also said if it had taken an extra 15 months to have designed better logic--which is how long it took to design the first TPU-- it could’ve increased clock speeds by another 50%. That could be a clue that if Google is indeed working on a new generation, that kind of design would be included in it.

Because the company rushed to integrate the TPU quickly in its data centers, it used whatever memory and interconnects were available. However, it said that if it were to use 4x as much bandwidth for its servers’ memory, it could increase the performance of the TPU by another 3x.

Google hasn’t specifically talked about its plans to build a new TPU chip, but going by the performance/Watt of the first generation and how much room there is to improve it, chances are it won’t leave this opportunity on the table. The use of machine learning for all of the company’s services is only going to increase over the next few years, making such chips even more necessary than they are today.

Specifications And Features

The Silicon Motion SM2258 controller is already shipping with 2D NAND in Intel's 540s (consumer) and 5400s (professional) SSDs. Intel leveraged the SM2258's powerful low-density parity check for one last gasp with 2D NAND, but we expect to see the SM2258 ship in several new products as IMFT 3D flash becomes widely available.

At Computex 2016, we spoke with several Tier 3 SSD manufacturers, which are companies without NAND flash manufacturing or SSD controller intellectual property, that were evaluating the SM2258 for future SSD designs with the new IMFT (Intel/Micron Flash Technology) 3D NAND. Silicon Motion, Inc. (SMI) built a good working relationship with both Intel and Micron by supplying them with controllers for existing and upcoming SSDs, so it doesn't just have a front row seat for the 3D NAND show; it is actually in the ring with IMFT's new 3D flash.

SMI has already committed to building the SM2260 NVMe controller for Micron's new Ballistix gaming brand, which features the company's new 3D multi-level cell (MLC) flash. The relationship helped the company gain working knowledge of the new flash, while some other controller manufacturers are still waiting to get a sample so they can build a prototype controller.

Let's take a first look at the entry-level SM2258, which now supports IMFT's 3D TLC flash.

Technical Features

To build the controller, SMI had to master two disciplines that are often at odds with each other. The first hurdle was to develop a new custom controller for the entry-level SSD market, which is the segment where the model with the lowest price often dominates sales. The second challenge was to develop and incorporate new technologies that allow low-cost, low-endurance 3-bit per cell flash to thrive under consumer SSD conditions through the warrantied period. The trick is to blend low cost and high technology into one design.

Architecture

• 32-bit RISC CPU
• High-efficiency 64-bit system bus
• Automatic sleep and wake-up mechanism to save power
• Built-in voltage detectors for power failure protection
• Built-in power-on reset and voltage regulators
• Built-in temperature sensor for SSD temperature detection
• Supports JTAG interface, UART (RS-232) interface, and I2C interface for on-system debug

Host Interface

• SATA Revision 3.1 Compliant
• ATA/ATAPI-8 And ACS-3 Command Compliant
• SATA interface rate of 6Gb/s (backward compatible to 1.5Gb/s and 3Gb/s)
• Native Command Queuing up to 32 commands
• Supports SATA device sleep (DevSleep)
• Data Set Management command (TRIM)
• Self-Monitoring, Analysis, and Reporting Technology (S.M.A.R.T.)
• Supports PHY Sleep mode (CFast PHYSLP)
• Supports 28-bit and 48-bit LBA (Logical Block Addressing) mode commands

Data Protection And Reliability

• Supports ATA8 security feature set
• Supports data security erase and quick erase
• Proprietary NANDXtend error-correcting and data protection technology triples the P/E cycles for 3D TLC SSD devices
• Internal data shaping technique increases data endurance
• Software/Hardware write protect option
• StaticDataRefresh technology ensures data integrity
• Early weak block retirement option
• Global wear leveling algorithm evens program/erase count and extends SSD lifespan

NAND Flash Support

• Supports 1z nm TLC and 3D MLC / TLC NAND
• Supports ONFI 3.0, Toggle 2.0, and Asynchronous interface
• Supports 1.8V/3.3V Flash I/O
• Supports 8KB and 16KB page size
• Supports 1-plane, 2-plane, and 4-plane operation
• 4-channel flash interface supports up to 32 NAND flash devices

DRAM Interface

• 16-bit wide DRAM interface
• Supports DDR3/DDR3L

SMI used its proprietary NANDXtend low-density parity check (LDPC) error correction codes with the SM2258. Error correction is the core technology that allows SSD manufacturers to build new low-cost SSDs with lower quality NAND. The dirty secret is that NAND endurance has decreased with each new lithography shrink, and LDPC provides both soft and hard decode options to boost endurance beyond the raw error rate.

In theory, IMFT's 3D flash was supposed to reset the clock on NAND endurance, but some SSD manufacturers are still preparing for 1,000 to 3,000 program/erase cycles without sophisticated error correction techniques.

NANDXtend is not a new technology. SMI used it on the SM2256 controller that it designed for planar TLC flash. Silicon Motion continues to improve on the LDPC code to deliver even more endurance and efficiency while reducing power consumption.

StaticDataRefresh is another proprietary technology from SMI, but other companies have similar features. The technique keeps your data from suffering from voltage drift, which occurs when the eight cell charge levels (with TLC) move around. The "drift" forces the controller to use robust ECC techniques to read the data properly when the voltages get close to the next charge level, but the extra steps increase latency and slow down read performance. StaticDataRefresh technology monitors the voltages and gives a quick refresh as needed to keep read performance high over time.

The SM2258 brings other improvements over the year-old SM2256 controller. We first talked about new direct-to-die writing schemes with the competing Phison's S10 controller, but SMI has a similar "direct-to-TLC" technology. Both work the same. When the SLC-programmed buffer gets full, the SSD starts to write the incoming data directly to the TLC flash. In previous SSDs, all of the incoming data passed through the SLC buffer before the SSD wrote it to the TLC layer. This technique decreased wear on the flash, but the 'fold' method forced the SSD to slow down the incoming data once the fast SLC buffer was full. The fold method allowed the SSD to make space available for more incoming data, but it occurred while the SDD was pushing data to the slower TLC area.

The SM2258 controller reports a large number of SMART readings. Our sample may have a link to the next-generation BX300. The BX series is Crucial's entry-level offering that also uses Micron flash. In the past, Crucial used SMI controllers for the BX series.  At this time, there is not a guarantee the BX300 will ship with Silicon Motion's SM2258 controller, and neither company has released a public comment about a BX300 design win.  

A Closer Look

IMFT 3D TLC flash is the world's first 384Gbit die, which equates to 48GB per die. The NAND provides 1.5x the capacity of 256Gbit MLC flash, which was simply the next evolution of the older 128Gbit die. The odd density means that SSDs with the flash will have very strange configurations. Most 256GB SSDs on the market use four or eight packages, but the SM2258 reference design we have on hand features six packages. Each package contains a single 48GB NAND die for a total of 288GB of raw capacity. 

Companies can slice the 288GB pool into 256GB of addressable capacity with 32GB reserved for background activity, or 240GB of capacity with 48GB reserved. The Crucial MX300 ships with 275GB of capacity, but we suspect other SSD manufacturers will choose higher spare area because of the performance benefits.

This should mark the end of 128GB SSDs for most markets, but it shifts low parallelization (AKA slower) SSDs into the 256GB capacity class. 256GB SSDs will soon become obsolete for most of our readers, and 512GB SSDs will take the helm for mainstream use. Even exotic 2TB models are becoming more common.

The SMI SM2258 controller supports 4-channels with 8 CE, which means it supports up to 1536GB of NAND with 384Gbit die. Micron already disclosed some details of its next generation 3D TLC, which is expected sometime in 2017. The new stack doubles from 32-layers to 64-layers, and the die density increases from 48GB to a whopping 96GB.

The extra flash capacity means the controller needs to address more DRAM to cache the flash translation layer data. Our SM2258 prototype sample has pads for two DDR3/DDR3L packages.

Micron's 3D TLC flash holds three times more data than the company's densest planar TLC. To get mainstream performance, SSD manufacturers will need to focus on 512GB-class products as the starting point. Anything under that capacity will suffer from higher latency and lower sequential performance during nearly all workloads.

To drive the point home, the SMI SM2258 prototype we are testing has the same parallelization as many current 64GB SSDs. When was the last time we talked about a fast 64GB SSD, or even any SSD at that capacity? That is the difference that IMFT's leap to 384Gbit made with TLC NAND.

MORE: Best SSDs

MORE: Latest Storage News

MORE: Storage in the Forums

Benchmarks And Comparisons

Comparison Products

We built a diverse group of low-cost SSD products to compare with the product under review. Most companies started pushing higher capacity products over the last year, so our stable of 256GB SSDs has not seen a significant refresh in some time.

The Mushkin Triactor is the newest retail 256GB-class SSD in our tests, and we are working on a full review of the 240GB and 480GB models for a future release. The other products in this review have all shipped for at least the last year.

The Samsung 850 EVO 250GB is the premium product in this group, even though it is a mainstream SSD that often sells at entry-level prices. The Crucial MX200 256GB and Plextor M6V 256GB both utilize planar MLC flash. The Plextor uses a Silicon Motion SM2246EN controller that was very popular from 2014 to early 2015.

Sequential Read Performance

To read about our storage tests in-depth, please check out How We Test HDDs And SSDs. Four-corner testing is covered on page six of our How We Test guide.

The SMI SM2258 with Micron 384Gbit TLC excels with sequential data reads, and it is just as fast as the Samsung 850 EVO 250GB with Samsung's 64Gbit-per-plane 3D TLC. Sequential reads under these conditions are rarely a problem for SSDs, and even modern low capacity products manage to break the 500 MB/s mark.

Sequential Write Performance

Sequential write performance is another story. Micron's new 3D TLC packs a quad-plane die to increase performance, which exceeds Samsung's dual-plane 3D TLC flash. The direct-to-TLC write technology keeps write performance steady, and we didn't observe any large performance drops throughout the sequential tests. The SM2258 prototype outperformed the Samsung 850 EVO 250GB at all queue depths. It's rare for an entry-level product to dominate the 850 EVO series in any test.

Native TLC Sequential Read Performance

The direct-to-TLC algorithm keeps 128KB block sequential write performance fast through the first 100GB of the SSD during our full-LBA-range write test. After the data fills the SLC buffer and secondary layer, the performance drops to a low rate and fluctuates between 20 MB/s and 75 MB/s.

Random Read Performance

The random read performance was much lower than we expected, especially compared to the impressive sequential performance. The queue depth 1 read performance is average for many of the new low-cost SSDs. The SM2258 scales well to queue depth 4, but the large jumps in performance slow down at higher queue depths.

The MX300 and the SMI prototype are the only two products we've tested with Micron's new 3D TLC flash. Neither product managed to breach 10,000 random read IOPS at a queue depth of 1. Without reaching that mark, we couldn't place either product in the modern mainstream SSD category. It is interesting that Silicon Motion's controller is faster at QD1 random reads than the MX300 750GB we tested. It will be very interesting to see what the SM2258 controller can do with more than just six die to address at one time, and it wouldn't be the first time a BX-series product outperformed the current mainstream MX series. 

Random Write Performance

The SM2258's random write performance at low queue depths is in line with other products in the chart, including those with MLC flash. The controller does a really good job of keeping performance high. Heavy workloads usually saturate the SLC buffer, but that doesn't happen with the SM2258 due to excellent buffer management.

80 Percent Sequential Mixed Workload

We describe our mixed workload testing in detail here, and describe our steady state tests here.

The high sequential performance for both reads and writes shines through in the light-use mixed workload. The difference between the SM2258 prototype and the 850 EVO in this test surprised us. Could SMI be in a position to overtake the long-standing mainstream performance leader with the help of Micron's 3D TLC?

80 Percent Random Mixed Workload

Apparently, it's still too early to go that far. SMI needs to address the SM2258's low random performance before anyone can make that claim. We see how low performance in the 100-percent read and write tests compounds during mixed workloads during this test. The results will have an impact on the real-world application performance later in the review.

Sequential Steady-State

Earlier, we looked at sequential write steady state performance with HD Tune Pro. SMI appears to trade a large buffer for longer recovery times. Most products armed with the SM2258 controller will fall into the entry-level to mainstream product category, so most users will not use this combination for professional applications with heavy drive writes. This test reveals that it takes quite a bit of time to recover once a user gets a drive into a degraded state.

Random Steady-State

The random steady state test focuses more on performance consistency than the data rate. The SM2258 delivers fairly consistent random performance, but the low performance means it's not a good product for RAID 0 arrays with desktop PCs.

MORE: Best SSDs

MORE: Latest Storage News

MORE: Storage in the Forums

Performance And Conclusion

PCMark 8 Real-World Software Performance

For details on our real-world software performance testing, please click here.

The SMI controller has reduced mixed random performance at lower queue depths, which has a real impact on application performance. We've seen this tendency many times in the past with entry-level products. Companies build controllers, even some with as many as eight cores, that perform really well with sequential data, but they lack either high random read or write performance. It's important to provide balanced performance, but companies should start by mastering random read performance.

Application Storage Bandwidth

In this chart, we combined the results of the ten PCMark 8 tests to determine the average throughput. The SM2258 with Micron 3D TLC compares well to the other products in the chart, but it's important to remember the difference of the parallelized die. In time, we will see products with this combination of components for sale and the price should be well under the current 256GB-class products. 256GB SSDs already sell for as low as $55, and we suspect that prices will dip into the $40 to $45 range before the end of the year for SSDs that use 3D flash technology.

PCMark 8 Advanced Workload Performance

To learn how we test advanced workload performance, please click here.

We discussed the slow recovery time during the sequential steady-state test, but now we get to see it in practice with real-world applications. These tests measure moderate and heavy workload performance in two states. The first phase of the test fills the drives with data to create a very dirty state (degraded), and the second phase (recovery) provides five minutes of idle time in between each test. The SM2258 doesn't recover completely in that amount of time, so its throughput performance could increase beyond what we recorded during the test.

We may also see an artificial limitation of Micron/Crucial's Dynamic Write Acceleration. The dynamic portion of the algorithm shrinks the SLC buffer as the drive fills. This test intentionally builds up dirty cells by filling the drive before it measures heavy loads, so the SLC buffer is smaller than it would be during most consumer workloads.

Total Service Time

The Crucial MX200 also suffers during the service time test, which adds weight to the theory that dynamic write acceleration issues, which we've observed with many Crucial SSDs dating back to the Micron M600, are cropping up. The M600 was the first SSD released with Dynamic Write Acceleration (DWA), and the first we tested with the feature. Crucial has used DWA technology sparingly since the M600's 2014 product release, and the feature has provided varying results in our testing.

Disk Busy Time

The disk busy time mimics the service times with minimal variation.

Notebook Battery Life

I suspect SMI has yet to optimize the SM2258 firmware for power consumption. We've tested a number of early products, both for preview articles and for private tests, to determine where a drive is during development. Power optimization and steady-state performance are usually the last stop before a controller moves to mass production (MP) firmware.

Conclusion

We're thankful to have the opportunity to test the SMI SM2258 controller with Micron's new 3D TLC flash. Micron hasn't delivered a lot of 3D flash to customers, so this is a rare opportunity to gauge the state of development with a combination of components we're sure to see a lot of in the future.

SMI is very close to distributing the SM2258 controller for Micron 3D TLC to SSD manufacturers. We found some behavior that indicates SMI has yet to complete some final optimization work, but the combination is mature enough to survive our testing with solid entry-level performance results.

We've discussed our early testing in other product reviews, and most of the early products fail to complete all of the tests before dying from one issue or another. We can report that our SMI SM2258 sample survived the full test suite, including our extended tests, and it still works. Taken alone, that may not seem like a big deal to many of our readers, but we usually kill three out of four early look, prototype-like SSD samples. In the last three weeks, two of three products expired during testing, and we even buried a retail product. SMI retail products have a long history of excellent service in the field, and we rarely hear of any retail SSD failures with its controllers.

Most of our observations revolve around the performance of the SMI/Micron hardware combination. We discussed the 384Gbit die and how it hurts parallelization and performance in low capacity SSDs, and the 240GB drive we tested is a good example of the issue because it is equivalent to the modern 64GB SSDs that ship with a 128Gbit die. We wouldn't even test a 64GB SSD today, and we try to avoid 128GB drives. We will take a serious look at removing 256GB-class SSDs from our charts in 2017. When the time comes to exit the 256GB market, the prices will be very low. We suspect Micron 3D TLC-enabled SSDs for the entry-level market will drop into the $40 range by the end of the year. The price is right, but the performance won't be sufficient for most of our readers.

Crucial recently disclosed the remaining capacities and performance for the MX300 series. The MX300 275GB lists performance at 530/500 MB/s sequential read/write, which is less than what Silicon Motion managed with the SM2258 controller. Even in this early stage of development, the SM2258 controller also managed to outperform the MX300 275GB in random performance tests. We were surprised to learn that Crucial chose the Marvell Dean controller to pair with 3D TLC in its MX300 series. Now we know that, other than speeding time to market, it may not have been the best option available.

MORE: Best SSDs

MORE: Latest Storage News

MORE: Storage in the Forums

Follow us on Facebook, Google+, RSS, Twitter and YouTube.

The USB Promoter Group announced a new cryptographic authentication protocol for USB Type-C devices that should put an end to faulty as well as malicious Type-C chargers and devices.

The USB Type-C standard was designed for both charging and data transfers as a convenience feature to allow people to carry fewer cables with them and to help device manufacturers cut costs.

However, once the two were combined, the risk that people would become infected by plugging their laptops and smartphones with strange USB Type-C chargers or devices also increased. The USB devices could have embedded malware, which could infect host devices. The chargers could also be uncertified and use lower quality standards, which could risk damaging the host notebooks or smartphones.

The new authentication protocol for USB Type-C aims to fix both problems by allowing users to set policies that would restrict their devices to using only USB chargers that are compliant with the standard or automatically block them until their authenticity has been confirmed. The verification will be done right when the cable is connected, before any power or data is transmitted to the host device.

The new authentication solution includes several key characteristics to achieve that goal:

A standard protocol for authenticating certified USB Type-C Chargers, devices, cables and power sourcesSupport for authenticating over either USB data bus or USB Power Delivery communications channelsProducts that use the authentication protocol retain control over the security policies to be implemented and enforcedRelies on 128-bit security for all cryptographic methodsSpecification references existing internationally-accepted cryptographic methods for certificate format, digital signing, hash and random number generation

It’s not yet clear if this solution also stops the BadUSB vulnerability uncovered two years ago at the BlackHat hacker conference. BadUSB allows malware to infect USB devices, which are then almost impossible to clean up, because the malware embeds itself into the firmware of the device. If the infected USB devices are then plugged into other systems, those systems can also become infected, thus spreading the infection. We’ve contacted the USB Implementers Forum for further clarification about this issue.

Consumers won't have to look for anything new in the new USB Type-C devices they buy, but the manufacturers of such devices will have to update them to the USB Power Delivery 3.0 specification.

Lucian Armasu is a Contributing Writer for Tom's Hardware. You can follow him at @lucian_armasu. 

Follow us on Facebook, Google+, RSS, Twitter and YouTube.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, announced that the CPU in its PIC32MZ family has been upgraded to MIPS M5150, Imagination's latest M-class (microcontroller) processor.

Hardware

The new MIPS-based Microchip PIC32MZ EF MCUs bring a clock speed of 200 MHz and a 330 DMIPS peak performance. They also include an integrated hardware floating point unit (FPU) for fast single- and double-precision math, 16 KB I-cache and 4 KB D-cache, up to 512 KB high-speed SRAM, and 2 MB flash.

The MIPS M5150 processor comes with a 5-stage pipeline based on a Harvard architecture with separate buses for instructions and data. It also has other MIPS32 Release 5 features including new instructions for enhanced functionality, secure debugging, and a DSP engine.

Software

The MIPS M5150 supports the microMIPS ISA, which contains most of the MIPS32 instructions in a new 32-bit encoding scheme, with some instructions also encoded in 16-bit format. This has the advantage of higher code density thanks to the 16-bit instructions, while also maintaining similar performance to the MIPS32 mode.

Security

One of the best features of Imagination's latest CPUs, including this M5150 microcontroller processor, is the OmniShield domain isolation system. It can keep up to seven separate operating systems and groups of applications running in parallel and isolated from each other. This can ensure that if one of the domains gets infected with malware, it can't affect the other domains.

Such isolation is one of the best and more practical ways to limit the spread of malware, whether it's in home computers (like with attempts from Qubes OS), enterprise systems or "Internet of Things" (IoT) devices, which many security experts expect to make the world a less safe place as they proliferate.

Microchip's PIC32MZ EF MCUs also bring a random number generator, a crypto engine for fast encryption/decryption, and advanced memory protection.

Imagination believes that chips such as Microchip's PIC32MZ EF family can shorten the time to market for device manufacturers and can bring much-needed strong security to the IoT world.

According to Imagination, there are already multiple development boards in production that are using the Microchip PIC32MZ EF MCUs, including the new version of the Arduino-compatible Digilent chipKIT Wi-FIRE development board.

Follow us @tomshardware, on Facebook and on Google+.

While the new Maxwell architecture leads the company's gaming portfolio, Nvidia has re-spinned the previous-generation Kepler GPU in order to produce the GK210 that powers the new Tesla K80 card for GPGPU accelerated computing applications.

The new GK210 is a modified version of the GK110B found in the Tesla K40, but with doubled-up register file and shared memory cache. The goal is to give applications more resources to enable more registers per thread without compromising the total number of threads that an SMX can process, reducing latencies and improving efficiency.

Note that the GK210 processors in the K80 have two of their 15 SMX blocks disabled, limiting the card to 4,992 CUDA cores (2,496 per GPU). This might not look as impressive as the Titan-Z, but keep in mind that the Tesla K80 is passively-cooled, with a tighter focus on performance-per-watt and limited at a 300 Watt TDP.

Of course, the Tesla K80 has other tricks up its sleeve, like an astonishing 24 GB of total graphics memory onboard, or 12 GB per GPU. At 5 GHz effective over a 384-bit memory interface, the GDDR5 RAM provides an aggregate 480 GB/s of bandwidth (240 GB/s per GPU). It's highly doubtful that we'll see a GeForce card ever carry the GK210, but when we asked, the company didn't rule out the possibility of a future Titan card powered by this graphics processor.

With two GPUs, it's no surprise that performance is significantly higher than that of the single GPU-equipped Tesla K40 card released last year. The Tesla K80 is available now for "high-performance computing, computational science, supercomputing, enterprise, complex data analytics and machine learning applications", according to Nvidia. The card has no MSRP, as the company let us know that OEMs set the price, but we can expect it to be significantly more expensive than the Tesla K40 12GB card that currently ranges between $3800 and $6400 on Amazon.com.

Follow us @tomshardware, on Facebook and on Google+.

VisionTek Products revealed on Thursday that its latest pocket-sized storage device is more than an ordinary thumb drive; it's a bus-powered SSD aimed at professionals and performance enthusiasts alike. The stick-shaped SSD is available now in capacities of 120 GB and 240 GB.

So what makes this storage device different than other pocket SSDs and thumb drives? The device includes an LSI SandForce controller enabling read speeds of up to 455 MB/s and write speeds of up to 440 MB/s. The drive also has a USB 3.0 connector, resulting in super-fast file transfers when connected to a PC's USB 3.0 port.

According to the company, the drive is encased in aircraft-grade aluminum, keeping your stored data safe and secure. The drive is also capable of playing host to a copy of Windows 8 or higher. Simply download and install the company's Boot Camp drivers, and then install the operating system on the SSD stick. This means users can boot up into Windows without the need for partitioning the local hard drive.

"This new line of ultra-portable drives delivers among the highest levels of reliability and performance in an SSD, but adds an incomparable level of convenience. Imagine…over 400MB/s of reliable storage speed that can attach to [a] key ring and can provide a full Windows environment wherever you require it," said Mark Bilson, Executive Vice President of VisionTek.

VisionTek indicates that this SSD-on-a-stick is ideal for downloading and saving uncompressed HD content. Parents can even use the stick to create a safe environment for their kids. Does your tablet or smartphone support USB OTG? Connect the drive and quickly back up your pictures and videos.

VisionTek's new SSD competes directly with the likes of Corsair, which offers the Flash Voyager GTX. Corsair's storage device, sold in 128 GB ($134.99) and 256 GB ($264.99) capacities, also utilizes an SSD controller. The drive is even encased in a durable brushed metal housing, and provides USB 3.0 connectivity. Read speeds are up to 450 MB/s and sequential write speeds are up to 360 MB/s.

But what seems to make VisionTek's solution stand out against the Corsair product is its ability to boot into a full Windows environment. That said, users can move from one computer to another with a full copy of Windows intact, and don't need to bother with re-saving configurations, files and so on. You can even run Windows 8 on a Mac computer thanks to the SSD.

Customers can buy VisionTek's 120 GB model now for $109.99, and the 240 GB version for $174.99. They're available at VisionTek, Dell, Newegg and Tiger Direct.

Follow Kevin Parrish @exfileme. Follow us @tomshardware, on Facebook and on Google+.

Three New CPUs For Enthusiasts

Editor’s Note: Eager to show off what it's doing with Intel’s Haswell-E architecture, system builder CyberPower PC is offering the Tom’s Hardware audience an opportunity to win a complete system based on Intel’s Core i7-5820K processor. Read through our review, and then check out the last page for more information on the configuration, plus a link to enter our giveaway!

A little more than 10 years ago, Intel introduced the Pentium 4 Extreme Edition 3.4 GHz. It boasted one Hyper-Threaded core, 512 KB of L2 cache, a 2 MB L3 cache, and a quad-pumped 800 MHz front-side bus. Haven't seen that term in a while, have you? Back then, the Pentium was manufactured at 130 nm and composed of 178 million transistors. Intel sold the thing for $1000, dropped it into the now-ancient Socket 478 interface, and gave the chip a thermal ceiling just over 100 W.

None of us could have guessed that, a decade later, Intel’s cutting-edge flagship would sport a lower base clock rate, accelerating to 3.5 GHz only in situations when thermal headroom allows. And yet, that’s exactly where the new Core i7-5960X lands. Of course, the difference is we’re dealing with an immensely more sophisticated piece of technology, and the world now knows frequency isn’t always the answer to improving performance.

The Core i7-5960X plays host to eight physical cores able to work on 16 threads concurrently by virtue of Hyper-Threading. So, applications optimized to break tasks into pieces are sped up through parallelism. Each core has its own 32 KB L1 instruction and data caches, along with 256 KB of L2 space. A massive 20 MB of L3 cache is shared between them, working out to the magical 2.5 MB per core Intel’s architects aim for.

And while 2004’s Extreme Edition handled host processing duties exclusively, 2014’s integrates a lot more functionality. The -5960X has its own on-die PCI Express controller, exposing up to 40 lanes at 8 GT/s (that’s official PCI Express 3.0 support). It’s also armed with the world’s first quad-channel DDR4 memory controller, officially rated for data rates as high as 2133 MT/s out of the gate.

In-Depth Reading

If you’d like to learn more about Intel’s Haswell architecture, which is the foundation for every core in a Haswell-E-based CPU, please check out The Core i7-4770K Review: Haswell Is Faster; Desktop Enthusiasts Yawn

Drilling down a bit deeper, the -5960X centers on Intel’s modern Haswell architecture. However, because this is the server/workstation-oriented version, it’s referred to as Haswell-E. You get the additional PCIe connectivity (Haswell-based desktop CPUs only come equipped with 16 lanes) and aforementioned memory controller (existing Haswell processors are limited to two channels of DDR3 support), but lose the on-die HD Graphics engine featured so prominently back when those fourth-gen Core CPUs launched.

Intel rightly assumes that anyone buying a powerful workstation or gaming box will install discrete graphics cards. Rather than eating into the transistor budget with a built-in GPU, all available resources are thrown into creating a more capable host processor.

Despite this smart accounting, the Haswell-E die still measures more than 355 mm² and is composed of 2.6 billion transistors—nearly 15x the Pentium 4 Extreme Edition’s count. It’s manufactured using Intel’s 22 nm node and specified for a 140 W TDP. Expect to see the CPU surface immediately at a familiar $1000 price point.

Core i7-5930K And Core i7-5820K

Any time we test one of Intel’s thousand-dollar showpieces, we acknowledge its gravitas, all the while contending that most enthusiasts prefer to spend less and lean on their technical acumen to maximize performance through overclocking. In the case of Haswell-E, only the Core i7-5960X is an eight-core model. Buying one of the lesser models means cutting a couple of cores and some cache, at least.

Fortunately, games typically don’t penalize you for dropping from eight to six cores, particularly when you’re running on Intel’s efficient architectures, and doubly so when frequency increases at the same time. As a result, the Core i7-5930K is a better candidate for gamers with money to spend on ultra-high-end hardware. It’s based on the same physical die as the -5960X. Intel simply disables two cores and 5 MB of shared L3. What remains is six cores, 15 MB of last-level cache, all 40 lanes of PCI Express 3.0, and the quad-channel memory controller. Base clock rate jumps to 3.5 GHz, while the peak frequency, controlled by Turbo Boost technology, increases to 3.7 GHz. The Core i7-5930K is priced at $583, potentially "saving" you more than $400.

If that’s still a little rich, the Core i7-5820K lands at a palatable $389. It too is a six-core chip with 15 MB of shared L3 and a four-channel DDR4 controller. However, Intel lops off some of the PCI Express, exposing 28 lanes instead of 40. Frankly, that’s not a particularly painful wound. It leaves lots of room for single-, dual-, and even triple-card graphics configurations, so long as AMD and Nvidia certify x8/x8/x8 arrays. The official word from Intel is that the -5820K supports bifurcation of its lanes into that arrangement; however, the breakdown has to be enabled at the motherboard level.

The Core i7-5820K does lose some frequency compared to the -5930K: its base clock rate is 3.3 GHz, while Turbo Boost accelerates as high as 3.6 GHz.

Core i7-5000 Series Turbo Boost Clock Rates

An Enthusiast-Friendly Trio

Still, all three of the models we’re testing are either Extreme Edition or K-series parts, meaning they feature unlocked multipliers and can be overclocked much more freely than most of Intel’s mainstream Haswell-based processors.

Even better, Intel uses solder as an interface material between its Haswell-E die and the large heat spreader covering these Core i7-5000-series CPUs. That’s in contrast to the lower-end Haswell parts, which utilize a less effective thermal compound. Even in our own lab, those dies topped with paste heat up quickly, limiting the amount of voltage we can put through them with air or liquid cooling. A solder-based interface material facilitates faster heat transfer, potentially raising the ceiling on what we can coax from Haswell-E.

It goes without saying, then, that the companies selling high-end hardware are excited about Core i7-5960X and its derivatives. We have big air coolers like Noctua’s NH-D15 in the lab, along with closed-loop systems like Intel’s own BXRTS2011LC. Memory maker G.Skill seeded us with DDR4-3000 modules rated for CAS 15 timings. ASRock and MSI armed me with a handful of impressive-looking motherboards for today’s launch, while Thomas works on our first round-up of LGA 2011-3 boards from every relevant player.

Wait, what? LGA 2011-3? Ah, yes—there’s a new platform in play, too.

X99, LGA 2011-3 and DDR4: Get Ready For A Big Upgrade

And by big I mean that a move to Haswell-E necessitates a lot of new hardware.

Intel got a lot of life out of LGA 2011. The interface surfaced alongside Core i7-3960X (Sandy Bridge-E) almost three years ago. However, a number of variables can change over time to break compatibility, including the introduction of DDR4 memory technology.

Physically, the old and new enthusiast processors are the same size. Their ball pattern pitch is the same, too. But Intel keys its Core i7-5000-series CPUs differently than the -4000s or -3000s, so you can’t accidentally drop an LGA 2011 model into LGA 2011-3, and vice versa.

In short, that -3 is important, and although both interfaces employ 2011 pins, Intel ensures you don’t mix up Haswell-E with Ivy Bridge-E or Sandy Bridge-E by notching the package uniquely. You need an X99-based motherboard for Core i7-5960X, -5930K, or -5820K.

There is good news, though. Consistent dimensions translate to cooling solution compatibility. Just be sure your old LGA 2011-specific heat sink or water block can handle Haswell-E’s slightly higher thermal ceiling. Intel’s previous-gen flagships were 130 W parts, these new Core i7s are rated at 140 W, and as we’ll see shortly, overclocking can quickly push power use much higher.

X99 Express: A Platform Controller Hub With Familiar Features

The evolution of Intel’s chipset business is painfully slow to watch. As functionality finds its way into the CPU itself, there’s less and less for the platform controller hub to handle. And what remains doesn’t change very often. If you were hoping for a connectivity revolution from X99, prepare for disappointment.

Fortunately, X79 was so old that X99 at least gets Intel’s top-end platform back up to modern standards. It enables 14 USB ports, six of which support USB 3.0 transfer rates. There’s an integrated gigabit Ethernet MAC. HD Audio is a requisite, of course. And we find a familiar eight lanes of PCI Express 2.0 for attaching add-ons, either through expansion slots or on-board third-party controllers. Perhaps the most notable step forward is support for up to 10 SATA 6Gb/s devices.

Now, the bummer is that Intel continues attaching its PCH to the host processor through a four-lane DMI 2.0 connection. You get 2 GB/s of bi-directional throughput, so it’s not hard to concoct a combination of peripheral, network, and storage traffic to overwhelm the narrow pipeline.

At least the top two SKUs give you plenty of PCIe for attaching the fastest graphics cards, SSDs, and 10 GbE add-ins, right?

DDR4: A New Memory Technology, But Why?

Given today’s multi-channel memory controllers built into processor dies, we rarely hear about bandwidth limitations unless integrated graphics is involved. Last generation’s Ivy Bridge-E supported up to four channels of DDR3 at up to 1866 MT/s, and that was good for more than 40 GB/s of throughput.

So, why DDR4?

The transition isn’t really motivated by a prescient need in the enthusiast space. But as you see some of Intel’s other processing products start emerging in the server and then mobile markets, DDR4’s inherent benefits will have more of an impact.

For example, a lower supply voltage of 1.2 V helps pull power consumption down compared to the 1.5 V DDR3 modules we’re used to. Some of that is mitigated in today's piece, since the DDR4 kits we have in-house are pushed to 1.35 V, sometimes requiring even more voltage. But in an enterprise-oriented configuration, multiple Haswell-EP-based CPUs are going to use registered modules down at the standard’s specified 1.2 V, delivering quantifiable power savings.

Foundries are also manufacturing DDR4 using more advanced processes, allowing for higher density. Again, this affects server customers looking to cram tons of capacity into their machines more than enthusiasts considering Haswell-E, perfectly content to spread 32 or 64 GB across eight slots.

DDR4 also paves the way for higher data rates, starting at 2133 MT/s and scaling up from there. Latencies are up too, though. What we noticed was that a Core i7-4960X armed with DDR3-1866 isn’t too far off a Core i7-5930K with DDR4-2133 in SiSoftware’s memory bandwidth benchmark.

More apparent from our testing is that there are still kinks to be worked out. The X99-based motherboards in our lab are continuously receiving firmware updates, most of which relate to DDR4 compatibility. Some won’t boot at all. Others struggle to hit data rates in excess of 2666 MT/s. At that point, we have to switch from a 100 MHz BCLK to 125 MHz or more. The 2800 and 3000 MT/s options still aren’t stable (at least in our SoCal lab; Igor got his 2800 MT/s setup running in Germany). Until firmware, module compatibility, and pricing improves, DDR4 may be the reason cautious enthusiasts camp out on the sidelines for a while.

How We Tested Core i7-5960X, -5930K, And -5820K

A number of companies helped us prepare for Haswell-E.

Because Intel is no longer in the motherboard business, it doesn’t have a platform of its own to send out. Instead, we worked closely with ASRock to benchmark using its X99 WS. MSI also supported our efforts by sending over several X99 SLI Plus boards.

Noctua helped us standardize on one high-performance air cooler by sending over its NH-D15, which is LGA 2011-3-compatible.

Representatives at G.Skill diligently helped us troubleshoot memory issues early in our testing, passing along their own experiences dialing in higher DDR4 data rates.

And of course, several other standardized components carry over from our existing bench setup: Corsair’s AX860i power supply, Samsung’s 840 Pro SSD, and a GeForce GTX Titan graphics card.

Synthetic Benchmarks

Our first benchmark chart is busy, so I’ll make the analysis easy. Those black bars represent graphics performance, which Futuremark deliberately biases to the GPU. Since that doesn’t change, most of the results appear similar. The red bar reflects 3DMark’s overall score. It’s affected by graphics and the rest of the platform. Any scaling seen there corresponds to larger differences in the blue bar, measuring CPU-based physics calculations.

Despite facing clock rate deficits, Intel’s eight-core processors dominate. They’re followed by the six-core chips, though Intel’s Core i7-4790K operates at high enough of a frequency to almost overtake the Core i7-5820K.

The benchmark suite we use features several OpenCL-accelerated metrics. And one observation we’ll make several times in today’s story is that a fast, heavily-threaded host processor doesn’t necessarily guarantee great results in a task emphasizing the GPU. Intel’s Core i7-4790K only features four physical cores. Yet, a blistering-fast base frequency catapults it to the top of our chart. All three Haswell-E-based processors appear near each other, but behind the Core i7-4960X.

The Fritz chess benchmark is perhaps a better indicator of parallel processing potential. Both eight-core CPUs appear out in front of the rest of the field. Four hexa-core Core i7s follow, trailed by Intel’s Haswell-refresh Core i7-4790K.

In addition to the previous three system-level synthetics, we also ran SiSoftware Sandra to better characterize different parts of each product. The Cryptography and Memory Bandwidth tests are two of my favorites.

AES-NI support allows all of these CPUs to tackle the Encryption/Decryption benchmark as fast as the memory subsystem sends instructions. Not surprisingly, the DDR4-equipped Core i7s are fastest, joined by an eight-core Ivy Bridge-EP-based Xeon E5. The Hashing routine is less consistent…unless you know what you’re looking for. CPUs employing Intel’s Haswell architecture allow for 256-bit integer operations through AVX2, and that’s where the doubling of performance comes from.

A more direct measurement of memory bandwidth aligns with each CPU’s top officially-supported data rate. In the case of the Haswell-E-based processors, that’s DDR4-2133. Xeon E5 hangs in with plenty of fast DDR3-1866, which is shared by Core i7-4960X. Dropping to Core i7-3970X pushes you to DDR3-1600, while the Core i7-4790K is at an inherent disadvantage with half as many memory channels.

Real-World Benchmarks

Content Creation

To be sure, Haswell-E is all about heavy lifting in content creation applications.

The flagship Core i7-5960X takes second place in our 3ds Max tests, but only because Intel’s Xeon E5-2687W v2 is an eight-core behemoth with a 3.4 GHz base frequency and 4 GHz peak clock rate. That processor sells for $2000—twice the -5960X. Shedding a couple of cores knocks the -5930K into third place, while the -5820K succumbs to Intel’s Core i7-4960X.

Next to all of that heavy metal, a $340 Core i7-4790K looks pretty darned good. There will be those times when a six-core -5820K for a few bucks more is even better, though.

Blender also rewards high core counts. Both eight-core models excel, and Core i7-5960X comes out on top (just barely) thanks to Haswell’s advantages over Ivy Bridge. The two six-core implementations of Haswell-E snag third and fourth place, employing architectural improvements to outpace Ivy Bridge-E and Sandy Bridge-E. The four-core Haswell design can’t keep up.

Sony’s video editing software gets some boost from our GeForce GTX Titan. And as promised on the previous page, folding OpenCL acceleration into the equation throws off our expectations. The outcome falls within a five-second range, but Haswell-E doesn’t start showing up until third place. More than anything, this tells us we’re limited by our GeForce GTX Titan. It’d take a much slower host processor to hurt the render time.

Adobe CC

The scaling in Premiere Pro isn’t as severe as, say, Blender. But the Xeon, with its eight cores and aggressive clock rate, still scores a first-place finish. Our other eight-core chip appears in fourth place, presumably due to its slower 3 GHz base frequency. Stepping up to the -5930K’s 3.5 GHz floor is enough for second place.

After Effects enjoys the Xeon’s tuned frequency, first, and Haswell-E’s efficient architecture, second. The other six-core CPUs pile in ahead of Core i7-4790K, corroborating evidence that this benchmark does benefit from parallelization.

As you no doubt already know, our Photoshop workload consists of two distinct metrics: one that uses well-threaded filters to tax host processors, and another laced with OpenCL acceleration. The former, in red, demonstrates the benefit of eight-core processors versus six-core models compared to a lone quad-core example. The latter is all over the place. The fact that Core i7-4790K is way in front suggests a few fast cores can feed Nvidia’s GeForce GTX Titan more effectively than wider CPUs operating at lower frequencies.

Productivity and Media Encoding

LAME and iTunes are our two single-threaded tests; both pummel the big eight-core -5960X for its relatively modest peak Turbo Boost bin. Core i7-5930K stretches up to 3.7 GHz, which is good enough for middle-of-the-pack finishes. But the Core i7-4790K hitting 4.4 GHz cannot be matched. Single-threaded software is so last decade, though.

Shifting gears to TotalCode Studio reminds us that the eight-core chips excel under the right conditions. And if you’re in the market for a $1000 CPU, the applications important to you are probably the sort able to benefit from lots of cores…

…like Visual Studio, for example. Haswell-E takes three of the top four positions, interrupted only by the eight-core Xeon built on an Ivy Bridge foundation. If you’re compiling big projects, paying extra for a Core i7-5820K over a Core i7-4790K could save you enough time to justify the premium.

FineReader similarly shows off what an eight-core chip is capable of. The six-core models clump up together, while four cores don’t show as well in our OCR-based test.

HandBrake rounds out a collection of benchmarks capable of utilizing whatever processing resources you offer. The $1000 Core i7-5960X matches the $2000 Xeon, both with eight cores. Haswell’s IPC-oriented advancements help carve out a victory over Ivy Bridge-E and Sandy Bridge-E at six cores. And the Core i7-4790K hangs in there thanks to the same modern architecture and a 4 GHz base clock rate.

Compression

Sorting by our CPU test, WinZip tells a similar story as most of the benchmarks preceding it: eight cores are fastest in a parallelized workload, six cores are also swell, and four execution cores appear quite mainstream.

WinRAR isn’t as damning. Its limited optimizations are more inclined to favor the Core i7-4790K’s high clock rate.

Meanwhile, 7-Zip breaks the tie. More so than we might have guessed at the outset of today’s review, a lower-clocked eight-core processor can flex its muscle in a collection of common software. You don’t necessarily need a specially-written engineering or financial analysis title to realize big gains.

Battlefield 4, Grid 2, And Metro: Last Light

Battlefield 4

I knew the content creation, productivity, and media encoding benchmarks would make the Core i7-5960X look good. After all, a great many of those tests were selected months and years ago for their ability to isolate host processor performance. But I’m counting on the games to show value in the six- and even four-core processors, since they often favor architecture and clock rate over core count.

Battlefield 4 gives us an early taste of that hypothesis in practice; the Core i7-5820K and -5930K take first and second place. More surprising is that the Core i7-4790K falls to last. It centers on Haswell and sports the highest clock rate in our comparison. Big L3 caches have to be giving the eight- and other six-core CPUs their advantage.

Grid 2

Known for its host processor and memory dependency, Grid 2 might have been expected to exhibit a wider delta between first and last place. But all of these CPUs feed a single GeForce GTX Titan quickly. The Core i7-5820K notably claims its second first-place finish, followed by Intel’s Core i7-4790K. It’s good to know you don’t need to drop disgusting amounts of cash on your next platform to get great frame rates, right? Invest in your graphics subsystem instead.

Metro: Last Light

Even though Metro is a GPU showcase, we can’t help but notice the Core i7-5820K in first place again. The -4790K and -5930K following it are just slightly faster than three generations of Extreme Edition processors, plus a $2000 Xeon.