Cerebras, the supplier of wafer-scale AI processors, has filed for an IPO for the second time after it cancelled such plans due to its ties with G42, an Abu Dhabi-based AI company backed by sovereign wealth fund Mubadala, last year. Financial results disclosed as part of the filing reveal that Cerebras appears to be one of the fastest-growing AI hardware companies right now. However, 86% of its revenue comes from two customers, and the company is bleeding money.

Cerebras positions itself as an AI infrastructure company, not just a maker of AI accelerators. Indeed, Cerebras designs a full stack: wafer-scale engine (WSE, literally a full silicon wafer turned into one processor), systems, and software, delivered as rack-scale systems. While Nvidia sells everything from AI GPUs to fully built rack-scale solutions, Cerebras only sells systems. Because WSE packs around 900,000 compute cores, 44 GB of on-chip SRAM, and 21 PB/s of on-chip bandwidth, its architecture by definition avoids an inter-chip communication bottleneck. Essentially, Cerebras trades system complexity for silicon complexity. There is a major weakness: wafer-scale chips are notoriously hard to yield, though WSE features plenty of redundant cores and memory cells to maximize yields.

Cerebras' revenue has grown rapidly from $24.6 million in 2022 to $510 million in 2025 (20x growth), but the quality of that growth is fragile as ~86% of revenue comes from just two customers (G42 and Mohamed bin Zayed University of Artificial Intelligence, MBZUAI), which makes the company dependent on a handful of large, project-based deployments rather than a diversified, repeatable revenue base that companies like AMD or Nvidia tend to have. The remaining 14% of revenue is generated by a fragmented base of smaller enterprise, government, and cloud customers, but none contribute enough individually to reduce Cerebras' heavy reliance on its top two clients. More recently, Cerebras inked agreements to supply its AI hardware to Amazon Web Services and OpenAI, which will diversify revenue streams for the company.

Right now, Cerebras has a massive $24.6 billion backlog (including the $20 billion OpenAI deal), which provides strong demand visibility. The company expects to recognize approximately 15% of this revenue within the first 24 months through December 31, 2027, 43% during months 25 to 48, and the remainder thereafter. Still, Cerebras warns that converting this backlog into revenue depends on the manufacturing capacity of its partners, infrastructure deployment, and power availability. The company further warns that all of its manufacturing services and components are bought on a purchase order basis without capacity or volume commitments, which poses massive risks as the company has a very long supply chain.

Cerebras reported GAAP net income of $237.8 million in 2025, compared to a net loss of $481.6 million in 2024. However, this income statement is misleading as the profit did not come from its core business, but from an accounting adjustment. Cerebras recorded a $363 million gain from a change in the fair value (and extinguishment) of a forward contract liability: the company had a financial obligation whose value was reduced, which allows it to book that reduction as income. If the value was not reduced, the company would be unprofitable. In fact, Cerbras' operating losses totaled $145.9 million in 2025.

When it comes to gross margins, they improved significantly from 12% in 2022 to 39% in 2025 as the scale of its business and product mix improved. However, Cerebras has never been profitable.

Cerebras postponed its IPO plans in 2024 after a national security review examined its ties with Abu Dhabi-based G42 amid concerns about potential foreign access to advanced AI processors. G42 is both a customer and investor of Cerebras, which controls a 1% stake in the company that it acquired for $40 million in 2021.

Cerebras has not specified an official fundraising target in its IPO filing, but current market expectations point to a roughly $3 billion raise. This is significantly higher than earlier $1 billion plans, which reflect the company's rapid revenue growth and the scale of its AI infrastructure ambitions.

The U.S. Department of Commerce issued a statement Thursday confirming that it is looking to change AI hardware export rules, but provided little by way of detail. The officials confirmed that the U.S. DoC aims to formalize an approach under which buyers of large quantities of AI accelerators must invest in U.S. AI infrastructure to obtain their hardware.

"The Commerce Department is committed to promoting secure exports of the American tech stack," a statement by the U.S. DoC reads. "We successfully advanced exports through our historic Middle East agreements, and there are ongoing internal government discussions about formalizing that approach."

The newly proposed export rules introduce a multi-level licensing structure tied to computing capacity. Smaller shipments of up to 1,000 Nvidia GB300 GPUs would undergo an expedited approval process; medium-scale deployments would need to secure pre-authorization from the U.S. Department of Commerce before applying for export license as well as operational transparency, disclosure of business activities, and potential on-site inspections by U.S. authorities; while planned large AI clusters set to use 200,000 of GB300 GPUs or more and operated by one entity in one country would require commitments to invest in U.S. AI infrastructure as part of the arrangement as well as intergovernmental talks with the U.S. to make national security assurances.

The terms attached to recent export licenses allowing Cerebras and Nvidia to supply hardware to the United Arab Emirates included a requirement that the Middle Eastern country invest one dollar in U.S. AI infrastructure for every dollar spent on its own domestic AI buildouts. If the same terms were to be attached to export licenses to other countries, then this would make hardware from AMD, Cerebras, Nvidia, and other suppliers of AI accelerators 2X more expensive for companies in these countries.

The U.S. DoC shot down claims of a return to anything resembling the AI Diffusion Rule from the Joe Biden era: "Today there was reporting that we were returning to the AI diffusion rule," the statement reads. "We will not. It was burdensome, overreaching, and disastrous."

While the AI Diffusion Rule was indeed very complicated, some approaches of the new rumored regulations would make them even more burdensome than the criticized export regime from early 2025.

The AI Diffusion Rule divided countries into three tiers based on trust and risk levels. Tier 1 included the U.S. and 18 close allies like Australia, Canada, Japan, Taiwan, the U.K., and much of Western Europe, which faced minimal restrictions on AI exports. In Tier 2 countries, entities could import up to 1,700 Nvidia H100 GPUs (or equivalent) without a license, and these did not count toward national AI chip limits. Tier 3 was banned altogether.

Meanwhile, getting up to 320,000 Nvidia H100 GPUs required entities in Tier 2 countries to qualify as National Validated End Users (NVEUs) and meet strict security requirements. Unverified organizations in Tier 2 were allowed to buy up to 50,000 GPUs per country, though the limit was expandable to 100,000 if their government reached a formal agreement with the U.S. Under no circumstances did the AI Diffusion Rule mandate investments in U.S. AI infrastructure by purchasers of American AI hardware.

If the new regulation is enacted, anything above 1,000 GB300 would be subject to pre-authorization before export licenses could be issued, which includes shipments to 18 allied nations. Getting 200,000 or more GB300 GPUs would essentially mandate investments in the U.S. AI buildouts. Then again, the reported rules are not final, and many of the requirements may be removed in the final versions of the proposed export regime.

The U.S. government is drafting sweeping new export regulations that would give it authority to approve nearly all global shipments of advanced AI accelerators made by American companies, including AMD and Nvidia, reports Bloomberg. The rules would expand existing country-based restrictions into a worldwide licensing system and will give Trump's administration power to allow or decline large-scale AI infrastructure buildouts. The rule turns out to be considerably stricter than the highly-criticized AI Diffusion Rule from the Biden era.

The newly proposed export regime establishes a tiered licensing system based on computing scale: small-scale batches would pass through a simplified review, mid-scale deployments would require 'preclearance before seeking export licenses' from the U.S. Department of Commerce, whereas large-scale AI clusters would require governments of host countries to negotiate the deal with the U.S. government and investments in the U.S. AI infrastructure as part of the deal.

• Shipments involving up to 1,000 Nvidia GB300 GPUs would pass through a simplified review and may qualify for limited exemptions.
• Larger installations would require pre-authorization before export licenses could be issued. These will introduce compliance obligations that may include operational transparency, disclosure of business activities, and potential on-site inspections by U.S. authorities.
• Clusters powered by 200,000 GB300 GPUs operated by a single company within one country — such as those currently deployed by AWS, Microsoft, Oracle, Open AI, or xAI — would trigger direct intergovernmental arrangements. In these cases, approvals would depend on national-security assurances as well as commitments to invest in American AI infrastructure.

For now, companies like AMD, Cerebras, and Nvidia cannot ship high-performance AI processors to select countries, such as China, Iran, North Korea, and Russia, just to name a few. Yet, shipping large-scale batches of AI accelerators to Middle Eastern countries requires direct intergovernmental arrangements and investments in the American AI infrastructure. If the newly proposed regulation becomes a law, then such arrangements would become much more common particularly with allied nations in Europe.

The proposed policy is by no means a total export ban, but an extremely powerful tool that lets the U.S. government influence how global AI infrastructure develops. If the Trump administration does not like the fact that a UK or France-based company deploys a cluster of over 200,000 GB300 GPUs or equivalent, it can deny appropriate export licenses if appropriate governments and companies do not meet their requirements.

If the proposed policy is enacted, for companies like AMD or Nvidia, which ship their products globally, everything will depend on how quickly licenses are granted and what conditions are attached. Fast approvals with light restrictions would let most small projects move forward, though with more paperwork. However, for larger installations, tougher requirements would delay construction and make operating large data centers outside the U.S. considerably more complicated. Meanwhile, building clusters comparable to those currently operated by AWS, Google, Oracle, Microsoft, or xAI outside of the U.S. would face extreme complications, which would lower their economic feasibility.

OpenAI on Thursday released GPT-5.3-Codex-Spark, its first AI model served on chips from Cerebras Systems, marking the ChatGPT maker’s first production deployment on silicon outside its long-standing core stack with Nvidia. The new model is a streamlined, lower-power variant of Codex designed for fast, interruptible coding tasks, and is initially rolling out as a research preview to ChatGPT Pro subscribers.

According to OpenAI, GPT-5.3-Codex-Spark is tuned for interactive development workflows such as editing specific sections of code and running targeted tests, and the model is optimized for high throughput when served on ultra-low latency hardware. The company claims it can exceed 1,000 tokens per second under the right configuration, while also defaulting to minimal edits, and will not automatically execute tests unless instructed.

The hardware behind all this is Cerebras’ third-generation Wafer Scale Engine. Unlike conventional GPU clusters built from many smaller chips connected over high-speed interconnects, Cerebras uses a single wafer-scale processor with hundreds of thousands of AI cores and large pools of on-chip memory. The architecture is designed to minimize data movement and reduce latency, which is often the bottleneck in interactive inference workloads.

OpenAI said last month that it had signed a deal to deploy Cerebras hardware for low-latency inference, and that it plans to bring 750 megawatts of Cerebras-backed compute online in phases through 2028. While that capacity will not replace Nvidia’s role in OpenAI’s training infrastructure, it gives the company a dedicated tier optimized for responsiveness rather than training.

Earlier this month, Sam Altman took to X.com to say that OpenAI loves working with Nvidia, and that “they make the best chips in the world,” adding, “We hope to be a gigantic customer for a very long time.” This came following a controversial report from Reuters that claimed OpenAI is unsatisfied with some Nvidia chips.

OpenAI has also described the partnership with Nvidia as “foundational” and said the company is anchored on Nvidia as the core of its training and inference stack, while also expanding the ecosystem around it through partnerships with Cerebras and others. OpenAI’s most powerful models continue to be trained and served on Nvidia systems.

OpenAI has also agreed to deploy 6 gigawatts in chips from AMD over multiple years and has also struck a deal with Broadcom to develop custom AI accelerators and networking components.

Codex itself now has more than 1 million weekly active users, according to OpenAI, and will expand beyond Pro users in the coming weeks as the company evaluates performance and demand.

Update: Cerebras has re-established control over its X account, with no suspicious activity in the past 24 hours.

Original Article:
Cerebras, the maker of the world's largest AI chips, has confirmed to Tom's Hardware that its X account was hacked as part of a fraudulent cryptocurrency launch that includes a fake crypto coin being launched under its company name.

A coin launched on June 15 under the name Cerebras, with the token $CEREBRAS, immediately raised suspicions from industry trackers, who noted that the coin could indeed be some kind of rug pull or scam.

Detecting malfunctioning cores and disabling them on a massive processor is challenging, but Tesla has developed its Stress tool, which can detect cores prone to silent data corruption across not only Dojo processors but also across Dojo clusters with millions of cores, all without taking them offline. This is an incredibly important capability, as Tesla says a single silent data error can destroy an entire training run that takes weeks to complete.

Tesla's Dojo is one of the two largest processors that currently exist on the planet. These massive wafer-scale chips use a whole 300-mm wafer, meaning it simply isn't possible to create a larger chunk of computing power in one go. Each Dojo wafer-scale processor packs up to 8,850 cores, but some of them may induce silent data corruptions (SDCs) after deployment, corrupting the results of extensive training runs. 

A big processor

Given the extreme complexity of the Dojo Training Tile (the large wafer-size chip), it isn't easy to detect defective dies even during the manufacturing process, but when it comes to silent data corruption (SDC), things become even more complex. 

Keep in mind that SDCs are inevitable on all types of hardware, but a Dojo processor consumes 18,000 amps and dissipates 15,000W of power, which has an effect. However, all cores should perform as intended, as otherwise Tesla's AI training will become more complicated, because a single error caused by data corruption can render weeks of AI training obsolete.

Tesla refers to each wafer-scale Dojo processor as a 'Training Tile.' Each Trailing tile packs twenty-five 645 mm^2 D1 'chips' with 354 custom 64-bit RISC-V cores featuring 1.25 MB of SRAM for data and instructions (which Tesla calls nodes, but we will call them cores for easier understanding) organized in a 5×5 cluster and interconnected using a mech network with a 10 TB/s of directional bandwidth.

Each D1 also supports 4 TB/s off-chip bandwidth. Each 'Training Tile' therefore packs 8,850 cores, supporting 8-, 16-, 32-, or 64-bit integers, as well as multiple data formats. Tesla uses TSMC's InFO_SoW technology to package its wafer-scale Dojo processors. 

Needs proper maintenance

To address the risk of core faults, Tesla first deployed a differential fuzzing technique. This initial version involved generating a random set of instructions and sending the same sequence to all cores. After execution, the outputs were compared to find mismatches. However, the process took too long due to the significant communication overhead between the host and the Dojo training tile. 

In a bid to boost efficiency, Tesla refined the method by assigning each core a unique payload consisting of 0.5 MB of random instructions. Instead of communicating with the host, cores retrieved payloads from each other within the Dojo training tile and executed them in turn. This internal data exchange utilized Dojo training tile's high-bandwidth communication, enabling Tesla to test approximately 4.4 GB of instructions in a significantly shorter timeframe. 

Then, Tesla further enhanced the method by enabling cores to run each payload multiple times without resetting their state between runs. This technique introduced additional randomness into the execution environment, enabling the exposure of subtle errors that might otherwise go undetected. Despite the increased number of executions, the slowdown was minimal compared to the gains in detection reliability, according to the company. 

Another improvement resulted from periodically integrating register values into a designated SRAM area using XOR operations, which increased the probability of identifying defective computational units by a factor of 10 (as tested in known defective cores) without substantial performance degradation.

Not only on the processor level

Tesla's method not only works at the Dojo training tile level or the Dojo Cabinet level (which packs 12 Dojo training tiles), but also at the Dojo Cluster level, enabling the company to identify a faulty core out of millions of active cores. 

Once tuned properly, the Stress monitoring system revealed numerous defective cores across Dojo clusters, according to the report. The distribution of detection times varied widely, though. Most defects are found after executing 1 GB to 100 GB of payload instructions per core, corresponding to seconds to minutes of runtime. Harder-to-detect defects may require 1000+ GB of instructions, meaning several hours of execution. 

It should be noted that Tesla's Stress tool testing runs are lightweight and self-contained within the cores, allowing it to perform background testing without requiring cores to be offline. Obviously, only the cores identified as faulty are disabled afterward, and even then, each D1 die can tolerate a few disabled cores without affecting the overall functionality.

Identifying design flaws

Tesla also mentioned that in addition to detecting failed cores, the Stress tool has also uncovered a rare design-level flaw, which engineers managed to address through software adjustments. Several issues within low-level software layers were also found and corrected during the broader deployment of the monitoring system.

By now, the Stress tool has been fully integrated into operational Dojo clusters for in-field monitoring of ongoing hardware health surveillance during active AI training. The company states that the defect rates observed through this monitoring are comparable to those published by Google and Meta, indicating that the monitoring tool and hardware are on par with those used by others.

In post-silicon and pre-silicon phases

Tesla now plans to use data obtained by using its Stress to study the long-term degradation of hardware due to aging. In addition, the company intends to extend the method to pre-silicon testing phases and early validation workflows to catch the aforementioned faults even before production, although it is challenging to envision exactly how this might be achieved, as SDCs can occur due to aging.

Thoughts

You might often think of processors as being relatively small, but TSMC is developing a version of its CoWoS technology that will enable its partners to build multi-chiplet assemblies that will be 9.5-reticle sized (7,885 mm²) and will rely on 120×150 mm substrates (18,000 mm²), which is slightly larger than the size of a CD case. TSMC claims these behemoths could offer up to 40 times the performance of a standard processor.

Virtually all modern high-performance data center-grade processors use multi-chiplet designs, and as demands for performance increase, developers want to integrate even more silicon into their products.

In an effort to meet demand, TSMC is enhancing its packaging capabilities to support significantly larger chip assemblies for high-performance computing and AI applications. At its North American Technology Symposium, TSMC unveiled its new 3DFabric roadmap, which aims to scale interposer sizes well beyond current limits.

From big to huge

Currently, TSMC CoWoS offers chip packaging solutions that enable interposer sizes of up to 2831 mm^2, which is approximately 3.3 times larger than the company’s reticle (photomask) size limit (858 mm^2 per EUV standard, with TSMC using 830 mm^2). This capacity is already utilized by products like AMD’s Instinct MI300X accelerators and Nvidia’s B200 GPUs, which combine two large logic chiplets for compute with eight stacks of HBM3 or HBM3E memory. But that's not enough for future applications.

Sometimes next year, or a bit later, TSMC plans to introduce the next generation of its CoWoS-L packaging technology, which will support interposers measuring up to 4,719 mm^2, roughly 5.5 times larger than the standard reticle area. The package will accommodate up to 12 stacks of high-bandwidth memory and will require a larger substrate measuring 100×100 mm (10,000 mm^2). The company expects that solutions built on this generation of packaging will deliver more than three and a half times the compute performance of current designs. While this solution may be enough for Nvidia’s Rubin GPUs with 12 HBM4 stacks, processors that will offer more compute horsepower will require even more silicon.

Looking further ahead, TSMC intends to scale this packaging approach even more aggressively. The company plans to offer interposers with an area of up to 7,885 mm^2, approximately 9.5 times the photomask limit, mounted on a 120×150 mm substrate (for context, a standard CD jewel case measures approximately 142×125 mm).

This represents an increase from an 8x-reticle-sized multi-chiplet assembly on a 120×120mm substrate that TSMC presented last year, and this increase likely reflects the requests from the foundry's customers. Such a package is expected to support four 3D stacked systems-on-integrated chips (SoICs, e.g., an N2/A16 die stacked on top of an N3 logic die), twelve HBM4 memory stacks, and additional input/output dies (I/O Die).

However, TSMC has customers who demand extreme performance and are willing to pay for it. For them, TSMC offers its System-on-Wafer (SoW-X) technology, which enables wafer-level integration. For now, only Cerebras and Tesla use wafer-level integration for their WFE and Dojo processors for AI, but TSMC believes there will be customers beyond these two companies with similar requirements.

Power delivery

Without a doubt, 9.5-reticle-sized or wafer-sized processors are hard to build and assemble. But these multi-chiplet solutions require high-current kilowatt-level power delivery, and this is getting harder for server makers and chip developers, so it needs to be addressed at the system level. At its 2025 Technology Symposium, TSMC outlined a power delivery strategy designed to enable efficient and scalable power delivery at kilowatt-class levels.

To address processors with kilowatt-class power requirements, TSMC wants to integrate monolithic power management ICs (PMICs) with TSVs made on TSMC's N16 FinFET technology and on-wafer inductors directly into CoWoS-L packages with RDL interposers, enabling power routing through the substrate itself. This reduces distance between power sources and active dies, lowering parasitic resistance and improving system-wide power integrity.

TSMC claims that its N16-based PMIC can easily handle fine-grained voltage control for dynamic voltage scaling (DVS) at the required current levels, achieving up to five times higher power delivery density compared to conventional approaches. In addition, embedded deep trench capacitors (eDTC/DTC), built directly into the interposer or silicon substrate, provide high-density decoupling (up to 2,500 nF/mm^2) to improve power stability by filtering voltage fluctuations close to the die and ensure reliable operation even under rapid workload changes. This embedded approach enables effective DVS and improved transient response, both of which are critical for managing power efficiency in complex, multi-core, or multi-die designs.

In general, TSMC's power delivery approach reflects a shift toward system-level co-optimization, where power delivery to silicon is treated as an integral part of the silicon, packaging, and system design, not a separate feature of each component.

Form-factor and cooling

Cerebras got Meta’s Llama 3.1 405B large language model to run at 969 tokens per second, 75 times faster than Amazon Web Services' fastest AI service with GPUs could muster.

The LLM was run on Cerebras’s cloud AI service Cerebras Inference, which uses the chip company’s third-generation Wafer Scale Engines rather than GPUs from Nvidia or AMD. Cerebras has always claimed its Inference service is the fastest for generating tokens, the individual parts that make up a response from an LLM. When it was first launched in August, Cerebras Inference was claimed to be about 20 times faster than Nvidia GPUs running through cloud providers like Amazon Web Services in Llama 3.1 8B and Llama 3.1 70B.

But since July, Meta has offered Llama 3.1 405B, which has 405 billion parameters, making it a far heavier model than Llama 3.1 70B with 70 billion parameters. Cerebras says its Wafer Scale Engine processors can run this massive LLM at “instant speed,” with a token rate of 969 per second and a time-to-first-token of just 0.24 seconds; that’s a world record according to the company, not just for its chips, but also for the Llama 3.1 405B model.

Compared to Nvidia GPUs rented from AWS, Cerebras Inference was apparently 75 times faster; the Wafer Scale Engine chips were 12 times faster than even the fastest implementation of Nvidia GPUs from Together AI. Its closest competitor, AI processor designer SambaNova, was beaten by Cerebras Inference by 6 times.

To illustrate how fast this is, Cerebras prompted Fireworks (the fastest AI cloud service equipped with GPUs) and Inference to create a chess program in Python. Cerebras Inference took about three seconds, while Fireworks took 20.

“Llama 3.1 405B on Cerebras is by far the fastest frontier model in the world – 12x faster than GPT-4o and 18x faster than Claude 3.5 Sonnet,” Cerebras said. “Thanks to the combination of Meta’s open approach and Cerebras’s breakthrough inference technology, Llama 3.1-405B now runs more than 10 times faster than closed frontier models.”

Even when upping the query size from 1,000 tokens to 100,000 tokens (a prompt that’s made up of at least a couple thousand words), Cerebras Inference apparently operated at 539 tokens per second. Of the five other services that could even run this workload, the best mustered just 49 tokens per second.

Cerebras also bragged that just a single second-generation Wafer Scale Engine outperformed the Frontier supercomputer by 768 times in a molecular dynamics simulation. Frontier had been the world’s fastest supercomputer until Monday, when the El Capitan supercomputer launched, and it has 9,472 Epyc CPUs from AMD.

Additionally, the Cerebras chip outperformed the Anton 3 supercomputer by 20%, a significant feat considering Anton 3 was built for molecular dynamics; its performance of 1.1 million simulation steps per second was also the first time any computer had broken the million-simulation-step barrier.

OpenAI once considered buying Cerebras, an AI hardware startup, aiming to secure chipmaking capabilities that would lessen its reliance on Nvidia, reports TechCrunch. Recent legal filings from Elon Musk's lawsuit against OpenAI reveal discussions between Musk, OpenAI executives, and Tesla about acquiring Cerebras, though the plan ultimately did not proceed.

The discussions originated with Ilya Sutskever, a co-founder of OpenAI, who suggested in 2017 that Tesla could be the acquisition vehicle for Cerebras. Sutskever noted that buying Cerebras through Tesla could create a conflict since Tesla's duty to maximize shareholder profit might not align with OpenAI's nonprofit-driven mission. His idea sparked further consideration, but ultimately the acquisition was shelved.

Multiple OpenAI leaders, including Musk and Greg Brockman, who is now OpenAI's president, participated in the conversation, which discussed merger terms and due diligence steps. Despite these efforts, the deal fell apart, though the legal filings do not specify why it was abandoned.

Cerebras, which designs wafer-scale AI processors that it claims outperform Nvidia's GPUs for AI training, is now preparing to go public. The company has raised $715 million and is targeting a valuation of around $8 billion. However, its reliance on a single client, Abu Dhabi's G42, for 87% of its revenue in the first half of 2024 poses a risk, especially as G42's historical ties to China's Huawei have drawn attention from U.S. lawmakers.

OpenAI's acquisition of Cerebras might have been mutually beneficial, allowing Cerebras to bypass the challenges of an IPO while giving OpenAI resources to design AI processors in-house and therefore not relying on Nvidia, which dominates the AI processor market these days.

Since abandoning the acquisition plan, OpenAI has revamped its hardware strategy. Initially, the company wanted to build a network of fabs operated by foundries like TSMC, and solely dedicated to AI processors. However, this was not exactly financially viable, so OpenAI shelved the idea. The company is now working with Broadcom to design its own AI processors that are expected to be made by TSMC.

By developing proprietary processors, OpenAI aims to reduce its dependency on Nvidia and cut operational costs. The first chips could be ready as early as 2026, allowing OpenAI to improve cost efficiency for training and deploying its AI models, which aligns with the company's long-term strategic goals.

Reuters reports that Cerebras is expected to delay its planned IPO due to complications with a U.S. government review of a minority investment from the UAE-based company G42. The review, conducted by the Committee on Foreign Investment in the United States (CFIUS), is focused on potential national security risks associated with G42's involvement.

The CFIUS is investigating the stake the UAE-based Group 42 plans to take in Cerebras, assessing whether the UAE-based investment could pose national security concerns. G42 is committed to buying $335 million worth of Cerebras shares, giving it a stake exceeding 5%. The investment plan sparked the U.S. investigation due to fears of G42's potential role in funneling AI technology to regions restricted by U.S. export laws, particularly China.

G42 is Cerebras's primary customer, and sales to the UAE-based company accounted for 83% of the AI company's revenue in 2023. Cerebras has been collaborating with G42 to train a large Arabic language model, now available through Microsoft Azure. Also, Group 42 currently holds less than 5% of Cerebras's Class A shares but may buy more based on the volume of its future purchases from Cerebras, the companies said earlier this month.

Cerebras hopes to receive clearance for an IPO from CFIUS by the end of this year, but the timing remains uncertain. According to Reuters, the company had scheduled its IPO roadshow for the upcoming weeks but is now likely to delay these plans. As the review process with CFIUS remains incomplete, it creates uncertainty around the company's timeline for going public.

Going public would give Cerebras the necessary money to better compete against various rivals, including Nvidia, AMD, and Intel. While the company probably has enough finances for now, IPO delays could impact its ability to compete in the longer term as it needs to build new products.

According to Reuters, Cerebras and G42 modified their CFIUS filing to streamline the review process, clarifying that G42's shares will be non-voting shares. The companies argued that this adjustment should exempt the transaction from a detailed CFIUS review. Despite this, the regulatory body is still evaluating the situation and has not yet approved it.

The U.S. Treasury Department, which oversees CFIUS, has stated that it would continue to take necessary steps to protect national security interests but has not commented on the specifics of the Cerebras case.

On Tuesday, Cerebras Systems, the company primarily known for wafer-scale processors for AI, filed for an IPO on the Nasdaq under the symbol CBRS. Cerebras, which offers both servers based on its Wafer Scale Engine 3 processors as well as cloud services (sometimes in partnership with giants like Group 42) revealed financial results for its recent years and it appears that company revenues are increasing, while its losses are decreasing. A great time for an IPO.
Cerebras's valuation is currently unclear.

Back in 2022, the Cerebras's total revenue comprising of hardware sales and services, was $24.62 million, whereas its loses topped $177.7 million. The company increased its revenue to $78.74 million in 2023 and shrank its losses to $127.15 million in 2023. This year, Cerebras's revenue skyrocketed to $136.4 million in the first half alone, whereas its losses dropped further to $66.60 million. 

Revenue growth has primarily been driven by the UAE Group 42 (aka G42), a UAE-based AI firm that accounted for 83% of Cerebras's revenue in 2023 and 87% of the company's revenue in the first half of 2024. In a deal signed in May 2024, Group 42 committed to purchasing $1.43 billion worth of Cerebras products by March 2025. Group 42 currently holds less than 5% of Cerebras's Class A shares but may acquire more based on the volume of future purchases.  

Relying on essentially one big customer, based in the UAE, a country which is under U.S. export restrictions, is a risk and Cerebras makes no secrets of that.

"While we have obtained an export license from BIS to export, reexport, or transfer (in-country) our CS-2 systems to G42 in the United Arab Emirates, all of the systems we have sold to G42, or for which purchase orders have been placed by G42, to date have been or are expected to be deployed in the United States, which does not require an export license from BIS," a statement by Cerebras reads. "To the extent that we cannot export to a specific customer without a license from BIS, we may seek a license for the customer. However, the licensing process is time-consuming. There is no assurance that BIS will grant such a license or that BIS will act on the license application in a timely manner. Even if BIS issues a license, it may impose burdensome conditions that we or our customer cannot accept or decide not to accept." 

The company competes both against AI giant Nvidia as well as other supporters of AI processors, such as AMD and Intel. The main advantage of Cerebras's Wafer Scaling Engine (WSE) processors is high-bandwidth low-latency on-wafer interconnect that optimizes both performance and power consumption. While it is hard to produce wafer-scale processors, their performance, power efficiency, and bandwidth promise to ensure that Cerebras will have a special place on the market due to unique advantages.

Leading chipmakers TSMC and Samsung are discussing mega factory building projects in the United Arab Emirates (UAE), according to a report published by the Wall Street Journal (WSJ). The source report indicates that investments of $100 billion or more are being considered. However, neither TSMC nor Samsung confirmed any specific plans. To be clear, we aren’t talking about a TSMC and Samsung hook-up in the UAE; they would invest and build in the region separately.

According to the WSJ, top TSMC executives have recently visited the UAE to explore expanding manufacturing operations. Interestingly, the world’s largest contract chipmaker “talked about a plant complex on par with some of the company’s largest and most advanced facilities in Taiwan,” said unnamed people familiar with the matter. Projects like this could be worth more than $100 billion, according to the WSJ.

The claims regarding TSMC are undoubtedly eye-catching, if not a little superstitious, as the Taiwanese firm is well known for limiting its crown jewels, its top technologies, to facilities on its home turf. Even its newest factories in old and trusted allied nations like the USA, Germany, and Japan don’t tread on the toes of its most advanced facilities in Taiwan – so why should the UAE be any different?

In response to Reuters questions about its purported UAE plans, TSMC said it hasn’t announced anything new. Instead of addressing the question directly, it repeated a boilerplate statement about always being open to constructive discussion on the development of the semiconductor industry. 

Moving on to the Samsung rumors, we have a similar story. The source report says senior Samsung execs have also recently visited the UAE to discuss factory building plans. According to the WSJ, such projects may be funded by the UAE, with a central role for the Abu Dhabi-based Mubadala investment company. Plans are still in the early stages, and various technical and other hurdles must be navigated. According to Reuters, Samsung declined to comment when quizzed about its UAE plans.

The UAE has featured quite frequently in tech news in recent months. We have reported on the oil-rich Middle East being at the center of an influence war between the U.S. and China. Over recent months, the pull of the U.S. and the more advanced technologies of its allies seems to have won the region over. This was likely inevitable as countries like the UAE seek to diversify from fossil fuels into technology, with eyes on AI in particular.

Megafactories run by TSMC and Samsung inside the UAE would help cement the country’s position as a Middle East tech hub, delivering enviable access to the latest semiconductors. 

The best-known AI /tech company based in the UAE is probably G42. Earlier this month, this pivotal firm got the green light from the U.S. to import advanced Nvidia GPUs for its data centers, joining its Cerebras-powered systems. G42 is also known to have divested from China-backed projects and purged its data centers of Chinese parts. Perhaps the timing of these decisions signals that the doors to mega factory investments from companies like TSMC and Samsung are now open.

The U.S. has granted permission for G42, a datacenter AI company from the UAE, to procure advanced Nvidia AI processors, such as the H100 and H200, Semafor reports. This approval is a significant step forward for G42 in particular, which already collaborates with Cerebrus on various markets, and the UAE in general, which strides to diversify its economy into new markets, which happen to be AI.   

G42 has been working for quite a long time to secure Nvidia's H100 processors, which are now beginning to be deployed. The UAE has made substantial investments in its AI infrastructure, focusing on data security as it attempts to become a major player in the global AI market. However, given the dominance of Nvidia in the AI sector generally due to the versatility of the CUDA technology, it is close to impossible to build a competitive infrastructure without Nvidia's GPUs.  

To gain approval for the Nvidia processors, G42 took significant measures to meet  U.S. security standards. As part of its general strategy, G42 ceased its business ties with Chinese firms in late 2023, effectively betting on its relationship with the U.S. for future technological growth and a way to move beyond oil dependency.  

This divestment from China was crucial in addressing concerns within the Biden administration about the UAE’s partnerships with Chinese companies, particularly in the AI space. 

The company ensured its datacenters were built with hardware from Western suppliers, excluding Chinese components. Next up, G42's datacenters use military-grade encryption and have isolated compute systems from other components like security cameras and cooling systems. This separation reduces the risk of hackers accessing servers through vulnerabilities in other hardware. Older datacenters were purged of any Chinese parts, even if they were unused to prevent any potential backdoor access by foreign powers. 

There is a catch though and that catch is Microsoft. This company played a key role in G42 by investing $1.5 billion in the company. This investment strengthens the collaboration between the two companies and allows Microsoft to expand its Azure cloud business in emerging markets. When it comes to compliance with regulations, Microsoft is a company that knows the game of being compliant with regulators. 

Nvidia dominates the market of AI processors controlling over 80% of sales, according to some recent estimates. But Jim Keller, a legendary designer of processors and current Chief Executive Officer of Tenstorrent, believes that there are markets not served well by Nvidia. As a result, there are opportunities for Tenstorrent and other developers of AI processors. 

"There are lots of markets that are not well served by Nvidia," said Jim Keller in an interview with Nikkei. 

Jim Keller has a truly distinguished computer industry history, making waves at AMD, Intel, and Tesla, and is now heading up the development of AI processors at Tenstorrent. His leadership at Tenstorrent aims to deliver affordable alternatives to Nvidia's expensive GPUs that cost $20,000 - $30,000 or more each. Tenstorrent’s business approach aims to serve markets that Nvidia does not adequately address, particularly in the edge space. According to Tenstorrent, its Galaxy systems are three times more efficient and 33% less expensive than Nvidia's DGX, which are perhaps the world's most popular AI servers.

Tenstorrent is on track to release its second-generation multipurpose AI processor by the end of the year, Nikkei reports, without disclosing the name of the processor. Based on Tenstorrent's latest roadmap from last fall, the company intends to release its Black Hole standalone AI processor and Quasar low-power low-cost chiplets for multi-chiplet AI solutions. 

The company claims its upcoming processors provide performance efficiency comparable to Nvidia's AI GPUs. The touted efficiency and lower cost is partly achieved by avoiding usage of high-bandwidth memory (HBM) and using GDDR6 instead, which is a logical thing for entry-level and mainstream AI processors mostly designed for AI inference. Meanwhile, Tenstorrent says that its architecture is less memory bandwidth-hungry than competitors, which is a key reason for its higher efficiency and lower cost. 

While Tenstorrent yet has to grab a significant part of the AI processor market, the company for now focuses on cost-effective yet scalable AI solutions that can address a wide range of applications currently not served properly by Nvidia. However, these markets are not going to be blue oceans as many companies will try to address them with their products in the coming quarters battling against the entrenched Nvidia. Rather than compete with Nvidia head-on, it will be much easier for new entrants to address niche markets that are indeed not directly catered for by the green team.

Amid a national security review, the U.S. government has delayed granting export licenses to designers of advanced processors for AI workloads, such as AMD and Nvidia, for shipments to the Middle East. The U.S. government is concerned that GPUs for AI and HPC workloads could be resold to China; accessed by Chinese entities in the cloud to train large language models; or used to develop military equipment. 

For obvious reasons, this greatly affects businesses of AMD, Nvidia, and other developers of similar hardware, reports Bloomberg.

In October, the U.S. Commerce Department imposed new export rules for shipments of high-performance AI and HPC processors to other countries. The U.S. government now demands companies like AMD and Nvidia obtain an export license when they ship reasonably advanced processors to China, Macau, Saudi Arabia, Vietnam, the United Arab Emirates, and some other countries, including those from the so-called Group D:5 [PDF]. Recently, license applications from Nvidia, AMD, Intel, and Cerebras Systems have been delayed or left unanswered.

The U.S. government's strategy includes developing a comprehensive plan for the deployment of advanced chips overseas. This plan involves ensuring proper management and security of facilities used to train AI models. While companies getting processors from AMD, Cerebras, Intel, and Nvidia to equip their datacenters will not resell valuable hardware to Chinese entities (as this contradicts their business model), there are concerns about Chinese companies accessing these processors through Middle Eastern datacenters to train their AI models or even develop military capability.

The UAE and Saudi Arabia are aiming to diversify their economies from oil by becoming leaders in AI. Both countries view U.S.-based companies like Cerebras and Nvidia as crucial partners in this effort. Additionally, Microsoft invested $1.5 billion in the Abu Dhabi-based AI firm G42.

Saudi Arabia and other Middle Eastern countries have shown willingness to keep Chinese supply chains separate or divest from Chinese technology entirely. Yet, Saudi Arabia has partnered with China's Lenovo to establish an R&D center in Riyadh.

One of the less-noticed tidbits from last week's TSMC North American Technology Symposium was announcement that Tesla's Dojo system-on-wafer processor for AI training is now in mass production and is on track to be deployed shortly. More details about the giant processor were revealed at the event.

Tesla's Dojo system-on-wafer processor (or, as Tesla calls it, the Dojo Training Tile) relies on a 5-by-5 array of known good processor chips (which are reticle size, or close to that) that are placed on a carrier wafer and interconnected using TSMC's integrated fan-out (InFO) technology for wafer-scale interconnections (InFO_SoW). The InFO_SoW technology is designed to enable such high-performance connectivity that 25 dies of Tesla's Dojo would act like a single processor, reports IEEE Spectrum. Meanwhile, to make the wafer-scale processor uniform, TSMC fills in blank spots between dies with dummies. 

Since the Tesla Dojo Training Tile essentially packs 25 ultra-high-performance processors, it is exceptionally power hungry and requires a sophisticated cooling system. To feed the system-on-wafer, Tesla uses a highly complex voltage-regulating module that delivers 18,000 Amps of power to the compute plane. The latter dissipates as much as 15,000W of heat and thus requires liquid cooling. 

Tesla has yet to disclose the performance of its Dojo system-on-wafer — though, considering all the challenges with its development, it seems poised to be a very powerful solution for AI training. 

Wafer-scale processors, such as Tesla's Dojo and Cerebras' wafer scale engine (WSE), are considerably more performance-efficient that multi-processor machines. Their main advantages include high-bandwidth and low-latency communications between cores, reduced power delivery network impedance, and superior energy efficiency. Additionally, these processors can benefit from having redundant 'extra' cores — or, in case of Tesla, known-good processor cores. 

But there are inherent challenges with such processors for now. System-on-wafers currently have to exclusively use on-chip memory, which is not flexible — and, which may not be enough for all types of applications. This will be solved by the next-generation system-on-wafer platform called CoW_SoW, which will enable 3D stacking and installation of HBM4 memory on processor tiles. 

For now, only Cerebras and Tesla have system-on-wafer designs. But TSMC is certain that, over time, more developers of AI and HPC processors will build wafer scale designs.

TSMC is taking the wafer-scale fabrication battle into the third dimension with a new technology. At its North American Technology Symposium, the company introduced its next-generation system-on-wafer platform—CoW-SoW—that will enable 3D integration with wafer-scale designs. This builds on the InFO_SoW system-on-wafer integration technology technology that TSMC introduced in 2020, which lets it build wafer-scale logic processors. So far, only Tesla has adopted this tech for its Dojo supercomputer, which TSMC says is now in production.

In its forthcoming CoW-SoW platform, TSMC will merge two of its packaging methods — InFO_SoW and System on Integrated Chips (SoIC) — into its system-on-wafer platform. Using the Chip-on-Wafer (CoW) tech will enable the stacking of memory or logic directly atop a system-on-wafer. The new CoW_SoW technology is expected to be ready for large-scale production by 2027, though it remains to be seen when actual products arrive on the market. 

"In the future, using wafer-level integrations [will allow] our customers to integrate even more logic and memory together," said Kevin Zhang, Vice President of Business Development at TSMC. "SoW is no longer a fiction; this is something we already work with our customers [on] to produce some of the products already in place. We think by leveraging our advanced wafer-level integration technology, we can provide our customer a very important path that allows them to continue to grow their capability to bring in more computation, more energy efficient computation, to their AI cluster or [supercomputer]."

Currently, TSMC's CoW-SoW focuses on integrating wafer-scale processors with HBM4 memory. These next-generation memory stacks will feature a 2048-bit interface, which will make it feasible to integrate HBM4 directly on top of logic chips. Meanwhile, it may also make sense to stack additional logic on wafer-scale processors to optimize costs.

Wafer-scale processors in general (i.e., Cerebras's WSE), and InFO_SoW-based processors in particular, offer significant performance and efficiency benefits, including high-bandwidth and low-latency core-to-core communications, low power delivery network impedance, and high energy efficiency. As an added bonus, such processors also have additional redundancy in the form of 'extra' cores.

However, the InFO_SoW technology has certain limitations. For instance, wafer-scale processors made using this method rely entirely on on-chip memory, which may fall short for future AI needs (but is good for now). CoW-SoW will solve this, as it will allow putting HBM4 on such wafers. In addition, InFO_SoW wafers are processed using a single node, and this node does not support 3D stacking, which will be supported by CoW-SoW products.

MGX, a newly established investment company from Abu Dhabi, is in talks to finance Sam Altman's ambitious plan to build excessive semiconductor manufacturing capacity for AI processors, reports the Financial Times. If the talks succeed, the move will be in line with the United Arab Emirates' strategy to become a key player in the global artificial intelligence industry.

OpenAI's push to develop its semiconductors is driven by the need to reduce dependency on Nvidia's AI GPUs, such as the H100. Meanwhile, besides developing AI processors, Sam Altman wants to ensure their steady supply to OpenAI and potentially other companies. After witnessing two major semiconductor supply crises in recent years (first for the automotive and PC industries and then for the AI industry), he seems to believe that traditional contract makers of chips do not have sufficient manufacturing capacities to fulfill the global demand for AI chips. As a result, he allegedly wants more fabs to be built.

OpenAI's CEO, Sam Altman, has reportedly estimated that the cost of building new semiconductor manufacturing facilities and supporting infrastructure could reach up to $7 trillion. While it is still unclear whether the chip venture is an OpenAI project or Sam Altman's project (most likely the latter), the CEO has been touring around the world talking to chipmakers and seeking support from nation-states, including discussions with Singapore's Temasek, as traditional venture capitalists are unlikely to invest such vast sums.

MGX, an AI-focused fund launched by the UAE, is chaired by Sheikh Tahnoon bin Zayed al-Nahyan, the national security adviser. The fund aims to make Abu Dhabi a central hub for AI development, leveraging the country's financial resources and political backing. The UAE's ambition to become a global AI powerhouse is evident in its efforts to attract leading figures in the AI industry, including Elon Musk, who has expressed interest in partnering with the Gulf state for his AI venture, xAI.

Sheikh Tahnoon's role extends beyond chairing MGX. He also leads G42, an AI-focused holding from the UAE, backed by Abu Dhabi's sovereign investment fund Mubadala. G42 has established partnerships with major players in the AI industry, including OpenAI, Microsoft, and Cerebras. The establishment of MGX, in collaboration with G42 and Mubadala, is another AI-related strategic move from Abu Dhabi.

The UAE's proactive approach to AI is highlighted by its early adoption of AI initiatives, such as appointing the world's first AI minister in 2017 and opening an AI-focused graduate university in 2019. These efforts demonstrate the country's dedication to advancing its position in the AI industry.

However, the UAE's AI ambitions come amid a complicated geopolitical landscape, such as the U.S.-China trade tensions that extend well beyond trade to national security grounds. G42 has had to reassess its partnerships with Chinese companies, including Huawei, in response to concerns from the U.S.

Cerebras Systems has unveiled its Wafer Scale Engine 3 (WSE-3), a breakthrough AI wafer-scale chip with double the performance of its predecessor, the WSE-2. This new device packs 4 trillion transistors made on TSMS's 5nm-class fabrication process; 900,000 AI cores; 44GB of on-chip SRAM; and has a peak performance of 125 FP16 PetaFLOPS. Ceberas's WSE-3 will be used to train some of the industry's largest AI models. 

The WSE-3 powers Cerebras's CS-3 supercomputer, which can be used to train AI models with up to 24 trillion parameters — a significant leap over supercomputers powered by the WSE-2 and other modern AI processors. The supercomputer can support 1.5TB, 12TB, or 1.2PB of external memory, which allows it to store massive models in a single logical space without partitioning or refactoring — streamlining the training process and enhancing developer efficiency. 

In terms of scalability, the CS-3 can be configured in clusters of up to 2048 systems. This scalability allows it to fine-tune 70 billion parameter models in just one day with a four-system setup, and to train a Llama 70B model from scratch in the same timeframe at full scale. 

The latest Cerebras Software Framework offers native support for PyTorch 2.0 and also supports dynamic and unstructured sparsity, which can accelerate training — up to eight times faster than traditional methods. 

Cerebras has emphasized the CS-3's superior power efficiency and ease of use. Despite doubling its performance, the CS-3 maintains the same power consumption as its predecessor. It also simplifies the training of large language models (LLMs), requiring up to 97% less code compared to GPUs. For example, a GPT-3 sized model requires only 565 lines of code on the Cerebras platform, according to the company. 

The company has already seen significant interest in the CS-3, and has a substantial backlog of orders from various sectors — including enterprise, government, and international clouds. Cerebras is also collaborating with institutions such as the Argonne National Laboratory and the Mayo Clinic, highlighting the CS-3's potential in healthcare. 

A strategic partnership between Cerebras and G42 is also set to expand with the construction of the Condor Galaxy 3, an AI supercomputer featuring 64 CS-3 systems (packing a whopping 57,600,000 cores). Together, the two companies have already created two of the biggest AI supercomputers in the world: the Condor Galaxy 1 (CG-1) and the Condor Galaxy 2 (CG-2), which are based in California and have a combined performance of 8 ExaFLOPs. This partnership aims to deliver tens of exaFLOPs of AI compute, globally.

"Our strategic partnership with Cerebras has been instrumental in propelling innovation at G42, and will contribute to the acceleration of the AI revolution on a global scale," said Kiril Evtimov, Group CTO of G42. "Condor Galaxy 3, our next AI supercomputer boasting 8 exaFLOPs, is currently under construction and will soon bring our system’s total production of AI compute to 16 exaFLOPs."

Scientists from the Institute of Computing Technology at the Chinese Academy of Sciences introduced an advanced 256-core multi-chiplet and have plans to scale the design up to 1,600-core chips that employ an entire wafer as one compute device.

It is getting harder and harder to increase transistor density with every new generation of chips, so chipmakers are looking for other ways to increase performance of their processors, which includes architectural innovations, larger die sizes, multi-chiplet designs, and even wafer-scale chips. The latter has only been managed by Cerebras so far, but it looks like Chinese developers are looking towards them as well. Apparently, they have already built a 256-core multi-chiplet design and are exploring ways to go wafer-scale, using an entire wafer to build one large chip. 

Scientists from the Institute of Computing Technology at the Chinese Ac ademy of Sciences introduced an advanced 256-core multi-chiplet compute complex called Zhejiang Big Chip in a recent publication in the journal Fundamental Research, as reported by The Next Platform. The multi-chiplet design consists of 16 chiplets containing 16 RISC-V cores each and connected to each other in a conventional symmetric multiprocessor (SMP) manner using a network-on-chip so that the chiplets could share memory. Each chiplet has multiple die-to-die interfaces to connect to neighbor chiplets over a 2.5D interposer and the CAS researchers say that the design is scalable to 100 chiplets, or to 1,600 cores. 

Zhejiang chiplets are reportedly made on a 22nm-class process technology, presumably by Semiconductor Manufacturing International Corp. (SMIC). We are not sure how much power a 1,600-core assembly interconnected using an interposer and made on a 22nm production node would consume. As The Next Platform points out, nothing stops CAS from producing a 1,600-core wafer-scale chip, which would greatly optimize power consumption and performance due to reduced latencies.

The paper explores the limits of lithography and chiplet technology and discusses the potential of this new architecture for future computing needs. Multi-chiplet designs could be used to build processors for exascale supercomputers, the researchers note, something that AMD and Intel do today.

"For the current and future exascale computing, we predict a hierarchical chiplet architecture as a powerful and flexible solution," the researchers wrote. “The hierarchical-chiplet architecture is designed as many cores and many chiplets with hierarchical interconnect. Inside the chiplet, cores are communicated using ultra-low-latency interconnect while inter-chiplet are interconnected with low latency beneficial from the advanced packaging technology, such that the on-chiplet latency and the NUMA effect in such high-scalability system can be minimized."

Meanwhile, the CAS researchers propose to use multi-level memory hierarchy for such assemblies, which could potentially introduce difficulties with programming of such devices. 

"The memory hierarchy contains core memory [caches], on-chiplet memory and off-chiplet memory," the description reads. "The memory from these three levels vary in terms of memory bandwidth, latency, power consumption and cost. In the overview of hierarchical-chiplet architecture, multiple cores are connected through cross switch and they share a cache. This forms a pod structure and the pod is interconnected through the intra-chiplet network. Multiple pods form a chiplet and the chiplet is interconnect through the inter-chiplet network and then connects to the off-chip(let) memory. Careful design is needed to make full use of such hierarchy. Reasonably utilizing the memory bandwidth to balance the workload of different computing hierarchy can significantly improve the chiplet system efficiency. Properly designing the communication network resource can ensure the chiplet collaboratively performing the shared-memory task." 

The Big Chip design could also take advantage of such things as optical-electronic computing, near-memory computing, and 3D stacked memory. However, the paper stops short of providing specific details on the implementation of these technologies or addressing the challenges they might pose in the design and construction of such complex systems. 

Meanwhile, The Next Platform assumes that CAS has already built its 256-core Zhejiang Big Chip multi-chiplet compute complex. From here, the company can explore performance of its chiplet design and then make decisions regarding system-in-packages with a higher number of cores, different classes of memory, and wafer-scale integration.

G42, a United Arab Emirates-based company specializing in cloud artificial intelligence (AI) services vows to cease using Huawei hardware, reports the Financial Times. The statement — with another one due in about a week — comes after it emerged that American secret services were investigating G42's ties with China-based Huawei.

G42 is a company that runs a fleet of Huawei's HiSilicon-based devices for its AI service provision. Meanwhile, G42 is preparing to use CS-2 hardware from Cerebras in a multi-billion deal that involves the creation of a network of AI-oriented supercomputers. The U.S. government has raised concerns over G42 and its ties with Huawei recently, precipitating two company statements to leading business media in the space of a week - asserting that it will not continue working with Huawei.

"For better or worse, as a commercial company, we are in a position where we have to make a choice," chief executive Peng Xiao told the Financial Times. "We cannot work with both sides. We cannot. […] The impression we are getting from [the] US government and US partners is, we need to be very cautious."

For now, G42 is poised to phase out the use of AI hardware from Huawei for running its AI workloads. The statement could mean that the company is not going to train any new AI models on its existing hardware from the Chinese company, though we must say that the CEO of G42 did not state this explicitly. Meanwhile, what he did say is that Huawei can hardly offer his company better hardware. This is expected, given the fact that G42 has inked a multi-billion deal with Cerebras.

"In order for us to further our relationship — which we cherish — with our U.S. partners, we simply cannot do much more with [previous] Chinese partners," Xiao added.

As G42 deploys its Cerebras-based machines, it could theoretically transfer its existing inference workloads to them. Yet, the technical and economic possibility of this is uncertain, to say the least. Furthermore, as the U.S. severely limits Chinese companies' access to AI hardware, they have no choice but to use domestically developed and produced processors or opt for cloud AI services, such as those from G42.

"It is unsurprising that G42, as an AI-focused start-up, engages with China, given China's extensive role in the global AI value chain, from hardware, talent, to end market," said Nikki Sun, an academy associate in the digital society initiative at the Chatham House think-tank. "Severing these connections entirely seems very unlikely."

G42 is building a network of AI-oriented supercomputers based on Cerebras's WSE-2, the largest 'wafer-size' chip with 2.6 trillion transistors and 850,000 AI cores. The device powers the CS-2 systems in G42's Condor Galaxy supercomputers, including the CG-1 in California. This supercomputer offers up to four ExaFLOPS for large language models with 600 billion to 100 trillion parameters. In the future, G42 and Cerebras will deploy six such supercomputers globally, raising CIA concerns due to their potential use by Chinese entities for AI training. This development places G42 amid U.S.-China tensions, yet it aligns with the UAE's economic diversification.

The U.S. government has raised concerns about G42, a United Arab Emirates-based technology holding company building up a network of A.I. supercomputers with massive performance. The company is apparently overseen by Sheikh Tahnoon bin Zayed of the UAE and has connections with Chinese firms the U.S. considers security threats (such as Huawei). G42 is set to use CS-2 hardware from Cerebras, a company that recently criticized Nvidia for supplying A.I. and HPC GPUs to "arm" Chinese companies, according to a report from the New York Times.

Cerebras' WSE-2 processors are the largest chips ever brought to market, with 2.6 trillion transistors and 850,000 AI-optimized cores all packed on a single wafer-sized 7nm processor, and they come in CS-2 systems. G42 is building several Condor Galaxy supercomputers for A.I. based on the Cerebras CS-2 systems. The CG-1 supercomputer in Santa Clara, California, promises to offer four FP16 Exaflops of performance for large language models featuring up to 600 billion parameters and offers expansion capability to support up to 100 trillion parameter models. 

Perhaps most worrisome for the U.S. government, CG-1, though located in the U.S., is only the first of three A.I. supercomputers (CG-1, CG-2, and CG-3) based on Cerebras hardware. Meanwhile, G42 and Cerebras plan to launch six four-Exaflop Condor Galaxy supercomputers worldwide; these machines are why the CIA is suspicious. 

Under the leadership of chief executive Peng Xiao, G42's expansion has been marked by notable agreements — including a partnership with AstraZeneca and a $100 million collaboration with Cerebras to develop the 'world's largest supercomputer.' But classified reports from the CIA paint a different picture: they suggest G42's involvement with Chinese companies — specifically Huawei — raises national security concerns. The CIA believes G42 is at risk of acting as a channel for sensitive American technologies and genetic data.

Xiao has been the focal point of the U.S. investigation, but the conclusions of the CIA document about Xiao are unclear. The U.S. administration has held discussions with UAE officials and has urged G42 to distance itself from Chinese companies. The U.S. has even suggested it may enact sanctions against the company if it continues to associate with Chinese entities.

Since these machines will be physically located outside of the U.S. and offer formidable performance, the CIA believes they could be used to train large language models for Chinese entities. As a result, G42 may now be at the forefront of the conflict between the U.S. and China. Of course, G42 is also an important instrument in the UAE's strategy to diversify its economy beyond oil. The UAE is strengthening its ties with China and Russia and is reducing its reliance on the U.S.

G42 declined to comment to the NYT about its Chinese partnerships and U.S. concerns. In a statement, G42 senior executive Talal Al Kaissi highlighted the company's global tech collaborations, mentioning talks with Microsoft and work with Cerebras (which is set to replace its hardware that originates from Huawei). Al Kaissi stressed G42's commitment to adhering to U.S. regulations, continuing ongoing discussions with U.S. agencies, and partnering with companies that align with their values in responsible A.I. development.

Nvidia has been remarkably nimble in its GPU specification tweaking in response to the US sanctions on tech flowing to China. However, Cerebras CEO Andrew Feldman reckons the green team’s activities are a classic case of following the letter but not the spirit of the law. “I think Nvidia armed China single-handedly,” Feldman said to The Register, before accusing the firm of lacking “moral responsibility.” Moreover, any firms looking to circumvent, limbo under, or find loopholes in matters of national policy were called out by Feldman for being “un-American.”

In his complaints about Nvidia, the Cerebras CEO makes it quite clear that rules and regulations put in place as a matter of national policy, with implications for national security, are a special case. “We believe very much in the US doing business with its allies, and when the Department of Commerce or when the President sets a rule, that you obey the spirit, not just the letter,” said Feldman to The Register. “When someone says this is a national policy, and here's some rules and you run up to within an inch of it, and you try, and try and circumvent the intent with a loophole, you make yourself look un-American.” Specifically, Nvidia “ran right up to the edge of the guidelines,” on China, Feldman complained.

Cerebras hasn’t done business in China, even before sanctions came into place. However, recent US tech export rule changes still affect its business as they cover several other countries. It didn’t go without comment in the source publication that Intel and AMD are also amenable to tweaking high-performance chip designs to limbo under China chip sanctions. Perhaps if Nvidia, Intel, AMD, et al didn’t act like this, in the pursuit of the best profits, shareholders might be quite unhappy.

We don’t expect any serious backlash against companies that don’t follow Cerebras' philosophy. But this could easily change if China ever uses any of the exported tech in a conflict affecting Western interests.

Cerebras and Nvdia at SC23

The rival-poking and thought-provoking comments by Feldman were made at the currently running SC23, where both Cerebras and Nvidia have been quite busy taking care of business.

At SC23, Cerebras announced it was behind a newly completed four-exaFLOP AI Supercomputer. It also highlighted (PDF) how its Cerebras CS-2 “is 130x faster than Nvidia A100” on a nuclear physics simulation workload. Cerebras has maintained a booth at the conference venue and hosted several SC23 sessions this week.

Nvidia’s big news at SC23 was its Grace Hopper GH200 GPU super chip and news of machines like the 1 ExaFLOP Jupiter Supercomputer. However, just before the kickoff of SC23, we reported that Nvidia had already prepared three new GPUs for artificial intelligence (AI) and high-performance computing (HPC) applications tailored for the Chinese market. According to sources, the Nvidia HGX H20, L20 PCle, and L2 PCle GPUs were already being shipped to China server makers. No time seems to have been wasted, as US sanctions on China were adjusted just a few weeks ago.

While everyone praises Nvidia — whose market capitalization broke $1 trillion earlier this year — for the ongoing artificial intelligence (AI) and high-performance computing (HPC) megatrends, there's another company that not only heavily benefits from said AI and HPC megatrends, but which basically controls production of AI processors.

Tens of Billions of Dollars

That company is TSMC — which produces some of the most complex processors for AI and HPC machines ever built, including those from Nvidia, AMD, Intel, Tenstorrent, Cerebras, and Graphcore (just to name a few), according to a report from DigiTimes. Nvidia's A100 and H100 (as well as its A800 and H800 derivatives for the Chinese market), the most popular compute GPUs used for AI and HPC workloads, are made at TSMC, as are AMD's EPYC CPUs and Instinct GPUs. Rising AI and HPC stars such as Tenstorrent, and developers of such exotic things as wafer scale processors such as Cerebras also chose TSMC for their products. 

While TSMC does not disclose how much it earns from selling CPUs, GPUs, and specialized processors or SoCs for AI, datacenter, HPC, and servers, these products use a lot of silicon — so TSMC probably earns tens of billions making those products for its high-profile customers. For example, Nvidia's GH100 compute GPU has a die size of 814 mm2, whereas AMD's EPYC 'Genoa' uses 12 Zen 4-based CCD chiplets — each measuring around 72 mm2 and thus using 864 mm2 of N5 silicon.

While we do not have revenue splits for TSMC's rivals Samsung Foundry and GlobalFoundries, given that these companies are so significantly behind the Taiwanese contract maker of chips, it is safe to say that TSMC benefits from AI and HPC in general. It particularly dominates shipments of AI GPUs, as it makes them for both Nvidia (which controls over 90% of shipments) and AMD (which controls less than 10%). 

AI and HPC Gaining Importance for TSMC

TSMC itself provides a rather detailed revenue split that clearly distinguishes between automotive, IoT, smartphones, and high-performance computing, but it is not detailed enough to tell the difference between chips for AI, HPC, client PCs, servers, and game consoles. For TSMC, all of these processors and SoCs belong to the HPC segment — a segment that is thriving. 

HPC products accounted for 30% of TSMC's revenue, or $10.389 billion, in 2019. That same year, smartphone SoCs accounted for 49% of TSMC's revenue, or $16.97 billion. But the share of HPC products in TSMC's revenue has been growing: the category accounted for 33% in 2020 ($15 billion), 37% in 2021 ($21 billion), and 41% in 2022 ($31.11 billion). The trend has been the opposite for smartphone SoCs, which accounted for 39% of TSMC's sales in 2022 ($29.59 billion).

While AMD and Nvidia buy boatloads of datacenter-oriented silicon from TSMC, Apple is still the largest customer for the world's No. 1 maker of chips — especially now that it has both smartphone and PC SoCs (which fall into the HPC category). Apple alone was responsible for approximately 23% of TSMC's total sales in 2022, according to DigiTimes.

More Chips Incoming

As the semiconductor sector recovers from its downturn, rising interest for generative AI is stimulating the market. Nvidia is benefiting greatly from this AI surge through its TSMC-manufactured A100/A30/A800 and H100/H800 compute GPUs. Similarly, AMD is expanding orders with TSMC for its upcoming Instinct MI300 series products that will enter mass production in the second half of 2023 at TSMC's N5-class node.

In addition, Apple, AMD, and Nvidia are committed to use TSMC's N3 (3nm-class) and N2 (2nm-class) production technologies for future chips, according to the DigiTimes report.

Cerebras, the company that builds the world's largest chip, the Wafer Scale Engine 2 (WSE-2), unveiled its Andromeda supercomputer today. Andromeda combines 16 of the wafer-sized WSE-2 chips into one cluster with 13.5 million AI-optimized cores that the company says delivers up to 1 Exaflop of AI computing horsepower, or 120 Petaflops of 16-bit half-precision. 

The chips are housed in sixteen CS-2 systems. Each chip delivers up to 12.1 TB/s of internal bandwidth (96.8 Terabits) to the AI cores, but the data is fed to the CS-2 processors via 100 GbE networking spread across 124 server nodes in 16 racks. In total, those servers are powered by 284 third-gen EPYC Milan processors wielding 64 cores apiece, totaling 18,176 cores. 

The entire system consumes 500 KW, which is a drastically lower amount of power than somewhat-comparable GPU-accelerated supercomputers. However, scaling a workload across such massively-parallel supercomputers has long been one of the primary inhibitors — at some point, scaling tends to break down, so adding more hardware results in a rapidly diminishing point of returns. 

However, Cerebras says that its implementation scales nearly linearly with GPT-class large language models, like GPT-3, GPT-J, and GPT-NeoX. Andromeda can also process 2.5-billion and 25 billion-parameter models that standard GPU clusters simply can't handle due to memory limitations. 

As a reminder, the Cerebras WSE-2 is the world's largest single-chip processor. Each 7nm chip is specifically designed to tackle AI workloads with 850,000 AI-specific cores spread out over 46,225 mm2 of silicon packed with 2.6 trillion transistors. The chip has 40 GB of on-chip SRAM memory, 20 petabytes of memory bandwidth, and 220 petabits of aggregate fabric bandwidth. Each WSE-2 consumes 15kW of power. 

Workload scaling is sub-par on most large systems, leading to a diminishing point of returns, often due to code, memory, fabric and/or networking limitations. However, Cerebras has shown that its CS-2 systems scale nearly linearly via data parallelism with no changes to the underlying code — the company's Andromeda supercomputer began crunching through workloads within ten minutes of being fully connected. 

The sixteen CS-2s use the company's MemoryX and Swarm-X interconnect to simplify and orchestrate splitting the model up across the systems. This approach stores model parameters off-chip in a MemoryX cabinet while keeping the model on-chip, allowing a single system to compute larger AI models than before and combating the typical latency and memory bandwidth issues that often restrict scalability with groups of processors. Cerebras says this allows the system to scale near-linearly across up to 192 CS-2 systems. 

Andromeda is deployed at the Colovore data center in Santa Clara, California. The company has opened Andromeda up to both customers and academic researchers, including the Argonne National Laboratory, which states it has already  put the entire COVID-19 genome into a sequence window and ran the workload across up to 16 nodes with "near-perfect linear scaling." That project is now a finalist for the prestigious ACM Gordon Bell Special Prize. Other users include JasperAI and the University of Cambridge. You can learn more about the system here. 

A team of researchers with the Massachusetts Institute of Technology (MIT) have been working on a new hardware resistor design for the next era of electronics scaling - particularly in AI processing tasks such as machine learning and neural networks. 

Yet in what may seem like a throwback (if a throwback to the future can exist), their work focuses on a design that's more analog than digital in nature. Enter protonic programmable resistors - built to accelerate AI networks by mimicking our own neurons (and their interconnecting synapses) while accelerating their operation a million times -- and that's the actual figure, not just hyperbole.

All of this is done while cutting down energy consumption to a fraction of what's required by transistor-based designs currently used for machine-learning workloads, such as Cerebras' record-breaking  Wafer Scale Engine 2.

While our synapses and neurons are extremely impressive from a computational standpoint, they're limited by their "wetware" medium: water.

While water's electrical conduction is enough for our brains to operate, these electrical signals work through weak potentials: signals of about 100 millivolts propagating over milliseconds, through trees of interconnected neurons (synapses correspond to the junctions through which neurons communicate via electrical signals). One issue is that liquid water decomposes with voltages of 1.23 V - more or less the same operating voltage used by the current best CPUs. So there's a difficulty in simply "repurposing" biological designs for computing.

“The working mechanism of the device is electrochemical insertion of the smallest ion, the proton, into an insulating oxide to modulate its electronic conductivity. Because we are working with very thin devices, we could accelerate the motion of this ion by using a strong electric field, and push these ionic devices to the nanosecond operation regime,” explains senior author Bilge Yildiz, the Breene M. Kerr Professor in the departments of Nuclear Science and Engineering and Materials Science and Engineering.

Another issue is that biological neurons aren't built on the same scale as modern transistors are. They're much bigger - ranging in sizes from 4 microns (.004 mm) to 100 microns (.1 mm) in diameter. When the latest available GPUs already carry transistors at the 6 nm range (with a nanometre being 1,000 times smaller than a micron), you can almost imagine the difference in scale, and how much more of these artificial neurons you can fit into the same space.

The research focused on creating solid-state resistors which, as the name implies, create resistance to electricity's passage. Namely, they resist the ordered movement of electrons (negatively-charged particles). If using material that resists electricity's movement (and that thus should in turn generate heat) sounds counterintuitive, well, it is. But there are two distinct advantages to analog deep-learning compared to its digital counterpart.

First, in programming resistors, you are including the required data for training in the resistors themselves. When you program their resistance (in this case, by increasing or reducing the number of protons in certain areas of the chip), you're adding values to certain chip structures. This means that information is already present in the analog chips: There's no need to ferry more of it in and out towards external memory banks, which is exactly what happens in most current chip designs (and RAM or VRAM). All of this saves latency and energy.

Second, MIT's analog processors are architected in a matrix (remember Nvidia's Tensor cores?). This means they're more like your GPUs than your CPUs, in that they conduct operations in parallel. All computation happens simultaneously.

MIT's protonic resistor design operates at room temperature, which is easier to achieve than our brain's 38.5 ºC through 40 ºC. Yet it also allows for voltage modulation, a required feature in any modern chip, allowing the input voltage to be increased or decreased according to the requirements of the workload - with consequences on power consumption and temperature output.

According to the researchers, their resistors are a million times faster (again, an actual figure) than previous-generation designs, due to them being built with phosphosilicate glass (PSG), an inorganic material that is (surprise) compatible with silicon manufacturing techniques, because it's mainly silicon dioxide.

You've seen it yourself already: PSG is the powdery desiccant material found in those tiny bags that come in the box with new hardware pieces to remove moisture.

“With that key insight, and the very powerful nanofabrication techniques we have at MIT.nano, we have been able to put these pieces together and demonstrate that these devices are intrinsically very fast and operate with reasonable voltages,” says senior author Jesús A. del Alamo, the Donner Professor in MIT’s Department of Electrical Engineering and Computer Science (EECS). “This work has really put these devices at a point where they now look really promising for future applications.”

Just like with transistors, the more resistors in a smaller area, the higher the compute density. When you reach a certain point, this network can be trained to achieve complex AI tasks like image recognition and natural language processing. And all this is done with reduced power requirements and extremely increased performance.

Perhaps materials research will save Moore's Law from its untimely death.

Cerebras, the company behind the world's largest accelerator chip in existence, the CS-2 Wafer Scale Engine, has just announced a milestone: the training of the world's largest NLP (Natural Language Processing) AI model in a single device. While that in itself could mean many things (it wouldn't be much of a record to break if the previous largest model was trained in a smartwatch, for instance), the AI model trained by Cerebras ascended towards a staggering - and unprecedented - 20 billion parameters. All without the workload having to be scaled across multiple accelerators. That's enough to fit the internet's latest sensation, the image-from-text-generator, OpenAI's 12-billion parameter DALL-E.

The most important bit in Cerebras' achievement is the reduction in infrastructure and software complexity requirements. Granted, a single CS-2 system is akin to a supercomputer all on its own. The Wafer Scale Engine-2 - which, like the name implies, is etched in a single, 7 nm wafer, usually enough for hundreds of mainstream chips - features a staggering 2.6 trillion 7 nm transistors, 850,000 cores, and 40 GB of integrated cache in a package consuming around 15kW.

Keeping up to 20 billion-parameter NLP models in a single chip significantly reduces the overhead in training costs across thousands of GPUs (and associated hardware and scaling requirements) while doing away with the technical difficulties of partitioning models across them. Cerebras says this is "one of the most painful aspects of NLP workloads," sometimes "taking months to complete."

It's a bespoke problem that's unique not only to each neural network being processed, the specs of each GPU, and the network that ties it all together - elements that must be worked out in advance before the first training is ever started. And it can't be ported across systems.

Pure numbers may make Cerebras' achievement look underwhelming - OpenAI's GPT-3, an NLP model that can write entire articles that may sometimes fool human readers, features a staggering 175 billion parameters. DeepMind's Gopher, launched late last year, raises that number to 280 billion. The brains at Google Brain have even announced the training of a trillion-parameter-plus model, the Switch Transformer.

“In NLP, bigger models are shown to be more accurate. But traditionally, only a very select few companies had the resources and expertise necessary to do the painstaking work of breaking up these large models and spreading them across hundreds or thousands of graphics processing units,” said Andrew Feldman, CEO and Co-Founder of Cerebras Systems. “As a result, only very few companies could train large NLP models – it was too expensive, time-consuming and inaccessible for the rest of the industry. Today we are proud to democratize access to GPT-3XL 1.3B, GPT-J 6B, GPT-3 13B and GPT-NeoX 20B, enabling the entire AI ecosystem to set up large models in minutes and train them on a single CS-2.” 

Yet just like clockspeeds in the world's Best CPUs, the number of parameters is but a single possible indicator of performance. Recently, work has been done in achieving better results with fewer parameters - Chinchilla, for instance, routinely outperforms both GPT-3 and Gopher with just 70 billion of them. The aim is to work smarter, not harder. As such, Cerebras' achievement is more important than might first meet the eye - researchers are bound to be able to fit increasingly complex models even if the company does say that its system has the potential to support models with "hundreds of billions even trillions of parameters".

This explosion in the number of workable parameters makes use of Cerebras' Weight Streaming tech, which can decouple compute and memory footprints, allowing for memory to be scaled towards whatever the amount is needed to store the rapidly-increasing number of parameters in AI workloads. This enables set-up times to be reduced from months to minutes, and to easily switch between models such as GPT-J and GPT-Neo "with a few keystrokes".

“Cerebras’ ability to bring large language models to the masses with cost-efficient, easy access opens up an exciting new era in AI. It gives organizations that can’t spend tens of millions an easy and inexpensive on-ramp to major league NLP,” said Dan Olds, Chief Research Officer, Intersect360 Research. “It will be interesting to see the new applications and discoveries CS-2 customers make as they train GPT-3 and GPT-J class models on massive datasets.”

AMD vs Nvidia. If you're building a gaming PC, you'll inevitably be faced with choosing between the two GPU heavyweights. Both companies make GPUs that power the best graphics cards, fighting for supremacy in our GPU benchmarks hierarchy. AMD vs Nvidia isn't the only decision you’ll need to make when building a PC, of course. You'll also need to choose between AMD vs Intel CPUs. Our focus here will be on graphics, however, and we'll be looking at performance, features, drivers and software, power and efficiency, pricing and more.

The AMD vs Nvidia flame wars have been cooking since the late 90s, with Nvidia currently leading in the GPU arena by many metrics. Its graphics cards account for the majority of GPUs on the Steam Hardware Survey, for example, and in terms of pure finances, Nvidia is worth roughly three times as much as AMD (with a large chunk of AMD's resources devoted to CPUs).

But we're not interested in the distant past or finances. We want to find a winner in the current battle of AMD vs Nvidia GPUs. That primarily means looking at AMD Big Navi and Nvidia Ampere graphics cards — and maybe one of these days, we'll even need to add Intel Arc into the mix.

It's important to keep the big picture in view throughout this analysis. We're not just focusing on the fastest GPU, or the most power-efficient GPU, or the best bang-for-the buck GPU. We'll consider all of the factors in each category, from budget to mid-range to high-end and extreme GPUs, along with the tech behind the GPUs. We will declare a winner today, but of course this isn't the end of the war. It's more like owning the heavyweight GPU title: A victory today doesn't mean your opponent won't come back leaner and meaner next year.

With that preamble out of the way, let's pull out the boxing gloves and go the rounds with AMD vs Nvidia.

AMD vs Nvidia: Gaming Performance 

For decades, faster GPUs have enabled game developers to create increasingly detailed and complex worlds. While you can find everything from budget GPUs to high-end offerings from both AMD and Nvidia, when it comes to outright performance, Nvidia has a slight overall lead thanks to the chunky GeForce RTX 3090 Ti.

Beyond the pole position, however, it's a closer match. If you look at our GPU benchmarks hierarchy, you'll see that AMD's RX 6950 XT owns the top spot at 1080p and 1440p, and Nvidia only wins at 4K or in ray tracing games. Of the top ten fastest GPUs, four are AMD and six are Nvidia, but part of that is thanks to quantity rather than truly different GPUs — the RTX 3080 12GB takes a bit of RTX 3080 Ti and a bit of RTX 3080 and mixes them together into a card that ended up matching the 3080 Ti at a lower price point.

Of course, the main benchmarks only look at games running APIs and settings that work on all GPUs, which means we haven't included ray tracing or DLSS in the results. We also haven't included any FSR results, and CPU bottlenecks certainly play a role at lower resolutions. Here's the updated 2022 performance rankings, showing the overall performance from eight games and four settings/resolutions combinations four our standard test suite, and four more charts for our ray tracing suite that uses six complex DXR (DirectX Raytracing) games.

Nvidia's RTX 3090 Ti isn't remotely affordable, while the GeForce RTX 3080 and Radeon RX 6800 XT represent a better view of performance. Those two trade blows in traditional rasterization games, with AMD taking a slight lead, while Nvidia easily jumps ahead — often by a large margin — as soon as ray tracing and/or DLSS get turned on. We give Nvidia a slight lead at the top of the performance ladder, but that's not the only category to consider.

Looking at the mainstream market ($400, give or take), things get a bit messy. AMD's Radeon RX 6700 XT takes on the GeForce RTX 3060 Ti, with slightly better performance — provided once again that we ignore RT and DLSS. In our review, we called it a net tie. However, while AMD's card theoretically costs 20% more than Nvidia's offering, in practice pricing actually favors AMD right now ($480 vs. $500 at the time of writing).

Older model GPUs are mostly outclassed by the new arrivals, so the best pairing would be pitting the RTX 3050 against the RX 6600, both of which can be had for around $300 (never mind MSRPs). AMD's GPU crushes the 3050 in standard gaming performance by 25–35%, and while ray tracing does favor the Nvidia GPUs by 7–15%, that's far less critical for this category.

What about budget offerings, like stuff for under $200? Sadly, we have to wonder where all the good budget GPUs have gone. The RX 6500 XT and RX 6400 sell for under $200, but performance is generally worse than the old RX 5500 XT 8GB and GTX 1660, instead going up against the GTX 1650 and 1650 Super. AMD's cards are easy enough to find brand new, while Nvidia's GTX 16-series parts are now coming up on three years old and supply and availability can be a bit spotty. Still, Newegg has GTX 1650 Super for $200, effectively making the budget sector a tie.

Winner: Tie This is simply too close to call, as there are so many ways to split things. Nvidia wins for 4K and ray tracing performance, AMD wins for standard 1080p and 1440p gaming, and also in performance at similar high-end and mid-range price points. DLSS also counts in Nvidia's favor, however, and while FSR 2.0 might be relatively competitive, it works on any GPU.

AMD vs Nvidia: Power Consumption and Efficiency 

Prior to AMD's Navi, GPU power efficiency was decidedly in favor of Nvidia. But Navi changed all that, and Big Navi has further improved AMD's efficiency. Using chips built with TSMC's 7nm FinFET process and a new architecture that delivered 50% better performance per watt, Navi started to close the gap. Except, it was so far behind that even a 50% improvement didn't fully address the efficiency deficiency.

But Nvidia's Ampere architecture pushed higher clocks at the cost of efficiency, while AMD's Big Navi gets a healthy boost in efficiency from the Infinity Cache. The net result is that Ampere and Big Navi are pretty close to tied.

Using Powenetics hardware to capture the real graphics card power use of GPUs, we've tested all of the current and recent graphics cards from both companies. We've also tested third party cards from both sides, but we'll confine the charts to the reference designs as much as possible.

While power use favored Nvidia's older GPUs, sometimes by a wide margin, the differences on the latest generation hardware go the other way. RTX 3090 Ti uses the most power, followed by the RX 6950 XT, RTX 3080 12GB (custom card), and then we get the RTX 3090, 3080 Ti, and 3080. AMD's RX 6900 XT and 6800 XT come next, before we start getting to previous generation GPUs.

It's more difficult to declare a winner outside of the extreme performance range. AMD's RX 6700 XT uses a bit more power than the RTX 3060 Ti and a bit less than the RTX 3070, but they're all in a 10W range. Drop down to the RTX 3060 and RTX 3050 against the RX 6600 XT and RX 6600, and power use tracks pretty closely with performance.

Among budget GPUs, the RX 6500 XT uses more power than the GTX 1650, but the RX 6400 is the only truly modern GPU that doesn't need at least a PCIe 6-pin power connector.

Winner: AMD Focusing just on the current generation AMD Big Navi and Nvidia Ampere GPUs, power and efficiency are relatively close. AMD takes a slight lead at the top, the middle's a tie, and AMD wins in the budget sector as well, giving it the overall nod. TSMC's N7 process also factors in, helping out AMD, while Nvidia's use of Samsung 8N likely accounts for reduced overall efficiency.

AMD vs Nvidia: Featured Technology 

Most of the features supported by AMD and Nvidia seem similar, though the implementations do vary. Both support ray tracing now, which allows for some nice effects, but it's not required to get a good gaming experience. Nvidia's DLSS is a bigger factor, as FidelityFX Super Resolution (FSR) doesn't look as good in the FSR 1.0 implementation, while FSR 2.0 isn't widely adopted yet — and in either case, FSR works on AMD and Nvidia GPUs, and even Intel integrated graphics. That's actually a point to AMD for not locking people into its hardware, but practically speaking there are a lot of games with DLSS support and it can be an nice extra.

There are other aspects as well. G-Sync takes on FreeSync, Radeon Anti-Lag goes up against Nvidia's ultra-low latency mode plus Reflex, Radeon Super Resolution (RSR) works in a similar way to Nvidia Image Scaling (NIS), and there other areas where features effectively match up as well.

Supporting the same APIs and similar hardware features doesn't make things equivalent, however. Ampere and RDNA2 also support mesh shaders and variable rate shading (VRS), as well as some other features that are all part of the DirectX 12 Ultimate spec. But Nvidia's performance in ray tracing tends to be quite a bit higher than AMD, even without DLSS.

While FreeSync and G-Sync might seem equivalent on the surface, the best G-Sync displays are almost invariably higher quality and better latency than FreeSync displays. The same goes for AMD's anti-lag and Nvidia's ultra-low latency and Reflex: Similar in theory, but in practice Reflex implementations come out on top.

Video encoding and decoding are another important aspect, and here Nvidia definitely comes out ahead. The Turing and Ampere codecs support higher-quality encodes and lower GPU utilization, both good things. There's no need for CPU-based video encoding with Nvidia's latest GPUs. AMD's budget Navi 24 chips lack some key video encoding features as well.

There is one area where AMD has a clear advantage, though it's also perhaps to AMD's detriment. TSMC's N7 process that AMD uses for RDNA2 (and RDNA and Zen 3 and the PS5/XSX) chips clearly delivers better performance and power characteristics than Samsung's custom 8N (really just an improved version of Samsung's 10LPP process). The catch being that lots of other companies also want to partake of TSMC's goodness — AMD, Apple, Nvidia GA100, Qualcomm, and even Intel all use TSMC, along with various other smaller players. This becomes a problem when TSMC doesn't have enough capacity to meet the demands of all of those companies.

Winner: Nvidia While AMD and Nvidia have superficial parity on most features, Nvidia's implementations are generally superior — and cost more. G-Sync, Reflex, DLSS, and NVENC all end up being at least slightly better than AMD's alternatives.

AMD vs Nvidia: Drivers and Software 

Trying to determine a clear winner in the drivers and software category is difficult. Quite a few people previously encountered black screen issues with AMD drivers on RX 5000 Navi series GPUs, while others didn't have any difficulties. Newer drivers have fixed these problems, as far as we can tell. Nvidia drivers aren't foolproof either, and depending on the game and hardware, issues crop up for both companies. But is one company doing better with drivers? 

AMD makes a lot of noise about its yearly driver overhaul. The Radeon Adrenalin 2020 drivers consolidated everything under one large umbrella, aiming to simplify things, though it can be confusing at first if you're used to the older drivers. AMD tends to skip WHQL (Windows Hardware Quality Labs) testing, which means fewer hoops to jump through and potentially more bugs slip through, but Microsoft's insurance of a minimum level of functionality doesn't really mean much for gaming purposes.

You can generally count on at least one new AMD driver per month, often more if there are major game launches. Nvidia's driver schedule follows a similar cadence. You'll get new drivers for major game launches or new graphics card hardware. Nvidia's releases (outside of rare hotfixes) are all WHQL certified, and Nvidia also has a separate Studio Driver branch for content creators.

One of the big differences between AMD and Nvidia drivers is that Nvidia has two separate user interfaces. The Nvidia Control Panel handles things like resolutions and certain graphics settings, while GeForce Experience tackles game optimizations, driver updates, and extra features including ShadowPlay, Ansel, NIS, and more. Annoyingly, you have to log in and solve a captcha prompt to use GeForce Experience, which is something I've done more times than I’d ever want to count. Just say no to data mining plus drivers.

Winner: Tie We prefer AMD's unified driver approach, as it's one less interface to navigate, but there's just so much stuff in the current releases. Nvidia's Q&A is arguably better, though plenty of bugs and issues end up slipping through on both sides. Quantifying drivers ends up being an incredibly subjective affair, however, so we're calling this one a draw as well.

AMD vs Nvidia: Pricing and Availability

Who offers the better value in the battle of AMD vs Nvidia? The past two years have been a bit of a joke (not a funny one, either), but things are now greatly improved. You can find all the latest graphics cards in stock at retail now, with many models selling at or below MSRP. But of the "many" selling at or below MSRP, far more are using AMD GPUs than Nvidia GPUs, with only the extremely priced RTX 3080 Ti and above selling below MSRP from Team Green.

Our GPU pricing index looks at eBay pricing as an alternative, but it's no longer required. In general, the simple fact is that the best values are currently from AMD, with the RX 6600, RX 6600 XT, RX 6650 XT, RX 6700 XT, and RX 6750 XT all ranking near the top of the FPS per dollar charts. Nvidia's RTX 3060, 3050, and 3060 Ti aren't horribly option, but you're paying about 15–25% more in terms of FPS per dollar (and getting DLSS for that money).

At the top of the pricing spectrum, the RTX 3090 Ti is the unquestioned worst value, priced at over $1,800 and only delivering slightly more performance than the RTX 3080 Ti. AMD's RX 6950 XT doesn't cost nearly as much and competes well against the 3080 Ti, but as we go down the pricing scale things begin to favor AMD a lot more.

Right now, the RX 6600 takes top honors with around 0.23 fps per dollar spent. Nvidia's highest ranking GPUs come from its previous generation Turing RTX 20-series, where the RTX 2060 scores 0.196 FPS/$, but the highest RTX 30-series part only rates 0.176 FPS/$. AMD's RX 6500 XT is right in the mix for a budget card, also at 0.176 FPS/$.

Winner: AMD With the supply of graphics cards greatly improving, at least partly thanks to cryptocurrency mining profitability being in the dumps, the value proposition finally becomes meaningful again for the first time in about two years. GPU prices continue to drop, but for now AMD's RX 6000-series cards represent a better value than Nvidia's RTX 30-series parts.

AMD vs Nvidia: Bottom Line 

With an overall score of four to three, AMD squeaks out a victory and lays claim to the king of the GPU world crown. Cue the band and light the fireworks. That doesn't mean AMD GPUs are a better choice in every case, and there's a lot of fuzzy math and subjectivity involved, but you should be well served by Team Red's RDNA 2 GPUs — and just about equally well served by Team Green.

Overall, which GPU you prefer will likely come down to personal preference rather than hard numbers. AMD clearly wins most match ups (comparing similar priced cards) in standard benchmarks, but it falls behind in ray tracing games and DLSS still factors in. We could certainly see people being willing to pay 10–15% more money to get an Nvidia card, even if it may not technically be the "best" choice.

At this point, we're now looking forward to the future RDNA 3 and Ada Lovelace graphics cards, both of which we expect to see before the end of the year. There are still too many unknowns to even venture a guess at who will be on top by the end of the year, but hopefully the end of 2022 ends up being far better for gamers looking to upgrade their GPU than 2020 and 2021 were.

Even as quantum computing develops at an increasingly fast pace, the technology is still far from achieving mainstream distribution. There are several reasons for that - physics and engineering complexity, cost, and the relatively nascent implementations being some of them. There are computing environments that have carried the torch for the complexity of the so-called classical systems: High-Performance Computing (HPC), the domain of the datacenters and supercomputers of the world. There too, it seems, lies the first frontier for quantum.

Pawsey's Supercomputing Research Centre in Australia has claimed the world's first installation of a Quantum Computing Processor (QPU) in an HPC-first environment. Based on Quantum Brilliance's diamond-based qubits, the partnership has been strategized to supercharge the pairing of quantum and classical systems through a hybrid research environment. The integration was facilitated by the fact that Quantum Brilliance's QPU can operate at room temperature - something that other qubit types, such as IBM's own superconducting transmon qubits, can't.

In Munich, Germany, the Leibniz Supercomputing Centre already has a quantum computing hub that's focused on creating the algorithms and tools that can bridge the quantum and classical realms via its Future Computing initiative. The hub is currently integrating one of AI accelerator's darlings, Cerebras' Wafer Scale Engine (CS-2). Further up in the globe, the UK government has recently also dipped its institutional toes in the world of quantum, acquiring a photonics-based quantum computing system from Orca Computing.

Another AI-forward chip designer, Ampere, has also entered into an HPC-integration partnership with Rigetti, which produces superconducting-qubit-based QPUs.

The hyper-sensitiveness of quantum computers to their surroundings has also meant that most quantum processing offerings available today are only accessible through a cloud-enabled environment. This allows quantum systems to be physically located on their designers' special-purpose installations while allowing for remote access. QPUs such as Xanadu's record-breaking Borealis are made available through the company's cloud environment. The same process holds true with IBM's Quiskit, and Nvidia's software-based quantum simulation cuQuantum platform. These stand as examples of cloud-accessible quantum computing simulators available today for researchers worldwide - with the only requirement being an active internet connection.

Amazon, which offers its own cloud-based supercomputing services, has also extended its offering towards the quantum computing realm by partnering with a number of quantum-forward companies. For example, Amazon Braket offers customers cloud access to various quantum topologies: quantum annealing systems from D-Wave, ion-trap quantum processors from IonQ, and superconducting qubit systems from Rigetti and, again, IonQ.

Phillipe Notton, CEO of SiPearl, envisions the future of QPUs as co-processors to the CPU and GPU accelerators of classical computing. The France-based company stands as one of the leading chipmakers for European exascale systems and is currently developing its Arm-based Rhea CPUs for integration as early as 2023. According to Notton, classical systems will be an indispensable part of quantum, serving as mediators for quantum accelerators.

It'll take long development times until mainstream quantum computing solutions are made available - and some might never be - in an off-the-shelf manner. Until then, HPC centers' secure, leading-edge infrastructure, cooling, and power delivery designs stand as essential elements towards enabling and democratizing access to quantum computing.

The organizers have shared the schedule for the Hot Chip Symposium 2022. Intel has booked a lot of presentation time with experts sharing information and insight about its latest GPUs, CPUs, foundry technologies, etc. Other key PC technology firms at Hot Chips 34 include AMD, Arm, and Nvidia. Well-known tech industry pioneers like Samsung, Tesla, MediaTek, and Cerebras will be there. Due to the ongoing pandemic situation, Hot Chips 34 will be a virtual conference that will take place live over the days specified. Still, all presentations will be recorded and made available after processing.

Intel's Hot Chips 34 Schedule

• Intel’s Ponte Vecchio GPU: Architecture, System and Software. Monday, August 22, 9 – 11am
• Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications. Monday, August 22, 11.30am – 1.30pm
• Semiconductors Run the World. Monday, August 22, 2.30 – 3.30pm
• Meteorlake and Arrowlake : Intel Next Gen 3D Client Architecture Platform with Foveros. Tuesday, August 23, 5 – 7pm
• Next-Generation Intel processor build for the edge - Intel Xeon D 2700 & 1700. Tuesday, August 23, 5 – 7pm

Our readers' most interesting Intel presentation will concern Meteor Lake and Arrow Lake technologies on Tuesday. Intel's Wilfred Gomes will host this presentation.

Meteor Lake first successfully booted up in Windows, Chrome, and Linux last month, and it is due to begin shipping to customers in 2023 as 14th Gen Core processors. It looks like Meteor Lake will be a mobile-first architecture, and the presentation will take place in a segment of Hot Chips devoted to mobile and edge processors. Meteor Lake chips will scale from 5W on the mobile side up to 125W for desktops.

To remind readers of the importance of Meteor Lake for Intel, it will be a platform that debuts several essential technologies. Meteor Lake utilizes the Intel 4 process node. We already know it will feature a flexible tiled architecture with chiplets and hybrid cores and a next gen integrated GPU and AI acceleration (a trend set by Arm mobile processors).

The Hot Chips 34 presentation descriptions confirm that Meteor Lake will feature a "Next Gen 3D Client Architecture Platform with Foveros," or a new generation 3D Foveros implementation, with doubled connection density compared to the previous gen. As far as we know, right now, Arrow Lake, or the 15th Gen Core processors, will carry through most of the features of Meteor Lake with a die shrink to Intel 18A. Meteor Lake and Arrow Lake might share a common platform like we have seen confirmed that Alder Lake and Raptor Lake do.

AMD, Nvidia, and Tesla

AMD will also have multiple presentations at Hot Chips. It will discuss its latest Instinct GPU accelerators for HPC on Monday. On Tuesday, it has a presentation about an SoC targeting networking hardware. Lastly, and probably the most interesting to us, will be a late Tuesday presentation about AMD Ryzen 6000 series processors (mobile). We saw this Ryzen APU family first unwrapped at CES, and they have only recently started to feature in laptop designs that are shipping. Since this presentation is part of the mobile segment, it could be that there are some more ULV models on the way. The current H-series are 35 to 45W+, and the U-series are 15-28W. Could we see some sub-15W APUs between now and the end of August?

If we had to pick a highlight from Nvidia's upcoming Hot Chips presentations, we would probably jump with both feet onto the Nvidia Grace CPU talk. We reported the 144-core Nvidia Grace CPU in quite some depth last month. However, Nvidia has promised more architectural insight later, and the Hot Chips 34 presentation looks like the right place at the right time.

The Tesla Dojo features two separate presentations at Hot Chips 34. Tesla decided to split the presentations regarding this exascale computer into an architectural segment, and a super compute scaling ML training segment, led by respective experts from the company. In our most recent report on the Tesla Dojo, we talked about this 7nm and 50 billion transistor chip's custom ASIC-for-AI design and performance potential. We are looking forward to an official update on the hardware, how it will be implemented, and more.

French research institutions CEA and C12 Quantum Electronics have announced a novel quantum computer design. One that can only describe as a waferscale engine... for quantum. In an approach to CMOS manufacturing techniques and backed by the CEA's $5 billion annual funding, the companies aim to manufacture carbon nanotube-based qubits at scale - a 200 mm (7.9 inches) wafer at a time. As a result, transistor density now sees itself as a parallel to quantum density.

There have been some other quantum computing designs that aim to approximate themselves with transistor manufacturing in one way or another. The idea is that the more compatible qubit manufacturing is to that of existing silicon-aimed processes (such as those of TSMC's 4N or Intel 7), the more efficiently manufactured - and scaled - they can be.

But none of the presented designs were for an entire 200 mm wafer scale. It's telling that in the $599.9 billion-dollar-worth semiconductor market, only Cerebras has deemed to build a waferscale chip. The difficulties in such a design are tremendous, yet C12 expects to have a working, final waferscale prototype by the end of the decade.

"Quantum technology offers great promise for the next computing generation but still faces significant developmental challenges for fabricating qubit chips," said Sébastien Dauvé, CEO of the CEA-Leti lab. "Combining well-established CMOS technologies with C12's original approach using carbon nanotubes could accelerate progress toward commercializing quantum computing and manufacturing those chips at scale."

C12 is confident: its technologies allow for ease of fabrication (relative to the more exotic approaches to quantum computing) that approaches that of a semiconductor device and would allow for a "scalable and ultra-coherent platform for quantum computing." Pierre Desjardins, CEO and co-founder of C12, said the ultimate aim is to "transfer an academic fab process to an industrial-grade semiconductor fab process."

The company says it can manufacture thousands of qubits per hour - and ultimately achieve densities in the order of the "hundreds of thousands" of qubits per wafer-sized quantum computing chip. The company's initial design goal was to focus on delivering a million-qubit quantum computer. Perhaps it ultimately doesn't need to be delivered within a single wafer.

C12's qubit design starts with the growth of ultrapure carbon nanotubes, which the company does within its facilities to guarantee their purity level. Then, via chemical vapor deposition, C12 isotopes of carbon are meticulously placed - atom by atom - to form the nanotube structure.

It is inescapable because the presence of any other isotope (or atomic particle) in the nanotubes would lead them to interact. That would, in turn, increase the dreaded "spin noise" - one of the primary sources of disturbances within quantum machinery that can lead qubits to collapse entirely, originating errors in calculations or interrupting workloads. So before they used nanotubes anywhere, they screened them for impurities non-invasive. Only those with a 99% purity (meaning they contain 99% C12 carbon isotopes) make it to the next step.

The carbon tubes are then meticulously placed on IC chips produced in massive scales already by the semiconductor manufacturing industry. The carbon nanotubes lay suspended above an array of gate electrodes, ensuring optimized environmental isolation for "drastically reducing decoherence due to charge and mechanical noise." A novel, microwave-based regulator, allows for the system's qubits to be coupled at will between one another. It simultaneously improves performance while reducing the environmental interference of changes to qubits' states.

Considering the already copious inspiration from the semiconductor industry, the thought that two of these wafer-scale computing chips could then scale through a networking solution (perhaps photonic based) sounds like the subsequent path of least resistance.

We must remember that the announcement comes before a working prototype - but after the actual hardware test runs already. Today, IBM's Eagle quantum computer counts 127 qubits, and IBM has previously said it would reach a million-qubit density by 2030. With CEA and C12's million-qubit prototype, there's another real contender for a pole position in that particular pursuit. But many metrics are responsible for a quantum computer system's performance, and other companies (such as incomparably wealthy Microsoft) are definitely in the race. 

On the surface, it would appear that it's happened: the largest and most complex semiconductor chip known to man has been turned to Bitcoin mining — all 850,000 cores of it. At least, that's the impression that the marketing department at NuMiner must've intended to give when they created their NuMiner NM440 press releases. The result? An impressive piece of mean, green machinery that claims a competitor-demolishing 440 TH/s in Bitcoin mining.

The only problem is that the new device is clearly Cerebras' CS-2 system with NuMiner's branding photoshopped on. However, the implication that NuMiner is using Cerebras' chips to power the company's NM440 Application Specific Integrated Circuit (ASIC) is clear: The largest and most complex semiconductor chip ever produced — 850,000 cores of human ingenuity — supposedly used for cryptocurrency mining.

But that actually isn't the case. 

We reached out to Cerebras, and the company tells us that it doesn't have any connection to NuMiner or its NM440 systems. Cerebras also made clear that NuMiner's use of the CS-2 design (it even had Cerebras' logo still on the bottom of the image) was not approved. The company also has no affiliation with NuMiner. Cerebras provided us with the following statement:

 "We are aware of a startup crypto mining company using a misappropriated, altered image of the Cerebras CS-2 product for their own business purposes. This image improperly passes off our CS-2 as their own product, as you can see by the Cerebras logo still visible at the bottom of the image. We are not working, or otherwise affiliated, with this company. We are taking steps to address the situation." - Cerebras spokesperson. 

Interestingly, it appears that NuMiner does have actual new mining equipment available: The company's initial announcement was accompanied by another press release - one that mentioned the purchase of 60,000 of the company's record-breaking NM440 ASICs. This purchase announcement was made by Sphere 3D, a publicly listed company, at the cost of $1.7 billion. Sphere 3D's Twitter had been silent since 2019, but rose again just for the announcement - and its stocks simultaneously jumped 30%.

So why would NuMiner misappropriate Cerebras' image? Perhaps it wanted to tickle a hornet's nest; perhaps it searched for "biggest computer chip" on a search engine and ended up at Cerebras' renders and thought "it needs some Mountain Dew spirit on it" and decided to call it a day. Or perhaps it was a play for the credibility that working with Cerebras would give their new, supposedly outrageously efficient ASIC? 

Perhaps so, as the NuMiner purportedly beats the competition by significant margins. At 20.2 J/T, it's also marketed as much more efficient than offerings from the current ASIC market maker, AntMiner, whose top-of-the-line "S19 Pro+ Hyd" miner only manages to deliver 198 TH/s. The supposed new product from NuMiner is more than twice the speed of one of the cryptocurrency ASIC manufacturers' leading players, all while purportedly allowing for 4.5 times greater returns due to their higher energy efficiency.

Not bad for a company whose online domain was only registered in March of last year.

Given Cerebras' statement, it's clear that the company's systems aren't being turned to cryptocurrency mining. We'll keep an eye out to see if NuMiner releases pictures of its actual products. 

Cerebras Systems today announced that it has created what it bills as the first brain-scale AI solution – a single system that can support 120-trillion parameter AI models, beating out the 100 trillion synapses present in the human brain. In contrast, clusters of GPUs, the most commonly-used device for AI workloads, typically top out at 1 trillion parameters. Cerebras can accomplish this industry-first with a single 850,000-core system, but it can also spread workloads over up to 192 CS-2 systems with 162 million AI-optimized cores to unlock even more performance. 

As the fastest AI processor known to humankind, the Cerebras CS-2 is undoubtedly one of the most unique semiconductor devices on the planet. With 46,225 mm2 of silicon, 2.6 trillion transistors, and 850,000 AI-optimized cores all packed on a single wafer-sized 7nm processor, its compute capability is truly in a league of its own. 

However, each massive chip comes embedded in a single CS-2 system, and even though it has plenty of memory, that can limit the size of AI models. The chip has 40 GB of on-chip SRAM memory, but adding a new external cabinet with additional memory allowed the company to run larger brain-scale AI models. 

Scalability is also a challenge. With 20 petabytes of memory bandwidth and 220 petabits of aggregate fabric bandwidth, communication between multiple chips is challenging using traditional techniques that share the full workload between processors. The system's extreme computational horsepower also makes scaling performance across multiple systems especially challenging — especially in light of the chip's 15kW of power consumption. That requires custom cooling and power delivery, making it nearly impossible to cram more wafer-sized chips into a single system.

Cerebras' multi-node solution takes a different approach: It stores model parameters off-chip in a MemoryX cabinet while it keeps the model on-chip. This not only allows a single system to compute larger AI models than ever possible before, but it also combats the typical latency and memory bandwidth issues that often restrict scalability with groups of 'smaller' processors, like GPUs. In addition, Cerebras says this technique allows the system to scale performance near-linearly across up to 192 CS-2 systems. 

The company uses its SwarmX Fabric to scale workloads across nodes. This interconnect consists of the company's AI-optimized communication fabric that has Ethernet at the PHY level but runs a customized protocol to transfer compressed and reduced data across the fabric. Each SwarmX switch supports up to 32 Cerebras CS-2 systems and serves up nearly a terabit of bandwidth per node. 

The switches connect the systems to the MemoryX box, which comes with anywhere from 4TB to 2.4PB of memory capacity. The memory comes as a mix of flash and DRAM, but the company hasn't shared the flash-to-DRAM ratio. This single box can store up to 120 trillion weights and also has a 'few' x86 processors to run the software and data plane for the system.  

Naturally, there are only a few hundred customers in the world that could use such systems, but Cerebras aims to simplify running AI models that easily eclipse the size of any existing model. Many of those customers probably include military and intelligence communities that could use these systems for any multitude of purposes, including nuclear modeling, but Cerebras can't divulge several of its customers (for obvious reasons). We do know that the company collaborates with the Argonne National Laboratory, which commented on the new systems:

“The last several years have shown us that, for NLP models, insights scale directly with parameters– the more parameters, the better the results,” says Rick Stevens, Associate Director, Argonne National Laboratory. “Cerebras’ inventions, which will provide a 100x increase in parameter capacity, may have the potential to transform the industry. For the first time we will be able to explore brain-sized models, opening up vast new avenues of research and insight.”          

The journey of Moore's Law is a technologically complex and expensive one, worth billions of dollars in research and development - just ask semiconductor manufacturers. The much-referred-to "soft" law coined by Intel co-founder Gordon Moore stated that the number of transistors in a densely-packed semiconductor should double every two years. The death of Moore's Law has been hailed time and time again, and is now understood as more of a target rather than a rule - yet it's a necessary goalpost for silicon designers to compare against. The ever-increasing transistor densities have posed many challenges for system designers, however - there are always limitations imposed by physics and the current level of technology that define a hard limit to how many transistors can be pushed into a single chip. And as transistor density and chip sizes increase, the impact of manufacturing defects (which may render parts of the chips inoperative) also has to be taken into account.

Decades of semiconductor design favored monolithic single chips until AMD showed the power of chiplets with its Zen architecture - essentially, AMD pioneered the mainstream use of smaller semiconductor "blocks" (in Zen, represented by the CCX, or Core Complex) that are then glued (as per Intel's own words) together into the final chip, interconnected by AMD's own Infinity Fabric (responsible for carrying information from one chiplet to another). This circumvents some limitations on currently available semiconductor manufacturing processes, since smaller chips are less likely to feature manufacturing defects, and allows chip designers to better spread out computing resources to achieve a better balance between transistor density and the heat generated by these closely packed-together components. Even as chiplets are gaining traction in the industry and are likely to become the new de-facto standard for performance scaling (Nvidia and Intel have also been exploring chiplets and MCM [Multi-Chip Modules] for future products), there are still some players looking into new ways of increasing chip performance density, such as Cerebras, with the 2.3 trillion transistors, 850,000 cores and 15 kW power requirement of its Wafer Scale Engine 2.

The Wafer Scale Engine is the world's largest chip, as you might have guessed from those eye-watering statistics, putting some supercomputers to shame by itself. The decision to go wafer-scale aimed to solve one of the problems arising from the deployment of larger and larger amounts of individual chips working in tandem - they have to communicate between each other, to know where information is, at what processing state the data is, and to transmit it towards the next processing step. Keeping everything in a single chip means that the distance between different ICs is shortened, and enabled Cerebras to develop their own interconnect technology (akin to AMD's Infinity Fabric) which enables transmission of data at up to 220 Petabits/S. However, Cerebras' Wafer Scale Engine is still a monolithic chip at heart, meaning that it still faces the same constraints as they do - particularly, a higher surface area for manufacturing defects to occur. While the company has built-in additional resources into the chips' design that aim to alleviate those issues - namely, additional cores and IC components that can substitute for those that have been disabled due to manufacturing defects - this still has to be considered when it comes to the future of computing. However, lessons learned from Cerebras' design are very likely to be carried over to future wafer-sized computing solutions.

One such solution presents a perfect theoretical marriage between both wafer-scale designs and the more cost-effective chiplet approach - a chiplet-based, wafer-scale chip. The idea is simple: take the basis of Cerebras' innovation - a wafer-sized substrate that enables an interconnect fabric between all components - and instead of carving a monolithic chip from that, you "simply" add chiplet-based blocks on top of the interconnect. I say simply, because the work of bonding a number of ICs on a substrate is much more complex than it sounds. Even so, this would allow a prospective chip designer to leverage and combine multiple, perhaps even disparate silicon blocks into the wafer-sized chip, thus improving yields and overall chip cost. Imagine an AMD-made wafer-scale engine that combined multiple Zen 3 CCX's as well as graphics chips, Xilinx-based FPGAs, Arm cores, and whatever else comes to your mind - just deployed on a wafer-sized substrate.

This actually coincides with the thought-process taken the first time a wafer-scale chip was discussed among the scientific community, authored by Saptadeep Pal and colleagues; the design of a wafer-scale chip based on heterogeneous computing philosophies. And even as powerful as Cerebras' Wafer Scale Engine is, it is already going up against the neverending pit of compute power requirements around the globe. Rakesh Kumar, a University of Illinois collaborator on the waferscale effort with Pal, described the entire heterogeneous wafer-scale design as such: ”A chiplet-based approach allows heterogeneous integration of technologies on the wafer. This means that a chiplet-based waferscale processor can have high density memories such as DRAMs, flash, etc., reside on the same processor. This can allow much better memory capacity characteristics than the Cerebras approach that cannot support heterogeneous technologies on the processor, limiting the processor’s memory capacity.  This is going to be critical for many applications (including many ML models) whose application requirements far exceed what is provided by the Cerebras processor."

The best part? Such a design can already be achieved with today's technology. It seems like it's only a matter of time before Moore's Law is proven yet again.

Cerebras, the company behind the Wafer Scale Engine (WSE), the world's largest single processor, shared more details about its latest WSE-2 today at the Linley Spring Processor Conference. The new WSE-2 is a 7nm update to the original Cerebras chip and is designed to tackle AI workloads with 850,000 cores at its disposal. Cerebras claims that this chip, which comes in an incredibly small 26-inch tall unit, replaces clusters of hundreds or even thousands of GPUs spread across dozens of server racks that use hundreds of kilowatts of power.

The new WSE-2 now wields 850,000 AI-optimized cores spread out over 46,225 mm2 of silicon packed with 2.6 trillion transistors. Cerebras also revealed today that the second-gen chip has 40 GB of on-chip SRAM memory, 20 petabytes of memory bandwidth, and 220 petabits of aggregate fabric bandwidth. The company also revealed that the chip consumes the same 15kW of power as its predecessor but provides twice the performance, which is the benefit of moving to the denser 7nm node from the 16nm used with the previous-gen chip. 

Cerebras Wafer Scale Engine 2 WSE-2 Specifications

These almost unbelievable specifications stem from the fact that the company uses an entire TSMC 7nm wafer to construct one large chip, thus sidestepping the typical reticle limitations of modern chip manufacturing to create a wafer-sized processor. The company builds in redundant cores directly into the hardware, which then leaves room for disabling defective cores, to sidestep the impact of defects during the manufacturing process.

The company accomplishes this feat by stitching together the dies on the wafer with a communication fabric, thus allowing it to work as one large cohesive unit. This fabric provides 220 Petabits/S of throughput for the WSE2, which is slightly more than twice the 100 Petabits/S of the first-gen model. The wafer also includes 40GB of on-chip memory that provides up to 20 Petabytes/S of throughput, both of which are also more than twice that of the previous-gen WSE. 

Cerebras hasn't specified the WSE-2's clock speeds, but has told us in the past that the first-gen WSE doesn't run at a very "aggressive" clock (which the company defined as a range from 2.5GHz to 3GHz). We're now told that the WSE-2 runs at the same clock speeds as the first-gen model, but provides twice the performance within the same power envelope due to its increased system resources. We certainly don't see those types of generational performance improvements with CPUs, GPUs, or most accelerators. Cerebras says that it has made unspecified changes to the microarchitecture to extract more performance, too.

As you can see below, cores are distributed into tiles, with each tile having its own router, SRAM memory, FMAC datapath, and tensor control.  All cores are connected via a 2D mesh low-latency fabric. The company claims these optimizations result in a 2x improvement in wall clock training time with a BERT-style network training that was completed using the same code and compiler used with the first-gen wafer-scale chip. 

As before, the chip comes wrapped in a specialized 15U system that's designed specifically to accommodate the unique characteristics of the wafer-scale device. We're told that the changes to the first-gen CS-1 system, which you can read about in-depth here, are very minimal in the new CS-2 variant. Given that the most important metrics, like power consumption and the size of the WSE, have remained the same, it makes sense that most of the system is identical.

Cerebras hasn't specified pricing, but we expect the WSE-2 unit will continue to attract attention from the military and intelligence communities for any multitude of purposes, including nuclear modeling, but Cerebras can't divulge several of its customers (for obvious reasons). It's safe to assume they are the types with nearly unlimited budgets, so pricing isn't a concern. On the public-facing side, the Argonne National Laboratory is using the first systems for cancer research and basic science, like studying black holes.

Cerebras also notes that its compiler easily scaled to exploit twice the computational power, so the software ecosystem that is already in place is supported. As such, the WSE-2 unit can accept standard PyTorch and TensorFlow code that is easily modified with the company's software tools and APIs. The company also allows customers instruction-level access to the silicon, which stands in contrast to GPU vendors.

Cerebras has working systems already in service now, and general availability of the WSE-2 is slated for the third quarter of 2021. 

The original Cerebras Wafer Scale Engine (WSE) is a marvel in truly every sense, but the company has now upped the ante. The original WSE brought an unbelievable 400,000 cores, 1.2 trillion 16nm transistors, 46,225 square millimeters of silicon, and 18 GB of on-chip memory, all in one chip that is as large as an entire wafer. Add in that the chip sucks 15kW of power and features 9 PB/s of memory bandwidth, and you've got a recipe for what is unquestionably the world's fastest AI processor. As you can see in the image above, the chip is nearly as large as a laptop.

How do you top that? According to the Cerebras slide deck it shared at Hot Chips 2020, you transition to TSMC's 7nm process, which allows a mind-bending 850,000 cores powered by 2.6 trillion processors - all in a single chip that's the size of an entire wafer. The company says it already has the massive chips up an running in its labs.

The current Cerebras Wafer Scale Engine (WSE) sidesteps the reticle limitations of modern chip manufacturing, which limit the size of a single monolithic processor die, to create the wafer-sized processor. The company accomplishes this feat by stitching together the dies on the wafer with a communication fabric, thus allowing it to work as one large cohesive unit. 

The end result is 55.9 times larger than the world's largest GPU (the new Nvidia A100 measures 826mm2 with 54.2 billion transistors). Here's a rundown of the existing architecture, and another article covering the massive custom system used to run the processors in data centers. 

Here you can see images of the first-gen system that houses the chip, which has a robust power delivery and cooling apparatus to feed the power-hungry chip. Naturally, the second-gen Wafer Scale Engine will still occupy the same amount of die area (the company is constrained by the size of single wafer, after all), but more than doubling the transistor count and the number of cores. We expect the company will also increase the memory capacity and beef up the chip interconnects to improve on-chip bandwidth, but we'll learn more details when the company announces the final product. 

Cerebras Systems' announced its new CS-1 system here at Supercomputing 2019. The company unveiled its Wafer Scale Engine (WSE) at Hot Chips earlier this year, and the chip is almost as impressive as it is unbelievable: The world's largest chip, weighing in at an unbelievable 400,000 cores, 1.2 trillion transistors, 46,225 square millimeters of silicon, and 18 GB of on-chip memory, all in one chip that is as large as an entire wafer. Add in that the chip sucks 15kW of power and features 9 PB/s of memory bandwidth, and you've got a recipe for what is unquestionably the world's fastest AI processor.

Developing the chip was an incredibly complex task, but feeding all that compute enough power, not to mention enough cooling capacity, in a system reasonable enough for mass deployments is another matter entirely. Cerebras has pulled off that feat, and today the company unveiled the system and announced that the Argonne National Laboratory has already adopted it. The company also provided us detailed schematics of the internals of the system. 

The system measures a mere 15 Rack Units tall, or roughly 26", so three can fit in a single rack. Given the performance, that's an incredibly compact package: It would take a 1,000-GPU cluster, which consumes 15 entire racks and half a megawatt of power, to match the performance of one CS-1 system. That's because a single Cerebras chip has 78 times more cores, 3,000 times more memory, and 10,000 times more memory bandwidth than a single GPU. It also has 33,000 times more bandwidth (PB/s). 

A pod of Google's TPU v3 chips consumes 100kW of power, but only provides 1/3 the performance of a single CS-1 system. Overall, the CS-1 draws 1/5th the power and is 1/30th the size, yet is three times faster than an entire TPU pod. 

In contrast, the Cerebras CS-1 consumes 20kW, with 4kW of power dedicated to the cooling subsystem, like fans, pumps, and the heat exchanger. The system delivers 15kW of power to the chip, and the remaining 1kW is lost to power supply inefficiencies. 

Twelve 100GbE connections line the upper left corner of the system. These systems will work in tandem with larger supercomputers that execute traditional forms of compute. Data processed by a supercomputer will then flow into the CS-1 for additional AI processing, leveraging the strengths of the both types of compute for differing workloads. The system also scales out to numerous nodes via the networking fabric, meaning the CS-1 systems can work in larger groups. Cerebras has tested 'very large' clusters, which can then be managed as a single homogeneous system in model parallel of data parallel modes, but hasn't released official scalability metrics. 

The entire Cerebras CS-1 consists of custom-built components. The system takes in power from the rear with twelve power connections. It then steps 54V down to 0.8V before delivering it to the chip. The power flows through the motherboard, as opposed to around it, and then into the processor, with separate regions of an unspecified number of cores each receiving their own supply of power. The wafer-scale chip consists of many die tied together with an on-die networking fabric, but we're told that the power delivery is more granular than a die/reticle flash. That ensures consistent delivery of power across the wafer, and also minimizes on-chip power distribution planes. 

The "engine block" sits up front. This is a sandwiched design that has the power subsystem, motherboard, chip, and cold plate mounted as one assembly (left). The cold plate receives water from a manifold to the right, which then delivers cooled water to several individual zones on the surface of the cooling plate. The heated water is then extracted, again from the small zones that ensure consistent thermal dissipation, and pumped down to the heat exchanger at the bottom of the unit. The exchanger consists of an EMI grill and is cooled by powerful fans that employ air straighteners. Overall, the chip runs at half the junction temperature of a standard GPU, which increases reliability. 

All of the individual units, like the 6+6 power supplies, heat pumps, fans, and heat exchanger, are redundant and hot-swappable to minimize downtime and failures. 

The chip is fabbed on TSMC's 16nm process, which the company chose due to its maturity and the scheduling of its product release. Cerebras hasn't specified the clock speeds, but tells us the chip doesn't run at a very "aggressive" clock (which the company defined as a range from 2.5GHz to 3GHz). The company will provide specifics in the near future. 

Cerebras hasn't specified pricing for the unit, though we're told it is "several million." We expect that this unit will attract attention from the military and intelligence communities for any multitude of purposes, including nuclear modeling, but Cerebras can't divulge several of its customers (for obvious reasons). It's safe to assume they are the types with nearly unlimited budgets, so pricing isn't a concern. 

On the public-facing side, the Argonne National Laboratory is using the first systems for cancer research and basic science, like studying black holes. Cerebras has a software ecosystem already in place, and the unit can accept standard PyTorch and TensorFlow code that is easily modified with the company's software tools and APIs. The company also allows customers instruction-level access to the silicon, which stands in contrast to GPU vendors. 

Cerebras Systems, makers of the world's largest single processor that weighs in with a whopping 1.2 trillion transistors and 400,000 AI cores, announced today that it has entered into a partnership with the Department of Energy (DOE), long the leader in the supercomputing space, to use its new wafer-scale chips for basic and applied science and medicine with super-scale AI.

The Cerebras Wafer Scale Engine (WSE) sidesteps the reticle limitations of modern chip manufacturing, which limit the size of a single monolithic processor die, to create the wafer-sized processor. The company accomplishes this feat by stitching together the dies on the wafer, thus allowing it to work as one large cohesive unit. 

That creates a massive processor that measures 42,225 square millimeters, the largest in the world, that packs 1.2 trillion transistors fabbed on TSMC's 16nm process. That's 56.7 times larger than the world's largest GPU (815mm² with 21.1 billion transistors). The massive chip also comes packing a whopping 40,000 AI-processing cores paired with 18GB of on-chip memory. That pushes out up to 9 PBps, yes, petabytes per second, of memory bandwidth. We recently had the chance to see the massive chip up close at the Hot Chips conference, and as you can see, it is larger than our laptop's footprint.

The Cerebras WSE's will find a home in the Argonne and Livermore National Laboratories, where they will be used in conjunction with existing supercomputers to speed AI-specific workloads.

The DOE's buy-in on the project is incredibly important for Cerebras, as it signifies that the chips are ready for actual use in production systems. Also, as we've seen time and again, trends in the supercomputing space often filter down to more mainstream usages, meaning further development could find Cerebras' WSE in more typical server implementations in the future.

The DOE also has a history of investing heavily in the critical software ecosystem needed for mass adoption, as we've seen with its investment in AMD's ROCM software suite for the exascale-class Frontier supercomputer, the work the agency is doing with Intel's OneAPI for the Aurora supercomputer, and the partnership with Cray for El Capitan.

AI models are exploding in size as models double every five months. That doesn't currently appear to be a problem with the WSE's 18GB of SRAM memory, but because SRAM can't be scaled retroactively, larger models could soon outstrip the chips' native memory capacity. Cerebras tells us that it can simply use multiple chips in tandem to tackle larger workloads because, unlike GPUs, which simply mirror the memory across units (data parallel) when used in pairs (think SLI), the WSE runs in model parallel mode, which means it can utilize twice the memory capacity when deployed in pairs, thus scaling linearly. The company also says that scaling will continue with each additional wafer-size chip employed for AI workloads.

We're told that today's announcement just covers the basics of the partnership, but that more details, specifically in regards to co-development, will be shared at the Supercomputer tradeshow in November.