In June, AMD overtook the predictive memory engine known as MEXT, which claims to offer upwards of 99% of the performance of a system with full DRAM capacity while running with as little as 25% of the physical DIMMs. The technology offloads cold memory pages to flash storage and uses an AI model to serve pages before they’re needed, and AMD says it plans to extend the tech across a wide swath of its IT infrastructure next year.

The pitch behind MEXT seems too good to be true. According to AMD and MEXT founder Gary Smerdon, the technology can cut the physical DRAM required in a server by 20% to 75% depending on the application and performance target. That missing memory still registers as installed DRAM to the OS. Instead of DRAM, however, MEXT uses relatively inexpensive flash storage to offload cold pages, flying them back in as they’re needed with an AI model. In some of AMD’s internal workloads, such as Synopsys PrimeTime, the company says it’s able to achieve 95% of the performance of a full server while running at 50% DRAM capacity with MEXT.

AMD has deployed MEXT internally on 145 servers, which it says will expand to 2,000 servers next year. In addition, the company has announced a partnership with HPE to bring MEXT to customers. Currently, we’re in phase 1 of the rollout, with some EPYC Venice servers carrying a “MEXT Ready” badge and a dedicated NVMe drive or bay for the offload. Phase 2 brings MEXT licenses out to these servers, as well as the RAM View application. AMD hasn’t said when Phase 2 will begin.

The AI-driven DRAM pricing surge impacts more than just gaming PCs, with enterprises also feeling the brunt of price increases, even if they aren’t running AI workloads. If MEXT is able to achieve what AMD claims, it could be transformative given the current market. Because of that, it’s worth understanding what exactly MEXT is, as well as what AMD claims it can do.

Although MEXT is exciting in concept, it’s obvious that AMD is taking a conservative approach to the rollout. Extraordinary claims require extraordinary evidence, after all. The applications of MEXT are currently narrow, though AMD says it’s expanding the workloads it’s using MEXT on with promising early results.

DRAM, Flash and an LLM

The basic setup of MEXT is simple in concept: cold pages go to flash, AI brings those pages back as needed, and it’s as if the memory was never missing in the first place. The main problem should be obvious. Flash is orders of magnitude slower than DRAM, so streaming pages back into memory from flash as they’re needed isn’t feasible. MEXT’s trick is using an AI model to predict the pages you’ll need. And, as long as the model is able to stay ahead by at least the transfer latency from the SSD, it’s as if the physical DRAM was installed the whole time.

This isn’t a crazy concept considering how a transformer-based LLM, which MEXT uses, operates. If you’re unfamiliar with the inner workings, this open-source visualization breaks down the concept of a transformer AI model cleanly. The foundational concept is next token prediction, which underpins the design of modern LLMs. Given a set of tokens, the LLM determines which token (word, portion of a word, etc.) is most likely to come next. It makes a prediction. In the case of MEXT, it’s predicting what page is needed next, not what word comes next.

Memory offloading to flash isn’t a new concept, but MEXT founder Gary Smerdon says that AI is the critical difference in this technology. MEXT itself is deployed as a Linux kernel module that works with any Linux distro. It uses an “ensemble of AI models,” with the primary transformer-based LLM driving the technology. And critically, it doesn’t come pre-trained.

Instead, AMD says that MEXT trains in under a second when first deployed, operates on one EPYC core without a GPU, and continually trains as the workload progresses. This approach makes sense given the varied workloads that MEXT may apply to. The idea is that it would learn the access patterns of the application in order to drive that prediction engine.

MEXT isn’t perfect, but it doesn’t need to be perfect in every situation. For instance, the order of stored pages isn’t important. With text, an LLM needs to predict the correct text in the correct order, but with MEXT, the order doesn’t matter. As long as the page is in DRAM when it’s needed, that’s fine.

In order to understand the application of MEXT to different workloads, AMD has developed RAM View to go alongside the tech. It’s a memory utilization tool that shows which pages are hot and which have gone cold. As you can see from the example above, a system with 1.5 TB of memory shows near-full utilization across the full workload, but around half of the pages stored in memory haven’t been touched in five minutes or more at any given time.

AMD provided this generalized example and didn’t clarify what workload it was testing. That’s very important, as the utilization breakdown will look vastly different depending on the application(s) running on the server. Initially, AMD is applying MEXT to critical EDA applications it uses internally, such as Synopsys PrimeTime, but the company says it has focused on optimizing agentic AI, database, and media and entertainment workloads as well.

This is important not only because memory access patterns change between applications, but also because performance in those applications reacts differently when a system doesn’t have enough memory. The “memory wall,” as AMD calls it, should be a familiar concept regardless of whether you’ve ever touched a server. With MEXT, AMD says it’s trying to extend this memory wall, which may look different for different applications.

For instance, the company is confident that many workloads can reduce capacity by around 20% to 25%. As the reduction increases, however, the applications become more specialized, and the performance delta becomes greater.

AMD’s internal MEXT results

AMD has shared some internal MEXT results, which look impressive, though as usual, it’s always smart to handle first-party benchmarks like this with skepticism. Starting with PrimeTime, where AMD has focused much of its attention on MEXT up to this point, it says servers running at 50% capacity retain 95% of the performance of a full server, and going down to as little as 25% capacity still maintains 80% of the application’s performance.

PrimeTime demands a lot of memory for large designs. There are some applications where performance is nearly identical, according to AMD. In a 3-node cluster running in Azure with 5th-gen EPYC CPUs, AMD says MEXT offers 99% of the performance of the full cluster while running at 50% DRAM capacity with the Spark SQL workload from the TPC-DS benchmark. SQL databases try to cache as much data as possible in memory to prevent I/O bottlenecks, creating a golden opportunity for tech like MEXT that wants to free cold pages.

Perhaps the most applicable workload at the current moment, however, is agentic AI, and AMD says MEXT has similar applications there. Across a five-agent concurrent geomean, AMD claims 99% of the performance of a full server with 50% memory capacity, and 85% of the performance with 25% capacity. With a “memory-hungry” agent, AMD claims 90% and 88% performance for 50% and 25% capacity, respectively.

The slide you can see above has footnote tags. However, AMD has not shared the footnotes with us yet, so we don’t have a view into how these tests were run. Naturally, we assume AMD has, at minimum, represented the performance of MEXT in the best light possible. We can’t do a full analysis without knowing how the tests were run, however.

What is interesting is AMD’s cautious approach to rolling out MEXT. It’s an EPYC-exclusive feature right now, though AMD left the door open for support on future products (consumer devices, such as Strix Halo) far down the road. It will be sold as a license, bundled with the RAM View software, but we don’t have a timeline on when that will happen. And, despite a partnership with HPE to push out “MEXT Ready” servers, we still don’t know when MEXT itself will be ready for deployment beyond AMD’s walls.

Given that conservative approach, there are likely pitfalls to MEXT that we’re not seeing yet, and it’s hard to imagine it will be broadly applicable to every server, at least at the 50% and 25% DRAM capacity levels that AMD showed off with its benchmarks.

However, even being able to trim 25% of a server’s DRAM capacity represents a massive cost savings in the current supply-constrained environment. If some workloads can push that to 50% capacity, that’s even better. Of course, we’ll need to see how MEXT holds up once it’s available broadly, but if AMD’s claims hold water, it could become a defining technology in data centers that can’t seem to get enough memory.

Newegg is one of the best places at the moment for deal bundles on otherwise expensive PC parts for a new gaming PC. With that in mind, you can pick up a brand-new AMD Ryzen 7 9950X3D with 32GB of DDR5 RAM and an Asus TUF Gaming X870E motherboard for $1,059.98.

● Check out this combo deal at Newegg

This deal saves you $128.99 compared to buying the parts separately. You're also getting a free Rosewill 360mm AIO liquid cooler thrown in for free, worth $89.99. More importantly, however, is the RAM. With this deal, you're bringing down the effective cost of the memory to just $351, or less if you count the free cooler.

Buying this RAM separately would cost you $479.99, while the cheapest 32GB DDR5 kit on sale anywhere right now is $438, so you're paying $87 less for RAM compared to what you'd have to pay elsewhere. That's a great deal considering how expensive RAM has become over the last year, especially if you need to build or upgrade your rig today.

The AMD Ryzen 7 9800X3D is no longer the fastest gaming CPU on the market, but it's still our favorite, with performance that's almost impossible to beat. It ships with eight cores, 16 threads, and a boost clock speed up to 5.2 GHz. The important stat, though, is 96MB of L3 cache. This is AMD's all-important 3D V-Cache technology in action. The extra cache provides a huge frame rate boost by giving the CPU more memory directly.

There's less need for it to drop down to slower system RAM while you're gaming, making frame rates higher and more stable. As the Bench charts below show, this is a CPU that, despite being marginally pipped to the post by newer CPUs like the 9850X3D, is still an absolute powerhouse for gamers.

Along with this world-class processor is a solid set of RAM for your rig. The V-Color Manta XSky RAM included here is a popular one among these Newegg bundles. You're getting two 16GB memory modules to run dual-channel, and it's fast DDR5 CL30 RAM, rated at 6,000 MT/s, with RGB lighting that you can configure. RAM prices are showing no signs of cooling, so getting RAM for nearly $90 less than you'd be paying elsewhere is a worthy option if you're building or upgrading a new PC.

Along with the RAM is an Asus TUF Gaming X870E-Plus WiFi 7 motherboard. This is an enthusiast-friendly board that's packed with a whole host of gaming features. Ready for an AM5 build, this motherboard has 13 USBs at the rear, including two USB-C ports that are rated at speeds of 40 Gbps. You're also getting four M.2 sockets for plenty of SSDs, and with the 9800X3D installed, two of them are rated for PCIe 5.0 speeds over four lanes. There's fast networking, with 2.5 Gb Ethernet and Wi-Fi 7 support included.

A nice extra, too, is that Rosewill AIO cooler. Worth $89.99 if you had to buy it, this 360mm cooler will help to keep your CPU cool, with three RGB fans and a built-in display that can show you your CPU's temperature, fan and pump speeds. No cost here: this one comes with the bundle for free.

Overall, the $1,059.99 sale price for this Newegg parts bundle means you're scoring a top-spec CPU with better-priced RAM than buying it separately before we even consider the motherboard and free CPU cooler. The $128.99 discount here isn't one you should ignore given current market prices, but with these bundles selling out fast, you'll need to be quick to secure it for yourself.

Elon Musk’s Terafab, a joint venture of Tesla and SpaceX, has informally told equipment makers it is seeking to produce 1 million wafers per month after 2032, according to Financial News. About 70% of this output, or 700,000 wafers, is planned to go to memory, with more than 300,000 going to logic chips. Terafab’s procurement team has already visited Japan to ask some local toolmakers for delivery within months. The memory allotment would rival Samsung’s estimated DRAM production capacity if it were all of that type.

Samsung’s DRAM capacity was estimated last year at 650,000–700,000 wafers a month, while SK hynix is reportedly at about 550,000, with about 1 million a goal by 2030. The comparison has to be taken in context, as Terafab’s 700,000 measures all of its expected memory output, which could be NAND or DRAM, while the Samsung and SK hynix figures measure only DRAM. As it is, the memory portion alone would be 3.5 times the reported 200,000 at SK hynix’s Wuxi fab in China.

Many in the industry were skeptical when Musk announced the plans in March, but orders are now leading more companies to see a real business opportunity. The timeline is aggressive, as it usually takes three years or more to get from planning to volume at a leading-edge fab, and Terafab is targeting volume production in the second half of 2028. Procurement officials from the company reportedly visited Japan earlier this month to meet local suppliers and to work on details on bringing in equipment, with some suppliers asked to deliver within a few months.

The Elec also reports that Terafab representatives visited booths of about 10 Korean materials, parts, and equipment firms at SEMICON West, with some NDAs signed.

Logic chips are one thing — Jiji Press reports Terafab is working with Intel to adopt its 2nm and 1.4nm processes — but memory is another, and it’s not clear what type of memory is on the docket. Technical help from a Taiwanese company is under consideration for memory, but no partner has been named, leaving 70% of the planned wafers without a disclosed process technology.

Memory production tends to split between DRAM and NAND flash, the latter for non-volatile storage. A Tesla job listing for a Terafab Memory Process Integration Engineer, reported in August, covers end-to-end DRAM process integration and DRAM node development, and supports emerging memories such as MRAM, RRAM, and 3D DRAM. Terafab hasn’t said how its DRAM would be divided among products like HBM and LPDDR, both useful for AI and both mentioned in its job postings, or whether it expects to make and stack the DRAM itself or package chips it brings in.

Building a cutting-edge logic fab on U.S. soil is its own challenge, and Tesla and SpaceX lack chip-manufacturing experience. Even Musk, on a SpaceX call last month, called Terafab’s dates “very aggressive” and said he put “big error bars” on the timeline. The first SRAM test chip is targeted for around May or June 2027 at the Austin research facility.

How TSMC might fit in remains open. TSMC says any fab with its involvement has to be run by TSMC, while Musk said his own companies would build and operate Terafab, a scenario which could leave TSMC as a space tenant. At least the spending plans are known: $16.8 billion for the first phase in Grimes County, Texas, with total investment of up to $119 billion if later phases proceed. A pilot plant could be completed as early as July 2027.

There's a great Newegg combo deal right now that'll net you half the parts you'll need for a new 4K gaming PC. For $1,090.98, you can pick up the AMD Ryzen 7 9800X3D, one of the best CPUs you'll find for gaming, along with 32GB of Corsair Vengeance DDR5-6000 RAM and a mid-tier Gigabyte X870 Aorus Elite Wi-Fi 7 motherboard.

● Check out this deal at Newegg

The $138.99 saving you're making here means you're getting the RAM for $371, almost $70 less than the current low price for 32GB DDR5 RAM right now. If you count the free Rosewill ATX case you're getting here, too, worth $59.99, the RAM is just $311. These parts give you the foundation for a high-spec AM5 gaming PC that, coupled with a recent GPU that you'll need to buy separately, will smash through high frame rates at 1440p and 4K.

Starting out in this combo is one of the fastest and best of the current-gen gaming CPUs on the market, the AMD Ryzen 7 9800X3D. This eight-core, 16-thread Zen 5 processor has a base clock speed of 4.6 GHz and a max boost speed of 5.2 GHz and a 120W TDP. More importantly for gamers, though, is the L3 cache. This boosted 96MB L3 cache capacity is the reason AMD CPUs have become the dominant force in gaming right now. They're able to deliver faster, more stable frame rates as the CPU doesn't need to rely on the slower system RAM as often while you're gaming.

As the CPU benchmark data shows, the 9800X3D sits near the very top of the food chain right now. Only CPUs like the 9850X3D can beat it; that CPU is 3% faster at 1080p than the 9800X3D, but has much higher power demands. As it stands, the 9800X3D continues to be a firm favorite, and one that'll sit comfortably in high-spec rigs for a few years to come.

You're also getting RAM with this bundle, with 32GB of Corsair Vengeance RGB DDR5-6000 memory included, split across two 16GB modules. If you wanted to buy this RAM separately, it'd currently cost you a huge $509.99 right now. As we mentioned, however, this bundle's collective cost and $138.99 discount bring the effective price down by $138. This black kit matches the motherboard and has customizable RGB, which you can switch on and off. With speeds of 6,000 MT/s, this RAM sits in the sweet spot for gamers, with CAS and latency timings of 36-44-44-96.

As for the motherboard, the Gigabyte X870 Aorus Elite Wifi 7 is a solid mid-range performer for an AM5 gaming PC build. There's plenty of connectivity here, with 12 USB ports on the rear, including two USB-C 4 ports rated for 40 Gbps. There are also four M.2 slots, one rated for PCIe 5.0 with the 9800X3D installed, along with Wi-Fi 7 and 2.5 Gb Ethernet connectivity. There's also a five-year warranty for support.

The Rosewill mid-tower ATX case is a nice extra, and if you bought it separately, it'd cost you $59.99. It's a gaming PC case, with four 120mm fans, a tempered glass side and a mesh front to keep your fans free from dust. Luckily, it's all free here.

The $1,090.98 sale price for this Newegg combo bundle with the 9800X3D means you can save nearly $140 on the RAM compared to buying it separately. The $138.99 discount will help towards the cost of a new SSD or GPU, especially given how expensive PC components have become recently. These bundles sell out quickly, though, so you'll need to be quick.

The smartphone industry is expected to see a spike in reballed memory adoption. According to a report by global market intelligence and research firm TrendForce, the current penetration rate is estimated at around 3–4%, with reballed memory primarily used in entry-level and budget smartphone models. However, this figure is expected to rise to 7–9% in 2027.

Reballed memory is recycled memory salvaged from older or discarded devices. The term reball comes from the process itself, in which the solder balls on a used memory chip are first melted so the chip can be removed from the old device, then re-soldered to a new device, thus allowing the component to be reused rather than discarded. You can see the process in action in the video below.

This offers manufacturers a cheaper alternative to sourcing new memory chips, potentially helping them keep production costs under control. Currently, reballed 4GB LPDDR4X memory modules make up the majority of such components on the market, and they are used in 4G smartphones priced below CNY 1,299 (approximately $200).

This tactic is becoming increasingly important for smartphone makers, as customers are particularly sensitive to price increases in the budget segment. This leaves limited room to raise retail prices without affecting demand. Using reballed memory can help offset rising bill of materials (BOM) costs while allowing brands to keep entry-level devices affordable.

TrendForce expects DRAM prices to rise even further in the first quarter of 2027, which may put additional pressure on smartphone manufacturers. As a result, the use of recycled memory and other lower-specification components could gradually expand beyond the entry-level segment and into more premium smartphones. What is currently a cost-saving measure for budget devices could eventually become a broader strategy for manufacturers looking to manage expenses amid a prolonged period of high memory prices.

The rising cost of memory is also pushing PC enthusiasts and hardware hobbyists to explore unconventional ways to reuse existing DRAM chips. Recently, an electronics hobbyist converted a relatively inexpensive $120 DDR5 SO-DIMM kit into a desktop memory kit valued at around $1,000. The project involved salvaging an SK hynix 2x 16GB DDR5-5600 SODIMM kit purchased from Facebook Marketplace and reballing the chips onto custom desktop DIMM PCBs, with the resulting modules reportedly capable of reaching DDR5-7800 speeds.

Converting laptop memory into desktop DIMMs is technically demanding and requires considerable expertise and specialized equipment. Similarly, reballing memory for use in smartphones is far from straightforward, particularly given the tiny solder connections in modern BGA (Ball Grid Array) packages. Nevertheless, both developments highlight how manufacturers, repair specialists, and hardware enthusiasts are exploring alternatives to reuse existing memory to offset rising costs and limited availability.

A recent report from The Information suggested that TSMC is exploring 3D DRAM production at Nvidia's request as surging demand for AI hardware strains global DRAM supplies and drives up prices. If the proposal were to come to fruition, it could mean a new, albeit prone to cyclical risks, business for TSMC and could dramatically expand its role in the AI supply chain. For its part, TSMC states that it is a pure-play logic foundry and plans to remain a logic foundry, which essentially means a denial of the report.

"Please note that TSMC focuses on our core business at all times, which is dedicated IC foundry," a TSMC spokesperson told Tom's Hardware. "Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come."

Despite the denial, according to two people familiar with the initiative cited by The Information, TSMC has begun preparing plans for 3D DRAM manufacturing following a request from Nvidia, its largest customer. The initiative is reportedly overseen by Hsu Kuo-chin, TSMC’s vice president responsible for advanced packaging and former head of Micron’s Taiwanese operations. The effort comes amid widespread memory shortages that turned memory from a commodity into a strategic asset that could determine whether a company can ship its products to customers or not.

Although TSMC works closely with DRAM producers as it packages memory into system-in-packages (SiPs) for its customers, the company lacks the expertise and production capacity to make DRAM, let alone 3D DRAM. Meanwhile, given that 3D DRAM is years away even for major memory makers, pursuing a 3D DRAM strategy cannot solve memory shortages for at least five years.

Unlike conventional DRAM, which arranges memory cells in a single plane, 3D DRAM places multiple levels of memory cells vertically to increase capacity per wafer. All three leading DRAM makers — Micron, Samsung, and SK hynix — are working on their 3D DRAM projects. However, Micron's DRAM strategy includes at least four more planar DRAM process technologies before 3D DRAM becomes a reality.

While TSMC has arguably the industry's best logic process technologies, DRAM production requires entirely different manufacturing processes, which TSMC would have to develop, should it pursue making memory for its customers. Meanwhile, producing 3D DRAM requires completely different fabrication techniques to construct multiple memory-cell layers while controlling defects and maintaining acceptable yields. It is hardly possible to develop a 3D DRAM manufacturing process without having a competitive planar DRAM process technology, and TSMC does not have one.

One of the options for TSMC to enter the DRAM business would be to acquire a small specialty memory producer that has its own fabrication capability. This would give TSMC a credible route into advanced DRAM manufacturing without having to develop the underlying memory technology and IPs from scratch. However, small makers do not have leading-edge commodity DRAM nodes, so TSMC would still need to invest billions of dollars and years of R&D into development of a leading-edge process technology for DRAM.

However, entering DRAM manufacturing would expose TSMC to substantial market risks. Memory shortages frequently encourage capacity expansions that eventually create oversupply, depressing prices and profitability. Such uncertainty could surely make TSMC think twice before going down the DRAM route. Furthermore, entering the DRAM business could also complicate TSMC's relationship with large DRAM makers in general, and SK Hynix, which partnered with the foundry in 2024 to manufacture logic base dies for next-generation HBM products, in particular.

TSMC’s potential entry into DRAM manufacturing could also raise antitrust questions, particularly if the company combines its dominant position in leading-edge logic manufacturing, leading position in advanced chip packaging, and ramping memory production. Regulators could examine whether such vertical integration would enable TSMC to favor its own memory products or disadvantage competitors that lack such a vertical integration. Then again, in-house DRAM development by TSMC could also strengthen competition by introducing another supplier into a market dominated by just three manufacturers.

Yet, TSMC does not necessarily need to manufacture DRAM to capitalize on growing demand for advanced memory. Instead, it could capture a larger share of the value generated by DRAM by producing sophisticated logic base dies for HBM, integrating memory with processors using its SoIC hybrid bonding technology, and developing customized memory solutions with partners such as GUC and established DRAM manufacturers. This approach would allow TSMC to expand its presence in the advanced memory market without investing billions of dollars in developing competitive DRAM process technologies from scratch and/or building additional fabs for tens of billions of dollars.

A Pat Gelsinger-backed Georgia Tech spinout, Nagare Labs, says its Z2RAM can put SRAM-speed memory, at DRAM density, directly on top of AI chips. The founders’ own papers show a fast-improving cell that, tested up to 85 degrees Celsius, holds data for over 300 seconds. Gen 1 is projected to have 5x SRAM density with six stacked layers, 14x DRAM speed, and 3x less read energy than SRAM.

AI chips require a lot of bandwidth, and it has been challenging to get sufficient yields of high-bandwidth memory (HBM) to feed them. Even when manufacturers can get it, some reportedly plan to settle for fewer layers for yield reasons, and heat is another. Heat is also why Samsung’s zHBM, which stacks DRAM directly on the processor, is planned at only about four layers.

Alternatives include high-bandwidth flash, still in development, which stacks NAND like HBM and would sit beside the GPU, or SRAM stacked directly on the die, which is less dense and more expensive for the capacity, but also faster. DRAM, which is more capacious, can sit on top of the compute, but heat limits how hard the logic underneath can run.

That limit is already shaping chipmakers’ design path for stacked memory. Micron’s vHBM plans, for example, include heat-spreading structures. With HBM stacked on a logic die, and DRAM needing to be kept at or below 95 degrees Celsius, the logic’s heat output is capped at 220 W/cm², or 300 W/cm² with better thermal vias, according to a 2025 simulation by co-founder Shimeng Yu’s group. Nagare Labs says peak compute has grown 70% a year over the past three decades, against 20% for memory bandwidth.

The company describes its Z2RAM as “Two transistors and a shield. No capacitor,” where a write transistor places a charge on a storage node and the shield blocks noisy neighbors. The read transistor can sense without draining. In a gain cell like this, the read transistor’s gate capacitance holds the charge, so reads are non-destructive and the cell avoids DRAM’s write-back. Nagare aims for well under a picojoule per bit.

Nagare builds Z2RAM by depositing its layers on top of the accelerator and patterning them “together on one die,” much as 3D NAND flash scales by adding layers. There’s no interposer and no bonds between the memory layers, which is part of the secret sauce. One lithography exposure covers several layers at once, and standard 300 mm tools with DUV do the job, with no EUV required. The current roadmap is aiming at over 100 layers with “hundreds of thousands” of vertical connections.

Retaining data at higher temperatures is the challenge, and one the founders have probed repeatedly with their testing. A 2020 paper from co-founder Suman Datta’s group, on a tungsten-doped indium oxide two-transistor cell, had retention of 1 second at 25 degrees Celsius and just 300 milliseconds at 85°C. An update in 2025, which has Datta as a co-author, adds a third transistor and removes the gate overlap from its transistors, managing over 1,000 seconds at 25°C, up from 200 seconds with overlapped ones. It also simulated a GPU L2 at twice SRAM’s capacity but in the same area with 75–80% lower energy-delay-area product, a combined score that multiplies energy, delay and area.

Six months later, both founders showed a “folded asymmetric boosted” three-transistor cell that held data for over 300 seconds at 85°C, as compared to only 100 milliseconds for a conventional three-transistor design. That’s still below the roughly 95°C that Nagare says DRAM must stay under, so neither the founders’ published cells nor Z2RAM have shown retention above that line yet. The boosted cell is also “refresh-free,” which means data in the GPU’s last-level cache, profiled from AI workloads, doesn’t have time to decay before it is overwritten.

Physical space is also limited for this application, and the founders project their boosted cell at 0.0168 µm² at 7nm, compared with 0.0199 µm² for a high-density SRAM cell on TSMC’s 3nm (N3) process. A separate study from Yu’s group found that a four-tier, 256MB cache of two-transistor gain cells at 7nm could reach 5.7x the bit density of 7nm SRAM in the same area, in simulation. However, the return on investment falls off past seven or eight tiers because masks scale with layers. Nagare Labs’ claim of single lithography would potentially bypass this limitation.

That has not yet been proven, and nothing published yet shows it. “Where we are is literally lab prototypes,” Datta told The Register, adding that sampling of Z2RAM tiles is targeted within four years and production shipments, if they arrive, within the next decade. Yu told the outlet that no standard yet exists for integrating this kind of memory with an accelerator, which means Nagare might have to come up with the interface itself. Datta also mentioned reliability to the outlet, as single-electron effects can shift a cell’s threshold enough to upset the stored bit. It also remains to be seen if the tested three-transistor cells work sufficiently well as a two-transistor, single-shield product.

Even if Nagare clears those hurdles, a more important one lingers: It currently has no fab. The plan to scale depends on getting partners for fabrication as well as packaging. Nagare is reportedly looking for an R&D fab partner so it can scale beyond the university clean room. Perhaps the most similar type of memory-on-compute shipping today, and the one Datta cited to the outlet as a model for working with chipmakers, is AMD’s 3D V-Cache.

Z2RAM isn’t the first capacitorless memory to promise a 5x improvement over SRAM in density; it follows in the footsteps of Innovative Silicon’s Z-RAM from 20 years ago, a technology AMD licensed, though it was not pursued. A Georgia Tech paper due at IEDM in December covers a different device, a one-transistor, one-ferroelectric-transistor cell, aimed at the same gap between SRAM latency and DRAM density.

Gelsinger, previously CEO of Intel, which started as a memory company, phased out Optane, a low-latency non-volatile memory, in favor of CXL. Optane sought to bridge the gap between slower non-volatile storage, such as HDDs and standard SSDs, and DRAM. Now he sits on Nagare’s board, and Playground Global, where he is a general partner, led the startup’s $5 million round as Nagare searches for a solution to a different but related problem.

Nagare declined to share measured retention, latency, or energy figures. The founders’ boosted cell already holds data at 85°C longer than a cache needs, but until a fab-built, multi-layer Z2RAM stack is measured, retention above 95°C included, its headline numbers remain projections.

Team Group CEO Chen Ching-wen said during the company’s November 2 earnings call that the memory chip shortage is expected to become worse from the end of 2026 until the end of 2027. BigGo Finance quoted Chen as saying that there is “no downward price trend whatsoever,” and that some purchasers could face a scenario “even money can’t buy goods.” He also noted that the spread between spot and contract prices for memory chips ranges from 30% to 50%, meaning short-term supply is significantly more expensive than long-term contracts.

"We have contracts but can't get enough volume, so we have to go to the spot market and pay a premium to grab supply," the Team Group chief said during the briefing. Contract prices for 16GB DDR5 chips climbed from $8.70 in October 2025 to $48 by September 2026. This is an increase of more than 550% in the past 12 months, and it seems that the price hikes are not letting up. He also estimated that supply and demand will not balance until the latter half of 2028 or perhaps even later. “How can prices fall when there’s nothing left?” said the CEO.

The Chairman also noted that even though CXMT and YMTC have increased their market share to almost 10%, most high-end DRAM and NAND flash chips still come from Kioxia, Micron, Samsung, and SK hynix. Even then, the prices for the chips that these Chinese companies make still track the market closely, meaning they’re not the budget savior that many were expecting. As such, he expects that pricing for budget components will not ease until 2029, while high-end chips will continue to remain in short supply.

These estimates go against Acer CEO Jason Chen’s prediction that component pricing will reverse by the latter half of 2027. Chen suggests that only high-end chips, like LPDDR5X-9600 and Nvidia N1-series SoCs, will remain in shortage while mainstream parts will finally go down. PCs will still experience hikes between 5% and 20% until the end of this year, plateau during the first half of 2027, before finally going down. Chen claims that most major suppliers want to hype the shortage for as long as possible to preserve their margins.

Unfortunately, there’s no way for us to know which of these predictions will come true. While consumers would gladly want to have a break from the nearly continuous price hikes that PC parts and components have been experiencing over the past months, the AI data center build-out is apparently continuing, even as many Americans voted against it.

Last month, Micron disclosed its DRAM and NAND memory roadmaps for the next several years, revealing plans to use wafer bonding, new materials that enable making NAND cells smaller, High-NA EUV lithography, and detailing its moves toward 3D DRAM. Perhaps the most revealing part of Micron's story is that the company plans to expand its portfolio of custom DRAM and NAND products as AI developers increasingly require memory and storage solutions optimized for their unique processor architectures and specific workloads.

" DRAM is nearing atomic limits at this point: although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view," said Scott DeBoer, president and chief technology and products officer at Micron, at the company's event earlier this month. "[With 3D NAND, we are] really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward."

DRAM: 4F2 cells axed, High-NA EUV lithography, new materials, and 3D DRAM enable future scaling

In a surprising move, Micron decided to abandon plans to produce DRAM with 4F² memory cells, unlike its rivals at CXMT, Samsung, and SK hynix, citing the lack of a viable scaling path beyond where Micron is today. Instead, Micron's roadmap for the coming years includes wafer bonding, High-NA EUV lithography, new materials, and eventually 3D DRAM. The company plans to begin mass production of its next-generation 1δ memory in the second half of 2027, while subsequent 1ε, ζÅ, and ηÅ technologies are at various stages of development. In parallel, Micron is developing two generations of 3D DRAM that could eventually succeed conventional planar memory.

Micron's current 1γ (1-gamma) DRAM process technology, which is in high-volume manufacturing (HVM), is the company's first DRAM node to use EUV lithography. Previously, Micron had used multipatterning with DUV lithography and remained competitive with Samsung and SK hynix, which relied on EUV for critical layers.

Micron's next-generation 1δ (1-delta) fabrication process is currently in the yield ramp stage and is scheduled to enter mass production in the second half of 2027. The company expects the technology to increase bit density by mid-20% compared to 1γ, while advanced high-k metal gate (HKMG) CMOS, new materials, angstrom-level process control, and equipment intelligence should improve performance, power efficiency, and ultimately yields as well as costs.

Micron plans to manufacture 1δ DRAM in the U.S. and use the technology for next-generation DDR, LPDDR, graphics memory, HBM5, vertical HBM (vHBM), and vertical Edge Inference Memory (vEIM) products. Meanwhile, to make HBM5, vHBM5, and vEIM products, the node will also support additional features like through-silicon vias (TSVs) and other elements to improve thermal performance.

The subsequent 1ε (1-epsilon) process will rely on wafer bonding, which will enable Micron to produce different structures on separate wafers and then bond them together. This approach could increase flexibility in memory design and manufacturing, but Micron has yet to disclose its plans to implement wafer bonding, which structures it will bond, or what improvements in density, performance, and power consumption the technology will provide. The process is currently under development, and there is no announced production schedule.

Micron's ζÅ (zeta-angstrom) production node is currently in early development and will introduce High-NA EUV lithography to memory manufacturing, which will enable further reductions in critical dimensions. The company has not disclosed how many layers will require High-NA lithography, the expected density improvements, or when the technology will enter mass production. However, it is obvious that the node will not be here until at least 2030, years after Samsung and SK hynix adopt High-NA EUV at their DRAM fabs (planned for 2028).

The ηÅ (eta-angstrom) process represents the most distant generation on Micron’s disclosed planar DRAM roadmap and is currently in the pathfinding stage. After Micron inserts High-NA EUV lithography into its DRAM production flow, the company intends to bet on other methods of scaling. Although Micron mentions new materials, it hasn't identified them or explained how they will affect device structures. These could include new photoresists, deposition precursors, dielectric materials, or conductive materials that would enable the company to manufacture smaller transistors and capacitors, and ultimately increase DRAM cell density.

In any case, Micron's roadmap is focused on continuing development of DRAM based on 6F² cells, which differs from the plans of CXMT, Samsung, and SK hynix.

3D1 and 3D2: Transition to 3D DRAM is looming

In parallel with conventional DRAM development, Micron is working on two generations of 3D DRAM, currently called 3D1 and 3D2. Unlike planar DRAM, which primarily relies on smaller memory cells to increase bit density, 3D DRAM would use the vertical dimension to accommodate more memory cells within a given area. Micron intends to introduce the technology when it becomes competitive with conventional DRAM in terms of manufacturing costs and performance. The company has not disclosed architectures, layer counts, or density targets.

In fact, while Micron has outlined its future memory architectures through 2030, its DRAM manufacturing roadmap provides a firm production window only for the 1δ process, which is scheduled to enter high-volume manufacturing in the second half of 2027. The company has not disclosed production dates for subsequent planar DRAM nodes or either generation of 3D DRAM.

Custom HBM and vertical memory architectures

In addition to conventional DRAM, Micron plans to use its future manufacturing technologies for HBM4E, HBM5, HBM5E, and new vertically integrated memory architectures. Starting with HBM4E, the company will offer both standard and custom HBM products, which will be followed by custom HBM5E, vHBM, and vEIM (vertical Edge Inference Memory). All of these will mark the re-emergence of custom memory in mass-produced products.

Custom HBM4E (cHBM4E) will enable Micron's customers to shrink memory I/O width and/or integrate additional logic into the memory's base die to free up valuable die space for compute and optimize performance and power consumption for specific AI accelerators. According to Scott DeBoer, Micron’s president and chief technology and products officer, some of these functions would otherwise reside in the ASIC itself, so moving them closer to memory should improve overall system efficiency.

"When we co-design a base die, and the certain logic elements that are desired to be put in that base die are generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory," said DeBoer. "Moving what makes more sense onto the base die will still be a reality in [the] vertical HBM timeframe as well."

To support these capabilities, Micron intends to use advanced foundry process technologies for the base dies of both standard and custom HBM products, although it has not disclosed specific nodes. For custom designs, the company will select the most cost-effective process that meets customer requirements. For example, Micron expects HBM4E to require more advanced CMOS technologies to meet its performance and power targets.

Further down the road, Micron intends to introduce vertical HBM (vHBM), which will stack memory directly on top of ASICs and CPUs rather than next to them on an interposer. This architecture promises substantially higher bandwidth, thanks to dense vertical connections (as well as significantly lower latencies) thanks to adjacent placement, but it is also set to create considerable challenges related to power delivery and heat dissipation. To address them, Micron plans to use hybrid bonding for advanced interconnects, integrated heat spreaders, and thermally aware designs. Interestingly, the company expects conventional HBM and vHBM to coexist in some designs, where vHBM provides maximum bandwidth, while traditional HBM serves capacity requirements.

Another technology under development is vertical Edge Inference Memory (vEIM), which shares many of its packaging and integration technologies with HBM, but targets applications that require power efficiency more than maximum bandwidth. Micron's 1^st Generation vEIM aims to deliver formidable HBM4-like 2 TB/s of bandwidth while consuming less than 1 picojoule per bit of data transfer energy.

Both architectures will require close cooperation with customers to optimize memory, logic, packaging, and thermal characteristics for particular applications, so Micron will need to work with its clients to make vHBM and vEIM successful. Interestingly, Micron's customer-specific development efforts extend beyond HBM and EIM.

For example, the company is collaborating with Meta to optimize LPDDR6 for data center applications, which primarily include reliability, serviceability, and availability. Micron expects LPDDR6 to reduce power consumption by approximately 35% compared to LPDDR5, which will be very important for dense memory deployments. The company also intends to develop DDR6 — which targets 2X DDR5 bandwidth — in cooperation with major customers to better understand and ultimately meet their needs.

Speaking of customer cooperation, DeBoer stresses that Micron now collaborates with customers from the earliest stages of product definition through joint design, development, validation, and volume production. According to the executive, this approach differs substantially from how the company worked with customers previously.

"Across our AI co-invention opportunities we are co-imagining, co-designing, co-developing, co-validating, and then delivering at scale," DeBoer said. "This opportunity is truly unique. It is very different than the way we interacted with customers even three or four years ago."

Advanced CMOS: More than 10X performance improvement

In addition to shrinking DRAM cells and developing vertical memory architectures, Micron is developing advanced CMOS technologies for peripheral circuitry. The company's roadmap includes several generations of DRAM CMOS logic with high-k metal gate transistors, followed by 1^st and 2^nd Generation 3D CMOS technologies.

Micron expects these advances to increase its CMOS logic performance by more than 10X between 2020 and 2030, which should help the company address the growing bandwidth and power requirements of AI-oriented memory products.

3D NAND: From next-gen 400L 3D NAND to AI-oriented NAND

Although Micron's event was mostly dedicated to the future of DRAM, the company also shared some details about its upcoming NAND innovations, which include 11^th Generation 3D NAND with 400 layers, post-G11 3D NAND, and AI-oriented NAND memory that either offers high bandwidth or high IOPS.

Micron's next-generation G11 (N170) 3D NAND technology represents a substantial departure from its current G9 (N160) process. The company plans to increase the number of active memory layers from 276 to more than 400, introduce wafer-on-wafer bonding, and implement an industry-leading memory cell pitch.

These improvements are expected to double the bit density of G11 3D NAND compared with G9 3D NAND, presumably from 21 Gb/mm² to 42 Gb/mm² in the case of 3D TLC devices, which should substantially reduce manufacturing costs per bit once the technology reaches mature yields.

In addition to increased storage density, G11 also targets a 50% increase in I/O speed compared with G9, which implies a potential transfer rate of approximately 5,400 MT/s. Furthermore, Micron expects to reduce data transfer energy consumption by more than 25% per bit, an important improvement for high-capacity SSDs and AI storage systems that tend to move huge amounts of data.

One of the most important changes with G11 is the adoption of wafer-on-wafer bonding, which lets Micron manufacture memory arrays and the periphery and I/O circuits on another wafer, then bond them together. Chinese manufacturer YMTC has used this method to maximize storage capacity and performance, so it is not surprising that Micron and other memory manufacturers are adopting the technique as well.

Micron expects to start mass production of G11 3D NAND in the second half of 2027.

Improving 3D NAND past G11: New materials and further XYZ scaling

Micron intends to continue improving 3D NAND beyond 11^th Generation through a combination of new materials, denser memory cell architectures, and more energy-efficient devices and data paths. Specifically, Micron is investigating high-mobility materials that could improve the electrical characteristics of future memory devices, as well as ultra-dense cell architectures intended to increase storage density beyond what an increase in active layers provides.

Meanwhile, more energy-efficient circuitry and data paths should help offset the growing power consumption associated with higher NAND capacities and faster interfaces.

"Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward," said DeBoer. "[…] The current industry direction and Micron’s direction is scaling both by adding layers [and] also by shrinking the cell dimensions."

The company has not identified the materials it intends to introduce or explained how they will affect memory cell structures. Nor has it provided quantitative density, performance, or power targets for NAND generations beyond G11.

AI-oriented NAND: Higher IOPS and bandwidth

Although Micron is not ready to share details about its G12 or G13 3D NAND generations, the company disclosed that it is developing two specialized NAND architectures for AI applications.

The first — High-IOPS AI NAND — architecture focuses on maximum random I/O performance and uses SLC-based designs with small blocks to accelerate workloads such as vector searches, graph analytics, and AI context management. Micron envisions products capable of delivering approximately 25 million to 100 million IOPS, depending on their configuration, and expects to bring products based on this approach to market over the next couple of years.

The second — High-Bandwidth AI NAND — architecture prioritizes bandwidth over random I/O performance. Micron is investigating vertically stacked NAND devices connected through TSVs and equipped with a logic base die that resides close to AI accelerators, so from many points of view this concept resembles SanDisk's HBF. However, Micron does not believe that simply placing NAND stacks alongside AI accelerators on an interposer offers sufficient advantages. Instead, the company is exploring alternative integration approaches that bring NAND closer to compute resources, but don't necessarily consume valuable shoreline (the perimeter, or edge) of AI accelerators.

"[The High-Bandwidth AI NAND is] more costly and has to be implemented in partnership with customers in a way to ensure that they are meeting the mark and the cost point to drive the value proposition," DeBoer said. "We are enabling TSV-stacked NAND with a logic base die to bring memory closer to accelerators. We do not think placing it along the shoreline of the GPU has merit. Instead, we want to position it closer to the compute itself to take advantage of this high-performance NAND."

These specialized AI-focused NAND architectures will complement Micron's conventional SSD roadmap, which includes plans for drives with capacities of up to 512 TB in the foreseeable future.

Apple is about to feel the squeeze from rising memory prices, with the cost of RAM climbing just as the company heads into its busiest shopping season. According to Reuters, Apple expects to pay more for memory in the December quarter, with the CEO, John Ternus, describing the current price increases as “unprecedented. The company has so far managed to soften the blow by using memory bought at lower prices, cutting costs elsewhere and raising prices on some products. However, it is reported that its manufacturing bill has climbed by $33 billion in just a few months.

But that cushion is getting thinner, and Apple expects memory purchases to become even more expensive into 2027. “What we're seeing with memory pricing right now is unprecedented. And as we said earlier in the September quarter, we did see higher memory costs as compared to the June quarter, which were partly offset by the benefit of carrying inventory and lower costs on certain non-memory components. Now for the December quarter, we expect even higher memory costs, partly offset by a few factors. So as you know, we changed the price on many of our products, including Mac and iPad at the end of June and iPhone in September, and these price increases provided some offset.” Ternus said during Apple’s November 2 earnings call.

Memory is used across Apple's hardware lineup, so sustained price increases could affect manufacturing cost for several product categories—although Apple has not announced another round of price increases. Absorbing higher components could, however, indefinitely become difficult. Dave Nicholson, Chief Research Officer at the Futurum Group, also identified memory prices as a growing pressure point for Apple's margins and hardware pricing through the holiday season and into 2027. According to him, Apple is in a different position from companies pouring hundreds of billions of dollars into AI data center infrastructure. The impact of higher component costs is easier to quantify than the eventual returns on massive AI capital expenditure, he said.

And the warnings from Apple's suppliers suggest that the cost pressure is unlikely to ease quickly. Last month, Samsung, a major supplier of RAM(DRAM), NAND flash storage and OLED displays for Apple, said that memory demand would far exceed supply as AI infrastructure continues to expand. Its memory division also reported a quarter-on-quarter increase in DRAM average prices during the third quarter, while NAND prices rose by high-teen percentages. Senior executive vice president of its memory business warned the supply crunch could extend to 2028 and beyond. Elsewhere, SK Hynix delivered a similar warning, saying it had secured long-term agreements covering more than Half of its production capacity for2027 and 2028. Micron, the third major supplier for Apple aside from Samsung and SK Hynix, is also benefiting from the surging demand for memory. Its latest published outlook warns that supply shortages in memory and storage could take “considerable time” to improve.

We have previously reported several signs of the pressure now confronting Apple. In January, the company was already scrambling to secure memory supplies amid strong demand, with then CEO Tim Cook warning that rising prices could have a greater impact on earnings. By June, rising component expenses had translated into higher retail prices. Apple increased prices across several Mac and iPad models, including a $400 increase to the starting price of the MacBook Pro, due to the RAM crisis. In July, Cook described the memory market as a “hundred-year-flood” and said Apple expected to pay more for memory in the September quarter. The company had also increased its inventory to $11.09 billion as it built a buffer against supply and price pressures.

Having jettisoned 4F² memory cells from its roadmap, Micron must use different methods to continue scaling its DRAM devices in the coming years to keep up with rivals planning to use smaller DRAM transistors towards the end of the decade. Instead, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. Meanwhile, the company is developing new types of memory, including vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM), which will be integrated directly on top of processors.

"DRAM is nearing atomic limits at this point," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. "Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view."

Wafer bonding, High-NA EUV, and new materials

Micron's current 1γ DRAM process is already in high-volume manufacturing, whereas its successor, 1δ, is scheduled to enter volume production in the second half of 2027. The latter promises a mid-20% increase in bit density and is optimized for future AI memory products, including HBM5, vHBM, and vEIM. Beyond 1δ, Micron plans to introduce wafer bonding with its 1ε process, which is currently under development. However, the company has not disclosed how it intends to implement wafer bonding or what improvements it expects from the technology.

For subsequent generations — ζÅ and ηÅ — Micron plans to adopt High-NA EUV lithography (ζÅ, zeta angstrom, Micron's 1^st Generation sub-10nm-class DRAM node) and new materials (ηÅ, eta angstrom, Micron's 2^nd Generation sub-10nm-class DRAM node) to continue shrinking DRAM cells. For many of its upcoming fabrication technologies that will be used over the next five to 10 years, Micron is also collaborating with Albany NanoTech. Of course, as with all organizations like Albany NanoTech, we are mostly talking about fundamental, or pre-competitive, IP that could be used for DRAM production at some point.

 "Albany NanoTech, our announced focus on advanced lithography [is] really driving High-NA EUV roadmap for DRAM," said DeBoer. "In particular at Albany with our team there, focused on the next five to ten years."

Micron is also developing 3D DRAM technologies and lists two generations — 3D1 and 3D2 — in its roadmap already. However, the company has not disclosed its architectures or launch schedules, as it intends to introduce 3D DRAM only when the technology offers sufficient advantages in manufacturing costs, complexity, and performance over conventional planar DRAM.

"When we look at three 3D DRAM we have that on the roadmap, as I mentioned, and it is shown here in between one zeta and one eta," said Micron's CTO. "But in reality, this is a parallel path, and we will implement it [3D DRAM] in a fashion that is ideal for cost, complexity, and device performance."

Going vertical, becoming critical

Beyond developing new process technologies for its upcoming DRAM products, Micron is also working on all-new types of DRAM products that are tailored for very specific use cases, including vertical HBM (vHBM), vertical edge inference memory (vEIM), and various custom HBM (cHBM) implementations.

vHBM will place memory stacks directly on top of processors (such as AI accelerators and AI GPUs) rather than next to them. This approach promises substantially lower latencies and higher bandwidth thanks to shorter connections. However, placing memory above a processor creates significant thermal challenges and limits the number of memory stacks that can be integrated on top of an ASIC. Therefore, Micron expects vHBM to complement conventional HBM, which will continue to provide the bulk of memory capacity in many AI accelerators.

Another technology under development is vertical edge inference memory (vEIM), which shares architectural and packaging characteristics with vHBM but targets different applications. Whereas vHBM prioritizes maximum bandwidth for high-performance AI accelerators, vEIM is focused on energy efficiency for edge AI processors used in autonomous vehicles, robotics, and other power-constrained devices. Nonetheless, even the 1^st Generation vEIM targets formidable 2 TB/s bandwidth at <1pJ/bit energy, which is in line with what HBM4 currently offers (at 8 GT/s over a 2,048-bit interface). Micron intends to optimize these products with customers according to their bandwidth, capacity, and power requirements.

Both vertical memory architectures will require advanced packaging technologies, particularly hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management will also be critical, especially for vHBM. To meet cooling requirements, Micron is developing specialized heat-spreading structures to transfer heat from hot regions of memory base dies through the DRAM stacks.

The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. What is important about the development of such types of memory is that it indicates that future improvements in memory performance will increasingly depend on advanced packaging and closer integration with processors, which will require collaboration between DRAM makers and logic developers. In turn, this transforms memory from a commodity to a critically important ingredient of an ASIC design.

DRAM featuring 4F² memory cells has long been considered one of the holy grails of the DRAM industry, as they promise to reduce cell area by 33% compared with conventional 6F² designs and therefore enable building DRAMs with more memory cells in the same area. However, after working on 4F² memory cells for a couple of decades, Micron has concluded that the architecture offers no meaningful density advantages, increases manufacturing complexity and costs, and has fundamental scaling limitations. This has a dramatic impact on Micron's future plans.

"Micron invented 4F² DRAM," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event on Wednesday. "The path with 4F² DRAM is always been an option through time, and we have evaluated it and not pursued it due to increased complexity and cost through this past two-decade period of time."

Interestingly, both Samsung and SK hynix still have 4F² memory cells in their roadmaps (according to TechInsights), so Micron's rejection of the technology puts the company on a unique trajectory. Several years ago, the company delayed integration of EUV lithography into its manufacturing flow, contrary to what its rivals did, and still managed to retain competitive positions both in terms of costs and in terms of performance. Therefore, skipping 4F² memory cells is not completely surprising.

4F² is not the future of Micron's DRAM

The main attraction of 4F² DRAM is its theoretically smaller memory cell. The 4F² naming refers to a cell area equivalent to four times the square of the minimum lithographic feature size (F), compared with six times F² for conventional DRAM.

At identical feature dimensions, a 4F² cell occupies approximately 33% less area than a 6F² cell, which could theoretically increase the number of memory cells per wafer by 50%. Such an improvement would reduce manufacturing costs per bit and increase per-device memory capacity even without an equivalent reduction in feature dimensions. However, to make these advantages possible, DRAM makers must develop a suitable transistor architecture and a sufficiently compact capacitor arrangement. This is not easy at all.

The CTO of Micron says that the theoretical advantages of 4F² DRAM do not necessarily translate into higher memory density in practice. DeBoer explained that dimensions and pitch of DRAM capacitors, rather than the nominal area of DRAM transistors, ultimately determine how many memory cells can fit on a wafer. Both 4F² and 6F² transistor structures must fit beneath the capacitors, which means that reducing transistor area alone does not guarantee a corresponding reduction in overall cell size because transistors need a capacitor. Furthermore, Micron believes that 4F² introduces additional manufacturing steps and complexity that increase costs without delivering sufficient benefits.

"It is important to understand the capacitor pitch, the capacitor size, and dimensions, is what sets the DRAM bit density, not whether it is 6F², 4F², 8F²," DeBoer said. "From our investigation of this technology over the past couple of decades, it is a bit of a myth that 4F² actually provides anything versus 6F². It is capacitor pitch that defines the DRAM. You can build the cells, the transistors underlying them in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM [cell size]. So, some of that is just smoke and mirrors in terms of talking about 6F² versus 4F²."

4F² memory cells may curb new process technologies

Instead of adopting the 4F² DRAM cell architecture, Micron plans to continue scaling conventional 6F² DRAM. The company believes it can increase bit density by reducing capacitor pitch and shrinking process technologies even without introducing a fundamentally different transistor architecture.

Advanced lithography, new materials, and wafer bonding should allow Micron to extend planar DRAM scaling for several more generations, according to the company. For example, its upcoming 1δ process technology, scheduled to enter volume production in the second half of 2027, promises a mid-20% improvement in bit density compared with its predecessor. Micron also plans to adopt High-NA EUV lithography for future DRAM generations.

Interestingly, DeBoer fully acknowledges that 4F² DRAM is technically feasible and that Micron itself has manufactured experimental devices based on the architecture. However, its manufacturing complexity and costs become increasingly problematic as feature dimensions shrink, so essentially Micron claims that it can either adopt 4F² or use more sophisticated process technologies, a claim that perhaps implies why China-based CXMT recently praised 4F². Although DeBoer did not identify any specific physical limitations involved, he stated that 4F² has no sustainable scaling path beyond a certain point. This suggests that Micron sees little value in introducing an intermediate architecture that would eventually require another major transition.

"When you look at a scaling path, you can go back a few nodes and absolutely, 4F² can be built back a few nodes, no question about it," DeBoer noted. "It is more complicated, it is more complex, it is more costly, but you can do that. When we look at scaling 4F² beyond where we are sitting today, there it is; it is physics. There are fundamental problems with 4F² scaling that ultimately will lead to 3D DRAM coming in instead of 4F²."

3D DRAM is the future

Indeed, Micron's preferred long-term solution is 3D DRAM, which would increase memory density by stacking memory cells vertically rather than relying exclusively on reductions in their lateral dimensions. Alongside development of multiple next-generation planar DRAM process technologies, the company is already developing multiple generations of 3D DRAM production nodes (which is not surprising, as 3D NAND nodes will rely on fundamental innovations developed for planar processes), although it has not disclosed when the new architecture will enter commercial production. DeBoer indicated that Micron will make the transition when 3D DRAM offers the right combination of density, manufacturing complexity, and cost.

Although both Samsung and SK hynix have 4F² DRAM products in their roadmaps, Micron believes that the assumption that reducing the nominal footprint of DRAM cells improves manufacturing economics is wrong and that extending 6F² scaling and eventually adopting 3D DRAM offers a better long-term strategy.

The two biggest NAND flash memory manufacturers on the planet, Samsung Electronics and SK Hynix, are reportedly working to upgrade their Chinese factories to produce more advanced chips for use in AI data centers, Reuters reports. The move comes as the two companies continue to fight off competition from the fast-growing Chinese memory makers like CXMT. Fierce competition in the lucrative AI RAM market has already seen manufacturers slash consumer-focused production to allow them to increase production capacity for the more advanced — and money-spinning — components.

Citing four people familiar with the companies' plans, the report claims that Samsung Electronics aims to switch its Xian plant to the production of 286-layer flash chips by the end of the year. SK Hynix has its sights set a little lower, targeting chips with 240 or more layers at its Dalian facility. That factory was taken over back in 2021, but a timescale for the new upgrades isn't clear.

However, while Samsung Electronics and SK Hynix are well placed to deal with the growing threat from Chinese chipmakers, both are faced with additional complications in the form of U.S. regulations. Export controls on chipmaking equipment were applied in 2022, with the aim of slowing China's technological progress. Both companies, based in South Korea, must now get licenses in order to install U.S.-built hardware in Chinese factories. The report points to this as a reason for the recent growth of Chinese firms like Yangtze Memory Technologies Co. (YMTC). The company told investors at a recent IPO preparation meeting that it aims to become the world's largest NAND flash producer by the end of 2027.

While both Samsung Electronics and SK Hynix say that they are working in consultation with the U.S. authorities, there's little doubt that this extra step has hampered the companies' ability to upgrade their factories to better meet the new AI memory demand.

It's impossible to overstate just how key Samsung and SK Hynix are to NAND supply. Samsung's Xian factory produces around 40% of the company's global output. It currently produces chips that have around 200 layers, but Samsung's plans aim to boost that to 286 layers for V9 NAND chips. For its part, SK Hynix's Dalian plant currently produces chips with 192 layers, with the company's aim for 240-layer chips reportedly confirmed by three people familiar with the plans.

Meanwhile, CXMT, China's premier chipmaker, is looking to move beyond DRAM production. A report from September 2026 noted that it was eyeing production of 3D NAND memory for use in solid-state storage (SSD) products. The country's largest DRAM producer, CXMT, posted $22.41 billion in revenue and $11.57 billion in net profit in the first half of 2026 after years of losing money. But despite this purple patch, the company is still much smaller than the likes of Samsung, SK Hynix, and Micron.

Micron faces a one-day labor stoppage at its Taoyuan operations in Taiwan on October 22, Reuters reports. Micron's employees are striking for concrete terms for this year's bonus and a clearer mechanism for sharing the company's future profits. The strike's teeth come from the resultant financial impact on Micron's operations, as semiconductor fabs are supposed to operate around the clock. The scheduled protest comes amid strong demand for memory chips and will have a minor impact on Micron's memory output.

The Taoyuan union wants Micron to present a specific proposal for this year's additional employee bonus and establish a transparent formula for distributing a portion of future profits. Previous negotiations between the company and the union ended unsuccessfully in September, which prompted employees to approve industrial action in early October. Nonetheless, the union stresses that the October 22 strike is intended to pressure Micron into reaching an agreement rather than terminate negotiations. The union is prepared to conclude a deal if the company presents terms acceptable to employees across its Taiwanese operations.

The situation could become more serious if employees at Micron's Taichung operations, its largest manufacturing site in Taiwan, decide to join the action. A separate labor organization that represents workers at that facility is scheduled to meet with Micron for mediation on October 22, the same day as the Taoyuan protest. However, the Taichung union has not yet authorized a strike.

Micron's fabs in Taiwan produce commodity DDR5 and LPDDR as well as expensive high-bandwidth memory (HBM) for AI accelerators. Amid record demand for memory of all types, even a one-day suspension of operations would have a material impact on Micron's output and earnings.

Modern semiconductor fabs are supposed to work 24/7/365, as many processes cannot be halted. However, if management has sufficient time and personnel to prepare, a one-day warning strike does not necessarily mean a complete shutdown of Micron's Taoyuan manufacturing operations, not to mention permanent damage to wafers or equipment. The actual consequences of the strike will depend on employee participation, which manufacturing operations are affected, and Micron's contingency plans. While it is likely that the output will drop, the decline will likely be negligible.

Micron employs approximately 15,000 people in Taiwan. The workers point to compensation arrangements at Samsung Electronics and SK hynix as examples of how semiconductor manufacturers can distribute profits among employees as AI-driven demand generates unprecedented cash flows for memory firms.

What if you could buy a cheap used DDR5 SODIMM (laptop memory) kit and transform it into a super-fast DDR5 desktop kit? That’s what electronics hobbyist Blighted Agent recently did when they succeeded in converting a SK hynix 2x 16GB DDR5-5600 SODIMM kit they got from Facebook Marketplace for $120 into a 2x 16GB DDR5-7800 desktop kit, claimed to be worth around $1,000. They also had to buy some blank DDR5 desktop memory PCBs from AliExpress for around $16 each, and a set of heatsinks for around $18.

In the above video, our hero says they bought the donor laptop 2x 16GB DDR5-5600 sticks for just $120, which is a bargain. With extra bits and pieces from AliExpress (desktop DDR5 PCBs, etc.), the total bill of materials came to $175. Blighted Agent comments that the SODIMMs used what he believed to be SK hynix A-die modules, which are the same as the ICs used in expensive desktop DDR5 modules like the G.Skill Trident Royal line.

The process began with taking the memory ICs from the donor modules using a hot air station. Then they were cleaned and had 0.45mm leaded solder balls added, using a DDR5 stencil, reballing jig, and hot air. Next, the blank desktop DDR5 PCBs were prepared. A little solder was added to the plethora of BGA connectors to be ready for the memory chips to connect to.

The old DDR5 ICs and the new desktop modules could now be mated, using flux, the preheater, hot air, and watching and prodding carefully with a dental pick. Blighted Agent’s experience lets him know when the BGA chips have successfully mated with the PCB. You can eyeball when they pop precisely into place due to surface tension, and offer up a modicum of resistance to pick prodding.

Finally, the enthusiast added the SPD chip and BIOS chip from the SODIMMs to the new desktop DIMMs. These new desktop DIMMs were quickly tested in a PC before they were finished off with carefully applied thermal pads and the fancy-looking heatsinks.

Blighted Agent felt lucky that there were no issues with the newly created desktop modules. There’s a lot of intricate things that can go wrong during such a process. The initial boot verification showed them recognized in his Asus ROG Maximus Z790 Apex Encore motherboard as two “SK hynix 16,384MB 5600MHz” modules, which was correct. Some tuning resulted in rock-steady performance at DDR5-7800 CL38 and 1.40V. This was verified by stress testing for 90 minutes, which the enthusiast reckons was ample for a gaming PC. It is very likely a better result than using those mechanical SODIMM-to-DIMM converters you can buy, which can be problematic.

Blighted Agent seems to specialize in BGA soldering work, and has also successfully upgraded several graphics cards with double the VRAM. Though videos like this are edited to be brief, and they make the process look easy, the TechTuber admits there is a lot that can go wrong during this kind of rework. Moreover, with RAM modules, they lack the testing equipment to locate an issue with any particular IC on the PCB. So, if this module didn’t work, they might have ended up in a world of pain, not knowing which memory chip had an issue due to either an internal fault or a BGA soldering glitch.

Looking around at used DDR5 SODIMMs, it looks like Blighted Agent was very lucky to get a used working 32GB kit for $120. I just checked eBay U.S., and the best deal there was $320. Meanwhile, the best price for a new 32GB DDR5-6000 kit seems to be $449 at the time of writing.

We reported on Russian enthusiast VIK-on succeeding in a similar project earlier this year, but all their costing was in Rubles, and they went the extra mile in flashing custom firmware so the remade modules would be auto-detected with 6400 MT/s XMP support on most motherboards. In late 2026, DDR5 RAM continues to be too expensive.

Are you looking to buy RAM for an upgrade or an existing PC? You've no doubt seen the news about the extortionate price rises on RAM and storage, thanks to the ongoing AI boom ruining the component market for PC enthusiasts; well, today, we have some slight light in the darkness, with a $108 price cut on some DDR5 memory from Corsair. You can pick up 32GB of Corsair Vengeance RGB RAM (DDR5-5600) for $409 direct from Corsair. I've checked against our own price tracking info and used various other online resources to confirm that this is indeed the cheapest available to purchase memory kit with these speeds.

● Check out this deal at Corsair

This 32GB kit comprises two 16GB matched memory sticks, both with RGB lighting running along the spine of the heat shroud. The Corsair Vengeance RGB RAM is DDR5 with speeds of 5600 MT/s and a CAS latency of 40. This kit comes with Intel XMP profiles that can be selected in the BIOS.

We can't compare prices of RAM now to those of even a year ago. That's just unrealistic in the current AI economic climate, and whether you love or hate AI, it's not going anywhere soon; the rollouts of large data centers and manufacturers focusing resources on profit-heavy AI component production will continue for the foreseeable future.

There's no denying that RAM prices are tough right now. All the signs point to prices going up even further as scarcity becomes more of an issue for anyone wanting to build a PC in the next few years. If you're waiting for a fall in price, or the AI bubble to burst, you could still be waiting for up to a decade for memory and RAM production to normalize to anywhere near previous figures.

If you desperately need RAM now, this is one of the better prices on a 32GB kit. There are faster memory kits available, but you have to, of course, pay more for them, and the performance upgrades in most situations won't even be perceivable for the average user.

Elon Musk has criticized memory makers for what he calls 'extortionate' pricing amid an unprecedented shortage of both conventional DRAM and high-bandwidth memory (HBM). Although Musk did not identify the companies he criticized, his remarks seem to be directed at Samsung Electronics and SK hynix, as he praised Micron for its more 'reasonable' approach at the same time. Interestingly, Micron also enjoys exceptionally high profitability: its latest quarterly gross margin reached 81%.

"Micron has been reasonable regarding future memory prices, while others have been extortionate, which is something today's customers will not forget," Musk wrote in a post on X. "Micron is making the smart move for long-term customer loyalty."

Musk did not provide specific details of said extortionate pricing or disclose terms offered by different memory suppliers (which tend to be confidential). Consequently, it is impossible to determine whether Samsung and SK hynix charge substantially more than does Micron for comparable products. Nevertheless, Musk's remarks suggest considerable frustration with the pricing policies of South Korean memory manufacturers.

Over the past several quarters, memory has transformed from an easy-to-obtain commodity to a strategic asset, and makers of 3D NAND and DRAM have certainly benefitted massively from this shift. Historically, memory makers have responded to strong demand and rising prices with aggressive capacity expansions, which eventually led to oversupply and falling prices. This time around, however, manufacturers have raised memory prices severalfold without comparable increases in production capacity. As a result, supply still lags behind demand and will continue to do so for years to come, which puts further upward pressure on memory prices.

What makes Musk's praise of Micron particularly interesting is the company's financial performance, which clearly suggests that the company is taking advantage of the situation in the market. In its fourth quarter of fiscal 2026, Micron reported revenue of $54.23 billion and a GAAP gross margin of 81%, up from 40% a year earlier. The company's cloud memory unit earned $16.283 billion, and its non-GAAP gross margin totaled 83%; its core data center storage business sold goods worth $18.002 billion with a 90% gross margin; while sales of the automotive and embedded units totaled $6.824 billion with gross margins reaching 84%.

Perhaps the most surprising part of Micron's last quarter report was its mobile and client revenue of $13.114 billion and non-GAAP gross margin of 90%, which means that Micron earned higher profit selling memory and storage for client devices than it did for selling memory solutions for data centers. Such results clearly indicate that even supposedly reasonable memory prices can generate extraordinary profits in the current market.

Memory manufacturers are increasingly shifting toward long-term supply agreements (LTAs) that guarantee future supply and provide customers with predictable prices of DRAM, HBM, and NAND. So far, Micron has signed 26 strategic customer agreements that cover more than 35% of its expected revenue through 2030. These contracts include $32 billion in customer financial commitments, most of which consist of cash deposits. The company acknowledges that its new agreements reflect higher prevailing memory prices, and it by no means is trying to sell memory at a discount.

Samsung has reportedly secured long-term contracts covering 75% – 80% of its planned memory output in 2027, according to South Korea's ⁠Korea Economic Daily (via @Jukan05). SK hynix is reportedly pursuing similar arrangements as AI infrastructure investments continue to absorb available memory capacity.

Market insiders and analysts expect memory supply shortages to persist through at least 2028, and that gives manufacturers considerable leverage in contract negotiations. Memory suppliers have little incentive to reduce prices and are eager to enjoy their position, but Musk's warning suggests that today’s pricing policies could influence customer relationships once supply and demand eventually return to balance.

The AI-induced PC component shortage, which has caused drastic increases in the cost of DIY building, continues to get worse. Since last year, RAM prices have increased by more than 500% and show no sign of slowing down. In August, we reported that DDR5 6000 RAM — the sweet spot benchmark for both performance and pricing — had reached $400; now, the price is $450.

• Save by going slower: CORSAIR Vengeance RGB 32GB (2 x 16GB) DDR5 5200 - $399 at Newegg

As mentioned, because DDR5 6000 RAM is a de facto standard configuration and capacity in terms of performance, tracking the price of this particular spec has proven to be a strong barometer of the industry overall. While we track RAM prices across multiple models and kits, we also track the price of 32GB DDR5 6000 RAM daily.

We've been creeping closer to $450 for some time. As of today, the cheapest 32GB DDR5 6000 kit on the market costs $449.97, or three cents shy of $450. Cheaper RAM is still available; this 32GB DDR5 4800 kit is $399 at Corsair, but good, speedy RAM is now harder to buy than ever before. The 4800 Corsair kit once cost just $80.

As RAM prices and other component hikes have a knock-on effect on PC pricing as a whole, it was recently reported that PC shipments in 3Q26 have tumbled by a massive 20%, with the top three vendors shipping 11.6 million fewer units than the same period last year.

Combo deals remain a rare bright spot. Various Newegg bundles could save you as much as $358 when you buy RAM alongside a motherboard, CPU, and even an SSD, and we've seen a recent resurgence in stock on these.

Pre-builts also continue to offer some solace to wannabe DIY builders, with price hikes trickling down to systems more slowly. With industry figures warning that memory shortages could persist well into next year, or even last up to a decade, in the space of just 12 months RAM has gone from being a PC gaming commodity to a luxury few

CXMT expects to launch its first 4F² product, a server DDR5 RDIMM, by the end of the year, company president Cao Kanyu said in remarks reported by Yicai. The memory will be built on a denser cell layout, not yet commercialized, using vertical transistors to reduce the cell’s footprint by about one-third on paper. No speeds or capacities have been announced yet for the new product.

Cao spoke about the new RDIMM at the Integrated Chips and Chiplets Conference on Saturday. A 4F² cell is 2F by 2F at about two-thirds the area of current 6F² cells at the same feature size, and designs so far all stand the transistor up. The company has produced research and patent filings on the technology with papers in 2021, 2023, and 2025, and an 8Gb full-array research example was demonstrated at IEDM 2023.

Cao said CXMT’s version, the Vertical Surrounded Gate (VSG) transistor, has a channel that stands vertically with the gate wrapped around it, allowing stronger gate control with less leakage. Most importantly, standing the transistor up shrinks the cell. CXMT now has more than 300 published patent families tied to 4F², he added. The report says the industry as a whole is moving toward 4F² with 3D solutions that decouple DRAM and CMOS processes, combining them with wafer-level hybrid bonding, which allows logic and cell density to be optimized independently. Cao also covered CXMT’s own hybrid-bonding work, which began in 2019, with published patents.

Aside from this announcement, China’s primary DRAM maker has been in the news lately for its manufacturing and market-share gains. Its fifth-generation G5 DRAM technology platform, announced Sept. 20, is in mass production. TrendForce puts CXMT’s share of global DRAM revenue at 9.5% in the second quarter, up from 7.6% in the first, good for fourth place. Last November, CXMT showed off DDR5-8000 and LPDDR5X-10667. It has revealed itself as a manufacturer to be taken seriously by the biggest existing players.

Samsung showed off a 16Gb, 10nm-class 4F² DRAM design in its ISSCC 2026 paper in February. That one also used vertical-channel transistors (VCT), with the array bonded on top of the periphery using wafer-to-wafer hybrid copper bonding. The company claims the bonding raises dies per wafer by more than 20% with the same design rules. In April, The Elec reported that Samsung had a working 4F² VCT die on its sub-10nm “10a” process, with mass production targeted for 2028. Later South Korean reports clouded that date: the VCT version has since been split off as “D0a-V” with no timeline, and there is no firm timeline for adopting 4F².

SK hynix laid out plans at VLSI 2025 for a 4F² vertical-gate platform and 3D DRAM at nodes of 10nm and below, with circuitry bonded under the cell array. The April report also puts SK hynix’s 4F² debut at the 10b node, one step after Samsung’s 10a. Micron’s plans remain less clear, with no widely reported 2026 statement.

The announcement is perhaps more interesting for what wasn’t mentioned: capacity, speed, die density, process node, named customers, or intended volume. All we have is a date and a purported cell design, admittedly well-supported by the literature, but no product that has been tested by anyone outside of CXMT. Beyond Cao’s talk, CXMT hasn’t posted a release about the product in its Chinese or English newsrooms.

South Korean reports have said that CXMT’s initial products may only partly use 4F² and that producing stable units at volume is a separate challenge. With about 11 weeks left in the year, it will be interesting to see what CXMT actually delivers.

PC shipments globally have dropped by 20.1% year-over-year in the third quarter of 2026, a decline of 15.8 million units. According to research firm IDC Global, this marks a steeper decline compared to the 3.8% year-over-year decrease that the market experienced last quarter. It’s also down 9.1% from the second quarter of this year. Many research firms have been warning about this since late last year, with IDC warning that the PC market could shrink up to 9%, with the budget sector being hit the hardest. Some experts estimate that the situation isn’t expected to improve until 2029, with Tom’s Hardware readers saying that they won’t upgrade their systems in the next two years.

These price increases have been directly caused by the boom in AI data centers, with hyperscalers pouring massive amounts of money into the crucial HBM needed to support AI GPUs. This has led to memory manufacturers pivoting toward this technology, leaving less production capacity for consumer memory. One good example of this is Micron, which killed the Crucial RAM and SSD brand in late 2025 so that it can focus on data center production. As PC makers fight for a shrinking supply of memory chips, we saw memory prices climb by as much as 500%, with 128GB of DDR5 now costing as much as $3,399.

Manufacturers didn’t sit idly by and let the market take its course, though. Many of them stocked up on inventory in the second quarter of 2026 to try and head off the projected higher prices caused by the shortage, which directly led to the reduced shipments being reported. “What we’re seeing is the result of the strong first half pull-in. Vendors and channels loaded up on inventory early in the year to get ahead of price hikes, and that has thrown off the usual seasonality, where Q3 is typically larger than Q2,” said IDC consumer devices research director Jitesh Ubrani. “Channels are now worried about carrying too much inventory into a market where high prices are suppressing demand. That could translate into promotions and some short-term relief for consumers, but we don’t expect pricing anywhere near what it was a year ago. Prices will remain elevated. With macro conditions worsening, the risk is that the outlook for the next few quarters gets worse before it gets better.”

The top three PC vendors suffered the most, with Lenovo shedding 22.6%, HP shipping 30.9% fewer units, and Dell shipments contracting by 25%. On the other hand, Apple’s shipments shrank by 11.3%, while Asus’s numbers fell by 8.6%, with the rest of the market shipping 14% less year-over-year. Despite being hit the hardest, Lenovo, HP, and Dell still maintained their lead at 23.8%, 16.5%, and 12.1% market share, respectively.

Even though other industry leaders, including Micron, say that the situation will not improve for the next few years, Acer CEO Jason Chen went against the grain and said that these fears are just being hyped to protect the margins of memory chip makers. He estimated that PC prices will decline by the latter half of 2027 as Chinese memory chip capacity comes online, with only high-end parts like LPDDR5X-9600 and niche CPUs such as the Nvidia N1 and N1X remaining in short supply.

If you're in the market for a deal on DDR5 RAM during the Amazon Prime sales, Corsair might have the answer with a sale on 32GB of DDR5 5600 memory. Right now you can save $103 and grab this kit for $414.99.

• Check out this deal at Corsair

This is obviously a lot more expensive than the RAM prices from a year ago, but it's as good as it gets in today's market, with prices continuing to rise and showing no sign of letting up anytime soon. The cheapest DDR5 6000 kit — the sweet spot for AM5 gaming — is $437. For slightly more modest speeds, this is a decent saving, and the cheapest kit of this capacity and clock on the market. Crucially (pun not intended), this kit supports both AMD EXPO and Intel XMP, so will work with either platform for best speeds. If your rig runs with an Intel CPU, you can save $5 more with this kit.

There's no denying that RAM prices are tough right now. Unfortunately, all the signs point to things getting worse, rather than better, with some industry figures suggesting the RAM shortage could last an entire decade.

If you need RAM right now, either for a new build or to upgrade your existing system, then this is about as good as it gets.

Corsair is actually hosting a RAM sale across lots of its products, with savings of up to 30%. Prices remain high, but you can check out the whole sale here.

Best Tech and PC deals | Best gaming PC deals | Best RAM combo deals | Best 3D printer deals | Best RAM deals | Best gaming laptop deals | Best gaming monitor deals | Best Wi-Fi Router deals | Best GPU deals | Best SSD deals | Best hard drive HDD deals | Best CPU deals | Best gaming chair deals | Best PC building tool deals | Best PC peripherals deals | Best filament and resin deals | Best motherboard deals | Best CPU cooler deals | Best PC case deals | Best Dell and Alienware deals | Best USB charger deals | Best gaming and productivity laptop deals under $1,000 | Best laptop PC deals

Also, you can join the Tom's Hardware deals Discord for up-to-the-minute hardware deals.

A YouTube channel best known for its skillful graphics card fixes has published its first RAM module repair video. Tony from NorthWestRepair’s latest video shows his attempts to mend a pair of high-capacity DDR5 sticks worth a purported $16,000. It isn’t the repair skills that are newsworthy here. Rather, it’s the shift in economics that makes the chuck-it-and-replace-it attitude to bad RAM a philosophy that simply doesn’t apply in 2026. The impact of the AI-pocalypse means that spending a couple of hundred dollars on repair labor to save a several-thousand-dollar DDR5 DIMM is now sensible. If you can repair RAM, you can now start a business.

Two DDR5 sticks were sent in to Tony, described as having physical damage. They are both ECC sticks, meant for servers, one with 128GB and the other with 256GB of DRAM ICs onboard. Tony sounded happy at the start of the video, as this is an excuse to use his Unified DDR Flasher Main Board, for which he had just acquired an RDIMM extension that works with these server sticks.

Initial close physical inspection didn’t reveal any conclusive evidence of the source of the problems. So, it was hoped electrical tests would provide more clues. A data line tester didn’t highlight any issues, though. Tony used flux and hot air to reflow the solder on the first DIMM, which is a far simpler process than a reball (where all the memory ICs are taken off, cleaned, and given new solder balls). Initial signs were that the module was now working OK. So, he moved to the next DDR5 DIMM.

The second DIMM “may have a faulty PMIC chip,” which is why it seemed more severely broken than the first module, Tony indicated. Powering on a system with this DIMM inserted showed no signs of life, and the DIMM didn’t even warm up (thermal camera checks). That contrasts with the first fix.

Because this DIMM is completely dead, Tony did some work on the non-DRAM chips like the PMIC and SPD EEPROM first. Then he decided to reflow some other chips, including memory ICs, like before, while the board was warm. Some ICs were also reballed after inspection, making Tony suspicious of them.

The repairer found a short circuit via voltage injection and thermal camera monitoring. This was fixed with a new capacitor and by fixing the short on the damaged edge of the PCB. Finally, a new PMIC chip ended the quest, and this second DDR5 DIMM powered on and trained successfully.

The repair is good to see, saving these valuable components from e-waste. However, the bigger picture is that repairing memory modules could now be a viable business. Previously, it didn’t make sense to spend a hundred or two on labor to fix a DIMM that would cost about the same or even less to replace with a new one. Now the repair fee might be just a fraction of a replacement price.

Micron released its fiscal Q4 2026 financial results on Wednesday, expectedly setting another record for revenue with $54.23 billion for the quarter, up nearly five times since the same period last year. Micron also hit a record 87% gross margin, the largest contributor to which was Micron's Mobile and Client (consumer) business unit. Further, Micron's client business was the only one that shipped less memory last quarter, despite bringing in the highest operating margin at 88%.

Micron's margins overall are up significantly year-over-year; Core Data Center surged from 25% to 85%, and Automotive and Embedded have climbed from 20% to 79%. The Mobile and Client unit also saw significant growth, with a 29% operating margin in fiscal Q4 2025, and now a margin of 88%. Cloud Memory margins grew, though not to the same extent as other units, moving from 48% to 76%.

The gross margins are interesting to look at, too. In a financial statement, the gross margin equals revenue minus cost of goods. Operating margin, on the other hand, equals revenue minus cost of goods and all other operational expenses. The operating margin simply excludes taxes and interest.

The gap between gross and operating margin is what's interesting in the breakdown above. The Mobile and Client unit has the smallest gap, with only a 2% difference. The Core Data Center unit matches the Mobile and Client unit with a 90% gross margin, but it has a lower operating margin at 85%. In other words, the cost of running Micron's consumer business is extremely low relative to the amount of revenue it currently generates.

It also saw the lowest amount of growth for the quarter, with revenue up 14% quarter-over-quarter. Micron says this was "driven by higher pricing, partially offset by lower bit shipments." Out of Micron's four business units, the Mobile and Client unit was the only one that shipped less memory in the past quarter.

For clarity's sake, a bit shipment is just a shipment. Micron measures shipments in bits rather than units. It's the capacity Micron has shipped in a quarter, not the actual number of DRAM or NAND chips.

Outside of Mobile and Client, Micron attributes higher revenue to higher pricing and bit shipments. The situation in the Mobile and Client unit echoes a sentiment we've heard elsewhere: growth in the consumer market is still happening, but it's driven by higher pricing, not growth in shipments.

Earlier this year, Intel's David Zinsner, chief financial officer, attributed a 13% YoY growth in Intel's consumer business to higher average selling price (ASP), not increased unit sales. Zinsner clarified that Intel "thought we had seen some inflation on our cost and needed to pass that on to the end customer."

Micron's outlook for fiscal Q1 2027 has revenue set at another record of $61.5 billion ± $1.5 billion, with gross margin rounding from 87% in fiscal Q4 2026 to 86.25%.

Another record quarter signals more squeeze on the DRAM and NAND markets. Echoing rival SK hynix, Micron says it expects memory and storage to be "much tighter" in 2027 and 2028, claiming that the company expects the industry to be supply-constrained in both years. That's despite a growth in supply that Micron anticipates.

The company says it expects industry NAND bit shipments to grow in the mid-20% range, and DRAM bit shipments to grow in the low-20% range. The industry broadly will produce more memory over the next two years, says Micron, but that still won't keep pace with demand.

Worrying still is this line in Micron's earnings slides: "we do not have line of sight to when supply and demand will return to balance." However, the company says it plans to increase its capital expenditure (capex) in fiscal 2027 compared to its prior estimates.

A "majority" of that increase is set aside for construction of additional clean room space, which Micron has set for 2028 through the end of the decade. Hopefully, that additional clean room space coming online will ease supply constraints, but we're still a long way from that point.

Micron said during its FY 2026 earnings call that RAM and storage chip shortages will worsen in 2027 and 2028, even as it announced a record gross margin of 86.25%. CEO and chairperson Sanjay Mehrotra said that the company has already sold most of its capacity for next year and that customers will have to pay more compared to 2026.

“In calendar 2027 as well as 2028, we see demand exceeding supply. In fact, we see greater tightness in the industry in 2027 and in 2028 versus 2026. Overall, supply-demand environment is only getting tighter,” Mehrotra said. “We do not have line of sight to when supply and demand will return to balance.”

The memory and storage industry is not holding back on increasing production, though, with Micron saying that NAND and DRAM shipments are expected to grow in the low-to-mid 20s percentage range for the next two years. However, it seems that this is not enough to match growing demand, as it expects “the industry to remain supply constrained in both years.” Still, it seems that manufacturers are prioritizing HBM demand for AI data centers, with the company expecting shipments of these chips to grow faster than conventional DRAM.

Micron and other chip manufacturers are bringing new factories online to increase output, but it’s going to take years before they can start producing chips. But even as we’re amid an unprecedented multi-year memory chip shortage, Micron also announced record financial guidance. It forecasted a record $61.5 billion FQ1 revenue and a gross margin of 86.25%, implying a gross profit of more than $53 billion. After accounting for an estimated $2.06 billion in operating expenses and a tax rate of around 15.5%, the company said its earnings per share sit at $38.15, plus or minus $1.00, for approximately 1.15 billion shares.

These are record numbers, but it’s not surprising given the amount of money being poured into AI data centers. It has gotten to the point where the memory workers from Samsung and SK hynix have demanded and received bonuses worth hundreds of thousands of dollars, with Micron’s workers in Taiwan threatening to strike if they do not receive a bigger slice of the AI pie. While this is good news for the average employee from these big companies, it’s unfortunately bad news for the average person who must pay for RAM and storage at higher prices.

Micron’s prediction goes directly against the Acer CEO’s prediction that PC prices will decline by late 2027, especially as Chinese RAM chips enter the market and consumers simply refuse to pay more for expensive memory chips. We can only wait and see which of these CEOs will be correct when it comes to DRAM and NAND pricing.

A PC RAM maker has honored its guarantee promises despite the memory kit in question’s price rising eightfold since it was bought. This is news in 2026, as we’ve heard of so many companies dealing with AI-inflated component pricing refusing to replace items, instead refunding the original purchasing price despite the products now being worth many multiples of the original price. These glad tidings come via Redditor Double-South8863, who says their $150 G.Skill Trident Z5 Neo RGB 64GB DDR5-6000 RAM kit, now priced at $1,200 on Amazon, was back at full capacity after the company replaced the stick. They received the replacement within two weeks.

“I will never buy any RAM other than G.Skill for as long as I live,” pledged Double-South8863 on Reddit. They informed their fellow social media posters that one of the 64GB RAM kit’s sticks died at the beginning of September. After some A/B testing, they were sure one of the 32GB sticks was dead.

On September 8, about a week after the issue first reared its head, Double-South8863 decided to start an RMA process and get the dud G.Skill Trident Z5 Neo RGB 32GB DDR5-6000 stick replaced. They remember buying this highly desirable RAM kit online in May 2025 for the princely sum of $150. Now it is worth a king’s ransom at $1,200 on Amazon, and price tracker sites show it's even been as high as $1,300.

Perhaps the Redditor was aware of the reports of companies and their dastardly deeds regarding RMAs, as they are active on the PCMR subreddit. However, they optimistically went ahead and completed the RMA paperwork, then received instructions, including a shipping address to initiate the warranty exchange. Double-South8863 says they mailed the misbehaving memory module back to G.Skill on September 15. The Redditor’s post celebrating G.Skill’s customer service, proclaiming that they were now a “customer for life,” was published on September 26.

If you check the G.Skill site, you will note that this RAM-first firm still offers a limited lifetime warranty on all its popular RAM kits. Please note that, according to the official terms, this lifetime warranty “automatically terminates upon discontinuation or end-of-life ("EOL") designation of that specific model by G.Skill.” That means you shouldn't expect to swap out a faulty DDR5 module for a replacement for the whole of your natural life.

PC enthusiasts and DIYers are having a hard time right now as several key components required for performance builds are at all-time-high pricing. Meanwhile, those with a working setup pray that nothing will go wrong with the precious equipment they already have. Sadly, things do break, some components more than others. However, warranty obligations seem to have come under increased strain in recent months as consumer product scarcity means component makers can’t or won’t follow RMA norms that had been established for decades. Some of the worst cases we’ve seen involve PCs and component makers trying to refund the original (low) prices paid, substituting failed parts with non-equivalent parts, or even worse.

The maker of XMG gaming laptops and Schenker workstations said the prices for DDR5 SO-DIMMs have increased sixfold since July 2025, and it believes RAM will be in short supply through 2027 and beyond. The company said this in the r/XMG_gg subreddit, where the company also announced a price increase of $113 (€100) and $228 (€200) for most of its gaming laptop models, plus a massive $342 (€300) hike for one professional laptop.

This dramatic DDR5 SO-DIMM price jump tracks closely with desktop RAM, which experienced a similar 500% climb in the past 12 months. But what’s also concerning is that other components have increased in cost, too. Aside from RAM and SSDs, XMG noted that PCBs, electronic components, CPUs, graphics cards, and video memory are also facing similar cost pressures, resulting in higher costs. The war in the Middle East has compounded the situation, especially as increased oil and fuel prices are making air freight costs higher, while also increasing insurance premiums for sea cargo traveling from Asia to Europe via the Red Sea and the Suez Canal.

Because of this, the company says it was forced to increase the prices of several of its models. It also reminded customers that its margins are fixed and that the resulting hikes are solely driven by higher upstream costs. A company representative also said, “If relevant input prices fall again, we will reflect this in our retail prices as well — just as we have done in the past.” This is similar to Framework’s pricing strategy, where it recently cut the memory prices for the Laptop 13 Pro after it was able to find another source for cheaper LPCAMM2

The post also gave a bearish outlook on the memory situation, echoing Micron CEO Sanjay Mehrotra’s words that the DRAM shortages will go well into 2027. This contrasts with Asus CEO Jason Chen’s prediction that component prices will start reversing in the latter half of 2027, and that the long-term predictions of high memory costs are just chip makers wanting to retain high gross margins for as long as possible. Chen said that Chinese memory makers increasing their production would help ease the shortage and that price increases are reportedly cooling as consumers refuse to pay more. Unfortunately, we have no way of knowing which of these two perspectives is correct, and we can only wait and see what happens with memory prices over the next 12 months.

Memory prices are at record highs due to demand from the AI sector and are not going to drop any time soon. In fact, the cost of manufacturing memory chips on a per-area basis can be higher than the price of silicon processed using TSMC's N2 and N3 fabrication technologies, which are used to make compute chips, according to an observation made by Kurnal Insights. While the comparison has merit, it has an important caveat.

Based on media leaks, Kurnal from Kurnal Insights considers that a 300-mm wafer processed using TSMC's N3 technology costs $20,000, which translates to approximately $0.283 per mm² when the wafer price is divided by its area. For TSMC's N2, the analyst assumes a considerably higher wafer price of $30,000, or around $0.424/mm². These calculations are based on unofficial information and do not account for unusable wafer edges, dicing, test structures, defects, or yield, so they should be viewed as nominal wafer-area prices rather than the actual price of usable silicon.

The calculation for DRAM works differently. Kurnal assumes a DRAM price of $1.50 per Gb and then multiplies it by the bit density of different generations. At 0.219 Gb/mm², 1y DRAM works out to $0.329/mm², whereas 1z DRAM with its 0.273 Gb/mm² density reaches $0.410/mm². Finally, 1b DRAM at 0.436 Gb/mm² produces a figure of $0.654/mm², considerably higher than the nominal $0.424/mm² calculated for an N2 wafer.

There is an important distinction here. The N2 and N3 numbers represent assumed prices charged by TSMC for processing a wafer, whereas the DRAM figures represent the potential selling value of the memory contained within a square millimeter of silicon, thus illustrating how much revenue a DRAM maker can theoretically get from a given die area at the assumed memory price.

Interestingly, Kurnal Insights' $1.50/Gb assumption is almost exactly in line with the current spot price of DDR5 eTT memory. According to DRAMeXchange, 16Gb DDR5 eTT chips carried a session-average price of $24.80 on September 21, equivalent to $1.55/Gb. At that price, 1b DRAM with a density of 0.436 Gb/mm² would be valued at approximately $0.676/mm², just 3% above Kurnal's $0.654/mm² estimate.

It goes without saying that producing DDR5 memory is considerably cheaper than making logic chips using TSMC's N3 process technology. However, with DRAM in short supply, memory makers are getting considerably more money for their silicon than they did historically.

There are a few important caveats that make the comparison somewhat less straightforward. The calculations do not account for packaging costs, with logic requiring more expensive techniques. Additionally, TSMC manufactures chips on a contract basis, and the actual price of a processed wafer depends on the volumes, customer, and other commercial terms. Thus, comparing estimated TSMC wafer prices with DRAM spot prices is not exactly an apples-to-apples comparison. Even TrendForce notes that DDR5 spot procurement remains limited and transactions are sporadic, which means spot prices do not necessarily reflect the prices at which Micron, Samsung, and SK hynix sell the bulk of their DRAM.

Therefore, contract DRAM prices would provide a considerably better basis for an economically meaningful comparison. However, we do not know contract prices, and while they are clearly higher than historical memory prices, they may not be as high as spot prices. To that end, we cannot state for sure that DRAM makers get more money for their wafers than TSMC does for its logic wafers.

China's DRAM champion CXMT has begun mass production using its 5th-generation DRAM process technology.

CXMT says its new process technology — G5, as the company calls it — reduces DRAM’s active-area half-pitch to 11.95nm using quadruple-patterning lithography. The 11.95nm half-pitch corresponds to an active-area pitch of 23.9nm, something that puts this particular dimension roughly in the range of other advanced 10nm-class DRAM technologies. However, it cannot be directly translated into a conventional DRAM node designation. Separately, CXMT says its DRAM-optimized high-K metal gate (HKMG) process reduced the height of the core cell array to 6,762nm.

The company also says it modified its process flow and introduced unspecified new materials to enable storage capacitors with a depth-to-width aspect ratio of about 45:1.The figure is certainly difficult to compare directly with competing DRAM process technologies, but SK hynix says that capacitor aspect ratios will need to exceed 100:1 as DRAM critical dimensions eventually fall below 10nm.

A 45:1 aspect ratio means CXMT’s storage capacitors are 45 times deeper than they are wide, which is what enables the company to reduce DRAM cell area and fit more memory arrays onto a wafer and retail predictable capacity. However, increasingly high aspect ratios make etching, deposition, mechanical stability, and ultimately high-yield manufacturing considerably more challenging.

The first disclosed mass-produced devices using G5 are said to be 24Gb LPDDR5X devices, which have already entered mass production. The chips offer 50% more capacity than CXMT's previous comparable products and are available in two package formats for different mobile-device designs. According to the Chinese report, the 24Gb LPDDR5X products are already entering mainstream Chinese flagship smartphones.

A nanometer caveat?

Meanwhile, there are some important caveats.

First up, CXMT's 11.95nm figure represents the active-area half-pitch rather than a conventional process-node designation, so calling G5 a 12nm process is a large degree of simplification at best.

Secondly, the two revealed physical dimensions do not mean technological parity with the latest DRAM processes from Micron, Samsung, and SK hynix, as density, capacitor scaling, transistor characteristics, power consumption, and, arguably most importantly when it comes to commodities, yields matter.

Thirdly, CXMT says G5 provides at least 50% more gross dies per wafer than G4, but without actual numbers, this is obsolete. CXMT also did not disclose yields, which makes it impossible to determine the increase in productivity, not to mention known-good dies or the actual manufacturing cost per bit. Yet again, even a claimed 11.95-class DRAM node is an achievement.

Acer chairperson and CEO Jason Chen is expecting that prices for components will start reversing in the latter half of next year. According to DigiTimes, Chen told reporters that only high-end DDR5 parts like LPDDR5X-9600 and niche CPUs like Nvidia’s N1 and N1X chips are in short supply. Since supplier pricing lags consumer pricing by about a few months, he also added that PC prices will still rise between 5% and 20% towards the end of this year, plateau by the first half of 2027, before finally declining after years of AI-drive hikes.

The AI boom has driven shortages for various PC components, beginning with GPUs in late 2022, before expanding to memory chips by late 2025. This made memory prices climb 500% in 12 months, although the increases have seemingly cooled as consumers refuse to absorb further hikes. Some memory companies like SK hynix are saying that the shortage will be worse next year and that it won’t be until 2030 before pricing will start to normalize. The Adata chief even said that the DRAM shortage would last another 10 years. This is plausibly true, especially as HBM demand from AI hyperscalers remains strong, and the various memory chip fabs under construction aren’t expected to come online until the 2030s.

However, Chen disagreed with this take. He said that the major memory suppliers naturally want to keep their margins as high as possible for longer, “so they keep putting out the message: let me tell you, prices won’t come down until the year 20-whatever.” The Acer chairperson argued that there’s already ample memory and SSD supplies, while the purported CPU shortage is now limited to specific models. He also added that Chinese memory makers churning out cheaper alternatives would disrupt the market — something that SK Group Chairman Chey Tae-won feared. In fact, Acer, alongside HP and Asus, has started using CXMT chips in some of its products, while some Lenovo models sold in Germany were found to have YMTC SSDs.

Nevertheless, he says that price increases are becoming their own trend, saying that SSDs, PCBs, and fiberglass cloth used in motherboards are seeing their own hikes. “A lot of people come and tell us they want to raise prices, and we find it a bit baffling — this needs to go up, too?” Chen said to the reporters.

The overall tenor from Chen is good news, though, if computer manufacturers could finally lower prices after years of shortages and expensive parts.

A new report claims Chinese DRAM champion CXMT is eyeing production of 3D NAND memory. Reuters reports, citing three people familiar with the company's plans, that CXMT intends to build a 3D NAND R&D production line at its second manufacturing facility near Beijing. There is no information on when the experimental production line will become operational, though, given that CXMT's second Beijing fab has not even broken ground yet, the line is at least two or three years away. In addition, the memory maker has established a research institute in Beijing that has NAND flash development among its projects, according to one source. CXMT has not formally confirmed any 3D NAND initiatives, so the information should be taken with a grain of salt.

For now, there are no details on CXMT's 3D NAND architecture, number of active layers, process technology, expected performance, or production capacity. Nevertheless, the report claims that CXMT has already discussed its NAND ambitions with prospective customers. One of them is said to be a recently established company that plans to use CXMT-made NAND devices in storage products aimed at AI and supercomputing applications.

It remains to be seen whether CXMT's 3D NAND project will eventually progress to high-volume manufacturing, but if it does, the initiative will take CXMT beyond its traditional DRAM specialization and directly into YMTC's territory. Until recently, China's two major memory producers had focused exclusively on their 3D NAND and DRAM realms where they have achieved quite a success. Yet, it looks like both companies want to become one-stop shops for DRAM and NAND — just like their bigger rivals Micron, Samsung, and SK hynix — as YMTC is reportedly exploring DRAM production.

While CXMT's alleged plan to build 3D NAND may look somewhat logical from business diversification point of view, it does not make a lot of commercial sense for now.

Or China's industrial policy?

CXMT is China's dominant DRAM producer and posted $22.41 billion in revenue and $11.57 billion in net profit in the first half of the year after years of bleeding money. Despite obvious success, the company is still considerably smaller than the Big Three memory suppliers, which means it has plenty of room to expand in the industry where it already has experience, process technology, fabs, and customers. Furthermore, AI gives CXMT an obvious reason to focus resources on advanced DRAM as well as HBM3E, which are arguably much more strategically valuable products than commodity 3D NAND.

That said, for CXMT, allocating resources to 3D NAND, which requires completely different process technologies, manufacturing expertise, and equipment, does not make much economic sense. However, from the Chinese government's perspective, turning CXMT into the country's second major 3D NAND producer fits almost perfectly within its semiconductor self-sufficiency plans.

CXMT was created with Hefei government money (which held a 37% stake in the company during its IPO) and received support from China's Big Fund, which means that federal and local governments retain control over the company and may shape its strategic decisions, which is exactly what they do. Whether or not CXMT can indeed become a decent 3D NAND maker is an entirely different question.

The memory chip that makes a router remember how to be a router is a world away from the sleek GPUs that are attracting eye-popping investments and alarming valuations, as well as sending stock markets shooting upwards. They’re small, historically have been cheap, and are based on technology that has been around for years.

But despite being a world away from GPUs, the price of these often overlooked chips is skyrocketing, thanks to the all-encompassing memory price crisis caused by the AI boom.

While public and press attention has focused on the expensive chips, there’s an equally large impact beginning to be felt on older, less attractive memory chips. HBM is vital for AI accelerators, while DRAM and high-capacity NAND are being swallowed up by rapidly expanding data centres. A June report from Morgan Stanley reckons memory prices have risen more than sixfold over the last year, breaking with decades in which memory became steadily cheaper as production increased.

It’s not just HBM and DRAM that’s being affected. The crunch is also spreading down into much older forms of memory, including NOR flash and single-level cell, or SLC, NAND. Morgan Stanley expects NOR flash to remain undersupplied through 2026, while JPMorgan has warned its forecasts don’t fully capture a potential supply crunch in SLC NAND. The effects are already showing up in prices. TrendForce says contract prices for both NOR flash and SLC NAND rose by more than 100% during the first half of 2026, while it expects SLC NAND prices to rise another 120% to 170% in the second half of the year compared with the first half.

Picking winners

An increase in prices will have an impact on the tech we use day in, day out. NOR flash is commonly used to store boot and program code, and is a core part of automotive, industrial, and networking equipment. SLC NAND is deployed across a number of uses because of its reliability and endurance when placed in embedded hardware with long lifespans.

Both are vital. And both are being overlooked in favour of higher-margin chips — pushing the supply crunch to tech that previously never faced any issues. “The SLC NAND market is probably under a billion dollars a year,” said Jim Handy, a semiconductor and SSD analyst at Objective Analysis, in an interview with Tom’s Hardware Premium. That tiny scale adds up to a big problem, because it disincentivises any new investment.

“What you've got going on is a purely economic phenomenon,” said Handy. Hyperscalers and cloud providers are “all trying to outspend each other”, pouring unprecedented sums into semiconductors to build AI infrastructure. That willingness to spend big means the most profitable customers naturally move to the front of the queue.

Companies including Nvidia, Broadcom and Marvell need huge amounts of semiconductor manufacturing capacity for chips destined for AI systems. “They’re sucking up all of the wafers,” says Handy. “And then the companies who make NOR flash and SLC are having a hard time getting wafers to build their product, and so they have to raise prices.”

The problem is even starker in the NAND market. Bryan Ao, research manager at TrendForce, told Tom’s Hardware Premium in an interview that major NAND manufacturers, including Micron, Kioxia and SK Hynix, have been cutting the wafer capacity devoted to SLC because they can make considerably more money using it for newer NAND technologies. Ao estimates that a 12-inch wafer devoted to mainstream NAND can ultimately generate close to $20,000 in revenue. Use the same space to produce SLC and the figure is closer to $6,000 to $8,000.

Even if they wanted to, smaller SLC suppliers in China and Taiwan can’t just spin up new production. Lead times for some semiconductor manufacturing equipment have stretched to between 12 and 15 months, said Ao. The result is what he calls “severe undersupply”.

Big prices, big returns

BNP Paribas forecasts the average NAND price will hit $279.50 per terabyte during 2026, up from $73.10 in 2025. JPMorgan expects the memory shortage to persist for at least another two years, with customers getting just 70% to 80% of their orders fulfilled. TrendForce says manufacturers are shifting capacity towards advanced, higher-value memory products, with mature processes increasingly squeezed as a result.

There are some alternatives available. Kioxia says its serial SLC NAND is an alternative to NOR flash. But moving an existing industrial or networking product onto a different chip can itself require engineering work and qualification. Nor is there much incentive for memory manufacturers to fix the problem by building new SLC capacity – which means manufacturers are unlikely to invest billions in capacity whose useful market may disappear. That creates an unusual trap: there may not be enough demand to justify new factories, but there is still more demand than the shrinking supply can satisfy.

Hardware manufacturers can eat the higher component bill and accept lower margins, or pass it on. “We'll just have to either have lower margins, or we'll have to raise the prices to the consumer,” Handy said.

An ongoing issue

The problem is one that seems to have no solution – at least in the short term. Ao expects memory prices to remain high over the next five years and does not expect them to return to 2023 or 2024 levels. That broadly fits with the structural nature of the shortage identified by TrendForce, which says there are no significant capacity expansion plans for NOR flash or SLC NAND.

Handy sees one possible way out, but it is hardly reassuring. “As long as the race between the hyperscalers keeps up to spend, then it will continue to be an issue,” he said.

Handy compares the AI buildout to the internet infrastructure boom of the late 1990s. Rather than enough capacity eventually arriving to restore balance, he thinks spending may simply overshoot what the market can economically support.

“I'm expecting the same kind of a thing to happen here that we've got too many people spending too much money on AI, and not really making any return on it yet,” he said.

Until then, the least exciting memory chips in a computer may become some of the hardest to replace. Or, as Ao put it: “Pretty much we have to get used to this high price, no matter which segment of memory.”

We've talked about the RAMpocalypse extensively, but there's seemingly no end to the continuing rise in memory pricing at the moment. Luckily, Corsair is keeping its store stocked with some gamer-friendly Vengeance RAM, with a 32GB DDR5-6200 set for $419.99, or a slower option for $409.99, offering the best price on these kits in the current market.

● Check out this deal at Corsair

No, we're not talking record-low pricing here, but memory prices aren't a joke right now. AI is pushing them higher and higher, and after $400 for 32GB DDR5 was breached recently, you won't find better-priced DDR5 RAM elsewhere. You'll need a kit like this if you're planning a new gaming PC build or upgrade.

The Corsair Vengeance range continues to be a popular option among gamers, and while we've not given this particular kit a test, the similar spec'd Corsair Vengeance RGB DDR5-6000 C36 performs well. You're getting even faster RAM here, at 6,200 MT/s. It isn't the fastest, but this is priced right in the middle of slower kits that range from 4,800 to 5,600 MT/s, so you're at least getting better bang for your buck.

This particular kit comes with two 16GB modules, with those rated speeds of 6,200 MT/s. It's significantly faster than older DDR4 RAM modules, which typically cap out at 3,600 MT/s. It has CAS latency and memory timings of 36-46-46-100, comes in a black colorway, and has a solid aluminum heat spreader to keep things cool. 6,200 MT/s is a good speed for a gaming RAM kit, and while you can get faster, you'll typically pay more.

That said, every dollar counts when gaming PC builds can go for thousands more than they did last year. You can save $10 and get this DDR5-5600 Corsair Vengeance 32GB kit for $409.99. Like the DDR5-6200 model above, this has two 16GB modules, but with a slower speed of 5,600 MT/s, with CAS latency and memory timings of 40-40-40-77. It also comes with adjustable RGB lighting, a feature missing on the spec above, if you want a more colorful kit. You're probably better off spending the extra $10, but if you're building a mid-tier or budget PC, the speed difference isn't likely to matter as much, but any extra savings might.

The $419.99 price for this 32GB Corsair Vengeance DDR5-6200 RAM is the best price you'll find for RAM with these speeds and capacity, although you can go a little cheaper with the $409.99 DDR5-5600 kit instead. Corsair even has cheaper, and slower RAM, but these two offer the best value for performance that you'd expect for a DDR5 gaming PC build. You'll want to grab this deal while you can before the RAM prices inevitably go up even more.

PieceMakers, a Nanya-backed DRAM designer, began trading on Taiwan’s Emerging Stock Board on September 16 at a NT$740 reference price, Cnyes reported ahead of the debut. PieceMakers is not an HBM company. Instead, it bets that inference memory diverges from training memory, President Lee Hsiao-wen told Cnyes, and that DRAM stacked directly on the processor with hybrid bonding can sit between Nvidia’s SRAM-only Groq LPU and HBM. As it stands, design fees, not chips, carry the company's profit, with AI custom-design work accounting for around 40% of the company's revenue in the first half of 2026. Piecemakers Chairman Joseph Ting told TechNews that its first volume customer program will not contribute to the company's financials until 2027 at the earliest.

At roughly 60.4 million shares outstanding, that price values the company at around NT$44.7 billion (around $1.4 billion). Taiwan's Emerging Board is the Taipei Exchange's pre-listing market, not a main-board IPO, so shares trade through market makers ahead of any formal listing application. The stock ended its first session at NT$915, 23.6% above the NT$740 reference price, after opening at NT$1,035 and trading as high as NT$1,205.

Nanya Technology is the largest holder of Piecemakers, at 33.96%, after selling 715,000 shares at NT$740 to seed the float, a disposal it disclosed in a Sept. 9 exchange filing reported by Knews.

What PieceMakers sells

PieceMakers was founded in January 2006 in Hsinchu, Taiwan, led by chairman Joseph Ting and president Lee Hsiao-wen. Historically, the company has designed standard SDR/DDR DRAM and known-good-die (KGD) parts through representatives in China, Japan, France, Turkey, and Israel. Now, the company seeks to shift from direct product sales to custom design services, paid as non-recurring engineering (NRE) fees, and then to IP licensing, royalties, and turnkey production from 2027, the company said at its Sept. 7 briefing, UDN reported.

Revenue from the AI custom design unit has risen from around 4% in 2024 to almost 40% in the first half of 2026. The products behind that increase are HBLL (High Bandwidth, Low Latency RAM), a 2D die rated at 144 GB/s that was taped out in 2016 for Intel’s HPC line and published at ISSCC in 2017, and HiBaLL, the 3D-stacked version rated at more than 1 TB/s, the company claims.

The company described its customers to Cnyes as developers of cloud AI inference accelerators, international semiconductor players, and North American customers, with some programs in design and verification, and none named. Qualcomm CEO Cristiano Amon’s Computex keynote backdrop in June listed PieceMakers among Taiwan ecosystem partners, although neither company has defined the relationship. The takeaway is that the profit is in design fees and not chips. The margin curve matches a pre-royalty Non-Recurring Engineering (NRE) business, rather than a traditional memory vendor.

Why Nanya is chasing this instead of HBM

Nanya’s AI-memory strategy is custom and edge rather than HBM3E. PieceMakers is the first half of a strategy laid out in 2024. On Aug. 7, 2025, Nanya announced a joint venture with Etron Technology, a Hsinchu-based chip designer, capitalized at NT$500 million, with 80/20 ownership. The venture was envisioned to design custom high-bandwidth memory for edge AI devices rather than for data center accelerators. Nanya president Pei-Ing Lee said earlier in 2025 that the company would not compete in HBM3 or HBM3E, TrendForce reported.

Both halves of the strategy rely on Formosa Advanced Technologies, the Formosa Plastics Group’s test and assembly affiliate, for packaging. It is building the through-silicon-via (TSV) and die-stacking processes that both need. The surge in DRAM pricing has made commodity memory Nanya’s real business, which leaves PieceMakers a cheap side bet that has become a windfall. Nanya took advantage of this by selling around 3% of its stake in a move that suggests it is acting more as an investor than a parent building a memory stack.

The inference gap

Groq is an AI inference startup that Nvidia struck a $20 billion licensing-and-talent deal for on Dec. 24, 2025. Nvidia announced its first chip built from that, the Groq 3 LPU (language processing unit), Nvidia’s SRAM-based inference chip, at GTC, its annual developer conference, in San Jose earlier this year.

There is no HBM or DRAM on the Groq 3 LPU. Instead, it uses 512MB of SRAM on the die to deliver 150 TB/s of bandwidth against 22 TB/s from the 288GB of HBM4 on each Rubin GPU. It’s a decode-only co-processor with Rubin handling the prompt prefill, displacing Nvidia’s Rubin CPX from the roadmap.

At Hot Chips 2026, Nvidia’s Igor Arsovski, Groq’s former chief architect, said the rack is in production and published the first third-party benchmark: 3,431 tokens per second on a 100K-context, 31B-parameter model, at about four times the next-fastest public endpoint, in a single-request test that we noted isn’t directly comparable to the shared endpoints it was measured against. The cost is capacity: at 512MB per chip, a 256-LPU rack holds 128GB, with the model needing 62 chips at FP8 just to hold the benchmark weights. Nvidia accepted that trade for decode speed, which supports Lee’s point that the market leader’s newest inference product contains no HBM.

At Hot Chips, Samsung’s Sangwook Han laid out a three-phase HBM roadmap that ends in zHBM, which is DRAM stacked directly on top of the processor rather than beside it on an interposer. Samsung projects about 70% less I/O power usage than HBM5 with roughly 2.3x the bandwidth of a four-stack HBM4E system, with zHBM’s stacks limited to about four-high due to heat, at around 100W less. This would require wafer-on-wafer hybrid copper bonding and tight co-design between DRAM and SoC teams. SK hynix’s Jaesik Lee, VP of package engineering, said on Aug. 23 that hybrid bonding won’t be ready for HBM4E, leaving HBM5 as the earliest point. Counterpoint Research expects full-scale HBM production with the technique around 2029–2030.

PieceMakers offers a different version. Instead of the GPU-plus-HBM 2.5D layout, it bonds the DRAM stack directly onto the processor, wafer-on-wafer, with hybrid bonding instead of microbumps. This fits far more connections with the finer pitch, improving bandwidth, and the shorter path reduces both latency and power consumption. The company puts its wafer-on-wafer product at more than 2 TB/s per layer with latency under 20ns, the company figures, but the target is more capacity than SRAM at a lower cost and power than HBM. PieceMakers is not doing the TSV or hybrid bonding itself, as this is handled by the customer’s logic wafer foundry, Ting added. This custom service promises a 2027 date against Samsung's undated roadmap end and SK hynix's HBM5-at-the-earliest timing. Nvidia and Samsung have each, in their own way, settled the architecture question, with the open question being the customer.

Yield is the product

Lee also said that yield is the biggest hurdle to wafer-on-wafer mass production. The repair architecture has to be designed in, with testing before bonding, after bonding, and then after logic integration. Lee’s own example was 80% yield per layer, at which four layers come out at about 41% and eight at 17%. Our recently-published hybrid bonding state of play covers the process side in more detail.

This better puts into perspective why the company sells repair and known-good-die IP as much as it does bandwidth. It’s also why an IP-and-royalty model fits the strategy — yield IP is portable across customers while a bandwidth number is not.

What to watch

For PieceMakers, AI revenue remains primarily NRE until there is a first named customer, with the first volume program expected in 2027 at the earliest. Ting said that Nanya’s Q3 2026 results, which come in late October, will gauge the PieceMakers gain and reveal further financial information. SK hynix’s hybrid-bonding timing, which targets HBM5 at the earliest, is the current benchmark, although its 16- and 20-layer memory stacks are a separate problem from a few DRAM layers on a logic wafer. Qualcomm may also describe its relationship with PieceMakers more formally.

PieceMakers is likely to end up as an IP licensor with a small number of accelerator customers and turnkey volume through Nanya and Formosa Advanced Technologies. The technology risk is the foundry’s and the customer’s, which is why PieceMakers’ design-fee model works. PieceMakers is expected to benefit from a 2027–2028 ramp, later than Ting’s 2027. If the largest HBM maker won’t bond its own memory this way before HBM5, PieceMakers’ own 2027 date is the one it must meet.

Micron this week introduced its first 512GB DDR5-9200 memory module that is designed for servers used for applications that demand a lot of memory. The new modules — which are currently being validated by AMD and Intel with their next-generation server platforms — will enable server makers to build machines with up to 12TB of fast memory. What remains to be seen is the price of such modules and servers.

To build its 512GB DDR5 RDIMM, Micron uses advanced packaging that stacks multiple DRAM dies vertically and connects them using through-silicon vias (TSVs). The company does not disclose which memory devices and how many of them it uses, but claims that a single 512GB RDIMM consumes over 60% less operating power than four 128GB modules — based on 16.0W for one 512GB module compared with the 44.2W total for four 128GB modules — which suggests that we are dealing with fairly advanced ICs.

Micron's 512GB module is not the industry's first 512GB DDR5 RDIMM — that achievement belongs to Samsung — but it is certainly the industry's first 512GB module certified to operate with a 9200 MT/s data transfer rate with standard 1.1V voltage (which implies on usage of Micron's 16Gb DDR5-9200 devices made on its 1γ (1-gamma) fabrication process that uses EUV lithography and consumes 20% less power than predecessors, though we are speculating).

Truth to be told, 512GB DDR5 memory modules are rather niche products, which is perhaps why Samsung's 512GB RDIMMs formally introduced in 2021 have not become widespread even after AMD and Intel introduced processors with over 100 cores. Micron positions its 512GB DDR5 RDIMM primarily for servers running analytics, in-memory databases, simulations, virtualization, agentic AI, and other workloads demanding high-core-count processors and plenty of memory. As processors with 200 or more cores emerge, 512GB modules may become more relevant as 12TB of memory in a server running two 256-core CPUs means 24GB per core, which no longer looks particularly excessive for applications like in-memory databases, analytics, or caching.

Micron claims that in memory-constrained Spark Support Vector Machine (SVM) analytics workloads, systems featuring 512GB memory modules can provide up to 1.4 times the performance of configurations equipped with 256GB DDR5 modules, though the company does not disclose how much memory in total these systems use. Micron also says the higher-capacity memory can increase throughput and concurrency for memory-intensive database and caching applications such as RocksDB and Redis.

AMD and Intel are working with Micron to qualify the new modules for their upcoming server platforms. Micron plans to begin volume production of its 512GB DDR5 RDIMMs sometime in the second half of 2027 and intends to align the schedule with customer requirements.

One of the more pressing questions about Micron's 512GB DDR5-9200 memory modules is their price. A 256GB DDR5-6400 RDIMM currently retails for around $19,000. Given the unique proposition that 512GB modules have for memory-constrained applications, such modules can cost significantly more than 256GB memory sticks, which will not help their broad adoption.

We're seeing 32GB DDR5 RAM prices regularly push above $400 now. That's just where the market is, and as unfair as it might seem, the world is still turning, and people still need memory for their PC upgrades. Luckily, this TeamGroup T-Force Delta RAM deal drops the price to $389.99 at Newegg, as long as you use the coupon code LUYRF228 at checkout.

● Check out this deal on Newegg

Deals like this continue to be the best way to pick up new RAM as the ongoing global DRAM shortage, caused by the AI boom, rolls on. We're not going to see lower prices for RAM or SSDs any time soon. Deals like this aren't ground-breaking, and we're nowhere near record lows, but they're the best prices in a difficult market. Sans a time machine, or going second-hand, you won't find better pricing today than this.

As for this particular RAM kit, it's a good option for a mid-tier build. It's DDR5-5200, meaning speeds of 5,200 MT/s. That isn't the fastest RAM on the market, by any means, but it's certainly an upgrade over older DDR4 modules, which would usually see speeds of around 3,600 MT/s at best.

You're getting two 16GB DDR5 modules here, with CAS and memory timings of 40-40-40-76. This is perfectly fine memory for workstation and gaming use, with built-in RGB lighting to spice up your build. Yes, it won't be the fastest you've used. If you need to max out a build with the best speeds and lowest latency, you'll need to look for higher-end DDR5 memory instead.

Luckily, you have options there. The next best option with faster speeds is this alternative kit, also from Team Group, for $415.99. The Team Group T-Force Vulcan has CAS and memory timings of 38-46-46-84, with speeds of 6,400 MT/s. Much faster, so ideal for a higher-end rig, but it lacks the RGB lighting. That might be a trade-off you're willing to accept if you've got the extra $27.

Honestly? The best option here, if you do have the extra cash, is the T-Force Vulcan for $415.99. It's faster, only slightly more expensive, and it's still a bargain compared to rival kits that can go as high as $600 or $700 at the moment. That said, a new PC build or upgrade on a budget requires a few compromises, and unless you're pushing your PC to its limits, the Team Group T-Force Delta RAM kit for $389.99 is a solid option.

Either choice is a deal worth considering in this awfully expensive market that PC builders face at the moment. AI isn't going anywhere, and we're probably going to see prices this high, if not higher, for some time. Deals like these, even if they aren't world-beating, are still the best way to get RAM at the moment.

A computing enthusiast has shared images of a fat stack of DDR4 RAM sticks that they found at home. VastOption8705 told other tech fans on Reddit that they “found 10k worth of RAM sitting in my garage.” We count 30 sticks of DDR4-2666, and three sticks shown separately are all 64GB modules. If they are all 64GB modules, that number of sticks would add up to 1,920GB of RAM…

How did this huge amount of RAM end up in VastOption8705’s garage? The story goes that the Redditor was allowed to keep an old server from their workplace. Such 'generosity' isn’t unheard of, and it might have actually saved the company some recycling fees.

Is server DDR4 useful?

Numerous comments on the Reddit post jokingly pitch for RAM stick donations. But they might be barking up the wrong tree. Looking more closely at the sticks, where the labels are clearly readable, reveals that they are Samsung 64GB DDR4 ECC registered DIMMs (RDIMMs).

These kinds of RAM sticks are commonly used in servers built around Intel Xeon, AMD Epyc, or AMD Threadripper platforms. Sadly for their market value and the folks on Reddit hoping for some spare RAM, they aren’t consumer PC friendly. Even if you have a DDR4-supporting motherboard, these ECC RDIMMs will be both physically and electrically incompatible with your home creator/gaming PC.

Pricing and the Australia question

A quick poke around eBay U.S. listings shows that a single 64GB DDR4-2666 stick like those shown can be bought for between $350 and $425. So, we could roughly value the 30 sticks at $12,000 if a price of $400 per stick were achieved. The OP’s touted $10K valuation wasn’t far off. But if VastOption8705 lives in Australia, as they seem to, and guesstimated the value in Australian dollars, AU$10,000 currently equates to ~US$7,200 – quite low.

If you have spare RAM in your garage, don't share your address on public forums. The best I could find is a pair of 8GB DDR4 SO-DIMMs in my drawer. I also had some 30-pin SIMMs, SDRAM, PowerMac ROMs, and DDR3 modules probably worth just pennies, despite the RAMpocalypse.

The saga involving Chinese DRAM maker CXMT's alleged theft of Samsung's trade secrets is going strong. The South Korean court case already includes multiple convictions, two of which carry prison sentences for ex-Samsung engineers. The latest chapter is a doozy, though. Korean publication NoCut News spilled the chips on Project Hefei, a purported CXMT roadmap outlining long-term planning about said technology "acquisitions," personnel poaching, and production tape-out — all key pieces that may have directly led to CXMT's ascension to 10% of the global DRAM market.

According to leaked court documents, the prosecution says that Project Hefei was CXMT's entire DRAM development plan and was spearheaded by the firm's head of development (formerly Samsung's DRAM development lead), around August 2016 — not much longer after CXMT itself was created in June 2016.

In brief, the purported plan was to nab Samsung's Process Recipe Plan (PRP) by September 2016, poach key Samsung engineers by October 2016, have R&D complete in July 2017, and start making DRAM wafers by August 2018 at a rate of 10,000 a month. NoCut says the PRP dataset comprises 620 steps in DRAM manufacturing and includes data on equipment, consumables, and production methods.

The report states that in August 2016, CXMT first attempted to make wafers of 18nm chips by relying on the collective memories of the Samsung engineers it had hired away. Those recollections apparently proved insufficient, so after allegedly gaining illicit access to Samsung's PRP, CXMT prepared its own document in September 2016. The leaked data even included specific equipment suppliers and model numbers.

CXMT's "new" PRP was then handed out to key specialists, many of them ex-Samsung engineers, whom the prosecution says ought to have immediately recognized the data as originating from the Korean firm. The document apparently included notation and notes on process developments that were all unique to Samsung. A convicted ex-Samsung researcher with the surname Jeon, previously sentenced to 7 years in prison for manually copying parts of the PRP before leaving for CXMT, testified in this case as a witness.

The whole CXMT debacle has been playing out in South Korean courtrooms since January 2024 and is arguably far bigger than just "a company stole some tech from another." A decade ago, most of the DRAM market was taken by the Big Three: Samsung, Micron, and SK hynix. CXMT was created in June 2016 in Hefei (hence the project name), with a modest government investment of around $1.9 billion USD, allegedly with no R&D facilities whatsoever or any plan for research.

Going from zero facilities and institutional expertise to DRAM wafer production in little over two years would be an unprecedented feat, and presumably nigh impossible without the alleged IP theft; getting just the memory fab up and running usually takes two to four years, let alone any time for research. The firm claimed in 2019 that it designed its then-new 8 Gb DDR4 chips entirely in-house as a "leapfrog, independent" technology and began selling DRAM chips locally.

Then the AI locusts charged in and ate every chip on the planet. This demand resulted in explosive growth for CXMT, from an estimated 4% of the global DRAM market in Q2 2025 to around 10% in Q2 2016, marking the first time in over a decade that the Big Three held less than 90% of the pie.

Production capacity expanded to three 12" wafer fabrication facilities, expected to churn out a collective 350,000 wafers until the year is done — close to the same figure that Micron produces, of 375,000 to 385,000. CXMT is also planning to open a second fab in Beijing, aiming to produce over 600,000 wafers per month once it's online.

Furthermore, CXMT's gains aren't coming just from its DRAM market share. Revenue grew 716% in Q2 2026 alone, and its IPO on the Shanghai STAR Market in July 2026 saw its stock climb 466%, netting the firm a cool $8.6 billion USD and making it the most valuable chipmaker in the Chinese stock market.

About 70% of that money is reportedly going towards further expansion of DRAM production, rather than pricier, more complicated HBM. However, the firm has supplied HBM3E samples to Alibaba's T-Head and Cambricon, even as Samsung and SK hynix enter HBM4 production.

As of the South Korean prosecution's last tally in December 2025, Samsung's damages due to CXMT's alleged machinations ascended to "at least tens of trillions of won." A back-of-the-envelope extrapolation, considering quite a while has passed, might suggest a figure in the range of ₩40 trillion, or $29.5 billion, and rising exponentially.

The lasting impact on the memory market and technology in general is going well beyond plain number descriptors, though. All things considered, if the allegations are true, then CXMT's machinations resulted in a geopolitical-scale economic event. Dr. Evil would be proud.

The goal of next-generation HBM5 memory specification is to double performance and increase power efficiency compared to HBM4E, Samsung announced at the 'Memory Executive Summit,' an event that precedes 'Semicon Taiwan 2026.' Considering that it is barely realistic to double the data transfer rate of HBM4E in just one generation, the comment made by Samsung may imply that HBM5 will double the number of interface pins to boost bandwidth.

The goal of HBM5, which is currently under development, is to double the performance and improve the performance per watt by 20% compared to the HBM4E generation, according to Choi Jang-seok, the head of the product planning team of the memory business department of Samsung Electronics DS division. Previously, Samsung announced that its HBM5 memory stacks will feature a heat path block (HPB), which will reduce thermal resistance by 20% and simplify cooling of HBM5 modules.

Doubling HBM5’s per-stack memory bandwidth would result in peak bandwidth of around 4 TB/s per stack already in 2028 – 2029. TSMC expects AI accelerators to get to 20 – 24 HBM5/HBM5E per package configurations by the end of the decade, which means that these systems-in-packages will get a whopping 80 TB/s – 96 TB of memory bandwidth just several years down the road.

Although both DRAM makers like Micron, Samsung, or SK hynix as well as developers of HBM controllers and PHYs like Cadence, Rambus, or Synopsys already offer HBM4/HBM4E controllers and interfaces rated for 16 GT/s data transfer rates, the official JEDEC transfer rate for HBM4E will be around 12 GT/s.

If Samsung expects HBM5 to deliver twice the bandwidth of HBM4E, the HBM5 specification must either double the per-pin data transfer rate from 12 GT/s to 24 GT/s, double the interface width from 2,048 to 4,096 bits, or combine a wider interface with a higher data transfer rate. Increasing HBM5 memory stack interface width to 4,096 bits has so far been envisioned by KAIST and Marvell; however, this is certainly not an even semi-official confirmation of the specification's target.

From a performance-per-watt perspective*, widening the interface is generally easier than doubling the per-pin signaling rate. Higher per-pin speeds require faster drivers, receivers, clocks, equalization, tighter timing margins, and a more sophisticated PHY since maintaining signaling integrity at speeds well beyond 20 GT/s is not easy. But while a wider HBM interface moves more bits in parallel at a lower speed per wire, going from 2,048 to 4,096 pins means twice as many TSV/I/O paths, drivers, receivers, bumps, more complicated routing, and extremely complicated base die. So while a 4,096 I/O at moderate speed is probably best for pJ/bit, the interface/package complexity gets so extreme that it may offset the gains. Furthermore, such a wide interface Perhaps a 3,072-bit interface combined with a moderate increase in data transfer rate would be a reasonable engineering compromise, though engineers involved in JEDEC’s decision-making process may think otherwise. In any case, for now, any discussion of HBM5 specifications remains speculative.

Nonetheless, the target to double the bandwidth of HBM4E (2 TB/s per stack) within one generation is clearly a very aggressive one.

*It should be noted that achieving a 20% higher energy efficiency can be achieved not only by increasing performance, but by improving DRAM process technology, optimizing base die, lowering TSV I/O voltages, architectural changes, or power management.

The RAMpocalypse means that, unfortunately, memory has become one of the most expensive parts in a new gaming PC build or upgrade. The ongoing global DRAM shortage means that you're going to need to pick up deals as they pop up. They're not ground-breaking deals or record lows, but they're the best prices in the current market. That's where this PNY DDR5 offer comes in, bringing the price of 32GB DDR5 down to just $399.99.

● Check out this deal on Amazon

Believe it or not, this is where we're at with DDR5 RAM kits right now, and without a time machine (or buying second-hand), you're not going to find better pricing. This is the cheapest kit on sale at this spec and capacity, and after prices recently shot up past $400, it's a good offer to see it drop back below for the time being.

Our RAM price tracker shows how bad the market is for memory right now. You won't find a single option hitting below its record-low price floor, with many of the most popular models out of stock, too.

With this PNY kit, you're getting two 16GB DDR5 modules in this kit, capable of running at 5,600 MT/s, with CAS and memory timings of 46-46-46-90. This is high-performance RAM, suitable for gaming and workstation use. It isn't the fastest, but it'll do the job, as long as you're not looking to match the speeds (and higher prices) you'll find in higher-end DDR5 memory.

Unlike some of the RGB-packed options that gamers sometimes prefer, this PNY kit is pretty bare-bones as far as design goes. There's no RGB lighting at all, with just a black PCB finish and no heatspreaders. This is an install-and-forget kit that isn't meant to be flashy.

The $399.99 sale price for this PNY Performance DDR5 32GB memory is the real factor here: it's a price that simply can't be beaten right now. If you're building a new PC or upgrading your existing one, this PNY kit is a deal worth considering in the current market.

Samsung has unveiled a three-phase roadmap to progressively transform high-bandwidth memory (HBM) into an integrated memory-and-compute system, culminating in the company's zHBM architecture, which places the processor directly beneath the DRAM stack and eliminates the conventional 2.5D interposer link between the two. Detailing the roadmap at Hot Chips 2026, Samsung's Sangwook Han, of the company's DRAM design team, identified the base die as the key enabler of the evolution, which began with the company’s decision to manufacture the HBM base die on an advanced logic process.

In conventional HBM, the base die (B-die) was fabricated on the same DRAM process node as the core dies (C-dies) in the stack above. Starting with HBM4, Samsung moved the base die to a 4nm logic process, primarily to reduce power draw and minimize die area. Additionally, it gave Samsung a much more capable piece of silicon.

The company contends that a die built on the same class of logic process as XPUs could do much more than serve as a data interface. Samsung now plans to progressively offload more functions into the base die, eventually removing the physical gap between memory and the XPU entirely.

The current state of HBM and its growing constraints

The current HBM architecture comprises multiple DRAM core dies stacked vertically on a base die and connected through thousands of TSVs. The stack sits beside an XPU on an interposer, with the base die bridging the memory and compute silicon.

Bandwidth has been the main driver of HBM’s evolution. The current HBM4 stack has roughly 1 to 5 TB/s of bandwidth obtained through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each. These figures are expected to rise with upcoming HBM generations. The problem is that conventional ways of scaling bandwidth present significant challenges.

TSV signaling speed is difficult to increase, so HBM generations have added more TSVs instead. However, this consumes area and forces tighter TSV pitches. The PHY has also grown more demanding. HBM4 doubled the data I/O count from 1,024 to 2,048 DQs, and signaling speed keeps rising. Power is an even bigger issue. While energy per bit is improving, total HBM power continues to rise as bandwidth is scaling faster. Samsung says this is why HBM4 moves the base die to an advanced logic process, as the denser, more efficient logic reduces power draw.

This move underpins and enables the three-phase plan. An advanced logic node shrinks the interface circuitry while enabling the HBM base die to perform functions previously handled by the processor. Samsung calls this direction custom HBM, or cHBM, which keeps the conventional DRAM stack but customizes the logic underneath it for a specific accelerator.

Phase 1: Reclaim XPU area

The first phase is about handing processor area back to compute in what Samsung calls “XPU area reclamation.” AI accelerators are hitting familiar scaling walls, such as slowing process scaling and dies pressing against reticle and interposer limits. To expand compute, Samsung plans to evict non-compute blocks, moving their functions to the base die’s underutilized silicon.

The first target is the HBM Physical Interface (PHY), one of the largest blocks on the base die. Samsung proposes replacing the traditional interface with a much smaller die-to-die (D2D) link. On an 11 × 12.8mm HBM4 base die, the conventional PHY occupies more than 8 × 4mm, while the custom HBM D2D block is about 8.5 × 1.5mm, with channel depth cut from 5.5mm to 2mm. Because the matching interface on the XPU shrinks too, Samsung also reclaims processor silicon.

Conversely, shrinking the same power into less silicon increases power density and creates hotspots. Samsung’s answer is a Heat Path Block (HPB) that provides an alternative route for heat to exit the concentrated interface region. The company says an HPB covering more than half of the PHY can slash peak temperature by more than 35%.

The bigger Phase 1 change is moving the memory controller from the XPU to the custom HBM base die. Han estimated controllers account for 5 to 10% of an XPU's area — space that, refilled with compute, could yield a 10–20% performance gain. Moving the controller next to memory also enables a new SRAM-based repair scheme in which failed C-die addresses can be redirected to SRAM on the base die, avoiding the need to sacrifice an entire spare row or column for a single defective cell.

Phase 2: Making the die a more useful smart memory subsystem

Even with the controller moved in, Samsung says a substantial portion of the base-die area remains unused. Phase 2 fills that space with more functions, first with some relatively straightforward additions. The company proposes SoC-like telemetry and reliability features, including thermal, voltage, process, and aging sensors, as well as more advanced self-test hardware.

It also wants to use the edge of the base die for direct memory expansion, arguing that capacity is becoming as important as bandwidth. Dedicated controllers and PHYs could connect a secondary tier of external memory directly to custom HBM, rather than going through conventional PCIe expansion. Han said that extra memory could be LPDDR or even HBM, offering higher bandwidth and lower latency than PCIe-based memory extension.

Last in Phase 2 is compute — right on the base die. Samsung wants to place selected processing elements (PEs) under the DRAM, offloading memory-bound work while compute-heavy operations remain on the GPU. It calls this broader 2.5D architecture advanced HBM (aHBM), citing benefits such as less traffic across the interposer and reduced latency and I/O power draw.

Phase 3: zHBM goes fully 3D, placing the processor underneath the memory

Phase 3 appears to be Samsung's most radical step, with the company halting HBM architecture optimization and rebuilding it instead. Introducing zHBM, Samsung's “ultimate solution” for maximizing bandwidth under future AI's brutal power limits.

The zHBM concept eliminates the conventional side-by-side arrangement of XPU and HBM across an interposer. Instead, the processor sits directly beneath the DRAM stack in a true 3D structure. This architecture allows Samsung to replace the large edge PHY with distributed I/Os spread across the die. Data no longer has to travel laterally across an interposer, thereby shortening the physical path and eliminating the need for conventional HBM PHY and D2D link interfaces.

Samsung says the biggest payoff is power. Its projections show zHBM cutting I/O power by around 70% compared with HBM5. In another example, Samsung models roughly 2.3X more DRAM bandwidth while reducing memory power by about 100W compared to a four-stack HBM4E system.

On the flip side, thermals are the obvious complication. Han said Samsung is targeting roughly four-high zHBM stacks, compared with the much taller 12-high or 16-high configurations possible with conventional HBM, specifically because of heat. Distributed I/O helps by spreading the circuitry rather than concentrating it into hotspots, but zHBM is a balancing act involving capacity, bandwidth, heat, and physical integration.

Manufacturing zHBM will also require advanced wafer-on-wafer bonding and hybrid copper bonding to meet the required I/O density, with a much tighter co-design process between the DRAM and SoC teams. Samsung did not provide a firm launch date or timeline for the phases. However, HBM4’s 4nm logic base die is the concrete starting point, while cHBM and aHBM are nearer-term extensions, with zHBM as the long-term endpoint.

China's DRAM champion ChangXin Memory Technologies (CXMT) has started risk production of HBM3E memory, The Information reports. Although CXMT remains a generation behind the big three memory manufacturers, which are mass producing HBM4, it goes without saying that reaching the HBM3E milestone highlights the company's rapid technological progress.

Specifications of CXMT's HBM3E products are unknown, though keeping in mind that we are dealing with risk production, specifications of actual HBM3E products from CXMT may differ from risk production samples. Meanwhile, general JEDEC specifications are well known: HBM3E modules feature a 1,024-bit-wide memory interface, supports data transfer rates up to 9.6 GT/s per pin, and can stack 8 or 12 memory devices. Depending on the exact speed bins, HBM3E can provide up to 1.228 TB/s of memory bandwidth.

Capacity of actual memory stacks depends on the number of DRAM dies used in that stack: HBM3E products can offer 24GB of capacity using an eight-die stack or 36GB using a 12-die stack when built with 24Gb DRAM devices.

Several Chinese developers of advanced processors are already evaluating CXMT's HBM3E with their processors, including Alibaba Group's T-Head and Cambricon Technologies, according to the report. If testing and qualification proceed as planned, these companies could begin using CXMT's HBM3E in commercial products as early as next year.

Since every HBM package requires multiple large DRAM dies, growing HBM output could consume considerable DRAM manufacturing capacity, which is when CXMT's aggressive capacity expansion will be useful.

CXMT's manufacturing of HBM3E is important for multiple reasons and arguably the HBM3E generation itself matters less than CXMT's ability to manufacture usable HBM at all.

Firstly, HBM is one of the critical components of modern AI accelerators, so if CXMT's HBM3E qualifies with processors from Cambricon, T-Head, and other Chinese designers, China becomes less dependent on Micron, Samsung, and SK hynix for building high-performance AI hardware.

Secondly, despite being a generation behind HBM4, HBM3E is still very capable memory and can provide several TB/s of bandwidth, sufficient for powerful AI accelerators. In fact, many Chinese developers of AI accelerators do not necessarily need HBM4/HBM4E to build useful AI systems.

Thirdly, HBM is substantially harder than making ordinary DRAM. CXMT needs not only competitive DRAM dies, but also high-yield stacking, through silicon vias (TSVs), very fine interconnects, thermal management, packaging, and testing. Reaching HBM3E risk production proves that China's memory ecosystem is advancing beyond simply manufacturing commodity DRAM.

Finally, there is also an important geopolitical angle. Export restrictions constrain China's access to advanced AI processors and HBM, so a combination of Chinese-designed accelerators, CXMT HBM3E, and advanced domestic packaging indicates that China becomes one step closer to semiconductor self-sufficiency.

ChangXin Memory Technologies (CXMT) has announced in a social media post that it has started mass production of LPDDR6 memory for a Xiaomi smartphone, Reuters reports. This is not entirely unexpected given the general LPDDR6 mass-production timeline, but the announcement is still surprising because two China-based companies are ahead of industry announcements. Yet, there are caveats.

LPDDR6 is perhaps the most substantial upgrade to the GDDR-class memory ever. Firstly, it uses PAM3 signaling, which encodes 3 bits of information across two symbols, compared with the NRZ signaling used by LPDDR5/LPDDR5X. Second, the data transfer rate increases to 43.2 GT/s. Third, the reduced I/O width from 32 bits to 24 bits requires rework at both the hardware and software levels.

Given the differences between LPDDR5 and LPDDR6, the most important factor here is not exactly LPDDR6 manufacturing, but a broader view.

On the one hand, CXMT reached mass production of LPDDR6 roughly at the same time as the established DRAM leaders, meaning it is on par with them, if not ahead. This marks a substantial change from earlier generations, when Chinese DRAM technology generally lagged considerably behind Samsung, SK hynix, and Micron.

On the other hand, reaching mass production does not necessarily mean that CXMT has achieved full technological or manufacturing parity with its larger rivals. The official announcement covers only one smartphone maker and one model, meaning CXMT's LPDD6 still has to pass validation for other handsets and other makers.

Still, the significance of CXMT's announcement is hard to understate. CXMT is no longer merely catching up by introducing a new memory generation years after its international competitors. With LPDDR6, CXMT is entering the market during the standard's initial commercialization, which means the technology gap between China's leading DRAM producer and the industry's established players has narrowed considerably.

Which brings us to the question of whether CXMT can maintain this pace. Developing a competitive LPDDR6 device is one thing, producing it at high yields and in sufficient volumes to supply major customers is another. For now, we are talking about a niche smartphone with memory operating at undisclosed performance.

If CXMT can mass-produce LPDDR6 for the whole market and manufacturers, we may well have seen the change of the industry leader. Yet, given one niche device, we certainly cannot say so for now.

China's leading DRAM producer ChangXin Memory Technologies (CXMT) has filed a lawsuit against the U.S. Department of Defense in an attempt to overturn its classification as a company linked to China's military, Reuters reports. CXMT claims that it has no connection to the Chinese People's Liberation Army, and argues that the Pentagon's decision lacks supporting evidence, violated due-process requirements, and has damaged both its business and reputation.

The Pentagon initially classified CXMT as a Chinese military company in January 2025, when Joe Biden was the president. The Trump administration subsequently maintained the designation when the Defense Department updated the list in June. CXMT says it spent more than a year supplying information to the Defense Department in an attempt to overturn the classification and remove itself from the list.

The company claims the DoD published a notice in February indicating that CXMT would be taken off the list but withdrew that notice later the same day without any explanation. In June, the Pentagon classified CXMT as 'directly affiliated with MIIT and indirectly affiliated with SASAC and MIIT.' MIIT is China's Ministry of Industry and Information Technology, whereas SASAC is the State-owned Assets Supervision and Administration Commission of the State Council, an organization that formally owns the government's stakes in non-financial state-owned enterprises.

While CXMT memory can certainly be found in systems used by the PLA or China's secret services, this does not automatically make CXMT a direct supplier to these entities and therefore does not prove that CXMT is a Chinese military company.

CXMT points out the Pentagon's original motivation to include the DRAM maker in its list was a remarkably weak-looking 'military grade' argument. According to the complaint, DoD's 2024 report said CXMT contributed to China's defense industrial base partly because its DRAM is dual-use and cited an advertisement describing CXMT products as 'military grade.' CXMT says that advertisement came from an unauthorized distributor, which later admitted the characterization was erroneous.

In addition, CXMT claims that its DRAM products conform to JEDEC commercial standards and lack the requirements imposed on Chinese military-grade semiconductor components involving areas such as temperature, packaging, testing, and military oversight. Also, it says that should its products be made in the U.S., they would be classified as for 'purely civilian uses' and that it 'does not hold any licenses to manufacture products for military use.'

Inclusion on the Pentagon's list of companies linked to the Chinese military can result in restrictions involving U.S. government contracts, something that CXMT barely seeks. But more importantly, it can affect a company's commercial relationships (as many companies do not want to be affiliated with companies linked to the Chinese military) and reputation. Indeed, CXMT claims that since January 2025 the designation has continuously hurt it commercially and reputationally, and that the lawsuit is intended to protect its business interests.

The ongoing DRAM crisis has led to a sharp increase in laptop prices, with manufacturers facing exponentially high component costs, particularly memory and SSDs. The situation has created a growing gap in the affordable gaming laptop segment, with most entry-level models becoming increasingly expensive. In its response, MSI has introduced the new Katana 15 HX C14 that features Intel’s 14th-gen Raptor Lake Refresh processors along with support for both DDR5 and DDR4-3200 memory.

Depending on the region, MSI will be offering the value-focused gaming laptop in two variants, featuring dual SO-DIMM slots with either DDR4 or DDR5 compatibility. For context, a 32GB (2x16GB) DDR4-3200 SO-DIMM memory kit can be purchased for around $200, while a DDR5-6000 kit goes for over $400. MSI did not specify the DDR4 capacity as standard, only that the laptop supports up to 96GB, which seems unlikely given no 48GB DDR4 SO-DIMMs exist.

Configurable with up to a 24-core Intel Core i9-14900HX processor, the laptop should offer plenty of CPU performance for demanding tasks besides gaming. It will be available with up to an Nvidia RTX 5070 laptop GPU offering support for the latest AI features, GDDR7 memory, DLSS 4.5, and real-time ray tracing. MSI claims that the Katana 15 HX C14 is tuned for up to 170W of combined CPU and GPU power, while the cooling system with dual fans, three heat pipes, and four exhaust outlets helps in sustained performance. There are also dual-PCIe Gen 4x4 M.2 slots, allowing gamers to add a separate SSD dedicated to their gaming library.

Display options include a 15.6-inch IPS panel available with either QHD (2560x1440) resolution that supports up to a 165 Hz refresh rate or FHD (1920x1080) resolution with up to a 144 Hz refresh rate. In terms of design, the laptop comes in a stealthy black finish with textured slash patterns inspired by traditional Japanese blades along with bright red logos. The chassis measures 22.9mm in terms of thickness and weighs 4.62 pounds, making it fairly compact for a 15-inch gaming notebook.

Other notable features include support for Wi-Fi 6E and Bluetooth 5.4, a 4-Zone RGB gaming keyboard with 1.7mm key travel, a 240W power adapter, USB Type-C with Power Delivery 3.0, a 60Whr battery, and DTS-enhanced dual 2W speakers. According to MSI, the new Katana 15 HX C14 will be available globally, although there's no pricing information at the moment.

High-bandwidth memory (HBM) is one of the key components of AI systems that is not currently assembled in the U.S., but this is going to change in 2029, when SK hynix initiates packaging of HBM memory modules at its facility in Indiana. This week, the company held a groundbreaking ceremony for its HBM production base in America and intends to start construction of the plant shortly.

SK hynix's HBM production site in West Lafayette, Indiana, will specialize in advanced packaging, testing, and R&D of HBM. The facility is set to cost the company around $4 billion, which highlights its advanced technology capabilities as well as vast capacity. The DRAM maker expects to open the cleanroom by October 2028 and begin volume production of next-generation HBM in the second half of 2029, which is about a year later than originally envisioned. Once commercial operations kick off, SK hynix expects the Indiana site to employ around 1,000 people.

Despite being described as an HBM production base, the Indiana site will not manufacture the DRAM wafers, but will package HBM stacks using DRAM wafers produced in South Korea and base dies produced in South Korea, Taiwan, or the U.S. Nonetheless, SK hynix intends to market the resulting devices as its first U.S.-made next-generation HBM products. Meanwhile, as custom HBM-class memory gains traction in the second half of the decade, assembling such stacks close to American customers may be particularly important both for SK hynix and its clients, as it enables SK hynix to shrink the feedback loop significantly.

In addition to building the advanced packaging and testing plant, SK hynix will also establish an Advanced Packaging R&D Testbed next to the manufacturing lines. The facility will enable SK hynix to work with customers, universities, and commercial partners on future packaging technologies, build prototypes, and quickly validate their performance and manufacturability in an actual production environment. In the era of customized HBM, such a facility could become a significant competitive advantage for SK hynix.

SK hynix also signed a memorandum of understanding with Purdue University to jointly research system integration and advanced packaging technologies, including HBM.

"The United States is the epicenter of AI innovation, bringing together premier customers, top-tier R&D capabilities, and partners and Indiana fab will become a gateway to deliver first Made in USA HBM products," said Kwak Noh-Jung, CEO of SK hynix. "We will expand our investments and collaboration in the U.S., grow together, and become the most trusted partner in shaping the future of AI in America."

When it comes to building a new PC, memory has seen the sharpest rise in pricing in years. Now, you have to seriously consider the cost of the RAM kit in your build, and especially for those stepping up from a DDR4 platform, whether the cost is worth it for the extra performance. Currently, the prices continue to rise with no end in sight. It's hard to suggest holding off on upgrading now, as we have no clue when the prices will start to fall - if at all. However, if you are looking for a brand new pair of DDR5-6000 RAM sticks for a desktop PC, then Corsair's Vengeance 32GB DDR5-6000 kit has just received a $215 discount that brings the price down to $401.99, from its $616.99 list price. This makes it the cheapest 32GB DDR5-6000 kit that you can purchase today.

● Check out this deal at Corsair

The kit includes two 16GB DDR5 modules that run at 6000 MT/s with a CAS latency of CL36 and further timings of 38-38-76. Corsair's Vengeance kits are a popular choice among PC building enthusiasts and feature black aluminum patterned heat spreaders with RGB lighting running across the spine of the sticks. They come with Intel XMP BIOS profiles for preconfigured overclocking.

Prices of memory, especially DDR5 kits, are very off-putting at the moment, and looking at upgrading can feel the same. With current-gen game consoles going up in price, expectations for next-gen consoles are that the prices will stretch over a thousand dollars. So if you're thinking of getting a new gaming PC or upgrading from an older DDR4-based system, it's probably best not to wait around. Just be prepared for some hurt to the bank account. Industry figures say the memory shortage could last for years or even a decade, with no relief at all in sight; prices are much likelier to go up rather than down.

Nvidia's NVLink Fusion program gives the company's partners the building blocks necessary to connect custom chips with the NVLink scale-up domain used to join many separate processors into a single coherent system like the Vera Rubin NVL72 rack-scale accelerator. Today, Nvidia is adding a new building block to that toolkit: NVHBM, a custom implementation of the high-bandwidth memory that underpins practically every AI accelerator in use today.

As Nvidia describes it, NVHBM is a custom HBM base die that promises higher bandwidth, lower power usage, and a smaller on-die footprint than traditional HBM4e. Nvidia says it's designed and validated with "leading memory vendors," so it promises custom silicon developers faster time-to-market than implementing commodity HBM from the ground up. But it's worth re-emphasizing that this isn't an HBM replacement. Instead, it's a new building block that Nvidia is only offering to its custom silicon partners.

Memory bandwidth is everything for AI accelerators, and NVHBM promises up to 30% higher bandwidth per stack than standard HBM4e. For memory-bandwidth-bound AI workloads, that higher bandwidth translates into higher throughput, such as a higher tokens-per-second rate for AI inference.

The custom NVHBM base die also reduces the footprint of memory-related circuitry on the main custom accelerator die. Traditionally, the HBM memory controller has been incorporated into the primary silicon die on the package. NVHBM instead moves the memory controller into the base die of the HBM stack and provides a smaller custom PHY that NVLink Fusion customers can then integrate into their designs.

Nvidia says this approach frees up precious package real estate that can then be used for additional compute die area — up to 30% more compute on the primary silicon die. NVHBM further promises to simplify the interposer routing used to join multiple chips together for designs using advanced packaging techniques.

NVHBM also provides power savings versus off-the-shelf HBM4e stacks. As Nvidia has continuously hammered home in the Vera Rubin roll-out, every watt that isn't going into token production is a watt wasted. Nvidia says NVHBM uses 15% less power than commodity HBM4e, and that power savings can be banked for performance-per-watt improvements, reallocated into more functional units for a custom accelerator design, or translated into higher sustained performance within the same power budget.

Higher bandwidth at lower power is a huge win for AI accelerators that are moving massive data structures like model weights and KV caches around, especially when those savings are multiplied across many thousands of chips. The energy saved on data movement can be plowed back into higher performance from the accelerator itself or reallocated to support larger numbers of accelerators within the same fixed power envelope.

But these are, as of now, reasons for Nvidia's prospective partners to consider incorporating NVLink Fusion and NVHBM into their custom designs, not benefits that will materialize in the Rubin rack-scale systems already in production.

Along with NVHBM itself, Nvidia announced that Amazon's Annapurna Labs will be its first partner on NVHBM. , and Annapurna VP Nafea Bshara says: “We look forward to this technology collaboration to benefit future AWS infrastructure designs.” Annapurna's next-generation Trainium 4 AI chips will already support the NVLink Fusion scale-up interface, so it seems likely that follow-on chips will support NVHBM, too.

d-Matrix presented Raptor, which it calls the first 3D DRAM accelerator for generative inference, at Hot Chips 2026 this week, showing a TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed DRAM die that delivers 100 TB/s of bandwidth from 32GB per card.

Co-founder and CTO Sudeep Bhoja put the vertical interface's energy cost at 0.37 pJ/bit against roughly 2.4 pJ/bit for moving data into an HBM4 base die, calling it "a measured number" from working silicon, and the accompanying ISCA 2026 paper, written with the University of British Columbia, projects around 4.7 times higher throughput per card than HBM-based designs. Bhoja, however, didn't disclose who manufactures the DRAM die.

CEO Sid Sheth told CNBC in June that Raptor is slated to launch in 2027, but at Hot Chips the company gave no firm date or information on volume and pricing, and every performance figure shown, including 988 tokens per second per user on the 2.8-trillion-parameter Kimi K3 model at 1M-token context, is a d-Matrix projection built on early silicon.

The custom DRAM die

Raptor inverts the usual 3D stacking arrangement by putting the logic die on top and the DRAM underneath, so a cold plate sits directly on the compute silicon and the DRAM die doubles as the interposer, carrying PCIe and die-to-die signals down through its TSVs. "For the same amount of power, you can drive the bandwidth up," Bhoja said during the session, "and so we were able to drive the bandwidth up here to 100 terabytes per second."

The one-high stack achieves a power density of roughly 0.5W per square millimeter, which liquid cooling can handle, but the DRAM is designed for a junction temperature of 105°C, where retention collapses from a standard 32ms to 4ms, and the memory must refresh eight times more often. d-Matrix absorbed that penalty by shrinking each microbank to 1,366 rows and about 5.33MB, so a full refresh sweep costs only 1.37% of overall bandwidth.

The die carries 840 banks per chiplet, of which 72 (around 9%) are spares wired into a two-level mux chain the company calls bank chaining, letting any two failed banks anywhere on the die be switched out while channels stay symmetric. A [132,128] Reed-Solomon code on the logic die corrects two symbol errors per 128 bytes, with a CRC behind it. The interface has no PHY, no burst structure, and no sideband pins, so conventional data-bus inversion was impossible; d-Matrix instead compares each 128-byte flit to the previous one and stores a 1-bit inversion tag alongside the ECC metadata, recovering roughly 20% of the I/O power DBI would have saved. At full tilt, the vertical interface still burns 296W of the 422W per-package budget the ISCA paper discloses.

The bank geometry, spare-bank mux tree, refresh behavior, and interleaved ECC columns were all co-designed with the compute die. The 0.37 pJ/bit figure exists only because of that pairing, and no memory maker has anything like this die in its catalog.

Who's supplying it?

d-Matrix has named TSMC for the N4P logic die and Alchip as its ASIC design and 2.5D/3D packaging partner, but neither company operates a DRAM fab, and across the Hot Chips talk, the ISCA paper, and every public announcement since the Pavehawk 3DIMC test silicon came online last September, the firm has never identified who fabricates its custom DRAM. Only three companies make leading-edge DRAM at volume, and all three are allocating capacity to HBM4 lines that are effectively sold out through 2026.

J.P. Morgan estimates DRAM prices will have risen more than 400% between the start of 2024 and the end of 2026. In addition, analysts have recorded contract price increases of 90% to 95% in Q1 2026 alone, and SK hynix CEO Kwak Noh-jung told Reuters in July that "customer demand will remain higher than our supply capacity even beyond 2030."

Nvidia, the memory makers' largest and most leveraged customer, is reportedly testing Rubin Ultra configurations with as little as 192GB because it may not be able to source enough HBM4E. A startup with roughly $450 million raised, asking a memory maker to run a bespoke die with non-standard bank geometry on capacity that could otherwise print HBM, is negotiating from a far weaker position than that, and until the supplier is named, Raptor's 2027 volume plan rests entirely on an unknown, undisclosed dependency.

The die's 11.4 MB/mm² density is roughly half of HBM4's 21.9 to 26.3 MB/mm², Bhoja acknowledged during the Q&A: "A lot of the drop for us was also because we used a not-so-advanced DRAM. And so if we used a more mainline DRAM, just like the HBM4 guys are doing, we would be able to push that up almost all the way to the HBM4 numbers." The density penalty therefore tracks back to whatever foundry arrangement d-Matrix currently has.

32GB per card

Raptor's 32GB per card stands against 192GB to 288GB for HBM4-equipped accelerators, so d-Matrix sizes deployments at rack scale instead: 72 cards carry 2.3TB, enough to hold Kimi K3's weights at 4-bit precision with headroom for around 54 concurrent users at 1M context, by its own calculations. "Even with 32 gigabytes of memory capacity, we are able to solve SOTA models in a scale-up network, so no bits are wasted," Bhoja said.

KV cache growth works against that arithmetic over time, and co-presenter Aayush Ankit, who led Raptor's SoC architecture at d-Matrix before joining Meta's MTIA team, explained the failure mode while dismissing SRAM alternatives: "We are making this unit of compute blazingly fast. Communication becomes a bottleneck soon enough." Once models and context no longer fit a single rack, inference spills into the inter-card synchronization overhead that the vertical bandwidth was meant to eliminate, which the ISCA paper concedes.

Cerebras claimed 969 tokens per second on Llama 3.1 405B in November 2024, with third-party firm Artificial Analysis verifying the figure on live hardware, and that remains the closest published reference point for Raptor's numbers. d-Matrix's 988 tokens per second per user on a model seven times larger would be a step change if it holds water, but no third party has measured Raptor, and the comparison points in the ISCA paper are simulations anchored to early silicon characterization.

Asked by an Nvidia employee about multi-layer stacking plans, Bhoja said: "Our roadmap is still a work in progress, and we have a hard enough time trying to get one-high to work and work around all of the thermal issues of that." Samsung brought its own version of the idea to Hot Chips with zHBM, a concept that stacks HBM directly on the processor and carries a claimed 70% power-efficiency gain over an HBM4E setup, with no production timeline before HBM5. The problem for d-Matrix is that Samsung runs its own DRAM fabs; d-Matrix doesn't. Whether it can get wafers at volume remains to be seen.

Full d-Matrix Hot Chips 2026 presentation

Earlier this month, Samsung introduced the industry's first LPDDR5X-PIM memory, adding in-memory logic to the low-power memory standard, and at Hot Chips 2026, it dove into the memory technology that we've previously seen at play through HBM stacks.

PIM, or Processing-in-Memory, is a technology Samsung demoed as early as 2021, piloted through HBM stacks in AMD accelerators. It's a small bit of logic that sits alongside DRAM cells, allowing basic calculations to happen directly in-memory. By handling those basic calculations locally, Samsung is able to eliminate the processor as a bottleneck and speed up, in particular, AI inference. In inference tasks, Samsung says its LPDDR5X-PIM is 2.28x faster than standard LPDDR5X, in fact.

The reason for adding in-memory processing to LPDDR5X is pretty clear: HBM is too damn expensive. Micron warned just a day earning at Hot Chips that the HBM wafer demand is only getting worse, and Samsung opened its presentation with something we're all well aware of. Memory makes up the bulk of AI chip costs, and its share of the pie continues to grow. Add on top of that the power demands of DDR5, much less HBM, and LPDDR5X seems like an ideal target for PIM.

Samsung introduced HBM-PIM in 2023, and at the time, introduced the concept of LPDDR5X-PIM. What it shared at Hot Chips is a real product, taking the concept of LPDDR5X-PIM and putting it through validation. Samsung is also looking ahead for LPDDR6X-PIM, and the company says it hopes to have an initial specification from JEDEC this year.

Bringing in-memory processing to Samsung LPDDR5X

Above, you can see a basic layout of how Samsung integrated PIM into LPDDR5X. Each memory bank has its own PIM, which is an advancement over HBM-PIM, where Samsung had to cut banks to fit the logic. The memory bank, scale register file, and source register file feed parallel MAC trees. Once calculated, the output (either integer or floating point output) is written to a vector register file.

Samsung says its LPDDR5X can operate in two modes: single-bank (traditional DRAM) or multi-bank (PIM). Traditional DRAM controllers work, with commands switching between standard read/write or a PIM read/write depending on the mode. The challenge, according to Samsung, was reordering with conventional DRAM.

Samsung uses what it calls Address Align Mode (AAM) to get around the reordering issue. It maps DRAM addresses to MAC instructions, assigning the VRF/SRF address based on the RA/CA address, respectively, and not the Instruction Register File.

To demonstrate how data moves through the memory cells and calculations are performed, Samsung provided an example of a MAC operation, assuming weight parameters for the data are already written into the cell, and the memory is operating in multi-bank (PIM) mode.

Storing 512 bytes of FP8 activation data, it's first broken down into 16, 256-bit packets, which are written into each of the banks in and noted in the Source Register File.

A PIMX_RD reads the weight data from the DRAM bank, feeding into the MAC trees alongside the data from the SRF. Once the calculation is done, the output vector from each operation is written into the Vector Register File.

Once the calculation is done, a PIMX_WR command transfers the output data back to the DRAM bank. Samsung noted there doesn't need to be a 1:1 relationship between reads and writes, but it's useful for this example. With a VRF size of 1 kbit, a maximum of four calculations can be written to the VRF.

With the output written back to memory banks, the host just needs to read the data from memory. The host switches to single-bank (conventional DRAM) mode and executes 16 reads to gather the output from all of the memory banks.

Samsung LPDDR5X specs and preliminary performance

Samsung's LPDDR5X-PIM looks a lot like LPDDR5X. It uses a standard 561-ball array for packaging, just like LPDDR5X, and Samsung uses two 64-bit ranks with 16 GB modules. The critical number here is bandwidth. With LPDDR5X-9600, peak bandwidth is 76.8 GB/s, but that's increased by eightfold with PIM to 614 GB/s by reducing data movement and keeping basic logic local.

Samsung uses four dies per rank, for a total of eight dies. Not the various registers above, as well, as they're important for the illustration of data flow through Samsung's LPDDR5X-PIM memory.

In Samsung's preliminary benchmarks, LPDDR5X-PIM is impressive. In model run time, Samsung say a 2.28x improvement with PIM, and in tokens per second (TPS), PIM offered a 3.01x increase in performance.

The slide above shows what happened behind the scenes to gather these numbers, with Samsung using an edge AI accelerator — we're not sure which, but perhaps an early Gaia SoC — and testing Llama 3.1 with 8 billion parameters. Notably, the output is different, which one attendee pressed Samsung about. The company says optimizations are ongoing to improve accuracy, but it expects the performance benefit to remain the same.

One of the main advantages of LPDDR5X is right there in the name: low power. With PIM, power consumption becomes more of a concern, but Samsung says it doesn't expect higher power consumption overall compared to conventional DRAM. The presenter noted that peak power consumption will be "much higher" due to the bursty power draw of the PIM, but Samsung still expects overall power draw to be lower than conventional DRAM.

That comes down to extra reads/writes. Although PIM represents a power increase, decreasing the number of times data needs to move between DRAM and the host will lead to overall lower power consumption. "We're not having significant power increase," as Samsung's Karam Hwang put it.

LPDDR5X has, until recently, only had applications in consumer products. However, SOCAMM2 serviceable modules allowed Nvidia to use LPDDR5X as the memory of choice with its Vera CPU. And Intel uses LPDDR5X with its new Crescent Island AI accelerator.

Even with PIM, LPDDR5X doesn't come remotely close to the bandwidth with available with HBM, but it has a lot of applications elsewhere. Samsung's targets of server, client, and mobile are telling, with LPDDR5X-PIM accelerating edge AI on mobile and client devices, as well as arriving in lower-scope accelerators like Crescent Island.

Full Samsung Hot Chips 2026 presentation

When it comes to building a gaming PC, DDR5 RAM clocked at speeds of 6,000 MT/s is often touted as the sweet spot for specs. While slower and faster speeds are available, it's very much the benchmark for both price and performance, which is why it's noteworthy that this particular configuration now costs $400, a more than 400% increase from the low prices we've seen in the past.

• $401 for Corsair Vengeance 32GB DDR5 600 ($215 off)

In addition to our ongoing RAM price tracking, we perform daily spot checks on pricing for discounts or deals for 32GB (2x16GB) of DDR5 RAM, given its aforementioned significance as the "benchmark" when it comes to capacity. In recent weeks, the price of 32GB DDR5 6000 RAM has been creeping ever closer to that unfortunate $400 milestone, and in the last few hours we've just crossed the threshold. That's not to say that prices might fluctuate back down in a day or two, but generally the traffic is only moving in one direction.

You can buy 32GB of DDR5 RAM at slower speeds for less — this Corsair Vengeance DDR5 4800 is "just" $359 — but good RAM is now harder (and more expensive) to come by than ever before.

According to data from PCPartPicker, this particular 32GB DDR5 6000 kit from Corsair has been as little as $80 in years gone by at Newegg, marking a full 400% price increase on the lowest we've ever seen on this model.

RAM prices elsewhere have climbed by as much as 500%, with 128GB of DDR5 now costing $3,399 in stores. The causes of the PC component crisis are numerous and well-documented. AI buildouts are consuming much of the world's NAND and flash manufacturing capacity, which is having a knock-on effect for consumer production. Famously, Micron even wound up its consumer brand Crucial in favor of serving more enterprise customers.

All signs point to the memory shortage, and thereby pricing, getting worse in the coming months. As such, bundles and pre-built PCs remain one of the only ways to insulate yourself from cost increases if you're in the market for new hardware. As mentioned, slower memory speeds are available at lower prices, but compromising for 4,800 MT/s RAM to save $40 when building a PC is an extremely tough state of affairs.