What could possibly go wrong when you try to steal trade secrets from a restricted facility using a 360-degree action camera hidden in snacks? Forgetting to turn off the device’s Bluetooth and Wi-Fi transmitters, as it turns out.

A senior engineer at Nanya Technology has been indicted in Taiwan for allegedly copying 32 files containing information about the company's DRAM manufacturing process, reports Freedom Times. The engineer was reportedly in talks with Chinese recruitment agencies and allegedly planned to pass Nanya's trade secrets to its next employer in the People's Republic in exchange for higher compensation.

Yeh Yen-wei, a senior engineer in the Advanced Process Development Division at Nanya, joined the company in 2022 and began to communicate with Chinese recruiters in 2025 to explore employment opportunities in the People's Republic. Sometime in mid-February 2026, he submitted his resignation. However, before leaving the company in mid-April, on March 28, April 4, and April 5 — during weekends and either late at night or early in the morning — he visited the company's restricted office areas with his Insta360 X4 Air action camera hidden among snacks to get it past security checks.

Once inside, Yeh used his legitimate account credentials to access Nanya's virtual machines and opened various internal research and development documents. He then used the camera to capture photographs and video of information associated with Nanya's DRAM process technologies and production methods. It goes without saying that he retained the information when he officially resigned from Nanya in mid-April.

However, his actions did not go unnoticed. Nanya's IT security team detected 'abnormal' wireless signals inside the company's restricted facilities (i.e., identified the device using its Bluetooth and/or Wi-Fi signals) and tied them to the employee's access records and activity logs. Eventually, Nanya reported the suspected theft to Taiwanese authorities, which led to an indictment.

The New Taipei District Prosecutors Office charged Yeh under Taiwan's Trade Secrets Act with unauthorized reproduction of trade secrets intended for use in China, an offense for which he faces up to 10 years in prison, as well as with breach of trust under the Criminal Code. Meanwhile, forensic examination of the seized equipment uncovered no evidence that Yeh had successfully transmitted Nanya's confidential information to a Chinese company or anyone outside the company, so he could potentially get off easy.

Since late 2025, RAM, storage, and graphics card prices have shot through the roof, making items that were once affordable out of reach for many people. Anyone still in the market for those parts has to rely on combo deals for any reasonable pricing. Newegg has an excellent 3-item combo running where you essentially get the 16GB of DDR5 RAM for FREE with a huge $274 discount. For only $658.99, you get the powerful Ryzen 9 9900X processor, a quality Asus X870E-Plus Wi-Fi 7 motherboard, and 2x8GB Team Group DDR5-5200 RAM, along with a free Cooler Master 240mm AIO.

● Check out this deal at Newegg

The star of the combo has to be the ‘free’ RAM. The combo offers 16GB (2x8GB) of TeamGroup’s T-Force Vulkan DDR5-5200. And while the RAM speed is outside of AMD’s sweet spot, you’d be hard-pressed to notice a performance difference without looking at a frame counter. These black, non-RGB sticks will also look great with the included motherboard. If you apply the ~$274 discount to the RAM, you’re getting it for free. And if 16GB isn’t enough, buy the same kit again net 32GB for only $240.

Although we didn’t review AMD’s Ryzen 9 9900X, we know the non-X3D chips, like its big brother, the Ryzen 9 9950X, were generally well received by our reviewer and the public alike. Its strong multicore and single-threaded performance, native AVX-512 support, and backward compatibility with AM5 motherboards make this CPU an excellent choice for someone who uses their PC for more than just gaming and can make use of the additional cores and threads, as you can see from our benchmark data:

The Ryzen 9 9900X is a 12-core, 24-thread processor built on TSMC’s 4nm FinFET process (6nm for the I/O die) with a base clock of 4.4 GHz and boost up to 5.6 GHz. It has a TDP of 120W and is relatively easy to manage the thermals, even when overclocking the fully unlocked processor. While overclocking isn’t what it used to be, you can still squeeze out a couple of hundred more GHz, and sometimes you can get there, even when lowering the voltage. In short, there’s a lot of performance out of the box, and even a bit more headroom left if you want to overclock.

Last, the Asus TUF Gaming X870E-Plus Wifi 7 is a solid all-around motherboard for the AM5 platform. It delivers sufficient power to support flagship-class processors and easily handles the 9850X3D in the combo, even with some overclocking. It comes with four M.2 sockets (one PCIe 5.0) and two SATA ports for storage, fast networking with integrated Wi-Fi 7 and 2,5 GbE, ample USB ports on the rear IO (13, including two USB4 40 Gbps Type-C), and a quality audio solution based on the last-gen Realtek flagship (ALC1220P). Asus’ AI solutions (AI Cache Boost, Overclocking, Cooling II, and Networking II) and the DIY-friendly design make it easy to build and get the most out of your system.

If you’re in the market for an AM5-based system that isn’t based on an X3D chip, this $658.99 combo (an incredible $274 savings) is one of the better deals available at Newegg right now. And you even get a free 240mm Cooler Master AIO. Getting RAM for what essentially amounts to ‘free’ is not something we see frequently. You can even upgrade to 32GB and still find yourself well ahead versus buying alone. Get this deal while it lasts.

Yangtze Memory Technologies (YMTC) shipped 14% of the world's NAND flash in the second quarter of 2026, entering the global top three for the first time and narrowly displacing Kioxia, according to Counterpoint Research's Memory & Storage Tracker published today. Samsung led with 25%, SK hynix followed at 22%, and Micron rounded out the top five. The Chinese vendor's climb comes during a quarter when enterprise SSDs absorbed 48% of every NAND bit shipped worldwide, up from 26% a year earlier, and industry revenue grew fivefold year over year by Counterpoint's count.

In terms of revenue, however, YMTC sits fifth behind both Kioxia and Micron, with nearly all of its output going into consumer products. Consumer bits now sell for a fraction of what hyperscaler buyers pay for enterprise eSSDs holding KV caches and inference datasets. The company has been included on the U.S. Entity List since December 2022, which bars it from achieving Western server qualification, where the big bucks are earned, limiting its addressable market to the Chinese domestic channel plus whatever consumer demand the incumbents leave behind.

They're leaving behind plenty — Samsung's shipment share has dropped from 32% in Q2 2024 to 25% as it caps NAND output in favor of higher-margin DRAM, SK hynix subsidiary Solidigm grew bit shipments 40% quarter over quarter on server demand, and Kioxia's entire 2026 production is already sold out, largely to enterprise customers. Kioxia itself sends over 30% of its bits into servers, per Counterpoint, but its customers pulled back as prices climbed, and slower growth cost it the number three spot it held a quarter earlier.

With NAND contract prices up roughly 75% in Q2 alone, the vacuum in the consumer channel is a segment that YMTC is perfectly set up to serve. The company grew shipments 22% year over year and 5% sequentially while mass-producing 267-layer 3D NAND on its Xtacking architecture, with development underway on devices exceeding 300 layers. Meanwhile, its third Wuhan fab has cleared Beijing's 50% domestic-tooling threshold and is due to begin production late this year, with two follow-on fabs planned.

Counterpoint says that it expects eSSDs to pass half of all NAND bits by year-end, meaning the consumer pool YMTC dominates is shrinking as a share of the total market even as YMTC's slice of it grows. According to the firm, YMTC plans to shift its mix toward eSSDs in the second half, backed by what it called growing avenues for capital support. That shift depends on winning server customers it currently can't reach outside China, and holding a number-three spot earned on cheap bits will get harder if it can't.

Intel CEO Lip-Bu Tan has revealed that new memory architectures — once thought a commodity business — are now strategically interesting and one of his pet projects, while speaking about the comeback of the American chip industry. He further noted that the memory industry is ripe for innovation, and also hinted at exploring ways to stack memory on top of a CPU.

After years of being a commodity, memory became a strategic asset in recent quarters and will likely remain one for a while, so suddenly, leading makers of 3D NAND and DRAM became highly profitable companies, something the Intel CEO is keenly aware of:  "I used to be, 'do not invest in memory because it is a kind of commodity business,' but now it has become different," Tan said. […] "There is a lot of new technology coming out. So, we are kind of looking at one of my pet projects, some of the new memory architecture. I think you just saw the news: I hired my good friend, Seok-Hee Lee, who used to run SK Hynix. So, you kind of know something that I am thinking about. We are not ready to unfold it."

Tan did not reveal anything about the pet project and did not even specify whether the project is one of his personally favored strategic initiatives at Intel, or an initiative in one of the companies that he has invested in. He did mention that stacking memory on top of a CPU could make a lot of sense, though did not elaborate. Tan's remarks also follow the revelation of an Intel XBM patent that does away with the silicon interposer of HBM.

" I think CPU and memory, I think there are a lot of ways we can really do stacking together," Tan said. "And also try to find some new architecture for memory. I think in some way the memory, a lot of innovation are not there. So, there is some really good area."

Not everyone in the industry remembers, but Intel started as a memory company in 1968 and was quite a successful memory maker until the eighties, when Japanese companies took the lead, and Intel had to exit the market completely after suffering severe losses. Since then, the company has attempted either to return to the memory market with NAND and Optane, or at least to capitalize on a new type of memory with RDRAM. In all three cases, the company abandoned its memory initiatives without incurring significant losses.

Given the current profitability of 3D NAND and DRAM makers, producing memory is certainly a good business again and will remain profitable for some time. However, to re-enter it, companies like Intel would need capital to build at least one fab, R&D to develop competitive process technologies, and time. While licensing a technology — assuming that a company has capital — is an option, we strongly doubt that at this point Intel may be inclined to invest capital in memory and not in its core products and foundry businesses. Furthermore, it is unclear how investors react to such investments given the fact that the company struggles to become a strong competitor in the foundry market and has exited 3D NAND and 3DXPoint/Optane businesses after failing to achieve strategic targets.

Apple reportedly has around $1 billion in "processor wafers on the shelves awaiting packaging" amid ongoing memory shortages, putting pressure on the firm as it nears the launch of the iPhone 18. Tim Culpan of Culpium says Apple is "scrambling" for memory supply ahead of release, working with suppliers to get memory ready so it can finish packaging the A20 Pro and C2 chips that are reportedly inside the iPhone 18 lineup.

It's an interesting peek behind the curtain of the current supply chain limitations, which reach beyond simply DRAM chips. With fully-integrated SoCs across both desktop and mobile, Apple is uniquely vulnerable to supply chain limitations, not only in DRAM supply, but also in packaging capacity to bring together DRAM chips with processor wafers.

According to Culpan, Apple primarily sources DRAM from Micron, with smaller engagements from SK Hynix and Samsung. Micron (along with the other major memory players) has reportedly sold capacity for DRAM and HBM through 2027. A flurry of long-term agreements (LTAs) have cropped up over the past several months, guaranteeing supply to certain companies for several years.

The A20 Pro is the first chip to use TSMC's N2 process, and it has been progressing well, with TSMC reportedly sitting on around $1 billion worth of Apple wafers awaiting packaging with DRAM. Packaging happens with TSMC's new Wafer-Level Multi-Chip Module (WMCM) process, according to Culpan, which is similar to the CoWoS packaging but for mobile parts.

Culpan reports that "Apple and its assemblers remain confident that they can meet initial demand," but DRAM shortages could put pressure on shipments past the initial launch. Apple reportedly plans to ship around 200 million iPhone 18 units across the lineup throughout the device's lifespan. The iPhone 17 range saw record shipments last year, surpassing 245 million devices shipped in 2025.

Apple is one of several companies reportedly looking to alternative suppliers for DRAM, namely China's CXMT. The Chinese memory supplier has become a hot topic in the halls of the U.S. government over the past several weeks, with Apple reportedly lobbying for clearance as the government weighs the option to ban CXMT.

This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.

Here's a breakdown of each type of technology that the company announced.

• zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
• zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
• BV-NAND (aka Samsung’s 10^th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).

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zHBM: Placing HBM stack on top of logic

Around the time we first heard about HBM4's 2,048-bit interface, we read a 'semi-official' report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung's zHBM appears to be a continuation of that effort.

Samsung's zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the 'performance of HBM5', while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.

While Samsung's claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a 'next-generation interface system incorporating zHBM' will deliver 'approximately eight times the performance of HBM5,' it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as '8x higher bandwidth.'

Instead, the general term 'performance' may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn't reveal which die stacking/bonding technology it will use for zHBM.

In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.

For now, Samsung hasn't disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.

zNAND-O(on-device): Put storage close to compute

Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company's V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.

Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.

Since the technology is in development, Samsung hasn't shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions 'improved I/O performance and low-latency,' it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.

BV-NAND: Good old V-NAND gets a new treatment

With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.

Samsung formally announced its 400-layer-class V-NAND (aka 10^th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm² with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung's 10^th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk's BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.

Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.

Samsung's new brand strategy

As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.

Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company's new tech, like zHBM and zNAND-O, is years away.

Following its massive $8.6 billion initial public offering (IPO) in July, ChangXin Memory Technologies (CXMT) began considering building its sixth DRAM fab in China to boost memory output in the coming years, Reuters reports. If all announced projects proceed as planned, the company's production capacity could more than double in the mid-term future, the report claims. Meanwhile, investment banker Dan Niles believes China could capture 30% of the DRAM market by 2030, according to P Equity Research.

Growing at a rapid pace

CXMT currently operates three 300-mm DRAM fabs: two near Hefei and one in Beijing's Yizhuang district. Unofficial reports claim that each fab is capable of processing around 100,000 wafers per month, so the company's output may be around 300,000 wafer starts per month (WSPM).

The company is pursuing an aggressive expansion strategy and is currently building additional fabs near Shanghai and Hefei, according to Reuters. The company's sixth fab will reportedly be located in Beijing's Yizhuang area, adjacent to its existing facility. Once these projects are fully operational, the company’s total manufacturing capacity could exceed 600,000 WSPM, which will double its current output, according to Reuters. Meanwhile, researchers from Citrini believe that CXMT could exit 2026 with a capacity of 350,000 WSPM, which is just 25,000 WSPM shy of what Micron targets by the end of the year. Citrini Research models that by 2030, CXMT will have production capacity of around 950,000 WSPM.

Building three big DRAM fabs is a big deal, from both financial and execution points of view. However, it is not a secret that virtually all fabs owned by Chinese companies are built using money from local and federal governments under the 'Hefei model,' which aims to transform cities into economic juggernauts by leveraging high-risk projects. So it is not surprising that both Shanghai and Beijing have provided financial assistance and other forms of support to attract CXMT to their regions, according to Reuters.

CXMT's existing Beijing fab, operated by Changxin Jidian, received backing from E-Town Capital and Beijing E-Town Technology, both affiliated with the Yizhuang development zone, according to a person familiar with the matter cited by Reuters. In fact, the district has evolved into a relatively major semiconductor manufacturing hub that already hosts CXMT, SMIC, Naura Technology, and Xiaomi, the report claims.

The right timing

The proposed fab would be located in Beijing's Yizhuang district, roughly 20 kilometers southeast of the city center, where CXMT already operates a 300-mm DRAM manufacturing facility. The planned production capacity and total capital investment for the project have not yet been disclosed, although Reuters points out that a leading-edge DRAM fab typically costs well over $10 billion.

Sources cited within the report said the company is seeking at least 60 million yuan ($8.9 million) in financial support from the Beijing Economic-Technological Development Area, and additional state-owned technology companies have also expressed interest in participating. Discussions remain preliminary, and neither the overall size nor the structure of the financing package has been finalized.

From CXMT's point of view, this is the right time for financial influxes as the company can sell all of its DRAM output at good prices to a variety of customers. Those being domestic PC and server makers (including Lenovo), and global brands such as Micron, Samsung, and SK hynix, which prioritize shipments of their DRAM output to the AI sector.

Apple, Dell, and HP have all reportedly qualified CXMT's memory and are ready to deploy it in their devices sold in China, while Acer and Asus have already begun to use DRAM from the Chinese maker. If CXMT signs long-term supply contracts with the world's leading PC makers, it is nearly guaranteed to sell out its output to these vendors in the coming years, which justifies investments in its expansion.

30% of DRAM market by 2030?

Dan Niles, founder of Niles Investment Management, believes that many investors underestimate how much share CXMT could capture over the coming years and how much share China may seize in the coming years.

His argument stems from historical DRAM market leadership shifts. In 1975, U.S. companies controlled 95% of the DRAM market, with Intel alone holding 75%. Japan then turned DRAM into a commodity business, increased its share to 80% by 1985, while the U.S. fell to 10% and then just 2% by 1990. Then South Korea repeated that playbook in the mid-1980s and eventually displaced Japanese suppliers, and today it accounts for roughly 62% of the global DRAM production.

With Micron's investments of hundreds of billions of dollars in U.S. DRAM capacity, the country is set to regain its massive presence on the global DRAM scene; China could capture 30% of the market by 2030, according to Niles.

China already consumes around 30% of global memory output, as it produces hundreds of millions of PCs and smartphones both for domestic and global consumption; it is reasonable to expect the country to produce as much commodity memory locally as possible. Keeping in mind China's push for semiconductor self-sufficiency and willingness to invest huge amounts of money in domestic fabs, it is possible to expect the country to rapidly gain DRAM output and share. China is already pushing its chipmakers hard to start DRAM production, and the government reportedly asked CXMT to share its process technologies with others.

Not that easy

There are multiple factors — both technological and political — that may, if not stop, but greatly slow down CXMT's and China's DRAM expansions in the coming years.

First up, there are export controls in place that prevent Chinese entities from getting sophisticated wafer fab equipment required to make DRAM using 18nm-class process technology or more advanced. If the proposed MATCH Act passes, then limitations on Chinese companies will get more severe, which will reduce their expansion ability.

Secondly, even if CXMT (or another Chinese DRAM maker) finds a way to produce more advanced DRAM using relatively outdated tools (i.e., use old tools for sub-16nm nodes), they will need to acquire those tools in quantity to increase their output. Meanwhile, companies like ASML have relatively limited production capacities, and CXMT is certainly not the only memory maker seeking to expand its production capacity in the coming years. While SMEE and SiCarrier are developing lithography tools in China, they will be unlikely to ramp up production of immersion DUV scanners to higher levels any time soon.

Thirdly, building fabs is one thing; operating leading-edge DRAM production at high yields is another. China has recruited engineers from Micron, Samsung, SK hynix, and TSMC for years, but scaling from three to six or more fabs requires thousands of experienced process, yield, device, lithography, and integration engineers. Building fabs adjacent to existing sites enables CXMT and other chipmakers to share experience and knowledge internally, which helps to develop experienced talent. But will it be enough for the long term?

Next, expanding wafer capacity alone is insufficient. DRAM producers must continuously migrate to finer process technologies (e.g., 16nm-class, 14nm-class, 12nm-class) to remain cost-competitive. If export controls delay access to equipment or materials needed for these nodes, Chinese fabs could end up producing more wafers at a higher cost per bit than competitors.

Finally, some American lawmakers want to prohibit U.S.-based companies from acquiring memory from CXMT and other Chinese vendors. They have every reason to believe that China wants to take control of a sizeable DRAM market share in a bid to use it in its strategic interest and have leverage over the market, something the country already has with rare earth metals. If the lawmakers manage to turn the proposal into law, demand for CXMT's and other China-made DRAM will drop. It will probably be sufficient inside China, but whether it will be enough to justify 10 or more big DRAM fabs is a different question.

Pushback against Micron's planned manufacturing complex in Clay, New York, which comprises four separate fabs, is once again at the center of an environmental lawsuit. Filed by Neighbors for a Better Micron and Jobs to Move America — the same groups that filed a separate lawsuit against Micron in January — filed a new complaint Friday, claiming that approved wastewater and air permits aren't valid and will allow Micron to leak "forever chemicals" into the Oneida River.

"The Permits were issued against eh backdrop of the significant environmental consequences already acknowledged through the course of the Micro Project's State Environmental Quality Review Act (SEQRA) review. including the release of PFAS and other highly persistent and hazardous chemicals," the complaint reads. "Rather than fully and meaningfully evaluate and address those consequences and impose the necessary protections before granting final authorization, [the Department of Environmental Conservation] issued permits that defer essential analyses, controls and limitations, and mitigation decisions until after issuance or until future regulations and studies have been conducted."

The lawsuit names the New York State Department of Environmental Conservation (DEC), Onondaga County (where Clay is located), and Micron. Its claim is that, despite Micron receiving wastewater and air permits from the DEC, those permits aren't adequate to regulate the plant's emissions. In one part of the lawsuit, the petitioners claim the permits are "not routine operating approvals," and in another, claim the loose permit guidelines "are not collateral or technical omissions."

Per- and polyfluoroalkyl substances, otherwise known as PFAS or "forever chemicals," are synthetic chemicals that are essential to semiconductor manufacturing. The chemicals are present throughout nearly the entirety of the manufacturing chain, necessitating strict water and air containment management to align with environmental regulations. "The SPDES permit authorizes the acceptance and discharge of Micron's industrial wastewater containing identified emerging contaminants, including PFAS compounds, but it imposes no substantive controls on those harmful contaminants beyond monitoring their presence and concentration."

In January, the two petitioners named in this complaint filed another lawsuit against Micron, claiming that the project failed to comply with the state's environmental review process. Last month, Micron asked a judge to dismiss the lawsuit. It's still set for oral arguments on August 25, however.

This lawsuit currently doesn't have a date set for oral arguments, if it ever reaches that point. The petitioners are seeking the nullification of both wastewater and air permits, which would force Micron back under the environmental review process, and costs associated with the suit.

Storage and memory manufacturer Lexar has listed a new 32GB (2x16GB) DDR5-7200 CL38 memory kit in China with a price tag of 3,999 yuan (roughly $592). Part of the second-generation Thor RGB series, the kit features a sandblasted aluminum heat spreader, thermal pads, and eight LEDs that support a variety of RGB lighting effects. It is rated for 38-48-48-86 timings at 1.40V and supports both Intel XMP 3.0 and AMD EXPO profiles.

Lexar says the modules use carefully selected domestically produced DRAM, although it does not specify the actual manufacturer. While there is no confirmation, the company may be using DRAM chips made by CXMT (ChangXin Memory Technologies). Lexar has also published a compatibility list covering 43 motherboards, including 30 Asus models and 13 MSI models across Intel Z890, Intel B860, and AMD B850 platforms. The compatibility list also includes supported boards for a faster 32GB (2x16GB) DDR5-7600 CL38 memory kit.

Interestingly, none of AMD's X870 or previous-generation motherboards appear on the list. That said, the kit should work on most DDR5 boards that Lexar hasn't tested, but the absence of AMD's flagship consumer chipset from the compatibility list is a bit odd. Notably, major motherboard manufacturers, including MSI and Gigabyte, have already started optimizing their motherboards to support CXMT memory ICs.

A few months ago, Corsair began adopting CXMT DDR5 chips in select memory kits, including its popular Vengeance lineup. Likewise, major PC manufacturers such as HP and Dell have started qualifying CXMT DRAM, while Acer and Asus have reportedly asked their Chinese manufacturing partners to source locally made memory chips.

The arrival of CXMT-made DDR5 chips earlier this year raised hopes that a new DRAM supplier could ease supply constraints and eventually lower memory prices. So far, there seems to be little evidence of that happening. At around $592, Lexar's new DDR5-7200 kit is priced in line or only slightly below many comparable 32GB DDR5-7200 kits currently available in the U.S. Similar kits from brands such as G.Skill, Corsair, and Kingston are currently selling anywhere from $585 to $700.

There’s been a shift toward using a single DIMM of DDR5 to skirt the worst of the RAM pricing crisis. AMD has suggested to us previously, at least, that it’s an option PC builders are exploring, and it’s a wrinkle that’s shown up in dozens of prebuilts; one that we’ve been careful to avoid when recommending products, particularly during peak shopping events. But just how much gaming performance are you giving up with a single DIMM when using one of the best CPUs for gaming?

The conventional wisdom is that you’re giving up quite a bit of performance, resting on the ideas of previous DDR generations, where going down a single stick will cut your bandwidth in half. The same is true with DDR5, but things are a bit messier, which we’ll dig into later.

At a high level, using a single DDR5 DIMM doesn’t compromise gaming performance by nearly as much as you might expect. We saw drops of around 8% to 10% across Intel and AMD CPUs, and less than a 5% difference with AMD’s Ryzen 7 9800X3D.

A proper dual-channel configuration is still the way to go for optimal performance. However, our testing shows that even a single DDR5 DIMM offers superior performance to dual-channel DDR4 on CPUs that support both memory generations.

Using a single DIMM isn’t ideal, and it brings up compatibility issues if you plan on adding another DIMM down the line (another area we’ll touch more on in-depth later). But as a stopgap measure amid surging DRAM prices, a single DIMM of DDR5 holds up surprisingly well in gaming scenarios, and it represents a nice on-ramp into a DDR5 platform while prices are out of control.

Testing single-DIMM DDR5 in games

The geomean below speaks for itself. Moving down to a single DIMM drops some performance, but it’s not nearly as stark as I expected. There are some important notes about how we tested before dissecting the results, however.

As usual, we tested at 1080p with a mixture of High and Ultra settings, using Nvidia’s RTX 5090 Founder’s Edition to minimize the influence of the GPU. That’s even more important here, as we’re not evaluating CPUs but the memory that feeds the CPU. We're looking at a separate GPU and CPU here, as well; dual-channel memory is vital if you're using an iGPU.

We also wanted to create a realistic testing scenario. Assuming you’re going for a 2x16GB configuration, that means starting with a single 16GB DIMM, not a 32GB one. That’s what we did here. Our single-DIMM configurations run with just 16GB of memory, while dual-DIMM configurations run with 32GB. Capacity isn’t a major limitation for our testing here, though it will pose performance issues if you’re running several applications alongside your game.

The Ryzen 5 7600X was our biggest loser, dropping 10.9% of its average performance across our 13-game geomean with a single 16GB DIMM. The Core Ultra 7 270K Plus, meanwhile, dropped 8.7% of its average performance, while the Core i5-14600K similarly dropped 8.3% of its performance. The 1% lows are especially notable here, scaling with average performance rather than falling off a cliff.

Unsurprisingly, the Ryzen 7 9800X3D fared the best, dropping just 2.8% of its performance on average. As you’ll see through our individual game tests, the Ryzen 7 9800X3D shows identical performance with two DIMMs and a single DIMM in multiple games. The large and speedy L3 minimizes the impact of using a single DIMM, giving AMD’s 3D V-Cache CPUs another notch in their belt (as if they needed another).

Our other geomeans don’t say much. A single-DIMM configuration consumes a few watts less, leading to slightly lower efficiency when balanced against the lowered performance.

007 First Light, the newest game in our test suite, shows good scaling across our test pool, so it’s a good place to start. The Core Ultra 7 270K Plus dropped 8.9% of its performance with a single DIMM, while the 9800X3D dropped 6.5%. The 14600K is worth highlighting here. A single DIMM lost us 7.9%, but that’s still better than dual-channel DDR4, and by a decent 6.8% margin.

This trend is fairly consistent, too. Starfield is punishing for single-DIMM configurations, with the 14600K losing 10.6% of its average performance. Even then, a single DDR5 DIMM is 6.9% faster than dual-channel DDR4. Intel platforms can scale up to high data rates, and we use 7,200 MT/s for Intel chips. With slower speeds, the performance will equalize. Still, I’d strongly consider a single DDR5 DIMM if you’ve been eyeing an LGA 1700 platform with DDR4, assuming you’re primarily focused on gaming.

Starfield shows the benefits of 3D V-Cache in this single-DIMM configuration clearly. While the performance losses with other CPUs are brutal in this title, the 9800X3D dropped just a few frames, a 1.6% decrease in average performance.

Doom: The Dark Ages is similarly harsh on single-DIMM configurations. The Ryzen 5 7600X dropped 17.3% of its average performance, and the 270K Plus fell by 14%. The 9800X3D holds up well, however, with just a 4.2% average performance loss. Marvel’s Spider-Man 2 (in the gallery below) shows a similar dynamic.

However, the addition of 3D V-Cache mainly helps in these games where we see bigger losses with other CPUs. There are several games in our suite where the performance loss between a single DIMM and dual-channel configuration was minor, particularly in GPU-heavy titles. The Last of Us Part One shows that in action.

Similarly, the performance loss is minor in Counter-Strike 2, just a handful of frames even north of 600 FPS. Even the Core i5-14600K, which was hit the hardest by far, dropped just 5.9% of its average performance (and it’s still faster than a dual-channel DDR4 configuration).

You can browse the results of the other games we tested in the gallery above, though they tell much the same story as the titles we highlighted. The two biggest learnings from this testing are that a single, fast DDR5 DIMM often outpaces dual-channel DDR4, and that AMD’s 3D V-Cache can smooth over the rough edges of using a single DIMM, particularly in those memory-sensitive titles.

How we tested

We tested on our normal test bed that we use for CPU reviews, with the only difference being dropping one of our DIMMs. As usual, we enabled XMP/EXPO for testing, both on single- and dual-DIMM configurations, opting for higher speeds on Intel platforms. AMD’s sweet spot is around 6,000 MT/s.

The data rate is noteworthy for the DDR4 comparison, in particular. With slower DDR5, we expect the delta between dual-channel DDR4 and single-DIMM DDR5 to decrease.

In addition to enabling XMP/EXPO, we disable Virtualization-Based Security (VBS), enable Resizeable BAR, and disable any automatic overclocking features that aren’t covered by warranty, including AMD’s Precision Boost Overdrive and Intel’s Extreme performance profile.

Complexities of DDR5

DDR5 has much higher data rates compared to DDR4 (2x or more), and that’s the result of significantly more complexity on DDR5 DIMMs compared to DDR4. Notably for this testing are the two 32-bit subchannels of DDR5, as well as enlarged prefetch and bank groups. You are getting half the total bandwidth with a single DDR5 DIMM, absolutely, but it’s a little more nuanced than simply running your memory in a single-channel configuration.

DDR4 uses a single 72-bit channel, and 64 of those bits transfer data (the additional 8 are for ECC). With DDR5, you get two 40-bit subchannels, 32 of which are used for data transfer. Critically, these subchannels have their own Command/Address (CA) interface, allowing them to operate independently of each other.

In addition, DDR5 doubles the prefetch size to 16N, doubles the number of banks and bank groups, and increases burst length from 8 bytes to 16 bytes. The math here is straightforward enough. With DDR4, you can transfer 64 bits of data over the interface at a burst of 8 bytes, giving you 64 bytes of data and aligning with cache line sizes. Each of the subchannels in DDR5 can transfer 64 bytes of data, as well, with a 32-bit width and burst length of 16 bytes.

It’s pseudo-dual-channel memory on a single DIMM. There are two independent memory operations that can happen each cycle, both of which transfer 64 bytes of data. That is a big reason why even a single DDR5 DIMM (particularly one with a higher data rate) can outpace even a proper dual-channel DDR4 configuration.

The common wisdom about using a single DIMM comes mainly from previous DDR generations, where you can only get that single 64-byte transfer each cycle, necessitating a second DIMM to have two independent operations.

Let me be clear: two DDR5 DIMMs are still better. Instead of two operations per cycle, you can perform four. The main difference is that, for modern CPUs and games, just those two operations give you the vast majority of your performance, and you don’t run into a massive performance bottleneck as you do with just a single operation via DDR4. After all, there are still a lot of DDR4 systems out there.

On the issue of compatibility

The elephant in the room with upgrading to a DDR5 platform with a single DIMM is compatibility. If you get a single DDR5 DIMM now, you should plan to add another in the future. Unfortunately, there aren’t a lot of easy answers when it comes to combining two DIMMs that aren’t in a kit together. It should work, but mixing and matching can lead to stability issues and/or lowered performance.

Generally, combining two DIMMs of the same spec should work. For instance, if you bought this Patriot Viper Venom DDR5-6000 CL30 DIMM to start your new build, and then bought a second one later, it should work. “Should” carries a lot of weight on its shoulders, however. Maybe Patriot sources DRAM from multiple places, or your second DIMM’s timings don’t completely align with your first. That could cause stability or performance issues.

There have been some attempts to get past this hurdle, such as the ROG Certified program with select Asus motherboards, but it’s impossible to know for sure if two separate DIMMs will work together or not without testing. The best you can do is to make sure you buy the same brand of memory, with the same spec, if you add a second DIMM. Make sure to keep your receipt handy in the event you need to return it, as well.

Once you have your second DIMM, make sure to test it first at stock JEDEC speeds/timings (no XMP/EXPO). Run games or applications you normally run, and then use a utility like MemTest64 to check for stability. I’d recommend keeping your PC running in this state for a few days to see if any BSODs, application crashes, or poor performance issues pop up. After that’s done, repeat the process with XMP/EXPO enabled, assuming you’re using matching DIMMs (incompatible XMP/EXPO profiles won’t work together).

Assuming DRAM prices continue at an elevated rate before you upgrade, you may want to consider investing in a dual-channel kit down the line and selling your single DIMM. Even kits can run into compatibility issues, though the likelihood is far, far lower.

Memory supply from major DRAM manufacturers to independent module makers could drop to just 30% of the amount supplied in 2026 next year, according to C.K. Chang, CEO of Taiwanese memory vendor Apacer, further tightening an already squeezed supply chain.

Chang made the comments during the company's 1H 2026 investor conference on July 24, and in subsequent media interviews after the conference. Although memory price increases are expected to slow during the second half of 2026 — reportedly due to consumers deciding that RAM is too expensive — he believes severe shortages will persist into at least the middle of 2027, and that DRAM will remain the most constrained segment.

According to Chang, the greatest risk facing Apacer, which buys memory wafers from manufacturers such as SK Hynix and Samsung and turns them into finished memory products, is no longer overpaying for the chips, but failing to obtain any supply at all.

In preparation for growing shortages and to prevent a wider shortfall next year, the company says it grew its inventory to NT$12.4 billion ($383.2 million USD) at the end of June, up from NT$8.38 billion ($259 million USD) one quarter earlier, representing an increase of approximately 48%. The company is also arranging a five-year syndicated loan of up to NT$4 billion ($123.6 million USD) to purchase additional chips whenever manufacturers make them available, among other needs.

Chang’s projection does not mean worldwide DRAM production will fall by more than 70%. His statement specifically refers to the volume major chip manufacturers may allocate to downstream module companies such as Apacer, which purchases memory chips and packages them into DIMMs, SSDs and embedded storage products. DRAM manufacturers are increasingly reserving their output for high-bandwidth memory (HBM), server memory, and other products purchased directly by large AI and cloud customers.

Samsung, SK Hynix and Micron — the world's biggest memory chip makers — are prioritizing higher-margin HBM and advanced server memory as AI infrastructure spending consumes an increasing share of available manufacturing capacity. Chang estimates that approximately 60% of DRAM capacity is now directed toward server-related applications, leaving conventional DDR4 and DDR5 products competing for a shrinking portion of the market.

DDR5 RDIMM server modules have received some of the most aggressive price increases and retain the greatest potential for future mark-ups, according to Chang. Demand from AI servers, enterprise storage, industrial computers and edge AI systems remains strong, while consumer PC and smartphone demand is considerably weaker and more sensitive to rising component costs. That weaker demand is, of course, mostly in comparison to the AI industry. Consumer demand remains strong enough to mop up the shrinking supply. The RAM shortage is now reportedly affecting the price of cars, far beyond consumer electronics.

NAND flash is also being pulled into the AI boom. High-capacity enterprise SSDs are increasingly being used for model storage, data staging and key-value cache offloading, allowing colder portions of AI workloads to spill out of expensive DRAM. Flash cannot replace DRAM outright because it offers considerably lower bandwidth, but it can still serve as a tier within AI memory systems, increasing demand for enterprise SSDs and NAND alongside server memory.

Chang expects DRAM contract prices to rise by approximately 30% during the third quarter of 2026 and NAND flash to increase by more than 20%. He expects price growth to moderate again during the fourth quarter.

Elsewhere, analysts project a 40% increase in DRAM prices in Q3 2026, even as demand extends to the oldest standards still in production. Samsung and SK Hynix, both South Korean companies — who together with US-based Micron Technologies control over 90% of the global DRAM market — had earlier warned that shortages could last beyond 2027. And the CEO of Adata projects that the global DRAM shortage will run for another 10 years.

Chinese manufacturers are not expected to provide immediate relief. Chang said Chinese memory maker CXMT’s DDR5 products had become competitive and that both CXMT and Chinese NAND producer YMTC had narrowed their pricing gaps with established international suppliers. However, domestic demand in China already exceeds available supply, while capacity expansion, manufacturing yields, product validation and platform compatibility continue to limit their ability to change the global balance. Furthermore, the prices of new DRAM modules from CXMT are reportedly similar to those of the big three.

Stockpiling memory inventory at historically high prices carries the risk of substantial losses if the market suddenly reverses. Apacer, however, says it has seen no evidence of an approaching collapse. For now, the company is betting that possessing expensive memory in 2027 will be considerably better than having no memory to sell at all.

Unless you already have a kit of DDR5, or deep pockets for PC hardware, you’re stuck right now. Despite seeing some of the best CPUs for gaming released just in the past year, the DDR5 tax represents a major hurdle to building or upgrading your PC. Intel’s LGA 1700 CPUs hold an unintended solution, offering support for both DDR4 and DDR5. We wanted to see if this on-ramp to a next-gen platform was really as smooth as it looks at first glance.

The idea is simple. If you already have a DDR4 kit, you can upgrade to a relatively new CPU while keeping the door open for a transition to DDR5 without buying a new chip. It’s inexpensive, and a bit more of a practical solution than upgrading to DDR5 with a single DIMM and worrying about pairing it with another later.

Our testing shows how much of a performance difference there is with DDR4 in games. We’re focused on games here for a few reasons. First, in non-gaming applications, memory speed is highly dependent on the specific workload you’re running. Games, despite using different engines, are largely similar workloads that stress the hardware in similar ways. Further, those workloads are continually evolving as new games, new technologies, and new hardware targets are released.

We kept our testing focused on Intel’s LGA 1700 CPUs because they’re the only options that give us a true apples-to-apples comparison between DDR4 and DDR5. We don’t have any AMD CPUs in our test pool because there aren’t any chips that support both DDR4 and DDR5. This isn’t intended to be a competitive analysis between AMD and Intel. That conversation opens up a much broader conversation about total platform cost.

Testing DDR4 vs. DDR5 on Intel’s LGA 1700 CPUs

To test DDR4 and DDR5’s gaming performance, we ran Intel’s main LGA 1700 stack through a 15-game gauntlet of benchmarks. Notably, we don’t have results for the Core i9-12900K, as our sample has a janky memory controller that won’t boot on DDR5 systems. You can read a full breakdown of how (and why) we tested in the way we did in the section below.

We ran all of the games through our 16-game benchmark suite, though we cut Doom: The Dark Ages from the results here. An update for the game rolled out mid-way through testing and skewed our results, so we’re omitting it. The 15 remaining games still paint a clear picture of the performance difference between DDR4 and DDR5.

As usual, we tested with the RTX 5090 Founder’s Edition at 1080p with a mixture of High and Ultra settings. We test at 1080p to maximize the differences between CPUs, and it remains the most widely-used resolution for gaming. Deltas between CPUs will decrease as the resolution climbs and the GPU becomes a larger influence in performance.

Below is our geomean from testing across the suite. Given that we’re looking to compare a single CPU’s performance with DDR4 and DDR5, we’ve highlighted some CPUs with the same color (13700K is always dark red, for instance, while 14700K is always dark blue).

The chart above is a bit difficult to parse, mainly because we’re often jumping several entries to get to a comparison point. For the stack of chips we tested, here’s a clearer overview of the performance difference with DDR4:

As we’ll get into with the individual game tests below, the drop in performance between DDR4 and DDR5 can be much larger than the comparison in our geomean (and, in turn, smaller in other games). What’s important for the overall performance drop is the trend as we move to newer chips. You can see a 9% drop grow to 14%, as DDR4 becomes a more significant bottleneck when the processor it’s feeding becomes more powerful.

That trend is one of the main driving forces behind our look at DDR4 and DDR5 gaming performance today. We looked at DDR4 and DDR5 performance extensively near the Alder Lake launch, and even more recently last year, evaluating performance across a wide range of applications. The testing here is focused solely on gaming to answer a critical question of building a PC today: Are you really giving up that much gaming performance with DDR4?

The answer is, yes, you’re giving up around 11% to 14% of your gaming performance overall when the memory is the only variable that changes. That’s a consistent drop, as well. Older titles care see less of a benefit from DDR5 generally, but we saw a steady decrease of around 11-14% across the games we tested, with some titles pushing above a 20% drop.

007 First Light is the newest game we tested, and it outpaces our averages. The 14900K sees a 16.5% drop with DDR4, while the 13600K drops 12.7% of its performance. Especially among the most powerful CPUs here, you can see DDR4 level off performance in a way that’s undesirable. The 14900K, for instance, is just 1.7% faster than the 13900K with DDR4, but it’s 4.6% faster with DDR5.

Similarly, in Crimson Desert, you can see the 13700K lose 13.7% of its performance with DDR4, and the 14600K drop 13.2% of its performance. It’s worth noting that neither of these games are particularly sensitive to memory speed. You can see in our recent Ryzen 7 5800X3D re-review that even a boost from 3D V-Cache doesn’t give CPUs with a robust memory chain an automatic advantage.

Perhaps the most consequential of the newer games we tested is Marvel Rivals, not only because it shows a much larger gap between DDR4 and DDR5, but also because it’s the most-played game in our test suite by a long shot (short of Counter-Strike 2). For weaker chips like the 12600K, the gap is 13.9%, just slightly above our geomean. For the more powerful 14700K, however, it shows a gap of 25.3%. Even the 14600K drops 17.4% of its performance with DDR4.

Counter-Strike 2 is less extreme, perhaps as a consequence of having such a high floor for average frame rates. You can see that the Alder Lake chips don’t care much about DDR4, with the Core i7-12700K performing identically across both memory standards. That gap grows with more powerful CPUs, however, with the 14700K creeping up toward a 10% delta.

In Spider-Man 2, we can see more consistent drops across the stack of chips we tested, with most CPUs dropping around 18% of their average performance with DDR4. That’s true even on the weaker 12700K, which lost 15% of its performance. The 14900K, meanwhile, was 18.7% slower with DDR4.

Even in an older, GPU-heavy title like Cyberpunk 2077, we can see a consistent drop. You can see in this game that we become completely bound by the GPU at the top of the rankings, but that’s a level these chips can’t hit when paired with DDR4. The 14700K drops about 14% of its performance, and the 13600K, about 13% of its performance.

You can browse through our remaining benchmarks using the gallery above, but most games tell a similar story. The gap between DDR4 and DDR5 persists, of course, but there’s another angle to look at the data. DDR4 flattens off performance, creating a bottleneck with faster CPUs. That could be justification for buying a weaker chip if you can only afford DDR4 memory right now.

Outside of performance, one important aspect of using a DDR4 system compared to DDR5 is power consumption. With DDR4, power consumption of the CPU increases, as you can see in the chart above. The jump is generally only a few watts, but it’s worth noting nonetheless. In games, we’re well below the operating temperature of all the chips in our test pool, but when pushing toward maximum power draw, DDR4 will post yet another limitation.

How (and why) we tested DDR4 vs. DDR5 now

DDR5 is way too expensive, and Intel’s LGA 1700 CPUs represent a unique value proposition given the unprecedented increases in memory prices over the past several months. The idea is that you can upgrade to a newer platform while sticking with DDR4, giving you a stopgap for an eventual DDR5 upgrade. It seems Intel recognizes this value proposition, as well, as it’s reportedly slated to launch Raptor Lake Next CPUs on the LGA 1700 socket.

We tested the main stack of chips, short of the Core i9-12900K, as described above. We didn’t test variants like KS releases to keep our testing focused, as well as lower-end SKUs like the 12100F or 14400. The memory controllers in these lower-end chips are weaker, sustaining lower DDR5 speeds, so expect less of a difference in performance with them.

Below, you can see the test benches we used. In addition to keeping hardware consistent, we use a frozen OS image with an identical software stack. We’re running the same version of the same apps on the same OS update, with identical drivers.

In the BIOS, we enabled XMP for both kits of memory. We also tested with Resizeable BAR turned on, and Virtualization-Based Security (VBS) turned off. Most motherboard vendors off a profile with the power limits removed on Intel CPUs, which can push the processor outside of warrantied specifications. We stuck with the default “Performance” profile for our testing here.

Is DDR4 still worth it?

It makes sense that we’ve seen a shift back toward DDR4. Although DDR4 prices have risen in lockstep with DDR5 prices, they started from a much lower base. A kit of DDR4 today is not much more expensive than a DDR5 kit of similar capacity a year ago. And, with estimates that the memory shortage could persist through 2030, there’s a strong argument for going with a DDR4 system if you’re in need of an upgrade.

The performance trade-off alone isn’t as big of a problem as it appears at first glance. You’re going to lose about 15% of your average gaming performance with Intel’s LGA 1700 CPUs (particularly Raptor Lake chips). You’ll spend more than twice as much on a 32GB kit of DDR5-6000 as you will on a 32GB kit of DDR4-3200, as you can see in our RAM price tracker. And, you might already have a DDR4 kit, cutting that cost completely out of an upgrade. Dollars spent for performance gained, DDR4 makes complete sense.

However, performance isn’t the only factor at play, and that’s the unfortunate reality of using a DDR4 platform right now. It’s a dead end, both for performance and upgrade potential. As we saw in our recent testing of the Ryzen 7 5800X3D, there’s a performance wall in games with DDR4, one which the 5800X3D often runs up against. The memory is a bottleneck, and it doesn’t seem like there’s a way around that problem without upgrading to DDR5.

We also aren’t seeing any new DDR4 CPUs, at least right now. AMD re-released the Ryzen 7 5800X3D, and there are murmurs of Raptor Lake Next. But given the current landscape, we don’t expect a CPU that will radically change the performance you can get out of a DDR4 platform.

Instead of sticking with DDR4 for a better CPU, the best course of action right now is to bite the bullet on DDR5 and buy a weaker CPU, particularly if gaming performance is your main concern. Given that memory prices are out of control, there are excellent deals on DDR5 CPUs right now, allowing you to offset the cost of an upgrade and giving you a kit of DDR5 to carry forward in future builds.

As an example, AMD’s recently-released Ryzen 7 7700X3D is $80 cheaper than the re-released Ryzen 7 5800X3D, despite coming in nearly 20% faster in average gaming performance. The $230 Ryzen 5 7600X3D shows similar gains, and it’s even more affordable.

In Intel’s camp, the Core Ultra 7 270K Plus and Core Ultra 5 250K Plus represent some of the best all-around value in the CPU world right now, with compelling gaming performance and chart-topping application performance, all for around $300.

You will spend more on a cheaper CPU and a kit of DDR5. There’s no indication that the memory shortage is ending soon, however. We’ve actually seen prices continue to increase despite the surge leveling off. Opting for DDR5 today buys you better gaming performance, but more importantly, it gives you a kit of memory that you can continue to use as new CPUs and platforms are released.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

You're probably already well aware of the three largest memory vendors: South Korea's SK hynix and Samsung, and the United States' Micron. There's a fourth player up and coming in the market, though, and that's China's ChangXin Memory Technologies, more commonly known as CXMT. CXMT is pumping out RAM as fast as it can to soften the effects of the RAMpocalypse on domestic (to China) consumers, and it's also expanding capacity quickly. Given these factors and the size of the Chinese market, it should come as no surprise that motherboard vendors, including Gigabyte, are advertising fresh support for the chip.

MSI appears to have been the first major motherboard vendor to publicly promote BIOS optimizations specifically for CXMT DDR5 memory, initially through China-market BIOS releases and later with global announcements. What Gigabyte is saying is a little different: not only is CXMT RAM supported on Gigabyte motherboards for both AMD's Socket AM5 and Intel's LGA 1851, but it's supported at impressive speeds of up to 8200 MT/s on select boards.

As proof, Gigabyte offers up a CPU-Z screenshot showing a pair of 16GB Lexar modules equipped with CXMT chips achieving a speed of 8200 MT/s with a CAS latency of just 40 cycles on one of its B850M FORCE motherboards. We have to remark that Gigabyte doesn't show the voltage required to hit these speeds, likely for good reason, but the firm did it without disabling the chip's integrated graphics. That doesn't prevent the chips from posting an excellent AIDA64 latency of just 65.4 nanoseconds on the monolithic Ryzen 5 8600G used for the test. For context, typical EXPO kits usually run around 80ns, JEDEC timings are more like 100ns, and LPDDR-based systems rarely come below 110-120ns.

As Gigabyte says, "CXSH (CXMT) chip-based memory offers a welcome additional source of supply for consumers." (CXSH is the JEDEC manufacturer ID code for CXMT) Gigabyte specifically notes that it is modules with 16-gigabit and 24-gigabit ICs that are supported; that means 16GB and 24GB single-rank modules, or 32GB and 48GB dual-rank modules.

While CXMT memory is certainly a welcome additional source of supply, it's also not really clear how much of that memory is actually making its way outside of China, particularly to the US and Europe. CXMT isn't on the US Commerce Department's "Entity List" yet, so the firm's parts aren't actually banned, but the company is once again considered a Chinese military company by the Department of Defense after being briefly removed from the 1260H list in February. Lawmakers here in the states, likely laden with donations from the big three memory firms, want to see CXMT banned, while US tech companies like Corsair, HP, and Dell are already integrating ChangXin RAM into their products, and Apple wants in, too.

The reality is that, as a DIY builder, you are fairly unlikely to know or care if your memory is manufactured by CXMT. You don't usually buy RAM directly from SK hynix, Samsung, or Micron (certainly not since Micron unceremoniously executed Crucial); you buy your RAM from Silicon Power, G.SKILL, Patriot, Corsair, or one of the many other vendors who assemble DIMMs. If the RAM runs at its rated specifications, there's not a lot of reason for the individual consumer to care where it came from. It's nice to hear that the new chips are officially supported by familiar mainboards, though.

As Apple and other American companies seek to use memory chips from China-based CXMT and YMTC amid massive supply constraints, U.S. lawmakers want to ban exports of Chinese memory chips to the U.S., citing concerns of weakening domestic and allied suppliers and indirectly supporting the development of 3D NAND and DRAM by Chinese companies, reports the Financial Times.

John Moolenaar, Republican chair of the U.S. House China Committee, and Democratic Congressman George Whitesides asked Commerce Secretary Howard Lutnick to prevent U.S. companies from purchasing semiconductors from businesses included either on the Pentagon's Chinese Military Companies blacklist or the Commerce Department's Entity List. They also called on the administration to add CXMT to the Entity List and impose additional restrictions on YMTC.

"Dependence on Chinese memory manufacturers creates an unacceptable risk for U.S. national security, economic security, and supply chain security," the letter by Moolenaar and Whitesides reads.

Apple has been seeking approval from the Trump administration to source memory from CXMT amid a severe global DRAM supply crisis caused by the rapid expansion of AI infrastructure. Corsair, and some other suppliers of branded memory modules and SSDs have been using DRAM from CXMT and 3D NAND from Yangtze Memory for some time now.

"We are alarmed that Apple and other U.S. tech companies seek to purchase memory from Chinese semiconductor manufacturers, including those with ties to the Chinese military," the U.S. lawmakers wrote.

DRAM maker CXMT is already on the Pentagon's Chinese Military Companies list, whereas 3D NAND producer YMTC is already in the DoC's Entity List. Their presence in the lists does not outright prevent American companies like Apple from buying their products, but at a significant political risk.

Technically, American companies could buy chips from CXMT and YMTC to use inside products bound for China or other countries and continue to use memory from traditional suppliers in products aimed at the U.S. market. To prevent this, Moolenaar and Whitesides also urge the American government to coordinate with Japan, South Korea, and the EU to prevent CXMT and YMTC from taking advantage of the current supply shortage to establish themselves in allied supply chains, which they believe could ultimately leave the West strategically dependent on Chinese memory.

Moolenaar and Whitesides argue that purchases from Chinese memory manufacturers could indirectly support technologies applicable to China's military.

"Leading Chinese memory manufacturers are all closely intertwined with the Chinese military; thus, every memory purchase by a U.S. company will directly subsidize the People’s Liberation Army's development of this critical dual-use technology," the letter stresses.

The lawmakers argue that CXMT and YMTC could repeat China’s playbook in solar, steel, telecom, and EV markets: use state subsidies to undercut foreign rivals, weaken their investments, and ultimately exploit the resulting dependence for strategic leverage. That said, using Chinese memory now could permanently weaken Western production capacity and leave the West strategically dependent on China for a critical component of AI infrastructure, Moolenaar and Whitesides believe.

Homegrown DDR5 memory from China, manufactured by ChangXing Memory Technologies, has been making the rounds lately as more and more vendors start legitimizing it. However, new testing from overclocker Safedisk, shared by Uniko's Hardware, purportedly shows that it actually carries inferior performance compared to similar options from SK Hynix, alongside significant variance in the silicon between different batches.

CXMT began producing DDR5 in late 2025 despite lacking any cutting-edge EUV lithography tools. Fast forward to today, and reports of the company matching Micron's memory capacity by this year are now floating around. If true, China would become the second-largest memory maker in the world. At such scale, it's no wonder that many companies in China have already started sourcing CXMT-made RAM to fill the gap in the consumer market.

Throughout 2026, we've seen motherboard manufacturers verify CXMT's DDR5 with official BIOS optimizations that allow it to run beyond 8,000 MT/s at this point. OEMs such as Dell and HP are using CXMT RAM in their region-bound systems, and even proper PC hardware companies like Corsair are using CXMT modules. Lexar, Kingbank, Netac, Asgard, Gloaway and more are also producing retail DDR5 kits with CXMT chips.

As such, the testing features a Kingbank 48GB (2x24) DDR5-6000 kit running at CL36 and found several weaknesses despite successfully achieving an 8,600 MT/s overclock at CL44. The first revelation is that CXMT modules don't scale with voltage, meaning you can't just increase voltage in hopes of achieving higher clocks. CXMT's DDR5 apparently doesn't respond well to tuning sub-timings either, forcing you to remain stuck with baseline CAS latency (or higher, like in this case).

Different batches of CXMT-equipped memory perform differently, too, so silicon lottery plays a much bigger role than it would with other vendors. Speaking of which, SK Hynix-made DDR5 modules allegedly performed better at identical clock speeds, while CXMT's modules were less susceptible to overclocking in general. We didn't get any comparative benchmarks for any metric, so take these claims with a grain of salt.

Overall, if the testing is to be believed, it serves as counterprogramming against the popular narrative forming around China as the savior of consumer interests. CXMT's strength lies in the fact that it doesn't have to cater to opulent AI clients as much as the Big Three, which reduces opportunity cost, allowing CXMT to produce more DDR5 memory. That doesn't mean it would be cheaper, though, or at least no evidence has suggested that so far.

CXMT has remained limited to the Chinese region for now, and breaking through to the Western market would mean impressing a lot of skeptics. Not only would pricing play a big factor, but the reliability of a new DRAM manufacturer would raise serious concerns. Stories like these certainly don't help, but with CXMT's IPO on the way, it's only a matter of time before it becomes a serious mainstream contender.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

SK Hynix CEO Kwak Noh-jung says that 2027 will be the "worst year" for the ongoing memory shortage in comments shared with Reuters. The remark comes on the heels of SK Hynix successfully marking the largest-ever IPO for a foreign company on the U.S. stock market, raising $26.5 billion. Although Kwak points to next year being the worst for RAM shortages, the executive expects the memory crunch to last until 2030.

"We forecast that next year will be the worst year in the industry's history from the supply perspective," Kwan told Reuters. "We still forecast that customer demand will remain higher than our ​supply capacity even beyond 2030. But we are doing our best to solve the problem."

In March, SK Group chairman Chey Tae-won also suggested shortages would last until 2030, and the company has previously pointed to 2027 as a key shortage point, alongside Samsung. DRAM demand is largely driven by the HBM used in AI accelerators, which require far more sophisticated manufacturing and packaging processes compared to consumer DDR5. On top of advanced manufacturing, HBM also consumes more wafer capacity than DDR5, forcing major memory brands to reallocate supply and double down on an already sticky supply situation.

Forecasts like this are tricky. It's in SK Hynix's financial interest for memory shortages to continue, even well beyond 2030. SK Hynix has set a record for quarter-over-quarter revenue, and rival Micron has seen its stock value increase 213% this year, pushing its share price to around $990.

However, Kwan's remarks aren't just a bid to rally behind SK Hynix stock. Over the past few months, we've seen Micron and SK Hynix ink long-term supply agreements (LTAs). These agreements commit supply over multiple years to particular companies and define a price floor and ceiling during the agreement term. Although LTAs don't directly influence market prices, they secure demand, and we've seen a lot of LTAs over the past several months to bind DRAM supply.

Although memory (and NAND) prices will remain elevated for at least the next several months, we've seen some signs of the market cooling. Earlier this month, a TrendForce report showed DRAM contract prices up 15% to 18% quarter over quarter for Q3 2026. That's a large increase, but far lower than the QoQ increases we've seen previously.

We're nearing some semblance of stability in the memory market, just stability at vastly elevated prices. How long that lasts is anyone's guess. Although memory brands like SK Hynix have visibility into market trends, those can rapidly change. Just this year, we've seen a massive pivot toward AI spending going toward CPUs, pushing Intel's stock to record highs while shedding around $1 trillion in Nvidia's market cap; a year ago, that would've been almost impossible to predict.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

ChangXin Memory Technologies, or CXMT, has just received official validation from MSI for its high-speed DDR5 memory modules. The manufacturer has released new beta BIOSes across its AM5 lineup, unlocking stable frequencies up to 8,200 MT/s for 3GB CXMT chips on dual-DIMM motherboards. Previously, RAM using these modules was limited to around 6,800 MT/s despite the hardware itself being capable of much more.

The test BIOS comes from MSI China — there's no announcement on global channels for some reason, and it's only available for select motherboards at the moment. MSI tested region-bound retail kits from Lexar and KingBank on boards with both two slots and four slots, but we only have screenshots for the former, courtesy of Videocardz.

One test was conducted using 24GB sticks (2x24) on the MEG X870E Unify model and a Ryzen 7 9700X CPU. This was mostly a standard kit since it came with a 6,000 MT/s EXPO profile. The other config consisted of 16GB sticks (2x16) with an EXPO profile already running at 7,200 MT/s, so it was somewhat cherry-picked silicon, paired with a Ryzen 5 9600X on a MAG B850 MPower motherboard.

The results showed that on dual-DIMM motherboards, 24Gbit (3GB) modules from CXMT were able to clock up to 8,200 MT/s, passing MemTest with 101% coverage. Conversely, 16Gbit (2GB) chips were also stable at 8,000 MT/s on the same test bench with 101% coverage. Moving over to quad-DIMM, the patch notes for the BIOS say they've "also been raised to DDR5-7200," where the limit was stuck at 6,800 MT/s prior.

This is not the first time MSI has optimized Chinese RAM for some of its motherboards. Earlier this year, the company did the same thing for Intel's 800-series models in China. Anyway, these specific BIOSes are meant for the AM5 socket and they're based on existing stable releases — just patched with unlocked memory overclocking features. More motherboards should be supported soon, but for now you can check out the MSI China's community release channel if you want to try one yourself.

Memory prices will keep climbing through the third quarter of 2026, but the blistering increases of the past few quarters are set to cool as consumer buyers reach the ceiling of what they can afford, according to a detailed TrendForce report. The research firm's latest memory pricing survey projects conventional DRAM contract prices to rise 13% to 18% quarter-over-quarter (QoQ) in Q3 2026, with NAND Flash contract prices increasing 10% to 15%; substantial gains, but a marked slowdown from the roughly 60% jumps recorded in the second quarter.

According to the report, the cooldown is driven by consumer electronics manufacturers' unwillingness and inability to absorb higher memory costs after months of relentless price increases, rather than by improved supply. In other words, memory remains in short supply, but consumers are no longer willing to keep paying ever-higher prices.

AI continues to be the market's driving force. Demand for AI inference systems and hyperscale data centers remains strong enough to keep both DRAM and NAND supply constrained, while memory manufacturers continue shifting production capacity toward higher-margin server products. This leaves less capacity available for consumer memory, preventing prices from falling even as demand from PCs and smartphones weakens.

As a result, the memory market is increasingly split between enterprise and consumer customers. On the server side, TrendForce expects demand to remain healthy through 2027 as improving CPU availability supports continued deployments of AI servers built around x86 processors and registered DIMMs (RDIMMs). Although server DRAM is expected to remain undersupplied during the third quarter, price increases should moderate because a portion of purchases is covered by long-term supply agreements.

Consumer markets appear to paint a very different picture. Notebook manufacturers are expected to keep replenishing inventories, but higher memory costs are gradually feeding through into retail pricing, a trend TrendForce believes could weigh on PC shipments for the rest of the year. Smartphone vendors face similar pressure, with many expected to raise handset prices to offset persistently high LPDRAM (low-power DRAM) costs while simultaneously becoming more cautious with production plans as consumer demand softens.

The same pattern is beginning to emerge across storage products. PC manufacturers accumulated substantial client SSD inventories during the first half of 2026, reducing their willingness to accept another round of price increases. Suppliers have responded by taking a more flexible approach during contract negotiations, helping to moderate SSD pricing even as enterprise storage continues to benefit from AI infrastructure spending.

Not every segment is seeing the same level of demand. TrendForce notes that NVIDIA's RTX PRO 6000 Blackwell has yet to generate the expected wave of GDDR7 demand, while weaker notebook shipments have also softened demand for graphics memory. At the opposite end of the market, retail products such as USB flash drives and memory cards remain sluggish as higher upstream costs become increasingly difficult to pass on to consumers.

For PC builders, the report suggests that meaningful price relief is still some way off. Memory prices are continuing to rise because AI infrastructure remains the industry's top priority. However, the pace of those increases is slowing as consumer demand reaches its breaking point.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

The price of DDR5 memory is setting new highs these days as demand badly outstrips supply. In a bid to save money, Meta is recovering legacy DDR4 memory from used servers and is installing it into new machines using its in-house developed Vistara ASIC that enables it to connect old memory modules to its latest servers running AMD EPYC 'Turin' processors that only support DDR5 memory.

Interestingly, Meta is not the only company developing such a solution. Panmnesia, a startup from South Korea, has developed an off-the-shelf CXL controller and switch that enables servers to attach considerably larger memory pools without extending latency, which differentiates Panmnesia’s solution from competing CXL offerings.

Custom ASIC enables DDR4 memory to work with new servers

Vistara is Meta’s first-gen custom CXL memory expander ASIC designed to attach outdated DDR4 memory to modern servers. The chip implements a CXL 2.0 Type-3 memory expander over a PCIe 5.0 x16 interface and bridges standard DDR4 RDIMMs to host processors. Each ASIC supports two independent 72-bit DDR4 memory channels and can provide up to 256 GB of capacity using 64 GB DIMMs. At present, Meta deploys 128 GB per ASIC using 32 GB DDR4 modules recovered from decommissioned servers.

Meta deploys Vistara in its MemServer platform, where two ASICs connect to a single 158-core AMD Turin processor over PCIe 5.0 x8 links. Each server combines 768 GB of DDR5-6400 local memory with 256 GB of CXL-attached DDR4-2400, which expands memory capacity to 1 TB. The software stack transparently exposes CXL memory as a separate NUMA node and enables Linux to migrate cold pages to the slower DDR4 tier (with 76 GB/s of bandwidth) and retain frequently accessed data in local DDR5 (with 614 GB/s of bandwidth).

The ASIC is based on three RISC-V processor cores for secure boot, device initialization, firmware management, and health monitoring. Meta claims it has optimized its CXL controller and memory pipeline to reduce protocol overhead, minimize queuing delays, and lower idle round-trip latency to around 50ns. The chip also incorporates advanced reliability features, including Reed-Solomon two-symbol error correction and x4 chip-kill support.

Not only Meta's Vistara

Meta is not the only company that wants to attach legacy DDR4 memory to newer servers that rely on DDR5 memory and save some money. While Vistara is available exclusively to Meta, there is a new CXL expander solution from Panmnesia that will be available to other companies.

"There has been a perception that putting a switch between the CPU and devices makes it hard to meet the memory-access latency these systems expect, so directly attached multi-headed devices (MHDs) stayed the norm even though they were harder to scale," said Myoungsoo Jung, chief executive of Panmnesia. "Our work shows this is not an inherent limit of CXL or CXL switches — it is a trait of early-stage CXL, and one that fades as the standard and the products around it mature. With a fabric switch that carries our next-stage CXL controller, scalability, low latency, and stable performance can come together."

CXL is a protocol that sits on top of the PCIe physical interface. As a result of this, many early CXL implementations were built by modifying existing PCIe IP, which is why such implementations inherited architectural characteristics optimized for PCIe rather than for memory-semantic communications, which added substantial latency, according to Panmnesia. By contrast, its new CXL controller IP features a redesigned data path that replaces separate per-layer buffers with shared buffers to eliminate much of the synchronization overhead. In addition, it features additional latency optimizations throughout the protocol stack that offset the additional hop introduced by the switch.

The accompanying CXL fabric switch introduces Port-Based Routing (PBR), which removes the tree-topology limitations of conventional Hierarchy-Based Routing (HBR) used by PCIe and early CXL implementations. The fabric switch still supports both PBR and HBR to enable flexible system topologies, optimized traffic routing, and stable performance. In practice, it enables companies like Meta to install more DDR4 memory into their modern servers without major performance degradation because of high latency.

Panmnesia claims that while early CXL deployments could connect only a handful of compute nodes to shared memory pools, its fabric scales to up to 64 nodes, which means greater flexibility for hyperscalers that tend to run thousands of servers, but which now have to rationalize usage of expensive DRAM.

Panmnesia says its next-generation CXL technologies are progressing toward commercialization. The company has pre-release silicon for its PCIe 6.4/CXL 3.2 Fusion Switch and has completed development of its PCIe 7.0/CXL 4.0 Combo IP, which supports the latest features introduced by the CXL 4.0 specification.

In a world where memory is no longer a commodity but a strategically valuable asset, customers are eager to sign long-term supply agreements (LTAs) with their suppliers to ensure a steady supply of 3D NAND and/or DRAM. Micron this week announced that it had signed 16 strategic customer agreements (SCAs), 14 of which are worth around $100 billion. Furthermore, the company expects to receive cash deposits and other commitments worth $22 billion, but has warned there is no foreseeable end in sight to the RAM crisis driving up PC component prices.

“14 of the 16 SCAs that we have signed have a cumulative revenue at minimum price per our contracts of approximately $100 billion over the remaining agreement term,” a statement by Micron reads. “Under the SCAs we have signed so far, we project to receive cash deposits and related financial commitments of $22 billion.”

Based on Micron’s claims, the company has about $100 billion of guaranteed baseline revenue already locked in under 14 of those 16 strategic customer agreements, assuming customers only buy the minimum committed volumes and only pay the minimum contract price. In reality, Micron can earn more if customers buy higher volumes or pay higher prices. Furthermore, Micron expects customers who signed these long-term SCAs to put up real money up front — or make equivalent binding financial commitments — as part of reserving future memory supply.

Micron claims it has signed strategic customer agreements with four 'very large customers' and three 'medium-sized customers,' which means that the contracts were inked with clients that previously did not commit to LTAs. The contracts are signed with a five-year term (except the automotive LTAs, which have a term of three years), from calendar 2026 to calendar 2030.

Micron claims that memory supply will be insufficient in 2027 and may improve gradually only in 2028. To that end, it is not surprising that its clients are willing to sign LTAs for 3D NAND and DRAM to ensure that they have enough memory for their products.

"With respect to supply, our customers are recognizing that supply shortages in memory and storage will take considerable time to improve," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks. "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand."

Normally, Micron and other memory producers inked LTAs with select clients only (read: with Apple, Nvidia). 16 LTAs is a lot for this kind of arrangement, and this looks like a business model shift for the company. It is noteworthy that the 16 signed contracts represent roughly 20% of Micron's DRAM volume and 33% of the company's NAND volume over the period through 2030. That said, Micron may sign more LTAs with more companies.

DDR2 contract prices rose 55% to 60% in the second quarter of the year and are projected to climb another 35% to 40% in the third, according to research published this week by TrendForce, pushing the AI-driven memory shortage onto a standard that first shipped in 2003 and that the three largest DRAM makers stopped prioritizing years ago. The increases come from buyers redesigning products around older memory to secure supply, and from a split among the handful of remaining DDR2 suppliers, with Winbond reducing output as ESMT expands it.

The shortage hasn’t hit DDR2 directly, but Samsung, SK hynix, and Micron have steered wafer capacity toward HBM and server DRAM to feed AI infrastructure spending, thinning the supply of mature-node parts, including DDR4. As DDR4 tightened, OEMs and ODMs began specifying DDR3 in its place, and some DDR3 designs were reworked to use DDR2, with each tier of buyers chasing whatever generation it could still source. The result of this is shortages moving down through successive generations, something we saw unfolding back in March, when earlier data showed DDR3 and DDR2 prices rising 20% to 40% in a single month.

This continues the market inversion we’ve watched unfold throughout the year, as DDR4 climbed past DDR5 on price despite being slower and older, and in which module makers and motherboard vendors restarted DDR4 production after the big three had moved to wind it down.

Winbond and ESMT are the two main remaining sources of DDR2 components, and they’re responding to the squeeze in different ways. Winbond is gradually cutting DDR2 production to shift capacity toward higher-margin DDR3, DDR4, and LPDDR4, while ESMT is doing the reverse, concentrating its wafer allocation at foundry partner PSMC on DDR2 to capture the demand Winbond is tossing aside. Taiwanese suppliers, including Nanya, are already struggling to match the volume of orders migrating down from DDR4, and because new capacity depends on slow process migration, Winbond's withdrawal removes supply faster than ESMT can replace it.

Of course, today’s PCs don’t use DDR2, so we’re likely to see the impact of these price increases landing in areas like embedded systems, networking equipment, industrial controllers, automotive electronics, and other long-lived devices that were designed around it and are too costly to requalify on newer memory generations like DDR4 and five.

The spread of rising contract prices to DDR2 suggests that we’re staring down the barrel of a very long-term DRAM shortage. Contract prices across the wider market are still rising with no sign of levelling off, and meaningful new capacity isn’t expected until late 2027 at the earliest as a best-case scenario.

Apple CEO Tim Cook has warned in an interview with the Wall Street Journal that price hikes on Apple products are unavoidable because the price of memory has increased to a degree that the company must now pass on increases to customers. The outgoing chief executive of Apple did not disclose the scope of the increases or when to expect them to happen, though the warning itself is noteworthy.

Cook said in the interview that price increases had become necessary due to skyrocketing prices of LPDDR and 3D NAND memory, which the company uses in its PCs, smartphones, tablets, and other products. He noted that Apple had attempted to offset rising component costs and protect customers from higher prices, but indicated in the interview that the company could no longer absorb the increases indefinitely. While Cook declined to discuss timing or the magnitude of the planned price hikes, some Apple products may see higher prices sooner rather than later. The company already raised the base price of its Mac Mini last month and eliminated its highest-end model.

TechInsights estimates that Apple will need to hike the price of a flagship iPhone Pro model by about $270 to maintain its current gross margins, which could push flagship iPhone pricing into a substantially higher price band. To make matters worse, Apple faces rising DRAM requirements as it expands memory-hungry on-device AI capabilities.

Apple is a unique company in the sense that it is both one of the world's largest suppliers of smartphones and one of the industry's biggest PC OEMs. Still, its Mac business is negligible compared to the iPhone business.

Memory makers are more inclined to ship non-volatile NAND memory to smartphone makers as they can ship LPDDR with it, according to Nelson Duann, a senior vice president of Silicon Motion, speaking in an interview with Tom's Hardware. If Duann is correct that NAND makers prefer smartphones because they can bundle NAND and LPDDR sales, then Apple should be among the most favored customers in the industry, not among the disadvantaged ones.

Also, keep in mind that historically Apple has used long-term supply agreements, prepayments, equipment financing, and advance capacity reservations to secure key components, including DRAM, NAND flash, displays, advanced packaging, and even semiconductor foundry capacity. As one of the world’s largest electronics manufacturers and semiconductor buyers, Apple is among the few companies capable of negotiating with memory suppliers from a position of considerable strength.

As a result, Apple is not in a situation where it cannot get enough memory; it can probably get more than other suppliers of smartphones and PCs, but it surely has to buy both DRAM and NAND at a premium. That said, it is not surprising that Apple will have to increase prices; what remains to be seen is the magnitude of the increase.

Memory is expensive right now, and there's just no escaping how AI has significantly pushed prices up across the board. Unfortunately, 32GB of DDR5 RAM is now pushing $385 as of this month. This same, exact kit is usually even pricier, costing $439.99 on Amazon, when a year ago, it would have cost less than $100. Memory firms are already warning that costs are expected to go up further, too, with prices likely to double over the next year. With that in mind, this Corsair Vengeance 32GB DDR5 RAM is on sale at Woot for $339.99 right now, and it's the cheapest kit going. If you've decided to bite the bullet before things get worse, this is as good as it gets.

● Check out this deal on Woot

Without a DeLorean time machine, if you need to upgrade or build a new PC, you're going to pay more today than you did back in 2025 or 2024. That doesn't mean that this is a bad option, or make it bad RAM. In fact, the $339.99 price means that, as it stands, this is the cheapest 32GB DDR5-6000 RAM kit you can buy right now on its own. We've tested a slightly different spec of Corsair Vengeance RGB DDR5-6000 RAM in a review, too, and it scored well, offering great performance, with the same striking black colorway for a gaming build as you'll find here.

So, here we are. Necessity means that, if you need to buy memory, you're going to have to pay current market prices for it, and the best way to do that is to find RAM on sale, like it is here. As mentioned, industry figures are warning that RAM prices are expected to double by the end of the year, bearing in mind they've already increased by 4-500%. Newegg combo deals can sometimes offer better value, but they require you to purchase a number of components together to get the RAM at an effectively lower price, and we've seen the best of these deals dry up over the last few weeks, too. Our RAM price tracker will give you a clear indication of just how bad the market has been for buyers lately: you won't find a single option below its record low price floor, with plenty of the most popular models out of stock.

Back to this Corsair memory, then. You're getting a 32GB kit of Corsair Vengeance RAM, rated at 6,000 MT/s, with CAS latency and memory timings of 38-44-44-96. While it isn't the fastest DDR5 you can buy, this DDR5 kit is a big step up over older DDR4 modules, which would usually see speeds of around 3,600 MT/s at best. This is dual-channel memory, meaning your PC will be able to double the bandwidth between the RAM and CPU to boost frame rates and load times significantly when both modules are installed.

The RAM comes with a solid aluminum heat spreader to reduce high temperatures while you're gaming or working. That'll be useful if you decide to overclock it, as you can with this kit, with support for Intel XMP and AMD EXPO OC profiles when installed in supported motherboards. It has RGB lighting, too, which you can customize using Corsair's iCue app on your PC or laptop.

Nobody wants to pay more, but for now, cheap RAM just isn't an option. The next best alternative if you need to buy RAM for a PC is to buy it on sale, and the $339.99 sale price for this 32GB Corsair Vengeance RAM from Woot is the best you'll find right now. There's a pretty lengthy period for this deal to run for, but it could sell out fast, so keep that in mind if you decide to buy. If it does run out, your next, cheapest option is this Patriot kit for $384.99.

If you're looking for more savings, check out our Best PC Hardware deals for a range of products, or dive deeper into our specialized SSD and Storage Deals, Hard Drive Deals, Gaming Monitor Deals, Graphics Card Deals, Gaming Chair, Best Wi-Fi Routers, Best Motherboard, or CPU Deals pages.

AMD on Monday announced that it had acquired MEXT, a startup that developed a memory tiering technology that makes NAND flash memory appear as DRAM to the operating system, which enables operators of data centers to save money on DRAM. AMD expects the acquisition to help customers improve system efficiency, lower operating costs, and deploy large-scale workloads more quickly.

As AI models continue to expand and datasets grow larger, memory availability has become an increasingly important factor affecting overall system performance. In many cases, memory resources, not CPUs or GPUs, are becoming a performance bottleneck. Meanwhile, in many cases DRAM is used inefficiently.

MEXT addresses memory efficiency challenges with an AI-based memory tiering technology that moves infrequently accessed data from expensive DRAM to NAND storage, which costs orders of magnitude less per unit of capacity, and in a way that's transparent to applications. MEXT's Predictive Memory Engine continuously analyzes memory access patterns and uses AI models to anticipate which data stored in flash will be needed next. Those memory pages are proactively transferred back into DRAM before applications request them and enable software to access data as though it were in main memory, thus preserving performance levels.

By increasing the amount of usable memory available to applications, MEXT's technology aims to improve utilization of existing infrastructure and at the same time reduce needs for expensive DRAM. This approach can potentially lower total cost of ownership for cloud providers and enterprise customers and enable larger workloads to run on existing hardware. AMD believes that these capabilities can benefit both traditional data center applications and modern AI deployments, where access to large memory pools is often critical for efficiency and scalability.

AMD plans to incorporate MEXT's technology into its data center product portfolio and expand its capabilities to address memory-hungry AI workloads. The company already offers integrated solutions that combine processors, accelerators, networking technologies, and software, so MEXT's Predictive Memory Engine will complement the already broad portfolio.

As an added bonus to the technology itself, AMD gains a team with expertise in memory architectures, infrastructure software, and large-scale computing systems. Terms of the deal are unknown.

Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

A coalition of nine US trade associations has urged the Trump administration to take immediate action on what it describes as an emerging memory chip shortage driven by the explosive growth of AI data centers. In a June 3 letter sent to US Commerce Secretary Howard Lutnick and Treasury Secretary Scott Bessent shared with Tom's Hardware, the organizations — representing telecommunications providers, automakers, medical device manufacturers, and major retailers — warned that AI infrastructure deployments are consuming an outsized share of global memory production, creating supply constraints and price increases that could ripple across large segments of the US economy.

The coalition warned that the AI data center expansion, which has consumed an unprecedented share of global memory capacity, has led to a memory chip shortage that could lead to higher prices for consumer electronics, increased costs for broadband and telecommunications infrastructure, disruptions to automobile and medical device production, and delays affecting federal contractors attempting to fulfill government procurement obligations. The letter argues that these risks are emerging despite billions of dollars of US investment intended to strengthen domestic semiconductor supply chains.

The signatories acknowledged AI's importance but argue it shouldn't come at the expense of the rest of the economy. "While recent developments in AI offer the promise of generational technological advances and are important for US tech leadership, we must also ensure other key industries are not negatively impacted by this disruption in the marketplace," the coalition said.

The organizations are asking the administration to work directly with memory suppliers and major chip buyers to address the imbalance. Their recommendations include accelerating expansion of memory manufacturing capacity in the United States and allied nations, using trade agreements to strengthen supply-chain resilience, ensuring adequate memory supply for non-AI industries, leveraging CHIPS Act programs where possible, and reducing regulatory barriers that may slow capacity growth.

"We urge the Administration to work with memory chipmakers and chip buyers to assess steps that can be taken to address this imbalance in the memory market and protect against harm to consumers, workers, and businesses of all sizes," the letter states.

The warning arrives as memory manufacturers increasingly prioritize high-bandwidth memory (HBM), the specialized memory used in AI accelerators from companies such as Nvidia and AMD. Demand for HBM has surged over the past two years as hyperscalers race to deploy larger AI clusters, prompting memory suppliers to devote an increasing share of their production capacity to AI-oriented products.

Samsung and SK Hynix — which together with Micron control over 95% of global DRAM production — have been diverting wafer capacity toward high-margin HBM for AI accelerators, starving the commodity DRAM and NAND markets in the process. Both companies warned in April that significant shortages will continue through at least 2027. IDC, meanwhile, has already revised its 2026 PC market forecast downward by up to 9% as a direct consequence of memory scarcity and rising prices.

Industry analysts have repeatedly warned for months that AI demand is reshaping the economics of the memory market. While memory shortages have historically been cyclical, the coalition argues that AI infrastructure spending is creating a structural shift large enough to affect industries far removed from data centers. The letter marks the first coordinated, multi-industry push for federal intervention. Whether the administration will respond — and how — remains to be seen.

Representatives told Tom's Hardware at Computex 2026 that counterfeit memory modules with G.Skill and V-Color badges have hit various marketplaces in China, and the problem is widespread enough that V-Color has observed lower sales to certain clients. Fake memory modules are nothing new, but in this case, forged DIMMs reportedly use printed circuit boards (PCBs) that are identical to those used by G.Skill and V-Color, which makes early detection of counterfeit products difficult.

“We have customers telling us that some Chinese manufacturers are making copies of our products, as well as products from other brands, and selling them at lower prices than we do,” a spokesperson for V-Color told Tom’s Hardware. “We do not really know how they are doing it. The PCB looks the same, even the heat spreader looks identical.”

Given the current situation with memory prices, counterfeit memory modules have become a growing problem in Asian online marketplaces, particularly in gray-market and second-hand channels. Recent reports described fake DDR5 modules containing dummy ‘chips’ made of plastic or fiberglass with fake markings, as well as mislabeled modules marked as products from well-known brands. However, the new case is different because forged memory modules use PCBs that are identical to those used by G.Skill and V-Color and use the same heat spreaders and perhaps complex RGB lighting, making distinguishing between real and counterfeit products particularly difficult.

While developing a PCB for an enthusiast-class memory module takes time and money, producing that PCB is fairly easy, as makers of DIMMs use neither complex PCBs nor too complex equipment. Also, developing enthusiast-grade memory modules (ensuring that they run at the right specifications with popular CPUs) also takes time and money. In addition, sourcing chips from DRAM makers or distributors to make fake memory modules is hard, if even possible at all today. Finally, quality control at the chip level and at the module level is relatively costly, and these two are the main value adders when it comes to enthusiast-grade memory. That said, forging high-end memory modules is easy and might be a profitable business, especially if perpetrators have access to second-hand memory chips. Speaking of chips, the V-Color representative could not say which ICs the fake modules used.

“We do not know because we have not had any of those modules in our hands,” the spokesman said. “We only use SK hynix memory, so we cannot say what chips they are using. We have not received any RMAs related to them. Other brands may have received returns and been able to inspect the products, perhaps because the memory chips were different.”

While a representative for G.Skill confirmed that there are counterfeit G.Skill memory modules sold on Chinese marketplaces, he said that the issue has existed forever, so users should buy their high-end DIMMs from official partners and resellers in a bid to avoid the problem.

As the demands of AI continue to consume manufacturing capacity at every level of the PC hardware supply chain, 32GB of DDR5 RAM — broadly understood to be the sweet spot for gaming PCs and enthusiast builds — can no longer be found for less than $375. Well, $374.97 to be precise.

RAM price tracking through 2026 will show you that kits that routinely cost less than $100 just a year ago are now fetching upwards of $240 (16GB). As the AI frenzy has taken hold, retailers far and wide have been pumping up their RAM prices to exorbitant levels. However, there's so much fluctuation and noise that average pricing is now something of a ludicrous fugazi. The going rate for 32GB of DDR5 RAM — the cheapest you can expect to pay — has hovered around $320 for some time, climbing past $350 in recent weeks. Price tracking courtesy of PCPartPicker now reveals the cheapest 32GB DDR5 RAM you can buy is $375. Specifically, four XPOWER kits from Silicon Power will set you back $374.97 thanks to a promo code. You can see the listings yourself below.

• Silicon Power Zenith Gaming DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)
• Silicon Power Zenith RGB DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)
• Silicon Power Pulse Gaming DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)
• Silicon Power Zenith RGB DDR5 6000MT/s (PC5-48000) CL36 32GB(2x16GB)

As you can imagine, this is enormous pricing pressure for enthusiasts trying to build gaming PCs or upgrade their rigs in 2026. A component that once cost less than $100 and was something of an afterthought now costs almost four times as much, and that's before you've even fired a neuron in consideration of aesthetics, timings, or brand. More popular kits from the likes of Corsair and Crucial, or RGB offerings to match the rest of your build, will easily set you back more than $400.

Of course, 32GB is really the minimum sweet spot you should be aiming for when building a PC in 2026. If you did want more capacity, 64GB will set you back an astonishing $679.99. 16GB of RAM as a compromise can be found for $200 at B&H Photo, but with SK hynix warning that manufacturing constraints will persist through 2030, there's no sign of prices letting up so that you can upgrade capacity any time soon.

The humble RAM combo deals we've been highlighting in recent months are a small source of solace for builders, letting you score RAM for less than the $375 going rate if you pair it with a decent motherboard, a processor, or even an entire set of PC components. A theme of ongoing Computex 2026 announcements remains a lack of pricing clarity on lots of PC hardware, including Nvidia's RTX Spark laptops and PCs, as well as new-build systems and, of course, RAM components themselves. Vendors are likely wary of scaring off potential buyers with higher-than-expected prices ahead of release. Perhaps more likely, the prices haven't been set because they're still going up. Storage isn't much better, with SSD price tracking revealing that drives which once cost as little as $38 are now fetching $200.

AMD is making a noticeable effort to keep PC gaming prices down, this week announcing the return of its Ryzen 7 5800X3D, and the advent of a new Ryzen 7 7700X3D. Intel, which warned this week that "something has to give" when it comes to memory prices, also teased dragging out some of its legacy products to give users more options on older memory technologies, namely Raptor Lake and DDR4.

This week at Computex 2026, we saw Nvidia reveal its RTX Spark, and last month, AMD detailed its Ryzen AI Max 400 "Gorgon Halo" lineup, a refresh of the Strix Halo APUs that lifts supported unified memory to 192GB and allows up to 160GB of that pool to be addressed as VRAM. AMD describes the flagship Ryzen AI Max+ PRO 495 as the first x86 client processor able to run a 300-billion-parameter language model locally, pitching the platform for use cases that need to keep multiple AI agents resident in memory at once.

The market for Gorgon Halo will likely be directly shared with other chips, such as Nvidia's RTX Spark, which debuted at Computex 2026. RTX Spark is also positioned as an on-device agentic computing device. With local AI computing demanding lots of on-device RAM, it poses a difficult issue for device vendors.

DRAM contract prices are forecast to climb another 58% to 63% this quarter, on top of the record 90% to 95% jump TrendForce recorded in Q1, which also saw Nvidia raise the price of its DGX Spark desktop from $3,999 to $4,699, citing memory supply. So, what happens to the dream of accessible local AI compute?

DRAM supply squeeze

The local AI PC has become a category defined by how much memory it carries, and it’s scaling that memory up at a time when memory has never cost more. AMD's three Gorgon Halo SKUs reuse the same Zen 5 cores, RDNA 3.5 graphics, and XDNA 2 NPU as the existing Ryzen AI Max 300 parts, with the Max+ PRO 495 gaining a 100 MHz boost-clock bump to 5.2 GHz, a 40-compute-unit Radeon 8065S, and a 55 TOPS NPU.

Memory capacity has been increased 50% from the 128GB ceiling on Strix Halo, with a leaked PassMark entry putting the 192GB figure as eight 24GB SK hynix LPDDR5X packages on an HP test board, though AMD hasn’t yet confirmed this. Partner systems from Asus, HP, and Lenovo are due in the third quarter of 2026.

It’s all well and good that Nvidia and AMD are releasing machines like the RTX Spark and the Gorgon Halo line-up. However, Samsung, SK hynix, and Micron have all shifted the bulk of their wafer capacity toward high-bandwidth memory for AI accelerators because HBM carries far higher margins than commodity DRAM, and the conventional memory supply has tightened as a direct result of this. HP told investors in February that memory now accounts for roughly 35% of the cost of building a PC, up from 15% to 18% a quarter earlier.

SK Group chairman Chey Tae-won, speaking at Computex 2026 on the show’s official opening day, repeated his position that the shortage will run through 2030, despite the company's intention to double wafer capacity within the next five years. New fabs from all three makers are under construction, but none will reach volume production before late 2027 at the earliest, and most forecasts now predict a structurally higher price floor that persists even after the acute shortage eases.

The 192GB in a Gorgon Halo box, the 128GB in an RTX Spark or DGX Spark, and the LPDDR5X soldered into every AI laptop announced at Computex all come off wafers the memory makers would otherwise sell as HBM. That’s why Nvidia raised the DGX Spark by $700 in February without changing a single spec, and why component makers have begun passing memory costs through directly. One vendor has even taken an extremely on-the-nose approach of adding a flat memory surcharge to every purchase, and in some cases, smaller buyers are now quoted prices that change by the hour.

Bandwidth caps inference speed

A single pool of 192GB would enable an APU to hold a model that would otherwise require a multi-GPU server. While it doesn’t make the model run quickly, dense language model inference reads close to the full set of active weights from memory for every token generated, so generation speed is governed by memory bandwidth divided by the per-token weight footprint, not by idle memory.

Gorgon Halo keeps the same 256-bit LPDDR5X-8000 interface as Strix Halo, which tops out around 256 GB/s in theory and which independent testers have measured closer to 212 GB/s on the GPU. By comparison, the Apple M3 Ultra that AMD and Nvidia are chasing on capacity is rated at 819 GB/s, and an RTX 5090 moves data at 1,792 GB/s.

This gap explains why a dense 70-billion-parameter model fully resident on a Strix Halo iGPU lands in the low single digits of tokens per second, regardless of how much headroom the memory pool has. Our own Corsair AI Workstation 300 review found that Nvidia's slightly higher-bandwidth GB10 pulled ahead of Strix Halo as context length grew, for exactly this reason.

Capacity matters most for mixture-of-experts models, which activate only a fraction of their parameters per token and run far faster than their total size suggests, and for long-context agentic workloads, where it’s KVcache rather than model weights that consume memory. It’s these use cases that AMD’s agentic pitch points at, with leaked details on the next-gen Medusa Halo parts showing a move to LPDDR6 and as much as 80% more bandwidth.

Holding the line on price

Agentic AI is also something of a pricing tool for vendors, beyond describing a workload. A 192GB workstation sold on the promise of running 300-billion-parameter models locally can hold a four-figure price more comfortably than a mini PC sold on cores and clocks, and it justifies loading the most expensive component in the build to its maximum. AMD's Ryzen AI Halo developer box, a 128GB Strix Halo system, opens pre-orders in June at $3,999 through Micro Center, matching the launch price of Acer's GB10-based Veriton GN100 and the original DGX Spark before its increase.

Apple, the one vendor with the scale to hold priority memory allocation, has moved the other way. It pulled the 512GB Mac Studio configuration from sale, raised the price of its 256GB upgrade, and in May removed several more high-memory Mac mini and Mac Studio options as supply tightened.

This shows us beyond doubt that expanding capacity while holding the line on premium pricing is a choice the AMD and Nvidia camps are making, not one that the market is forcing. Whether buyers accept it rests on whether local agentic inference delivers enough value over cloud services to justify the outlay, on machines shipping with memory capacities that outpace the bandwidth that ultimately determines what that memory can do.

SK hynix will double its memory wafer capacity within five years, SK Group chairman Chey Tae-won told reporters at Computex in Taipei on June 2nd, while repeating his forecast that the AI-driven shortage gripping the memory market will run until 2030. As reported by Bloomberg, Chey declined to put an exact dollar figure on the expansion, saying instead that the company's 2026 spending would climb well above the 30.2 trillion won (roughly $20 billion) it spent in 2025, and confirmed SK hynix has filed to list American depositary receipts in New York this year.

On its own timeline, the pledge will do little to shorten the squeeze. Chey put the lead time for a greenfield fab at more than five years, placing fresh output near the tail end of the shortage window that he’s predicting. This new stance is also a significant departure from his March comments at Nvidia’s GTC conference, where he said a new fab wasn’t planned and that capacity couldn’t be added on demand.

Chey also said the cost of the buildout is difficult to pin down because prices for land, equipment, and electricity keep moving, which is likely why no figure accompanied the announcement. With the company's existing lines already saturated, customers have offered to buy SK hynix's EUV scanners and prefund fab lines as available capacity has fallen to near zero. "Until 2030, there's still some shortage," Chey told reporters

Ultimately, it’s HBM that’s driving the massive gap between wafer supply and demand. HBM consumes far more wafers per bit than standard DRAM and carries the industry's highest margins, so capacity keeps tilting toward them. SK hynix holds about 57% of the HBM market and 32% of global DRAM, and Chey has said he wants the company to become a major HBM supplier for Nvidia's Vera Rubin platform and is seeking more manufacturing partnerships in Taiwan beyond TSMC.

But buyers aren’t waiting on new fabs for relief. TrendForce projected DRAM contract prices to rise 63% in the second quarter after climbing roughly 95% in the first, and DDR4 spot pricing ran up around 2,200% over 12 months before a recent decline. Even with capacity doubling, outlooks across the next five years are unchanged, and the market is likely to stay tight for the rest of the decade as things currently stand with AI demand.

If you thought DDR5 was already too expensive right now, Cooler Master and G.Skill have a surprise in store for you. The two manufacturers are partnering up to make "MasterDIMM" — a new line of DDR5 memory kits that come with active cooling and a promise of temperatures that are up to 15 degrees cooler than conventional RAM. These sticks feature a thick heatsink with a fan built-in to emulate a blower-style cooler you see in some GPUs. There are no pricing or availability details yet, but it's not hard to imagine these kits, made for "demanding next-gen systems," will be even pricier than regular DDR5.

MasterDIMM will be properly shown off at Computex 2026 in just a few days, so expect more information then. For now, we know that these are high-end UDIMMs (desktop) that will push the envelope for DDR5 RAM in terms of style. The design of these sticks is very classy, sporting a black and gold aesthetic with part of the copper heatsink visible on the front, along with the fan on the other end. Naturally, they're a little larger than regular DIMM's, so motherboard compatibility remains to be seen.

There are two RGB strips running along the top, also flanked by gold accents, and the whole thing looks oddly similar to a fancy M.2 SSD. The RAM itself is made by G.Skill, while the heatsink is designed by Cooler Master. MasterDIMM will offer speeds up to 6,000 MT/s at CL26 latency with AMD EXPO, or up to 8.400 MT/s on Intel platforms via XMP 3.0. Capacities will scale up to 128GB at the top-end through 64GBx2 configs.

The companies claim the fan inside is whisper-quiet, delivering optimal cooling at just 35 decibels. That's the same noise level as a library. The heatsink and fan combo can drop temperatures by up to 15 degrees Celsius, which would be a remarkable improvement if proven true in testing. Keep in mind that DDR5 RAM, in general, is already rated for operation at up to 95°C, but it stays between 70-80°C in most cases.

Now, this is not the first time someone has put a massive cooler, or even two fans, on some RAM, but it's the most mainstream version of such a combination yet. Both G.Skill and Cooler Master are huge names in the PC hardware industry, so it'll be interesting to see how well this product does. Of course, that depends on pricing, and DDR5 prices are still out of control despite some semblance of the AI boom slowing down as of late.

More than a decade ago, Corsair tried to actively cool memory with its Vengeance Airflow modules, and vendors have tried to fit their DIMMs with creative heatsinks forever. Last year, we even tested a Silverstone AIO that could attach optional fans to itself to cool your memory and SSD.

SK hynix announced iHBM today, a memory heat management technology designed to enhance AI system performance. The thermal packaging solution improves heat dissipation by integrating ICEs (integrated cooling elements) directly into the HBM package. SK hynix says the result is an over 30% reduction in thermal resistance, “ensuring stable operating characteristics even in high-temperature and high-load environments.”

The iHBM architecture embeds non-conductive silicon cooling elements directly into the Die-to-Die Physical Layer (D2D PHY), the critical, high-speed connection interface between the HBM base die and the AI processor, which is prone to high temperature spikes as a result of extreme data traffic. By placing cooling elements in this layer, SK hynix mitigates the severe thermal throttling that cripples AI system performance during heavy computational workloads.

The company believes that structurally preventing thermal throttling will enable next-generation memory layers (targeted for future generations like HBM5) to scale to higher stack heights and sustain maximum data transfer speeds under the heavy computational loads of AI data centers.

“iHBM is the optimal solution for minimizing heat generation developed by combining memory design capabilities and advanced packaging technology,” said SK hynix Vice President Lee Kang-wook. “We will proactively provide the value customers need in the AI environment and further solidify our leadership in AI memory.”

SK hynix plans to apply iHBM technology from next-generation products, such as HBM5, to meet the thermal management requirements of high-performance computing (HPC), AI data centers, and other ultra-high-density and ultra-high-bandwidth environments, thereby improving overall system stability and efficiency.

Heat management is one of the biggest challenges facing HBM (High-Bandwidth Memory) technology. Unlike conventional memory, HBM achieves massive bandwidth by vertically stacking multiple DRAM dies, dramatically shortening the distance data must travel and enabling far higher transfer speeds with better power efficiency.

To minimize latency and feed AI processors fast enough to avoid bottlenecks, HBM is placed extremely close to the GPU or AI accelerator on the same package, connected through a high-speed silicon interposer. However, this dense arrangement also creates severe thermal problems.

The Die-to-Die Physical Layer (D2D PHY) — the ultra-high-speed interface linking the processor and HBM stacks — continuously moves terabytes of data per second. As thousands of signaling lanes and billions of transistors switch at extremely high frequencies, switching losses, leakage current, and electrical resistance generate substantial heat.

The problem is compounded by the processor itself, which already produces enormous amounts of heat. With the HBM stacks packed tightly around the processor, heat accumulates rapidly in a very small area. When temperatures exceed safe limits, the system automatically reduces clock speeds and voltages through thermal throttling to prevent physical damage, lowering overall performance.

SK hynix's new iHBM approach attempts to tackle the problem at the structural level. Unlike conventional HBM cooling designs that primarily dissipate heat indirectly through the core die and surrounding package structures, the company's iHBM architecture instead places Integrated Cooling Elements (ICEs) directly around the D2D PHY region — the exact zone where thermal concentration is most severe. This approach creates a dedicated dissipation path at the source, reducing overall thermal resistance by 30% and allowing the chip to maintain stable operation under the high-temperature, high-pressure conditions that dense AI workloads demand.

SK hynix says the technology can be manufactured at scale using its existing Wafer Level Packaging (WLP) process, which is built on its Mass Reflow Molded Underfill (MR-MUF) packaging technology already used in commercial HBM products. The design is also architecturally compatible with existing System-in-Package configurations, meaning customers can integrate the new thermal capability without major redesigns.

A Redditor has caused a stir by coaxing a workstation build using Optane PMem DIMMs as RAM to run a 1-trillion-parameter LLM. APFrisco explains in a mini tutorial/guide on the Local LLaMA subreddit how they bought some used Intel Optane Persistent Memory, acquired relatively cheaply second-hand, to “run a 1 trillion parameter model (in this case Kimi K2.5) locally at ~4 tokens/second” on their Xeon workstation.

Central to the headlining feat was the Redditor’s sourcing of six Optane PMem (DCPMM) sticks. The discontinued memory format was designed to bridge the DRAM-SSD divide. While the 768GB of Optane (6x 128GB) does indeed offer far lower latency than the best NVMe SSDs, it is still two or three times slower than DRAM. These characteristics are still rather sweet for LLM inference frameworks, and the second-hand price was “much less than what the equivalent DRAM capacity would cost.” But, alas, Optane is dead, so this is an exotic solution.

APFrisco’s hardware specs were given as follows:

• Intel Xeon Gold 6246 CPU
• Tyan S5630GMRE-CGN motherboard
• Asus Dual GeForce RTX 3060 OC 12GB GPU
• 6x 32GB Samsung 2666MHz DDR4 ECC DRAM sticks
• 6x 128GB Intel Optane DCPMM PC4-2666 NMA1XBD128GQS persistent memory modules
• Western Digital WD SN850X 2TB M.2 2280 NVMe SSD
• ASRock Steel Legend SL-850G 850W 80 PLUS GOLD & Cybenetics Platinum Fully Modular Power Supply
• Silverstone SST-GD08B (Black) Grandia Series Home Theater PC Case

The build was configured with the Optane in memory mode and the Samsung DDR4 as cache.

The software side of the equation relied on the aforementioned Kimi K2.5’s mixture-of-experts architecture. APFrisco used a hybrid GPU/CPU inference methodology with llama.cpp. Also, to optimize processing, the routing components were shoehorned into the 12GB GPU using llama.cpp’s 'override-tensor' flag.

The Redditor is rather proud of the resulting ~4 tokens per second performance. “Given the fact that this is a trillion-parameter frontier-class model running on such a limited hardware budget, I would consider it to be a great success,” writes APFrisco. They go on to lament Intel’s withdrawal of Optane products.

If you are interested in this rig rundown and what it achieved in terms of local LLM inference, you can find some more details about the configuration in the source post. Furthermore, APFrisco sticks around in the comments to answer questions. They also appear to benefit from recommendations about how to achieve even better results, given the foundation they have laid.

The bigger picture, though, seems to be that there is room for a memory product in the chasm between DRAM and SSDs, particularly for LLMs. Many expect that the gap will soon be bridged by the CXL (Compute Express Link) standard, which promises huge pools of affordable, byte‑addressable memory for these kinds of workloads.

In late 2024, China-based ChangXing Memory Technologies (CXMT) began producing DDR5 modules aimed at the consumer market. Since then, the company has even laid out a roadmap that currently puts its max DDR5 capabilities at 8,000 MT/s across 16 Gb and 24 Gb densities. Fast forward to today, and we're finally seeing Chinese DRAM in a mainstream product, more specifically, a Corsair Vengeance DDR5 16GB stick purchased in China by @wxnod, running at 6,000 MT/s with CL36 speeds.

We can see the "CMK5X16G3E60C36A2-CN" part number, where "CN" denotes it's a China-exclusive kit. It's still certified for both Intel XMP and AMD EXPO (since it runs beyond JEDEC speeds), and we also see the rest of the specs printed on the label, such as the timings and operating voltage. There are also "UKCA" and "CE" signs that indicate this kit meets European and British standards for sale in those regions.

The post above shows CPU-Z screenshots clearly revealing that the DRAM powering this kit is from CXMT and not one of the big three memory makers: Micron, Samsung, or SK Hynix. All of those companies are busy selling out their entire production lines to data centers instead, so it makes sense that Corsair is shifting around its suppliers. CXMT might seem like an unusual choice, but the company is well-positioned for this transition.

See, unlike the major DRAM manufacturers, CXMT doesn't even possess the latest cutting-edge tools to produce memory for hyperscalers. The company isn't tied to any data center contracts, so it has, relatively speaking, empty production lines just waiting for customers. And that clientele CXMT seems to be targeting is regular consumers left in the dust by the rest of the RAM industry.

Until now, CXMT has only really sold to local businesses and lesser-known brands, but being featured in a Corsair kit marks a major shift in the landscape. Even if this kit is exclusive to Chinese markets, it's still made by one of the biggest names in consumer memory — a name that people trust. Besides, most customers won't actually check what factory their DRAM chips are coming from as long as the specs seem up to par.

Speaking of which, we're looking at a DDR5-6000 CL36 kit, which is not the fastest, but it's plenty for gaming and daily tasks. There's generally less than 5% difference between a CL30 and CL36 kit at 6,000 MT/s, so if you're saving a lot of money going for the slower latency, it might be worth it in some cases, such as, you know, a RAM shortage. That brings us to the main question: Is this RAM actually cheaper?

There was no explicit mention of a price, so for all we know, Corsair is sourcing cheaper memory from CXMT but still selling it at the same inflated rates. If supply from Samsung, SK Hynix, and Micron is tight, it makes sense that DRAM bought from those companies would be expensive, but CXMT-made DDR5 should be significantly more affordable for it to matter and make an actual dent in the market.

Moreover, there would be concerns about how stable these modules are and whether they're fit for overclocking. Since a brand like Corsair is backing them up, a customer would expect it to perform just as well as any other Corsair kit. Another post from the same OP shows a similar KingBank-branded DDR5-6000 kit overclocked to 8,000 MT/s with 44-56-56-128 timings at around 1.5V, so there's clearly some potential here.

PC memory manufacturer Team Group has agreed to settle a class action lawsuit to the tune of $1.1 million over allegations it advertised deceptive speeds for its DDR3, DDR4, and DDR5 memory products purchased in the U.S. between May 3, 2020, and April 8, 2026. Similar to a recent case involving G.Skill, the lawsuit claims that consumers were led to believe that the advertised speeds on Team Group’s memory kits could be achieved out of the box without requiring BIOS tweaks or overclocking profiles.

It was alleged by the plaintiffs that the company marketed its RAM kits using rated speeds that could only be achieved after enabling XMP or EXPO memory profiles via the motherboard BIOS/UEFI menu. Team Group has denied all allegations of wrongdoing and says that its “products were appropriately labeled and performed as represented.”

An individual can claim as part of the settlement class if they purchased Team Group DDR3, DDR4, or DDR5 memory products while living in the United States between May 3, 2020, and April 8, 2026. The settlement only applies to individual consumers, while purchases made directly by a business, such as a company, LLC, corporation, or partnership, do not qualify for compensation. However, if you personally bought the memory as an individual consumer, you may still qualify even if you later used the product for work or business purposes.

As there is no fixed amount out of the total settlement fund of $1.1 million, the money will be divided among every individual who submits a valid claim. Payments will be made based on how many eligible Team Group DRAM products each person claims. The settlement also clarifies that one may claim compensation for up to five memory products per household without providing proof of purchase, while claims beyond that require supporting documentation.

Eligible customers can head to the Claim Hub website and follow the instructions carefully to file an official claim. You can also submit an objection or exclude oneself from the lawsuit completely. The deadline for the claim is currently set for July 7, 2026.

Earlier this year, G.Skill settled a similar $2.4 million lawsuit involving its DDR4 and DDR5 memory products. Plaintiffs argued that advertised speeds above JEDEC defaults required additional BIOS adjustments and overclocking settings that were not clearly disclosed on packaging or product pages. Most memory kits for modern PC platforms ship with conservative default speeds based on JEDEC standards, while higher advertised frequencies, such as DDR5-6000 or DDR5-7200, require users to manually enable XMP or EXPO profiles. The lawsuit argued that average consumers may not realize these additional steps are necessary to achieve the marketed performance levels.

G.Skill was also required to change its packaging and be clearer about overclocking and BIOS adjustments as part of its agreement. The Team Group settlement doesn't seem to include any such provisions and is rather purely offering a payout to affected buyers.

Researchers at the University of Tokyo say they have demonstrated a non-volatile magnetic switching device capable of flipping states in just 40 picoseconds while consuming unusually little power and generating far less heat than many previous ultrafast switching approaches — potentially addressing one of the biggest problems facing modern AI hardware: the enormous energy and cooling demands created by moving and storing data.

The researchers built the device using an antiferromagnetic material called manganese-tin (Mn₃Sn), then showed that ultrashort electrical pulses could reliably switch its magnetic state while retaining the stored information after power removal. They also demonstrated similar switching using ultrafast photocurrent pulses generated from a telecom-band laser and photodiode, effectively converting optical signals directly into memory-writing electrical pulses.

At its most fundamental level, modern computing is really the science of switching physical states. Every operation inside a computer — whether running a game, training an AI model, opening a browser tab, or loading a file from storage — ultimately involves billions or trillions of tiny physical state changes. Transistors switch on and off, memory cells charge and discharge, cache states update, data moves through interconnects, and storage cells trap or release electrons.

Those switching events are what physically represent binary information. The problem is that switching states requires energy, and almost all of that energy eventually becomes heat. That reality is becoming increasingly problematic in the AI era. Modern AI accelerators process enormous volumes of data. But much of their power consumption comes not just from computation itself, but from constantly moving and refreshing information between caches, memory, storage, and interconnects. As GPU clusters scale to hundreds of thousands of accelerators, power delivery and cooling are becoming some of the industry's biggest bottlenecks.

Current memory technologies all handle switching differently, but each comes with major tradeoffs. DRAM — the main system memory used in PCs, servers, and GPUs — stores information as electrical charge inside tiny capacitors. A charged capacitor represents one state, while a discharged capacitor represents another. However, those capacitors constantly leak charge, meaning the system must repeatedly refresh the memory cells thousands of times per second simply to preserve data. That constant re-switching consumes significant power and generates heat, even when systems are relatively idle.

Flash memory used in SSDs avoids that problem by trapping electrons in floating-gate structures, which retain data without continuous power. On the other hand, changing those states is slower and more energy-intensive, making flash unsuitable for high-speed working memory.

SRAM, used inside CPU caches, achieves extremely fast switching using transistor feedback circuits that continuously maintain state. But SRAM consumes significant chip area and power, making it expensive and difficult to scale to large capacities.

The industry has spent decades searching for a kind of "universal memory" that could combine the speed of SRAM, the density of DRAM, the persistence of flash, and low power consumption. That challenge becomes even harder at ultrafast timescales, where many experimental switching technologies partially rely on brute-force heating to destabilize and flip states rapidly.

The faster the switching, the more severe the thermal problem often becomes. Several previously demonstrated picosecond-scale switching approaches cited in the paper involve temperature rises of several hundred Kelvin during operation.

The Tokyo researchers are instead pursuing a radically different switching mechanism through a field known as spintronics. Instead of storing information as an electrical charge, spintronic devices store information using magnetic states.

Conventional magnetic memories typically use ferromagnets — materials such as iron, cobalt, or nickel in which magnetic moments align in the same direction. The new device instead uses an antiferromagnetic material called Mn₃Sn, where neighboring magnetic moments largely cancel one another out.

Researchers are interested in antiferromagnets because they can potentially switch much faster, resist magnetic interference more effectively, and scale to smaller dimensions without generating large stray magnetic fields.

The researchers fabricated layered Mn₃Sn/Ta structures on silicon substrates and then used ultrafast electrical pulses to flip the material between two stable magnetic configurations, representing binary states.

Crucially, the switching mechanism is not primarily based on heating the material. Instead, the pulses generate what is known as spin-orbit torque — a process that transfers angular momentum directly into the magnetic structure itself, flipping the magnetic state without requiring extreme temperature spikes.

That distinction is the paper's central claim. The research is not merely about creating a new kind of memory, but about finding a potentially more energy-efficient way to switch digital states themselves. Currently, almost all electrical energy consumed by computing hardware eventually becomes heat. Modern AI infrastructure is already hitting serious power and cooling limits as GPU clusters scale to hundreds of thousands of accelerators.

The team's device reportedly achieved switching in just 40 picoseconds — roughly 1,000 times faster than typical nanosecond-scale memory switching. Normally, pushing switching speeds into the picosecond regime causes heat generation to spike dramatically, as systems often rely partly on intense transient heating to destabilize states quickly enough for reversal.

However, simulations in one device configuration showed temperature rises of only about 8 K (14.4°F) during switching, supporting the researchers' claim that the mechanism relies primarily on direct angular-momentum transfer rather than brute-force thermal switching. This also confirms that the Mn₃Sn device may avoid much of the heat problem that has plagued earlier ultrafast memory research.

The optical switching demonstration may also prove important for future data-center architectures. The researchers generated 60-picosecond photocurrent pulses using a telecom-band laser and photodiode, then used those pulses to switch the device's magnetic state.

That could eventually align with broader industry efforts toward optical interconnects and silicon photonics, where hyperscalers are increasingly seeking ways to move information using light rather than conventional electrical signaling.

If technologies like this ever become commercially viable, they could theoretically reduce memory refresh overhead, lower cooling requirements, reduce idle power draw, and potentially blur the distinction between memory and storage. For personal computing, that could someday translate into systems that retain working memory contents without standby power, resume instantly, and generate less heat. For hyperscale AI infrastructure, the implications would center more around power efficiency and cooling reduction across massive GPU clusters.

For now, however, the technology remains firmly experimental. The current devices are tiny laboratory structures rather than manufacturable memory chips, and the paper notes that the present implementation still requires an external bias magnetic field for deterministic switching — a major practical limitation for commercial hardware.

Manufacturing scalability, endurance validation, cost competitiveness, and integration with existing CMOS manufacturing processes also remain unresolved. The history of computing is full of promising "next-generation memory" technologies that never displaced mature DRAM or NAND ecosystems. Even so, the work highlights the growing reality in the computing industry that future performance gains may depend less on shrinking transistors and more on reducing the energy required to physically switch, move, and store information.

Don't walk, run (to your PC) and hit that order button on a deal that cuts the cost of buying a new stack of DDR5 memory modules by $70. The folks at B&H Photo have slashed the price of this Corsair Pro Overclocking DDR5 32GB (2 x 16GB) to just $329.99 right now. With RAM prices still impacted by the AI-fueled boom, a $70 price cut on RAM, given current market prices, is one you can't ignore, but you'll need to be quick, as this deal is likely to run out soon.

● Check out this deal at B&H Photo

Unfortunately, the ultra-low prices we saw last year are a distant memory (no pun intended). The term skyrocketing might be a cliché, but it's unfortunately true, with RAM like this significantly more expensive than it would have been 12 months ago. Those old prices aren't coming back any time soon, with hardware manufacturers like Framework warning about even more price rises this year. Right now, $239.99 is a bargain, with the next-best option with equivalent speeds costing you at least $40 more, and prices likely to go up, not down in the next 12 months.

This particular kit comes with two 16GB modules, with rated speeds of 6,400 MT/s. That's a big speed jump over older DDR4 memory, where you'd see max speeds of 3,600 MT/s. As our Corsair Pro Overclocking DDR5-6400 review shows, however, you can push this RAM even further, as it's overclockable using Intel XMP and AMD EXPO OC profiles on motherboards that support it. For enthusiasts, you can push this RAM to speeds of 6,600 MT/s or higher, making it an ideal option for seriously powerful gaming PC builds.

You're getting CAS latency and memory timings of 38-40-40-84 with this Corsair Pro Overclocking RAM kit, operating at a voltage of 1.35V. Unlike some of the flashier RAM kits on the market, including Corsair's own Vengeance models, you're not getting any RGB with this kit. It instead comes in a simple white colorway, with a solid aluminum integrated heat spreader to help keep things cool during heavy workloads.

It's true: this isn't a record-breaking deal, but that's missing the point. What it is, however, is a great deal given the current market. A $70 price drop, and one that makes it the cheapest 32GB DDR5 RAM kit on the market right now, is worth a buy if you're thinking about upgrading your PC or building a new one.

You won't find better, faster RAM as cheap as this $329.99 Corsair Pro Overclocking 32GB RAM kit from B&H Photo. This isn't a no-brand kit, either, so you'd be buying high-quality and reliable RAM at a price that, given the tough market conditions, is pushing against the grain. Past experience tells us that these discounted RAM kits sell out fast, so if you're interested, you should order it before it sells out.

If you're looking for more savings, check out our Best PC Hardware deals for a range of products, or dive deeper into our specialized SSD and Storage Deals, Hard Drive Deals, Gaming Monitor Deals, Graphics Card Deals, Gaming Chair, Best Wi-Fi Routers, Best Motherboard, or CPU Deals pages.

It's a bad time to build a PC right now, given all the component shortages and political tensions that seemingly never leave sight of uncertainty. Bad times call for desperate measures, and that's precisely the window of opportunity that scammers are waiting to bank on. As such, reports of fake DDR5 memory circulating in Asian markets have begun to pop up, with some scammers replacing entire modules with counterfeit, hollow plastic chips. You can see the clever counterfeits by expanding the tweet below.

The post above from Japanese user TAKI shows laptop DDR5 memory (SODIMMs) with some of these fake chips. The sticker on the RAM says it's a Samsung stick, but the modules are clearly from SK Hynix. They also look a bit weird with the edges looking abnormally rounded off, exposing a white material around the perimeter. If you look closely, one of the ICs on the PCB is also knocked out of place, suggesting these components have been dropped on the board rather prematurely.

Looking closer at one of the DDR5 modules, it's clearly been shaved off; that explains the white perimeter. But there's nothing inside because these chips are just made of plastic or fiberglass with no circuitry inside. The second giveaway then becomes clear — since these are literally just bits of plastic, the SK Hynix part number markings are also fake, printed on top to make the RAM look convincing.

These counterfeit memory kits are common on secondhand marketplaces, such as Mercari and Yahoo Auctions, and some are listed as broken. The description on one of these listings outlines a whole story about where these sticks come from, and that the buyer shouldn't purchase them expecting a functional product.

People looking to make a quick buck would pounce on such ads, or even worse, scammers would buy these lots to actually resell as working sticks to unsuspecting customers. And these are SODIMMs with no heatspreaders, so you can actually see the part numbers and likely make out the fact they're not authentic. For desktop memory that does come with heatsinks, you're basically out of luck until you actually test it.

The sellers peddling these fake DDR5 modules also accept no returns, which is common for "as is" purchases. Another possibility is that these sticks are coming from Amazon bait-and-switch scams where people buy an authentic product, swap it for a fake (or nothing at all), and return it, from where it ends up in a returns warehouse. It then gets picked up by a larger seller who might sort and sift through the lot to identify valuable items like RAM and put them up on the aftermarket.

Ultimately, the point remains that you should be extremely vigilant when buying used products, especially in times like these. If a deal is too good to be true, it most likely is. Purchase from reputable stores and vendors that accept returns or refunds, or at least those who'll exchange faulty items for you. While memory is the most price-hiked PC hardware category right now, similar scams run through GPUs and even CPUs.

Make sure to tally any product numbers with authentic ones you find online and thoroughly test the components to ensure they work. The latter practice should be enough to spoof out any bad actors, but try to secure a warranty as well, just in case.

In Samsung’s full earnings report released on April 30, 2026, the company’s memory chief Kim Jaejune warned that “significant shortages” across memory products are expected to continue through at least 2027. According to the company, demand fulfillment rates have fallen to record lows as customers rush to secure future supply, SCMP reports. The warning closely mirrors comments made by “rival” SK Hynix during its earnings call just a week earlier.

Together with US-based Micron Technology, Samsung and SK hynix control well over 90% of the global DRAM market. When two of the world’s three biggest memory suppliers simultaneously warn of multi-year shortages, it wouldn’t be too out of place to worry.

The shortages are being driven largely by the need for artificial intelligence infrastructure. Modern AI systems require enormous amounts of high-speed memory to continuously feed data to GPUs and accelerators. At the center of this demand surge is HBM (high-bandwidth memory), a vertically stacked form of DRAM designed to deliver extremely high bandwidth while remaining physically close to processors.

HBM has become critical for AI accelerators. However, the technology is difficult and expensive to manufacture, requiring advanced die stacking, precision bonding, and sophisticated packaging techniques. As a result, supply is limited, and demand is outpacing manufacturers' ability to build capacity.

While the shortage is driven primarily by HBM demand, its effects are beginning to spill over into the broader memory market. Because HBM itself is a form of DRAM, manufacturers are increasingly reallocating manufacturing capacity, engineering resources, and investment toward high-margin AI memory products. That shift risks tightening supply for more conventional DRAM products used in servers, PCs, and mobile devices. Enterprise SSD demand is also rising as AI data centers require massive storage infrastructure alongside compute hardware.

Ironically, the industry is simultaneously searching for alternatives because current memory architectures consume enormous amounts of power. We recently reported on efforts to develop next-generation memory technologies such as 3D X-DRAM and ZAM (Z-Angle Memory), which aim to reduce power consumption and ease scaling limitations.

Yet despite massive investment into future alternatives, demand for the existing memory technologies remains overwhelming.

Samsung reportedly stated that some customers have already secured supply allocations through 2027. Earlier this year, SK Group chairman Chey Tae-won suggested that AI-related memory demand pressure may persist even toward 2030.

The shortages are not necessarily bad news for the companies themselves.

Samsung’s semiconductor division posted 53.7 trillion won ($36.1 billion) in operating profit during the first quarter of 2026, accounting for roughly 94% of the company’s total quarterly profit as soaring AI memory demand drove record sales. Meanwhile, SK hynix reported record quarterly revenue of 52.6 trillion won ($35.5 billion), and operating profit of 37.6 trillion won ($27.8 billion), fueled largely by booming HBM sales for AI infrastructure.

Part of the problem is cyclical. The memory industry has historically swung between oversupply and shortages. However, analysts increasingly believe this cycle is different, as growth in AI infrastructure is consuming hardware at unprecedented rates.

To address the crisis, the companies are aggressively expanding production capacity and increasing investment in advanced packaging and memory fabrication. According to the Korea Times, recent regulatory filings show that Samsung Electronics invested 465.4 billion won in its Xi’an memory chip plant in 2025, a 67.5% year-over-year increase. SK hynix also significantly increased spending, investing 581.1 billion won into its Wuxi facilities and 440.6 billion won into its Dalian operations.

However, semiconductor fabrication plants and advanced memory packaging facilities take years to expand and ramp up, meaning supply growth cannot catch up to the pace of AI-driven demand.

The memory crunch is joining a growing list of resource shortages emerging from the AI explosion.

GPU shortages have already become severe across parts of the industry. Earlier this month, we reported Intel’s confirmation that extreme demand had become so intense that customers were even buying chips that might previously have been discarded or treated as low-value products.

Power is becoming another major bottleneck. AI data centers are consuming enormous amounts of electricity, forcing technology companies to seek increasingly unconventional energy solutions. Earlier this month, Meta Platforms backed plans involving space-based solar power systems that could theoretically beam solar energy back to Earth to help support future AI infrastructure demands.

Dr. Semiconductor is back in his shed, and this time he’s checking whether Joe Public can DIY themselves out of the DRAM crisis. In the video embedded below, you can see the good doctor go through the semiconductor process steps required to make an array of memory cells in a backyard shed cleanroom. This is the “first time ever RAM has been made at home,” boasts our hero.

RAMageddon isn’t the only issue affecting PC DIYers and the industry in general. Dr. Semiconductor mentions the AI-industry-fueled RAM price disruption being driven by the big three players (but there are others) not being able to keep up with demand. We are seeing similar effects on storage, GPUs, and some reckon CPU supplies will also begin to be impacted.

With the existing industry incapable of addressing consumer RAM needs at attractive prices in 2026, the TechTuber asks, “I turned a shed in my back yard into a class 100 semiconductor cleanroom… but the question is, can I make my own RAM?”

After the intro, Dr. Semiconductor gives a brief description of how computer memory works, and how it is largely made up of huge arrays featuring oodles of capacitors and transistors.

Moving on to the practicalities of the job at hand, the good doctor begins by snipping a couple of silicon chips from a large sheet. This is the beginning of the preparation and cleaning stage of the chipmaking process.

Next up, we move to the initial patterning stage. A layer of oxide is built on the surface of the silicon in a high-temperature furnace. It is estimated that this layer is 330nm thick. On top of this layer, an adhesive layer and photoresist film are applied. UV exposure projects a design mask onto this newly created surface, which allows a developer solution to wash away the areas that have been hit by the light rays.

The source and drain of the transistors in the design are formed in the following steps. This involves more layer etching, doping exposed silicon to make it highly conductive, then annealing the chips to push the doping agent deeper.

Several more carefully targeted deposition and erosion steps later, we are ready for the metallization of the silicon chip. A tiny stencil is used to accurately spray the sample with aluminum, the excess stripped away, and the fully layered and formed chip is at last ready for some tests!

Checking the results

The freshly fabricated DRAM cells are so small that wires can’t be used to hook them up to test machinery by the DIYers. Micromanipulator probes are precisely positioned instead. The good news is that Dr. Semiconductor was pleased with his finished DRAM chips, as cells were measured to offer a hobbyist sweet spot of 12pF capacitance.

At the end of the video, the doc teases that he’s going to build on this significant, though admittedly small-scale, achievement. He’s looking to prepare a much larger array of finished memory cells and says that they will be prepared to “hook up to a PC.” Stay tuned for the PC-scale practical implementation, folks.

We reported on Dr. Semiconductor's creation of this garden shed-based cleanroom back in March.

A couple of days ago, Intel, TeamGroup and ASRock came together to unveil the "HUDIMM" spec for DDR5 RAM. HUDIMM use a single 32-bit subchannel instead of populating a 64-bit wide bus with two 32-bit channels. This effectively cuts bandwidth and capacity in half but allows for cheaper DDR5 that uses less ICs per stick. Today, new testing done by HKEPC, with the help of Asus, confirms exactly that — HUDIMM will incur an almost 50% bandwidth penalty, reducing performance significantly.

First things first, HKEPC did not get their hands on an actual retail HUDIMM kit manufactured by TeamGroup; instead, they used standard DDR5 RAM but taped half of the contact points. This allowed for one of the 32-bit subchannels to become unrecognizable, hence simulating HUDIMM. A member of Asus' R&D team has already tried this before the announcement, and we mentioned it in our previous coverage.

This new testing is more substantiated and was done on an Asus ROG Maximum Z890 Extreme motherboard, using an Intel Core Ultra 9 285K. The outlet "matched the BIOS that supports HUDIMM modules" because, unlike a retail 1x 32-bit stick, the modified 2x 32-bit RAM's SPD will still tell the memory controller it's supposed to have a 64-bit wide bus. The PC will fail to initialize (POST) otherwise and be stuck with training errors.

We start with a single rank 16 GB 7,200 MT/s stick that showed up as 8 GB. In AIDA64, it achieved read speeds of 32,447 MB/s, write speeds of 25,195 MB/s, and copy speeds of 26,894 MB/s, with an 87.7 ns latency. In contrast, the same stick when untaped hit 58,913 MB/s read, 48,800 MB/s write, and 52,648 MB/s copy speeds. That's essentially double the throughput across the board, but latency was the same at 85.7 ns.

As expected, disabling one of the 32-bit subchannels slashes the numbers in half pretty consistently. You get to build cheaper sticks that require only 4 ICs instead of the usual 8 for a 16 GB DIMM, but it clearly comes at a cost. The standard 16 GB stick is almost at 60 GB/s of effective bandwidth while the simulated 8 GB HUDIMM stick only reaches 32 GB/s. That's the kind of discrepancy you'll notice.

Switching gears to a dual channel setup, HKEPC put 2x 16 GB 7,200 MT/s sticks on the motherboard, which showed 32 GB in the standard config, but only 16 GB when taped. The same story follows; half of the bandwidth is gone when simulating HUDIMM. We drop from 106 GB/s read speeds to just 58 GB/s, the write speeds go from 93 GB/s to 48 GB/s, and the copy speeds fall from 97 GB/s to 51 GB/s. The latency remained identical.

The HUDIMM numbers here basically match the performance of a regular 16 GB stick running in single channel, which is to be expected. It's simple math, really. Across the board, we're just halving the bandwidth and capacity just to be able to make cheaper DDR5. The performance hit is significant, but since HUDIMM is aimed at budget gamers and business users, perhaps the tradeoff will be worthwhile for some.

One claim from the announcement that HKEPC didn't check was asymmetric dual channel support — combining HUDIMM with regular DDR5 with 2x 32-bit subchannels is supposed to drastically improve performance. ASRock said that using an 8 GB HUDIMM stick with a standard 16 GB stick nets more bandwidth than a single 24 GB UDIMM (despite having the same capacity). The 24 GB stick on its own is apparently more expensive to manufacture, too, so this is a sort of "best-of-both-worlds" pitch.

40 years ago today IBM was in the news for becoming the first computer company to make use of 1-megabit memory chips. Thus, the megabit memory era began with an American company and its Vermont fab leading the way, pushing back stubbornly against the seemingly unstoppable Japanese takeover of the memory market.

IBM’s 3090 (Sierra series) mainframe computers were the first to adopt this new high-density memory. However, the New York Times reported the occasion as “a rare, if fleeting, moment of glory,” as it thought the Japanese semiconductor industry would inexorably rise beyond its already impressive 75% market share.

The NYT’s take contrasted with IBM’s triumphant tone. “This is a signal of our semiconductor technology leadership,” said IBM SVP, Jack D. Kuehler, at the time. He went on to emphasize how these DRAM chips were built in the USA. Some of the newspaper’s cynicism came from the fact that it already knew the likes of Fujitsu, Hitachi, Mitsubishi, NEC, and Toshiba were busy sampling their own 1-megabit DRAM chips. Once they were satisfied and moved them to mass production, it was expected the Far East tiger economy would roar back to pole position.

If we turn the clock back to 1986, most computing devices in use might have packed memory chips of the 64 kilobit variety. The state-of-the-art Japanese memory tech at the time was churning out 256 kilobit memory chips. In that context IBM’s 1-megabit chips, fabricated on a 1.2 micron process, were very impressive, bringing a leap in both density and efficiency.

The arrival and establishment of 1-megabit memory chips would enable memory makers to produce 30-pin SIMMs with 1MB RAM capacity, using eight to nine chips in a single-side configuration. Such SIMMs will be very familiar to users of home and personal computers from the mid-1980s to the mid-1990s. Additionally, you would be able to use the same SIMMs in printers, on sound cards, and even graphics cards like the Tseng ET3000 / ET4000, Trident TVGA 8800 / 8900, and Cirrus Logic GD542x series.

Thanks to the AI boom, component prices have skyrocketed in the past few months, leading constituents to come up with creative ways to fight the RAMpocalypse. ASRock has previously introduced a motherboard with both DDR4 and DDR5 slots to help alleviate the crisis, but now it's teaming up with Intel and TeamGroup to launch "HUDIMM" — a new type of DDR5 RAM that can potentially help you save money.

DDR5 memory (UDIMM) typically uses two 32-bit subchannels per stick, requiring enough chips to populate a full 64-bit wide bus. This constitutes a single rank. HUDIMM, or Half Unbuffered DIMM, uses just a single 32-bit subchannel instead, effectively halving the bandwidth and density of the RAM. This allows for cheaper sticks that use fewer modules and are basically "half-rank" in nature.

ASRock has partnered up with TeamGroup to produce some of these first HUDIMM sticks, which are already working on Intel 600, 700 and 800-series motherboards. ASRock is also making HSODIMM, which is basically the same concept but for SO-DIMM (laptop/mobile) instead of U-DIMM (desktop). The company is targeting entry-level users across both segments that don't need the highest performance, or capacity.

According to ASRock, "two sub-channel (2*32-bit)" architecture is beneficial for high-capacity single DIMM module, however, it is not so practical for current PC market." That being said, HUDIMM has asymmetrical dual-channel support at the BIOS level. This should allow you to mix and match different DDR5 RAM to circumvent the single subchannel limitation and achieve higher bandwidth, while still maintaining compatibility.

For instance, an 8 GB HUDIMM stick paired with a 16 GB UDIMM stick will run in proper dual-channel mode with at least 3x 32-bit subchannels active — one from the HUDIMM and two from the standard UDIMM. This Frankenstein 24 GB setup apparently provides better bandwidth than a single 2x 32-bit 24 GB stick, which would be more expensive to manufacture anyway. Though ASRock's press material shows a 90 ns latency, which would be considered high by any modern standards.

Following ASRock's announcement, Asus also chimed in with its own HUDMM showcase on a ROG Maximum Z890 Apex motherboard. A member of the R&D team took two regular 24 GB DDR5 RAM sticks and just taped half of the contact points, effectively disabling half of the ICs. Instead of showing 48 GB in the BIOS, these taped sticks showed only 24 GB.

The company didn't say whether it was partnering up with TeamGroup as well to add official HUDIMM support, but the fact that an engineer acknowledged it could signal something is in the works. If Asus hops on board the standard, an industry-wide push for this would be imminent, and we could genuinely see more affordable DDR5 soon. There is no word on availability or pricing from any side, however.

Some better news today if you're looking for some RAM to fill a system. For owners of an AM5-platform-based PC in particular, today's memory deal offers some of that 6000MT/s speed that hits the sweet spot for AMD CPU performance. It also happens to be the absolute cheapest DDR5 memory kit you can currently purchase at these speeds and capacities, thanks to a double-dipping discount frenzy at Newegg.

Originally priced at $429.99, Newegg has discounted the RAM by $55 to $374.99, and then added a further $90 discount code SSF5767 to bring the price of Team Group's 32GB Team T-Create Classic DDR5-6000 RAM to just $284.99 - the lowest price as of today for 32GB DDR5-6000 kits.

• Grab this deal at Newegg

This is not a gaming-oriented RAM kit! There are no fancy RGB lights or accents on the heat spreaders. This T-Create Classic memory is packaged for professional use, where the design of the aesthetics isn't the primary concern. So the heat spreaders are black with just the logo and naming conventions visible in white. The timings of the RAM are fairly loose, with a CAS latency of 48 and further timings of 48-48-96. Not ideal for a cutting-edge gaming system where every frame counts, but perfect for applications or standard rendering. It will, of course, still function perfectly well in a gaming rig, but just be aware it's not the fastest kit out there.

At one point in time, over a year ago this same RAM kit was on sale for only $87, but that was well before the AI-crunch that saw memory prices quadruple and more in a matter of weeks. Today's deal is a very good deal based on the current climate, but not on historical data. We won't be seeing RAM prices that low again for some considerable time - if ever. If you need RAM urgently, then today's DDR5 Team T-Create Classic RAM deal for $284.99 is a winner.

If you're looking for more savings, check out our Best PC Hardware deals for a range of products, or dive deeper into our specialized SSD and Storage Deals, Hard Drive Deals, Gaming Monitor Deals, Graphics Card Deals, Gaming Chair, Best Wi-Fi Routers, Best Motherboard, or CPU Deals pages.