Following Nvidia's GTC 2026 keynote, where CEO Jensen Huang laid out the company's Vera Rubin architecture and the Groq 3 LPU acquisition, Nvidia VP of Hyperscale and HPC Ian Buck sat down with press for a Q&A session in San Jose.

Buck addressed CPX's delay, the LPU-GPU decode architecture, the Vera CPU’s role in the AI data center, and took questions on the Intel NVLink Fusion partnership. This is a full transcript of a session attended by Tom's Hardware at GTC 2026, and as such, the transcript can occasionally be unclear; we have denoted any moments as such within the copy. Before diving into the transcript, it's worth refamiliarizing yourself with Jensen Huang's keynote from last week, which we've linked below.

CPX delay and LPU decode architecture

Ian Buck: As part of bringing the LPU to market this year with Vera Rubin... we've pulled CPX. It's still a good idea, but in order to dedicate our focus on... optimizing the decode with LPU this year. So we'll be thinking about CPX more in the next generation [and] we're going to execute on decode with LPU now, this year.

A couple other things I wanted to touch on. I also get a lot of questions about how we're doing this. How does the LPU work? How does it work with the GPU? Jensen went over it briefly. This might be more technical, but it's an important point.

The way we do the decode is with a Groq 3 LPU LPX rack. Here we have 256 LPU chips combined with a Vera Rubin NVL72. We're going to do the decode using Dynamo. We've combined the two teams, so Groq's software team has joined our Dynamo team.

We now do not only disaggregation of separate GPUs that you pre-fill and decode, but also the decode itself is actually split between the LPU and GPU. That's what makes the extremely fast token generation economical. We can focus and run the computations that benefit from the fast SRAM of the LPU over here in one layer, and literally the next layer, we can send the intermediate activation state over to the GPUs to do all the attention math, all the softmax, all the routing, all the KV calculations, so that only the LPUs need to have copies of the weights. All the per-query state, all the KV[cache] state, which can get quite large, can operate and stay in the HBMs.

Of course, both processors can do both things. The LPUs can do the attention math. Obviously the GPUs can do the [...] as well. So you can optimize for resiliency.

Dynamo was launched a year ago. It was nicknamed the operating system of [the] AI factory. I will say it's been a roaring success. If any of you got to go to the Dynamo meetups, it was where all of the different users of Dynamo, developers, and customers were all talking. I think we get about 100 GitHub submissions a day now, and about a third of them are coming from external [sources].

Vera CPU positioning

Ian Buck: Definitely happy to talk about Vera. I've actually brought with me the Vera board. This is the Vera module. It's a reference module that we give to system partners, which they can build. It has two Vera CPUs and LPDDR5 memory. So this is a dual-socket server that will operate and run all of the tooling: PyTorch, compiling, SQL queries, as well as for HPC partners.

It is the world's best agentic CPU. It has 88 cores designed so that you can put everything on. Turn on everything. Run them all at full speed. Compile on every core. Browse or render on every core. Python on every core. SQL on every core.

The agentic world needs a CPU that has the world's best single-threaded performance under load, has the world's best memory bandwidth under load, and has the best energy efficiency under load. And it turns out, while it started with a CPU that was an excellent CPU to be married with our GPUs, it makes perfect sense that all the things we needed to do to operate and run AI with our GPUs also makes a great CPU as well.

Journalist 1: Is it safe to say [Rubin] CPX is not going to come out in 2026?

Ian Buck: I'm never going to say no to how fast we can innovate. But I think we can do a lot better [with LPU decode first].

Journalist 2: Jensen was asked about the target market, target use case. And he said he was very careful about how he answered that. He didn't want to position it as a direct drop-in replacement for x86.

Ian Buck: We only are going to build one Vera SKU [...] other people are going to build x86 SKUs [...] the world is not going to be served by one SKU of CPU. And that's not our intention. The intention is that we'd like to solve a workload problem. It's not designed to be a dollar-per-vCPU chip. The amount of technology and, frankly, just the cost to build something that solves that critical workload makes it not for that market; it's a bad gaming chip.

But it is inspired by single-threaded performance. You may not need 88 cores, but it's actually a unique workload because in agentic AI, it's in the critical path for both training and running these models. When you're training a model to code, for example, you start from a model that needs to learn how to code better. And as you're training on Vera Rubin, you're halfway through training, and you say: go write a program that computes the Fibonacci series, or solves a New York Times crossword puzzle.

The AI model will then try to write that program. It then needs to score how well it did. We're not going to run that Python on the GPU. It's a CPU job. The GPU tells the CPU to go run it. So it opens up a sandbox, boots a Linux instance, starts the Python interpreter, executes, compiles, and runs that code. And it's got to score it — how well did it do? Lines of code, accuracy, did it crash? — very quickly. So that all those results from the training run can get back to the GPU in order to do the next iteration of training.

It is in the critical path. There are ways of overlapping. You'll hear about off-policy, where maybe you're training on the N-minus-one data, doing pipelining. But you can't do too much of that because you get model drift.

So what the world is asking for, what it needs, is a really fast CPU that can generate a lot of training data while you're training in order to make the model faster, and never let [the] GPU go idle. This might be a $30 billion, gigawatt data center of GPUs. I'm not going to skimp on the CPU side and have it sit idle, or have the potential of that model come up short because I couldn't run the compilation for too long and had to cut it off.

And then finally, when you actually deploy AI after you're done training, it's not just the AI model. The GPUs are telling the CPUs what to do. They run a SQL query, or they render an image, or they go to a website — all that’s happening on the CPUs. The more tool calling that can happen in fixed power, the more efficient it can be and still maintain these interactive use cases, the more valuable those tokens are.

And lastly, as we get to the agent world, where it's not just us doing chatbot with humans in the loop, we're going to have agents talking to agents at machine speed. You just took humans out of the loop again. That can happen as fast as the computers can compute.

Journalist 2: So, just to be clear, your customers — your ODMs, your Dell, HPs — if they want to build a system, that’s what they’ll get?

Ian Buck: They can build it like this [referring to the reference board brought to the Q&A] or, we will ship the chip itself.

Journalist 2: So, in theory then, your partners could go off the reservation and build a gaming PC, or whatever they wanted to do with it?

Ian Buck: They could. I think they’re all highly motivated to build what Nvidia recommends [and take advantage of] the opportunities with agentic use cases.

Intel NVLink Fusion partnership

Journalist 3: Ian, what's become of the partnership with Intel? Last year, you guys announced a partnership.

Ian Buck: We didn't talk about it in this keynote, but it's progressing. Fusion is a key part of that strategy. It's an IP block plus a chiplet that allows CPUs like x86 to talk across NVLink to our GPUs, or even other accelerators. We've announced multiple partnerships including Intel, and that is definitely progressing. It takes a little while to integrate at the silicon level. Obviously, it's pretty intimate integration. But I think we'll see some more announcements about that shortly.

Journalist 4: Is that partnership going to involve implementing Nvidia IP on Intel process technology? And if so, who's going to be doing the lifting there?

Ian Buck: There's a separation between the manufacturing of who builds the chip or chiplets from the IP integration. The integration I talk about is the IP hooking into the fabric of the processor. This [the Vera module] is actually multiple chiplets. You've got multiple I/O dies, memory interface tiles, as well as the core. If you look at the right angle, you can see one, two, three, four, five, six pieces of silicon come together. So who builds which piece, in which factory, and who does the integration, that's up to the partners. It'll be different for each integration.

Journalist 2: We asked Jensen about that, and he said, look, our bits will be coming from TSMC, the Intel stuff will be coming from wherever they choose to get it.

Journalist 4: I think we're trying to determine, is this a toe in the water to develop Nvidia IP on Intel process technology? I asked Jensen yesterday, and he said he's not excited.

Ian Buck: Obviously those questions are his [Jensen’s] domain. He's a good person to be asking about those questions.

CPX is still a good idea, says Buck

Journalist 4: Looking at the disaggregated architecture that you've implemented with LPX, it does strike me as a situation where it almost makes more sense to pair CPX with LPX racks rather than relying on an HBM-based product like Rubin.

Ian Buck: CPX is still a good idea. It is the opportunity to improve token throughput, to get to that next tier of agents talking to agents that need to run a 1 trillion, 2 trillion parameter model with 400,000 to 500,000 KV input context at token rates of about 1,000 tokens per second, because there's no human in the loop. Input tokens do impact decode speed [...] so 400,000 tokens of context significantly changes the token rate.

When we talk about pivoting from CPX to LPU, that's where the focus was. Right now there's a limit to how many chips [...] we want to do this this year. We want to do this with Vera Rubin. Just because of that effort, this will help those agentic AI frontier labs be able to take that level of intelligence to market.

The volume AI market is offline inference, non-reasoning chatbots, recommendation systems, reasoning chatbots, multimodal, deep research. This [LPX] will not add value to all of those. Everything can be served on [Vera Rubin NVL72]. But that next tier is super important as we turn the corner, and it was important to make sure we had that brought to market this year.

CPX is an optimization, it’s still a good idea [and] it would help break down the cost of the pre-fill stage, but sing these GPUs for the pre-fill portion of the workload is sufficient right now.

LPX paired with Vera Rubin

Journalist 4: If CPX is not coming until 2027, but Vera as a standalone is available sooner than that, is the Vera CPU going to be available sooner [unintelligible] will there be something that doesn’t use AI to compare it with before 2027?

Ian Buck: The LPU racks, Groq, they would run the whole model on the LPU racks alone. That capability exists. But the challenge with doing that is you had to feed not only the entire model, but all of the KV cache and all of the multiple queries on an SRAM chip that only has 500 megabytes. This [Vera Rubin GPU] has 280 gigabytes.

So as models got bigger and contexts got larger, and you just had to keep all of that state around, as well as do all that attention math, it gets costly to have that many LPUs run a trillion-parameter model with the weights plus KV cache. It didn't need to be paired with anything. But it was very expensive. And Jensen showed that in the chart as well. You could get to 1,000 tokens per second, but the economics of doing that with that many chips just don't work.

It has nothing to do with prefill. Pre-fill is just step one, how quickly can you get to your first token. After you've done that, there's pre-fill, GPUs, or whatever you're using in pre-fill. It doesn't matter. Your token rate is all about the number of processors you're using to generate every token after that. So it's not as simple as that. If you just did [Groq 3] LPX, you would need a lot of chips because of all that context.

By combining the LPX with Vera Rubin, we don't need all that. We just do on the LPU what it's good at, which is basically the memory bandwidth, seven times faster than HBM. That lets the mixture-of-experts layers that are inside each expert group run here. The whole rest of the model, all the attention math, can run on the GPUs.

So instead of dozens of racks of LPX, we can deliver that level of performance with just two racks of LPX and one rack of Vera Rubin. And as a result, the token rate gets to 1,000 tokens per second, but the economics go back to the sweet spot. Tokens will be higher value for sure, tens or hundreds of tokens per second rather than thousands. And you can also deploy at data center scale to serve a market. Building it once, serving a few customers in a highly constrained environment is nice, but that doesn't create a market. You have to build an architecture that, by combining LPX with Vera Rubin at one-to-one, or one-to-two, or maybe one-to-four rack ratios, can activate a market to deploy a 100-megawatt data center, a 500-megawatt, a gigawatt data center and serve those models economically.

Journalist 4: And just to be clear, all those benefits you're talking about are on the decode side, after we're over the pre-fill hump?

Ian Buck: Pre-fill [...] it’s just the first token. How long does it take to get the first token? That's all CPX was trying to optimize. It's an important problem, but you can solve it with existing hardware. You can solve it with NVL72, with the older architectures. We can reduce the time to first token, and we can also solve it today by just adding a few more [...] it parallelizes very easily. But it's just the first token. [LPU decode] will increase the speed of every token after that.

LPX chip-to-chip

Journalist 3: I was wondering if you could talk a little bit more about how the LPX is going to connect to other chips, both in the Nvidia ecosystem and outside the Nvidia ecosystem? What about working with CPUs that other companies might make or that customers might procure from elsewhere?

Ian Buck: When we licensed the IP, obviously there was limited stuff that we could change. But there were some last-minute changes that we were able to make to bring it to market. So this is the version [Groq 3/LP30], which is almost largely what it was. We're still using the chip-to-chip signaling that was already there.

Journalist 4: So there's no Nvidia NVLink chip-to-chip on it yet.

Ian Buck: Not yet. As the roadmap shows, it's coming with LP40 in the next generation. That's when we'll add the NVLink interconnect. On the next version, we'll also rev the compute side, and we'll add FP4 capabilities and all the Tensor Core math stuff that we have in our GPUs.

Scale-up rack-to-rack

Journalist 1: Can you walk us through how scale-up rack-to-rack works?

Ian Buck: [Pointing to the Vera Rubin module] This is a Vera Rubin. I have two Rubin GPUs here, one Vera CPU. These are the NVLink connections. This is purposely that close. This stuff is flying. The bandwidth in this direction [NVLink] is between 10x to 20x more, in terabytes per second, than in this direction [PCIe]. Here, we just use the same connector, but we have multiple lanes of PCIe connected to networking, multiple NICs, storage planes, or other systems.

The significance between the amount of bandwidth [intelligible] this way... you need that much bandwidth to have all GPUs within one rack really operating as one. The main use of scale-up is parallelism, taking the most compute-intensive part of the computation and doing tensor parallelism across all the GPUs.

When the world went to mixture of experts, where every layer has many experts [intelligible], Kimi K2 has over 200 experts per layer but only activates eight of them. Imagine using your entire brain to do two plus two. All those experts have to talk to all those experts extremely fast. That's why NVLink is so fast and why we have a dedicated NVSwitch, a lot of them in the rack, purposely in the middle of the racks so the signal is super fast.

We do it all in copper. You'll see the copper cables in the back. There's over 5,000 of them, because short-run copper is both fast and cheap. There's no retimers. It's also the lowest power. I don't have to drive a retimer or a transceiver or an optical fiber. One of the real reasons we went to liquid cooling was not just to get GPU performance, but to connect as many GPUs together in copper so that we could provide scale-up without exploding the cost. You could build 72 GPUs all with fiber and that many transceivers, but it's expensive and would consume a lot of power. A transceiver can consume significant power just slamming the laser on and off.

This generation, we're all in copper. Jensen did talk about going beyond 72 GPUs per rack. In the overall design of the NVSwitches, we're actually building an NVSwitch that has ports in the front. We can do a level two of NVLink and actually scale up the number of GPUs to 576. We have a prototype of that working with Grace Blackwell right now.

The models today don't benefit from that, but the models tomorrow will. It's a chicken-and-egg relationship between what capability we have versus what the models can do. And it's important that we show we're doing that, so that next-generation models can take advantage of it and design for that future where we have two layers of NVLink scale-up.

With the Kyber rack, we can densify further. We can put 144 GPUs in a single rack, again all in copper. And then we can even go a step further: with 144, we can scale to 576, and then double to 1,152. I really look forward to showing you that when we get there.

Journalist 4: Could you clarify how optical connections intersect with the roadmap? If there's an optical-capable rack with Grace Blackwell in it, does that mean you're going to put co-packaged optics with that generation?

Ian Buck: Rubin gets optical. And Ambulink is CPO [co-packaged optics].

Journalist 1: With LP30 only supporting FP8, are you looking at on-the-fly dequantization, or do you need to run everything in FP8?

Ian Buck: You don't need to run everything in FP8. Today's FP4, NVFP4, is done layer by layer, or actually block by block. When you go and look at Nvidia-optimized versions of all these models, you'll see that some of the math is FP16, FP8, and FP4. We can mix and match.

The way the engineers do it is they explore the space and then they run both hand-coded and AI-generated kernels to try all the different combinations. We then run that on a fleet of GPUs that we've rented back from the clouds to explore the space to make sure it's performant and accurate. We also test to make sure the accuracy didn't fall off or drop to a point where it's no longer valuable.

One big data point that's kind of fun: in October to January, the team was optimizing specifically focused on DeepSeek and DeepSeek-like models. They got that 4x uplift in just four months. Same GPUs, all the ones that everyone's already bought, the whole install base 4x faster.

To do that, they actually ran about 250 simulations and then about 1.2 million GPU hours. We had all sorts of ideas exploring the entire space across a massive fleet of GPUs for four months to get those results.

There is still more to come. Software is an untold story here. People like to say who's got the faster chip, and I'm like, who's got the better software ecosystem? That's why it's so hard to benchmark these things, because the whole stack end-to-end matters. How efficiently all of your different chips work together. We need six chips today, seven chips tomorrow to make all this stuff actually get performance. And the combinatorial optimization space is massive. We've got 400 engineers that work on that, and it came to 1.2 million GPU hours.

[Session ends]

Nvidia unveiled the Groq 3 language processing unit at GTC 2026 in San Jose on Monday, marking the first chip to emerge from its $20 billion licensing and talent deal with AI inference startup Groq, which was struck on Christmas Eve last year. The SRAM-based inference accelerator slots into the Vera Rubin platform as a dedicated decode-phase co-processor, and Nvidia plans to ship it in Q3 2026, manufactured by Samsung on a 4nm process. It is the company's first rack-scale product built around non-GPU silicon — and its arrival has already displaced a homegrown Nvidia chip from the roadmap.

The LP30 chip at the heart of the Groq 3 LPX rack carries 512 MB of on-chip SRAM per die, delivering 150 TB/s of memory bandwidth. That figure dwarfs the 22 TB/s available from the 288 GB of HBM4 on each Rubin GPU. A full LPX rack houses 256 LPUs for a total of 128GB of SRAM and 40 PB/s of aggregate bandwidth. Nvidia claims the LPX rack, paired with a Vera Rubin NVL72, delivers 35 times higher throughput per megawatt than Blackwell NVL72 alone for trillion-parameter models, at a target price point of $45 per million tokens.

Groq 3 and Vera Rubin

Rubin GPUs handle the compute-intensive prefill phase of a query, processing long input contexts, while Groq LPUs take over the decode phase, generating output tokens at low latency. Nvidia's Dynamo orchestration platform manages the split across heterogeneous hardware, distributing workloads based on batch size and parallelism requirements.

The original, pre-Nvidia Groq LPU design used a fixed Very Long Instruction Word (VLIW) pipeline and large on-chip SRAM pools, with the compiler pre-scheduling the entire execution path at compile time, which meant deterministic latency with no cache misses or stalls. These chips also demonstrated raw single-user token rates in the thousands per second, but the architecture's weakness was always capacity. At 230MB of SRAM per chip in prior generations, fitting even medium-sized models required high chip counts, and the architecture was initially designed for convolutional neural networks.

The Groq LP30 addresses some of these limitations with 512 MB of SRAM per die and 1.23 FP8 PFLOPS of compute capability. Samsung has ramped production from roughly 9,000 wafers to about 15,000 wafers as output shifts from samples to commercial manufacturing, with AWS announcing at GTC that it will deploy Groq 3 LPUs alongside more than one million Nvidia GPUs as part of an expanded partnership.

Beyond the LP30, a future LP35 will add NVFP4 support, aligning with the Rubin Ultra generation, and an LP40 is planned for the Feynman architecture cycle after that.

Rubin CPX axed?

One conspicuous absence from GTC was the Rubin CPX, a GDDR7-based inference accelerator announced in September 2025 as part of the Vera Rubin platform; it was absent from all keynote slides and received no stage time. It appears — though not officially confirmed — that the CPX has been removed from Nvidia’s roadmap entirely, replaced in the platform hierarchy by Groq 3 LPX.

Rubin CPX was designed to use cheaper, more available GDDR7 memory to accelerate the context phase of inference at lower power. But the Groq LPU offers higher bandwidth without requiring large quantities of any external memory, which is ideal in a market where HBM supply remains constrained, and GDDR7 production is still scaling. Off-roadmap parts could still ship to customers who have already invested in CPX software optimization, but there’s a clear shift in priorities at Nvidia.

There’s also an uncanny comparison between this and the Mellanox acquisition in 2019. That ended up turning Nvidia’s NVLink and InfiniBand technologies into foundational infrastructure for AI clusters. Groq appears to be following a similar trajectory, whereby start-up tech is absorbed into the platform as a permanent new architectural layer.

Inference chip consolidation

Nvidia's Groq deal is the largest in a wave of inference-focused acquisitions that swept through the semiconductor industry in 2025. In June, AMD acquired the engineering team from Untether AI, a RISC-V inference chip developer, after the startup shut down, and Nvidia itself paid over $900 million for networking startup Enfabrica's team and IP in September. Meta acquired custom-chip startup Rivos in October, and Intel attempted to buy SambaNova for a reported $1.6 billion, but the talks collapsed; the two companies settled on a $350 million investment and multi-year partnership last month instead.

There’s a consistent pattern here, where independent inference chip startups are being absorbed by large incumbents, and the economics of competing independently against Nvidia's CUDA ecosystem have proven unsustainable regardless of technical merit. Groq itself was targeting $500 million in revenue for the fiscal year 2025, but even that wasn’t enough to sustain independence. Bernstein analyst Stacy Rasgon noted in a research report that the deal's non-exclusive licensing structure may keep "the fiction of competition alive" while effectively neutralizing a rival.

Hyperscaler custom silicon

While startups consolidate into incumbents, the hyperscalers are building their own inference hardware at an accelerating pace.

Meta announced four successive MTIA chip generations on March 11, all developed in partnership with Broadcom: the MTIA 300 (already in production for ranking and recommendation training), MTIA 400 (completing lab testing), MTIA 450, and MTIA 500, with the latter two targeted at generative AI inference and scheduled for mass deployment in 2027. The company has already deployed hundreds of thousands of earlier MTIA chips for inference across its apps. From MTIA 300 to 500, HBM bandwidth increases 4.5 times, and compute FLOPS increase 25 times.

Google's Ironwood TPU v7 delivers 4,614 TFLOPS per chip with 192 GB of HBM per die, scaling to 42.5 exaflops in 9,216-chip pods. AWS continues developing Trainium and Inferentia, though internal data reported in 2024 showed Trainium at just 0.5% of Nvidia GPU usage within AWS and Inferentia at 2.7%, suggesting adoption has lagged.

Spending figures also demonstrate this diversification, with a Futurum Group survey from November 2025 finding that XPU accelerators are expected to lead data center compute spending growth at 22% in 2026, outpacing GPUs at 19% and CPUs at 14%. Meanwhile, TrendForce projects custom ASIC shipments from cloud providers growing 44.6% in 2026, compared to 16.1% growth for GPU shipments.

Nvidia's response is to make sure its platform includes non-GPU silicon before someone else's does, and the Groq 3 LPU is the product of that. Meanwhile, the future of Rubin CPX appears uncertain, at least for now.

Although Nvidia claims that demand for its Vera processors is beating expectations and that it expects its CPU business to earn billions of dollars, the company does not plan to offer multiple Vera models, it revealed in a briefing at GTC 2026. This approach will reduce Nvidia's costs while enabling it to achieve its strategic goals, but will limit its market penetration.

"We only are going to build one Vera CPU [SKU]," said Ian Buck, Nvidia's VP and general manager of hyperscale and HPC business at Nvidia, at a news conference attended by Tom's Hardware at GTC. "The world is not going to be served by one SKU of CPU, and that is not our intention. We like a workload problem to go solve, to go swarm, and Nvidia is making one CPU to help in that agentic workload."

Nvidia has always positioned its processors to work with its own compute GPUs for AI and HPC, rather than to serve the broader market of CPU workloads. To that end, Vera is optimized for maximum single-threaded performance rather than for maximum core count — unlike AMD's EPYC and Intel Xeon processors.

"We created a brand-new CPU that is designed for extremely high single-threaded performance, incredibly high data output, incredibly good at data processing, and extreme energy efficiency, […] we built that so it could go along with these racks for agentic AI processing," Nvidia CEO Jensen Huang said at GTC. "[Vera CPUs are] twice the performance-per-watt than any CPUs in the world. […] I am very pleased with our architects, we have designed a revolutionary CPU."

Limiting the number of Vera stock keeping units (SKUs) to one makes sense for Nvidia. A quick look at the die shot of the processor reveals that it packs 91 cores, which enables Intel to keep three of them for redundancy and get decent yields with an 88-core part. While this means that everything that has less than 88 fully functional cores will be scrapped, this makes sense as Nvidia will not have to spend money on binning. At the end of the day, the company's goal is to use Vera processors for its NVL72 VR200 and VR300 rack-scale systems rather than to build a fully-fledged CPU business.

Still, there is significant market interest in Nvidia's Vera processor, so the company will sell them separately as well. According to Jensen, the company expects CPUs to become a billion-dollar business. However, there are no plans to make it bigger or compete against AMD and Intel — for now, at least.

"We never thought we will be selling CPUs standalone, but we are selling a lot of CPUs standalone," Huang said. "This will for sure be a multi-billion dollar business for us."

Nvidia presented its updated data center product roadmap at its GPU Technology Conference this week, revealing several surprises but mostly reassuring that the company is on track to introduce a brand-new GPU architecture every couple of years and to update the AI GPU family every year. As it turns out, Nvidia intends to use die stacking and custom HBM memory with its Feynman GPUs, which will also be accompanied by its Rosa CPUs, previously never mentioned in the roadmap.

2026: Rubin, Vera, LP30, BlueField-4

Just as expected, Nvidia plans to roll out its Vera Rubin platform this year, based on the Vera CPU and Rubin GPU. It will be accompanied by five additional processors, including the Groq LP30 low-latency inference accelerator, the BlueField-4 data processing unit (DPU), the NVLink-6 switch, Spectrum-X Ethernet with co-packaged optics, and the ConnectX 9 1600G SuperNIC.

The Vera Rubin platform is interesting not only because of the new CPU and GPU architectures, but also because Nvidia is integrating its Groq LPUs into its hardware portfolio. Furthermore, it looks like the company favors LPUs over its own Rubin CPX processors to the point that it no longer mentions the latter on the roadmap.

2027: Rubin Ultra, LP35, NVLink 7

Next year, the company plans to update its offerings with the Rubin Ultra AI accelerators, which will feature four compute chiplets and be equipped with 1 TB of HBM4E memory, thus dramatically increasing performance compared to this year's Rubin. In addition, these GPU accelerators will be mated with the Groq LP35 LPU, which will support the NVFP4 data format and therefore improve performance.

Yet another tangible performance improvement for Nvidia's AI platforms is the introduction of the company's Kyber NVL144 rack-scale solution, which will pack 144 Rubin Ultra GPU packages (enabled by an NVLink 7 switch) and therefore offer at least 4X performance improvement compared to Oberon NVL72 racks with 72 Blackwell GPU packages.

2028: Feynman, Rosa, LP40, NVLink goes optics

Nvidia's data center portfolio will improve in 2027 by increasing the number of GPUs per rack (i.e., quantitative improvements) and introducing a new LPU with NVFP4 support. The company's 2028 data center products will be based on all-new architectures that will bring qualitative improvements to the company's products.

"The next generation from here is Feynman," said Jensen Huang, chief executive of Nvidia, at the GTC. "Feynman has a new GPU, of course; it also has a new LPU LP40 […] now uniting the scale of Nvidia and the Groq building together LP40, it is going to be incredible. A brand-new CPU called Ros, short for Rosalyn, Bluefield-5, which connects the next CPU with the next SuperNIC CX10. We will have Kyber, which is copper scale up, and we will have Kyber CPO scale-up. So, for the first time we will scale up with both copper and co-packaged optics."

First up, Nvidia's Feynman data center GPU will adopt die stacking, which will enable a new way for the company to scale performance. Secondly, Feynman GPUs will also use custom high-bandwidth memory (most likely a variant of C-HBM4E), which will likely enable Nvidia to boost HBM capacity beyond 1 TB per GPU package and increase memory bandwidth.

Thirdly, the Feynman platforms will be powered by Rosa CPUs, Nvidia's next-generation processors developed in-house with the focus on ultimate single-thread performance. The emergence of Rosa shows that the company has shortened its CPU development cycle from four years to two (probably by introducing a new design team), putting it on par with leading CPU developers AMD and Intel, which tend to release new microarchitectures every couple of years.

Fourthly, this platform will also integrate the LP40 LPU, which will not only support Nvidia's NVFP4 format but also connect to other system components using the NVLink protocol, thereby integrating Groq hardware with Nvidia's GPUs.

Fifthly, the Feynman platform will also be the first one to adopt NVLink switches with co-packaged optics, which will enable optical interconnections using the NVLink protocol (they are not impossible today, but CPO makes them significantly easier and cheaper to implement). Optical interconnects will enable Nvidia to increase scale-up world size of its rack-scale solutions to 576 GPU packages (using Oberon chassis) or even 1152 GPU packages (using Kyber chassis), which will make the company's rack-scale systems even more competitive against alternative solutions like AMD's Instinct or custom accelerators deployed by hyperscalers than they are today.

Last but not least, Nvidia plans to introduce BlueField 5 DPU, 7^th Generation SpectrumX Ethernet with co-packaged optics, as well as ConnectX 10 SuperNIC in 2028.

At a press event attended by Tom's Hardware at GTC 2026, Nvidia CEO Jensen Huang confirmed the company has received export licenses for multiple Chinese customers, has purchase orders in hand, and has restarted H200 manufacturing, marking the first time its China supply chain has been back in motion since export restrictions froze shipments over a year ago.

Huang described the situation as “new news,” stating that Nvidia “[has] received purchase orders from many customers [in China], and we're in the process of restarting our manufacturing… our supply chain is getting fired up.”

The H200 is Nvidia's Hopper-generation accelerator featuring 141GB of HBM3e memory. It sits below the current Blackwell architecture but remains roughly six times more powerful than the H20, the downgraded chip Nvidia originally designed to stay within earlier export limits. The H200 is what Chinese hyperscalers have been waiting patiently for.

President Trump announced in December 2025 that Nvidia would be permitted to ship H200 chips to approved Chinese customers, with 25% of sales revenue going to the U.S. government as part of the deal.

The Commerce Department's Bureau of Industry and Security formally published the licensing framework in January 2026, and Nvidia confirmed in late February that it had secured a license to ship a small number of H200 units. However, it declined to include any China data-center revenue in its first-quarter sales outlook.

Chinese authorities granted ByteDance, Alibaba, and Tencent permission to purchase H200 chips in January, with the three companies collectively approved to buy more than 400,000 units, following earlier reports that Alibaba and ByteDance were ready to order over 200,000 chips each.

Nvidia had largely wound down Hopper-class production to focus on Blackwell, but in light of Chinese demand and the green light from Washington, the company said it hoped to reopen H200 orders in 2026.

Huang at the Q&A also said that President Trump’s position is that the U.S. should lead in access to Nvidia's best technology while still competing for global markets. "He would like us to compete worldwide and not concede those markets unnecessarily," he said.

The H200 approval covers only a 50% volume cap relative to domestic U.S. sales, and a third-party laboratory must verify each shipment before re-export to China.

At a press Q&A with Tom's Hardware at GTC 2026, Nvidia CEO Jensen Huang downplayed criticism of DLSS 5, the company's new use of AI and neural rendering to infer how certain features of games would look if they were more photorealistic.

Since the debut of the feature, some critics have vocally complained on social media that the technology is making games look worse, homogenous, or only show Nvidia's view of the world. Much of the criticism has focused on the updated appearances of Resident Evil Requiem's Grace Ashcroft and Leon Kennedy.

"Since DLSS 5 was revealed yesterday, there's been a pretty vocal response from some of the gaming community that the technology appears to make games appear worse, homogenous, or show only NVIDIA's view of how games should look. How do you feel about that criticism?' asked Tom's Hardware editor-in-chief Paul Alcorn.

"Well, first of all, they're completely wrong," Huang said in response. "The reason for that is because, as I have explained very carefully, DLSS 5 fuses controllability of the of geometry and textures and everything about the game with generative AI," Huang continued.

He added that developers can still "fine-tune the generative AI" to make it match their style, adding that DLSS 5 adds generative capability to the existing geometry of the game, but that it "doesn't change the artistic control."

"It’s not post-processing, it’s not post-processing at the frame level, it’s generative control at the geometry level," he said.

Huang also said that developers can try the tool and see how they want to use it, suggesting that it's up to a developer to try to make a "toon shader" or see if the game should be "made of glass."

"All of that is in the control — direct control — of the game developer," he said. This is very different than generative AI; it’s content-control generative AI. That’s why we call it neural rendering."

We'll see if the vocal gamers who say they dislike what they see change their mind as we see more. DLSS 5 is set to launch in the fall, and there will likely be far more demos of this technology that are more fully baked before then.

Update 3/19/2026 4:38pm PT: Added full text of question to Jensen.

Nvidia announced seven chips in full production at GTC 2026 on Monday, composing the Vera Rubin platform that the company intends to ship in the second half of this year.

Rather than a single product launch, several announcements covered the full silicon stack required to build what Nvidia now calls an AI factory: GPUs, CPUs, a dedicated inference accelerator, networking ASICs, a data processing unit, and an Ethernet switch. All seven are designed to operate as a single co-designed system across five rack types, scaling from individual racks to 40-rack PODs delivering 60 exaflops of compute.

The so-called AI factory is a massive shift in how Nvidia packages and sells its hardware, where the unit of compute is no longer a GPU or even a server; it’s the rack, and increasingly, the POD. Each of the seven chips fills a specific architectural role — and understanding what each does is the fastest route to understanding what Vera Rubin fundamentally is.

The compute layer: Rubin GPU, Vera CPU, and Groq 3

Three chips handle the core compute workload, each optimized for a different phase of the AI pipeline.

The Rubin GPU is the training and inference workhorse built on TSMC's 3nm process. Each GPU uses a dual-die design packing 336 billion transistors, carries 288 GB of HBM4 memory with 22 TB/s of bandwidth, and delivers 50 PFLOPS of inference compute and 35 PFLOPS of training compute in the NVFP4 format. Those figures represent 5 and 3.5 times improvements over Blackwell, respectively.

In the flagship Vera Rubin NVL72 rack, 72 Rubin GPUs connect via NVLink 6 to behave as a single accelerator. Nvidia claims that the NVL72 can train Mixture-of-Experts models with one quarter the GPU count required by Blackwell, and cut inference token costs by 10 times.

The Vera CPU, meanwhile, is Nvidia's first data center CPU built from the ground up. It uses 88 custom Arm-based Olympus cores with Spatial Multithreading for 176 threads, up to 1.5TB of SOCAMM LPDDR5X memory, and 1.2 TB/s of memory bandwidth. Vera connects to Rubin GPUs via NVLink-C2C at 1.8 TB/s of coherent bandwidth, which is seven times faster than PCIe Gen 6. Its role in the rack is orchestration: scheduling workloads, routing KV cache data, managing context, and running the control plane for agentic AI workflows. It also handles reinforcement learning environments and CPU-native workloads.

The Groq 3 LPU — purpose-built for low-latency decode-phase inference — is the most unexpected addition to the platform, and a direct product of Nvidia's $20 billion acquisition of Groq in December. Where Rubin GPUs offer massive memory capacity through HBM4, the Groq 3 trades capacity for bandwidth: Each LPU can carry roughly 500MB of stacked SRAM and delivers approximately 80 TB/s of bandwidth per chip. The Groq 3 LPX rack houses 256 LPUs with about 128GB of aggregate on-chip SRAM and 640 TB/s of scale-up bandwidth.

Rubin GPUs handle the compute-heavy prefill phase of inference, processing long input contexts, with the Groq 3 LPUs stepping in to handle the decode phase, generating output tokens at low latency. Nvidia claims the combination delivers 35 times higher inference throughput per megawatt and 10 times more revenue opportunity for trillion-parameter models, compared with running both phases on GPUs alone.

The fabric: NVLink 6, ConnextX-9, and Spectrum-6

As for moving data between chips at rack scale and between racks at cluster scale, Nvidia has architected this via three dedicated networking ASICs.

The NVLink 6 Switch, due to be upgraded to a 7th generation, handles scale-up connectivity within the rack. Each switch delivers 3.6 TB/s of bidirectional bandwidth per GPU, doubling Blackwell's NVLink performance, while a single switch tray provides 28.8 TB/s of total switching bandwidth and 14.4 TFLOPS of FP8 in-network compute, which accelerates collective operations like the all-to-all communication patterns used in MoE routing. Nine switch trays per NVL72 rack deliver 260 TB/s of aggregate scale-up bandwidth.

The ConnectX-9 SuperNIC provides a scale-out networking endpoint at 1.6 Tb/s throughput per GPU. Where NVLink 6 connects GPUs within a rack, ConnectX-9 connects racks, linking NVL72 systems into multi-rack clusters via either Nvidia's Spectrum-X Ethernet or Quantum-X800 InfiniBand fabrics. Each compute tray uses eight ConnectX-9 NICs to deliver the aggregate bandwidth quoted for the tray's four GPUs.

The Spectrum-6 Ethernet Switch is the switching silicon and the backbone of the Spectrum-6 SPX networking rack, delivering 102.4 Tb/s of aggregate bandwidth, and is Nvidia's first switch to use co-packaged optics, employing silicon photonics to reduce optical power consumption. Nvidia claims five times improved power efficiency and 10 times improved resiliency over prior Spectrum-X generations. Available in two configurations, the SN6800 offers 512 ports of 800G Ethernet or 2,048 ports at 200G.

The infrastructure layer: BlueField-4

The final chip, BlueField-4 DPU, functions as a specialized processor that handles networking and storage tasks that would otherwise consume CPU and GPU cycles.

A dual-die package that combines a 64-core Grace CPU with an integrated ConnectX-9 NIC, the BlueField-4 DPU offloads networking, storage, encryption, virtual switching, telemetry, and security enforcement from the main compute path, running Nvidia's DOCA software framework for infrastructure services. Nvidia says it features twice the bandwidth, three times the memory bandwidth, and six times the compute of BlueField-3.

BlueField-4 underpins the new BlueField-4 STX storage rack, which implements Nvidia's CMX context memory storage platform, essentially extending GPU memory into NVMe storage to cache the key-value data generated by agentic AI workflows. As context windows grow to hundreds of thousands, and in some cases millions, of tokens, operations on the KV cache are becoming a bottleneck, and the STX rack is designed to break through it. Nvidia claims up to five times higher inference throughput when the STX storage tier is deployed alongside compute racks, via the new DOCA Memos software framework.

Five racks, one supercomputer

All seven chips map into five rack types that compose the Vera Rubin POD: the NVL72 for core training and inference (72 Rubin GPUs, 36 Vera CPUs); the Groq 3 LPX rack for decode acceleration (256 LPUs); the Vera CPU rack for RL and orchestration (256 Vera CPUs); the BlueField-4 STX rack for KV cache storage; and the Spectrum-6 SPX rack for Ethernet networking. A full POD spans 40 racks, 1,152 Rubin GPUs, nearly 20,000 Nvidia dies, 1.2 quadrillion transistors, and 60 exaflops.

Vera Rubin-based products are scheduled to ship in the second half of 2026.

Neural rendering—the use of AI models to create pixels—is already a familiar concept in real-time graphics. When you’re using DLSS upscaling or frame generation, for example, many of the pixels you see are already generated rather than natively shaded, and those extra pixels and frames come at a surprisingly low computational cost via the matrix math acceleration of Nvidia’s Tensor Cores.

Given that almost magical cost-to-benefit ratio, research is unsurprisingly well under way to expand generative AI techniques beyond relatively transparent applications like upscaling and frame generation to replace portions of the traditional graphics pipeline as we know it today—and possibly even in its entirety.

Nvidia’s DLSS 5 reveal at GTC is a startling indication of just how close we are to that future. The RT cores that debuted in Turing nearly eight years ago have brought much more lifelike lighting effects into the realm of real-time graphics, but natively shading even a subset of the pixels in a frame to a Hollywood polish remains well outside the realm of today’s graphics hardware. Even the 575W, ~750mm² RTX 5090 isn’t up to the task, and further scaling-up of GPU die sizes and power envelopes in pursuit of that lifelike ideal would only make it less accessible. And given AI’s crowding-out of leading-edge fab capacity, next-gen gaming GPU silicon seems less and less likely to arrive any time soon.

DLSS 5 is the most prominent example so far of how neural rendering offers an alternate way forward compared to brute-force increases in compute resources. Its AI model is trained to infer how certain complex features of game scenes like characters, skin, hair, and environmental lighting “should” look in the real world given certain inputs from the game engine (including, but not limited to, the color buffer and motion vectors) in combination with an input frame.

The DLSS 5 model then uses this input data and its semantic understanding of parts of a scene to bring its appearance closer to how it might look in reality while still respecting the artistic intent embedded in environments and character models. Because it's deeply tied to the underlying game engine and assets, DLSS 5’s output is consistent and predictable in ways that the prompt-driven and iterative workflow of generative AI imagery and video distinctly aren’t.

We had an opportunity to preview DLSS 5 in five games at GTC, and for modern games with assets built to match, DLSS 5 unquestionably improved the image quality and fidelity of the small group of titles we saw. (For a group of high-resolution side-by-side comparisons that you can really pixel-peep, check out Nvidia's launch article.)

Even in games that already feature real time ray-traced effects, like Hogwarts Legacy, flipping DLSS 5 on and off creates even more convincing lighting effects for environments and characters alike. Hogwarts students standing in front of massive sunlit windows are rendered with convincing rim lighting around the edges of their hair and clothing that’s absent with DLSS 5 off. Improved ambient occlusion better darkens every fold of students’ robes and every nook, cranny, and corner of Hogwarts itself. Even everyday objects like couches look better situated in scenes thanks to more accurate shadows underneath.

I’ve also spent lots of time recently looking at Assassin’s Creed Shadows as I’ve begun a new round of benchmarking for our GPU Hierarchy, and it’s a game where RT plays a huge part in creating a rich and convincing-looking world. Even with Shadows’ already impressive RT implementation, DLSS 5 makes the light and shadow playing across the game’s forested vistas appear even closer to life, and it straightforwardly corrects minor rendering errors like a character’s robe not properly shadowing their leg in a crouch.

Those improvements carry over to games like Starfield that never implemented ray tracing to begin with. Flipping on DLSS 5 adds considerably greater sophistication to the appearance of environments and objects (and characters’ faces, but more on that in a second). That experience also holds in The Elder Scrolls IV: Oblivion Remastered, where reflections on water become more convincing and environmental features like the spaces under wooden docks and the arches and filigrees of bridges and buildings all look

DLSS 5 is also meant to better replicate how light interacts with human hair and skin, and nowhere are its enhancements more dramatic – for better or for worse – than with human faces.

Nvidia says that we’re not used to seeing faces of this fidelity in real-time rendering, and sometimes, the effect is breathtaking. The visages of the characters in Nvidia’s Zorah demo went from looking like “a good video game” to “incredibly lifelike.” And the flatly lit and (frankly) dead-eyed characters of Starfield practically come alive with DLSS 5 enabled, transforming into something resembling actual humans rather than aliens wearing human skin suits.

But in Oblivion Remastered, which uses character models that still exhibit some of the awkwardness of the 2006 original, the results are more mixed. It’s incredible that DLSS 5 can simply infer that flowing hair should create shadows that the game’s native lighting model completely fails to cast, but when that same character’s facial features are comically exaggerated, rendering their skin and hair with cinematic detail and precision can be more off-putting than immersive. The uncanny valley becomes the uncanny Grand Canyon.

And that’s where the advent of DLSS 5 and its reception moves into the realm of the philosophical rather than the purely technical. Real-time graphics as a field has relentlessly pursued more photorealistic rendering ever since the advent of the first GPUs, and working in the wide gap between real life and the capabilities of our tech to reproduce it has required considerable artistic skill, taste, and judgment to partially bridge those limitations.

If DLSS 5 is going to drastically narrow that gap, carelessly applying it has the potential to produce results that aren’t consistent with a game’s creative direction, and the inflamed community response to the results of some of Nvidia’s demos so far suggests that the company and its game dev partners will need to tread carefully to avoid those pitfalls. Assuming a developer includes DLSS 5 in a title using the existing Streamline SDK, Nvidia says that the model offers controls for color grading, intensity, and masking to fine-tune its overall effect on a game's appearance.

Of course, DLSS 5 will be toggle-able just like upscaling and frame gen, so if you’re not a fan of its implementation in a particular game, you can just leave it off entirely. And although the company acknowledges that the model could certainly be shoehorned into games by enterprising modders, the results thereafter are purely those folks’ responsibility, not devs' or Nvidia's.

The final open question for DLSS 5 regards its hardware requirements. The demos we saw were all running on a PC featuring dual RTX 5090s, one to run the game itself and one dedicated to accelerating the model. That’s a massive amount of compute, but the company said it hasn’t begun performance optimizations on the model yet, so we’ll have to withhold judgment on its hardware requirements until later. Nvidia also didn’t offer any indication of which of its RTX GPU architectures would be best compatible with DLSS 5, either.

All told, this remains an early look, but even at this stage, we’re excited and cautiously optimistic for the changes that expanded uses of neural rendering holds for gaming graphics. The fact that DLSS 5 is an AI model means that it can be continually fine-tuned and improved, just as DLSS upscaling has progressed in its capabilities over time.

Given that fact, Nvidia will doubtless continue to work internally and with game studios to refine DLSS 5’s outputs and requirements as the tech continues to be developed ahead of its launch this fall. The company claims over a dozen games will support DLSS 5 at launch so far, and given the widespread adoption of DLSS tech generally, that number is sure to grow by leaps and bounds. From what we’ve seen so far, we can’t wait to get our hands on it and give it a spin in a wider range of titles.

Nvidia announced BlueField-4 STX at GTC 2026 on March 16, a modular reference architecture for accelerated storage designed to address the data access bottleneck limiting agentic AI inference.

Built around a new storage-optimized BlueField-4 DPU and ConnectX-9 SuperNIC, the platform targets GPU underutilization that occurs when AI agents operating across extended sessions and expanding context windows exceed the throughput of conventional storage paths. Nvidia says STX delivers up to five times the token throughput, four times better energy efficiency, and twice the page ingestion speed compared with traditional CPU-based storage architectures.

The specific issue that Nvidia is targeting with STX is KV cache management. During transformer inference, the attention mechanism computes KV pairs for every token in context, which must be stored and retrieved for each subsequent generation step. But these context windows are growing into the hundreds of thousands of tokens, meaning that the KV cache is outgrowing GPU HBM capacity. The usual fallback is to offload to host DRAM or NVMe storage, but both routes pass through the CPU, adding latency that compounds with context length and stalls GPU execution as data transits.

STX bypasses the host CPU by routing data through a dedicated accelerated storage layer via RDMA over Spectrum-X Ethernet. BlueField-4 manages NVMe SSDs directly and handles data integrity and encryption for the KV cache, keeping context accessible at the storage processor rather than transit­ing the host. The full stack runs on the Vera Rubin platform and integrates the Vera CPU — also announced at GTC on March 16 — alongside ConnectX-9, Spectrum-X Ethernet, DOCA software, and AI Enterprise software. The first rack-scale implementation built on STX is the Nvidia CMX context memory storage platform.

Storage and infrastructure vendors co-designing systems based on STX include DDN, Dell Technologies, HPE, IBM, NetApp, and VAST Data, alongside manufacturing partners AIC, Supermicro, and Quanta Cloud Technology. Meanwhile, eight cloud and AI providers — including CoreWeave, Lambda, Mistral AI, and Oracle Cloud Infrastructure — committed to early adoption for context memory storage. STX-based platforms are expected from partners in the second half of 2026.

"Agentic AI is redefining what software can do — and the computing infrastructure behind it must be reinvented to keep pace," Jensen Huang, founder and CEO of Nvidia, said at GTC. "AI systems that reason across massive context and continuously learn require a new class of storage."

One thing that caught our attention during Jensen Huang's keynote at GTC 2026 on Monday was the lack of any mention of the Rubin CPX context phase accelerator that the company promoted last year as an important part of the Vera Rubin platform. The Rubin CPX was also absent from the slides demonstrated during the keynote, but the slides mention Nvidia's upcoming Groq 3 LPU processors and LPX racks, which may indicate that these processors are replacing the CPX in Nvidia's roadmap.

Nvidia's Rubin CPX GPU was meant to be a part of the company's Vera Rubin and Vera Rubin Ultra platforms. These GPUs were designed to accelerate an initial compute-intensive context phase of a query that processes the input to generate the first output token. The main advantage of the context phase accelerator was its reliance on GDDR7 memory, which does not offer extreme bandwidth like HBM3E or HBM4 but consumes dramatically less power, which was said to greatly improve the competitiveness of Nvidia's Rubin platform for inference workloads.

However, the slides demonstrated by Nvidia at GTC lack Rubin CPX products, but include Groq 3 LPU, which may indicate that the company is now more focused on the latter rather than the former.

Nvidia's Groq 3 low-latency inference accelerators — which Nvidia calls LPUs — are designed to offer significant inference performance with extremely low latency, as it mainly relies on internal SRAM, which is by definition faster, lower latency, and lower power than any type of DRAM. For example, Nvidia's LP30 processor comes with 512 MB of SRAM and offers 1.23 FP8 PFLOPS performance, or 9.6 PFLOPS per Groq 3 LPX compute tray or 315 FP8 PFLOPS per rack. By contrast, the Rubin CPX accelerator was to deliver up to 30 NVFP4 PetaFLOPS of compute throughput, but with considerably higher latency.

For now, it remains to be seen whether Nvidia will actually offer its Rubin CPX accelerators or will refocus its efforts to Groq 3 LPU low-latency inference accelerators. Given Nvidia's recent $20 billion non-exclusive license acquisition of startup Groq's chip tech and talent, the move would make sense. The lack of Rubin CPX in roadmap slides and publicly favoring LPU processors is a rather clear indicator of the company's priorities. Nonetheless, it is possible that some of Nvidia's customers will deploy its CPX accelerators, as they have already invested in their deployment by tweaking their software for these processors. After all, off-roadmap parts are pretty common in the industry.

Micron has announced that it has entered high-volume production of its HBM4 36GB 12-Hi memory, designed for Nvidia's Vera Rubin GPU platform. Making the announcement at GTC 2026, the memory giant simultaneously confirmed high-volume production of the industry's first PCIe 6.0 data center SSD and a new SOCAMM2 module, making it the first memory supplier to bring all three products to volume shipment for the Vera Rubin ecosystem at the same time.

The HBM4 36GB 12H stack runs at over 11 Gb/s pin speeds, delivering bandwidth greater than 2.8 TB/s. Compared to Micron's HBM3E at the same 36GB 12H configuration, that represents a 2.3 times bandwidth increase alongside more than 20% improvement in power efficiency, according to Micron's internal power calculator data.

"The next era of AI will be defined by tightly integrated platforms developed through joint engineering innovations across the ecosystem. Our close collaboration with NVIDIA ensures that compute and memory are designed to scale together from day one," said Sumit Sadana, executive vice president and chief business officer at Micron Technology, in a press release. "With HBM4 36GB 12H, alongside the industry's first SOCAMM2 and Gen6 SSD now in high-volume production, Micron's memory and storage form a core foundation that unlocks the full potential of next-generation AI."

Micron has also shipped samples of a 48GB 16H HBM4 stack to customers. The additional four die layers give the 16H configuration a 33% capacity increase per HBM placement over the 36GB 12H product, a milestone that points toward denser configurations in future AI accelerator generations.

Last month, the company announced that the 9650 SSD had entered mass production, marking the first time that a PCIe 6.0 SSD had entered that stage of production. The drive supports up to 28 GB/s sequential read throughput and 5.5 million random read IOPS, doubling PCIe 5.0 read performance at 100% higher performance per watt. Unsurprisingly, it targets AI inference, training, and agentic workloads in liquid-cooled environments and is optimized for Nvidia's BlueField-4 STX reference architecture.

Meanwhile, the 192GB SOCAMM2 module is designed for Nvidia Vera Rubin NVL72 systems and standalone Vera CPU platforms, with Micron's SOCAMM2 portfolio spanning 48GB to 256GB capacities. The Vera Rubin platform supports up to 2TB of memory and 1.2 TB/s of bandwidth per CPU using the module.

Nvidia CEO Jensen Heung has announced the Vera Rubin Space Module at the company’s ongoing GTC 2026 event, claiming up to 25 times more AI compute than the H100 for orbital inference workloads. Six commercial space companies are understood to have already deployed the platform.

According to the official Nvidia press release, the Vera Rubin Space Module is designed for orbital data centers running LLMs and advanced foundation models directly in space, with a tightly integrated CPU-GPU architecture and high-bandwidth interconnect built to handle large data streams from space-based instruments in real time.

Below that sits the Nvidia IGX Thor, targeting mission-critical edge environments with support for real-time AI processing, functional safety, secure boot, and autonomous operation. The Nvidia Jetson Orin, meanwhile, handles the smallest form factor, targeting SWaP-constrained satellites for onboard vision, navigation, and sensor data processing.

Back on planet Earth, Nvidia has positioned the RTX PRO 6000 Blackwell Series Server Edition GPU for geospatial intelligence workloads, claiming up to a 100 times performance uplift versus legacy CPU-based batch processing systems when analyzing large image archives.

Nvidia says that six companies are currently using its platforms across orbital and ground environments: Aetherflux, Axiom Space, Kepler Communications, Planet Labs PBC, Sophia Space, and Starcloud, with Kepler deploying Jetson Orin across its satellite constellation for AI-driven data management. "Nvidia Jetson Orin brings advanced AI directly to our satellites, allowing us to intelligently manage and route data across our constellation," said Mina Mitry, the company’s CEO, in Nvidia’s official press release.

Last October, Amazon and Blue Origin founder Jeff Bezos predicted that gigawatt-scale data centers in orbit were 10 to 20 years away, citing continuous solar power and the simplified cooling environment of space as the primary advantages. Starcloud, one of Nvidia's six partners, is already building what it describes as purpose-designed orbital data centers aimed at running training and inference workloads in orbit.

"Space computing, the final frontier, has arrived," said Jensen Huang, adding that "AI processing across space and ground systems enables real-time sensing, decision-making and autonomy, transforming orbital data centers into instruments of discovery and spacecraft into self-navigating systems."

The IGX Thor, Jetson Orin, and RTX PRO 6000 Blackwell Server Edition are available now. The Vera Rubin Space Module has no release date; Nvidia says it’ll be available "at a later date."

Nvidia today announced the Nemotron Coalition at its GTC conference in San Jose, California, recruiting eight AI companies to co-develop open frontier models on NVIDIA DGX Cloud, with the work feeding into the upcoming Nemotron 4 model family. Alongside the coalition, Nvidia released a new generation of open models spanning agentic AI, robotics, autonomous vehicles, and drug discovery.

The founding members are Black Forest Labs, Cursor, LangChain, Mistral AI, Perplexity, Reflection AI, Sarvam, and Thinking Machines Lab — the latter of which was founded by Mira Murati, who served as CTO of OpenAI until her departure in 2024.

"Open models are the lifeblood of innovation and the engine of global participation in the AI revolution," said Nvidia CEO Jensen Huang in an official press release.

The coalition's first deliverable is a base model co-developed by Nvidia and Mistral AI, trained on DGX Cloud. Other members will contribute data, evaluation frameworks, and domain expertise during post-training, and Nvidia plans to open-source the model on completion and said it will “underpin” the upcoming Nemotron 4 family of models.

Contributions across the coalition span multimodal capabilities from Black Forest Labs, real-world coding performance benchmarks from Cursor, and agentic tool-use and long-horizon reasoning evaluation from LangChain, which reported over 100 million monthly downloads of its AI frameworks.

Nemotron 3 Ultra — the new flagship of the Nemotron family — runs on Nvidia's Blackwell platform and claims 5 times throughput efficiency using the NVFP4 numerical format. Nvidia has said it will power “AI-native applications,” including coding assistants and complex workflow automation. Meanwhile, Nemotron 3 Omni adds audio, vision, and language understanding in a single model, while Nemotron 3 VoiceChat handles real-time simultaneous listen-and-respond conversations by combining automatic speech recognition, LLM processing, and text-to-speech in a unified system.

For robotics, Isaac GR00T N1.7 — an open reasoning vision language action (VLA) model purpose-built for humanoids — is now commercially viable for real-world deployment. Huang also previewed GR00T N2 during his keynote, a next-gen robot foundation model that currently ranks first on both MolmoSpaces and RoboArena for generalist robot policies. “Built on a new world action model architecture, the model helps robots succeed at new tasks in new environments more than twice as often as leading VLA models,” says the official press release. Nvidia expects to ship GR00T N2 by the end of 2026.

Last but not least, Cosmos 3, a world foundation model unifying synthetic environment generation and physical AI reasoning, is also expected to arrive later this year, while the new Proteina-Complexa model — forming part of the BioNeMo platform — targets protein binder design for drug discovery; Novo Nordisk, Viva Biotech, and Manifold Bio are listed as early adopters.

Huang also announced NemoClaw, a software stack for the OpenClaw open-source agent platform. NemoClaw installs Nemotron models and the new OpenShell runtime in a single command, adding a sandboxed privacy and security layer beneath autonomous AI agents. It can run on any dedicated platform, including GeForce RTX PCs and laptops, RTX PRO workstations, DGX Station, and DGX Spark. A local privacy router lets agents tap cloud-based frontier models while keeping data processing on-device when required.

Select Nvidia open models will be available on GitHub, Hugging Face, and as NIM microservices for deployment on Nvidia-accelerated infrastructure.

Intel announced today at Nvidia GTC 2026 in San Jose that its Xeon 6 processor will serve as the host CPU in Nvidia's DGX Rubin NVL8 systems, extending the x86 pairing the two companies established with the Xeon 6776P in current DGX B300 Blackwell-based platforms.

The DGX Rubin NVL8 is Nvidia's next-generation flagship AI server system. In that configuration, the host CPU is responsible for task orchestration, memory management, scheduling, and data movement to the GPU accelerators. With inference workloads shifting toward agentic AI and reasoning systems, those functions place increasingly heavy demands on per-core performance and memory bandwidth.

Intel said Xeon 6 addresses those demands through a combination of memory capacity, bandwidth, and I/O capabilities. The platform supports up to 8TB of system memory, which Intel cited as key for supporting large language models with growing key-value caches.

Meanwhile, memory bandwidth has improved 2.3 times generation-on-generation via MRDIMM technology, raising the rate at which data reaches the GPU accelerators. PCIe 5.0 lanes handle high-bandwidth accelerator connectivity, and a feature Intel calls Priority Core Turbo dedicates strong single-thread performance to orchestration, scheduling, and data movement tasks, keeping GPU utilization high as workload complexity increases.

Security coverage extends across the CPU-to-GPU data path through Intel Trust Domain Extensions (TDX), which adds hardware-rooted isolation and attestation via an Encrypted Bounce Buffer. Intel said end-to-end confidential computing is increasingly required as AI inference scales across data center, cloud, and edge deployments. Xeon 6 also now supports Nvidia Dynamo, an inference orchestration framework that enables heterogeneous scheduling across CPU and GPU resources within the same cluster.

"In this new era, the host CPU is mission-critical," said Jeff McVeigh, corporate vice president and general manager of Data Center Strategic Programs at Intel. "It governs orchestration, memory access, model security, and throughput across GPU-accelerated systems."

Intel also cited Xeon's x86 software ecosystem and enterprise deployment history as factors in the selection, noting compatibility with existing AI software stacks. The DGX Rubin NVL8 configuration builds on the same architectural foundation as DGX B300, giving operators platform continuity between Blackwell and Rubin generations.

Nvidia's Vera Rubin platform is poised to massively power up the next generation of AI data centers, or "factories," as CEO Jensen Huang calls them, when those systems start arriving later this year. Today, during his GTC keynote, Huang revealed how Nvidia is using the IP it acquired from Groq last year to expand Rubin's capabilities. The Rubin platform now includes a new chip, the Nvidia Groq 3 LPU, an inference accelerator that bolsters these systems' ability to deliver tokens in volume and at low latency for high interactivity at the leading edge of AI models.

Recall that the Rubin platform already includes six chips from which Nvidia builds up rack-scale systems and scales them out into AI factories: the Rubin GPU itself, the Vera CPU, NVLink 6 scale-up switches, the ConnectX 9 smart NIC, the Bluefield 4 data processing unit, and the Spectrum-X scale-out switch with co-packaged optics. The Groq 3 LPU becomes another building block for Rubin at scale.

Unlike most AI accelerators, which rely on HBM as their working memory tier, each Groq 3 LPU incorporates 500 MB of SRAM, the same memory used for ultra-high-speed caches on CPUs and GPUs. That’s paltry compared to the vastly more capacious 288GB of HBM4 on each Rubin GPU, but as you would expect, that SRAM delivers 150 TB/s of bandwidth, far more than the 22 TB/s of that same HBM. For bandwidth-sensitive AI decode operations, the massive bandwidth boost of the Groq 3 chip offers tantalizing benefits for inference applications.

In turn, Nvidia will build up Groq 3 LPX racks comprising 256 Groq 3 LPUs. That rack offers 128GB of SRAM with 40 PB/s of bandwidth for inference acceleration, and it joins those chips together with a dedicated scale-up interface of 640 TB/s per rack.

Nvidia envisions Groq LPX as a co-processor for Rubin that will boost decode performance at “every layer of the AI model on every token,” according to Nvidia hyperscale VP Ian Buck, and it positions Rubin to serve the next frontier of AI: multi-agent systems that need to deliver interactive performance while inferencing models of trillions of parameters with context windows of millions of tokens.

As the AI agents in those multi-agent systems begin talking more and more to other AIs rather than humans looking at chatbot windows, the frontier for responsiveness requirements also shifts. What might seem like a reasonable rate of tokens generated per second for a human is glacial for an AI agent. In the future of multi-agent systems that Buck describes, the combination of Rubin GPUs and Groq LPUs moves us from a world where 100 tokens per second is a reasonable throughput to one of 1500 TPS or more for AI agent intercommunication.

The addition of the Groq 3 LPU to the Rubin arsenal could help the platform fend off challengers in the low-latency inference frontier. Cerebras, whose wafer-scale engines fuse massive amounts of SRAM and compute for low-latency inference with advanced models, has frequently needled Nvidia regarding the perceived disadvantages of its GPUs for that purpose, and customers as large as OpenAI have signed up for Cerebras capacity to serve some of their state-of-the-art models with the favorable latency characteristics of that platform.

Buck also hinted that the Groq 3 LPU might lead to a reduced role for the Rubin CPX inference accelerator, saying that the company is currently focused on integrating the Groq 3 LPX rack with Rubin. While he didn’t offer more details, that focus shift would make sense in today’s memory-constricted world, since the two chips are meant to offer similar enhancements for inference performance and the Groq LPU doesn't require the large amount of GDDR7 memory that each Rubin CPX module does.

We’re on the ground at GTC this week, and we’ll be exploring what the fusion of Groq and Nvidia IP means for the future of AI inference through conversations and sessions at the event. Stay tuned.

Nvidia announced more details about its new 88-core Vera data center CPUs at GTC 2026 here in San Jose, California, claiming impressive 50% performance gains over standard CPUs, fueled by a 1.5X increase in IPC from its Olympus cores and an innovative high-bandwidth design that Nvidia says delivers the fastest single-threaded performance on the market. The company also unveiled its new Vera CPU Rack architecture, which brings 256 liquid-cooled CPUs into one rack for CPU-centric workloads, claiming a 6X gain in CPU throughput and twice the performance in agentic AI workloads.

The evolution of the Vera CPU and its integration into deployable rack-scale systems marks Nvidia’s entry into direct CPU sales, positioning itself as a competitor to Intel and AMD in the traditional CPU market. That’s not to mention competing against the many flavors of custom Arm processors used by the world’s largest hyperscalers. This doesn’t come as a complete surprise, coming in the wake of the company’s announcement that Meta will now deploy multiple generations of Nvidia CPU-only systems across its infrastructure. Nvidia will also continue to use the CPUs for its own GPU-focused systems, such as the Vera Rubin platform we covered more in depth here.

Nvidia originally introduced its first-gen Grace CPUs at GTC in 2022, foreshadowing that its continued evolution of the series would eventually position it to compete with the broader CPU market. The new processors target both AI-centric and more general-purpose use-cases, with a heavy emphasis on the former, and Nvidia’s broadening of both the capabilities and its target markets will provide stiff competition for AMD and Intel as they battle for sockets in AI data centers. The chips are now in full production and will be available to Nvidia’s partners in the second half of this year. Let’s take a closer look at the new chips, and then the rack-scale architecture.

Nvidia Vera CPU specifications and performance

Nvidia designed the Vera CPU to provide the best of many worlds, with the intention of melding the high core counts of hyperscale cloud CPUs with the high single-thread performance of gaming CPUs and the power efficiency of mobile chips, all with the goal of speeding common GPU-driven tasks in agentic AI, training, and inference workloads, such as Python execution, SQL queries, and code compilation.

All told, Nvidia claims 1.5x the performance-per-sandbox over x86 competitors, 3x the memory bandwidth per core, and twice the efficiency. To meet those goals, the company designed an 88-core CPU with 176 threads, an increase over the first-gen Grace’s 72 cores. Nvidia also claims the cores offer a 1.5X improvement in instructions per cycle (IPC) throughput, a massive generational jump relative to other competing architectures, which tend to gain a single-digit or a low-teens percentage increase with each generation. With the previous-gen Grace, Nvidia used off-the-shelf Arm Neoverse cores, but the firm does stipulate that the new Olympus cores found on Vera are ‘Nvidia designed,’ signaling that the company has made custom modifications to the reference design.

The Arm v9.2-A Olympus cores feature spatial multi-threading, which physically isolates the various components of the pipeline by not time-slicing the key elements, like the execution units, caches and register files, with the other thread running on the same core. This contrasts with the standard time-slicing found in other simultaneous multi-threading (SMT) implementations, a process that has the threads take turns utilizing the resources. Spatial Multi-Threading increases Instruction Level Parallelism (ILP), throughput, and performance predictability by pulling instructions from other threads when execution elements are idle, thus ensuring full utilization.

In effect, this allows both threads to truly run simultaneously on a single core, whereas in a standard SMT implementation the threads essentially take turns running on a single core. Naturally, this will be a boon for multi-tenancy environments.

Nvidia arranges all 88 cores in a single domain, so there are no latency-inducing NUMA eccentricities to be found, in stark contrast to current high core-count x86 competitors. This has dramatic implications for latency, predictability, bandwidth, and ease-of-programmability. The firm has not shared the full details of how it accomplished this feat while maintaining adequate latency to each core, but the chip features a new generation of the Nvidia Scalable Coherency Fabric (SCF), a mesh topology built from Arm’s CMN-700 Coherent Mesh Network used in Grace’s Arm Neoverse cores. Arm has moved forward to the newer Neoverse CMN S3 mesh with its latest designs, and Vera likely employs that design, or a variant thereof.

The mesh network can deliver impressive memory throughput to the cores in aggregate, and even more when certain cores are more bandwidth-hungry than others. Grace supported 546 GB/s of memory throughput to the mesh, working out to an average of 7.6 GB/s per core. Vera more than doubles that to 1.2 TB/s of bandwidth fed by 1.5TB of SOCAMM LPPDDR5 modules (a 3x increase in capacity), which works out to an average of 13.6 GB/s per core in full-load conditions. Importantly, the architecture now supports up to 80 GB/s of throughput to any single core when load conditions aren’t consistent across the mesh, an impressive uplift for bandwidth-hungry threads.

The execution pathway includes a 10-wide Instruction Decode unit, a neural branch predictor that supports two branch predictions per cycle, a custom graph database analytics prefetch engine, and a PyTorch-optimized Instruction Buffer.

The chip fully supports Confidential Computing, a notable advance over Grace that allows for fully protected CPU+GPU domains. The CPU also features an NVLink-C2C die-to-die interface with up to 1.8 TB/s of throughput, a doubling of Grace’s 900 GB/s interconnect and seven times faster than PCIe 6.0. It also supports two-processor (2P) configurations.

Overall, Vera supports the full suite of technologies expected from a modern data center processor, including PCIe 6.0 and CXL 3.1 support, but with a bandwidth and latency-focused compute design that positions its uniquely well for use in AI workflows.

The Vera CPU Rack and Benchmark Performance

Grace has already served as a fundamental building block in many Nvidia GPU+CPU systems, including some of the fastest AI supercomputers on the planet, but Nvidia’s expanded goal is to leverage Vera in pure-play CPU racks that can be more widely deployed.

The Vera CPU rack meets that goal with 256 liquid-cooled Vera CPUs paired with 74 Bluefield-4 DPUs and ConnectX SuperNIC networking. The rack weighs in with up to 400 TB of LPDDR5 and 300 TB/s of aggregate memory throughput. That feeds the 45,056 threads, which Nvidia says supports 22,500 concurrent CPU environments running independently.

Nvidia shared benchmarks in a wide range of workloads, touting from a 1.8x to 2.2x performance improvement over Grace in scripting, compilation, data analytics, graph analytics, and HPC workloads, among others.

Naturally one would expect this system to be deployed at Meta, which recently announced its partnership with Nvidia for CPU-only systems, but Nvidia says it will also offer the Vera CPU rack system to hyperscalers, including Oracle, Coreweave, Nebius, Alibaba, and others.

A broad range of OEMs and ODMs will also provide single- and dual-socket servers for the broader market for a wide range of use cases, including industry heavyweights like Dell, HPE, Lenovo, Supermicro, Foxconn, and many others. The Vera CPUs will also be used for Nvidia HGX NVL8 systems.

Perhaps most importantly, these racks will also serve as an integral part of Nvidia’s broader Vera Rubin platform, which features seven chips in total, including the Rubin GPU, NVLink6 Switch for rack-scale interconnect, ConnectX-9 SuperNIC for networking, Bluefield 4 DPU, Spectrum-X 102.4T Co-packaged Optics switch, and Nvidia’s Groq 3 LPUs.

The Vera CPUs are in full production now and are slated for deliveries beginning in the second half of this year.

Nvidia has used its DLSS technology across several GPU generations to upscale lower-resolution images in our favorite games. At CES 2026, Nvidia introduced DLSS 4.5, along with Multi Frame Generation 6X, to reduce unwanted artifacts, improve overall image quality, and smooth frame pacing.

But just as soon as DLSS 4.5 was introduced, Nvidia has now given us a brief preview of the next-generation: DLSS 5.

According to Nvidia, this is the single most significant advancement in computer graphics since the introduction of ray tracing eight years ago.

DLSS 5 fundamentals are based on a new real-time neural rendering model that greatly ramps up photorealism in games by combining "photoreal lighting" and lifelike materials. Gone are the somewhat flat, uncanny-valley facial details on character models, and in their place are vastly superior hyper-realistic replacements. Nvidia promises that these improved visuals will enable ultra-smooth gameplay at up to 4K resolution.

According to Nvidia, unlike Video AI models, which must run offline and can produce unpredictable output, DLSS 5 operates in real time, using a game engine's motion vectors and source color as inputs for its AI model. Those inputs are then used to combine the aforementioned photoreal lighting and materials, delivering consistent performance frame-to-frame. DLSS 5 has been trained to apply its visual enhancements across various model details, including hair, skin, and even fabric.

Given that DLSS 4.5 was just introduced earlier this year, we still have quite a long runway before we reach DLSS 5. Nvidia is targeting a "Fall 2026" launch for DLSS 5, and it currently has some heavy hitters in the industry on board, including Ubisoft, Bethesda, Capcom, Tencent, and Warner Bros. Games (among others). Games currently on deck to receive DLSS 5 enhancements include:

• AION 2
• Assassin’s Creed Shadows
• Black State
• CINDER CITY
• Delta Force
• Hogwarts Legacy
• Justice
• NARAKA: BLADEPOINT
• NTE: Neverness to Everness
• Phantom Blade Zero
• Resident Evil Requiem
• Sea of Remnants
• Starfield
• The Elder Scrolls IV: Oblivion Remastered
• Where Winds Meet

Nvidia's GTC 2026 keynote has wrapped. During the two-hour (and change) presentation, Nvidia CEO Jensen Huang delivered several announcements, from new Vera CPUs to Groq LPUs, as well as laid out a vision for AI over the next 12 months.

As with any Nvidia event these days, we heard a lot about AI, as well as learned about Vera Rubin systems and DLSS 5. See our full live blog below.

We're moments away from GTC 2026

Hello and welcome to Tom's Hardware's live blog for the GTC 2026 keynote. Jensen Huang is moments away from taking the stage. Myself, Jake Roach, will be tending the blog while our very own Paul Alcorn and Jeffrey Kampman are on the ground to cover all of the announcements in real-time.

What to expect from GTC 2026

There's always room for surprises, especially at Nvidia's own GTC event, but there are a few key announcements we're focused in on:

• Intel x Nvidia partnership — Nvidia bought $5 billion in Intel stock last year, and at the time, announced that the two companies would be working together on custom x86 processors across both the data center and consumer PCs. The deal has apparently been decades in the making. It's not clear if we'll hear about consumer or enterprise chips, or both, but there's a good chance we'll hear something from the partnership.
• The 'future of real-time rendering' — Nvidia presented at GDC (not GTC) about neural rendering, but just a week later, the company is teasing that it will reveal the "future of real-time rendering" at GTC (not GDC). Maybe it's a new DLSS feature, maybe it's something completely new. We don't know, but Nvidia has already confirmed something is coming for gamers during the keynote.
• More on Vera Rubin — Nvidia officially launched its Vera Rubin NVL72 in January, and it started shipping samples to customers just weeks ago. These next-gen AI data center boards are on-track for the second half of the year, so we expect to hear a lot about them during the keynote.
• AI agents — Since the release of OpenClaw, the tech industry has been washed in talk of AI agents. Nvidia will talk about AI agents during the keynote, that much is almost guaranteed. We could see an announcement of "NemoClaw," which is an AI agent Nvidia is reportedly developing to compete with OpenClaw.
• Nvidia N1/N1X — Perhaps the biggest rumor around Nvidia over the past year has been the N1 and N1X, which are two SoCs reportedly being developed for the consumer market. Do we finally see a reveal at this year's GTC? Perhaps, but this is the last item on this list for a reason.

T-Minus 5 Minutes

Run to the bathroom, get your drink ready, and settle in. We're just a few minutes away from the start of GTC 2026. Jensen will probably start with a short history of Nvidia's role in AI, but we expect the announcements to rapid-fire out after that point. We're sat down in the SAP Center in San Jose and ready to dig in.

Running a bit behind schedule

We're a few minutes past the top of the hour, and we're still waiting on the keynote to start. In the meantime, a quick reminder that you can watch along with us through the live stream above.

That's... a lot of country music?

We're all sitting in surprise here at Tom's Hardware at the amount of country music playing before Jensen takes the stage. We're nearly a quarter past the top of the hour at this point and still waiting for the keynote to start. There's nothing wrong with country music, but rustic Americana and enterprise AI isn't a combo I'd normally expect.

And we're off!

We may have started a few minutes late, but the keynote has officially begun. We begin with a short video about AI tokens and all the wonderful things (according to Nvidia) we've all done with them, from healthcare to space to construction.

The man of the hour is here: CEO Jensen Huang

Jensen Huang has taken the stage in a familiar leather jacket. Sorry folks, there's no special jacket this time around. Jensen is starting off the show thanking some of the people that hosted the preshow leading up to the keynote.

'We've been working on CUDA for 20 years'

CUDA is one of the major reasons Nvidia is in the position it's in today, and this GTC marks the 20th anniversary of CUDA. "The single hardest thing is to have built up our install base, we're in every cloud and computer company in every single industry," says Jensen.

Pricing of Ampere in the cloud is going up

The prevalence of CUDA has accelerated what Nvidia calls a "flywheel." Nvidia attracts developers who develop on CUDA, which leads to more people adopting Nvidia hardware, and the lifecycle continues. Because of this, Jensen says the price of GPUs using the now-dated Ampere architecture has actually gone up in the cloud.

'GeForce is Nvidia's greatest marketing campaign'

Jensen says that "GeForce is Nvidia's greatest marketing campaign." It's an interesting way to frame the conversation, and one that Nvidia has been trying to crack for the past few years. Jensen paints a picture of Nvidia creating the first programmable shader 25 years ago, which eventually led to CUDA, and used GeForce as a vehicle to drive adoption.

Nvidia is showing off the next generation of computer graphics: DLSS 5

The first announcement is a big one: DLSS 5. Nvidia is showing it off in Resident Evil: Requiem, Hogwarts Legacy, and Starfield. We're all waiting eagerly to hear more details about what DLSS 5 includes, but the side-by-side comparisons are compelling.

What is DLSS 5?

Nvidia says it combined controllable 3D graphics and structured data with generative worlds. "This concept of fusing structured data with generative AI will repeat itself in one industry after another industry after another industry."

'This is my best slide'

Jensen jokes that he's going to spend the rest of the keynote going through the slide you can see above about structured data. This is "the ground truth" of enterprise computing.

AI can solve unstructured data, says Jensen

Jensen is describing the importance of AI in unstructured data. He says this data makes up 90% of the world's data but it's been "useless" because you can't search or query it. IBM, the inventor of SQL, is accelerating WatsonX data with the cuDF acceleration framework.

More Moore's Law talk

Jensen likes to talk about the death of Moore's Law, and he's doing so once again. "Moore's Law has run out of steam, accelerated computing allows us to take giant leaps forward." Jensen is showing off an example with Google Cloud and showing how Nvidia's acceleration can be repeated across companies and industries.

Nvidia is bringing OpenAI to AWS this year

"As you know, [OpenAI] is completely compute-constrained." Jensen says that OpenAI will come to AWS this year, hopefully lightening the load on its massive infrastructure demand.

'Vertically integrated but horizontally open'

Jensen describes Nvidia as "vertically integrated but horizontally open," which may or may not raise some eyebrows at the FTC. Regardless, Nvidia says there's "no other way" it can be given what it's trying to do with accelerated computing, delivering the entire stack to customers.

Nvidia says it needs domain-specific libraries to address the needs of different industries

AI has a lot of applications, but Jensen says it isn't as simple as throwing GenAI at the wall and hoping it sticks. "We have to have domain-specific libraries that solve problems in every one of these verticals," he says.

Bringing it back to CUDA

"We are an algorithm company," says Jensen, after spending 10 minutes talking about the applications of Nvidia's software stack in just about every industry. Everything comes back to Nvidia's CUDA-X libraries, and Jensen describes them as the "crown jewel" of the company.

cuDNN is what caused the 'big bang' of AI

Nvidia says cuDNN, or CUDA Deep Neural Network, is one of the most important libraries the company has ever made, saying it caused the "big bang" of modern AI. Nvidia is showing a short video about its various CUDA-X libraries, including a life-like video that's entirely simulated.

Nvidia 'reinvented computing'

Jensen is talking about some of the many "AI native" companies, which are only possible because Nvidia "reinvented computing," says the executive. We're at the beginning of a new platform shift, he says, and it's akin to the PC revolution. This really kicked off over the past two years with ChatGPT kicking off the generative AI era.

An accelerated timeline of AI

There's been rapid AI development over the past few years. In 2023, it was ChatGPT. In 2024, it was reasoning models like o1, and in 2025, it was huge models with massive context windows like Claude Code. It's the first "agentic model," says Jensen. The executive says 100% of Nvidia is using Claude Code, along with other models. In 2026, Nvidia says we've reached an "inflection point for inference."

Nvidia says it's going to double demand through the next year

Last year, Nvidia said it saw about $500 billion of high confidence demand and purchase orders for Blackwell and Rubin through 2026. "I see through 2027 at least $1 trillion," says Jensen. "Now, does it make any sense?" Jensen says that's what he's going to spend the rest of the keynote talking about.

Nvidia is the only company that runs every domain of AI across every domain of AI models

Jensen says Nvidia is the only company that runs every domain of AI across every domain of AI models. Between Nvidia, Anthropic, and Meta SL, Jensen says that represents a third of the world's AI compute. Nvidia says it's proven that "you can build with complete confidence" as an AI infrastructure company.

Nvidia says Grace Blackwell was 'a giant bet'

Nvidia NVL72 was a "giant bet," says Jensen, and he thanked Nvidia's partners for sticking with the company. "It wasn't easy for anybody... inference is the ultimate hard." The bet paid off, according to Nvidia, which you can see in the slide above.

50x performance per watt, 35x lower cost

"Nobody believed me," says Jensen. When Nvidia says it delivered 30x better performance per watt, on NVL72, it was wrong. Apparently, it delivers 50x better performance per watt. Jensen once again goes back to Moore's Law, saying it would maybe deliver 1.5x perf in a year.

'It's now a factory to generate tokens'

Jensen says data centers used to be a place to store files, and they're now a factory to generate tokens. Inference is the workload and tokens are the new commodity, says Nvidia. Now, onto a short video showing how we got here.

Vera Rubin joins Jensen on stage

Vera Rubin NVL72 is the "engine supercharging the era of agentic AI." A new addition is the Groq 3 LPX tray, and as a whole, Nvidia says it's delivered 40 million times more compute over the past decade. Jensen is showing off Vera Rubin on stage; the whole thing. It's "one giant system."

Jensen says the Vera CPU is designed for high single-threaded performance, and the company built it go along with its racks for agentic processing.

Learn more about Nvidia's Vera CPU

The 88-core Vera CPU fits into a rack with 256 chips, each of them liquid-cooled. If you want to dig in deep on Nvidia's latest chip that aims to take on AMD and Intel, take a look at our Vera CPU deep dive.

Groq 3 LPU and Groq LPX join the fray

A new addition to the system is a Groq LPX rack, which we learned about ahead of GTC. You can read Jeffrey Kampman's breakdown of Groq 3 in Vera Rubin now.

Jensen shows off NVLink for Rubin Ultra

Jensen explains how NVLink for Rubin Ultra works, with compute sitting in the front and the scale-up fabric in the back.

This is 'the most important chart' for companies, says Nvidia

Tokens are "the new commodity," according to Nvidia. For businesses, Nvidia says that the throughput of an AI factory at iso power is something that will be "studied for years." More tokens means smarter models, and the smarter the models get, you need better token throughput. Nvidia says that, at every tier, Vera Rubin delivers much higher throughput.

Low latency and high throughput are 'enemies of each other'

Groq is important for Nvidia because it pushes beyond the limits of NVL72. With Groq LPX, Nvidia says it's able to deliver up to 10x in revenue to companies using Vera Rubin. It helps solve the problem of delivering low latency and high throughput, which Jensen described as "enemies of each other."

Nvidia combined one chip for high throughput and one for low latency, which it achieved with disaggregated inference.

Vera Rubin sampling is going 'incredibly well'

Jensen admits that the Grace Blackwell sampling had some issues, but apparently Vera Rubin sampling is going smoothly. In fact, the first Vera Rubin is system is apparently already running in Microsoft's Azure Cloud.

Vera Rubin is 7 chips across 5 rack systems

Vera Rubin is undoubtedly Nvidia's most ambitious system to date, featuring seven chips across five rack systems. Compared to x86 and Hopper, Nvidia says Vera Rubin is able to deliver 700 million tokens per second compared to just 2 million

Here's Nvidia roadmap

Jensen is teasing next-gen Feynman systems. It has a new GPU, new LPU, new CPU called Rosa, Bluefield 5, and Kyber with copper and CPO scale up. Feynman systems are on-track for 2028, so we'll hear a lot more about them throughout the year. At next year's GTC, we'll probably run back the same talking point with Feynman that we hard about with Vera Rubin this year.

Meet me in the Omniverse

Nvidia built Omniverse to meet suppliers virtually, allowing co-design in the data center at a much broader scale. The goal is to leave "no power squandered." They're blueprints for AI factories, which Nvidia calls its DSX platform.

Data centers are going into space

Nvidia is working on a system called Vera Rubin Space-1, which will be the first data center in space. Sounds like we're in early stages, but Nvidia has "a lot of great engineers" working on it.

NemoClaw makes using OpenClaw easy

Nvidia is streamlining the process of setting up an AI agent with OpenClaw. Type two lines of shell commands, and you're off to the races with an AI agent. From there, Nvidia says you just need to give it a task and let the agent run its course.

What is OpenClaw? Nvidia says it's an OS

Now Jensen is describing what OpenClaw is, which is a description no one in the room at GTC actually needs. For anyone who isn't aware, it's an agent that can connect to cloud systems. It can spawn other agents, do scheduling, decompose a problem, etc. Jensen says it's an operating system. "It's no different than how Windows allowed us to make personal computers."

Nvidia worked with OpenClaw to make it enterprise-secure

NemoClaw is enterprise-secure, helping protect sensitive information. AI agents can communicate externally and execute without intervention, which is obviously a problem. NemoClaw provides a reference software stack for businesses to keep OpenClaw secure.

Nvidia is building a Nemotron coalition

Nvidia says that Nemotron 3 Ultra will be the best base model in the world. In order to scale out Nemotron, Nvidia is creating a coalition for Nemotron 4, including companies like Black Forest Labs, Perplexity, Mistral, and Cursor.

Bringing agents to the physical world

Nvidia is showing off 110 robots at GTC, showcasing its "physical AI." Nvidia announced several new partners, including four new partners for robo-taxis, including BYD, Hyundai, and Nissian. Nvidia is also partnering with Uber, connecting robo-taxis into Uber's network in select cities.

Olaf joins Jensen on stage

In a not-at-all-awkward meeting, Olaf from Frozen joins Jensen on stage. The executive is now describing the various AI models used to make Olaf, which is... something. Anyway, Olaf is helping close out the keynote.

That's a wrap, with country song that's probably generated by AI

Well, we're done now, I guess. Nvidia closed out its keynote with an animation of several robots (plus Jensen) sitting around a fire singing a song about the keynote. It's a country song, and probably generated by AI? I don't really know what to say about this one. A rough-talking robot singing about tokens and open-source software wasn't on my bingo card.

The biggest developer artificial intelligence conference, GTC, takes place in San Jose, California, from March 16 to March 19, 2026.

Tom's Hardware will be on the ground, attending keynotes, important conferences, and reporting on some of the latest upcoming AI technology from the show.

This year promises to be another exciting event, starting with a keynote with Nvidia CEO Jensen Huang.

▪️Nvidia Keynote - Monday, March 16, 2026, at 11:00 a.m. PT

Nvidia is reportedly planning to launch an AI agent that will compete with OpenClaw. According to Wired, the company calls it “NemoClaw,” and it’s designed for use in enterprise environments, with the company offering the security and privacy that many companies require when running AI tools. More important, it’s said that the Nvidia AI agent will be open-source, making it easy for anyone who wants to use it to customize it to their needs.

The new tool has already been offered to various Nvidia partners, including Adobe, Cisco, CrowdStrike, Google, and Salesforce, although none have confirmed interest in it. According to the report, the new tool will work on any hardware, not requiring Nvidia's chips to run.

While generative AI tools are quite powerful when it comes to reasoning, they still require human intervention to execute workloads. So, to increase its automation and allow it to accomplish tasks, you need an AI agent to orchestrate the operation independently. While Clawdbot/Moltbot/OpenClaw did not pioneer the idea of an AI agent, it popularized using the tool with any LLM, giving users unprecedented capabilities with their AI tools. It has gotten to the point that high-end Apple Macs configured with massive amounts of Unified Memory are in short supply because of the massive interest from consumers.

Using this tool comes with its own risks, however, such as malicious “skills” targeting crypto users being uploaded to ClawHub. Even Meta Director of Alignment Summer Yue got burned by this AI agent after it started deleting emails in her personal inbox, despite giving it instructions not to do anything without her specific say-so. Nvidia’s NemoClaw will hopefully not have these issues, especially as it has the weight of the company driving the current AI infrastructure buildout behind it.

Another probable reason that the company is pushing NemoClaw towards its customers is that it wants to capture the corporate market early. This is especially true as OpenAI hired Peter Steinberger, the “genius” creator of OpenClaw, in February 2026 — some three months after the launch of their AI agent — to work on smart agents for the company. While OpenClaw will remain open source, hiring Steinberger gave the creator of ChatGPT the brilliant mind behind the tool, allowing it to make its models far more useful to the average user.

Nvidia's GTC conference begins March 16 -- if the rumors are true, expect to hear more about NemoClaw there.

We've been waiting for Nvidia's return to the consumer SoC market for a while, ever since the company's partnership with MediaTek was first announced. The N1/N1X chips, born from this partnership, have been in the rumor mill for ages, but it finally feels like the time is right, with major leaks intersecting recently. Now, a new report from The Wall Street Journal says the N1/N1X SoCs are ready to launch in the first half of 2026.

"People familiar with Nvidia’s supply chain said PC makers including Dell Technologies and Lenovo were working with the chip maker on models using the Nvidia-MediaTek system-on-a-chip, which is built on architecture from U.K. chip designer Arm. The first PCs with the chip could come in the first half of this year, they said."

The excerpt above implies that Dell & Lenovo would be among the first OEMs to debut the N1 silicon, and that the initial models will start rolling out in H1 2026. The timeframe aligns with previous reports where DigiTimes said N1X-based laptops were set to release this quarter. Prior to that, a shipping manifest (dated November 2025) leaked out showing a 'Dell 16 Premium' laptop with an N1X engineering sample.

As a reminder, the N1 and N1X chips are Arm-based SoCs from Nvidia, purportedly featuring up to 20 CPU cores (split across two 10-core clusters) and a rumored RTX 5070-level integrated GPU. CEO Jensen Huang has confirmed that the GB10 Superchip powering the DGX Spark mini-PC is actually based on N1 silicon, so it's already out there... just not with the gaming-focused slant we expect from the N1.

These SoCs are aimed at consumers looking for thin and light devices that can stand toe-to-toe with Apple's MacBook lineup, according to WSJ. The M-series chips in those laptops are also Arm-based and, so far, Microsoft doesn't have a proper answer to those with its Windows-on-Arm initiative. Qualcomm's efforts haven't been able to replicate that level of success, due to both laggardly GPU drivers and spotty compatibility with x86 applications.

Nvidia, of course, is a GPU manufacturer, so irrespective of the Arm CPU cores, we can expect the N1/N1X chips to be targeted at gaming. The company already supplies the chips for the Nintendo Switch 2, but the last time we saw it release a chip to the public was back in 2015 with the Tegra X1 (which also powered the original Switch). Therefore, a return to this segment has been a long time coming. Over the past decade, Nvidia has mainly focused its SoC development at the robotics and automotive markets.

Apart from the N1, Nvidia is also partnered with Intel to develop "Intel x86 RTX SOCs," which would combine Intel's CPU cores with an Nvidia GPU chiplet on a single package. Apart from the architectural differences of x86 versus Arm, this silicon would likely be much more powerful and at least a couple of years out at this point, but the WSJ report still mentions it.

Following several rumors that touted a 2025 release as early as 2024, we eventually learned that the N1/N1X chips have been pushed back to 2026. It's possible the upcoming Nvidia GTC, planned for March 16-19, is likely the stage where these chips will be unveiled. Pricing will remain a key factor in its prevalence; Jason Tsai of DigiTimes said that "it may remain a niche luxury product" unless it lands around the $1,500 range.

Unsuspecting YouTube viewers looking for Nvidia's GTC keynote on Tuesday might well have found themselves accidentally watching an AI-generated Jensen Huang deepfake promoting a cryptocurrency scam, after YouTube promoted the video over the official stream.

As spotted by eagle-eyed Dylan Martin on X, the stream (now disabled) was actually hosted by a channel called Offxbeatz.

"Heads up: There's a fake Nvidia GTC DC keynote stream happening now on YouTube hosted by a channel called NVIDIA Live," Martin warned. "It appears to be a deepfake of Jensen Huang promoting a "crypto mass adoption event." Obviously don't do anything to connected to that QR code."

Around 20 minutes after the real keynote went live, there were some 90,000 people watching the fake live stream, with Martin noting that it was even the top result on YouTube if you searched for Nvidia GTC DC, a perfectly plausible query for anyone trying to watch the video. At one point, there were some 95,000 people watching the fake crypto scam stream and only 12,000 people watching the real stream as Jensen Huang took to the stage to share the latest from Nvidia. (Expand the below tweet to see the thread.)

A marvel of the modern AI world we live in, Martin was even able to generate an Otter AI transcription of the scam. Fake Jensen welcomed everyone to the event before stating, "But before we get into the keynote, I've got a surprise that's too exciting to wait. We're postponing the main talk for just a moment to announce something truly special, a crypto mass adoption event that ties directly into Nvidia's mission to accelerate human progress."

Fake Jensen went on to emphasize that the move was not just a random stunt, hailing Nvidia GPUs for powering Ethereum smart contracts, high-speed Solana transactions, and efficient cross-border payments with XRP. This is, of course, all nonsense. The scam, replete with a QR code for duped viewers to engage with, offered a crypto distribution scheme, calling on viewers to send in supported cryptocurrencies.

Nvidia’s keynote speech at GTC Paris was big, with many announcements that make us feel for the blistered fingers of the copywriters in Nvidia’s newsroom – though if it used AI to generate them, we wouldn’t be surprised. Just about everything out of CEO Jensen Huang’s mouth was prefaced by the term “AI” in some way or another, and no wonder: Nvidia continues to bet big on AI, and it’s doing it in truly international fashion. If you missed Huang's keynote, you can find it below.

Tokenizing Europe

What began as an evangelizing of the tokenization of computing quickly pivoted into a discussion on Nvidia’s major investments and partnerships in the European theater. These are broad and comprehensive, with Nvidia announcing deals with companies in France, Italy, Germany, Spain, Poland, the UK, Sweden, and Finland, among others.

It’s partnering with a range of telecom companies to push the development of sovereign artificial intelligence infrastructure. Some of that is in the development of its “AI Factories” idea, with Telenor in Norway helping to build a new AI data center, and Telefónica in Spain deploying Nvidia GPUs on scale in a new edge AI initiative.

Nvidia is also working with national governments to build and expand AI Technology Centers, which are designed to help train up the people who will work with future AI developments, as well as accelerate scientific research with AI in collaboration with academic institutions. “By building Europe’s first industrial AI infrastructure, we’re enabling the region’s leading industrial companies to advance simulation-first, AI-driven manufacturing.”, Huang said at the GTC Paris keynote.

These announcements were backed by national figures like French President Emmanuel Macron and the UK’s Technology Secretary Peter Kyle, who likened the use of AI to the adoption of coal to generate the electricity that powered the industrial revolution.

In total, Nvidia claimed to be deploying over 3,000 exaflops of Blackwell computing power in its range of European initiatives. Nvidia claims this will come from over $20 billion in EU investment in AI, including over 10,000 GPUs in the form of DGX B200 systems and RTX PRO servers at a single facility in Germany alone.

Huang also made a noteworthy push to frame many of these investments as building out sovereign AI solutions. This seems like a way to get ahead of concerns about an over-reliance on the US and companies like Nvidia. With the on-again, off-again trade tariffs from the Trump administration, and ongoing questions about global shipping times and technology availability, this seemed particularly poignant.

I am Gr00T

More immediate in both timescale and physicality, Huang also talked about how Nvidia and its partners are using agentic AI to introduce a new generation of robots to the workplace, smart cities, and our homes. Alongside European partners showcasing their own AI-driven robots accelerated by Nvidia hardware, Huang talked about Nvidia Isaac Gr00T N1.5, a foundational model for humanoid robot reasoning and skills that’s now available to download. This includes new robotics simulation frameworks, which have been optimized for Nvidia’s RTX Pro 6000 workstations.

Again, seeming to get ahead of concerns and misgivings, Nvidia highlighted its Halos platform, a comprehensive safety system for robotic hardware. That includes an extension package for its IGX platform, which makes it easier to program safety functions into the robots, and an AI-powered agent that can monitor the robot’s operations to improve its safety over time.

Nvidia also talked up how its virtual training ecosystems were accelerating robotic development and training, allowing for faster iteration and innovation in this burgeoning space.

Hitting the road (not pets or people)

Some people have been hyping up self-driving cars for over a decade, but Nvidia is confident it really is becoming more of a viable reality. To showcase that, Huang highlighted how Nvidia had won the CVPR End-to-End AV Grand Challenge for autonomous driving for the second year in a row.

This year, Nvidia was able to take the top spot thanks to its development of the Generalized Trajectory Scoring for End-to-end Multimodal Planning, or GTRS. Designed to help autonomous cars handle dramatically shifting traffic conditions or sudden events that require bespoke solutions, GTRS proved effective at selecting from a wide range of potential responses.

Focusing on safety, comfort, and traffic rule compliance, GTRS was able to break down what was happening and find subtle differences between it and competing scenarios to find the most appropriate response.

Huang also discussed how Nvidia is furthering autonomous driving research and training by using virtual worlds to massively ramp up the amount of data it can feed its AI systems. By leveraging imaginative, synthesized scenarios, Nvidia is able to train autonomous driving algorithms on a much broader array of scenarios than real-world driving can manage alone.

Assuaging concerns, massaging wallets

Thought it was hard to get an Nvidia RTX 50-series Blackwell GPU? Things are potentially going to get even more difficult, as Nvidia has now revealed its Blackwell RTX Pro series of graphics cards. These will target both laptops and desktops, as well as standalone PCs and data center products.

We've heard from some people at GDC/GTC that Nvidia is working to improve the supply of all of its Blackwell GPUs, and some even suggested we "might" see supply finally start to catch up to demand by May/June — meaning we could see MSRP-priced models on sale and readily available. We'll believe that when we see it.

We expected the Blackwell professional announcement, and certainly Nvidia would know it was incoming and would plan for the increased production required. But we would also say the same of the RTX 50-series launches. Nvidia should have known demand would be high, and yet the supply has been woefully insufficient.

And given the choice between shipping GB202/GB203/GB205 GPUs as consumer parts with an ostensible $550~$2,000 MSRP, or shipping professional and data center parts that can cost five times as much (or more), we suspect the latter category will be served first whenever possible.

Details on the specifications and configurations (some of them, anyway) were shared after the keynote, and the higher solutions will use the same GB202 chip as the GeForce RTX 5090, but with a dramatically altered memory configuration. The top RTX Pro 6000 will also be equipped with 24Gb (3GB) GDDR7 chips, the same chips that are currently going into the RTX 5090 Laptop GPU.

24Gb chips potentially bumps the memory configuration from 32GB on a 512-bit interface to 48GB, or from 16GB on a 256-bit interface (for lower tier parts) to 24GB, and for a 192-bit interface there will be 18GB options. But that's only part of the potential upgrade.

As we've traditionally seen with professional and data center solutions, Nvidia will ship some products with memory chips in "clamshell" mode — with GDDR7 chips on both sides of the PCB. That doubles the maximum capacity for every interface width, yielding up to 96GB for GB202 and its 512-bit interface, up to 48GB for GB203 and its 256-bit interface, and up to 36GB for GB205's 192-bit interface.

And that's not some hypothetical number. Nvidia has stated that it will have a Blackwell RTX Pro GPU with 96GB of GDDR7 memory, with ECC enabled. Laptops on the other hand look like they'll stick to similar capabilities as the RTX 50-series mobile solutions, with an RTX Pro solution sporting up to 24GB — the same as the RTX 5090 Laptop GPU, which uses the GB203 silicon.

At present, the four workstation models only use two of the Blackwell chips: GB202 and GB203. The RTX Pro 6000 uses a near-complete GB202, with 188 of the potential 192 SMs. It also has the full 128MB L2 cache, and the aforementioned 96GB of GDDR7 ECC memory, with 16 chips on each side of the PCB. It also has the full complement of four NVDEC/NVENC units for video encoding/decoding. Power use for the workstation and server variants is set to 600W max (the Server Edition has a configurable TDP), while the Max-Q variant clamps the power limit to 300W.

Nvidia didn't disclose clocks or theoretical TFLOPS on the other three RTX Pro GPUs, so we've just estimated 2.5GHz for now. The step-down RTX Pro 5000 still uses GB202, just trimmed down quite a lot. It has 110 SMs enabled, which is only 57% of the computational elements. It also has four of the 32-bit memory interfaces disabled, giving it a 384-bit interface. Nvidia sticks with the more readily available 16Gb (2GB) GDDR7 chips as well, with 12 on each side of the PCB yielding 48GB of total VRAM — with no mention of the L2 cache size, though we suspect it will have 96MB. Along with the other reductions, the RTX Pro 5000 has just two NVENC/NVDEC units enabled. It has a 300W TDP.

Nvidia's RTX Pro 4500 switches to the GB203 chip, the same chip found in the RTX 5080 and 5070 Ti. It's also a nearly complete solution, with 82 of the potential 84 SMs enabled alongside all eight memory channels. Like the RTX Pro 5000, it uses 2GB GDDR7 modules in clamshell mode, for 32GB of total VRAM. It also features two NVENC/NVDEC units, and a power limit of just 200W — surprisingly low, considering it's otherwise similar to the RTX 5080 that has a 360W TGP.

Last  up, the RTX Pro 4000 also uses the GB203 chip, with some severe trimmings in some areas. It has 70 SMs enabled, the same as the RTX 5070 Ti, but the memory interface is only 192 bits wide, the same as the RTX 5070. Nvidia sticks with the 2GB GDDR7 modules as well, which in clamshell mode gives the GPU 24GB total VRAM. Dual NVENC/NVDEC are again present, and the power limit gets slashed to just 140W.

All of the models feature a full PCIe 5.0 x16 slot, with 16-pin 12V-2x6 connectors. Nvidia had the RTX Pro 6000 variants on display, which appear to be launching first. The other RTX Pro models will presumably launch in the coming months, and it's not clear when exactly the laptop solutions will become available.

Nvidia also announced a change in branding, if you didn't notice. Where the previous professional and data center solutions were sold under various RTX names (RTX A6000/A5500/A5000/etc. for Ampere, then RTX 6000/5000/4500/etc. for Ada), the new Blackwell generation of professional and data center GPUs will use RTX Pro nomenclature.

Nvidia already listed the RTX Pro 6000/5000/4500/4000 series GPU names for desktops. For laptops, there will be RTX Pro 5000/4000/3000/2000/1000/500 models, and for data center so far there's only an RTX Pro 6000. That last will, naturally, be the full-fat model with 96GB of GDDR7 ECC memory, taking over from the Nvidia L40.

We're glad to see the change in naming, as things were becoming a bit obfuscated after Nvidia killed off its Quadro branding several generations back. Now, RTX Pro will very clearly indicate that something is different from the standard GeForce RTX lineup.

There's still the matter of those numbers, however. RTX Pro 6000 quite obviously implies a Blackwell GPU for now, but what will happen with the next generation Rubin (or whatever the codename ends up being for the non-DC parts) GPUs? This is where the Ampere RTX A6000 branding made sense, but Ada parts dropped the "A" and things became a little fuzzy. Hopefully, that's something Nvidia addresses when those future products finally arrive.

The Nvidia Blackwell RTX Pro 6000 GPU was announced during the GTC 2025 keynote. These will use the same GB202 die that goes into Nvidia's RTX 5090 graphics card, but with some significant changes in some of the other aspects. There will be three variants of the RTX Pro 6000: the Blackwell Workstation Edition, Max-Q Workstation Edition, and Blackwell Server Edition.

The core specifications for the RTX Pro 6000 are the same across all three models. You get 188 SMs enabled, out of a potential 192 maximum from GB202. That's 10.6% more SMs, shader cores, tensor cores, RT cores, etc., relative to the RTX 5090. Clock speeds weren't given, but Nvidia does list up to 125 TFLOPS of FP32 compute via the shaders, and 4000 AI TOPS from the tensor cores. That works out to a boost clock of around 2.6 GHz, but that won't be the same for all three variants.

The RTX Pro 6000 features the full 128MB L2 cache of GB202, along with four NVENC and four NVDEC video blocks. RTX 5090 only has 96MB of L2 cache and three each for NVENC/NVDEC. It's very close to a fully enabled chip, with only 2% of the SMs disabled.

The memory configuration is the same for all three variants. As discussed in the initial RTX Pro 6000 announcement, Nvidia uses 24Gb (3GB) GDDR7 chips rather than the 2GB chips used on the consumer GeForce RTX 50-series cards. That increases the memory capacity to 48GB per PCB side, and with chips on both sides of the PCB in 'clamshell' mode, there's 96GB total. The memory has the same 28 Gbps clocks as most of the 50-series parts, with 1792 GB/s of total bandwidth.

The Blackwell Workstation Edition looks basically the same as the RTX 5090, except with a glossy black finish in places rather than a matte black. TDP (TGP) for the card is 600W, 25W higher than the 5090, but otherwise, the two cards look about the same. You also get four DisplayPort 2.1b outputs, whereas the 5090 typically offers at least one HDMI 2.1b output.

For the Max-Q Workstation Edition, the TGP gets capped at 300W. Half the power will naturally mean lower typical boost clocks for a lot of workloads, though there will undoubtedly be cases where it will still run nearly as fast as the 600W card. It also has a standard FHFL (full-height, full-length) dual-slot form factor with dual-blower fans at the back of the card. It also has four DP2.1b outputs.

Finally, the Blackwell Server Edition has a similar form factor to the Max-Q card but ditches the fans, instead relying on the server fans to provide airflow and cooling. That's usually in ample supply for servers, and noise levels are usually less of a concern — you get high RPM fans moving lots of air in a regulated environment to make everything run sufficiently cool. The power on the Server Edition is configurable up to 600W, so some installations might opt for lower power to optimize the efficiency if they're power-limited.

All three models use the same 16-pin connector found on desktop RTX cards. Servers and workstations tend to be built to much tighter specifications, and so far there haven't been any widespread reports of servers or workstations with melting connectors. That suggests perhaps that the biggest issues with 16-pin connectors are component quality and proper installation — companies are less likely to cheap out on the cables in a server or workstation, so there aren't impurities causing hot spots and melting.

Pricing hasn't been discussed, but we typically see professional and server solutions like the RTX Pro 6000 selling for 4X~5X more than the equivalent consumer GPUs. It wouldn't be surprising if the various RTX Pro 6000 cards cost $10,000 or more. We'll find out exactly where they fall in the coming days.

Nvidia announced updates to its data center roadmap for 2026 and 2027 at the company's GTC 2025 conference today, showcasing the planned configurations for the upcoming Rubin (named after astronomer Vera Rubin) and Rubin Ultra.

Even though the company has just finished bringing Blackwell B200 into full production, and has Blackwell B300 slated for the second half of 2025, Nvidia is already looking forward to the next two years and helping its partners plan for the upcoming transitions.

One of the interesting points made is that "Blackwell was named wrong." In short, Blackwell B200 actually has two dies per GPU, which CEO Jensen Huang says changes the NVLink topology.

So even though the company calls the current solution Blackwell B200 NVL72, Huang says it would have been more appropriate to call it NV144L. Which is what Nvidia will do with the upcoming Rubin solutions.

Above we have the Rubin NVL144 rack that will be drop-in compatible with the existing Blackwell NVL72 infrastructure. We have the same configuration data for the Blackwell Ultra B300 NVL72 in the second slide for comparison. Where B300 NVL72 offers 1.1 EFLOPS of dense FP4 compute, Rubin NVL144 — that's with the same 144 total GPU dies — will offer 3.6 EFLOPS of dense FP4.

Rubin will also have 1.2 ExaFLOPS of FP8 training, compared to only 0.36 ExaFLOPS for B300. Overall, it's a 3.3X improvement in compute performance.

Rubin will also mark the shift from HBM3/HBM3e to HBM4, with HBM4e used for Rubin Ultra. Memory capacity will remain at 288GB per GPU, the same as with B300, but the bandwidth will improve from 8 TB/s to 13 TB/s. There will also be a faster NVLink that will double the throughput to 260 TB/s total, and a new CX9 link between racks, with 28.8 TB/s (double the bandwidth of B300 and CX8).

The other half of the Rubin family will be the Vera CPU, replacing the current Grace CPUs. Vera will be a relatively small and compact CPU, with 88 custom ARM cores and 176 threads. It will also have a 1.8 TB/s NVLink core-to-core interface to link with the Rubin GPUs.

Rubin Ultra will land in the second half of 2027, and while the Vera CPU will remain, the GPU side of things will get another massive boost. The full rack will be replaced by a new layout, NVL576. Yes, that's up to 576 GPUs in a rack, each with an unspecified power consumption.

The inference compute with FP4 will rocket up to 15 ExaFLOPS, with 5 ExaFLOPS of FP8 training compute. It's about 4X the compute of the Rubin NVL144, which makes sense considering it's also four times as many GPUs. The GPUs will feature four GPU dies per package this time, in order to boost the compute density.

Where the NVL144 Rubin solution has 75TB total of "fast memory" (for both CPUs and GPUs) per rack, Rubin Ultra NVL576 will offer 365TB of memory. The GPUs will get HBM4e, but here things are a bit curious: Nvidia lists 4.6 PB/s of HBM4e bandwidth, but with 576 GPUs that works out to 8 TB/s per GPU. That's seemingly less bandwidth per GPU than before.

Perhaps it's a factor of how the four GPU dies are linked together? There will also be 1TB of HBM4e per four reticle-sized GPUs, with 100 PetaFLOPS of FP4 compute.

The NVLink7 interface will be 6X faster than on Rubin, with 1.5 PB/s of throughput. The CX9 interlinks will also see a 4X improvement to 115.2 TB/s between racks — possibly by quadrupling the number of links.

Obviously, there's plenty we don't yet fully know about Rubin and Rubin Ultra, but those details will get fleshed out in the future. Data centers need a lot more planning than consumer GPUs, so Nvidia has shared full details well in advance of the products being ready to ship. And it's not quite done...

After Rubin, Nvidia's next data center architecture will be named after theoretical physicist Richard Feynman. Presumably that means we'll get Richard CPUs with Feynman GPUs, if Nvidia keeps with the current pattern.

The Nvidia Blackwell Ultra B300 data center GPU was announced today during CEO Jensen Huang's keynote at GTC 2025 in San Jose, CA. Offering 50% more memory and FP4 compute than the existing B200 solution, it raises the stakes in the race to faster and more capable AI models yet again. Nvidia says it's "built for the age of reasoning," referencing more sophisticated AI LLMs like DeepSeek R1 that do more than just regurgitate previously digested information.

Naturally, Blackwell Ultra B300 isn't just about a single GPU. Along with the base B300 building block, there will be new B300 NVL16 server rack solutions, a GB300 DGX Station, and GB300 NV72L full rack solutions. Put eight NV72L racks together, and you get the full Blackwell Ultra DGX SuperPOD: 288 Grace CPUs, 576 Blackwell Utlra GPUs, 300TB of HBM3e memory, and 11.5 ExaFLOPS of FP4. These can be linked together in supercomputer solutions that Nvidia classifies as "AI factories."

While Nvidia says that Blackwell Ultra will have 1.5X more dense FP4 compute, what isn't clear is whether other compute have scaled similarly. We would expect that to be the case, but it's possible Nvidia has done more than simply enabling more SMs, boosting clocks, and increasing the capacity of the HBM3e stacks. Clocks may be slightly slower in FP8 or FP16 modes, for example. But here are the core specs that we have, with some inference of other data (indicated by question marks).

We asked for some clarification on the performance and details for Blackwell Ultra B300 and were told: "Blackwell Ultra GPUs (in GB300 and B300) are different chips than Blackwell GPUs (GB200 and B200). Blackwell Ultra GPUs are designed to meet the demand for test-time scaling inference with a 1.5X increase in the FP4 compute." Does that mean B300 is a physically larger chip to fit more tensor cores into the package? That seems to be the case, but we're awaiting further details.

What's clear is that the new B300 GPUs will offer significantly more computational throughput than the B200. Having 50% more on-package memory will enable even larger AI models with more parameters, and the accompanying compute will certainly help.

Nvidia gave some examples of the potential performance, though these were compared to Hopper, so that muddies the waters. We'd like to see comparisons between B200 and B300 in similar configurations — with the same number of GPUs, specifically. But that's not what we have.

By leveraging FP4 instructions, using B300 alongside its new Dynamo software library to help with serving reasoning models like DeepSeek, Nvidia says an NV72L rack can deliver 30X more inference performance than a similar Hopper configuration. That figure naturally derives from improvements to multiple areas of the product stack, so the faster NVLink, increased memory, added compute, and FP4 all factor into the equation.

In a related example, Blackwell Ultra can deliver up to 1,000 tokens/second with the DeepSeek R1-671B model, and it can do so faster. Hopper, meanwhile, only offers up to 100 tokens/second. So, there's a 10X increase in throughput, cutting the time to service a larger query from 1.5 minutes down to 10 seconds.

The B300 products should begin shipping before the end of the year, sometime in the second half of the year. Presumably, there won't be any packaging snafus this time, and things won't be delayed, though Nvidia does note that it made $11 billion in revenue from Blackwell B200/B100 last fiscal year. It's a safe bet to say it expects to dramatically increase that figure for the coming year.

Nvidia’s annual GPU Technology Conference (GTC) is happening today, and Jensen Huang is set to give the keynote address this morning. The multi-day event focuses on artificial intelligence, computer graphics, and other technologies that rely on GPUs' specialized computational power. The keynote address will happen live at the SAP Center in San Jose, California at 10 am Pacific Time, but it will also be live-streamed to a global audience via YouTube.

A pre-broadcast livestream, Live at Nvidia GTC with Acquired, will start on YouTube at 8 am Pacific Time. The company says this event will feature speakers who will dive into Nvidia’s over 30-year history to see how it became the AI giant it is today.

But what’s more exciting for everyone is that Huang is expected to unveil the Blackwell Ultra GPU, which has since been renamed the B300 series, that is expected to deliver more performance and have upgraded memory configurations. Huang said he will also show off next-generation Rubin AI GPUs and more at GTC.

The B300 series AI GPUs are expected to be available in the latter half of this year, while the next-generation Rubin is scheduled for 2026. Many people are anticipating the arrival of these more powerful chips, especially as tech giants and startups alike are battling for supremacy in the AI space.

Nvidia’s competitors, like AMD and Intel, also have their own AI GPU offerings. However, they are miniscule compared to Team Green, which currently owns around 92% of the entire data center GPU market. Its near-monopoly on AI GPUs, plus the hype around AI models, allowed it to become the most valuable company in the world practically overnight.

It has since dropped to third place after some market corrections, with the company losing more than half a trillion dollars in market cap after the release of DeepSeek AI. But as long as there’s demand for powerful AI GPUs, it’s unlikely that Nvidia will go away anytime soon.

It’s just a shame that many gaming enthusiasts, which was Nvidia’s primary market before AI exploded into the scene, feel that they’re being left behind by the company. While it’s understood that the company will prioritize its AI cash cow, the pricing and availability (or lack thereof) of its recently launched RTX 50-series GPUs has disappointed millions of its core fan base.

It's been a very busy year so far for GPUs, with Nvidia launching the RTX 5090, RTX 5080, RTX 5070 Ti, and RTX 5070 in the span of just two months. AMD also launched its RX 9070 XT and RX 9070, while Intel released the Arc B580 late last year and the Arc B570 in mid-January. The only problem? Outside of the Arc B570 (kind of but not really), every GPU launched so far has ended up being sold out or severely overpriced. But have no fear, because Nvidia claims it has shipped twice as many Blackwell GPUs as Ada during the first five weeks of each product series. Except that comparison is questionable, at best. 

The above chart looks pretty good, right? And then you go check the data and discover that the RTX 4090 launched on October 12, 2022, and was the only Ada GPU for the first five weeks — the RTX 4080 arrived on November 16, 2022, exactly five weeks and one day later. By comparison, the RTX 5090 and RTX 5080 both launched on January 30, 2025; the RTX 5070 Ti arrived on February 20; and the RTX 5070 just came out on March 5. So, in the first five weeks, Nvidia appears to be comparing the sole halo card from its Ada Lovelace and RTX 40-series GPUs to the first four Blackwell and RTX 50-series GPUs — or at least, that's how we read it. Maybe the launch supply of the 4080 was also factored in.

If we were to get a more direct comparison, we'd need to look at the first five weeks of the 4090 and 4080, plus the first two weeks of the 4070 Ti, plus the first day of the 4070. We think it's a safe bet that all those added together would easily eclipse the number of RTX 50-series GPUs shipped so far. Even at the most simplistic level, Blackwell had two GPUs (5090 and 5080) launch on the same day compared to one GPU for Ada (4090), so shipping twice as many would be the baseline.

This was a 'great' way to obfuscate the number of units shipped and claim to have shipped more inventory than in the past. It also completely neglects the fact that RTX 30-series GPUs were still relatively available right up to the launch of the 40-series, while the 40-series cards have been disappearing from shelves since last fall. We're told that more RTX 50-series GPUs are being produced, and Nvidia and its add-in board (AIB) partners are making them as fast as possible, but concrete numbers are not something anyone is willing to disclose.

However you want to slice it, Nvidia's latest GPUs are hard to come by. The current lowest prices online have just one RTX 5070 for $739 at Newegg, with third-party scalpers listing RTX 5070 cards at Amazon for $900 or more. RTX 5070 Ti starts at $1,149, the 5080 costs $1,609 or more, and the RTX 5090... you don't even want to know. (None are listed at PC Part Picker, but on eBay during the past 30 days the average sold 5090 at auction cost nearly $4,500, with 194 units sold.) AMD's RX 9070 series GPUs aren't doing much better, with an $853 RX 9070 on Amazon and a $939 RX 9070 XT also at Amazon. It could be a long wait for supply to catch up to demand, needless to say.

Besides making some misleading, at best, claims about Blackwell RTX availability, Nvidia also discussed the advances it's working with developers to enable DLSS 4 MFG and upscaling, Neural Shading, and ACE. RTX Remix officially left beta today as well, and there will be a public Half-Life 2 RTX demo available on March 18, offering vastly improved visuals compared to the original game that's now over 20 years old. [Ed: Where's my cane?]

You can see the rest of the announcements in the above slide deck. There's more marketing hype around the performance boost offered by DLSS 4 and Multi Frame Generation (MFG), which, as we discussed in our own in-depth testing, tends to be a highly inflated way of looking at performance. It's not that MFG is bad, per se, but even Nvidia's own numbers should cause some raised eyebrows. Like this performance result from Portal RTX:

Updates to the RTX Remix toolset combined with neural rendering features like the neural radiance cache deliver more than double the performance compared to the Remix beta. And then we look at the details.

Base RTX Remix beta performance was 125 FPS — that's with DLSS 3.5 and frame generation. Runtime optimizations and texture streaming account for a 22% increase, and there's another 18% improvement from the neural radiance cache. Together, those would result in performance of 175 FPS, an impressive 40% improvement. Then DLSS 4 MFG4X, on top of that, "increases" performance by 73%. But what it really does is drop the base non-framegen performance from ~88 FPS to ~76 FPS.

Either way, it's still running fast enough that the result should be very playable and look incredibly smooth, particularly if you have a 240 Hz 4K monitor. But that's also with an RTX 5090, which in our testing provides up to 60% higher performance than the RTX 5080 for demanding ray traced games, 75% higher performance than the RTX 5070 Ti, and 143% more performance than the RTX 5070.

By those metrics, 4K with performance upscaling and MFG4X on an RTX 5070 might only get around 125 FPS in Portal RTX on an RTX 5070, and it would feel more like 31 FPS in terms of input sampling and latency. That's still playable, but nowhere near what the MFG numbers might suggest in terms of user experience. 120 FPS via MFG isn't the same feel as a native 120 FPS, or even 120 FPS with regular framegen. And how will Half-Life 2 RTX run, given it's presumably an even more demanding game? We'll find out next week.

As we've noted in so many of our recent GPU reviews, the fundamental problem is supply and demand. The demand — and record $130 billion in revenue — for AI and data center GPUs and hardware dwarfs what Nvidia or any other company might make on consumer GPUs for gaming right now. Until that changes, we're not likely to see sufficient supply to meet demand for gaming GPUs, never mind finding GPUs available at their ostensible MSRPs.

One thing Nvidia didn't talk about yet is the widely rumored impending announcement of the RTX 5060 Ti and RTX 5060. Prices have started popping up online, and the full specs have been leaked multiple times. The TLDR: They're both 128-bit memory interfaces, and it looks like they'll launch with 8GB configurations, with an optional 16GB 5060 Ti as an upgraded solution. Prices and availability are still unknown factors.

Nvidia CEO Jensen Huang is well-known for giving his keynotes wearing a black leather motorcycle jacket. He hasn't addressed why he chose his (now iconic) black leather jacket specifically (considering other tech CEOs are known for hoodies and black turtlenecks, it's a pretty good choice), but he mentioned in an interview with HP last year that his wife and daughter are responsible for his current style. 

So we weren't terribly surprised to see Jensen in yet another black leather motorcycle jacket for the 2024 GTC keynote. But this time, it was a different leather jacket—still black but looking like it was made of lizard skin. Naturally, Tom's Hardware editors quickly went to the staffroom to discuss this fascinating disruption in Jensen's wardrobe. 

(Just kidding, it took me all of two seconds to find Jensen's jacket — I'm nothing if not a leather jacket connaisseuse.)

If you're curious about where the CEO of a multi-trillion dollar tech company shops, we're pretty sure he's wearing Tom Ford's Tejus lizard-embossed leather jacket from the Tom Ford SS2023 menswear collection, based on the collar, zippers, and cuffs (see detailed pictures below). It's not lizard or crocodile skin as some people might have suspected — most exotic skins are banned in California — but is, in fact, just embossed calf leather. Still, it doesn't come cheap: it retails for a cool $8,990 (or just over ten shares of Nvidia stock). 

But there's good news (sort of) for those looking to adopt the cool, casual look of Nvidia's CEO. You can pick up this exact Tom Ford leather jacket on sale for 40% off at Italian luxury retailer Luisa Via Roma. Of course, 40% off $8,990 is still... $5,394, or just over six shares of Nvidia stock.

While wearing this $9,000 Tom Ford jacket, Jensen announced the Blackwell B200 (the next-gen data center and AI GPU successor to the Hopper H100 and GH200 Grace Hopper superchip). Nvidia also announced that it has integrated generative AI into its cuLitho workflow, which TSMC and Synopsys are now employing to speed up computational lithography.

Nvidia currently sits atop the AI world, with data center GPUs that everybody wants. Its Hopper H100 and GH200 Grace Hopper superchip are in serious demand and power many of the most powerful supercomputers in the world. Well hang on to your seats: Nvidia just revealed the successor to Hopper. AT GTC 2024 today, CEO Jensen Huang dropped the Blackwell B200 bomb, the next-generation data center and AI GPU that will provide a massive generational leap in computational power.

The Blackwell architecture and B200 GPU take over from H100/H200. There will also be a Grace Blackwell GB200 superchip, which as you can guess by the name will keep the Grace CPU architecture but pair it with the updated Blackwell GPU. We anticipate Nvidia will eventually have consumer-class Blackwell GPUs as well, but those may not arrive until 2025 and will be quite different from the data center chips.

Nvidia Blackwell GPU

At a high level, the B200 GPU more than doubles the transistor count of the existing H100. There are some caveats that we’ll get to momentarily, but B200 packs 208 billion transistors (versus 80 billion on H100/H200). It also provides 20 petaflops of AI performance from a single GPU — a single H100 had a maximum 4 petaflops of AI compute. And last but not least, it will feature 192GB of HBM3e memory offering up 8 TB/s of bandwidth.

Now, let’s talk about some of the caveats. First and foremost, as the rumors have indicated, Blackwell B200 is not a single GPU in the traditional sense. Instead, it’s comprised of two tightly coupled die, though they do function as one unified CUDA GPU according to Nvidia. The two chips are linked via a 10 TB/s NV-HBI (Nvidia High Bandwidth Interface) connection to ensure they can properly function as a single fully coherent chip.

The reason for this dual-die configuration is simple: Blackwell B200 will use TSMC’s 4NP process node, a refined version of the 4N process used by the existing Hopper H100 and Ada Lovelace architecture GPUs. We don’t have a ton of details on TSMC 4NP, but it likely doesn’t offer a major improvement in feature density, which means if you want a more powerful chip, you need a way to go bigger. That’s difficult as H100 was basically already a full reticle size chip — it has a die size of 814 mm2, where the theoretical maximum is 858 mm2.

B200 will use two full reticle size chips, though Nvidia hasn’t provided an exact die size yet. Each die has four HMB3e stacks of 24GB each, with 1 TB/s of bandwidth each on a 1024-bit interface. Note that H100 had six HBM3 stacks of 16GB each (initially — H200 bumped this to six by 24GB), which means a decent chunk of the H100 die was dedicated to the six memory controllers. By dropping to four HBM interfaces per chip and linking two chips together, Nvidia can dedicate proportionately less die area to the memory interfaces.

The second caveat we need to discuss is with the maximum theoretical compute of 20 petaflops. Blackwell B200 gets to that figure via a new FP4 number format, with twice the throughput as Hopper H100’s FP8 format. So, if we were comparing apples to apples and sticking with FP8, B200 ‘only’ offers 2.5X more theoretical FP8 compute than H100 (with sparsity), and a big part of that comes from having two chips.

That’s an interesting point that again goes back to the lack of massive improvements in density from the 4NP process node. B200 ends up with theoretically 1.25X more compute per chip with most number formats that are supported by both H100 and B200. Removing two of the HBM3 interfaces and making a slightly larger chip might mean the compute density isn’t even significantly higher at the chip level — though of course the NV-HBI interface between the two chips also takes up some die area.

Nvidia provided the raw compute of other number formats with B200 as well, and the usual scaling factors apply. So the FP8 throughput is half the FP4 throughput at 10 petaflops, FP16/BF16 throughput is half again the FP8 figure at 5 petaflops, and TF32 support is half the FP16 rate at 2.5 petaflops — all of those with sparsity, so half those rates for dense operations. Again, that's 2.5X a single H100 in all cases.

What about FP64 throughput? H100 was rated at 60 teraflops of dense FP64 compute per GPU. If B200 had similar scaling to the other formats, each dual-die GPU would have 150 teraflops. However, it looks like Nvidia is stepping back FP64 performance a bit, with 45 teraflops of FP64 per GPU. But that also requires some clarification, as one of the key building blocks will be the GB200 superchip. That has two B200 GPUs and can do 90 teraflops of dense FP64, and other factors are at play that could improve the raw throughput on classical simulation compared to H100.

As far as utilizing FP4, Nvidia has a new second generation Transformer Engine that will help to automatically convert models to the appropriate format to reach maximum performance. Besides FP4 support, Blackwell will also support a new FP6 format, an in-between solution for situations where FP4 lacks the necessary precision but FP8 isn't needed either. Whatever the resulting precision, Nvidia classifies such use cases as "Mixture of Experts" (MoE) models.

We also need to clarify some things here, as there are multiple different variants of Blackwell available. Initially, Nvidia is providing specs in terms of full server nodes, and there are three main options. We've also broken out the two "single" GPUs based off the HGX configurations.

The largest and fastest solution will be a GB200 superchip, which we'll discuss more below, but as noted it has two B200 GPUs. The full superchip has a configurable TDP up to 2700W. That's for two GPUs (four GPU dies), plus a single Grace CPU. The numbers we just provided above — up to 20 petaflops of FP4 for a single B200 — are from half of a GB200 superchip. The configurable TDP for a single B200 GPU in the superchip goes up to 1200W peak, or 2400W for the two GPUs with 300W for the Grace CPU.

The next Blackwell option is the HGX B200, which is based on using eight B200 GPUs with an x86 CPU (probably two CPUs) in a single server node. These are configured with 1000W per B200 GPU, and the GPUs offer up to 18 petaflops of FP4 throughput — so on paper that's 10% slower than the GPUs in the GB200.

Finally, there will also be an HGX B100. It's the same basic idea as the HGX B200, with an x86 CPU and eight B100 GPUs, except it's designed to be drop-in compatible with existing HGX H100 infrastructure and allows for the most rapid deployment of Blackwell GPUs. As such, the TDP per GPU is limited to 700W, the same as the H100, and throughput drops to 14 petaflops of FP4 per GPU. There are likely other differences in the hardware that account for the B200 vs. B100 naming, besides the difference in TDP.

It's important to note that in all three of these servers, the HBM3e appears to be the same 8 TB/s of bandwidth per GPU. We would assume potential harvested dies for the lower tier parts, meaning fewer GPU cores and perhaps lower clocks, along with the difference in TDP. However, Nvidia has not revealed any details on how many CUDA cores or Streaming Multiprocessors will be available in any of the Blackwell GPUs yet.

Nvidia NVLink 7.2T

It’s not just about raw compute and memory bandwidth. One of the big limiting factors in AI and HPC workloads is the multi-node interconnect bandwidth for communication between different nodes. As the number of GPUs scales up, communication becomes a serious bottleneck and can account for up to 60% of the resources and time utilized. With B200, Nvidia is introducing its fifth generation NVLink and NVLink Switch 7.2T.

The new NVSwitch chip has 1.8 TB/s of all-to-all bidirectional bandwidth, with support for a 576 GPU NVLink domain. It’s a 50 billion transistor chip manufactured on the same TSMC 4NP node. That's relatively close to the size of Hopper H100 and shows how important the interconnect has become. The chip also supports 3.6 teraflops of Sharp v4 in-network compute on chip, which can help with the efficient processing of larger models — all that processing power can go toward intelligent load balancing of workloads.

The previous generation supported up to 100 GB/s of HDR InfiniBand bandwidth, so this is a huge jump in bandwidth. The new NVSwitch offers an 18X speedup compared to the H100 multi-node interconnect. This should enable significantly improved scaling for larger trillion parameter model AI networks.

Related to this, each Blackwell GPU comes equipped with 18 fifth generation NVLink connections. That's eighteen times as many links as H100. Each link offers 50 GB/s of bidirectional bandwidth, or 100 GB/s per link, which will help tremendously when scaling to larger models. In a sense, it allows larger groups of GPU nodes to function on some levels as though they're just a single massive GPU.

Nvidia B200 NVL72

Take the above and put them together and you get Nvidia’s new GB200 NVL72 systems. These are basically a full rack solution, with 18 1U servers that each have two GB200 superchips. There are some differences compared to the prior generation here, however, in terms of what constitutes a GB200 superchip. There are two B200 GPUs paired with a single Grace CPU, whereas GH100 used a smaller solution that put a single Grace CPU alongside a single H100 GPU.

Each compute node in the GB200 NVL72 has two GB200 superchips, so a single compute tray has two Grace CPUs and four B200 GPUs, with 80 petaflops of FP4 AI inference and 40 petaflops of FP8 AI training performance. These are liquid-cooled 1U servers, and they take up a large portion of the typical 42 units of space offered in a rack.

Alongside the GB200 superchip compute trays, the GB200 NVL72 will also feature NVLink switch trays. These are also 1U liquid-cooled trays, with two NVLink switches per tray, and nine of these trays per rack. Each tray offers 14.4 TB/s of total bandwidth, plus the aforementioned Sharp v4 compute.

Altogether, the GB200 NVL72 has 36 Grace CPUs and 72 Blackwell GPUs, with 720 petaflops of FP8 and 1,440 petaflops of FP4 compute. There’s 130 TB/s of multi-node bandwidth, and Nvidia says the NVL72 can handle up to 27 trillion parameter models for AI LLMs. The remaining rack units are for networking and other data center elements.

Nvidia B200 SuperPOD

Wrapping things up, we have the new SuperPODs with GB200 systems. We noted earlier that the latest NVLink chips support up to a 576 GPU domain. That’s important, because the new DGX SuperPOD scales to precisely that number of GB200 Blackwell GPUs. Each SuperPOD can house up to eight GB200 NVL72 systems, which works out to 288 Grace CPUs and 576 B200 GPUs.

The full SuperPOD is quite the AI supercomputer in itself, with 240TB of fast memory and 11.5 exaflops of FP4 compute — or if you prefer, 5.75 exaflops of FP8 or 2.88 exaflops of FP16. Installations can scale to many SuperPODs, with potentially tens of thousands of Blackwell GPUs and Grace CPUs.

While nothing was said, we're guessing Nvidia is already starting or will soon begin installing GB200 SuperPODs in either a new supercomputer, or perhaps as an expansion of its existing Eos supercomputer. Nvidia did provide an example installation with a hypothetical 56 SuperPODs and over 32,000 total B200 GPUs. Should that become a reality, it would be an AI supercomputer with 645 exaflops of FP4 compute, 13PB of HBM3e memory, , 58 PB/s of aggregate NVLink bandwidth, and 16.4 petaflops of in-network compute.

The SuperPODs are intended to scale up to trillion parameter AI datasets, and Nvidia says compared to H100 solutions, each SuperPOD offers a 4X increase in training performance, and up to a 30X increase in inference speeds. It also claims up to a 25X improvement in energy efficiency compared to the previous H100 based solutions, though the comparison is clearly not something that will apply universally. In this case, it's using the same number of GPUs, running a "massive model" and using the new FP4 number format.

Nvidia will also offer DGX B200 systems, which will presumably use Xeon or EPYC processors instead of Grace. These systems are for workloads that specifically want x86 support. Nvidia says DGX B200 can deliver up to a 3X increase in training speed, 15X for inference, and 12X energy savings.

As with the previous A100 and H100 SuperPODs, these are designed to offer a quick scale-up solution for data centers and cloud service providers. Nvidia is working with Amazon Web Services, Google Cloud, and Oracle Cloud to offer GB200 NVL72 solutions, and says that AWS will have Project Ceiba that will have over 20,000 B200 GPUs, 4PB of HBM3e memory, and over 400 exaflops of AI compute in the coming months.

The Blackwell Tour de Force

Nvidia is throwing down the gauntlet again with Blackwell and its related technologies. The company was already at the top of the AI heap, and it knows where the biggest bottlenecks lie and how to address them. From the core GPU to the interlinks to the node-to-node communications, the Blackwell ecosystem looks to shore up any potential shortcomings of the previous solutions.

The previous Hopper H100 and Ampere A100 solutions have proven incredibly prescient and successful for Nvidia. Whoever is looking in a crystal ball trying to predict where the industry is heading next nailed it with these AI solutions. CEO Jensen recently quipped that Nvidia's competitors couldn't give their AI solutions away — shots fired back at those claiming Nvidia's dominance was "pure luck", no doubt. Whatever the cause, the result is that Nvidia's latest earnings show an obscene 126% year-over-year increase, with over a 600% improvement for the latest quarter compared to one year ago in the data center division.

It's a safe bet that things aren't going to slow down any time soon with Blackwell. Nvidia has more than doubled down on the GPU size, with dual chips and major overhauls to the underlying hardware. The Grace Blackwell GB200 superchip also represents another doubling down, with two full B200 GPUs paired to a single Grace CPU for the "superchip" module. Blackwell is also designed to scale to much larger installations than Hopper, enabling ever larger AI models.

How much will Blackwell solutions cost compared to Hopper? Nvidia didn't say, but with H100 GPUs generally going for around $40,000 each, and given everything that's involved with Blackwell, $100,000 per GPU wouldn't be surprising.

The competition isn't standing still, obviously, and just about every major tech company is talking about AI and deep learning and how they're going to be at the forefront of the AI revolution. But talk is cheap, and Nvidia is already at the head of the pack. It invested big into AI starting about a decade back and is now reaping the fruits of those investments, and at least for the next year or two, Blackwell looks like it will power the most advanced AI installations.

Blackwell B200 hardware should begin full production and shipping later in 2024. Nvidia hasn't committed to an exact timeframe yet, but additional details will be revealed in the coming months.

Nvidia announced here at GTC 2024 that TSMC and Synopsys have now employed its cuLitho software in production to speed up computational lithography, a key workload that helps chipmakers sidestep limitations as they move to 2nm and smaller transistors produced with the latest cutting-edge chipmaking tools, like High-NA EUV. The computational horsepower required to produce today's chips is increasing with each new node, and Nvidia touted an example of a cuLitho-powered system with 350 H100 GPUs delivering a 60X performance speedup to a workload that typically requires 40,000 CPU systems crunching away for up to 30 million or more hours of compute time.

Nvidia announced cuLitho last year, but the company has also now integrated generative AI into the workflow, thus providing an additional 2X speedup over the already impressive gains. Overall, Nvidia claims cuLitho drastically reduces the time required for heavy computational lithography workloads of all ilks, and with Synopsys integrating the tech into its software tools, it's likely to permeate to other chipmakers, too.

Printing nanometer-scale features on a chip requires a chunk of transparent quartz called a photomask. The quartz has an imprinted pattern of a chip design and works much like a stencil. By shining ultraviolet light through the mask, called an exposure, the chip design can be etched onto the wafer, thus creating the billions of 3D transistors and wire structures that comprise a modern chip.

Early chipmaking tools employed a single photomask to print an entire wafer, but new chips require such high resolution that a photomask is used with a reticle to print each die on the wafer individually. Each chip design requires multiple exposures to build up the chip's design in layers, and the number of photomasks used during the chipmaking process varies based on the chip; it can even exceed 100 masks. However, new problems have cropped up as the tool's print features finer than the wavelength of the ultraviolet light used for exposures. 

The continued shrinkage of the features has led to issues with diffraction, which essentially 'blurs' the design being printed onto the silicon. These issues with optical imperfections occur due to a number of factors, like mirror curvature, chemical properties, and positioning offsets, among others, which require mitigations to ensure the design is printed without defects. 

Resolution Enhancement Technologies (RET) techniques paired with computational lithography counteract the clarity issues by conducting complex mathematical operations that optimize the mask layout, bending the light in such a way that chipmakers can achieve higher resolutions than before. However, this task is becoming increasingly compute-intensive as features shrink even further and billions more transistors are added to each design, creating an escalating computational workload that grows with each new generation of chips.

The key to addressing the issue lies in creating ever-more sophisticated masks, but they’re incredibly complex - for instance, Intel says each of its masks holds the equivalent of an astounding five petabytes of data, or ten times as much data as an IMAX movie. High-NA EUV and new techniques, like Inverse Lithography Technology (ILT), which employs curvilinear masks, are expected to increase the amount of data processing for masks by 10X in the coming years.

The advent of multi-beam writers, a new class of mask creation tool, allows finer control of the mask-making process and enables much more complex designs, like those found in curvilinear masks. However, this requires much more intense computation. Nvidia's cuLitho is designed to shift the computational lithography workload to GPUs and, through the company's software libraries, reduce the amount of time required to complete any given workload. 

The cuLitho library can be integrated into computational lithography software that designs masks using ILT (curvilinear shapes), Optical Proximity Correction (OCP, which uses 'Manhattan' shapes), and Source Mask Optimization (SMO). 

Now that cuLitho has employed generative AI and has been moved to production, Nvidia has shared the results of its tests, with a Manhattan workload experiencing a 58X improvement, a curvilinear mask design receiving a 45X speed up, and an Nvopc workload getting a 40X boost. 

TSMC is now employing cuLitho in its mask-making operations, and the great effect; “Our work with NVIDIA to integrate GPU-accelerated computing in the TSMC workflow has resulted in great leaps in performance, dramatic throughput improvement, shortened cycle time and reduced power requirements,” said Dr. C.C. Wei, CEO of TSMC. “We are moving NVIDIA cuLitho into production at TSMC, leveraging this computational lithography technology to drive a critical component of semiconductor scaling."

“Synopsys has a proud history of empowering engineering teams to solve previously unsolvable challenges, and now we’re taking that to the next level by harnessing the power of AI and accelerated computing,” said Sassine Ghazi, president and CEO of Synopsys.

Synopsys and TSMC are the first to employ cuLitho, but other EDA and chipmaking companies can also employ the software in their mask-making operations, thus improving the amount of time required to fabricate new masks while saving power and reducing cost. 

Today's the day. Nvidia CEO Jensen Huang takes the keynote stage at the San Jose Convention Center at 4 pm ET / 1 pm PT to kick off the company's 2024 GTC conference. Huang is widely expected to reveal a next-generation AI GPU, codenamed B100 while talking and demonstrating about the latest developments in artificial intelligence. 

We'll be publishing articles about the most important news from the keynote, but you can watch it live on the YouTube stream below.

So what can you expect from Huang's keynote address? It's almost certain he'll show demos of Nvidia technology powering various AI workloads. A trailer for the keynote shows demos of a text-to-image generator, a 2D floorplan being transformed into a 3D world and someone using Blender to generate a complex 3D image of a space ship. 

"The purpose of GTC is to inspire the world on the art of the possible and accelerated computing," Huang says in the trailer.

However, the real star of the show will be the hardware that Huang shows off. The rumored B100 is said to use the company's upcoming Blackwell architecture. Considering that Nvidia unveiled its A100 and H100 AI GPUs at the 2020 and 2022 GTC keynotes, a new model fits right into the timeline.

The B100 is rumored to use a multi-chiplet design with faster memory than the H100 and H200 and the need to consume more than 1,000 watts of power. While the B100 and GPUs like it are made for the datacenter (or perhaps AI workstations), the Blackwell architecture behind it will likely power the next generation of consumer graphics cards whenever the RTX 50-series launches.

Nvidia's annual GPU Technology Conference (GTC) kicks off today at 8:30 a.m. PT. Due to the Covid-19 restrictions, the chipmaker will be holding the event online with over 1,500 sessions, covering a broad spectrum of topics.

It wouldn't be a GTC without a keynote from Jensen Huang, which the CEO will deliver from his kitchen again. Don't forget that Nvidia is still hosting its GTC 2021 treasure hunt, where the ultimate spoil is the $1,499 GeForce RTX 3090. The graphics card shortage isn't letting up anytime soon so this could be a good opportunity to get your hands on Nvidia's flagship Ampere graphics card for free.

GTC doesn't focus on gaming, rather more complex subjects, such as AI, deep learning, quantum computing, or telecommunications - just to mention a few. So we don't expect Nvidia to launch any new GeForce gaming graphics cards to shake up the best graphics cards on the market. However, we might witness a few Quadro or Tesla announcements.

GTC 2021 runs from April 12 to April 16. Registration is free, and you'll get access to all the tech sessions, panels and demos. However, if you're interested in a particular DLI training workshop, it's priced at $249 each.

Stealing a page out of Intel's playbook, Nvidia is holding a treasure hunt leading up to GTC (Graphics Technology Conference) 2021. To give the public an extra bit of motivation to participate, the chipmaker is offering up a ton of prizes, including the elusive GeForce RTX 3090 (Ampere) graphics card.

Earlier today, Nvidia released a short video to promote GTC 2021, which starts on April 12, 8:30 a.m. PT. Since we're still in the middle of the pandemic, GTC 2021 will be an online affair with Nvidia CEO Jensen Huang scheduled to deliver his keynote from his legendary kitchen. 

However, Nvidia sneakily left a small Easter egg in the 30-second video. The video ends with a curious golden neuron and corresponding blinking bulbs. It would appear that a hidden message was encoded in Morse code and deciphers to "hidden treasure." To make a long story short, the first treasure map leads to a secret landing page where Nvidia explains the dynamics of the scavenger hunt and encourages users to keep uncovering the other hidden treasures.

Apparently, there are other Easter eggs that are waiting to be discovered. However, Nvidia didn't specify if the remaining clues are inside the same video or in subsequent videos. 

A couple of hours ago, Nvidia posted another short video on one of its Twitter accounts so that might be a good place to start looking for the next clue. Like Effie Trinket said in The Hunger Games movie, "May the odds be ever in your favor."

Next week Nvidia will kick off its annual GTC conference, a virtual-only event for the second time. GTC will traditionally start with a keynote by Jensen Huang, chief executive of Nvidia, delivered from his kitchen. The main intrigue is: what will he talk about? Last year he announced the Ampere architecture in general and the A100 compute GPU in particular.

Just like Nvidia is no longer a graphics-only company, GTC is no longer a GPU technology conference. In recent years, it covered many theoretical and practical aspects of artificial intelligence, deep learning, high-performance computing, healthcare, autonomous vehicles, robots, and many others. That said, it isn't surprising that the core topic of this year's GTC will be accelerated computing. But from what angle?

Apparently, Jensen Huang intends to reveal the company's vision for the future of computing 'from silicon to software to services.' Computing is pervasive these days; it spans from client devices to the edge and from the data center to the cloud, so expect him to talk about many things (and perhaps even products) in his address. One of the highlights that Nvidia's CEO is set to discuss will be its vision for manufacturing and factories of the future.  

Nvidia CEO Jensen Huang’s GTC keynote is scheduled for Monday, April 12, starting at 8:30 a.m. PT. The conference will feature over 1,500 sessions covering various technological innovations.

As COVID-19, the disease caused by the novel Coronavirus, spreads internationally, it has caused tech companies and event organizers to reconsider whether it’s safe to hold large conferences and tradeshows.

The Center for Disease Control (CDC) recommends that you avoid being close to people who are sick, wash your hands frequently, stay home when you are ill and disinfect surfaces you touch. However, when you put a lot of people in the same place, transmission can happen.

Much of the world still hasn’t seen cases or outbreaks, but some conferences have already been canceled out of an abundance of caution. Mobile World Congress in Barcelona was canceled after a number of vendors, including Ericsson, ZTE, LG, MediaTek, Facebook, Nvidia and more either pulled out of the show, scaled back operations or chose not to send employees. Facebook has also canceled its F8 developer conference.

Now others are deciding whether or not to hold their events. Companies like Sony, Microsoft, Epic and Unity have pulled out of the Game Developers Conference (GDC) in San Francisco, but that show is still scheduled to go on from March 16 through March 20.

Here’s a list of upcoming tech events and what we know about them.

Canceled

• Mobile World Congress in Barcelona, Spain (February 24-27)
• SXSW in Austin, Texas (March 13 - March 22)
  Officials in Austin, Texas declared a disaster in the city and issued an order to cancel SXSW.
• Facebook F8 in San Jose, California (May 5-6)
  
• Google I/O in San Jose, California (May 12-14)
  Google’s developer conference is not occurring in the Shoreline Amphitheater. "Over the coming weeks, we will explore other ways to evolve Google I/O to best connect with and continue to build our developer community. We’ll continue to update the Google I/O website," Google told news outlets. Ultimately, Google decided to nix the whole thing.
• E3 in Los Angeles, California (June 9-11)
  E3 2020 has been canceled. In a statement, the Entertainment Software Association wrote that "[a]fter careful consultation with our member companies regarding the health and safety of everyone in our industry – our fans, our employees, our exhibitors and our longtime E3 partners – we have made the difficult decision to cancel E3 2020, scheduled for June 9-11 in Los Angeles."

Postponed

• Game Developers Conference (GDC) in San Francisco, California (Postponed) Originally scheduled to run from March 16 to 20, GDC has been delayed until "later in the summer." New dates in August have been announced form August 4-6.
• Computex in Taipei, Taiwan (Postponed)
  The biggest tech show in Asia has been pushed back to September 28-30 from its original dates in June. The show's organizer, Taitra, wrote that the delay is for "health and safety of exhibitors and visitors, the effectiveness of the exhibition, and maintaining the COMPUTEX brand image."
  

Moved to Online Only

• Microsoft MVP Global Summit  (March 16-19)
• Adobe Summit (March 29 - April 20)
• Nvidia GPU Technology Conference (GTC)  (March 22-26)
  Nvidia has moved GTC to be an online-only event because of "growing concern over the coronavirus." CEO Jensen Huang will give a keynote over livestream. Registrants will receive a full refund.
• Google Cloud Next (April 6-8)
• Microsoft Build (May 19-21)
  Microsoft will host its developer event online, instead of in Seattle. "The safety of our community is a top priority. In light of the health safety recommendations for Washington State, we will deliver our annual Microsoft Build event for developers as a digital event, in lieu of an in-person event," Microsoft told news outlets. "We look forward to bringing together our ecosystem of developers in this new virtual format to learn, connect and code together. Stay tuned for more details to come."
• Apple Worldwide Developers Conference (WWDC) (June 22)
  Apple's WWDC website says that this year's event will be "a completely new online experience" with keynotes and presentations.
• Gamescom  (August 25-29)
  The gaming show originally meant to be in Cologne, Germany will go digital-only.

In Person

• IFA (September 3-5)
  IFA has announced a shorter, three day show that won't be open to the public. The invite-only show will be comprised of four smaller events, each limited to 1,000 people per day.

Where can I learn more about the coronavirus?

Our friends at LiveScience are constantly updating with the latest news and updates on the coronavirus.

Additionally, the World Health Organization and Centers for Disease Control have information and resources about COVID-19. 

The Nvidia A100 GPU based on the Ampere architecture has arrived, and Nvidia's CEO Jensen Huang talks about the technology, applications, and other advancements in his eight part digital keynote. The A100 is the highlight of the keynote, but Nvidia has its fingers in a lot of other pies. Here are the nine (one was missing earlier) different parts with a short summary of each:

Kicking things off, we have Jensen in the kitchen cooking up some server hardware. This one is pretty light on details, just getting things started for what would have been a 90 minute live keynote in the past. There's a new "I am AI" video included as well, showing the possibilities of machine learning.

While this talks tangentially about RTX and ray tracing, the main point of this video is to discuss the Tensor cores and DLSS, Deep Learning Super Sampling. It's still not clear if A100 includes RT cores or not, but DLSS has been enhanced since the initial release to create a high performance and high quality real time upscaling and anti-aliasing solution. Besides showing off what DLSS 2.0 can do, Jensen also introduces the Nvidia Omniverse, a cloud-based system for software development and collaboration. Also shown is Marbles RTX, basically a modern take on Marble Madness, now enhanced with ray tracing effects.

Did you know Nvidia recently finalized its Mellanox acquisition? As a provider of high performance networking interlinks between data center systems, it's an important addition to Nvidia's portfolio. Also, Nvidia's GPUs will now accelerate Apache Spark 3.0, which could be a huge benefit to many data processing workflows.

There's a lot of content and information out there, more than any of us could ever hope to grok. Recommender systems are a way to sift through all that data via AI, pulling out the golden nuggets that are most interesting. Nvidia's recommender solution is called Merlin.

There's no Iron Man here, but Jarvis shows up to power conversational AI in the form of a floating water droplet. Looks like Nvidia wants to compete with Siri and Hey Google, with more natural language constructs. Also, watch a voice-to-face animated gray face lip syncing some Nvidia rap.

You're probably here to learn more about Ampere and the A100, and this is where the real meat of the keynote lies. Not surprisingly, this video is also twice as long as the other segments. Jensen digs into some of the details of the A100, comparing performance to the previous generation V100 data center processor. Depending on the workload, the A100 is anywhere from 2.5X to 20X faster than the V100. Also, it's 54 billion transistors and 826mm square, the largest GPU ever created.

Link eight of them together via 600 GBps NVSwitch links and each DGX A100 system can function as an even larger GPU, sort of. Jensen says DGX A100 systems can replace potentially hundreds of older data center servers: "The more you buy, the more you save." Only $199,000 each. I'll take two, please!

The A100 is also going into other devices, like the EGX A100 converged accelerator that can be used for edge computing and inferencing. EGX A100 also powers the next iteration of the Isaac robotics platform, providing a massive boost in performance.

Last but not least, autonomous cars are still a major target for many companies. Nvidia is working with many of them, and Orin is basically the next iteration of Nvidia's Drive platform. It can be used for a range of autonomous vehicles, from ADAS to autopilots and even fully autonomous solutions.

And that's a wrap. This concluding video just recaps everything that Jensen discussed in the other videos. There's also a behind the scenes segment on the "I am AI" video from the introduction.

On May 14 at 6 a.m. PT, Nvidia's CEO Jensen Huang will host the GTC 2020 keynote on YouTube. Now although the announcement of this keynote doesn't specifically mention Ampere, it would be a major surprise if we didn't hear about the next-generation graphics architecture. 

Ampere is set to succeed Turing and power the RTX 3000-series graphics cards. Not a lot of details are available at this time, with Nvidia proving quite good at keeping the details under wraps, but that doesn't stop us from being excited. The biggest thing we're looking forward to is the transition to 7nm, when Nvidia will finally transition away from 12nm and catch up with AMD. Supposedly, Ampere will deliver 50% faster performance.

Although an Ampere announcement isn't totally guaranteed, Nvidia did say we should "Get amped for latest platform breakthroughs in AI, deep learning, autonomous vehicles, robotics, and professional graphics" — a not so subtle hint of Ampere if ever we saw one.

The GTC keynote was originally scheduled for March 23, but due to the COVID-19 outbreak, it ended up canceled. This happened after promises of hosting the keynote online instead of at the conference, but in the end, Nvidia decided to postpone all GTC news altogether, to the dismay of its fans.

To view the GTC 2020 keynote, go to Nvidia's YouTube page on May 14 at 6 a.m. PT.

If you've been anxious to learn all about what Nvidia has in store for us at its GPU Technology Conference (GTC), you'll have to be a little more patient. Due to the increasing severity of the Coronavirus outbreak, Nvidia has decided to postpone sharing its GTC news, which we expected to include information pertaining to the upcoming Ampere GPU architecture.

"This is a time to focus on our family, our friends, our community. Our employees are working from home. Many hourly workers will not need to work but they’ll all be fully paid." wrote Jensen Huang, Nvidia's CEO on the blog post. 

Previously, Nvidia had reassured us that its annual GPU Technology Conference would go on despite lots of other shows getting canceled, but later it turned out that it would be an online-only event after all. Following that, Nvidia decided to cancel the streamed keynote too, in favor of news releases on the 24th of March. Now, we won't be getting those either.

The tech talks and presentations from researchers and developers will go on as streamed content, but the news that Nvidia was planning on sharing as announcements will have to wait. We expected this news to include information about the upcoming Ampere GPU architecture, and perhaps even a little information about the RTX 3000-series GPUs. 

For now, Nvidia has not shared a new date when the GTC news will be shared.

Following the cancellation of Nvidia's physical GPU Technology Conference (GTC)in favor of an online-only event, we have been awaiting a new date and time at which Nvidia will broadcast its GTC keynote. It turns out that Nvidia has decided against streaming the keynote and will be sharing the news announcements in text instead. 

In its announcement, Nvidia said that "in light of the spread of the coronavirus, it is deferring plans to deliver a webcast keynote" as part of its digital version of GTC.

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"The company believes that continuing public health uncertainties would challenge its ability to produce and deliver a digital keynote." Nvidia stated. 

Immediately following the news announcements, Nvidia will hold an investor call at 8 am Pacific Time. The call will be open to the public for listening.

Nvidia hasn't revealed what it plans on announcing, but we expect Nvidia's next-generation GPU architecture, Ampere, to make its debut, likely with the announcement of (some of) the RTX 3000-series graphics cards but without the full technical specifications.

GTC is usually held in San Jose, California and is Nvidia's annual developer's conference where industry specialists, engineers and scientists gather to learn about the developments in GPUs, artificial intelligence, deep learning and more. However, this year the in-person show that was set to take place from March 22 through 26 was canceled due to the coronavirus outbreak.

Over the last few months, many events around the world have been canceled due to the coronavirus outbreak; however, Nvidia is adamant that its GPU Technology Conference (GTC) will go on.

The company stated in an interview with  that "GTC is definitely on, it told CRN. "With the coronavirus, there were some concerns about other events around the world. It's one of our most important events, and we plan to host it, and we believe it will be just as important, if not bigger than the ones we've had one the past."

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GTC is Nvidia's annual conference in San Jose, California, where it showcases developments in GPU technology, unveiling new technologies in both hardware and software. Many of Nvidia's partners also show up as exhibitors to showcase their advancements in research and development, as the show is primarily aimed at a scientific community that uses GPUs for research. 

Nvidia published a page detailing  the precautions it would be taking at the show in consideration of COVID-19: 

• The use of electrostatic sprayers to disinfect high-traffic areas daily.
• Frequent disinfection of all common touch areas, including door handles, knobs, and push bars of all meeting rooms, halls, and access points as well as stair railings, escalators, lecterns, microphones, light switches, trash receptacles, elevator buttons, water stations, and bathroom areas.
• The number of hand sanitizer stations will be significantly increased throughout the convention center.
• Plus other incremental cleanliness steps, including daily employee pre-shift safety meetings.

Additionally, Nvidia also recommended measures for attendees to take to ensure hygiene. It said  will be recording all sessions, so that attendees who get ill can watch them remotely.

Given that it's time for Nvidia to unveil its new GPU architecture, we're expecting CEO Jensen Huang to unveil the Ampere GPU architecture during  his keynote on March 23. 

However, there's still reason to be skeptical. Mobile World Congress' (MWC's) organizers were also insistent that the show would go on right up until 12 days before its scheduled start. 

When high bandwidth memory (HBM) launched in 2015, there were high hopes for it, but it was still too immature to compete with the GDDR5 memory popular with graphics cards at the time. This changed quickly with the arrival of HBM2. Now, five years after the introduction of HBM's first generation, Samsung is the first to announce mass production of third-generation HBM2E memory. Flashbolt, which Samsung first revealed at Nvidia's GTC event in March, will see mass production in the first half of 2020. 

By stacking DRAM dies, HBM in general allows for the realization of a much wider memory bandwidth (as seen by the Flashbolt's 1,024-bit bus). As a result, a tiny package can achieve a very high bandwidth. This is useful for integrating onto the GPU chips themselves, saving valuable space on a graphics card's printed circuit board.

Since originally announcing Flashbolt in March, Samsung hasn't changed any of its specifications, which include eight 16 gigabit (Gb) dies stacked on top of one another to create a 16GB memory stack. 

At 3,200 MHz, Flashbolt offers a memory transfer speed of 410 GBps with its 1,024-bit memory interface. Nevertheless, Samsung has tested the memory to run at up to 4,200 MHz, which brings the bandwidth all the way up to a massive 538 GBps, telling us that HBM2E might have some great overclocking potential. 

In comparison, the previous-generation HBM2 memory 'Aquabolt' from Samsung offered a total capacity of 8GB, ran at 2,400 MHz and had a maximum bandwidth of 307.2 GBps per stack.

The DRAM used is built on 10nm lithography, and the package uses 40,000 Through-Silicon Via's (TSV). Each of the eight 16Gb dies has 5,600 microbumps.

“With the introduction of the highest performing DRAM available today, we are taking a critical step to enhance our role as the leading innovator in the fast-growing premium memory market,” said Cheol Choi, EVP of Memory Sales & Marketing at Samsung, said in a statement accompanying today's announcement. “Samsung will continue to deliver on its commitment to bring truly differentiated solutions as we reinforce our edge in the global memory marketplace.”

HBM2E memory isn't immediately aimed at consumer products, but it's possible it could end up in a handful of consumer-facing offerings, just like how the AMD Radeon VII (16GB) came with two HBM2 stacks. The primary target of HBM2E, however, is high-performance computing (HPC) and supercomputers. 

Given the timing of this release, it wouldn't come as a surprise to see Nvidia's next-generation HPC Tesla GPUs pack Flashbolt memory. We already know that Indiana University postponed GPU installation in its supercomputer to wait for the 70-75% performance increase from the successor to Volta-based Tesla V100 GPUs. This successor, likely called the Tesla A100, will be based on the Ampere architecture, which Nvidia could announce at its GTC keynote on March 23.  

Samsung will continue to offer Aquabolt while Flashbolt awaits mass production.