TSMC and Elon Musk's Terafab semiconductor production initiative are discussing a potential collaboration under which TSMC would build and operate a facility that will exclusively serve Elon Musk's Tesla, SpaceX, and xAI companies, according to Tim Culpan’s Culpium newsletter on Friday. Elon Musk confirmed the discussions early on Saturday, but did not elaborate.

"Just discussions, but something may come of it," Musk wrote in an X post, while TSMC has so far remained tight-lipped.

Under the arrangement Culpan considers most probable, TSMC would own and operate the new semiconductor production facility, while SpaceX/Terafab could invest in the venture, commit to buying a guaranteed volume of chips, or combine both approaches. However, the exact ownership structure remains under discussion. Another option would put SpaceX in control of the venture with the majority ownership; TSMC would invest less, but would still provide 'operational expertise' and process technologies. Perhaps, an interesting background detail from Culpium is that TSMC's rumored intentions to build a fab complex in Texas are tied to the foundry's effort to support Terafab.

The proposed 'Plan A' arrangement could resemble TSMC's JASM and ESMC joint ventures in Japan and Germany, where local partners provide capital and demand while TSMC contributes process technology and operates the fabs. The proposed 'Plan B' structure — under which SpaceX will hold the majority ownership of Terafab while TSMC would operate the facility and bring its own process technology — would be completely new for the world's No.1 contract chipmaker, though.

The development certainly raises questions about Intel's role in Terafab. For now, Intel is to supply its 1.4nm-class 14A process technology to Terafab, which would produce chips for Elon Musk's SpaceX, Tesla, and xAI. If TSMC becomes involved, then Intel's 14A could drop out of the game because TSMC will bring its own node.

Since nothing is official at this point, both 'Plan A' and 'Plan B' should be considered as speculations rather than the two options currently on the table, as there might be 'Plan C,' 'Plan D,' and even 'Plan E.'

TSMC is a leading advanced packaging supplier, so Musk's Terafab might be interested in making chips in Texas (presumably using Intel's 14A process technology) and then package them in Texas, which is where TSMC might come into play. Another thing to consider is that while Intel has a broad cross-patent license agreement with TSMC, Terafab does not, so producing chips using an Intel-developed node might infringe one of TSMC's patents, which might become a problem. To that end, Musk needs to keep TSMC close, perhaps to the point of buying into Terafab.

One thing to certainly keep in mind is that Elon Musk barely wants Terafab to become a foundry that competes against Intel Foundry, Samsung Foundry, or TSMC. What he needs is an uninterrupted and surplus supply of custom silicon to SpaceX, Tesla, and xAI to support their AI, automotive, and space vehicles. Given the rather broad strategic goal, Musk is probably very flexible when it comes to both tactics and strategy.

A rumored SKU table for Intel's upcoming Nova Lake desktop CPUs has surfaced, showcasing seven models that will (presumably) make up Intel's initial NVL-S lineup. The list includes three models with the "BFC" tag, which seems to be Intel's branding for bLLC, or big last level cache. It's been heavily rumored to show up with Nova Lake, countering AMD's assault on the best CPUs for gaming with its X3D chips.

As previously rumored, the table tops out at the flagship Core Ultra 9 4970K BFC, which the spec list suggests is a 28-core chip with 8 P-cores, 16 E-cores, and 4 LPE-cores. It also lists a 125W TDP and an integrated GPU with 32 Execution Units (EUs). This 32-EU iGPU is apparently a staple across the range, short of the Core Ultra 5 4650KF, which lacks integrated graphics.

Intel retired the use of "EUs" in favor of its Xe cores several years ago. Rumors suggest Intel isn't releasing a large, 12-Xe core model of Nova Lake. The 32-EU count here likely comes out to 4 Xe cores (each core has eight matrix and vector ALUs).

The table does not include the heavily rumored 52-core Nova Lake model. However, as the Nova Lake launch approaches, it has become clear that the 52-core model, as well as other potential models with a dual-tile configuration, will arrive after the main range of chips. Presumably, these models will target the HEDT crowd with their high core counts.

*Names and specifications rumored, unconfirmed by Intel

There are several interesting details when looking at the range broadly. Most notably is the four-number model identifier, which Intel didn't use with Arrow Lake chips like the Core Ultra 7 270K Plus. This larger identifier has been previously rumored, and it makes sense if the lineup above is indeed real. There's quite a bit of specificity in this stack, and something like the "Core Ultra 9 497K" doesn't signal what a "Core Ultra 9 4970K" does.

Regardless of naming, the SKU table shows three models with BFC, two of which fall under the Core Ultra 9 umbrella. There isn't a Core Ultra 5 BFC option. The most interesting model is the Core Ultra 9 4900 BFC, which matches the 22-core count of the Core Ultra 5 models, though with the addition of BFC and a lower 65W TDP. Given this chip doesn't have a K suffix, it looks like a specialized, low-power gaming chip, perhaps for small form factor desktops.

In addition, the Core Ultra 5 model is the only one with an F suffix, noting that it lacks integrated graphics. As we saw with the Arrow Lake refresh, Intel released a Core Ultra 5 250KF Plus, though it never gave the 270K Plus the KF treatment.

According to the table, Intel could use "BFC" to note chips with a larger L3 cache, something that's been heavily rumored for Nova Lake as AMD's X3D chips dominate gaming in our CPU benchmark hierarchy. This is the first time we've heard it referred to as BFC; however, with previous rumors referring to the additional cache as bLLC.

As for what BFC stands for, there are a few possible candidates, and we'll leave it to your imagination as to what words that start with "F" could fit between "Big" and "Cache."

Although Intel's Nova Lake chips have been the topic of the rumor mill for well over a year, the launch is approaching. At the beginning of the year, Intel's CEO confirmed Nova Lake would arrive before the end of the year. Assuming that's still true, we'd expect to learn more any day now.

Signs certainly point to a launch happening soon. Just this week, Nova Lake platforms passed compliance at USB and PCIe standard bodies. At Computex earlier this year, we saw two Z990 motherboards in the flesh. And last month, a leaked slide presumably from one of Intel's partners provided a tease as to what the platform could look like.

Hopefully we'll have more details soon. In the meantime, make sure to check out our recent interview with Intel's Robert Hallock, where the executive goes into some of the expectations around Nova Lake, on Tom's Hardware Premium.

The USB Implementers Forum now lists some of Intel's Core Ultra 400-series 'Nova Lake' platforms in its Integrators List, meaning that the products have passed applicable USB compliance and interoperability tests. The PCI-SIG Integrators List also includes Intel’s 900-series chipsets for Nova Lake-S processors. Such tests are conducted ahead of product launches to ensure interoperability and to gain the right to use the PCIe and USB logos on new products.

The USB-IF listing confirms that Intel's mobile Nova Lake-H processor (Device ID D331, D333) is compliant with the USB4 80 Gbps specification (which is not surprising, as the part is also supposed to support Thunderbolt 5). In contrast, Intel's desktop Nova Lake PCH-S chipset (Device ID 6E6E) is compliant with the USB 3.2 Gen2 standard and supports a data transfer rate of up to 20 Gbps, which is in line with unofficial information about Intel's 900-series chipsets. Meanwhile, the Integrators List lacks Intel's desktop Nova Lake processor that is expected to support USB4 (more on this later).

The choice of the products to certify first — a desktop chipset and a high-performance notebook CPU — may seem a bit odd. However, there is a good explanation for why Intel submitted these parts to the Integrators List ahead of others and why the order of such submissions for compliance testing does not matter significantly in this case.

The USB-IF has a program called Qualification by Similarity (QbS) for sufficiently similar products, under which testing one product can enable related products to be certified and added to the Integrators List with limited or no additional compliance testing. Since USB4 and USB 3.2 circuitry in different Nova Lake products is similar, Intel can submit select CPUs and chipsets for USB-IF compliance tests and then follow up with the QbS.

Meanwhile, since USB-IF certification is formally attached to a specific product name, model, and revision, differently named products are not certified automatically simply because they contain identical USB circuitry. These products must be submitted separately under QbS, after which USB-IF decides whether the differences are significant enough to require additional testing.

The PCI-SIG Integrators List has included Intel's 900-series chipset (Device 6E38-6E3F, 6E30-6E35, 6E40-6E47) for Core Ultra 400-series 'Nova Lake-S' processors since April. In early August, the company’s as-yet-unidentified processor (Device IDs D461, D465, and D467–D46A) with a PCIe 5.0 x16 root complex passed interoperability tests and was listed alongside the chipset. We cannot state with certainty that this is a desktop Nova Lake CPU, although it is reasonable to suspect that the device belongs to the desktop Core Ultra 400-series platform.

As the official launch of Intel’s Core Ultra 400-series ‘Nova Lake’ processors for desktops and laptops looms, these platforms must pass various compliance and interoperability tests administered by industry standards organizations. So far, Intel’s Nova Lake CPUs and supporting chipsets have passed interoperability tests with the PCI-SIG and USB-IF. However, in the coming weeks or months, they will likely appear on other compliance and interoperability lists as well. Intel will also eventually need various regulatory and environmental documents, depending on what exactly is being sold and where, though such documents rarely enter the public domain ahead of formal launches.

Anyway, Nova Lake's listings in PCI-SIG and USB-IF Integrators List point to Intel's preparations for the launch of new CPUs for desktops and laptops. The latest leaks point to Core Ultra 400-series launches in Q1 2027, so setting the stage for their release early next year is a natural move for Intel.

Intel has published a patent to integrate MicroLEDs directly into a CPU package. Aside from communication functions, Intel lists many possible uses, including using multi-colored lights to light up the wording on a processor. The patent, filed in 2022 but only published earlier this month, describes embedding a MicroLED into the package by using a glass substrate and through-glass vias (TGV), connecting directly to a die for power and signal routing. The patent says the purpose of the LEDs is "either aesthetic components of the electronic device or to indicate certain operations being performed by the electronic device."

As is the case with any patents, the purpose of embedding MicroLEDs into a chip is left open-ended. However, Intel interestingly calls out implementing MicroLEDs into a CPU, specifically, and provides several examples of how the tech might be used. The patent says the processor "may operate the micro LEDs so that the micro LEDs visually indicate that certain functions are being performed by the processor or simply for aesthetic effects."

In one part of the patent, Intel describes the LEDs being used to "light up wording across a central processing unit," suggesting some sort of read-out available directly on the CPU. How that would work on a standard processor with a heatsink atop remains an open question. In addition, the patent explicitly calls out that the LEDs can be different colors depending on the implementation. That could mean something more akin to RGB memory than a diagnostic readout. The patent leaves room for both designs.

You can see the main drawing for the patent above. In the middle is the glass substrate, sandwiched between two layers of package substrate. A semiconductor die is partially embedded within the glass substrate, leaving just the back surface of the die exposed; however, the patent says the die can be fully embedded in other implementations. The LEDs are connected directly to the semiconductor die, or through nanowires, and TGVs deliver power and signal to the semiconductor die through the glass substrate.

Intel says it builds the package with two layers of silicon nitride, which are formed on the package substrate surface and then attached to the glass substrate. Intel has been working through glass substrates for over three years now, as Intel claims it has 10 times better interconnect density than organic substrates.

The main patent drawing only shows a single IC, though the patent notes that's simply shown "for clarity." A finished product implementing this technology "will have an array or arrays of micro LEDs on one or more IC packages." So, given an ambitious-enough design, Intel could implement multiple LED-based functions directly into the processor.

Patents aren't products, and that's always an important reminder. Intel filed this patent over four years ago, and it's just now being published. Whether we actually see MicroLEDs embedded in a processor remains an open question. However, Intel has laid the groundwork to do something like that in the future.

Intel has been granted a U.S. patent that discusses embedding MicroLEDs inside chip packaging, as TrendForce reports. The design embeds semiconductor dies fitted with MicroLEDs directly into a glass substrate and connects them using Through-Glass-Vias (TGV) to provide power and signal connections, allowing them to emit red, green, and blue (RGB) light. Intel suggests this technology could be used for diagnostic testing and to create customized light effects on the chip's surface for personalized electronics and improved aesthetic appeal.

The potential for this to support optical signaling is intriguing, and likely holds significant commercial potential for Intel. Taiwanese optoelectronics firm AU Optronics has a technology roadmap that overlaps with Intel's patent, with some rumored collaboration between the pair, suggesting the two companies may be jointly developing companion technologies in this space.

AUO recently showcased Micro LED optical communication at SEMICON Taiwan 2026, with a design goal interconnect range of up to 10 meters, targeting use in AI data centers. Embedding Micro LEDs into a glass substrate could offer an alternative integration approach for co-packaged optics to Intel's previous demonstration of a co-packaged optical I/O chiplet.

How Intel wants to build chips with glass

In the patent, Intel describes using laser treatment and etching to create the through-holes and die cavities within the glass substrate. It would then use copper electroplating to form the TGVs before embedding the dies carrying MicroLEDs into the substrate. Silicon nitride layers join the glass to polymer package substrates on either side, while conductive vias carry signals and power.

The patent also describes the potential for differing structural variations, including alternative arrangements for horizontal or vertical die placement, and the integration of reflectors to direct light out of the package through the glass substrate.

Intel has been investing in glass substrate technology since the early 2010s and has showcased test packages using glass substrate materials. In January this year, at NEPCON Japan, it demonstrated an engineering sample of a glass core package combined with its EMIB multi-chip module technology.

At ECTC in May, Intel also showcased a 24-layer glass-core panel with copper-filled TGVs, with two embedded EMIB bridges. Arguably more importantly for its chip design and fabrication business, it presented results demonstrating progress towards high-volume manufacturing validation for its glass core substrate designs.

Potential for diagnostics and aesthetics

MicroLEDs built into the chip packaging itself hold potential for diagnostic and testing purposes. They could be used to provide visual indicators of completed tests or failures, without requiring external LEDs or other indicators on motherboards or connected components. Intel's patent doesn't describe a complex diagnostic system, but with pre-determined lighting patterns assigned specific meaning, die-embedded MicroLEDs could provide more streamlined feedback during validation and testing phases.

The patent also discusses the potential for aesthetic use cases of in-package LED lighting. DIY electronics could use it for personalization, including illuminated lettering on the chip's surface. Such designs would need to take cooling into consideration, though. Dies that draw enough power to demand external cooling may not be able to avoid obscuring the MicroLEDs on the package surface.

That could limit this use of the technology to low-power chips, or simply demand a specific heatsink configuration, leaving portions of the packaging bare to ensure the MicroLED light is still visible.

A potentially more significant application of this technology, however, is in an alternative optical interconnect system. The patent doesn't establish a high-speed working optical interconnect, but with AUO's parallel developments in Micro LED CPO modules, the potential is certainly there.

The implications for CPO

MicroLEDs also have potential for optical signaling. AUO's showcase earlier this month highlights this. Combining MicroLED transmitters and Micro photodetector receivers, AUO is developing a system-level MicroLED CPO module designed for high-speed interconnect applications.

Intel's patent could lay the groundwork for something similar. It hasn't proposed that application, nor does the patent make such claims, but embedding MicroLEDs in-package could provide a starting point for integrating optical transmitters.

Embedding emitters is only part of the communication system, though. Where AUO and its partners have showcased MicroLED optical interconnection as a real development direction for CPO, Intel's patent only describes a packaging technique that could support such a system. Like AUO, it would need the receivers and optical fiber solutions to develop a full optical interconnect module.

Intel is clearly investing heavily in glass substrate technologies and has been developing advanced interconnects for years. If it were to partner with AUO on its existing developments, it could accelerate its own efforts in this space and provide an alternative method for bringing interconnects within chip packages.

But that's still very much up in the air. Until Intel makes a more concrete announcement, this is more potential than actual.

Intel's 14A (1.4nm-class) process technology is expected to deliver performance 'within 5%' of TSMC's A14 (1.4nm-class) production node, Naga Chandrasekaran, the chief technology and operations officer as well as general manager of Intel Foundry, told investment banking firm KeyBanc (via @Alex_Intel_). Given TSMC's track record of delivering steady performance, power, and area (PPA) gains with every new node, this might sound like entirely good news. However, the statement deserves a closer examination.

Delivering 'within 5%' performance is an ambiguous statement that may mean that 14A will be 5% faster than A14, or that 14A will be 5% slower than A14. While 'within 5%' performance compared to the direct rival of the same class may sound like a good competitive position, in recent years Intel's process technologies trailed TSMC's nodes in transistor density and remained competitive in performance or power. This was, to a large degree, attributed to Intel's historic focus on CPU performance, but not necessarily transistor density, as its own fabs have offset additional costs associated with larger dies.

In fact, actual shipping processors suggest Intel's 18A is at least competitive with TSMC's N2 in maximum achievable CPU frequency as Intel's Core Ultra X9 388H 'Panther Lake' can hit 5.10 GHz (at an 80W max turbo power), AMD's EPYC 9586F has the highest single-core clock of 5.0 GHz (at a default 500W CPU power), Apple's A20 Pro can achieve 4.93 GHz, whereas Apple's M6 can hit 4.78 GHz. These numbers should not be converted directly into a statement such as '18A is X% faster than N2,' because the processors use different architectures, voltages, standard-cell libraries, thermal envelopes, and physical implementations. However, they do provide a useful real-world reference point: the available N2 processors do not show a substantial frequency advantage over 18A. If anything, the highest observed CPU frequencies favor Intel's process.

Based on internal estimates, Intel officially states that compared to its already fast 18A, its 14A is expected to provide 15% – 20% higher performance at the same power, or 25% – 35% lower power at the same frequency and transistor count. By contrast, TSMC expects its A14 to be 10% - 15% faster than N2 at the same power, or 25% - 30% lower power at the same clocks and transistor count.

Combining the observed 18A and N2 CPU frequencies of Intel's 18A and TSMC's N2 with Intel's stated 15% – 20% 14A gain and TSMC's assumed 10% – 15% A14 gain would ordinarily suggest a modest 14A performance advantage of A14 even in most conservative scenarios for Intel. Therefore, Intel's new expectation that 14A will be 'within 5%' of A14 is notably less ambitious than one might infer from the company's published process specifications, even though the 'within 5%' statement does not tell us which process Intel expects to lead.

In fact, advantages of Intel's 14A over TSMC's A14 can be calculated using the highest observed 18A and N2 CPU clocks combined with Intel's and TSMC's official iso power performance projections.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 5.00 GHz (EPYC 9586F).

With Intel’s Core Ultra X9 388H and AMD’s EPYC 9586F as the starting points, the official iso-power performance projections imply a 2% – 11.3% potential performance advantage for 14A over A14, depending on the combination of process-performance assumptions.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 4.78 GHz (Apple M6).

Using Apple's M6 as the real-world N2 reference, a similar calculation gives Intel 14A a 6.5% – 16.2% implied advantage over TSMC A14. Even the worst possible combination for Intel — 14A achieves only +15% while A14 achieves the full +15% — puts Intel's node well beyond the 'within 5%' estimate given by Naga Chandrasekaran.

It should be clearly noted that our calculations do not predict 14A or A14 CPU frequencies, as we use clocks from current CPU architectures with improvement claims for upcoming process technologies. The calculation is useful primarily for illustrating what the companies' published numbers imply relative to today's products.

Intel's 'within 5%' assessment raises an interesting question: why does Intel expect 14A and A14 to be so close when the companies' published process gains appear to suggest a larger gap? Perhaps Intel's assessment incorporates factors that these simple calculations do not capture. Or perhaps the head of Intel Foundry took a page from his boss Lip-Bu Tan's book and now prefers to underpromise.

The Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has developed an experimental process flow for building stacked-nanosheet gate-all-around (GAA) transistors using immersion DUV lithography and demonstrated functional devices. The flow is intended for eventual use with 3nm-class and smaller process technologies by Chinese chipmakers that do not have access to EUV scanners, reports DigiTimes.

While IMECAS has demonstrated functional GAA devices, it has not disclosed the critical geometrical parameters that would allow comparisons to 3nm-class transistors from other chipmakers. Furthermore, the experimental process flow for building transistors is not even a defined process flow for building research chips, much less a complete 3nm-class manufacturing process.

Nonetheless, the achievement is quite important as it demonstrates that China is capable of developing its own branch of semiconductor evolution without using leading-edge tools from Western companies.

Early process integration complete

Ye Tianchun, chief engineer of China's National Major Special Project 02, said at the IC World conference in Beijing that IMECAS had completed 'early process integration' for stacked nanosheet-channel GAA transistors fabricated with DUV lithography. The researchers from IMECAS obtained devices with Ion/Ioff ratios of 9.7×10⁵ and 7.6×10⁵, both exceeding the 5×10⁵ threshold, which means gate control of the stacked sheets is working. These figures indicate that the experimental transistors can distinguish between their conducting and non-conducting states, but they say little about transistor density or whether their physical dimensions correspond to those expected from commercial 3nm-class technologies.

In particular, IMECAS has not disclosed gate pitch, metal pitch, nanosheet dimensions, transistor density, SRAM density, or other geometrical characteristics that could put its devices into perspective against 3nm-class production nodes from Intel, Samsung Foundry, or TSMC. Therefore, the achievement should be viewed as validation of a stacked-nanosheet GAA process flow based on DUV lithography rather than evidence that China has developed a 3nm process without EUV.

The most important part of the experiment is that IMECAS is investigating how GAA devices intended for future 3nm-class and more advanced technologies can be fabricated without using EUV lithography, something that nobody has done before in volume production.

GAA transistors have succeeded FinFET devices at leading-edge nodes because placing the gate around nanosheet channels provides better electrostatic control as transistor dimensions shrink. IMECAS has been developing technologies required for this transition since 2020, and its particular focus was on nodes below 3nm, which is why it now mentions 3nm as part of its announcement.

Reducing China's dependence on advanced foreign tools

It goes without saying that IMECAS' work in recent years has been focused on reducing China's dependence on tools, software, and other technologies that are designed by Western companies and therefore subject to export restrictions imposed by American, Japanese, or European countries.

Among other things, Ye mentioned architectural innovation, design-technology co-optimization (DTCO), system-technology co-optimization (STCO), and 'extracting more value' from mature fabrication technologies. For now, IMECAS' result demonstrates a DUV-based route for researching stacked-nanosheet GAA transistors intended for future 3nm-class technologies, but not a China-developed 3nm process ready for manufacturing even in the long-term future.

Even if IMECAS eventually demonstrates appropriately scaled GAA devices using DUV, or discloses critical geometry parameters of the current work, this would still be far from a production-ready 3nm-class technology. Commercial manufacturing requires integration of lithography with deposition, etching, cleaning, metrology, process control, materials, temperatures, and many other steps and parameters. For now, IMECAS has not demonstrated such a manufacturing flow.

Phoronix reported that Intel appears to have suspended its bounty program that once paid up to $100,000 per bug. Intel’s replacement for the Intigriti program offers no rewards, and no reason was given for the change. The Intigriti site states that it “is a responsible disclosure program without bounties,” confirming the report. A check of the site shows that the bounty board is still up but lists the program as suspended.

Intel’s site still lists details on the bug bounty program with awards that range “from $500 up to $100,000, based on quality of the report” and other factors. This program launched, invite-only, in 2017, and became open to all researchers in 2018, covering software, hardware, firmware, and open-source projects. Almost half of the CVEs Intel addressed in 2020, 105 out of 231, arrived through the bounty program, Intel said.

The old bounty board split vulnerabilities into four tiers, which were priced accordingly: Tier 1 from $2,000 to $100,000, Tier 2 $1,000 to $30,000, Tier 3 $500 to $10,000, and Tier 4 $250 to $5,000. Intel expanded the program’s scope to include web services between mid-2025 and October 2025, but it said in a January 6 update on Intigriti that it was evaluating “enhanced bounty and bonus criteria.” In about eight months, the bounties went from evaluation to suspension.

The outlet speculated that with the Linux kernel and other open-source projects being “bombarded” with security reports, it would not be surprising if AI bug-seeking played a role. Linux kernel CVEs have approached 2,000 per release, a fourfold increase from about 500, with maintainers “completely overwhelmed.” Linus Torvalds, the creator of the Linux kernel, has said that duplicate AI reports on the kernel security list are “almost entirely unmanageable.” Curl, for one, closed its bounty program due to AI slop floods.

As a point of reference, HackerOne’s Internet Bug Bounty (IBB) program paused submissions effective March 27. “AI-assisted research is expanding vulnerability discovery across the ecosystem, increasing both coverage and speed,” HackerOne said on the program’s page. HackerOne is still paying queued submissions, with rewards from $68 to $2,257 based on severity. This supports the idea that AI has affected software programs, but it may not be as significant for hardware and firmware.

Intel’s next steps are worth watching to see if this suspension ends up permanent in a fast-changing landscape. Researchers are still able to submit vulnerabilities through the new program; it just offers no bounties for them. Checking AMD’s Intigriti page today shows that the program there is also suspended, although Intigriti does have an auto-suspend mechanism. This follows an earlier payment dispute over scope with a bounty hunter in June.

Even if AI tools carry a stigma and may be a factor in these recent events, they have proven handy. AI company OpenAI paid Hacktron researchers a $6,500 bounty for a discovered exploit chain using rival Anthropic’s model. Torvalds, who previously dismissed AI as mostly marketing, has also called AI “clearly a useful” tool, and acceptance in the field may grow.

An Intel Celeron 1200 (Tualatin) was revived from the dead following an intricate bit of repair work by Bits und Bolts. The quarter-century-old chip looked like it had a fatal injury, with one of the pins missing and the underlying pad ripped off. As things stood, a system with this close relative of the Pentium III installed simply wouldn’t boot. However, thanks to careful digging “deep into the substrate” and some delicate preparation work, the enthusiast managed to solder on a donor pin and get this CPU running again – and then overclocked it by 33%.

As the Celeron 1200’s missing pin was a data pin (D47), this was a definite fix-or-be-damned situation. Sometimes CPUs can have a pin or two missing, and they will work anyway. I’ve seen CPUs shrug off such missing connections when several remaining pins duplicate a function – power or ground pins, for example.

Bits und Bolts started the repair process with a close-up of the serious-looking damage. Then we see the missing pin area after they have apparently “dug a hole” so that the work/issue can be seen more clearly. Zoomed-in images show that there were several layers of copper exposed from under the green surface. The new pin must be connected solely to the central circular area you can see, and not accidentally connect with any of the copper planes surrounding it. Thus, the TechTuber started by applying solder mask to this area. Remember, these pins are very small, and it would have been an intricate job to mask the surrounding area solidly yet cleanly.

While the solder mask surrounding the Intel Celeron 1200’s vacant pin cured, Bits und Bolts harvested a few pins from another Tualatin chip that was “definitely broken.” Returning to the CPU under repair, it was time to add flux, then try to ‘tin’ the central circular copper area to which the donor pin would be soldered.

Soldering the donor pin went smoothly, leaving it perfectly in position and upright. You can definitely see which pin has been added by Bits und Bolts, but after nervously adding the repaired Celeron 1200 to a socket, the TechTuber was relieved that everything mated cleanly.

Instead of firing up the computer with the repaired processor installed straight away, the tech tinkerer took a few readings with their multimeter. There were no obvious issues. At last, the moment of truth came, and the patched-up processor-packing PC system booted without issues. Bits und Bolts commented that this was the first time they’d repaired a processor pin issue that looked so grave. The end of the video sees the CPU tested in various benchmarks, including SiSoft Sandra. Moreover, it was even overclocked by 33%, stable at 1,600 MHz.

Intel's Nova Lake CPUs are no stranger to leaks. We've been talking about the processors for close to two years now, with rumors swirling about bLLC and a 52-core flagship for well over a year. However, this week (and this month more broadly), we've seen leaks hit a fever pitch, suggesting that Intel is finally gearing up to release a generation of processors that's been the zeitgeist for over 24 months.

Intel hasn't shied away from discussing Nova Lake, with Intel's enthusiast channel VP Robert Hallock telling Tom's Hardware Premium that it's one of the most important launches for the company ever. At the beginning of the year, Intel CEO Lip-Bu Tan said that Nova Lake would launch in the second half of 2026, and despite expected hubbub about delays/cancellations, that's the North Star Intel itself has set. So, that's also going to be our North Star here.

There are three stories that have come out over the past week and a half. First, a screenshot of some high-level details about Nova Lake surfaced online, showing the launch schedule and platform details. The slide in question is almost certainly from one of Intel's partners and not Intel itself.

Just in the past few days, we've also seen a barrage of Z990 motherboards from ASRock surface in the NBD shipping database, as well as some entries in the SiSoftware database for a next-gen HP EliteBook X sporting an unknown Intel processor.

An increase in the number of leaks/rumors, especially those that are more than a known leaker writing up a post on X, usually points to an imminent launch. We've heard about Nova Lake for over two years, yes, but now we're seeing more concrete details. In addition to the shipping manifest, snapped slide, and SiSoftware results, we also saw two Z990 motherboards ourselves at Computex earlier this year, with a third rumored. We will not predict the Nova Lake release date here. However, the launch is coming soon. That much we're confident in.

Intel's typical release cycle for desktop CPUs

In order to establish a timeline, we first need to look back. We could go back far, but we're cutting the timeline short here at Alder Lake. That was when Intel finally moved off 14nm, following generation after generation of either an underwhelming launch or a delayed one, and it's most relevant to what Intel is doing today.

The timeline above is fairly straightforward. Intel has, short of 2025, launched a new generation of desktop processors in the fall every year for the past five years. This annual cadence was even more intense previously; 7th-Gen and 8th-Gen CPUs were both released in 2017, and 9th-Gen in 2018. Then, Intel took a year off and followed up with 10th-Gen in 2020 and 11th-Gen in early 2021. Keep in mind that we're talking about desktop CPU launches with a new microarchitecture here. Obviously, Intel has released a ton of other products in between the gaps.

The interesting bit about the timeline is actually the end with Arrow Lake Refresh. When we spoke to Robert Hallock earlier this year, he told us that a team that was "pretty much completely different" worked on Arrow Lake Refresh compared to Arrow Lake. That might explain the strangely large gap between Arrow Lake and Arrow Lake Refresh. Even looking at the Arrow Lake and Arrow Lake Refresh stacks side-by-side, it's obvious that a different mentality went into how they were positioned in the market. That team is in in-place now, and Hallock told us the team is "moving faster than we ever have in product, in release cadence."

Don't take Hallock's comments about Intel moving faster than ever at face value — he was probably being at least a little hyperbolic — but the sentiment is clear. Following the poor reception of Arrow Lake, Intel reorganized and set a new roadmap in motion that extends out to 2030, and now, that roadmap is being executed, starting earlier this year with Arrow Lake Refresh. That sets up Arrow Lake Refresh similar to 11th-Gen Rocket Lake, serving as somewhat of a stopgap before the next generation properly arrives (that is, thankfully, where the comparisons between Arrow Lake Refresh and Rocket Lake end).

Back to Nova Lake. Earlier this year at Computex, we saw two Z990 motherboards, one of which we confirmed was not a finalized unit. The complete development process takes generally four to six months for a motherboard, and you can add another two months or so on top of that for channel sales, as pallets of PCBs are loaded onto ships and swim across the Pacific Ocean. That was in June.

The shipping manifest that surfaced this week showed shipments in July for ASRock. Critically, it also shows shipments from two different sources: Taiwan and Vietnam. Given what we saw at Computex and the two different sources for ASRock, we're firmly past the early prototype and engineering validation stage of motherboard design. Assuming everything goes according to plan, that means Z990 motherboards should be ready to go on store shelves by no later than October or November.

Keep in mind that does not mean Nova Lake will launch in October or November, just that motherboards will most likely be ready by then. This aligns with what motherboard vendors told us earlier this year, with some brands pointing to Q3 but most to Q4 for a Z990 rollout.

Parsing the details about Nova Lake so far

Currently, there are two camps when it comes to when Nova Lake will release. Some say it'll arrive this year, likely in Q4, while others say CES 2027 in January of next year. As we wrote earlier in the article, we will not predict the Nova Lake release date. However, we will side with one of the camps here as more likely based on what we've seen so far.

Given everything we've seen, a late 2026 launch is more likely. The strongest evidence of that is the comment from Tan earlier this year, where the executive said Nova Lake is "coming at the end of 2026." The critical context is that Tan made that comment as part of his prepared remarks, preceding the actual financials that you hear in an earnings call. An earnings call is not a keynote, and making material promises you knowingly can't keep can land you in hot water.

Executives massage the truth all the time during earnings calls — that's half the reason there are prepared remarks ahead of the financials. However, that key detail about an end of 2026 launch isn't massaging the truth. It's a concrete claim devoid of weasel words and qualifiers. In addition, Intel's fiscal year aligns with a calendar year; when Tan said end of 2026, he meant end of 2026, regardless of fiscal or calendar year.

It's possible that something changed between now and January when that call took place. However, the timeline still lines up given the various motherboards that showed up between June and July of this year. At this point, Intel can slide the actual release date around by a bit, but not by months. Retailers aren't going to sit on pallets of motherboards with no home indefinitely.

The one wrinkle in this is the leaked slide you can see above, which claims Nova Lake will enter mass production in Q4, with a launch in Q1 2027. There are reasons to be skeptical of this slide, however. For starters, the slide doesn't say anything that hasn't been heavily rumored for months (sometimes even years) at this point: 52-core flagship, up to 288MB of bLLC, LGA 1954 socket, and multi-generation socket support. The strange bit is a mention of Hammer Lake at the bottom of the slide.

We've heard very little about Hammer Lake, and nothing that's passed muster for us to cover on Tom's Hardware. Even among the rumors, the launch has been pinned somewhere in the 2029/2030 range, if the lineup is even real to begin with. Regardless, Hammer Lake isn't what we'd expect to see next to Razor Lake — the generation rumored to follow Nova — and certainly not what we'd expect to see under a "Q4 2027+" badge.

That doesn't mean the slide is fake; it doesn't appear to be fake. There's some very critical context missing from it, though. It's a Chinese source, but did it come from an OEM? A distributor? A retailer? The validity of the slide changes dramatically depending on that. Further, we're only seeing maybe half of a single slide here. There's too much context missing to take this single slide and run with it as concrete truth.

At the very least, it fares poorly against prepared comments made by Intel's CEO, motherboards we've seen (and held) ourselves, and have circulated through photos online, and strong indications from Intel's motherboard partners that they'll be ready for a launch in Q4. Add on top of that the fact that Intel took 2025 completely off for new desktop launches (and its usual cadence of launching in the fall), and a Q4 rollout of Nova Lake looks far more likely.

Likely isn't the same as confirmed. We're still awaiting details on Nova Lake from Intel proper, and hopefully those will arrive soon. Given the anticipation Intel has already built around Nova Lake without a single performance claim or spec shared, we'll have a lot to talk about.

Even as chipmakers race to build the most advanced chips inside the United States, experts are saying that their efforts are facing one monumental challenge: a massive shortage of skilled workers to run the fabs and factories. According to CNBC, global consulting firm McKinsey and the SEMI Foundation suggest the industry will have up to 157,000 positions that could remain unfilled by 2030.

“I’m concerned,” Samsung semiconductor division EVP Jon Taylor told CNBC in an interview. “We just don’t see that there’s enough technical people in the pipeline.” The McKinsey report says that only 3% of U.S. engineering graduates end up working in the semiconductor industry, and that 73% of chip companies are finding it hard to fill engineering roles. This is a huge contrast to other tech jobs, which saw record layoffs by June of this year, when over 40,000 positions were axed, ostensibly largely due to AI.

The massive demand for memory and storage chips driven by the AI boom, combined with Washington’s efforts to bring semiconductor manufacturing back to the United States, has led to the buildup of multiple fabs and facilities dedicated to it. TSMC was one of the first companies to kick off this building spree, when it started construction on its Arizona campus in 2021. The site started churning out chips last year, with the company committing another $100 billion in July 2026 to build four more 2nm fabs. Intel’s Ohio One plant, which was, at one point, America’s largest fab complex, is also underway, with the site expected to start production between 2030 and 2031.

The big three memory makers — Micron, Samsung, and SK hynix — are also planning or have recently completed major expansions in the U.S. Samsung is starting advanced semiconductor manufacturing in the U.S., with its Taylor, Texas, fab entering risk production this year. The fab is targeting an output of 50,000 wafer starts per month, and it is expected to create 3,500 jobs. “We’re hiring engineers, we’re hiring technicians, we’re hiring people in the supply chain,” Taylor told the publication. “Everybody wants and needs the same thing, and it’s a bit of a race against time right now as everything is starting to come online.”

Micron is also currently building its Boise, Idaho, memory chip fab, which began construction in 2022 and is projected to begin wafer production by 2027. The company has also formally broken ground on its $100-billion New York “megafab,” with aims to produce 40% of its global output within the U.S. by the 2040s. Aside from these massive manufacturing sites, it has also committed $10 billion toward new research labs in the U.S., to be built near the global Micron R&D center in Boise.

Finally, SK hynix also started construction of its first HBM plant in the U.S., with its West Lafayette, Indiana, campus dedicated to packaging these crucial components for AI data centers. There have also been rumors that the South Korean company is in talks with Intel to either lease space at its Ohio One factory or launch a joint venture alongside other AI hyperscalers to build memory chips in the U.S.

All these construction projects, plus the requisite supply chains, will necessitate thousands of workers. Local universities like Purdue University and Arizona State University are already investing millions of dollars to help prepare a capable workforce, with the former launching degrees in 2022 focused on semiconductors. Samsung and Intel are also investing in various programs, including internships and scholarships, to help secure a future workforce for the companies.

However, salary is one major concern listed by the SEMI Foundation. U.S. chip fabs typically pay $127,000 to $187,000, with senior staff getting $238,000 or more. While this is a more-than-competitive salary in the U.S., it’s dwarfed by the bonuses recently offered by Samsung and SK hynix in South Korea, which have reached hundreds of thousands of dollars. With the projected worker shortfall, we should expect the job offers from these semiconductor companies to catch up with their eastern counterparts if they want to secure and maintain talent here in the U.S.

South Korean memory chip manufacturer SK hynix is in talks with Intel to start manufacturing inside the U.S., according to Reuters. The company is reportedly considering multiple options, including leasing space at the under-construction Intel Ohio One site and forming a joint venture with Intel and other AI hyperscalers desperate for HBM.

This move could help alleviate the memory shortage. It would also complement the company’s expansion in Indiana, where it recently broke ground on an HBM packaging plant a few weeks after its historic $26.5-billion Nasdaq listing. It’s unclear yet if these talks are part of the results of the South Korean president’s visit to Silicon Valley in an effort to expedite negotiations between its top tech companies and their U.S. counterparts, but SK Group chairperson Chey Tae-won told reporters in July, “I think we need to build a factory in the United States. If possible, I believe we should build it.”

However, there are also concerns that Seoul might object to such investment. The South Korean government just unveiled a $520 billion investment plan to increase chipmaking capacity within its shores and keep the country competitive in the AI race; at the same time, it’s also in talks with the U.S. to finalize its $350 billion investment commitment to Washington to reduce tariffs on South Korean goods, $200 billion of which is still undecided on which projects it will be deployed on. Meanwhile, the Commerce Department has threatened to impose more tariffs on South Korean and Taiwanese tech companies if they fail to invest in U.S. manufacturing. This potentially puts SK hynix at a precarious position, especially as it balances the demands from the White House and the Blue House.

Neither company has confirmed these rumors, though. SK hynix told Reuters that it’s “reviewing various measures, including establishing additional production bases, to strengthen the competitiveness of its memory business,” but “no matters have been determined at this stage.” On the other hand, Intel called them speculation and declined to comment on the matter, only saying that it was continuing to invest in the Ohio project, which is expected to come online between 2030 and 2031.

Intel won't launch a Nova Lake-S SKU with 12 Xe3P graphics cores, according to tipster Jaykihn, who originally flagged a beefed-up APU design with the Nova Lake architecture. The original SKU was said to come with 4 P-cores, 8 E-cores, and 4 LPE-cores, along with the 12 Xe3P cores, presumably offering an inexpensive onramp to a gaming desktop without a discrete GPU. Now, the leaker says that design is cancelled, and Intel intends to pick it back up with Razor Lake, the generation that will follow Nova Lake.

Originally, Intel's 12 Xe3P Nova Lake SKU was said to require 65W of dedicated power to drive the iGPU, necessitating the use of two VCCGT phases on the motherboard for integrated graphics. Intel's Arc B390 GPU, which is the 12 Xe3-core model available in Panther Lake and Arc G-series processors, has a thermal design that can sustain up to 80W. However, it's currently being used in Panther Lake machines and handhelds like MSI Claw 8 EX AI+ that have lower power targets.

The Xe3P architecture is slotted for use in Intel's Crescent Island AI accelerator, but it hasn't been announced for any other products yet. Xe3P supports a wide deployment of Xe cores (up to 32), a deeper XMX engine with support for low-precision data types like FP8 and FP4, an increased 512KB L1 cache per Xe core, and a new unified L2 cache (32MB on Crescent Island).

Even by desktop APU standards, an 80W iGPU is a beefy accelerator to have on the same package. In addition, Intel's Nova Lake stack is said to extend up to a 175W TDP with the rumored top-end 52-core SKU, meaning the full 12 Xe3P iGPU would likely only be possible lower down the stack (and maybe only in the 4 + 8 + 4 + 12 Xe design originally suggested).

Earlier in the year, rumors suggested Intel was working on a mobile APU to counter AMD's Strix/Gorgon Halo products, featuring a large pool of unified memory and a large iGPU, dubbed Nova Lake AX. Now, the rumor mill suggests Intel will recycle the Nova Lake CPU cores for Razor Lake AX on mobile while pushing a larger iGPU.

*Specs rumored, unconfirmed by Intel

Intel has told us that Nova Lake is one of the most important desktop CPU launches for the company ever, following on the heels of the mediocre Arrow Lake rollout. Perhaps the biggest addition to the lineup is rumored to be bLLC, or big last-level cache, which is said to show up on select SKUs to counter AMD's X3D assault among the best CPUs for gaming. The company has yet to confirm that bLLC is even possible with its current packaging capabilities, though enthusiast channel VP Robert Hallock hinted to Tom's Hardware that Intel has plans to address X3D in the next generation.

The main stack is rumored to climb up to 28 cores, with two additional dual-tile SKUs that can go as high as 52 cores. The dual-tile models look like a bid for HEDT, perhaps competing with AMD's Threadripper CPUs, though it's not clear how Intel will position its dual-tile models yet.

Earlier this month, a leaked slide gave us a glimpse into Intel's launch plans for Nova Lake. The slide suggested Intel will announce the main stack (up to 28 cores) in Q4 of this year, with the chips arriving in Q1 2027. Intel will apparently follow up later in the year with the 52-core model. This aligns with what we've heard from our sources about Intel's Nova Lake rollout.

Alongside Nova Lake, Intel will introduce the new LGA1954 socket, along with the flagship Z990 chipset. We've already seen multiple Z990 motherboards in the flesh, suggesting Intel is preparing for a Nova Lake release in short order.

Intel has reversed its decision to shelve its open-source font project designed specifically with developers in mind. The font’s GitHub repository was archived earlier this week, only for the company to reportedly restore the project and potentially continue to maintain it. The cancellation came amid a wider reduction in Intel’s open-source efforts. According to Phoronix, Intel has been closing down projects where development has slowed, or the employees responsible for them have exited the company.

Introduced back in 2023, One Mono is a monospace font where each character occupies the same horizontal width. Intel carried out the development in collaboration with type design studio Frere-Jones Type and marketing agency VMLY&R. Working with low-vision and legally blind developers during the design process, live testing sessions were conducted to identify characters that could be difficult to distinguish when reading code.

“Identifying the typographically underserved low-vision developer audience, we designed the Intel One Mono typeface for maximum legibility to address developers' fatigue and eyestrain and reduce coding errors,” said Intel in its introduction.

The font was designed with several features to improve legibility, including distinctions between similar-looking letters and coding characters. For example, characters such as the lowercase “e” and uppercase “G” were given more distinctive shapes to make them easier to identify. The difference in height between uppercase and lowercase letters was also increased, along with longer ascenders and descenders to make blocks of code easier to read. Additionally, the font supports more than 200 languages using the Latin script and is available in Light, Regular, Medium, and Bold weights, along with matching italics.

As mentioned, One Mono is available under an open-source license; thus, developers are free to use and modify it. Unfortunately, the font has not witnessed any significant updates since 2024, with activity during 2025 reportedly limited to Readme updates. Thus, its archival seemed pretty obvious, especially with Intel shutting down projects that were no longer seeing active development. For now, the font has managed to avoid becoming a casualty of Intel’s open-source cleanup. While the project remains silent, its revival means the developer-focused font is not being abandoned after all.

Architectural enhancements and significantly higher clock speeds enable Apple's A20 Pro application processor (AP), used in the company's latest iPhones, to deliver not only a substantial generation-to-generation performance boost but also to outperform leading desktop CPUs from AMD and Intel by up to a whopping 32% in the single-thread Geekbench 7 benchmark, setting the record for the highest single-thread performance. While high-end PC CPUs still have more oomph for multi-threaded workloads, the tiny A20 Pro is still faster than mainstream laptop CPUs even when many threads are involved.

Fastest smartphone SoC

Apple's A20 Pro system-on-chip (SoC) delivers 4,006 points in single-thread and 11,460 points in the multi-thread Geekbench 7 benchmark, which represents a 23.3% higher ST performance and 27.1% higher MT performance compared to the immediate predecessor, the Apple A19 Pro, according to an early submission (which may or may not demonstrate performance of actual A20 Pro-based products, so take the results with a grain of salt).

The new SoC delivers the highest generation-over-generation performance improvement for Apple's smartphone processors in years and is currently the highest-performing mobile AP. Furthermore, the A20 Pro beats AMD’s 16-core Ryzen 9 9950X3D by 26% and Intel’s Core i9-14900KS by 32% in single-thread performance.

When it comes to the single-thread Geekbench 7 benchmark, Apple's A20 Pro outperforms its closest rivals — Qualcomm's Snapdragon 8 Elite Gen5 (SM8850) and Xiaomi's XRing O3 — by 31.5% - 33.7%. In fact, both SM8850 and XRing O3 perform on par with Apple's two-years-old A18 Pro. The six-core A20 Pro also beats the eight-core SM8850 by 12.2% in multi-thread workloads in Geekbench 7 and offers roughly similar multi-thread performance to the 10-core XRing O3.

Compared with other flagship smartphone processors, Apple's A20 Pro holds a commanding lead in Geekbench 7. It is 76% faster in single-thread and 48% faster in multi-thread performance than MediaTek's eight-core Dimensity 9400, while it nearly doubles the performance of Google's eight-core Tensor G5, with advantages of 99% and 96%, respectively. But the most striking gap of A20 Pro is with Huawei’s Kirin 9050 Pro: Apple's flagship is 290% faster in single-thread and 139% faster in multi-thread Geekbench 7 workloads.

A great laptop CPU

While Apple's A20 Pro continues to feature 'only' six cores like many generations before it, this time around the processor packs two 'super' desktop-class general-purpose cores running at up to 4.93 GHz, four efficiency cores running at lower clocks, and a memory interface that delivers +50% higher memory bandwidth compared to its predecessor (allegedly using a 96-bit memory I/O).

The architectural enhancements of advanced CPU cores running at nearly 5 GHz, along with a more capable memory subsystem, not only enable a massive generational performance uptick, but also allow the chip to offer unbeatable single-thread performance and massive multi-thread performance that is comparable to that of laptop CPUs, including previous-generation laptop CPUs from Apple.

Indeed, Apple's A20 Pro is 7% faster than M5, 20% faster than M4, and 43% faster than M3 in single-thread performance. Its six-core design cannot match its multi-thread performance, trailing the 10-core M5 by 39% and the 10-core M4 by 27%. Yet, it is only 5% behind the eight-core M3.

When compared to Intel's Panther Lake, the A20 Pro is 48.7% faster in single-thread performance than the flagship Core Ultra X9 388H, yet the 16-core Panther Lake processor is 63% faster in multi-thread workloads. Against lower-end Panther Lake parts, the A20 Pro is 74% – 88% faster in ST workloads and even leads the Core Ultra 5 325 and Ultra 5 332 by 3% and 64%, respectively, in multi-thread benchmarks.

The particularly striking results of Apple's A20 Pro are the 26% – 33% single-thread advantage over flagship AMD and Intel desktop CPUs, though the desktop processors remain dramatically faster in multi-thread workloads.

First 2nm smartphone SoC

When Apple transitioned to TSMC's N3B (3nm-class) process technology from N4 (4nm-class) with its A17 Pro SoC back in 2023, the new processor was barely 9.8% faster in ST and 6.8% faster than its predecessor A16 Bionic. By contrast, with its first 2nm smartphone SoC made on TSMC's N2 node, Apple offers a massive performance boost over the A19 Pro produced on N3P.

Indeed, Apple's A19 Pro packs two 'desktop-class' 'super cores' whose design is 'driven in part by increased front-end bandwidth, a new cache hierarchy, and enhanced branch prediction,' as Apple described its 'super cores' inside the M5 processor earlier this year. Such architectural enhancements obviously massively increase performance in single-thread workloads at the cost of increased die size, transistor count, and power. Apparently, N2 enabled Apple's designers to squeeze two desktop-grade CPU cores into a smartphone SoC.

Speaking of M5, it is noteworthy that A20 Pro delivers 7.1% higher single-thread performance than M5 while running at a clock speed that is 7.1% higher than that of M5, which is probably a good indicator that Apple's A19 Pro uses the same 'super cores' as M5.

While some may consider using PC-grade general-purpose CPU cores in a smartphone chip an overkill, Apple is known for using and supporting PC technologies in its mobile SoCs (NVMe, PCIe, DisplayPort-over-USB-C, hardware virtualization, etc.). Keeping in mind that Apple also uses A-series SoCs inside iPads and inexpensive laptops, it makes a great sense to have these technologies in its smartphone application processors. With desktop-grade cores inside the A20 Pro, the company greatly expands use cases of these CPUs while also solidifying their position in traditional segments that they will address in the coming quarters.

Without any doubts, Apple's transition to TSMC's N2 starts with a massive general-purpose performance increase, driven by 'fat' super cores and a memory subsystem featuring 50% more bandwidth compared to the A19 Pro. Over the next few weeks, we are also going to learn how Apple upgraded the GPU, NPU, and other aspects of the A20 Pro, and we are going to find out whether the upgrades are as impressive or incremental. In any case, so far, the A20 Pro looks very good.

Discrete graphics card shipments for desktop PCs in Q2 2026 totaled 12.5 million units, the highest number since Q1 2022 despite record-high prices and cratering shipments of desktop CPUs, according to findings from Jon Peddie Research. The result highlights a broader trend that shows that unit sales of standalone GPUs for gaming have so far remained immune to rising prices, perhaps because gamers are expecting even higher prices in the coming quarters.

The industry shipped 12.5 million standalone graphics cards for desktop PCs in the second quarter of 2026, up around 5.9% sequentially and 7.8% year-over-year. 12.5 million add-in boards (AIBs) is the highest number of graphics cards sold in one quarter since the first quarter of 2022, when the industry shipped 13.38 million AIBs.

It is particularly noteworthy that 2026 is shaping up to be better for unit sales of desktop graphics boards than 2025 despite raising prices. For the first half of 2026, 24.3 million desktop AIBs were shipped, up significantly from 20.8 million graphics cards supplied in the first half of 2026. JPR analysts also note that only around 14 million desktop PCs were sold during the quarter, which — given an unusually high 89% attach rate — largely means that the majority of AIBs shipped during the quarter were aimed at gamers buying in retail and not at PC makers.

"Defying common wisdom, high-end AIB sales spiked as prices increased," said Jon Peddie, president of JPR. "Our theory is consumers rushed to buy AIBs before the prices went any higher, as the war in Iran is driving prices up in all segments."

Having shipped about 11.25 million discrete GPUs for desktop computers in Q2 2026, Nvidia remained the undisputed leader of the market with around 90% market share. AMD controlled roughly 8% of the market, shipping about one million discrete desktop GPUs, while Intel's share increased to 2% on shipments of several hundred thousand units. Meanwhile, Jon Peddie Research notes that market share changes were negligible during the quarter: AMD’s overall AIB market share decreased by -0.16% from the previous quarter, Intel's market share increased by 0.3%, and Nvidia's market share decreased by -0.1%.

For Nvidia, the quarter was particularly good as it sold the highest quantity of discrete GPUs for desktop PCs in a single quarter since Q3 2017, when it sold approximately 11.72 million units. By contrast, sales of AMD's standalone graphics cards have been floating below or around one million units per quarter for nearly four years now, with only three quarters being exceptions (Q3 2023, Q4 2023, Q4 2024). Still, one million is higher than the around 700 thousand discrete desktop GPUs the company sold in Q2 2025.

In total, Nvidia shipped approximately 17.365 million discrete graphics processors in the second quarter: roughly 11.25 million units went to desktops, and around 6.115 million units were installed into notebook and compact PCs. Since both AMD and Intel have quietly quit the market for standalone GPUs for mobile PCs, their shipments to this market segment were essentially zero.

A Linux developer has shared a photo of their laptop using realtime visual feedback during an AMD Radeon GPU driver tuning task. Justin Schroeder (@jpschroeder) explains that “the MacBook is using its webcam to look at its screen in a mirror to improve AMD Radeon chip support in Omarchy.” Linux distro Omarchy is tailored “for the age of agents,” a field in which Schroeder is something of an expert. So, we assume the MacBook is running some kind of programming agent like Claude Code, and it is watching its own screen to assess the GPU driver tweaks it is making.

Schroeder’s quirky hack has gained many admirers. We note that the Epic Games boss, Tim Sweeney, humorously commented on this use of AI, giving him “HAL 9000 lip-reading vibes.” Of course, HAL 9000 was the increasingly unhinged superintelligent computer from Kubrick’s 2001: A Space Odyssey. In the movie, it famously read the lips of astronauts plotting to limit its operational scope.

Since the MacBook is working on itself, it must be an older Intel Mac with an AMD GPU inside. Thus, the coding agent can refine Radeon hardware support and actually benefit from the webcam’s visual feedback.

Omarchy can be a good fit for users of older Intel-based Macs due to its specialized drivers and configurations. However, this interesting flavor of Linux is headlined as a handsome Linux distro designed for the age of agents. The OS’s homepage also boasts of a lightning-fast installation, with built-in agents that can debug issues. In short, users can “vibe your way through every alteration, tweak, or trouble.”

More details about this operating system can also be found on its GitHub repository. Omarchy isn’t just for ‘vintage’ Intel Macs like Schroeder’s image shows. It is available for Apple Silicon Macs and modern x86 PCs. Moreover, it is also suitable for ‘potato PCs’ like “a 2011 ThinkPad X220 with 2GB of RAM,” according to the developers. Omarchy is distributed under the MIT license.

ASML, Intel, Samsung, and TSMC are teaming up to drive the industry transition to 6×12-inch photomasks (reticles). This shift is paramount for High-NA EUV lithography, as the larger stencil would enable printing large chips in a single pass, instead of having to stitch smaller designs together, as ASML explained in a press release this week.

This kind of collaboration between chipmakers isn't entirely unheard of, but it is rare. But when they face an industry-wide challenge, they set aside their rivalry and join forces to move the industry forward. This happened several times in recent decades, first with the failed transition to 450-mm wafers co-funded by GlobalFoundries, IBM, Intel, Samsung, TSMC, and New York State, then with the EUV transition, which was spearheaded by Intel, TSMC, and Samsung.

Higher resolution comes with a nuance

High-NA EUV lithography is a major step forward from today's Low-NA EUV tools. With a numerical aperture of 0.55, High-NA systems can achieve an 8nm single-exposure resolution, compared with 13nm for 0.33-NA EUV scanners. The higher resolution enables chipmakers to pattern smaller, denser features in a single exposure, replacing complex Low-NA EUV multipatterning schemes with a single High-NA exposure. This can reduce the number of masks and process steps, shorten manufacturing cycle times, and potentially improve pattern fidelity and yields, especially on critical layers of next-generation process technologies.

However, this improvement comes with a significant tradeoff. Conventional 0.33-NA EUV uses 4X reduction optics in both directions, which enables a 26×33 mm exposure field with standard 6×6-inch photomasks. By contrast, High-NA EUV uses 4X/8X anamorphic optics, so the same mask can only expose a 26×16.5 mm half-field, which is hardly a problem for client-oriented designs that are barely larger than 429 mm². However, large dies that fit within a conventional 26×33 mm EUV field must now be patterned using two High-NA exposures stitched together, or split into a multi-chiplet design.

Stitching is a workable near-term solution that all chipmakers, including Intel, Samsung, and TSMC, use, but it comes with multiple drawbacks. First, it reduces the throughput of ASML's Twinscan EXE:5200B scanner from up to 175 wafers per hour for half-field exposures to around 125 wafers per hour when stitching is used. Secondly, chip designers must account for the stitching boundary, which means additional design rules and reduced floor planning freedom.

Finally, the two exposures must be aligned with extreme precision so that features crossing the boundary connect properly. Even tiny alignment errors can distort lines and vias, or compromise interconnects and thus potentially create defects and lower yields. Such yield loss is very expensive in the context of large CPUs and GPUs produced using Low-NA EUV systems. If yield is lost on more expensive High-NA EUV tools, the costs will be even higher, which greatly lowers the appeal of using these scanners.

New photomasks are needed

To eliminate the need for stitching, the industry is exploring larger orthogonal 6×12-inch photomasks to compensate for anamorphic optics. By doubling the reticle dimension corresponding to High-NA's 8X reduction direction, these masks are set to restore the traditional 26×33 mm full exposure field and enable even reticle-sized dies to be patterned without stitching.

However, 6×6-inch photomasks have been an industry standard for around three decades since the 1990s. Even the transition from DUV to EUV did not change the basic mask dimensions: EUV replaced transmissive masks with reflective multilayer masks but retained the 6×6-inch substrate form factor. As a result, the adoption of 6×12-inch reticles would require the industry to change the entire mask-making, mask handling, and lithography infrastructure built around the existing format.

Mask-blank suppliers like AGC and Hoya would need new or modified equipment to produce larger substrates and deposit uniform reflective EUV multilayers across a much larger area. Mask shops would need new or modified writers and etch tools to pattern the larger masks, as well as inspection and metrology systems capable of precise characterization of the new format. Cleaning equipment, pellicles, and pellicle-mounting devices would also require modifications.

The mask handling infrastructure would have to change as well. Suppliers would need larger mask pods, while fabs and mask shops would require compatible storage, transport, and automated handling systems. At the same time, they would have to retain support for existing 6×6-inch masks since existing and future Low-NA EUV and DUV scanners will continue to use the established format.

Perhaps the biggest changes would be required from ASML. Its High-NA EUV scanners would need modifications or a redesign to accept, clamp, move, and position the substantially larger reticles with the extreme precision required for EUV lithography.

Intel, Micron, Samsung, SK hynix, TSMC, and other chipmakers planning to adopt High-NA EUV lithography would then have to qualify the new masks, scanners, and other tools for their process flows and ensure that the full-field exposure capability works as intended.

As a result, the adoption of 6×12-inch masks would require a coordinated effort and significant investments from chipmakers, ASML, mask makers, and numerous equipment and materials suppliers.

To make matters more complicated, 6×12-inch masks will not replace the existing 6×6-inch format altogether, as noted above. The industry would therefore have to manufacture, inspect, transport, store, and handle two mask formats in parallel, which will add cost and complexity to an already expensive transition.

Timeline

The transition to 6×12-inch reticles is an industry effort currently supported by ASML, Intel, Samsung, and TSMC. It is going to take years and will happen well after High-NA EUV enters high-volume manufacturing with today's 6×6-inch photomasks, as the semiconductor industry prefers to adopt new technologies gradually.

Intel already uses High-NA EUV scanner(s) for select Intel 18A layers (patterned at Fab D1X) and supports both floorplanning within the half-field and stitching; Samsung plans to introduce High-NA EUV into DRAM high-volume manufacturing by 2028, and TSMC intends to deploy the technology for advanced-node production starting in 2030. All three companies plan to start High-NA EUV adoption with 6×6-inch masks.

Intel seems to be leading the pack with 6×12-inch reticles as it has been working for three years to make them a reality, but the company remains tight-lipped about the timing of its adoption of the new photomasks. Meanwhile, the ASML-TSMC initiative targets a 6×12-inch photomask pilot line by 2031, which should provide the foundry with a platform to develop and qualify the new mask format and associated manufacturing infrastructure. The ultimate target is full lithography-system readiness for advanced-node production by 2033.

That said, 6×6-inch and 6×12-inch photomasks for High-NA EUV patterning will likely co-exist on the market at least for some time rather than undergo an abrupt transition. At the end of the day, square 6×6-inch reticles that enable High-NA EUV scanners to expose fields as large as 26×16.5 mm (or 429 mm²) should be sufficient for the vast majority of client processors produced in the coming years. Larger 6×12-inch masks will matter primarily for much bigger designs, such as high-end AI accelerators, data center CPUs, DPUs, high-end GPUs, and FPGAs, where the ability to expose a full 26×33 mm field without stitching becomes considerably more valuable.

Following an early access period that included over 60,000 participants, auto-overclocking tool Hypertune has released its Gaming Performance Engineering platform, which is built on top of Intel's Extreme Tuning Utility (XTU) SDK and developed in partnership with Intel. The company claims the utility can boost frame rates by up to 60%, though you shouldn't expect that as the norm. The tool includes automated CPU and GPU overclocking, as well as customizable Windows features, network optimization, and game-specific optimizations.

Hypertune partnered with Intel to build the tool, which the company says "evaluates each supported system individually" before optimizing rather than relying on generalized profiles. In its press release, Hypertune says it collaborated with famed overclocker SkatterBencher (Pieter Plaisier) to refine the software. We've reached out to Plaisier to confirm their involvement.

Automated tuning programs usually don't work as well as advertised, and we haven't had the chance to test Hypertune ourselves yet. Especially on more recent hardware, expect performance gains to be minor. Hypertune shared some of its internal benchmarks to back up the claim, showcasing the actual test systems it used, the numbers it gathered, and what each step of Hypertune contributed to the performance increase.

Hypertune tested two systems: one with a Core Ultra 9 285K and an RTX 5090, and another with a Core i7-14700K and an RTX 3080. For the 285K system, the team saw an 18.9% improvement in Homeworld 3 and a 28.2% improvement in Tomb Raider. For the 14700K system, the boost was up to 9.8% in Rainbow Six Siege and 4.3% in Marvel Rivals.

Notably, these results are with Hypertune's Game Hub disabled. Game Hub automatically applies a graphics settings profile to select games, leading to massive increases in performance. Naturally, tweaking your own graphics settings in the same way leads to the same result.

In Homeworld 3, you can see how each step in the process impacted performance, with CPU tunning contributing the single biggest increase in performance. As shown by Marvel Rivals in Hypertune's data, some games will see little to no benefit from Hypertune, though select titles with certain hardware may see a significant performance increase. In this case, the Core Ultra 9 285K has plenty of room for overclocking, and Homeworld 3 is particularly sensitive to the CPU, so the uplift makes sense.

Elsewhere, the gains aren't as pronounced. In Rainbow Six Siege, you can see that Hypertune contributed about a 9.8% jump in performance, though the vast majority of the improvement comes through Game Hub, where Hypertune changes in-game settings.

In a press release, Hypertune founder Austin Copeland wrote that the team was "not trying to build a tool for overclockers," suggesting it's aimed toward users who may not know about specific settings (i.e., the Balanced power plan on dual-CCD X3D CPUs, or HAGS for DLSS Frame Generation). Copeland was previously a coach for eSports organization TSM, coaching Valorant teams under the name "Apex."

Hypertune works through Intel's XTU SDK, and the company says its optimizations are non-destructive and fully reversible. The software is mainly targeted toward competitive titles (naturally, given Copeland's background), but it can apply optimizations globally across the system. Hypertune says it's safe to use with anti-cheat software, including Riot Vanguard, Easy Anti-Cheat, and BattlEye.

Although there are plenty of free tools that claim to optimize your system, Hypertune isn't among them. It's a subscription service, available for either $9.99 per month or $59.99 per year. In addition to software, Hypertune offers its "expert tuning" service for $80, where a technician will remote into your machine and manually tune it. On the subscription front, Hypertune offers a 7-day free trial.

Hypertune looks like one of the more robust automated overclocking tools we've seen, but it's worth highlighting that, in most cases, these tools don't do anything you can't accomplish yourself. If you're looking for a starting point, make sure to read our guides on how to overclock your graphics card and how to overclock your CPU.

Intel is reportedly set to hike CPU prices by 10%, according to a new Digitimes report. Citing supply chain sources, the outlet says the increase follows two others, one in the first quarter of 2026 and another in July, among some server and client CPUs. Notably, the sources didn't say which products the price increase applies to, though presumably, the increases would come through Intel's mobile and server businesses before desktop client. Citing industry sources, DigiTimes also reports that Intel is set to launch "major annual products" in March 2027, with AMD following up with launches of its own between June and July.

The increases come on the back of Intel seeking higher gross margins for its products as the PC market shrinks. This is a story we've heard directly from Intel in the past. In its most recent earnings call in July, Intel chief financial officer David Zinsner attributed a 13% YoY increase in Intel's client revenue to higher average selling price, not a higher volume of sales.

Although the Digitimes report doesn't clarify which products will see a price increase, server and mobile seem like the most likely candidates. Intel's most recent Panther Lake calls for high-speed LPDDR5X-7467 memory as a minimum, and last-gen Lunar Lake CPUs have on-package memory. Naturally, higher memory prices put more pressure on fully built systems like laptops more so than socketed, standalone desktop processors.

On the server end, there's been an unprecedented increase in demand for server CPUs on the back of agentic AI workloads. That demand led to several consecutive records for Intel's share price, even without any major product announcements. Earlier in the year, Wall Street estimated the server CPU market would rise to around $120 billion by 2030 (currently around $30 billion). Now, those projections go up to as high as $220 billion.

According to the report, Intel is set to launch a major new annual product in March 2027, followed by AMD between June and July. Last week, a leaked Intel roadmap showed the company's next-gen Nova Lake desktop CPUs entering mass production in Q4 2026 with a release in Q1 2027, lining up with DigiTimes' report.

Although the timelines line up, the rumor mill has suggested an early Q1 launch for Nova Lake. It's worth noting that the DigiTimes report doesn't make mention of which product Intel will launch in March. This year, for instance, Intel launched its Xeon 600 CPUs for HEDT in March.

Perhaps more interesting is the AMD timeline. We already know of one major AMD product launch in the second half of 2027, which is Venice-X. Those are Zen 6 server CPUs with AMD's 3D V-Cache, packing up to 1,152 MB of L3 cache on the chip. Otherwise, that timeframe seems to point to AMD's next-gen desktop CPUs with the Zen 6 architecture, codenamed Olympic Ridge.

AMD launched its Venice server CPUs earlier this year, the first sporting the Zen 6 architecture. We haven't heard anything official about Zen 6 in the desktop yet. That's strange given AMD's last several releases. There was about a two-year gap between Zen 3 and Zen 4, as well as Zen 4 and Zen 5, on desktop. We've just crossed the two-year mark for Zen 5, so assuming AMD keeps a similar launch cadence, we'd expect to hear something sooner than June or July or next year.

That same explosive demand in server CPUs could have changed AMD's launch plans, however. Given that we haven't heard anything official about Olympic Ridge at this point, a launch in June or July isn't out of the question.

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.

One million High-NA wafers

Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.

Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.

Sticking to stitching

Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.

Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.

6×12 mask effort progressing

To avoid using stitching, the industry — led by Intel — plans to shift to larger 6×12 masks, which will enable a 26×33 mm full field in one exposure. While this looks easy on paper, make the mask twice as long, changing the mask represents an enormous ecosystem change.

Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.

It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.

Sales of discrete graphics processors for consumer PCs were up both sequentially and year-over-year in the second quarter despite soaring prices caused by component shortages, according to a newly released report by Jon Peddie Research. Although PC CPU shipments dropped in Q2 2026 year-over-year amid seasonality and shortages, sales of standalone graphics processors for consumer computers were up 12.2% sequentially and 14.1% YoY, the best market dynamics in some time.

Sales of graphics processing units for consumer PCs — which include integrated and standalone GPUs for desktops and laptops — totaled 75.5 million in the second quarter of 2026, up 10.4% quarter-over-quarter and 1.1% year-over-year, primarily driven by notebooks. This happened as the consumer CPU market contracted by 1.1% YoY amid a massive sequential drop in desktop CPU shipments and a significant rise in mobile CPUs shipments. Desktop GPU shipments declined by 4% quarter-over-quarter, while notebook GPU shipments surged by 16.8%, JPR claims.

But despite declining desktop PC unit shipments and modest growth in notebooks, unit shipments of discrete GPUs increased by 12.2% sequentially and 14.1% year-over-year in Q2 2026, according to JPR data. Jon Peddie Research does not publish absolute numbers of standalone graphics processors shipped in the second quarter, but our estimate is that around 20 million discrete GPUs were sold by AMD, Intel, and Nvidia in Q2, based on attach rates and Nvidia's market share and dynamics.

The results indicate that demand for PCs with discrete graphics remained remarkably resilient despite soaring component prices and slowing demand for desktop PCs. However, JPR's shipment data does not reveal whether the increase was primarily driven by gamers buying graphics cards, stronger demand for gaming notebooks, or other factors.

"The second quarter is typically down compared to the previous quarter," said Dr. Jon Peddie, president of Jon Peddie Research. "This quarter, discrete GPUs increased by 12.2%, even while a global memory crisis sent component prices soaring, driven by a mix of supply-side positioning, artificial demand shocks, and localized market dynamics."

Jon Peddie Research has yet to publish its complete desktop AIB report, which is expected later this month and will include market shares for AMD, Intel, and Nvidia; yet it is safe to say that the latter has maintained its undisputed leadership.

As for the overall consumer PC GPU market, Intel retained its leadership with a 56% market share as it increased shipments of consumer CPUs in Q2 2026. Nvidia came second with 23%, which is not bad at all considering that it only ships discrete GPUs. AMD came third with 21% share, up significantly from 14% in the same quarter a year ago, as it managed to gain seven percentage points of the consumer GPU market YoY amid growing sales of its consumer CPUs.

Intel's upcoming Core Ultra 400-series 'Nova Lake-S' CPU platform promises to be the company's biggest desktop launch in years, with range-topping processor offering up to 52 cores and gaming processors featuring up to 288 MB of bLLC cache, at least according to the rumor mill. Intel is reportedly on track to start mass production of its Nova Lake-S CPUs in the fourth quarter of 2026, according to a slide published by @wxnod. However, only the 28-core version will launch in the first quarter of 2027, with the 52-core model arriving later in the year, as we covered out of this year's Computex.

When initial leaks and roadmap disclosures about Intel's Nova Lake-S surfaced across 2025, the projected production schedule placed mass production in Q4 2026, so the new slide confirms that plan. Meanwhile, the actual CPU roll-out will be somewhat different to what Intel is used to as the company only intends to release unlocked 28-core SKU (or SKUs) in Q1 2027 and push the release of flagship models allegedly using two compute tiles featuring up to 52 cores to sometimes later in 2027. Some rumors pointing to a timeframe between late May and September, 2027. Normally, Intel launches flagship and unlocked models first. However, reports suggest the 52-core model will fit in a different class above a typical flagship, primarily targeting the HEDT crowd.

The slide revealed by the blogger does not look like an official Intel roadmap or an Intel presentation slide. A more plausible explanation is that the slide comes from a motherboard maker's presentation (or one of Intel's OEM partners), which compiled information the manufacturer got from Intel, which means that while it is most likely accurate, it is not final.

Intel's Core Ultra 400-series 'Nova Lake-S' CPUs will reportedly use up to 16 all-new high-performance Coyote Cove cores with 16MB of L2 cache, up to 32 energy-efficient Arctic Wolf cores, and up to four low-power Arctic Wolf cores, according to various leaks and the slide published by @wxnod. Even though each pair of Coyote Cove cores will reportedly share a 2 MB L2 cache, which will inevitably affect single-thread performance, Intel has an ace up its sleeve in the form of bLLC (big Last Level Cache), which will apparently scale to 288 MB to offer unbeatable performance in memory bandwidth-hungry applications, if media reports are correct. bLCC is apparently Intel's plan to fight back against AMD's X3D CPUs, which top the charts among the best CPUs for gaming.

The highest-end Core Ultra 9 400-series processors are expected to pack up to 52 cores using two compute tiles, whereas Core Ultra 7 400-series models are projected to feature up to 44 cores using two compute tiles, though exact configurations are currently unknown. Meanwhile, CPUs with two compute chiplets will reportedly consume up to 474W of power and will require motherboards featuring three 12V EPS power plugs.

On the I/O side of matters Intel's Nova Lake processors will reportedly feature a dual-channel DDR5 memory subsystem supporting up to DDR5-8000 modules as well as provide up to 24 PCIe 5.0 lanes directly from the CPU, including 16 lanes for graphics that can be split into two x8 or four x4 connections, plus two x4 links for SSDs.

Intel's new Core Ultra 400-series 'Nova Lake-S' processors for desktops will require Intel's new 900-series chipsets as well as will use an LGA1954 socket, according to leaks. Intel reportedly intends to keep LGA1954 around for a longer time than it usually does with its sockets, ensuring an upgrade path for years to come. We've already seen Z990 motherboards sporting the LGA1954 socket in the flesh.

Speaking of years to come, the slide lists Razor Lake and Hammer Lake processors that will succeed Nova Lake-S sometime after the fourth quarter of 2027. The slide does not provide technical details about either family, and we can only wonder whether Razor Lake corresponds to Core Ultra 500-series and Hammer Lake belongs to the Core Ultra 600-series, or both will be a part of one CPU family.

Intel notified its employees last week that it would no longer title its top scientists, researchers, and developers as 'Fellows,' but will call them 'distinguished engineers,' a change that will not affect their compensation but which means a lot more than a simple formality. The new designation reflects the company's new 'standard of technical leadership' that combines deep expertise with strategic vision and 'measurable tactical progress,' reports OregonLive.

Under the new hierarchy, Fellows become Distinguished Engineers, while Senior Fellows become Senior Distinguished Engineers. Intel CTO Pushkar Ranade told employees that the move represents more than a simple renaming and establishes a new standard for technical leadership.

"The future of Intel will be determined by leaders who combine deep domain expertise with outstanding problem-solving ability, creative innovation with disciplined execution, and an expansive and strategic vision with measurable tactical progress," the Intel CTO reportedly wrote.

Interestingly, despite the fact that at least a dozen semiconductor companies — including AMD, ASML, Applied Materials, Arm, Broadcom, IBM, Nvidia, Micron, Texas Instruments, Qualcomm, and TSMC — have Fellows, Ranade told Intel employees that the new titles are more consistent with terminology used elsewhere in the technology industry. While Apple, Google, IBM, and Microsoft have Distinguished Engineers, at Google, IBM, and Microsoft, Fellows are above Distinguished Engineers.

Intel established the Fellow title in 1980 to recognize employees with a sustained record of exceptional technical accomplishments. The designation had deliberately academic roots because scientific societies and then engineering organizations have long used 'Fellow' for distinguished members, for example, the Fellow of the Royal Society (FRS) or IEEE Fellow. So, by the time semiconductor companies, such as IBM, TI, or Intel, were developing formal technical career ladders, Fellow already carried a very specific implication: an engineer recognized by their peers as one of the leading authorities in the field.

Across semiconductor companies, the Fellow rank typically carries compensation, resources, and influence equivalent to a vice president (VP) or senior vice president (SVP), so that top architects and device physicists can shape company strategy without moving into people management (yet, Fellows did not work alone for obvious reasons). It is unclear whether Distinguished Engineers will now have similar resources and influence as Intel's VPs and SVPs that report to the CEO. Furthermore, at Intel, the Fellow (or senior Fellow) title reflected Intel's position as a semiconductor research powerhouse as well as its emphasis on long-term technology development.

The most notable people to hold the Intel Fellow rank title include distinguished specialists in microprocessor architecture, process scaling, high-speed interconnects, and silicon physics, including Marcian 'Ted' Hoff (the inventor of the Intel 4004 processor), Justin Rattner (for his work on massively parallel supercomputers), Mark Bohr (for leading Intel process technology development and fundamental work on things like strained silicon, hafnium, high-K metal gate, FinFET, etc.), Yan Borodovsky (for leading development and adoption of optical lithography extensions, immersion 193nm ArF lithography, and multi-patterning, just to name a few), and Ajay Bhatt (for leading development of USB, AGP, and PCIe). Perhaps the most unexpected Intel Fellow is Boris Babayan, who is primarily known as the father of Soviet supercomputing and the creator of the Elbrus VLIW CPU architecture. He became an Intel Fellow focused on optimizing binary translation and advanced compilers in November 2004, months after joining Intel.

All in all, Fellows historically had a very specific organizational and status value at Intel, as in many cases they have been the key people to solve Intel's strategic and tactical technical challenges while not being in a formal management role. From now on, Intel wants its Distinguished Engineers to be accountable for business decisions and essentially become managers.

The biggest question about renaming Fellows to Distinguished Engineers is whether this is done in a bid to further flatten the organization (after all, Intel got rid of 250 VPs out of 450, according to Intel's CFO), or is it a deliberate move away from the old research lab model, where Fellow signified scientific stature and long-horizon research, toward engineers whose status depends on products, execution and measurable business impact. For now, we do not have any answers to this question.

Hybrid bonding, the copper-to-copper joining technique that replaces solder microbumps in 3D chip stacks, is in high-volume production on logic chips and has just been postponed for use with memory. TSMC has scaled its SoIC bond pitch from 9 microns to 6 and laid out a path to 4.5 by 2029; Intel began shipping Foveros Direct hybrid bonding in its Clearwater Forest server CPU in the first half of 2026, and AMD has used the technology in volume since the first 3D V-Cache parts. However, a JEDEC decision earlier this year to raise the HBM stack-height limit lets HBM4 stay on the less sophisticated and expense microbump technology, deferring hybrid bonding's arrival in high-bandwidth memory, and is now set to debut in HBM4E and HBM5 at the end of the decade.

The technique works by polishing two dies flat, then bonding their copper pads and surrounding dielectric directly under heat and pressure, with no solder bump in between. Because there’s no bump to collapse, the connections can be packed far tighter. AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking, and figures presented at TSMC's 2026 technology symposium put face-to-face hybrid bonding at around 14,000 signals per square millimeter against roughly 1,500 for face-to-back through-silicon-via stacking.

Wafer-to-wafer, die-to-wafer, and throughput

Microbumps have historically run at pitches around 40 microns, tightening toward 10 for the latest memory. Hybrid bonding, however, starts where microbumps end and keeps scaling: the leading edge is at 6 microns now, with 4.5- and 3-micron generations in development and sub-micron pitches demonstrated in research. Each step down multiplies the number of vertical connections between stacked dies, allowing a cache die or a compute tile to behave as if it were part of the chip rather than a separate component wired across a package.

The method is split into two different approaches: wafer-to-wafer and die-to-wafer. Wafer-to-wafer bonding joins two full patterned wafers face-to-face and dices them afterward, which allows the tightest pitch and fastest production because alignment happens once at the wafer scale. Imec and EV Group demonstrated a 200-nanometer wafer-to-wafer pitch with post-bond overlay below 40 nanometers at ECTC in May. The constraint here is that both wafers must carry identically sized dies, and every die gets bonded, including defective ones, so a single bad die on either wafer ruins the pair.

In contrast, die-to-wafer bonding places individual, pre-tested dies onto a wafer — which is what chiplet and HBM stacks require — because it allows known-good-die selection and the mixing of different die sizes and process nodes. There’s a penalty in terms of throughput with die-to-wafer as each die is picked, aligned, and placed in sequence rather than in one wafer-scale step.

The best die-to-wafer pitch shown at ECTC 2026, from CEA-Leti, was 1 micron, roughly five times looser than the wafer-to-wafer record. Because the dies are placed one at a time, the speed the bonder runs at sets the limit on how many chips it can produce. Applied Materials and Besi cite around 1,600 die placements per hour on the Kinex platform, and Besi's Chameo bonders are rated near 2,000 chips per hour, with the next generation aiming for 50-nanometer placement accuracy to reach finer pitches.

Hybrid bonding is difficult to achieve, as two surfaces have to be almost perfectly flat and clean. The dielectric holds on contact through van der Waals forces, so the polished surface can vary by no more than around 0.2 nanometers, and the copper pads have to sit a few nanometers below it, close enough that they swell into contact when the stack is heated to 200 to 300℃. A single particle smaller than a micron holds the surfaces apart and leaves a gap spanning many pads at once. So keeping the wafer clean and flat through the polishing step (known as chemical-mechanical planarization) is critical for good yields.

TSMC SoIC and Intel Foveros Direct

In terms of who’s leading hybrid bonding, TSMC’s System on Integrated Chips (SoIC) platform leads in terms of volume. At its 2026 North American Technology Symposium, the company laid out a pitch roadmap moving from 9 microns in 2023 to 6 microns in 2025 and 4.5 microns by 2029, with second-gen SoIC adding face-to-face bonding on top of the face-to-back stacking that the first generation supported. The node-stacking roadmap runs in parallel, from N3P-on-N4 today toward N2P-on-N2P by 2028 and A14-on-A14 by 2029.

With SoIC, the hybrid-bonded stack is built first as a vertical block, then placed into a CoWoS module alongside HBM on a silicon interposer, a combination the industry calls 3.5D. AMD's MI300 is the reference case, stacking compute and I/O dies by hybrid bonding before the assembly is mounted in CoWoS with its memory. SoIC handles the front-end vertical density; CoWoS handles the back-end lateral integration with memory.

Capacity is slowly growing, with TSMC building out its Chiayi AP7 site as its largest advanced-packaging campus. Output is targeted for 2026, and analysts at TrendForce have estimated SoIC capacity roughly doubling year on year from a few thousand wafers a month in 2024. Customers include AMD, whose 3D V-Cache and MI300 accelerators were the first volume SoIC products, and the Broadcom-built Fujitsu Monaka CPU.

Meanwhile, Intel's hybrid-bonding implementation, Foveros Direct, reached high volume with Clearwater Forest, the Xeon 6+ server processor built on the 18A node and demo’d at MWC back in March. The design uses a 9-micron copper-to-copper pitch to bond compute and I/O tiles onto base tiles that act as an active interposer, and Intel has described a second generation targeting a 3-micron pitch. Enabling that on a leading-edge logic node required a dedicated process variant, 18A-PT, which adds the through-silicon vias (TSVs) and bonding support that standard 18A doesn’t carry. The shift from Intel's earlier Foveros, which used solder microbumps across the Ponte Vecchio GPU's chiplets, to direct copper bonding is a generational change now playing out across its server offerings.

The unexpected HBM delay

The widely held assumption was that HBM, the stacked DRAM that sits beside every AI accelerator, would be hybrid bonding's largest market by volume. That changed back in January when JEDEC raised the HBM package height limit from 720 to 775 microns, and the extra room means 16-high HBM4 stacks can be assembled with microbumps after all. With HBM4 pad pitch at 10 microns, reporting from SemiEngineering noted that moving to hybrid bonding at that pitch wouldn’t yet make economic sense.

SK hynix has reflected that logic in its own planning, reportedly sticking with advanced mass-reflow molded underfill for 16-high HBM4 while keeping hybrid bonding as a backup and continuing to validate 12-high hybrid-bonded samples for later generations. The company demonstrated a 16-layer HBM4 sample at CES 2026, built without the all-hybrid bonding many expected the generation to require. The result pushes hybrid bonding's HBM debut toward HBM4E and HBM5, expected around 2027 to the end of the decade, where taller stacks and tighter pitches finally make the older bonding methods run out of room.

Meanwhile, the memory makers are building the packaging capacity regardless. SK hynix is investing $3.87 billion in an advanced-packaging plant in Indiana, with production targeted for 2028, and Micron broke ground on a $7 billion HBM advanced-packaging facility in Singapore early last year, with output expected around 2027. Those plants are sized for the volumes hybrid bonding will eventually carry, even as the first HBM4 generation ships on the older interconnect, meaning the equipment commitments are running ahead of the technology's confirmed deployment date in memory.

Samsung is doing the same thing from the memory side. Its SAINT packaging family includes SAINT-D, which stacks DRAM directly on a logic die, and the company has discussed a bufferless HBM4 design that removes the separate base die, with custom HBM logic dies reportedly moving to its 2nm foundry process for 2027 samples. At GTC in March, Samsung claimed hybrid bonding cuts thermal resistance by more than 20% against thermocompression bonding.

Another drag on the timeline is intellectual property. Adeia, which holds a large portfolio of bonding patents, sued AMD last year, alleging that the hybrid bonding behind 3D V-Cache infringes 10 of its patents.

China is pursuing the technique as a way around its lack of access to cutting-edge lithography. With SMIC limited to 14nm-class production and cut off from next-gen EUV, domestic researchers have identified 3D hybrid bonding as a route to competitive performance by stacking older logic and DRAM, with public claims of 14nm parts paired with domestic DRAM aimed at rivaling far newer GPUs. Given that it’s China we’re talking about here, those claims remain claims, and no foundry has demonstrated mass production of hybrid-bonded logic memory in China.

A scramble for tools

In terms of tooling, Applied Materials and Besi, partners on hybrid-bonding equipment since 2020, launched their Kinex die-to-wafer bonding system late last year, billed as the first fully integrated die-to-wafer hybrid bonder combining surface preparation, bonding, and metrology. Applied Materials has taken an equity stake in Besi, and reports from March placed Besi at the center of takeover interest from both Lam Research and Applied Materials, an indication of how important the bonding-tool market has become as logic adoption ramps and memory adoption is staged behind it.

Analyst tracking put Besi’s hybrid-bonding revenue on a path toward roughly €476 million by 2026, up from about €36 million in 2023, with second-half 2025 orders rising more than 60% against the first half on early HBM4 production-line bookings. Competing tool vendors are moving in alongside it: ASMPT has partnered with EV Group on hybrid bonding, and SK hynix is working with Hanwha Semitech on bonders targeting a commercial HBM launch in 2027. The sheer scale of this equipment build-out is a clear demonstration that the industry is treating hybrid bonding as an inevitability, even where the products that’ll use it are still years out.

Hybrid bonding is already in volume production, but its capability is outpacing its adoption. TSMC offers 6-micron pitch while its newest disclosed customer ships at 9; Intel ships at 9 with 3 on the roadmap; and the memory market that was meant to consume it in quantity has bought itself one more generation on microbumps. Two things will show where it goes next — whether any leading logic product drops below 9 microns in volume, and whether HBM4E marks hybrid bonding's first real use in memory before the end of the decade.

Intel's confidence in its 14A (1.4nm-class) fabrication process is rising as defect density drops. The company's own design teams are at work developing products that will use the technology, while external customers are now asking about 14A volumes Intel can get them, according to David Zinsner, chief financial officer of Intel, who spoke at Deustche Bank's 2026 Technology Conference. The CFO went as far as saying that 14A is Intel's best process since 22nm technology from the 2010's. But while the comment is optimistic, there is a caveat.

"When you look at the defect density, 14A is tracking better than the target curve we had for 14A," Zinsner said at Deutsche Bank's 2026 Technology Conference. "It is also doing better than any of the previous nodes in terms of how quickly we are bringing down the defects. In fact, we have not seen this performance since 22nm, which is arguably one of the best nodes Intel has ever put out."

Intel intends to begin risk production of its own products on 14A fabrication process in the second half of 2027 and then initiate its high-volume manufacturing in 2028, so 14A is two years away from mass production. So, what Intel's CFO said at the conference is that at this point in 14A's development, its defect reduction trajectory looks at least as healthy as the trajectory of the company's exceptionally successful 22nm process at a comparable point in its development (i.e., in 2010). There are a couple of catches with such phrasing, though. Firstly, the defect density on 14A now is not necessarily equivalent to a defect density on 22nm two years away from mass production. Secondly, due to advances of wafer processing and inspection equipment, what Intel counts as a defect now may not be the same thing as what it counted as a defect 16 years ago. Furthermore, defect density itself does not directly equal product yield.

Intel's 22nm was the company's first manufacturing process to rely on FinFET transistors and at the time was the most advanced process technology in the world; the rest of the industry moved to FinFET devices only with their 14nm and 16nm-class nodes in 2014 and 2015. By contrast, 14A will use second-generation gate-all-around (GAA) RibbonFET transistors, second-generation backside power delivery called PowerDirect, and will be able to use High-NA EUV lithography due to extremely complex patterning. Keeping all of that in mind, Intel's claim that 14A defect density reduction is progressing unusually well this far ahead of HVM is certainly good news.

Meanwhile, comparing 14A to 22nm's successors should be quite comforting for Intel as 14nm mass production was delayed by a year due to insufficient yield, the first-generation 10nm node was a failure, 20A was cancelled, 18A defect density was high even as it hit HVM milestone, while the company did not share almost any information about the progress of its Intel 4 and Intel 3 nodes.

There are good signs for 14A though: external customers are already developing products for this node, whereas the interest from external customers is now practical rather than theoretical.

"We are now seeing demand from our internal customers on 14A [and] they are actually probably the most cynical bunch out of anybody," Zinsner said. "The fact that they are now designing products on 14A was a good confidence boost for us as well. Then, engagements with customers externally, from a foundry perspective has significantly increased. Lip-Bu and the team are now meeting on weekly basis with customers. They are moving away from just looking at data to thinking about 'how much capacity can I get?' 'what does that supply look like?' So, we are now at a point where we have conviction around customers on 14A externally as well."

Intel initiated mass production of its 22nm-based Ivy Bridge processors in late 2011 and early 2012 and released them commercially in late April 2012. The product was highly successful (though overclockers did not like it because of inefficient thermal interface material between the die and integrated heatspreader), and 22nm fabrication technology served the company for many years, first for CPUs in 2012 through 2016, then for other products. Intel's 14A also promises to be a long-lasting node for Intel.

Glass-core substrates, the replacement for organic chip packaging that Intel promised in September 2023 with more than $1 billion behind it, are now in final qualification. However, the product is still not in a single commercial product. SKC, a material manufacturer and chemical affiliate of the SK Group, said on its July 27 earnings call that embedded glass substrate samples from its Absolics plant in Covington, Georgia, are undergoing package-level reliability evaluation in Taiwan, with results possible before year-end.

Samsung Electro-Mechanics formalized a 482.1 billion won ($310 million) glass-core joint venture with Sumitomo Chemical's Dongwoo Fine-Chem on July 2, targeting first production in the second half of 2027. Intel, which started the race, has shifted to licensing its patents and showing demo vehicles, with its own deployment now pointed at around 2030. However, and rather predictably, every timeline in the segment has slipped. Absolics originally planned mass production for the first half of 2024, and reported claims that AMD would adopt glass substrates for CPUs between 2025 and 2026 have come and gone unfulfilled.

Why glass?

The technical case for glass core substrates leans heavily on numbers Intel published a while back, such as 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion. Glass cores can be tuned to a thermal expansion coefficient of roughly 3 to 10 ppm per degree Celsius against silicon's 2.6, which cuts warpage by about half compared with organic cores, and rectangular panels in the emerging 510mm x 515mm format use more than 75% of their area for large die against roughly 50% for round 300mm wafers. Through-glass vias have been demonstrated at six microns in diameter with aspect ratios beyond 15:1 at ECTC 2025, and Georgia Tech has shown stacked glass running at 220 GHz with 0.3 dB of loss.

Glass also chips and cracks at the edges during drilling and dicing, and MIT Technology Review reported in March that early Absolics production runs broke hundreds of panels every couple of days during early testing days. Edge-coating work has cut measured edge stress from 95 MPa to 49 MPa, and low-temperature dielectrics that cure below 180°C have been developed to reduce thermal stress during build-up, but metallizing vias below 10 microns and holding nanometer-scale flatness across half-meter panels remain open manufacturing problems.

Intel's program

Intel demonstrated a working system booting Windows on a glass-core substrate in early 2025, and Rahul Manepalli, Intel's VP of module engineering, told MIT Technology Review that the benefits of glass cores are "undeniable" and that Intel wants "to be one of the first ones who do it." The commercial plan around that engineering has changed shape, however. DigiTimes reported in late July that Intel is in early-stage talks with Chinese cover-glass maker Lens Technology about a packaging partnership, but there has been no solid agreement made to date.

At NEPCON Japan in January, Intel Foundry showed its first thick-core glass substrate with two EMIB bridge dies embedded directly in the glass: a 78mm x 77mm package with two 800-micron-class glass layers, 10 redistribution layers on each side, and around 1,716 mm2 of silicon on top, roughly two full reticles, with no micro-cracking reported in testing.

There’s currently no production time to this, however, with TrendForce placing Intel’s commercialization somewhere around 2030, alongside co-packaged optics prototypes built on glass at its Rio Rancho, New Mexico site. Meanwhile, Amkor, Intel's packaging partner on the optics work, put commercialization within three years at an industry event in Seoul in April.

Korea aiming for 2027

Samsung Electro-Mechanics moved its glass program from advanced R&D into a business-execution unit in February and has been sampling from a pilot line at its Sejong plant since late 2024. The GLASEM joint venture announced on July 2 splits ownership: 66% to Samsung Electro-Mechanics and 34% to Dongwoo Fine-Chem, with site production in Pyeongtaek, and targets an operating plant in the second half of 2027, with the joint venture making the drilled and metallized glass core that feeds Samsung's substrate line. Korean industry reporting says samples have gone to AMD and Broadcom, and also puts Samsung's overall glass maturity at 40 out of 100, a gap between marketing dates and process readiness worth keeping in mind.

Absolics' $600 million plant in Covington, Georgia, backed by $75 million in CHIPS Act funding plus a further $100 million through the government's advanced packaging R&D program with Georgia Tech, has a Phase 1 capacity of 12,000 m² of substrate per year, enough for roughly two to three million H100-sized packages. The company produced mass-production samples in the first quarter, began customer qualification that reportedly includes AMD and AWS, and is targeting mass production by the end of 2026. LG Innotek runs a third Korean program from its Gumi plant, with prototypes delivered in 2024 and production targeted for 2027 to 2028.

TSMC and Japan

TSMC's CoPoS line in Chiayi, built around 310mm x 310mm rectangular panels, received tools in February, completed its pilot line around June, and is aiming for pilot production in 2027, with mass production in the second half of 2028. Equipment supplier SCHMID has described glass integration in that platform as under review, not committed, and TrendForce puts TSMC's commercial-scale glass-core production after 2030, meaning that the industry's biggest packaging operation is going panel-level first and glass later, if at all. TSMC revived glass substrate research a couple of years ago after earlier deprioritizing it, reportedly under pressure from Nvidia, whose accelerator packages are the main thing outgrowing current packaging.

Japan’s Dai Nippon Printing began phased operation of a TGV glass-core pilot line at its Kuki plant in Saitama in December 2025 on 510mm x 515mm panels, with sample shipments from early 2026 and full mass production targeted for fiscal 2028. Toppan's pilot line for glass cores and interposers at its Ishikawa plant was scheduled for commissioning in July, and Nippon Electric Glass has scaled its ceramic-reinforced GC Core panel to 515mm x 510mm at 1mm thickness. Rapidus is studying panel-level packaging on 600mm x 600mm glass as part of its 2nm program, with viability put at the late 2020s. China has its own entrants, led by display maker BOE, whose pilot line is sampling.

TrendForce estimates Nvidia's Rubin Ultra package at roughly 7,470 mm², about nine reticles' worth of silicon and memory, against around 2,739 mm² for Blackwell, and CoWoS interposer wafers cost on the order of $10,000 each, comparable to a processed 7nm wafer.

Organic substrates warp and lose dimensional stability at those sizes, and round interposer wafers waste a growing share of their area, which is what glass panels are meant to fix. SEMI's first dedicated market report on glass cores, published in May with Global Net, projects initial production around 2028 in select high-performance applications and a 67.2% compound annual growth rate from 2028 to 2040, while Yole puts the advanced IC substrate market at $31 billion by 2030 with glass cores among the drivers.

At the moment, no production design exists, and all customers that have been named or otherwise attached to the tech, including AMD, Broadcom, AWS, and Nvidia, come from wider industry reporting. Nothing has been confirmed officially. As for whether we might see more substantial progress next year, Absolics will need to publish some solid package-level reliability results by the end of this year, or a first officially named customer at any of the Korean manufacturers. We also need to hear from TSMC on whether glass cores will go into CoPoS or remain under review into the 2030s.

Intel's Wildcat Lake is unassuming, launching with the message that it was a cutting-edge alternative to the MacBook Neo with Intel's latest node and some trimmings around the edges. Although Wildcat Lake is, indeed, a budget part with major concessions to reach a market increasingly pushed to the side by powerful PC hardware, it also comes with a major innovation: UCIe.

The Universal Chiplet Interconnect Express (UCIe) specification first debuted in 2022, coincidentally around the time that planning around Wildcat Lake began. Both AMD and Intel have rallied behind UCIe as an open interconnect communications standard, though they've primarily relied on their own chiplet communication technology like AMD's Infinity Fabric. In Wildcat Lake, Intel leveraged UCIe to reduce cost. Further, it was a key technology that allowed Wildcat Lake to exist in the first place.

Opening the Hot Chips 2026 presentation, Intel's Lance Hacking, lead engineer on Wildcat Lake, said the company had the choice between a monolithic design or a basic, low-cost Multi-Chip Package (MCP). Intel has Foveros for advanced 2.5D and 3D packaging, but for a budget part like Wildcat Lake, that wasn't an option.

Choosing to leverage UCIe over an MCP design shaped the Wildcat Lake we have today, setting a roadmap for where Intel could cut compute to save cost and in areas where it would need to optimize to fit the necessary communication channels for the two chiplets.

UCIe integration in Intel Wildcat Lake

As Hacking explained during his presentation, budget parts usually involve an N-1 design. You leverage older IP, trim around the edges to improve the economics of yields, and repackage it as a mainstream part. Wildcat Lake is different in that regard. It's taking Intel's latest, most advanced, and most expensive IP for compute and applying it to the budget domain.

With 18A at the center of the compute and ISMC's N6 handling the I/O die, Intel decided to make an MCP, which comes with some considerations. Advanced packaging allows designers to spend less die space on interconnects and use less power. With UCIe, Wildcat Lake's interconnect is 70% larger than that on Panther Lake, and even then, Intel says the change was worth it from a cost perspective.

Outside of space, power was the primary concern with using UCIe. Battery life, especially for a budget part meant to handle lighter workloads, is extremely important, and UCIe brings increased power demands. UCIe die-to-die is packetized, which led to a challenging design point, particularly around the display.

Intel says that idle systems without panel self-refresh were the "biggest power concern," as display signals need to cross the UCIe connection. To address the issue, Intel says it built a buffer to hold panel refreshes while the system was idle. This buffer is before the UCIe link, and it serves as an additional output buffer alongside the typical display buffer between the memory controller and display engine.

Without a base die for interconnect communication, UCIe also represents a large increase in die area. Intel trimmed a lot on both the compute and I/O dies to account for UCIe.

On the compute die, Intel trimmed down everything. Four Xe cores dropped to two, and without a dedicated ray tracing accelerator, the NPU went from three tiles to a single tile, and the memory subsystem was downgraded to a 64-bit bus, with lower maximum speeds and lower capacity. As mentioned, there were a lot of cuts in the display engine, which was a primary concern for die space and power.

Intel uses three display pipelines instead of four, opting for HBR3 as opposed to the massive bandwidth offered with UHBR20. That still provides 4K60 and can drive three external displays, which is plenty for a device in the class that Wildcat Lake is targeting. Trimming down the compute die allowed Intel to claw back 38% of its die space.

On the I/O die, Intel claimed back 15% die area by removing the camera PHY, reducing PCIe and USB support, and slimming down the audio engine. The camera was completely removed, placing the onus on OEMs to integrate their own controllers.

UCIe 3.0 is capable of up to a data rate of 64 GT/s, but Intel capped the transfer rate in Wildcat Lake at 8 GT/s. That still allowed Wildcat Lake to support mainstream PCIe 4 SSDs and 4K60 external displays, but running at a lower data rate reduces bit-rate errors and therefore allowed Intel to remove some bit-correction systems.

Reducing the cost of Wildcat Lake

Cutting down the compute and I/O dies saves money, but there are several other considerations when talking about the cost of a mobile SoC like Wildcat Lake. The economics need to work in the final product, which Intel touched on in its Hot Chips presentation, both from the perspective of the total bill of materials for OEMs and the yield/loss rate.

The big factor in cost savings was the elimination of the base die, which not only reduces raw material costs but also comes with the yield upside, without advanced packaging.

As usual, Intel bins Wildcat Lake into different SKUs, though it was careful to only attempt recovery where it could. For instance, it could package a single working P-core as a Core 3 304 instead of a 320. However, it didn't attempt recovery in areas that would compromise key design points of Wildcat Lake.

For instance, it didn't attempt recovery on LPE clusters and I/O, as they're critical components of Wildcat Lake. The goal, according to Intel, was to create a stack that customers actually wanted to buy while trying to maximize yields where possible.

Intel also considered the full bill of materials for Wildcat Lake. Intel integrated Wi-Fi 7 and a USB PD controller, cutting costs for OEMs to integrate their own controllers. Perhaps the biggest point of savings was in memory, using a much slimmer bus and a 6-layer PCB as opposed to eight layers. Extending off the chart above is Project Firefly, Intel's initiative to leverage the mobile supply chain for budget laptops.

Interestingly, Intel also included an area that led to higher cost but met the design goals of Wildcat Lake, that being a dedicated power rail for the LPE cluster. The "low-power island," as Intel calls its LPE cluster, is critical to Wildcat Lake considering every SKU comes with only one or two P-cores. That dedicated power rail allows the vast majority of lightweight workloads to run on the LPE cluster and earn back battery life.

Wildcat Lake is one of the more interesting consumer launches we've seen in the past year. There's the MacBook Neo and Snapdragon C competing in the same space, but both use mobile SoCs in the traditional N-1 design point for budget platforms. Wildcat Lake is different, based on Intel's latest node, and leveraging newer open standards to achieve a lower price. That's why it won a Tom's Hardware innovation award for 2026, after all.

Full Intel Wildcat Lake Hot Chips 2026 presentation

Intel shared more details of its Crescent Island AI accelerator, powered by the Xe3P architecture, at the Hot Chips symposium this week. Unlike Nvidia's Rubin and AMD's MI455X GPUs, which are high-power, exclusively liquid-cooled chips with massive pools of HBM4 memory that provide maximum performance across both AI training and inference workloads, Crescent Island is designed to fit into a lower-power, inference-first niche in the AI accelerator market.

As a refresher, Crescent Island is a 350W air-cooled PCIe card that uses up to 480 GB of LPDDR5X memory, meaning it can be deployed in traditional servers without exotic power and cooling requirements. We've already learned about some of Crescent Island's DNA from past disclosures, but Intel went deeper into the chip's architectural details at Hot Chips.

Crescent Island is built up from four Xe3P slices, each containing eight Xe Cores, for a total of 32. Each Xe Core has eight Xe Vector Engines and eight XMX matrix accelerators, for a total of 256 of each resource.

The Xe3 graphics architecture, as seen on Intel's Panther Lake processors, already modified the capacity and flexibility of the GPU cache hierarchy to improve utilization and decrease performance-sapping register spills, and Xe3P further refines that hierarchy.

The Xe3P Xe Core has twice the amount of general register file space for working data versus Battlemage. Each Xe Core now has 1MB of general-purpose register file space, up from 512KB on Battlemage and Xe2. In addition, Xe3P offers 512KB of L1 cache or shared local memory per Xe Core, a structure that started out at 256KB on Battlemage and grew by approximately 1.33x on Panther Lake's Xe3 GPU. The chip also has 32MB of shared L2 cache. These expanded caches are meant to serve the chip's larger matrix accelerators on its AI compute-focused mission.

Xe3P boasts a larger systolic depth in its XMX engines than past Xe GPU designs. Xe3P's XMX systolic engines are a 16-deep design, meaning they can process matrices in much larger chunks than the four-deep systolic design of Xe2 and Xe3. Nvidia doesn't discuss the architecture of its Tensor Cores in anywhere near this level of detail, but as an AI inference-focused part, the fact that Xe3P can theoretically work on more elements at once during general matrix-multiply operations is an important capability boost for Crescent Island's inference ambitions.

Intel is also prioritizing a broad range of data types with this chip, from FP4 formats with microscaling support (aka MXFP4) all the way to what it describes as full-rate double-precision (via 64 FP64 FMA units per Xe Core). FP64 isn't widely used in AI workloads, but Intel says that the inclusion of full-rate processing for that data type makes Crescent Island useful as a converged high-performance computing and AI chip.

Each Xe Core also supports sigmoid and tanh transcendental functions, which are important to a variety of operations during AI inference, especially the softmax function. AMD and Nvidia have prioritized the performance of these functions in their recent architectures as well, so the fact that Xe3P offers support for them is key for its AI-first initiatives.

While Crescent Island does have a media codec block featuring four encoders and decoders to help serve up video to multimodal AI models, gamers hoping for a glimpse of future Arc cards won’t find it with this product, as graphics-specific functionality like RT cores has been omitted from this chip to preserve die area for compute functionality.

As a data-center-focused part, Crescent Island offers a full suite of reliability, availability, and serviceability features, including ECC and parity protection across the die and a range of memory reliability features.

As for the specific applications that Crescent Island will target, Intel highlights the rise of mixture-of-experts models paired with speculative decoding as a new class of workload that Crescent Island can serve well.

Speculative decoding strategies vary, but in general, they use a fast, lightweight mechanism to create drafts of future tokens that the main model can then be used to accept or reject, potentially improving decode performance. Not every draft token generated this way will be approved, but much like speculative execution in CPUs, it helps produce useful work from compute resources that would otherwise be left idle.

As model serving recipes pursue more aggressive drafting mechanisms, more compute is required to generate those draft tokens. At a high level, that understanding changes the common perception of decode as being a mostly memory-bandwidth-bound operation.

As an LPDDR5X-powered chip, Crescent Island won't have the eye-popping bandwidth of HBM-backed accelerators at its disposal for maximum performance with traditional autoregressive decode, so any help it can get from these speculative methods will be helpful.

Overall, Intel claims that Crescent Island is built to offer high FLOPS per watt and that it's optimized for compute-bound workloads like prefill (aka prompt processing and KV cache construction). Intel's emphasis on those areas of AI performance, as well as heterogeneous deployments, suggests that this chip could have a niche alongside HBM-backed accelerators whose resources are best used for decode operations.

Intel and its partner SambaNova could both stand to benefit from such an arrangement, as that company's SN50 inference accelerators are explicitly built to benefit from disaggregated prefill processing powered by GPUs. SN50 racks and Crescent Island are both meant to serve as lower-power, air-cooled systems that customers can deploy in existing data centers without dramatic upgrades to power or cooling infrastructure, so there is broad synergy in the shape of those products.

Intel still isn't discussing just how many theoretical compute FLOPS to expect from Crescent Island, nor is it disclosing memory bandwidth figures. But the architectural decisions it's shared so far — getting lots of data close to the compute engines of the chip and processing more of it at once in a relatively narrow power envelope — seem sound in a world where the company is still trying to reset its AI ambitions after a string of high-profile product failures and cancellations.

Intel has promised Crescent Island for a second-half 2026 time frame, and the clock is ticking on that launch window, so we’re eager to learn more about the chip’s final specifications, as well as customer and partner wins, when that launch does occur.

AMD has been the dominant force in DIY PC building CPUs for several years now, thanks to the advent of Zen 3 and great chips like the Ryzen 7 5800X3D, and more recently its potent Ryzen 7 X3D SKUs like the 9800X3D. Now, just days after AMD touted that it continues to occupy all 10 slots in the Amazon CPU best-sellers list, a couple of Intel CPUs have broken into the list for the first time in months, as spotted by WCCFTech.

The two chips in question aren't surprising if you know ball. Coming in at number six is the Core Ultra 7 270K Plus for $290 USD; Intel's most recently released desktop CPU, and at nine we have the workaday Core i7-14700K for $312, a steady seller since its launch in 2023. It offers less performance in gaming than many of the other chips in the top 10 (including the cheaper 270K Plus), but it has the advantage of being able to slot into both aging LGA 1700 systems as well as new builds with DDR4 memory. That's also likely why the Ryzen 5 5500 continues to stay near the top of the chart at #2, while the Ryzen 5 5600X and Ryzen 7 5800X3D (in its 10th Anniversary guise) also rate high. As for the Core i7-14700K, we actually recommended it over the Ryzen 7 5800X3D in our review of the 10th Anniversary re-release of that chip for people who are building new DDR4 machines.

The Core Ultra 7 270K Plus appearing this high is heartening for Intel's sake, though. If you haven't kept up with Intel's CPU releases, this chip is a course correction from the first-generation "Arrow Lake" processors, offering outstanding productivity performance and very solid gaming performance, just a few percentage points off of the beloved Ryzen 7 7800X3D that sits one position above it in the rankings. Put frankly, the Core Ultra 7 270K Plus beats everything else in the top 10 for both single- and multi-core performance save for the $569 Ryzen 9 9950X3D, which is in an entirely different price class from the $290 Intel chip (though discounted quite significantly at $569, 19% off the $699 list price)

It's clear that gaming continues to be a top driver for the DIY market. Five of the chips in the top 10 have been on our list of the Best CPUs for Gaming either now or at some point, including the number one seller, the Ryzen 7 9800X3D. AMD's 3D V-Cache continues to be unbeatable in gaming, even if the Arrow Lake 'Plus' parts do their best to close the gap with extremely high single-core performance. It's not single-threaded speed that's the bottleneck anymore, though, and not for some time; the limitation in gaming frames is multivariate as it has ever been, but on the CPU side, it's largely down to memory performance these days, and that's exactly why AMD's 3D V-Cache chips dominate.

Of course, if you're reading Tom's Hardware, you probably don't need me to tell you that. But it's interesting to look at the pricing of the parts that are moving the most units. The Ryzen 5 5500 is a tame processor, but if you need a gaming PC for the absolute bottom dollar, it's hard to beat six Zen 3 cores with a CPU cooler for $84. The Ryzen 7 7800X3D seems an absurd choice next to the much faster Ryzen 7 9800X3D for less than $100 more, but the gaming performance is really pretty close, and you're likely to desire a drop-in Zen 6 processor upgrade late this year or early next year, so why spend the extra $85 now?

That CPU upgrade angle warrants consideration. Any Socket AM5 processor has a path forward, and that's not the case for any extant Intel platform nor for Socket AM4, despite the fact that Intel is apparently releasing new LGA 1700 chips eventually. Ultimately, memory pricing is probably driving a lot of these choices, but in the upgrade context, it's not quite as surprising to see five and a half of the top ten CPUs on platforms that require DDR5 memory—the 'half' being the Core i7-14700K, naturally.

You absolutely can build a DDR4 machine using the Raptor Lake Refresh CPUs, but the performance penalty can be significant; in our testing, we found that it was actually worse than just running a single DDR5 DIMM. It's the PC builder's Sophie's Choice: buy a last-generation CPU to save significant cash on the RAM, or suck it up and spend out massively on a system that offers the best performance now.

Pricing is naturally also a factor; the Core Ultra 7 270K Plus launched at the comically low price of $299 in comparison to the $589 Core Ultra 9 285K, which it performs very close to, so $290 isn't much of a discount there. Meanwhile, the Core i7-14700K's $311.99 price tag is 16% off of Amazon's list price of $370.99, but it's a bit larger markdown from Intel's $419 recommended customer price. Still, if pricing is your primary motivator, it's hard to ignore the $330 Ryzen 7 7800X3D (27% off list), at least as long as gaming is your main concern. There's the 5800X3D 10th Anniversary, too, but again, the Core i7-14700K actually offers better minimum framerates and vastly superior productivity performance, especially if you're willing to do some memory tuning.

Clearly, gamers have accepted that memory pricing isn't coming back down any time soon, and that the time to buy is now before it gets even worse. The shortage isn't expected to abate between now and late 2028; if you're keen to build a new machine in the in-between, make sure you keep an eye on our Deals posts to save yourself from bleeding too much at the checkout.

The second quarter of 2026 was quite favorable for CPU suppliers, as unit growth was 10% sequentially, with data center and laptop processor shipments more than offsetting declining sales of desktop CPUs and lower-end products for embedded and IoT applications, according to a new report by Mercury Research. AMD continued to gain market share, so its unit shipments and share reached a new record during the quarter; Intel managed to increase shipments of its client and data center CPUs; whereas Apple sold a boatload of processors in its popular MacBook Neo laptops. Overall, the report describes the desktop X86 CPU market as "ugly."

The sky is blue for CPU (for now)

"In spite of a decidedly gloomy outlook on client processors from the suppliers for the second quarter, actual results for both x86 and Arm CPUs were up strongly in the second quarter of 2026, with sequential quarterly growth of the total market exceeding 10%, far in excess of normal seasonal trends which call for a slight decline in the quarter," said Dean McCarron, principal analyst at Mercury Research. "Behind this growth was a large increase in Intel's CPU supplies, especially in mobile client, after a couple of heavily supply-constrained quarters, and continued strong ramps for AMD's products. […] Arm shipments also appeared to be strongly higher in the quarter as well."

While the CPU market was up quarter-over-quarter (QoQ) mostly because AMD, Apple, and Intel increased their shipment volumes, on a year-over-year (YoY) basis, the CPU market contracted in terms of units. However, the decline was primarily driven by significantly lower IoT, SoC, and embedded shipments — largely due to AMD's shrinking game console business — as well as a substantial drop in desktop CPU volumes. At the same time, shipments of data center and notebook processors grew strongly.

Excluding IoT, SoC, and embedded products, both AMD and Intel substantially increased CPU shipments sequentially, but AMD grew faster and gained unit share in every major segment, so the company now controls 30.7% of the overall x86 processor market, its highest share ever, according to Mercury Research. With IoT, console SoCs, and embedded CPUs included, AMD now controls 34.1% of the x86 processor market. Intel continues to lead, but AMD's growth is impressive.

"AMD's total unit shipments and total market share reached new record highs in the second quarter of 2026, with a sequential share gain of 0.7% and an on-year gain of 6.5%," McCarron said.

Client CPUs: AMD gains share as Intel increases shipments

Performance of the client x86 CPU market was a mixed bag in the first quarter as sales of desktop CPUs declined badly, whereas shipments of laptop processors grew significantly. Intel remained the clear volume leader with 69.7% of client CPU shipments, but lost share both sequentially and year-over-year. AMD continued to gain ground in Q2 2026 as its unit share reached a record 30.3%, up from 29.6% in Q1 and 23.9% in Q2 2025.

AMD gained share in both client categories. Its desktop unit share rose from 33.2% to 34.9% QoQ, even though AMD itself shipped fewer desktop CPUs; Intel's shipments declined even faster. In notebooks, AMD increased its share from 28.3% to 28.9%, even as Intel expanded production capacity and shipped millions more CPUs.

In general, the results for the quarter suggest that Intel's improved client CPU supply helped to meet demand from PC makers and led to a client PC market rebound, the company could not stop AMD's share gains.

Desktop CPUs: The ugliest segment of the market

Hit by limited availability of graphics cards and high prices of components like motherboards, memory modules, and SSDs, the desktop CPU market was particularly weak in Q2 and contracted by over 20% YoY as well as quarter-over-quarter due to seasonality. Both AMD and Intel suffered significant annual shipment declines, but AMD held up better, according to Mercury Research.

Despite dropping desktop CPU unit shipments and overall market weakness, AMD increased market share in Q2 2026. AMD's desktop CPU unit share upticked to 34.9%, up from 33.2% in Q1 and 32.2% in Q2 2025, while Intel's share fell to 65.1%, from 66.8% sequentially and 67.8% a year earlier.

During the quarter, AMD gained 1.8% QoQ and 2.7% YoY in unit share because declines in its shipments were considerably smaller than Intel's. So, while normally we say that AMD is gaining desktop share because of strong sales of its latest Ryzen CPUs, in this case AMD's success was driven by slower declines than rapid gains.

Mobile CPUs: Sales of laptops are growing

The mobile CPU market segment performed completely differently from the desktop CPU market segment. Mobile x86 CPU shipments grew significantly quarter-over-quarter and were also modestly higher YoY. Mercury Research says Intel added millions of units of mobile CPU capacity during Q2, which helped close the supply-demand gap that had constrained the company in previous quarters. Yet, AMD's shipments increased at nearly the same pace as Intel's, which enabled it to capture 0.6% of the market.

AMD's mobile CPU unit share rose to 28.9%, up from 28.3% in Q1 and from 20.6% in Q2 2025. Intel remained dominant with 71.1% of shipments, down from 71.7% sequentially and 79.4% a year earlier. As a result, AMD gained a modest 0.6% sequentially, but a much more impressive 8.4% YoY increase.

Server CPUs: +20% year-over-year

Demand for server CPUs increased for both traditional data center processors — AMD EPYC and Intel Xeon — and CPUs used in networking and storage applications, so x86 server processor shipments posted nearly 20% YoY growth and moderately strong sequential growth. AMD continued to gain market share and now commands over 1/3 of the server CPU market, according to Mercury Research. There is a catch, though: due to Intel accounting peculiarities, AMD's unit share is artificially low and so is Intel's own dollar share.

In Q2, AMD’s server CPU unit share increased to 34.5%, up from 33.2% in Q1 and 27.3% in Q2 2025. Intel remained the volume leader with 65.5% of shipments, but its share fell from 66.8% sequentially and 72.7% a year earlier. While some may say that AMD's gains are slow (not too slow at +7.3% YoY), there is an explanation behind that slow growth.

Mercury Research notes that its broad server share calculation somewhat disadvantages AMD because Intel's edge and networking processors are now reported within its Data Center and AI (DCAI) business, so in reality, AMD's unit share should be higher. If the comparison is narrowed to EPYC versus Xeon processors for servers, AMD's unit share reaches 46.4%, up a substantial 2.9% QoQ and 9.2% YoY, which puts AMD very close to Intel in the core data center CPU market. Meanwhile, if CPUs for edge and networking applications are ignored in Mercury's analysis, Intel's dollar share would increase considerably.

Mercury Research indicates that server CPU supply constraints could limit gains in Q3, but in Q4 sales of data center-grade processors will increase noticeably both compared to Q2 and Q3.

Summary

After a weak Q1, the CPU market rebounded strongly in Q2 2026 as unit shipments grew more than 10% sequentially. The market growth was driven by rising notebook and server CPU sales, which more than offset a sharp decline in desktops, according to Mercury Research.

AMD's performance was stellar as it gained ground in every major segment even as Intel substantially improved processor availability. Despite improved availability of Intel client and data center processors, AMD still outgrew Intel and reached record overall and client CPU unit shares.

Desktop remained the major weak spot due to high component costs and generally lower demand as enthusiasts pulled in their purchases to 2025, greatly lowering sales of high-end hardware in 2026. Shipments of desktop x86 CPUs fell more than 20% YoY, whereas mobile and server volumes increased.

In core data center processors, AMD's EPYC share approached Intel’s Xeon share, which highlights how dramatically the competitive balance in the server market has shifted.

Intel will launch its new core with Nova Lake on desktop first, not in the data center. Tom’s Hardware Premium recently sat down with Intel VP and general manager of the enthusiast channel business Robert Hallock and asked about his reaction to AMD launching Zen 6 first in the data center with new EPYC Venice CPUs — breaking with over a decade of AMD leading with a client release for its new architectures. Hallock opened up about Intel’s enthusiast roadmap and said the company is “very serious” about executing that roadmap.

“I think it's a natural reaction for them. Makes a lot of sense. What I would say is, as we think about our own roadmap, I have a new core. It's coming to desktop first. I mean, I hope enthusiasts do the math about that one, and that's all I'm going to say,” said Hallock when we asked for his reaction to the Venice launch.

AMD has a unified processor architecture across client and enterprise, which, combined with chiplets, allows AMD to easily scale up or down new architectures to fit a wide range of applications. The core architecture and chiplets at work in the data center are largely identical to the ones in a consumer processor; minus some obvious cutting around memory channels, PCIe lanes, etc.

Intel’s architecture sharing isn’t as clean, with various codenames thrown around for each core with each new generation of products, regardless of whether those products are from Xeon or not. However, Intel’s core architectures share a lot of DNA. Golden Cove was launched first with Sapphire Rapids but was tweaked for Raptor Lake with Raptor Cove; Redwood Cove launched in Meteor Lake first before working its way into Granite Rapids. The rumored “Panther Cove” core architecture for upcoming Diamond Rapids CPUs is likely a refresh of the Cougar Cove cores in Panther Lake. With Nova Lake, the new core (rumored to be called Coyote Cove) will launch on desktop first, with whatever variation (or perhaps an entirely new core) working its way into Xeon eventually.

The sudden surge in demand for CPUs in new agentic AI data centers has upended the traditional release cadence of AMD and Nvidia. Nvidia has shifted great focus toward its new Vera CPU, while AMD moved forward with Venice ahead of Olympus Ridge; the codename for consumer CPUs with the Zen 6 microarchitecture. Intel’s roadmap, at least among the enthusiast desktop business, remains steadfast, Hallock suggested.

“I have all the new CPUs all the way out to 2030. I have [a] back to back to back to back cadence of product for gamers, for desktop, built for that purpose,” Hallock said. “Obviously I can’t go into what any of that is, but I am accelerating for the gaming market… we’re moving faster than we ever have in product, in release cadence.”

It’s worth reiterating that Hallock is referring to Intel’s roadmap here. He does not have processors in hand reaching out to 2030.

Although the roadmap sounds ambitious, Intel lost plenty of points with the enthusiast community when Arrow Lake launched. You know the story by now, with the new range often underperforming the older Raptor Lake offerings in games. Hallock says he understands that hesitation.

“I understand people are skeptical after the last couple years. I truly get that. But the signal Intel is trying to send is, like, we’re gearing up for one of the most significant desktop CPU launches we have ever had.”

Intel has made some efforts to regain the lost trust with Arrow Lake with Arrow Lake Refresh. The two CPUs in the range, the Core Ultra 5 250K Plus and Core Ultra 7 270K Plus, rank among the best CPUs for gaming, helping erode the narrative that the original Arrow Lake range set in stone. That wasn’t an accident. Hallock revealed that a “pretty much completely different” team worked on Arrow Lake Refresh, and that team is moving forward with Nova Lake.

“We took a team that was time-shared with other businesses, and now this slice of the market has a full org structure inside Intel… they’re putting real people with a lot of budget behind it, right? And having an owner, a sponsor, people that care about it, looking after it, custodians of that work, it makes a real difference,” Hallock said. “[The team was] pretty much completely different. Marketing people, different product managers, different business people, and we simply have a different philosophy on how this market should run and what people should get for their dollar.”

Presumably, Hallock’s team and the philosophy driving it is born partially out of his time at AMD. The VP spent 12 years at AMD, covering numerous significant milestones, including the introduction of Ryzen and the Zen core, and AMD’s first 3D V-Cache CPU. He joined Intel in 2023, and has overseen the launch of Arrow Lake and Arrow Lake Refresh. As a technical marketing leader, Hallock doesn’t meddle in the nuts and bolts of processor design. However, he covers the rollout of products, including aspects like naming and branding.

You can read the transcript of the full interview at our Tom's Hardware Premium site.

45 years ago, in August 1981, the PC age began in earnest with the launch of the IBM PC Model 5150. At its heart was the Intel 8088 microprocessor, a cheaper sibling of the processor that pioneered the x86 architecture, the famed Intel 8086. Intel’s new affordability-targeted processor, its IBM PC design win, and Big Blue’s decision to allow the making of PC clones would kickstart four and a half decades of PC compatibles dominating personal computing.

It is interesting to read about why sales engineer Earl Whetstone managed to return to Intel with a signed and sealed deal for supplying the Intel 8088 (June 1979), while the superior 8086 (June 1978) was overlooked. In a nutshell, it is the economics that won it for the Intel 8088.

Bits and busses

Intel’s influential Intel 8086 delivered the first x86 architecture chip and had a 16-bit internal architecture, with a matching 16-bit external data bus. Meanwhile, the 8088, introduced a year later, took that design and sliced the external data bus width in half, to 8-bit. This would make the newer 8088 slower, probably just into double digits, all else being equal. However, the 8088 was cheaper and also allowed IBM to pick up common 1980s-era components to configure the Model 5150, which also boosted system affordability.

Meanwhile, software written for the 8086, an ecosystem developed in the few years between the introduction of the first x86 architecture chip, would be central to IBM’s plans for the Model 5150 being realized. By 1981, there were versions of DOS for x86 ready, and the creators of key third-party software like WordPerfect, Lotus 1-2-3, dBase, and a host of other early suites and tools were developing for x86. This helped the IBM PC Model 5150 become a hit product out of the gate.

There have been over a dozen x86 processor manufacturers

Commenting on this important date for Intel, IBM, and the birth of the PC industry as we know it, analyst Patrick Moorhead tweeted about the diverse canon of x86 processor manufacturers over the years. In addition to Intel and AMD, most computer history buffs will be familiar with Cyrix x86, and perhaps even efforts from IBM, NEC, and NexGen. However, Moorhead reminds us that NEC also made x86 chips, as have Texas Instruments, IDT (Centaur Technology), Rise Technology, SGS-Thomson, and Transmeta.

Moorhead’s dozen wasn’t even a fully complete list. Others on social media pointed out that the following firms may have (if memory serves correctly) produced x86 chips at some point: ALi/ULi, Harris, Fujitsu, and Zhaoxin.

Into the AI-computing era

On its IBM partnership giving birth to the PC age, Intel concluded its anniversary message by saying “We look forward to continuing that teamwork for another 45 years and beyond.”

However, we note that Intel also talks about building on the legacy of the original PC into the AI-computing age. Ironically, it is the AI boom that has caused many people to be priced out of new PCs, new components, and/or upgrades in the last few months.

Nvidia’s $5 billion purchase of Intel stock last year, made as part of the companies’ strategic AI infrastructure partnership announced in September, has become a highly lucrative investment, generating nearly $25 billion, the company revealed in an SEC filing this week. In addition, Nvidia owns nearly $21 billion worth of SpaceX stock and holds stakes valued at more than $10 billion in various customers, partners, and suppliers.

With quarterly revenue exceeding $80 billion and net income approaching $60 billion, Nvidia has plenty of unspent cash to invest. Traditionally, the company invests in stocks poised to grow and makes strategic investments.

Nvidia's investment in Intel was both strategic and financial, helping Intel survive hard times and generating $24.989 billion for the company. Interestingly, after investing in Intel, Nvidia has sold its 1.1 million Arm shares (worth $178.1 million last August). Without any doubts, Nvidia will continue developing Arm-based CPUs, though for now it does not own any Arm stock.

The SpaceX investment — valued at $20.975 billion — seems entirely strategic at present, since SpaceX's xAI has committed to exclusively using Nvidia hardware in its AI data centers both on Earth and in orbit. Once SpaceX's stock regains its lost value, Nvidia may well earn on it, though it remains to be seen when this happens.

Other notable investments that Nvidia has made over the past year include Coherent, a major maker of lasers, optical materials, and semiconductors; Nokia, a telecommunications giant; and Synopsys, an electronic design automation (EDA) provider.

Coherent is expected to make Ultra-High-Power Continuous-Wave (UHP CW) lasers for Nvidia's next-generation data center platforms relying on co-packaged optical (CPO) interconnects, so Nvidia invested $2 billion in the company earlier this year. Since then, the stock has almost skyrocketed.

Something similar happened to the Nokia investment. Last October, the company announced plans to invest $1 billion in Nokia to accelerate AI-RAN innovation and lead the transition from 5G to 6G. By now, the shares that Nvidia owns are worth $2.2 billion.

Synopsys has been aggressively adding artificial intelligence capabilities for its tools, so to support the company, Nvidia acquired $2 billion worth of Synopsys stock last December. Right now, the stake is valued at $2.15 billion, making it a profitable investment for the AI hardware giant.

In addition, Nvidia continues to own stock of its clients, but the picture is different for CoreWeave and Nebius. Last year, the company owned 24.277 million CoreWeave shares worth $3.959 billion. Nvidia now owns 47.213 million shares of CoreWeave valued at $4.699 billion, which essentially means that the company substantially increased its position as CoreWeave's stock price declined. As for Nebius, Nvidia's position remained at 1.19 million shares, but while the stake was worth $65.869 million in 2025, its value has since surged nearly fivefold to $328.77 million.

If you've not subscribed to our subscription service, Tom's Hardware Premium, we've collated every article that you've missed out on over the past seven days.

Last month, hot off the BC-250's full 40 CU unlock patch, we thought the time was ripe and finally put together a BC-250 build of our own to see what all the fuss was about. In case you're out of the loop, the AMD BC-250 is a repurposed PS5 APU, designed for cryptocurrency mining. With mining firmly out of fashion, the chip has now found new life, thanks to community-made patches and fixes that get things up and running for gaming. After all, where else are you going to find 16GB of memory and a capable single-board computer for $200 (or thereabouts) in the current market?

The experience of reading Jake's trials and tribulations feels like harkening back to the days when everything wasn't simply plug-and-play, and if you wanted the most out of your hardware, you were going to have to get a little bit uncomfortable and more intimately familiar with the nature of the silicon you're running. If you're interested in running one of your own BC-250 systems, you don't want to miss this fantastic (and lengthy) read, which features extensive benchmarks comparing the build to the Steam Machine, alongside performance results using different CU counts and OS images.

• Benchmarking AMD's BC-250, offering Steam Machine-like performance at half the price

We also interviewed Intel's VP and GM of Enthusiast Business (and AMD's ex-Technical Marketing Director) Robert Hallock. As always, we give premium readers full access to our entire 45-minute session with Hallock, no redactions, no fluff. During the interview, Hallock addresses how Intel's entire team shifted between the release of Arrow Lake and Arrow Lake refresh platforms. He also gave us some insight into the importance of CPU software optimization, as well as dishing out some details about the highly anticipated Nova Lake lineup. (Yes, we asked if they had a V-Cache competitor, and you'll have to read the article to find out how Hallock responded.)

Catching a high-level executive in between product cycles is usually against the traditions of the press and marketing cycles that companies usually go through. This offers a fairly unique perspective, where we get to see how Intel is not only iterating upon its previous products, but also being somewhat reflective on the last few bumpy years for the company's consumer CPU segment.

• Intel VP Robert Hallock sets Nova Lake expectations, teases return to Raptor Lake for DDR4 platforms — our full 1:1 interview transcript

Elsewhere in the industry, we're starting to see real PCIe 6.0 devices that companies are actually going to be able to purchase. The standard suffered from a false start, mainly owing to the shift to PAM4 signaling, which behaves very differently from the Non-Return-to-Zero (NRZ) signaling that was deployed across prior generations. Several years on, we're now seeing commercial devices begin to arrive, including SSD's with capacities up to a staggering 2 Petabytes.

But for an ecosystem to thrive, you don't just need the devices; you need the ability for systems to communicate with them, too. So, we've offered an overview of the controllers, in addition to the drives themselves, to assess the current state of the PCIe 6.0 market.

• The current state of PCIe 6.0 SSDs and controllers — Marvell, Phison, and SMI prepare controllers as drives finally come to market following years of delays

In the news

In addition to the three features that we ran on Tom's Hardware Premium this week, we've also published a slew of News Analysis pieces, which aim to dig deeper into the biggest topics in the hardware and semiconductor industry.

Firstly, there have been dozens of headlines across the U.S. over the ongoing AI data center buildout. We've covered the protests, the impact, and the voices who are lending their ears to striking back against Big Tech's appetite for more compute by any means necessary. Our report collates the ongoing sentiment surrounding the accelerating buildout and how residents are fighting back.

• Over 70% of Americans oppose AI data centers; US protests intensify as more arrests are being made — almost 40 arrested this year in backlash to AI factory buildout

Hyperscalers are not backing down from putting money down to build more compute, which is currently constrained as AI models grow larger and more complex and as demand grows. To that end, we've seen that an eye-watering $2 trillion USD has been pledged to secure AI hardware and DRAM alone. The ongoing AI megatrend is transforming the semiconductor industry, all the way down the entire supply chain, and that's forcing companies to rethink how compute is purchased. At least for Apple and Google, that means putting up billions to secure critical components like NAND, DRAM, and more.

• Hyperscalers commit nearly $2 trillion to secure AI hardware and memory — Google leads $811 billion spending surge while Apple trails at $57 billion

Optical interconnects and photonics have become a flashpoint amid the ongoing AI saga. With the limitations of copper meeting the very real demand for faster connection speeds, optics is the answer that the industry has been developing for quite some time. However, the FCC's proposed Secure Networks Act could put the deployment of silicon photonics in jeopardy. The FCC's proposal to ban new-model optical transceivers could put an already incredibly strained supply chain at risk.

With 56% of global manufacturing for optical modules shored up in China, this would pose an immediate problem, and one that the markets have already responded to in-kind. We have broken down exactly how optical became the hottest topic in the semiconductor manufacturing industry, as well as how the U.S-China trade summit next month could weaponize the technology.

But what if there were other options? The photonics supply chain remains constrained and relatively immature. Full co-packaged optics chips might not be ready for full volume production, despite Spectrum-X CPO being rolled out across Nvidia's Vera Rubin lineup. The answer, in the short-term, may be near-packaged optics, as we explain all of the comings and goings in the wild world of silicon photonics.

• FCC proposes import ban on Chinese optical transceivers — blockade targets key AI interconnects as China holds 56% global market share
• How optical interconnects and silicon photonics emerged as AI's next hot commodity — looming US-China summit puts photonics into the crosshairs
• Near-packaged optics (NPO) gains ground as the industry hedges against CPO's growing pains

That just about wraps up everything we've published over on Tom's Hardware Premium this week. To read the above articles and to gain access to Bench, you'll need to purchase a subscription, which we've linked above.

We'll be back next week with another roundup of exclusive Tom's Hardware Premium reads that you won't find anywhere else.

Intel’s Robert Hallock, vice president and general manager of the enthusiast channel business, believes that the consumer market will see a split in sockets for mainstream and enthusiast platforms to address the rising costs of PCs for cash-strapped buyers. Tom’s Hardware Premium recently spoke with the technical marketing leader about the state of the PC market, which Hallock described as a “tale of two kingdoms.”

“I think the market's experiencing a tale of two kingdoms. For the folks who have a significant amount of discretionary budget, they can absorb the cost impacts of what's going on in the industry, and most other people cannot,” Hallock said. “And that's having a very different impact, as you can imagine, on different parts of the market. Low-end, mainstream is really taking a beating. Enthusiast and premium, not so bad. You could, depending on the device class, maybe even [say] growing positive. So it's a very starkly divided market at the moment.”

Hallock’s take on the market is interesting. The doom and gloom of the RAM and NAND shortages is omnipresent, but we’ve also seen very expensive launches despite that. Gigabyte launched the $5,300 RTX 5090 Infinity OC in June. Asus demoed its 20th anniversary ROG lineup at the same time, which includes a $3,300 motherboard and CPU cooler bundle, as well as a $6,000 RTX 5090. Saying the enthusiast market is growing given the current market conditions may be a stretch, but RAM prices haven’t killed it — an extra $300 or $400 in RAM in the context of a $5,000 PC doesn’t really move the needle.

That’s not the majority of the market, however, and presumably, those few high spenders aren’t enough to sustain a business at the scale of Intel. We’ve already seen concessions in hardware to reach buyers during the memory shortage, particularly in laptops, with the MacBook Neo, Intel’s own Wildcat Lake, and the newly-detailed Snapdragon C. On the desktop, we’ve seen AMD re-release the Ryzen 7 5800X3D and introduce the Ryzen 7 7700X3D. Intel has sold off its new Arrow Lake Refresh chips at much lower prices than expected, with the new Core Ultra 5 250K Plus recently dropping to just $155 in a limited-time sale.

On desktop, at least, these seem like short-term measures. Hallock suggests that, going forward, there will be a more clear divide between mainstream and enthusiast platforms, not just at Intel, but across the industry if prices don’t let up.

“I truly believe that what the market is going to see going forward, and this is just like an industry-level comment… and I want to stress this is not just Intel. You're probably going to see a split. You'll have a premium socket and a mainstream socket from everybody,” Hallock said. “If you’re playing in desktop space, that is probably what you'll do because the supply chain costs, the upstream costs, the same costs that are currently harming the entry-level and mainstream market, I don't see those abating anytime soon.”

AMD has stressed in its previous two earnings calls that gaming revenue, in particular, is declining due to higher component costs. In Intel’s most recent earnings, it reported revenue in its client business up 13% year-over-year, though clarified that was due to higher average selling price, not increased unit sales, because of “some inflation on our cost and [needing] to pass that on to the end customer,” said Intel’s chief financial officer David Zinsner during the earnings call at the time.

Hallock buttoned up the point clearly: “You're going to have to make some concessions in your product stack, and that's purely to control costs and give people an option that they can actually afford. Otherwise, if you don't do it, the other alternative is it just disappears because it's unaffordable.”

It seems for Intel that the socket split looks like LGA 1700 for mainstream and LGA 1954 for enthusiasts, though Hallock didn’t say that explicitly. In June, Tom’s Hardware first reported on “Raptor Lake Next,” which is supposedly a third refresh to Intel’s Raptor Lake lineup set for early 2027. Hallock didn’t confirm the range to us, though he said that Raptor Lake remains a “core part of the portfolio” that he wants to offer “for years to come.”

LGA 1954 is the socket that Intel’s upcoming Nova Lake CPUs will use. There’s a lot of anticipation surrounding Nova Lake, not only due to the lackluster reception of Arrow Lake, but also the various rumors that have swirled around the range, including the introduction of bLCC as a 3D V-Cache competitor and a 52-core flagship, neither of which have been confirmed by Intel.

Although a lot is riding on Nova Lake, Hallock was clear that, given the current market, it won’t appeal to everyone. “A product like Nova Lake cannot address every single slice of the market. It just can't, given the current market that we're in,” Hallock said. “But I do hope and do believe that people will look back and go, ‘Damn, you know, that was pretty freaking good.’ That's what we’re hoping for.”

You can read the transcript of the full interview at our Tom's Hardware Premium site.

Intel’s Robert Hallock, vice president and general manager of Intel’s enthusiast channel business, told Tom’s Hardware Premium in an interview that the Raptor Lake architecture will be part of Intel’s offerings “for years to come.” Intel has no plans to abandon Raptor Lake, and if anything, the company says it’s working to “smooth out” some of the supply and pricing inconsistencies among the range. Raptor Lake CPUs still rank among the best CPUs for gaming, not only due to the underperforming Arrow Lake (not Refresh), but also due to high DDR5 prices.

“Going forward, 10nm products like Raptor Lake; that is a core part of the portfolio that I want to offer to people for years to come,” said Hallock. “LGA 1700 is still a good socket. Lots of people [are] still interested in DDR4, so [we’ll] keep offering, and you'll see [pricing] smooth out over time. It'll come back to normal. That's the plan.”

Raptor Lake has become a key part of Intel’s roadmap as the RAM shortage strangles budget builders from upgrading to a DDR5 platform. In June, Tom’s Hardware first reported on motherboard manufacturers increasing production of DDR4-based boards with the LGA 1700 socket (the socket Raptor Lake CPUs use), and we’re seeing those products roll out now. Just days ago, in fact, Gigabyte introduced a new LGA 1700 board with DDR4 support.

Motherboards were one issue with Raptor Lake on DDR4 platforms; there were never a ton of LGA 1700 motherboards with DDR4 support to begin with. They were something of a stopgap with 12th-Gen Alder Lake CPUs as Intel transitioned to DDR5, largely falling out of favor (and inventory) as Raptor Lake rolled out and DDR5 prices started coming down. Obviously we’re living in a much different world now.

But as the DDR5 pricing crisis started hitting, Raptor Lake inventory started faltering, in part due to increased demand (at least according to Hallock), and likely also in part due to the gradual phasing out of older products. Today, the pricing situation with Raptor Lake is problematic. The Core i5-14600K, for example, sold for $200 or less for the better part of last year. It’s since jumped to around $250, if you can find it in stock at all. At the time of writing, it’s on backorder at Newegg and $262 at Amazon. Similarly, the Core i7-14700K should be selling for around $330, but it’s $380 at Newegg at the time of writing and sold out at Amazon. Again, for the majority of last year, the 14700K often sold for less than $350.

This wobbly inventory and pricing situation is due to the “sudden inrush of demand” for Raptor Lake CPUs as the RAM pricing crisis started to take hold, and Intel didn’t see it coming. “If people are going to go to more affordable hardware, they still want the fastest available for their money, and that happened to be Alder Lake and Raptor Lake. So there was a sudden inrush of demand into these parts — certainly not anticipated when you start your wafers, and your builds, long before that moment ever happens. So it's very hard to predict,” Hallock said.

And Raptor Lake CPUs do remain top DDR4 performers. In our recent re-review of the Ryzen 7 5800X3D, the Core i7-14700K and 13700K matched the 5800X3D in games, all three of which were using DDR4, and offered much better application performance. In our recent comparison of DDR4 against DDR5 across Intel’s LGA 1700 stack, we found that DDR4 is the major bottleneck in games, which is something even the 5800X3D can’t overcome.

Hallock indicates that we’ll see an increase in Raptor Lake inventory, though he didn’t specify what that inventory will look like. As Tom’s Hardware first reported in June, motherboard vendors are gearing up for “Raptor Lake Next,” which is supposedly another slate of refreshes set to launch at the beginning of next year. There are also Bartlett Lake processors that use strictly P-cores, exclusively for embedded applications. Although they haven’t made their way to DIY desktops, the range shows that Intel continues to produce 10nm products and likely will for several years in the future.

Although Intel is making efforts to improve Raptor Lake supply — be that through more stock or Raptor Lake Next — that isn’t coming at the cost of next-gen Nova Lake parts. Hallock indicated that Intel, as well as the industry more broadly, is looking at splitting mainstream and enthusiast offerings due to pricing pressure elsewhere in the market. You can read the transcript of the full interview at our Tom's Hardware Premium site.

This week, we managed to sit down with Robert Hallock, Intel VP and General Manager of Enthusiast Channel Business, in a rare interview that catches the company during a curious time, between product cycles and several months after the launch of the Core Ultra 200S Plus lineup of CPUs. With the company’s data center business booming, have consumer products been left behind, or will Intel continue to step in the right direction in regaining trust with a core audience that it’s appealed to for decades: the humble enthusiast?

The following is a transcript of our interview with Hallock, which has been lightly edited for flow and clarity. We hope you enjoy this unredacted look, exclusively available to Tom’s Hardware Premium subscribers. You can also catch session transcripts from earlier in the year, featuring Intel, AMD, Nvidia, Valve, and more.

Jake Roach (Senior CPU Analyst, Tom’s Hardware): I appreciate you doing this outside of a typical product cycle.

Robert Hallock (VP & GM Enthusiast Channel Business, Intel): Of course.

Roach: I really just wanted to get your read on a lot of things because things are crazy in the enthusiast desktop space right now.

Hallock: They are.

Roach: So, how are things going in enthusiast desktop land given memory shortages, NAND shortages, everything going on right now?

Hallock: I think the market's experiencing a tale of two kingdoms. Yeah. For the folks who have a significant amount of discretionary budget, they can absorb the cost impacts of what's going on in the industry, and most other people cannot. Right? And that's having a very different impact, as you can imagine, on different parts of the market. Low-end mainstreams really taking a beating. Enthusiast and premium, not so bad. You could, depending on the device class, maybe even be growing positive. So it's a very starkly divided market at the moment.

Roach: I guess I hadn't heard that kind of take on it before. I guess it makes sense that you have more discretionary spending, or if you already were kind of invested in a certain ecosystem. I haven't heard that before.

Intel’s flexibility in the consumer market

Roach: I'm curious about the position of Intel right now. There's AMD, Intel, and Nvidia, right? And you've seen a kind of big shift for AMD and NVIDIA. Nvidia doesn't even break out gaming as a business category anymore; it's embedded now, and I think AMD is now coming up on close to double the data center revenue that they have from their client business. But for Intel, the majority of your revenue still comes from the client business. Does that put you in kind of a unique position right now with so much focus on the data center?

Hallock: I think that it does. I like to believe that it does, and I'm hoping, selfishly for myself, that it does. One of the things that I believe that Intel, that people truly sleep on about Intel when talking about the big fight of this company versus that company, just how big Intel is, how many resources Intel has. As I look at, for example, you know our desktop enthusiast roadmap, I don't have to trade supply with a data center part; I don't have to worry about it. I don't have to think about it.

I can build a roadmap and a plan for the market that is sized against purely what is going on in the client market. And that kind of freedom is very empowering when you're trying to run an enthusiast desktop business for enthusiasts, and it doesn't mean that we're immune to what's going on in the market. It doesn't mean we're immune to supply fluctuations upstream of us. That happens too, right? But at a fundamental level, I can sit down with my team and my partners and build a plan for a product for the year, and not have to worry about what's going on with Xeon, as an example, and vice versa, right? That's their luxury too, right? I can do my thing in client land, and they can do theirs in data center land, and it's okay. And so the size of Intel is what allows that to happen. And at it is at its best, it allows us to maximize the investment and the return on multiple product categories. It's a nice one that works out that way.

Roach: I think it's been maybe a few earnings calls back. There were some mentions in a couple of earnings calls about wafer allocation moving toward the data center to meet demand for Xeon. But you're saying that's not really a concern when it comes to future launches.

Hallock: No, and so, just to give a little inside baseball. It depends on what era you're talking about. If we're just coming into the sudden AI boom, where prices are multiplying very, very rapidly. That was a surprising moment for everyone in the industry. Like we kind of felt it coming.

We heard the rumors, but the size and scale were very abrupt. It was immediate. That is still surprising. It was immediate, and in those cases, yeah, you’re probably going to have to trade some supply around. But once you’re in, like once you’re in it, now you know the plan for it.

Roach: Okay, so that was a temporary measure, gotcha.

On Intel’s enthusiast roadamps

Roach: So, shifting back to the desktop, I know you've mentioned several times about this ambitious enthusiast roadmap, presumably that centers around 18A and Nova Lake. So far, what we've seen out of 18A has been more premium offerings. Obviously, we have Panther Lake; we have Wildcat Lake. Wildcat Lake [is] not a premium offering, but it makes some pretty big concessions to reach that budget price point of single-channel memory and all of that. So I'm curious, given that there is such a large divide between this enthusiast premium category, this budget category, do you think that the DIY PC market can be served by a single product stack, especially on this kind of cutting-edge node?

Hallock: I truly believe that what the market is going to see going forward, and this is just an industry-level comment, is, and I want to stress this is not just Intel...You're probably going to see a split. You'll have a premium socket and a mainstream socket from everybody. If you're playing in desktop space, that is probably what you'll do because the supply chain costs, the upstream costs, have the same costs that are currently harming the entry-level and mainstream market; I don't see those abating anytime soon, right? And so it means that in order to continue providing affordable computer hardware, you're going to have to make some design concessions.

You're going to have to make some concessions in your product stack, and that's purely to control costs and give people an option that they can actually afford. Otherwise, if you don't do it, the other alternative is it just disappears because it's unaffordable. So, seeing a split is likely the outcome for everybody.

Roach: I was telling Thomas yesterday when Gamer Days first came out, I think there was a day when the Core Ultra 250K Plus was $150. I’m like, ‘Man, at that price, that is one hell of a deal.’

Hallock: Hell of a CPU? Yes, it is.

Roach: So obviously we have Arrow Lake Refresh. Arrow Lake Refresh is great, very positive reception. But we've also seen this… One of the stories we really heard a lot from the motherboard guys at Computex was spinning up older DDR4 boards with LGA 1700. I think Gigabyte just reintroduced one a few days ago, and that's great to see because there weren't a ton of those boards even when Alder Lake launched.

But, one of the things that has been concerning for me – covering CPUs – is a lot of volatility in pricing on 13th- and 14th-gen processors, oftentimes selling for much more than comparables from AMD or even for certainly from from Arrow Lake. I'm wondering: are there any plans to maybe improve supply, or some sort of effort to stabilize the pricing of those so it's a bit more consistent?

Hallock: Well, I think what you're seeing is the fact that those 10nm parts are still phenomenally good. We don't spend a lot of time talking about them in the media or at Intel. It's old stuff, and we've all moved on. But they're still phenomenally good CPUs. And if you look at the sort of bucket of options that you can buy for these older DDR4 platforms, it is very likely that Alder Lake or Raptor Lake are the fastest of the bunch in that mix.

Roach: They are. I just recently did a whole DDR4 vs DDR5 article.

Hallock: And so what you're seeing is just like if people are going to go to more affordable hardware, they still want the fastest available for their money, and that happened to be Alder Lake and Raptor Lake. So there was a sudden inrush of demand into these parts that was certainly not anticipated when you start your wafers and your builds long before that moment ever happens. So it's very hard to predict. But going forward, 10-nanometer products like Raptor Lake – that is a core part of the portfolio that I want to offer to people for years to come. LGA 1700 is still a good socket. Lots of people are still interested in DDR4, so keep offering. And you'll see it smooth out over time. It'll come back to normal. That's the plan.

Roach: Yeah, it was really interesting going back because obviously with Alder Lake’s launch, there was a bunch of discussion about DDR4 versus DDR5, but seeing how it scaled all the way up to 14th-gen. You have the 14700K with DDR4 at parity with a 5800X3D in gaming, and obviously much faster in applications. So yeah, I’ve been hoping for a $300 14700K that I can recommend to people.

On Intel's approach to AI in the enthusiast segment

Roach: I wanted to shift a little bit away from desktop. I know that is your, well. I guess maybe not desktop, but the kind of traditional view of just a single-socketed processor. Intel has this kind of breadth of IP, great graphics IP, lots of experience with memory and advanced packaging. And honestly, it's been surprising to me that we haven't seen what I like to call the 'big chip’ out of Intel yet, a consumer 'big chip' out of Intel. Between Strix Halo, I guess Gorgon Halo now, the M-series from Apple, and of course RTX Spark. I appreciate that that's not directly under your purview, but do you think that's an important area of the market, or is this a way to kind of capitalize on this sudden rush in demand for kind of these AI developer workstations?

Hallock: Tricky to say. I'm not sure about that part of the roadmap, but it's an interesting place because in a before time, a big integrated graphics device would have been pitched for gaming, right? It would have been pitched for gaming.

And the market has not always responded positively to that sort of setup, like whether or not the performance is right or the power is right, and oftentimes it's better than the CPU plus discrete option you can get for the same price and the same power. It's better.

Just, there's something about it people just don't take it, and then this whole AI thing came along in a real way – the agentic AI component of it – and certainly renewed demand for that kind of hardware. Now, does that sustain? I don't know. Do people come out of this seeing the value for gaming again – that I also don't know. But you know, we are looking at it, we are exploring it. It's certainly an interesting part of the market. A lot of excitement. People love to talk about it. But interestingly, I don’t think the actual run rate is all that high. So, it’s something we’re cautious about.

Roach: I will tell you every single event I have been to where they've had one of these agentic 'buy your box and run an agent forever’ demos, I don't think I've ever seen a single person actually sitting and watching one of those demos. I don't know what that says, but interesting to note.

Hallock: Just on AI software in general… It's an evolutionary process. Businesses can absolutely benefit now, like Intel has. I personally have agents running for me at work to do processes that honestly took a lot of my time. Sure. And now they're completely automated, and I just have to fact-check them, and that's great. I've saved a lot of time doing this, but you know, the transition to an average consumer – I don't know if we're there yet, right? We're not there yet, and I suspect that's probably informing the demo interest. But it is also a bit of a chicken-and-egg thing.

If you are not AI-aware or AI-ingrained, if you haven't just been dunked in the AI bucket because of your job or your profession or whatever, it is difficult to imagine what you could use it for, right? So now you're caught in this trap, 'well, I've heard about it, I don't know what I could use it for, but then I can get my hands on it, and now I don't know what to do with it.' It's like learning a search engine when we all had to do that, right? But on steroids.

Roach: It’s funny having conversations with friends and people who aren’t in this world because… recording and transcription, right? Like, that’s a super great use case of just, I mean, it’s not even an agentic or an advanced thing. I’ll explain that to them. They’re like, ‘Oh, that’s a great use case.’ I mean, for most people, AI is the sloppy AI images and things like that. That’s AI. They see no other use case for it.

Hallock: That's the great injustice in this industry, right? There are so many things that we all call AI. They all have the same name. And some of them are just like a sticker on a toaster, and some of them are legitimately useful, and they run on your computer, and you have custody over your information and your privacy. That's not bad, but that's quite a spectrum. Yeah, one word, and it's such a shame.

Roach: It is a shame too. With the hardware advancements, it's a bummer being at Tom's Hardware, being mostly a consumer-facing brand, and talking about things like Vera, things like Venice. I'm sure later this month, things like Diamond Rapids. You know, and all that stuff is very interesting from a hardware perspective.

Challenging AMD with new consumer hardware

Roach: I was interested to hear your perspective on this. I was at Advancing AI last month for the Venice launch, and I don't know how long it's been, but it's certainly been since Ryzen, since the original Zen, that AMD's leading with Zen 6 in the data center instead of on client. I just wanted to get your reaction to that.

Hallock: I think it's a natural reaction for them. Makes a lot of sense. What I would say is, as we think about our own roadmap, I have a new core. *chuckles* It's coming to desktop first. I hope enthusiasts do the math about that one, and… That's all I'm going to say.

Roach: Okay, perfect. I would expect no less of a diplomatic response, but I appreciate the response nonetheless. That is, it is exciting to hear that there's still a focus on consumers, because I know for GPUs especially, but even some questions with CPUs about, are we even going to get new hardware? Like, is that a thing?

And I think this goes to a bit of an extreme that all of our local compute's going to wither away, and then it's all going to be cloud instances or whatever that we rent from some data center somewhere. I don't think that's the case, but it is encouraging to hear that there is at least some focus on launching new enthusiast products. I'm wonderi–

Hallock: Not just some focus; I have new CPUs all the way out to 2030. I have a back-to-back-to-back-to-back cadence for gamers, for desktop built for that purpose. Obviously I can’t go into what any of that is, but I’m accelerating for the gaming market. We are moving faster than we ever have in product and release cadence. We’re very serious about this.

Yeah, I understand people are skeptical after the last couple of years. I truly get that. But the signal Intel is trying to send is like… We’re gearing up for one of the most significant desktop CPU launches we have ever had.

We took a team that was time-shared with other businesses. And now this slice of the market has a full org structure inside Intel, and if you're not in corporate America, what that means is the company is so serious about it. They're putting real people, with a lot of budget behind it, right? And having an owner, a sponsor, people that care about it, looking after it – custodians of that work – it makes a real difference.

Just... The difference between Arrow Lake and Arrow Lake Refresh. That’s the difference.

Roach: Oh man, that was a big difference. Oh. Different teams on those? Okay, I hadn’t realized because when we talked about Arrow Lake Refresh, it was… You had made mention of like ‘Hey, we’ve updated our roadmap, and this is our first, maybe peace offering after Arrow Lake.’

But I didn’t realize it was a completely different, or not completely different, but a different team.

Hallock: Yeah, well. Pretty much completely different. Marketing people, different product managers, different business people, and simply, we have a different philosophy on how this market should run, and what people should get for their dollar. And I’m glad that people appreciate it.

A post-Arrow Lake shakeup

Roach: Okay, so there was a big shakeup after. That was one of the questions I had. What were the key takeaways from Arrow Lake? But it sounds like those takeaways were addressed immediately.

Hallock: A couple takeaways that you saw manifest in the [Arrow Lake] refresh launch: The software experience for DIYers, which nobody likes to admit that we all need software for our CPUs because they all have a lot more cores than any game typically expects these days. And so the resilience of that software experience. How do people obtain it? How do they install it? How can they validate your performance? How can they verify that they're getting what you are promising? All of that was kind of open-loop in the Arrow Lake original timeframe.

We had some aspects coming from motherboard vendor websites, some from Windows updates, some from Intel.com. It's too complicated for people, so that directly led into the Intel platform performance package- like, kind of crazy- but put all your useful bits in one spot and tell people to download it.

Well, when you lose sight of this enthusiast DIY space and how people consume software and hardware in this part of the market, it's easy to get turned around. OEMs have a very different strategy. They go through these massive validation efforts and have huge QA labs and can set up a system image with point releases, and… Normal people don't have those resources.

You have to make it very easy for them. So, software resilience was a big one. And then when you look at a pile of IP, some engineer says, ‘Hey, your CPU can do this to this.’ That's your range of capability, and inside you open the box. You've got some stuff you can smudge around, like frequencies or voltage or core counts or specs on and off. You can decide to remix those very differently too. You decide to price it differently.

So what you're seeing is Intel got healthy on its software foundations for DIYers. Intel got healthy on its respect for performance per dollar for customers. We set up some really healthy internal processes for future platforms. Arrow Lake was a tough, tough lesson to learn, but a good one, because it drove some really, really useful changes inside Intel.

The importance of CPU software optimization

Roach: You've really beaten the drum on the importance of software; software is just as important as hardware. Just this past week I was testing out the BC-250. If you're familiar.

Hallock: Yeah.

Roach: The PS5 APU that was repurposed. And if you need a crash course in the importance of software to a gaming experience, just boot up one of those things. But can you explain, from your view, what the importance of software is, especially given Intel's… This is pretty ancient history at this point, but you know, use of specific compilers and things like that. What is your view about the importance of software to an overall performance package?

Hallock: I am scared to open this box, lest I get misinterpreted. So, here’s the deal. From the perspective of a software developer, it's actually really tough to be a professional software developer, especially if you are not self-publishing, especially if you have a publisher breathing down your neck. Because it means that your publisher is picking the release time, not you.

That's time crunch number one. Time crunch number two is… What hardware are we targeting? What CPU do I have at my desk as a developer? What does our QA lab have? What has the publisher allowed us to buy with our budget for QA? What does my historical install base look like for other games? And every time you open the box on any of those, you find more subdivision of compatibility that you need to worry about. That's time crunch number two.

Time crunch number three is, did you start on a console, or did you start on PC? Which were you targeting first? Probably console. So now you have to do a port, which is a time crunch. Some publishers outsource this. There are companies that all they do is console ports to PC.

Roach: A lot of Sony games.

Hallock: You know, I’m thinking of Nixxes. What a great developer! They've been amazing over the years at doing these kinds of ports. So all you're really doing is budgeting a decreasing amount of time as a dev, and then you're like, okay, well, my game has to run on a CPU anywhere from four cores to, gosh, like 32 threads, 24 threads, depending on the vendor. It's a lot.

And so what ends up happening is they just draw a line in the sand. This is the hardware we have in QA. This is what's on my desk. This is what's in the console, and that's what we have time to look at. And maybe we'll look at other stuff later. And a lot of the time, one thing that many gamers still don't quite understand is, like, it's not even really the Windows scheduler or the OS scheduler that's determining how these CPUs get used when you're running a game-they have their own layer.

It's called an affinity mask, and they tell the OS how to use the CPU. So the game is in control of how to do the scheduling, sending all these hints to the operating system. What if those hints are wrong? What if those aren't the right hints for the CPU you have in the socket? What if the game is newer than your hardware, or substantially older than your hardware? Or the developer never looked at your combination?

These are all moments where the game can easily give up huge chunks of performance, or just not run. And everybody has to deal with this, right? Every CPU vendor has to address these challenges somehow. We call it the Intel Platform Performance package; AMD calls it the chipset driver.

Right, we've all got this, and it's so important because it can reach into the operating system, or reach into the application, or reach into the firmware of the CPU itself, and make those real-time adjustments to get the performance back. Gamers would not like how this industry looks without this software from the CPU vendors. It would be a much, much less performant, much slower, higher frame time, more stuttering, sort of environment.

Roach: Yeah, it’s already quite surprising to deal with.

Hallock: Yeah, software cannot replace the CPU, and that is not what we're proposing, right? We're not saying, 'hey, I'm going to give up 10% on the hardware and give you 10% back on the software because it's cheaper.' No, I want 10% of both.

That it’s not trade; it’s both. And that is why we’re interested in pursuing it, and why I think it’s so important, because I’ve now spent serious time at two processor companies and have seen the performance gains that come from this kind of software, and what they contribute to the experience, including my own gaming system that I’m talking to you on right now.

And so, that’s why I’m big on software, because the performance would be much, much worse without it – not insurmountably, but it would functionally limit the kind of hardware that you can produce if everything has to fit in this lowest common denominator of software. That’s the other outcome, and that would be even worse. We cannot have the hardware be stagnant because of the software.

Roach: Gotcha. Yeah. That’s certainly giving up. It’s not the 10% hardware for 10% software. Leaving stagnant software gives up a lot more.

Hallock: That’s right.

Roach: Yeah. You know, we did a story probably a couple of days ago. This guy who, we call him a hardware researcher, but he really just does memes. He made a C compiler that would compile completely with Move and Assembly, and then he made a leaderboard of… it was the x86 Hall of Shame, where he tried to find a single assembly instruction, how to make it run as slow as possible, and he got one up to 189 billion cycles.

Yeah, it was ridiculous. He basically found the two slowest areas in the fabric, the two highest-latency areas in the fabric. Ran the instruction on one of them, and then had the other one make a bunch of frivolous four-byte reads, and like lock it up. Yeah. Anyway, just a great example of how you can make hardware–

Hallock: What people don't understand, every CPU architecture is like the fine art of intelligent compromise, and it's like, okay, well, just as like a random example, could you make the read and write link the same size? Sure.

But what if the reads are like 10 times more common than the writes? Do you really need them to be bidirectionally the same size? Like it's going to show up on a micro benchmark. Someone's going to complain about it, but in real performance, day-to-day, do you actually need it? Yeah, probably not. And there's stuff like that all over a modern CPU based on decades of just, like, learning how people are likely to use this thing; it actually does shape the microarchitecture itself somewhat, like a reflexive principle, right? We speak it into existence by using our processors in a certain way. It's fun.

Checking in on IBOT

Roach: On software, I think I'm probably much higher on IBOT personally than you know. We've seen some interest in it. We did some testing for it. I think it's this thing that probably becomes more important as time goes on. I'm just wondering how it's going. We've had one update, I believe, one game update. I just wanted to check in on how IBOT’s coming along.

Hallock: Going well. You know, we continue to work on multiplayer support, which was kind of in the initial scope. It's taking, I think, longer than the public may have expected, because we certainly do not want people to get in trouble using this technology. And that means you have to talk to a lot of people to do it. We're actively working on non-gaming workloads.

We are working on another upcoming release. I don't have the exact date for this, but we're working on the bits for the next update. And then we're also thinking about, for Nova Lake, you know, what is version 2.0, for lack of a better phrase? What do we want to build into that release based on the new hardware capabilities? Which I know is both some details and not a lot of details, but it's very important to us; it is a long-term, permanent aspect of our roadmap.

Roach: Yeah, I think the game selection has been interesting to see. Obviously, when we spoke around Arrow Lake refresh, you had mentioned, ‘Hey, there's going to be a lot of games where there's no benefit whatsoever, or a lot of workloads in general where there's no benefit whatsoever. We just want to improve where we can.’

I'm curious how you go about finding those improvements, because surely it can't be just throwing everything at the wall and seeing what sticks.

Hallock: No, well, sometimes it is. Okay. Sometimes it is. It’s a multi-part process. We do have a team that proactively goes out and evaluates things that are very popular, high profile in the community. Just because it's so obvious to go grab those and take a look. We also have automated systems that go through workloads and try to find opportunities. That does a lot of heavy lifting. Dirty word, but we have AI tools that can also help us analyze and find opportunities. So it's one part manual and a lot of automation to find these, and we go from there.

Adressing Nova Lake rumors

Roach: I wanted to ask something a little bit more direct about Nova Lake because speculation around Nova Lake has been going on for a while. I wanted to focus on the high-end, there's been kind of these endless rumors about a 52-core part. You have teased previously scaling up Thread Director to deal with these higher core-count CPUs. I'm wondering right now: What does something like this ultra-high core count, or like a high-end desktop processor, what is that offering right now to the market, in your view?

Hallock: My view has always been that the market will initially go. ‘Ah, what am I going to do with this kind of hardware?’ And then they figure it out. And my most recent example of this comes from my time at AMD. I was sitting at Computex, and at the time we were unveiling our first 12-core CPU. So that would have been the 5900X, I think, maybe the 3900x. It's been a while, and I was sitting in the room with a bunch of journalists who – 18 months ago – had been like, "Why eight-core in consumer? What are you even talking about? Why? Why does this exist?” Same people sitting in front of me. I'm talking about a 12-core CPU, and they're like, "Where's your 16-core?" Like a poorly, poorly kept secret at that point, right? Like it was only like a week away from getting announced, and everybody knew it existed.

How quickly perspectives change. Suddenly, we went from four-core to eight-core, to 12, to 16 in three years. And man, how quickly people’s opinions changed about the value of [higher] core counts. I don’t think, in the history of the PC industry, [that] bigger bar better, more performance better. Never a bad answer. And that does inform my thinking about the roadmap, and Intel’s thinking about the roadmap going forward. It’s never a bad idea to offer more hardware to people.

Roach: The irony. About that, I think it was Zen...It must have been Zen 2. The irony about that is that the 12-core SKUs are always significantly worse than the eight-core and the 16-core. I guess there are some workloads where it makes sense, but yeah, it's interesting to hear.

I think, you know, one of the big hopes for Nova is a competitor to V-Cache. I know this is something you're well aware of, and you know has been brought up numerous times. I watched some previous interviews that you did, I believe, with a recent one with PC Games Hardware, and you had mentioned ways to improve cache locality as something like, ‘Hey, we don't just need to stack a bunch more cache on the chip. We have other levers we can pull to find this performance or to offer something that the X3D chips offer.’

I'm curious what those levers are, because you've made reference to them before, and I just wanted to get a little bit more of a technical explanation.

Hallock: We will have to wait for the fullness of time, won’t we?

Roach: Yes, we will. Hey. You can’t knock me for trying.

Hallock: No, you have to try, and I appreciate and respect that. You know, my bottom line is this is going to be both an answer and a non-answer. Sorry. But I want to try to answer the question for the public more generally. We understand and appreciate there is a like a lot of hope, a lot of expectation, and a lot of desire surrounding Nova Lake. We get it.

And in some ways... selfishly. We’ve lived through it. Every negative comment, every bad tweet, every crappy article. It wears on you. It really does. And we want to deliver a product with Nova Lake that meaningfully addresses these criticisms.

Yeah, just pick one [CPU from Intel or AMD]. I’m not going to confirm anything else, but pick one. I think the Nova Lake product will do the job.

Roach: Okay. Well, that's good to hear. I have to imagine, especially with Nova Lake in particular, given how much they're, you know… There's probably a story on Videocardz or WCCFTech, probably a lot on Tom's Hardware every two or three days. So, yeah, it's a lot.

Hallock: Well, I think it’s reflective of how excited people are, how much anticipation, how much demand is pent up for this moment.

Roach: I know we're almost out of time, but I did want to share with you real quick. It was a big thing that we talked about this year at CES. Actually, I was talking to AMD PR, and they were getting reactions [to AMD’s new announcements]. And I told them, I was like, man, there is a Dark Knight sentiment. You live long enough to see yourself become the villain…happening right now in the industry. I think there's certainly a lot of that reaction that we've seen at least. So, for what that's worth…

Hallock: I have read those comments. Yeah. You know, a product like Nova Lake cannot address every single slice of the market. It just can't, given the current market that we're in. But I, I do hope and do believe that people will look back and go, ‘damn, you know, that was pretty, pretty freaking good.’ Yeah, that's what we were hoping for. And if Intel just keeps going, we're gonna be okay. And that's the trajectory we're on. That's who I want to be, as a business for gamers.

Roach: Yeah, I've heard you say that numerous times, which is encouraging to hear. So I appreciate it, and yeah, thank you so much for taking the time to do this. You know, I always enjoy talking with you, and I'm excited to see what comes next.

[Session ends]

Coming on the heels of Intel's $19.7 billion common stock offering from earlier this week, AMD on Thursday announced plans to borrow $4.75 billion through a new senior unsecured debt offering. AMD does not tie the proceeds to a particular project, saying they will be available for general corporate purposes, including potentially paying down existing debt. Meanwhile, the increasing capital intensity of the industry gives AMD numerous options to use the money.

"We intend to use the net proceeds from this offering for general corporate purposes, which may include the repayment of debt," an AMD statement with the Securities and Exchange Commission reads.

The offering comprises four tranches: $1.25 billion of 4.6% notes due in 2029; $1.50 billion of 5% notes due in 2031; $1 billion of 5.25% notes due in 2033; and $1 billion of 5.5% notes due in 2036. Their yields to maturity are 4.64%, 5.018%, 5.264%, and 5.532%, respectively, while spreads over comparable U.S. Treasuries range from 43 to 90 basis points, which indicates that the market is generally confident in AMD and is willing to lend it money at rates that barely exceed those of the U.S. Treasury. Moody's and S&P are expected to rate the securities A1 and A, respectively.

AMD did not disclose how it plans to spend $4.75 billion, but the additional money obtained at attractive rates gives it room to finance its increasingly capital-intensive business as well as cash for debt repayment and other corporate requirements.

AMD hardly appears desperate for additional money. At the end of Q2 2026, the company had approximately $13.1 billion in cash, cash equivalents, and short-term investments. AMD's debt totaled $3.2 billion, and only $875 million is classified as current, which means that the proceeds from the offering by far exceed AMD's current obligations. Meanwhile, AMD's business is becoming very capital intensive.

At the end of 2025, the company had around $12.2 billion in unconditional commitments, which include purchases of wafers and substrates, multi-year cloud-service agreements, software and technology licenses, and guaranteed obligations to third parties. Approximately $8.5 billion was due in 2026.

Also, AMD's working capital requirements are growing. Inventories reached approximately $8.47 billion by the end of Q2, while accounts payable climbed to $5.36 billion. AMD also spent $1.20 billion on property and equipment during the first half of 2026, compared with $494 million a year earlier.

If we were to speculate where AMD can put $4.75 billion, then long-term supply agreements for commodities like memory, logic production, or advanced packaging immediately come to mind. However, given the current market realities, $4.75 billion is 1.8x smaller than AMD's inventories as of late Q2 2026. Furthermore, an average long-term supply deal with a major memory maker now amounts to $7.14 billion (according to Micron's comments made in its recent earnings release).

That said, $4.75 billion may not be enough for AMD to make strategically important purchase commitments. Nonetheless, getting nearly $5 billion at attractive rates amid global undersupply of pretty much everything certainly gives AMD some additional flexibility to run its business.

Intel chief executive Lip-Bu Tan has invested $12 million of his own money in Intel this week as part of the company's $19.7 billion stock offering, indicating his confidence in the company. Meanwhile, Bank of America analysts view the capital raise as an indicator of management's 'increasing foundry conviction,' suggesting growing confidence in Intel's foundry prospects.

"The capital raise […] is still a good leading indicator of management's increasing Foundry conviction (vs. defensive balance-sheet action)," reads an excerpt from BofA's note to clients published by John Intel. "We flag the capital raise also aligns with the recent step-up in capex (for internal customer) and ongoing 14A progress, with further capex increase expected on potential incremental external customer wins (18A-P, 14A, advanced packaging EMIB-T)."

Indeed, it is hard to believe that Intel's management would raise almost $20 billion without a more or less clear plan on how to spend it. In fact, Lip-Bu Tan has said repeatedly that he would not authorize building capacity for external customers unless there was a customer commitment. Of course, at some point, Intel will need additional 18A capacity for its own products as well, but $20 billion is a lot of money, which may indicate that the additional capacity will be aimed both at internal and external clients. This is by no means a confirmation that a formal deal has been reached with a big customer like Apple, AMD, Nvidia, or Qualcomm, but it is at least an indicator of management's confidence in Intel's performance going forward.

In fact, Intel's $19.7 billion stock offering was several times oversubscribed and about 33% of investors who submitted orders received no shares at all, reports @FirstSquawk, which indicates great confidence in the company by regular investors. Apparently, Intel's chief executive, Lip-Bu Tan, was among the investors who managed to get $12 million worth of stock using his own money.

In March 2025, shortly after becoming the head of Intel, Lip-Bu Tan bought $25 million of Intel shares (approximately 1.04 million shares) through a family trust to hold them for five years as a required part of his employment contract. Since then, he neither bought nor sold his Intel stock, so the acquisition of $12 million worth of Intel shares is a significant deal.

"Overall, we view the raise as net positive given foundry scale and customer conviction driving longer term top-line and operational efficiency, more than offsetting modest near-term EPS dilution," the note by BofA reads. "We also flag positive read-through for both front-end and back-end packaging semicap vendors."

Intel CEO Lip-Bu Tan has revealed that new memory architectures — once thought a commodity business — are now strategically interesting and one of his pet projects, while speaking about the comeback of the American chip industry. He further noted that the memory industry is ripe for innovation, and also hinted at exploring ways to stack memory on top of a CPU.

After years of being a commodity, memory became a strategic asset in recent quarters and will likely remain one for a while, so suddenly, leading makers of 3D NAND and DRAM became highly profitable companies, something the Intel CEO is keenly aware of:  "I used to be, 'do not invest in memory because it is a kind of commodity business,' but now it has become different," Tan said. […] "There is a lot of new technology coming out. So, we are kind of looking at one of my pet projects, some of the new memory architecture. I think you just saw the news: I hired my good friend, Seok-Hee Lee, who used to run SK Hynix. So, you kind of know something that I am thinking about. We are not ready to unfold it."

Tan did not reveal anything about the pet project and did not even specify whether the project is one of his personally favored strategic initiatives at Intel, or an initiative in one of the companies that he has invested in. He did mention that stacking memory on top of a CPU could make a lot of sense, though did not elaborate. Tan's remarks also follow the revelation of an Intel XBM patent that does away with the silicon interposer of HBM.

" I think CPU and memory, I think there are a lot of ways we can really do stacking together," Tan said. "And also try to find some new architecture for memory. I think in some way the memory, a lot of innovation are not there. So, there is some really good area."

Not everyone in the industry remembers, but Intel started as a memory company in 1968 and was quite a successful memory maker until the eighties, when Japanese companies took the lead, and Intel had to exit the market completely after suffering severe losses. Since then, the company has attempted either to return to the memory market with NAND and Optane, or at least to capitalize on a new type of memory with RDRAM. In all three cases, the company abandoned its memory initiatives without incurring significant losses.

Given the current profitability of 3D NAND and DRAM makers, producing memory is certainly a good business again and will remain profitable for some time. However, to re-enter it, companies like Intel would need capital to build at least one fab, R&D to develop competitive process technologies, and time. While licensing a technology — assuming that a company has capital — is an option, we strongly doubt that at this point Intel may be inclined to invest capital in memory and not in its core products and foundry businesses. Furthermore, it is unclear how investors react to such investments given the fact that the company struggles to become a strong competitor in the foundry market and has exited 3D NAND and 3DXPoint/Optane businesses after failing to achieve strategic targets.

SK hynix has resumed investments in its fab in Dalian, China, which is operated by its Solidigm subsidiary, and plans to boost its output by 50% already in 2027, reports Sedaily. Coincidentally, the company is mulling listing some of Solidigm's shares on NASDAQ to raise capital, but to retain control over its North America-based subsidiary, according to The Korea Herald.

After SK hynix acquired Intel's 3D NAND and SSD business in 2021 and formed its Solidigm subsidiary shortly after, it suspended any expansions of Solidigm's capacity in China partly due to the memory market downturn in 2022 – 2023 and partly due to U.S. export controls that curb exports of advanced fab tools to China. However, as demand for solid-state storage is setting records in general and demand for Solidigm's high-capacity SSDs is exceptionally strong, SK hynix is reconsidering its capacity plans for the Dalian fab just in time for Solidigm's initial public offering.

Following a four-year pause, Solidigm has reportedly resumed investment in its Dalian facility in China this year. The company has completed construction of the second phase of the fab and is preparing to start installing production equipment as early as November, the report claims. The facility is expected to begin mass production of floating gate 3D NAND flash in the first half of 2027, if the report is accurate.

The second phase of Solidigm's fab in Dalian is reportedly designed for a wafer output capacity of around 50,000 wafer starts per month (WSPM). Combined with approximately 100,000 WSPM at the existing first phase of the facility, the new phase would boost Solidigm's NAND production capacity in Dalian by roughly 50%, to around 150,000 WSPM.

Late last year, the U.S. government granted SK hynix and Samsung annual licenses to ship semiconductor production equipment that contains technologies developed in America to their Chinese fabs through 2026, which replaced their previous open-ended Validated End User (VEU) exemptions. As a result, both companies can now upgrade their fabs in the People's Republic and even use new process technologies there.

Solidigm, for example, intends to start making floating gate 3D QLC NAND memory with over 200 active layers at its Dalian facility in the second half of 2026, which was made possible by the timely tool upgrades. The additional capacity will further increase bit output of the Dalian campus, which in turn will enable Solidigm to produce its 245TB-class SSDs due to be introduced in the coming months in decent quantities, sometimes in 2027.

Solidigm, which controls roughly a quarter of the data center-grade SSD market, is a crown jewel in SK hynix's portfolio as it makes unique products that are sold at a premium and are in high demand. Listing Solidigm on NASDAQ would enable SK hynix to gain capital (up to $7 billion, if unofficial reports are correct), but retain control over the precious asset. The money that SK hynix will raise should be roughly enough to expand Solidigm's capacity and increase output of premium data center-grade solid-state drives.

It should be noted that SK hynix did not officially confirm the Solidigm IPO plan last week, as its regulatory filing on August 5 said that Solidigm was considering various ways to improve its competitiveness, but the final decision is yet to be made.

Intel is set to raise $19.7 billion by selling new common stock in a bid to finance the building out of new production capacity, the development of next-generation leading-edge process technologies like 14A and others, and day-to-day operations. While the company does not assign money to a particular project, Intel needs to build capacity to land orders from large external clients, so capacity expansion will likely be a priority. According to Bloomberg, the share sale attracted $100 billion in demand.

Intel will sell 210,526,315 shares for $95 apiece through an underwritten public offering. In addition, participating banks have 30 days to acquire as many as 31,578,947 more shares at the same $95 price, minus applicable underwriting discounts. Should they exercise all their options, Intel could sell approximately 242.1 million shares altogether and increase the proceeds to roughly $23 billion. Without the additional shares, Intel expects net proceeds of approximately $19.7 billion after underwriting discounts, commissions, and estimated expenses. The transaction is scheduled to close on August 12, 2026.

Intel's market capitalization increased from roughly $90 billion last August to $491 billion at press time, so the time is right to sell some shares and raise some much-needed cash, as the company must compete against giants like TSMC and Samsung, which spend tens of billions of dollars every year on new fabs and advanced process technologies. Meanwhile, Intel's capitalization reached its all-time high of $673 billion on June 20, 2026.

Intel has not assigned the money it is going to raise to particular projects and says the capital can be used across the business, including for capital expenditures and working capital. The company is currently ramping up its Fab 52 in Arizona and is on track to start using adjacent Fab 62 when it needs to. In addition, the company still has to build its fab complex in Ohio, which is expected to cost over $100 billion when fully built, so it badly needs money.

In its risk disclosures, the company specifically mentioned Intel 14A — which is due to enter mass production in 2028 — and other advanced process technologies, manufacturing expansion required to support them, and the need to secure design wins and volume commitments from major external foundry customers. While Intel does caution that these long-term investments amounting to tens of billions may not generate adequate returns, it is impossible to land sizeable contracts from external customers without having production capacity readily available.

Interestingly, Intel also mentioned alternative financing arrangements, government grants, and the U.S. government's significant equity position in the company among relevant factors.

Apple used to be among a few companies willing to buy memory and other components worth billions of dollars under long-term supply contracts at fixed prices. But the artificial intelligence era represents a new reality with new purchasing champions, marking a tectonic shift in the high-tech world. Alphabet, Microsoft, Meta, and Amazon have purchase commitments totaling about $2 trillion, and a significant portion of these commitments are for memory, according to estimates by analyst Claus Aasholm. While the commitments are approximate, span many years, and should be generally taken with a grain of salt, they still reflect the direction the industry is moving.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

The mid-range CPU segment has become more competitive than ever, with both Intel and AMD refreshing their lineups and pushing aggressive pricing. In one corner, we have the Intel Core Ultra 7 270K Plus, an important reset for Intel that prioritizes class-leading productivity performance over efficiency, while also offering solid value. In the other corner is AMD's newly launched Ryzen 7 7700X3D, a more affordable, slightly lower-clocked alternative to the 7800X3D.

This faceoff is particularly interesting because the two chips take very different approaches despite costing about the same price. The Core Ultra 7 270K Plus packs 24 cores and excels in productivity workloads, while also delivering Intel's strongest gaming performance in years. The Ryzen 7 7700X3D, meanwhile, relies on AMD's proven 3D V-Cache technology to deliver gaming performance within 5% of the 7800X3D, although it trails significantly in single- and multi-threaded workloads.

While the Ryzen 7 7700X3D is aimed at gamers looking for X3D performance at a lower price, it faces stiff competition from Intel's aggressively -priced Core Ultra 7 270K Plus, as well as its own sibling, the Ryzen 7 7800X3D, which is often available for only a little more.

So, is AMD's gaming-focused approach enough to beat Intel's well-rounded Arrow Lake Refresh processor, or has Intel finally found the right balance of price and performance to reclaim the mid-range crown? In this six-round faceoff, we compare these two sub-$350 CPUs to find out which one comes out on top.

Features and Specifications: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

Taking a look at the technical specifications, it's clear that each chip adopts a distinct strategy for the mid-range market. While Intel has optimized its architecture for a higher core and thread count along with improved interconnect speeds, AMD continues to leverage its stacked cache to maintain gaming dominance on a long-lived platform.

The Intel Core Ultra 7 270K Plus is based on the original Arrow Lake-S family, utilizing the same microarchitecture that we saw on the 265K, built using TSMC’s 3nm process. It matches the flagship 285K with a 24-core configuration (8 Lion Cove P-cores and 16 Skymont E-cores) and operates with a 125W TDP. The chip can scale to a 250W Maximum Turbo Power (MTP), which is the maximum power limit that this CPU can consume for short periods when running at maximum turbo boost frequencies

Intel has also standardized several enthusiast-level performance tweaks for Arrow Lake Refresh, most notably a 900 MHz increase in die-to-die frequency and a 400 MHz fabric speed boost. It also officially supports faster DDR5-7200, along with 20 lanes of PCIe Gen 5 and 76MB of total cache. Possibly the only major concern with the Core Ultra 7 270K Plus is the LGA 1851 platform. With Intel's next-generation Nova Lake processors expected to launch later this year, the current platform will have a relatively short lifespan, restricting any future upgrade options.

The AMD Ryzen 7 7700X3D serves as a more affordable, lower-clocked variant of the 7800X3D, featuring the same eight Zen 4 cores with a peak boost clock of 4.5 GHz. Its primary architectural strength is its 104MB of total cache including 64MB of vertically stacked L3, which is specifically tuned to eliminate memory latency bottlenecks.

The chip is rated at a 120W TDP with a 162W Package Power Tracking (PPT) limit, though it frequently operates well below these levels during gaming. A major selling point for Team Red is motherboard flexibility as the 7700X3D can be used with existing AM5 motherboards (600 and 800-series chipsets), and AMD has committed to supporting the socket through at least 2029.

⭐ Winner: Intel Core Ultra 7 270K Plus

While AMD offers a more stable platform and superior gaming efficiency thanks to its large cache size, Intel’s hardware package is more comprehensive for the price. The 270K Plus offers triple the core count, significantly higher frequencies, and faster memory support.

Gaming Benchmarks and Performance: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

To evaluate the gaming performance of these two chips, we conducted our testing at 1080p resolution using an Nvidia GeForce RTX 5090. We used this setup to prevent the GPU from becoming the bottleneck, allowing each CPU's gaming performance to shine through. By removing the graphics card as a limiting factor, we can see exactly how the 7700X3D’s 3D V-Cache stacks up against the higher core count and clock speeds of the 270K Plus.

We used identical systems for testing. You can read more about our full system configuration in our Ryzen 7 7700X3D review and Core Ultra 7 270K Plus review.

Across a comprehensive 16-game geomean, the AMD Ryzen 7 7700X3D holds its position as the superior gaming chip, delivering a 174.3 FPS average. This represents a 5.3% performance lead over the 270K Plus, which produced a 165.6 FPS average. While Intel's latest flagship has significantly narrowed the gap compared to the original Arrow Lake silicon, AMD’s 3D V-cache architecture continues to provide a higher performance in the majority of tested titles.

Even when examining the 1% low frame rates, which is the perceived smoothness while gaming, the 7700X3D maintains a slight edge with a 118 FPS average compared to the 115 FPS from the 270K Plus.

AMD's stacked cache gives the 7700X3D a clear edge in games that are sensitive to memory latency. For instance, in Minecraft RT, the 7700X3D delivered 144.5 FPS average, dwarfing the 89.7 FPS produced by the 270K Plus for a massive 61.1% performance advantage. We see similarly dominant leads for AMD in F1 2024, where it leads by 30.4% (201.8 vs. 154.7 FPS), and in Final Fantasy XIV, where it holds a 21.7% lead (177.7 vs. 146.0 FPS). Even in esports titles like Counter-Strike 2, the 7700X3D maintains a comfortable 7.3% lead with 707.9 FPS over Intel’s 660.0 FPS.

Intel’s Core Ultra 7 270K Plus is no slouch, however, as it leverages its higher boost frequencies and the new iBOT runtime translation layer to take the lead in several games. Intel manages a win in Hogwarts Legacy, producing 135.3 FPS for a 9.1% advantage over AMD’s 124.0 FPS, a result directly attributed to iBOT. Team Blue also edges out victories in The Last of Us Part 1 with 175.6 FPS (6% lead) and Spider-Man 2 with 207.2 FPS (5% lead).

In many other modern titles, the two processors are essentially locked in a dead heat. For example, in DOOM: The Dark Ages, the 270K Plus delivers 200.4 FPS while the 7700X3D is right beside it at 200.0 FPS. The story is similar in Flight Simulator 24, where Intel's 120.5 FPS and AMD's 114.9 FPS result in a negligible difference during actual gameplay. These results indicate that while the 7700X3D is the more consistent gaming choice, especially in cache-heavy titles, the 270K Plus is a highly competitive gaming chip that delivers impressive results for its $300 price tag.

The biggest difference between these two architectures is noticeable when analyzing power consumption and efficiency metrics. Based on our 16-game CPU power geomean, the 7700X3D is clearly way more efficient, drawing an average of just 60.9 watts while gaming. In comparison, the 270K Plus consumed 107.3 watts on average, which is a significant 76.2% increase in power. This results in a massive gap in gaming efficiency where the 7700X3D delivers 2.86 FPS per watt, making it roughly 85.7% more efficient than the 270K Plus, which trails at 1.54 FPS per watt.

Intel does take the lead when it comes to raw frequency, with the 270K Plus maintaining an impressive 5,247 MHz average clock speed across our gaming suite. This is over 700 MHz faster than the 7700X3D, which averaged 4,505 MHz. Despite the much higher clocks and power draw of the Intel chip, its thermal management remains surprisingly competitive when paired with the right cooling solution. The 270K Plus averaged 59°C during gaming, though it still runs warmer than the 7700X3D, which stays at a cooler 55°C average.

When factoring in the cost of the silicon, the competition for the best bang for your buck is incredibly tight. The Ryzen 7 7700X3D provides a value of 0.53 FPS per dollar, narrowly edging out the Core Ultra 7 270K Plus, which sits at 0.52 FPS per dollar.

⭐ Winner: AMD Ryzen 7 7700X3D

The 7700X3D’s overall higher average frame rates and excellent efficiency makes it the more attractive option for a dedicated gaming build. Since raw gaming performance, efficiency, and thermals all favor Team Red in this category, the Ryzen 7 7700X3D takes the win for this round.

Productivity Performance: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

AMD's X3D processors are widely known for their gaming prowess. However, they have historically struggled to maintain the same level of dominance in productivity performance. The Ryzen 7 7700X3D is no exception, as its cache-focused architecture and lower clock speeds result in relatively weak single- and multi-threaded results.

In contrast, Intel has managed to maintain its standing in the productivity segment even when its gaming performance faced challenges. The 270K Plus is a productivity workhorse that is capable of delivering excellent productivity performance making it a standout choice for users who need a balanced system for both work and play.

In multi-threaded workloads, the performance gap between these two processors is pretty massive, primarily driven by Intel's higher core count advantage. Across our multi-threaded performance ranking geomean, the Intel chip delivers a score of 626 compared to the 272 produced by the 7700X3D, representing a staggering 130% performance lead for Team Blue. This level of parallel processing power places the 270K Plus in a completely different performance tier, making it more comparable to much more expensive flagship processors.

Individual benchmarks further highlight this lopsided victory for Intel across various professional tasks. In Cinebench 2024’s multi-core test, the 270K Plus scores 2,509 points, which is roughly 135.6% faster than the 1,065 points achieved by the 7700X3D. This trend continues in POV-Ray, where Intel leads by approximately 169.5% (15,697 vs. 5,823 PPS), and in V-Ray 6, where it maintains a massive 129.5% advantage (45,016 vs. 19,615). Even in intensive video encoding tasks via HandBrake x265, the Intel chip more than doubles the performance of its AMD rival, delivering 29.9 FPS compared to just 14.3 FPS for the 7700X3D. These results demonstrate that for heavy rendering or data-crunching workloads, Intel is the undisputed leader in this price bracket.

A similar trend can be seen when examining single-threaded performance, a crucial metric for general system responsiveness and applications that do not scale across multiple cores. In our single-threaded geomean, the 270K Plus scores 278 points, which is 42.5% faster than the 195 achieved by the 7700X3D. Specific tests like Cinebench 2024’s single-core benchmark show the 270K Plus maintaining a 39.7% lead over the 7700X3D (145 vs. 103.8 points), while the lead grows to a staggering 82.6% in POV-Ray’s single-core test (1,138 vs. 623 PPS). Even in audio encoding, the Intel chip finishes the Lame Extended task in 68.61 seconds, whereas the 7700X3D trails at 91.53 seconds.

⭐Winner: Intel Core Ultra 7 270K Plus

Ultimately, the 270K Plus simply blows the competition out of the water when it comes to productivity. While the 7700X3D is a highly efficient and specialized CPU for gaming, it cannot match the raw horsepower that Intel offers. For any user whose daily routine involves video editing, 3D rendering, or heavy multitasking, the 270K Plus is the obvious choice and should be the clear favorite for a multi-purpose system.

Overclocking: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

While both manufacturers provide tools to squeeze extra performance from their silicon, the Intel Core Ultra 7 270K Plus is built as an enthusiast-friendly, fully unlocked processor. The AMD Ryzen 7 7700X3D, on the other hand, is a more restricted processor designed primarily for out-of-the-box gaming efficiency.

For the Intel Core Ultra 7 270K Plus, overclocking is a centerpiece of the experience. As a fully unlocked K-series SKU, it offers users granular control over per-core voltages, power limits, and clock speeds via an unlocked multiplier. While these changes can be done by entering the BIOS, one can also download the Intel XTU (Extreme Tuning Utility) software to fine tune the CPU.

One of the most significant changes seen on Arrow Lake Refresh is that Intel has standardized several high-end performance tweaks including the 900MHz die-to-die frequency bump and the 400MHz fabric speed increase. This means users receive enthusiast-level interconnect performance without necessarily needing a premium Z-series motherboard. That said, Z890 boards are still necessary as they offer sophisticated tools for manual tuning and pushing the CPU to its limits.

In contrast, the AMD Ryzen 7 7700X3D follows the same path as previous Zen 4 X3D processors including a locked multiplier, which prevents traditional manual overclocking. Users are instead limited to automated and semi-automated features like Precision Boost Overdrive 2 (PBO2) and Curve Optimizer. PBO2 allows the CPU to dynamically adjust its frequencies based on available power and thermal headroom, while Curve Optimizer enables more advanced fine-tune voltage offsets for each of the eight Zen 4 cores.

While these tools can lead to sustained higher boost clocks, the sensitive nature of the 3D V-Cache stack leads to thermal challenges that limit frequency headroom. Thus, overclocking gains on the 7700X3D are often minimal compared to the flexibility offered by the Intel chip.

⭐Winner: Intel Core Ultra 7 270K Plus

The 270K Plus is a far more overclocking-friendly product. It offers a vast suite of features that AMD simply cannot match due to its architectural restrictions and locked multiplier.

Power Consumption, Efficiency, and Cooling: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

This is a crucial section of the faceoff as it highlights the most significant architectural divide between these two processors. While the 270K Plus prioritizes raw performance throughput, the 7700X3D focuses on extreme efficiency. This is immediately evident in their official power ratings where Intel specifies a 125W TDP with a massive 250W Maximum Turbo Power (MTP), while AMD utilizes a 120W TDP with a 162W Package Power Tracking (PPT) limit.

In synthethic multi-threaded workloads, the difference is quite evident. While running HandBrake x265 10-bit encode, the 270K Plus consumes an average of 226W, which is more than triple the 72W required by the Ryzen 7 7700X3D. A similar trend appears in VP9 encoding, where Intel draws 184W compared to AMD’s efficient 65W. Even in lighter tasks like single-threaded y-cruncher AVX workloads, the Intel chip requires 55W while the AMD chip stays at a modest 32W. Idle power consumption also favors Team Red where the 7700X3D idles at 19W and draws 22W during YouTube playback, whereas the 270K Plus sits higher at 29W and 38W, respectively.

When we translate these power figures into efficiency metrics, AMD’s lead tends to stay ahead in most traditional benchmarks. In Cinebench 2024, the 7700X3D produces 14.4 points per watt, significantly outperforming the 10.4 points per watt from the 270K Plus. In HandBrake x265, AMD achieves a superior efficiency rating of 5W per FPS , while Intel trails at 7.56W per FPS.

However, the efficiency scatter plots provide a more nuanced look at how performance scaling impacts total energy consumption. In the Blender Classroom scatterplot, the 270K Plus delivers a much higher performance of roughly 135 samples per minute, but it consumes over 33,000 kJ of task energy. In contrast, the 7700X3D finishes with only around 60 samples per minute but uses significantly less total energy at roughly 4,500 kJ.

The HandBrake x265 scatterplot shows a similar trade-off where Intel reaches 30 FPS but consumes over 55 kJ, while AMD provides 14 FPS at roughly 36 kJ. Interestingly, the Linpack scatterplot shows the 270K Plus reaching over 850 GFLOPS with roughly 11WHr of energy, making it slightly more efficient in terms of performance-per-energy than the 7700X3D, which delivers roughly 340 GFLOPS for 10Whr.

From a cooling perspective, the 250W MTP on the 270K Plus means that it requires a robust cooling solution, like a 360mm AIO, to avoid thermal throttling during extended all-core loads. The 7700X3D is far easier to manage, remaining remarkably efficient and manageable with a mid-range air cooler. While the 270K Plus delivers class leading performance, it does so by significantly compromising efficiency in heavy workloads compared to AMD.

⭐Winner: AMD Ryzen 7 7700X3D

Pricing: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

The Intel Core Ultra 7 270K Plus was initially introduced with a justified $300 price tag, but you'll now find it between $300 and $320. The AMD Ryzen 7 7700X3D made its debut just last month and carries a $330 MSRP, placing it right under the 7800X3D. Essentially, there is not a major difference when it comes to the chips themselves, however, the true financial divide becomes apparent when we look at the total platform cost.

The Core Ultra 7 270K Plus demands a more substantial investment to reach its full potential. While one can opt for a B860 motherboard, a compatible Z890 motherboard is necessary in order to access premium overclocking and tuning features. These typically start around $150-$200, and can go as high as $600 packed with premium features. To handle the processor′s 250W Maximum Turbo Power(MTP) during heavy productivity tasks, a high−end 360mm AIO liquid cooler ($100-$150) or a dual-tower air-cooler ($50-$100) is recommended.

In contrast, the AMD Ryzen 7 7700X3D offers a much more budget-friendly entry point. A solid B650 motherboard can be found for around $120-$150 and the chip can be effectively cooled with a modest $50 air cooler.

Unfortunately, both platforms are held back by the ongoing global shortage of memory, which has caused prices to shoot up significantly. Since both CPUs require DDR5 RAM, builders are stuck in a RAMpocalypse where a basic 32GB kit costs over $400. This extra cost is bad news for both sides as it cancels out any price advantage.

Overall, the lower upfront platform cost makes the 7700X3D a slightly more attractive option for users prioritizing their budget. Furthermore, the AM5 socket offers a clear upgrade path through at least 2029, ensuring that your motherboard investment remains viable for future CPU generations. That is not the case with Intel, as the LGA 1851 socket is expected to be replaced once the next-generation of Nova Lake CPUs arrive.

⭐ Winner: AMD Ryzen 7 7700X3D

Ultimately, while both the chips are available at a very similar price range, the AMD Ryzen 7 7700X3D is the smarter financial play for a majority of users. Its significantly lower platform costs, superior gaming efficiency, and guaranteed platform longevity provide a level of value that the more power-hungry Intel refresh cannot quite match.

Bottom Line: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

The Ryzen 7 7700X3D and Core Ultra 7 270K Plus are designed for very different users, even though they sit in roughly the same price range. Like previous X3D chips, AMD's latest processor is built with gaming in mind, using its large 3D V-Cache to deliver excellent frame rates while keeping power consumption impressively low. Intel, on the other hand, combines a 24-core design with higher clock speeds and platform improvements to create one of the strongest productivity processors in its class without giving up much gaming performance.

The final score is tied at three rounds apiece. AMD comfortably wins gaming performance, power efficiency, and platform value, three factors that matter a lot for buyers shopping in this price segment. The AM5 platform also provides a significantly longer upgrade path, allowing users to drop in future processors without replacing their motherboard.

Intel, however, deserves recognition for what it has accomplished with the 270K Plus. It delivers outstanding single- and multi-threaded performance, offers a fully unlocked overclocking experience, and narrows the gaming gap to just a few percentage points in many modern titles. If your workload includes video editing, software development, 3D rendering, or other heavily threaded applications, the 270K Plus is the obvious choice and justifies its higher power draw.

For everyone else, the Ryzen 7 7700X3D is the more compelling CPU. It offers faster gaming performance, exceptional efficiency, lower platform costs, and a future-proof AM5 ecosystem. Unless your workload regularly extends beyond gaming into demanding productivity applications, AMD's latest X3D chip is the easier processor to recommend.

⭐ Winner: Tie

More CPU Faceoffs

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The owner of what is claimed to be “the original engineering copy of the Intel 8080 rubylith mask” has shared a social media shout-out, looking for a skilled restorer. From the shared photograph, this important artifact from the history of computing looks like it would benefit from remounting and reframing. Hopefully, the hand‑crafted, large‑scale sheet of red film (Rubylith) has remained in good condition under glass, though. The framed artifact is likely genuine and original, as its current owner is thought to be related to Internet Hall of Fame inductee Dan Lynch, a pivotal figure in the early Internet’s success.

In you unfurl the tweet above, you can see Tom Lynch, a self-described arborist and the owner of an AI infrastructure startup, standing behind the framed chip artwork. Folks comment on the Rubylith looking just like the one that the Intel Trinity: Andy Grove, Robert Noyce, and Gordon Moore, were photographed beside in 1978.

Rubylith is simply an adhesive, peelable red film that found favor in graphic arts and chip design before designers went digital. Engineers could cut away parts of the film to define where light would be exposed during photolithography processes. Rubyliths would often be marked with pens, tape, and overlays, especially as designs were iterated and refined ahead of tape-out.

The Intel 8080’s primary architect was Federico Faggin, and it was manually drafted in the age before modern CAD. This human-scale draft is likely 100x magnification compared to the finished processor die. Even scaled this large, it would still be quite an intricate drawing as it had to map around 5,000 transistors, traces, etc., into an approximate 20- x 16-inch sheet. The commercial Intel 8080 release ended up being manufactured on a 6 μm silicon gate process. It originally ran at 2.0 MHz clocks, but later revisions would boast clock speeds up to 3.125 MHz.

Intel’s 8080 was an important 8-bit microprocessor for both the company and the advancement of personal computing. This 8-bit CPU was the one chosen for the Altair 8800, was the original target architecture for the CP/M operating system, and would be a big influence on the later x86 architecture. We also recently wrote how the 8080 bottlenecked the Space Invaders arcade design, unintentionally resulting in the space shoot-em-up’s thrilling increase in pacing as aliens were zapped from the sky.

An Intel patent application published on August 6, spotted by Patentlyze, describes an orbital data center architecture that moves some of the computing used to operate massive satellite constellations off the ground and into space. The architecture proposes a two-tier satellite network in which a small number of more powerful satellites in higher orbits manage large constellations of relatively simple satellites in low-Earth orbit, handling much of the computing and constellation coordination normally performed by data centers and network operations centers on the ground.

The application, US 2026/0230175 A1, is a continuation of an earlier Intel filing that was granted as US 12,542,604 B2 in February.

Intel’s proposed architecture is a different proposition from the orbital AI data centers now being pursued by companies such as SpaceX and Google, which aim to move AI compute itself into low-Earth orbit. SpaceX’s planned AI1 satellite and Google’s Project Suncatcher both envision running large-scale computing workloads in space, with the resulting data beamed back to Earth over high-bandwidth optical links. Intel’s orbital data centers, on the other hand, are designed primarily to serve the satellite network itself, acting as higher-orbit compute and control hubs for the much larger constellations operating below them.

In large LEO constellations such as Starlink, Telesat Lightspeed, and Amazon’s Project Kuiper, thousands of satellites are constantly moving relative to one another and the Earth. While the satellites perform their individual tasks, the network itself still has to determine how traffic is routed, which satellites and links should communicate, how spectrum is allocated, and how the constellation responds to failures, interference, weather, and other changing conditions. Much of that network planning and control processing is traditionally handled by computers on the ground, with routing and operational instructions calculated at terrestrial network operations centers and then transmitted back up to the satellites.

Intel says that this constant dependency on terrestrial infrastructure delays time-sensitive decisions, increases reliance on ground stations, and makes management harder as constellations grow into the thousands of satellites. Intel’s solution is to move part of that control and compute layer into orbit. Its architecture places more powerful satellites — which contain much more compute and storage capability than the individual LEO satellites — in Medium Earth Orbit (MEO), Geosynchronous Earth Orbit (GEO), or highly elliptical orbits, where they can maintain a broader and more persistent view of the LEO constellation below and take over tasks such as routing, mission planning, scheduling and network coordination without continually sending those workloads back to Earth.

The proposed setup does not eliminate the need for ground stations. It just keeps satellite network control processing in space. Intel specifically describes moving mission planning and scheduling operations into orbit. The company also argues that offloading heavier network-management tasks to a smaller number of powerful satellites could allow operators to build simpler, cheaper LEO spacecraft. Under current architectures, individual satellites still have to actively participate in network-control functions, requiring additional onboard compute and communications hardware. There’s currently no indication that Intel is actively building the satellites.

The requirements of AI clusters have made optical interconnections practical for scale-out connectivity, but as bandwidth needs increase, optical connectivity is becoming viable for scale-up connections as well. As a result, the industry is moving optical interfaces closer to CPUs and GPUs, from the front-panel transceiver to the package itself through co-packaged optics (CPO) — and eventually directly into the processor package.

Optical connectivity has been used for decades, since electrical links cannot efficiently and reliably transmit data over long distances at high data transfer rates. But the cost and complexity of optical components limited their use to long-reach connections.

Today, the importance of CPO is rising: Electrical interconnects are no longer scaling as quickly as AI processors, and feeding thousands of accelerators within a data center requires an exponential increase in communication bandwidth. In a traditional optical networking architecture, the processor or switch ASIC communicates electrically with a pluggable optical transceiver located at the front panel of a server or switch. As signaling speeds climb to 200 – 400 Gb/s per lane and beyond, however, transmitting electrical signals over long copper PCB traces on a motherboard becomes increasingly inefficient, causing higher insertion loss, greater power consumption, and tighter signal integrity requirements.

While technically possible, it demands the use of better materials, re-timers, complex compensation processing, and equalization circuitry, which increases the cost of server infrastructure and its power consumption. CPO moves optical engines next to the processor or switch ASIC to shorten the electrical path before signals are converted into light, which means lower power consumption per transmitted bit, increased bandwidth density, and predictable scalability. As a result, CPO is increasingly viewed as a necessary technology for next-generation AI infrastructure.

Because AI is viewed as a major megatrend, CPO is set to become ubiquitous; there are dozens of companies working in the CPO ecosystem, including foundries, OSATs, optical I/O startups, laser manufacturers, fiber suppliers, packaging houses, and networking vendors.

As there are so many vendors pursuing different goals with different strategies, for this story, we are going to limit ourselves only to companies that actually produce things and whose roadmaps reflect their technological capabilities. So far, only four foundries have publicly articulated meaningful CPO manufacturing strategies: Intel Foundry, GlobalFoundries, Samsung Foundry, and TSMC.

The four companies each represent four different CPO strategies and have very distinct plans for the future, so their visions and capabilities may not be directly comparable. Nonetheless, reviewing their offerings gives us an idea about where the industry is going from the perspective of actual foundries.

TSMC: COUPE for everything

TSMC has historically been absent from the optical connectivity market as a product supplier. But having worked on silicon photonics for many years, it now has the broadest ecosystem and manufacturing roadmap with its Compact Universal Photonic Engine (COUPE).

TSMC's silicon photonics technology roadmap currently has three stages that span from a 1.6 Tbps optical engine with conventional pluggable optics to a 12.8 Tbps optical engine located within a processor package. The COUPE roadmap is tightly coupled with the company's advanced packaging technologies and the evolution of the company's micro-ring modulators (MRMs) that adjust light and directly impact performance. As a result, several TSMC customers (e.g., Nvidia) plot their silicon photonics strategies around the evolution of COUPE.

The first phase of the roadmap — called COUPE on PCB — relies on a COUPE that bonds a 65nm electronic integrated circuit (EIC) with a photonic integrated circuit (PIC) using the company's SoIC-X bonding technology. The initial implementation targets OSFP (Octal Small Form-factor Pluggable) optical modules and delivers 1.6 Tbps of bandwidth (2x the throughput of copper Ethernet solutions, along with 2x the power efficiency). Therefore, the first-gen COUPE is out of the scope of this article. TSMC says the SoIC-X interface features very low impedance and enables lower power consumption at high signaling speeds.

The second generation — dubbed COUPE on substrate — marks TSMC's transition from conventional pluggable optics to co-packaged optics (CPO). In this stage, COUPE is integrated with the company's chip-on-wafer-on-substrate (CoWoS) advanced packaging technology and co-packaged with a network switch ASIC. This architecture enables motherboard-level optical interconnects with aggregate bandwidth up to 6.4 Tbps, 2x power efficiency, and 10x lower latency than existing pluggable solutions, which is fantastic for a variety of applications, such as NVLink, Ethernet, and InfiniBand switches.

The third phase — called COUPE on interposer — pushes silicon photonics even closer to compute dies: A 12.8 Tbps optical engine is integrated directly into the processor package to enable ultimate bandwidth and scalability. Beyond doubling bandwidth again, the company expects the architecture to offer 5x power efficiency and 20x lower latency than today's pluggable solutions. That will make it particularly attractive for hyperscalers that build clusters with thousands of accelerators. Unfortunately, TSMC characterizes this phase as exploratory and has not disclosed its commercialization timeline.

The main agenda of COUPE is to move the optical engine as close to compute as possible. There is another dimension in TSMC's silicon photonics strategy, however: the evolution of the photonic devices themselves, the MRMs integrated into PICs. The company plans to bring the world's first 200 Gbps/lane (wavelength) micro-ring modulator into production in 2026 and then continue scaling the technology with 400 Gb/s MRMs, additional optical wavelengths, and denser fiber-array integration. This evolution is expected to increase COUPE’s bandwidth density from 0.5 Tb/s/mm in 2026 to 4 Tb/s/mm by 2030, providing an 8x improvement over four years.

It is noteworthy that TSMC presents the MRM roadmap separately from the evolution of COUPE packaging, which suggests that advances in micro-ring modulators represent an independent technology roadmap for the photonic integrated circuit (PIC), rather than being tied to a specific packaging generation. This potentially means that future COUPE products could adopt newer generations of MRMs regardless of whether the optical engine is mounted on a PCB, package substrate, or silicon interposer — although the latter will probably deliver the greatest system-level benefits by minimizing the electrical distance between compute dies and optical interfaces.

Intel: Optics for CPUs, GPUs, DPUs, and accelerators

Intel has been shipping various products with optical interconnections for decades and even attached its silicon photonics solutions to Xeon and Xeon Phi processors in the mid-2010s. Today, Intel's public CPO roadmap is less explicit than TSMC's, but its direction is fairly clear: move optical I/O directly next to CPUs, GPUs, accelerators, and eventually other compute chiplets. Meanwhile, so far, Intel has not unveiled plans to use its CPO technology for switches.

Intel's CPO strategy is largely focused on its Optical Compute Interconnect (OCI) chiplet, which is a self-contained optical I/O subsystem packing both EIC and PIC that can be co-packaged with any compute device using a PCIe interface to enable high-performance optical connectivity. Intel demonstrated the first OCI in 2024. That prototype implementation used 64 PCIe 5.0 lanes at 32 GT/s in each direction to connect to the host and provided 4 Tbps of bidirectional optical bandwidth over eight fiber pairs over a distance of up to 100 meters. Each fiber carried eight DWDM wavelengths spaced at 200 GHz, and every wavelength (lane) transported about 32 Gbps (8 FPs × 8 WLs × 32 Gbps = 2,048 Gbps in each direction).

The 2024 OCI implementation is good for testing the technology, but with rather slow 32 Gbps lanes, it has not been adopted commercially. Meanwhile, this technology has already been proven and demonstrated. Intel is currently working on its next-generation OCI with 200G/lane PICs to support 800 Gbps and 1.6 Tbps applications, though it is unclear when it is set to be available, as Intel has not yet disclosed an equivalent to TSMC's MRM roadmap.

It should be noted that future OCI implementations supporting bandwidth of 10s of terabits per second could interface with compute dies using next-generation PCIe 6.0 interfaces or even native die-to-die UCIe links when integrated into commercial products. Furthermore, Intel can naturally integrate OCI chiplets using its advanced packaging technologies to ensure high performance and low power.

As noted above, Intel's focus with OCI has always been its integration with CPUs, GPUs, DPUs, accelerators, or other compute devices, but not necessarily switches. It remains to be seen whether Intel's next-generation AI hardware roadmap will include switching silicon, but for now, it does not seem that the company is targeting optical switches with its OCI chiplets. Since OCI is protocol-agnostic, limiting it to compute devices seems like an artificial limitation, though we have little indication about Intel's reasoning behind the decision.

Samsung Foundry: Addressing everything

Samsung Foundry's silicon photonics strategy is arguably the most comprehensive among leading foundries. Unlike Intel, whose CPO roadmap is focused on its OCI chiplet for integration with compute devices, or TSMC, whose COUPE optical engine is another major ingredient of its foundry platform, Samsung intends to offer all types of optical connectivity devices, starting from pluggable transceivers in 2026, to switch CPO later on, and all the way to optical engines on the interposer of a processor package in 2030. Unfortunately, Samsung does not publicly provide a lot of information about its plans, so our main source of information will be SF's slide from a conference published by SemiVision.

This year, Samsung Foundry intends to offer a merchant PIC platform that relies on an EIC and a PIC mounted side by side on a PCB for conventional pluggable optics. The PIC will support 100 Gbps-class optical interfaces using CWDM technology, which is good enough for traditional pluggable optical transceivers (though Samsung does not specify the exact implementation), so there's no indication of CPO here.

In 2027, Samsung Foundry intends to catch up with TSMC's first-gen COUPE and offer an optical engine that stacks an EIC on top of a PIC using thermo-compression bonding (TCB). Samsung expects energy efficiency of this generation to improve from approximately 10 pJ/bit for its initial PIC platform to 5 pJ/bit, though Samsung has said nothing about bandwidth or latency. Samsung's TCB-based OE seems to be an intermediate product between merchant PICs and true CPO, so it will generally address onboard optics and pluggable transceivers.

By 2028, SF intends to move optical engines to the substrate of Ethernet or InfiniBand switch ASICs, which will be its first true CPO. The company intends to adopt hybrid copper bonding (HCB) with 10 µm pitches for its OEs to improve bandwidth density. Based on the slide from the roadmap, to address next-generation switches, Samsung is poised to increase optical lane speeds from 100 Gbps to 200 Gbps and ultimately 400 Gbps, although the company does not disclose when exactly each speed bin will be introduced (though it looks like 400 Gbps will come in 2029 – 2030) as well as the underlying modulator technology or other device-level details behind this scaling.

In 2029, Samsung Foundry will finally integrate its optical engine on an interposer next to CPU/GPU/XPU or other compute device, which will reduce energy consumption to 2 pJ/bit while providing extremely high bandwidth. Samsung calls this 'CPO Turnkey,' which implies that such integration will require its own packaging technologies. The next step in Samsung's roadmap is called 'next-generation CPO Turnkey,' and it integrates virtually the entire optical subsystem — including lasers — alongside compute and memory, which will be its ultimate CPO offering expected by 2030 and onwards.

While Samsung Foundry's ultimate goal to offer highly integrated turnkey CPO solutions is clear, the company also intends to offer two merchant platforms for pluggable optical transceivers, perhaps to de-risk development of its future products and to capitalize on the high demand for optical connectivity that exists today and will continue going forward.

GlobalFoundries: A bespoke vendor-agnostic OCI-MSA CPO platform

Unlike Intel Foundry, Samsung Foundry, and TSMC, GlobalFoundries does not produce or intend to produce AI processors, switch ASICs, or advanced packages. Instead, it aims to become a merchant co-packaged optics provider that will produce and sell bespoke CPO solutions that enable optical connectivity (including OCI MSA connectivity) for processors made by other chipmakers.

GF's silicon photonics effort dates back to the IBM Microelectronics acquisition in 2015, which brought IBM's silicon photonics technology and engineering teams into the company. Over the years, GlobalFoundries has expanded its silicon photonics capabilities into what eventually became the GF Fotonix platform and, more recently, the company acquired AMF and InfiniLink to further strengthen its production and design capabilities.

The key element of GlobalFoundries' CPO strategy is its Silicon photonics Co-packaged Advanced Light Engine (SCALE) platform that combines photonic IP, advanced packaging technologies, and a reference optical engine architecture that includes EIC and PIC. Unlike Intel's OCI chiplet, SCALE allows GF's clients to customize optical engines in accordance with their needs and have them manufactured by GF.

Under the program, GlobalFoundries manufactures the PIC and EIC using its own process technologies and then packages them into an OCI MSA-compliant optical engine using its methods. If the EIC requires a leading-edge node that GF does not have, it could instead be fabricated by another foundry and then integrated by GF. Customers then co-package the optical engine alongside their own switch ASICs or AI accelerators.

For now, SCALE supports both CWDM and DWDM transmission using qualified 50 Gbps and 100 Gbps MRMs, integrated photodiodes, and coupled-ring resonators. The platform has demonstrated bidirectional operation with up to 16 DWDM lanes per fiber, which theoretically opens doors to optical links with up to 1.6 Tb/s of bandwidth per direction. On the integration side of things, it supports advanced 2.5D and 3D integration using TSVs and copper bonding with pitches ranging from 110 µm to below 45 µm, which is good enough for integration using CoWoS-S and CoWoS-L technologies.

Just like Intel with its OCI, GlobalFoundries does not necessarily tie its SCALE CPO customers to its silicon or packaging technologies. Furthermore, the company allows its clients to customize their optical engines while retaining compatibility with the OCI-MSA requirements.

The future of CPO

Co-packaged optics (CPO) is set to become a key technology for next-generation AI infrastructure as conventional electrical interconnects struggle to keep pace with the bandwidth demands of rapidly developing AI processors.

Among foundries, TSMC, Intel, Samsung Foundry, and GlobalFoundries have each developed distinct CPO strategies that range from merchant optical engines to optical I/O chiplets and vertically integrated CPO platforms.

Given the different capabilities of the contract chipmakers, their roadmaps differ significantly in both scope and implementation, with some companies trying to lock in customers with a proprietary platform and others offering different degrees of freedom.

However, they all share the same objective: move optical interfaces progressively closer to compute dies to reduce power consumption, increase bandwidth density, and lower latency for the next generation of AI systems that will require considerably more bandwidth than today's clusters.