“Going forward, 10nm products like Raptor Lake; that is a core part of the portfolio that I want to offer to people for years to come,” said Hallock. “LGA 1700 is still a good socket. Lots of people [are] still interested in DDR4, so [we’ll] keep offering, and you'll see [pricing] smooth out over time. It'll come back to normal. That's the plan.”

Raptor Lake has become a key part of Intel’s roadmap as the RAM shortage strangles budget builders from upgrading to a DDR5 platform. In June, Tom’s Hardware first reported on motherboard manufacturers increasing production of DDR4-based boards with the LGA 1700 socket (the socket Raptor Lake CPUs use), and we’re seeing those products roll out now. Just days ago, in fact, Gigabyte introduced a new LGA 1700 board with DDR4 support.

Motherboards were one issue with Raptor Lake on DDR4 platforms; there were never a ton of LGA 1700 motherboards with DDR4 support to begin with. They were something of a stopgap with 12th-Gen Alder Lake CPUs as Intel transitioned to DDR5, largely falling out of favor (and inventory) as Raptor Lake rolled out and DDR5 prices started coming down. Obviously we’re living in a much different world now.

But as the DDR5 pricing crisis started hitting, Raptor Lake inventory started faltering, in part due to increased demand (at least according to Hallock), and likely also in part due to the gradual phasing out of older products. Today, the pricing situation with Raptor Lake is problematic. The Core i5-14600K, for example, sold for $200 or less for the better part of last year. It’s since jumped to around $250, if you can find it in stock at all. At the time of writing, it’s on backorder at Newegg and $262 at Amazon. Similarly, the Core i7-14700K should be selling for around $330, but it’s $380 at Newegg at the time of writing and sold out at Amazon. Again, for the majority of last year, the 14700K often sold for less than $350.

This wobbly inventory and pricing situation is due to the “sudden inrush of demand” for Raptor Lake CPUs as the RAM pricing crisis started to take hold, and Intel didn’t see it coming. “If people are going to go to more affordable hardware, they still want the fastest available for their money, and that happened to be Alder Lake and Raptor Lake. So there was a sudden inrush of demand into these parts — certainly not anticipated when you start your wafers, and your builds, long before that moment ever happens. So it's very hard to predict,” Hallock said.

And Raptor Lake CPUs do remain top DDR4 performers. In our recent re-review of the Ryzen 7 5800X3D, the Core i7-14700K and 13700K matched the 5800X3D in games, all three of which were using DDR4, and offered much better application performance. In our recent comparison of DDR4 against DDR5 across Intel’s LGA 1700 stack, we found that DDR4 is the major bottleneck in games, which is something even the 5800X3D can’t overcome.

Hallock indicates that we’ll see an increase in Raptor Lake inventory, though he didn’t specify what that inventory will look like. As Tom’s Hardware first reported in June, motherboard vendors are gearing up for “Raptor Lake Next,” which is supposedly another slate of refreshes set to launch at the beginning of next year. There are also Bartlett Lake processors that use strictly P-cores, exclusively for embedded applications. Although they haven’t made their way to DIY desktops, the range shows that Intel continues to produce 10nm products and likely will for several years in the future.

Although Intel is making efforts to improve Raptor Lake supply — be that through more stock or Raptor Lake Next — that isn’t coming at the cost of next-gen Nova Lake parts. Hallock indicated that Intel, as well as the industry more broadly, is looking at splitting mainstream and enthusiast offerings due to pricing pressure elsewhere in the market. You can read the transcript of the full interview at our Tom's Hardware Premium site.

The following is a transcript of our interview with Hallock, which has been lightly edited for flow and clarity. We hope you enjoy this unredacted look, exclusively available to Tom’s Hardware Premium subscribers. You can also catch session transcripts from earlier in the year, featuring Intel, AMD, Nvidia, Valve, and more.

Jake Roach (Senior CPU Analyst, Tom’s Hardware): I appreciate you doing this outside of a typical product cycle.

Robert Hallock (VP & GM Enthusiast Channel Business, Intel): Of course.

Roach: I really just wanted to get your read on a lot of things because things are crazy in the enthusiast desktop space right now.

Hallock: They are.

Roach: So, how are things going in enthusiast desktop land given memory shortages, NAND shortages, everything going on right now?

Hallock: I think the market's experiencing a tale of two kingdoms. Yeah. For the folks who have a significant amount of discretionary budget, they can absorb the cost impacts of what's going on in the industry, and most other people cannot. Right? And that's having a very different impact, as you can imagine, on different parts of the market. Low-end mainstreams really taking a beating. Enthusiast and premium, not so bad. You could, depending on the device class, maybe even be growing positive. So it's a very starkly divided market at the moment.

Roach: I guess I hadn't heard that kind of take on it before. I guess it makes sense that you have more discretionary spending, or if you already were kind of invested in a certain ecosystem. I haven't heard that before.

Intel’s flexibility in the consumer market

Roach: I'm curious about the position of Intel right now. There's AMD, Intel, and Nvidia, right? And you've seen a kind of big shift for AMD and NVIDIA. Nvidia doesn't even break out gaming as a business category anymore; it's embedded now, and I think AMD is now coming up on close to double the data center revenue that they have from their client business. But for Intel, the majority of your revenue still comes from the client business. Does that put you in kind of a unique position right now with so much focus on the data center?

Hallock: I think that it does. I like to believe that it does, and I'm hoping, selfishly for myself, that it does. One of the things that I believe that Intel, that people truly sleep on about Intel when talking about the big fight of this company versus that company, just how big Intel is, how many resources Intel has. As I look at, for example, you know our desktop enthusiast roadmap, I don't have to trade supply with a data center part; I don't have to worry about it. I don't have to think about it.

I can build a roadmap and a plan for the market that is sized against purely what is going on in the client market. And that kind of freedom is very empowering when you're trying to run an enthusiast desktop business for enthusiasts, and it doesn't mean that we're immune to what's going on in the market. It doesn't mean we're immune to supply fluctuations upstream of us. That happens too, right? But at a fundamental level, I can sit down with my team and my partners and build a plan for a product for the year, and not have to worry about what's going on with Xeon, as an example, and vice versa, right? That's their luxury too, right? I can do my thing in client land, and they can do theirs in data center land, and it's okay. And so the size of Intel is what allows that to happen. And at it is at its best, it allows us to maximize the investment and the return on multiple product categories. It's a nice one that works out that way.

Roach: I think it's been maybe a few earnings calls back. There were some mentions in a couple of earnings calls about wafer allocation moving toward the data center to meet demand for Xeon. But you're saying that's not really a concern when it comes to future launches.

Hallock: No, and so, just to give a little inside baseball. It depends on what era you're talking about. If we're just coming into the sudden AI boom, where prices are multiplying very, very rapidly. That was a surprising moment for everyone in the industry. Like we kind of felt it coming.

We heard the rumors, but the size and scale were very abrupt. It was immediate. That is still surprising. It was immediate, and in those cases, yeah, you’re probably going to have to trade some supply around. But once you’re in, like once you’re in it, now you know the plan for it.

Roach: Okay, so that was a temporary measure, gotcha.

On Intel’s enthusiast roadamps

Roach: So, shifting back to the desktop, I know you've mentioned several times about this ambitious enthusiast roadmap, presumably that centers around 18A and Nova Lake. So far, what we've seen out of 18A has been more premium offerings. Obviously, we have Panther Lake; we have Wildcat Lake. Wildcat Lake [is] not a premium offering, but it makes some pretty big concessions to reach that budget price point of single-channel memory and all of that. So I'm curious, given that there is such a large divide between this enthusiast premium category, this budget category, do you think that the DIY PC market can be served by a single product stack, especially on this kind of cutting-edge node?

Hallock: I truly believe that what the market is going to see going forward, and this is just an industry-level comment, is, and I want to stress this is not just Intel...You're probably going to see a split. You'll have a premium socket and a mainstream socket from everybody. If you're playing in desktop space, that is probably what you'll do because the supply chain costs, the upstream costs, have the same costs that are currently harming the entry-level and mainstream market; I don't see those abating anytime soon, right? And so it means that in order to continue providing affordable computer hardware, you're going to have to make some design concessions.

You're going to have to make some concessions in your product stack, and that's purely to control costs and give people an option that they can actually afford. Otherwise, if you don't do it, the other alternative is it just disappears because it's unaffordable. So, seeing a split is likely the outcome for everybody.

Roach: I was telling Thomas yesterday when Gamer Days first came out, I think there was a day when the Core Ultra 250K Plus was $150. I’m like, ‘Man, at that price, that is one hell of a deal.’

Hallock: Hell of a CPU? Yes, it is.

Roach: So obviously we have Arrow Lake Refresh. Arrow Lake Refresh is great, very positive reception. But we've also seen this… One of the stories we really heard a lot from the motherboard guys at Computex was spinning up older DDR4 boards with LGA 1700. I think Gigabyte just reintroduced one a few days ago, and that's great to see because there weren't a ton of those boards even when Alder Lake launched.

But, one of the things that has been concerning for me – covering CPUs – is a lot of volatility in pricing on 13th- and 14th-gen processors, oftentimes selling for much more than comparables from AMD or even for certainly from from Arrow Lake. I'm wondering: are there any plans to maybe improve supply, or some sort of effort to stabilize the pricing of those so it's a bit more consistent?

Hallock: Well, I think what you're seeing is the fact that those 10nm parts are still phenomenally good. We don't spend a lot of time talking about them in the media or at Intel. It's old stuff, and we've all moved on. But they're still phenomenally good CPUs. And if you look at the sort of bucket of options that you can buy for these older DDR4 platforms, it is very likely that Alder Lake or Raptor Lake are the fastest of the bunch in that mix.

Roach: They are. I just recently did a whole DDR4 vs DDR5 article.

Hallock: And so what you're seeing is just like if people are going to go to more affordable hardware, they still want the fastest available for their money, and that happened to be Alder Lake and Raptor Lake. So there was a sudden inrush of demand into these parts that was certainly not anticipated when you start your wafers and your builds long before that moment ever happens. So it's very hard to predict. But going forward, 10-nanometer products like Raptor Lake – that is a core part of the portfolio that I want to offer to people for years to come. LGA 1700 is still a good socket. Lots of people are still interested in DDR4, so keep offering. And you'll see it smooth out over time. It'll come back to normal. That's the plan.

Roach: Yeah, it was really interesting going back because obviously with Alder Lake’s launch, there was a bunch of discussion about DDR4 versus DDR5, but seeing how it scaled all the way up to 14th-gen. You have the 14700K with DDR4 at parity with a 5800X3D in gaming, and obviously much faster in applications. So yeah, I’ve been hoping for a $300 14700K that I can recommend to people.

On Intel's approach to AI in the enthusiast segment

Roach: I wanted to shift a little bit away from desktop. I know that is your, well. I guess maybe not desktop, but the kind of traditional view of just a single-socketed processor. Intel has this kind of breadth of IP, great graphics IP, lots of experience with memory and advanced packaging. And honestly, it's been surprising to me that we haven't seen what I like to call the 'big chip’ out of Intel yet, a consumer 'big chip' out of Intel. Between Strix Halo, I guess Gorgon Halo now, the M-series from Apple, and of course RTX Spark. I appreciate that that's not directly under your purview, but do you think that's an important area of the market, or is this a way to kind of capitalize on this sudden rush in demand for kind of these AI developer workstations?

Hallock: Tricky to say. I'm not sure about that part of the roadmap, but it's an interesting place because in a before time, a big integrated graphics device would have been pitched for gaming, right? It would have been pitched for gaming.

And the market has not always responded positively to that sort of setup, like whether or not the performance is right or the power is right, and oftentimes it's better than the CPU plus discrete option you can get for the same price and the same power. It's better.

Just, there's something about it people just don't take it, and then this whole AI thing came along in a real way – the agentic AI component of it – and certainly renewed demand for that kind of hardware. Now, does that sustain? I don't know. Do people come out of this seeing the value for gaming again – that I also don't know. But you know, we are looking at it, we are exploring it. It's certainly an interesting part of the market. A lot of excitement. People love to talk about it. But interestingly, I don’t think the actual run rate is all that high. So, it’s something we’re cautious about.

Roach: I will tell you every single event I have been to where they've had one of these agentic 'buy your box and run an agent forever’ demos, I don't think I've ever seen a single person actually sitting and watching one of those demos. I don't know what that says, but interesting to note.

Hallock: Just on AI software in general… It's an evolutionary process. Businesses can absolutely benefit now, like Intel has. I personally have agents running for me at work to do processes that honestly took a lot of my time. Sure. And now they're completely automated, and I just have to fact-check them, and that's great. I've saved a lot of time doing this, but you know, the transition to an average consumer – I don't know if we're there yet, right? We're not there yet, and I suspect that's probably informing the demo interest. But it is also a bit of a chicken-and-egg thing.

If you are not AI-aware or AI-ingrained, if you haven't just been dunked in the AI bucket because of your job or your profession or whatever, it is difficult to imagine what you could use it for, right? So now you're caught in this trap, 'well, I've heard about it, I don't know what I could use it for, but then I can get my hands on it, and now I don't know what to do with it.' It's like learning a search engine when we all had to do that, right? But on steroids.

Roach: It’s funny having conversations with friends and people who aren’t in this world because… recording and transcription, right? Like, that’s a super great use case of just, I mean, it’s not even an agentic or an advanced thing. I’ll explain that to them. They’re like, ‘Oh, that’s a great use case.’ I mean, for most people, AI is the sloppy AI images and things like that. That’s AI. They see no other use case for it.

Hallock: That's the great injustice in this industry, right? There are so many things that we all call AI. They all have the same name. And some of them are just like a sticker on a toaster, and some of them are legitimately useful, and they run on your computer, and you have custody over your information and your privacy. That's not bad, but that's quite a spectrum. Yeah, one word, and it's such a shame.

Roach: It is a shame too. With the hardware advancements, it's a bummer being at Tom's Hardware, being mostly a consumer-facing brand, and talking about things like Vera, things like Venice. I'm sure later this month, things like Diamond Rapids. You know, and all that stuff is very interesting from a hardware perspective.

Challenging AMD with new consumer hardware

Roach: I was interested to hear your perspective on this. I was at Advancing AI last month for the Venice launch, and I don't know how long it's been, but it's certainly been since Ryzen, since the original Zen, that AMD's leading with Zen 6 in the data center instead of on client. I just wanted to get your reaction to that.

Hallock: I think it's a natural reaction for them. Makes a lot of sense. What I would say is, as we think about our own roadmap, I have a new core. *chuckles* It's coming to desktop first. I hope enthusiasts do the math about that one, and… That's all I'm going to say.

Roach: Okay, perfect. I would expect no less of a diplomatic response, but I appreciate the response nonetheless. That is, it is exciting to hear that there's still a focus on consumers, because I know for GPUs especially, but even some questions with CPUs about, are we even going to get new hardware? Like, is that a thing?

And I think this goes to a bit of an extreme that all of our local compute's going to wither away, and then it's all going to be cloud instances or whatever that we rent from some data center somewhere. I don't think that's the case, but it is encouraging to hear that there is at least some focus on launching new enthusiast products. I'm wonderi–

Hallock: Not just some focus; I have new CPUs all the way out to 2030. I have a back-to-back-to-back-to-back cadence for gamers, for desktop built for that purpose. Obviously I can’t go into what any of that is, but I’m accelerating for the gaming market. We are moving faster than we ever have in product and release cadence. We’re very serious about this.

Yeah, I understand people are skeptical after the last couple of years. I truly get that. But the signal Intel is trying to send is like… We’re gearing up for one of the most significant desktop CPU launches we have ever had.

We took a team that was time-shared with other businesses. And now this slice of the market has a full org structure inside Intel, and if you're not in corporate America, what that means is the company is so serious about it. They're putting real people, with a lot of budget behind it, right? And having an owner, a sponsor, people that care about it, looking after it – custodians of that work – it makes a real difference.

Just... The difference between Arrow Lake and Arrow Lake Refresh. That’s the difference.

Roach: Oh man, that was a big difference. Oh. Different teams on those? Okay, I hadn’t realized because when we talked about Arrow Lake Refresh, it was… You had made mention of like ‘Hey, we’ve updated our roadmap, and this is our first, maybe peace offering after Arrow Lake.’

But I didn’t realize it was a completely different, or not completely different, but a different team.

Hallock: Yeah, well. Pretty much completely different. Marketing people, different product managers, different business people, and simply, we have a different philosophy on how this market should run, and what people should get for their dollar. And I’m glad that people appreciate it.

A post-Arrow Lake shakeup

Roach: Okay, so there was a big shakeup after. That was one of the questions I had. What were the key takeaways from Arrow Lake? But it sounds like those takeaways were addressed immediately.

Hallock: A couple takeaways that you saw manifest in the [Arrow Lake] refresh launch: The software experience for DIYers, which nobody likes to admit that we all need software for our CPUs because they all have a lot more cores than any game typically expects these days. And so the resilience of that software experience. How do people obtain it? How do they install it? How can they validate your performance? How can they verify that they're getting what you are promising? All of that was kind of open-loop in the Arrow Lake original timeframe.

We had some aspects coming from motherboard vendor websites, some from Windows updates, some from Intel.com. It's too complicated for people, so that directly led into the Intel platform performance package- like, kind of crazy- but put all your useful bits in one spot and tell people to download it.

Well, when you lose sight of this enthusiast DIY space and how people consume software and hardware in this part of the market, it's easy to get turned around. OEMs have a very different strategy. They go through these massive validation efforts and have huge QA labs and can set up a system image with point releases, and… Normal people don't have those resources.

You have to make it very easy for them. So, software resilience was a big one. And then when you look at a pile of IP, some engineer says, ‘Hey, your CPU can do this to this.’ That's your range of capability, and inside you open the box. You've got some stuff you can smudge around, like frequencies or voltage or core counts or specs on and off. You can decide to remix those very differently too. You decide to price it differently.

So what you're seeing is Intel got healthy on its software foundations for DIYers. Intel got healthy on its respect for performance per dollar for customers. We set up some really healthy internal processes for future platforms. Arrow Lake was a tough, tough lesson to learn, but a good one, because it drove some really, really useful changes inside Intel.

The importance of CPU software optimization

Roach: You've really beaten the drum on the importance of software; software is just as important as hardware. Just this past week I was testing out the BC-250. If you're familiar.

Hallock: Yeah.

Roach: The PS5 APU that was repurposed. And if you need a crash course in the importance of software to a gaming experience, just boot up one of those things. But can you explain, from your view, what the importance of software is, especially given Intel's… This is pretty ancient history at this point, but you know, use of specific compilers and things like that. What is your view about the importance of software to an overall performance package?

Hallock: I am scared to open this box, lest I get misinterpreted. So, here’s the deal. From the perspective of a software developer, it's actually really tough to be a professional software developer, especially if you are not self-publishing, especially if you have a publisher breathing down your neck. Because it means that your publisher is picking the release time, not you.

That's time crunch number one. Time crunch number two is… What hardware are we targeting? What CPU do I have at my desk as a developer? What does our QA lab have? What has the publisher allowed us to buy with our budget for QA? What does my historical install base look like for other games? And every time you open the box on any of those, you find more subdivision of compatibility that you need to worry about. That's time crunch number two.

Time crunch number three is, did you start on a console, or did you start on PC? Which were you targeting first? Probably console. So now you have to do a port, which is a time crunch. Some publishers outsource this. There are companies that all they do is console ports to PC.

Roach: A lot of Sony games.

Hallock: You know, I’m thinking of Nixxes. What a great developer! They've been amazing over the years at doing these kinds of ports. So all you're really doing is budgeting a decreasing amount of time as a dev, and then you're like, okay, well, my game has to run on a CPU anywhere from four cores to, gosh, like 32 threads, 24 threads, depending on the vendor. It's a lot.

And so what ends up happening is they just draw a line in the sand. This is the hardware we have in QA. This is what's on my desk. This is what's in the console, and that's what we have time to look at. And maybe we'll look at other stuff later. And a lot of the time, one thing that many gamers still don't quite understand is, like, it's not even really the Windows scheduler or the OS scheduler that's determining how these CPUs get used when you're running a game-they have their own layer.

It's called an affinity mask, and they tell the OS how to use the CPU. So the game is in control of how to do the scheduling, sending all these hints to the operating system. What if those hints are wrong? What if those aren't the right hints for the CPU you have in the socket? What if the game is newer than your hardware, or substantially older than your hardware? Or the developer never looked at your combination?

These are all moments where the game can easily give up huge chunks of performance, or just not run. And everybody has to deal with this, right? Every CPU vendor has to address these challenges somehow. We call it the Intel Platform Performance package; AMD calls it the chipset driver.

Right, we've all got this, and it's so important because it can reach into the operating system, or reach into the application, or reach into the firmware of the CPU itself, and make those real-time adjustments to get the performance back. Gamers would not like how this industry looks without this software from the CPU vendors. It would be a much, much less performant, much slower, higher frame time, more stuttering, sort of environment.

Roach: Yeah, it’s already quite surprising to deal with.

Hallock: Yeah, software cannot replace the CPU, and that is not what we're proposing, right? We're not saying, 'hey, I'm going to give up 10% on the hardware and give you 10% back on the software because it's cheaper.' No, I want 10% of both.

That it’s not trade; it’s both. And that is why we’re interested in pursuing it, and why I think it’s so important, because I’ve now spent serious time at two processor companies and have seen the performance gains that come from this kind of software, and what they contribute to the experience, including my own gaming system that I’m talking to you on right now.

And so, that’s why I’m big on software, because the performance would be much, much worse without it – not insurmountably, but it would functionally limit the kind of hardware that you can produce if everything has to fit in this lowest common denominator of software. That’s the other outcome, and that would be even worse. We cannot have the hardware be stagnant because of the software.

Roach: Gotcha. Yeah. That’s certainly giving up. It’s not the 10% hardware for 10% software. Leaving stagnant software gives up a lot more.

Hallock: That’s right.

Roach: Yeah. You know, we did a story probably a couple of days ago. This guy who, we call him a hardware researcher, but he really just does memes. He made a C compiler that would compile completely with Move and Assembly, and then he made a leaderboard of… it was the x86 Hall of Shame, where he tried to find a single assembly instruction, how to make it run as slow as possible, and he got one up to 189 billion cycles.

Yeah, it was ridiculous. He basically found the two slowest areas in the fabric, the two highest-latency areas in the fabric. Ran the instruction on one of them, and then had the other one make a bunch of frivolous four-byte reads, and like lock it up. Yeah. Anyway, just a great example of how you can make hardware–

Hallock: What people don't understand, every CPU architecture is like the fine art of intelligent compromise, and it's like, okay, well, just as like a random example, could you make the read and write link the same size? Sure.

But what if the reads are like 10 times more common than the writes? Do you really need them to be bidirectionally the same size? Like it's going to show up on a micro benchmark. Someone's going to complain about it, but in real performance, day-to-day, do you actually need it? Yeah, probably not. And there's stuff like that all over a modern CPU based on decades of just, like, learning how people are likely to use this thing; it actually does shape the microarchitecture itself somewhat, like a reflexive principle, right? We speak it into existence by using our processors in a certain way. It's fun.

Checking in on IBOT

Roach: On software, I think I'm probably much higher on IBOT personally than you know. We've seen some interest in it. We did some testing for it. I think it's this thing that probably becomes more important as time goes on. I'm just wondering how it's going. We've had one update, I believe, one game update. I just wanted to check in on how IBOT’s coming along.

Hallock: Going well. You know, we continue to work on multiplayer support, which was kind of in the initial scope. It's taking, I think, longer than the public may have expected, because we certainly do not want people to get in trouble using this technology. And that means you have to talk to a lot of people to do it. We're actively working on non-gaming workloads.

We are working on another upcoming release. I don't have the exact date for this, but we're working on the bits for the next update. And then we're also thinking about, for Nova Lake, you know, what is version 2.0, for lack of a better phrase? What do we want to build into that release based on the new hardware capabilities? Which I know is both some details and not a lot of details, but it's very important to us; it is a long-term, permanent aspect of our roadmap.

Roach: Yeah, I think the game selection has been interesting to see. Obviously, when we spoke around Arrow Lake refresh, you had mentioned, ‘Hey, there's going to be a lot of games where there's no benefit whatsoever, or a lot of workloads in general where there's no benefit whatsoever. We just want to improve where we can.’

I'm curious how you go about finding those improvements, because surely it can't be just throwing everything at the wall and seeing what sticks.

Hallock: No, well, sometimes it is. Okay. Sometimes it is. It’s a multi-part process. We do have a team that proactively goes out and evaluates things that are very popular, high profile in the community. Just because it's so obvious to go grab those and take a look. We also have automated systems that go through workloads and try to find opportunities. That does a lot of heavy lifting. Dirty word, but we have AI tools that can also help us analyze and find opportunities. So it's one part manual and a lot of automation to find these, and we go from there.

Adressing Nova Lake rumors

Roach: I wanted to ask something a little bit more direct about Nova Lake because speculation around Nova Lake has been going on for a while. I wanted to focus on the high-end, there's been kind of these endless rumors about a 52-core part. You have teased previously scaling up Thread Director to deal with these higher core-count CPUs. I'm wondering right now: What does something like this ultra-high core count, or like a high-end desktop processor, what is that offering right now to the market, in your view?

Hallock: My view has always been that the market will initially go. ‘Ah, what am I going to do with this kind of hardware?’ And then they figure it out. And my most recent example of this comes from my time at AMD. I was sitting at Computex, and at the time we were unveiling our first 12-core CPU. So that would have been the 5900X, I think, maybe the 3900x. It's been a while, and I was sitting in the room with a bunch of journalists who – 18 months ago – had been like, "Why eight-core in consumer? What are you even talking about? Why? Why does this exist?” Same people sitting in front of me. I'm talking about a 12-core CPU, and they're like, "Where's your 16-core?" Like a poorly, poorly kept secret at that point, right? Like it was only like a week away from getting announced, and everybody knew it existed.

How quickly perspectives change. Suddenly, we went from four-core to eight-core, to 12, to 16 in three years. And man, how quickly people’s opinions changed about the value of [higher] core counts. I don’t think, in the history of the PC industry, [that] bigger bar better, more performance better. Never a bad answer. And that does inform my thinking about the roadmap, and Intel’s thinking about the roadmap going forward. It’s never a bad idea to offer more hardware to people.

Roach: The irony. About that, I think it was Zen...It must have been Zen 2. The irony about that is that the 12-core SKUs are always significantly worse than the eight-core and the 16-core. I guess there are some workloads where it makes sense, but yeah, it's interesting to hear.

I think, you know, one of the big hopes for Nova is a competitor to V-Cache. I know this is something you're well aware of, and you know has been brought up numerous times. I watched some previous interviews that you did, I believe, with a recent one with PC Games Hardware, and you had mentioned ways to improve cache locality as something like, ‘Hey, we don't just need to stack a bunch more cache on the chip. We have other levers we can pull to find this performance or to offer something that the X3D chips offer.’

I'm curious what those levers are, because you've made reference to them before, and I just wanted to get a little bit more of a technical explanation.

Hallock: We will have to wait for the fullness of time, won’t we?

Roach: Yes, we will. Hey. You can’t knock me for trying.

Hallock: No, you have to try, and I appreciate and respect that. You know, my bottom line is this is going to be both an answer and a non-answer. Sorry. But I want to try to answer the question for the public more generally. We understand and appreciate there is a like a lot of hope, a lot of expectation, and a lot of desire surrounding Nova Lake. We get it.

And in some ways... selfishly. We’ve lived through it. Every negative comment, every bad tweet, every crappy article. It wears on you. It really does. And we want to deliver a product with Nova Lake that meaningfully addresses these criticisms.

Yeah, just pick one [CPU from Intel or AMD]. I’m not going to confirm anything else, but pick one. I think the Nova Lake product will do the job.

Roach: Okay. Well, that's good to hear. I have to imagine, especially with Nova Lake in particular, given how much they're, you know… There's probably a story on Videocardz or WCCFTech, probably a lot on Tom's Hardware every two or three days. So, yeah, it's a lot.

Hallock: Well, I think it’s reflective of how excited people are, how much anticipation, how much demand is pent up for this moment.

Roach: I know we're almost out of time, but I did want to share with you real quick. It was a big thing that we talked about this year at CES. Actually, I was talking to AMD PR, and they were getting reactions [to AMD’s new announcements]. And I told them, I was like, man, there is a Dark Knight sentiment. You live long enough to see yourself become the villain…happening right now in the industry. I think there's certainly a lot of that reaction that we've seen at least. So, for what that's worth…

Hallock: I have read those comments. Yeah. You know, a product like Nova Lake cannot address every single slice of the market. It just can't, given the current market that we're in. But I, I do hope and do believe that people will look back and go, ‘damn, you know, that was pretty, pretty freaking good.’ Yeah, that's what we were hoping for. And if Intel just keeps going, we're gonna be okay. And that's the trajectory we're on. That's who I want to be, as a business for gamers.

Roach: Yeah, I've heard you say that numerous times, which is encouraging to hear. So I appreciate it, and yeah, thank you so much for taking the time to do this. You know, I always enjoy talking with you, and I'm excited to see what comes next.

[Session ends]

"We intend to use the net proceeds from this offering for general corporate purposes, which may include the repayment of debt," an AMD statement with the Securities and Exchange Commission reads.

The offering comprises four tranches: $1.25 billion of 4.6% notes due in 2029; $1.50 billion of 5% notes due in 2031; $1 billion of 5.25% notes due in 2033; and $1 billion of 5.5% notes due in 2036. Their yields to maturity are 4.64%, 5.018%, 5.264%, and 5.532%, respectively, while spreads over comparable U.S. Treasuries range from 43 to 90 basis points, which indicates that the market is generally confident in AMD and is willing to lend it money at rates that barely exceed those of the U.S. Treasury. Moody's and S&P are expected to rate the securities A1 and A, respectively.

AMD did not disclose how it plans to spend $4.75 billion, but the additional money obtained at attractive rates gives it room to finance its increasingly capital-intensive business as well as cash for debt repayment and other corporate requirements.

AMD hardly appears desperate for additional money. At the end of Q2 2026, the company had approximately $13.1 billion in cash, cash equivalents, and short-term investments. AMD's debt totaled $3.2 billion, and only $875 million is classified as current, which means that the proceeds from the offering by far exceed AMD's current obligations. Meanwhile, AMD's business is becoming very capital intensive.

At the end of 2025, the company had around $12.2 billion in unconditional commitments, which include purchases of wafers and substrates, multi-year cloud-service agreements, software and technology licenses, and guaranteed obligations to third parties. Approximately $8.5 billion was due in 2026.

Also, AMD's working capital requirements are growing. Inventories reached approximately $8.47 billion by the end of Q2, while accounts payable climbed to $5.36 billion. AMD also spent $1.20 billion on property and equipment during the first half of 2026, compared with $494 million a year earlier.

If we were to speculate where AMD can put $4.75 billion, then long-term supply agreements for commodities like memory, logic production, or advanced packaging immediately come to mind. However, given the current market realities, $4.75 billion is 1.8x smaller than AMD's inventories as of late Q2 2026. Furthermore, an average long-term supply deal with a major memory maker now amounts to $7.14 billion (according to Micron's comments made in its recent earnings release).

That said, $4.75 billion may not be enough for AMD to make strategically important purchase commitments. Nonetheless, getting nearly $5 billion at attractive rates amid global undersupply of pretty much everything certainly gives AMD some additional flexibility to run its business.

"The capital raise […] is still a good leading indicator of management's increasing Foundry conviction (vs. defensive balance-sheet action)," reads an excerpt from BofA's note to clients published by John Intel. "We flag the capital raise also aligns with the recent step-up in capex (for internal customer) and ongoing 14A progress, with further capex increase expected on potential incremental external customer wins (18A-P, 14A, advanced packaging EMIB-T)."

Indeed, it is hard to believe that Intel's management would raise almost $20 billion without a more or less clear plan on how to spend it. In fact, Lip-Bu Tan has said repeatedly that he would not authorize building capacity for external customers unless there was a customer commitment. Of course, at some point, Intel will need additional 18A capacity for its own products as well, but $20 billion is a lot of money, which may indicate that the additional capacity will be aimed both at internal and external clients. This is by no means a confirmation that a formal deal has been reached with a big customer like Apple, AMD, Nvidia, or Qualcomm, but it is at least an indicator of management's confidence in Intel's performance going forward.

In fact, Intel's $19.7 billion stock offering was several times oversubscribed and about 33% of investors who submitted orders received no shares at all, reports @FirstSquawk, which indicates great confidence in the company by regular investors. Apparently, Intel's chief executive, Lip-Bu Tan, was among the investors who managed to get $12 million worth of stock using his own money.

In March 2025, shortly after becoming the head of Intel, Lip-Bu Tan bought $25 million of Intel shares (approximately 1.04 million shares) through a family trust to hold them for five years as a required part of his employment contract. Since then, he neither bought nor sold his Intel stock, so the acquisition of $12 million worth of Intel shares is a significant deal.

"Overall, we view the raise as net positive given foundry scale and customer conviction driving longer term top-line and operational efficiency, more than offsetting modest near-term EPS dilution," the note by BofA reads. "We also flag positive read-through for both front-end and back-end packaging semicap vendors."

After years of being a commodity, memory became a strategic asset in recent quarters and will likely remain one for a while, so suddenly, leading makers of 3D NAND and DRAM became highly profitable companies, something the Intel CEO is keenly aware of:  "I used to be, 'do not invest in memory because it is a kind of commodity business,' but now it has become different," Tan said. […] "There is a lot of new technology coming out. So, we are kind of looking at one of my pet projects, some of the new memory architecture. I think you just saw the news: I hired my good friend, Seok-Hee Lee, who used to run SK Hynix. So, you kind of know something that I am thinking about. We are not ready to unfold it."

Tan did not reveal anything about the pet project and did not even specify whether the project is one of his personally favored strategic initiatives at Intel, or an initiative in one of the companies that he has invested in. He did mention that stacking memory on top of a CPU could make a lot of sense, though did not elaborate. Tan's remarks also follow the revelation of an Intel XBM patent that does away with the silicon interposer of HBM.

" I think CPU and memory, I think there are a lot of ways we can really do stacking together," Tan said. "And also try to find some new architecture for memory. I think in some way the memory, a lot of innovation are not there. So, there is some really good area."

Not everyone in the industry remembers, but Intel started as a memory company in 1968 and was quite a successful memory maker until the eighties, when Japanese companies took the lead, and Intel had to exit the market completely after suffering severe losses. Since then, the company has attempted either to return to the memory market with NAND and Optane, or at least to capitalize on a new type of memory with RDRAM. In all three cases, the company abandoned its memory initiatives without incurring significant losses.

Given the current profitability of 3D NAND and DRAM makers, producing memory is certainly a good business again and will remain profitable for some time. However, to re-enter it, companies like Intel would need capital to build at least one fab, R&D to develop competitive process technologies, and time. While licensing a technology — assuming that a company has capital — is an option, we strongly doubt that at this point Intel may be inclined to invest capital in memory and not in its core products and foundry businesses. Furthermore, it is unclear how investors react to such investments given the fact that the company struggles to become a strong competitor in the foundry market and has exited 3D NAND and 3DXPoint/Optane businesses after failing to achieve strategic targets.

After SK hynix acquired Intel's 3D NAND and SSD business in 2021 and formed its Solidigm subsidiary shortly after, it suspended any expansions of Solidigm's capacity in China partly due to the memory market downturn in 2022 – 2023 and partly due to U.S. export controls that curb exports of advanced fab tools to China. However, as demand for solid-state storage is setting records in general and demand for Solidigm's high-capacity SSDs is exceptionally strong, SK hynix is reconsidering its capacity plans for the Dalian fab just in time for Solidigm's initial public offering.

Following a four-year pause, Solidigm has reportedly resumed investment in its Dalian facility in China this year. The company has completed construction of the second phase of the fab and is preparing to start installing production equipment as early as November, the report claims. The facility is expected to begin mass production of floating gate 3D NAND flash in the first half of 2027, if the report is accurate.

The second phase of Solidigm's fab in Dalian is reportedly designed for a wafer output capacity of around 50,000 wafer starts per month (WSPM). Combined with approximately 100,000 WSPM at the existing first phase of the facility, the new phase would boost Solidigm's NAND production capacity in Dalian by roughly 50%, to around 150,000 WSPM.

Late last year, the U.S. government granted SK hynix and Samsung annual licenses to ship semiconductor production equipment that contains technologies developed in America to their Chinese fabs through 2026, which replaced their previous open-ended Validated End User (VEU) exemptions. As a result, both companies can now upgrade their fabs in the People's Republic and even use new process technologies there.

Solidigm, for example, intends to start making floating gate 3D QLC NAND memory with over 200 active layers at its Dalian facility in the second half of 2026, which was made possible by the timely tool upgrades. The additional capacity will further increase bit output of the Dalian campus, which in turn will enable Solidigm to produce its 245TB-class SSDs due to be introduced in the coming months in decent quantities, sometimes in 2027.

Solidigm, which controls roughly a quarter of the data center-grade SSD market, is a crown jewel in SK hynix's portfolio as it makes unique products that are sold at a premium and are in high demand. Listing Solidigm on NASDAQ would enable SK hynix to gain capital (up to $7 billion, if unofficial reports are correct), but retain control over the precious asset. The money that SK hynix will raise should be roughly enough to expand Solidigm's capacity and increase output of premium data center-grade solid-state drives.

It should be noted that SK hynix did not officially confirm the Solidigm IPO plan last week, as its regulatory filing on August 5 said that Solidigm was considering various ways to improve its competitiveness, but the final decision is yet to be made.

Intel will sell 210,526,315 shares for $95 apiece through an underwritten public offering. In addition, participating banks have 30 days to acquire as many as 31,578,947 more shares at the same $95 price, minus applicable underwriting discounts. Should they exercise all their options, Intel could sell approximately 242.1 million shares altogether and increase the proceeds to roughly $23 billion. Without the additional shares, Intel expects net proceeds of approximately $19.7 billion after underwriting discounts, commissions, and estimated expenses. The transaction is scheduled to close on August 12, 2026.

Intel's market capitalization increased from roughly $90 billion last August to $491 billion at press time, so the time is right to sell some shares and raise some much-needed cash, as the company must compete against giants like TSMC and Samsung, which spend tens of billions of dollars every year on new fabs and advanced process technologies. Meanwhile, Intel's capitalization reached its all-time high of $673 billion on June 20, 2026.

Intel has not assigned the money it is going to raise to particular projects and says the capital can be used across the business, including for capital expenditures and working capital. The company is currently ramping up its Fab 52 in Arizona and is on track to start using adjacent Fab 62 when it needs to. In addition, the company still has to build its fab complex in Ohio, which is expected to cost over $100 billion when fully built, so it badly needs money.

In its risk disclosures, the company specifically mentioned Intel 14A — which is due to enter mass production in 2028 — and other advanced process technologies, manufacturing expansion required to support them, and the need to secure design wins and volume commitments from major external foundry customers. While Intel does caution that these long-term investments amounting to tens of billions may not generate adequate returns, it is impossible to land sizeable contracts from external customers without having production capacity readily available.

Interestingly, Intel also mentioned alternative financing arrangements, government grants, and the U.S. government's significant equity position in the company among relevant factors.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

This faceoff is particularly interesting because the two chips take very different approaches despite costing about the same price. The Core Ultra 7 270K Plus packs 24 cores and excels in productivity workloads, while also delivering Intel's strongest gaming performance in years. The Ryzen 7 7700X3D, meanwhile, relies on AMD's proven 3D V-Cache technology to deliver gaming performance within 5% of the 7800X3D, although it trails significantly in single- and multi-threaded workloads.

While the Ryzen 7 7700X3D is aimed at gamers looking for X3D performance at a lower price, it faces stiff competition from Intel's aggressively -priced Core Ultra 7 270K Plus, as well as its own sibling, the Ryzen 7 7800X3D, which is often available for only a little more.

So, is AMD's gaming-focused approach enough to beat Intel's well-rounded Arrow Lake Refresh processor, or has Intel finally found the right balance of price and performance to reclaim the mid-range crown? In this six-round faceoff, we compare these two sub-$350 CPUs to find out which one comes out on top.

Features and Specifications: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

Taking a look at the technical specifications, it's clear that each chip adopts a distinct strategy for the mid-range market. While Intel has optimized its architecture for a higher core and thread count along with improved interconnect speeds, AMD continues to leverage its stacked cache to maintain gaming dominance on a long-lived platform.

The Intel Core Ultra 7 270K Plus is based on the original Arrow Lake-S family, utilizing the same microarchitecture that we saw on the 265K, built using TSMC’s 3nm process. It matches the flagship 285K with a 24-core configuration (8 Lion Cove P-cores and 16 Skymont E-cores) and operates with a 125W TDP. The chip can scale to a 250W Maximum Turbo Power (MTP), which is the maximum power limit that this CPU can consume for short periods when running at maximum turbo boost frequencies

Intel has also standardized several enthusiast-level performance tweaks for Arrow Lake Refresh, most notably a 900 MHz increase in die-to-die frequency and a 400 MHz fabric speed boost. It also officially supports faster DDR5-7200, along with 20 lanes of PCIe Gen 5 and 76MB of total cache. Possibly the only major concern with the Core Ultra 7 270K Plus is the LGA 1851 platform. With Intel's next-generation Nova Lake processors expected to launch later this year, the current platform will have a relatively short lifespan, restricting any future upgrade options.

The AMD Ryzen 7 7700X3D serves as a more affordable, lower-clocked variant of the 7800X3D, featuring the same eight Zen 4 cores with a peak boost clock of 4.5 GHz. Its primary architectural strength is its 104MB of total cache including 64MB of vertically stacked L3, which is specifically tuned to eliminate memory latency bottlenecks.

The chip is rated at a 120W TDP with a 162W Package Power Tracking (PPT) limit, though it frequently operates well below these levels during gaming. A major selling point for Team Red is motherboard flexibility as the 7700X3D can be used with existing AM5 motherboards (600 and 800-series chipsets), and AMD has committed to supporting the socket through at least 2029.

⭐ Winner: Intel Core Ultra 7 270K Plus

While AMD offers a more stable platform and superior gaming efficiency thanks to its large cache size, Intel’s hardware package is more comprehensive for the price. The 270K Plus offers triple the core count, significantly higher frequencies, and faster memory support.

Gaming Benchmarks and Performance: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

To evaluate the gaming performance of these two chips, we conducted our testing at 1080p resolution using an Nvidia GeForce RTX 5090. We used this setup to prevent the GPU from becoming the bottleneck, allowing each CPU's gaming performance to shine through. By removing the graphics card as a limiting factor, we can see exactly how the 7700X3D’s 3D V-Cache stacks up against the higher core count and clock speeds of the 270K Plus.

We used identical systems for testing. You can read more about our full system configuration in our Ryzen 7 7700X3D review and Core Ultra 7 270K Plus review.

Across a comprehensive 16-game geomean, the AMD Ryzen 7 7700X3D holds its position as the superior gaming chip, delivering a 174.3 FPS average. This represents a 5.3% performance lead over the 270K Plus, which produced a 165.6 FPS average. While Intel's latest flagship has significantly narrowed the gap compared to the original Arrow Lake silicon, AMD’s 3D V-cache architecture continues to provide a higher performance in the majority of tested titles.

Even when examining the 1% low frame rates, which is the perceived smoothness while gaming, the 7700X3D maintains a slight edge with a 118 FPS average compared to the 115 FPS from the 270K Plus.

AMD's stacked cache gives the 7700X3D a clear edge in games that are sensitive to memory latency. For instance, in Minecraft RT, the 7700X3D delivered 144.5 FPS average, dwarfing the 89.7 FPS produced by the 270K Plus for a massive 61.1% performance advantage. We see similarly dominant leads for AMD in F1 2024, where it leads by 30.4% (201.8 vs. 154.7 FPS), and in Final Fantasy XIV, where it holds a 21.7% lead (177.7 vs. 146.0 FPS). Even in esports titles like Counter-Strike 2, the 7700X3D maintains a comfortable 7.3% lead with 707.9 FPS over Intel’s 660.0 FPS.

Intel’s Core Ultra 7 270K Plus is no slouch, however, as it leverages its higher boost frequencies and the new iBOT runtime translation layer to take the lead in several games. Intel manages a win in Hogwarts Legacy, producing 135.3 FPS for a 9.1% advantage over AMD’s 124.0 FPS, a result directly attributed to iBOT. Team Blue also edges out victories in The Last of Us Part 1 with 175.6 FPS (6% lead) and Spider-Man 2 with 207.2 FPS (5% lead).

In many other modern titles, the two processors are essentially locked in a dead heat. For example, in DOOM: The Dark Ages, the 270K Plus delivers 200.4 FPS while the 7700X3D is right beside it at 200.0 FPS. The story is similar in Flight Simulator 24, where Intel's 120.5 FPS and AMD's 114.9 FPS result in a negligible difference during actual gameplay. These results indicate that while the 7700X3D is the more consistent gaming choice, especially in cache-heavy titles, the 270K Plus is a highly competitive gaming chip that delivers impressive results for its $300 price tag.

The biggest difference between these two architectures is noticeable when analyzing power consumption and efficiency metrics. Based on our 16-game CPU power geomean, the 7700X3D is clearly way more efficient, drawing an average of just 60.9 watts while gaming. In comparison, the 270K Plus consumed 107.3 watts on average, which is a significant 76.2% increase in power. This results in a massive gap in gaming efficiency where the 7700X3D delivers 2.86 FPS per watt, making it roughly 85.7% more efficient than the 270K Plus, which trails at 1.54 FPS per watt.

Intel does take the lead when it comes to raw frequency, with the 270K Plus maintaining an impressive 5,247 MHz average clock speed across our gaming suite. This is over 700 MHz faster than the 7700X3D, which averaged 4,505 MHz. Despite the much higher clocks and power draw of the Intel chip, its thermal management remains surprisingly competitive when paired with the right cooling solution. The 270K Plus averaged 59°C during gaming, though it still runs warmer than the 7700X3D, which stays at a cooler 55°C average.

When factoring in the cost of the silicon, the competition for the best bang for your buck is incredibly tight. The Ryzen 7 7700X3D provides a value of 0.53 FPS per dollar, narrowly edging out the Core Ultra 7 270K Plus, which sits at 0.52 FPS per dollar.

⭐ Winner: AMD Ryzen 7 7700X3D

The 7700X3D’s overall higher average frame rates and excellent efficiency makes it the more attractive option for a dedicated gaming build. Since raw gaming performance, efficiency, and thermals all favor Team Red in this category, the Ryzen 7 7700X3D takes the win for this round.

Productivity Performance: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

AMD's X3D processors are widely known for their gaming prowess. However, they have historically struggled to maintain the same level of dominance in productivity performance. The Ryzen 7 7700X3D is no exception, as its cache-focused architecture and lower clock speeds result in relatively weak single- and multi-threaded results.

In contrast, Intel has managed to maintain its standing in the productivity segment even when its gaming performance faced challenges. The 270K Plus is a productivity workhorse that is capable of delivering excellent productivity performance making it a standout choice for users who need a balanced system for both work and play.

In multi-threaded workloads, the performance gap between these two processors is pretty massive, primarily driven by Intel's higher core count advantage. Across our multi-threaded performance ranking geomean, the Intel chip delivers a score of 626 compared to the 272 produced by the 7700X3D, representing a staggering 130% performance lead for Team Blue. This level of parallel processing power places the 270K Plus in a completely different performance tier, making it more comparable to much more expensive flagship processors.

Individual benchmarks further highlight this lopsided victory for Intel across various professional tasks. In Cinebench 2024’s multi-core test, the 270K Plus scores 2,509 points, which is roughly 135.6% faster than the 1,065 points achieved by the 7700X3D. This trend continues in POV-Ray, where Intel leads by approximately 169.5% (15,697 vs. 5,823 PPS), and in V-Ray 6, where it maintains a massive 129.5% advantage (45,016 vs. 19,615). Even in intensive video encoding tasks via HandBrake x265, the Intel chip more than doubles the performance of its AMD rival, delivering 29.9 FPS compared to just 14.3 FPS for the 7700X3D. These results demonstrate that for heavy rendering or data-crunching workloads, Intel is the undisputed leader in this price bracket.

A similar trend can be seen when examining single-threaded performance, a crucial metric for general system responsiveness and applications that do not scale across multiple cores. In our single-threaded geomean, the 270K Plus scores 278 points, which is 42.5% faster than the 195 achieved by the 7700X3D. Specific tests like Cinebench 2024’s single-core benchmark show the 270K Plus maintaining a 39.7% lead over the 7700X3D (145 vs. 103.8 points), while the lead grows to a staggering 82.6% in POV-Ray’s single-core test (1,138 vs. 623 PPS). Even in audio encoding, the Intel chip finishes the Lame Extended task in 68.61 seconds, whereas the 7700X3D trails at 91.53 seconds.

⭐Winner: Intel Core Ultra 7 270K Plus

Ultimately, the 270K Plus simply blows the competition out of the water when it comes to productivity. While the 7700X3D is a highly efficient and specialized CPU for gaming, it cannot match the raw horsepower that Intel offers. For any user whose daily routine involves video editing, 3D rendering, or heavy multitasking, the 270K Plus is the obvious choice and should be the clear favorite for a multi-purpose system.

Overclocking: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

While both manufacturers provide tools to squeeze extra performance from their silicon, the Intel Core Ultra 7 270K Plus is built as an enthusiast-friendly, fully unlocked processor. The AMD Ryzen 7 7700X3D, on the other hand, is a more restricted processor designed primarily for out-of-the-box gaming efficiency.

For the Intel Core Ultra 7 270K Plus, overclocking is a centerpiece of the experience. As a fully unlocked K-series SKU, it offers users granular control over per-core voltages, power limits, and clock speeds via an unlocked multiplier. While these changes can be done by entering the BIOS, one can also download the Intel XTU (Extreme Tuning Utility) software to fine tune the CPU.

One of the most significant changes seen on Arrow Lake Refresh is that Intel has standardized several high-end performance tweaks including the 900MHz die-to-die frequency bump and the 400MHz fabric speed increase. This means users receive enthusiast-level interconnect performance without necessarily needing a premium Z-series motherboard. That said, Z890 boards are still necessary as they offer sophisticated tools for manual tuning and pushing the CPU to its limits.

In contrast, the AMD Ryzen 7 7700X3D follows the same path as previous Zen 4 X3D processors including a locked multiplier, which prevents traditional manual overclocking. Users are instead limited to automated and semi-automated features like Precision Boost Overdrive 2 (PBO2) and Curve Optimizer. PBO2 allows the CPU to dynamically adjust its frequencies based on available power and thermal headroom, while Curve Optimizer enables more advanced fine-tune voltage offsets for each of the eight Zen 4 cores.

While these tools can lead to sustained higher boost clocks, the sensitive nature of the 3D V-Cache stack leads to thermal challenges that limit frequency headroom. Thus, overclocking gains on the 7700X3D are often minimal compared to the flexibility offered by the Intel chip.

⭐Winner: Intel Core Ultra 7 270K Plus

The 270K Plus is a far more overclocking-friendly product. It offers a vast suite of features that AMD simply cannot match due to its architectural restrictions and locked multiplier.

Power Consumption, Efficiency, and Cooling: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

This is a crucial section of the faceoff as it highlights the most significant architectural divide between these two processors. While the 270K Plus prioritizes raw performance throughput, the 7700X3D focuses on extreme efficiency. This is immediately evident in their official power ratings where Intel specifies a 125W TDP with a massive 250W Maximum Turbo Power (MTP), while AMD utilizes a 120W TDP with a 162W Package Power Tracking (PPT) limit.

In synthethic multi-threaded workloads, the difference is quite evident. While running HandBrake x265 10-bit encode, the 270K Plus consumes an average of 226W, which is more than triple the 72W required by the Ryzen 7 7700X3D. A similar trend appears in VP9 encoding, where Intel draws 184W compared to AMD’s efficient 65W. Even in lighter tasks like single-threaded y-cruncher AVX workloads, the Intel chip requires 55W while the AMD chip stays at a modest 32W. Idle power consumption also favors Team Red where the 7700X3D idles at 19W and draws 22W during YouTube playback, whereas the 270K Plus sits higher at 29W and 38W, respectively.

When we translate these power figures into efficiency metrics, AMD’s lead tends to stay ahead in most traditional benchmarks. In Cinebench 2024, the 7700X3D produces 14.4 points per watt, significantly outperforming the 10.4 points per watt from the 270K Plus. In HandBrake x265, AMD achieves a superior efficiency rating of 5W per FPS , while Intel trails at 7.56W per FPS.

However, the efficiency scatter plots provide a more nuanced look at how performance scaling impacts total energy consumption. In the Blender Classroom scatterplot, the 270K Plus delivers a much higher performance of roughly 135 samples per minute, but it consumes over 33,000 kJ of task energy. In contrast, the 7700X3D finishes with only around 60 samples per minute but uses significantly less total energy at roughly 4,500 kJ.

The HandBrake x265 scatterplot shows a similar trade-off where Intel reaches 30 FPS but consumes over 55 kJ, while AMD provides 14 FPS at roughly 36 kJ. Interestingly, the Linpack scatterplot shows the 270K Plus reaching over 850 GFLOPS with roughly 11WHr of energy, making it slightly more efficient in terms of performance-per-energy than the 7700X3D, which delivers roughly 340 GFLOPS for 10Whr.

From a cooling perspective, the 250W MTP on the 270K Plus means that it requires a robust cooling solution, like a 360mm AIO, to avoid thermal throttling during extended all-core loads. The 7700X3D is far easier to manage, remaining remarkably efficient and manageable with a mid-range air cooler. While the 270K Plus delivers class leading performance, it does so by significantly compromising efficiency in heavy workloads compared to AMD.

⭐Winner: AMD Ryzen 7 7700X3D

Pricing: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

The Intel Core Ultra 7 270K Plus was initially introduced with a justified $300 price tag, but you'll now find it between $300 and $320. The AMD Ryzen 7 7700X3D made its debut just last month and carries a $330 MSRP, placing it right under the 7800X3D. Essentially, there is not a major difference when it comes to the chips themselves, however, the true financial divide becomes apparent when we look at the total platform cost.

The Core Ultra 7 270K Plus demands a more substantial investment to reach its full potential. While one can opt for a B860 motherboard, a compatible Z890 motherboard is necessary in order to access premium overclocking and tuning features. These typically start around $150-$200, and can go as high as $600 packed with premium features. To handle the processor′s 250W Maximum Turbo Power(MTP) during heavy productivity tasks, a high−end 360mm AIO liquid cooler ($100-$150) or a dual-tower air-cooler ($50-$100) is recommended.

In contrast, the AMD Ryzen 7 7700X3D offers a much more budget-friendly entry point. A solid B650 motherboard can be found for around $120-$150 and the chip can be effectively cooled with a modest $50 air cooler.

Unfortunately, both platforms are held back by the ongoing global shortage of memory, which has caused prices to shoot up significantly. Since both CPUs require DDR5 RAM, builders are stuck in a RAMpocalypse where a basic 32GB kit costs over $400. This extra cost is bad news for both sides as it cancels out any price advantage.

Overall, the lower upfront platform cost makes the 7700X3D a slightly more attractive option for users prioritizing their budget. Furthermore, the AM5 socket offers a clear upgrade path through at least 2029, ensuring that your motherboard investment remains viable for future CPU generations. That is not the case with Intel, as the LGA 1851 socket is expected to be replaced once the next-generation of Nova Lake CPUs arrive.

⭐ Winner: AMD Ryzen 7 7700X3D

Ultimately, while both the chips are available at a very similar price range, the AMD Ryzen 7 7700X3D is the smarter financial play for a majority of users. Its significantly lower platform costs, superior gaming efficiency, and guaranteed platform longevity provide a level of value that the more power-hungry Intel refresh cannot quite match.

Bottom Line: Intel Core Ultra 7 270K Plus vs AMD Ryzen 7 7700X3D

The Ryzen 7 7700X3D and Core Ultra 7 270K Plus are designed for very different users, even though they sit in roughly the same price range. Like previous X3D chips, AMD's latest processor is built with gaming in mind, using its large 3D V-Cache to deliver excellent frame rates while keeping power consumption impressively low. Intel, on the other hand, combines a 24-core design with higher clock speeds and platform improvements to create one of the strongest productivity processors in its class without giving up much gaming performance.

The final score is tied at three rounds apiece. AMD comfortably wins gaming performance, power efficiency, and platform value, three factors that matter a lot for buyers shopping in this price segment. The AM5 platform also provides a significantly longer upgrade path, allowing users to drop in future processors without replacing their motherboard.

Intel, however, deserves recognition for what it has accomplished with the 270K Plus. It delivers outstanding single- and multi-threaded performance, offers a fully unlocked overclocking experience, and narrows the gaming gap to just a few percentage points in many modern titles. If your workload includes video editing, software development, 3D rendering, or other heavily threaded applications, the 270K Plus is the obvious choice and justifies its higher power draw.

For everyone else, the Ryzen 7 7700X3D is the more compelling CPU. It offers faster gaming performance, exceptional efficiency, lower platform costs, and a future-proof AM5 ecosystem. Unless your workload regularly extends beyond gaming into demanding productivity applications, AMD's latest X3D chip is the easier processor to recommend.

⭐ Winner: Tie

More CPU Faceoffs

• AMD Ryzen 9 9950X3D2 vs Ryzen 9 9950X3D
• Intel Core i5-14400 vs AMD Ryzen 5 7600X
• AMD Ryzen 7 9850X3D vs Intel Core i9-14900K
• AMD Ryzen 7 9850X3D vs Ryzen 7 9800X3D

In you unfurl the tweet above, you can see Tom Lynch, a self-described arborist and the owner of an AI infrastructure startup, standing behind the framed chip artwork. Folks comment on the Rubylith looking just like the one that the Intel Trinity: Andy Grove, Robert Noyce, and Gordon Moore, were photographed beside in 1978.

Rubylith is simply an adhesive, peelable red film that found favor in graphic arts and chip design before designers went digital. Engineers could cut away parts of the film to define where light would be exposed during photolithography processes. Rubyliths would often be marked with pens, tape, and overlays, especially as designs were iterated and refined ahead of tape-out.

The Intel 8080’s primary architect was Federico Faggin, and it was manually drafted in the age before modern CAD. This human-scale draft is likely 100x magnification compared to the finished processor die. Even scaled this large, it would still be quite an intricate drawing as it had to map around 5,000 transistors, traces, etc., into an approximate 20- x 16-inch sheet. The commercial Intel 8080 release ended up being manufactured on a 6 μm silicon gate process. It originally ran at 2.0 MHz clocks, but later revisions would boast clock speeds up to 3.125 MHz.

Intel’s 8080 was an important 8-bit microprocessor for both the company and the advancement of personal computing. This 8-bit CPU was the one chosen for the Altair 8800, was the original target architecture for the CP/M operating system, and would be a big influence on the later x86 architecture. We also recently wrote how the 8080 bottlenecked the Space Invaders arcade design, unintentionally resulting in the space shoot-em-up’s thrilling increase in pacing as aliens were zapped from the sky.

The application, US 2026/0230175 A1, is a continuation of an earlier Intel filing that was granted as US 12,542,604 B2 in February.

Intel’s proposed architecture is a different proposition from the orbital AI data centers now being pursued by companies such as SpaceX and Google, which aim to move AI compute itself into low-Earth orbit. SpaceX’s planned AI1 satellite and Google’s Project Suncatcher both envision running large-scale computing workloads in space, with the resulting data beamed back to Earth over high-bandwidth optical links. Intel’s orbital data centers, on the other hand, are designed primarily to serve the satellite network itself, acting as higher-orbit compute and control hubs for the much larger constellations operating below them.

In large LEO constellations such as Starlink, Telesat Lightspeed, and Amazon’s Project Kuiper, thousands of satellites are constantly moving relative to one another and the Earth. While the satellites perform their individual tasks, the network itself still has to determine how traffic is routed, which satellites and links should communicate, how spectrum is allocated, and how the constellation responds to failures, interference, weather, and other changing conditions. Much of that network planning and control processing is traditionally handled by computers on the ground, with routing and operational instructions calculated at terrestrial network operations centers and then transmitted back up to the satellites.

Intel says that this constant dependency on terrestrial infrastructure delays time-sensitive decisions, increases reliance on ground stations, and makes management harder as constellations grow into the thousands of satellites. Intel’s solution is to move part of that control and compute layer into orbit. Its architecture places more powerful satellites — which contain much more compute and storage capability than the individual LEO satellites — in Medium Earth Orbit (MEO), Geosynchronous Earth Orbit (GEO), or highly elliptical orbits, where they can maintain a broader and more persistent view of the LEO constellation below and take over tasks such as routing, mission planning, scheduling and network coordination without continually sending those workloads back to Earth.

The proposed setup does not eliminate the need for ground stations. It just keeps satellite network control processing in space. Intel specifically describes moving mission planning and scheduling operations into orbit. The company also argues that offloading heavier network-management tasks to a smaller number of powerful satellites could allow operators to build simpler, cheaper LEO spacecraft. Under current architectures, individual satellites still have to actively participate in network-control functions, requiring additional onboard compute and communications hardware. There’s currently no indication that Intel is actively building the satellites.

Optical connectivity has been used for decades, since electrical links cannot efficiently and reliably transmit data over long distances at high data transfer rates. But the cost and complexity of optical components limited their use to long-reach connections.

Today, the importance of CPO is rising: Electrical interconnects are no longer scaling as quickly as AI processors, and feeding thousands of accelerators within a data center requires an exponential increase in communication bandwidth. In a traditional optical networking architecture, the processor or switch ASIC communicates electrically with a pluggable optical transceiver located at the front panel of a server or switch. As signaling speeds climb to 200 – 400 Gb/s per lane and beyond, however, transmitting electrical signals over long copper PCB traces on a motherboard becomes increasingly inefficient, causing higher insertion loss, greater power consumption, and tighter signal integrity requirements.

While technically possible, it demands the use of better materials, re-timers, complex compensation processing, and equalization circuitry, which increases the cost of server infrastructure and its power consumption. CPO moves optical engines next to the processor or switch ASIC to shorten the electrical path before signals are converted into light, which means lower power consumption per transmitted bit, increased bandwidth density, and predictable scalability. As a result, CPO is increasingly viewed as a necessary technology for next-generation AI infrastructure.

Because AI is viewed as a major megatrend, CPO is set to become ubiquitous; there are dozens of companies working in the CPO ecosystem, including foundries, OSATs, optical I/O startups, laser manufacturers, fiber suppliers, packaging houses, and networking vendors.

As there are so many vendors pursuing different goals with different strategies, for this story, we are going to limit ourselves only to companies that actually produce things and whose roadmaps reflect their technological capabilities. So far, only four foundries have publicly articulated meaningful CPO manufacturing strategies: Intel Foundry, GlobalFoundries, Samsung Foundry, and TSMC.

The four companies each represent four different CPO strategies and have very distinct plans for the future, so their visions and capabilities may not be directly comparable. Nonetheless, reviewing their offerings gives us an idea about where the industry is going from the perspective of actual foundries.

TSMC: COUPE for everything

TSMC has historically been absent from the optical connectivity market as a product supplier. But having worked on silicon photonics for many years, it now has the broadest ecosystem and manufacturing roadmap with its Compact Universal Photonic Engine (COUPE).

TSMC's silicon photonics technology roadmap currently has three stages that span from a 1.6 Tbps optical engine with conventional pluggable optics to a 12.8 Tbps optical engine located within a processor package. The COUPE roadmap is tightly coupled with the company's advanced packaging technologies and the evolution of the company's micro-ring modulators (MRMs) that adjust light and directly impact performance. As a result, several TSMC customers (e.g., Nvidia) plot their silicon photonics strategies around the evolution of COUPE.

The first phase of the roadmap — called COUPE on PCB — relies on a COUPE that bonds a 65nm electronic integrated circuit (EIC) with a photonic integrated circuit (PIC) using the company's SoIC-X bonding technology. The initial implementation targets OSFP (Octal Small Form-factor Pluggable) optical modules and delivers 1.6 Tbps of bandwidth (2x the throughput of copper Ethernet solutions, along with 2x the power efficiency). Therefore, the first-gen COUPE is out of the scope of this article. TSMC says the SoIC-X interface features very low impedance and enables lower power consumption at high signaling speeds.

The second generation — dubbed COUPE on substrate — marks TSMC's transition from conventional pluggable optics to co-packaged optics (CPO). In this stage, COUPE is integrated with the company's chip-on-wafer-on-substrate (CoWoS) advanced packaging technology and co-packaged with a network switch ASIC. This architecture enables motherboard-level optical interconnects with aggregate bandwidth up to 6.4 Tbps, 2x power efficiency, and 10x lower latency than existing pluggable solutions, which is fantastic for a variety of applications, such as NVLink, Ethernet, and InfiniBand switches.

The third phase — called COUPE on interposer — pushes silicon photonics even closer to compute dies: A 12.8 Tbps optical engine is integrated directly into the processor package to enable ultimate bandwidth and scalability. Beyond doubling bandwidth again, the company expects the architecture to offer 5x power efficiency and 20x lower latency than today's pluggable solutions. That will make it particularly attractive for hyperscalers that build clusters with thousands of accelerators. Unfortunately, TSMC characterizes this phase as exploratory and has not disclosed its commercialization timeline.

The main agenda of COUPE is to move the optical engine as close to compute as possible. There is another dimension in TSMC's silicon photonics strategy, however: the evolution of the photonic devices themselves, the MRMs integrated into PICs. The company plans to bring the world's first 200 Gbps/lane (wavelength) micro-ring modulator into production in 2026 and then continue scaling the technology with 400 Gb/s MRMs, additional optical wavelengths, and denser fiber-array integration. This evolution is expected to increase COUPE’s bandwidth density from 0.5 Tb/s/mm in 2026 to 4 Tb/s/mm by 2030, providing an 8x improvement over four years.

It is noteworthy that TSMC presents the MRM roadmap separately from the evolution of COUPE packaging, which suggests that advances in micro-ring modulators represent an independent technology roadmap for the photonic integrated circuit (PIC), rather than being tied to a specific packaging generation. This potentially means that future COUPE products could adopt newer generations of MRMs regardless of whether the optical engine is mounted on a PCB, package substrate, or silicon interposer — although the latter will probably deliver the greatest system-level benefits by minimizing the electrical distance between compute dies and optical interfaces.

Intel: Optics for CPUs, GPUs, DPUs, and accelerators

Intel has been shipping various products with optical interconnections for decades and even attached its silicon photonics solutions to Xeon and Xeon Phi processors in the mid-2010s. Today, Intel's public CPO roadmap is less explicit than TSMC's, but its direction is fairly clear: move optical I/O directly next to CPUs, GPUs, accelerators, and eventually other compute chiplets. Meanwhile, so far, Intel has not unveiled plans to use its CPO technology for switches.

Intel's CPO strategy is largely focused on its Optical Compute Interconnect (OCI) chiplet, which is a self-contained optical I/O subsystem packing both EIC and PIC that can be co-packaged with any compute device using a PCIe interface to enable high-performance optical connectivity. Intel demonstrated the first OCI in 2024. That prototype implementation used 64 PCIe 5.0 lanes at 32 GT/s in each direction to connect to the host and provided 4 Tbps of bidirectional optical bandwidth over eight fiber pairs over a distance of up to 100 meters. Each fiber carried eight DWDM wavelengths spaced at 200 GHz, and every wavelength (lane) transported about 32 Gbps (8 FPs × 8 WLs × 32 Gbps = 2,048 Gbps in each direction).

The 2024 OCI implementation is good for testing the technology, but with rather slow 32 Gbps lanes, it has not been adopted commercially. Meanwhile, this technology has already been proven and demonstrated. Intel is currently working on its next-generation OCI with 200G/lane PICs to support 800 Gbps and 1.6 Tbps applications, though it is unclear when it is set to be available, as Intel has not yet disclosed an equivalent to TSMC's MRM roadmap.

It should be noted that future OCI implementations supporting bandwidth of 10s of terabits per second could interface with compute dies using next-generation PCIe 6.0 interfaces or even native die-to-die UCIe links when integrated into commercial products. Furthermore, Intel can naturally integrate OCI chiplets using its advanced packaging technologies to ensure high performance and low power.

As noted above, Intel's focus with OCI has always been its integration with CPUs, GPUs, DPUs, accelerators, or other compute devices, but not necessarily switches. It remains to be seen whether Intel's next-generation AI hardware roadmap will include switching silicon, but for now, it does not seem that the company is targeting optical switches with its OCI chiplets. Since OCI is protocol-agnostic, limiting it to compute devices seems like an artificial limitation, though we have little indication about Intel's reasoning behind the decision.

Samsung Foundry: Addressing everything

Samsung Foundry's silicon photonics strategy is arguably the most comprehensive among leading foundries. Unlike Intel, whose CPO roadmap is focused on its OCI chiplet for integration with compute devices, or TSMC, whose COUPE optical engine is another major ingredient of its foundry platform, Samsung intends to offer all types of optical connectivity devices, starting from pluggable transceivers in 2026, to switch CPO later on, and all the way to optical engines on the interposer of a processor package in 2030. Unfortunately, Samsung does not publicly provide a lot of information about its plans, so our main source of information will be SF's slide from a conference published by SemiVision.

This year, Samsung Foundry intends to offer a merchant PIC platform that relies on an EIC and a PIC mounted side by side on a PCB for conventional pluggable optics. The PIC will support 100 Gbps-class optical interfaces using CWDM technology, which is good enough for traditional pluggable optical transceivers (though Samsung does not specify the exact implementation), so there's no indication of CPO here.

In 2027, Samsung Foundry intends to catch up with TSMC's first-gen COUPE and offer an optical engine that stacks an EIC on top of a PIC using thermo-compression bonding (TCB). Samsung expects energy efficiency of this generation to improve from approximately 10 pJ/bit for its initial PIC platform to 5 pJ/bit, though Samsung has said nothing about bandwidth or latency. Samsung's TCB-based OE seems to be an intermediate product between merchant PICs and true CPO, so it will generally address onboard optics and pluggable transceivers.

By 2028, SF intends to move optical engines to the substrate of Ethernet or InfiniBand switch ASICs, which will be its first true CPO. The company intends to adopt hybrid copper bonding (HCB) with 10 µm pitches for its OEs to improve bandwidth density. Based on the slide from the roadmap, to address next-generation switches, Samsung is poised to increase optical lane speeds from 100 Gbps to 200 Gbps and ultimately 400 Gbps, although the company does not disclose when exactly each speed bin will be introduced (though it looks like 400 Gbps will come in 2029 – 2030) as well as the underlying modulator technology or other device-level details behind this scaling.

In 2029, Samsung Foundry will finally integrate its optical engine on an interposer next to CPU/GPU/XPU or other compute device, which will reduce energy consumption to 2 pJ/bit while providing extremely high bandwidth. Samsung calls this 'CPO Turnkey,' which implies that such integration will require its own packaging technologies. The next step in Samsung's roadmap is called 'next-generation CPO Turnkey,' and it integrates virtually the entire optical subsystem — including lasers — alongside compute and memory, which will be its ultimate CPO offering expected by 2030 and onwards.

While Samsung Foundry's ultimate goal to offer highly integrated turnkey CPO solutions is clear, the company also intends to offer two merchant platforms for pluggable optical transceivers, perhaps to de-risk development of its future products and to capitalize on the high demand for optical connectivity that exists today and will continue going forward.

GlobalFoundries: A bespoke vendor-agnostic OCI-MSA CPO platform

Unlike Intel Foundry, Samsung Foundry, and TSMC, GlobalFoundries does not produce or intend to produce AI processors, switch ASICs, or advanced packages. Instead, it aims to become a merchant co-packaged optics provider that will produce and sell bespoke CPO solutions that enable optical connectivity (including OCI MSA connectivity) for processors made by other chipmakers.

GF's silicon photonics effort dates back to the IBM Microelectronics acquisition in 2015, which brought IBM's silicon photonics technology and engineering teams into the company. Over the years, GlobalFoundries has expanded its silicon photonics capabilities into what eventually became the GF Fotonix platform and, more recently, the company acquired AMF and InfiniLink to further strengthen its production and design capabilities.

The key element of GlobalFoundries' CPO strategy is its Silicon photonics Co-packaged Advanced Light Engine (SCALE) platform that combines photonic IP, advanced packaging technologies, and a reference optical engine architecture that includes EIC and PIC. Unlike Intel's OCI chiplet, SCALE allows GF's clients to customize optical engines in accordance with their needs and have them manufactured by GF.

Under the program, GlobalFoundries manufactures the PIC and EIC using its own process technologies and then packages them into an OCI MSA-compliant optical engine using its methods. If the EIC requires a leading-edge node that GF does not have, it could instead be fabricated by another foundry and then integrated by GF. Customers then co-package the optical engine alongside their own switch ASICs or AI accelerators.

For now, SCALE supports both CWDM and DWDM transmission using qualified 50 Gbps and 100 Gbps MRMs, integrated photodiodes, and coupled-ring resonators. The platform has demonstrated bidirectional operation with up to 16 DWDM lanes per fiber, which theoretically opens doors to optical links with up to 1.6 Tb/s of bandwidth per direction. On the integration side of things, it supports advanced 2.5D and 3D integration using TSVs and copper bonding with pitches ranging from 110 µm to below 45 µm, which is good enough for integration using CoWoS-S and CoWoS-L technologies.

Just like Intel with its OCI, GlobalFoundries does not necessarily tie its SCALE CPO customers to its silicon or packaging technologies. Furthermore, the company allows its clients to customize their optical engines while retaining compatibility with the OCI-MSA requirements.

The future of CPO

Co-packaged optics (CPO) is set to become a key technology for next-generation AI infrastructure as conventional electrical interconnects struggle to keep pace with the bandwidth demands of rapidly developing AI processors.

Among foundries, TSMC, Intel, Samsung Foundry, and GlobalFoundries have each developed distinct CPO strategies that range from merchant optical engines to optical I/O chiplets and vertically integrated CPO platforms.

Given the different capabilities of the contract chipmakers, their roadmaps differ significantly in both scope and implementation, with some companies trying to lock in customers with a proprietary platform and others offering different degrees of freedom.

However, they all share the same objective: move optical interfaces progressively closer to compute dies to reduce power consumption, increase bandwidth density, and lower latency for the next generation of AI systems that will require considerably more bandwidth than today's clusters.

It’s time to look back, not just on Tom’s Hardware’s role in the world of CPUs over the past 30 years, but on the broader CPU market. Earth-shattering releases at a given time turned out to be footnotes in hindsight, and bubbling competition that seemed like no real threat turned into seismic shifts in the AMD vs. Intel battle. Hopefully, along the way, we’ll see some reflections of what’s going on in the world of CPUs today.

This is a celebration of 30 years of CPU coverage here at Tom’s Hardware, a history lesson about how the AMD and Intel of yesteryear arrived at the positions they’re in today, and a retrospective of the CPUs that stood the test of time against the refreshes that faded into obscurity just as soon as they were released. We hope you enjoy it.

Ruffling feathers from day one (1996 - 1998)

Ruffling feathers from day one (1996 - 1998)

Like much of the early internet, the true beginnings of Tom’s Hardware (or, rather, Tom’s Hardware Guide) is difficult to pin down, but the earliest archived article concerns the SoftMenu BIOS, which allowed you to change CPU settings through software rather than physical jumper cables; it should go without saying that this article was from July 1, 1996. There were articles before this one, with the original domain of sysdoc.pair.com going online in February 1996.

Tom’s Hardware gained a lot of traction a year later with a CPU review: a look at the Intel Pentium II ‘Klamath’ processor.

Tom’s Hardware’s founder, Thomas Pabst, had discussed CPUs previously, like in a dense CPU guide published the same year, but the Intel Pentium II review marked a turning point. It was published March 1, 1997, more than two months before Intel launched the Pentium II 80522 (or Klamath). It was not positive: “...since I wouldn't eat [Mad Cow Disease] infected beef, I wouldn't be interested in risking an infection of my computer with this CPU either,” wrote Pabst.

The CPU wasn’t officially available, but Pabst was able to test the chip with a pre-release unit shared by two German magazines: C'T Magazin fur Computertechnik and PC Professionell. Following the publication of all three reviews, Intel targeted the two German magazines, threatening to withhold advertising dollars and take legal action against them. Pabst publicized this fiasco and was contacted by The New York Times, which also covered the story. Intel backed down. Pabst later wrote that “...this 'David against Goliath'-incident made Tom's Hardware Guide very famous.”

In the following months, Pabst focused on CPUs quite a bit, breaking from the performance-tuning guides and general enthusiast information the website had previously published. The situation with Intel made Pabst a “secret star,” so much so that AMD not only offered Pabst a free review unit of the upcoming K6, but also apparently offered to cover legal fees should Intel pursue the situation further.

Although the unofficial review of the Pentium II predates it, the first review that looks most like the technical reviews that have been published on Tom’s Hardware for decades came in April 1997 with a review of the AMD K6, a CPU that established AMD as a true competitor to Intel, claiming Pentium II-like speeds for less money.

The performance wasn’t quite on the level of a Pentium II, most notably because the K6 originally arrived at 233 MHz, when 266 MHz was promised. But it was competitive, particularly when compared to the Pentium II 233, and much cheaper. Pabst concluded the review, “All in all I'm sure that this CPU will be very successful… Whoever is contemplating the purchase of an Intel Pentium or Pentium MMX CPU can forget about this now. The AMD K6 is faster and cheaper.”

Later that same month, Pabst published a proper review of the Pentium II, now using finalized silicon. In DOS games and the 32-bit Windows NT, Pentium IIs showed a commanding lead over the K6, though the battle on Windows 95 was closer. “The world is back to normal. Intel’s managers can sleep quietly again. The Pentium II shows that Intel is still the leader in the CPU market,” the review concluded.

A review of the Cyrix/IBM 6x86MX went live in 1997, as well, showing competitive performance with the K6, but much of the rest of the year was focused elsewhere after the Pentium II/K6 showdown. Looking back, it’s interesting to note the dynamic at play between AMD and Intel, with Pabst using a running gag of referring to Intel as the “Empire,” and competitors like AMD and Cynix as “Rebels.” Although Intel backed away from further action on Pentium II, it wouldn’t be the last time Pabst and Intel butted heads.

The Pentium III incident (1999 - 2001)

The Pentium III incident (1999 - 2001)

The competitive performance of K6 brought AMD into focus as the rival to Intel, which Pabst often described as “almost-monopolistic” at the time. However, AMD really put itself on the map with the release of K7, or as it’s better known, Athlon, in June 1999. In our review, we described it as “a milestone in the whole processor scene,” due in part to AMD’s unique three-way instruction decoder, which allows instructions of variable complexity through all three lanes. Intel’s P6 architecture in Pentium III also had a three-way instruction decoder, but they were segmented based on the complexity of the instruction.

We’re still firmly in the single-core era of CPUs here, so an architectural divergence like this, even before testing, represented a goldmine of speed gains. Rather than releasing several variants of silicon sliced up in different ways, as we see with modern CPUs, Intel and AMD refined their chips and released new versions with faster clock speeds. AMD released the Athlon 600 as the fastest chip in the range at 600 MHz first, but less than two months later, it introduced the Athlon 650, and two months after that, the Athlon 700.

Intel was caught off guard and quickly introduced the Pentium III 600 to counter AMD. The original Pentium III range, codenamed Katmai, was largely a refinement of Pentium II ‘Deschutes’ chips; both were built using a 250nm node, in fact. In our original Athlon review, we noted instability with the Pentium III 600, suggesting the architecture couldn’t handle such high clock speeds.

The original ‘Katmai’ range of Pentium IIIs was short-lived, and later in 1999, Intel introduced a new revision called Coppermine. Coppermine introduced an on-chip L2 cache for Intel, and it was built on a 180nm node, allowing Intel to go from 9.5 million transistors on Katmai to 28 million on Coppermine, as well as push clock speeds up to 733 MHz with the initial range, squeezing out a minor increase over the Athlon 700. Less than two months later, AMD introduced Orion, or Athlon Model 2, which also used a 180nm node and clocked up to 750 MHz. This back and forth of minor clock speed improvements is going to stick with us for at least another half of a decade, so strap in.

The goal, of course, was the first 1 GHz CPU, a milestone that AMD claimed for itself in March 2000 with the introduction of the Athlon 1000. Intel had shown a 1 GHz Pentium III, but AMD released a 1 GHz Athlon first. Intel followed shortly after with its first CPU to hit the gigahertz milestone. Intel didn’t want to place second again, so it went to work on the Pentium III 1.13 GHz, which it introduced in July.

Pentium II made Tom’s Hardware a name in the PC industry, but the Pentium III 1.13 GHz gave it a name among enthusiasts. Our review found that the processor wasn’t stable at 1.13 GHz, and less than a month after introducing the chip, Intel recalled it. The Pentium 1.13 GHz would eventually come back in 2001, but at the pace of CPU innovation at the time, even a six-month delay was detrimental.

In June 2000, AMD introduced a refinement of Athlon, codenamed Thunderbird, and days before Intel’s recall, introduced the Athlon 1100. AMD remained uncontested throughout the rest of the year, pushing Thunderbird up to 1.2 GHz. Intel was closing the curtain on Pentium III and trying to move attention away from Athlon toward its upcoming Pentium 4 range.

Going for gigahertz (2001 - 2004)

Going for gigahertz (2001 - 2004)

Intel was struggling to keep pace with Athlon, but work was going on behind the scenes on the new NetBurst microarchitecture, which was set to become the successor to P6. It was introduced to the world with the Willamette core inside the first Pentium 4. Like most major microarchitecture shifts we’ve seen from Intel and AMD, NetBurst wasn’t an immediate success. However, Pabst noted in our review: “I am certain that Intel will deliver very fast Pentium 4 processors very soon. Intel has finally won back the ability to make AMD's life a lot harder.”

Intel pushed P6 down to a 130nm node with the release of Tualatin Pentium III chips, but the focus was on Pentium 4 and optimizing NetBurst. In March, AMD introduced the Athlon 1333, but Team Red was losing steam. Intel had already released a Pentium 4 1.5 GHz, and it introduced the Pentium 4 1.7 GHz (along with a price cut to the range) in April 2001. With a new microarchitecture seemingly bursting with potential, it was only a matter of time before Intel made its way back to the top.

That came in August, when Intel planted its flag on the 2 GHz milestone with Pentium 4, and beat out AMD’s fastest Athlon chip. AMD didn’t like that. Later in the year, in October, AMD introduced its Athlon XP range, and with it came a sneaky switch in marketing strategy. Rather than include the clock speed as part of the processor name (i.e., Athlon 1333), AMD started using model names. No, the Athlon XP 1500+ wasn’t clocked at 1.5 GHz; it was clocked at 1.3 GHz. This nomenclature climbed all the way to the top, with the Athlon XP 2100+, which was not 2.1 GHz, but rather 1.7 GHz.

At the time, AMD described this shift as an alignment with what it was able to deliver with Athlon. During this era, we start to see more significant architecture divergences between Intel and AMD, so much so that like-for-like clocks could result in vastly different performance. That’s what we found in our Athlon XP review, in fact, with the Athlon XP 1800+ (clocked at 1,533 MHz) contesting the Pentium 4 2 GHz. Still, it’s not hard to see what AMD was trying to do. In January 2002, Intel introduced its Northwood core for Pentium 4, which could clock up to 2.2 GHz. AMD wasn’t able to break the 2 GHz barrier yet, but it used product names to suggest it had.

Names weren’t enough. By the middle of 2002, Northwood had picked up steam and could clock as high as 2.8 GHz; even the 2.4 GHz Pentium 4 was able to beat AMD’s fastest Athlon XP 2100+ across our benchmarks. AMD was working on the Thoroughbred revision of Athlon XP, including a node shrink down to 130nm to match Intel’s new Northwood core, which it trickled out through 2002. By the end of the year, AMD had shown the Athlon XP 2800+ as a rival to the Pentium 4 2.8 GHz.

Despite lagging in clocks, AMD had become quite popular during this time due to the competitive performance of Athlon XP and (most importantly) a lower price point than the expensive Pentium 4s. Still, there was a stalemate in technology between Intel and AMD, and Intel would break it in November 2002 with the Pentium 4 3.06 GHz.

It was the first consumer CPU to clock to 3 GHz out of the box, adding another notch to Intel’s belt, but it was also the first CPU to bring Intel’s long-standing simultaneous multithreading implementation, called Hyper-Threading, to market. With higher clocks and two threads to play with, the Pentium 4 3.06 GHz cemented Intel at the top of the performance charts, beating out AMD’s fastest Athlon XP and even a 3.6 GHz Pentium 4 (no Hyper-Threading) in some benchmarks. Tom’s Hardware actually benchmarked the Pentium 4 3.6 GHz nearly a year before it was available, and had data in time to compare to the Pentium 4 3.06 GHz with Hyper-Threading.

More cores, more fun (2004 - 2007)

More cores, more fun (2004 - 2007)

The clock speed battle from the late 90s and early 2000s was starting to fall apart. AMD had demonstrated that performance was more than peak clocks with Athlon XP, and Intel was pushing ahead with Hyper-Threading to get more work done simultaneously each clock cycle. The first half of 2003 was dull in the world of CPUs as Intel worked on its Prescott core and AMD mulled over “ClawHammer,” which would eventually become Athlon 64.

Athlon 64 would be the first to bring AMD’s x86-64 ISA extension (called AMD64) to the desktop market (it previously showed up in Opteron). It rolled out in September 2003, and just a week before release, Intel launched the Pentium 4 Extreme Edition, which was widely considered a panic switch in response to Athlon 64 while Prescott was still under wraps. Although Intel maintained the performance crown with P4 Extreme against the Athlon 64 FX-51, it did so at a much higher price.

Still, this late-stage battle as Intel and AMD moved toward a 90nm node was important. Intel started marketing expensive, high-performance processors directly to enthusiasts in a market that would eventually get the HEDT, or high-end desktop, name. Meanwhile, AMD designated some Athlon XP chips with the FX name, which signaled high-performance chips with unlocked multipliers.

Intel was first to get down to 90nm with its highly anticipated Prescott core, though it arrived with a whimper. It clocked slower, allowing the FX-51 to remain competitive and Northwood chips to remain at the top of the charts in our review. There, our reviewer Patrick Schmid wrote: “In our opinion, Intel today does not care about Prescott as a processor, but as a marketing instrument. It is fast enough, which is mainly what counts, and since the 90 nm production process yields cheap processors in vast quantities, the Santa Clara-based company gains new flexibility.”

AMD made it down to 90nm later in the year with the FX-55. The FX-55 allowed AMD to close the gap with higher-clocked Pentium 4s, as we found in our review. However, it was becoming clear that the chase for higher clocks wouldn’t be enough. In our review, Schmid wrote in 2004: “Today, the performance gap between the fastest and the slowest processors in our benchmark charts is rather small.”

Intel fired back at the beginning of 2005 with Prescott 2M, a minor revision to the Prescott core with 64-bit ISA extensions, and released the Pentium 4 Extreme Edition 3.73. The tide shift came in the summer of 2005 when AMD launched the Athlon 64 X2, built on a 90nm node, and featuring two cores on the same package.

Intel had released its double-core Pentium D just weeks earlier, which was also a dual-core chip, but the design forced Intel to compromise clock speeds — an important spec given how few applications could actually leverage a dual-core chip in consumer software. AMD ultimately won the battle with the Athlon 64 X2, largely due to the fact that it could keep pace with single-core Athlons in most benchmarks, as you can see in our early preview of the chip.

AMD released more Athlon 64 X2 chips throughout 2005, while Intel rolled out various chips under different Pentium brands, including the Smithfield core on Pentium D. Intel built out the range into 2006, using another node shrink down to 65nm with the Presler core, which was the final revision under the Pentium brand. In January 2006, Tom’s Hardware first reported that Intel planned to drop the Pentium brand, a name that it had kept for over a decade.

In its place? The new Core microarchitecture, finally moving on from NetBurst, which had been plagued with thermal issues as clocks climbed. Built out of Intel’s work in mobile chips, the Core 2 Duo was Intel’s first proper dual-core processor — the “double-core” Pentium D was just two Pentium dies fused together. It was a tide shift.

As we found in our Core 2 Duo review, the base E6600 and E6700 often beat, or at least matched, AMD’s Athlon 64 FX-62, while the supercharged Core 2 Extreme X6800 established a new performance tier at the high-end. Further, it did so at reasonable power levels, finally taking the efficiency fight back to AMD.

Intel doubled down, literally, with the Core 2 Extreme QX6700 at the end of 2006. Although Intel had introduced a four-thread processor previously, the Core 2 Extreme QX6700 was the first CPU with four cores to hit the market. It took two dual-core dies from Core 2 Duo and put them together on a single package. AMD brute-forced a quad-core with the 4x4 platform and dual Athlon 64 FX-70 chips, but there was a major tradeoff in cost, thermals, and power demands.

The coast of Nehalem (2007 - 2010)

The coast of Nehalem (2007 - 2010)

For the first time in the early aughts, Intel was firmly in the driver’s seat for enthusiasts. AMD drummed up some interest with its dual-chip Athlon 64 systems, and it finally moved down to a 65nm node at the start of 2007. But Intel was on a tear, and it would continue its momentum for years to come.

That started by formalizing the success of the Core microarchitecture. Instead of squeezing everything out of a microarchitecture for several generations, as it had done with P6 and NetBurst, Intel transitioned to its well-known tick-tock cycle. First, there’s a node shrink on its existing architecture, then there’s a new microarchitecture on that node, and the cycle continues. Core was the tock at 65nm, and it would move down to Penryn revision at 45nm later in 2007.

AMD struggled to keep pace. After introducing its AM2 socket in 2006, it continued refining the Athlon 64 X2 lineup with a new 65nm node, but Intel was firmly in the lead, forcing AMD to slash prices and settle into the market as a budget-focused alternative to the shiny Core 2 Duos. AMD doubled down in this area with its K8 microarchitecture, releasing a series of efficient “BE” series chips throughout the back half of 2007, which we found were excellent for efficiency and price-to-performance in our review.

Team Red had its chips on K10, and specifically, the new Phenom brand that it made noise about throughout 2006 and 2007. The Phenom X4 series launched in November, featuring the first true quad-core design; that is, using a monolithic die as opposed to MCM like Intel’s Core 2 Quad. Unlike Intel’s Core 2 Extreme, which was reserved for only the most entrenched enthusiasts, AMD targeted midrange builders.

In our Phenom 9700 review, we found that Intel still maintained the performance crown, but AMD offered a cheaper quad-core and offered identical price-to-performance at release. Further, AMD offered support for the chips on both the AM2 socket and the new AM2+ socket, starting a trend of socket longevity that we can still see in action today. With cheaper quad-core CPUs and less upgrade cost, AMD focused less on battling Intel at the high-end and more on delivering in the midrange.

Intel continued to release more Core 2 Duo and Core 2 Quad models throughout 2008, but behind the scenes, it was working on its next major architectural shift: Nehalem. AMD built out its Phenom line, meanwhile, introducing a tri-core variant, as well as several “Black Edition” models that featured peak clocks and unlocked multipliers for enthusiasts, likely in a bid to grab some attention from Intel’s Extreme lineup.

Nealem came onto the scene in late 2008 in the form of Bloomfield chips. They required an entirely new platform and DDR3 memory, but also promised entirely new performance benefits. Intel managed to create a true quad-core chip with Bloomfield, and one that enthusiasts could actually afford, with the range going down as low as $280. Further, it reintroduced Hyper-Threading after ditching the technology during the early dual-core days, giving enthusiasts eight threads to play with.

The spread between Intel and AMD grew wider. In our review of the Core i7-965 Extreme, we found it was 64% faster than AMD’s fastest chip at the time. Despite offering compelling products at competitive prices, AMD was falling further behind. Intel was far ahead; it had a die shrink ahead, and the legendary Sandy Bridge microarchitecture was waiting in the wings to pick up the tick-tock cycle once again.

AMD bit back in early 2009 with Phenom II (along with Athlon II), finally moving down to 45nm. It brought Team Red back up in the rankings, but Bloomfield still held onto top-end performance. In our original Phemon II review, we found that Intel was about 22% ahead of AMD at the high-end, but AMD offered compelling performance given the platform costs. Sounds familiar.

With tight integration of design and manufacturing under one roof, Intel was moving faster than AMD on process improvements, allowing it to keep a consistent lead in performance, particularly at the high-end. Intel had its Lynnfield chips at 45nm, as well as Clarkdale chips at 32nm, but the 32nm successor to Bloomfield came in early 2010, known as Gulftown. And with Gulftown, Intel could claim a multi-core milestone on a monolithic die for the first time with the six-core Core i7-980X.

At $1,000, the Core i7-980X still only appealed to a small number of enthusiasts. AMD helped fill the gap later in the year with the Phenom X6 launch, introducing six-core models of its own. AMD couldn’t match the 980X at the high-end, but Phenom represented an affordable entry-point to six-core chips if you ran heavily-threaded workloads, as we noted in our review. Still, Phenom X6 was AMD trying to keep pace with Intel. Behind the scenes, AMD was working on a new microarchitecture called Bulldozer, which was built from the ground up for a new generation of chips and finally allowed AMD to move down to 32nm.

Bulldozer bulldozes world records, thermals (2010 - 2013)

Bulldozer bulldozes world records, thermals (2010 - 2013)

It’s easy to pick on Bulldozer in hindsight, but leading up to release, the anticipation was palpable. K8 was a smash success, and K10 built on that success, but Bulldozer was built from the ground up, presumably for the position AMD had found itself in the market. Nearly a year before Bulldozer showed up on the market, however, Intel introduced an architecture that still resonates among enthusiasts today — Sandy Bridge.

Intel unified its product stack with Sandy Bridge and set much of the foundation for the company’s releases through Raptor Lake Refresh. Instead of two broad ranges, Intel placed most of the Sandy Bridge lineup on a single socket. It also brought integrated graphics to all the chips in the lineup, at least in the initial range (some later releases cut the iGPU), as well as unlocked the multiplier on some non-Extreme SKUs to compete with AMD’s unlocked Black Edition chips.

It was a smash success. Reviewing four Sandy Bridge chips, our reviewer Chris Angelini wrote: “Existing Lynnfield- and Clarkdale-based processors already offer strong performance compared to AMD’s lineup. Significant gains, clock-for-clock, compound in the face of notable frequency increases across the board (thanks to a mature 32 nm process), giving Sandy Bridge an even more commanding position.”

Raw performance improvements are one thing, but Sandy Bridge was attractive for several other reasons, as well. Overclocking still represented a solid performance boost in this era, and Intel was offering overclocking capabilities at mainstream price points alongside chart-topping performance out of the box. They also introduced Quick Sync to accelerate video encode/decode, and although we have video encode/decode acceleration in modern GPUs, Quick Sync still serves as a fundamental feature for video editing and media servers.

AMD’s response was Bulldozer, which was rumored ahead of release to outperform Intel’s Core i7-950 by upwards of 50%, as well as introduce a true eight-core chip to the consumer market for the first time. If that wasn’t enough, prior to release, the flagship FX-8150 set a world record for clock speed, peaking at 8.429 GHz. AMD would be the first to release a consumer CPU with eight cores, but just about every other aspect of Bulldozer was problematic.

Achieving eight cores in a single package came with significant trade-offs. Up to this point, AMD hadn’t used any form of simultaneous multithreading, but it implemented a version of SMT in Bulldozer. Unlike Intel’s traditional SMT implementation, Bulldozer used two integer units on a core, but shared floating point resources. The major trade-off was how small the integer execution clusters were in order to save space. AMD designed an architecture for a world of heavily-threaded software that just didn’t exist at the time, and it traded very important single-core speeds to achieve that design.

The flagship FX-8150 was marketed as an eight-core chip, with the eight-core count coming from AMD’s odd SMT implementation. Although there were two integer execution units per “module,” as AMD calls them, the floating point unit was shared. This discrepancy was actually the focal point of a 2015 lawsuit, which AMD settled in 2019 to the tune of over $12 million.

It was a flop. Angelini sums up the issue nicely in his October 2011 review of the FX-8150: “[Intel doesn’t] have to do anything at all. Its nearly year-old 95 W parts fend for themselves without even a price adjustment.” Intel had new chips of its own, as well. Just six months later, it introduced Ivy Bridge, taking the solid foundation of Sandy Bridge and moving it down to a 22nm node.

Ivy Bridge wasn’t a big hit on desktop, but it didn’t need to be, given the advantage Intel had already established with Sandy Bridge. Improvements were in the single digits, as we noted in our Core i7-3770K review, but Ivy Bridge brought improvements to integrated graphics to fight against AMD’s burgeoning lineup of APUs and thermal improvements targeting small form factor devices — especially laptops in a new category of “ultrabooks” that Intel was targeting.

12 months after the FX-8150 was introduced, AMD released a revision of the Bulldozer architecture named Piledriver. It promised better IPC and higher clock speeds, which was compelling, as AMD’s FX-4170 released earlier in the year as the first CPU to hit 4 GHz out of the box. Piledriver had a test run earlier in the year through AMD’s Trinity APUs, as well, showing around a 15% improvement compared to Bulldozer.

The flagship Piledriver, the FX-8350, was indeed better than its Bulldozer predecessor, but it was clear the underlying architecture had issues that wouldn’t allow AMD to scale up. AMD’s flagship was only competitive with Intel’s Core i5 options, and power use, although tamed in Piledriver, still meant the chip ran hot. It was immediately forced into a price cut upon release. After two failures to launch flagships, Intel effectively owned the high-end, which it continued to dominate with CPUs like the Core i7-3970X.

Around six months after Piledriver chips shipped, AMD released another two chips, both running at an insane 220W TDP and shipping with their own liquid cooling system. The highest-end offering, the FX-9590, was the first CPU to hit 5 GHz out of the box. AMD had learned the hard way what it had preached back in the Athlon XP days — clock speed isn’t everything.

The dawn of 14nm (2014 - 2016)

The dawn of 14nm (2014 - 2016)

With a 22nm product shipped, Intel went back to a tock and came out the other side with Haswell. Today, Haswell is heralded as a legendary architecture; we’ve all seen forum comments about gaming with a Core i7-4770K more than a decade after it was released. At the time, however, it established a narrative that would follow Intel for the next several years. That narrative being that Intel ships a new generation of quad-cores, each year, with minor IPC improvements and not much more. That’s certainly the impression Angelini came away with after reviewing the Core i7-4770K.

Intel didn’t have to move the needle beyond that point. Although AMD had shipped Bulldozer and Piledriver, a lot of turmoil was going on behind the scenes. Two further revisions of Bulldozer, Steamroller, and Excavator were planned, but AMD largely canceled the two revisions outside of a few low-end products. During this time, AMD underwent a series of sweeping layoffs and executive changes, cutting thousands of employees. Looking back at the time through a modern lens, some long-time AMD employees say that the company would’ve faced bankruptcy had it not been for semi-custom partnerships with Microsoft and Sony for their game consoles.

From the release of Piledriver in late 2012 through 2017, AMD didn’t release a ton of new CPUs. It released some revisions of Piledriver chips like the FX-8370, but we didn’t see any new microarchitecture. And planned node shrinks with Steamroller and Excavator were canned, with only a handful of desktop CPUs surviving, which were repurposed as low-end Athlon X4 CPUs years later. Intel had won.

It didn’t immediately rest on its laurels, however. Hearing the criticism of Haswell for desktop enthusiasts, Intel introduced the Core i7-4790K alongside other ‘Devil’s Canyon’ chips in mid-2014 as it worked on another tick behind the scenes down to 14nm. The result, which arrived almost a year to the day after Devil’s Canyon, was Broadwell. The Broadwell-H range — not Broadwell-E, which shows up later — isn’t very big and didn’t have much for enthusiasts. But Broadwell got Intel down to 14nm, and it would stay there until the release of Alder Lake CPUs in 2021.

We didn’t know that at the time, though. Broadwell laid the 14nm foundation for Skylake, which came hot on the heels of Broadwell-H after that architecture experienced a series of delays. Intel’s first true eight-core chip, the Core i7-5960X from the Haswell-E range, still gave the HEDT market what they were looking for, but Skylake was pushing ahead in the mainstream. In early performance testing, we said Skylake was the first architecture “to really get enthusiasts excited since Sandy Bridge.”

Intel didn’t need to rush at the time, so it didn’t. There wasn’t an Athlon 64 breathing down Team Blue’s neck. A year later, in 2016, Intel launched Broadwell-E for HEDT, marking the first-ever 10-core desktop CPU with the Core i7-6950X. It wasn’t a massive leap forward over Haswell-E, but Intel was competing with itself. “Intel’s clearly the prettiest girl in the room, is well aware of this fact and, based on Broadwell-E's pricing, doesn't need to beat the ‘value’ of last generation's -Es by much,” our reviewer Igor Wallossek wrote in his Broadwell-E review.

Although Intel was a clear market leader, it was slowing down significantly. Earlier in 2016, it quietly revised its tick-tock cycle, moving to a tick-tock-tock cadence where we’d see a new process followed by a new microarchitecture followed by an optimization of that architecture. Intel wasn’t juiced up with Moore’s Law like it was in the early aughts, but it competed in a category of one. What were you going to do? Buy AMD?

Feeling Zen (2017 - 2020)

Feeling Zen (2017 - 2020)

Shortly after the ball dropped into 2017, Intel released its Kaby Lake range of CPUs, now sporting the “14nm+” process and serving as the first optimization pass in Intel’s new release cadence. It was fine. The range came with a clock speed bump over Skylake, but otherwise, Intel released the same architecture sporting nearly identical specs, from core counts to cache sizes.

Behind the scenes, trouble was brewing. Six months before Kaby Lake made its way to market, AMD detailed its first entirely new microarchitecture since Bulldozer, named Zen. In addition to promising a 40% improvement in IPC over Excavator, the Zen platform would come with support for DDR4 and finally move AMD down to a 14nm node. For the architecture itself, AMD implemented SMT, completely redesigned its cache hierarchy, and added a micro-op cache to aid an updated branch predictor.

Two months after Kaby Lake rolled out, AMD launched the Ryzen 7 1800X. The revolution didn’t happen in a day. In our Ryzen 7 1800X review, reviewer Paul Alcorn (now Tom’s Hardware editor-in-chief) wrote: “AMD's Ryzen 7 launch represents more than just a new CPU family. For most of our readers, it signals the return of competition to the enthusiast-oriented processor market. And considering the flagship 1800X’s potent cost advantage compared to Intel's Core i7-6900K… Ryzen 7 does deliver. It's just not as universally superior as the company wanted everyone to believe.”

AMD still had quite the year ahead. A month later, the Ryzen 5 1600X launched with performance that could rival Broadwell-E, just for a much cheaper price. And by Summer, the Ryzen 3 1300X proved you didn’t need an expensive CPU and motherboard to get into overclocking. AMD capped its Ryzen rollout with Threadripper, scaling up the Zen microarchitecture to massive core arrays and finally bringing something to the HEDT market — a market that Intel had almost wholly owned since the Pentium 4 days.

Still, Zen had shortcomings, particularly in games, where just about any quad-core from Intel still ruled the roost. AMD was competitive, but Intel was still firmly in the driver’s seat. It barely reacted to the Ryzen onslaught over the summer, rolling out its high-end Skylake-X and Kaby Lake-X HEDT offerings throughout the back half of 2017. Even then, however, problems started emerging.

Kaby Lake-X was effectively a rerelease of Kaby Lake with a bit of extra headroom, but restricted to the expensive X299 platform. It was discontinued less than a year after release. Skylake-X was Intel’s true next-gen HEDT offering, signaled by the first use of “Core i9” in front of its flagship SKU. It performed like an Extreme Edition, and it was priced like one too, despite an issue in thermal dissipation that we uncovered in our Core i9-7900X review. Meanwhile, AMD was rapid-firing firmware and chipset updates for its small Ryzen range, and fixing several issues that came up in reviews in the process.

Less than a year after Kaby Lake launched, Intel released Coffee Lake, which was yet another Skylake revision built on 14nm, but this time with extra cores in tow. As you can read in our Core i7-8700K review, Coffee Lake did what Intel wanted it to do, shoring up the fight in heavily-threaded productivity applications against AMD while maintaining leadership in games. Still, AMD was making headway. By the end of 2017, estimates suggest AMD took back anywhere from 2% to 12% market share from Intel, with the higher end of the spectrum coming mainly from the DIY PC market. That’s no small feat for a company that was dead in the water with CPUs 12 months earlier.

Back on more even footing, the next goal post was a node shrink. Intel was gunning for 10nm, which is a milestone it failed to meet with both Kaby Lake and Coffee Lake. AMD, as a fabless designer, was at the mercy of its then-partner GlobalFoundries for the next node shrink. AMD struck first with Ryzen 2000 in early 2018, built on GlobalFoundries 12LP node, which was a revision of the 14LP (14nm) node used in the original Zen. Fittingly, AMD called it Zen+.

Debuting the architecture was the Ryzen 7 2700X, which was an iterative update. However, it helped reacquaint the market with the progress AMD had made. Zen+ came with higher frequencies and reduced memory latency, and all of the software adjustments AMD had made after the original Zen launch. And the range seemed specifically designed to undermine Intel, offering overclocking support across the full stack (and with B-series chipsets), and bundling a surprisingly decent cooler in the box.

Intel still held the edge in gaming, but the margins were narrowing, especially with a bit of overclocking thrown into the mix. Intel was feeling the heat, due in no small part to its continued issues moving down to 10nm. It responded in late 2018 with Coffee Lake Refresh, bringing the Core i9 branding into its main lineup for the first time with the Core i9-9900K and offering an eight-core, 16-thread chip. The strategy, it seems, was to push out AMD at the high-end, as Ryzen 7 was closing in on Core i7.

It worked. Intel had the fastest gaming processor on the market, and even the Core i7-9700K managed to push Intel’s lead in the Ryzen 7 battle higher. These marginal updates were buying time for AMD and Intel. Both companies clearly understood that whoever could go below 14nm first would have a massive advantage, and likely define an entirely new market dynamic.

AMD claimed that advantage for itself with the introduction of Zen 2 in mid-2019. Bolstered by TSMC’s 7nm node, AMD pushed out the Ryzen 9 3900X, moving beyond eight cores to AMD’s first 12-core consumer design. Intel held a slight edge in gaming through Coffee Lake Refresh, as you can read in our Ryzen 7 3800X review, but that delta was becoming less important as AMD took the lead in heavily-threaded workloads.

Later in the year, AMD rolled out the Ryzen 9 3950X, the first 16-core desktop processor ever. It was a bloodbath. Less than a year earlier, Intel had introduced its Skylake-X HEDT platform, including the Core i9-9980XE priced at $2,000. Now, at stock settings, the $750 Ryzen 9 3950X offered better multithreaded performance, along with competitive single-threaded and gaming performance. And you didn’t need to shell out for Intel’s expensive HEDT platform. And you could unlock PCIe 4.0, whereas Skylake-X (and even the following Cascade Lake-X) were locked to PCIe 3.0. You don’t spend top dollar on an HEDT platform for last-gen connectivity.

Intel was getting pushed into a corner, and it followed up less than six months later with Comet Lake to stave off AMD’s Ryzen onslaught. The flagship Core i9-10900K allowed Intel to maintain the lead in gaming, but now, AMD was in a clear lead in applications with the Ryzen 9 3950X.

Reviewing the Core i9-10900K, Alcorn wrote: “The Core i9-10900K is exactly what we would expect from an overclocked 10-core 14nm Skylake derivative: Exceptional performance in gaming and lightly-threaded workloads, competitive performance in multi-threaded work, and downright ugly power consumption and thermal output. And that's pretty much what you get with the Core i9-10900K – an overclocked 14nm processor right out of the box.”

AMD didn’t let up. It moved onto Zen 3 later in the year, launching its 16-core Ryzen 9 5950X alongside the main range in late 2020. And with its fourth Ryzen salvo launched, the battle was over. Opening our Ryzen 9 5950X review, Alcorn wrote, “With the Ryzen 5000 series, it's fair to say that AMD has finally, and fully, eclipsed Intel's performance dominance in desktop PCs.” It was a clean sweep, with AMD taking the lead in gaming, multithreaded, and single-threaded performance. Three years and four CPU generations later, AMD was back on top.

Forging a new path (2021 - 2024)

Forging a new path (2021 - 2024)

In the years leading up to 2021, it had become clear that a tick-tock, or even a tick-tock-tock, wasn’t possible any longer. Process shrinks were arriving later, and a pesky little pandemic threw the tight supply chain required for chip manufacturing into a frenzy. Both AMD and Intel knew they needed a different approach, but that would manifest in wildly different ways.

Intel was all-in on a hybrid architecture, using a mixture of microarchitectures on a single package to bolster core counts, similar to Arm-based designs. Intel talked a lot about Alder Lake leading into 2021, overshadowing its own launch of 11th-Gen Rocket Lake chips. The flagship Core i9-11900K was a massive disappointment, carrying all of the issues of the previous-gen Core i9-10900K while packing two fewer cores. Yes, Intel actually cut two cores from its flagship.

It seems Intel knew the issues with Rocket Lake. The chips launched with little to no fanfare, and as opposed to a gradual rollout like we see with most CPU generations, Intel blasted every model of Rocket Lake onto the market, knowing full well that Alder Lake chips would take their place eight months later. AMD, with renewed confidence, slowly built out the Zen 3 lineup with new APUs and variations of Ryzen 5000 as it worked on its next-gen Zen 4 architecture.

In late 2021, Intel swept Rocket Lake under the rug with the release of Alder Lake. Intel had finally moved on from 14nm with Intel 7 (10nm), and it was mostly successful. Intel reclaimed top placements in gaming, multithreaded, and single-threaded performance, and although the margins were thin, Alder Lake made it clear that Intel wouldn’t go quietly. “The Alder Lake processors mark a massive generational leap forward for Intel in nearly all facets, including gaming, performance in lightly- and heavily-threaded work, power consumption, overclocking, and platform connectivity options,” wrote Alcorn in our Core i9-12900K review.

AMD was working on something unique of its own, however. Zen 4 was in the oven, and it was clear there would be a competitive battle with Alder Lake. But before Zen 4 arrived, AMD introduced the Ryzen 7 5800X3D. It was the first processor with AMD’s 3D V-Cache packaging, and at the time, it looked like a slightly-tuned processor targeting gamers, with somewhere in the range of a 10% to 15% uplift in gaming performance specifically. In a surprising turn, the speculation actually undersold just how big of a deal the Ryzen 7 5800X3D would become.

Six months after the release of the Core i9-12900K, AMD was back on top of the gaming charts with the Ryzen 7 5800X3D, no less sporting a last-gen architecture and an SRAM stacking technique that limited boost clocks and locked the multiplier down. It outran the Core i9-12900K by nearly 10% in games while costing hundreds less, and it was nearly 30% faster than a stock Ryzen 7 5800X, as you can see in our Ryzen 7 5800X3D review.

Intel would come back with Raptor Lake in late 2022, but the Ryzen 7 5800X3D established a new category of true gaming CPUs that traded some application performance for peak frame rates. And that’s a category of chips that even today Intel hasn’t managed to crack.

AMD came first, however, launching Zen 4 in September 2022. The flagship Ryzen 9 7950X managed to leapfrog the Core i9-12900K, as you can see in our Ryzen 9 7950X review, but not by much, and the Ryzen 7 5800X3D remained at the top of the gaming charts. Immediately, speculation around 3D V-Cache chips for Zen 4 went into motion. Also tampering the Zen 4 release was an entirely new platform, which required costly DDR5 memory.

Intel capitalized with Raptor Lake mere weeks later. The flagship Core i9-13900K was back on top across tests, even managing to outclass the Ryzen 7 5800X3D in games. For the first time since the heyday of Athlon, we had a hotly competitive CPU market with AMD and Intel leapfrogging each other with each new release. Still, there was a niche that wasn’t being filled. 3D V-Cache disrupted the status quo for gaming processors, but it came with a significant trade-off to application performance. The stage was set for a CPU that could offer the best of both worlds.

AMD delivered that in early 2023 with the Ryzen 9 7950X3D and (to a much lesser degree) Ryzen 9 7900X3D. A couple months before, Intel cracked the 6 GHz barrier out of the box with the Core i9-13900KS, but AMD was offering something more compelling than peak clocks. The Ryzen 9 7950X3D managed to outclass Intel in multithreaded and single-threaded performance, all while offering a double-digit jump in gaming performance thanks to 3D V-Cache.

Raptor Lake saw a refresh later in 2023, and although the flagship was able to close the application performance gap in our Core i9-14900K review, AMD still held a firm grip on gaming performance, especially with the trimmed-down and relatively affordable Ryzen 7 7800X3D. AMD had taken the lead, but Intel, finally, executed its tick-tock-tock strategy and set its eyes on a radically new architecture in the form of Arrow Lake.

Reckoning with the real world (2024 - today)

Reckoning with the real world (2024 - today)

Under AMD’s thumb and clearly behind in pace, Intel needed to innovate. The result was Arrow Lake. Like Bulldozer, it’s easy to write Arrow Lake off in hindsight, especially given how recent it is. As you can read in our Core Ultra 9 285K review, Arrow Lake chips only marginally improved in application performance over their 14th-Gen counterparts, and they were actually slower across most games. But, architecturally, Arrow Lake is as big a swing as Bulldozer was.

For the first time, Intel outsourced manufacturing to TSMC, clearly behind the Taiwanese manufacturer for cutting-edge nodes. It disabled Hyper-Threading, killing off a staple of Intel CPUs for decades, and it doubled down on Intel’s hybrid architecture. Those bets didn’t pay off, but they were big bets for a company struggling to reckon with a reinvigorated AMD.

AMD followed up Zen 4, predictably, with Zen 5 in mid-2024, shortly before the Arrow Lake release. With Arrow Lakes' struggles, it’s easy to forget the problems Zen 5 had at launch, and the relatively small generational uplift it offers even today. AMD has continued to build out this lineup with X3D chips, and it finally delivered 3D V-Cache on both CCDs with the Ryzen 9 9950X3D2. But going back to our Ryzen 9 9950X review, Zen 5, at its core, isn’t the massive uplift we had become accustomed to in the early days of Zen.

Intel tried to give Arrow Lake a bit more life with a small refresh earlier this year in the form of the Core Ultra 7 270K Plus and Core Ultra 5 250K Plus, and those CPUs set the stage for the next era of CPUs. They put Intel into the position AMD found itself during the Bulldozer/Steamroller days, clearancing off silicon to maintain a competitive position in the market.

That’s where we are today, with our sights set on Zen 6 and Nova Lake. But there are some realities in the PC enthusiast space that we have to contend with today. DRAM pricing is out of control, and showing no signs of slowing down, and a sudden boost in demand for CPUs for agentic AI means consumer chips have taken a backseat. Zen 6 and Nova Lake were both expected by the end of the year; it’s looking more likely that they’ll slip into 2027.

History doesn’t repeat, but it often rhymes, and we can see traces of days past over the last 30 years start to creep into the dynamics today. Today, we see a defiant AMD and an Intel that seems ready to get scrappy in order to earn back market share. Will it pay off? We don’t know, but Tom’s Hardware will be here to cover whatever comes next in the world of CPUs, just as we’ve been for the past 30 years.

A then-practicing doctor and surgeon, Pabst began testing hardware in the early days of the desktop PC revolution, first publishing under the name of Tom’s Roadrunner Page in 1996, then rocketing the brand to fame after it evolved to become Tom’s Hardware Guide later that same year. In the early days, Pabst focused on testing motherboards and CPUs, but he also began testing graphics cards with the Nvidia Riva 128 being the first, followed by others like the 3Dfx Voodoo, among many, and he even penned a custom benchmark that was billed as the world’s first real-world 3D benchmark. Those foundational categories still live on today in our coverage.

Pabst’s biggest breakthrough came when he published an unsanctioned pre-release review of an Intel Pentium II CPU that he acquired from friends in the publishing business, who also published reviews. Naturally, Intel wasn’t fond of the resulting negative coverage, and the firm threatened to pull ads from two of the publications involved if the reviews weren’t removed. The ensuing spat garnered widespread coverage, with the conflict making it into the pages of the New York Times and other mainstream news outlets. Intel admitted to using its advertising contracts to threaten the sites and apologized, and the issue thrust the Germany-based Tom’s Hardware into the spotlight on the international stage right as CeBIT 1997 began, where Pabst met many of the industry contacts that helped move the site forward.

A few years later, Pabst discovered persistent bugs with the Intel Pentium III, some of which he exposed in Linux, which wasn’t commonly used for benchmarking at the time. Pabst refused to surrender his sample to Intel, saying it was his only proof of the issue. Due to the bugs Pabst discovered, Intel eventually pulled the processors from the market until a new chip stepping could be developed. Intel then excluded Pabst from coverage of the Pentium 4, which he viewed as another retaliation, sparking another very public conflict that cemented the brand's reputation for uncompromising independent journalism.

Tom’s Hardware Guide evolved over the intervening 30 years, spreading into new categories like networking and news coverage, eventually becoming known as Tom's Hardware — though it is still easy to spot our veteran readers because they still refer to the site as ‘THG.’ Pabst sold the site in 2007 to Best of Media Group and served as Chairman until 2008. Our sister site, Tom’s Guide, was born in 2007, and Tom’s Hardware has also branched out with multiple non-English licensees of the brand over the years, with Tom’s Hardware France and Tom’s Hardware Italy still operating to this day. Tom's Hardware was acquired by our current publisher, Future plc, in 2018.

PC building certainly looks a lot different today than it did when Pabst first began testing PC hardware. Back in those early days of the PC, things such as user-friendly BIOS tuning didn’t exist; enthusiasts simply adjusted jumpers and DIP switches to fine-tune their systems, paving the way for the overclockers of today with skill and a determination to wring more performance out of their systems. That spirit lives on in our coverage and in our vibrant community of enthusiasts.

You’ll see constant references to our past in our valued forums, where thousands of enthusiasts, from newcomers to veterans of 20 years or more (many who still remember setting DIP switches by hand), help the community solve vexing issues with their tech while also providing valuable insight and commentary on the latest happenings in the tech sphere.

Today, our ethos remains the same — we strive to deliver unbiased coverage of the latest technology, backed by comprehensive benchmarking to underline our conclusions, thus delivering the best possible buying advice to our readers. We now cover the full breadth of PC components and peripherals while continuing to branch out into new areas that resonate with our audience, such as 3D printing and associated products, but we’ll always remain grounded in our core areas of PCs and PC components.

Despite newfound challenges facing the publishing business, such as the rise of AI that lifts our expertise without compensation — and often without attribution — and an ever-more punishing Google landscape, we work tirelessly to stay on our current growth trajectory while developing additional new means to serve our readers, such as our Tom’s Hardware Premium service. This subscription-based service provides our readers with longer-form news, analysis, testing, and features for those who want to dig even deeper into our core coverage areas. Our service also includes access to our Bench database, which provides up-to-date benchmarks of the latest PC hardware in an easy-to-compare format.

The silicon, software, and publishing landscape have all changed dramatically over the last three decades, but our goals haven’t shifted, and yes, we still carry on with many of our old traditions. We thank you, the readers, for providing us with the opportunity to share our passion for hardware with you for the last thirty years, and invite you to join us for the next 30.

Before getting on with the digital signage-to-gaming conversion, Garkus investigated the hardware in hand. Labeling indicated that the three slim mini PCs were all Advantech DS-081 models (official PDF link). Pondering over that data sheet, we see that the variant with the Intel Core i3 6100U, as these were, carries the full designation of DS-081GB-U21A1E.

The processor is now both long in the tooth and low powered, so immediately we know this 2C/4T @ 2.3 GHz CPU, configured to suck between 7.5W and 15W, won’t be ideal for modern AAA titles. Moreover, the iGPU is the Intel HD Graphics 520 with 24 EUs and clocks up to just 1.00 GHz, sharing the DDR4 system RAM.

A DS-081GB-U2A1E is quite expandable for such a small, low-powered set-it-and-forget-it unit. It has twin HDMI 1.4, twin Ethernet, four USB 3, audio in/out, and an RS-232 serial port accessible from the outside. Inside, users can configure the machine via twin DDR4-2133 SODIMM slots (up to 32GB total), a SATA III HDD/SSD, and an mSATA port that looked like it was an M.2 2242 slot in the video. This passive machine is designed to run signage 24/7 in environments with 0 ~ 40° C (32 ~ 104 ° F) ambient temperatures.

Setup and gaming

These systems were found to actually come with just 4GB of RAM (one slot used) and with a 64GB SATA SSD installed. They booted to Windows and went straight to kiosk mode, displaying the Subway sandwich menu. We saw an extra 4GB DDR4 stick added to bring the test system(s) up to 8GB RAM in total.

After a bit of OS wrangling, Garkus decided to set up the salvaged trio of passive mini PCs as follows. One kept Windows 10, another got Bazzite Linux (because SteamOS balked at the SATA-only storage), then another went Hackintosh with macOS Monterey installed.

Gaming tests began with a very light test. The system ran Peggle, and this 2D puzzler posed no problems. After this modest victory, Garkus ambitiously leapt straight to GTA V. This legendary but now older title could only reach a frame rate of about 15 fps. But it was found to have defaulted to high settings, took ages to get ready to run on Bazzite, then crashed on exit.

Probably not following best benchmarking practice, the tech tinkerer appears to have decided to test Mario Kart Wii emulation performance while GTA V was still compiling shaders… Later, a test run in Minecraft delivered a wildly inconsistent but roughly 25 fps performance. As is now established as the Garkus testing MO, resolution, quality settings, and so on weren’t shared.

To conclude the gaming part of the video, the TechTuber suggests that these ex-kiosk machines are probably best suited to emulating older consoles up to the PS2 and original Xbox era. We think that for PS2 emulation, you will still need to restrict yourself to lighter titles and reduced settings for smooth action.

Intel provided Rosaic access to an unknown Atom-class core, which enables the company to build its own custom processors based on x86 general-purpose cores, according to the report. The renowned chipmaker plans to ship Rosaic register-transfer level (RTL) code ​for the Atom processor core, which will let the startup build its custom system-on-chip (SoC) both at Intel Foundry and elsewhere.

The startup is reportedly led by Amarjit Gill, a venture capital investor who partnered with Intel's CEO, Lip-Bu Tan, on multiple occasions in the past. The two invested in such companies as Nuvia and Rivos, which were later acquired by Qualcomm and Meta, respectively.

RosaicLabs does not have a website or a LinkedIn profile, which is common for startups when they operate in stealth mode. The company was incorporated in May and is currently seeking a seed funding round of $10 million, according to a document seen by Reuters.

Since RosaicLabs does not have a website or a LinkedIn profile, it is completely unknown what kind of SoC it plans to develop and which markets it is going to pursue. One could imagine that it is in Intel's interests to license technology to companies that seek to address markets which Intel has no plans to address.

Arguably the biggest question is which Atom-class core Intel licensed to Rosaic. Traditionally, Atom cores were developed for inexpensive low-power devices, applications that Intel ceased to address about a decade ago. Since then, the low-power x86 architecture has been used to build custom SoCs for telecom and adjacent applications, embedded CPUs, efficiency (E) cores for client CPUs, and more recently cloud-optimized Xeon processors. Intel's most advanced low-power x86 cores to date are Crestmont, which powers Xeon 6700E-series CPUs, Skymont, which is used in Core Ultra 2-series CPUs, and Darkmont, which powers Xeon 6+ CPUs.

Skymont and Darkmont feature a 9-wide decode, 8-wide out-of-order engine, and 16-wide retire, which makes them fairly capable cores that wed high performance potential with energy efficiency. Meanwhile, Darkmont is optimized for data center workloads, so it has better branch prediction, improved prefetch, an enhanced vector engine, and higher L2 bandwidth. By contrast, Crestmont features a 6-wide decode and an 8-wide retire, which puts it well behind the newer cores.

If Intel gives Rosaic complete, synthesizable RTL of an Atom-class core, Rosaic could technically modify the core at several levels, including changing cache sizes, reorganizing the pipeline, increasing clocks, and altering power-management logic, just to name a few options. However, this does not automatically mean Rosaic has unrestricted rights to enhance Intel's technology, as the company could provide RTL under various conditions with numerous restrictions. After all, it does not want to create a competitor for itself. Still, we do not know the terms of the license.

Intel granted about a dozen manufacturing licenses to build its 80286 and 80386 CPUs in the 1980s to various chipmakers in a bid to provide chipmakers with second sources for its processors and expand usage of its x86 ISA. However, only AMD got an actual x86 license that allowed it to build x86 CPUs of its own designs.

After disposing of its StrongArm/XScale business to Marvell in 2006, Intel witnessed the smartphone revolution essentially empty-handed as its Atom processors could not compete with highly integrated Arm-based SoCs in handsets. Intel tried to expand the reach of its low-power Atom CPU cores in 2009, so it signed a memorandum of understanding with TSMC and planned to port its Atom cores to a TSMC node and enable TSMC clients to integrate that hard IP into their processors.

That initiative has never taken off, so eventually Intel kicked off its SoFIA (Smart or Feature Phone on Intel Architecture) joint SoC development program that enabled third parties to use Intel Atom cores and modem technology (implemented using TSMC's 28nm node) in their application processors for handsets. While both Rockchip and Spreadtrum eventually came up with their SoFIA 3G and SoFIA 4G SoCs based on Airmont cores and made on TSMC's 28nm technology, both processors were released in 2015, had to compete against SoCs made on Samsung's 14nm-class node or TSMC's 16FFC node, and never got popular. Ultimately, Intel produced an eight-core Spreadtrum SoC at its fabs using its 14nm manufacturing technology, but that processor also failed on the market.

As a result, Intel licensing a CPU core to a third party is a very rare occurrence these days and the first in this decade. The reasons behind the move are completely unclear because the RosaicLabs startup is two months old, it cannot pay Intel cash, and its commercial prospects are completely unclear. While one may argue that now that Rosaic has access to x86 cores, it is not going to pursue Arm or RISC-V cores, keeping in mind that hundreds of startups choose Arm or RISC-V every year, addressing one startup does not enable Intel to expand its x86 share compared to Arm or RISC-V tangibly.

In any case, for now, the deal between Intel and RosaicLabs leaves more questions than answers, mainly because all we know about RosaicLabs is that it is led by an old acquittance of Intel's chief exec, Lip-Bu Tan.

The announcement doesn't name any customers that Intel may have secured as a result of RAMP-C, although the program roster has been public for years and includes Nvidia, Microsoft, IBM, Qualcomm, Boeing, and Northrop Grumman. That may be down to the sensitive nature of any actual defense industrial base (DIB) products that are likely to be produced with the Secure Enclave defense-focused manufacturing flow for those products, which spans project stages from design to chip fabrication to advanced packaging.

Intel says RAMP-C was one of the programs that influenced Secure Enclave, and having a number of potential DIB customers run and test prototypes on 18A through likely generated valuable knowledge for Intel, the U.S. government, and its partners as those stakeholders work together to create a defense-ready domestic chip source.

Stu Pann, then SVP and GM of Intel Foundry Services, told Tom's Hardware back in February 2024 that the program's announced partners were IBM, Microsoft, and Nvidia, and that all three were running test chips paid for by RAMP-C. The funding let them "operate with immature PDKs, which normally they wouldn't do," Pann said, and covered their associated costs. Intel got PPAC data in return: how prospective customers rated 18A on power, performance, area, and cost.

Intel disclosed the roster in stages rather than all at once. Nvidia, Qualcomm, Microsoft, and IBM were named across the first two phases, Boeing and Northrop Grumman joined in July 2023, and Trusted Semiconductor Solutions and Reliable MicroSystems came in under a third phase that Intel says was awarded in April 2024.

Nvidia's participation runs back to the program's early phases, four years before it agreed to buy $5 billion of Intel common stock in September 2025, a deal that closed in December at $23.28 per share for more than 217.4 million shares. That agreement covers custom x86 CPUs and RTX SoCs, and carries no commitment to manufacture Nvidia silicon at Intel.

Secure Enclave, the follow-on program Intel references, is worth up to $3 billion and was finalized alongside the company's $7.86 billion CHIPS Act award in November 2024. Congress required that CHIPS money pay for it, which is why the commercial grant is smaller than the $8.5 billion originally proposed.

Intel Foundry booked $293 million in external revenue last quarter against $5.8 billion in total segment revenue and a $2.1 billion operating loss, according to the company's Q2 2026 financial results. Fortinet, named last week as the first publicly disclosed external foundry customer under CEO Lip-Bu Tan, is building its security processor on Intel 4 rather than 18A. On the same earnings call, Intel committed to 14A high-volume manufacturing in 2028.

The GHz race ends with an architectural revolution

One of the defining characteristics of the first Intel Core 2 Duo chips was that they kicked the GHz race to the periphery of the battlefield. After years of chips being sold with this performance statistic placed most prominently, Intel and the tech media had to educate the wider public that higher GHz numbers didn’t define performance.

Intel Conroe desktop chips came with a generational performance uplift we don’t see often. These third-generation dual-core processors from Team Blue would “provide up to a 40 percent increase in performance and are more than 40 percent more energy efficient versus Intel's previous best processor,” according to launch-day PR. Testers also observed that even the entry-level new Conroe chips could outpace the mighty flagship desktop Pentium Extreme Editions, despite running at nearly half the clock speed.

Behind the real-world performance successes Intel eagerly highlighted, and reviewers seemed genuinely excited by, there were a number of architectural innovations and refinements. Intel boasted that the Core 2 Duo contained “a whopping 291 million transistors” and had achieved many benchmark firsts in internal tests. Conroe arrived with higher efficiency, shorter pipelines, improved branch predictions, new shared Smart Cache, and substantially higher IPC, all built upon Intel’s newest 65nm process technology. With this attractive new price, it wasn’t difficult for Intel to retire its former king, with its hot, power-hungry, and big GHz Netburst architecture.

Defining the next decade+

With the Core 2 Duo, Intel regained its performance leadership from AMD and its Athlon parts. Conroe, the desktop Core 2 architecture, didn’t get singled out in our five best Intel CPUs of all time article (2024), but it was the direct ancestor of the legendary Core 2 Quad CPUs. These quad-core CPUs would take the Gillette-like next logical step with four cores on a chip, combining two Conroe dies in a single package, and launching in January 2007.

Moreover, from the mid 2000s onwards, multi-core became mainstream and developers seriously began to optimize applications and games for processors boasting more than just Core 0. Admittedly, single-threaded performance can still be important in Windows/apps/games in 2026.

To conclude, Intel’s Conroe would set the foundations for the firm’s CPU market dominance for more than a decade. Most would argue this successful run lasted all the way until the AMD Ryzen family matured and hit full stride with the Ryzen 3000 series.

After two cities in the region denied the California-based AI data center recycled wastewater for cooling, it filed a lawsuit demanding to get water from the Colorado River for cooling. The 330-megawatt facility was not only designed to be the biggest AI data center in California, but it specifically committed not to use water from the Colorado River because it was promised wastewater. But now the owner of the data center is essentially asking to redirect water supply from agriculture to the facility.

Imperial Valley Computer Manufacturing — the owner of the 330 MW AI data center — is requesting access to approximately 287 million gallons of water per year after two cities — El Centro and Imperial — declined to supply reclaimed wastewater for cooling. The Imperial Irrigation District (IID), which distributes Colorado River water throughout Imperial Valley, also denied the company's request. The Colorado River supplies water to roughly 40 million people across seven western states and serves as the valley's sole freshwater source for roughly 180,000 people. Agriculture consumes about 80% of California's allocation from the river, while roughly 95–97% of the water IID delivers goes to agriculture.

The data center is seeking roughly 287 million gallons per year (about 750,000 gallons per day, or ~880 acre-feet per year), whereas the Imperial Irrigation District (IID) holds rights to approximately 3.1 million acre-feet of Colorado River water annually, which means that the data center demands only a small fraction — 0.028% — of IID's total water supply.

Sebastian Rucci, a Huntington Beach attorney who leads the project, claims that the facility's water consumption would be comparable to that of a 160-acre farm and will require no additional Colorado River allocation. In fact, he states that the facility would not increase pressure on the river because the company intends to purchase nearby farmland together with its associated water allocations.

Under the proposal, irrigation on those properties would cease, thus transferring the existing water quotas to be redirected to the data center cooling, at the expense of local farming output and associated jobs. "There's a lot of resistance in any agricultural community to 'buy and dry' because that's jobs," a senior fellow at the Pacific Institute focused on Colorado River Basin water use told the outlet. According to them, local resistance to the plan is less about the amount of water, and more about buying up farmland and reallocating it for industrial use.

The approach, of course, differs from the earlier plan that intended to avoid using Colorado River water altogether. However, after the data center was denied wastewater from two cities, it does not have a choice if it wants to go ahead with the buildout.

Rucci reportedly indicated that the project would provide substantial economic benefits for the local community, including 1,688 construction jobs, more than 100 permanent positions, and an estimated $2.95 billion in economic impact over 30 years. For a region where unemployment stood at approximately 17% in May, the economic diversification is essential. However, the big question is whether 100 permanent roles could offset the lost positions in the farming industry and industries tied to agriculture.

Water policy specialists interviewed by Business Insider said that the debate extends beyond the project's annual consumption. Instead, they questioned whether converting irrigated farmland into industrial use is an appropriate long-term direction for the region, which has historically depended on farming. The experts also warned that although landowners could benefit from selling land or water rights, surrounding rural communities may lose employment and business activity adjacent to agriculture, which includes equipment suppliers, repair shops, and sellers of fertilizers. Another factor mentioned by the experts was the U.S. reliance on farms around Imperial, California, and Yuma, Arizona, as they were the main suppliers of certain agricultural products in winter.

We wrote about the F-14 Tomcat’s CADC last year after discussions erupted on social media about whether this flight computer was actually powered by the "world’s first microprocessor." The brains behind the CADC were provided by the MP944. This chip lived in the shadows for quite some time, though. Despite the MP944 microprocessor beginning service in June 1970, over a year before Intel’s legendary 4004 would become available (November 1971) it was an official secret until 1998. Thus, the Intel 4004 managed to steal the limelight from the true first microprocessor, say those in the MP944 camp.

To recap, the MP944 was a 20-bit, pipelined, parallel multi-microprocessor melded with state-of-the-art MOS technology and ran at 375 kHz, executing 9,375 instructions per second. The flight-system powering chip, designed by Steve Geller and Ray Holt and a 25-strong team, also passed stringent ruggedness tests and was capable of running in temperatures spanning -55 to +125 degrees Celsius.

The MP944 worked as part of a six-chip system in the CADC, for the real-time calculation of flight parameters such as altitude, airspeed, and Mach number – and was a key innovation to enable the Tomcat’s articulated sweep-wing system. So it had to be performant, and some chip architecture enthusiasts assert that the MP944 was actually “8x faster than the Intel 4004.” Remember though, the Intel chip was originally designed for a far more humble desktop calculator.

3D printed F14 swing wing test

Getting back to Adam Taylor’s recent achievement, and we now have a full open source set of VHDL source code, documentation, and testbenches for an FPGA recreation of the F‑14’s CADC. The GitHub repo says the FPGA used was a Spartan-7 based SoM, part of the Adiuvo Embedded System Tile. The resource isn’t just the MP944 logic, Taylor includes complete synthesizable VHDL implementations for all six original CADC chips.

Typically, companies initiate high-volume manufacturing (HVM) using a new process technology about a year after initiating risk production. Assuming that Intel intends to start risk production using 14A in the second half of 2027, it is reasonable to expect the company to start 14A HVM in the second half of 2028. It remains to be seen whether by the 'second half' Intel means July or December. If Intel initiates high volume ramp in November or December 2028, actual products made using the technology will emerge in 2029. In any case, Intel typically begins manufacturing using its leading-edge nodes in its development fab in Oregon and while it formally calls it HVM, actual volumes produced at such fabs are relatively low.

Another thing to note about Intel's 14A is that in 2028 it will start making its own products using this process, not products from external customers. Apparently, Intel still does not have any external clients that have committed to use the technology to make their products.

TSMC typically initiates production using its latest nodes in December and usually calls it the 'second half of the year.' Assuming that it follows the same pattern with A14 (though the progress of the node can enable the company to pull mass production in provided that customers' designs are ready), then the volume ramp will occur in 2029. TSMC claims that multiple customers have already taped out their ICs on A14.

Intel reported a strong second quarter as its revenue reached $16.1 billion, up 25% year-over-year and $1.8 billion above the midpoint of its guidance. Formally, Intel's GAAP losses reached a whopping $11 billion. However, this was driven by the $13.619 billion of mark-to-market losses on Escrowed Shares related to Intel's CHIPS Act Secure Enclave agreement with the U.S. government. Meanwhile, the company's non-GAAP net income was $2.2 billion, which reflects profitable underlying operations. The company's GAAP gross margin increased to 40.1%, up from 27.5% in Q2 2025. Intel's Operating cash flow totaled $7.0 billion, prompting the company to raise its capital spending outlook for both 2026 and 2027 as AI-driven demand continues to exceed available supply.

Intel's Client Computing and Physical AI Group (CCPG) generated $8.9 billion in revenue, up 13% year-over-year. The company confirmed that the CCPG result was not driven by increased unit sales, but was a result of higher average selling prices (ASP) due to supply constraints.

"Client obviously exceeded expectations. I would say it was largely ASP, of which some of that was mix related, some of that was our own like-for-like changes in ASPs where we thought we had seen some inflation on our cost and needed to pass that on to the end customer," said David Zinsner, chief financial officer of Intel, during the call.

The Data Center and AI (DCAI) business delivered the strongest growth as its sales climbed 59% year-over-year to $6.3 billion amid surging demand for Xeon processors, expanding AI infrastructure deployments, and rapidly growing purpose-built silicon sales.

"Q2 year-over-year server growth was the strongest on record, Xeon 6 continue to be one of the fastest ramping products in Intel history, reflecting improving execution and strong customer demand," Tan said.

"We also continue to see strong momentum in our purpose-built silicon product line, with revenue up roughly 20% sequentially and nearly tripling year-over-year," Zinsner said. "Purpose-built silicon revenue nearly tripled year-over-year."

Intel Foundry posted $5.8 billion in revenue, an increase of 31% year-over-year, as Intel 18A production ramped. At the same time the production units losses dropped to $2.1 billion — down from $2.4 billion in the previous quarter and $3.2 billion in the same quarter a year ago. External foundry revenue reached $293 million.

"Intel Foundry operating loss in Q2 was $2.1 billion and $348 million better quarter-over-quarter as higher yields improved cycle times and increased factory scale across Intel 4, Intel 3, and 18A drove improved wafer costs," Zinsner said.

Intel guided its third-quarter revenue to $15.8 billion – $16.8 billion and a projected non-GAAP gross margin of 42% and an EPS of $0.38.

Some customers have discussed commitments running two years or longer, one of the people told Reuters, with the deals covering unit volumes only, which leaves Chinese cloud providers and internet companies fully exposed to a market that has already added 40% to some CPU prices in under seven months. Memory makers struck similar long-term agreements with hyperscalers over the past year as AI demand consumed DRAM and NAND output, but those contracts typically trade a volume commitment for some pricing visibility. Buyers here get neither price protection nor, based on current lead times, fast delivery, but they do get a place in the queue.

Intel said in March that it was pursuing long-term agreements with potential customers as server CPU demand spiked, with CEO Lip-Bu Tan telling analysts on the company's April earnings call that demand "continues to run ahead of supply," singling out Xeon server parts. Tan also cited a multi-year supply deal with Google among several long-term contracts signed in the first quarter, so the model now spans U.S. hyperscalers and Chinese channel buyers alike.

Reuters first reported in February that Intel had warned Chinese customers of lead times stretching to six months on some server CPUs, with AMD quoting eight to 10 weeks. By late March, server makers told Nikkei Asia that average CPU lead times had blown out from one to two weeks to eight to 12 weeks and beyond. Intel CFO David Zinsner put a value on that in April, telling investors that unmet Xeon demand "starts with a B," and the company later confirmed price hikes on select consumer and server CPUs.

Agentic AI workloads are driving much of the demand, as inference and orchestration tasks pull server CPU-to-GPU ratios back toward parity. AMD, which is due to report earnings in early August, has raised its server CPU market forecast to more than $120 billion by 2030, based on the same trend.

Intel will report its second-quarter results later today, where the shortage and the durability of these commitments are likely to come up. Chinese buyers remain cut off from the most advanced AI accelerators under U.S. export controls, but Xeon and EPYC server CPUs carry no such restrictions, making them one of the few U.S.-made AI infrastructure components China can still purchase freely, if it can get them.

Intel 4's record

Intel's Accelerated announcement back in July 2021 said that Intel 4 would reach production readiness in the second half of 2022 for products shipping in 2023, naming "Meteor Lake for client and Granite Rapids for the data center." The release and its accompanying fact sheet, however, contained no reference to foundry customers, networking, or custom ASICs on the node.

At VLSI 2022, Intel disclosed that it wasn't building a high-density library for Intel 4 and that Intel 3 would be the first new node offered through what was then Intel Foundry Services. A 2024 post on Intel's own foundry blog describes Intel 3 as "Intel Foundry's first leading-edge process node," and Intel's fiscal year 2024 annual report listed the processes available to external customers as 18A, Intel 3, Intel 7, Intel 16, and a 12nm node co-developed with UMC. Intel 4 appears nowhere on that list.

Ericsson's RAN Compute processors, announced in November 2023, were built on Intel 4, so Fortinet's part won't be the first third-party silicon to come off the node. That work grew out of a bespoke Intel-Ericsson collaboration, though, and Ericsson's formal foundry agreement with Intel, announced in July 2023, covered 18A. Fortinet is the first named customer buying Intel 4 as a foundry service, and the first cybersecurity vendor on any Intel node. The Ericsson engagement is also the closest thing in the public record to networking silicon on Intel 4, two years after the strategy Intel now says it outlined for the node.

Fab 34 economics

Intel 4 entered high-volume manufacturing at Fab 34 in Leixlip, Ireland, in September 2023, producing the compute tile for Meteor Lake-based Core Ultra chips, and shares the fab with Intel 3. Intel sold a 49% stake in the facility to Apollo-managed funds for $11.2 billion in June 2024, then bought it back in April 2026 for $14.2 billion, funded with $7.7 billion in cash and $6.5 billion in new debt. That buyback returned 100% of Fab 34's wafer economics to Intel at a premium of roughly 27%, and it only pays off if the fab's EUV capacity stays loaded.

Meteor Lake is aging out of Intel's lineup as 18A-based Panther Lake ramps through 2026, which leaves open the question of what fills Intel 4 capacity next. A multi-generation firewall ASIC program is a reasonable answer with mature yields, a customer that values supply stability over bleeding-edge density, and a part Intel described as tailored for cost-sensitive applications. Intel said in April that yields were improving across Intel 4, Intel 3, and 18A.

Fortinet's supply chain

Fortinet's 2025 annual report names Renesas and Toshiba America as the contract manufacturers for its ASICs, utilizing foundries in Taiwan and Japan operated either by TSMC or by the contract manufacturers themselves. The current SP5, a monolithic 7nm Arm-based SoC announced in February 2023, sits in that supply chain, so SP6 on Intel 4 moves Fortinet's next flagship security processor out of a TSMC-linked flow and into Intel's. The disaggregated design language in the announcement points to a chiplet-based part, a first for Fortinet's SP line.

Fortinet re-engineered three FortiGate models in 2022, the 70F, 600F, and 3700F, to accept alternative components during the chip shortage, and CMO John Maddison told SDxCentral at the time that the company wouldn't wait for parts to arrive in 2023. The "resilient and diversified" supply chain used in the SP6 press tracks back to that experience. Ken Xie called Fortinet "the #1 firewall leader with a 55% unit market share" in the company's 2025 results in February, with approximately six million FortiGates deployed, so there’s real, substantial volume here even if the parts are relatively inexpensive.

Intel Foundry reported $307 million in external revenue for 2025, up from $159 million the year before, against total foundry revenue of $17.8 billion and an operating loss of $10.3 billion. External revenue in Q1 2026 was $174 million. Fortinet's hardware business runs at roughly 30% of its revenue, and, per analysis from ServeTheHome, SP6 is ultimately a component of a portion of an annual hardware stream around $2 billion, so the deal won't move Intel's foundry line materially, even at full production.

CEO Lip-Bu Tan told CNBC in May that he expected commitments from multiple foundry customers in the second half of 2026, and Intel told investors in January that two prospective customers were evaluating 14A test chips. The SP6 announcement comes inside Tan's stated window, and it finally gives Intel something its foundry marketing has lacked in a named customer with shipping volume on a node with mature yields. Meanwhile, an 18A or 14A commitment from a major external customer is still missing, and Fortinet's cost-sensitive parts on a 2023 node don't substitute for one.

Intel told Tom's Hardware that SP6 will be built on Intel 4, the EUV process the company has so far used only for its own products, making Fortinet both the first cybersecurity vendor named as an Intel silicon customer and the first named external customer for the node. However, the announcement specifies no production timeline, and it comes in the same Q3-Q4 2026 window in which CEO Lip-Bu Tan said the company expects commitments from multiple foundry customers.

SP6 will draw on what the companies described as Intel's expertise in disaggregated semiconductor design and advanced packaging tailored for both AI-enabled and cost-sensitive applications.

That points to a chiplet-based part, which would be a departure from the current SP5, a monolithic 7nm Arm-based SoC that Fortinet launched in 2023 for its entry-level and mid-range FortiGate appliances. The deal will help Fortinet "accelerate and strengthen our ASIC strategy," said Ken Xie, founder, chairman, and CEO of Fortinet, in the announcement.

Intel 4 was the company's first process node to use EUV lithography and entered high-volume manufacturing at Fab 34 in Ireland in September 2023, where it produces the compute tile for Meteor Lake-based Core Ultra chips. The node didn't appear among the processes Intel listed for external foundry customers in its fiscal year 2024 annual report, which named 18A, Intel 3, Intel 7, Intel 16, and a 12nm process co-developed with UMC. Intel said the SP6 work reflects plans it laid out for Intel 4 several years ago, including support for custom networking ASIC workloads.

Microsoft agreed in early 2024 to build an unnamed custom chip on Intel's 1.8nm-class 18A node, a deal that reportedly covers a next-generation Maia AI processor. That announcement followed a similar pattern, with no product details, node variant, or timeline at signing and specifics emerging over the following 18 months.

Intel CFO David Zinsner said in March that the company was fielding inbound interest in 18A-P from prospective foundry customers as yields improved, and Tan told CNBC in May that foundry commitments were expected in the second half of 2026.

Fortinet does bring real volume, though, if not marquee volume. IDC ranked Fortinet first in firewall appliances shipped as of early 2023, with a 48% unit share. The company ships its own ASICs across its entry-level and high-end FortiGate ranges, and SP6 extends a silicon program now in its sixth generation.

Neither company committed to work beyond SP6, though the release described the agreement as a starting point, with further collaboration on chip technology and manufacturing under discussion.

“As part of our broader strategy to become a more focused and efficient company, (the data center group) is aligning its organization to ensure it has the right roles and skills in place to position the business for long-term success,” Intel told the publication in a statement. It also added, “We are committed to treating all impacted employees with respect and providing resources to support them through this transition.” Unfortunately, the company did not say how many positions will be cut and when it is happening — it only assured that the reduction-in-force won’t affect its business commitments and plans to launch new products.

While the AI infrastructure build-out was initially powered by GPUs and memory chips, advancements in agentic AI have greatly increased the demand for CPUs, putting Intel in a good position with its Xeon chips. Aside from that, the company is reporting customer interest, possibly including Apple, for its 18A and 14A nodes. It’s also planning to launch an AI GPU in the latter half of 2026 that will compete against Nvidia’s RTX Pro 5000 GPU.

This is a slow reversal of its misfortunes in the first half of the decade, but it seems that it’s not happening fast enough for its data center group employees who will be affected by the job cuts. It’s quite surprising that Intel plans to gut its Data Center group, which is one of its strongest performers and is in a good position to take advantage of the ongoing AI data center boom. But despite the high demand for AI data centers, it seems that the company still needs to cut its personnel count to streamline its operation.

The report also claims to reveal the review embargo windows and launch timeline for several Nova Lake models: Intel will initially introduce a 28-core DS package, which is expected to launch between January and March 2027. The new DS suffix is said to be an internal package designation for processors featuring dual-compute tiles.

This will reportedly be followed by 28-core K-series (unlocked) models between March and April 2027, while 16-core and 8-core variants are expected to arrive between late March and May 2027. The flagship 52-core DS model is reportedly scheduled for a much later launch, potentially between late May and September 2027.

While Intel is yet to officially confirm a launch date for Nova Lake, various leaks have suggested that the lineup could be one of the company's biggest generational leaps in recent years. The flagship desktop SKU, featuring a 52-core configuration, is expected to combine 16 Coyote Cove Performance (P) cores, 32 Arctic Wolf Efficiency (E) cores, and four Low Power Efficiency (LPE) cores. This would be a notable jump over the current Core Ultra 9 285K, which features a total of 24-cores. The introduction of Coyote Cove and Arctic Wolf also points to an entirely new CPU architecture, replacing the Lion Cove and Skymont cores found in Arrow Lake.

Nova Lake is also rumored to bring new platform upgrades including support for DDR5-8000 memory, up to 24 PCIe 5.0 lanes for expansion, Thunderbolt 5, and Intel's next-generation Xe3 Celestial integrated graphics. The processors are also expected to feature an upgraded NPU5 for AI workloads along with a 150W Processor Base Power (PBP) and 253W Maximum Turbo Power (MTP) on the flagship model, despite the substantial increase in core count. Earlier reports have also indicated that Nova Lake will transition to a new LGA1954 socket, meaning users will likely need a new motherboard to upgrade from the existing Arrow Lake platform.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

The announcement comes just shy of a year after CEO Lip-Bu Tan cancelled Intel's planned €30 billion fab complex in Magdeburg, Germany, and a €4.6 billion assembly and test plant in Wrocław, Poland. Those cancellations came with a memo in which Tan wrote that Intel had "invested too much, too soon – without adequate demand."

The Ireland program, however, passes the test Magdeburg failed on every measure that Intel boss Lip-bu Tan set: It uses cleanrooms that already exist; it's funded from Intel's own capex with no announced state aid; and it expands an already shipping revenue product into a demand pipeline Intel says currently exceeds its supply.

What €5 billion buys

It’s understood that no new manufacturing plants are part of the program, with the money instead going to upgrades of existing fab facilities, installation of leading-edge production equipment, and an expansion of the automated track system that links the campus's manufacturing modules into a single production flow. Intel said the work began earlier this year and will employ around 2,000 specialized tradespeople during the build-out, on top of the permanent hires.

Fab 34 is the focal point of the spending, with Chandrasekaran telling the Irish Times that "Ireland is our centre of excellence for Intel 3; we are not running Intel 3 in any other Intel manufacturing facilities." The fab began high-volume production on Intel 4 in September 2023, as the first EUV facility in Europe, and it now runs both Intel 4 and Intel 3, producing compute tiles for Core Ultra parts and Xeon 6 server processors. Intel has spent more than €30 billion in Ireland since 1989, over half of it between 2019 and 2023, doubling the campus's manufacturing footprint.

The spending follows directly from a transaction Intel closed in April, when it bought back the 49% stake in the Fab 34 joint venture it had sold to Apollo-managed funds for $11.2 billion in 2024, paying $14.2 billion to reclaim it. Apollo walked away with a roughly 27% gain in under two years. Intel now owns 100% of every wafer Leixlip produces, so each additional Intel 3 wafer the €5 billion generates flows entirely to Intel's own margin, rather than being shared with an outside capital partner.

The projects Intel cancelled

Magdeburg had roughly €9.9 billion in pledged German subsidies attached when Tan killed it, and Wroclaw had €1.9 billion in approved EU state aid. Fab 38 in Kiryat Gat, Israel, remains paused, and the Ohio site has slipped to around 2030. Every leading-edge wafer Intel produces for the foreseeable future comes from three U.S. states and one Irish campus, a concentration that made Leixlip the only European site left to expand and the cheapest place anywhere in Intel's network to add advanced capacity quickly, since the shells, EUV tools, and workforce are already in place.

Intel's Data Center and AI revenue rose 22% year over year to $5.1 billion in Q1 2026, and CFO David Zinsner told analysts on the April earnings call that Intel faces "unprecedented demand for silicon," with demand exceeding supply across the company's server lines. Intel Foundry revenue grew 16% to $5.4 billion in the same quarter, but external foundry revenue was just $174 million against a $2.4 billion operating loss, so the wafers that pay for Leixlip's tools are overwhelmingly Intel's own Xeon chips, rather than customer designs. A single campus running the entirety of a revenue-critical node also concentrates risk: Any disruption at Leixlip has no second source, because Intel 3 exists nowhere else.

Europe's most advanced node, without European money

Intel 3 is now the most advanced process technology manufactured anywhere in Europe, and Chandrasekaran told the Irish Times the expansion provides "a technology sovereignty within the EU that the EU is targeting." Interestingly, no EU or Irish state aid accompanied the announcement, which distinguishes it from TSMC's €10 billion ESMC fab in Dresden, where the European Commission approved a €5 billion funding package for a plant producing 28/22nm and 16/12nm chips for automotive and industrial customers, scheduled to be operational from late 2027. Europe's only leading-edge logic production is self-funded by an American company for its own products, while its subsidized flagship project makes trailing-edge silicon.

Commercial electricity in Ireland runs up to twice the rates Intel pays in Arizona or Taiwan. Intel warned Irish ministers in August 2025 that its competitiveness was under threat from energy costs, and the company flagged up to 195 mandatory redundancies at Leixlip in mid-2025 as part of its global workforce reduction. IDA Ireland paid Intel €30 million in 2023 to offset elevated EU power bills, so that "self-funded" framing has at least one recent caveat.

Meanwhile, Intel's 14A node is being developed in Oregon; no Irish role in it has been announced, and two prospective 14A customers will decide the node's fate in commitments expected between late 2026 and early 2027. Ultimately, the €5 billion makes Leixlip the fully-loaded workhorse of a node Intel will eventually move past, not a contender for the leading edge. Whether Europe gets anything newer than Intel 3 remains to be seen.

The upgrade of the facility will involve installation of new tools presumably at Fab 34 as well as extensive infrastructure improvements designed to increase manufacturing efficiency. One of the key elements of the project is the expansion of the campus' automated material transport network, which will connect separate manufacturing modules into a single high-speed production system. Meanwhile, the modernization will not involve cleanroom expansion. Intel expects the upgrade to enable the Leixlip site to produce larger volumes of Intel 3-based products and make better use of the existing cleanroom capacity.

Intel opened its Fab 34 near Leixlip, Ireland, in 2023 and has been making various chips — including Core Ultra 100-series using Intel 4 and Xeon 6 using Intel 3 production node — using its process technologies that rely on EUV lithography at the site. At present, Intel's Fab 34 is Europe's only high-volume semiconductor production facility that uses EUV tools.

In mid-2024, Intel announced the €10.1 billion sale of a 49% stake in Fab 34 with Apollo Global Management as it badly needed money. This April, the company announced that it would repurchase the 49% stake in Fab 34 for $14.2 billion, which opened doors to the current expansion and investment. Intel claims that it kicked off execution of the project earlier this year, though it did not disclose when the upgrades will be completed.

"By investing in our existing fabs with state-of-the-art technology and installing cutting-edge tools, we are not just increasing output of critical products like Xeon 6 and next gen Intel Xeon processors built on Intel 3, we are ensuring that Ireland remains at the forefront of the world's most advanced manufacturing ecosystems, while strengthening the region’s role in the global technology landscape," said Naga Chandrasekaran, Executive Vice President, Chief Technology and Operations Officer and General Manager of Intel Foundry.

Among other things, Intel says that the investment will strengthen Europe's semiconductor supply chain and support the European Union's technology sovereignty objectives by increasing domestic production of leading-edge CPUs. There is a catch about that claim, though. All the silicon produced in Ireland is transported back to the U.S. for testing and assembly, as well as makes the end products, such as Core Ultra or Xeon 6, 'made in America.'

Both SKUs share the same layout of four Intel 18A P-cores, four low-power efficiency cores, a three-tile NPU also on 18A, and a four-core Xe GPU with 64 execution units built on Intel 3. The Low Power part runs its P-cores at 1.0 GHz, efficiency cores at 850 MHz, and the GPU between 800 MHz and 1.0 GHz. The Performance part clocks the P-cores to 3.1 GHz, efficiency cores to 2.1 GHz, and the GPU to 2.0 GHz. Both carry 12 PCIe Gen4 lanes, support LPDDR5 or DDR5, and are rated for a 10-plus year lifetime.

Intel builds the CPU and NPU on 18A and the GPU on the older Intel 3, the same node division it used for Clearwater Forest, the 288-core Xeon that stacks 18A compute tiles on Intel 3 base tiles. Smaller transistors hold less charge per stored bit, which makes leading-edge silicon more prone to radiation-induced bit flips, so committing 18A to orbit leans on RibbonFET and design-level hardening rather than a mature, inherently more tolerant node.

The market Starfire is targeting has run on BAE Systems' RAD750 for two decades. That radiation-hardened PowerPC part clocks 110 to 200 MHz, carries 10.4 million transistors, and is built on 150nm or 250nm lithography, per public specifications, and it flies on the Mars rovers, Kepler, and Fermi, among more than 150 spacecraft. BAE's multi-core RAD5545 and the Microchip-built processor NASA is developing to reach 100 times the throughput of current spaceflight chips are the more recent step up. Starfire's up to 75 TOPS and dedicated NPU put it in a different bracket, built for on-orbit AI inference rather than telemetry and control.

Intel lists the radiation data, covering total ionizing dose, single-event latch-up, and single-event effects, as characterization in process, so the part isn't radiation-qualified yet, and it notes the specs are subject to change. Intel Government Technologies is handling Starfire, with samples in Q3 2026 and a pitch of market-competitive pricing and domestic manufacturing. Intel Foundry is the only U.S.-based maker of leading-edge logic, holds Trusted Foundry status, and has tied its 18A and packaging roadmap to Pentagon programs including RAMP-C and SHIP, though 18A yields aren't expected to reach industry-standard levels until 2027.

Formally, Intel's codenamed Dunlow platform will succeed the company's Catlow platform with Xeon 6300P-series CPUs and will support Xeon E-class Nova Lake-S processors (presumably) with up to 28 cores that feature a dual-channel memory subsystem, come in an LGA1954 form-factor, and have a processor base power of 95W, according to shipments manifests at NBD data.

Intel's next-generation Core Ultra 400-series platforms for desktop computers, codenamed Nova Lake-S, allegedly feature up to 52 cores, which include up to 16 high-performance Coyote Cove cores and up to 32 energy-efficient Arctic Wolf cores in the compute tile, as well as four low-power Arctic Wolf cores presumably in the SoC tile. These Nova Lake-S CPUs are aimed at enthusiasts and reportedly pull up to 474W with a single purpose: to offer unbeatable performance and feature set to put Intel back on the map of enthusiast-grade platforms currently dominated by AMD.

By contrast, the Dunlow platform seems to be a completely different kind of animal. The CPU deliberately features 28 cores and up to 95W PBP (TDP). All Xeon processors except Xeon 6700E, Xeon 6+, and some Atom-based solutions for specialty applications released to date have only featured high-performance cores. Even Intel's Xeon 6300P-series 'Raptor Lake-E' based products feature up to 12 P-cores to offer higher sustained all-core frequencies. Therefore, unless Intel plans to offer energy-efficient cores in its next Xeon CPU aimed at entry-level servers and workstations, we may be dealing with a very special processor that features 28 P-cores that is designed to beat all desktop-grade platforms in demanding applications.

While, for now, 28 P-cores inside Nova Lake-S processors for the Dunlow platform is speculation, it should also be noted that 28 cores do not naturally derive from a 16P+32E desktop design and are impossible to derive from a notebook-grade 8P+16E design. Also, Intel typically does not create server/workstation products by fusing off nearly half a desktop die (it does not even matter whether it disables some P-cores and some E-cores, disabling 20 cores in a 48-core tile hardly makes a lot of sense).

A Nova Lake-S CPU for Dunlow featuring a compute tile with 28 P-cores would resemble the abandoned Raptor Lake-32C, which featured an all-P-core design aimed at workstations and entry servers before being canceled. It is also possible that this could be a derivative of a small Xeon die adapted to an LGA1954 packaging and dual-channel memory to reduce platform costs. At the end of the day, many server applications like storage or web hosting do not need extremely high memory bandwidth, so two DDR5 channels could be enough.

Another reason for Intel to release a Nova Lake-S CPU with up to 28 P-cores is to fill the gap between high-end enthusiast-grade desktops that feature up to 16 P-cores and expensive Xeon 6 server and workstation CPUs that may start at 16 cores, but feature an octa-channel memory subsystem that is costly and is an overkill for many applications. Also note that since Xeon 'Diamond Rapids' processors with an octa-channel memory subsystem have been canceled, the gap between desktop and high-end server CPUs just gets way too wide in 2028, making Nova Lake 28 P-core silicon a potentially viable option.

Intel's proposed design is a memory stack that addresses the assembly costs that make conventional HBM expensive by dropping the costly silicon interposer and shrinking the package, while building in its own defect repair.

The filing lays out a stack of memory dies, each holding one-transistor one-capacitor (1T1C) DRAM fabricated in the back-end-of-line, wired together with through-silicon via (TSV) "gutters" and both-sided high-bandwidth interconnect (HBI) connections. Intel describes dies of roughly 1.5 gigabytes (GB) apiece — 768 "datablocks" arranged in a 32-by-24 grid, grouped into eight channels of eight sub-channels each — stacked eight high and scaling to 16. Data then leaves the stack over UCIe I/O bundles running at 32 gigatransfers per second (GT/s), funneled out through a base die.

To understand what Intel is changing, it helps to recall what standard high-bandwidth memory does. HBM stacks DRAM dies vertically on a base logic die, threads them together with TSVs, and communicates with the processor across a silicon interposer using an extremely wide parallel interface — on the order of 1,024 bits per stack. This width is how HBM delivers its bandwidth, but it is also what makes it expensive to package and hard to scale, as every one of those wires has to be routed through an interposer sitting between the memory and the compute die. As AI accelerators have outrun the rate at which memory can feed them, this "memory wall" has become the dominant constraint on performance, which is why nearly every large chipmaker is now attacking the interface and the stack rather than the logic.

XBM's first major change is structural. Conventional DRAM cells are built in the front-end-of-line, the base silicon layer where transistors are normally fabricated. XBM instead moves the 1T1C cell into the back-end-of-line, the metal-and-via stack above the transistor layer, using thin-film transistors. Building memory in the BEOL is what lets Intel pack the die into many small, independently addressable memory blocks, and it is the same backend-transistor direction Intel has pursued for placing memory directly over logic.

The second change is the interface. Rather than HBM's wide parallel PHY, XBM serializes data onto UCIe bundles at 32 GT/s, with the base die handling the serialize/deserialize step and routing all I/O to the compute die. Moving to a standard chiplet interconnect is what makes the design "chiplet-native" and, Intel argues, simpler and cheaper to package than an interposer-bound HBM stack. The tradeoff is that 32 GT/s is UCIe's current top data rate, so the interface is already running at the spec ceiling rather than leaving obvious headroom.

Intel also leans heavily on repairability. The base die carries dedicated spare channels, built-in self-repair (BISR), decode and debug logic, and four sub-channels of redundant memory arrays that act as fungible spares for defects in the dies above — post-assembly repair designed to claw back yield on a very tall stack.

A large portion of the patent application focuses not on the memory cell at all but on how to mount it. Intel details memory-on-package (MoP) and "reversed overhang" structures aimed at cutting the stack's Z-height — conventional MoP can add 300 to 350 micrometers (µm) — while removing the stiffener normally needed to control warpage and feeding DRAM power directly from the voltage regulator. This is the concrete basis for the "smaller, cheaper package" claim.

XBM should not be confused with ZAM (Z-Angle Memory), the architecture Intel is co-developing with SoftBank subsidiary SAIMEMORY and set to present at the VLSI Symposium 2026. ZAM's innovation is on the bonding side — a fusion-bonded, nine-layer stack of largely conventional DRAM with roughly 3-µm-thin silicon between tiers — and it reportedly targets around twice HBM4's bandwidth density, with commercialization aimed at 2029. XBM, by contrast, is an Intel-only filing that changes the DRAM transistor itself and the interface. Read together, they suggest Intel is running at least two parallel HBM alternatives, a fitting move for a company that began in 1968 as a memory maker.

The caveats on Intel’s proposed HBM architecture are the usual ones for a patent. The patent was filed 18 months ago, and there’s currently no product or roadmap, signaling potential intent rather than a shipping part. The UCIe interface is already at its rate ceiling, backend-transistor DRAM remains unproven at manufacturing scale, and the whole thing still has to justify itself against HBM4E and Intel's own ZAM timeline.

Both accounts hold up at the wafer stage but omit the same downstream step: every Blackwell die that leaves TSMC's Arizona fab still crosses the Pacific to be packaged, no HBM is manufactured or packaged on U.S. soil, and the facilities intended to close those gaps won’t start production until 2028 at the earliest.

Lofty projects

Foxconn is building a Houston factory to produce GB300 tray modules for Nvidia, and Wistron will assemble and test Nvidia AI systems at a new facility in Fort Worth, Texas. Coherent broke ground in June on an expanded Sherman, Texas, plant that the company describes as the first volume-production 6-inch indium phosphide fab, supplying the lasers and optical components that link AI systems together.

Corning is adding more than 3,000 jobs across optical manufacturing sites in North Carolina and Texas. The post also cites an estimate from consultancy Public First that Nvidia-driven AI demand will contribute $485 billion to U.S. GDP in 2026 and support over 100,000 jobs. “AI is driving a once-in-a-generation opportunity to reinvigorate American manufacturing and supply chains,” said Nvidia’s Jensen Huang in the post.

Meanwhile, Intel's post lists R&D and manufacturing across Oregon, Arizona, New Mexico, and California, describes Ohio as “a planned site,” and devotes most of its length to workforce programs, K-12 AI education, and the company’s America250 partnership. Neither post addresses where the most advanced AI processors are actually assembled into finished chips.

The Pacific round-trip

Nvidia and TSMC produced the first Blackwell wafer at Fab 21 near Phoenix last October, and the site has since moved to volume output of Blackwell silicon on TSMC's 4NP node, the custom 4nm-class process built for Nvidia. On the other side of the Phoenix metro area, Intel's Fab 52 became fully operational in the same month as the first high-volume home of Intel 18A, and Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is capable of more than 10,000 18A wafer starts per week. Panther Lake reached broad availability in January, Clearwater Forest is due in the first half of this year, and 18A yields are expected to reach industry-standard levels in early 2027, which I covered in my examination of Intel's fab roadmap.

This ultimately means that leading-edge logic wafers are now being fabbed in the U.S. by two companies on two competing nodes. That’s a genuine change and, by any measure, a monolithic achievement when compared to the start of the decade, and neither company overstates that in their corporate blogs.

However, a Blackwell data center GPU pairs two reticle-sized compute dies with eight stacks of HBM3e on a silicon interposer using TSMC's CoWoS-L packaging, and all of TSMC's CoWoS capacity is located in Taiwan. TSMC’s U.S. facilities currently send 100% of their chips to Taiwan for packaging, including wafers fabbed in Phoenix. A Blackwell die fabbed in Arizona therefore travels roughly 7,000 miles to be diced, stacked, and mounted, then travels onward through system assembly before any of it returns to a U.S. data center.

As for HBM, every stack in production today comes out of SK hynix and Samsung facilities in South Korea or Micron's fabs in Taiwan and Japan, and the ABF substrates beneath the interposer are similarly concentrated in Japan and Taiwan. No U.S. facility currently manufactures or packages HBM. The one company running advanced packaging at scale on U.S. soil is Intel, whose Foveros operation in New Mexico handles its own 3D-stacked products and has started attracting outside interest; Google has reportedly booked Intel to package more than 3 million TPUs in 2028. Intel doesn’t currently appear anywhere in Nvidia's list of manufacturing partners.

Nothing before 2029

Amkor also broke ground on its Peoria, Arizona campus last October, a $7 billion, two-phase project with up to 750,000 square feet of cleanroom, roughly $400 million in CHIPS Act funding, and Apple and Nvidia signed as lead customers. Its first factory will be completed in mid-2027, with production beginning in early 2028. TSMC formalized the relationship on June 16th, signing a 10-year agreement under which it will procure packaging and test services from Amkor, while TSMC executives said in April that the foundry's own Arizona packaging facility will bring CoWoS and 3D-IC capacity online before 2029.

SK hynix began initial work in April on its $3.87 billion advanced packaging plant in West Lafayette, Indiana, targeting mass production of HBM4E and HBM5 in the second half of 2028, the same window Amkor’s aiming for. The timing means the entire Blackwell family, and likely the first Rubin generation, will complete their product lifecycles without a fully domestic manufacturing path. The first AI accelerators that can be fabbed, packaged, and fitted with U.S.-packaged memory without leaving the country will be HBM4E-era parts arriving around 2028 to 2029.

Unfortunately, the Section 48D advanced manufacturing tax credit, raised to 35% last July, doesn’t apply to projects whose construction begins after December 31st, 2026, which gives Coherent's June groundbreaking, SK hynix's April piling work, and Amkor's October start a shared fiscal deadline if they want to benefit from it.

As for Foxconn and Wistron’s Houston and Fort Worth plants, they’ll receive GPUs packaged in Taiwan and assemble them into trays, racks, and systems on U.S. soil. It’s that type of assembly work that’s carrying most of the $500 billion figure, which counts the value of AI infrastructure produced rather than capital spent on factories. Wafers are American, racks are American, but everything in between isn’t. Whether that changes on schedule is a question for 2028, and it depends highly on two packaging campuses in Arizona and one in Indiana meeting their deadlines.

"The recent pricing updates reflect current market dynamics, including rising supply chain costs and strong demand for our Intel Core Ultra 200S Plus processors," an Intel spokesperson told Tom's Hardware. "These updates are in line with recent price increases for other Intel product families based on similar factors."

This week it turned out that Intel had quietly increased recommended customer prices (RCPs) of its latest Core Ultra 200-series Plus processors for desktops — the Core Ultra 7 270K Plus and the Core Ultra 7 250K Plus — by $30 - $50, depending on the model. Both processors belong to the Arrow Lake family and, like the rest of them, are produced by TSMC. Yet, Intel's original 'non-Plus' Core Ultra 200-series processors did not increase their MSRP. The flagship Core Ultra 9 285K still carries a $599 RCP, just like it did at its launch in Q2 2024. Something similar applies to the least advanced Arrow Lake processor for desktops — the Core Ultra 5 225 — that has an RCP between $183 and $236, which is a bit lower than its launch RCP of $241.

If Intel did see supply-chain inflation, it would be reasonable to expect the company to adjust prices of the whole family. Instead, the company raised prices only on select products that apparently had become unexpectedly attractive to customers who can afford them and who have probably demonstrated willingness to buy them above recommended prices. This means that we are not dealing with a simple cost pass-through, but rather with a price hike associated with strong demand for specific SKUs.

When it comes to data center-oriented processors, we see rather massive price hikes. While higher-end Xeon 6 'Granite Rapids' CPUs cost less than they used to at launch in 2024, they are noticeably more expensive after Intel slashed their recommended prices in 2025, and they can be twofold higher when compared to retail prices from mid-2025. Perhaps the biggest surprise is that select Xeon 8000-series 'Emerald Rapids' processors now carry higher RCPs than they used to when they were released in late 2023.

All Intel Xeon processors are produced internally (so Intel cannot blame higher costs on TSMC), and while Intel gets raw materials from its partners, it is doubtful that overpriced photoresist can significantly affect RCPs of CPUs that sell for thousands of dollars. Meanwhile, Intel has been saying for several quarters now that demand for its Xeon processors exceeds supply. Therefore, it makes a lot of sense for Intel to finally capitalize on that and increase RCPs of popular models.

There is a caveat, though. Actual prices of data center hardware tend to differ from list prices as they depend on many factors, including volumes and strategic relations between suppliers and consumers. To that end, while it is evident that Intel has increased RCPs of its Xeon CPUs, it remains to be seen how this affects its average selling prices (ASPs) for the ongoing quarter and for the whole year.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

While the increase amounts to an additional $30–$50 (depending on the model), it is worth noting that these higher prices have already been reflected on Amazon. We have reached out to Intel to confirm the pricing changes and will update this article if and when the company responds.

The Core Ultra 270K Plus and the 250K Plus are part of Intel’s Arrow Lake Refresh lineup and were introduced with a relatively low price compared to their non-Plus predecessors. Intel claimed up to 15% improvement in gaming performance at 1080p compared to stock Arrow Lake chips thanks to several key improvements aimed at addressing the architectural bottlenecks of the original Arrow Lake processors.

The Core Ultra 7 270K Plus comes with 24 cores, including 8 P-cores and 16 E-cores, which is similar to the more expensive Core Ultra 9 285K. The Core Ultra 5 250K Plus comes with 18 cores across 6 P-cores and 12 E-cores, which is slightly below the 20 cores available on the Core Ultra 7 265K. Intel also increased the die-to-die interconnect frequency by 900 MHz to reduce latency and improve gaming performance.

The new chips also offer native support for faster DDR5-7200 memory, as opposed to 6400 MT/s on the non-Plus Arrow Lake chips. Then there’s Intel's new Binary Optimization Tool, a free software utility that analyzes executables and automatically recompiles them with CPU-specific optimizations. According to Intel, this alone is responsible for a significant portion of the gaming performance gains.

While the increase in price may hamper the value advantage that these chips initially offered, there is no doubt that they bring meaningful performance to the table. In our testing, we found the Core Ultra 7 270K Plus to deliver excellent productivity performance with a noticeable uplift in gaming over the original Arrow Lake chips. In fact, it is currently the best Intel CPU on the market. As for the Core Ultra 5 250K Plus, it offers one of the strongest value propositions at its price point. It also remains our top pick for the best budget CPU, thanks to its ability to compete with similarly priced gaming processors while excelling in heavily threaded workloads.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

Tesla poaches an Intel veteran

Gary Jiang joined Tesla in June 2026 after spending over 17 years at Intel, according to his LinkedIn profile. Interestingly, there is little to glean about his current role from his LinkedIn profile, aside from noting that he is a director at Tesla. His final position at Intel was as Factory Manager, where he oversaw the construction of the production facility, the installation of fabrication equipment, factory startup, product certification, preparation for high-volume manufacturing, and, ultimately, the transfer of Intel 18A technology from the development fab in Oregon to high-volume Fab 52 in Arizona.

Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies (which include Intel 10nm SuperFin and 10nm Enhanced SuperFin/ Intel 7) at Fab 32 and Fab 42.

Tesla has been looking for a Technical Program Manager (TPM) for semiconductor infrastructure, focused on end-to-end fab program delivery, since March, but without any success, as the job listing is still listed on the company's website. Therefore, Terafab — the joint initiative between Tesla, SpaceX, and xAI — still does not have a formal leader who is going to lead the whole project.

In his most recent role at Intel, Gary Jiang worked closely with supply chain, finance, and materials logistics for new factory planning for output, wafer cost, yield, and profit & loss, according to his LinkedIn profile. He also managed the billion-dollar capital equipment and startup of the fab. Hence, without any doubt, Jiang appears to have been one of the senior manufacturing leaders responsible for building and equipping Intel's new 18A-capable manufacturing facilities in Arizona (primarily Fab 52, and potentially Fab 62 as the campus expands). However, it would still be inaccurate to say he was the person responsible for building Fab 52 alone.

Jiang's skills roughly match what one would expect from a senior manufacturing executive helping commission a new leading-edge fab, so he will be instrumental in turning a newly constructed fab shell (or even cleanroom) into a production-ready semiconductor manufacturing facility.

However, he did not oversee the entire Fab 52/Fab 62 program and was not responsible for every stage of the project — from permitting and groundbreaking to construction, tool installation, and the ramp to high-volume manufacturing. Likewise, he is unlikely to lead the Terafab project as a whole. Nonetheless, given that Terafab is set to license Intel's 14A process technology, Gary Jiang is probably among the best candidates to equip a fab for an Intel manufacturing node.

One major caveat

In fact, one of the most confusing parts about Tesla's hiring people to work at Terafab is that Tesla itself will not own any high-volume semiconductor production facilities; SpaceX will, according to Elon Musk.

In the near term, Tesla plans to build a $3 billion semiconductor R&D center at its Texas campus. The facility will house a small pilot line capable of processing a few thousand wafers per month to develop and validate new manufacturing technologies before they are scaled for commercial production.

Once the pilot line shows signs of success, SpaceX is expected to construct a full-scale high-volume manufacturing fab. However, coordinating a joint project between Tesla and SpaceX will add complexity, as major decisions require approval from both companies' boards and must undergo conflict-of-interest reviews, which will likely slow execution.

That said, given that Gary Jiang was hired by Tesla, not SpaceX, his responsibilities could be to equip and ramp a development facility at its Gigafactory Texas campus rather than build, equip, and ramp a high-volume fab for SpaceX. In any case, we are speculating here, and nothing can really stop SpaceX from hiring Jiang at some point down the line.

In the image above, you can see Tarlin has inked some kind of official licensing deal with ASRock, Gigabyte, MSI, and Intel. There’s already been four series of networking equipment gachapon launched by Tarlin, for some context.

As far as we can see from the social media posting, the new Tarlin gachapon series includes three branded miniature motherboards: the ASRock Z890 Steel Legend WiFi, the Gigabyte Z890 Aorus Elite WiFi7 Plus, and the MSI MEG Z890 Ace. Premium stuff. Intel’s Core Ultra 7 270K Plus seems to be the only CPU choice. There are also case fans, a PSU, and a tower case for your minuscule components PC build.

Tarlin’s eccentric gachapon pedigree

Compared with gachapon rivals like Bandai and Takara Tomy, Tarlin has carved a niche, eccentric furrow in the industry. It has a reputation for turning everyday, mundane, or highly technical objects into accurate scale miniatures.

Examples of other incredibly niche Tarlin-produced capsules include its Temporary Toilet Series, a realistic Articulated Crayfish, and its series of Cisco rackmount network gear toys. In this context, it's “serious spec” PC component capsule toys, which are made to such exacting precision that they can be assembled to make tiny tower PCs, aren’t so unusual.

In 2024, we spotted a Japanese capsule toy machine filled with Intel CPUs. One gacha chancer acquired an Intel Core i7-8700 CPU after inserting 500 Yen (around $3.25) and twisting the customary knob.

PL2, or Power Limit 2, represents the maximum power a CPU can draw during short boost periods. That said, a PL2 target of 474W remains quite demanding, although a previous rumor suggests Intel may also have a PL4 emergency power limit over 700W. It is important to note that these power limits may only apply to the top-end models with the dual-tile architecture.

Additionally, the leak also sheds light on the upcoming platform, including the previously rumored LGA1954 socket. We already know that Nova Lake-S will require a new generation of motherboards. Motherboard vendors are expected to classify their boards by sustained PL1 power levels, with configurations for 35W, 65W, 125W, and 175W CPUs. Enthusiast-grade motherboards, likely the Z990 series, are also rumored to feature three EPS 8-pin CPU power connectors instead of the traditional two. While vendors will have the option to include a third connector, its primary purpose would be to support extreme overclocking and would not affect the CPU's rated performance profile.

The upcoming Nova Lake-S lineup is expected to carry the ‘Core Ultra 400S’ moniker and will be Intel's biggest desktop CPU overhaul in years. We’ve previously reported leaked specifications indicating configurations ranging from 6 to 52 cores, with support for DDR5-8000 memory. The flagship 52-core model is expected to feature 16 performance cores, 32 efficiency cores, and a new Big Last Level Cache (bLLC) design to take on AMD's 3D V-Cache gaming dominance. The company is also rumored to introduce integrated Xe3 graphics, Thunderbolt 5, PCIe 5.0 connectivity, and an upgraded NPU for AI workloads.

While these specifications are unconfirmed, it is clear that Intel is targeting substantial gains in gaming, multi-threaded performance, and overall platform capabilities with its next-gen processors.

Solidigm originates from Intel's Non-Volatile Memory Solutions Group (NSG), the company's NAND and SSD business unit, which used to have a unique technology strategy that differed from that of other flash and drive producers. To that end, it is not surprising that Solidigm also has a unique positioning as it only offers data center drives, most of which are based on floating-gate memory and proprietary in-house designed controllers. Furthermore, Solidigm is a fully vertically integrated company.

At Computex 2026, we sat down with Avi Shetty, who is vice president of AI ecosystem, Solutions & Market Enablement at Solidigm. Before his current position at Solidigm, he spent 14.5 years at Intel's storage division, so he has deep knowledge both about technology and the market. During our conversation, we discussed how Solidigm keeps evolving, including floating-gate NAND memory, advanced packaging technologies, next-generation SSDs, liquid-cooled SSDs, and more.

Anton Shilov: Could you introduce yourself to our readers and describe what do you do at Solidigm?

Avi Shetty: My name is Avi Shetty. I work at Solidigm, where I help lead AI solutions and ecosystem initiatives. My team works with global platform providers, software ISVs, and ODMs to ensure Solidigm solutions are validated, benchmarked, and included in reference designs at both the device and cluster levels, enabling customers to fully utilize our products.

A part of SK hynix that acts independently

Anton Shilov: You were previously a part of Intel. How is the integration going? Are you now fully integrated part of SK hynix, or do you operate independently?

Avi Shetty: Let me provide some background. While Solidigm was established in December 2021, our history goes back decades. Many of us came from Intel's Non-Volatile Memory Solutions Group (NSG), which developed Intel’s NAND SSDs for both client and data center markets.

In 2021, SK hynix acquired Intel’s NAND and SSD business and established Solidigm. Since December 2021, we have operated as a wholly owned U.S. subsidiary of SK hynix, headquartered in Rancho Cordova, California.

Anton Shilov: So, you are part of SK hynix, but still maintain a degree of independence?

Avi Shetty: Absolutely. We operate as an independent subsidiary of SK hynix. Our strategy is focused entirely on enterprise SSDs. Every bit of [floating gate] NAND [at our fab in Dalian, China] we produce goes into enterprise storage solutions.

This is one of the ways we differentiate ourselves from competitors such as Samsung and Micron, which also serve mobile and client markets. We made a deliberate decision to focus exclusively on enterprise storage and AI.

We are also fully vertically integrated. We manufacture our own NAND, develop our own controllers, write our own firmware, and design our own SSDs. While we work with manufacturing partners to build products, we control the entire technology stack.

I also believe we are the only company with access to two different NAND architectures. Through SK hynix we have access to charge trap flash (CTF) technology, and we continue to develop floating gate NAND technology for our high-density QLC SSD products.

Anton Shilov: What is Solidigm's current share of the enterprise SSD market?

Avi Shetty: Approximately 24%. That is enterprise SSDs only. We do not participate in any other NAND markets. As of the first quarter of 2025, plus or minus a few percentage points, our measured enterprise SSD market share is approximately 24%. We evaluate market-share data quarterly and semiannually, and that is the latest figure we’ve publicly discussed.

Anton Shilov: How much of your business today is concentrated in high-capacity SSDs versus higher-performance products?

Avi Shetty: High-density SSDs now represent a significant portion of our business. Because Solidigm is privately held, we do not publicly disclose that breakdown. We report our financial metrics through our parent company, SK hynix.

What I can tell you is that both our 61TB-class and 122TB-class products became customer favorites almost immediately after launch. Demand for high-density storage has been extremely strong.

Anton Shilov: I assume you also work directly with hyperscalers?

Avi Shetty: We work with a broad range of customers globally. That includes U.S. cloud service providers, Chinese cloud service providers, OEMs around the world, NeoCloud providers, software ISVs, and channel partners. We maintain customer support, engineering, and sales organizations globally. Our business spans the Americas, EMEA, China, and the rest of Asia-Pacific.

Anton Shilov: Which customer segment represents the largest opportunity for growth right now? Traditional cloud providers or something else?

Avi Shetty: We intentionally maintain a diversified customer base.

What is interesting is how quickly new segments emerge. For example, the NeoCloud market has existed for some time, but AI-focused infrastructure providers such as CoreWeave, Lambda, Crusoe, and Nebius have become much more important over the last two years.

Before the AI boom, these companies represented only a small portion of demand. Today, they are becoming a meaningful part of the market.

As AI infrastructure continues to expand, Solidigm is adapting both its customer strategy and product portfolio to support these emerging deployments while continuing to serve our traditional customers.

Floating gate NAND in 2026

CTF NAND used by major memory makers has approached 276 - 286 active layers, whereas Solidigm's floating gate flash is still at 192 layers, meaning that the company is somewhat behind some of its rivals in terms of active layers as of mid-2026. It is set to catch up with its next generation that will have over 200 layers, but only in the second half of this year. However, floating gate NAND memory still has a number of advantages over CTF, particularly for applications that Solidigm targets.

Floating gate uses a conductive polysilicon island to store charge, which provides excellent cell isolation — charge stays well-contained and is less likely to spread to or interfere with neighboring cells — and this is particularly important for 3D QLC NAND with very high layer counts. In addition, Solidigm claims that floating gate gives a strong voltage threshold window and better cell isolation, which enables the company to keep scaling QLC more while maintaining good reliability.

Anton Shilov: Are you still producing floating gate NAND, and do you intend to continue?

Avi Shetty: Absolutely. We introduced our first QLC foating gate NAND product in 2018, and today we are on our fourth generation of QLC NAND.

Our flagship high-capacity product currently ships with 192-layer floating gate NAND technology and powers our 122TB SSD.

Anton Shilov: Haven't you also announced a larger drive?

Avi Shetty: We have announced a higher-capacity product and expect it to become available later this year.

Anton Shilov: The 256TB-class drive?

Avi Shetty: Correct. Approximately 245TB usable capacity.

Anton Shilov: So you are going to have a roughly 245TB SSD available this year?

Avi Shetty: Correct.

Anton Shilov: What advantages does Floating-Gate NAND provide?

Avi Shetty: Floating gate NAND gives us scalability. We have consistently been first in the industry to push storage density in standard form factors. We were the first to introduce a 30TB SSD, then a 60TB SSD, and later a 122TB SSD.

We have been shipping the 122TB drive for nearly five quarters. We launched it in the fourth quarter of 2024, and it has since become our flagship product. It is probably our most popular product of 2025.

The reason customers like the 122TB drive is efficiency. When you look at AI data centers, customers want low power consumption, scalability, and performance. While this particular product is a PCIe Gen4 solution, our roadmap continues to increase both density and bandwidth. You will see future products based on PCIe Gen5 and PCIe Gen6.

The real attraction of the 122TB SSD is scale. In a 1U server, you can install 24 of these drives and get nearly 3PB of storage in a single rack unit.

If you look at the AI data pipeline — from training to archiving — the first and last stages require massive datasets. That is where these high-capacity SSDs are being deployed today.

Now we are also seeing growing demand from inference deployments. Inference can run in core data centers or in edge and back-office environments. Those deployments require storage that can efficiently feed GPUs and support workloads such as context storage and KV cache management. High-density SSDs help provide the capacity required for those applications.

Next-generation SSDs: PCIe Gen6 drives with liquid cooling

Anton Shilov: You mentioned PCIe Gen5 and Gen6 [next-generation drives]. I assume you are referring both to next PCIe generations and future NAND generations?

Avi Shetty: Both.

We maintain separate technology and product roadmaps. Earlier, I mentioned that our current QLC NAND is our 4^th Generation technology based on 192 layers. We will continue investing in future NAND generations as well.

On the product side, we are talking about PCIe generations. We currently ship both PCIe Gen4 and PCIe Gen5 SSDs. All of our TLC products are PCIe Gen5 today, while our QLC lineup currently remains PCIe Gen4.

Future QLC products will move to PCIe Gen5, and eventually, we will introduce PCIe Gen6 SSDs as platform vendors such as AMD, Intel, and Nvidia adopt PCIe Gen6 in their systems.

Anton Shilov: You mentioned PCIe Gen6 SSDs. You have not shipped one yet, correct?

Avi Shetty: Correct. PCIe Gen6 products are part of our future roadmap.

Anton Shilov: How close are they?

Avi Shetty: We are not making product announcements at Computex, but you will hear more from us soon.

Anton Shilov: At the moment there is really only one platform that can take advantage of them anyway. Well, two, if you consider Nvidia Vera.

Avi Shetty: That is part of the equation. When we evaluate our roadmap, we consider demand, platform readiness, and overall value to customers.

For example, we have what we call a refresh philosophy. We may introduce a PCIe Gen4 refresh or a PCIe Gen5 refresh that lowers cost or improves efficiency rather than immediately moving to a new PCIe generation.

The question is whether customers gain more value from Gen6 today or from a more mature, lower-cost Gen5 product. Those are the kinds of decisions our planning teams evaluate.

What I can say is that Solidigm maintains a full roadmap covering PCIe Gen4, Gen5, and future Gen6 SSDs across all major form factors, including U.2, E1.S, E3.S, and other EDSFF variants. Our portfolio spans capacities from 2TB all the way to 122TB.

Anton Shilov: Launching an all-new product early still gives you time to validate products with platform vendors.

Avi Shetty: Absolutely. We already work closely with platform providers to validate prototypes long before products are launched. Our engineering teams participate in interoperability events and PCI-SIG workshops to ensure products are ready when platforms become available.

Anton Shilov: That is actually interesting because PCIe Gen6 interoperability workshops have been delayed multiple times. Back in 2024, people expected the ecosystem to move much faster and interoperability workshops to start in 2024, with the list of compatible products emerging in 2025.

Avi Shetty: That is true. A lot depends on platform readiness and ecosystem scaling. PCIe Gen6 by itself is not enough. This is my personal opinion, but to fully benefit from Gen6 storage performance, the industry must also address cooling. That is one reason we invested heavily in liquid-cooled storage.

Last year, we introduced what we believe was the world's first liquid-cooled storage solution for Nvidia environments. It used E1.S PCIe Gen5 SSDs with direct liquid cooling. Historically, liquid cooling was focused on CPUs and GPUs. We extended it to storage by allowing coolant to flow through a cold plate attached to the SSD. The cold plate removes heat directly from the drive. To fully exploit PCIe Gen6 performance, the ecosystem must develop those kinds of technologies as well.

Anton Shilov: So you believe PCIe Gen6 SSDs will require liquid cooling?

Avi Shetty: At least in high-performance AI environments, particularly Nvidia-based deployments, we believe liquid cooling will be necessary.

Next-generation SSDs: PLC NAND

Anton Shilov: Will future NAND generations include both TLC and QLC? And what about PLC?

Avi Shetty: Never say never. We demonstrated PLC technology using floating gate NAND at the Flash Memory Summit several years ago. However, this business requires factory optimization and maintaining a manageable number of SKUs to maximize utilization and profitability.

That said, there absolutely will be opportunities for PLC. We have not announced any specific products or timelines, but there is active PLC development underway inside Solidigm.

Anton Shilov: That is interesting. However, PLC by itself only increases capacity by about 20% compared to QLC and at the same time requires significantly more sophisticated controllers and error correction.

Avi Shetty: That is true. However, those same concerns existed during every previous transition: from SLC to MLC, MLC to TLC, and TLC to QLC.

We were the first company to commercialize QLC NAND. Initially, many competitors questioned its value. Today, the industry increasingly recognizes the total-cost-of-ownership advantages that QLC provides, and multiple vendors now offer QLC products. I think the same process will occur with PLC.

It is also important to consider the broader market. Roughly 80% of storage capacity worldwide is still deployed on hard drives. PLC does not necessarily need to replace QLC on a one-to-one basis. Instead, it can create new opportunities where the advantages of solid-state storage — lower power consumption, higher density, smaller physical footprint, and lower total cost of ownership — become compelling.

You will likely see future solution development involving software partners that help address some of the limitations you are describing.

Anton Shilov: Do you expect retention characteristics to become a major challenge with PLC NAND?

Avi Shetty: Of course. PLC is a new technology, and retention characteristics will differ from what we see with QLC today.

The same is true across all NAND types. SLC, MLC, TLC, QLC, and eventually PLC all have different retention characteristics based on the underlying technology. The existence of those challenges does not mean we stop exploring future solutions. We will continue investing in that area.

Advanced packaging for NAND

Anton Shilov: As I mentioned, PLC only increases capacity by about 20%. Advanced packaging may ultimately have a much larger impact on SSD capacity. Could you discuss where packaging technology stands today and where it is headed?

Avi Shetty: Absolutely. Let me use our current products as an example. The 122TB SSD represents a significant packaging achievement. It is a U.2 drive with 48 NAND packages. Each package contains a 22-die stack. Each die is a 1.33Tb QLC device. Those 22-die stacks are what enable us to reach 122TB in a standard form factor.

Packaging technology remains one of our core investments. We continue developing technologies that allow us to place more dies into each package and deliver higher capacities to customers.

Anton Shilov: What about increasing the number of dies per package?

Avi Shetty: That is one of the primary ways to increase density. You can either increase die capacity or increase the number of dies per package. We intend to pursue both approaches.

Anton Shilov: How many dies per package do you think remain practical?

Avi Shetty: Today we are at 22. Future products will go beyond that, although I cannot discuss specific numbers.

Anton Shilov: What did previous generations use?

Avi Shetty: Depending on capacity requirements, previous products used 4-, 8-, or 16-die stacks. Of course, we are talking about a single NAND package in each case.

Storage-Class Memory, Optane, and Nvidia's Storage Next

Anton Shilov: What about storage-class memory?

Avi Shetty: Like Optane?

Anton Shilov: Not necessarily Optane itself, but something similar — something faster than NAND flash, yet capable of offering significantly higher density than DRAM at a lower cost.

Avi Shetty: Understood. Let me frame it from the perspective of the problem we are trying to solve. If you are asking whether Solidigm is developing a storage-class memory technology similar to Optane, then the answer today is no.

What we are focused on is addressing the requirements emerging from Nvidia's Storage Next initiative. The fundamental challenge is bandwidth. HBM is extremely fast, but it is also expensive and difficult to scale economically. As AI systems continue to grow, the industry needs additional memory and storage tiers that provide greater capacity at lower cost. That creates demand for NAND-based solutions that remain non-volatile while delivering improved latency and bandwidth characteristics.

We have not made any public announcements regarding storage-class memory technologies, but we continuously evaluate future technologies and architectural approaches.

Anton Shilov: So you are exploring concepts that could potentially bridge the gap between traditional NAND and memory?

Avi Shetty: We are evaluating a wide range of technologies that could help us continue delivering leadership products to our customers. When and if we have something to announce, we will do so publicly. At this point, however, we have nothing to disclose.

Anton Shilov: So storage-class memory is not currently a product category that Solidigm is actively pursuing?

Avi Shetty: If you are specifically referring to something similar to Optane, then no.

Optane was based on a fundamentally different technology. It was not NAND. It relied on a phase-change-memory-derived architecture and represented a completely different storage medium. We are not pursuing that type of technology today. What we are investing in is future NAND technology.

Anton Shilov: You think that future NAND technologies could eventually move closer to that space?

Avi Shetty: Exactly. Future NAND innovations could help narrow the gap between HBM, DRAM, and the next storage tier. That’s certainly one of the directions the industry is evaluating as AI systems continue to demand larger memory pools and greater bandwidth.

Today's competition is Intel’s Core i7-14700K, based on the Raptor Lake Refresh architecture. At the time the Ryzen 7 5800X3D released, Intel’s 12th-gen Alder Lake CPUs were its main competition. Here, we revisit the comparison with Intel’s newer Core i7-14700K, which is available around the same price of $350.

The focus of this faceoff is to determine which CPU is the superior all-around chip. We will put the two CPUs through a series of tests spanning different categories to ultimately determine which CPU you should buy for your system.

This faceoff breaks down how two CPUs compare to each other in a head-to-head battle. If you'd like to read more about either processor, as well as see our full suite of tests, make sure to read our AMD Ryzen 7 5800X3D re-review and Core i7-14700K faceoff.

Features and Specifications: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

The Ryzen 7 5800X3D was first launched in April 2022 as a part of the Vermeer desktop CPU family. It is based on the Zen 3 architecture and built on TSMC’s 7nm production process. The CPU features 8 cores and 16 threads, with a TDP of 105W and a PPT of 142W. It has a base clock of 3.4 GHz and can boost up to 4.5 GHz.

The 5800X3D only supports DDR4 memory at a rated speed of 3200 MT/s over a dual-channel interface. It is compatible with the AM4 socket, with support for 300-series, 400-series, and 500-series AMD chipsets (though check support with your specific motherboard). It also supports 20 lanes of PCIe Gen 4. However, the 5800X3D does not have integrated graphics.

On a more positive note, the Ryzen 7 5800X3D was the first CPU to employ the new 3D V-Cache technology. As a result of stacking the cache vertically on the die, the 5800X3D has a total L3 cache of 96 MB. Of this pool, 64 MB is part of the 3D V-Cache stack. Core overclocking is disabled on the Ryzen 7 5800X3D due to its 3D V-Cache layout; DRAM overclocking still remains available.

Its competitor, Intel’s Core i7-14700K, uses a vastly different layout. It features the Raptor Lake Refresh architecture, which is a refined version of the 13th-generation Raptor Lake base architecture. The Core i7-14700K was launched in October 2023 and was built on a 10nm production process (Intel 7).

Intel’s 14th-generation CPUs use a hybrid core layout with performance-focused “P-cores” and more efficient “E-cores.” The 14700K also follows this structure, featuring 8 P-cores and 12 E-cores, for a total of 20 cores. In the 14700K, Hyper-Threading is only available on the P-cores, so the CPU has a total of 28 threads. The chip can boost the P-cores up to 5.6 GHz, while the E-core boost clock is 4.3 GHz.

Interestingly, the Core i7-14700K supports both DDR4 and DDR5 memory at 3200 MT/s and 5600 MT/s, respectively. The CPU is compatible with the LGA 1700 socket featured in the 600-series and 700-series Intel motherboards. There is also support for 16 PCIe Gen 5 lanes and 4 PCIe Gen 4 lanes.

The Core i7-14700K has a TDP of 125W, with a higher PL2 limit of 253W. Integrated graphics are also offered in the 14700K in the form of UHD Graphics 770. There is 33MB of shared L3 cache on the chip. Perhaps more importantly, the Core i7-14700K is fully unlocked for overclocking, which is a big advantage over its competitor for today, though that requires a Z-series motherboard.

Zooming out a bit, it is clear that the Core i7-14700K is vastly superior to the Ryzen 7 5800X3D on paper. It is a newer CPU, so it has a better feature set, including PCIe Gen 5 and DDR5 support. It offers more cores, a higher boost clock, integrated graphics, and an unlocked multiplier for overclocking.

⭐Winner: Intel Core i7-14700K

Nothing is decided on paper alone, but the Core i7-14700K offers much better specs, newer features, and even has overclocking support. It takes this round quite easily.

Gaming Benchmarks and Performance: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

AMD claims to have “re-engineered” the Ryzen 7 5800X3D for its 2026 re-release, so we have tested it again, along with a whole bunch of worthy competitors, including the 14700K. We chose the 1080p resolution for our 16-game test suite in order to maximize the performance differences between the various CPUs. The graphics card used was the GeForce RTX 5090 to keep potential GPU bottlenecks to a minimum. Let’s get into the results.

Starting off with our 16-game FPS geomean at 1080p, the Core i7-14700K dominates the Ryzen 7 5800X3D with an average result of 166.7 FPS across our tested games, compared to the 145.6 FPS result of the Ryzen 7 5800X3D. That is a 14.5% difference in favor of the 14700K in our performance geomean. In 1% lows, the 14700K leads the Ryzen 7 5800X3D by 20% on average, putting out 114 FPS against the Ryzen’s 95.

However, there is another side to this benchmark table. The Core i7-14700K supports both DDR4 and DDR5 memory, so we tested it in both configurations. With DDR4-3200 memory, the 14700K’s advantage vanishes, and instead the Ryzen 7 5800X3D leads by 1.04%, or just 1.5 FPS. The 1% lows are in favor of 14700K by only 3 FPS (3.15%), which is astonishingly close.

When the Intel CPU is paired with DDR5 memory, the Ryzen 7 5800X3D’s cache advantage seems to be struggling against the Core i7-14700K’s raw core count and higher boost clock (along with far faster memory speeds). Looking at individual titles, we see a similar pattern with the Core i7-14700K holding a consistent lead over the 5800X3D.

In 007 First Light, the 14700K paired with DDR5 memory has a 25.7% lead on average over the 5800X3D. That lead shrinks to 21.5% in Crimson Desert, and the difference is 13.7% in favor of the 14700K in Cyberpunk 2077. Interestingly, the Core i7-14700K leads the entire pack in Flight Simulator 24, establishing a 26.6% lead over the 5800X3D in this title. The DDR5-equipped 14700K also leads the 5800X3D in Spider-Man 2, Starfield, The Last of Us Part One, Baldur’s Gate 3, and Counter-Strike 2.

However, when the Core i7-14700K is paired with DDR4-3200 memory, the picture changes completely. The Ryzen 7 5800X3D leads the i7-14700K with DDR4 memory in Baldur’s Gate 3 by 11.7%. In Crimson Desert, the lead is 3.2% for the 5800X3D, and 2.6% in Cyberpunk 2077. The Ryzen 7 5800X3D sits between the DDR5 and DDR4 versions of the 14700K in a few other titles, including Counter-Strike 2 and DOOM: The Dark Ages.

There are also some titles in which the Ryzen 7 5800X3D leads both the DDR4 and DDR5-equipped versions of the Core i7-14700K. In F1 2024, the Ryzen 7 5800X3D leads the DDR5 14700K by 5.6%, and the DDR4 14700K by 13.7% on average. The same pattern can be seen in Final Fantasy XIV, with a 6.6% lead over the 14700K using DDR5 memory, and in Minecraft RT, with a 18.5% lead over the 14700K using DDR4 memory.

It is certainly all over the place when you put both configurations of the 14700K into the mix, but the two behave more like separate CPUs. The long and short of it is that the 14700K with DDR5 memory provides the best gaming performance on average, followed by the Ryzen 7 5800X3D. The DDR4-equipped 14700K is ever-so-slightly slower than the 5800X3D, but it really just depends on the game you’re playing.

During our testing, the Core i7-14700K averaged 4.93 GHz with DDR5 memory and 4.88 GHz with DDR4 memory. The Ryzen 7 5800X3D could only manage 4.34 GHz, but it sipped only 77.5 watts during our gaming tests. The 14700K DDR5 averaged 132.4 watts, while the DDR4-equipped 14700K averaged a whopping 155.1 watts during gaming. This is why the 14700K with DDR4 reached an average temperature of 80 °C, compared to 62 °C for the 14700K with DDR5 and 59 °C for the 5800X3D.

In addition to running the coolest, the Ryzen 7 5800X3D is also the most efficient CPU of the bunch. The 5800X3D had an FPS-per-watt output of 1.88, compared to 1.26 for the Core i7-14700K with DDR5 memory, and just 0.93 for the DDR4 version. It is amazing how much the Core i7-14700K suffers when paired with DDR4 memory.

Lower overall performance also hurts the value proposition of the DDR4-equipped 14700K, as it puts out just 0.39 FPS-per-dollar, compared to the 0.45 of the DDR5-equipped 14700K. Astonishingly, the Ryzen 7 5800X3D falls between the two 14700K versions, delivering 0.42 FPS per dollar. This makes the Core i7-14700K the value king, but only if you pair it with DDR5 memory. I suspect that will be tricky in the current market.

⭐Winner: Tie

While the Ryzen 7 5800X3D does slightly pull away from the DDR4-equipped 14700K, both of these setups get demolished by the 14700K when it is paired with DDR5 memory. We're calling this round a tie considering the massive price disparity between DDR4 and DDR5 memory right now.

Productivity Benchmarks and Performance: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

Productivity performance spans single-threaded and multi-threaded workloads, so we tested the CPUs across a range of benchmarks covering both categories. Just like in our gaming tests, we tested the 14700K with both DDR5 and DDR4 memory, since it does impact the performance significantly.

Intel’s hybrid architecture has historically been quite strong at multi-threaded workloads due to E-cores, and that pattern appears here too. In our multi-threaded performance ranking geomean, the Core i7-14700K scores 492 points, a massive lead of 116.7% over the Ryzen 7 5800X3D that could only manage 227 points on average. Even when the Core i7-14700K is paired with DDR4 memory, it has a 105% higher average score than the Ryzen 7 5800X3D.

The superior core count of the 14700K is proving to be the difference maker in this category. In the Cinebench 2024 multi-core test, the 14700K with DDR5 memory is a whopping 126.6% faster than the Ryzen 7 5800X3D. Even the DDR4-equipped 14700K secures a 107% lead over the 5800X3D in Cinebench. The lead for the 14700K is about 137% in POV-Ray, and it shrinks to 135% when using DDR4 memory.

Blender tests were also favorable for the 14700K, but we didn’t see a big difference between DDR4 and DDR5 systems in these benchmarks. In Junkshop, the DDR5-equipped 14700K leads the 5800X3D by 116.4%; in Monster, by 116.6%; and in Classroom, by 118.3%. The DDR4 variant follows closely behind, by 1 or 2 percentage points.

The memory generation again comes into play when we look at HandBrake x265 10-bit encoding, with the DDR5-14700K leading the 5800X3D by 90.5%, while the DDR4-14700K manages a 82% lead. The gap is even larger in x264 encoding, with the DDR5 variant gaining a 105% lead over the 5800X3D, while the DDR4 variant can only manage a 63% lead.

That still makes the Core i7-14700K far better than the 5800X3D in productivity workloads, regardless of the memory generation. However, we still have single-threaded results to look at. Our single-threaded performance ranking geomean puts the Core i7-14700K 36.6% faster on average than the Ryzen 7 5800X3D. Interestingly, there is no difference in single-threaded performance between the DDR5 and DDR4 variants of the 14700K.

The same trend is seen in individual benchmarks as well. The 14700K is about 25% faster than the 5800X3D in Lame’s audio encoding test, and the DDR4 variant is in the same ballpark as well. Curiously, the DDR4-equipped 14700K is slightly faster than the DDR5-14700K in Cinebench 2024 and also outperforms the 5800X3D by 36.6%. Safe to say, the RAM difference doesn’t really come into play in these tests.

Overall, though, the winner is quite clear. The Ryzen 7 5800X3D is a gaming-oriented chip with only 8 cores and 16 threads, so it is no match for the 20-core 14700K in productivity workloads. Whether you go for DDR4 or DDR5 is your decision, but the productivity champion of this faceoff is the Core i7-14700K.

⭐Winner: Intel Core i7-14700K

With an average lead of 116% over the Ryzen 7 5800X3D in multi-threaded tasks, the Core i7-14700K sweeps the productivity round quite easily.

Overclocking: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

Overclocking has never been a strong suit of AMD Ryzen processors; however, the Ryzen 7 5800X3D doesn’t support core overclocking at all. AMD cited the 3D V-Cache technology as the reason the 5800X3D can’t be overclocked, and they were right to assume so.

Due to the vertically-stacked cache, heat transfer from the CPU die to the heatspreader was a real issue. An overclocked 5800X3D would have sipped more power and produced more heat. Therefore, an efficient heat-transfer system was needed but could not be developed in time for the first-generation V-Cache product.

AMD has since reinstated overclocking support for Ryzen 9000 series X3D CPUs by flipping the cache layout, so it no longer hinders heat transfer. However, the Ryzen 7 5800X3D’s core multiplier still remains locked, but you can still tune the DRAM and Infinity Fabric clocks.

The Core i7-14700K, on the other hand, is tailor-made for overclocking. Being a K-series SKU, the 14700K comes with an unlocked multiplier and all the Intel bells and whistles for overclocking. It can reach 6.1 - 6.2 GHz on individual cores with proper cooling, and users can expect a 5.6 - 5.8 GHz all-core overclock on most setups.

Its overclocking toolkit features traditional multiplier adjustments, voltage controls, and established BIOS interfaces that most enthusiasts are already familiar with. The Core i7-14700K also has a significant amount of power headroom to play with, although temperatures become a concern as soon as the power consumption ramps up.

By all overclocking metrics, the Core i7-14700K is the superior CPU for tinkerers. The Ryzen 7 5800X3D can’t be manually tuned, at least not in the traditional sense, and therefore doesn’t really stand a chance in this round.

⭐Winner: Intel Core i7-14700K

The 14700K is the real deal when it comes to overclocking support. The Ryzen 7 5800X3D is locked and therefore can’t be overclocked, so Intel sweeps this round.

Power Consumption and Efficiency: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

The Ryzen 7 5800X3D has a base TDP of 105W and a PPT of 142W. Intel’s is much higher, with the 14700K clocking in at 125W TDP and a PL2 limit of 253 watts. However, TDP numbers don’t give us a good idea of real-world power consumption, so we ran our own detailed tests.

First, at idle, the 5800X3D consumed only 5 watts, while the 14700K consumed 27 watts. In an active-idle situation, such as YouTube playback, the Core i7-14700K consumed 28 watts with DDR5 memory and a concerning 39 watts with DDR4 memory. The 5800X3D, on the other hand, sipped only 9 watts, making it anywhere from 67% - 76% more efficient than the 14700K.

Moving on to all-core workloads, in our y-cruncher multi-threaded AVX power test, the Ryzen 7 5800X3D consumes 119 watts, while the Core i7-14700K clocks in at a staggering 335 watts, a 181.5% higher figure. Even the Core i7-14700K with DDR4 memory consumed 307 watts, which is still a 158% increase over the 5800X3D’s power consumption.

In Linpack, the Ryzen 7 5800X3D is again more reserved, with the 14700K consuming 168.6% more power than the Ryzen. The DDR4 setup was not much better, with a 137.2% higher power consumption than the 5800X3D in this test. The gap widens even more in Cinebench 2024’s multi-core render and our Blender tests, which show the 14700K consuming anywhere from 250% to 285% higher power than the 5800X3D.

In our encoding tests, the situation remains pretty much the same. In Handbrake x264, the DDR5-14700K consumed 242% more power than the 5800X3D, while the DDR4-14700K consumed nearly 200% more. Similar numbers were seen in Handbrake x265 and SVT_AV1 encoding, with the 5800X3D being the clear winner.

We even looked at single-threaded workloads to determine the power consumption of those tasks. In y-cruncher’s single-threaded AVX power test, we saw the 14700K consume 157% more power when paired with DDR5 memory, and 132% more when using DDR4 memory. Safe to say, the Intel CPU does not fare any better in these workloads either.

To determine the efficiency, we calculated the watts-per-FPS number in Handbrake x265. The 5800X3D was 43.4% more efficient than the 14700K with DDR5 RAM, and about 41% more efficient in this task than the 14700K with DDR4 memory. The pattern can again be seen in Cinebench 2024’s efficiency test, where we look at points-per-watt. The 5700X3D is anywhere from 62% to 68% more efficient than the 14700K in this task.

We can also visualize the efficiency differences using our handy scatter plots. In the Linkpack power efficiency plot, the 5800X3D is towards the bottom left of the chart, while the 14700K is more towards the top. This means that the 14700K uses substantially more energy to deliver marginally higher performance than the 5800X3D. Ideally, you want to be towards the bottom right of this graph.

So, the Ryzen 7 5800X3D consumes much less power in both single-threaded and multi-threaded productivity workloads, and as we saw in our gaming tests, it runs cooler as well. The Core i7-14700K has a distinct performance advantage in all-core workloads, but the power consumption ramps up quickly once it gets going. Still, the Ryzen 7 5800X3D is the clear winner in this round.

⭐Winner: AMD Ryzen 7 5800X3D

The Ryzen 7 5800X3D consumes between 150% and 300% less power than the Core i7-14700K in all-core workloads, making it the definitive winner in this round.

Pricing: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

The pricing situation is a bit of a wildcard in this comparison, since these are not exactly “new” CPUs. The Ryzen 7 5800X3D was recently re-released at $350, which is $100 lower than its 2022 price tag. The Core i7-14700K is currently priced at $370 at the time of writing, which makes the 5800X3D $20 cheaper in a direct comparison.

However, comparing the two CPUs is more than just comparing their sticker price. We must also look at the platform costs of the two CPUs. The Ryzen 7 5800X3D uses the fan-favorite AM4 socket, which has a whole heap of chipsets in all price brackets. You can pair the Ryzen 7 5800X3D with a mid-range B550 or a high-end X570 motherboard, but older 400-series motherboards are also compatible, depending on the board.

As far as the price goes, B550 motherboards can be purchased for $80 - $180, while higher-end X570 motherboards range from $150 - $300. Some premium models can even go beyond $400, but those are not really needed for our CPU since it doesn’t support overclocking. A nice mid-tier B550 or X570 motherboard will be more than enough for our needs.

Memory is where the price difference really grows. The Ryzen 7 5800X3D only supports DDR4 memory, so it is relatively safe from the ongoing DRAM crisis. A nice 32GB DDR4-3200 kit can run you about $140 - $160, which is definitely higher than DDR4 prices of the past, but nothing compared to current DDR5 rates. The Ryzen 7 5800X3D also needs an aftermarket cooler since it doesn’t come with one, and that can cost you about $100 - $150 too.

For the Core i7-14700K, you have the option of either a DDR4 or a DDR5 motherboard. Even then, you still have to choose between a 600-series or a 700-series chipset. For the sake of this comparison, let’s go with a Z790 motherboard since the 14700K is unlocked and we want those overclocking capabilities. A basic Z790 motherboard can be found around the $150 mark, but we would want to go with something that has decent VRMs. That can cost around $200-$250 at current prices.

Of course, as evidenced in our benchmarks, DDR5 memory is the best way to maximize the 14700K's performance. Due to the RAMpocalypse, DDR5 memory is ridiculously expensive, and a 32GB DDR5-6000 kit can cost between $390 - $550 at the time of writing. Going with DDR4 would require a motherboard swap, but it would save you between $300 and $350 on the system based on these two components alone.

For cooling, the 14700K requires special consideration, as we have the option to overclock. Even a stock 14700K sips more power and produces more heat than a 5800X3D, but if you plan to overclock, the thermals can get out of hand pretty quick. You’ll ideally use a solid 360mm AiO liquid cooler for the 14700K, which can add about $100 - $150 to the cost of your build.

Another factor to consider when determining the value of a CPU is the longevity of its platform. AMD’s AM4 platform has been going strong for a decade, and AMD has continued to support it through updates and releases such as the 5800X3D. However, it would be hard to see AMD releasing more CPUs for the AM4 platform going forward.

On the other hand, Intel’s LGA 1700 socket was already semi-retired, but new reports suggest that Intel will bring this platform back in early 2027. New “Raptor Lake Next” CPUs will reportedly be available on the same socket and the same motherboards, so there is certainly a better upgrade path on Intel’s side.

When we put everything together, the Core i7-14700K is a bit hard to recommend from a value perspective. The motherboards for the 14700K are more expensive on average, and if you want to maximize its performance, you will have to take a massive hit to your wallet with DDR5 memory. Moreover, it is more expensive to cool, too. Its platform looks more future-proof in light of recent rumors, but that can’t guarantee it a win in this round.

⭐Winner: AMD Ryzen 7 5800X3D

The 5800X3D is cheaper to get up and running, since you only need an affordable B550 motherboard and some DDR4 memory to get started. The 14700K can be cheap, but that requires you to leave serious performance on the table and go with a DDR4 setup.

Bottom Line: AMD Ryzen 7 5800X3D vs Intel Core i7-14700K

After a grueling 6-round back-and-forth, we finally have our winner. The Intel Core i7-14700K is the superior CPU of the two. Now, it is not as black-and-white as the 4-3 score might suggest, but the 14700K is still the winner of this faceoff.

The Core i7-14700K delivers better gaming performance on average than the 5800X3D. Sure, there are some titles that favor AMD’s 3D V-Cache, but those wins were not as frequent. However, AMD’s 5800X3D has a better chance if the 14700K is limited by DDR4 memory.

Intel’s 14700K is also vastly superior in productivity and has support for manual overclocking. AMD’s main selling point for the 5800X3D in 2026 is its low price, both upfront and in terms of platform costs. It is also an easier CPU to maintain since it runs cooler and consumes less power.

Interestingly, the choice also depends heavily on your memory generation of choice. It is better to save a few bucks and go with a 5800X3D if you plan to stay on DDR4 for now. However, if you are willing to make the (difficult) jump to DDR5, the 14700K is the clear choice.

Potential buyers who want to stick to gaming should still prioritize a Ryzen 7 5800X3D over a Core i7-14700K with DDR5 memory. On the other hand, if you regularly run any type of productivity workload, the 14700K blows the Ryzen out of the water.

⭐ Winner: Intel Core i7-14700K

Nonetheless, the overall winner of our faceoff is Intel’s Core i7-14700K.

Check Out More CPU Faceoffs

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