Atomic Semi, the semiconductor tooling startup founded by chip architect Jim Keller and DIY fabrication pioneer Sam Zeloof, has rebranded as Fab2 and moved its operations to Texas, according to the company's new site at fab2.com. The rebrand recasts the company around the idea they're calling a "fab fab," a factory that mass-produces small semiconductor fabs and the tools inside them.

Fab2 designs and builds every tool in its fabs in-house, from pumps, valves, and gas lines to lithography and the vacuum chambers that house it. The company assembles those components into machines, the machines into complete fabs, and then aims to mass-produce the fabs themselves. It pairs the hardware with Studio, an in-browser, collaborative EDA tool for layout, schematic, and simulation work, previously branded as Atomic Studio.

Rather than moving 300mm wafers through ginormous production lines, Fab2 targets small, software-defined fabs that pattern chips far smaller than a wafer and turn prototypes around in hours. Zeloof built the concept's proof point as a teenager, fabricating lithographic chips in his parents' garage down to roughly 300nm features before co-founding this company with Keller in 2022.

The method's main constraint, however, is throughput. Electron-beam lithography writes patterns directly rather than projecting them through a mask, which makes it slow: a single patterning step on a small chip can take far longer than an EUV scanner needs to expose an entire 300mm wafer. That's a big tradeoff that only really suits prototyping and low-volume runs rather than high-volume production at commercial foundries.

Fab2 now operates three sites: a 120,000 square foot facility in Austin serves as the new headquarters for research and production, a 30,000 square foot site in Lockhart houses the "fab fab" itself, and the original 25,000 square foot "garage fab" remains in San Francisco.

Fab2 said it shifted its hiring focus to Texas after four years in California, and Tracxn lists the company at around 84 employees as of May 2026. The startup raised a reported $15 million seed round in 2023, led by the OpenAI Startup Fund, at a valuation of about $100 million, with angel backing from Naval Ravikant, Nat Friedman, and Fred Ehrsam.

In moving to Texas, Fab2's model of many small, printable fabs now sits beside the likes of Tesla and SpaceX, which announced Terafab back in March, a single Austin megafab targeting a terawatt of annual compute at a cost of up to $119 billion. The contrasting businesses are clearly not competitors; Fab2 sells small fabs and prototyping speed, while Terafab is built for high-volume AI. But they represent competing answers to the same question of how the U.S. should expand its chipmaking capacity — consolidate everything in massive manufacturing campuses, or distribute production across many small, replicable fabs?

Qualcomm is evaluating an acquisition of Jim Keller-led AI processor developer Tenstorrent in a transaction that could value the company at between $8 billion and $10 billion, reports The Information. The discussions are ongoing, and there is no guarantee that a deal will be reached, but if the takeover proceeds, it will not only value Tenstorrent at a premium but will be one of the most expensive transactions in Qualcomm's history.

The report claims that Qualcomm is particularly interested in Tenstorrent's RISC-V-based AI accelerators and data center-grade CPU IP, though it does not specify how the company plans to integrate Tenstorrent and its products into its lineup. For AI, Qualcomm already has its Qualcomm AI200 and AI250 accelerators based on its Hexagon neural processing units (NPUs) customized for data center AI workloads that are due to ship in 2026. For general-purpose computing, Qualcomm is developing its own server CPUs, presumably based on the Arm instruction set architecture, and recently acquired Ventana Micro, which has a data center-grade RISC-V-powered CPU design.

Qualcomm is known for having a multi-faceted strategy, but having two different types of AI accelerators and three types of data center CPUs (one Arm-based, two RISC-V-based) may not be the most optimal strategy for the company.

Qualcomm is one of the companies that acquires other entities, both to get new IP and competencies as well as actual development teams. While the company's acquisition of Atheros in 2011 transformed Qualcomm from primarily an application processor and cellular modem supplier into a company with a broad portfolio of communication products that includes Ethernet and Wi-Fi, the takeover of Nuvia brought the company fresh blood and put it on the map as a client CPU supplier. The same applies to more recent acquisitions of Alphawave Semi (optical connectivity, chiplets, SerDes, IP, new engineers) and Ventana Micro (RISC-V CPU IP, a CPU developers team).

The potential valuation is another point of concern. Last year, the company was seeking approximately $800 million from investors at a valuation of around $3.2 billion, although it remains unclear whether that financing round was completed, according to The Information. Meanwhile, right now Qualcomm and Tenstorrent are reportedly discussing a valuation between $8 billion and $10 billion, and it is unclear whether this valuation is performance milestones-based.

Yet, given that Qualcomm already has AI acceleration and CPU IP, paying $8 billion – $10 billion for Tenstorrent would be difficult to justify. Such sums represent a massive premium for a company whose hardware business remains relatively small compared to established AI accelerator vendors. That said, the more compelling explanation is people.

Tenstorrent has assembled one of the industry's strongest collections of CPU, AI, interconnect, compiler, and systems architects. The obvious name is Jim Keller, but the company has spent years hiring engineers from AMD, Apple, Intel, Tesla, and others, and this team knows how to build chips. Qualcomm has consistently demonstrated that it is willing to spend billions to acquire elite engineering teams rather than build them from scratch.

The Nuvia acquisition is the best precedent: Qualcomm did not buy Nuvia because it lacked Arm licenses or CPU design capability. It bought Nuvia because it wanted the team led by Gerard Williams III and the ability to accelerate its CPU roadmap by years with the Oryon IP.

That said, Tenstorrent looks less like an AI accelerator acquisition and more like a talent and future-architecture acquisition, as in addition to the talented team, Qualcomm would also get plenty of RISC-V expertise, which will make it the leading developer of RISC-V-based solutions in general.

Unlike many startups producing nothing but vaporware, Jim Keller's TensTorrent has actually delivered impressive-looking RISC-V AI accelerators, but there could be some trouble brewing. Starting with firmware version 19.5.0, the firm has now chopped the tensor core count on Blackhole p150 cards from 140 to 120, affecting both new cards and existing units already in customers' hands.

The news was apparently communicated to customers via email, with the same wording present on the firmware update's GitHub page. Tenstorrent isn't elaborating on why the change was made, leaving existing and potential buyers scratching their heads. The quote follows:

The statement seems to raise more questions than answers. Twenty out of 140 cores is about a 14% chop. When comparing the old and new Blackhole p150 product pages on Tenstorrent's site, the raw compute capacity is 774 vs 664 TFLOPS, a change that appears substantial, especially in the context of multi-card setups like the QuietBox. And yet Tenstorrent claims that in practice, for one card, this should amount to a 1-2% performance delta when using TT-Metalium, a low-level developer kit that operates close to the hardware.

One user in the company's Discord server raised the question of whether the SDK even fully utilizes the underlying hardware to begin with, while another remarked that changing the core grid layout and timing can negatively affect existing, tested code. It's not that existing users have much of a choice, either: update the firmware and lose cores, or lose out on new features of a nascent, in-development product. Predictably, jokes about the 14% core chop were plentiful.

One can but hypothesize as to why the change was needed. Perhaps Tenstorrent wasn't getting good yields for their Blackhole chips, but that would be an odd twist given that they're reportedly manufactured on a 6-nm process, pretty mature technology by today's standards. Tenstorrent is already in conversations with multiple 2-nm chip manufacturers for its next generation of products, but in the meantime, has yet to deliver its upcoming two-chip, 64 GB Blackhole p300.

Tenstorrent's existing lineup of Blackhole products comprises AI accelerator cards for workstations and developers wanting to run AI models locally. They're actually reasonably priced, as the p150 model can deliver 664 TFLOPs and comes with 32 GB of VRAM for just $1,399, or about one-third the price of a single RTX 5090, while theoretically delivering several times the performance. The cards can be wired together to pool VRAM, too, and the chips combine CPU and tensor cores on the same die, bypassing a number of limitations of conventional designs.

It's reasonable to expect some turbulence, as it's exceedingly difficult to create an entire new AI accelerator plus its software, on an unusual architecture, with an unusual chip layout. TensTorrent's current aim at small-scale AI accelerators for small businesses, laboratories, and individuals may well carve out a niche of the market and offer dividends in the long run, so long as turbulence is kept to a minimum.

TensorWave, a cloud-platform for AI workloads powered by AMD's MI Instinct accelerators, is kicking off the Beyond CUDA Summit starting today. The event focuses on the concept of the 'CUDA moat,' and how developers can optimize their AI-centric workloads using other alternatives. Attendees can expect to see demonstrations, hot takes, panels, and expert opinions from influential leaders in the AI field including computer architect icons like Jim Keller and Raja Koduri.

It's no secret that Nvidia-built GPUs constitute the majority of hardware in the AI space. Although AMD's Instinct accelerators offer performance comparable to Nvidia hardware, the already-established and mature CUDA ecosystem is indispensable to some users / organizations. Nvidia realized the potential of parallel computing on its GPUs early on and developed a proprietary platform dubbed CUDA, which is now the de facto standard for GPU-accelerated computing.

Through continuous efforts, optimizations, and the sudden rise of AI which coincidentally is powered by GPUs, Nvidia has positioned itself as a leading solution provider. In fact, 90% of Nvidia's revenue is now driven by its data-center offerings, with CUDA being a central selling point. This creates a vendor lock-in situation, where CUDA (software) effectively confines the industry to Nvidia's hardware, limiting innovation and competition.

The industry is shifting gears to a more open-source and hardware-agnostic future, but that's easier said than done. We have OpenCL, ROCm, oneAPI, and Vulkan as alternatives, however, each trails Nvidia in one or many aspects. Enter Beyond CUDA, where key figures in the AI field have rallied up to congregate and develop a more diverse and heterogeneous future. Hosted by TensorWave, the Beyond CUDA Summit will address the many challenges the AI computing industry faces, such as hardware flexibility, cost efficiency, and exploring the available alternatives to CUDA.

Platforms like ROCm require significant developments to achieve parity with CUDA. Even now, ROCm only supports a small selection of modern GPUs while CUDA maintains compatibility with hardware dating back to 2006. AMD's latest RDNA 4 GPUs are still not officially supported by ROCm. Developers have long bemoaned AMD's slow adoption of new features and support on new hardware. On the positive side, Strix Halo is now ROCm-compatible, though only on Windows.

If you live in San Jose, buckle up as the summit takes place at The Guildhouse, which is with notable irony just three blocks away from the McEnery Convention Center, the site of Nvidia's GTC, which also commences today. Participants have the opportunity to win an AMD Instinct MI210 GPU with 64GB of HBM2e memory. The event runs from 12 PM to 10 PM PDT, with four time slots for various sessions. You can learn more details about the summit here.

Jim Keller, a legendary CPU designer and the chief executive of Tenstorrent, this week announced that he had joined the board of directors of AheadComputing, a startup formed by ex-Intel engineers that develops 'breakthrough' application processors based on the RISC-V instruction set architecture. AheadComputing was established by Intel veterans working at the Advanced Architecture Development Group, the crème-de-la-crème of Intel engineers.

"Happy to announce I am on the board of AheadComputing," Jim Keller wrote in an X post. "Debbie Marr is the CEO, she is great. We are making the RISC-V ecosystem, rich, broad, and solid. CPUs, AI, support IP, and software. Open RISC-V is where you can innovate. Unconstrained."

AheadComputing's founding team used to work at Intel's Advanced Architecture Development Group (AADG). It shaped multiple Intel CPU generations spanning desktops, laptops, and servers while specializing in CPU microarchitecture, performance, memory controllers, and even AI/ML workloads.

Given the expertise of its co-founders and Jim Keller's comments, AheadComputing seems likely to specialize in AI and HPC and support IP, which resembles the focus of Jim Keller's Tenstorrent. The company indicates that one of its goals is to develop CPU cores that excel in per-core performance, which is a focus of virtually all CPU developers today, including Apple, AMD, Intel, and Qualcomm.

AheadComputing was founded last year by four Intel veterans: Debbie Marr (now CEO), Jonathan Pearce, Srikanth Srinivasan, and Mark Dechene. Together, they worked at Intel for about a century.

Debbie Marr had an extraordinary career at Intel. She joined 1988 as a design engineer for Intel's Super VGA graphics accelerator and then switched to the Intel 386SL processor, the company's first laptop CPU, in 1989. She was also one of the architects of Intel Pentium Pro (the company's first server processor), numerous Pentium 4 generations (Willamette, Foster, Prescott), and Intel's breakthrough Nehalem architecture.

Marr also developed Intel's Hyper-Threading technology while working on various Pentium 4 iterations. She then became the chief CPU architect for Intel Haswell and Intel Icelake, from pathfinding to execution. In 2019, she became the chief architect of AADG and led it until mid-2024, when she left to found AheadComputing. Jim Keller worked at Intel during Marr's tenure at AADG.

Other founding team members also worked on various of Intel's high-performance and energy-efficient CPU microarchitectures, including Nehalem, Haswell, Broadwell, and Tremont. Meanwhile, Jonathan Pearce led a proof-of-concept research project of an innovative 'microprocessor architecture with breakthrough performance for AI/ML/HPC algorithms.' Overall, AheadComputing has a very experienced team that used to work on some of the best CPUs ever designed and contributed to developing AI and GPU architectures.

Earlier this month, AheadComputing announced that it had secured $21.5 million in initial funding to develop a new microprocessor architecture designed to handle workloads for AI, cloud computing, and edge devices. Investors include Eclipse Ventures, Maverick Capital, Fundomo, EPIQ Capital Group, and Jim Keller. With this funding, AheadComputing plans to expand its engineering team and accelerate the development of its core technology. At present, the company has around 40 employees.

"As esteemed former senior Intel CPU architects, AheadComputing's leadership team is uniquely equipped to solve the complex challenges facing today's computing industry," said Greg Reichow, Partner at Eclipse. "Their commitment to delivering the highest performance cores — while ensuring energy efficiency — will significantly impact multiple industries like mobile, industrial and networking."

Ex-Intel lead silicon engineer Jim Keller says Intel may not make as much money as it used to earn historically, but selling the company or some of its businesses is not a way to unlock shareholder value, but rather a fire sale of a company that has high chances to prosper. Jim Keller, a legendary chip designer and now the chief executive officer of Tenstorrent, a promising AI processor developer, took to Twitter to express his views on the latest news of a potential split or sale of Intel. 

"You build value by having a great goal and a team that loves working to the goal," Keller wrote in an X post. "Intel built the fastest CPUs on the best process [technologies]. This [Handling Intel's businesses to third parties] is not unlocking shareholder value, it is a fire sale. It makes me sad."

"[…] I think a great Intel is worth $1 trillion. Seems a little careless to throw it away," he added later.  

The latest rumors indicate that Broadcom could be interested in taking over Intel's products business, whereas the Intel Foundry unit could form a joint venture with TSMC or even with a conglomerate involving TSMC, Broadcom, Qualcomm, and other companies that would inject money into a new independent chipmaker. 

One commenter in the thread suggested that a better outcome for Intel would be to become a private company with the help of American investors, fire the current board of directors, and then take the time to reinvent Intel. 

"It would be hard but doable," Keller wrote in another post. "Humans are amazing when they have a great goal and a team they believe in." 

The current U.S. government will unlikely support Intel's fabs being run by TSMC or other foreign entities, even though the Trump administration encourages domestic manufacturing. However, if Intel gives up its own manufacturing, it will not only cease to be an integrated device manufacturer (IDM) but also lose one of its strong points: complete control over products and their manufacturing. Also, it's unlikely that TSMC and other potential investors will be tremendously interested in investing in Intel Foundry, which bleeds money as it has yet to land orders from major companies. 

However, companies with deep pockets, such as Broadcom, could take over Intel's products division to gain CPU capability and world-class product design teams. However, a change of Intel ownership automatically terminates the company's broad cross-licensing agreement with AMD. This means the new entity could lose access to innovations developed by AMD and shared between companies as part of their broad cross-license agreement unless a new agreement is inked.

Amazon founder Jeff Bezos has reportedly backed a $700 million funding round for Tenstorrent, an AI chip startup, valuing the company at $2.6 billion. The investment, led by South Korea’s AFW Partners and Samsung Securities, positions Tenstorrent as a serious competitor to Nvidia which is currently the dominant player in the AI chip market. Other investors include LG Electronics, Fidelity, and Hyundai Motor Group.

Tenstorrent, headquartered in Santa Clara, California, plans to use the funds to expand its engineering team, strengthen its global supply chain, and build AI training servers to showcase its technology. The startup aims to develop chips that offer more cost-effective and power-efficient solutions for AI development, leveraging open-source technology and avoiding the costly high-bandwidth memory (HBM) favored by Nvidia.

“You can’t beat Nvidia if you use HBM, because Nvidia buys the most HBM and has a cost advantage. But they’ll never be able to bring the price down the way HBM is built into their products and their sockets,” said Tenstorrent CEO Jim Keller.

Unlike Nvidia’s proprietary ecosystem, Tenstorrent is focusing on interoperability with other technology providers. It advocates for the open-standard RISC-V processor architecture, which Keller believes attracts engineers and fosters innovation.

Tenstorrent’s approach reflects a growing trend in the AI chip industry, where startups are challenging Nvidia’s dominance by offering alternatives tailored to specific needs. While Nvidia generates tens of billions in datacenter revenue each quarter, Tenstorrent has secured nearly $150 million in contracts—a modest figure but a signal of its potential.

The company aims to release a new AI processor every two years. Its first chips were manufactured by GlobalFoundries, with future iterations planned through Taiwan Semiconductor Manufacturing Co. (TSMC) and Samsung. Tenstorrent is also exploring 2-nanometer chip designs, aligning with TSMC and Samsung’s production timelines and Japan’s Rapidus Corp., which targets 2nm output by the year 2027.

As Tenstorrent scales up, it faces the challenge of proving its technology in a market where Nvidia’s dominance remains unmatched. However, with backing from high-profile investors and an innovative open-source approach, it’s positioned as a formidable challenger in the AI chip landscape.

LG and Tenstorrent have announced that they will expand their collaboration efforts. The tech twosome already has some SoC plans in progress, but today they voiced the intention to develop new AI chips to push forward LS’s concept of ‘Affectionate Intelligence’ in AI-powered home appliances, smart home solutions, mobility, and commercial applications.

While Affectionate Intelligence may be merely LG’s marketing Twist on AI, like Cupertino’s ‘Apple Intelligence,’ we are sure there is some serious chip design going on in the background – thanks to chip icon Jim Keller’s involvement and some other clues in today’s press release.

In our main picture, you can see LG CEO William Cho meeting with Tenstorrent CEO Jim Keller at the LG Twin Towers in Yeouido, Seoul. Other senior execs were there, from both companies, to discuss the plans for expanded collaboration.

Regular readers, with some familiarity with Tenstorrent’s recent projects, won’t be surprised that next-gen semiconductors including processors using the RISC-V architecture and multiple chiplets were hot topics during the discussions. The tech CEOs warmly praised each other, with Cho saying Keller’s firm “is bringing the industry’s best AI and RISC-V technology to this collaboration.” Keller’s response was that “LG has a strong SoC development organization and Tenstorrent is excited to continue to partner with them.” The chip architecture icon behind the Athlon 64 and Zen architectures went on to underline that any future ‘Affectionate Intelligence’ SoCs would likely come packing “our AI and RISC-V technology.”

LG recently established a dedicated SoC R&D center specializing in system semiconductor design and development, which should help along any collaborative chip design efforts. According to the press release this facility excels in chiplet-based SoC design, development, and verification. SoCs that have already come from this lab include the DQ-C for AI home appliances and the Alpha 11 AI Processor for OLED TVs.

Tenstorrent’s success in expanding its LG collaboration seems very much in line with its publicly stated strategy of looking for design wins in markets “not well served by Nvidia.” While Tenstorrent seems fully capable of designing high-performance RISC-V CPUs and AI accelerators like the Wormhole, a profitable high-volume niche in mass-market consumer goods could be a great opportunity to embrace.

During the company's latest earnings call, Oracle founder Larry Ellison admitted (via Barron’s) that he had to beg Nvidia CEO Jensen Huang to supply his company with its latest GPUs. “In Nobu Palo Alto, I went to dinner with Elon Musk, Jensen Huang, and I would describe the dinner as me and Elon begging Jensen for GPUs. Please take our money; no, take more of it. You’re not taking enough of it; we need you to take more of our money, please,” Ellison said during the call. “It went okay; it worked.”

It looks like this dinner was very productive indeed and that it was money well spent for Ellison and Oracle. The company recently announced that it will create a Zettascale AI supercluster composed of 131,072 Nvidia GB200 NVL72 Blackwell GPUs that delivers 2.4 ZettaFLOPS of AI performance—more powerful than Musk and xAI’s Memphis Supercluster, which currently has 100,000 Nvidia H100 AI GPUs.

Oracle’s AI plans demand an incredible amount of power, which is also why the company has already secured permits to build three modular nuclear reactors to deliver the electrical needs of its facilities. However, since deploying nuclear reactors to data centers will likely take several years, the company could, in the meantime, follow Musk’s lead and use massive mobile generators to boost local power supply if needed.

Despite being smaller than other big tech companies that offer data center services, like Amazon Web Services, Microsoft Azure, and Google Cloud, Oracle Cloud Infrastructure (OCI) has a distinct advantage over these giants. According to Barron’s report, OCI provides better flexibility and can meet specific requirements that some customers demand. It can even provide offline servers that run on its own networking infrastructure to maximize security for the most demanding clients.

But despite its size, Oracle is pushing its investments in AI. Ellison says that frontier AI models coming in the next three years will cost $100 billion to train, echoing Anthropic CEO Dario Amodei’s thoughts on the matter. And it seems that OCI wants to become one of the leaders in AI processing. “Someone’s going to be better at this than anybody else, and multiple people are trying, and there is a race,” said Ellison during the call. He then added later, “Getting there first is a big deal.”

AI start-up Tenstorrent has announced the commercial release of its Wormhole processors, built to power AI accelerators to compete with Nvidia. Wormhole will power the new Wormhole n150 and n300 AI accelerators, as well as the TT-LoudBox and TT-QuietBox workstations containing four n300s. 

The Wormhole n150 and n300 AI accelerators are 3/4 size PCIe add-in cards based on the Wormhole processor. The n150 has a single Wormhole processor and the N300 holds a pair. The cards are Tenstorrent's second line of dev kits, replacing the Grayskull boards powered by the chip of the same name. Both Wormholes are passively cooled, and operate at up to 160W and 300W respectively.

The Wormhole processors are based on the Tensix core created by Tenstorrent. Each Tensix Core contains what Tenstorrent describes as "five 'baby RISC-V' microprocessors, " with hardware and software support to effortlessly scale up with other Tensix cores across multiple Wormhole chips. 

This native scalability is part of what Tenstorrent hopes will allow it to claim market space away from Nvidia, which controls 80% of the AI accelerator market. Wormhole processors have been around since 2021, and are only seeing a full developer roll-out now for unknown reasons.

Wormhole processors can scale up or down depending on the needs of the end user. In a typical workstation solution with four Wormhole n300 cards, the Wormholes can combine to act as one single processor, looking like a single massive network of Tensix cores to software. The accelerators in a single workstation can also split across to four developers, or run eight unique AI models concurrently. Key to the success of this scaling is that it supposedly does not require virtualization, performing all scaling natively. 

Tenstorrent's preferred way to get Wormhole n300s into the hands of developers is with its pair of prebuilt workstations, the TT-LoudBox and TT-QuietBox. Containing four n300 cards for a total of eight Wormhole processors, the TT-LoudBox is also powered by two Intel Xeon 4309Y 8-core processors, 512GB RAM, 4TB NVME storage, and twin 10 GbE copper ethernet. Available as a tower or rack-mounted, the LoudBox costs $12,000 and is available today.

For those looking for a liquid-cooled experience, Tenstorrent will offer the TT-QuietBox, available today for pre-order. Four Wormhole n300s inside will be complemented by a single AMD EPYC 8124P 16-core CPU, with all other specs the same now under liquid cooling. The price tag will rise to $15,000. 

CEO Jim Keller has been chasing the Nvidia whale for years as head of Tenstorrent. "It’s always rewarding to get more of our products into developer hands," shared Keller in a press release. "Releasing development systems with our Wormhole card helps developers scale up and work on multi-chip AI software." 

The industry pro has enjoyed a lengthy career across many companies, including Apple, where he designed the M1 chip, AMD, Intel, and Tesla, before landing as CEO of Tenstorrent seeking to take on Nvidia's near-monopoly over AI compute. The company, which is set to release the second-gen Blackhole in early 2025, will hope to beat the firmly entrenched Nvidia by serving edge use cases and fringe needs that Nvidia can't meet.

Nvidia dominates the market of AI processors controlling over 80% of sales, according to some recent estimates. But Jim Keller, a legendary designer of processors and current Chief Executive Officer of Tenstorrent, believes that there are markets not served well by Nvidia. As a result, there are opportunities for Tenstorrent and other developers of AI processors. 

"There are lots of markets that are not well served by Nvidia," said Jim Keller in an interview with Nikkei. 

Jim Keller has a truly distinguished computer industry history, making waves at AMD, Intel, and Tesla, and is now heading up the development of AI processors at Tenstorrent. His leadership at Tenstorrent aims to deliver affordable alternatives to Nvidia's expensive GPUs that cost $20,000 - $30,000 or more each. Tenstorrent’s business approach aims to serve markets that Nvidia does not adequately address, particularly in the edge space. According to Tenstorrent, its Galaxy systems are three times more efficient and 33% less expensive than Nvidia's DGX, which are perhaps the world's most popular AI servers.

Tenstorrent is on track to release its second-generation multipurpose AI processor by the end of the year, Nikkei reports, without disclosing the name of the processor. Based on Tenstorrent's latest roadmap from last fall, the company intends to release its Black Hole standalone AI processor and Quasar low-power low-cost chiplets for multi-chiplet AI solutions. 

The company claims its upcoming processors provide performance efficiency comparable to Nvidia's AI GPUs. The touted efficiency and lower cost is partly achieved by avoiding usage of high-bandwidth memory (HBM) and using GDDR6 instead, which is a logical thing for entry-level and mainstream AI processors mostly designed for AI inference. Meanwhile, Tenstorrent says that its architecture is less memory bandwidth-hungry than competitors, which is a key reason for its higher efficiency and lower cost. 

While Tenstorrent yet has to grab a significant part of the AI processor market, the company for now focuses on cost-effective yet scalable AI solutions that can address a wide range of applications currently not served properly by Nvidia. However, these markets are not going to be blue oceans as many companies will try to address them with their products in the coming quarters battling against the entrenched Nvidia. Rather than compete with Nvidia head-on, it will be much easier for new entrants to address niche markets that are indeed not directly catered for by the green team.

As a strong supporter of open standards, Jim Keller tweeted that Nvidia should have used the Ethernet protocol chip-to-chip connectivity in Blackwell-based GB200 GPUs for AI and HPC. Keller contends this could have saved Nvidia and users of its hardware a lot of money. It would have also made it a bit easier for those customers to migrate their software to different hardware platforms, which Nvidia doesn't necessarily want.

When Nvidia introduced its GB200 GPU for AI and HPC applications, the company primarily focused on its AI performance and advanced memory subsystem, telling little about how the device was made. Meanwhile, Nvidia's GB200 GPU comprises two compute processors stitched together using TSMC's CoWoS-L packaging technology and the NVLink interconnection technology, which uses a proprietary protocol. This isn't an issue for those who already use Nvidia's hardware and software, but this poses a challenge for the industry in porting software from Nvidia's platforms.

There is a reason why Jim Keller, a legendary CPU designer and chief executive officer of Tenstorrent, an Nvidia rival, suggests that Nvidia should have used Ethernet instead of proprietary NVLink. Nvidia's platforms use proprietary low-latency NVLink for chip-to-chip and server-to-server communications (which compete against PCIe with the CXL protocol on top) and proprietary InfiniBand connections for higher-tier comms. To maximize performance, the software is tuned for both technologies' peculiarities. For obvious reasons, this could somewhat complicate software porting to other hardware platforms, which is good for Nvidia and not exactly suitable for its competitors. (You can see his thread if you expand the tweet below.)

There is a catch, though. Ethernet is a ubiquitous technology both on the hardware and software level, and it is a competitor to Nvidia's low-latency and high-bandwidth (up to 200 GbE) InfiniBand interconnection for data centers. Performance-wise, Ethernet (particularly next-generation 400 GbE and 800 GbE) can compete with InfiniBand. 

However, InfiniBand still has some advantages regarding features for AI and HPC and superior tail latencies, so some might say that Ethernet's capabilities don't cater to emerging AI and HPC workloads. Meanwhile, the industry — spearheaded by AMD, Broadcom, Intel, Meta, Microsoft, and Oracle — is developing the Ultra Ethernet interconnection technology, poised to offer higher throughput and features for AI and HPC communications. Of course, Ultra Ethernet will become a more viable competitor to Nvidia's InfiniBand for these sorts of workloads.

Nvidia also faces challenges with its CUDA software platform dominance, hence the advent of the widely industry-supported Unified Accelerator Foundation (UXL), an industry consortium that includes Arm, Intel, Qualcomm, and Samsung, among others, that's intended to provide an alternative to CUDA. 

Of course, Nvidia needs to develop data center platforms to use here and now, which is probably at least part of its desire to spend billions on proprietary technologies. If open-standard technologies like PCIe with CXL and Ultra Ethernet will outpace Nvidia's proprietary NVLink and InfiniBand technologies regarding performance and capabilities, Nvidia will have to redevelop its platforms, so Keller advises (or trolls) that Nvidia should adopt Ethernet. However, this may be years away, so for now, Nvidia's designs continue to leverage proprietary interconnects.

Several years ago, AMD adopted a multi-chiplet design for its client desktop and data center processors well ahead of its rivals. Back then, it was the only way for AMD to offer products with higher core counts than rival Intel, and now the move is seen as a strategic pivot towards an inevitable multichiplet design methodology. Today, Sam Naffziger, senior vice president and corporate fellow at AMD, thinks about how the Universal Chiplet Interconnect Express (UCIe) specification will create a chiplet ecosystem and enable custom multi-chiplet design.

For modular multichiplet designs, a high-performance, low-latency, and low-power interface is a must. The Infinity Fabric interface enabled AMD to build unique EPYC, Ryzen, and now Instinct MI300-series processors with unrivaled core counts, performance, and feature sets, Naffziger explained in a YouTube video conversation with Mark Papermaster, AMD's chief technology officer.

"The [interface] latency was too high, the power cost was too high, but we had a team of can-do engineers who said, 'I know how to solve that problem,' 'I will deliver a lightweight interface,' 'I will slim this down,' and 'I will eliminate cycles of latency,'" Naffziger said referring to the era when AMD was developing its multi-chiplet 2nd-gen EPYC and Ryzen processors. "If we hit these targets, now we have a multi-die solution that behaves just like a monolithic SoC. We set those targets, and then we oversaw the team's execution to make it happen. It was so transformative."

To a large degree, Infinity Fabric was a savior for AMD when it was introduced. However, since this is a proprietary technology, it cannot be used by third parties. This is where the open UCIe specification for die-to-die interconnects comes into play. The open spec, largely based on Intel's AIB, defines a 32 GT/s 16 to 64 lanes physical layer, protocol stack (CXL.io, CXL.mem, and CXL.cache), software model, and compliance testing procedures. As for performance, the UCIe 1.0 technology enables bandwidth density up to 1.35 TB/s per mm^2 for a common 45-micrometer bump pitch. 

"What we can do [with UCIe] is have a chiplet ecosystem and library, […] UCIe opens up the opportunity for third parties to exploit that [modular design capability]," said Naffziger. "Companies who want to do a custom platform and leverage everything else can just do one little chiplet and bolt it up. So, the opportunities are endless. I mean this; we're going to see much more of this proliferating in the industry, but it does require standards and carefully thought-through design platform capability." 

While AMD was part of the group that developed the UCIe specification, whether the company plans to build UCIe-compatible chiplets remains to be seen. 

Nvidia CEO Jensen Huang recently took to the stage to claim that Nvidia's GPUs are "so good that even when the competitor's chips are free, it's not cheap enough." Huang further explained that Nvidia GPU pricing isn't really significant in terms of an AI data center's total cost of ownership (TCO). The impressive scale of Nvidia's achievements in powering the booming AI industry is hard to deny; the company recently became the world's third most valuable company thanks largely to its AI-accelerating GPUs, but Jensen's comments are sure to be controversial as he dismisses a whole constellation of competitors, such as AMD, Intel and a range of competitors with ASICs and other types of custom AI silicon. 

Starting at 22:32 of the YouTube recording, John Shoven, Former Trione Director of SIEPR and the Charles R. Schwab Professor Emeritus of Economics, Stanford University, asks, "You make completely state-of-the-art chips. Is it possible that you'll face competition that claims to be good enough – not as good as Nvidia – but good enough and much cheaper? Is that a threat?"

Jensen Huang begins his response by unpacking his tiny violin. "We have more competition than anyone on the planet," claimed the CEO. He told Shoven that even Nvidia's customers are its competitors, in some cases. Also, Huang pointed out that Nvidia actively helps customers who are designing alternative AI processors and goes as far as revealing to them what upcoming Nvidia chips are on the roadmap.

This does indeed sound like quite an extraordinary way of doing business, but Huang's next claim that Nvidia operates as a "completely open book" while working with almost everyone else in the industry may be harder to believe. Remember, there were strong accusations of Nvidia operating a GPU Cartel just recently, with customers reportedly scared to speak to rival GPU / AI accelerator makers for fear of delayed orders. An industry consortium has also formed in an attempt to unseat the company's dominant CUDA programming model. 

Returning to the Stanford interview, Jensen Huang outlined Nvidia's currently unassailable unique selling points. The Nvidia CEO said that whereas you could build a chip to be good at one particular algorithm, Nvidia's GPUs are programmable. Moreover, the Nvidia platform is "a great standard… in every single cloud computer company." A typical data center that wants to support a wide range of customers, from financial services to manufacturing and so on, will therefore be drawn towards Nvidia hardware.  

Free isn't cheap enough to compete with Nvidia

Huang also sought to provide a contrast that might be counterintuitive to those focused on GPU prices: people who buy and sell chips think about the price of chips, and people who operate data centers think about the cost of operations, he clarified.

Of course, companies will be well aware of the Total Cost of Ownership (TCO), which basically means that Nvidia's claimed benefits like time to deployment, performance, utilization, and flexibility are "so good that even when the competitor's chips are free, it's not cheap enough," according to Huang. 

Concluding his answer to Shoven, the Nvidia CEO underlined that keeping this far ahead, with this unbeatable TCO, is Nvidia's goal. Huang reminded summit attendees that what Nvidia does takes a lot of hard work and innovation — no luck involved here — and nothing is taken for granted.

Naturally, Nvidia's competitors would beg to differ with Huang's statements, but the incumbent is the unquestioned 800lb gorilla of the AI world right now, placing the onus on its competitors to prove Jensen's statements wrong. 

Elon Musk has shared some previously unseen photos of when Nvidia CEO Jensen Huang called round to donate the world’s first DGX-1 server to budding startup OpenAI. The pictures were taken back in 2016, but this is the first we've seen of the two silicon mega celebs enjoying each other's company. Musk was one of the co-founders of OpenAI in 2015, but stepped away in 2018 over rumored conflicts of interest and the perceived change of direction at the artificial intelligence pioneering 'nonprofit.'

OpenAI is now a for-profit company and seems to have steered away from its early open-source leanings, which has caused some highly public friction between Musk and current OpenAI CEO, Sam Altman. With the burgeoning success of AI in recent years and OpenAI’s central role becoming obvious, Musk set up a new AI venture called xAI and announced the AI chatbot Grok last year.

Moving our focus back to the newly shared images, we know they come from August 2016, when Musk Tweeted “Would like to thank @Nvidia and Jensen for donating the first DGX-1 AI supercomputer to @OpenAI  in support of democratizing AI technology.” It looks like happier times, with all the jolly folk in the images clearly delighted with the donation, looking forward to the exciting future of accelerated AI. Note also that a single DGX-1 rack-mounted server does not constitute a "supercomputer" — not without dozens or hundreds more such units — but that's a separate topic.

Underlining his now older and pessimistic persona, Musk shared the happy images shortly after commenting “And now look what’s happened :( .” This is an obvious grumble about the path OpenAI has steered in recent years. Last February, Musk clarified his objections to the stewardship of OpenAI, complaining that “OpenAI was created as an open source (which is why I named it “Open” AI), non-profit company to serve as a counterweight to Google, but now it has become a closed source, maximum-profit company effectively controlled by Microsoft.” #SourGrapes

Nvidia’s DGX-1 ‘AI supercomputer in a box’ has been updated significantly since its launch in 2016, but when this machine was donated it was a $129,000 system that integrated eight Nvidia Tesla P100 (Pascal) GPUs, with the whole system capable of up to 170 teraflops (FP16) to tackle machine learning tasks. Nvidia subsequently rolled out the DGX-2 (Volta), the DGX A100 Server (Ampere), and its latest gen the DGX H100 Server (Hopper). Bigger systems like the DGX GH200 AI Supercomputer using 256 total Grace Hopper Superchips are the newest products in the family.

Jim Keller, a legendary processor architect who has worked on x86, Arm, MISC, and RISC-V processors, this weekend criticized Nvidia's CUDA architecture and software stack and likened it to x86, which he called a swamp. He pointed out that even Nvidia itself has multiple special-purpose software packages that rely on open-source frameworks for performance reasons. 

"CUDA is a swamp, not a moat," Keller wrote in an X post. "x86 was a swamp too. […] CUDA is not beautiful. It was built by piling on one thing at a time." 

Indeed, just like x86, CUDA has gradually added functionality while maintaining backward compatibility in software and hardware. This makes Nvidia's platform complete and backward compatible, but it affects performance and makes program development harder. Meanwhile, many open-source software development frameworks can be used more efficiently than CUDA. 

"Basically nobody writes CUDA," wrote Keller in a follow-up post. "If you do write CUDA, it is probably not fast. […] There is a good reason there is Triton, Tensor RT, Neon, and Mojo." 

Even Nvidia itself has tools that do not exclusively rely on CUDA. For example, Triton Inference Server is an open-source tool by Nvidia that simplifies deploying AI models at scale, supporting frameworks like TensorFlow, PyTorch, and ONNX. Triton also provides features like model versioning, multi-model serving, and concurrent model execution to optimize the utilization of GPU and CPU resources. 

Nvidia's TensorRT is a high-performance deep learning inference optimizer and runtime library that accelerates deep learning inference on Nvidia GPUs. TensorRT takes trained models from various frameworks, such as TensorFlow and PyTorch, and optimizes them for deployment, reducing latency and increasing throughput for real-time applications like image classification, object detection, and natural language processing. 

But although architectures like Arm, CUDA, and x86 might be considered swamps because of their relatively slow evolution, mandated backward compatibility, and bulkiness, these platforms are also not as fragmented as things like GPGPU, which may not be a bad thing at all.  

It isn't clear what Jim Keller thinks of AMD's ROCm and Intel's OneAPI, but it is clear that even though he spent many years of his life designing x86 architectures, he isn't enamored with its future prospects. His statements also imply that even though he has worked stints at some of the largest chipmakers in the world, including the likes of Apple, Intel, AMD, Broadcom (and now Tenstorrent), we might not see his name on the Nvidia roster any time soon. 

Masayoshi Son, the founder of SoftBank Group, plans to raise $100 billion for a new chip venture called Project Izanagi, aiming to rival Nvidia in artificial intelligence processors, reports Bloomberg, citing sources with knowledge of the matter. Son envisions this initiative as contributing to the development of artificial general intelligence (AGI), leading to a future where machines surpass human intelligence.

The project seeks to complement SoftBank’s Arm Holdings, which designs processor architectures. But it is unclear whether the AI processors designed by Project Izanagi will rely on technologies such as instruction set architecture (ISA) developed by Arm. Furthermore, how the venture will co-exist with Arm’s purported plans to create reference chip designs for various workloads remains to be seen. An interesting wrinkle is that the venture is named after the Japanese god of creation and life, reflecting Son’s ambitious vision for the project.

Building a company that could compete against Nvidia successfully is challenging. The green company not only has plenty of talented hardware engineers and highly competitive hardware, but it also has a ubiquitous CUDA software stack. It is tough to compete against something that has been evolving for well over 16 years now.

Project Izanagi is part of Son’s broader focus on AGI, which he believes will be realized within the next decade. He has consistently advocated for adopting AI, leading to a safer, healthier, and happier world. Son’s enthusiasm for AGI is intense, to say the least, despite facing numerous setbacks in his startup investments. He told a group of Japanese enterprise clients to embrace AI or risk being left behind, emphasizing the transformative potential of AGI.

“AGI is what every AI expert is after,” Son is reported to have said by Bloomberg. “But when you ask them about a detailed definition, a number, the timing, how much computing power, how much smarter AGI is than the human intelligence, most of them don’t have an answer. […] I have my own answer: I am convinced AGI will be real in 10 years.”

SoftBank’s financial position is strong, with ¥6.2 trillion ($41 billion) in cash and cash equivalents as of December 31. According to the report, Son intends to invest $30 billion from SoftBank, with the remaining $70 billion potentially sourced from Middle Eastern institutions. The specifics of the funding and execution are still being determined, and the project may evolve further as plans solidify, according to Bloomberg. Son’s approach to investment is dynamic, and he is known for abruptly changing his mind.

The initiative is separate from any collaboration with OpenAI’s Sam Altman, although Son and Altman have reportedly discussed joining forces in semiconductor manufacturing.

Reports say that OpenAI CEO Sam Altman plans to raise $5 to $7 trillion to build a network of fabs to produce enough chips for artificial intelligence (AI) applications, raising many eyebrows in the industry. Nvidia's Jensen Huang said that the architectural innovation of AI processors is more important than the quantity of these processors. Now, Jim Keller, a legendary CPU developer who now works at Tenstorrent developing AI and HPC processors, essentially claims the same thing.

"I can do it for less than $1 trillion," Keller wrote in a quote tweet in response to Altman's tweet that says "f* it why not 8" in an apparent reference to raising the fundraising amount to 8 trillion.

Altman's plan to raise trillions of dollars and build enough AI processors for all workloads and emerging AI companies is very ambitious. Still, it essentially involves a radical expansion of the semiconductor supply chain, which could lead to overcapacity at foundries and devaluation of these processors on the market. But instead of building more chips for AI, both Keller and Nvidia CEO Huang say that these processors (see our list of best CPUs) must get more sophisticated. Furthermore, the supply chain of AI hardware has to get simpler to reduce the costs of AI servers and other devices.

"Start by eliminating the margin stacking," wrote Keller, implying the cost or profit margin added by each participant in the supply chain to deliver a product to the end user. "There are two–three layers. Then, make chips way faster so the hardware matches the software. That is harder but doable."

Tenstorrent itself has a very ambitious roadmap that involves the development of processors for AI and HPC applications. Each AI processor in the roadmap increases the number of processing units, and the units become more advanced, improving their performance efficiency. Yet, demand for AI performance is growing fast, so only time will tell whether Tenstorrent and other companies will catch up with it in the foreseeable future.

Altman's fundraising goal of $5 trillion to $7 trillion far exceeds the present valuation of the worldwide semiconductor industry, which recorded sales of $527 billion last year and is anticipated to hit the $1 trillion mark by 2030. Meanwhile, chip manufacturers invested $99.5 billion in chip fabrication equipment in 2022 and are projected to allocate $97 billion for fabrication tools this year.

Artificial intelligence pioneer OpenAI announced a new generative tool on Thursday. Dubbed Sora (the Japanese word for sky), it is OpenAI’s most ambitious development to date, able to generate complex high-definition videos up to a minute long from a mere text prompt. Image prompts can also be used. Sora isn’t open to the general public yet, as OpenAI has decided to restrict access to a select group of researchers and visual professionals while it refines its offering. Importantly, this pre-market period will also be used to implement safety measures so the tool isn’t used to build misinformation, hateful content, etc.

Let’s dive straight into some examples. If a picture says a thousand words, a video can do the same at tens of frames per second. The first example is a full-minute clip from a relatively complex prompt. Here, Sora flexes its muscles, rendering the neon-lit streets of Tokyo, which have recently been dampened by rainfall, and the movements of the elegant central character.

In its blog post about Sora, OpenAI explains that this prompt-to-video tool has been designed to generate complex scenes with multiple characters with accurate and true-to-life details. “The model understands not only what the user has asked for in the prompt, but also how those things exist in the physical world,” it asserts. By way of illustration, OpenAI leads with the video below. However, this representation of a Jeep speeding along a dry dusty mountainside road through a forest appears to be very ‘video game’ like.

On the topic of video game techniques, seasoned tech industry analyst Patrick Moorhead, reckons that most of the generated videos have both characters and camera moving simultaneously to “trick the brain into not noticing the details that would point out the uncanny valley.” Some believe Sora was at least partially trained using synthetic video sourced from Unreal Engine.

It is good that OpenAI isn’t shy about admitting its model still has weaknesses. The blog explains that Sora-generated videos “may struggle with accurately simulating the physics of a complex scene, and may not understand specific instances of cause and effect.” Moreover, OpenAI again shows us some video examples. Of the five it highlights, probably the most jarring to our eyes are the ones featuring the gray wolf pups, and the video embedded below which was generated from the prompt “Archeologists discover a generic plastic chair in the desert, excavating and dusting it with great care.”

Beneath this video in the OpenAI blog, Sora’s gaffe is explained as being due to the model not understanding that a chair is a rigid object. That shouldn't take long to fix...

Safety – why we can’t have nice things

We mentioned safety briefly in the intro and it is clear that a generative AI tool like Sora is going to be used for all kinds of mischief by the general public. However, OpenAI is understandably keen to implement safety measures in Sora before it goes prime time to lessen the tide of nasty stuff some folk will wish to generate.

Specifically, the OpenAI blog says it will be working with the first testers to prevent the generation of “misinformation, hateful content, and bias.” Additionally, it is taking steps to both prevent and detect any such content in videos. Other verboten prompt topics will include “extreme violence, sexual content, hateful imagery, celebrity likeness, or the IP of others.”

Fake audio and video recordings have previously hit the news headlines and had all sorts of repercussions, so keeping a lid on the scope of Sora’s output may be a priority for a responsible developer.

Sora isn’t the first text-to-video generator we have seen, but it is the most advanced, complex, and realistic generator so far. Many have commented that the impact of Sora will be significant and felt far beyond the computer and tech news sphere.

In a new note to its clients, analyst firm UBS says that the lead time (wait time) for Nvidia's hugely popular H100 80GB GPU for AI applications has shortened from 8-11 months to just 3-4 months (via SeekingAlpha). According to the firm, this shift suggests a potential peak in near-term growth but could signal trouble for Nvidia's future growth prospects. However, UBS still upgraded its outlook on Nvidia, increasing its earnings forecasts and target price to $850. 

The reduction in lead times is a double-edged sword. On the one hand, it indicates that Nvidia's production partner TSMC (or its chip-packaging subcontractors) is expanding its CoWoS packaging production capacity (which limited the supply of H100 and other advanced processors used for AI applications), which means better supply and quicker fulfillment of orders. This efficiency could lead to short-term revenue and earnings boosts as the company can ship more products within a shorter timeframe. On the other hand, as lead times approach zero, Nvidia will transition from shipping against both backlogs and new orders to solely new orders, likely resulting in a decline in revenue.

TSMC said it would expand CoWoS capacity by the end of 2023 and double capacity from mid-2023 levels by the end of 2024. Perhaps the expansion of CoWoS capacity at TSMC or one of its OSAT partners is proceeding faster than expected, leading to the reduction in H100 lead times. 

On the other hand, now that Nvidia cannot ship fully-enabled H100 to China due to U.S. restrictions, reportedly leading to lower demand in China, it might simply have plenty of 'spare' H100 silicon to ship elsewhere. While China accounts for a significant portion of Nvidia's revenue, it isn't clear if its reduced shipments could cause H100 lead times to shrink from 8-11 months to just 3-4 months.

The market currently anticipates continued growth for Nvidia, with no expected quarter-on-quarter drops in revenue up to January 2026. However, the rapid decrease in lead times suggests that this growth might cool off much sooner, potentially within the next two or three quarters. Analysts note this scenario is not reflected in the stock's current valuation, which assumes uninterrupted growth. 

Despite the potential for a slowdown in Nvidia's growth, it's important to note that the overall AI capacity will continue to expand. Nvidia's shipments will contribute to the growing install base of GPUs, and other competitors will add to this growth. Therefore, while Nvidia's sequential growth may face challenges, the broader AI industry will continue to advance.

When we first heard that OpenAI's head, Sam Altman, was looking to build a chip venture, we were impressed but considered it as another standard case of a company adopting custom silicon instead of using off-the-shelf processors. However, his reported meetings with potential investors to reportedly raise $5 to $7 trillion to build a network of fabs for AI chips is extreme given that the entire world's semiconductor industry is estimated to be around $1 trillion per year. Nvidia's Jensen Huang doesn't believe that much investment is needed to build an alternative semiconductor supply chain just for AI. Instead, the industry needs to continue its GPU architecture innovations to continue improving performance — in fact, Huang claims that Nvidia has already increased AI performance 1 million fold over the last ten years.

"If you just assume that that computers never get any faster you might come to the conclusion [that] we need 14 different planets and three different galaxies and four more Suns to fuel all this," said Jensen Huang at the World Government Summit. 

Investing trillions of dollars to build enough chips for AI data centers can certainly solve the problem of shortages in the course of the next three to five years. However, the head of Nvidia believes that creating an alternative semiconductor supply industry just for AI may not be exactly the best idea since, at some point, it may lead to an oversupply of chips and a major economic crisis. A shortage of AI processors will eventually be solved, partly by architectural innovations, and companies who want to use AI on their premises will not need to build a billion-dollar data center. 

"Remember that the performance of the architecture is going to be improving at the same time so you cannot assume just that you will buy more computers," said Huang. "You have to also assume that the computers are going to become faster, and therefore, the total amount that you need is not going to be as much."

Indeed, Nvidia's GPUs evolve very fast when it comes to AI and high-performance computing (HPC) performance. The half-precision compute performance of Nvidia's V100 datacenter GPU was a mere 125 TFLOPS in 2018, but Nvidia's modern H200 provides 1,979 FP16 TFLOPS. 

"One of the greatest contributions, and I really appreciate you mentioning that, is the rate of innovation," Huang said. "One of the greatest contributions we made was advancing computing and advancing AI by one million times in the last ten years, and so whatever demand that you think is going to power the world, you have to consider the fact that [computers] are also going to do it one million times faster [in the next ten years]."

Rumors about Sam Altman's chip production ambitions have been circulating for a while, and now they are finally taking shape. Apparently, Sam Altman is not going to establish a company that would develop and build processors for artificial intelligence (AI). What he is working on is a very ambitious effort: He wants to raise $5 trillion to $7 trillion to build a network of fabs run by foundries that would produce chips not only for OpenAI, but for others, too, reports the Wall Street Journal. If he succeeds, the project will reshape the whole semiconductor industry.

Sam Altman is reportedly exploring a collaborative venture that would connect OpenAI, various investors, contract chip manufacturers, and power providers to build a network of fabs that would make ample use of chips for OpenAI (the company will commit to become a significant client for these chip plants) and other clients. The fabs will be operated by existing foundries (the WSJ specifically mentions TSMC, which is reportedly a company that Altman had met in recent weeks), whereas power plants for these fabs will be run by other companies. The whole project will require investments between $5 trillion to $7 trillion, according to the WSJ.

This fundraising target is exceptionally high, dwarfing the current valuation of the global semiconductor industry, which stood at $527 billion in sales last year, with projections to reach $1 trillion by 2030. Meanwhile, chipmakers spent $99.5 billion on fab equipment in 2022 and are expected to spend $97 billion on fab tools this year.

At present, a leading-edge semiconductor production facility costs from $20 billion to $30 billion, but going forward they are going to get considerably costlier. There is no information about how many fabs Altman is envisioning and over how many years, but the $5 trillion to $7 trillion estimations probably include building not only the fabs themselves, but a whole new infrastructure around them, which includes power plants, over several years. One of the many remaining questions is where those fabs will be located.

Funding strategies may include leveraging debt, but the project is still in the preliminary discussion phase, with many uncertainties regarding investor participation and long-term success. 

Altman has been meeting with various high-level investment figures to talk about the project, including Sheikh Tahnoun from the UAE and Masayoshi Son from SoftBank. Meanwhile, the information about the potential venture is strictly unofficial at this point, so take it with a grain of salt.

A significant concern for this endeavor is the geopolitical sensitivity surrounding the semiconductor supply chain. The U.S. government exhibits caution over allowing foreign governments substantial influence in an industry pivotal to the digital economy's infrastructure. This factor adds a layer of complexity to Altman's vision, as he needs to find a balance between securing foreign investment and adhering to the national security interests of the U.S.

CPU-Z is an app that shows a PC's hardware specifications, providing in-depth details about the CPU in particular. It also comes with a CPU benchmark, and although it's not nearly as popular as Cinebench, it's still popped up in some reviews and even AMD's marketing slides. However, technical analysis site Chips and Cheese has found that CPU-Z's benchmark just isn't perfect for evaluating the best CPUs.

CPU benchmarks can test lots of different things because there's so much to a CPU on a microscopic level, and so other benchmarks give different rankings. But what a benchmark doesn't test can also be necessary, and that's the critical issue with CPU-Z's benchmark, according to Chips and Cheese, as it doesn't adequately test cache or branch prediction.

The cache is a small amount of memory integrated into processors to lower the time spent communicating with RAM, which is much slower. The CPU-Z benchmark is less than 32KB large, which fits into the L1 (first level) cache of even old CPUs. While technically very efficient, it also makes for a benchmark that can't stress a CPU's cache, so CPUs with better cache don't score any better.

Branch prediction is the process of a chip attempting to guess upcoming tasks. Correct predictions mean faster execution, while wrong predictions lose time. In CPU-Z, Chips and Cheese found that even the infamous FX-8150 Bulldozer CPU had a branch prediction success rate of 95%. That's pretty generous for a CPU that received universally bad reviews when it launched in 2011.

It's not just Chips and Cheese that thinks cache and branch prediction performance is essential, as the report quotes Jim Keller in the conclusion. The legendary engineer in 2021 claimed some of the most significant limitations on performance today are "branch predictability and data locality." With the latest AMD and Intel CPUs bulking up in cache to keep data as accessible to the CPU as possible, Keller is probably right.

While everyone praises Nvidia — whose market capitalization broke $1 trillion earlier this year — for the ongoing artificial intelligence (AI) and high-performance computing (HPC) megatrends, there's another company that not only heavily benefits from said AI and HPC megatrends, but which basically controls production of AI processors.

Tens of Billions of Dollars

That company is TSMC — which produces some of the most complex processors for AI and HPC machines ever built, including those from Nvidia, AMD, Intel, Tenstorrent, Cerebras, and Graphcore (just to name a few), according to a report from DigiTimes. Nvidia's A100 and H100 (as well as its A800 and H800 derivatives for the Chinese market), the most popular compute GPUs used for AI and HPC workloads, are made at TSMC, as are AMD's EPYC CPUs and Instinct GPUs. Rising AI and HPC stars such as Tenstorrent, and developers of such exotic things as wafer scale processors such as Cerebras also chose TSMC for their products. 

While TSMC does not disclose how much it earns from selling CPUs, GPUs, and specialized processors or SoCs for AI, datacenter, HPC, and servers, these products use a lot of silicon — so TSMC probably earns tens of billions making those products for its high-profile customers. For example, Nvidia's GH100 compute GPU has a die size of 814 mm2, whereas AMD's EPYC 'Genoa' uses 12 Zen 4-based CCD chiplets — each measuring around 72 mm2 and thus using 864 mm2 of N5 silicon.

While we do not have revenue splits for TSMC's rivals Samsung Foundry and GlobalFoundries, given that these companies are so significantly behind the Taiwanese contract maker of chips, it is safe to say that TSMC benefits from AI and HPC in general. It particularly dominates shipments of AI GPUs, as it makes them for both Nvidia (which controls over 90% of shipments) and AMD (which controls less than 10%). 

AI and HPC Gaining Importance for TSMC

TSMC itself provides a rather detailed revenue split that clearly distinguishes between automotive, IoT, smartphones, and high-performance computing, but it is not detailed enough to tell the difference between chips for AI, HPC, client PCs, servers, and game consoles. For TSMC, all of these processors and SoCs belong to the HPC segment — a segment that is thriving. 

HPC products accounted for 30% of TSMC's revenue, or $10.389 billion, in 2019. That same year, smartphone SoCs accounted for 49% of TSMC's revenue, or $16.97 billion. But the share of HPC products in TSMC's revenue has been growing: the category accounted for 33% in 2020 ($15 billion), 37% in 2021 ($21 billion), and 41% in 2022 ($31.11 billion). The trend has been the opposite for smartphone SoCs, which accounted for 39% of TSMC's sales in 2022 ($29.59 billion).

While AMD and Nvidia buy boatloads of datacenter-oriented silicon from TSMC, Apple is still the largest customer for the world's No. 1 maker of chips — especially now that it has both smartphone and PC SoCs (which fall into the HPC category). Apple alone was responsible for approximately 23% of TSMC's total sales in 2022, according to DigiTimes.

More Chips Incoming

As the semiconductor sector recovers from its downturn, rising interest for generative AI is stimulating the market. Nvidia is benefiting greatly from this AI surge through its TSMC-manufactured A100/A30/A800 and H100/H800 compute GPUs. Similarly, AMD is expanding orders with TSMC for its upcoming Instinct MI300 series products that will enter mass production in the second half of 2023 at TSMC's N5-class node.

In addition, Apple, AMD, and Nvidia are committed to use TSMC's N3 (3nm-class) and N2 (2nm-class) production technologies for future chips, according to the DigiTimes report.

Jim Keller, chief executive officer of Tenstorrent, shared the company's performance forecasts for CPUs based on its own Ascalon processor core compared to competitors, including AMD's Zen 5, Amazon's Graviton 3, and Nvidia's Grace. Tenstorrent's Ascalon is projected to provide market-leading integer performance-per-watt, but what attracted a lot of attention is that Tenstorrent expects AMD's Zen 5 to be the performance champion in raw integer throughput. In fact, Keller predicts that AMD's Zen 5 will be 30% faster than the current-gen Zen 4 in integer workloads. 

Jim Keller shared the company's performance projections for Tenstorrent's in-house-designed 8-wide out-of-order execution Ascalon RISC-V core against potential competitors in the SPEC CPU 2017 INT Rate benchmark that measures integer performance. The company expects its Ascalon 1.9 SPEC2K17INT/GHz to hit 7.03 points and its Ascalon 2.2 SPEC2K17INT/GHz to hit 8.14 points. 

Tenstorrent's performance expectations for its own CPUs were revealed at the Nerds Talking to Nerds About RISC-V event in India, as you can see in the slide below. 

The predictions put Tenstorrent's upcoming CPU core comfortably ahead of Intel's Sapphire Rapids (7.45 points), Nvidia's Grace (7.44 points), and AMD's Zen 4 (6.80 points). Yet, AMD's Zen 5 is projected to hit 8.84 points, making it the absolute integer performance champion in 2024 – 2025. 

There is a major catch with Tenstorrent's performance expectations: they are all projections and not real or even simulated benchmarks, Tenstorrent told Tom's Hardware. So while we can expect engineers from Tenstorrent to accurately model the performance of their own CPU design and try to predict what AMD could offer next, these are still projections, not actual benchmark results.

For obvious reasons, AMD's Zen 5 performance number has attracted the most attention, even though it is highly unlikely that this projection is completely accurate. But what is perhaps more important is that Tenstorrent expects AMD's Zen 5 to run north of 4.0 GHz and have a TDP south of 250W, as opposed to Ascalon running at around 3.80 GHz at a TDP of approximately 200W.

If power consumption is taken into account, it looks like processors based on Tenstorrent's Ascalon microarchitecture (such as the company's own Aegis chiplet) will indeed offer leading integer performance-per-watt, which is particularly important for the types of applications the processor is designed to satisfy. 

Just two weeks after retiring from Intel, Raja Koduri joined the board of directors of Tenstorrent, an AI and high-performance RISC-V CPU company that intends to challenge the blue giant in the coming years, as noticed by @SquashBionic. A renowned developer of GPUs for graphics and compute, Raja Koduri will be joining his former colleagues from AMD, ATI, and Intel.

Tenstorrent is developing datacenter solutions comprising of RISC-V-based AI/ML accelerators as well as high-performance RISC-V general purpose processors. The company was established in 2016 by Ljubisa Bajic, and it is presently led by Jim Keller, a renowned CPU architect who has spearheaded the creation of revolutionary processor architectures at companies such as Apple, AMD, and DEC. (We recently outlined Tenstorrent's short and mid-term plans.)

Truth to be told, a position in the board of directors does not imply that Raja will be able to influence development of CPUs or AI accelerators. Yet, he will have his word when setting Tenstorrent's strategic goals and strategic roadmap, something that is particularly important. Being developer of AI accelerators and high-performance RISC-V CPUs, Tenstorrent is essentially travelling in uncharted watersm since AI-related technologies are changing rapidly, whereas the open-source RISC-V microarchitecture is poised to change fast in general. 

To a large degree, development of AI and RISC-V hardware these days resembles development of GPUs back in the 1990's and 2000's when companies tried a variety of approaches and usually changed microarchitectures radically once in a year or two. That's something that we barely see these days in the fields of x86 and Arm CPUs as well as GPUs from companies like Arm, AMD, Nvidia, and Intel.

Koduri has already worked both with Jim Keller and Ljubisa Bajic while at AMD (with both), Intel (Keller), and Apple (Keller). Most recently Koduri and Keller worked together at Intel developing high-performance compute GPUs and CPUs, respectively. While the two have very different backgrounds and fields of expertise, both have plenty of experience in building high-performance hardware, something that Tenstorrent can certainly take advantage of. 

Having assembled a team of top-notch AI and CPU engineers, start-up Tenstorrent, helmed by industry icon Jim Keller, has huge plans that involve both general-purpose processors and artificial intelligence accelerators.

At present, the company is working on the industry's first 8-wide decoding RISC-V core capable of addressing both client and HPC workloads that will be first used for a 128-core high-performance CPU aimed at data centers. The company also has a roadmap of several more generations of processors, which we'll cover below. 

Why RISC-V?

We recently spoke with Wei-Han Lien, the chief CPU architect at Tenstorrent, about the company's vision and roadmap. Lien has an impressive background, with stints at NexGen, AMD, PA-Semi, Apple, and is perhaps best known for for his work on Apple's A6, A7 (world's first 64-bit Arm SoC), and M1 CPU microarchitectures and implementation. 

With many world-class engineers with vast experience in x86 and Arm designs, one may ask why Tenstorrent decided to develop RISC-V CPUs considering that the data center software stack for this instruction set architecture (ISA) is not as comprehensive as that for x86 and Arm. The answer Tenstorrent gave us is simple: x86 is controlled by AMD and Intel, and Arm is governed by Arm Holding, which limits the pace of innovation. 

"Only two companies in the world can do x86 CPUs," said Wei-Han Lien. "Due to the x86 license restriction, innovation is basically controlled by one or two companies. When companies get really big, they become bureaucratic hierarchically, and the pace of innovation [slows]. […] Arm is kind of the same thing. They claim they are like a RISC-V company, but if you look at their specification, [it] becomes so complicated. It is also actually kind of dominated by one architect. […] Arm kind of dictating all the possible scenario even to architecture [license] partners." 

By contrast, RISC-V is developing quickly. Since it is an open-source ISA, it is easier and faster to innovate with it, particularly when it comes to emerging and rapidly developing AI solutions, according to Tenstorrent. 

"I was looking for a companion processor solution for [Tenstorrent's] AI solution, and then we wanted BF16 data type, and then we went to Arm and said, 'Hey, can you support us?' They said 'no,' it requires like maybe two years internal discussion and discussion with partners and whatever," explained Lien. "But we talked to SiFive; they just put it in there. So, there is no restriction, they built it for us, and it is freedom." 

On the one hand, Arm Holding's approach ensures high quality of the standard as well as a comprehensive software stack, but it also means that the pace of ISA innovation gets slower, which might be a problem for emerging applications like AI processors that are meant to be developed quickly. 

One Microarchitecture, Five CPU IPs in One Year

Since Tenstorrent is looking forward and addressing AI applications at large, it needs not only different system-on-chips or system-in-packages but also various CPU microarchitecture implementations and system-level architectures to hit diverse power and performance goals. This is exactly the department of Wei-Han Lien. 

A humble consumer electronics SoC and a mighty server processor have little in common but can share the same ISA and microarchitecture (albeit implemented differently). This is where Lien's team comes in. Tenstorrent says that the CPU crew has developed an out-of-order RISC-V microarchitecture and implemented it in five different ways to address a variety of applications. 

Tenstorrent now has five different RISC-V CPU core IPs — with two-wide, three-wide, four-wide, six-wide, and eight-wide decoding — to use in its own processors or license to interested parties. For those potential customers who need a very basic CPU, the company can offer small cores with two-wide execution, but for those who need higher performance for edge, client PCs, and high-performance computing, it has six-wide Alastor and eight-wide Ascalon cores.  

Each out-of-order Ascalon (RV64ACDHFMV) core with eight-wide decode has six ALUs, two FPUs, and two 256-bit vector units, making it quite beefy. Considering that modern x86 designs use four-wide (Zen 4) or six-wide (Golden Cove) decoders, we are looking at a very capable core. 

Wei-Han Lien was one of the designers responsible for Apple's 'wide' CPU microarchitecture, which can execute up to eight instructions per clock. For example, Apple's A14 and M1 SoCs feature eight-wide high-performance Firestorm CPU cores, and two years after these were introduced, they are still among the most power-efficient designs in the industry. Lien is probably one of the industry's best specialists in 'wide' CPU microarchitecture, and, as far as we understand, the only processor designer who leads a team of engineers developing an eight-wide RISC-V high-performance CPU core. 

In addition to a variety of RISC-V general-purpose cores, Tenstorrent has its proprietary Tensix cores tailored for neural network inference and training. Each Tensix core comprises of five RISC cores, an array math unit for tensor operations, a SIMD unit for vector operations, 1MB or 2MB of SRAM, and fixed function hardware for accelerating network packet operations and compression/decompression. Tensix cores support a variety of data formats, including BF4, BF8, INT8, FP16, BF16, and even FP64.

Impressive Roadmap

Right now, Tenstorrent has two products: a machine learning processor called Grayskull that offers performance of around 315 INT8 TOPS that plugs into a PCIe Gen4 slot, as well as a networked Wormhole ML processor with approximately 350 INT8 TOPS of performance and uses a GDDR6 memory subsystem, a PCIe Gen4 x16 interface and has a 400GbE connection to other machines. 

Both devices require a host CPU and are available as add-in-boards as well as inside pre-built Tenstorrent servers. One 4U Nebula server containing 32 Wormhole ML cards offers around 12 INT8 POPS of performance at 6kW.

Later this year, the company plans to tape out its first standalone CPU+ML solution — Black Hole — that combines 24 SiFive X280 RISC-V cores and a multitude of 3rd Generation Tensix cores interconnected using two 2D torus networks running in opposite directions for machine learning workloads. The device will offer 1 INT8 POPS of compute throughput (approximately three times performance uplift compared to its predecessor), eight channels of GDDR6 memory, 1200 Gb/s Ethernet connectivity, and PCIe Gen5 lanes.  

In addition, the company is looking forward to adding a 2TB/s die-to-die interface for dual-chip solutions as well as for future use. This chip will be implemented on a 6nm-class fabrication process (we would expect it to be TSMC N6, but Tenstorrent has not confirmed this), yet at 600mm^2, it will be smaller than its predecessors produced on TSMC's 12nm-class node. One thing to remember is that Tenstorrent has not taped out its Blackhole yet, and its final feature set may differ from what the company discloses today. 

Next year the company will release its ultimate product: a multi-chiplet solution called Grendel that features its own Ascalon general-purpose cores featuring its own RISC-V microarchitecture with eight-wider decoding as well as a Tensix-based chiplet for ML workloads.  

Grendel is Tenstorrent's ultimate product set to be released next year: the multi-chiplet solution comprises an Aegis chiplet featuring high-performance Ascalon general-purpose cores and a chiplet or chiplets with Tensix cores for ML workloads. Depending on business requirements (and the financial capabilities of the company), Tenstorrent may implement an AI chiplet using a 3nm-class process technology and therefore take advantage of higher transistor density and Tensix core count, or it can keep using Black Hole chiplet for AI workloads (and even assign some work to 24 SiFive X280 cores, the company says). The chiplets will communicate with each other using the aforementioned 2TB/s interconnect.   

The Aegis chiplet with 128 general-purpose RISC-V eight-wide Ascalon cores organized in four 32-core clusters with inter-cluster coherency will be made using a 3nm-class process technology. In fact, the Aegis CPU chiplet will be among the first to use a 3nm-class fabrication process, something that will probably put the company on the map when it comes to high-performance CPU designs. 

Meanwhile, Grendel will use an LPDDR5 memory subsystem, PCIe, and Ethernet connectivity, so it will offer tangibly higher inference and training performance than existing solutions from the company. Speaking of Tensix cores, it is necessary to note that while all of Tenstorrent's AI cores are called Tensix, these cores actually evolve.

"The [Tensix] changes are evolutionary, but they are definitely there," explained Ljubisa Bajic, the company's founder. "[They add] new data formats, change ratios of FLOPS/SRAM capacity, SRAM bandwidth, network-on-chip bandwidth, new sparsity features, and features in general."

It is interesting to note that different Tenstorrent slides mention different memory subsystems for Black Hole and Grendel products. This is because the company is always looking at the most efficient memory technology and because it licenses DRAM controllers and physical interfaces (PHY). Therefore it has some flexibility when choosing the exact type of memory. In fact, Lien says that Tenstorrent is also developing its own memory controllers for future products, but for 2023 ~ 2024 solutions, it intends to use third-party MCs and PHYs. Meanwhile, for now, Tenstorrent does not plan to use any exotic memory, such as HBM, due to cost concerns. 

Business Model: Selling Solutions and Licensing IP

While Tenstorrent has five different CPU IPs (albeit based on the same microarchitecture), it only has AI/ML products in the pipeline (if fully configured servers are not taken into account) that use either SiFive's X280 or Tenstorrent's eight-wide Ascalon CPU cores. Thus, it is reasonable to ask why it needs so many CPU core implementations.  

The short answer to this question is that Tenstorrent has a unique business model that includes IP licensing (in RTL, hard macro, or even GDS forms), selling chiplets, selling add-in ML accelerator cards or ML solutions featuring CPU and ML chiplets, and selling fully configured servers containing these cards.  

Companies building their own SoCs can license RISC-V cores developed by Tenstorrent, and a broad portfolio of CPU IPs allows the company to compete for solutions requiring different levels of performance and power.  

Server vendors can build their machines withTenstorrent's Grayskull and Wormhole accelerator cards or Blackhole and Grendel ML processors. Meanwhile, those entities that do not want to build hardware can just buy pre-built Tenstorrent servers and deploy them. 

Such a business model looks somewhat controversial since, in many cases, Tenstorrent competes and will compete against its own customers. Yet, at the end of the day, Nvidia offers both add-in cards and pre-built servers based on these boards, and it doesn't look like companies like Dell or HPE are too worried about this because they offer solutions for specific customers, not just building blocks.

Summary

Tenstorrent jumped onto the radar about two years ago with the hire of Jim Keller. In two years, the company recruited a host of top engineers who are developing high-performance RISC-V cores for data center-grade AI/ML solutions as well as systems. Among the development team's achievements is the world's first eight-wide RISC-V general-purpose CPU core, as well as an appropriate system hardware architecture that can be used for AI as well as HPC applications. 

The company has a comprehensive roadmap that includes both high-performance RISC-V-based CPU chiplets as well as advanced AI accelerator chiplets, which promise to enable capable solutions for machine learning. Keeping in mind that AI and HPC are major megatrends poised for explosive growth, offering AI accelerators and high-performance CPU cores seems like a very flexible business model. 

Both AI and HPC markets are highly competitive, so getting some of the world's best engineers onboard is a must when you want to compete against the likes of established rivals (AMD, Intel, Nvidia) and emerging players (Cerebras, Graphcore). Like large chip developers, Tenstorrent has its own general-purpose CPU and AI/ML accelerator hardware, which is a unique advantage. Meanwhile, since the company uses RISC-V ISA, there are markets and workloads that it cannot address for now, at least as far as CPUs are concerned. 

Tenstorrent, a developer of heterogeneous processors for AI applications led by ex-AMD engineers Ljubisa Bajic and Jim Keller, has licensed a general-purpose CPU design developed by SiFive based on the RISC-V architecture. Licensing general-purpose cores and IP will speed up time-to-market of Tenstorrent's products. 

Tenstorrent develops high-performance AI training and inference system-on-chip architectures based on its own Tensix processor cores optimized for machine learning (ML). To run traditional workloads, Tenstorrent's SoCs will use SiFive's new general-purpose Intelligence X280 64-bit RISC-V-based cores with fully integrated 512-bit wide RISC-V Vector extension (RVV). SiFive is expected to disclose details about its vector processing solutions later this week at the Linley Spring Processor Conference.  

Along with SiFive's Intelligence X280 IP, Tenstorrent will also get a RISC-V software stack that will further speed up time-to-market for the AI SoC company.  

"SiFive Intelligence is a new initiative dedicated to bringing cutting-edge software and hardware technologies to those looking to innovate in the AI market," said Chris Lattner, President of Engineering and Product at SiFive. "Tenstorrent, with its team of industry leaders and an already impressive track record of silicon success, is an ideal partner for SiFive’s new products targeted at machine learning applications." 

The AI SoC designer has not disclosed all of the specifications of its upcoming processors just yet, but it is now obvious that the company wants its SoC architectures to be capable of general-purpose processing, vector processing (for AI inference and high-performance computing), and ML. Ultimately, Tenstorrent's architectures could be used for a wide variety of applications, including next-generation supercomputers that require both AI and HPC capabilities. 

Ljubisa Bajic and Jim Keller spent decades working on x86-based designs at AMD. Keller has also worked on multiple Arm-based designs while at Apple. The very fact that Tenstorrent chose to use SiFive-developed RISC-V CPU design is noteworthy by itself and is a testament to the new architecture.

"The Tenstorrent architecture addresses the growing demands that come with data-written code as part of Software 2.0," Keller said in a press release. "We are excited to partner with SiFive because of their ability to deliver CPUs and software for the modern RISC-V ecosystem."

Jim Keller, a famed chip architect with notable stints at Intel, AMD, and Tesla, has joined AI chip startup Tenstorrent as President, CTO, and board member. Keller previously worked with Tenstorrent founder Ljubisa Bajic at AMD and personally provided the first funding for the startup.     

Keller is known as a leader of transformational efforts during his storied past at several leading semiconductor firms, with his most recent position at Intel following the same trajectory. Keller joined Intel in 2018 and, in tandem with Raja Koduri and Murthy Renduchintala, was responsible for designing a new six pillar strategy meant to help the company recover from an extended period of roadmap delays. 

In a move seen by many as a sign that Intel's efforts to get back on track had stalled, Keller left Intel for personal reasons in June 2020 with plans to serve a six-month stint as a consultant to help the company transition to a new leadership team. Shortly thereafter, Intel announced that its 7nm process was delayed to such an extent that, for the first time, the company might have to turn to outside foundries to help produce its core logic devices. Keller's former boss, Murthy Renduchintala, was ousted a few days later.  

With Keller's six-month consulting agreement with Intel now apparently over, he has now joined the Tenstorrent team. The AI chip startup, based in Toronto, Canada, is designing new Grayskull inference processors for image recognition and voice processing tasks. Tenstorrent's approach melds high-performance inference processors with a new approach that uses AI to optimize low-level software functions, thus unlocking higher levels of speed and efficiency in an approach known as Software 2.0. 

“Software 2.0 is the largest opportunity for computing innovation in a long time. Victory requires a comprehensive re-thinking of compute and low level software,” Keller said. “Tenstorrent has made impressive progress, and with the most promising architecture out there, we are poised to become a next gen computing giant.”

Keller had previous jobs at Tesla, where he served as the Vice President of Autopilot and Low Voltage Hardware, helped architect the Zen microarchitecture while he was AMD's corporate vice president and chief cores architect, and is also famous for designing AMD's successful K7 (Athlon) and K8 architectures. AMD's canceled K12 uArch was another of Keller's more famous projects, and he has also worked for Apple, helping develop the A4 and A5 processors.

Keller is known for relatively short tenures at companies, typically leading turnaround efforts for roughly three years before moving on to other challenges. His time at Intel, where he served as Intel's senior vice president in the Technology, Systems Architecture and Client Group and general manager of the Silicon Engineering Group, was notably shorter at roughly two years. 

Intel announced today in its Q2 2020 earnings release that it has now delayed the rollout of its 7nm CPUs by six months relative to its previously-planned release date, undoubtedly resulting in wide-ranging delays to the company's roadmaps that could cause the company to lose ranks in our CPU Benchmark Hierarchy. Intel's press release also says that yields for its 7nm process are now twelve months behind the company's internal targets, meaning the company isn't currently on track to produce its 7nm process in an economically viable way. The company now says its 7nm CPUs will not debut on the market until late 2022 or early 2023. 

Here's the snippet from Intel's press release:

"The company's 7nm-based CPU product timing is shifting approximately six months relative to prior expectations. The primary driver is the yield of Intel's 7nm process, which based on recent data, is now trending approximately twelve months behind the company's internal target."

On the earnings call, Intel CEO Bob Swan said the company had identified a "defect mode" in its 7nm process that caused yield degradation issues. As a result, Intel has invested in "contingency plans," which Swan later defined as including using third-party foundries. The company will also use external third-party foundries for its forthcoming 7nm Ponte Vecchio GPUs, the company's first graphics chips. Ponte Vecchio comes as a chiplet-based design, and Swan clarified that production for some of the chiplets (tiles) will be outsourced to third parties. Swan noted the GPUs will come in late 2021 or early 2022, portending a delay beyond the original schedule for a 2021 launch in the exascale Aurora supercomputer. 

Intel's first 7nm server CPUs (Granite Rapids) will arrive in 2023, which is later than listed in earlier roadmaps that projected a launch in 2022. That timeline is concerning in the face of AMD's continued execution with its EPYC data center chips – AMD's roadmaps outline its 5nm Genoa processors coming to market before the end of 2022. Swan also said that Intel's first 7nm processors will debut for the client market, meaning chips targeting either desktop PCs or laptops. Intel's first 10nm desktop CPUs, Alder Lake, will arrive in the second half of 2021.

For perspective, rival foundry TSMC plans to be on the 3nm node in the same time frame as Intel's new schedule for 7nm. Intel clearly isn't pleased with its execution on the 7nm node, as an embattled Swan remarked that "And we feel pretty good about where we are, though we’re not happy. I’m not pleased with our 7nm process performance" at the end of the call after a bruising question and answer session with analysts. Swan also said "we have root-caused the [7nm] issue and believe there are no fundamental roadblocks," and that the company would provide further updates at an upcoming Architecture Day. 

Swan said the company had a built-in buffer in its roadmap to account for process node delays. That accomodation comes as a result of hard-learned lessons from the company's incessant 10nm delays. Intel says it will use its advanced packaging technologies, which allow it to mix and match components produced from external sources with its own chips, to help reconcile the six month delay to its 7nm processors with the year-long delay to its internal 7nm yield projections. Swan also noted that Intel could use third-party foundries for entire chip designs. In the past, Intel stated that it would also enable newer architectures to be portable to older nodes, so it's plausible that Intel could resort to back-porting some architectures as part of its contingency plan.

The 7nm delay reflects yet another setback as Intel still struggles to overcome the multi-year yield issues it has encountered with its 10nm process. Those delays have allowed its competitors, like AMD, to wrest the process node leadership position from Intel for the first time in the company's history. That's triggered a price war in the market as Intel fights a true x86 competitor with a better node, not to mention Amazon's new Graviton 2 ARM chips based on TSMC's 7nm node. Apple also recently announced that it is transitioning from Intel's chips to its own ARM-based 7nm silicon. The 7nm delay also exacerbates the recent news that rock star chip architect Jim Keller, who was a key part of a team effort to revitalize the company's roadmaps, has left the company. 

Intel CFO George Davis has previously indicated that the company's process tech would lag its its competitors until 7nm arrived in 2021, and that the company would regain the lead with its 5nm process at an undefined time:

"So we bring a lot of capability to the table for our customers, in addition to the CPU, and we feel like we're starting to see the acceleration on the process side that we have been talking about to get back to parity in the 7nm generation and regain leadership in the 5nm generation."

That plan to regain a competitive footing has now obviously shifted due to the 7nm delay. Intel had planned to speed the delivery of its 7nm node to offset the underperforming 10nm, which it said would not perform as well as other nodes. At the time, Davis noted that the company was trying to be clear with investors about the impacts of 10nm on the company's gross margins: "...but the fact is that I wanted to be clear what was happening during the 10nm generation. The fact is, it isn't going to be as strong a node as people would expect from 14nm or what they'll see in 7nm."

In regards to the 10nm node, Davis commented: "As we said back at our analyst day in May of 19: Look, this isn't just going to be the best node that Intel has ever had. It's going to be less productive than 14nm, less productive than 22nm, but we're excited about the improvements that we're seeing and we expect to start the 7nm period with a much better profile of performance over that starting at the end of 2021."

"Also, we were at a time when in order to regain process leadership we had to accelerate the overlap between 10nm, 7nm, and then 7nm and 5nm, so the cost that you're absorbing, starting in particular in 2021, you’ve got this intersection of the performance of 10nm, the investment in 7nm, and were also well into starting the investment in 5nm: All of those elements just combine to impact gross margin."

Today Intel said that it plans to increase its shipments of 10nm chips by 20% over its prior projections, so it appears the company's 10nm plans have shifted out of necessity. Intel's new plan centers on gaining another 'full node' of performance from its current 10nm node, meaning 10nm may have longer legs than the company expected when it announced last year that it would accelerate 7nm production. Intel pulled off a similar feat with its 14nm processors through a series of "+" revisions that added incremental performance improvements, so it does have a track record of successful inter-node improvements that could help it remain competitive until it can correct the issues with its 7nm process.

Intel has also traditionally used third-party fabs, currently to the tune of ~20% of its production, for low-margin, non-CPU products built on trailing-edge nodes. Intel's new plans to more aggressively leverage external fabs could result in it using other fabs for its core logic, like CPUs and GPUs, which the company hasn't done in the past. As Swan noted, that will present challenges in maintaining attractive ASPs for Intel's products, especially given the scale of its production needs. Ultimately, Intel could also face significantly reduced margins if it outsources significant portions of its fabrication of high-margin products, like CPUs, to third parties. Relying upon an outside vendor for leading-edge node production also incurs more risk in terms of supply assurance as Intel could be forced to compete with deep-pocketed rival semiconductor companies, like Apple, Nvidia and AMD, among others, for production capacity. 

Intel announced today that famed chip architect and lead silicon engineer Jim Keller will leave the company, effective today, due to unspecified personal reasons. Intel's press release clarifies that Keller will stay on with the company as a consultant for a six month period to help with the transition to a new leadership team. 

Keller is known as a leader of transformational efforts, and his depth of experience designing heterogeneous architectures played well to Intel's move towards multi-chip processor designs. In tandem with Raja Keller and Murthy Renduchintala, Keller was responsible for designing and aligning Intel's silicon portfolio under a new six pillar strategy that plays to the strengths of the company's IP.

Keller is known for relatively short stints at companies, typically leading turnaround efforts for roughly two years before moving on to other challenges. He served as Intel's senior vice president in the Technology, Systems Architecture and Client Group (TSCG) and general manager of the Silicon Engineering Group (SEG),

Given the long lead times in the chip design process and manufacturing, designs can take several years to come to market. That means that Keller's legacy will live on in a string of products that will mostly come to market long after his exit. For instance, his efforts on the Zen architecture didn't debut until he left the company.

Intel says that Keller will assist in a transition period over the next six months as it realigns its leadership under the following structure: 

·         Sundari Mitra, the former CEO and founder of NetSpeed Systems and the current leader of Intel’s Configurable Intellectual Property and Chassis Group, will lead a newly created IP Engineering Group focused on developing best-in-class IP.

·         Gene Scuteri, an accomplished engineering leader in the semiconductor industry, will head the Xeon and Networking Engineering Group.

·         Daaman Hejmadi will return to leading the Client Engineering Group focused on system-on-chip (SoC) execution and designing next-generation client, device and chipset products. Hejmadi has over two decades of experience leading teams delivering advanced SoCs both inside and outside of Intel.

·         Navid Shahriari, an experienced Intel leader, will continue to lead the Manufacturing and Product Engineering Group, which is focused on delivering comprehensive pre-production test suites and component debug capabilities to enable high-quality, high-volume manufacturing.

Jim Keller's hire was considered by many to be a coup for Intel, given that he has a long track record of success, including at Tesla, where he served as the Vice President of Autopilot and Low Voltage Hardware. Keller helped architect AMD's Zen microarchitecture while he was the company's corporate vice president and chief cores architect. Keller is also famous for designing AMD's successful K7 (Athlon) and K8 architectures. AMD's canceled K12 uArch was another of Keller's more famous projects, and he has also worked for Apple and helped develop the A4 and A5 processors.

AMD CEO Lisa Su and several of the company's famous past-and-current architects, like Jim Keller and Mike Clark, receive much of the public recognition for the company's amazing resurgence. But Mark Papermaster has served as the company's CTO and SVP/EVP of Technology and Engineering since 2011. He's been at the helm of developing AMD's technology throughout its David versus Goliath comeback against industry behemoth Intel, giving him incredible insight into the company's past, present, and future.  

We sat down with Papermaster during the Supercomputing 2019 conference to discuss the company's latest developments, including shortages of Ryzen processors, what we can expect from future CPUs, the company's new approach of enabling a mix of faster and slower cores, thoughts on SMT4 (quad-threaded processor cores), and the company's take on new Intel technologies, like Optane Persistent Memory DIMMs and OneAPI. 

Given AMD's success in the data center, we also discussed if EPYC Rome is impacting industry interest in competing x86 alternatives, like ARM. 

How Many Cores Are Enough?

It takes a lot of engineering wizardry to enable, but a big part of AMD's success stems from the rather simple concept of delivering more for less. For enthusiasts and data center architects alike, that starts with more cores. AMD's Zen has spurred a renaissance in core counts, boosting the available compute power we can cram into a single processor, forcing Intel to increase its core counts in kind. That incredible density started with the EPYC lineup that now stretches up to 64 cores, besting Intel's finest in the data center. 

On the consumer side, the Ryzen 9 3950X brings an almost-unbelievable boost to 16 cores on mainstream platforms, a tremendous improvement over the standard of four cores just a mere two years ago. As AMD moves forward to smaller processes, that means we could theoretically see another doubling in processor cores in the future. That makes a lot of sense for the data center, but begs the question of how many cores an average consumer can actually use. We asked Papermaster if it would make sense to move up to 32 cores for mainstream users: 

"I don’t see in the mainstream space any imminent barrier, and here's why: It's just a catch-up time for software to leverage the multi-core approach," Papermaster said. "But we're over that hurdle, now more and more applications can take advantage of multi-core and multi-threading.[...]"

"In the near term, I don’t see a saturation point for cores. You have to be very thoughtful when you add cores because you don’t want to add it before the application can take advantage of it. As long as you keep that balance, I think we'll continue to see that trend."

Are Processors Going to Get Slower as they Shrink?

Over the years, we've become accustomed to higher clock speeds with smaller nodes. However, we've reached the point where smaller nodes that enable more cores can also suffer reduced frequencies, like we've seen with Intel's Ice Lake family. As potent as TSMC's engineering team is, there's possibly a diminishing point of frequency returns, if not frequency declines, on the horizon as it moves to the smaller 5nm process. Papermaster is confident in AMD's ability to offset those challenges, though.

"We say [Moore's Law] is slowing because the frequency scaling opportunity at every node is either a very small percentage or nil going forward; it depends on the node when you look at the foundries. So there's limited opportunity, and that's where how you put the solution together matters more than ever," Papermaster said. 

"That's why we invented the Infinity Fabric," he explained, "to give us that flexibility as to how we put in CPU cores, and how many CPU cores, how many GPU cores, and how you can have a range of combinations of those engines along with other accelerators put together in a very efficient and seamless way. That is the era of a slowed Moore's Law. We’ve got to keep performance moving with every generation, but you can't rely on that frequency bump from every new semiconductor node."

AMD will also evolve its Infinity Fabric to keep up with higher-bandwidth interfaces, like DDR5 and PCIe 5.0. "In an era of slowed Moore's Law where you are getting less frequency gain, and certainly more expense at each technology node, you do have to scale the bandwidth as you add more engines going forward, and I think you're going to see an era of innovation of how in doing so you design to optimize the efficiency of those fabrics," Papermaster said.

Ryzen 3000 Shortages

AMD's boosted core counts come as a byproduct of TSMC's denser 7nm process, but the company initially suffered from nagging post-launch shortages of its high-end SKUs and had to delay its flagship desktop processor, leading to questions about AMD's ability to satiate demand. Those questions are exacerbated by reports that TSMC has extended lead times for its highly-sought-after 7nm process, and because AMD competes for wafer output with the likes of Apple and Nvidia. 

"We're getting great supply from our partner TSMC." Papermaster said, "Like any new product, there is a long lead time for semiconductor manufacturing, so you have to guess where the consumers are going to want their products. Lisa [Su] talked about the demand simply being higher than we anticipated for our higher-performance and higher-ASP [products], the Ryzen 3900 series. We've now had time to adjust and get the orders in to accommodate that demand. That's just a natural process; in a way, it’s a good problem to have. It means the demand was even higher than we originally thought."

As a natural result of semiconductor fabrication, each wafer has dies with different capabilities, which are then binned (sorted) according to their capabilities. AMD's faster processors require the cream-of-the-crop dies, and the company simply wasn't receiving enough of those premium dies. We asked if getting more high-end die is simply a function of ordering more wafers:

"We work closely with the foundry to get the right mix on any chip. You have various speed ranges that come out of the manufacturing line. You have to decide in advance what you think is the distribution of chips and work with the foundry partner to make sure you call the demand right," Papermaster elaborated.

Unlocking Faster Performance With New Boost Technology

The looming frequency scaling challenges can be addressed through a range of techniques, but AMD already has a new innovative technology that helps wring out the utmost performance from every core. 

Just like the capabilities of each die harvested from a wafer will vary, every core on a chip has differing capabilities. Like all processors, AMD's chips come with a mix of faster and slower cores, but we discovered that the company uses an innovative technique to extract higher frequencies from the faster cores, which stands in contrast to the standard approach in the PC industry of adjusting to the lowest common denominator. We asked Papermaster about the rationale behind the new technology:

"There's typically a fairly small variation of the performance across cores," Papermaster responded, "but what we enable on our chips is the opportunity to boost and maximize the performance of any given chip. We're enabling these boost technologies to the advantage of our end customers, to make sure that we are optimizing power, yet delivering the best performance."

Does SMT4 Make Sense?

There have been persistent rumors and reports in the media that AMD will adopt SMT4, which involves enabling each core of the processor to run four threads as opposed to the standard dual-thread implementations. Knowing that AMD won't reveal direct information about its forthcoming chips, we asked Papermaster about his opinion of the technology coming to the desktop:

"We've made no announcements on SMT4 at this time," Papermaster responded. "In general, you have to look at simultaneous multi-threading (SMT): There are applications that can benefit from it, and there are applications that can't. Just look at the PC space today, many people actually don’t enable SMT, many people do. SMT4, clearly there are some workloads that benefit from it, but there are many others that it wouldn’t even be deployed. It's been around in the industry for a while, so it's not a new technology concept at all. It's been deployed in servers; certain server vendors have had this for some time, really it's just a matter of when certain workloads can take advantage of it."

Papermaster's Thoughts of Persistent Storage (Optane) on the Memory Interface

Intel lists Optane Memory among its technological advantages over its peers, but like all processors that use standardized interfaces, AMD's EPYC also supports Optane when used as a storage device.

However, Intel also offers its Optane Persistent Memory DIMMs that are used as memory after dropping them into memory slots. Intel has a proprietary interface that enables the functionality, so AMD's EPYC platforms don’t support the feature. We asked Papermaster about AMD's take on persistent memories, and if we could see similar DIMM support from AMD in the future using Optane memory from its ally Micron.

"Eventually, the way the industry is heading is to enable storage class memory to be off the I/O bus." Papermaster said, "That's where they really want to be because that's where it is more straightforward from the software stack to leverage these dense storage class memories (SCM). So, you're seeing an evolution there, you're seeing the industry working on SCM solutions. There's been a number of industry standards to align on that interface, and now CXL has taken off. We've joined it along with many other members of the industry, and so you're starting to see convergence on that interface for these types of devices. It's going to take a little time because they're going to have to get out there, and then the applications have to be tuned and qualified to run and really leverage this."

We dove in a bit deeper, asking if Papermaster thinks there is more interest in the industry for standards-based I/O interfaces (like NVMe) as opposed to using the memory bus, to which he responded, "I believe so. I think that's where you're really going to see SCM become pervasive in the industry."

Would AMD Adopt Intel's OneAPI?

Intel's OneAPI is a collection of libraries that enable programmers to write code that is portable between different architectures, thus allowing programs that run on CPUs to seamlessly transfer over to other architectures, like GPUs, FPGAs, and AI accelerators. 

Interestingly, Intel recently announced that OneAPI will work with other vendors' hardware and that they are free to adopt the technology. We asked Papermaster if AMD would consider adopting OneAPI.

"We've already been on a heterogeneous software stack strategy and implementation for some time. We already released the Radeon Open Compute stack at a production level two years ago, so we have a path that is open and allows a very straightforward path to compiling workloads that are heterogeneous across our CPUs, our GPUs, and also interface with standards like OpenMP so you can then create high performance compute cluster capabilities." 

"This is a path that we've already been on in AMD for some time, and we're glad to see the endorsement from our competitor that they see it the same way."

Is EPYC Sucking the Oxygen out of ARM?

As we've seen with Intel's recent shortages, a monopoly-like hold on the processor market isn’t good for pricing or sourcing stability. As such, the industry has long pined for alternative processors, but in reality, it really isn't searching for an x86 alternative. Rather, the industry wants an Intel alternative.

ARM and other architectures require expensive and time-consuming re-coding and validation of existing software, while AMD's EPYC Rome is plug-and-play with the x86 instruction set, thus reducing the additional expenses associated with moving to a different architecture.

Many have opined that EPYC Rome is sucking the oxygen out of industry interest in other architectures, like ARM, due to those advantages. We asked Papermaster for his take:

"x86 is the dominant architecture for computing today, and there's just such a massive amount of software code for x86, and such a massive toolchain that makes it easy for developers on this platform. So, we just see such a long and healthy opportunity, and frankly for AMD, with the strength of our roadmap, a tremendous share gain opportunity for us," Papermaster said.

"We're very focused on our strategy to ensure that every generation we have brings tremendous value to our customers, and in doing so, I do think it makes it harder for new architectures to enter. You'll see specialized applications that are less architecture-dependent. Because they’re specialized, they don’t care as much about that broad x86 base. So I do think, as you already see today, a small market for specialized architectures that'll continue, but we couldn’t be more excited about the future prospects for x86, and for our AMD roadmap in that market."

AMD to Support BFloat 16

The industry has broadly adopted the Google-inspired BFloat16, a new class of numerical format that boosts performance for certain AI workloads. The industry is inexorably shifting to AI-driven architectures, and large hyperscalers have signaled that they require hardware that supports the new format. Papermaster revealed that AMD would support BFloat16 in future revisions of its hardware.

"We're always looking at where the workloads are going. BFloat 16 is an important approximation for machine learning workloads, and we will definitely provide support for that going forward in our roadmap, where it is needed."

On a Personal Note...

In a turnaround of fortunes that hardly anyone could have predicted several years ago, AMD has taken the process lead from Intel and has an innovative architecture that is pressuring its competitor in every segment the company competes in. We asked Papermaster if he personally thought the plan would be this successful when it was laid out four years ago. 

"We set out a roadmap that would bring AMD back to high performance and keep us there. It is independent of our competitors roadmaps and semiconductor node execution on 10nm. And we'll continue to drive our roadmap in that way. We called a play, we've been executing as we called it, and that's what you're going to see at AMD, just tremendous focus on execution. If we do that, then it is less about focusing on our competition, and about being the very best we can be with every single generation."

Papermaster has been at the helm of developing nearly all of AMD's newest technologies, so we asked what makes him the proudest about the turnaround: 

"It's the team at AMD. The AMD commitment to win is unsurpassed. We're a smaller player in the industry, and the company as a whole just punches above its weight class, if you were to make a boxing analogy. It's so exciting to be a part of that team and to see that personal dedication, that willingness to really listen to customers, understand what problems they want solved, and then go to the drawing boards and innovate and really surprise the industry."

"And then the other piece I'm proud of is that focus on that execution. It’s the ability to be a street-fighter, and then focus and hunker down and execute and deliver what we promised."

Forbes today reported that Intel had hired Devon Nekechuk from AMD. He lastly served as Senior Manager of Product Management since 2017, where he was responsible for managing Radeon GPUs throughout their lifecycle. This included everything from product definition with strategy teams, product development with engineering teams, launches with marketing teams and demand generation with sales teams. According to his LinkedIn profile, Nekechuk joined Intel in February.

Nekechuk is the latest in Intel's vast graphics-oriented hiring spree that was kickstarted in late 2017 with the establishment of the Core and Visual Computing Group under Raja Koduri, who left AMD after a sabbatical as head of the Radeon Technologies Group (RTG). This was followed by Jim Keller, who came from Tesla (which detailed its self-driving chip last week), and Chris Hook from AMD’s marketing team. 

Other notable people that Intel hired to Raja Koduri’s graphics group include Tom Forsyth, former Larrabee architect, Mark Hirsch from AMD, and few other technical people that have been previously reported. A month ago, Intel hired Tom Peterson from NVIDIA, where he had served as director of technical marketing, and most recently, earlier this month Intel snatched Heather Lennon from AMD, where she was the manager of RTG’s marketing and communications.

Even before launching its first discrete graphics card (possibly as early as the middle of next year) based on the Xe architecture, Intel has already assembled a whole army of industry veterans and has also started up its Odyssey program, a community-focused graphics marketing program. 

In the early days of Intel’s discrete graphics announcement, people would often point to Intel’s failed Larrabee attempt last decade, but these hires clearly signal that Intel is in the business of becoming a strong and serious competitor. However, Intel has yet to detail any specifications or other technical details of its discrete graphics line-up that will feature both consumer and data center products.

Intel Architecture Day

Intel's new heads of silicon development, led by Raja Koduri, the Senior Vice President of Core and Visual Computing, and Jim Keller, the Senior Vice President of Silicon Engineering, hosted its Architecture Day here in Santa Clara to outline the company's broad new vision for the future. Dr. Murthy Renduchintala, Intel's chief engineering officer and group president of the Technology, Systems Architecture & Client Group (TSCG) also presented at the event, which was held in the home of Intel co-founder Robert Noyce.

Highlights included the unveiling of the company's new Sunny Cove CPU microarchitecture, its new Gen11 integrated graphics, 'Foveros' 3D chip stacking technology, a teaser of the company's new Xe line of discrete graphics cards, and a new "One API" software designed to simplify programming across Intel's entire product stack. We also caught a glimpse of the first 10nm Ice Lake processor for the data center.

Intel has amassed a treasure trove of new technologies over the last several years as it has diversified into new areas like AI, autonomous driving, 5G, FPGAs, and IoT, and other areas. It's even added GPUs to the list. Intel's process technology touches every segment of all that tech, as well as the chips that power them, but its delayed 10nm process has slowed the company's progress.

To help get back on track, Intel brought in Raja Koduri and Jim Keller to outline a new cohesive vision that spans all facets of its operations. Together with the company's leadership, the pair identified six key building blocks that the company will focus on over the coming years. Those pillars include process technology, architectures, memory, interconnects, security, and software. The company hopes that focusing on these key areas will accelerate its pace of innovation and help it regain its competitive footing.

The event was a wide-ranging affair with an almost overwhelming amount of information and insight into the company's plans for the future, but a few new key technologies stood out as particularly promising. Let's take a look at some of the most interesting new technologies Intel is working on.

3D Chip Stacking With Foveros

Foveros (Greek for "awesome") is a new 3D packaging technology that Intel plans to use to build new processors stacked atop one another. The concept behind 3D chip stacking is a well-traveled topic that has been under development for decades, but the industry hasn't been able to circumvent the power and thermal challenges, not to mention poor yields, well enough to bring the technology to high-volume manufacturing.

Intel says it built Foveros upon the lessons it learned with its innovative EMIB (Embedded Multi-Die Interconnect Bridge) technology, which is a complicated name for a technique that provides high-speed communication between several chips. That technique allowed the company to connect multiple dies together with a high-speed pathway that provides nearly the same performance as a single large processor. Now Intel has expanded on the concept to allow for stacking die atop each other, thus improving density.

The key idea behind chip stacking is to mix and match different types of dies, such as CPUs, GPUs, and AI processors, to build custom SOCs (System-On-Chip). It also allows Intel to combine several different components with different processes onto the same package. That lets the company use larger nodes for the harder-to-shrink or purpose-built components. That's a key advantage as shrinking chips becomes more difficult.

Intel had a fully functioning Foveros chip on display at the event, that it built for an unnamed customer. The package consists of a 10nm CPU and an I/O chip. The two chips mate with TSVs (Through Silicon Via) that connect the die through vertical electrical connections in the center of the die. The channels then mate with microbumps on an underlying package. Intel also added a memory chip to the top of the stack using conventional a PoP (Package on Package) implementation. The company envisions even more complex implementations in the future that include radios, sensors, photonics, and memory chiplets.

The current design consists of two dies. The lower die houses all of the typical southbridge features, like I/O connections, and is fabbed on the 22FFL process. The upper die is a 10nm CPU that features one large compute core and four smaller 'efficiency' cores, similar to an ARM big.LITTLE processor. Intel calls this a "hybrid x86 architecture," and it could denote a fundamental shift in the company's strategy. The company later confirmed that it is working on building a new line of products based on the new hybrid x86 architecture, which could be the company's response to the Qualcomm Snapdragon processors that power Always Connected laptops. Intel representatives did confirm the first product draws less than 7 watts (2mW standby) and is destined for fanless devices but wouldn't elaborate further.

The package measures 12x12x1mm, but Intel isn't disclosing the measurements of the dies. Stacking small dies should be relatively simple compared to stacking larger dies, but Intel seems confident in its ability to bring the technology to larger processors. Ravishankar Kuppuswamy, Vice President & General Manager of Intel's Programmable Solutions Group, announced that the company is already developing a new FPGA using the Foveros technology. Kuppuswamy claims Foveros technology will enable up to two orders of magnitude performance improvement over the Falcon Mesa FPGAs.

Intel Xe Discrete Graphics and Gen11 Graphics

Intel also unveiled its new Gen11 integrated graphics engine and presented a demo of Tekken 4 playing amazingly well using the new graphics architecture. The demo ran on a 10nm processor, marking the company's first public demo of a graphics engine running on a 10nm processor.

Intel cautioned that the diagrams it used for the presentation aren't entirely to scale, but they do give us a close look under the hood of the new graphics engine. The Gen11 engineering team focused heavily on creating a dramatic performance improvement over its previous-gen graphics engine, stating that the goal was to cram 1 teraflop of 32-bit and 2 teraflops of 16-bit floating point performance into a low power envelope.

Intel employed the familiar modular arrangement with sub-slices that house eight execution units (EU). Intel brought the design up to eight sub-slices, or 64 execution units (EUs). That's a big improvement from Gen9's 24 EUs. The revamped engine also processes two pixels per clock.

The new design features support for tile-based rendering in addition to immediate mode rendering, which helps to reduce memory demands during some rendering workloads. The engineers also improved the memory subsystem by quadrupling the L3 cache to 3MB and separated the shared local memory to promote parallelism. The new design also has enhanced memory compression algorithms.

Other improvements include a new HEVC Quick Sync Video engine that provides up to a 30% bitrate reduction over Gen9 (at the same or better visual quality), support for multiple 4K and 8K video streams within a lower power envelope, and support for Adaptive Sync technology. 

Intel Xe Graphics Technology, Now Including a Discrete GPU

Intel shocked the enthusiast community earlier this year when it announced that it would enter the discrete graphics market. Intel is quick to remind us that it "lights up quintillions of pixels across the planet every day," which is a true statement based on the fact that, courtesy of its integrated graphics chips in its CPUs, Intel is the world's largest GPU producer. Now the company is bringing that experience to the discrete GPU market, and yes, that means it is bringing gaming-focused GPUs to market.

Translating that experience in integrated graphics to its new lineup of discrete GPUs isn't going to be an easy task: Their last successful entry into the GPU space occurred 25 years ago. But Intel has an IP war chest (at one point it owned more graphics patents than the other vendors combined) and has been on a full-court press recruiting the right talent for the task.

Intel presented a slide outlining its new Xe architecture that will come after the Gen11 graphics engine. Intel says the next generation of its graphics architecture will denote a transition from the "Gen" naming convention and will scale from integrated on-chip graphics up to discrete GPUs that will span the mid-range, enthusiast, and data center markets. That means it will scale from teraflops of performance integrated into a standard processor up to petaflops of performance with discrete cards.

This announcement certainly hints that both the integrated graphics and discrete cards will share the same underlying architecture, but Intel wouldn't answer further questions. Intel is also on track to deliver on its previously-announced timeline, saying the Xe graphics cards will debut in 2020.

CPU Core Roadmap, Sunny Cove Microarchitecture, 10nm Ice Lake

Intel also took the wraps off its new CPU core roadmap and "Sunny Cove" microarchitecture at the event. The company's dominance in the chip market has long been predicated on process and microarchitecture leadership, but Intel's approach to designing new processor cores has been inextricably tied to its onward march to smaller process nodes. That means that its new CPU core designs (microarchitectures) have traditionally required a move to new, smaller manufacturing processes.

That approach became a liability as Intel encountered massive delays with its 10nm process. Instead of bringing out new core designs, the company was mired on the 14nm process for four years as it constantly refined the process through a cadence of "+" iterations. Each new iteration of the 14nm process found the company offering higher frequencies, and thus more performance, as it marched from 4.2 GHz up to 5.1 GHz. These improvements delivered up to 70% more performance since 14nm's debut in 2014, but the lack of a new microarchitecture, which typically improves the processors' instruction per clock (IPC) throughput, slowed its progress.

After learning a hard lesson exacerbated by the resurgent AMD nipping at its heels, Intel tells us that the company will now design new microarchitectures to be portable between nodes. That will allow the company to move forward even if it encounters roadblocks on its path to smaller transistors.

The Sunny Cove microarchitecture is the first new design that can be used on multiple nodes, and even though Intel has stated the new core will debut on the 10nm node, it hasn't verified that it will come with the Ice Lake chips. In line with its new design ethos, Intel also tells us that it will select different nodes for different products based on the needs of the segment. That's similar to the approach taken by third-party fabs like TSMC and Global Foundries, and it means Intel could choose to use Sunny Cove with 14nm processors as well.

Intel's CPU Core Roadmap

Intel has typically used the same naming convention for its microarchitectures as it does for its processors. Hence, Skylake processors came with the Skylake architecture, and Kaby Lake processors came packing the Kaby Lake architecture. That old paradigm changes now that Intel has decoupled its architectures from the end products, so the company debuted a new roadmap specifically for CPU cores.

Intel presented its new roadmap for both its Core and Atom lineups. As usual, the Core series addresses the company's bread-and-butter high-performance chips, while the Atom chips serve the low power segment.

Intel's Sunny Cove will debut in 2019, bringing with it higher performance in single-threaded applications, a new instruction set architecture (ISA), and a design geared for scalability. Willow Cove will follow with an improved cache hierarchy, security features, and transistor optimizations. The Golden Cove microarchitecture will debut in 2021 with a focus on yet more single-threaded performance, AI performance, networking improvements, and new security features. Atom will receive a slower cadence of improvements, with Tremont debuting in 2019 and Gracemont in 2021. 'Next' Mont will arrive before 2023.

Intel plans for general performance improvements through three key design tenets of going deeper, wider, and smarter, but it is also improving what it calls 'special purpose' use cases, like AI, cryptography, and compression/decompression workloads.

A Refresh On Skylake (Refresh)

Intel presented us a quick refresh on its Skylake architecture that underpins its Skylake, Kaby Lake, Coffee Lake, and Cascade Lake processors. The design (left) processes operations through two reservation stations (RS). It can process seven operations simultaneously and propel them to the integer (INT), vector (VEC), store data, and address generation units (AGU).

Deeper

The new Sunny Cove design features improvements in every level of the pipeline. Key improvements to the front end include larger reorder, load, and store buffers, along with larger reservation stations. This allows the processor to look deeper into the set of incoming instructions to find operations that are independent of each other but can run simultaneously. The operations are then executed in parallel to improve IPC.

Intel increased the L1 data cache from 32KB, the same capacity it has used in its chips for a decade, to 42KB. The L2 cache is also larger, but the capacity is dependent upon each specific type of product, such as chips designed for either the desktop or server market. Intel also expanded the micro-op cache (UOP) and the second-level translation lookaside buffer (TLB).

Wider

A key facet of improving performance is to increase parallelism. That starts with the deeper buffer and reservation stations we covered above, but it also requires more execution units to process the operations.

Intel moved from a four-wide allocation to five-wide to allow the in-order portion of the pipeline (front end) to feed the out-of-order (back end) portion faster. Intel also increased the number of execution units to handle ten operations per cycle (up from eight with Skylake). The Store Data unit can now process two store data operations for every cycle (up from one). The address generation units (AGU) can now also handle two loads and two stores every cycle. These improvements are necessary to match the increased bandwidth from the larger L1 data cache, which now does two reads and two writes every cycle. Intel also tweaked the design of the sub-blocks in the execution units to enable data shuffles within the registers.

Smarter

Intel reiterated that just increasing the size of the buffers and the number of execution units requires smart algorithmic management to strike a balance between performance and the power budget. That revolves around improving branch prediction accuracy and reducing latency under load conditions. The net effect is a 'significant' increase in IPC. Intel didn't provide specific measurements. but promises to share more information as products come to market. 

Specialization

Intel also designed Sunny Cove to address specific use cases, like cryptography, AI, and compression/decompression workloads. The company accomplished these goals by creating new instructions and features to improve performance.

Exploding Memory Capacity

Intel also improved the amount of memory the processor can address, which is a key consideration given its goal of boosting memory capacity with Optane DC Persistent Memory DIMMs. The speedy Optane memory modules provide up to 512GB of memory-addressable storage per DIMM, meaning memory capacity is set to explode as more data centers transition to the technology.

Intel's Sunny Cove moves to a five-level paging structure (up from a four-level structure). That increases the virtual address space up to 57 bits and the physical address space up to 52 bits, meaning it supports up to 4 petabytes of memory. That's up from 64 TB of addressing capability with Skylake.

Intel's New Course with OneAPI

Intel's Sunny Cove is an innovative design that looks promising, but as with all designs, we won't know the true benefits until we see the silicon in our labs. Intel's new vision to decouple its CPU core designs from its process improvements is the real advance that will help the company remain competitive in the future. Intel surely can't afford another period of stagnation like we've seen during its struggles with the 10nm process.

Third-party fabs have proven to be Intel's greatest competitor. TSMC has taken the process lead with its pending 7nm node, and as a result, new 7nm chips will soon flow from the stalwarts of the semiconductor space, like AMD, Apple, Qualcomm, and Nvidia. These companies work together with TSMC to bring their new designs to market, meaning that Intel isn't just competing with one company -- it faces the combined might of several of the behemoths in the chip market.

Intel does have a plan to outmaneuver its rivals by leveraging its wide-ranging product stack, but it surprisingly revolves around software. Intel is working on its new "One API" software, which is designed to simplify programming across its GPU, CPU, FPGA, and AI accelerators. The software goes by the tagline of "no transistor left behind," and given its goals, that's an accurate statement. The new software provides unified libraries that will allow for applications to move seamlessly between Intel's different types of compute. If successful, this could be a key differentiator that other firms will not be able to match with as many forms of compute.

10nm Ice Lake

The company does have its own plans for its resurgence on the process front, though, as evidenced by the brief display of its 10nm Ice Lake data center chip. The company didn't share any details about the new processor.

Questions And Answers

Intel has been notoriously silent on its roadmap and future plans, but its Architecture Day event seems to signal a new level of openness and disclosure from the company. Several executives from Intel's executive management team were present for the event and were willing to answer our questions openly and frankly. The company also plans to hold future events to drill down more on these topics as it comes closer to delivering products to market. 

Intel held roundtable discussions at the event, where Raja Koduri (R) and Jim Keller (J), and Dr. Murthy Renduchintala (M) fielded questions during the last session. Here are some of the questions and answers:

Q: A lot of the CPU microarchitecture at Intel has been hamstrung by delays on process node technology. What went wrong, and what steps have been made to make sure it doesn't happen again?

R/J: Our products will be decoupled from our transistor capability. We have incredible IP at Intel, but it was all sitting in the 10nm process node. If we had had it on 14nm then we would have better performance on 14nm. We have a new method inside the company to decouple IP from the process technology. You must remember that customers buy the product, not a transistor family. It’s the same transformation AMD had to go through to change the design methodology when they were struggling. At Apple it was called the ‘bus’ method.

M: This is a function of how we as a company used to think about process node technologies. It was a frame tick (limiting factor) for how the company moved forward. We've learned a lot about how this worked with 14nm. We now have to make sure that our IP is not node-locked. The ability to have portability of IP across multiple nodes is great for contingency planning. We will continue to take aggressive risks in our designs, but we also will have contingency. We need to have as much of a seamless roadmap as possible in case those contingencies are needed, and need to make sure they are executed on ASAP if needed to keep the customer expectations in line. You will see future node technologies, such as 10/7, have much more overlap than before to keep the designs fluid. Our product portfolio on 14nm could have been much better if our product designs were not node-locked to 10nm.

R: In the future there will be no transistor left behind, no customer left behind, and no IP left behind.

Q: Will we ever see a 10nm monolithic desktop CPU at the high end?

R: Yes.

Q: How is 10nm? Has it changed?

R: It is changing, but it hasn't changed. There are a lot of lessons learned in how Intel approached it to begin with. We are established a much better model between manufacturing and design. We want good abstractions in product and process node going forward. When everything was going well, this issue didn't manifest and so wasn't an issue. There's complexity here when something bad happens on process, so the whole pipeline clogs up -- the rest of the world solves this with abstraction. We need to make sure it won't happen again, and we have a desire to build resilience in the roadmap.

Q: Are there plans for mixed SoCs, combining CPU / GPU / AI / FPGA ?

R: In our roadmap there will be scalable vector/matrix combinations. What our customers want are very scalable solutions. Customers want similar programming models regardless of the silicon.

Q: What has been the effect of hiring Raja/Jim and bringing outsiders to Intel?

M: Intel is very innovative. We want to add to that chemistry and make sure we bring in people who understand Intel but also bring in good ideas. It's about respecting the rest of the market and make sure Intel is competitive. It's balancing the center of internal debates by making sure we are challenging internal beliefs and the status quo by bringing in people who have done this sort of thing before. It shows to Intel's strengths in its ability to absorb interesting ideas from the outside. We went for the very best on the outside because that was what required to join with the very best on inside.

Q: What is Intel’s current approach to 5G, given the topics discussed today?

M: We think about 5G from the datacenter to the network to the edge and to the device. We at Intel believe the transition to 5G and its implications on the network, in terms of accelerating data and catalyzing a software-defined network where bespoke silicon gets replaced by containers, is as transformative as the jump from analogue to digital. It will accelerate the "cloudification" of the network. The edge is important, especially to minimize latency for new services. Sub-millisecond latency for these services is critical. The over-the-air interface is important too. The intelligent cloud domain is going to be the flywheel about how fast the industry evolves. We mentioned in November that our XMM 5G modem will be in the hands of partners in the second half of 2019 with products in early 2020. It is a multi-mode 5G LTE architecture from day one, supporting all 3 mmWave bands, and sub-6 GHz frequencies.

Q: As Thunderbolt 3 requires additional chips, how do you see future OEM adoption?

M: Integrated Type-C Thunderbolt 3 is the first generation. We will refine it in the future - that's the natural genealogy of the technology. We constantly think about how much we integrate into the chip and how much we leave on the board.

R: This is a big IP challenge, not only for TB3, but for other IP. Integrated PHYs are important. For example, by dis-aggregating the transceiver in our FPGA lineup, it has allowed us to focus on that decoupled IP a lot.

Q: In the demo of FOVEROS, the chip combined both big x86 cores built on the Core microarchitecture and the small x86 cores built on the Atom microarchitecture. Can we look forward to a future where the big and little cores have the same ISA?

R: We are working on that. Do they have to have the same ISA? Ronak and the team are looking at that. However I think our goal here is to keep the software as simple as possible for developers and customers. It's a challenge that our architects have taken up to ensure products like this enter the market smoothly. We’ll also have a packaging discussion next year on products like this. The chip you see today, while it was designed primarily for a particular customer to begin with, it’s not a custom product, and in that sense will be available to other OEMs.

M: We've made the first step on a journey. That first step is a leap, and the next step is incremental. As we've said about One API strategy – if we homogenize the API then it'll go into all our CPUs. Foveros is also a new part/product that shows that we had a gap in our portfolio – it has helped us create technologies to solve an issue and we expect to expand on this in the future with new IP.

Q: Are you having fun with Foveros?

J: Because Raja deals in GPUs, he’s having fun with high bandwidth communications between compute elements. It's a new technology and we're having some experimentation with it. What is frustrating is that as an industry we hit a limit for current flux density a year before stacking technology became viable, so for high performance on stacking we're trying a lot of things in different areas. There's no point having to make thermal setbacks if it also removes the reason why you're using the technology. But we're having fun and trying a lot, and we'll see Foveros in a number of parts over the next 5 years. We will find new solutions to problems we don't even know exist yet.

Q: When is Manufacturing Tech Day?

M: We will tell you when it happens! I'm sure you all have opinions on Intel 10nm right now and yes we are looking at what we're doing, eating an amount of humble pie, but we're re-adjusting our process to make sure that we can take the best process no matter what the product is.

Intel announced this week its acquisition of NetSpeed Systems. The moves comes as Intel looks to grow its Silicon Engineering Group and expand its portfolio of interconnect-related intellectual property. Terms of the deal weren't disclosed, but Intel did say it plans to honor NetSpeed's existing contracts prior to bringing all of its work in-house.

NetSpeed is a system-on-chip (SoC) company with six products: four interconnects called Orion, Gemini, Orion AI and Crux and two add-ons called Pegasus and SoC Builder. Besides Intel, its customers include several Fortune 100 companies in the telecommunications, semiconductor and mobile industries, as well as Arm. Altera, which Intel acquired in late 2015, was also a NetSpeed customer (talk about internal synergy).

Those products are supposed to help NetSpeed offer the "easiest and most cost effective way to assemble an SoC." Promises like that are going to become increasingly important to companies like Intel as more and more devices are expected to offer "smart" features. NetSpeed said its products have applications from connected homes and cars to cloud computing and mobile--all of which have become areas of focus for Intel.

"NetSpeed’s highly configurable and synthesizable offerings will help Intel more quickly and cost-effectively design, develop and test new SoCs with an ever-increasing set of IP,." Intel said in its announcement.

NetSpeed co-founder and CEO Sundari Mitra will become an Intel vice president reporting to Jim Keller, the lead architect of AMD's Zen microarchitecture who joined Intel after a stint at the Tesla electric car maker.

The company also explained how it plans to use NetSpeed's technologies and expertise:

"As SoCs grow more complex and as new fabrication processes explode the number of design rules, architects are increasingly utilizing front-end tools like NetSpeed’s to automate the design and validation process – saving time and money. NetSpeed’s technology helps architects estimate and optimize SoC performance in advance of manufacturing through a system-level approach, user-driven automation and state-of-the-art algorithms."

Mitra told the Silicon Valley Business Journal that this deal is also something of a homecoming for her. She worked at Intel right out of college before heading to Sun, founding Prism and selling that company to Mosys, Inc. Combine that familiarity with Intel and NetSpeed's age--four years is an eternity for a startup--and it's not hard to imagine why Mitra and Co. would decide it was time to become part of something bigger.

Intel has added another famous player to its discrete-graphics dream team. Chris Hook, who recently left AMD after 17 years leading the company's global marketing efforts, announced via his Facebook page that he has joined Intel (statement below). His arrival fuels speculation that the CPU maker will be coming out with its own line of gaming GPUs to compete with Nvidia and AMD.

Hook will lead Intel's marketing for visual technologies and discrete graphics products. As such, Hook appears to be Intel's first dedicated marketer for discrete graphics cards. Hook joins ex-AMD'ers Raja Koduri, who is leading Intel's graphics design teams, and Jim Keller, who joined Intel last week to head up its silicon engineering.  

Intel's re-entry into the discrete graphics card market came as shocking news earlier this year. Intel has made two prior attempts to bring a discrete gaming GPU to market, but it eventually shuttered both programs. The chip-maker hasn't confirmed that it will target the gaming market with its new products, instead saying the GPUs are designed for "a broad range of computing segments.”

Given Hook's history, his hire will certainly fuel speculation that Intel is developing gaming GPUs, which would make sense from a broader perspective. 

Intel is focusing on increasing sales in its "data-centric" businesses, which doesn't include desktop PCs. Overall, those segments accounted for 46 percent of Intel's revenue last quarter, with the high-margin Data Center Group leading the charge. The data center is rapidly transitioning to AI-heavy workloads due to power efficiency and performance gains, and GPUs are used for a broad range of those workloads.

Intel has multiple products for AI workloads, but data centers use GPUs for many of those same tasks. For example, Nvidia claims it can replace up to 300 Xeon processors, which consume 15 racks of space, with a single DXG-2 server. That certainly threatens to chip away at Intel's Xeon sales, so developing GPUs for the data center is a no-brainer.

Much like Nvidia does with its GPUs and Intel does with its desktop CPUs, sales to the broader desktop PC market drive up production volume and build the economy of scale that lowers costs. In turn, that assures low pricing and high margins. Intel will likely need to build GPU production volume in the PC market to compete with Nvidia's pricing, so we doubt that Intel will reinvent the wheel with its production model.

Intel's maneuvering comes after it has made some structural changes to its hierarchy, which is likely to deal with production challenges with the 10nm process. The company is obviously bringing in some of the industry's top guns to expand into GPUs at the same time, which is a smart tactic. It's helpful to have experienced hands at the helm when you're testing new waters.

We're sure to learn more about Intel's future discrete graphics cards in the coming months. Here is Hook's statement (via Facebook):

Friends, I’m exhilarated and energized to be starting a new marketing leadership role at Intel in Santa Clara, CA.Intel is a company I’ve long admired and is without a doubt the finest silicon engineering company in the world. It also has a rich history of processor innovation dating back to the Intel 4004, which was released the year I was born. It has an equally rich history in marketing innovation, having succeeded what was once the unthinkable - turning what started as an unassuming 16-pin black ceramic integrated circuit into a household name and notable consumer brand.As many of you know, it was recently announced that Intel is embarking on a journey to expand its leading position in integrated graphics for PC with high-end discrete graphics solutions for a broad range of computing segments, and will be growing its technology portfolio across computing, graphics, media, imaging and machine intelligence for clients and data centers, AI, and edge computing.That’s a pretty exciting journey, and one I personally want to be part of. So starting tomorrow, I’ll be assuming a new role in which I’ll be driving the marketing strategy for visual technologies and upcoming discrete graphics products.I’m also excited to meet the Intel team. The folks I’ve met there so far are the best in the world at what they do; they’re laser-smart and driven to win. And there are also a few good Intel folks that I’ve had the privilege of working with in the past at AMD, world-class engineering leaders Ari Rauch, Raja Koduri and Jim Keller, who at multiple points in their careers have architected and engineered some of the most respected software and silicon in history.So here’s to the future – one with competition, choice and incredible technology.Cheers,Chris

Intel announced that it has hired famed chip designer Jim Keller to head up its silicon engineering. Intel's press release also has a few interesting tidbits that hinted the company restructured its CISA group, which consists of its IoT businesses and system architecture design groups. We've since confirmed that Intel has brought its silicon manufacturing group (TMG) under the CISA umbrella.

Intel also recently hired former AMD executive Raja Koduri, a premier name in graphics architecture designs, so it's clear the company is collecting some of the best and brightest minds in the semiconductor industry as it struggles to ramp its long-overdue 10nm process.

Jim Keller hails from Tesla, where he served as the Vice President of Autopilot and Low Voltage Hardware. More importantly, Keller was the lead architect of AMD's Zen microarchitecture while he was the company's corporate vice president and chief cores architect. Keller is also famous for designing AMD's successful K7 (Athlon) and K8 architectures. AMD's canceled K12 uArch was another of Keller's more famous designs, and he has also worked for Apple in the past.

Keller is taking on the official title of an Intel senior vice president, where he will lead silicon engineering. Dr. Murthy Renduchintala, who Intel CEO Brian Krzanich brought in from Qualcomm to revitalize the company's engineering division, provided a quote for Intel's official press release announcing Keller's hire.

We noticed that Murthy has a new title. Murthy, who was previously the group president of the Client and Internet of Things (IoT) Businesses and Systems Architecture Group (CISA) and chief engineering officer, is now listed with the title of Intel's chief engineering officer and group president of the Technology, Systems Architecture & Client Group (TSCG).

This is an interesting development: Murthy's new title portends changes to Intel's CISA group. We followed up with Intel, and the company confirmed that is has combined its Technology and Manufacturing Group (TMG) into the newly-named group, which is a shift in the current alignment.

Murthy’s group has recently been renamed the Technology, Systems Architecture & Client Group (TSCG) to reflect nature of what is now encompassed within his organization. Recently Intel Labs and the Technology & Manufacturing Group (TMG) were merged into Murthy’s group, with the collective remit spanning Intel Labs, TMG, Systems Architecture, as well as the Client and Connectivity businesses.

This realignment has been rumored for several months, but now it's official. We'll certainly learn more on this topic during Intel's earnings call later today.

Keller's hire is quite fitting given Intel's current switch to MCM (Multi-Chip Module) based designs. In fact, Murthy's statement clearly indicates that Keller will lead Intel's heterogeneous design initiatives:

"Jim is one of the most respected microarchitecture design visionaries in the industry, and the latest example of top technical talent to join Intel," said Dr. Murthy Renduchintala, Intel's chief engineering officer and group president of the Technology, Systems Architecture & Client Group (TSCG). "We have embarked on exciting initiatives to fundamentally change the way we build the silicon as we enter the world of heterogeneous process and architectures. Jim joining us will help accelerate this transformation."

Transitioning to a heterogeneous design, which combines several separate components onto a single package, solves several problems for Intel. Heterogeneous designs allow the company to peel off certain types of components, such as analog devices, that don't scale well to smaller lithographies. That will help as lithography shrinks become more difficult. In that vein, Intel has invested heavily in its EMIB (Embedded Multi-Die Bridge) technology to tie together disparate compute resources. Head to our Hot Chips 2017: Intel Deep Dives Into EMIB article for all the deep-dive details.

This approach plays perfectly to Keller's experience with heterogeneous designs, as it is a key tenet of the AMD's Zen architecture. Jim Keller will lead the company's silicon engineering, but it isn't clear if he replaces another Intel executive, such as current TMG head Dr. Ann Kelleher.

Ex-AMD alums Keller and Koduri have both now landed at Intel, and Chris Hook is also rumored to be joining the company, though that hasn't been confirmed.

Overall, Intel is obviously scooping up some of the industry's top semiconductor engineers. The new talent will drive the company's broader design decisions over the years to come, so we won't see the direct result of new architectures for several years. However, we can expect that they will be instrumental in addressing some of the company's more urgent issues right now, such as the delayed 10nm process.

AMD hasn't been having the greatest year. After drastic first and second quarter loses, a lackluster graphics card launch that didn't quite meet consumer expectations, and the recent departure of Jim Keller (one of AMD's most prominent microprocessor architects), many are assuming these are the first signs of the company's pending demise. However, AMD appears to be taking measures to correct its course, and it disclosed more of the company's restructuring plans that were announced back in July with its recent 8-k filing.

In an official statement to Tom's Hardware, AMD clarified the details of its restructuring goals, which included the development of several new key positions and teams. The Enterprise Solutions Team will be created within the company's enterprise, embedded and semi-custom segment to align business, engineering and sales efforts in the data center and embedded markets, a segment in which AMD sees huge potential for growth.

Two Regional President positions will be created in Europe and China to bolster operations in parts of the world critical to AMD's long-term success. The restructuring to-do list also includes aligning AMD's global real estate footprint with its business needs, so perhaps we will see an AMD home office in Beijing or London sometime in the future (though this is of course just speculation).

AMD is also streamlining its computing and graphics sales structure by focusing its teams on priority customers, markets and geographies. This includes the formation of the already-announced Radeon Technologies Group, which will be headed by Raja Koduri and is meant to bring a vertical focus to the graphics side of the business.

The part of the restructuring plan that has people upset is the section describing the goal of its IT model, which will be simplified by outsourcing AMD's IT support and internal application development. However, the end user experience will not be impacted by any of this, as these cuts are specifically targeted at AMD's internal IT support for employees, not its customers. End user drivers and programs will not be affected. The term "outsourcing" is a sensitive subject these days, but AMD's estimates of workforce reduction are not as damning as some have made it out to be.

The company estimated that as a result of these strategic decisions, approximately 5 percent of AMD's current workforce will be purged. With the company employing just about 10,000 people (and using the power of math), we deduce that these reductions will eliminate around 500 positions in the company. The cuts are expected to affect almost every division, but least of all its engineering and development teams, which are being properly invested in for future products.

The estimated cost of the restructuring and impairment charges tops $41 million, with AMD expecting savings of $9 million for the remainder of 2015 and $58 million in 2016. The restructuring will more than pay for itself in roughly a year's time, and by no means does it indicate the company is on some sort of funeral march.

If anything should be taken from this announcement, it's that AMD is focused on cutting costs and expanding enterprise solutions, not that the end is near. Although it's always unfortunate when people lose their jobs, a 5 percent cut in the workforce is a drop in the bucket compared to some other companies' restructuring plans, and it should be taken with a grain of salt. AMD is confident about its future. With Zen cores arriving next year and VR about to hit the mainstream, the company is simply positioning itself for the future, and we shouldn't be quick to judge a restructuring as a death knell.

Follow Derek Forrest @TheDerekForrest. Follow us @tomshardware, on Facebook and on Google+.

AMD has reportedly hired two senior engineers to help the chipmaker expand into new markets beyond the the slowing PC industry. These two new hires include a previous Qualcomm engineer and a previous Apple engineer, both of which have taken high-level positions within America's #2 chip company.

According to unnamed sources, Charles Matar has expertise in low-power and embedded chip design. He previously worked at Qualcomm, and will now serve as AMD's vice president of System-on-Chip Development. Joining him will be former Apple engineer Wayne Meretsky who is now AMD's new vice president of software IP development. He will lead software development for AMD's various chips.

Both Matar and Meretsky reportedly worked at AMD earlier in their careers. Their return follows another return of a former AMD employee, Jim Keller, who joined the company as chief architect in August 2012. Previously he served at Apple as a director in charge of designing mobile processors used in the iPads and iPhones.

AMD is slated to release a new low-power processor, Temash, for tablets and hybrid laptops running Windows 8 Pro during the first half of 2013. The company is also expected to release its Kabini laptop processor, which promises 50-percent better performance than its predecessor, in early 2013. Matar will reportedly focus on designing a post-Temash SoC and beyond.

AMD's need to leap beyond the PC sector isn't unexpected. Even its partners are flocking to mobile form factors as market tastes move from desktop to tablets and hybrids. Market watchers are predicting the start of a post-PC era, and a declining PC market seems to pave the way.

Unfortunately, 80-percent of AMD's revenue is generated from the PC sector. AMD has felt the impact of this declining market, and is now quickly looking to enter different avenues to make a buck. These avenues include communications, microservers, digital signs and stripped down "thin client" computers, Reuters said.

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AMD has had it kind of rough as of late. The company has lost a number of high profile employees over the last year, including Rick Bergman, Bob Feldstein, Eric Demers, Emilio Ghilardi, Bob Rivet, Marty Seyer, and John Bruno. In addition to some of their top guys jumping ship, the company late last year announced plans to cut a total of 1400 jobs. However, today AMD showed that the company still has what it takes to attract top talent. The company announced that Apple's top chip architect Jim Keller is jumping ship and joining AMD as the company's corporate vice president and chief architect for CPU cores.

Prior to his position at Apple as director of platform architecture, Keller was the VP of Design for PA Semi, which was purchased by Apple in 2008. Apple bought PA Semi for its engineering talent, which it planned to use to build custom chips for the iPhone, iPod, iPad, and other mobile devices. During Keller's time at Apple, Cupertino has churned out both the A4 and the A5.

Though the news comes as a surprise, Keller isn't exactly a stranger to AMD. From 1998 to 1999, Keller was a Senior Fellow at the company and lead architect for K8, co-author of the HT specification, co-author of the 64 bit x86 spec and part of the system engineering team that launched K7. In his new role as corporate VP and chief architect for CPU cores, he'll report directly to AMD CTO Mark Papermaster, who also served at Apple. 

Keller holds a BS in Electrical Engineering from Penn State University. He graduated in 1980.

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