As the semiconductor industry increasingly relies on ASML's EUV lithography tools both for logic and memory production, ASML is considering increasing prices of these systems as they deliver greater productivity and better value for its customers. However, with 2027 production nearly sold out and substantial 2028 orders already booked, meaningful increases may primarily affect systems delivered from late 2028 onward. Nonetheless, the idea has already angered TSMC, ASML's largest client, reports The Information.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. "Given the long order lead times that we have, that... doesn't translate into pricing effects tomorrow."

Value-based pricing set to persist… in a new way

ASML has long followed what it calls value-based pricing and gradually increased its quotes based on output, patterning costs, power consumption, and other benefits its new tools offer to clients.

Usually, this involved increasing prices once in a while. For example, if early Twinscan NXE Low-NA EUV systems cost roughly €100 million – €120 million ($115 million–$137 million), the more advanced are priced starting at €170 million ($195 million. It is still well below rumored quotes for High-NA EXE scanners that exceed €350 million ($400 million). At the same time, Low-NA productivity has risen from 160–170 wafers per hour (WPH) and ≤1.1nm matched-machine overlay to 220 WPH/260 WPH with NXE:3800E/NXE:3800F at 0.9nm. Future NXE:4200G/NXE:4200H systems are expected to exceed 300 WPH and improve overlay to ≤0.8nm–≤0.7nm.

"Clearly, the environment that we live in today, with the value that our products bring to customer — it's substantial— of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, later during the call, Dassen emphasized that ASML intends to maintain its value-based approach even in the current environment of high demand and limited supply in the semiconductor world. Yet, he stressed that from now on, ASML might want to charge for things beyond just productivity.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. "[But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out," he said, suggesting that ASML shares value with its clients.

No price hikes in the short term

ASML will be unable to hike prices of Low-NA EUV systems for another couple of years. Since orders that are in ASML's backlog already carry a sales value, subject to inflation adjustments, prices for much of the 2027 and early 2028 output may already be contractually determined. Unless existing contracts can be renegotiated, higher pricing could therefore primarily apply to 2028 shipments and beyond, or for new orders that somehow get squeezed in in 2027. The NXE:4200G, due in 2029, should naturally lift average selling prices anyway as it gets major performance improvements.

TSMC is upset

For TSMC, however, the issue is strategic. The foundry's leading-edge roadmap through 2030 relies on extending Low-NA EUV with better masks, computational lithography, and multipatterning. Until then, TSMC's strategy has always been avoiding High-NA EUV until at least its 10A-class (1 nm-class) technology. If ASML hikes prices of its future Low-NA EUV lithography systems, it will likely affect all of TSMC's plans for the next several years.

TSMC already operates the world's largest Low-NA EUV fleet and needs many more scanners for fabs in Taiwan, the U.S., and Japan as it executes its global expansion strategy. Consequently, even modest increases beyond TSMC's projections could add billions to capital spending, reduce the economic advantage of postponing High-NA, and ultimately raise its manufacturing costs. Moreover, accepting higher prices now could establish the baseline for dozens or hundreds of future systems, which will allow ASML to capture a larger share of the economic value created by increasingly productive lithography equipment.

Can this force TSMC to transition to High-NA EUV tools earlier than planned? Moving to High-NA EUV requires not only €350-million-plus scanners but also new resists, masks, pellicles, metrology, design rules, and computational lithography flows, which are likely not ready at TSMC.

Tower Semiconductor has announced a dual-track expansion of its 300mm silicon photonics, silicon germanium, and advanced packaging operations in Japan, committing up to $3 billion net of grants with backing from the country's Ministry of Economy, Trade and Industry (METI). Alongside the announcement, the Israeli specialty foundry raised its 2028 business model to approximately $3.6 billion in revenue and $1.2 billion in net profit, and it says those targets rest entirely on the first of the plan's two tracks: reviving the shuttered Arai fab it inherited from Panasonic and maximizing its running 300mm fab in Uozu, Toyama Prefecture.

Two tracks, one committed

Track One converts the former Arai facility, designated Fab 6, into a 300mm silicon photonics and advanced optical packaging plant while expanding output at Fab 7 in Uozu, with full production readiness expected during the fourth quarter of 2027. The Arai plant ceased operations in July 2022 because it exclusively served Nuvoton Technology Corporation Japan (NTCJ) rather than Tower's foundry customers, according to Tower's SEC filings, leaving an intact fab shell sitting idle for four years.

Track Two calls for constructing a new 300mm fab adjacent to Fab 7, which Tower says would deliver a multi-fold increase in silicon photonics and silicon germanium capacity and become "highly accretive beginning in 2029." The company hasn't signed definitive agreements for it, however, and none of the new 2028 targets depend on it.

A restructuring of the TPSCo joint venture, announced in March 2026, cleared the way for all this. Tower entered Japan in 2014 by buying 51% of Panasonic's three-fab semiconductor manufacturing operation, and Panasonic sold its remaining stake to Nuvoton in 2020. Under the March agreement, Tower takes full ownership of the 300mm Fab 7, while NTCJ absorbs the 200mm operations and pays Tower $25 million, with closing expected on April 1, 2027. Sole ownership of Fab 7 removed the joint-venture structure that would have complicated a $3 billion buildout.

Tower CEO Russell Ellwanger contrasted the approach with greenfield construction and fab acquisitions, which he said typically require years of process development, customer qualification, and financial stabilization while ramping from zero revenue against high fixed costs. Reusing a dormant building next to a qualified, cash-generating photonics fab is why Tower can achieve production readiness roughly 18 months ahead; Rapidus, by comparison, broke ground on its greenfield Chitose site in September 2023 and doesn't expect mass production until 2027.

29% increase in revenue

Tower reported $1.566 billion in revenue and $220 million in net profit for 2025, up from $1.436 billion and $208 million in 2024. The new 2028 model more than doubles 2025 revenue and implies a net margin of around 33%, against roughly 14% today. Measured against the prior 2028 model of $2.8 billion in revenue and $750 million in net profit, which Tower reaffirmed in its Q1 2026 report in May, the new targets add 29% to revenue and 60% to net profit.

Silicon photonics revenue is doing most of the heavy lifting, with Ellwanger telling analysts on the company's Q4 2025 earnings call in February that silicon photonics revenue reached $228 million in 2025, up from $106 million in 2024, and hit a $380 million annualized run rate in the fourth quarter, a figure he noted includes some non-wafer engineering revenue. In May, Tower disclosed $1.3 billion in contracted silicon photonics revenue for 2027 from its largest customers, backed by $290 million in prepayments already collected.

Tower's photonics customer roster includes Innolight, which builds 400G, 800G, and 1.6T optical transceivers on Tower's PH18 platform family, and Marvell, which said in June it had shipped more than five million coherent photonic ICs manufactured with Tower. The company claims more than 50 active silicon photonics customers and supplies foundry capacity for 200 Gb/s-per-lane devices used in 1.6T transceivers.

Tower's forward-looking disclosures flag construction delays, equipment lead times, permitting, and METI grant covenants that "may result in loss of a portion or all of the grant funds." The implied margin expansion also assumes sustained AI and data center optics demand from a concentrated group of very large customers through 2028, a dependency Tower acknowledges.

Tower’s position in the photonics foundry race

GlobalFoundries paid $453 million in cash for Singapore's Advanced Micro Foundry in November 2025, according to its annual report, a deal the company said made it one of the largest silicon photonics manufacturers. TSMC's COUPE co-packaged optics platform is tracking Nvidia's optical interconnect roadmap, with 1.6 Tb/s optical engines arriving in 2026 products.

Tower occupies a different lane from TSMC, as a merchant foundry serving dozens of transceiver makers and chip designers, rather than a packaging platform aligned with one customer's rack-scale plans. GlobalFoundries competes with Tower far more directly, and the two are also in court, with GlobalFoundries pursuing patent infringement claims against Tower.

MarketsandMarkets estimates the silicon photonics market at $2.65 billion in 2025, growing to $9.65 billion by 2030 at a 29.5% compound annual growth rate. Demand for optical data movement in AI clusters underpins those forecasts, as interconnects shift from copper to light at 800G and 1.6T speeds.

METI's support for Tower joins a Japanese subsidy program that has committed up to ¥1.2 trillion to TSMC's JASM fabs in Kumamoto, roughly ¥536 billion to Micron's Hiroshima operations, and around ¥2.9 trillion in planned funding for Rapidus. Tower's award appears to be the program's first at this scale for a dedicated silicon photonics foundry.

Intel agreed to buy Tower for $5.4 billion in 2022, but abandoned the deal in August 2023 after Chinese regulators declined to approve it, paying Tower a $353 million termination fee. The Japan program is the largest capital commitment in Tower's history, well beyond the up-to-$300 million arrangement it struck with Intel in September 2023 for 300mm capacity in New Mexico. Three years after nearly becoming an Intel subsidiary, Tower is building its own flagship instead.

Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Researchers from Osaka Metropolitan University have developed a programmable thermal device that can control where heat is radiated while remembering its configuration even after power is removed, a capability that could one day contribute to smarter thermal management in high-performance chips, silicon photonics, infrared sensors, and energy-harvesting systems. The work, published in Laser & Photonics Reviews, overcomes two longstanding obstacles that have prevented the practical realization of nonreciprocal thermal devices.

The device combines a magneto-optical material — a material that changes its optical properties in the presence of a magnetic field — with a phase-change material known as germanium-antimony-tellurium (GST) to independently control how a surface absorbs and emits infrared radiation. Unlike previous designs that lost their functionality once power was removed or only worked when light struck the surface at extreme angles, the researchers say their device operates almost straight on while retaining its programmed state without continuous energy input.

Under normal circumstances, materials follow a principle stating that if a surface efficiently absorbs heat at a particular wavelength and direction, it must also emit heat equally well under the same conditions. This relationship, defined by Kirchhoff's law of thermal radiation, holds for conventional materials and limits how precisely engineers can manipulate heat. Rather than directing thermal energy where it is most useful, these materials simply emit heat based on how they absorb it.

Circumventing this relationship has become an active area of research, as it could give engineers an entirely new way to control thermal energy. Devices capable of independently steering absorption and emission could improve radiative cooling, thermophotovoltaic systems that convert heat into electricity, infrared sensing, thermal communication, and other photonic technologies where controlling heat is just as important as controlling light.

Researchers have explored several ways to achieve this by breaking Lorentz reciprocity, the physical principle that links incoming and outgoing electromagnetic waves. Most approaches rely on magneto-optical materials, magnetic Weyl semimetals, or actively modulated metasurfaces. However, these designs have generally encountered two major problems. First, they require light to strike the surface at very oblique, or grazing, angles to produce strong directional behavior. While this works experimentally, it significantly reduces the amount of usable thermal radiation and produces broad, inefficient emission patterns. Second, many existing designs are volatile. Their behavior disappears as soon as the magnetic field, electrical signal, or heating source controlling them is removed, making continuous power necessary simply to maintain their operating state.

The Osaka Metropolitan University team tackled both limitations by combining two materials that perform complementary roles. The first is indium arsenide (InAs), a magneto-optical semiconductor whose interaction with infrared light changes in the presence of a magnetic field. Rather than allowing light to behave identically in all directions, the material introduces a directional asymmetry that enables nonreciprocal thermal behavior. The second ingredient is GST, a phase-change material that can reversibly switch between amorphous and crystalline states, dramatically changing its optical properties while retaining whichever state it is written into, even after power is removed.

The researchers patterned GST into a microscopic grating above the InAs layer, forming what they describe as a magneto-optical metagrating. The InAs provides the directional control needed to separate heat absorption from heat emission, while the GST layer acts as a non-volatile switch that stores the device's operating mode. Applying a magnetic field tunes how infrared radiation interacts with the structure, while changing the phase of the GST permanently alters that behavior until it is intentionally rewritten. In effect, the device can be programmed to emit heat differently and retain that configuration without requiring continuous energy.

According to the researchers, the prototype achieved a nonreciprocity factor approaching 0.9 while operating at an incidence angle of just three degrees, much closer to normal incidence than the steep angles typically required by previous designs. The system also supports continuous tuning via changes in the magnetic field or incident angle, as well as digital on-off switching via the GST phase transition. The team further analyzed why the nonreciprocal effect weakens when GST changes state, concluding that the reduction results from a combination of optical field redistribution and increased damping rather than simple absorption losses alone.

Although the technology remains an early-stage research demonstration, the ability to program thermal radiation could eventually become valuable in computing hardware as processors continue to pack more transistors, chiplets, and photonic components into increasingly compact packages. Future thermal metasurfaces could give engineers another tool for directing heat away from hotspots, reducing thermal interference between neighboring chiplets, or stabilizing silicon photonic devices whose optical characteristics shift with temperature.

Beyond computing, the researchers also envision applications in radiative cooling, thermophotovoltaic energy conversion, infrared emitters, thermal communication systems, and photonic memory technologies. For now, however, the work remains a laboratory demonstration rather than a deployable technology. Considerable engineering challenges remain before programmable thermal emitters find their way into commercial electronics.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Intel has unveiled Starfire, a space-grade system-on-chip designed for the U.S. government that pairs eight CPU cores and a three-tile NPU built on its Intel 18A node with an Intel 3 graphics tile, all in one Foveros package. Intel published the Starfire sell sheet, listing two versions that draw 10 W and 35 W and reach up to 45 and 75 TOPS, respectively, rated to run between -55 and 125 Celsius.

Both SKUs share the same layout of four Intel 18A P-cores, four low-power efficiency cores, a three-tile NPU also on 18A, and a four-core Xe GPU with 64 execution units built on Intel 3. The Low Power part runs its P-cores at 1.0 GHz, efficiency cores at 850 MHz, and the GPU between 800 MHz and 1.0 GHz. The Performance part clocks the P-cores to 3.1 GHz, efficiency cores to 2.1 GHz, and the GPU to 2.0 GHz. Both carry 12 PCIe Gen4 lanes, support LPDDR5 or DDR5, and are rated for a 10-plus year lifetime.

Intel builds the CPU and NPU on 18A and the GPU on the older Intel 3, the same node division it used for Clearwater Forest, the 288-core Xeon that stacks 18A compute tiles on Intel 3 base tiles. Smaller transistors hold less charge per stored bit, which makes leading-edge silicon more prone to radiation-induced bit flips, so committing 18A to orbit leans on RibbonFET and design-level hardening rather than a mature, inherently more tolerant node.

The market Starfire is targeting has run on BAE Systems' RAD750 for two decades. That radiation-hardened PowerPC part clocks 110 to 200 MHz, carries 10.4 million transistors, and is built on 150nm or 250nm lithography, per public specifications, and it flies on the Mars rovers, Kepler, and Fermi, among more than 150 spacecraft. BAE's multi-core RAD5545 and the Microchip-built processor NASA is developing to reach 100 times the throughput of current spaceflight chips are the more recent step up. Starfire's up to 75 TOPS and dedicated NPU put it in a different bracket, built for on-orbit AI inference rather than telemetry and control.

Intel lists the radiation data, covering total ionizing dose, single-event latch-up, and single-event effects, as characterization in process, so the part isn't radiation-qualified yet, and it notes the specs are subject to change. Intel Government Technologies is handling Starfire, with samples in Q3 2026 and a pitch of market-competitive pricing and domestic manufacturing. Intel Foundry is the only U.S.-based maker of leading-edge logic, holds Trusted Foundry status, and has tied its 18A and packaging roadmap to Pentagon programs including RAMP-C and SHIP, though 18A yields aren't expected to reach industry-standard levels until 2027.

Apple's planned M7 Ultra chip is being designed to support up to 1.5 TB of unified memory and to push AI performance toward the class of Nvidia's Blackwell accelerators, according to a new Bloomberg report published by Mark Gurman. But whether the lofty top memory config can ship at all will depend on the state of the memory market, and the part isn't expected until 2028. The same report says Apple has compressed its Mac silicon timeline, taping out the M7 roughly six months after the M6.

We've already heard that Apple plans to release a base M6 chip this fall for entry-level Macs, then skip the Pro, Max, and Ultra versions of that generation and move straight to the M7 line. However, Gurman now reckons that we'll see a base M7 in the first half of 2027, M7 Pro and M7 Max at the end of 2027, and the M7 Ultra in 2028. Apple reportedly began taping out the M7 about six months after it started the same process for the M6, which is what has enabled the company to pull the schedule forward.

The 1.5 TB target for the M7 Ultra is roughly twice the capacity Apple has planned for the M5 Ultra, per Gurman, who tied the configuration directly to memory availability. Apple already pulled the 128GB Mac Studio this year over supply constraints as DRAM prices climbed, and a 1.5 TB part would call for far more of the same scarce, high-cost memory.

Apple's current M3 Ultra already reaches 819 GB/s of memory bandwidth by fusing two Max dies, and it's the Ultra tier, not the base chips, that carries the heaviest local-AI workloads. Gurman describes the M7 Ultra as a large step up in AI performance rather than stated parity with Nvidia's data-center silicon. "I'm told the processor dramatically upgrades AI performance, bringing it closer to the class of dedicated AI accelerators such as Nvidia Corp.'s Blackwell," Gurman wrote in his report.

Apple is also preparing an AI server built on the M5 Ultra under the code name J246 for deployment soon, with a second server chip based on the M7 Ultra planned for 2029, according to the report. The 2028 generation, which includes an M8 chip code-named Soko and a high-end Mac part called Cardinal, moves to a 1.4nm process. That aligns with TSMC's A14 node, which the foundry has scheduled for mass production in the second half of 2028.

None of the dates or specifications have been confirmed by Apple.

SK hynix has completed the largest-ever foreign company IPO in U.S. history, raising $26.5 billion in its Nasdaq debut today, July 10. The South Korean memory giant sold 177.9 million American depositary receipts (ADRs) — a U.S.-listed stand-in for a foreign share — at $149 apiece, each representing a tenth of a Seoul-listed share. The offering was more than seven times oversubscribed and drew demand from more than 500 investment firms, according to Financial Times. Temporary Nasdaq trading is underway under the ticker SKHYV before regular-way trading begins as SKHY on Monday, July 13.

The offering was led by Bank of America, Citigroup, Goldman Sachs, and JPMorgan, with nine additional firms rounding out a 13-bank syndicate. Anchor demand came from heavyweight institutions including Baillie Gifford, Coatue Management, and Situational Awareness Partners, which together signaled interest in as much as $7 billion of stock, according to people familiar with the matter cited by Financial Times.

SK hynix is the world's leading maker of high-bandwidth memory (HBM), the vertically stacked DRAM that has become critical infrastructure for AI accelerators. The company has said it will steer the proceeds toward boosting its AI-memory manufacturing capacity. Confirmed build-outs include the first-phase fab at the massive Yongin semiconductor cluster, a new P&T7 advanced-packaging line in Cheongju, and EUV lithography equipment slated for delivery by the end of next year. Separately, SK hynix is constructing its first U.S. production site, a $4 billion advanced-packaging plant in West Lafayette, Indiana, targeted for completion around 2028. The facility is eligible for up to $458 million in CHIPS Act grants and up to $570 million in federal loans.

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SK hynix is seeing sensational growth thanks to the ongoing AI boom. The company is reportedly on track to post over 200 trillion won ($133 billion) in operating profit this year, a record-breaking figure that would see SK hynix employees earn around $400,000 each in bonuses. The company’s Seoul-listed stock is up roughly 220% year-to-date and has climbed more than sixfold over the past year.

In late June, SK hynix briefly surpassed Samsung as South Korea's most valuable company, closing at around 2,080 trillion won (about $1.35 trillion), a meteoric rise for a company that almost declared bankruptcy in 2001 and, more recently, recorded an annual operating loss of 7.73 trillion won in 2023. That rise doesn't seem like it will be slowing down any time soon. SK hynix has said its entire 2026 output of HBM, DRAM, and NAND is already sold out, with the crunch expected to extend into 2027.

Japanese chipmaker Rapidus will try to lure customers away from TSMC not only by offering a different kind of service, but also by offering its manufacturing services at lower prices, chief executive Atsuyoshi Koike announced this week. The company's plan to rival TSMC in terms of pricing appears on the surface as a risky move, as the company moves to develop leading-edge process technologies.

At present, Rapidus is looking at charging ¥3 million – ¥3.5 million ($18,550 - $21,635) per wafer processed using its 2nm-class fabrication process, which is significantly below TSMC's rumored quote of around $30,000 per N2 wafer, and is comparable to what Samsung is rumored to offer with its SF2 manufacturing technology, set at $20,000 per-wafer. Actual prices will depend on exchange rates, though Rapidus' general idea of offering significantly lower quotes than TSMC is immediately apparent.

Rapidus plans to start high-volume manufacturing (HVM) using its 2nm-class fabrication technology by the second half of 2027. The ramp of a new fab will take some time, so expect meaningful volumes from Rapidus to only be produced in 2028, when TSMC's N2 will no longer be its leading-edge node.

By the time Rapidus starts HVM at its IIM-1 in 2027, TSMC will have ramped production of chips using its performance-enhanced N2P manufacturing node, and the company will also absorb all the yield learning with gate-all-around the company will have with its N2 present at five fab modules. Furthermore, by the time Rapidus reaches meaningful volumes at IIM-1 in 2028, TSMC will have ramped up production using its advanced A16 fabrication process with Super Power Rail backside power delivery as well as a 3^rd-generation 2nm-class node named N2X.

In addition to the vast 2nm-capable capacity and process maturity that should be kept in mind when comparing Rapidus with TSMC, there is another factor to consider. One of TSMC's major advantages over its rivals is its Open Innovation Platform (OIP) ecosystem, which includes comprehensive electronic design automation tools, silicon-proven IPs, even for the latest nodes, a host of contract chip designers, and advanced packaging services not only from TSMC but also from its partners. For now, neither Rapidus nor Intel and Samsung Foundry can offer anything close to TSMC's OIP.

Given the advantages that TSMC will likely have over competitors with its 2nm-class fabrication technologies in 2028, lower pricing may be among the few ways to compete against the world's largest foundry. Rapidus' strategy of offering lower quotes while operating a single fab does not seem like the best way of earning money, but perhaps a certain way to lose it.

However, Rapidus may have another ace up its sleeve with single wafer processing across all process steps. The approach will greatly speed up the production cycle, which will be its indisputable advantage over other chipmakers, albeit at the cost of tool usage efficiency. Will lower quotes and shorter production cycles be enough for Rapidus to win customers from TSMC? Only time will tell.

Rapidus is reportedly negotiating with more than 60 potential customers, mainly overseas companies, which demonstrates the company's ambitions to become a viable rival to the global leader TSMC as well as contract chipmakers Intel Foundry and Samsung Foundry.

Researchers in Korea and Japan have presented two separate memory-integration proposals that aim to increase HBM (High-Bandwidth Memory) capacity and bandwidth without trapping more heat inside ever-taller DRAM (Dynamic Random Access Memory) stacks, one of the most pressing challenges facing future AI accelerators. Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits held in June, the two approaches — V-Die from a Korean research collaboration and MOSAIC from a University of Tokyo-led group — both explore the same broad idea of standing DRAM memory dies on their edges instead of stacking the memory dies only upward like conventional HBM.

The Korean proposal, called Vertical-Die (V-Die), was presented by researchers at the Ulsan National Institute of Science and Technology (UNIST). The design rotates custom DRAM dies upright, drops through-silicon vias to free die area for more memory cells, gives each die its own bottom-edge I/O, and runs liquid-cooling channels between adjacent dies. In simulations against an HBM4 system at equal capacity, the V-Die system reportedly achieved 540 tokens per second on a GPT-3-sized workload, compared to 296 tokens per second for HBM4.

The Japanese project, MOSAIC, takes a similar “sideways stack” idea but focuses on the practical difficulty of connecting so many vertical dies to a GPU or package substrate. Presented by University of Tokyo researchers, the MOSAIC work uses orthogonal die stacking and a contactless die-to-die interface, in which data is transferred through tiny inductive coils rather than requiring every signal pad to land perfectly on a physical contact. The researchers say the prototype interface achieved up to 4 Gbps per channel, while the memory structure could double HBM4-class capacity in a DRAM-on-GPU configuration.

Both projects aim to solve the growing problem of AI chips being held back by memory. Modern accelerators can perform enormous amounts of computation, but large, powerful models depend on moving huge amounts of data between memory and compute. This is why HBM has become one of the defining technologies of modern AI hardware.

The technology addresses the memory wall by stacking multiple DRAM dies vertically on a base die and placing that stack very close to the processor. Nvidia's Blackwell Ultra B300, for instance, carries up to 288GB of HBM3E memory, without which much of the silicon would sit idle waiting for data. The dies are connected via through-silicon vias (TSVs) — tiny vertical channels etched through the silicon and filled with metal.

The stack then communicates with the GPU over an extremely wide interface, often routed through a silicon interposer or an advanced package. This is the core reason HBM can deliver terabytes per second of bandwidth: it uses a very wide, very short data path instead of sending memory traffic across a motherboard, as with conventional DIMMs (Dual In-line Memory Modules), physical sticks of RAM used in computers.

However, that same structure creates several problems. While taller stacks add more capacity, they also make it harder to remove heat. Heat generated in the lower dies and at the high-speed interface must pass through layers of silicon, bonding materials, underfill, and package structures before it reaches a heat spreader. Furthermore, TSVs consume die area that could otherwise be used for memory cells, and as bandwidth rises, more routing and I/O place additional pressure on both signal integrity and packaging costs.

HBM4, the latest generation of HBM, addresses a number of these challenges. Meanwhile, companies such as SK hynix, Samsung, and Micron are racing to improve speed, capacity, base-die performance, and thermal management. SK hynix has already shown iHBM, which embeds cooling elements into the HBM interface area, and Samsung has shown an HBM5 mockup with Heat Path Block cooling to more directly extract heat from the stack. However, they all retain the same upward stacking structure.

This convention is what V-Die and MOSAIC are challenging. By standing DRAM dies upright, the researchers expose far more silicon surface area to the cooling path. In theory, this turns the memory stack into something closer to a heat-sink fin array, where heat can move laterally and escape more directly instead of being trapped in the middle of a thick vertical pile. It also opens the door to new connection schemes along the bottom or side of each die, rather than forcing every die to communicate through TSVs running vertically through the stack.

For V-Die, the key shift is removing TSVs from the memory dies and replacing them with bottom-edge connections. Each DRAM die gets its own I/O along the bottom edge and connects directly to the substrate, with links reportedly spaced every 20 microns. The team says this layout gives four times as many connections as HBM4 and cuts memory read time by 37%, although some signals must travel farther across the package to reach the processor.

Cooling is the other half of the V-Die argument. The proposal places microfluidic cooling channels between adjacent upright DRAM dies, allowing coolant to dissipate heat closer to its source. According to the researchers, this could keep the stack around 45°C, far below the 80°C-plus range associated with dense HBM systems. In a simulated 16-die stack matched to H100-class hardware on a GPT-3-scale model, V-Die hit 540 tokens per second, compared to HBM4's 296, and cut first-token latency by 32%, or about 24 milliseconds.

MOSAIC, meanwhile, is focused on making the sideways stack manufacturable. Because the dies are assembled flat and then turned on edge, even a few microns of die-thickness variation across dozens of dies can add up to an alignment miss where the signal pads no longer land. The Japanese team’s answer is a contactless interface based on inductive coupling. One side of the memory die carries oblong coils, while a corresponding set of coils sits on the substrate or mating chip. Current in one coil induces a signal in the other, allowing data to cross the small gap without a direct metal-to-metal signal contact. This eliminates the need for precise overlapping, giving the package greater tolerance for assembly variation. Power, which requires fewer, larger connections than data, can still be supplied via physical contacts on the sides of the memory cube.

The VLSI MOSAIC prototype achieved up to 4 Gbps per channel and demonstrated TSV-free 3D integration for a memory-on-GPU layout. The team says the approach can enable twice the memory capacity of HBM4 without significantly increasing peak temperature. A related bump-MOSAIC hardware demonstration at ECTC used 100-micron-pitch microbumps, achieved stacking alignment within 6 microns as verified by X-ray CT, and showed a configuration with three times the thermal conductivity of conventional stacking while adding up to 30% more memory capacity.

While the results look promising, neither V-Die nor MOSAIC is close to replacing commercial HBM. Neither is close to shipping. V-Die is still a proposed architecture, with a prototype in the works to validate its thermal and electrical behavior; MOSAIC has proof-of-principle hardware, but the researchers have yet to show it scales to commercial DRAM capacity, yield, cost, and reliability.

Still, any viable solution to the multifaceted AI memory problem is a welcome development. SoftBank and Intel’s Z-Angle Memory (ZAM) and NEO Semiconductor’s 3D X-DRAM — both still in development — aim to solve the constraints of conventional memory. Meanwhile, the overall market is already feeling the squeeze on price and availability, even as memory makers divert capacity toward the more lucrative AI HBM and server products, driving consumer RAM prices even higher.

Micron has said it will invest up to $3 billion in the U.S. semiconductor supply chain, with $500 million of that going to GlobalWafers as strategic financing for its 300 mm raw silicon wafer plant in Sherman, Texas, alongside a 10-year agreement giving Micron access to that plant's wafer output. In a separate announcement, the memory maker raised its planned U.S. spending to more than $250 billion through 2035, up from $200 billion, and confirmed the first concrete pour at its Clay, New York campus more than a quarter ahead of schedule.

Sherman is the sole operating facility in the U.S. capable of producing advanced 300 mm raw silicon wafers, the substrate on which every leading-edge DRAM, NAND, and logic die is built. GlobalWafers opened the plant in May last year and holds a $406 million CHIPS Act award covering the site and a silicon-on-insulator facility in St. Peters, Missouri. The 142-acre campus is designed for up to six phases, one of which is running. Micron's other American sites draw their wafers from Japan, Taiwan, Germany, and South Korea; Shin-Etsu, SUMCO, GlobalWafers, Siltronic, and SK Siltron together control the overwhelming majority of global 300 mm supply, making raw silicon the most concentrated layer in the chip space.

Doris Hsu, chairperson and CEO of GlobalWafers, set out her terms for building phase two at Sherman during the plant's opening last year, telling Reuters the company needed profitability at the first two phases, customers willing to sign long-term contracts, reasonable pricing, prepayments, and government support. Thursday's announcement supplies most of that list in a single transaction.

Wafer suppliers spent the 2023-2024 downcycle protecting margins rather than adding capacity, and SUMCO is winding down 200mm production at Miyazaki this year while holding the line on new 300mm expansion. Customers, not suppliers, are therefore now underwriting the capacity. The last time the industry did this, during the 2017-2018 megacycle, chipmakers signed prepaid long-term agreements that turned into liabilities when pricing rolled over.

Silicon wafer shipments reached 3,275 million square inches in Q1 2026, up 13.1% year over year, with SEMI.org attributing the growth to AI data center demand across advanced logic, memory, and power devices. Micron's first new Idaho fab, ID1, is expected to begin wafer output in mid-2027, and production at Clay isn't expected until around 2030. The company began making 1-alpha DRAM at its Manassas, Virginia fab in May.

Micron told investors last December that it can serve only half to two-thirds of customer demand, and nothing announced Thursday changes the supply position of DRAM this year or next.

Rapidus is bidding Japan's entire return to leading-edge logic on one fab in Chitose, Hokkaido, and the schedule now turns on a 2027 mass-production target for a 2nm process that no high-volume customer has yet committed to.

Since opening the IIM-1 pilot line in April last year, the company has run wafers through Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached its expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike said the same month that more than 60 companies are in talks over 2nm capacity, but not one has yet signed a volume agreement. Given that its entire production base is the single IIM-1 facility, this leaves Rapidus with no diversification and no fallback site if the node doesn’t go ahead as planned.

However, the fab has the hopes of an entire nation pinned on it, and its plans are promising. Here's the breakdown.

A ticking clock on IIM-1

IIM-1, short for Innovative Integration for Manufacturing, broke ground in September 2023 at Bibi in Chitose, with the cleanroom completed in 2024. ASML delivered a TWINSCAN NXE:3800E in December 2024, the first mass-production-grade EUV system installed in Japan, and the tool completed its first exposure on April 1st last year. The pilot line also began operating that month.

Rapidus is currently targeting 2027 for mass production, but the company has given that date without any further qualification, with its business plan simply pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The same plan sets out a capacity ramp from roughly 6,000 wafer starts per month at the outset to around 25,000 within the first year, a fourfold increase that Rapidus is counting on to bring per-wafer costs down.

IIM-1’s siting in Chitose offers the abundant water that wafer cleaning demands, a cool climate that eases cooling loads, and some of Japan's strongest renewable-energy potential across wind, solar, and hydro. Local and prefectural authorities have organized around the project under a “Hokkaido Valley” initiative that aims to build a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.

The 2nm process

Rapidus’s 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to learn the node, with roughly 80 later returning to Chitose to transfer and tune the process for production, according to IBM.

The differentiator the company is leaning on is manufacturing flow, with IIM-1 running single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. It’s understood that the 2nm Process Design Kit (PDK) reached early customers in Q1 this year. Still, Rapidus hasn’t yet published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.

The program extends beyond the wafer, with Japan’s New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus providing funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also floated panel-level glass-substrate packaging as part of its longer-term roadmap. Building that back-end capability in Chitose rather than outsourcing it would mirror the integrated approach Intel and Samsung take.

Japan’s government as a shareholder

Rapidus’s February funding round closed at ¥267.6 billion, or about $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment, the first made possible by a 2025 revision to Japan's subsidy law permitting government equity in Rapidus, made Tokyo the largest single shareholder, with a golden share giving it veto power over major decisions, including share transfers and technology partnerships.

That round sits on top of a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, taking Rapidus’s combined capital and capital reserves to around ¥425 billion. The shares the state holds are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates, a clause that pairs with the golden share to give Tokyo both upside alignment and a downside lever.

Rapidus’s buildings and equipment are also currently owned by Japan's New Energy and Industrial Technology Development Organization (NEDO) and leased back, with the company previously obligated to buy them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.

The customer conundrum

Koike said in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10 of them. The names attached to those talks in reporting by TrendForce are IBM and the Canadian RISC-V accelerator startup Tenstorrent, with Fujitsu, a founding investor, separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, the firm led by chip architect Jim Keller and currently being considered for takeover by Qualcomm, agreed back in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center (LSTC) project, with Tenstorrent handling the CPU and Rapidus' AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.

Neither of these amounts to the committed high-volume order that Rapidus needs, and fast. Koike has described interest as growing “like a runaway steam engine,” but interest is not the same as allocation. Rapidus’s cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan’s current mainstream parts, a premium that’ll only narrow with volume.

Japan's two-track strategy

Rapidus is the leading half of a national plan that’s running on two tracks. The other is TSMC's JASM venture in Kumamoto, on the southern island of Kyushu, where a first fab backed by Sony, Denso, and Toyota began mass production in December 2024 on mature 12nm, 16nm, 22nm, and 28nm nodes aimed at automotive and industrial chips.

A second Kumamoto fab broke ground in 2025, and its planned node was upgraded twice, first to 4nm and then to 3nm, with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north. The Kumamoto plants carry far less technical risk and are already shipping; Rapidus carries nearly all of the program's execution risk and none of its proven output.

Even as the 2nm line ramps, Rapidus plans to begin 1.4nm process development in 2026, start construction on a 1.4nm fab in 2027, and reach mass production around 2029. The node leans on the company's research ties: Rapidus joined imec's core partner program in April 2023, giving it access to the Belgian institute's pilot line, and imec's position is that 1.4nm single-patterned layers require High-NA EUV, the 0.55 numerical-aperture tool that resolves the most critical metal layers in one exposure rather than several. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production, according to figures cited by both TrendForce and Nikkei.

Rapidus’ financials highlight how far all this is from being self-sustainable, having posted a ¥375 million loss for fiscal 2025 with total assets of ¥749.5 billion, while still aiming to raise around ¥1 trillion from private investors. The ASEAN+3 Macroeconomic Research Office has been cited as estimating that committed funding still falls short of the roughly ¥5 trillion needed for stable production, dependent on a private investor base that has yet to materialize at scale.

Meanwhile, TSMC moved its N2 node to volume production in late 2025, and Samsung began first-generation SF2 mass production the same year, which puts Rapidus roughly two years behind both on a node that customers can already buy elsewhere with proven yields. There’s also something of an adversarial backdrop developing: TSMC employees were reportedly accused last year of taking 2nm trade secrets said to be destined for Rapidus, an allegation a Japanese government official later characterized as non-critical. The episode has no confirmed bearing on Rapidus’s process, which is built on IBM IP.

Rapidus is targeting operating profitability around fiscal 2030 and an IPO in fiscal 2031, a timeline that assumes the 2027 ramp lands on schedule and that the customers now in talks convert into committed volume. Three milestones will indicate whether those targets are possible: a named customer with a committed volume order, evidence that 2nm yields are tracking toward the levels TSMC and Samsung already run at, and confirmation that the capacity ramp is hitting its 25,000-wafer target.

An Intel patent application published on July 2, 2026, surfaced by Underfox, has revealed the company's plans for a new high-bandwidth memory (HBM) architecture that aims to ease the packaging and cost bottleneck of today's interposer-based HBM. The patent application — filed back on December 26, 2024 — describes what Intel calls cross-batch memory (XBM), an "ultra-high-bandwidth memory with backend transistors" built with the goal of matching HBM4's footprint while swapping conventional DRAM and its ultra-wide interface for back-end-of-line (BEOL) transistors and serial Universal Chiplet Interconnect Express (UCIe) links.

Intel's proposed design is a memory stack that addresses the assembly costs that make conventional HBM expensive by dropping the costly silicon interposer and shrinking the package, while building in its own defect repair.

The filing lays out a stack of memory dies, each holding one-transistor one-capacitor (1T1C) DRAM fabricated in the back-end-of-line, wired together with through-silicon via (TSV) "gutters" and both-sided high-bandwidth interconnect (HBI) connections. Intel describes dies of roughly 1.5 gigabytes (GB) apiece — 768 "datablocks" arranged in a 32-by-24 grid, grouped into eight channels of eight sub-channels each — stacked eight high and scaling to 16. Data then leaves the stack over UCIe I/O bundles running at 32 gigatransfers per second (GT/s), funneled out through a base die.

To understand what Intel is changing, it helps to recall what standard high-bandwidth memory does. HBM stacks DRAM dies vertically on a base logic die, threads them together with TSVs, and communicates with the processor across a silicon interposer using an extremely wide parallel interface — on the order of 1,024 bits per stack. This width is how HBM delivers its bandwidth, but it is also what makes it expensive to package and hard to scale, as every one of those wires has to be routed through an interposer sitting between the memory and the compute die. As AI accelerators have outrun the rate at which memory can feed them, this "memory wall" has become the dominant constraint on performance, which is why nearly every large chipmaker is now attacking the interface and the stack rather than the logic.

XBM's first major change is structural. Conventional DRAM cells are built in the front-end-of-line, the base silicon layer where transistors are normally fabricated. XBM instead moves the 1T1C cell into the back-end-of-line, the metal-and-via stack above the transistor layer, using thin-film transistors. Building memory in the BEOL is what lets Intel pack the die into many small, independently addressable memory blocks, and it is the same backend-transistor direction Intel has pursued for placing memory directly over logic.

The second change is the interface. Rather than HBM's wide parallel PHY, XBM serializes data onto UCIe bundles at 32 GT/s, with the base die handling the serialize/deserialize step and routing all I/O to the compute die. Moving to a standard chiplet interconnect is what makes the design "chiplet-native" and, Intel argues, simpler and cheaper to package than an interposer-bound HBM stack. The tradeoff is that 32 GT/s is UCIe's current top data rate, so the interface is already running at the spec ceiling rather than leaving obvious headroom.

Intel also leans heavily on repairability. The base die carries dedicated spare channels, built-in self-repair (BISR), decode and debug logic, and four sub-channels of redundant memory arrays that act as fungible spares for defects in the dies above — post-assembly repair designed to claw back yield on a very tall stack.

A large portion of the patent application focuses not on the memory cell at all but on how to mount it. Intel details memory-on-package (MoP) and "reversed overhang" structures aimed at cutting the stack's Z-height — conventional MoP can add 300 to 350 micrometers (µm) — while removing the stiffener normally needed to control warpage and feeding DRAM power directly from the voltage regulator. This is the concrete basis for the "smaller, cheaper package" claim.

XBM should not be confused with ZAM (Z-Angle Memory), the architecture Intel is co-developing with SoftBank subsidiary SAIMEMORY and set to present at the VLSI Symposium 2026. ZAM's innovation is on the bonding side — a fusion-bonded, nine-layer stack of largely conventional DRAM with roughly 3-µm-thin silicon between tiers — and it reportedly targets around twice HBM4's bandwidth density, with commercialization aimed at 2029. XBM, by contrast, is an Intel-only filing that changes the DRAM transistor itself and the interface. Read together, they suggest Intel is running at least two parallel HBM alternatives, a fitting move for a company that began in 1968 as a memory maker.

The caveats on Intel’s proposed HBM architecture are the usual ones for a patent. The patent was filed 18 months ago, and there’s currently no product or roadmap, signaling potential intent rather than a shipping part. The UCIe interface is already at its rate ceiling, backend-transistor DRAM remains unproven at manufacturing scale, and the whole thing still has to justify itself against HBM4E and Intel's own ZAM timeline.

Huawei is planning to enter South Korea's AI accelerator market in the fourth quarter of 2026 with its Ascend 950 series processors and Atlas 950 SuperPod AI computing platform, according to a report by Korean publication ETNews last week. The move would mark Huawei's first major push into one of Nvidia's strongest overseas AI markets, with the Chinese company reportedly planning to undercut Nvidia on price while pitching its hardware as an alternative for customers seeking to reduce dependence on the US chipmaker.

The chips spearheading the move are the Ascend 950PR and the Ascend 950DT, the latest models in Huawei's Ascend line of neural network processing units (NPUs) for AI computing. The Ascend 950PR, an inference-focused chip, entered mass production in April, while the Ascend 950DT, designed for AI training workloads, is scheduled for release in the fourth quarter. Both processors are expected to debut in Korea together with the Atlas 950 SuperPod, an integrated AI computing platform that Huawei says can scale to as many as 8,192 Ascend processors in a single deployment.

According to the report, Huawei Korea has completed master distributor agreements with two local partners, Hansol PNS and longtime Huawei collaborator SK Shieldus, and has already begun preparations for commercialization, including technical training, pricing policies, marketing strategies, and localized branding for the Korean market. Huawei is reportedly building its Korean campaign around aggressive pricing and processing power.

The company claims its Ascend 950PR delivers approximately 2.87 times the inference performance of Nvidia's H20 AI accelerator while costing around one-quarter as much. The H20 is Nvidia's export-compliant AI processor developed specifically for the Chinese market after US export restrictions prevented sales of more powerful GPUs. Huawei concedes its chip falls short on raw performance compared to Nvidia's flagship H200, but argues the gap can be closed by clustering thousands of Ascend processors together via the Atlas 950 platform.

The Ascend 950 series uses Huawei's "self-developed" high-bandwidth memory (HBM), which the firm constructs from dies obtained from foreign sources. The 950PR uses Huawei's HiBL 1.0 memory and the 950DT its HiZQ 2.0 standard.

Huawei's strategy for the South Korea move, which comes as the country's demand for AI infrastructure surges, appears aimed at competing on both cost and ecosystem maturity, positioning its hardware as a viable Nvidia alternative. Nvidia's flagship accelerators reportedly command tens of thousands of dollars each, with supply remaining tight. A chip at one-quarter the price of the H20 gives Korean buyers a real incentive to seek a second source. Huawei also says it is improving compatibility between its Compute Architecture for Neural Networks (CANN) software stack and Nvidia's CUDA programming ecosystem to ease migration for developers.

Huawei is not new to penetrating South Korea's market, having successfully entered the country’s highly competitive LTE equipment market in 2013. However, past experience is not a guarantee of future success. ETNews notes that industry observers expect Huawei to face resistance in Korea, citing local sensitivity toward Chinese technology, security concerns, the power and heat overhead of high-density Chinese silicon, and the vendor lock-in risk of adopting a proprietary stack. There is also a domestic dimension, as the Korean AI-chip scene is made up largely of accelerator startups, making Huawei's arrival — backed by its supply scale and software depth — read as a competitive threat.

Intel has resolved wafer-to-wafer yield variability issues with its 18A process technology, according to a report from BlueFin Research Partners. If the report coming from an unofficial source is accurate, then Intel can expect consistent and predictable yield improvements for its products made using the latest 1.8nm-class node from now on.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

Tesla has hired Gary Jiang, an Intel veteran who most recently was responsible for installing equipment and transferring Intel's leading-edge 18A technology process from development fab in Oregon to the company's high-volume fab in Arizona, as spotted by Electrek.co. The appointment marks the first publicly identified senior leadership hire for Elon Musk's semiconductor production project, Terafab, which demonstrates Tesla's effort to build an experienced semiconductor manufacturing organization from the ground up by hiring veterans from other companies.

Tesla poaches an Intel veteran

Gary Jiang joined Tesla in June 2026 after spending over 17 years at Intel, according to his LinkedIn profile. Interestingly, there is little to glean about his current role from his LinkedIn profile, aside from noting that he is a director at Tesla. His final position at Intel was as Factory Manager, where he oversaw the construction of the production facility, the installation of fabrication equipment, factory startup, product certification, preparation for high-volume manufacturing, and, ultimately, the transfer of Intel 18A technology from the development fab in Oregon to high-volume Fab 52 in Arizona.

Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies (which include Intel 10nm SuperFin and 10nm Enhanced SuperFin/ Intel 7) at Fab 32 and Fab 42.

Tesla has been looking for a Technical Program Manager (TPM) for semiconductor infrastructure, focused on end-to-end fab program delivery, since March, but without any success, as the job listing is still listed on the company's website. Therefore, Terafab — the joint initiative between Tesla, SpaceX, and xAI — still does not have a formal leader who is going to lead the whole project.

In his most recent role at Intel, Gary Jiang worked closely with supply chain, finance, and materials logistics for new factory planning for output, wafer cost, yield, and profit & loss, according to his LinkedIn profile. He also managed the billion-dollar capital equipment and startup of the fab. Hence, without any doubt, Jiang appears to have been one of the senior manufacturing leaders responsible for building and equipping Intel's new 18A-capable manufacturing facilities in Arizona (primarily Fab 52, and potentially Fab 62 as the campus expands). However, it would still be inaccurate to say he was the person responsible for building Fab 52 alone.

Jiang's skills roughly match what one would expect from a senior manufacturing executive helping commission a new leading-edge fab, so he will be instrumental in turning a newly constructed fab shell (or even cleanroom) into a production-ready semiconductor manufacturing facility.

However, he did not oversee the entire Fab 52/Fab 62 program and was not responsible for every stage of the project — from permitting and groundbreaking to construction, tool installation, and the ramp to high-volume manufacturing. Likewise, he is unlikely to lead the Terafab project as a whole. Nonetheless, given that Terafab is set to license Intel's 14A process technology, Gary Jiang is probably among the best candidates to equip a fab for an Intel manufacturing node.

One major caveat

In fact, one of the most confusing parts about Tesla's hiring people to work at Terafab is that Tesla itself will not own any high-volume semiconductor production facilities; SpaceX will, according to Elon Musk.

In the near term, Tesla plans to build a $3 billion semiconductor R&D center at its Texas campus. The facility will house a small pilot line capable of processing a few thousand wafers per month to develop and validate new manufacturing technologies before they are scaled for commercial production.

Once the pilot line shows signs of success, SpaceX is expected to construct a full-scale high-volume manufacturing fab. However, coordinating a joint project between Tesla and SpaceX will add complexity, as major decisions require approval from both companies' boards and must undergo conflict-of-interest reviews, which will likely slow execution.

That said, given that Gary Jiang was hired by Tesla, not SpaceX, his responsibilities could be to equip and ramp a development facility at its Gigafactory Texas campus rather than build, equip, and ramp a high-volume fab for SpaceX. In any case, we are speculating here, and nothing can really stop SpaceX from hiring Jiang at some point down the line.

South Korean President Lee Jae Myung on Monday, June 29, announced an 800 trillion won ($520 billion) public-private investment plan alongside Samsung Electronics and SK Hynix to expand the country's chipmaking capacity, a move the government framed as essential to keeping South Korea competitive in the global artificial intelligence race. Lee unveiled the plan in a televised state address at his office in Seoul, flanked by Samsung Electronics Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won, the leaders of the world's two largest memory chipmakers.

"Right now is truly a decisive moment, as the landscape of the global economy is being reshaped," Lee said in televised remarks. "Major countries, including the U.S. and China, are engaged in all-out competition with massive stakes." He added that only through cooperation between the private and public sectors could South Korea hope to triumph. Industry Minister Kim Jung-kwan said the plan would let the country rapidly expand production by sharply shortening the timeline from licensing to construction.

The centerpiece of the partnership is the construction of four production facilities, with Samsung and SK Hynix each building two. According to the government, the new plants will be built in the southwestern part of the country, near the city of Gwangju, a mostly rural area far from the existing semiconductor base south of Seoul, where both companies operate major clusters. Samsung will also build packaging facilities for high-bandwidth memory (HBM) chips in Chungcheong as demand for the advanced components soars.

"HBM, which is indispensable for the training and inference of AI models, requires cutting-edge technology for stacking semiconductor chips," the Samsung chairman said. "We will focus our investment on HBM fabs, which require main-fab-level processes, alongside existing semiconductor back-end fabs in the Chungcheong region, including Cheonan and Onyang."

One detail the government did not provide was the split between public and private money, as the project is a combined public-private commitment rather than a government spending program. While it is not immediately clear how much of the 800 trillion won would come from the state versus the two chipmakers, the disclosed line items are comparatively modest.

Industry Minister Kim Jung-kwan said the government and industry would jointly invest more than 30 trillion won over 15 years across the semiconductor value chain, while President Lee said Gwangju and South Jeolla province would contribute a further 5 trillion to 20 trillion won. Kim put another 81 trillion won toward the Chungcheong packaging hub, though he did not say how much of that is public.

The balance of the headline number is widely expected to be company capital expenditure, with the state's role concentrated in subsidies, faster permitting, and infrastructure. Kim said the government would streamline approvals and bring fab construction forward by up to 12 years, from the mid-2040s to the mid-2030s.

The plan also absorbs and accelerates projects already underway. The government said it would help Samsung and SK Hynix speed up construction of their existing capital-region clusters, with SK Group pulling forward the ramp of its Yongin memory site from 2045 to 2033, part of a stated goal to double the country's memory output within five years. SK Hynix supplies the bulk of the HBM that Nvidia depends on for its AI accelerators, the very strain this expansion is meant to relieve. While semiconductors are the focus of the investment, with the priority being a decisive lead in memory chips, the companies will also work on AI robots, physical AI, and AI data centers.

The investment partnership appears to be the latest piece of a broader strategy. SK Hynix had already committed $15 billion to new semiconductor facilities in February, a figure that now reads as an early piece of the larger national framework. Earlier iterations of the country's cluster plan had pegged long-term investment at around $471 billion, stretching to 2047, so the new figure represents a substantial expansion as AI demand projections have climbed. The fabs are targeted for completion in the mid-2030s.

The announcement caps an extraordinary stretch for both firms. SK Hynix overtook Samsung in June to become South Korea's most valuable listed company for the first time in more than 25 years, lifted by its commanding lead in HBM, while Samsung's chip division alone booked 53.7 trillion won in first-quarter operating profit as AI-driven memory shortages are expected to strain the companies' capacity past 2027.

The scale of the investments also invites inevitable comparison. At roughly $520 billion, South Korea’s plan dwarfs the United States' CHIPS Act, which provided about $52 billion in direct subsidies, by a factor of ten. Although the comparison is imperfect, since the U.S. figure is a government subsidy while the Korean number appears to be mostly private investment that the state is coordinating.

The strategic logic is the same on both sides of the Pacific: secure domestic capacity for the chips that underpin AI, at a moment when the U.S., China, Japan and the EU are all pursuing their own semiconductor industrial strategies. For Seoul, the specific prize is memory, the segment where its two companies already hold a commanding global position, with the goal being to extend that lead rather than merely defend it.

Imec's semiconductor process technology roadmap sets the general direction of industry development and showcases the challenges the sector is set to face over the next few decades. The roadmap gives us an idea of the timelines for the next major process nodes and transistor architectures the company will research and develop in cooperation with industry giants, such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML, among many others.

Imec's latest production node roadmap shows that the international research and development organization envisions 3 angstrom-class (0.3nm) fabrication technologies by 2038, but expects contact poly pitch (CPP) to stop scaling at A10 in 2030. While things might not be looking great for Moore's Law for imec, to continue scaling the chipmaker will need to adopt new technologies, such as CFET transistors and likely Hyper-NA EUV Lithography systems.

GAA transistors have seven years left

As the production of semiconductors becomes substantially more complicated, chipmakers no longer introduce all-new process technologies every couple of years. Instead, they typically roll out a new node generation every three years, with annual incremental enhancements in between. TSMC ramped N3B production in 2023, then followed it up with N3E in 2024, and N3P in 2025. Intel planned to follow the same pattern with 20A in 2024 (which was canceled), 18A in 2025, and 18A-P in 2027.

Next-generation process technologies will continue to emerge at similar cadences, according to imec's roadmap.

Interuniversity Microelectronics Centre considers that we now live in the 2nm-class era (N2) with contact poly pitch (CPP) of around 48nm, as well as cell height of around 132nm and 6 metal tracks. The reality may be a bit different as Intel's 18A has a CPP of 50nm as well as a cell height of 160nm (high density) or 190nm (high performance), whereas TSMC's N3 can boast with a CPP of 45nm. N2 (or 18A, if you wish) will be followed by its performance and efficiency-enhanced version in the next couple of years, which is in line with how the industry has been operating in recent years.

"Of course, we are going to extend our logic roadmap to the next generation beyond N2," said Julien Ryckaert, vice president of R&D at imec. "As you know, in two nanometers we have already jumped into a new technology device paradigm in the nanosheet era, and that is going to bring us deep into the Angstrom node."

Imec expects the A14-class to emerge in 2028. TSMC expects to start high-volume manufacturing using A14 in late 2028, so the actual ramp will happen in 2029. Intel's 14A follows the same pattern. With A14, imec projects CPP to shrink to 45nm and cell height to drop to 115nm and 5.5 metal tracks. Around 2030–2031, imec expects an A10-class technology — or a 1nm-class — with a 42 nm CPP and 98 nm cell height, which will still rely on a 5.5-track architecture.

It is noteworthy that gate-all-around (GAA) transistor-based nodes can be implemented either with conventional frontside power delivery networks or with backside power delivery, which reflects both imec's and TSMC's belief that BSPDN will not immediately become mandatory across all applications, as many of them do not benefit from it.

It is also worth mentioning that imec expects High-NA EUV tools insertion at A14, which is in line with Intel's plans, but not with TSMC's plans.

CFET insertion in the early 2030s

The roadmap becomes particularly interesting at the A7 generation, which imec expects to come in 2033. While CPP remains at 42 nm, cell height drops to roughly 80nm, and the standard-cell architecture moves to 4.5 tracks. More importantly, A7 is the point where CFET emerges as a serious candidate for production insertion. Instead of placing n-type and p-type transistors side by side, CFET stacks them vertically, which adds a third dimension to transistor scaling.

Imec’s roadmap explicitly positions CFET as the leading contender for A7, which means that the organization sees conventional nanosheet architectures approaching practical scaling limits in the early 2030s. Yet, since A7's CPP does not change from A10, chipmakers may or may not adopt the all-new transistor architecture at A7. Also note that imec seems to consider BSPDN as mandatory for CFETs.

"Moving into A7, the seventh-angstrom generation, which is the fourth generation of nanosheet, we see more and more challenges in scaling the conventional nanosheet device technology," Ryckaert said. "There is a contender that we have already mentioned as well in previous presentations, where CFET could start emerging as the solution for the next era of transistors."

Beyond A7, the roadmap seems to depend on CFET evolution. The A5 generation, expected in 2035–2036, retains a 42nm CPP but reduces cell height to about 64nm using a 4-track library. By 2038, the roadmap reaches A3 with a 39nm CPP and 50nm cell height. At this point, imec envisions sequential CFET implementations and eventually bonded CFET structures that further exploit vertical integration. In fact, vertical integration seems to be the new way we should look at Moore's Law's evolution. Meanwhile, to get to a 39nm CPP and 50nm cell height, chipmakers might need to use Hyper-NA EUV lithography scanners, according to imec.

Redefining Moore's Law

The most interesting thing about imec's roadmap is that it essentially redefines what Moore's Law means. Traditionally, we consider Moore's Law as the observation that the number of transistors on a chip of a certain size doubles every 18 – 24 months, as they are getting smaller.

The fact that imec shows CPP stuck at 42 nm from A10 through A5 is almost an admission that classical transistor scaling is running out of steam, and future density gains must come from vertical integration. In the imec roadmap, transistors are still getting denser, but not exactly because individual transistors are shrinking at the same pace they used to decades ago, but because chip designers can fit more logic gates into a given area because of different transistor architectures, 3D integration, or backside power delivery.

As a result, in the coming years, we may no longer care how many nanometers a gate pitch is, or individual transistors, but rather the size of a standard cell. After all, when companies like AMD, Intel, or Nvidia design a chip, they do not place individual transistors, but actual blocks built from standard cells. Yet, calculating the size of a standard cell is complicated because while cell height is fixed, its width is not, and depends on the actual function.

Library height × CPP is not the size of a specific standard cell. It is the fundamental footprint unit of a standard-cell library and a widely used proxy for logic density. Actual standard cells have that height, but their width varies depending on function. Instead, the industry uses such metrics as logic cell area (standard-cell footprint) — Cell Height × CPP — that measures the actual footprint of the logic building blocks that designers use, not just the dimensions of individual transistors.

The transition from 6-track cells at N2 to 3-track cells at A3 illustrates how future density gains will rely as much on shrinking standard-cell height as on reducing transistor pitch. As a result, despite the fact that CPP shrinkage is expected to stall for years, logic cell area is set to decrease; designers will be able to extract transistor density gain from future nodes, proving that Moore's Law is still here.

Hetrogenous Large-Scale Integration × Cross-Technology Co-Optimization

Given all the changes that the semiconductor industry is already experiencing and what is set to come, imec believes the sector is entering a new era that it calls Heterogeneous Large-Scale Integration (HLSI). The concept reflects a shift away from traditional VLSI scaling, where progress largely depended on the evolution of transistors and increasing transistor density, toward a model that combines multiple technologies within a single compute platform.

Future systems will rely on heterogeneous integration of logic, memory, power-delivery circuitry, and optical I/O using advanced 3D and 3D + 2.5D packaging technologies, according to imec's predictions. Of course, the organization expects AI workloads to become the main driver of semiconductor demand, so expect both compute architectures and the semiconductor industry to evolve in a direction that satisfies the needs of AI applications.

"As we will move deeper into AI-driven architecture, we will need to double down on the heterogeneity that technology offers, and this will probably move the VLSI paradigm to the HLSI paradigm, the Heterogeneous Large Scale Integration," Ryckaert said.

To optimize future platforms on the system level rather than develop individual components in isolation, imec has established its Cross-Technology Co-Optimization (XTCO) framework, which could be seen as an integral part of the HLSI vision. XTCO is designed to wed development logic, memory, interconnects, power delivery, cooling, and packaging, and assesses their impact on key system metrics such as compute density, energy efficiency, thermal performance, and memory.

It remains to be seen how this is going to work out, if at all, given the fact that logic process technologies are developed at foundries, memory technologies are designed at DRAM makers, whereas cooling is developed at third parties like CoolIt or Frore Systems.

Power and cooling

As individual chips get denser and more power-hungry, power delivery is set to become a critical bottleneck, which is why all leading chipmakers — Intel, Samsung, and TSMC — are implementing or set to implement backside power delivery technologies and integrated voltage regulators.

Imec expects future AI accelerators and CPUs to rely on a combination of BSPDN, IVRs, embedded capacitors, and advanced power semiconductors to reduce losses and improve efficiency. Over time, more power-conversion stages are expected to migrate from racks and motherboards into packages themselves to deliver cleaner power directly to transistors.

Since we are talking about multi-chiplet packages consuming kilowatts of power, the importance of cooling is hard to overestimate. For sure, 3D stacking and CFETs will not make cooling any easier because thermal power density is set to increase linearly with the number of transistors, thermal resistance is set to increase, and local hotspots will become an even bigger problem than they are today. As a result, imec expects future compute platforms to rely on a combination of more advanced cooling technologies, improved heat spreading, fine-grained thermal sensors, and system-level thermal optimization techniques.

"At the end of the day, what we need to achieve is a reduced energy cost of data movement. We need to improve the TDP for better thermal management," Ryckaert said. "We need to improve the efficiency of the power delivery, and we need to obviously increase the compute density to improve the functionality."

In short, useful future scaling will depend not only on the ability to build transistors and increase their density, but on delivering power efficiently and removing heat effectively.

Paving the path forward

Imec's latest semiconductor roadmap projects logic process technologies all the way to A3 generation around 2038 and argues that Moore's Law can continue despite the slowing pace of traditional transistor scaling. While the Dennard scaling for semiconductors is over, there are plenty of interesting things incoming.

According to the roadmap, conventional gate-all-around nanosheet transistors should remain viable through A10, while CFET architectures become a candidate for production insertion at the A7 generation around 2033. Meanwhile, future transistor density gains are expected to come from vertical integration, reduced standard-cell footprints, and eventually sequential and bonded CFET structures rather than from aggressive shrinking of transistor dimensions.

IBM on Thursday said it has produced the first test chip using its 0.7nm-class (7 angstroms) fabrication technology, the industry's first sub-1nm manufacturing process. The concept process technology relies on the so-called nanostack transistors and promises rather dramatic power, performance, and area (PPA) gains compared to IBM's 2nm-class node. To produce nanostack transistors, IBM uses two wafers instead of one, along with ultra-thin dielectric bonding, an arrangement that has never been used before.

IBM's 7A-class (or 0.7nm-class) fabrication process based on nanostack transistors is said to offer up to 50% higher performance and 70% higher energy efficiency compared to IBM's 2nm-class node based on nanosheet gate-all-around transistors the company introduced in 2021. Perhaps more importantly, IBM's nanosheet architecture provides a 40% higher SRAM density and even higher density improvements for logic transistors, gains that are extremely hard to achieve these days.

Such massive gains have been enabled by numerous innovations, but the key enabler is IBM's nanostack transistor architecture, which conceptually resembles CFETs and stems from GAA nanosheet transistors.

Two wafers instead of one

In modern process technologies, all logic transistors live in one active device tier, and NFETs and PFETs sit side by side laterally in the standard-cell layout. Nanosheet GAA transistors feature a more advanced internal geometry, but they still reside in this single-transistor tier, which gets harder to shrink with every generation.

IBM's nanostack concept seems to separate complementary n-type and p-type transistors into vertically bonded tiers instead of placing them side by side in a single transistor layer. The payoff is a major reduction in the lateral footprint of a CMOS pair, as the architecture effectively turns one NFET+PFET structure from a 2D layout into a 3D stacked layout, which is why IBM can claim roughly double transistor density versus its 2nm research node without relying on conventional planar shrink.

While conceptually IBM's nanostack transistors resemble CFETs, the way IBM builds its nanostacks is fundamentally different compared to monolithic CFETs proposed by various chipmakers and organizations. N-type and p-type transistors are fundamentally the same kind of transistor used as complementary partners in CMOS logic, but they differ in carrier type (electrons for n-type and electron holes for p-type), switching polarity, and electrical behavior, which is why advanced process technologies tend to optimize them separately. However, these n-type and p-type transistors are made on the same wafer using essentially the same materials, so the level of their optimization is limited today.

Instead of building n-type and p-type transistors on the same wafer using the same materials, IBM builds them separately on different wafers and integrates them together using ultra-thin dielectric bonding in CMOS integration. This enables the company to optimize n and p-type channels independently, as each tier now can use different process conditions, different channel materials, different strain engineering, or even different geometries (though images from IBM indicate that the geometry of different transistors is the same).

As we see with all new process nodes, the nanometer-scale measurement doesn't coorelate to the physical dimensions of the device, but this remains a tremendous achievement.

Numerous caveats

Using two wafers for active transistor tiers instead of one could let IBM stack NFETs and PFETs vertically and optimize them independently, but such a method comes with a number of caveats that do not exist today with single-tier logic nodes.

The biggest issues are alignment and bonding yield, because two advanced logic wafers must line up with extreme precision, and any defect at the bond interface can kill the stack. Secondly, routing and power delivery could get more complex with two active device tiers. Thirdly, cooling gets harder now that one active tier sits farther from the heat sink. Last but not least are the costs. IBM has to pay for two advanced FEOL wafers, additional bonding and thinning steps, and manage higher process complexity and likely lower yields. As a result, the whole concept only makes sense if the density, SRAM, and performance-per-watt gains are large enough to offset manufacturing difficulties and cost penalty. IBM says nothing about costs and manufacturability, and the test chip it has completed is the size of a fingernail,' so not hard to make by today's standards. Meanwhile, it is highly likely that the approach only makes sense for heavy-duty data center AI solutions (which are near reticle size) and not for mainstream processors for client applications. For others, monolithic CFETs can do the job.

On the bright side, IBM's 7A-class fabrication process does not rely on High-NA EUV lithography, as there are simply no such tools at the semiconductor research facility in Albany, New York, where IBM develops its technologies. Usage of proven Low-NA EUV systems makes it easier to get high yields now. Meanwhile, it remains to be seen how IBM's dual wafer approach works with High-NA EUV scanners that have half the exposure field compared to Low-NA EUV machines and therefore require field stitching, which does not really help yields. IBM implies that its next-generation nodes will use High-NA EUV lithography, so the company probably has ideas how to wed these new tools with its approaches to transistor designs.

In production in the next five years

When dealing with IBM's manufacturing technologies, one has to keep in mind that these are not fabrication processes that can be licensed and rapidly deployed at a high-volume fab, but are essentially a set of pre-competitive IPs, patents, and some R&D know-how that can be used to design an actual production node. For example, Rapidus licensed IBM's 2nm-class process, though it has yet to prove that it can create a competitive high-volume node.

IBM believes nanostack could make sense for sub-1nm generations and potentially enter mass production within the next five years.

TSMC has reportedly told customers to prepare for price increases across its advanced chipmaking portfolio, extending the hikes beyond the newer 3nm process to include 7nm and even legacy products. According to a June 23rd Culpium report, the increases would affect the bulk of TSMC’s wafer revenue and could raise costs for major chip designers, including Apple, Nvidia, AMD, Qualcomm, Broadcom, and MediaTek.

The exact size of the increases remains unclear, as figures would reportedly vary by customer, node, and product category, but generally appear to fall in the 5% to 10% range. TSMC price increases have reportedly already started rolling out in some cases, while other customers have been told to build the higher cost structure into future purchase orders.

The company declined to discuss specific pricing with Culpium. “TSMC does not comment on pricing. Our pricing strategy is strategic, not opportunistic,” the company said in a statement to the publication. “We will continue to work closely with customers and sell our value to them.” Although the company had earlier said it would refrain from raising prices.

Earlier reports from Taiwanese media had mainly pointed to increases at TSMC’s 3nm node, one of its most advanced processes currently used for premium smartphones, PC, and AI chips, with price pressure also expected at the newest 2nm-class production. However, Culpium reports that TSMC has informed clients that “all advanced nodes” will become more expensive, meaning the hikes would extend beyond 3nm and 2nm to include older but still advanced processes such as 5nm and 7nm.

3nm alone accounted for 25% of TSMC’s wafer revenue in the first quarter of 2026, while the company’s full advanced-node portfolio — defined by TSMC as 7nm and more advanced technologies — accounted for 74% of wafer revenue. Therefore, the hikes would span nearly three-quarters of the company’s wafer business.

The inclusion of 7nm is especially notable because the node is no longer TSMC’s flagship technology. However, it's not exactly surprising as 7nm remains heavily used across processors, accelerators, networking silicon, and other high-performance chips. Many products remain on older, more advanced nodes because they offer better cost, yield, and maturity than the newest processes, especially when a design does not require the density or efficiency gains of 3nm or 2nm.

The client notices follow weeks of public comments from TSMC executives suggesting that higher prices were at least under consideration. At the company’s annual shareholders’ meeting in Hsinchu on June 4, CEO C.C. Wei said customers remained positive on the AI demand outlook, while also acknowledging cost pressures and the widening gap between chip demand and available manufacturing capacity. CFO Wendell Huang also said earlier that TSMC did not rule out price increases as inflation, overseas expansion, and advanced manufacturing costs continue to rise.

The timing of the price increases reflects TSMC’s strong negotiating position. The company remains the dominant manufacturer of leading-edge logic chips, and its most advanced capacity is in high demand among AI accelerator vendors, smartphone chip designers, and custom ASIC developers. With customers competing for access to the same manufacturing lines, TSMC has more room to pass on rising costs than it would in a weaker cycle.

The move also comes as TSMC benefits from a surge in AI-related demand. In its first-quarter results, the company reported $35.9 billion in revenue and a 66.2% gross margin, both supported by strong demand for high-performance computing and advanced-node production. TSMC has also raised its 2026 revenue growth target to more than 30%, with capital spending expected to remain elevated as the company expands capacity in Taiwan, the U.S., Japan, and Germany. The company’s Arizona manufacturing capacity has been sold out through 2027 since early 2025.

The reported increases are still far smaller than the recent price spikes seen in the memory market, where AI-driven demand for HBM and other high-end memory products has allowed suppliers to push through much steeper increases. Conversely, TSMC does not need memory-style pricing to meaningfully improve its margins. Because advanced nodes account for most of its wafer revenue, even a mid-single-digit increase across that base could add billions of dollars in annual revenue if demand remains strong.

For chip designers, the immediate impact is a higher manufacturing bill. For consumers, the effect is less direct but still important. A 5% to 10% wafer price increase does not automatically translate into a 5% to 10% increase in the price of a GPU, CPU, smartphone, or laptop, since the wafer is only one part of the final product cost. However, when combined with higher memory prices, packaging constraints, AI demand, and rising manufacturing costs, it creates another reason for device makers and component vendors to raise prices or protect margins by cutting costs elsewhere.

An interesting conversation on X has unearthed the existence of a rare ASML-focused Special Edition Monopoly board. Two chipmaking and engineering enthusiasts appear to have clinched a deal where one hands over an ASML Lego kit, a scale model of the world’s first High-NA EUV machine. In the no-cash deal, the other party will receive an ASML Special Edition Monopoly board. It appears that the deal is done, barring any regulatory hurdles and no one changing their minds, but it did pique our interest in the history of the board.

While we’ve seen and reported on the ASML chip tool Lego sets previously, this is the first time the firm’s special edition Monopoly set has blipped on our radar. It is possible this obscurity is due to this board game edition coming out way back in 2007, when the pioneering Dutch semiconductor company’s profile wasn’t quite as high as it is now. With the semiconductor segment becoming all the more important in recent years, driving the current AI boom, cutting-edge chip tool firms like ASML have risen to great prominence.

ASML’s special edition merchandise is also in high demand in the 2020s. Thankfully, we can learn a little more about the provenance of the headlining Monopoly board as it is featured in the board game’s Wiki. As previously mentioned, it was produced in 2007. Specifically, it was prepared for the Christmas period at the end of that year “as a gift to ASML employees and their families this holiday season.” From that ‘publisher’s description, it sounds like quite a few employees will have received one of these games, but it is still obviously an attractive collector’s item.

Sadly, the Wiki imagery doesn’t clearly show what the playing ‘tokens’ are (that’s Hasbro’s official term for the little metal playing pieces). The normal game has tokens like a boot, a dog, and a car, but we can’t quite make out the detail on this. Instead of streets and avenues, the ASML Monopoly board appears to have technologies and machines. Furthermore, the traditional stations are replaced by ASML campuses. Elsewhere on the board, special spaces include Corporate Tax and Press Release, where you must pick up a card. Regular Monopoly features such as Go, Water Works, Go To Jail, and the Electric Company remain.

Other non-consumer-facing semiconductor brands like TSMC and SK hynix have released successful sellout merchandise and memorabilia in recent years. Some items are easier for non-employees to get a hold of than others. For example, it is easy for anyone to find resellers of TSMC-related merchandise on Taiwan’s Shopee marketplace.

ASML has told Tom's Hardware that claims one of its extreme ultraviolet (EUV) lithography systems has ended up in China despite export restrictions is both inaccurate and damaging to its reputation. It follows a report that Commerce Secretary Howard Lutnick questions senior leadership, concerned that one of the machines had ended up in China in breach of export restrictions.

The company is refuting a recent report claiming the U.S. government believes that one of ASML's extreme ultraviolet (EUV) lithography systems may have somehow reached China despite export restrictions, according to Bloomberg, citing sources familiar with negotiations between the U.S. officials and ASML executives. ASML denies any wrongdoing and claims that it knows the location of every EUV tool it has ever built.

The issue reportedly emerged during meetings between U.S. Commerce Secretary Howard Lutnick and ASML executives. According to people familiar with the discussions cited by Bloomberg, Lutnick questioned whether an EUV system may have found its way into China. Such a development would represent a major breach of export controls because, under the Wassenaar Arrangement, ASML can not ship EUV lithography equipment to Chinese customers. In fact, the only EUV tool that China-based Semiconductor Manufacturing International Corp. (SMIC) has bought remains in the Netherlands. As a result, ASML calls the accusations 'unfounded' and 'damaging.'

"In recent years, ASML has refuted several unfounded rumors regarding non-compliance with export controls concerning China which were inaccurate and damaging to our reputation," a spokesperson for ASML told Tom's Hardware.

The U.S. government has not publicly produced evidence that a complete EUV scanner is operating in China. Yet, several senior administration officials told Bloomberg that they possess information indicating that ASML exported equipment associated with EUV systems, including specialized systems used to 'transport EUV machines.' Those officials declined to disclose any evidence, citing sensitivity concerns.

"ASML has never shipped an EUV machine to China, nor have we shipped to China any component, module or equipment specially designed to be used in an EUV machine," the spokesperson told us.

An ASML EUV scanner is made of 100,000 components and weighs 180 tons. It is transported only by air on multiple planes, and it would be impossible to intercept such a shipment without causing an international scandal. Meanwhile, given the complexity of the machine, it is impossible to build one using spare or scrap parts or reverse engineer it using its components, as we reported back in December.

Bloomberg claims that ASML has circulated an internal presentation titled 'No indication of any ASML EUV System in China,' which reportedly states there are 314 EUV systems currently operating worldwide and another 26 that have been retired. According to the document, none are located in China. The presentation further notes that EUV scanners continuously communicate with ASML, so the company can detect interruptions, abnormal activity, or connectivity issues. In addition, customers cannot simply dismantle, transport, and reinstall an EUV scanner without direct assistance from ASML due to specialized logistics and handling requirements.

ASML certainly understands concerns of the West regarding China, so claims it has never shipped an EUV tool to the People's Republic initially due to the Wassenaar Arrangement and then due to more recently imposed export controls.

"ASML regularly engages in transparent and open dialogue with government leaders globally," ASML told us. "We recognize the national security considerations behind export control regulations in the U.S. and the Netherlands. As a company, we are fully committed to abiding by all laws and regulations applicable to our business activities, including all applicable relevant export control regulations, and we have consistently adjusted our business to any development in export controls to comply to any new rules."

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer at a 50nm contacted poly pitch, the tightest pitch demonstrated to date for complementary 2D devices and one that lands within range of leading-edge silicon.

The trio presented the work this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, using a single EUV exposure to print channel lengths as short as 28nm. Imec reported that 94% of the integrated transistors switched correctly, with an on/off current ratio above 100,000. The n-channel devices use molybdenum disulfide (MoS₂), while the p-channel devices use tungsten diselenide (WSe₂) or tungsten disulfide (WS₂).

2D transition metal dichalcogenides have been studied for more than a decade — imec has been fabricating MoS₂ test transistors since the late 2010s — so while it’s not a new material breakthrough, the result is a solid milestone in terms of integration and scaling. What’s changed with this work is that both transistor polarities were built together on a standard 300mm process flow, rather than as isolated single devices patterned with coarser lithography.

The demonstrated transistors reached active widths down to 75nm and an equivalent oxide thickness near 2nm. Both polarities turned fully off at zero gate voltage, and imec said the WSe₂ p-channel devices performed close to the best lab-scale results reported so far, narrowing the gap on the historically weaker p-type side of 2D CMOS. For perspective on the pitch, 50nm is tighter than the 54nm contacted gate pitch of Intel's 10nm-class node.

Building the transistor upside down

Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, partly because the metal pins the semiconductor's Fermi level and raises the Schottky barrier that carriers must cross. Lab devices have compensated by keeping large contact areas, which in turn blocks the pitch scaling that makes the transistors worth pursuing in the first place.

To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.

"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.

EUV resolution, not High-NA

The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.

Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS₂. University groups have pushed monolayer MoS₂ transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.

2D channels

2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.

Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node, N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.

And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.

This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity. In the space of 12 months, Intel has gone from canceling fabs to running short of them. In July last year, the company scrapped a planned €30 billion megafab in Magdeburg, Germany, and a $4.6 billion assembly and test plant near Wroclaw, Poland, citing a lack of committed demand. Then, in April this year, it paid Apollo $14.2 billion to repurchase the 49% stake in its Ireland fab that it had sold for $11.2 billion in 2024. Three weeks later, CFO David Zinsner described "unprecedented demand for silicon" alongside Q1 results that sent the stock up 24% in a single session, its best day since October 1987.

The next round of capacity development now hinges on two key deadlines: CEO Lip-Bu Tan told investors in January that prospective 14A customers will begin to make firm supplier decisions "starting in the second half of this year and extending into the first half of 2027." Separately, the enhanced 35% advanced manufacturing investment credit signed into law last July applies only to fab construction that begins before December 31st, 2026; projects that break ground in 2027 get nothing.

Both clocks run out within months of each other, and both bear on the same construction projects.

Arizona

Fab 52 at the Ocotillo campus in Chandler is the production foundation for everything on Intel's 2026 to 2028 product roadmap. The facility became fully operational in October last year as the first high-volume home of Intel 18A, building Panther Lake compute tiles and, later this year, Clearwater Forest. Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is "capable of more than 10,000 18A wafer starts per week," which works out to roughly 40,000 wafer starts per month at full ramp and makes it larger than TSMC's Fab 21 phase 1 and phase 2 combined.

That’s named capacity, however, not current output; Intel has indicated that 18A yields will reach industry-standard levels in early 2027, and until then, the company is capping CPU output on the node, leaving part of Fab 52's capacity idle. Tan said in May that 18A yields are improving by 7% to 8% per month.

Fab 62, the second from Intel's $20 billion 2021 Arizona expansion, is expected to be ready around 2028. Intel hasn’t officially assigned it a node, leaving it open as a stopgap for 14A if Ohio isn't ready, or as additional 18A capacity if external demand comes sooner. Brookfield Infrastructure put up to $15 billion into the two Chandler fabs in 2022 for a 49% share of the joint venture, and unlike the Apollo arrangement, Intel has made no move to buy that stake back, so every wafer out of Fab 52 and Fab 62 will have revenue share commitments attached to it.

Oregon

As the home of 14A, D1X complex at Gordon Moore Park in Hillsboro — a low-volume fab and development site — is currently the only place Intel develops leading-edge process technology, with Chandrasekaran telling CNBC the node will be developed first in Oregon, with a goal of risk production in 2028 and high-volume manufacturing in 2029.

Hillsboro houses Intel's High-NA EUV machines, including the first ASML Twinscan EXE:5200B system delivered anywhere, and 14A is the first Intel node designed around it. Oregon also carried early 18A production while Arizona ramped up. Intel began permitting work in February 2024 for a multibillion-dollar expansion of the campus following the approval of an air quality permit, though no construction start has been announced to date.

Ohio One

Ohio is Intel’s most problematic fab project on paper. It broke ground in New Albany way back in 2022 on a $28 billion first phase, originally targeting 2025 production. In February 2025, however, Chandrasekaran reset its schedule, targeting 2030 for the completion of Mod 1 with operations between 2030 and 2031, and Mod 2 in 2031 with operations in 2032. In a memo setting out this new schedule, Chandrasekaran said Intel preserves “the flexibility to accelerate work and the start of operations if customer demand warrants.”

Spanning nearly 1,000 acres, the site is designated for 14A and future nodes, and has room for up to eight fabs. Intel has spent roughly $5 billion there to date as of March 2025, including $1.4 billion in total for that year. Bechtel, the lead contractor, posted a wave of new construction job listings in January, the same month Tan declared Intel is “going big time into 14A.”

Still, customers (or a lack thereof) remain the gating factor for 14A production. Intel told investors in January that it’s got two prospective customers evaluating 14A test chips, and its SEC filings still warn that without a significant external customer, it “may pause or discontinue” 14A, successor nodes, and various manufacturing expansion projects.

Elon Musk said in April that his planned TeraFab project — the first named taker for the node — will use 14A process technology to make AI chips, though test production is expected to be years out. This also isn’t such a big win in terms of the volume commitment Intel’s filings say it needs for 14A to be viable. At the time of writing, 14A’s next and arguably most critical milestone is the 14A v0.9 PDK, which Tan says will reach external customers in October.

"The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Ireland and canceled projects

Launched in 2023, Fab 34 in Leixlip is Intel's only EUV-class site in Europe, producing Intel 4 and Intel 3 silicon for Core Ultra and Xeon 6 parts. In 2024, Apollo-managed funds paid $11.2 billion for a 49% interest in the joint venture entitled to the fab's output, a deal that gave Intel a much-needed cash injection at the time.

In April this year, Intel bought that stake back for $14.2 billion — at a premium of roughly 27% — funded from cash and about $6.5 billion in new debt issuance. Apollo walked away with around $3 billion in return for two years of exposure, and Intel paid a nine-figure annual cost of capital to reclaim needed wafer revenue.

“Flexibility and alignment are core to how we approach relationships as a long-term, solutions-oriented capital partner, and we are pleased to facilitate this transaction in support of Intel's evolving strategic and operational priorities,” said Apollo Partner Jamshid Ehsani at the time.

Magdeburg, once pitched as a €30 billion home for 14A-era production with roughly €10 billion in German subsidies attached, was postponed to 2029-2030 in November 2024. This prompted the German government to reallocate those subsidies to the federal budget and, following a $3.2 billion operating loss with Q2 2025 financial results, Intel killed the project, the subsidies dying with it.

Wroclaw's $4.6 billion assembly and test plant was canceled the same day, and Costa Rica's assembly and test operations were consolidated into Vietnam and Malaysia. Fab 38 in Kiryat Gat, Israel, the planned $25 billion expansion announced in 2023 with $3.5 billion in Israeli government backing, has been paused for the last two years, with no restart announced. Every leading-edge wafer Intel produces for the foreseeable future will come therefore come from three U.S. states and one campus in Ireland.

Packaging and test

Fab 9 in Rio Rancho, New Mexico, a $3.5 billion conversion that opened in January 2024, is the only high-volume Foveros 3D stacking site in the United States. Foveros is the packaging behind every tiled Intel design since Meteor Lake, bonding compute, graphics, and I/O dies vertically rather than laying them side by side, and it is integral to the stacked Clearwater Forest parts now ramping on 18A.

Intel runs it alongside the neighboring Fab 11x as a single co-located operation, which EVP Keyvan Esfarjani called “the only U.S. factory producing the world's most advanced packaging solutions at scale.” The buildout created hundreds of Intel jobs and more than 3,000 construction roles, and the campus later drew a further $500 million in CHIPS funding for modernization.

The $7 billion Penang complex in Malaysia, placed on indefinite hold in early 2025, has been revived: the buildout is now 99% complete, and first-phase assembly and test operations are due to begin later this year, according to Malaysian Prime Minister Anwar Ibrahim, following an earlier briefing with Tan. Intel has also outsourced EMIB production to Amkor's Songdo facility in South Korea, and its next-generation EMIB-T packaging rolls out across production fabs this year.

With Magdeburg and the Penang delay having stripped packaging options elsewhere, Rio Rancho is now the load-bearing U.S. node for the back-end work that makes Intel's entire chip roadmap possible.

Two deadlines and three things to watch

Intel’s 14A commitment window and the cutoff for tax credits both converge in the second half of this year. Tan’s stated expectation is that customers make firm supplier decisions between the second half of 2026 and the first half of 2027, with results from the upcoming October PDK potentially being the trigger for those decisions.

On June 8th, Cadence announced a multi-year agreement with Intel Foundry to co-optimize designs for 14A and deliver production-ready process design kits. This is exactly the EDA groundwork that needs to be in place before any fabless customer can commit volume, and a committed volume customer will be what unlocks acceleration at Ohio and gives Fab 62 a job. The alternative, per Intel, is to cancel 14A altogether.

Unlike the customer deadline set by Intel, the tax deadline can’t slip. The so-called One Big Beautiful Bill Act raised the Section 48D advanced manufacturing investment credit from 25% to 35% in July last year, but the law's termination clause is unchanged: the credit doesn't apply to “property the construction of which begins after December 31, 2026.”

Treasury rules let a physical-work test or a 5% spend safe harbor establish a construction start, so Intel has roughly six months to break ground on any new shells, in Ohio, Arizona, or Oregon, that it wants the U.S. government to part-fund. The government, of course, has been a shareholder since August, when $5.7 billion in unpaid CHIPS grants from Intel's $7.86 billion award and $3.2 billion in Secure Enclave funds were converted into a 9.9% equity stake.

Ultimately, we’re going to be watching for three things before January: a named 14A customer with a volume commitment; a construction-start announcement timed to beat the credit deadline; and 18A yield milestones that free up the Arizona capacity Intel’s currently sitting on.

Following a paper published earlier this year, Intel has provided more details on its optimized 18A-P process at VLSI 2026. The performance-optimized node is an enhancement of 18A that Intel is using in products like Panther Lake and Xeon 6+, promising a 9% improvement in performance at the same power, or an 18% reduction in power consumption at the same performance level. In addition to greater technical detail, Intel has revealed that 18A-P has entered risk production.

If you’re unfamiliar with that term, it’s the stage of semiconductor manufacturing just before high-volume mass production. It’s a low-volume manufacturing stage where Intel will produce full wafers of 18A-P on a standard production line, just with a limited scope to gather data on defect rate, performance, and variability before full production begins. Risk production usually leads mass production on advanced logic by 12 to 24 months, though we’re not dealing with an entirely new node here, so expect a tighter timeline.

18A-P is a revision of 18A, and although it carries new transistor designs (more on those soon), they live in the same libraries at cell heights of 180mm (High Performance) and 160mm (High Density). The new process is backward compatible with 18A designs, meaning designers can port to 18A-P without making any changes. Some of the new transistor options could spur a design change, but it’s not required; anything built on 18A can be built on 18A-P with more minor performance benefits, but no design changes.

For performance, Intel arrived at its numbers by testing on a standard Arm core subblock, noting the 9% frequency increase or 18% reduction in power specifically at 0.75 volts. The chart you can see in the gallery below is a beautified version of a chart published in Intel’s original research; in other words, it’s not just random lines without any correlation. You can see that even as voltage moves outside that 0.75V mark, 18A-P retains a frequency/power improvement.

With 18A-P, Intel is adding three transistor designs to its library. The W1 design is available in the 180mm cell height library (it was previously available in the 160mm library), while W1.5 is available in the 160mm library. The enhanced W3P design is available in both libraries. W1 and W1.5 are both narrow designs optimized for low-power usage, helping fill gaps in power-optimized designs in Intel’s library, while W3P is a new dual-contact transistor with “Power Boost,” as Intel calls it. As you can see in the gallery below, the original W2 and W3 designs still see a boost in ring oscillator frequency (moving an electrical signal through a ring of inverters) with 18A-P.

W3P is the most interesting design due to Power Boost. 18A already uses backside power delivery with PowerVia, which uses the back of the wafer to route power, freeing up space for front side signal wiring and reducing thermal resistance. The W3P design has contacts on the front side and backside, reducing parasitic resistance and enabling higher drive current to speed up switching.

Although the standard W2 and W3 transistors will see a benefit moving from 18A to 18A-P, it’s minor. The biggest frequency improvement comes from W3P, while W1 pushes 18A-P down to lower capacitance levels for energy-optimized designs.

Intel is also adding a new VT (threshold voltage) pair to its lineup. Typically, we see four flavors of VT pairs: HVT, SVT, LVT, and ULVT, noting high, standard, low, and ultra-low threshold voltage, respectively. The lower the threshold voltage, the less power a transistor needs to activate, and therefore the more power it leaks. So, ULVT transistors are the most performant, but they leak the most power, while HVT transistors are the least performant but leak the least amount of power. Chip designers need to balance these different flavors of threshold voltage for their application.

The new VT pair adds another option: ULVTLL, or Ultra-Low Voltage Threshold Low Leakage. It lives between ULVT and LVT, offering better performance than LVT but lower leakage than ULVT. Like the new transistor design, it gives designers more flexibility when designing a chip for 18A-P.

In addition to the expanding 18A-P’s capabilities, Intel says the revision comes with a 20% to 40% improvement in thermal resistance, as well as a 10% to 30% improvement in via resistance at “perf critical layers.” The reduction in thermal resistance comes from grinding the wafer down with advanced EDA tools for better thermal conductivity.

Intel 18A is currently ramping in two U.S. fabs, and although the company has taken some heat for poor 18A yields, Intel says that defect rates continue to drop along with its expectations. 18A is being used already in Panther Lake and Xeon 6+, and Intel is reportedly in talks with Apple and Nvidia to build on 18A, as well.

Full presentation

SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm, tighter than the 36nm pitch shipping in Intel’s Panther Lake chips on 18A. The analysis was conducted on a HiSilicon Kirin 9030, the processor found inside Huawei’s Mate 80 phones and built on the N+3 process, which SemiAnalysis says trails Intel’s 18A high-density library by 38%. The SemiAnalysis Teardown Engineering & Evaluation Lab (STEEL) has been opened in Hillsboro, Oregon, and built to take on TechInsights in advanced-node reverse engineering.

A 36nm pitch is what Panther Lake ships with, but the 18A process on the whole supports a 32nm minimum metal pitch. With Panter Lake, Intel opted to relax the pitch because routing power through the back of the wafer — via PowerVia — clears the front-side metal stack for signal wiring.

Intel has said doing this buys roughly 10% higher density and looser front-side pitches, which is how a node built on GAA RibbonFET transistors and backside power can ship a wider local pitch than a DUV Chinese process and maintain a wide overall lead. SMIC reached 32.5nm without EUV lithography, leaning on DUV tools and quadruple-patterning that needs extra masking and etch passes.

Counting transistors per area, SemiAnalysis put N+3 at 113.4 million per square millimeter, just ahead of TSMC's mature N6 at 107.7 million and well behind 18A. SMIC got there by spending every density trick available without EUV: two fins per transistor, contacts landed directly over the active gate, and single diffusion breaks between cells.

Each of those workarounds obviously adds complexity and cost, with N+3’s ceiling ultimately showing a huge trade-off. The Kirin 9030 Pro's prime core runs at 2.75 GHz and lands near Arm's 2021-era Cortex-X2 per clock, leaving the chip roughly level with Android flagships from three years ago and behind current parts from Apple, Qualcomm, MediaTek, and Samsung. Huawei’s roadmap does say that it’s targeting 5 GHz by 2031, but, as SemiAnalysis notes, that’s “far beyond what planar scaling alone could deliver.”

SemiAnalysis said it spent the past 18 months building the lab and has already earned revenue analyzing datacenter silicon. “We have already generated revenue on advanced datacenter chip teardowns, including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack.”

The company is taking aim at the Ottawa-based TechInsights, which is backed by private equity and held by the likes of Oakley Capital and CVC Growth. SemiAnalysis claims its rival is up for sale and has underinvested in equipment as a result, though that hasn’t been officially confirmed. The teardown also found the Kirin 9030 Pro carrying Samsung LPDDR5X memory, with 16 GB variants turning up DRAM from Chinese maker CXMT as well.

The race is on to build the massive chip packages that power the future of AI, with some technologies being developed to produce a single chip that houses a monstrous 58 chips in one unit. But the future pathway to those sorts of massive chips isn't entirely agreed upon yet, as learned at TSMC's recent European Technology Symposium that we attended.

Although panel-level packaging technologies are set to enable much larger chip packages, they will not provide, at least initially, the same interconnection densities as today's wafer-level packaging technologies like CoWoS, according to Kevin Zhang, TSMC’s senior vice president of business development and global sales and deputy co-COO.

"The geometry complexity panel-based process has to deal with is nowhere near the wafer level technology capability," Zhang said. "CoPoS, I would say it is one way to basically using panel-based process to continue driving the interposer scaling."

One of the common misconceptions in the semiconductor industry is that panel-based chip packaging technologies will replace existing wafer-based technologies like CoWoS as they promise to enable considerably larger package sizes — think 310mm×310mm, up from existing 120mm×150mm — at lower costs. This is not the case, though, according to TSMC.

"That is an option on the table," Zhang said. "But remember, if you look at our CoWoS roadmap, we still have a lot of runway left with wafer-level technologies. We can scale CoWoS all the way to 14X using wafer-level processes, and we also have wafer-level integration. […] You can integrate 58 large reticle-sized dies together. So, there is still plenty of room for us to continue advancing wafer-level integration. At the same time, our team always wants to make sure we evaluate all future options. Obviously, one of those options is panel-based packaging."

But panel-level packaging cannot leverage the tools currently used for wafer-level packaging, as essentially technologies like CoWoS use the same lithography, etching, deposition, and other tools that were previously used to make logic chips. By contrast, panel-level integration tools are considerably less advanced.

 "From technology point of view, wafer-level-based process is far more advanced than panel," Zhang said. "I am not talking about just TSMC, I am talking about the industry as a whole. Wafer-level processing is where the most advanced manufacturing technology exists today. To move to panel-based manufacturing, the industry needs to improve panel processes rapidly so they can eventually offer a better next-generation solution relative to wafer-level technology."

In fact, the main advantage that panels have over wafers is indeed larger package size: currently, TSMC can use 120mm×150mm substrates, next-generation CoWoS technologies will enable 150mm×250mm substrates, but even substrates the size of a hardcover book look pale compared to the initial 310mm×310mm panels. Furthermore, future packages can get to 515mm×510mm or even 750mm×620mm, which is larger than a wafer. When asked specifically whether CoPoS will complement CoWoS rather than replace it, Zhang essentially answered positively.

 "I think that may be a way to look at it because it depends on the specific product configuration," Zhang said. "At some of the product will continue to get optimum benefit by leveraging wafer-level processing capability. Our goal is to offer our customer all the options they would need in order to find the optimum solution for their next-generation product. CoWoS today [has a lot of] scaling room for us to continue to drive this technology forward. But at the same time, we are looking at a fan-out-based process, some use the word CoPoS, as another alternative path going forward."

TSMC is currently expected to complete its first CoPoS pilot line this June. The gap between pilot and meaningful production is often around two or three years, so a reasonable expectation for high-volume manufacturing (HVM) using CoPoS would be 2028 – 2029. However, keeping in mind that CoPoS uses new tools and since the peculiarities of these tools are unknown, it is more reasonable to expect the first CoPoS-based products in 2029 or 2030, with more meaningful volumes sometime in the first half of the next decade. At the end of the day, CoWoS existed for years before explosive adoption, so CoPoS will likely repeat this pattern.

When we referred to TSMC just several years ago, we called it 'the world's largest foundry,' implying that Intel was still the world's largest producer of advanced logic chips. However, having spent nearly $240 billion on capacity expansion over the last 10 years, TSMC now has nine sites with dozens of 300-mm fabs, many of which can process orders of magnitude more wafers using EUV-based process technologies than Intel*, which makes TSMC the world's largest maker of advanced logic chips.

Being the world's largest maker of advanced AI processors requires TSMC to stay ahead of its rivals, Intel and Samsung Foundry, both in terms of process technologies and, perhaps, even more importantly, in terms of production capacity.

Therefore, TSMC has kicked off the most aggressive manufacturing expansion in its history as the company races to meet explosive demand for AI processors, logic chips made on leading-edge nodes, and advanced packaging.

During TSMC's Tech Symposium 2026 manufacturing presentations, the company revealed that in 2025 – 2026, it effectively doubled its historical construction pace, building or converting nine fab phases annually, up from an average of four phases per year. The company is simultaneously building or ramping new fabs in Taiwan, the U.S., Japan, and Germany. In addition, it introduces new ways to improve the productivity of existing facilities.

N2 ramp: Six-figure amounts of wafers per-month by 2029

The central part of TSMC's expansion plan is its N2 process technology. At present, the company is ramping up production of chips using N2 at two sites: Fab 20 phase 1 and phase 2 in Hsinchu near TSMC's global R&D center, and Fab 22 phase 1 in Kaohsiung. Ramping a leading-edge node at three facilities simultaneously is highly uncommon for foundries. The company also plans to ramp up production at Fab 22 phase 2 shortly and Fab 22 phase 3 by the end of the year. Eventually, Fab 22 phase 4 will come online as well. As a result, TSMC aims to start mass production on its N2 process technology at five facilities in the first year, which is at an unprecedented scale.

As a result of such an aggressive ramp, TSMC expects its N2 wafer-out capacity to be 45% higher than that of N3B in the first year. Reports from 2023 – 2024 indicate that TSMC ramped its N3B production at two or three phases of Fab 18 in 2023 and reached a capacity of around 60,000 wafer starts per month by the end of that year. If the reports are accurate, then TSMC expects its N2 capacity to reach around 90,000 wafer starts per month (WSPM) by the end of the year. This exceeds the fully ramped capacity of Intel's 18A-capable Fab 52, which is believed to be at around 40,000 WSPM.

What is even more impressive is that TSMC intends to increase its N2/A16-capable capacity by 70% every year through 2028, which means hundreds of thousands of WSPM in 2029.

In addition to reaching vast capacity, ramping up five fab phases simultaneously enables TSMC to mitigate risks. If one fab phase experiences a contamination issue, tool failure, or yield issues, the entire N2 supply chain will not collapse. The same applies to ramping up production at two sites located in different parts of the country: an earthquake or utility failure can interrupt production or even cause yield loss at one of them, but it will not affect another. Such risk mitigation is critically important when customers like Apple, AMD, Nvidia, or Qualcomm, which demand a continuous supply. There is potentially another bonus with ramping up these fab phases in parallel rather than in serial, so read on.

N2 ramp: One Team and the Super Manufacturing Platform

Such an unusual ramp strategy seems to be enabled by two programs at TSMC: the "One Team" collaboration between R&D and fab operations, and the Super Manufacturing Platform (SMP) that enables multiple fabs (or rather fab phases) to work as one, which likely has similarities to Intel's "Copy Exactly." TSMC hasn't shared many details about the One Team and SMP, though we can make some educated guesses.

The One Team is a global manufacturing knowledge-transfer system that links R&D, process integration, equipment management, and high-volume manufacturing expertise during technology development and ramp-up. To speed up feedback loops, TSMC likely inserts manufacturing teams relatively early in node development so that R&D teams adjust their work to what is possible at fabs. As a result, yield learning, process optimization, and tool productivity improvements can be done quickly at one fab and then transferred to others. TSMC says that One Team enabled a 20% faster technology transfer compared to N3, without disclosing the time it typically takes to transfer technology from one fab to another.

In addition, all of TSMC's GigaFab sites now rely on its Super Manufacturing Platform (SMP), which is essentially a centralized manufacturing-control system that makes multiple fabs operate as one giant synchronized fab with standard process recipes, tool configurations, metrology, and yield management flows. This should enable TSMC to transfer production between fabs more easily, ramp new nodes faster, introduce yield fixes globally instead of locally, and reduce customer requalification work when production of chips is moved from one fab to another.

Moreover, since every fab phase generates its own tool behavior data, defect density data, process window statistics, and yield learning information, multiple simultaneous ramps may actually accelerate yield/defects learning when SMP and One Team are in place. In turn, it may speed up ramping of fab phases.

A 70% CAGR in N2/A16 capacity in the coming years is an extraordinarily aggressive ramp for leading-edge manufacturing. Without something like TSMC's' One Team structure and SMP, coordinating that scale of expansion across multiple Fab 22 phases, Fab 20, and eventually Fab 21 phase 3 in Arizona would be barely possible both from organizational (operational control) and from economic (yield learning, process window, etc.) points of view.

TSMC also noted that despite the significantly higher complexity associated with gate-all-around (GAA) nanosheet transistors, N2 is achieving a better yield learning curve than N3, which again can be attributed to the innovative approaches that the company uses.

Beyond N2: A14, A13, and A12

TSMC's N2/N2P/N2X/N2U/A16 production will largely be concentrated at Fab 20 phase 1 and 2, Fab 22 phases 1, 2, 3, 4, and, to some degree, Fab 21 phase 3. However, for nodes beyond 2nm-class (A16 is essentially N2P with a backside power delivery network), such as A14, A13, and A12, TSMC will build Fab 21 phase 3 and then the all-new Fab 25 site in central Taiwan with at least four phases.

A14 is set to start high-volume production in late 2028, so there is a good chance that TSMC will ramp it at both Fab 20 phase 3 and Fab 25 phase 1. However, given the company's aggressive approach to capacity expansion, TSMC might well surprise us once again. Also, we do not yet know how TSMC plans to upgrade N2/A16-capable fabs to subsequent nodes, if at all.

Expansion beyond N2

The expansion is not limited to the N2 production node and subsequent technologies. TSMC is continuing to grow combined N3 and N5 capacity at a 25% compound annual growth rate (CAGR) from 2022 through 2027. To address immediate demand, the company is converting some N5 capacity into N3 production, which is not particularly expensive, since N3 reuses 85% - 90% of the tools used for N5. Furthermore, as much of TSMC's N3 and N5 capacities are concentrated at Fab 18 (four phases N5, four phases N3), converting some of the N5 capacity to N3 is relatively easy from a logistical perspective.

AI is here to help (to build more AI processors)

Alongside the conversion of N5 to N3 capacity, TSMC also heavily uses AI to improve the performance of each tool, and the whole fab in particular. Essentially, TSMC uses AI to build more AI processors, which seems to be a paradox, but it is becoming popularized as AI becomes embedded within workflows.

One of the things that greatly slows down cycle times of modern fabs is batch processing of wafers in various chambers, something that is an inevitable part of some 5,000 steps. Essentially, 25 wafers ‘wait’ in a (perhaps in a CVD chamber) for a lithography tool to process them individually.

Atsuyoshi Koike of Rapidus thinks differently and believes that a single-wafer processing across all steps can significantly speed up cycle time, but at the cost of tool efficiency. TSMC does not seem to plan to use single-wafer processing (despite its purchasing power, it can likely persuade fab tool makers to produce appropriate tools), but it can certainly optimize the ways in which it uses existing tools to boost the productivity of its existing fabs.

TSMC revealed at its recent Technology Summit that it uses intelligent scheduling systems that incorporate 'state-of-the-art linear programming and heuristic algorithms' to optimize equipment efficiency, though it did not reveal what exactly is done and what is achieved. TSMC further revealed that it uses generative AI algorithms to identify optimal parameters that 'challenge the physical limits of equipment' while maintaining wafer quality. In parallel, the company analyzes tool logs using big-data analytics and text-mining systems to dynamically adjust key parameters, minimize tool idle time, and maximize output.

AI systems are also used for real-time chamber condition analysis to determine optimal chamber-cleaning timing and avoid unnecessary maintenance that could reduce machine uptime and available capacity. In addition, TSMC disclosed that AI-assisted comparison and fine-tuning of large volumes of machine verification parameters reduced the time required to validate new tools and reach high-volume manufacturing by more than 20%, which helps to ramp up new fab modules faster.

TSMC also said it achieved more flexible allocation and higher combined N3 and N5 capacity at Fab 18 in Tainan by increasing equipment commonality and integrating 'cross-technologies planning,' which essentially means that the company re-uses as many tools as possible.

Expansion beyond Taiwan

Outside of Taiwan, TSMC continues to broaden its geographic footprint. In Arizona, Fab 21 phase 1 is already producing chips using N4 technology (with capacity increasing by 1.8X this year alone), while Fab 21 phase 2 is on track to start N3 production in Q3 2027. Fab 21 phase 3 targets N2 sometime later this decade, as the company continues to construct shells both for phase 3 and phase 4. The company also reaffirmed plans for an advanced packaging facility, an R&D center, and additional land acquisitions to support future expansion.

In Japan, the company’s Kumamoto Fab 23 phase 1 is already producing 28nm and 22nm chips, while Fab 23 phase 2 underwent a major strategic shift. Originally planned for 7nm-class production, the facility will instead manufacture using technologies down to N3 3nm to address stronger-than-expected local demand and onshoring intentions of local chip designers.

Meanwhile, Fab 23 in Dresden, Germany, which is under construction, is aimed at automotive and industrial applications with legacy planar transistors and FinFET-based 28nm, 22nm, N16, and N12 production nodes.

Advanced Packaging

AI itself is now one of the main drivers behind the company's unprecedented capacity growth. TSMC disclosed that wafer shipments for AI accelerators are expected to rise 11X between 2022 and 2026. The company also highlighted the rapid growth of extremely large dies exceeding 500 mm^2, as shipments of those devices are projected to increase 6X over the same period. Such products typically require lots of wafer capacity (wafer starts) and advanced packaging technologies, since many of these designs use HBM3E memory.

Advanced packaging has therefore become just as important as wafer fabrication itself. TSMC said its CoWoS capacity will grow at an 80% CAGR between 2022 and 2027, while SoIC capacity will expand at a 90% CAGR during the same timeframe. TSMC also said it has improved development-to-HVM transition times by 30% for CoWoS and by 75% for SoIC compared to earlier generations.

TSMC currently operates 11 advanced packaging facilities in Taiwan (AP1 in Hsinchu, AP2A/AP2B/AP2C and AP8 in Tainan, AP3 in Longtan, AP5 in Taichung, AP6A/AP6B/AP6C in Zhunan, and AP7 in Chiayi). According to a recent DigiTimes report, the company is simultaneously expanding multiple advanced packaging campuses, including AP5, AP6, AP7, and AP8.

The AP7 site in Chiayi will reportedly become TSMC's largest advanced packaging campus using SoIC to support major customers like Nvidia, which plans to use 3D packaging technologies for its next-generation Feynman GPUs. AP8 — converted from a former Innolux LCD fab — is expected to exceed 40,000 wafers per month of CoWoS capacity by late 2026.

While CoWoS is the de facto standard for AI processors, SoIC is set to become much more widely used in the coming years. As a result, the company is also rapidly expanding its SoIC production capacity. DigiTimes claims that AP6 in Zhunan could approach 10,000 SoIC wafers per month, whereas AP7B may add approximately 12,000 wafers per month. Future AP7 phases are expected to support both SoIC and CoPoS technologies, though CoPoS is a part of TSMC's roadmap in the 2030s.

Advanced packaging now requires tight ecosystem integration that includes HBM suppliers, substrate vendors, OSAT partners, testing companies, materials providers, and toolmakers, with which TSMC works to standardize those tools. The very emergence of such an ecosystem emphasizes the increasing role of TSMC in the burgeoning AI industry.

An all-encompassing roadmap

After investing nearly $240 billion into capacity expansion over the last decade, TSMC has evolved from the world’s largest foundry into the world's largest producer of advanced logic chips, producing the lion's share of AI processors today.

To support the explosive AI demand and to stay ahead of Intel and Samsung Electronics, TSMC has doubled its historical fab construction pace to nine fab phases annually in 2025 – 2026 while simultaneously expanding in Taiwan, Arizona, Japan, and Germany. The company's N2 ramp is unprecedented as the company preps to ramp five fab phases within the node's first year, and N2/A16 capacity is projected to grow at a 70% CAGR through 2028.

TSMC said this aggressive expansion is enabled by its One Team organizational structure and Super Manufacturing Platform (SMP), which synchronizes manufacturing, yield learning, and process control across multiple fabs. The company is also implementing various AI-driven manufacturing optimizations, including intelligent scheduling systems, generative AI process tuning, and real-time tool analytics to improve throughput, reduce cycle times, and accelerate tool qualification.

At the same time, TSMC is rapidly expanding advanced packaging capacities. The company intends to increase CoWoS and SoIC capacities at 80% and 90% CAGR, respectively, through 2027, as demand for both technologies is expected to grow as chiplet-based designs and HBM memory are technologies of choice for AI accelerators.

*TSMC's wafer processing revenue for 2025 was $103,708.5 billion, thus representing around 84% of consolidated revenue of $122.4 billion. EUV-based N3 and N5 process technologies accounted for 60% of TSMC's wafer revenue in 2025, thus earning around $62,225 billion. Intel Foundry earned $17.826 billion in 2025, $307 million came from external customers that mainly ordered advanced packaging. It is estimated that process technologies that use EUV account for more than 10% but less than 20% of Intel's wafer revenue.

Intel does not disclose a revenue split similar to TSMC's (wafer fabrication vs. packaging/testing vs. other) in its official filings, so its wafer processing revenue is hard to estimate, especially given the fact that some of its silicon is made at TSMC and is packaged internally. Nonetheless, even 20% of Intel Foundry's 2025 revenue is $3.565 billion, which is over 17 times less than TSMC earns on its EUV-based nodes.

Chinese semiconductor start-up Prinano announced that it has successfully validated the mass production of photonic chips without using the industry-standard lithography equipment. According to an SCMP report, the company said in a WeChat post on Friday, June 5th, that it had made 8-inch optical chip wafers in collaboration with Shenzhen Litra Technology. The company said it achieved this while “completely avoiding” the need for deep-ultraviolet lithography (DUV), a significant breakthrough in China’s push to reduce its dependence on ASML lithography tools, which remain subject to export restrictions.

Instead of conventional optical lithography, Prinano said it used its PL-AS vacuum air-cushion nanoimprint lithography (NIL) system, which, according to the company, can reduce manufacturing costs to roughly one-tenth that of traditional DUV-based processes, while supporting wafer-level production of photonic chips.

Modern chips are typically produced using highly sophisticated DUV or more advanced EUV (extreme ultraviolet) systems that project circuit patterns onto silicon wafers using light. These machines contain some of the most complex optics ever built and can cost hundreds of millions of dollars. Nanoimprint lithography takes a very different approach. Rather than projecting patterns using light, it physically presses nanoscale structures into a specially prepared resist layer, basically stamping microscopic patterns directly onto the wafer surface. This process eliminates the need for many of the expensive optical systems required by conventional lithography equipment.

Nanoimprint lithography has long been viewed as a potential alternative to conventional optical lithography because of its potential for lower costs and extremely high pattern resolution. However, despite its promise, the technology has struggled to achieve widespread adoption in semiconductor manufacturing due to concerns about defect rates, template wear, throughput, and production yields, all of which become increasingly important in high-volume manufacturing environments.

Founded in 2017, Prinano has spent the past several years working to overcome those limitations by developing its own nanoimprint lithography ecosystem. The company took a significant step in 2025 when it announced the delivery of what it described as China's first semiconductor nanoimprint lithography system to a domestic customer, marking an early effort to commercialize the technology.

The company's latest announcement suggests it may have progressed beyond equipment development and pilot deployments. According to Prinano, its PL-AS vacuum air-cushion nanoimprint lithography platform incorporates wafer-level pressure control, customized double-layer imprinting materials, and proprietary process technologies capable of producing sub-10-nanometer features. The company now claims those developments have enabled the successful validation of wafer-scale photonic chip production on 8-inch wafers.

Importantly, Prinano is not attempting to replace the production of cutting-edge processors or AI accelerators. Instead, the company's announcement focuses on photonic chips, a category of semiconductors that manipulate light rather than electrical signals. These devices are widely used in fiber-optic communications, data center interconnects, sensing systems, and LiDAR technologies.

Photonic chips are considered particularly well suited to nanoimprint lithography because many of their critical structures, including waveguides, gratings, and ring resonators, consist of repeating nanoscale patterns that can be replicated efficiently through imprinting techniques. This characteristic makes them a more practical near-term application for NIL than advanced logic chips, where defect rates and alignment requirements are far more demanding.

Another noteworthy detail is the use of 8-inch wafers. While leading-edge processors are increasingly manufactured on larger 12-inch wafers, 8-inch wafers remain widely used across specialized sectors such as compound semiconductors and power electronics. Demonstrating production on full 8-inch wafers suggests the process has moved beyond laboratory-scale demonstrations and into a format more compatible with commercial manufacturing.

The development also highlights China's broader search for alternative semiconductor manufacturing pathways amid ongoing export restrictions. Access to advanced lithography equipment from ASML — required for EUV and DUV — has been increasingly constrained under US-led controls, prompting Chinese companies to explore alternative approaches ranging from advanced packaging technologies to new chip architectures and novel manufacturing methods. Huawei recently announced a new LogicFolding chip architecture that allows the company to develop high-performance processors without relying on restricted EUV lithography machines.

Significant questions remain about Prinano’s announcement. While the claims have been validated in mass production, the company did not disclose production volumes, yield rates, defect densities, customer shipment data, or independent third-party validation. These metrics are critical for determining whether a semiconductor manufacturing technology is commercially viable rather than merely technically feasible.

TSMC CEO C.C. Wei has told company shareholders that it still won’t be able to completely address the production demands for AI chips in the years to come. Even though the company has opened multiple fabs across the world, including the one in Arizona, the insatiable demand for the most advanced processors means that there still isn’t enough production capacity to go around for all customers. Bloomberg reports that the additional capacity that is expected to go online in the U.S. is still not enough to feed the increasing demand from hyperscalers.

“It will be a long time before we can meet customer demand,” C.C. Wei said. Despite that, TSMC is still forecasting a 30% increase in sales this year. It’s also not taking advantage of the supply bottleneck, with Wei adding that the company will avoid sudden price hikes similar to the memory and storage chip market industry’s experience to ensure business stability.

Hyperscaler buildouts are expected to hit $725 billion just this year. And unless the AI bubble bursts, demand is only expected to go up every year. TSMC has been building many new fabs in Taiwan, the U.S., and other parts of the world. But building these manufacturing plants would take years, and it seems that semiconductor manufacturing demand would outpace supply if the current AI infrastructure build-out continues.

TSMC Arizona’s manufacturing capacity has been sold out through 2027 since early 2025, showing the massive demand for the company’s output. The company is continually expanding this site, too, with its Taiwan headquarters authorizing a $20 billion capital injection last month to continue the development of Fab 21 phase 2. It’s expected that this would allow the company to start mass producing 3nm chips in Arizona in 2027, which is about a year earlier than the original 2028 launch date. There have also been reports of additional fabs and other units, bringing the total Arizona site to 12 fabs, 4 packaging facilities, and an R&D center.

These production shortages mean that TSMC can expect that their expansion plans will have customers once they’re completed. However, this is also an opportunity for Intel, which is trying to win customers for its 18A and 14A processes. Both Apple and Nvidia are reportedly considering Intel for some of their 2028 chip production, and sources say that the former has already reached a preliminary agreement with Team Blue.

The lack of availability has also led Elon Musk into semiconductor manufacturing. Even though building chips is a totally different beast when compared to building electric cars and even rocket ships, it seems that the billionaire founder is ready to take on the challenge with Terafab. It seems that he’s pretty serious, too, with his team already in talks with various suppliers and that they’re willing to pay a premium to ensure priority.

Samsung displayed its first physical mockup of HBM5 memory at Computex 2026 in Taipei. Tom's Hardware dropped by to see its pairing of the eighth-generation AI memory with a new in-package cooling structure it calls Heat Path Block, or HPB. Just last week, rival SK hynix unveiled its own iHBM thermal design, meaning both companies are now focusing on the same heat bottleneck in the die-to-die interface that connects memory to the processor. Samsung also confirmed that it’ll fab HBM5’s base die on its in-house 2nm process, down from the 4nm node used for HBM4 and HBM4E.

Rather than letting heat escape outward through the core dies, HPB builds a separate set of thermal pillars that pull heat from inside the stack and carry it to a spreader sitting above or beside the package, according to Samsung at Computex.

The design concentrates on the D2D PHY layer, the high-speed link between the HBM base die and the GPU, where power density and temperatures increase exponentially as stacks grow taller and run quicker. Samsung said it has already implemented and verified HPB on HBM4E, the generation whose first 12-layer samples it began shipping last month at 14 Gbps, scaling to 16 Gbps, with 3.6 TB/s of bandwidth per stack.

Samsung runs both a memory business and a logic foundry, letting it build the HBM5 stack and the 2nm die beneath it in-house. "AI systems are becoming more powerful and densely integrated, making heat management, data-processing efficiency, and packaging stability just as important as memory performance itself," Song Jai-hyuk, president and CTO of Samsung's Device Solutions division, told reporters at Computex, according to the Korea Herald. Song said the company would keep building its competitiveness in next-generation memory through cooperation with partners, including Nvidia.

Last year, a roadmap from KAIST projected HBM5 reaching a 4,096-bit interface, roughly 4 TB/s per stack, and about 100 watts of per-stack power, a thermal load that goes a long way in explaining why both Korean memory giants are reworking their packaging now rather than at launch.

SK hynix faced the same problem via a different route. Its iHBM design embeds cooling elements made of electrically non-conductive, thermally conductive silicon into the D2D PHY layer, which the company said cuts thermal resistance by more than 30% against current products.

SK hynix has opted to place a cooling element directly at the hotspot, while Samsung has built a route to evacuate heat away from it. Both methods are slated to debut with HBM5, but it’ll be a little while before we see either in action, as neither company expects it to reach mass production before 2028.

South Korean media has noted a surge in spending on luxury goods following big bonus payouts to semiconductor workers. For example, the Chosun Daily (machine translation) reports that luxury consumption in southern Gyeonggi Province, where the nation’s 'Semiconductor Belt' is located, has rocketed. In one local department store, some luxury goods category sales are up nearly 150%. The flood of cash and spending shows that towns in Gyeonggi Province are now enjoying their own 'Gangnam Style.'

The Korean news source provides some interesting stats showing the rapid increase in conspicuous consumption since the fab workers at Samsung and SK hynix earned their envy-inducing bonuses. At a department store/mall called Shinsegae South City, located in Yongin, Gyeonggi Province, luxury jewelry sales in May were up 146.3%, it says. Moreover, luxury watch sales rose 85.3%.

Chosun Daily also shared some retail stats for the Lotte Department Store Dongtan Branch (also in Gyeonggi Province). It says that from Jan 1 to May 27, 2026, luxury sales were up 40% compared to the same period last year. A breakdown of these figures shows customers didn’t just target luxury brands but big-ticket home appliances (a category up 30%). A statement from this department store shows they are aware of the economic driving force behind the spending on luxury goods. "Sales of high-end goods such as luxury and home appliances have increased due to the boom in semiconductor companies, the creation of advanced industrial clusters, and the move-in of new large apartment complexes," said a store statement.

It was a similar story at The Hyundai Department Store, Pangyo Branch (also in Gyeonggi Province). Here, luxury goods sales were up 46.1% in May. That compares with an increase observed across all Hyundai Department Store stores nationwide of about 32%. High-end watches and jewelry (66%) and high-end clothing brands (36.9%) were major contributors to the sales boom.

With locals snapping up luxury goods like kids picking up candy, the semiconductor boom in South Korea looks like it will be highly beneficial to mostly European brands like Chanel, Hermès, Prada, Gucci, Rolex, Cartier, etc.

Recent reports suggest the good times are rolling at SK hynix, where workers are tipped to receive bonuses of up to $900,000 next year, on top of $447,000 this year. It's good to see the huge influx of RAM and NAND cash not just going to Samjeon Nix (Samsung Electronics, SK hynix) corporate accounts, or one or two billionaires, but that the good times are being shared with those at the coal face.

Thousands of SK hynix employees fled their factory stations earlier today as a fire broke out in a room where fluorine gas was used. Yonhap News reports that seven of the workers have been hospitalized, five are being treated for eye irritation, and two are under observation (machine translation). At the time of writing, a cleanup operation appears to be continuing at SK hynix’s Cheongju 4th campus, with all 3,600 employees evacuated. A company official told Yonhap, “There are no issues with equipment operation, so there will be no production disruption.”

Reports indicate that the fire began at around 10.23 am Korean time today. An unintentional fire is probably not a great thing anywhere in an advanced semiconductor fab, even in the burgers and cigars wing. However, in “the gas room on the 6th floor connecting the M15 and M15X factories at SK Hynix's Cheongju 4th campus,” it could have been a particularly nasty incident. This room includes equipment/canisters/pipelines holding highly toxic fluorine gas.

According to the Korean news source, the fire in the gas room was extinguished immediately by sprinklers, but fluorine escaped into the room at a concentration estimated to be 5 ppm. This is where the seven hospitalized workers had been situated.

Fluorine gas is used in various industrial processes, but it is a highly reactive gas that can cause spontaneous combustion or explosions if it comes into contact with common materials. It is also quite deadly to humans. Wikipedia states that “significant irritation of the eyes and respiratory system as well as liver and kidney damage occur above 25 ppm… The eyes and nose are seriously damaged at 100 ppm… and inhalation of 1,000 ppm fluorine will cause death in minutes.”

Official insists there will be “no production disruption”

With the immense demand and pressure on memory-making titans like SK hynix, some may be concerned that a facility like Cheongju closing even for a few hours could impact supplies, schedules, pricing, and more. However, an official insisted, “There are no issues with equipment operation, so there will be no production disruption.” It was also suggested that the fire/leak occurred in the gas pipeline, but that fact had yet to be determined.

At the time of writing, there may still be environmental purification and repair work to do. If and when that’s completed, operatives will begin safety inspections, including air quality measurements. After the all-clear, “we plan to return the employees,” the official told Yonhap. We’ve linked to the latest report on this incident available at the source.

TikTok owner ByteDance is reportedly developing its own custom AI CPUs in a bid to reduce its reliance on US chipmakers. Per a Reuters report, ByteDance's new chip is inspired by Groq's "language processing units," a fancy term for a chip optimized for inference tasks — running AI models instead of training them. The move comes in a context where inference-heavy agentic AI is quickly becoming the new normal. The project is seemingly in the concept and design stage, with Reuters' sources claiming that ByteDance is evaluating both Arm and RISC-V designs.

Additionally, The Information claims ByteDance is partnering with Chinese startup InnoStar Semiconductor for memory technology related to the project, potentially obviating the need to acquire rare and expensive HBM chips from Samsung and the like. The Chinese startup got investments from ByteDance and Alibaba, China's cloud and e-commerce giant.

However, ByteDance doesn't appear to have its own chip design teams, and will purportedly rely on "several external partners", who are expected to also take care of the actual silicon manufacturing. The firm's CPU project takes place against a geopolitical tussle that got China's government banning the purchase of Nvidia H200 Blackwell chips, after the Trump administration backtracked on its technological export controls.

This is hardly ByteDance's first rodeo with investing in its own technology, too, as it started designing its own SeedChip AI accelerator with TSMC back in 2024, a silicon slab expected to tape out and be mass-produced this year still. For now, the expectation is that ByteDance will use hybrid architectures for its servers as dependence on Nvidia is still an unfortunate necessity, but over time, it wouldn't be surprising to see the firm waving goodbye to the back of Jensen Huang's leather jacket.

Furthermore, much like any other advanced chip vendor these days, Intel and AMD reportedly keep increasing prices every quarter as they hold the lion's share of the CPU market. Nvidia's recently unveiled Vera chips show great promise, but once again, we're talking about a U.S. firm. Although Bytedance is best known for TikTok, the world's leading short-form video app, the company runs China's AI chatbot app Doubao and has a handful of AI models under its belt.

The global foundry market is dominated by TSMC, which captured 69.9% of global foundry revenue in 2025, but beyond the glitz and glamor of the leading edge sit a tier of foundries that collectively manufacture the chips found in cars, power supplies for AI servers, RF front-end modules, display drivers, industrial controllers, and defense systems. GlobalFoundries, UMC, and SMIC posted a combined 2025 revenue of roughly $24 billion and hold approximately 13.5% of the global foundry market between them.

Each is pursuing a fundamentally different strategy shaped by geography, regulation, and technology choices. GlobalFoundries is becoming a U.S. and European specialty foundry, backed by $1.575 billion in CHIPS Act funding and a $3.1 billion Department of Defense contract.

Meanwhile, UMC is bridging from pure mature-node services into 12nm FinFET territory through a manufacturing partnership with Intel, and SMIC is China's de facto national champion, expanding mature-node capacity at enormous scale while pushing the limits of what DUV lithography can achieve under tightening export controls. We break down each of these trailing-edge foundries to see what might be coming up next.

GlobalFoundries

GlobalFoundries (‘GF’) exited leading-edge development in 2018 when it canceled its 7nm program and has since repositioned as a specialty foundry focused on differentiated process platforms. That strategy produced FY2025 revenue of $6.79 billion (up 1% year-over-year), with Q4 gross margin of 27.8% and full-year operating cash flow of $1.73 billion. The company's automotive segment hit a record $1.4 billion, up 17% year-over-year, according to its SEC filing.

Its current node portfolio runs from 12LP FinFET down to 180nm and spans several specialty platforms. The company's flagship is 22FDX, a 22nm fully depleted silicon-on-insulator (FD-SOI) process targeting ultra-low-power IoT, automotive radar, millimeter-wave 5G, and microcontrollers with embedded MRAM support. Meanwhile, 45RFSOI is the dominant global platform for 5G RF front-end modules. Below those sit 28nm, 40nm, and 55nm logic nodes, alongside BCD for power management, SiGe BiCMOS for high-frequency analog, and a ramping GaN-on-silicon platform at its Vermont facility.

Two recent acquisitions, however, have expanded GF beyond pure-play manufacturing. It bought Singapore-based Advanced Micro Foundry last year, making it one of the world's largest silicon photonics foundries, and acquired MIPS (for RISC-V CPU and AI inference IP) along with Synopsys' ARC and RISC-V processor IP portfolio. The company now offers customers pre-built compute IP alongside fabrication, a model no other trailing-edge foundry currently can.

GF operates five manufacturing sites. Fab 8 in Malta, New York, is its most advanced 300mm facility and holds Trusted Foundry Category 1A accreditation from the U.S. Department of Defense. A new fab at the Malta site, funded partly by a $1.587 billion CHIPS Act award, will triple the site's capacity over the next decade as part of a $16 billion, 10-year U.S. investment plan.

Fab 1 in Dresden is Europe's largest semiconductor fab, with a €1.1 billion expansion underway to push output toward 1.5 million wafers per year by the end of 2028. Fab 7 in Singapore opened in September 2023 after a $4 billion build-out, adding 450,000 wafers per year. The two remaining sites are both 200mm facilities in the U.S.: Fab 9 in Burlington, Vermont, which is targeted for the company's first high-volume GaN production line.

The company's 2026 capital expenditure guidance of 15% to 20% of revenue represents a sharp jump from 8% in 2025, driven by what management described as oversubscribed demand in silicon photonics, 22FDX, and SiGe. That investment will compress free cash flow margins in the near term, but GF has said customer prepayments and long-term agreements underpin spending.

Reports surfaced in 2025 of an internal assessment dubbed "Project Ultron" exploring a potential takeover of UMC that would create a mature-node foundry with roughly 28% combined market share. UMC denied active merger talks, and, in any case, the regulatory barriers across Taiwan, China, and the U.S. are more than likely insurmountable.

UMC

UMC reported Q1 2026 revenue of NT$61.04 billion (approximately $1.93 billion), with net income surging 107.9% year-over-year to NT$16.17 billion. Gross margin was 29.2% and capacity utilization stood at 79%, with Q2 guided to the low-80% range and wafer shipments expected to rise by high single-digit percentages.

The 22nm node is UMC's primary growth driver. Revenue from 22nm grew 93% year-over-year in 2025 and now accounts for 14% of total revenue, up from single digits the prior year. Combined, 22nm and 28nm represent 34% to 36% of quarterly wafer revenue.

UMC dominates small-panel display driver IC (DDIC) production at 28nm, holding over 90% market share in that segment, and launched an advanced 22nm embedded high-voltage (eHV) platform in 2024, targeting next-generation smartphone OLED displays. Specialty processes extend across embedded non-volatile memory (eFlash from 350nm to 28nm), RFSOI, RF CMOS, and BCD for analog and power applications down to 55nm.

UMC operates 12 fabs with combined capacity exceeding 400,000 12-inch-equivalent wafers per month. The newest, Fab 12i Phase 3 in Singapore, opened in April last year after a $5 billion investment and will start 22/28nm volume production this year, with an initial capacity of 30,000 wafer starts per month and with space reserved for a second phase.

The most significant item on UMC's roadmap is its 12nm FinFET node, co-developed with Intel and targeted for mass production in 2027 at Intel's fabs in Chandler, Arizona. The process offers 10% higher performance, 20% lower power, and roughly 10% area reduction compared with UMC's existing 14FFC, with three fewer mask layers.

UMC's CFO Chi-Tung Liu confirmed last May that the majority of UMC's R&D spending is now directed at this node. The partnership gives UMC its first U.S. manufacturing footprint and a FinFET node at scale, while Intel gains mature-node foundry volume through what are largely depreciated fabs.

SMIC

SMIC posted record full-year 2025 revenue of $9.33 billion, up 16.2% year-over-year, according to the company's annual results. Full-year utilization averaged 93.5%, a jump of eight percentage points from 2024, and wafer shipments rose 20.9% to roughly 9.7 million 8-inch-equivalent wafers.

Annual capex, meanwhile, ran at over $7 billion, reflecting an aggressive capacity build-out that is compressing margins: full-year gross margin was 21%, and the company guided Q4 2025 gross margin to 18% to 20% as depreciation from new fabs weighed on profitability even at near-full loading.

SMIC's production stack officially spans 350nm to 7nm, but the vast majority of output sits at 28nm and above. 28nm HKMG and PolySiON variants serve smartphones, networking, and DDICs. Nodes from 40nm through 180nm cover analog, power management, RF, image sensors, and microcontrollers.

At the advanced end, SMIC's N+2 process (7nm-class) is in production for Huawei's Kirin 9000S, 9020, and Ascend 910C, with an estimated 20,000 WSPM of capacity. N+3, confirmed on the Huawei Kirin 9030 in December, extends 7nm-class scaling using DUV multi-patterning, though TechInsights characterized it as firmly 7nm/6nm-equivalent in absolute terms rather than a true 5nm node.

Four major new 12-inch fabs are under construction or recently completed, in Shanghai (Lin-Gang), Shenzhen, Beijing, and Tianjin, including an $8.87 billion facility, collectively targeting approximately 340,000 wafer starts per month of new 28nm-and-above capacity.

Export controls from the U.S., the Netherlands, Japan, and Taiwan constrain SMIC's ability to scale its advanced nodes. The company has been on the U.S. Entity List since December 2020, blocking access to ASML EUV scanners and progressively tightening DUV and etch equipment supply.

Taiwan added SMIC and Huawei to its own export-control blacklist in June 2025, requiring permits for high-tech equipment shipments. Although it was reported back in August that SMIC planned to double its 7nm capacity in 2026, the company remains constrained by tooling access: analysts estimate SMIC's advanced-node capacity will remain in the low tens of thousands of wafer starts per month rather than the hundreds of thousands that an unconstrained buildout would target.

SMIC's pricing reflects the competitive pressures in the mature-node segment, with the company having reportedly cut 28nm wafer prices by roughly 40% in early 2025, dropping from approximately $2,500 to $1,500 per wafer, before reversing course with a roughly 10% increase later in the year as utilization exceeded 95%.

Pricing and demand

After two years of price declines driven by Chinese capacity additions, the mature-node segment is reaching a floor. TrendForce reported in March that UMC, VIS, Powerchip, and Nexchip were preparing price increases of up to 10% from April through June this year, with the latter confirming a 10% hike effective from June.

One big factor is tightening supply alongside the cyclical recovery: TSMC has been reallocating 40-90nm production capacity toward CoWoS advanced packaging and silicon interposer fabrication for AI accelerators, reducing the available mature-node wafer supply from the world's largest foundry.

Demand from automotive (GF's automotive revenue alone is on track for $1.5 billion in 2026), power management ICs for AI servers (typically manufactured on 28-55nm BCD processes), DDICs, and embedded flash microcontrollers continues to grow.

Whether these three foundries remain independent is an open question. The Project Ultron reports suggest that at least one party has considered consolidation, and the logic for doing so, at least in terms of economics, grows as margins compress and capex requirements grow.

While SMIC's expansion is state-backed and largely insulated from commercial return calculations, GF is tied to U.S. industrial policy and defense spending, and UMC's future hinges on whether 12nm FinFET with Intel can deliver the revenues that pure mature-node services cannot.

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool built specifically for Huawei's LogicFolding architecture, according to the South China Morning Post. The tool takes what researchers described as a "true-3D" approach, optimizing an entire multilayer chip as a single vertical structure rather than designing each layer in two dimensions and stacking them afterward. In early tests of open-source circuit designs, the university reported a 30% reduction in total internal wire length, along with improvements in performance and thermal management, compared to conventional EDA workflows.

The announcement came two days after Huawei presented LogicFolding and its accompanying Tau Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai. Huawei's goal is to produce chips with transistor density equivalent to 1.4nm processes by 2031, all without access to the extreme ultraviolet (EUV) lithography equipment restricted under U.S. export controls.

LogicFolding works by folding traditional 2D circuit layouts into vertical 3D stacks, shortening the physical paths that electrical signals travel through a chip. That reduces resistance and capacitance on critical wiring, compressing signal propagation delay. Huawei's Kirin smartphone processors launching later this year will be the first commercial chips to use the architecture.

Synopsys and Cadence both offer 3D IC design platforms for multi-die stacking and advanced packaging. But those tools address a different problem: integrating separate chiplets or dies within a package. LogicFolding folds transistor-level logic within a single chip into vertical layers, an intra-die optimization that requires place-and-route tools to work across the full vertical structure simultaneously instead of partitioning separate dies.

Peking University's prototype reportedly addresses this by treating the multilayer structure as a unified design space from the start, but whether their claim of 30% wire-length improvement holds up at production scale remains to be seen.

Synopsys, Cadence, and Siemens EDA command 31%, 30%, and 13% of the global EDA market, respectively, and their combined share within China exceeds 80%, according to EE Times China. The U.S. imposed and then lifted EDA export restrictions last year as part of a rare-earth materials deal. Still, the episode highlighted how dependent Chinese chipmakers remain on Western tools.

China's domestic EDA companies, including Empyrean Technology and Primarius, have made progress in analog, mixed-signal, and physical verification, but none offer a full digital design flow competitive with the Western incumbents at advanced nodes.

A university prototype is a very long way from production-grade commercial software. EDA tools require years of development, extensive process design kit integration with foundries, and validation across thousands of tape-outs before chipmakers trust them. "No single company can independently find all the answers along the path of semiconductor evolution," He Tingbo, chairwoman of the Huawei Scientist Committee and president of the company's semiconductor business department, said at a media briefing on Monday.

China's official technology security bodies on Tuesday certified nine domestically designed AI processors for state procurement, according to the South China Morning Post, creating a brand-new "AI training and inference chips" category under the country's Anke security certification framework. The approved products include Huawei's Ascend 310 and Ascend 910 processors, Alibaba's T-Head Zhenwu M530 and M890, and chips from Biren Technology, Hygon Information Technology, Iluvatar CoreX, MetaX, and Moore Threads. Two of China's most prominent AI chip developers, Cambricon Technologies and Baidu-backed Kunlunxin, didn’t appear on the list.

The certifications are valid for three years and were issued jointly by the China Information Technology Security Evaluation Centre and the National Secrecy Science and Technology Evaluation Centre. Their approvals function as a de facto procurement catalog for government agencies, central state-owned enterprises, and other entities covered by Beijing's Xinchuang initiative, the long-running campaign to replace Western hardware and software across sensitive Chinese IT systems.

The new list represents a substantial expansion from China's initial foray into certifying domestic AI hardware. In December, Beijing added only Huawei and Cambricon to the Xinchuang procurement list (a separate state approval mechanism) for AI processors. Five months later, seven vendors now hold Anke security certification for nine separate chips. The Xinchuang program had previously focused on replacing Intel and AMD CPUs and Oracle databases in government systems, but AI accelerators are the newest addition to that.

Cambricon's absence stands out given that the company was on the December list and is targeting 500,000 AI chip shipments in 2026. An anonymous source told the SCMP that companies can choose whether to submit products for testing, so exclusion doesn’t necessarily indicate a failed evaluation. Each chip must pass tests under the Anke V3.0 requirements to qualify.

Chinese chipmakers continue to eat into Nvidia's position in the domestic market. Chinese semiconductor firms delivered 1.65 million AI GPUs in 2025 out of a total of 4 million units, claiming 41% of local AI server shipments. Huawei alone shipped roughly 812,000 AI chips and is projecting $12 billion in AI processor revenue for 2026. Morgan Stanley estimates China's total AI chip market could reach $67 billion by 2030, with domestic supply covering roughly 76% of demand.

Wafer fab capacity remains a big constraint, however, with all of the certified chipmakers competing for limited production slots at SMIC, whose most advanced stable node is its N+2 process, which is roughly equivalent to 7nm. SMIC reported overall utilization rates above 93% for 2025 and spent $8.1 billion in capex last year, with plans to hold that level through 2026.

SK hynix announced iHBM today, a memory heat management technology designed to enhance AI system performance. The thermal packaging solution improves heat dissipation by integrating ICEs (integrated cooling elements) directly into the HBM package. SK hynix says the result is an over 30% reduction in thermal resistance, “ensuring stable operating characteristics even in high-temperature and high-load environments.”

The iHBM architecture embeds non-conductive silicon cooling elements directly into the Die-to-Die Physical Layer (D2D PHY), the critical, high-speed connection interface between the HBM base die and the AI processor, which is prone to high temperature spikes as a result of extreme data traffic. By placing cooling elements in this layer, SK hynix mitigates the severe thermal throttling that cripples AI system performance during heavy computational workloads.

The company believes that structurally preventing thermal throttling will enable next-generation memory layers (targeted for future generations like HBM5) to scale to higher stack heights and sustain maximum data transfer speeds under the heavy computational loads of AI data centers.

“iHBM is the optimal solution for minimizing heat generation developed by combining memory design capabilities and advanced packaging technology,” said SK hynix Vice President Lee Kang-wook. “We will proactively provide the value customers need in the AI environment and further solidify our leadership in AI memory.”

SK hynix plans to apply iHBM technology from next-generation products, such as HBM5, to meet the thermal management requirements of high-performance computing (HPC), AI data centers, and other ultra-high-density and ultra-high-bandwidth environments, thereby improving overall system stability and efficiency.

Heat management is one of the biggest challenges facing HBM (High-Bandwidth Memory) technology. Unlike conventional memory, HBM achieves massive bandwidth by vertically stacking multiple DRAM dies, dramatically shortening the distance data must travel and enabling far higher transfer speeds with better power efficiency.

To minimize latency and feed AI processors fast enough to avoid bottlenecks, HBM is placed extremely close to the GPU or AI accelerator on the same package, connected through a high-speed silicon interposer. However, this dense arrangement also creates severe thermal problems.

The Die-to-Die Physical Layer (D2D PHY) — the ultra-high-speed interface linking the processor and HBM stacks — continuously moves terabytes of data per second. As thousands of signaling lanes and billions of transistors switch at extremely high frequencies, switching losses, leakage current, and electrical resistance generate substantial heat.

The problem is compounded by the processor itself, which already produces enormous amounts of heat. With the HBM stacks packed tightly around the processor, heat accumulates rapidly in a very small area. When temperatures exceed safe limits, the system automatically reduces clock speeds and voltages through thermal throttling to prevent physical damage, lowering overall performance.

SK hynix's new iHBM approach attempts to tackle the problem at the structural level. Unlike conventional HBM cooling designs that primarily dissipate heat indirectly through the core die and surrounding package structures, the company's iHBM architecture instead places Integrated Cooling Elements (ICEs) directly around the D2D PHY region — the exact zone where thermal concentration is most severe. This approach creates a dedicated dissipation path at the source, reducing overall thermal resistance by 30% and allowing the chip to maintain stable operation under the high-temperature, high-pressure conditions that dense AI workloads demand.

SK hynix says the technology can be manufactured at scale using its existing Wafer Level Packaging (WLP) process, which is built on its Mass Reflow Molded Underfill (MR-MUF) packaging technology already used in commercial HBM products. The design is also architecturally compatible with existing System-in-Package configurations, meaning customers can integrate the new thermal capability without major redesigns.

Belgian semiconductor research giant imec this week announced what it describes as the world's first quantum dot qubit device fabricated using High-NA EUV lithography, marking one of the earliest demonstrations of advanced quantum hardware built using the semiconductor industry's most cutting-edge manufacturing technology. The device, unveiled at ITF World in Leuven on May 19, uses silicon quantum dot spin qubits — nanoscale structures that trap individual electrons and exploit their quantum spin states to store information — patterned at gate gaps of barely 6 nanometers.

At first glance, the announcement may seem like another entry in the increasingly crowded quantum computing race. The actual significance, however, has less to do with raw quantum performance and more to do with manufacturing — arguably the single biggest obstacle standing between experimental quantum systems and commercially useful quantum computers.

Qubits can theoretically solve computational problems that would take classical supercomputers longer than the age of the universe, but only at a scale nobody has yet achieved. With several advancements in the physics side of quantum computing, manufacturing now represents the major limitation. Imec claims to have addressed that directly by using the semiconductor industry's latest and most advanced lithography tool to fabricate silicon quantum dot spin qubits with tolerances compatible with industrial chip production for the first time. If that holds up, the implications for quantum scaling could be tremendous. It’s a significant step towards quantum computing, but we are still not quite there.

Manufacturing, not physics, is now quantum computing’s major bottleneck

Quantum computing’s central problem is no longer simply whether researchers can create functioning quantum systems. Our detailed quantum computing roadmap analysis showed that companies including IBM, Google, IonQ, Quantinuum, D-Wave, PsiQuantum, and others have already demonstrated a wide range of working architectures, from superconducting qubits to trapped ions and photonic systems. The problem is scaling those systems into reliable machines containing millions of reproducible, controllable qubits. — the level widely considered necessary for commercially useful, fault-tolerant quantum computers. The most ambitious industry players' roadmaps place that milestone around or beyond 2030, further proving that manufacturing, not physics, is the current hindrance.

Imec's technology directly targets that problem. The company’s approach centers on silicon quantum dot spin qubits, often described as “industry qubits” because they can, in theory, leverage conventional CMOS semiconductor manufacturing infrastructure. Instead of relying on exotic standalone fabrication ecosystems, silicon quantum dots attempt to piggyback on decades of transistor scaling and wafer manufacturing expertise already developed by the semiconductor industry.

The qubits themselves work by trapping individual electrons inside nanoscale silicon structures. The electron’s quantum “spin” state stores information, while surrounding metallic control gates manipulate interactions between neighboring quantum dots. While the concept may sound deceptively straightforward, its fabrication is exponentially more complex.

Quantum dot performance depends heavily on the spacing between those control electrodes. As neighboring quantum dots move closer together, coupling strength rises exponentially, improving controllability and interaction fidelity. But achieving those gains requires reliably patterning gaps measuring only a few nanometers across an entire wafer.

Imec says it fabricated functioning qubit arrays with gaps of barely 6nm between plunger and barrier gates, using High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography, the industry’s latest precision lithography technology.

High-NA EUV: not yet standard, already essential

High-NA EUV is the semiconductor industry’s next major lithography transition, developed primarily for future sub-2nm processors, advanced AI accelerators, and dense memory technologies. The systems, built by ASML, improve patterning precision by increasing the optical system’s numerical aperture, allowing dramatically smaller and more accurate features to be printed onto silicon wafers than current EUV systems can reliably achieve. The key difference between the new High NA EUV and conventional EUV is the increase in numerical aperture from 0.33 to 0.55

The machine weighs around 150 tons, spans the length of a double-decker bus, and requires an entirely redesigned optical system with mirrors twice as large and ten times heavier than those in standard EUV tools, polished by ZEISS to atomic precision. The technology is a ground-up engineering effort years in the making.

Even among mainstream semiconductor manufacturers, High-NA EUV technology is only just entering commercial deployment. Intel installed the industry's first commercial High-NA EUV lithography tool late last year, while imec received the technology in its 300mm cleanroom in March 2026 — two months ago. The machines themselves reportedly cost hundreds of millions of dollars apiece and represent one of the most complex manufacturing systems ever built.

The fact that imec has already applied High-NA EUV to quantum hardware — before most chipmakers have even integrated it into standard production flows — suggests quantum computing may be converging directly with the semiconductor industry's existing manufacturing roadmap rather than evolving as a separate technology stack entirely. That possibility can have significant implications. Instead of waiting for quantum-specific fabrication ecosystems to mature independently, silicon quantum hardware may be able to exploit the extremely advanced infrastructure of a multibillion-dollar industry, potentially significantly compressing quantum computing timelines. Although this does not mean manufacturable quantum computers are suddenly close.

The implications of imec’s achievement for quantum computing and the semiconductor industry

While imec's prototype remains far from a large-scale fault-tolerant quantum computer, it still represents a functioning silicon quantum dot spin qubit device — a type of quantum hardware designed to store and manipulate information using the quantum spin states of trapped electrons. These qubits belong to a class of quantum architectures viewed as promising candidates for tackling computational problems that quickly overwhelm even the world's most powerful supercomputers due to their enormous combinatorial and quantum-mechanical complexity.

Silicon quantum dot spin qubits are particularly notable among those candidates because their production process is compatible with standard CMOS semiconductor manufacturing — the same ecosystem that produces CPUs, GPUs, and AI accelerators. It is worth clarifying that imec's breakthrough lies in the manufacturing process, not in the qubit architecture itself. Silicon quantum dot spin qubits already exist and have been an active area of semiconductor and quantum research for over a decade. Previous devices have been demonstrated using conventional lithography at the laboratory scale. While that proved the architecture works, it stopped well short of what industrial scaling demands: consistent, reproducible fabrication at nanoscale tolerances across an entire wafer.

That is the gap imec is now targeting. By demonstrating that High-NA EUV lithography can pattern silicon quantum dot spin qubits at gate gaps of just 6 nanometers on a 300mm fab-compatible process, imec has shown for the first time that the semiconductor industry's most advanced manufacturing tool can be brought to bear on this class of quantum hardware — moving the architecture from lab-scale demonstration toward something that could eventually be manufactured like a chip.

If sufficiently scaled and stabilized, silicon quantum dot spin qubit systems could accelerate progress in molecular simulation, advanced materials discovery, pharmaceutical research, cryptography, logistics optimization, and complex physical-system modeling — fields whose computational demands can be prohibitively difficult for classical supercomputers, regardless of how powerful those machines become.

Rather than serving consumers directly, these systems would likely be deployed by hyperscalers, governments, national laboratories, pharmaceutical firms, and defense organizations tackling computational problems where even incremental breakthroughs could have massive scientific or strategic consequences. The technology would most probably be accessed through cloud-based quantum infrastructure rather than on-premises hardware.

Huawei has announced a new chip design framework aimed at closing the technology gap with global semiconductor leaders like TSMC and Nvidia, targeting '1.4nm-class' transistors and a 55% increase in transistor density. The firm also unveiled a new 'Tau Scaling Law' that's designed to replace Moore's Law for future chip scaling. Unveiled at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai on Monday, this new design method is intended to circumvent strict US trade sanctions. It allows the company to develop high-performance smartphones and AI processors without relying on restricted Western manufacturing equipment like extreme ultraviolet (EUV) lithography machines.

Delivering a keynote address at the symposium, He Tingbo — a Huawei board member and President of its semiconductor division, HiSilicon — unveiled the company's new, proprietary “LogicFolding” architecture. The cutting-edge design blueprint is built directly upon the newly introduced Tau Scaling Law.

He revealed that Huawei has spent the last six years quietly refining the methodology, secretly designing and mass-producing 381 chips based on the principle. The company will debut the LogicFolding architecture in flagship Kirin smartphone processors this autumn.

Traditional chipmaking relies on Moore's Law (geometric scaling), which involves shrinking physical transistor sizes. However, as US sanctions blocked China's access to the extreme ultraviolet lithography machines required to implement this approach, HiSilicon has pivoted to a completely different methodology: the Tau scaling law.

Tau Law is a "temporal scaling" framework that prioritizes signal speed, optimizing how fast data moves across a system rather than how small the components are. To execute this theory on a commercial level, Huawei engineered the LogicFolding architecture, a blueprint that physically folds and stacks logic circuits into a dual-layer framework. By drastically shortening internal wiring to eliminate signal delay, the resulting hardware achieves a 55% increase in transistor density and a 41% boost in power efficiency, enabling Huawei to build cutting-edge processors that rival foreign counterparts without Western equipment.

The company’s upcoming Kirin smartphone chips — highly anticipated for the flagship Huawei Mate 90 series — will be the first commercial processors to feature the LogicFolding architecture. The company aims to scale this architecture to its Ascend AI processors and high-capacity data center clusters by 2030. This will provide local alternatives to restricted Nvidia hardware. By 2031, Huawei confidently projects it can design high-end chips with a transistor density equivalent to a 1.4-nanometer (nm) process.

Huawei's announcement comes as China continues its push to end dependence on foreign semiconductor players — amid sanctions and concerns about over-reliance — by aggressively investing in domestic companies and alternative technologies.

Following the announcement, shares for China's largest contract chipmaker, SMIC, surged by 7.6%. The breakthrough is a major symbolic and practical win for Beijing’s push toward complete technological self-sufficiency. While global foundry leader TSMC expects to mass-produce true 1.4nm chips by 2028, Huawei's alternative path means China can dramatically close the performance gap by packaging and structuring chips differently — significantly mitigating the impact of the US clampdown.

Samsung's tentative profit-sharing deal with its largest labor union averted an 18-day strike just days ago, but the agreement has triggered internal conflict that’s now threatening the company's ability to ship AI memory on schedule, according to a Seoul Economic Daily report published yesterday.

It’s understood that meetings are being canceled across Samsung's non-memory and shared business units. That work negligence has become widespread in the foundry and TSP (Test & Package) divisions, which handle the back-end packaging and testing work essential to producing high-bandwidth memory. One source told the publication that “decision-making on major projects has come to a complete halt,” as inter-departmental resentment deepens over the bonus gap.

This disruption in TSP could be especially consequential for Samsung as it looks to ramp up its HBM4 production for Nvidia’s next-gen Rubin AI accelerators. TSP uses an integrated turnkey system that routes chips through its own foundry and packaging lines, and any slowdown in back-end operations will directly constrain HBM output as all three major memory producers are racing to fulfill hyperscaler orders.

Another source speaking to the publication warned that continued negligence on production and verification lines could damage Samsung's customer relationships and jeopardize delivery commitments.

The root of the conflict is a massive disparity in proposed payouts. Under the tentative deal, employees in Samsung's memory division stand to receive bonuses of roughly 600 million won (~$400,000). In contrast, workers in the DX (Device eXperience) division, which covers smartphones, TVs, and home appliances, would receive approximately 6 million won (~$4,000). The deal allocates 10.5% of the semiconductor division's operating profit as stock-based bonuses, with an additional 1.5% in cash.

Workers outside the memory unit have pushed back hard, with a smaller union representing DX employees filing a court injunction this week to block the larger, chip-dominated union from handling collective bargaining. That union's membership surged from 3,000 to nearly 13,000 after the deal was announced. Separately, the Korea Shareholder Action Headquarters has threatened legal action, arguing the profit-linked bonus structure requires shareholder approval under Korean law.

Union members began casting electronic ballots on Friday, with voting open through May 27. Ratification requires participation from more than half of eligible members and a majority yes vote, but approximately 43,000 non-memory union members within the DS division could swing the outcome. According to reports from Korea, internal message boards have shown strong opposition from workers who view the deal as favoring the memory unit at everyone else's expense.

Samsung's semiconductor CEO, Jun Young-hyun, urged employees in an internal memo Thursday to move past the conflict, but the dispute now poses a tangible risk to Samsung during what Bloomberg estimates will be a record year, with 2026 operating profit projected at 330 trillion won (~$218 billion).

Nvidia still holds approximately 70% of the AI chip market share, but that share is projected to erode as Google, Amazon, Meta, Microsoft, and OpenAI invest billions in purpose-built chips designed for their specific workloads. ASIC-based AI server shipments are projected to reach 27.8% of the market in 2026, the highest share since 2023, which also forecasts that custom ASIC shipments will grow 44.6% year-over-year in 2026, nearly triple the 16.1% growth rate projected for merchant GPUs.

This is being enabled almost entirely by TSMC, which fabricates chips for all five hyperscalers and for Broadcom, the dominant custom AI chip architect. Broadcom alone carries a $73 billion AI backlog and is targeting $100 billion in annual AI chip revenue by 2027.

Marvell, which has partnered with Amazon on Trainium and Microsoft on Maia, projects up to $11 billion in AI ASIC revenue for 2026. Together, Broadcom and Marvell control roughly 95% of the custom AI ASIC co-design market.

So, with the market projected to expand significantly across 2026 and beyond, we take a look at what companies are currently up to and where they might be headed in the future.

Broadcom

Broadcom, which has arguably emerged as the core enabler of the AI ASIC ecosystem, reported $8.4 billion in AI semiconductor revenue for Q1 FY2026 (ending February 2026), a 106% year-over-year increase, and guided to $10.7 billion in Q2. CEO Hock Tan told investors the company has "line of sight to achieve AI revenue from chips in excess of $100 billion in 2027," backed by a disclosed $73 billion AI backlog.

Broadcom has confirmed six major XPU customers, including Google, which remains the longest-standing partner, with seven generations of co-designed TPU's since 2014. OpenAI signed a multi-year collaboration in October 2025 for 10 gigawatts of custom accelerators, with first deployment targeting the second half of 2026 using both 3nm and 2nm designs. That deal came after OpenAI was widely reported to be behind a separate $10 billion order. However, Broadcom semiconductor president Charlie Kawwas joked on CNBC that OpenAI "has not given me that PO yet," leaving the identity of the mystery customer officially unconfirmed.

Meta, ByteDance, and Fujitsu round out the confirmed customer list, and analysts have identified Apple and Arm/SoftBank as potential future engagements. Arm is separately developing a custom CPU for OpenAI's Broadcom-built accelerator, a contract that could be worth billions to SoftBank.

The tech behind this growth is Broadcom's 3.5D XDSiP platform, which uses face-to-face 3D stacking via TSMC's SoIC process combined with 2.5D CoWoS integration. The platform enables packages exceeding 6,000 mm squared of silicon with up to 12 HBM stacks, far beyond the roughly 2,500 mm squared limit of conventional 2.5D designs. In February, Broadcom announced it had begun shipping the industry's first 2nm compute SoC built on this platform, integrating four N2 compute dies, one I/O die, and six HBM modules.

In terms of networking, Broadcom’s Tomahawk 6 switch chip entered volume production in March as the industry's first 102.4 Tbps Ethernet part. The companion Jericho 4 fabric chip (51.2 Tbps) began shipping last August and is designed to interconnect over one million XPUs across data centers. Nvidia's competing Spectrum-X1600, meanwhile, isn’t expected in volume until the second half of 2026.

Google TPU

Google's TPU program is the most mature custom AI silicon effort among the hyperscalers, and its latest generation represents a significant architectural leap. The TPU v7, codenamed Ironwood, was announced at Cloud Next in April 2025 and entered preview in November. Each chip delivers 4,614 FP8 TFLOPS with 192 GB of HBM3E memory at 7.37 TB/s bandwidth. It’s manufactured on TSMC's N3P process in a dual-chiplet design co-developed with Broadcom and MediaTek, and features two TensorCores with doubled 256x256 MXU arrays plus four SparseCores.

The 9,216-chip superpod configuration delivers 42.5 FP8 exaflops with 1.77 PB of aggregate HBM. Per-chip, Ironwood's 4,614 TFLOPS sits close to Blackwell's approximately 5,000 FP8 TFLOPS, but SemiAnalysis estimates that TPUs achieve higher sustained model FLOP utilization of roughly 90% for transformers versus 70% to 80% for GPUs, narrowing or erasing the real-world performance gap. Google claims that the total cost of ownership (TCO) per Ironwood chip is roughly 44% lower than a GB200 server from its own procurement perspective.

Google is now selling TPU access aggressively beyond its own services. Anthropic committed to up to one million TPUs in the largest deal in Google Cloud history back in October, while Meta entered talks for multi-billion-dollar TPU deployments in February this year. The current-generation TPU v6e Trillium remains widely available on Google Cloud at $2.70 per chip-hour on demand, delivering roughly four-times better price-performance than H100 instances for LLM workloads, according to Google's own benchmarks. Google's Axion ARM CPU, based on Neoverse V2 and reportedly manufactured on TSMC 3nm according to TrendForce, complements TPUs for general-purpose cloud workloads.

Amazon Trainium

AWS has matched Google's pace with an aggressive custom silicon roadmap developed by Annapurna Labs, the Israeli chip design house acquired by Amazon in 2015. Trainium3, which went generally available at re:Invent in December, is AWS's first 3nm chip. Each Trainium3 delivers 2.517 PFLOPS FP8 with 144GB HBM3E at 4.9 TB/s bandwidth, roughly double the compute and 1.5 times the memory of its predecessor. The new Trn3 UltraServer packs 144 chips delivering 362 FP8 petaflops with 20.7 TB of memory, a 4.4 times improvement over Trn2 UltraServers.

AWS CEO Matt Garman said at re:Invent 2025 that the company had "already deployed more than 1 million Trainium processors" and was selling them as fast as production allowed. CEO Andy Jassy called it "already a multibillion-dollar business." The Project Rainier facility in Indiana, an $11 billion, 2.2 GW campus, had roughly 500,000 Trainium2 chips running for Anthropic by October 2025, and AWS also confirmed an OpenAI deal to supply 2 GW of Trainium computing capacity.

Trainium4 was announced in December 2025 for late 2026 or early 2027 availability, promising three times FP8 performance, six times FP4 throughput, and four times memory bandwidth over Trainium3, with an estimated 288 GB of memory. One notable feature is support for Nvidia NVLink Fusion, enabling hybrid clusters that mix Trainium and Nvidia GPUs. AWS's Graviton5 ARM CPU (192 cores, TSMC 3nm, Neoverse V3) was also announced at re:Invent 2025.

Meta MTIA

Meta disclosed one of the most ambitious custom chip roadmaps in the industry in March, unveiling four new MTIA generations (300 through 500) for deployment through 2027, in addition to the already-shipping MTIA 100 and 200. The company has deployed hundreds of thousands of MTIA chips for inference across Facebook and Instagram.

The MTIA 400 delivers 6 PFLOPS FP8 and 18 PFLOPS MX4 with 288GB HBM at 9.2 Tbps bandwidth in a 1,200W envelope. The MTIA 500, scheduled for 2027 mass deployment, scales to 10 PFLOPS FP8 and 30 PFLOPS MX4 with up to 512GB HBM at 27.6 Tbps in a 2x2 chiplet configuration, consuming 1,700W. From the MTIA 300 to the 500, HBM bandwidth increases 4.5 times and compute scales 25 times, with a new chip roughly every six months.

Meta has been explicit that MTIA is not a replacement for Nvidia GPUs. The company expanded its Nvidia partnership in February for "millions of AI chips," including Grace Blackwell and future Vera Rubin platforms, in a deal reportedly worth tens of billions. Custom silicon handles optimized inference at a massive scale, while Nvidia handles frontier model training.

With $115-135 billion in 2026 capex guidance, Meta is buying everything it can from both sources. The MTIA chips are fabricated on TSMC's advanced nodes: MTIA 100 on 7nm, MTIA 200 on 5nm, and the 300-series onward reportedly moving to 3nm with CoWoS packaging.

Microsoft, Tesla, and other efforts

Microsoft's custom silicon program took a significant step forward in January with the deployment of Maia 200, manufactured on TSMC 3nm with over 140 billion transistors. The chip delivers more than 10 PFLOPS FP4 and 5 PFLOPS FP8 with 216GB HBM3E at 7 TB/s bandwidth in a 750W envelope. Microsoft claims it offers 30% better performance per dollar than the best hardware in its existing fleet and calls it "the most performant first-party silicon from any hyperscaler." Maia 200 currently serves GPT-5.2 models for OpenAI and powers Microsoft 365 Copilot workloads from its Des Moines data center.

The path to Maia 200 was far from smooth, though. The original Maia 100, built on TSMC 5nm, was reportedly designed more for image processing than generative AI and never powered production AI services at scale. Maia 200 was delayed roughly six months due to design changes requested by OpenAI that caused simulation instability, plus chip team turnover. CEO Satya Nadella has emphasized that Microsoft will continue purchasing Nvidia and AMD chips alongside Maia. Microsoft's Cobalt 200 Arm CPU (TSMC 3nm, 132 Neoverse V3 cores) was announced at Ignite 2025 and is now live in Azure data centers.

Tesla’s Dojo project, meanwhile, met a very different fate. Despite years of development and an innovative D1 chip (TSMC 7nm, 50 billion transistors, 362 TFLOPS BF16, with a unique 354-core mesh architecture), Tesla disbanded the Dojo team in August. Lead architect Peter Bannon departed, and roughly 20 engineers left to found DensityAI. Elon Musk explained that "once it became clear that all paths converged to AI6, I had to shut down Dojo." Tesla is now focusing on AI5 and AI6 inference chips, with AI6 backed by a $16.5 billion Samsung fabrication deal, while relying on Nvidia hardware for current training needs.

Among other contenders, Intel's Gaudi 3 has struggled with software maturity and missed targets. Shipment goals were cut by more than 30% in 2024, and the Habana Labs brand is being absorbed into Intel's broader accelerator efforts under CEO Lip-Bu Tan. In China, Huawei's Ascend 910C (SMIC 7nm, roughly 800 TFLOPS FP16, 128GB HBM) targets 600,000 units in 2026 but faces yield challenges at around 20%. Cambricon, meanwhile, plans to triple output to 500,000 chips.

TSMC enables it all

TSMC is the indispensable enabler across all these custom AI ASIC efforts. The foundry generated $122.4 billion in 2025 revenue, up 36% year-over-year, and forecasts a 60% compound annual growth rate for AI chip revenue through 2029.

Its CoWoS advanced packaging capacity is scaling from roughly 65,000-75,000 wafers per month in 2025 to a target of 120,000-130,000 wafers per month in 2026, and capital expenditure of up to $56 billion is planned for the year. The 2nm node entered mass production at the back-end of last year, with capacity fully booked and targeting over 60,000 WPM by the end of the year. Nvidia has secured roughly 60% of CoWoS allocation (c. 595,000 wafers), Broadcom about 15% (c. 150,000 wafers), and AMD approximately 11% (c. 105,000 wafers). Every custom ASIC in this article depends on CoWoS or its successor CoWoS-L for HBM integration, and TSMC's packaging capacity is now a more binding constraint than wafer fabrication itself.

The driving factor behind custom ASIC adoption is, of course, the rapid growth of inference workloads, which Deloitte projected to account for two-thirds of all AI compute this year.

With custom silicon’s up to 65% TCO advantage over conventional GPUs for inference at production scale, it’s easy to see why so many hyperscalers are pursuing custom ASICs. Broadcom and Marvell together control roughly 95% of the ASIC co-design market, so the question is no longer whether custom silicon will take share from Nvidia, but how quickly it erodes Nvidia's pricing power as these programs reach full production scale.

AMD has announced that its 6th Gen EPYC processor, codenamed Venice, has entered production ramp on TSMC's N2 (2nm-class) process technology in Taiwan. The chip, which packs up to 256 Zen 6 cores and claims a 70% compute performance gain over the current EPYC Turin lineup, is the first high-performance computing product in the industry to reach production on N2. AMD also announced a follow-on processor called Verano and said it plans to eventually produce Venice at TSMC's Arizona campus as well.

TSMC began volume production on its N2 node late last year, and the foundry is ramping five separate 2nm fabs this year to meet what it has described as record demand. Apple reportedly secured the lion’s share of initial N2 capacity for consumer silicon, but it’s AMD with Venice that’ll be the first HPC product on the node. Server and data center dies are larger and architecturally more complex than smartphone SoCs, and getting them through yield qualification on a brand-new process is a much bigger challenge.

"As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster," said Dr. Lisa Su, chair and CEO of AMD, in the company's press release.

Venice brings the new SP7 socket, up to 16 memory channels delivering 1.6 TB/s of per-socket bandwidth, and doubled CPU-to-GPU bandwidth that likely indicates PCIe 6.0 support. AMD previewed these specs at its Advancing AI event last year and at CES in January, but this announcement puts the chip on track for commercial shipments later this year.

AMD could face limited next-gen competition in the server market right now, with Intel’s Diamond Rapids — the P-core Xeon 7 family that would be Venice's direct counterpart — rumored to be delayed to mid-2027. Intel's only new server product expected this year is Clearwater Forest, an E-core design built on Intel 18A with up to 288 cores. Clearwater Forest is optimized for high-density deployments at scale, not the high single-thread and general-purpose performance segment that Venice is targeting.

AMD already holds a record 46% server CPU revenue share as of Q1 2026, according to Mercury Research, up from roughly 40% at the company's Financial Analyst Day in November last year. Venice will likely extend that momentum into a segment where Intel will be relying on its existing Granite Rapids Xeon 6 lineup for at least another year.

AMD also confirmed Verano, another 6th Gen EPYC processor built on TSMC 2nm and optimized for performance-per-dollar-per-watt. AMD also says it plans to ramp Venice production at TSMC’s Arizona facility. That’s likely referring to Fab 21 Phase 3, which broke ground last April and is slated for N2 and A16 processes. Volume 2nm production isn’t expected before 2028 at the earliest here, however.

Lip-Bu Tan, chief executive of Intel, this week confirmed that the company had already begun to work on its 10A and 7A fabrication technologies that will succeed Intel's current-generation 18A and next-generation 14A production nodes sometime in the next decade. Both 10A and 7A processes will presumably be able to use ASML's EUV lithography tools with high numerical aperture optics (High-NA), which will first be used for 14A.

"Now I am starting to work 10A, 7A, the roadmap," said Lip-Bu Tan at JP Morgan's Global Technology, Media and Communications Conference. "People do not [simply] go to you, they are looking for the roadmap for the future. So we want to build a long-term business. […]."

Tan emphasized a long-known business practice that ambitious roadmaps that are properly executed are as important as competitive products or fabrication technologies, as many companies do not just buy products, but roadmaps, as they prefer to work with suppliers for years to come. That said, Intel must offer its partners long-term roadmap visibility, so it has to work on technologies that are years from commercialization.

When it comes to Intel's 14A, its development is proceeding as planned, with version 0.5 of the process design kit (PDK) already available and version 0.9 of the PDK due in October.

"Clearly, the 14A, and we announced in Q1, we have v0.5 PDK so that they can do the test chip to look at our yield and see whether they can, over time, to really design their product and fabricate with us," Tan said. "The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Tan says multiple customers have expressed interest in 14A, though Intel has not yet disclosed them.

"We have multiple customers engaged with us [with 14A], and to really define what product, what foundry location wants to be, what kind of capacity we need," Tan said. "I do not disclose the customer. If the customer wants to disclose, we will support that."

As for Intel's 14A timeline, Intel expects risk production in 2028 and then volume production in 2029, which is about the time when TSMC begins to volume produce chips on its A14 fabrication technology.

Three things must be kept in mind here. Firstly, TSMC's A14 is not a direct rival for Intel's 14A as the latter features backside power delivery and is better suitable for high-end data center-grade processors. Secondly, TSMC is said to start making chips using A14 in late 2028, and the company tends to initiate high volume manufacturing (HVM) with very high yields and volumes. By contrast, Intel initiates volume production at development fabs, and it takes the company some time to reach comparable yields and volumes. Thirdly, Intel's 14A will be one of the first nodes to be compatible with High-NA EUV lithography systems (for select layers) and will be the first production node to have the capability to use such scanners for high-volume manufacturing.

Insertion of all-new High-NA EUV tools — along with new photoresists, new photomasks, new pellicles, new metrology tools, new design rules, new computational lithography flows, and a lot of other innovations — is not going to be easy for Intel, so the company is hard at work working with both ASML and partners to ensure that the new ecosystem is ready for prime time. Coincidentally, Christophe Fouquet, the head of ASML, reportedly said that the first test chips made using these High-NA EUV tools will emerge in the coming months, though he did not specify at which vendor or facility.

SMIC founder Richard Chang and AMEC chairman and CEO Dr. Gerald Yin appeared together on CCTV's Dialogue program on May 17th to make a coordinated case for Chinese chipmakers to give homegrown equipment more production-line trial time, according to DigiTimes.

The strange joint TV appearance came days after Chinese industry figures told Securities Times that the next three to five years will determine whether domestically built tools can move from functional prototypes to equipment that meets the yield, throughput, and uptime demands of volume manufacturing.

China's semiconductor equipment vendors collectively posted record revenues in 2025, but profitability is under pressure from domestic price competition, and the hardest remaining bottleneck, lithography, has no credible near-term domestic solution. U.S. export controls, meanwhile, continue to tighten.

Record revenues, falling margins

China's equipment industry grew incredibly fast last year. AMEC, the country's leading etch-tool maker, reported full-year revenue of $1.74 billion USD (12.38 billion RMB), up 36.6% year-on-year, with net profit totaling around $310 million (2.11 billion RMB), up 30.6%.

Naura Technology, the broadest-line domestic supplier, posted $3.91 billion (27.14 billion RMB) in revenue across just the first three quarters, while Piotech, which specializes in thin-film deposition, roughly doubled its nine-month revenue to $617 million (4.22 billion RMB). ACM Research, the U.S.-listed cleaning-equipment maker with the bulk of its operations in Shanghai, booked $901.3 million for the full year, up 15.2%.

Despite these lofty revenues, margins moved in the opposite direction: AMEC’s full-year 2025 gross margin fell 1.9 percentage points to 39.2%, with the third quarter alone dropping 5.8%, and ACM Research's gross margin slid from 50.1% in 2024 to 44.4% in 2025. The pattern was consistent across the sector.

This squeeze is coming from domestic competition rather than foreign pressure. With U.S., Japanese, and Dutch export controls restricting shipments of advanced tools to Chinese fabs, domestic vendors are competing fiercely with each other for orders that previously went to Applied Materials, Lam Research, and Tokyo Electron; Needham & Co. analyst Charles Shi recently told Nikkei Asia that this internal price war is the primary driver of margin erosion.

Chinese fabs are now thought to be sourcing roughly 35% of their equipment domestically, up from about 25% a year ago. Beijing's informal target for new fab construction is 50% domestic content, a threshold that YMTC's third Wuhan fab has reportedly already cleared, but the gains are concentrated in mature-node tool categories. Etch localization at mature nodes sits at roughly 50% to 60%, and resist stripping exceeds 80%. According to data from Ijiwei thin-film deposition runs from 20% to 30%, and lithography sits below 5%.

A public appeal

The Chang-Yin CCTV appearance was ultimately a strange, public, state-sanctioned appeal to Chinese fabs. Chang argued that domestic equipment can’t improve without real production-line trials and said fabs should start with small wafer batches of up to 100 wafers before scaling up to limit the risks of early adoption. Meanwhile, Yin said that Chinese customers still default to foreign tools out of habit, and even new systems from the world's largest equipment vendors typically require two to three years of tuning when first deployed at leading fabs.

Industry-standard timelines for qualifying a new etch or deposition tool on a leading-edge production line run 18 to 24 months from installation to qualified production status. The process tests reliability, particle contamination, process drift, and throughput under sustained operation, not just whether the tool can produce a working wafer under controlled conditions.

An example highlighted by Yin is that of AMEC, which, in December 2023, decided to enter the large flat-panel display equipment segment, a category he said was previously 100% imported. The tool in question weighs roughly 150 tonnes and measures 15 by 15 meters, but AMEC reportedly built a working prototype in 12 months, met a customer's next-gen specifications four months later, and shipped the tool to a production line within 18 months total. Needless to say, those claims haven’t been independently verified and shouldn't be taken at face value.

AMEC also claims SMIC has purchased at least 800 of its tools, a figure Chang cited on the same broadcast, and that its etch technology is used in TSMC's supply chain at nodes from 65nm down to 5nm and 3nm. TSMC hasn’t publicly confirmed the scope of AMEC's role in its production lines, however.

Recent disclosures show that SMIC faced yield losses tied to equipment maintenance and validation stalls in 2025, the exact production-line qualification problem Chang acknowledged on CCTV. The foundry has reportedly acquired some foreign tools that are sitting idle because spare parts and field service from sanctioned suppliers are no longer available under normal terms.

Still no lithography solution

None of China's equipment progress addresses the most critical chokepoint: lithography. Shanghai Micro Electronics Equipment (SMEE), the only Chinese supplier of lithography scanners in any volume, produces a 90nm-class ArF system. While a 28nm-class tool has been reported in development, it’s not confirmed in mass production, and details are scarce.

One project to watch, however, is the Shanghai Yuliangsheng immersion DUV scanner under test at SMIC. That tool, linked to Huawei-backed SiCarrier under the codename "Mount Everest," resembles ASML's Twinscan NXT:1950i from 2008, two product generations behind the NXT:2000i used in current 7nm and 5nm production. SMIC is thought to be targeting the Yuliangsheng tool for its 28nm production flow in 2027, but sub-10nm lithography on purely domestic equipment is unlikely before 2030.

In Q3 2025, 42% of ASML's system sales by revenue went to Chinese customers, confirming that Chinese fabs are buying DUV scanners as fast as current export rules allow. But Washington is working to narrow this window further, with the MATCH Act, which was introduced last month. It names and designates the likes of AMEC, Naura, Piotech, ACM Research, SiCarrier, and SMEE, among SMIC, YMTC, Hua Hong, CXMT, and Huawei, as “Covered Facilities” and would impose a country-wide prohibition on exporting DUV immersion lithography tools to China.

The House Foreign Affairs Committee passed the bill 36 to 8 in late April after removing a proposed ban on cryogenic etch tools, which would have affected Lam Research and Tokyo Electron. The DUV immersion ban remains in the bill as it heads toward a Senate floor vote. As of the time of writing, it’s currently sitting in a Senate Committee.

China criticized the legislation less than a week before the duo’s state-sanctioned television address to chipmakers. The broadcast itself is ultimately best viewed as part of Beijing's response: a coordinated message that domestic fabs need to accelerate qualification of Chinese-built alternatives before the remaining supply lines are cut.

Russia’s Mikron is earning a bit of cash on the side by selling picture-framed test wafers as souvenirs. There are 12 designs in the product gallery, all priced at 12,500 rubles (~$170), with various frame backgrounds and commemorative texts. Mikron says supplies of these exclusive silicon wafer artworks are limited.

Spotted by Dmitrii Kuznetsov @torgeek on X, some of these wafers will feature the AMUR MIK32 RISC-V chip, produced in Russia since 2022. The computer and data science enthusiast also notes that Mikron is busy “preparing to release a new RISC-V — MIK32-2.” (machine translation)

The souvenir product pages also reveal that the framed 200mm wafers may also come packing between 30 to 120,000 chips, depending on the product. For example, one of the wafer designs may be full of transport card chips as used by the Moscow Metro.

Buyers visiting the Mikorn souvenir shop pages will choose their framed wafer by selecting the frame color and/or theme. For example, there are products with simple black or white frames. But there are other designs with lace, paisley, or even an outer space theme. What kind of wafer you get with your choice of frame, appears to be pot luck.

We used machine translation on the new 2026 edition wafer souvenirs, to see what the information panel to the lower left of the frame said. The top row of the table reads: 2026 | Made in Russia | Techno exclusive | Russian chips | 200mm. Moving to the second row: Silicon wafer with integrated circuits | The satellite plate is used in the technological process for quality control at all stages of microcircuit production.

If you manage to buy one of these Russian semiconductor industry souvenirs, you will need a space on your wall for a 270 x 270 x 15mm (10.6 x 10.6 x 0.6-inches) frame, which weighs 365g (~13 ounces). I think they look smart, but it would be even better if you had a piece of tech that actually used one of the chips from the wafers for your wall presentation.

If you have followed the link to Mikron’s souvenir shop and had a browse around, like us, there are a few other interesting trinkets to see. A much cheaper souvenir flagged as ‘new’ is the small tube of air from the firm’s NWP clean room in Zelenograd, priced at around $2. Elsewhere there are gift shop trinkets of the style you might find anywhere, like dolls, mugs, magnets, and puzzles.

President Donald Trump described a pending $14 billion arms sale to Taiwan as a "very good negotiating chip" with China in a Fox News interview taped in Beijing on Friday, saying he had not yet approved the deal and was holding it "in abeyance." The package, which includes PAC-3 MSE interceptors and NASAMS air defense missiles, had been ready for Trump's signature since Congress approved it in January.

Trump's remarks came at the close of a two-day summit with Chinese President Xi Jinping, during which Xi warned that Taiwan is "the most important issue" in the bilateral relationship and that mishandling it could lead to "clashes and even conflicts." Trump told reporters aboard Air Force One that the two discussed Taiwan arms sales "in great detail."

Karen Kuo, spokesperson for Taiwanese President Lai Ching-te, called China the "sole destabilizing factor" in the Indo-Pacific and said arms sales between the U.S. and Taiwan reflect Washington's security commitment under the Taiwan Relations Act.

Secretary of State Marco Rubio told NBC News that U.S. policy toward Taiwan is "unchanged" and called any Chinese attempt to take the island by force "a terrible mistake." A bipartisan group of U.S. senators had written to Trump ahead of the trip, urging him not to treat Taiwan's defense as a bargaining tool, stating that American support for the island "is not up for negotiation."

Trump, however, framed the situation in transactional terms to Fox News, saying that when looking at the odds, “China is a very, very powerful, big country. That's a very small island," adding, "I do say this: Taiwan would be very smart to cool it a little bit."

Taiwan produces more than 90% of the world's most advanced semiconductors through TSMC, which fabricates chips for Nvidia, AMD, Apple, and Qualcomm. That concentration of manufacturing capacity is the foundation of what analysts and Taiwanese officials call the island's "silicon shield," the idea that global dependence on Taiwanese chips gives allied nations a strategic incentive to defend it.

Trump's willingness to treat Taiwan's military support as leverage over Beijing could, however, test that assumption. The U.S. struck a trade deal with Taiwan earlier this year that commits Taiwanese firms to over $500 billion in U.S. semiconductor investment, and TSMC is already building $165 billion in Arizona fab capacity. But reshoring chip production takes years, and the most advanced nodes remain in Taiwan under legal restrictions designed to preserve that shield.

In 2023, U.S. intelligence officials privately briefed the CEOs of Nvidia, Apple, and AMD that China could invade or blockade Taiwan by 2027. Trump announced an $11 billion weapons package for Taiwan in December 2025, but has yet to begin fulfilling it.

All three leading-edge foundries — Intel Foundry, Samsung Foundry, and TSMC — have initiated mass production of chips using 2nm-class process technology. Samsung was the first one to start production using its SF2 node (though it could be argued that this is a rebadged SF3P) around mid-2025, Intel followed suit with its 18A node in November (albeit at development lines in Oregon, not production lines in Arizona), and TSMC initiated high-volume manufacturing using its N2 process at two volume fabs in Taiwan in December. We outline what's next for these three leading-edge foundries.

The current state of the market

The amount of capital, expertise, and experience required to develop leading-edge process technologies and build high-volume fabs supporting advanced nodes is so high that only three companies in the world are currently capable of producing them. Companies like Rapidus have yet to prove they are a viable leading-edge chipmaker. Meanwhile, all three leading foundries are transitioning from traditional node scaling to a more segmented, architecture- and product-driven approach, but are doing so with different priorities.

TSMC is focused on predictable scaling, combined with aggressive specialization, which is why its roadmap is split into high-performance computing-oriented technologies with backside power delivery network (BSPDN) and cost/density-optimized nodes without it.

Samsung has a wide range of node variants, though it is currently more focused on yield improvement, rather than on scaling, which is why its roadmap appears more iterative than breakthrough-focused. This is perhaps why it is behind competitors with its BSPDN implementation.

Intel seems to be pursuing the most aggressive technological roadmap with a conjoined implementation of gate-all-around (GAA) RibbonFET transistors and PowerVia BSPDN, rapid iteration, and the aggressive pursuit of High-NA EUV lithography in 2027 – 2028, years before its rivals.

Intel Foundry: The most ambitious chipmaker

Being a new player in the foundry market and a large integrated design manufacturer (IDM), Intel is pursuing a multi-faceted strategy aimed at addressing the needs of its own products, as well as attempting to land customers that do not necessarily require leading-edge process technologies.

Intel's roadmap is the most ambitious, but arguably the most volatile one, when compared to the plans of other leading foundries. On the one hand, Intel needs the best fabrication technologies to differentiate its own consumer and data center products. To that end, with its 18A and subsequent process technologies, Intel bet on the simultaneous implementation of GAA transistors and a BSPDN to maximize performance, power efficiency, and transistor density. On the other hand, since Intel has zero customers from the automotive and smartphone sectors, it does not have any technologies tailored specifically for these applications.

Intel's 18A is probably the most important technology for the company in years, as it will return production of the company's consumer CPUs back to its own fabs, something that promises to greatly improve margins. Although the company is in the process of improving yields on 18A and current 18A volumes are not significant, Intel is already preparing follow-on refinements such as 18A-P (with enhanced performance and improved power efficiency) and 18A-PT (which supports through silicon vias (TSVs) and can be used for 3D-integrated systems-in-package).

Beyond that, Intel is targeting 14A and 14A-E for 2027 ~ 2028 production readiness and an early ramp. The nodes will introduce Intel's 2^nd Generation RibbonFET GAA transistors, revamped PowerDirect backside power delivery, and Turbo Cells to improve the performance of critical data paths.

These will be the company's first nodes to use High-NA EUV lithography, at least for some 14A and 14A-E variants, which will be another attempt to introduce a technology that will differentiate Intel compared to competing nodes. Intel has said that the interest in 14A from external customers is significant. Musk's Terafab project is set to make use of Intel's 14A, as a licensee, but not as a customer.

At the same time, Intel is heavily relying on node variants to address different use cases, including performance enhancements (P), feature enhancements (E), and through-silicon via support (T). These process technologies are required to enable Intel to build custom multi-chiplet products for consumer and data center applications, which directly support its strategy to produce most of its products at in-house fabs.

Intel's roadmap also includes continued investment in mature nodes such as Intel 16 and UMC 12 as the company pursues a strategy to capture demand outside leading-edge applications, to ensure steady revenue streams.

While Intel's plans are aggressive and ambitious, the abrupt cancellation of 20A in late 2024 highlights the execution risks associated with such a roadmap.

Samsung Foundry: When yields matter more than nodes

Samsung was the first company to adopt GAA transistors with its SF3E technology in 2022, three years before Intel and TSMC. However, low and unpredictable yields have limited the adoption of this technology to niche applications like cryptocurrency mining ASICs. While SF3 was more mature, it was still adopted by select applications, mostly internally. As a result, the highest-performing chips made by Samsung are produced using FinFET-based SF4P and SF4X, which puts the company behind its rivals.

For now, reducing defect density, increasing yields, and ensuring stable yields are the top priorities for Samsung. Last year, it began making mobile system-on-chips (SoCs) using its SF2 node (which it calls the 1^st Generation 2nm GAA process), but among the major goals for the company for this year is to ramp up '2^nd Generation 2nm [SF2P] and prepare performance and power-optimized 4nm process,' which suggests limited adoption of SF2. The fact that the low-power 4nm-class node will be a major workhorse for the company. The company's roadmap also indicates SF2X (HPC-oriented) in 2026 as well as SF2A (for automotive applications) and SF2Z (SF2X with BSPDN) in 2027, though we can only wonder whether these nodes will be widely adopted.

Nonetheless, Samsung's iterative approach to the evolution of its SF2 nodes (SF2=>SF2P=>SF2X=>SF2X with backside power) is evident, which gives us hope that the company's yields will gradually improve.

Samsung's next major node will be SF1.4, a 1.4nm-class process technology optimized for consumer and smartphone applications, which won't feature backside power delivery. Samsung's slides put SF1.4 above the SF3 and SF2 families, which may suggest that this manufacturing process will feature some major enhancements, such as a new GAA transistor design or other major refinements. Samsung expects to mass-produce chips on its SF1.4 technology in 2027, so it can formally leave Intel and TSMC behind with its 1.4nm node.

A big question lingers, and that's whether Samsung plans to finally start using pellicles with its EUV lithography tools starting with SF1.4, or later. A lack of pellicles greatly increases the number of potentially yield-killing stochastic mask-borne defects, which are increasingly dominant at the 2nm and are getting much worse at thinner nodes.

TSMC: New technologies like clockwork

TSMC's roadmap remains the most structured and execution-focused among the three. The world's largest contract chipmaker initiated mass production of chips using its N2 process technology — its first node with GAA nanosheet transistors — at two fabs simultaneously late last year in a bid to meet demand from a wide range of applications, starting from Apple's smartphones and all the way to AMD's server-bound EPYC 'Venice' CPUs. Initiating volume production at two fabs simultaneously is something that rarely happens in the industry, though it looks like structural changes caused by demand from the AI segment are changing many things in the industry.

TSMC is on track to start making chips using performance-enhanced N2P with traditional frontside power delivery and A16 technology that adds backside power delivery on top, a split which highlights TSMC's increasingly segment-specific approach to leading-edge technologies.

Going forward, the company is set to continue offering advanced technologies with and without BSPDN, as this feature may be too expensive for consumer and smartphone applications, but is clearly valuable for heavy-duty data center processors. For example, A14 will emerge as a smartphone-oriented node in 2028, but then will re-emerge as a data center-oriented node once it gets BSPDN in 2029.

In addition, the company will continue to offer mainstream nodes like N4C, N3C, and eventually N2C for applications that are more sensitive to costs. Automotive-specific nodes (N7A, N5A, N3A) will lag leading-edge nodes by one to two generations, as they prioritize reliability and longevity over performance and transistor density.

TSMC's segmentation and yearly cadence for advanced manufacturing nodes enable the foundry to address the most demanding clients like Apple, AMD, Intel, Nvidia, or Qualcomm with competitive process technologies. Ultimately, such cadence and a wide range of nodes reinforce TSMC's position as the most predictable and commercially disciplined foundry.

Fractured futures

To sum things up, TSMC continues to bet on execution discipline and segmentation as it ramps its 2nm-class node at two fabs to meet overwhelming demand from a variety of applications, starting from humble cell phones all the way to heavy-duty servers.

Intel leads in architectural ambitions, as currently it is the only company that uses a process technology that features both gate-all-around transistors and backside power delivery. However, the company admits that its yields will only get to world-class level by 2027, which likely makes Intel's 18A node significantly less attractive to demanding customers.

Samsung sits somewhere in the middle, offering a wide variety of process technologies for different applications, but the company's yields with GAA-based nodes have been a challenge, which is why the firm is now focused on yield increases rather than on breakthroughs, so it does not attempt to leapfrog its competitors.