Taiwan is expanding its list of controlled exports to include AI servers and the latest chips in a move to align its policies with the U.S.’s trade bans. Bloomberg reports that after the export controls take effect, anyone caught smuggling these items will be criminally charged under the Foreign Trade Act, which carries a penalty of up to five years in prison and/or a fine of around $92,500.

“Going forward, some of our measures on controlled items will correspond to American ones because we have made quite some commitments in the Agreement on Reciprocal Trade,” Taiwan Minister of Economic Affairs Kung Ming-hsin said. The two parties signed the trade deal earlier this year, which saw the U.S. cutting tariffs on Taiwanese goods down to 15% in exchange for direct investments in the U.S. tech industry, among others.

The U.S. has long been trying to stamp out the smuggling of advanced Nvidia chips into China. One of the biggest cases that U.S. authorities have prosecuted so far includes three Super Micro employees, including its co-founder Yih-Shyan “Wally” Liaw, who are accused of smuggling $2.5 billion worth of AI servers. A few months after this revelation, Taiwanese authorities raided Super Micro’s Taipei offices in connection with the Nvidia B300 smuggling probe, which eventually led to the indictment of nine individuals related to the case.

Since Taiwan doesn’t treat AI chip exports to China as a crime before this new set of export controls is enacted, people violating the chip bans would have to be charged under other laws. This is what Singapore did when it arrested suspected Nvidia AI GPU smugglers — because it doesn’t have a law that prohibits the export of advanced AI chips to China, it instead charged the individuals with fraud and money laundering.

The expansion of the Foreign Trade Act will be one of the strictest measures that the Taiwanese government has put into place against exports to China, which is something that it has been considering earlier this year. This move will likely please Washington as it pressures other countries to take more steps in its controlling the flow of advanced AI chips into China. However, it will also likely provoke Beijing, which has already condemned Taipei after it applied export restrictions on Huawei and SMIC last year.

Being unable to procure EUV litho tools from ASML, China must develop such systems locally, so from time to time we learn about an EUV-related 'breakthrough' in China that will turn into an actual EUV scanner over the following several years. This week, Chinese startup Langdao Silex demonstrated a prototype extreme ultraviolet (EUV) light source with over 15W of output power, 90% domestic components, and decent uptime. The company will need another three to five years to commercialize its technology, reports TrendForce, citing various sources. Yet, a light source alone does not make an EUV scanner.

An LPP EUV source from China

Langdao Silex, which was established in 2024 by Tsinghua University's Gas Discharge Plasma Laboratory alumni, demonstrated its EUV light source prototype at the 26^th China International Industry Fair in Shanghai, for obvious reasons, without lighting it up. Just like modern light sources from ASML, the company's low-power FlintNano LPP-OXXO system uses laser-produced plasma (LPP) technology that produces EUV radiation by bombarding tiny heated metal droplets with high-energy laser pulses to create extremely hot plasma. The system features a 1,000W driving laser (presumably a CO₂ one) with an operating frequency of 1 kHz – 20 kHz and conversion efficiency exceeding 2%. Its EUV output exceeds 15W (presumably measured at the plasma rather than at intermediate focus, as the company has not demonstrated a complete EUV collection system) while its brightness reaches 100 W/(mm²·sr). The source has an étendue of 1 × 10⁻³ mm²·sr and generates plasma with a diameter of 60 μm.

According to Langdao's specifications, the FlintNano LPP-OXXO can operate continuously for over 100 hours with plasma stability of 3% RMS and EUV output power stability of 5%. These characteristics make the system suitable for semiconductor exposure experiments, although its output remains insufficient for high-volume chip production. Meanwhile, the 'over 100 hours' availability is very impressive for a pre-production light source, though we must admit that there is no way to verify the claim.

Langdao is also developing the FlintMicro-LPP high-power EUV source, which has completed proof-of-principle validation, according to reports. However, Langdao has not disclosed its output power, conversion efficiency, or operating lifetime.

On paper, Langdao's EUV source is comparable in output to some of the earliest EUV sources developed by Western and Japanese equipment makers, albeit with a major caveat: Langdao seems to measure EUV power at the plasma rather than after the collector or at intermediate focus as ASML does. ASML's early EUV demonstration equipment used approximately 10W at intermediate focus DPP sources in 2007, while Cymer's LPP sources installed in early NXE:3100 systems delivered up to 11W during wafer exposure in 2012 (note that ASML's machines are source agnostic, so some NXE:3100 prototypes used DPP sources, while others used LPP sources). By 2013, Cymer demonstrated approximately 40W at intermediate focus over extended operating periods. Meanwhile, Japan's Gigaphoton targeted 25W with its first prototype in 2013 and demonstrated 43W in early 2014. By late 2014, Gigaphoton had achieved 118W during a 10-minute test. However, since these historical figures involve different measurement conditions and operating durations, direct comparisons are vastly inaccurate.

Not quite there

Langdao Silex has not demonstrated its EUV light source in action, so all we know about it comes from the company itself. As noted, 15W power looks comparable to early EUV sources developed by Philips Extreme UV (DPP) and Cymer (LPP). Meanwhile, early NXE:3400-series machines came with 125W – 150W at intermediate focus sources, which was far from enough for high-volume manufacturing (HVM).

Modern EUV lithography equipment comes with considerably more powerful sources. ASML introduced 250W-class EUV sources for commercial production in 2018 – 2019 and has since achieved substantially higher output levels. Increasing output requires more powerful CO₂ lasers, highly accurate tin-droplet generators, effective debris mitigation, durable collector mirrors, and considerably better long-term reliability.

Langdao claims that 90% of its prototype's components are domestically sourced and that most critical parts were developed in China. However, the company has not explained whether the localization figure reflects component count, value, or another metric. Furthermore, its representatives reportedly acknowledged that increasing EUV output and improving long-term operational stability are the targets to be achieved in a bid to commercialize the source.

Not an EUV scanner

Yet, even without complete EUV scanners, Langdao's source could support EUV photoresist development, mask inspection research, development of EUV collection and illumination optics, and eventually experimental exposure testing.

Developing a complete EUV lithography scanner will require further advances in EUV collection and illumination systems, high-precision multilayer mirrors, wafer and reticle stages, overlay accuracy, and system integration. Meanwhile, all of these devices require a separate supply chain that hardly exists in China today.

Therefore, even if Langdao successfully develops its EUV source and increases its output to levels suitable for high-volume manufacturing, this would not necessarily mean that China could manufacture its own EUV lithography machines any time soon. Moreover, while Langdao's progress is impressive, it took ASML/Cymer approximately six years to increase the output of its LPP EUV source from 11W to 125W – 150W at intermediate focus, so there is no way that Langdao's LPP source could be used for anything beyond development tools in the next three to five years.

Meanwhile, Langdao has not disclosed where its reported 15W of EUV output is measured. If this figure represents radiation generated at the plasma rather than power delivered at intermediate focus, the source's usable output would be considerably lower than 15W when measured according to industry-standard practices. That said, it does not look like China got significantly closer to building its own EUV lithography scanners with the current announcement.

Taiwan is raising at least $4 billion through the Taiwan Electrical and Electronic Manufacturers’ Association to build an industrial park in Texas. According to Bloomberg, the site is designed to support the countless smaller manufacturers that major manufacturers like TSMC and Foxconn rely on.

“We are going to establish a long-term, sustainable supply chain there that can also be joined by American firms and local workers, and not just Taiwanese companies,” Taiwan Minister of Economic Affairs Kung Ming-hsin said.

Major Taiwanese companies are more than capable of spending the billions of dollars needed to set up shop in the U.S. TSMC, for example, has already spent $165 billion to put up its Arizona site, and has committed a further $100 billion to build four more 2nm fabs. However, they also rely on several smaller manufacturers that do not have the financial capability to expand operations into the U.S. independently. Nvidia CEO Jensen Huang has even recognized some of these companies in a keynote in Taipei earlier this year, nothing the crucial part that these smaller companies play in the global AI supply chain.

Support for these businesses will not be limited to the planned industrial park, too. The Taiwanese government said that it will also offer loan guarantees to the companies that want to operate on the land, plus support them in communicating with local and federal U.S. officials regarding visas, permits, and other documentation.

Taiwan has reportedly secured a piece of land in Texas specifically for this project, but the Ministry of Economic Affairs didn’t give out any details yet, saying that it will elaborate on the project later. It’s also not limiting itself to a single industrial park, with the government saying that it’s planning for “more than one” site that would cost between $2 billion and $4 billion.

While the U.S. government hasn’t commented on Taiwan’s industrial park plan, the planned $4-billion investment would follow the “Taiwan model” that would help its companies invest in America easily and shorten the AI semiconductor supply chain that relies on Taiwanese industry. But even though these companies are primarily focused on meeting the needs of Taiwanese giants like TSMC, Foxconn, and Wistron, American companies are also welcome to work with them. Kung even said that Elon Musk’s Terafab can take advantage of this prospective supply chain, although he also said that they will not transfer their technologies so that he could integrate them vertically.

The EU is currently in talks with China to lift restrictions the country imposed on Sindlhauser Materials GmbH, a German company in ASML’s supply chain, as the sanctions risk putting the company out of business. In return, the EU would remove restrictions it placed on one unnamed Chinese firm accused of aiding Russia in the war with Ukraine, according to an Oct. 14 Bloomberg report citing people familiar with the matter.

The deal was discussed during EU Commissioner for Trade and Economic Security Maroš Šefčovič’s visit to Beijing. The EU is expected to make the first move, with any delisting on its end requiring unanimous support from member states. Both sides also agreed to share more information and give advance warning on future export restrictions.

In July 2026, China put Sindlhauser, a German precision-manufacturing and advanced-coatings firm, on its export-control list, along with 13 other European companies, in apparent retaliation for the EU’s 21st Russia sanctions package, which sanctioned several Chinese firms accused of supplying Moscow with components that can be used to make weapons. Beijing’s official reason was the firms’ alleged dealings with Taiwan.

China’s selection of Sindlhauser is not random, as the company sits in ASML’s supply chain. According to Bloomberg, officials believe Beijing has spent the last year and a half gathering information on Western supply chains, and used the data to identify the seemingly obscure German firm as a pressure point on the world’s most important chipmaking-equipment company.

Sindlhauser relies almost entirely on Chinese rare earths and critical minerals. Therefore, the restrictions, which ban Chinese exporters from selling dual-use items to the firm, cut off its main source of input. They also prohibit foreign companies and individuals from passing on China-origin dual-use items to the firm, thus preventing Sindlhauser from simply sourcing the same materials through a third-party distributor.

After the listing, which initially sparked panic over the company’s survival, the German government and Bavaria’s state government stepped in, helping the company explore workarounds such as alternative suppliers and recycling existing materials. However, due to its heavy dependence on China, Sindlhauser now faces the risk of going out of business in the coming months if the sanctions remain.

EU officials in Brussels had been raising the case with Beijing for weeks, culminating in the delisting swap discussed during Šefčovič’s visit. The incident highlights China’s influence on several aspects of the global technology supply chain, including semiconductor manufacturing, which is critical to the AI boom. The country placed export restrictions on several rare earth metals, limiting their availability across the supply chain. Meanwhile, the West has been investing heavily in domestic supply chains to reduce reliance on China.

ASML this week reported record quarterly revenue of $13.06 billion (€11.66 billion) and profitability of nearly $5.79 billion (€5 billion) as demand for advanced semiconductor manufacturing equipment continues to accelerate and investments in AI infrastructure continue to increase. The company now expects demand for its lithography systems to exceed its production capacity in 2027 and 2028, despite plans to increase output substantially. Some clients are already interested in placing orders for equipment as far ahead as 2030, which makes ASML consider further capacity expansions beyond its previously announced intentions.

Record financial results

ASML reported third-quarter 2026 revenue of $13.06 billion USD (€11.66 billion), up 55% year-over-year and 25% sequentially. The company's gross margin reached a record 57.5%, up from 51.6% a year earlier, while operating income rose to $5.79 billion (€5.17 billion). Net income reached $5.56 billion USD (€4.96 billion) , although this figure includes approximately $570 million (€510 million) from the re-evaluation of the company's investment in Mistral AI.

During the quarter, ASML sold 121 lithography systems, including 113 new and eight refurbished machines, up from 91 systems in Q2 2026. The company generated $4.59 billion USD (€4.1 billion) from 17 EUV lithography systems and $4.82 billion USD (€4.3 billion) from 85 DUV (including 45 ArFi scanners) and 19 i-line litho tools. In addition, ASML recognized revenue from one High-NA EUV system in Q2. Of total equipment revenue, 54% came from logic chipmakers and 46% from memory manufacturers.

Taiwan accounted for 32% of ASML's equipment sales in Q3 2026, followed closely by South Korea at 31%. China represented another 23%, while the United States accounted for 13% and the rest of Asia contributed just 1%. Combined, Taiwan and South Korea generated 63% of ASML's equipment revenue, which reflects substantial investments in advanced logic and memory manufacturing capacity that by far exceed those in the U.S. and Japan.

ASML’s Installed Base Management business generated $3.68 billion (€3.29 billion), approximately $450 million (€400 million) above guidance, largely due to strong demand for productivity upgrades (more on this later), which contributed to the company’s record profitability.

For the fourth quarter, ASML expects revenue of $15.9 billion to $17.0 billion (€14.2 billion to €15.2 billion) and gross margin of approximately 57%. Full-year revenue should reach $49.3 billion to $50.4 billion (€44 billion to €45 billion), up approximately 36% YoY. The company projects EUV revenue should increase by more than 45% year-over-year, while memory-related equipment sales are expected to rise by approximately 75%, which indicates growing demand from DRAM producers.

Demand for litho tools spans to 2030

One of the biggest learnings from these results and accompanying statements is that semiconductor manufacturers are increasingly interested in securing lithography equipment years before they actually need it. According to ASML CEO Christophe Fouquet, customers expect demand for its products to exceed available supply through at least 2028, which encourages them to accelerate construction of new fabs as well as expand their existing capacity.

"Our leading-edge high-volume customers are sharing very good visibility as a result of the increasing number of long-term commitments they are securing with their customers," Fouquet said during the company's conference call with analysts and investors. "This extended visibility has led them to conclude that demand for their products will outpace supply through at least 2028. As a result, customers are accelerating capacity build-out plans and preparing for further expansion beyond 2028 in order to better meet the anticipated level of demand."

ASML is already receiving orders that are to be delivered in 2028, while some customers have expressed interest in equipment for 2029 and even 2030.

"As customers shift focus to their needs beyond 2027, our order momentum continues to build," Fouquet added. "We are increasingly receiving orders for 2028, and customers are also expressing interest in placing orders for 2029 and even 2030."

To address this demand, ASML plans to manufacture approximately 65 Low-NA EUV systems in 2026, up from 44 scanners shipped in 2025. Production of immersion DUV systems should remain approximately at last year's level, even though proveiously the company expected shipments of DUV tools to decline.

The company previously announced plans to increase production capacity for both Low-NA EUV and immersion DUV systems by 30% in 2027, followed by another potential 30% increase in 2028. Based on its 2026 EUV production target, this implies capacity for approximately 85 Low-NA EUV systems in 2027 and roughly 110 in 2028, assuming both increases materialize.

However, ASML now believes even this level of output will be insufficient and is investigating ways to expand its 2028 capacity beyond the previously planned 30% increase. However, the company has not disclosed revised production targets.

"Looking further ahead, we shared our intent last quarter to increase our capacity in 2027 by 30% for both Low NA EUV and DUV immersion systems, as well as to investigate adding a further 30% in 2028," explained Roger Dassen, Chief Financial Officer at ASML. "However, given the dynamics of this quarter, we now anticipate that our current planned levels of output in 2027 and 2028 will not fully meet the demand of our customers."

High-NA EUV adoption

Meanwhile, High-NA EUV adoption is progressing. Intel has already exposed more than one million wafers using High-NA systems and plans to start using High-NA EUV with its 14A process technology in 2028. Samsung plans to introduce High-NA EUV into high-volume manufacturing (HVM) in 2028 for DRAM and for logic later, while TSMC plans to use High-NA EUV scanners by 2030 – 2031. ASML says availability across its installed High-NA fleet is approaching 90%, which suggests that the tools are becoming mature enough for HVM deployment.

Interestingly, Samsung's planned 2028 introduction may create additional demand for High-NA equipment from memory manufacturers, as they will need to compete against their larger rival. However, ASML has not disclosed specific shipment targets for these tools.

New tools, more capacity

ASML also intends to increase semiconductor production capacity by introducing more productive lithography systems. Its upcoming Twinscan NXE:3800F, scheduled for introduction in early 2027, will process up to 260 wafers per hour, compared with 230 wafers per hour for the existing NXE:3800E. While this represents 'only' approximately 13% higher throughput, this translates to 21,600 extra EUV exposures per month without corresponding increases in cleanroom space. Three such tools per fab enable 90 additional EUV exposures per hour, 2,160 per day, or 64,800 per month. The company also plans to introduce a new critical-layer immersion DUV system capable of processing 330 wafers per hour.

Keep in mind that the actual fab capacity improvements depend on the number of lithography exposures required per wafer on a particular node, as well as the capabilities of other manufacturing equipment.

Another important element of ASML's strategy is its growing portfolio of productivity upgrade packages for existing EUV and DUV systems. Such upgrades enable chipmakers to increase wafer throughput without purchasing additional scanners, which can provide additional capacity considerably faster than procuring new tools or constructing new fabs.

Value-based pricing is a go

One of the controversial things that ASML discussed back in early Q2 was its value-based pricing, which many thought was a blanket price hike. This is not and CFO Roger Dassen this week confirmed that negotiations with major customers have been completed, although the financial benefits for ASML will not become visible immediately.

The company expects the first effects of higher pricing to appear during 2027, with the full impact becoming apparent in 2028 and beyond, which essentially means that the company is not setting new prices on its backlog, but generally setting new prices on new tools.

"We completed those conversations," said Dassen. "So that has been done with the key customers. The effect of that is not really visible in 2026. It will start to become visible partly in the course of 2027. The full impact of that you will start to see in 2028 and beyond."

This strategy could further improve ASML's already substantial gross margins, particularly as customers have no alternatives for advanced lithography equipment.

China remains important

Despite export restrictions that prevent Chinese chipmakers from acquiring EUV scanners and advanced DUV systems, China remains a substantial market for ASML. The company expects China to account for approximately 20% of its total revenue in 2026, which implies annual sales of roughly €8.8 billion to €9 billion based on current guidance.

Although China's share of ASML's business has declined from its levels in 2023 - 2025, the country's semiconductor manufacturers continue to invest in mature node capacity and equipment that remains available under existing export regulations. Meanwhile, it is impossible to predict what is going to happen if the U.S. lawmakers approve the MATCH Act.

Yet, ASML management emphasizes that its key growth opportunities lie with advanced logic and memory manufacturers, which are accelerating their investment in advanced lithography tools, including sophisticated DUV systems, Low-NA EUV machines, and High-NA EUV scanners.

The future of ASML

Thanks to gaining momentum in AI infrastructure investments, ASML reported record quarterly revenue of $13.06 billion (€11.7 billion) as demand for advanced lithography equipment continued to accelerate. The company expects demand to persist for years as its customers are interested in placing orders for tools to be delivered as far ahead as 2030. To meet growing demand, the company plans to expand production capacity beyond its previous targets for 2028. ASML also intends to introduce new EUV and DUV systems with higher productivity, offer productivity upgrades, and raise equipment prices to capitalize on unprecedented demand.

ASML has said that the unprecedented spending and investment brought about by the artificial intelligence (AI) boom is not slowing down at all, as customers are already lining up to place orders for its advanced chipmaking tools for 2029 and 2030, according to a Reuters report citing ASML's Q3 2026 earnings published today, October 14. ASML CEO Christophe Fouquet said that the company would struggle to meet the demand despite plans announced in July to raise capacity by 30% in 2027 and another 30% in 2028. The company also confirmed on Wednesday that it will raise prices starting in 2027, with the full effect showing in 2028.

The Dutch company's comments follow its Q3 2026 earnings report, which detailed a net profit of €4.96 billion on net sales of €11.7 billion. It projects Q4 sales of €14.2 billion to €15.2 billion ($15.9 billion to $17 billion), boosting its full-year sales projections from at least €43 billion to €44-45 billion. ASML's shares rose 2% on Wednesday, up almost 70% so far this year, with its €586 billion market valuation making it Europe's largest firm by market cap.

According to Reuters, there had been concerns that the AI investment boom was losing steam. However, positive projections from the largest manufacturer of the tools for making AI chips and advanced semiconductors signal that chipmakers will keep expanding, sustaining demand across the AI industry well into the foreseeable future. "There were concerns that the AI trade was running out of steam," Gordon Kerr, European macro strategist at KBRA, said. "Demand for chips remains strong, and infrastructure spending is likely to continue well into 2027."

ASML's customers include logic chip manufacturers such as Samsung, Intel, and TSMC, which manufactures chips for Nvidia, all of whom are heavily investing in increasing chip production. Memory chip makers SK Hynix and Micron ⁠have also announced expansion plans that involve ASML machines. Meanwhile, the company's CFO Roger Dassen said it is "still kicking the tires on the exact size of that (Terafab) opportunity," referring to Elon Musk's 100 million square feet semiconductor manufacturing facility that aims to output millions of logic and memory chips. Terafab will reportedly receive its first EUV chipmaking tool from ASML in mid-2027.

ASML's order book reflects a wave of spending across the AI industry. As of April this year, Google, Amazon, Microsoft, and Meta reportedly collectively planned to spend $725 billion on capex in 2026, up 77% from last year's record $410 billion. Since then, Alphabet has raised its 2026 capex guidance from $180–190 billion to $195–205 billion, Amazon from $200 billion to $220 billion, and Meta has raised the floor of its range from $125 billion to $130 billion, keeping its $145 billion ceiling. Some of the spending reflects rising chip prices, with Microsoft CFO Amy Hood attributing $25 billion of the company's record capex budget to higher prices for memory chips and other components. Still, analysts such as Gartner expect global AI spending to rise 49.5% in 2026 to $2.7 trillion and another 36.2% in 2027.

C.C. Wei, chief executive and chairman of TSMC, confirmed on Thursday that the company is considering expansion of its American production capacity beyond Arizona and Texas is one of the options it is evaluating. The head of the world's largest contract chipmaker also confirmed negotiations with Elon Musk regarding usage of Terafab, but stressed that to be a part of it, the fab must be managed by TSMC, which automatically excludes burgers and cigars in the cleanroom.

"We expanded our capacity consideration to see outside Arizona, whether we can get another chance to expand our capacity," said C.C. Wei during the company's earnings call with financial analysts and investors. "Texas is one [of our options]. We sent the teams to Texas to do all the evaluation.  We also talked to one of our customers, who is trying to build a fab, Terafab, let me be more specific."

Recently in transpired that Elon Musk's Terafab was in talks with TSMC over using the giant semiconductor production facility together. Elon Musk confirmed the negotiations, whereas TSMC did not comment.

"We are discussing with them to see whether we can be utilizing that actual capacity also," Wei added. "So, we are still in discussion. If we have any solid conclusion, we will share with you."

The information about negotiations between Elon Musk's Terafab and TSMC immediately triggered chatter that the parties are set to adopt TSMC's typical business model it uses for ESMC and JASM facilities under which it operates fabs co-owned with other investors. However, Musk then said that Terafab's facility would be operated by Terafab and TSMC could only sub-lease part of its cleanroom. Now, C.C. Wei said that if TSMC joins the project, it will insist on operating the fab.

"We are still in discussion," Wei replied when asked whether TSMC is not becoming a part of the Terafab project. "Let me say that. […] Either way, it will be possible, but the fab has to be run by TSMC."

The key question now is whether Musk and TSMC can agree on an arrangement that satisfies both parties. Musk wants Terafab to retain control of its manufacturing complex, whereas TSMC insists on operating any fab it uses. One potential compromise would be for Terafab to own the facility and lease a portion of it to TSMC, which would independently operate its production lines. Such an arrangement would allow Musk to retain ownership of the whole complex while giving TSMC control over select manufacturing lines. However, if Terafab itself uses Intel's 14A process technology at the facility, TSMC's presence there will be extremely complicated, if possible at all. In any case, so far the parties have not come to any agreement.

TSMC on Thursday reported revenue of $46.72 billion for the third quarter of 2026, up 41.2% year-over-year and 16.2% sequentially. The foundry's net income reached approximately $23.9 billion, an increase of 68.7% from the same quarter a year earlier, driven by elevated demand for chips used by AI infrastructure. The company's gross margin was 66.4%, which is below gross margins reported by DRAM makers, but still a historic record.

For the fourth quarter of 2026, TSMC expects revenue between $52.3 billion and $54.3 billion, which represents approximately 14% sequential growth at the midpoint. The company projects gross margin between 65% and 67%, up both sequentially and YoY.

Geopolitics and sanctions have mostly cut off the Russian public from Western hardware — at least officially. In recent ages, the country's homegrown chip designs are Arm, RISC-V, and Elbrus architectures. A handful of interesting designs were on display at the Microelectronics 26 (ME26) forum in Sochi, using retro gaming as a demonstration point. A couple of years back, the government even issued an order to create a high-end gaming console, albeit with relatively little success. The result of that initiative didn't appear to be on display at the event.

The report comes from Dmitrii Kuznetsov, a RISC-V and Rust enthusiast who displayed photos from the event. The first units on display use Baikal Electronics' BE-U1000 microcontroller. According to our digging, the chip packs a CPU with three CloudBear cores (32-bit RISC-V) — two BR-350s clocked at 200 MHz, along with a BM-310 at 100 MHz.

Given the microcontroller nature, embedded resources are intentionally sparse, with 256 KB of flash and 192 KB of SRAM — though there's support for external flash. A host of I/O interfaces, including USB 2.0, I2C, I2S, UARTs, and 48 GPIO lines, round out the 10x10 mm QFN-88 package. These parts are seemingly aimed at robotics, automation, IoT, sensors, and similar applications.

There was a business card-sized controller-and-console on display with a BE-U1000 chip, along with an "Ushka" console styled like the original NES (with matching controllers). The game on display appears to be Chip 'n Dale: Rescue Rangers.

Next up, there's the Elvis Hypercom-U, a SoC packing four Arm Cortex-A53 CPU cores at up to 1.2 GHz, dual ELcore-50 DSPs, a PowerVR GE8300 GPU, and dedicated video, image, and navigation processing blocks. The main silicon can be paired with up to 8 GB of LPDDR4, and supports USB 3.0, Gigabit Ethernet, Wi-Fi, and Bluetooth connectivity, and HDMI output.

This product is apparently aimed at multimedia, navigation, SBCs, and smart cameras. At the show, a board with the Hypercom-U was shown playing the original Super Mario as a demonstration.

Finally, there were MCST's Elbrus-based PCs, though the tweeter offered few details on which were on display. For context, Elbrus is a Russian-developed chip architecture, often poised as the basis for high-end desktop and server applications.

Our best guess is that the machines at the forum were based on the leading-edge Elbrus-16S chip with 16 cores at up to 2 GHz and up to 8 channels of DDR4-3200 RAM. The chip is manufactured on a 16 nm process and comprises 12 billion transistors. There are dual-processor server prototypes with up to 2TB of RAM using this design.

The other chip likely being demoed is the Elbrus-2S3, a chip targeted at mini-PCs and laptops. We've covered the Rostec MP21 previously, a Raspberry Pi-like machine with 8GB of RAM and SSDs up to 480GB. The 16-nm SoC is fairly decent, clocked at up to 2 GHz and capable of 196 GFLOPS. There's support for DDR4-3200 and PCIe 3.0, but power consumption can be fairly nasty, as the MP21 board can chew around 40W.

Two workers have been confirmed dead and another seriously injured after an explosion at Intel’s Kiryat Gat plant in southern Israel on Wednesday, The Times of Israel reports. Police suspect a gas cylinder malfunction caused the explosion, and Israel’s Fire and Rescue Services said the fire involved nitrogen trifluoride (NF3), a toxic gas mainly used to clean the process chambers of chipmaking tools. So far, Intel hasn’t made any statements about the victims or about any potential production impacts at the site.

The site houses Fab 28, which, per Intel, makes “processors, 5G, and AI products” on Intel 7, formerly 10nm Enhanced SuperFin. Intel 7 products include 13th and 14th Gen Core “Raptor Lake,” 5th Gen Xeon “Emerald Rapids,” and the I/O die of Xeon 6 “Granite Rapids,” although these are not explicitly linked to the site. Fab 38, adjacent to Intel’s existing Kiryat Gat fabs, was announced in December 2023 with a $3.25 billion Israeli grant but has been paused since mid-2024. Intel reportedly considered closing Fab 28 in July 2025, but no closure decision has been announced.

The Kiryat Gat police commander at the scene laid out the sequence: a blast occurred during a material transfer into the factory’s tanks after one truck had disconnected and another connected. At least eight Fire and Rescue Services teams, including hazmat, searched for trapped people, contained the fire, and monitored the hazardous substance.

“At this moment, I cannot point to any suspicion of criminal activity or negligence,” the commander added. Magen David Adom, Israel’s national emergency medical service, said two of the injured underwent resuscitation efforts and all three suffered severe burns. Ultimately, one of the injured was pronounced dead, a second later died of their wounds, and one remains hospitalized in serious condition inside the ICU, based on a statement from Soroka Medical Center in Beersheba.

The gas, although hazardous if inhaled, is not flammable. It’s not clear if the trucks were delivering NF3 or if it was directly involved in causing the explosion. Once the fire was put out, crews kept cooling the scene to prevent a secondary incident, and the commander said things appeared to be under control, with no sign so far of further leaks and no need to evacuate residents or factory workers. Kiryat Gat Mayor Kfir Suissa told residents to stay away while crews worked and added, “There is no danger to the public.”

At the time, there was no word on possible production delays, but these would be problematic as Intel 7 capacity was already tight. Last year the company’s CFO said that Intel 7 and Intel 10 constraints had limited its ability to meet demand, with shortages expected into 2026 with server wafers getting priority. Intel reports third-quarter results on Oct. 29 and will hold a call to discuss them, although the company has not mentioned whether it will address the explosion.

Advanced packaging technologies have become integral parts of advanced CPU and GPU designs, and virtually all of Intel's high-end client and data center CPUs rely on its Embedded Multi-die Interconnect Bridge (EMIB) and Foveros technologies. But what's next for these two advanced packaging methods? Before we try to see where both technologies are going, let's first take stock of where we are today.

Although Intel's advanced packaging saga began in 2017 with the Kaby Lake-G CPUs and Stratix 10 FPGAs, packaging technologies weren't quite the hot topic they are today. However, both Intel and its industry peers were working relentlessly to advance these technologies, so Intel was among the first companies to outline a detailed roadmap for multi-chiplet processors featuring its 2.5D and 3D integration technologies — EMIB and Foveros — back in 2020. Following the fiasco with its initial 10nm process technology, the company made it clear that its multi-chiplet strategy is a sustainable way to deliver performance and feature enhancements cost-efficiently and at a predictable cadence. While we certainly cannot say that all of Intel's multi-chiplet projects were a success, it is safe to say that the majority of Intel's client and data center CPU products launched in recent years use multiple chiplets and rely on EMIB and Foveros advanced packaging technology.

In fact, as Intel's advanced packaging roadmap evolves, EMIB and Foveros not only become more sophisticated to address the demands, but they also become simpler to cover cost-sensitive products. Another peculiarity about Intel's packaging duo is that they no longer seem to be two mostly separate technologies. In many cases, they complement each other and Intel's upcoming process technologies, thereby becoming key building blocks of the company's future products. The ultimate goal is to build system-in-packages (SiPs) the size of 12 reticles using both EMIB and Foveros Direct 3D, but Intel is not quite there yet, so let's take a look at where we are today and what's on the horizon.

EMIB: Fantastic bridges and where to find them

Intel's EMIB has evolved dramatically since entering high-volume manufacturing in 2017. What started as a relatively straightforward way to connect adjacent chiplets without using an expensive silicon interposer has become a sophisticated packaging technology used for data center processors and is set to enable massive AI accelerators 12 times the size of a reticle with dozens of silicon bridges, more than 24 HBM stacks, and advanced power delivery.

The basic idea behind EMIB remains unchanged almost a decade after its first introduction. Instead of placing compute and memory dies on a large silicon interposer, Intel embeds tiny silicon bridges into an organic package substrate only where high-density die-to-die connectivity is required (try to find those bridges!). This reduces silicon usage and allows the rest of the package to use conventional substrate wiring and relaxed bump pitches. Early EMIB implementations used a 55-µm first-layer-interconnect (FLI) bump pitch, which Intel subsequently reduced to 45 µm. Intel's recent roadmaps indicate further reductions to around 36 µm and ultimately 25 µm, which dramatically increases the number of connections that can fit along a chiplet's edge (shoreline density).

In addition to shrinking FLI bump pitches and increasing connection density, Intel is also adding functionality to the bridges themselves. EMIB-M incorporates metal-insulator-metal (MIM) capacitors into the bridge to improve power delivery and suppress voltage fluctuations close to compute dies. The newer EMIB-T takes this concept considerably further by adding through-silicon vias (TSVs), which enable power to travel vertically through the bridge instead of taking longer paths around it. This becomes increasingly important for multi-kilowatt system-in-packages (SiPs) and HBM4-class memory subsystems, where both current density and power integrity are major packaging constraints.

Such SiPs are not only complex, but they are physically large, so Intel's EMIB has evolved to support larger designs. Firstly, a finer FLI pitch increases the interconnect density required to build bigger SiPs. Secondly, EMIB-M addresses the power-integrity problem created by big processors, such as Intel's Xeon 6 'Granite Rapids.' Thirdly, EMIB-T simplifies power routing, lowers impedance, and reduces noise, which will get more important when faster versions of UCIe (32 GT/s and higher) become commonplace. Intel's consistent EMIB technology development has enabled the company to move from an SiP of 4X reticle size on an 80×80 mm package earlier this decade, to something closer to 8X reticles on a 120×120 mm package today, and even larger 12X SiPs on a 120×180 mm package in the future.

Eventually, Intel plans to combine finer-pitch EMIB technology with glass-core substrates. Glass offers better stability and reduced warpage compared with organic materials, which becomes increasingly important as packages grow to enormous sizes. Glass will likely be one of EMIB's biggest advancements, as it will enable improvements in multiple directions, including performance and dimensions.

Intel says EMIB-T is on track for mass production in 2027 and its yields and reliability are meeting its targets. If those ramps proceed as planned, EMIB will have evolved from an alternative to a silicon interposer into one of Intel Foundry's key technologies for building massive AI systems.

"Customer interest in EMIB-T continues to be very high – the technology is compelling, providing capabilities for advanced AI silicon solutions which are not possible with today's mainstream offerings," said Lip Bu Tan, chief executive of Intel, in an August 2026 earnings call. "We continue to have a growing EMIB-T backlog, yield and reliability are hitting targets, and we are focused on ramping the technology into high volume and high quality to support customer ramps in 2027."

Intel is scaling EMIB along several directions simultaneously: finer interconnect pitch, more bridges, larger substrates, denser power delivery, faster memory interfaces, and dramatically larger SiPs. Intel formally positions EMIB as a cost-effective advanced packaging technology that uses local silicon bridges for logic-to-logic and logic-to-HBM connections in an organic substrate instead of large silicon interposers used by solutions like TSMC's CoWoS-S. Meanwhile, there are applications that can benefit from large, rigid interposers or flexible organic redistribution layer interposers. To address these applications, Intel's Foveros portfolio includes Foveros-S, Foveros-R, and Foveros-B, which more directly mirror TSMC's CoWoS-S, CoWoS-R, and CoWoS-L packaging technologies, respectively.

Foveros 2.5D: A fistful of packages

Intel's Foveros packaging technology is evolving from its original chip-on-wafer implementation that emerged in 2019 with the Lakefield processor into a broad family of 2.5D and 3D integration technologies designed to address everything from cost-sensitive client processors to large HPC and AI systems.

The original Foveros technology used an active 22FFL-based silicon base die, or interposer, with through-silicon vias (TSVs) and active dies attached using face-to-face bonding. Intel's Lakefield and Ponte Vecchio used active base dies and 36 µm microbump pitches, whereas Meteor Lake, Arrow Lake, and Panther Lake implementations use a passive base with a 36 µm microbump pitch. Since the introduction of Foveros with active and passive base dies in 2019 – 2023, Intel has also diversified Foveros to address different cost and integration requirements. The latest Foveros 2.5D roadmap — which mentions -S, -R, and -B variants with similar characteristics — presented in mid-2025, takes Foveros considerably further from its original capabilities: it targets pitches below 25 µm, bump density increase from 772 to 1,600 connections per mm², and chip-to-chip interconnect power of 0.15 pJ/bit.

For now, the most advanced and yet production-proven Foveros 2.5D technology is Foveros-S. This packaging technology places multiple chiplets on a silicon interposer and currently supports packages up to four reticles in size, which is below what TSMC offers with CoWoS-S (up to 5.5X reticles). Since Foveros-S is essentially an evolution of the original Foveros from 2019, Intel legitimately says that it has been in volume production since 2019. Yet, going forward, Foveros-S will be evolving in multiple directions, which includes larger package sizes, interconnect density, and interconnect power efficiency.

Foveros-R removes the silicon interposer altogether and uses fan-out RDL technology to optimize cost and interconnect density. Intel says the implementation can use up to three redistribution layers. The method is designed to offer a balance between cost and interconnect density and enable heterogeneous integration of chiplets from different sources through UCIe. Like the other members of Intel's current Foveros 2.5D family, the technology uses 36 µm microbump pitches, but is designed to support pitches below 25 µm as well as bump density scaling from 772 to 1,600/mm² and chip-to-chip interconnect power of 0.15 pJ/bit. Intel says Foveros-R will be production-ready in 2027.

Foveros-B extends the concept toward larger and more complex AI/HPC designs. Instead of relying on a full silicon interposer, the technology combines RDLs with local active or passive silicon bridges that provide high-density connections only where they are needed. This potentially gives Intel an intermediate option between an RDL-only implementation and a large silicon interposer, as well as a direct competitor for TSMC's CoWoS-R.

Note that Intel does not explicitly say that Foveros-B uses EMIB bridges, though given similar microbump pitch sizes and the plan to use active local bridges in the future, Foveros-B's bridges are likely to closely resemble EMIB-M and EMIB-T bridges. If Foveros-B can indeed use EMIB bridges, future Foveros-B designs could also incorporate cache disaggregation, integrated voltage regulators (IVRs), or MIM capacitors.

As for interconnection densities and power, Foveros-B is listed as designed to support pitches below 25 µm, bump density scaling up to 1,600/mm², and chip-to-chip interconnect power of 0.15 pJ/bit. Meanwhile, Intel has not disclosed when Foveros-B will be ready for commercial production, so its actual specifications remain to be seen.

With EMIB and the Foveros 2.5D portfolio, Intel can address a broad range of applications, but Intel's scaling is not stopping. In addition to 2.5D lateral scaling enabled by EMIB or Foveros 2.5D, it can stack chiplets on top of each other using its Foveros 3D and EMIB 3.5D packaging technologies.

Foveros Direct 3D: There will be copper (and no bumps)

Unlike simple package-on-package stacking, which has existed for decades, densely interconnected 3D stacking essentially turns separate dies into parts of the same tightly coupled chip, increasing bandwidth, reducing latency, cutting interconnect power, and shrinking footprint. The challenge is manufacturing thousands of extremely fine connections between dies while maintaining yield, power delivery, signal integrity, and — perhaps most importantly — removing heat from chips buried inside the stack.

The biggest architectural step in Intel's Foveros roadmap is Foveros Direct 3D, which moves from microbump-based connections toward direct copper-to-copper hybrid bonding. Conventional microbumps cannot shrink forever, as solder bumps need sufficient dimensions to maintain manufacturing yield and reliability, while the solder itself introduces additional resistance and parasitic effects. Foveros Direct 3D eliminates solder altogether and directly bonds copper pads on one die to those on another, which enables an interconnect pitch below 10 µm — up to 10 times finer than conventional microbump technology.

Intel claims that Foveros Direct 3D can offer bonding pitch of sub-10 µm, interconnect density of up to 10,000 connections per mm², and chip-to-chip interconnect power below 0.05 pJ/bit. Such dense connectivity shortens signal paths between stacked dies, increases bandwidth, reduces latency, and cuts the energy required to move data. In addition to electrical advantages, direct bonding creates more continuous thermal paths between dies, which Intel says improves heat dissipation compared with conventional packaging, which is crucially important as vertically stacked logic pushes power density dramatically higher.

Intel's Foveros Direct 3D bonding interface supports both face-to-back and face-to-face stacking. In addition, Intel has described chip-to-wafer as well as wafer-to-wafer bonding.

As Intel's schematic drawing of a Foveros Direct 3D-based system-in-package shows (and Intel confirms), the technology is much more flexible than simply placing one logic die on top of another. The method can support different die sizes, multiple stacking levels, and can combine dies manufactured using different process technologies in one SiP.

Intel's Xeon 6+ 'Clearwater Forest' processor is the first product to use Foveros Direct 3D copper bonding in volume to attach Intel 18A compute chiplets to active base dies. The CPU uses the 1^st Generation Foveros Direct 3D with 9 µm copper bonding pitch. Meanwhile, Intel plans to shrink bonding pitch to 3 µm with its 2^nd Gen Foveros Direct 3D. To put these numbers into perspective, TSMC's 1^st Gen SoIC from 2023 supports pitches of 9 µm (AMD's 2^nd Gen 3D V-Cache uses this version), whereas the latest generation that entered volume production in 2025 features bonding pitches of 6 µm. TSMC expects to shrink SoIC's interconnection pitch to 4.5 µm by 2029.

EMIB 3.5D: Everything everywhere all at once

Finally, Foveros and EMIB do not have to operate independently. Intel can combine Foveros 2.5D or Foveros Direct 3D with substrate-embedded EMIB bridges to create what it calls EMIB 3.5D in a bid to build its ultimate products. In this architecture, Foveros provides dense local 2.5D or 3D connectivity within individual chiplet assemblies, while EMIB provides high-bandwidth horizontal connections between these modules, essentially building a massive system-in-package out of smaller SiPs. Intel says the individual SiPs can be identical to scale performance, or distinctive, to enable different functionality.

The combination of EMIB and Foveros is particularly useful because it enables Intel to scale both horizontally and vertically without placing the entire system on one massive silicon interposer. Intel says EMIB 3.5D can achieve a total silicon surface area considerably larger than what its existing silicon-interposer-based technologies can accommodate. Intel first used EMIB 3.5D to build its Ponte Vecchio compute GPU that integrated 47 active tiles manufactured on five process nodes and contained more than 100 billion transistors. Although Intel's Data Center GPU Max can hardly be called a smashing success, it certainly demonstrated what Intel can do with its advanced packaging technologies.

Going forward, the EMIB 3.5D architecture becomes considerably more promising when combined with Foveros Direct 3D. Using both will enable Intel to build tightly coupled compute modules using ultra-dense vertical copper-to-copper connections, and then link multiple modules laterally using EMIB, essentially scaling complex processors both vertically and horizontally. However, surprisingly, Intel decided not to use EMIB 3.5D for its next-generation Xeon 'Diamond Rapids' processor: while the CPU uses Foveros Direct 3D for vertical integration, UCIe-S connections are used for lateral interconnects.

Multi-die another day

While Intel's EMIB and Foveros technologies emerged to serve different kinds of scaling, the company is evolving them into a complementary platform that can scale complex processors both horizontally and vertically.

EMIB is progressing toward finer interconnect pitches, vertical power delivery, glass substrates, and packages exceeding 12 reticles with more than 24 HBM stacks, while the expanding Foveros family spans from 2.5D integration all the way to ultra-dense Foveros Direct 3D hybrid bonding. In fact, Foveros Direct 3D already enables sub-10-µm copper-to-copper connections and is headed toward even finer pitches.

Meanwhile, EMIB 3.5D combines vertically stacked modules with lateral EMIB links to create large heterogeneous system-in-packages for ultimate AI and HPC applications without using enormous silicon interposers.

What is perhaps interesting to note is that, for now, Intel lacks a system-on-wafer platform to enable Cerebras WSE and Tesla Dojo-like wafer-scale processors, though this is explainable, as demand for such technologies is too limited today and may not pick up significantly tomorrow.

Elon Musk's Terafab will get its first EUV lithography tool in the middle of next year, reports Tim Culpan, citing sources with knowledge of the matter. But considering that the shell of the firm's development fab will not be completed until late 2027 and that tools will only begin to be moved in later that year, according to SemiAnalysis, the scanner will sit idle for some time.

Tesla broke ground on its research fab on the north campus of Giga Texas near Austin this past April. SemiAnalysis expects the building to be completed in 15 months and predicts it will take Tesla a further six months to install equipment and production tools, after which it will be able to start processing wafers, or rather experimenting with chip production to get the team prepared for completion of the Terafab volume fab phase 1.

Given how hard it is to get an ASML Twinscan NXE EUV lithography tool these days, storing it for several months before putting it to use may sound like an expensive slack period, but it's not the significant financial problem for Terafab that it would be for a traditional chipmaker.

The projected delivery of a conventional EUV lithography system to Terafab also indicates that while Elon Musk has praised free electron laser (FEL) light sources for lithography tools, the first-generation efforts of his semiconductor production company will rely on more traditional equipment. This is not particularly surprising, as Terafab is set to use Intel's 14A manufacturing technology. 14A will use not only existing Low-NA EUV scanners, but also next-generation High-NA EUV machines.

Using lithography systems with unconventional and largely untested light sources would require substantial modifications to the manufacturing process, extensive equipment qualification, and potentially changes to photomasks and photoresists, which would complicate the transfer of Intel’s 14A technology and delay Terafab's production ramp.

But usage of standard lithography equipment does not mean that Musk's company has no plans to use tools that are different from those used by Intel, though for now it is too early to make guesses about what Terafab engineers might change in terms of fab configuration.

SpaceX announced that it had selected Grimes County for Terafab in early August 2026. By now, there is evidence that work has progressed beyond clearing land, as drone footage published by Joe Tegtmeyer in mid-September showed foundation excavation and rebar cage installation at the northwestern part of the site. This suggests that contractors had begun structural construction by early September, although the precise purpose of the foundation is unknown.

Right now, SemiAnalysis reports that project Terafab Grimes phase 1 will be built in 20 months, equipped in 17 months, and ramped to volume in six months. Analysts project that the fab will begin operation in late 2029 and then ramped to volume by mid-2030.

An interesting note about Terafab's volume fab is that SpaceX reportedly ordered semiconductor manufacturing equipment in April 2026, several months before officially announcing the Grimes County location. This indicates that the company committed to its manufacturing plans well before the public groundbreaking. In addition, this makes the mid-2028 equipment installation forecast plausible, given the long lead times associated with advanced semiconductor manufacturing equipment.

Intel plans to begin risk production using its 14A (1.4nm-class) fabrication process in the second half of 2027 and initiate high-volume manufacturing (HVM) in the second half of 2028 if everything goes as planned. This puts Intel's ramp into HVM at least 1.5 years ahead of SpaceX’s Terafab Grimes Phase 1.

This means that while Terafab will get a proven advanced manufacturing technology, presumably with decent yields, it will not be the absolute best production node at the time, as TSMC intends to start volume production of chips using its A12 fabrication process in late 2029. A12 is a 1.2nm-class process with TSMC's second-generation nanosheet GAA transistors and backside power delivery. Intel will be close to unveiling its 14A-P node at the same time.

Nonetheless, since Terafab will likely exclusively serve SpaceX, Tesla, and xAI, a slightly less advanced node will not be a big problem for the company, as the potential cost increases incurred by using a more sophisticated manufacturing technology will be offset by using an in-house production facility.

When GlobalFoundries abandoned development of leading-edge nodes in 2018, it also canceled the development of its 7nm-class FinFET fabrication technology that it co-developed with IBM. Almost exactly eight years later, GlobalFoundries is back with a 7nm-class manufacturing process, only this time the node relies on planar transistors and fully-depleted silicon-on-insulator (FD-SOI). It is aimed at automotive, edge AI, industrial, robotics, sensors, and other devices that prioritize low power consumption, high integration, and cost efficiency over maximum performance.

"We are delighted that GlobalFoundries has announced its next-generation 'single-digit FD-SOI; node, building on technology that CEA-Leti has been advancing for decades," said Sébastien Dauvé, chief executive of CEA Leti. "Through the FAMES pilot line, CEA-Leti continues to shape the future European roadmap for FD-SOI and works every day to promote its adoption in a wide range of applications."

FDX Fusion enters the scene

The new fabrication technology from GlobalFoundries is called FDX Fusion, and it promises 7nm-class 'digital performance' (an ambiguous claim; we will try to interpret it later) and more than twice the transistor density of its original 22FDX process introduced circa 2015. To achieve its target goals, the first generation of FDX Fusion will combine innovations in SOI substrates, transistor structures, and back-end interconnects, though keep in mind that GF has not disclosed transistor dimensions, contacted gate pitch, minimum metal pitch, or actual transistor density. GF plans to launch production of chips on FDX Fusion at its Dresden, Germany, facility in 2028, which will mark its return to the development of substantially more advanced FD-SOI fabrication processes after years of efforts to enhance its existing 22nm-class platform.

In addition to improved 'digital performance,' FDX Fusion will support RF transistors with fT/fmax of up to 0.5 THz, analog and mixed-signal circuitry, embedded nonvolatile memory, and in-memory computing capabilities. The combination is intended to enable highly integrated chips that can process information from sensors, execute AI inference workloads, control external devices, and communicate wirelessly without the need for numerous separate ICs. GF also intends to provide processor IP based on MIPS, ARC, and RISC-V architectures to accelerate the development of such products.

That being said, the main selling point of FDX Fusion is not necessarily its 7nm-class 'digital performance' and high-performance processor IP, but rather its ability to combine relatively powerful digital logic with RF, analog and mixed-signal circuitry, embedded nonvolatile memory, and in-memory computing capabilities on a single chip. This combination — which is why GloFo calls the process technology FDX Fusion — could enable highly integrated SoCs that would otherwise require multiple chips manufactured on different process technologies, which means additional tapeout costs as well as power consumption.

GlobalFoundries said it plans to deliver initial demo silicon for customer evaluation in early 2027, followed by the first process design kit (PDK) in mid-2027. The company is already collaborating with several customers on the technology, although it has not identified specific products or committed production volumes. Specifically, GF mentioned in its press release that BMW, Bosch, Infineon, NXP, Siemens, and Tesla have expressed interest in FDX Fusion, though only Infineon specifically confirmed collaboration on future 7nm-class technologies for radar and wireless communications.

Significant development

The GlobalFoundries announcement represents a significant development for GF's FD-SOI roadmap. The company introduced 22FDX in 2015 and announced its 12FDX successor in 2016, which promised performance comparable to 10nm FinFET, full-node density improvements, and up to 50% lower power consumption. Initial 12FDX customer tape-outs were expected in 2019, but the technology has never been adopted for commercial products. Instead, GF focused on enhancements to 22FDX and eventually the introduction of 22FDX+ (around the time when Samsung unveiled its 18FDS+), with additional capabilities for RF, embedded memory, and low-power applications. Interestingly, 12FDX was still a part of GF's investor roadmap in 2022.

FDX Fusion could therefore represent the realization of GF's original ambitions to scale FD-SOI beyond 22nm-class, although the company has not explained whether the new technology incorporates developments from its earlier 12FDX program. Meanwhile, CEA-Leti, which has conducted research into advanced FD-SOI technologies for years, describes FDX Fusion as a single-digit FD-SOI node. Nonetheless, GF's claim of 7nm-class 'digital performance' does not necessarily imply comparable transistor dimensions or integration density.

From an industry perspective, FDX Fusion could provide an alternative to advanced FinFET and perhaps even gate-all-around processes for applications that require reasonably powerful digital logic alongside RF, analog, and embedded memory. Such integration could reduce system complexity and power consumption, particularly in edge AI devices where energy efficiency and real-time responsiveness are critical.

Perhaps more importantly, the technology could give European semiconductor developers access to a more advanced locally manufactured process without dependence on leading-edge foundries in Asia or the U.S.

Questions remain

However, the commercial success of FDX Fusion will depend on its actual performance, density, production costs, and the availability of a competitive design ecosystem, the latter arguably being the hardest part given the lack of any comments from leading electronic design automation (EDA) and IP developers.

When GlobalFoundries claims 2X 'digital performance' comparable to that of 7nm-class technologies, it doesn't reveal whether it means transistor switching speed, standard cell performance, achievable operating frequency, or something else. In addition, the company promises more than twice the logic density of its first-generation FDX technology, although the firm does not reveal any actual numbers. Consequently, it is unclear how FDX Fusion will compare with established 7nm-class FinFET technologies, which offer mature defect density and yields, plenty of supply, an established design ecosystem, and predictable pricing among other things, in terms of transistor density, performance, power consumption, and production costs. While CEA-Leti's comment seems promising, actual numbers are always better.

The very fact that GF's FDX Fusion planned 2028 introduction will come roughly nine years after the originally anticipated first 12FDX tape-outs illustrates significant technological and/or financial difficulties associated with the development of FD-SOI beyond the 22nm generation. So, while GlobalFoundries' FDX Fusion initiative certainly looks promising, it remains to be seen how that is going to play out for the contract chipmaker and its clients.

For now, the lineup of supporters from the automotive and industrial sectors — BMW, Bosch, Infineon, NXP, Siemens, and Tesla — certainly looks promising. But what about other applications? While established semiconductor companies such as Infineon and NXP already possess extensive processor IP portfolios, smaller fabless developers could benefit from GF’s MIPS and ARC processor cores, RISC-V expertise, and custom chip design capabilities, which could substantially reduce the cost and complexity of developing specialized SoCs. Still, to attract a broader range of chip developers, GlobalFoundries will need a mature ecosystem of EDA tools, standard-cell libraries, memory compilers, interface IP, and other silicon-proven building blocks. These are the things that GlobalFoundries has not touched upon in its press release.

GlobalFoundries and TSMC have entered into a five-year manufacturing agreement valued at $2 billion under which GlobalFoundries will produce silicon interposers for TSMC's CoWoS advanced packaging technology. The arrangement will establish a U.S.-based manufacturing source for these components, which will enable TSMC's clients to brand their products as completely made and packaged in America. Volume production is scheduled to ramp up in the first half of 2028.

"By providing manufacturing service using GF's trusted U.S. manufacturing footprint, we are creating a secure, scalable source of essential advanced-packaging elements that will help customers accelerate innovation and strengthen the semiconductor supply chain," said Ed Kaste, senior vice president of CMOS Business at GlobalFoundries.

GF and TSMC team up

Under the agreement, GlobalFoundries will expand manufacturing capacity at its fabrication facility in Malta, NY, to produce silicon interposers used in TSMC's CoWoS-S packaging ecosystem. Such interposers are custom pieces of silicon that provide high-density connections between logic chiplets and high-bandwidth memory (HBM) stacks and enable the creation of complex multi-die processors for artificial intelligence (AI) and high-performance computing (HPC) applications. The companies have not disclosed the production capacity to be installed, but the agreement provides a framework for additional expansion depending on demand.

Silicon interposers used for TSMC's CoWoS-S packaging technology are customized for particular processor designs, as their configurations depend on the number, dimensions, and placement of logic chiplets and HBM stacks, as well as the interconnections between them.

In addition, interposers must meet the power-delivery requirements of specific processors, including power distribution networks and embedded deep trench capacitors (DTC), and their designs must account for signal integrity, power integrity, and thermal characteristics. Furthermore, large interposers may exceed the maximum lithographic reticle size and therefore require stitching, so it remains to be seen how well GlobalFoundries will stitch such interposers for extra-large system-in-packages (SiPs).

While certain manufacturing processes and structural elements can be standardized, the resulting interposers are generally application-specific. GlobalFoundries will not be a TSMC supplier, but a subcontractor that will manufacture multiple customer-specific interposer designs rather than standardized components that require close cooperation with TSMC. Specifically, GlobalFoundries will need to ensure compatibility between its design rules, manufacturing processes, and qualification procedures so that interposers produced by GF can be used in TSMC's CoWoS packaging flows. It remains to be seen how the companies will handle ownership and protection of intellectual property, as interposer layouts may incorporate technologies and production methods specific to TSMC and its customers.

By transferring some interposer production to GlobalFoundries, TSMC could free up some of its own manufacturing resources and increase availability of components required for advanced packaging.

Manufacturing silicon interposers is only one part of the CoWoS-S production process. The technology also requires attaching logic chiplets and HBM stacks to interposers using high-precision bonding equipment, assembling the resulting structures onto organic substrates, and then performing electrical testing. These operations require dedicated manufacturing capacity, which the agreement between the two companies does not address.

Becoming a part of TSMC's CoWoS ecosystem

Following its exit from development of leading-edge process technologies in 2018 and consequent inability to produce leading-edge AI and HPC accelerators, GlobalFoundries is now becoming a part of TSMC's advanced packaging supply chain in the U.S. that will supply custom components for AI and HPC processors.

For GlobalFoundries, the agreement represents an opportunity to participate in the manufacturing of advanced AI processors without producing their leading-edge logic dies. Although the company abandoned the development of leading-edge process technologies eight years ago, its manufacturing capabilities remain suitable for producing certain components used in sophisticated multi-chip packages, including CoWoS-S interposers. It remains to be seen though whether it can also participate in TSMC's CoWoS-L supply chain.

The agreement with GlobalFoundries is particularly important considering TSMC's plans to establish advanced packaging operations in Arizona. The company intends to introduce CoWoS and 3D-IC packaging capabilities in the state before 2029 and has signed a 10-year agreement with Amkor Technology, which is building an advanced packaging facility in Peoria, Arizona, that is scheduled to begin production in early 2028.

As GlobalFoundries ramps up interposer production in New York in the first half of 2028, TSMC could potentially establish a largely domestic CoWoS supply chain that comprises logic dies manufactured in Arizona, silicon interposers produced in New York, and advanced packaging and testing performed by TSMC and/or Amkor in Arizona. For a while, HBM stacks would still have to be sourced from memory manufacturers in Asia, though both Micron and SK hynix intend to bring HBM assembly facilities to the U.S. already this decade, so it is safe to say that the U.S. will have a vertically integrated supply chain for production of advanced AI processors by 2029 – 2030.

There is a catch, though, as GloFo and TSMC have not disclosed how CoWoS assembly operations will be divided between TSMC and Amkor, or whether GlobalFoundries' interposers will be used in Arizona at all. Yet, GF's wording about a trusted U.S. manufacturing footprint strongly implies that its interposers will be primarily aimed at SiPs fabricated entirely in the U.S. Meanwhile, expanding interposer production alone will not increase the number of finished AI processors unless sufficient chip-on-wafer assembly and testing capacity is available.

Some things remain unclear

The initial agreement covers five years and establishes a mechanism for further capacity additions. However, the companies have not disclosed the planned manufacturing volumes, capital expenditures associated with the expansion, or the breakdown of the $2 billion agreement. Furthermore, we yet have to find out how GF's manufacturing capabilities are aligned with CoWoS-S' advancements.

U.S. Semiconductor Manufacturer Wolfspeed Inc. has received a conditional 30-year, $1.5 billion loan commitment letter from the U.S. Department of War (DoW) through its Office of Strategic Capital (OSC), as the country continues its push to boost domestic semiconductor manufacturing. According to an official press release on Oct. 7, Wolfspeed — which specializes in silicon carbide (SiC) and gallium nitride (GaN) materials and devices — will use the long term-financing to upgrade its GaN epitaxy capabilities and to develop radiation hardening capabilities for current SiC and future GaN products.

The company says SiC and related technologies are “critical to next generation power and radio-frequency applications across defense, aerospace, AI, critical infrastructure and other strategic commercial markets,” and that it will focus on U.S. national security applications, including communications infrastructure and electronic warfare systems. “SiC and GaN have critical national security applications,” said Wolfspeed CEO Robert Feurle. “With this financing, the company would be well positioned to not only continue to serve the DoW but also expand its capabilities for the benefit of U.S. national security as a whole,” he continued.

Under the terms of the loan — which is subject to final agreements — Wolfspeed is required to issue the DoW warrants to buy up to 7.5% of its fully diluted equity. The warrants would be priced off the stock's volume-weighted average price (VWAP) and handed over in proportion to each tranche of the loan as it's funded. As of this report, the loan remains conditional, pending the OSC’s completion of its due diligence. Wolfspeed also needs to secure government approvals and appropriations, as well as the consent of its existing lenders. The company itself warns there's no guarantee the financing will go through.

“This conditional 30-year commitment represents another significant milestone in our ongoing efforts to optimize Wolfspeed’s capital structure and improve our financial foundation,” said Wolfspeed CFO Gregor van Issum. “Subject to the satisfaction of diligence, negotiation of definitive agreements, and other financial, legal, and investment conditions, the broader commitment is expected to provide additional long-dated capital to support our strategic priorities, improve financial flexibility, and further position Wolfspeed for long-term value creation.”

The announcement marks the U.S.’s latest move to onshore critical semiconductor manufacturing and strengthen the domestic supply chain, combining direct capital subsidies, major tax incentives, and strict regulatory changes. Through the $54.2 billion CHIPS and Science Act, the U.S. government has injected billions into massive fabrication facilities for industry leaders like TSMC, Intel, GlobalFoundries, and Micron, while simultaneously utilizing the Section 48D Advanced Manufacturing Investment Credit to offer a 25% tax credit that has led to over $827 billion in private sector announcements.

A little less than seven months since signing a memorandum of understanding (MOU) concerning memory supply and collaboration in various fields with Samsung, AMD's chief executive Lisa Su is visiting South Korea to secure additional supply of HBM memory for AI accelerators, reports Chosun.biz. Meanwhile, Samsung is seeking a broader partnership and 'hopes to turn its memory supply relationship with AMD into foundry' chip production orders, the report claims.

"We are going to talk about our broader partnership," said Lisa Su when asked by reporters about what she planned to discuss with Samsung's executives. "We have many partners at Samsung."

Before visiting Samsung headquarters, Lisa Su and Jack Huynh, senior vice president and general manager of AMD's Computing and Graphics Group, attended the AMD Gamer Day event where Su and Huynh answered some questions from South Korean journalists and called local memory makers 'important strategic partners,' something that reflects the significance of data center-grade DDR5 and HBM memory for the company's AI and data center businesses.

"Samsung Electronics and SK hynix are key supply-chain partners for AMD," Su said, Chosun reports. "AI demand is extremely high, so we are planning our long-term supply chain with our partners. […] It is important to plan three to five years ahead with our partners."

The non-binding MOU that AMD and Samsung signed this March covered four areas and remained in effect for a period of three years:

• Supply of next-generation memory products, including HBM4 and advanced DDR5;
• Co-development and optimization of memory solutions for Al and high-performance computing systems;
• Exploration of foundry manufacturing opportunities for the future AMD platforms;
• Co-optimization of advanced packaging and related semiconductor technologies.

While Samsung has become a principal supplier of HBM4 for AMD's Instinct MI400-series accelerators, expansion of collaboration beyond memory supply is considerably more complicated, as it involves considerable efforts to design chips for Samsung Foundry's process technologies as well as risks associated with a product ramp at a new contract chipmaker. Truth to be told, AMD already uses Samsung Foundry and UMC to make its "ICs in the form of programmable logic devices" however, moving production of more advanced products to Samsung is risky. Meanwhile, Samsung badly needs big customers like AMD, and the latter's dependence on HBM supply certainly gives the former leverage.

"If we transition the production of some of our products to new manufacturers, we may experience delayed product introductions, lower yields or poorer performance of our products," AMD wrote in its most recent Annual Report.

AMD has already started shipments of its Instinct MI455 accelerators with 432GB of HBM4 memory onboard as well as rack-scale Helios AI systems to interested parties.

"We have started shipping our next-generation MI455 and Helios systems," Su told journalists, according to Chosun. "These are all systems that use HBM4."

So, it looks like the company is negotiating for more memory supply. The question is, will it take a risk and adopt Samsung Foundry for something more serious than niche programmable chips in a bid to get more high-bandwidth memory and sell more expensive AI accelerators? Only time will tell.

Two former Groq engineers are suing Groq’s former board and former CEO Jonathan Ross, alleging the board handed over employees and company technology to Nvidia in a $20 billion deal. The proposed class action, filed in Delaware’s Court of Chancery by Benjamin Serebrin and Joshua Rubin and unsealed Monday, alleges the deal, with a $17 billion license fee for all backers and a separate $3 billion Nvidia stock pool for engineers who transferred, kept billions from other shareholders. Meanwhile, Groq is planning to deploy its own technology, now Nvidia’s Groq 3 LPX, the Financial Times reports.

Nvidia’s annual report (10-K) books $14.4 billion of the license as goodwill “primarily attributable to the workforce and future development of the licensed technology” plus $2.5 billion for the technology itself. The plaintiffs concede that “no Delaware decision has directly answered the question this case raises,” but the deal is already under a reported Department of Justice (DOJ) inquiry. The lawsuit’s outcome has implications for future license-plus-hire deals. Groq told CNBC the suit is “meritless” and said its licensing agreement with Nvidia “delivered exceptional value for Groq, our investors, and our employees.”

The deal involved both the LPU technology and the people who built it, including Ross, a former Google TPU engineer who founded Groq in 2016. The LP30 has 500MB SRAM per die and 150 TB/s bandwidth, uses Samsung’s 4nm process technology, and is rated by Nvidia at up to 1.23 FP8 PFLOPS. A single LPX rack has 256 LPUs with 128GB SRAM, 40 PB/s, and 315 FP8 PFLOPS in aggregate, as a decode co-processor for Vera Rubin NVL72. The LP30 appears to be the next-gen LPU Groq roadmapped in August 2023 on Samsung’s SF4X process with its first-gen Tensor Streaming architecture.

During Hot Chips in August of this year, Igor Arsovski, Groq’s former chief architect and now Nvidia VP of hardware, called the occasion “a pinch me moment for the Groq team that’s now integrated into the Nvidia group.” The rack was already in production at the time, Arsovski said. This supports the complaint’s factual premise, but does not answer the legal question about whether more is owed.

Nvidia’s 10-K notes indicate that “no customer contracts, existing products, or equity interests were purchased” with “$13.0 billion paid at closing and $4 billion, inclusive of imputed interest, payable within one year.” The goodwill number, as reported above, is about 85% of the $16.9 billion Nvidia booked and around 5.8x the value of the technology asset. Nvidia put significantly more value on the LPU design team and the technology’s future development than on the design itself.

Groq said when the deal was announced that it would continue “to operate as an independent company,” and it joined the Nvidia Cloud Partner program in August. Also in August, “Groq LLC” had a $350 million Series A and a $3.5 billion valuation after raising $650 million in June. Before the deal, in September 2025, the valuation was put at $6.9 billion after a $750 million round. Groq says it now operates 13 data centers and expects to scale from 54 to 200+ MW in 2027. Nvidia was slated to participate in the Series A, which Groq says will support those seeking “clusters of NVIDIA accelerated computing.”

Groq also said in August that it is “among the first adopters of NVIDIA Groq 3 LPX” with Nvidia’s Vera Rubin NVL72, deploying with Dell. Those racks are built on the LPU technology Groq licensed to Nvidia, and Groq claims to be “the only team with hands-on experience operating LPUs in production at scale.” The Financial Times said Groq “pivoted entirely to AI cloud computing, dropping its chip design efforts.”

The suit alleges that the Groq board was conflicted, failing to secure the best terms for every shareholder and denying some of them a vote on the deal. Specifically, it says Ross and other top Groq employees were allowed to “take a discount on those shares and be paid separately for following the technology to Nvidia.” According to the suit, Nvidia hired “nearly all” of Groq’s engineers, as many as 200. However, the final payout is alleged to have ignored potential upside and synergies with Nvidia.

The plaintiffs also say that because Nvidia didn’t buy Groq outright, the $17 billion license payment was taxable as income at Groq, and that the Series A valued the remaining Groq above the price paid to the shareholders who were bought out. They say four “conflicted funds” on Groq’s board, BlackRock, Social Capital, Infinitum, and Disruptive, which are not named as defendants in the case, engineered that gap and profited by staying with Groq after the buyout.

As reported by Axios in December 2025, though, sources close to the deal said that most shareholders would get per-share payouts “tied to the $20 billion valuation.” Around 90% of employees would join Nvidia, with vested shares paid in cash and unvested shares paid in vesting Nvidia stock. Staff who stayed with Groq would be paid for vested shares and get a package including “economic participation in the ongoing company.”

As for the DOJ, the New York Times reported in September that the department sent Nvidia a formal request for information with a fine being possible. Nvidia said at the time that the Groq story was “a prime example of the American system working as designed.” The deal did not go unnoticed by some senators who, in February, put it under the “reverse acqui-hire” deal label. Federal Trade Commission Chair Andrew Ferguson said in January that the agency is “beginning to examine these acqui-hires to make sure they are not an attempt to get around” its merger review process.

The litigation comes not long after Nvidia’s agreement to acquire Hugging Face (HF) a month ago, which included a purchase price and equity for HF employees who join Nvidia, a similar split. The deal is waiting on approval, but unlike the Groq deal, it is an outright purchase of the company. When the Groq deal was announced, Nvidia CEO Jensen Huang told employees in an email, obtained by CNBC, that while Nvidia was adding Groq staff and licensing its IP, “we are not acquiring Groq as a company.”

The legal question on the Groq deal remains open, and more details will come out as the case proceeds and the defendants respond. As for the LPX customers, Nvidia calls Nebius the first AI cloud to adopt LPX and says the racks will be online there later this year. Looking ahead, Nvidia has the LP35, with NVFP4 support, alongside the Rubin Ultra and LP40 for Feynman on its roadmap.

Intel will remain a part of Elon Musk's Terafab project, Lip-Bu Tan, chief executive of Intel, told reporters on Wednesday. Around the same time, Elon Musk, chief executive of SpaceX, Tesla, and xAI, said that Terafab remains committed to building and operating its fab itself, but proposed to lease a part of the fab to TSMC.

Intel will continue its involvement in Terafab, Lip-Bu Tan told Bloomberg prior to the company's event in Japan that commemorates the company's presence in Japan. Back in April, Intel and Terafab, the semiconductor production venture by SpaceX, Tesla, and xAI, announced that the new chipmaker would use Intel's next-generation 14A fabrication process to make chips. Details of the collaboration are still unknown, but there is a general understanding that Intel will license its manufacturing technology to Terafab, though it is unclear whether it will also help ramp up production using the node.

At around the same time, Elon Musk debunked rumors that his companies would invest in Terafab and then partner with TSMC, which will build and operate the fab. Instead, Elon Musk proposes that TSMC sublease a part of Terafab to make chips for its customers.

"No, we will build and run the fab," Elon Musk wrote in an X post. "Let there be ZERO doubt about that. Maybe TSMC subleases part of the Terafab if they want, but nothing more than that."

Offering TSMC, the world's largest foundry that owns and operates dozens of advanced 300-mm fabs around the world, to 'sublease' a part of Terafab is quite an unusual arrangement for many reasons.

First up, TSMC has its own production facilities as well as aggressive plans for about 10 new fab phases in the coming years, and it hardly needs to sublease any capacity or part of the building or site from a third party.

Secondly, semiconductor fabs are not generic facilities: if Terafab is initially equipped and qualified around Intel's 14A process technology, converting part of the facility for TSMC's A14, A13, or A12 processes that the company will use in the back half of the decade would require different process flows, equipment configurations, materials, automation, qualification, and contamination control. Theoretically, TSMC could install a largely independent production line within the same enormous building, but at that point the arrangement would resemble TSMC building and operating its own fab inside a Musk-controlled site rather than simply renting spare manufacturing capacity.

Thirdly, if Intel licenses 14A technology to Terafab, the agreement would almost certainly contain extensive provisions governing access to Intel IP, process information, equipment configurations, and personnel. Putting TSMC engineers and manufacturing operations inside the same facility could create contractual and IP-isolation issues even if TSMC never directly touches the Intel production line. In fact, IP protection would be extraordinary at Terafab, which will complicate its operation.

Fourthly, if indeed two chipmakers end up in the same fab building, or even in the same campus, responsibility for downtime becomes messy. In the case of a Terafab-owned power distribution system, water plant, chemical system, or cooling installation fails and takes someone's production offline, determining operational responsibility and financial liability for potentially hundreds of millions of dollars of affected wafers would be considerably more complicated than at a site controlled by one company.

Finally, if Terafab can equip enough cleanroom space by the end of the decade to satisfy semiconductor requirements of Tesla, SpaceX, and xAI while still leaving substantial capacity available to TSMC, that would raise questions about whether the project had significantly overbuilt capacity in its initial phases.

Since Musk's statements at X are deliberately vague, it is hard to interpret them. In fact, there might be a conceptual problem with Musk's statement. If TSMC installs its own tools, hires its own employees, brings process technology, and production management, while Terafab just provides land, shell, and infrastructure, calling this a 'sublease' undersells what would be a TSMC fab embedded within the Terafab campus. Alternatively, if Terafab provides the tools and infrastructure and TSMC just operates them, that starts to look much closer to precisely the kind of TSMC operational involvement Musk appears to be denying.

Anyhow, while Intel has confirmed its involvement in the project and Musk wants TSMC to be part of it as well, the latest comments raise more questions than they answer.

Qualcomm has reached a deal to license Huawei patents behind the LogicFolding chip-stacking method, Bloomberg reports. The technology, which is used in the Kirin 9050 Pro, splits nearly every block across two bonded dies, and a teardown and die shots show the lower die holds mostly cache and I/O.

Qualcomm’s multiyear, cross-license deal with Huawei has a wide scope, covering 5G devices, AI services, near- and co-packaged optics and networks, a Huawei spokesperson told Bloomberg. Qualcomm also intends to purchase specific Huawei U.S. patents in compute, AI, networking, and other technologies, according to a release. Neither company’s announcement named any patents, LogicFolding, or any chip that uses it.

Bloomberg's report frames the deal as a win for Huawei, validating its chipmaking acumen. The deal remains subject to approval, and Qualcomm will reportedly pay Huawei to license its patents for the first time. According to the report, LogicFolding targets faster data transmission as a workaround for China’s lack of access to EUV lithography machines.

The Kirin 9050 Pro is used in the Huawei Mate XT 2 tri-fold smartphone, launched Sept. 7. Geekerwan, a Chinese tech review channel known for in-depth chip testing, had a lab slice the chip for its teardown. Kurnal, a semiconductor researcher who publishes die-shot analysis, also posted annotated shots of both dies on X. Geekerwan’s cross-section shows the two dies bonded face to face, and both show the execution units on top, with the PLLs also on the lower die.

LogicFolding was first unveiled on May 25 by He Tingbo, president of Huawei’s semiconductor business, at IEEE ISCAS 2026 in Shanghai, under the company’s “Tau Scaling Law,” which uses signal delay rather than transistor size as a measure. Huawei describes both layers as active and working as one. Vertical interconnects work to create shorter signal paths, which can reduce energy consumption. Peking University’s “true 3D” design tool for the technology shows a 30% wire-length cut in its own tests.

Huawei’s papers describe a “Kirin 2026” chip whose figures match the Kirin 9050 Pro’s. In a paper last month, relayed by TrendForce, Huawei said the chip uses a 1.5-micrometer hybrid-bonding pitch with about 50 million interconnects. About 10–15% of those carry signals. Core routing is 20% shorter, with critical paths up to 70% shorter. Power is reduced by as much as 66% for NPU, 58% for GPU, and 41% for a CPU performance core at the same performance level. NPU performance holds 29 TOPS at 63% less frequency and at a lower voltage.

Huawei does not name a process node. On its roadmap is Kirin 2027 at a 1-micrometer pitch and more than 100 million interconnects; for around three years out, a 720-nanometer pitch with over 200 million. It is targeting a 1.4nm-class density by 2031, with LogicFolding in the Ascend 990 AI accelerator around 2030. HiSilicon, Huawei’s chip-design unit, designs the Kirin chips, and SMIC is believed to make them, according to Reuters via TrendForce. It isn’t stated who handles the bonding process.

As for the Kirin 9050 Pro, Geekerwan tested it in a Mate 90 Pro Max phone. Analysis shows that the two dies are bonded with copper-to-copper hybrid bonding, metal layer to metal layer. The bonded circuit layers of both dies sit between two thick layers of silicon rather than directly on the package substrate. For the interconnects, about 80,000 through-silicon vias (TSVs) run through the lower die, taking up, with their keep-out zones, about 8% of the lower die’s usable area, Geekerwan says.

The split spans both dies. In the big CPU core, the execution units are on top, with the L1 and L2 caches directly beneath the load/store units, Geekerwan says. Kurnal's die shots put the GPU and NPU logic over their caches too. The lower die also holds a shared L3, a 12MiB system cache, PLLs, and the LPDDR, PCIe, camera, display, UFS, and USB interfaces, while the top die carries the ISP, modem, and memory controllers. Cache, I/O, and PLLs produce less heat and are less sensitive to the process, so they go below, Geekerwan explains; the denser compute goes on top, on a somewhat more advanced process.

Each die is just over 120 mm², which is smaller than the previous chip’s 140-plus mm². The total silicon area for both is therefore over 240 mm², up 70% overall. Density rose from 155 to 238 MTr/mm² at launch, about 53.5% higher, according to Huawei’s launch numbers. Other notable changes include the NPU’s area, up 150% across both dies, with Geekerwan measuring 68 TOPS INT8. The configuration makes sense and the rationale follows the layout, but an independent die analysis is needed for full understanding.

Huawei’s stacking approach has its competitors. TSMC’s SoIC roadmap set a 6-micrometer bond pitch for 2025 and 4.5 micrometers by 2029, with 3nm chip stacking in volume production last year. Intel’s Foveros Direct is said to have “copper bonding at a pitch of 9µm,” which reached high volume with the Clearwater Forest Xeon, and a second generation targets 3 micrometers. AMD’s first-generation 3D V-Cache stacks a 64MB L3 SRAM die on a complete CPU die, using direct copper bonding at a 9-micrometer pitch. Huawei’s 1.5-micrometer claim comes from its own paper and any comparison has to be taken with a grain of salt.

As to why Qualcomm might be interested, John Han, executive vice president and general manager of Qualcomm Technology Licensing, said the agreement reflects Qualcomm’s “recognition of Huawei’s continued innovation and intellectual property in 5G and other technology fields.” Bloomberg’s report says that at least some of the patents underpin LogicFolding, but no source names the patents. Dr. Ian Cutress, chief analyst at More Than Moore, questioned how new Huawei’s Tau Scaling is, writing on X that it is “a repackaging of what the industry has always done.”

Upon “receipt of the necessary regulatory approvals,” the cross-license and patent purchase deal should proceed. The deal is also subject to Federal Trade Commission review under the Hart-Scott-Rodino Act, Bloomberg reported. That U.S. premerger law sets a minimum deal size, $133.9 million this year, among other tests, and the deal’s value wasn’t disclosed.

Nikkei Asia reported that Qualcomm will be the net payer under the deal. However Qualcomm said on October 6 that reports characterizing it as a net payor on the license agreement are incorrect and that assertions linking the agreement to LogicFold are not accurate. Qualcomm’s licensing revenue stopped including Huawei royalties in fiscal Q2 2025, after the license expired. This follows a long history of Huawei paying for Qualcomm licenses, an agreement first inked in 2001. Huawei says it has brought in more license-related income than it’s spent since 2021. Patents behind its chip-stacking method reportedly join that business under the deal.

The industry now waits to see what comes of the FTC review. Qualcomm’s fiscal Q4 results should come early next month, as last year’s did, but its fiscal year ended Sept. 27, before the deal was announced. Additional independent analysis of the 9050 Pro’s die may come from TechInsights or SemiAnalysis. Also of interest is the next iteration in Huawei’s Kirin 2027, to see if its claims are met. The deal between the two companies currently lacks details on the extent of patent coverage, but the silicon on record can help reveal the nature of Qualcomm’s interest.

Update: 10/12/2026, 02:50 PT: Added passage reflecting Qualcomm's October 6 statement.

Qualcomm will pay Huawei for patent rights under a multi-year cross-licensing agreement that highlights both 5G and AI technologies, and will buy some of Huawei’s U.S. patents outright, the firm announced. The joint announcement comes 25 years after Huawei began to pay Qualcomm for patents, a reversal that reportedly has Qualcomm paying for the first time. The agreement also covers compute and networking patents, and the patent purchase will close once it receives regulatory approval, the South China Morning Post reported. Qualcomm said on October 6 that reports characterizing it as a net payor on the license agreement are incorrect and that assertions linking the agreement to LogicFold are not accurate.

The two companies’ licensing ties date back to 2001, when Huawei, then a Chinese telecom-infrastructure supplier, took a royalty-bearing license to build CDMA network equipment. Qualcomm, which once supplied chips for some Huawei phones, stopped counting royalties from Huawei in its revenue in early 2025.

The “broad patent license agreement” allows “cross licenses” and reflects both companies’ commitment to intellectual property rights and to licensing consistent with “fair, reasonable and non-discriminatory (FRAND) principles.” The deal involves no other business cooperation, Huawei said, according to SCMP; this implies no chip sales are involved. The deal follows a settled back royalty dispute in 2020, the U.S. revoking Qualcomm’s license to sell some hardware to Huawei in 2024, and the expiration of Huawei’s license by early 2025.

Qualcomm’s patent purchase covers compute, AI, networking, and “other technologies,” according to the announcement, but the number of patents was not disclosed, nor was any value figure. Each company credits the other’s portfolio. This suggests that the two are trading official recognition of each other’s patents.

Huawei says that, with the Qualcomm deal, the total value of its patent-licensing contracts will top $6.9 billion, counting from its first licensing income from Motorola in 2011. Since 2021, it says, its licensing business has brought in more than the company pays for other firms’ patents. In August, the company signed a multi-year Wi-Fi patent cross-license with HP and, as of 2025, the company held 165,000 active granted patents worldwide.

Huawei has also gone to court to enforce its patents, as in a 2024 lawsuit against MediaTek. It halted royalty payments to Qualcomm in 2018, and its general counsel testified for the FTC about Qualcomm’s licensing terms in the agency’s 2019 antitrust trial against the chipmaker. Huawei can now take some satisfaction in leveling the playing field with Qualcomm.

No timetable has been given for closing the patent purchase. Qualcomm’s Q4 report is expected next month, but its fiscal year ended before the announcement, so the deal will not make it into those numbers. The company also renewed its Apple license last month, effective April 1, 2027, after the current extension ends. Qualcomm’s relationship with Huawei is now on the other side, as Qualcomm reportedly becomes the one that pays.

Update: 10/12/2026, 02:50 PT: Added passages to the article to reflect Qualcomm's October 6 statement.

Chinese chipmakers have accumulated an estimated 343 immersion DUV lithography chipmaking tools from 2012 to early 2026, many of which can be used to make chips using 7nm-class process technologies, according to a report from the Centre for Technology & Statecraft (CTS). The Washington-based group asserts that this equipment gives Chinese fabs considerable potential to produce sophisticated processors despite their inability to procure ASML's more advanced EUV systems. While the total number of ArFi tools owned by Chinese chipmakers seems plausible, some other estimates look questionable.

China has been particularly aggressive in procuring wafer fabrication equipment in recent years as the U.S. government has been busy imposing various curbs on its semiconductor industry. Since 2012, Chinese chipmakers, including logic and memory makers, have imported 343 immersion DUV lithography scanners from ASML, excluding imports to multinational fabs located within China.

The authors of the report claim that the existing export controls leave an important gap because lithography equipment originally acquired for less advanced process technologies can potentially be reassigned for more sophisticated process technologies, such as 7nm-class nodes (which the industry adopted in 2018 – 2019). This happens at a cost, but if no other options are available, Chinese chipmakers have no choice. They propose to prohibit exports of all immersion DUV systems to China and restrict replacement components and maintenance services for machines installed at advanced fabs, a proposal consistent with the bipartisan MATCH Act introduced in April.

CTS claims that 270 of these immersion DUV tools are ASML's Twinscan NXT:1980i scanners featuring a 38nm resolution and a 2.5nm matched-machine overlay capability crucial for multipatterning for 7nm-class nodes, which can be used to make chips using 7nm-class fabrication technologies. In addition, CTS claims that Chinese fabs own 22 NXT:2050i and six NXT:2000i systems. It is unclear how many of the 296 advanced immersion DUV scanners shipped to China are currently operational.

Dutch authorities introduced licensing requirements for exports of ASML's NXT:2000i and more capable immersion DUV scanners in September 2023, which effectively prevents their shipment to China. As a result, Chinese chipmakers had to opt for the least capable NXT:1980i. CTS now estimates that Chinese fabs purchased approximately 90 NXT:1980i scanners in 2024 and another 89 units in 2025, spending more than $13 billion during the two-year period. While the Netherlands expanded export controls to the NXT:1980i in September 2024, individual exports of this model can still receive approval. Furthermore, ASML can also potentially sell its NXT:1965Ci systems to clients in China, though we are not sure it has all the components needed for these outdated scanners.

ASML's own results reflect unusually high demand from China: the country represented 41% of its net system sales by shipment destination in 2024 and 33% in 2025. That share subsequently declined to 19% in Q1 2026 and 14% in Q2, which is something that ASML had warned about before.

One should keep in mind that the CTS numbers — ~90 NXT:1980i systems in 2024 and 89 in 2025 — cannot be independently reconstructed from ASML's published financial data. At most, ASML's disclosures provide a useful sanity check: China was indeed an exceptionally large destination during precisely those years, while ASML sold 129 and 131 ArFi systems globally in 2024 and 2025, respectively. If CTS' numbers are correct, then Chinese chipmakers bought the lion's share, 70% and 68%, of ASML's immersion DUV tools output in 2024 and 2025 despite export controls introduced in 2024. Meanwhile, the NXT:1980Di systems are readily available on the secondhand market.

*The source mentions the NXT:1980i machines, which probably include the original 1980Di and newer 1980Fi featuring higher productivity. We will use the 'NXT:1980i' name in this story for consistency, even though ASML has never produced a scanner named NXT:1980i.

Russia-based Zelenograd Nanotechnology Center (ZNTC) has completed the third R&D stage of the company's first lithography tool capable of processing 200-mm wafers using a 130nm process technology, reports CNews. The tool is currently being tested internally and is years away from being used at a real fab to produce chips in mass quantities. Blogger Dmitrii Kuznetsov suggests that the device is the "first Russian 130nm-capable lithograph" that consists of components made in Russia. This may not be the case, though.

"The creation of a prototype of a domestically developed photolithography system designed for a 130nm process is an important milestone for Russia's microelectronics industry," Alexander Mikhailov, an analyst with Strategy Partners, told CNews. "It demonstrates that Russia has its own engineering expertise required to develop such equipment and paves the way for developing a range of systems targeting smaller process nodes (90nm and 65nm)."

Truth be told, while the Zelenograd-based ZNTC is responsible for the project, Belarus-based Planar was responsible for developing the lithography system, according to documents seen by CNews (which corroborates earlier reports). In addition to the system itself, Planar was responsible for manufacturing mechanical assemblies and components, as well as commissioning the prototype. Lasers for the unit were developed by Lassard. Meanwhile, ZNTC is responsible for development of the overall system, design of the test and process equipment, projection-lens calculations, as well as process modeling and development, the report claims. Russia's Ministry of Industry and Trade allocated approximately $70 million for the entire development program.

It is estimated that one 130nm-capable ZNTC stepper costs $6.7 million, while its laser light source costs around $600,000, bringing the cost of a single tool to around $7.3 million. To put the number into context, ASML's PAS 5500/150 stepper had a list price of $3.1 million when it was launched in Q1 2001. Implying a cumulative inflation of about 88%, this translates to around $5.8 million in 2026 dollars. Meanwhile, the Russian stepper is a 200-mm machine capable of 130nm fabrication technologies.

Speaking of 130nm manufacturing processes — which Intel and AMD adopted in 2001 and 2002, respectively — Russian chipmakers have historically developed two 130nm-class nodes, but those technologies rely on lithography equipment from ASML. Whether or not ZNTC's stepper could be integrated into existing nodes remains unclear, but ZNTC claims that it is also responsible for process technology 'modeling and developing.' This likely refers to developing/qualifying the lithographic process around this particular machine —resist, exposure dose, focus/process window, masks, alignment/overlay, develop conditions, temperatures, etc. —rather than inventing an entire 130nm technology from scratch.

Given a typical lithography tool development cycle, ZNTC's 130nm stepper is still likely years away from being used for actual chip production. For now, ZNTC's 130 nm step-and-repeat system is still an engineering prototype, which was delivered five months later than expected. The first prototype is currently undergoing internal engineering and acceptance testing, after which ZNTC will have to finalize the design and validate everything from imaging and overlay to reliability and throughput, which will take well over a year. Only after that, it can build prototype machines for actual chipmakers that will have to characterize them and then qualify them for their production flows, which will take months, if not years.

Even established lithography suppliers typically require several years to move from the first integrated engineering system to production deployment, so a realistic timeframe for the Russian machine to begin processing commercial wafers would probably be around 2029 at the earliest. Limited production of the steppers themselves could potentially begin earlier as long as ZNTC has all the required parts, but that should not be confused with their qualification for volume semiconductor manufacturing.

TSMC and Elon Musk's Terafab semiconductor production initiative are discussing a potential collaboration under which TSMC would build and operate a facility that will exclusively serve Elon Musk's Tesla, SpaceX, and xAI companies, according to Tim Culpan’s Culpium newsletter on Friday. Elon Musk confirmed the discussions early on Saturday, but did not elaborate.

"Just discussions, but something may come of it," Musk wrote in an X post, while TSMC has so far remained tight-lipped.

Under the arrangement Culpan considers most probable, TSMC would own and operate the new semiconductor production facility, while SpaceX/Terafab could invest in the venture, commit to buying a guaranteed volume of chips, or combine both approaches. However, the exact ownership structure remains under discussion. Another option would put SpaceX in control of the venture with the majority ownership; TSMC would invest less, but would still provide 'operational expertise' and process technologies. Perhaps, an interesting background detail from Culpium is that TSMC's rumored intentions to build a fab complex in Texas are tied to the foundry's effort to support Terafab.

The proposed 'Plan A' arrangement could resemble TSMC's JASM and ESMC joint ventures in Japan and Germany, where local partners provide capital and demand while TSMC contributes process technology and operates the fabs. The proposed 'Plan B' structure — under which SpaceX will hold the majority ownership of Terafab while TSMC would operate the facility and bring its own process technology — would be completely new for the world's No.1 contract chipmaker, though.

The development certainly raises questions about Intel's role in Terafab. For now, Intel is to supply its 1.4nm-class 14A process technology to Terafab, which would produce chips for Elon Musk's SpaceX, Tesla, and xAI. If TSMC becomes involved, then Intel's 14A could drop out of the game because TSMC will bring its own node.

Since nothing is official at this point, both 'Plan A' and 'Plan B' should be considered as speculations rather than the two options currently on the table, as there might be 'Plan C,' 'Plan D,' and even 'Plan E.'

TSMC is a leading advanced packaging supplier, so Musk's Terafab might be interested in making chips in Texas (presumably using Intel's 14A process technology) and then package them in Texas, which is where TSMC might come into play. Another thing to consider is that while Intel has a broad cross-patent license agreement with TSMC, Terafab does not, so producing chips using an Intel-developed node might infringe one of TSMC's patents, which might become a problem. To that end, Musk needs to keep TSMC close, perhaps to the point of buying into Terafab.

One thing to certainly keep in mind is that Elon Musk barely wants Terafab to become a foundry that competes against Intel Foundry, Samsung Foundry, or TSMC. What he needs is an uninterrupted and surplus supply of custom silicon to SpaceX, Tesla, and xAI to support their AI, automotive, and space vehicles. Given the rather broad strategic goal, Musk is probably very flexible when it comes to both tactics and strategy.

Three companies, Cadence, Synopsys, and Siemens EDA, dominate chip design software. Their software takes you from chip specification to a manufacturable layout. As AI has rapidly advanced, so have their Electronic Design Automation (EDA) agents, all sporting notable improvements in 2026. The addition of a reasoning model helps drive that flow for Cadence’s ChipStack super agent, Synopsys’ AgentEngineer, and Siemens’ Fuse EDA AI agent, each with its own claims to fame. Cadence at Computex on June 1 said its agent reached what it calls Level 5 autonomy. Rob Knoth, Senior Group Director of Strategy and New Ventures at Cadence, told Tom’s Hardware Premium that the demo was “what we call bounded Level 5 in one domain,” with the bulk of super-agent tech at “I’d say advanced Level 4.”

Synopsys said its spec-to-RTL (Register Transfer Level) workflow shown on March 11 reached “L4,” and the company told Tom’s Hardware Premium it now claims L5 capabilities for its long-horizon agents. Siemens’ agent launched March 16 with “self-verifying” loops announced on July 26. Meanwhile, outside these big three, Empyrean’s chairman, Liu Weiping, stated on Sept. 9 that its agent cut a layout task from four weeks to one, according to the South China Morning Post.

While the claims about what these agents do are specific and now known, what they have measured is not. All of the claimed improvements to speed are the vendors’ or their customers’ own figures, with many “up to” or “early evaluation” caveats. These figures often measure different things against different baselines, and the only evaluator Synopsys named in July, AMD, has not provided analysis beyond an endorsement.

From copilot to closure

In an evolving field, it can be difficult to hit a moving target, especially when the reported numbers measure different things. Some clarity is possible by following the distinct stages from human-only to human-reviewed agent autonomy. The agents fundamentally rely on existing technologies with known desired outputs for accurate evaluation.

Progress has so far followed three distinct generations. At Synopsys, by DSO.ai and reinforcement learning in 2020, generative AI capabilities with Synopsys.ai in 2023, and finally an open agentic AI stack from 2025–2026. All decisions must be validated by proven EDA engines, with the agent focused on evaluating intermediate results and determining subsequent actions. A model’s proposal is examined by an existing deterministic engine such as Xcelium, Jasper, Questa, Calibre, or Fusion Compiler within an iteration loop until final verification.

Measuring progress here does not follow a standard, but there are autonomy ladders with a general rating from Level 1 or L1 to Level 5 or L5 or, in Siemens’ case, no numbered level. Cadence, which uses levels, moves from optimization AI to conversational LLM, complex reasoning, agentic workflows, and then finally full autonomy, defined as taking a design from spec to verification “with minimal human intervention.”

Synopsys’ L framework goes from actions of single agents on a single design step to more complex ones with multiple agents, with further development focusing on adaptive learning and, ultimately, the agent’s ability to make decisions autonomously. The critical part for Synopsys is that “human engineers will and must always be in the loop.” Given the claims of progress, it’s clear that ladders, where they exist, are a form of marketing scaffolding that describes the same underlying architecture or loop.

Specification to verified RTL

The greatest claimed gains thus far are in the front-end design and verification stages, taking a specification from RTL to a verified design. This part of the process is a natural fit for LLMs, as the RTL, testbenches, and assertions are code. Where the loop used to wait on human analysis and input, the agents can run simulations in parallel and make decisions with fast, concrete pass-or-fail answers. These loops already existed and are prime real estate for agents to speed things up, with claimed orders-of-magnitude improvements by moving from human to agent on what is often the slowest part of the process, triage.

Getting from the chip specification to verified RTL code involves generating the code from natural language and formal specification, according to Synopsys’ March release. From there, the agents generate unit-level testbenches and engage in a verification loop. In July, Synopsys claimed RTL validation could be up to 50x faster with a 20% improvement in coverage, compared with its own non-agentic flow.

For Cadence’s ChipStack from February, the scope includes “autonomous RTL design, verification, and debug.” Named early users include Altera, Nvidia, and Qualcomm. ChipStack started as a Seattle startup that was acquired in November of last year after a multi-year integration with Xcelium and Jasper. In June, Cadence said RTL validation could happen over 40x faster, with each engineer using ChipStack agents “to run hundreds of dynamic simulations with Cadence Xcelium ... reducing a typical five-week verification loop to less than a day.”

Siemens’ Questa One Agentic Toolkit, detailed in February, has five separate agents: RTL Code Agent, Lint Agent, CDC Agent, Verification Planning Agent, and Debug Agent. These work with mainstream AI coding applications including Claude Code, Cursor, and Siemens’ own Fuse. Akshay Aggarwal, senior director of engineering for MediaTek, noted “immediate and significant” gains. The numbers from Synopsys and Cadence should be read as the vendor’s own ratio comparison to the old loop, as regression loops are already automated. All three companies are now focusing on the decision-making process. For details on specific claims, refer to the table below.

The back end

Things are tougher when you move from RTL verification to implementation. Outside of specific tasks that look like front-end loops, claimed gains are harder to come by. This phase deals with geometry and physics, not code, and the pace is limited by compute. Some tool runtimes are “days to weeks … just running the tool itself,” and a tool call that takes “hours to days” to return a value “really gives the AI industry a much different problem to solve,” Knoth said. Complex trade-offs remove singular pass-or-fail judgments, and mistakes later in the process become much more expensive. Earlier AI integration also already exists for this flow, so the agentic touch is more on experiment-running. This makes things cloudier.

Cadence’s InnoStack runs parallel experiments from synthesis to ECO execution. ViraStack, which is for custom and analog solutions, handles the design flow from drawing to simulation, optimization, and layout porting, with some customers “reporting 3–10x productivity improvements,” according to a report from Futurum in April.

Synopsys’ looping implementation agents, driving Fusion Compiler directly or through other platforms, help “reduce manual engineering effort,” according to AheadComputing, and Synopsys said they improve quality of results, including timing, power, and area.

Siemens Fuse, meanwhile, coordinates at least nine named tools, including Solido for custom IC design and verification, Aprisa for physical implementation, Calibre for signoff verification, and design-for-test with Tessent. Improvements vary, with Solido mentioned as improving characterization turnaround times by more than 10x and token costs by 5x to 10x, according to Siemens. One third party, STMicroelectronics, mentions that the Solido Layout Analyzer is helping “cut down the time we spend debugging complex design blocks by weeks,” according to Non-Volatile Memory Design manager Gianbattista Lo Giudice.

Empyrean, according to the SCMP’s September reporting, is shifting from “humans operating tools” to “humans commanding agents” with its agentic EDA platform. This platform would work with its partners’ agents. One claim is that 3D verification went “from two to three months to less than a month,” according to TrendForce reporting. Empyrean is the largest domestic EDA vendor in China and is state-controlled as of December 2024.

Self-checking agents

What we inevitably keep coming back to with agentic EDA is one simple term: trust. The agents must be trusted to varying degrees to check their own work. Important checkpoints are still verified by a human: “The crucial approval checkpoints are still going to be human-driven,” Anand Thiruvengadam, executive director of product management at Synopsys, told Tom’s Hardware Premium. Inside the loop, the use of reliable tools such as deterministic engines allows for results that can largely be trusted. Outside of this, trust is based on evaluation, and internal verification is only as good as the tests. There remains reliance on what the vendors claim, and that depends on exactly how each defines the self-checking loop and goals.

The Siemens Agent loop, put simply, is: Plan, Act, Reflect, Iterate, over “Develop, Publish, Execute, Refine.” “Self-verifying” in Siemens’ case means that agents “continuously validate decisions against deterministic, physics-based EDA engines.” According to SemiWiki’s Bernard Murphy, describing the Fuse launch, “the orchestrator can trigger repair agents, then re-run validation. This may resolve most errors,” although we were unable to get any comment on specific triggers.

Cadence’s description is that “every action the super agent takes is anchored” in its own proven design and verification engines, to ensure accurate results. These, like Siemens’ solution, can run “within a secure Nvidia OpenShell sandbox” to enforce guardrails and ensure predictability. This allows engineers to “inspect, guide and collaborate as needed” even at Level 5. The human engineer works from their own runtime environment, then “once the super agent finishes that loop … the auto-run environment can interpret, understand, and then fire off that next message, right, that next iteration,” Knoth said.

Synopsys also retains the human element, with the debug workflow’s output as root-cause analysis and resolution through engineers. The flow iteratively runs checks against generated, unit-level testbenches, with the agent handling design and the tests themselves. When a check fails in Synopsys’ Verification AgentEngineer, the logs are consulted, and errors are aggregated to paint a picture of the most likely cause, checked against simulation waveforms. When applying the fix, the agent must prove that the bug has actually been fixed and should be able to produce a bug-fix manifest. Beyond this, the quantity of checkpoints is determined by customers’ trust and desired flexibility, and over time, “they might relax and take away those checkpoints,” Thiruvengadam said. The internal process, such as the specifics on retry limits, the definition of unfixable, and states requiring escalation, remains murky.

Early access everywhere

All of the numbers and roadmaps in the world don’t replace actual value to the customer, or actual customers with a released product. Thus far, the agentic platforms have been in early access and evaluation. Engagements have been listed, and major customers exist, but none are confirmed with a generally available product. General availability hasn't arrived yet, but it has been promised by the end of 2026 by Synopsys, with Cadence’s AuraStack, its PCB and advanced-packaging agent, also due this year. Usable products and workflows exist, but the efforts remain nascent, despite relatively rapid claimed gains over the last year or so.

Cadence ChipStack has been in early access since February. In June, this extended to the promise of Level 5 capabilities with early access for customers in the second half of 2026. Synopsys has debug and implementation workflows, announced in July, available for evaluation on Microsoft Discovery, if requested. Microsoft’s platform is designed to assist in the construction and management of agentic AI workflows related to scientific and engineering fields. Siemens has the Questa One Agentic Toolkit, announced in February, and the Fuse Agent as of March, with promises made in July surrounding self-verifying capabilities in forthcoming releases. Empyrean is also developing its own platform as of the time of writing.

The current stacks largely run on Nvidia’s Nemotron and its OpenShell sandbox. Nemotron is a reasoning model family. OpenShell is an open-source runtime that keeps the agent contained with kernel-level isolation, protecting customer IP and guarding against rogue actions. Nemotron and OpenShell are open, so nothing on record prevents Empyrean from using them, but without announcements, it appears to be the outside case. What each EDA vendor does with this technology and the flexibility it offers its customers are the defining differences.

Earlier this week, Nvidia announced its Open Agent Safety Platform, a combination of OpenShell and the Sentry reference design, an “out-of-band watchdog” that runs on BlueField-4 DPUs to “continuously monitor agent behavior” and can quarantine an agent in milliseconds. Cadence, Synopsys, and Siemens are named among the more than 100 organizations working with Nvidia on the platform. Cadence’s Knoth told Tom’s Hardware Premium that OpenShell “helps ensure the agents are well behaved ... don’t go rogue and start accessing data they’re not supposed to,” as agents need to become productive and trusted. Thiruvengadam from Synopsys echoed these sentiments, with both companies aware of the dangers of rogue agent actions.

Cadence and Synopsys, at least, needed licenses as of May 2025 for EDA sales to China, but the requirement was rescinded as of July of that year. EDA is expected to be critical for the industrial software space “toward the high end of the global value chain” by 2030, according to ChinaTechNews. According to Liu, as reported by the SCMP, Empyrean is trending away from traditional software licenses to a token-consumption pricing model with agentic EDA.

Startups in this space include ChipAgents, Cognichip, Agentrys, Silimate, and Ricursive Intelligence, most funded since December 2025. The big three buy other companies, from startups such as ChipStack to simulation software maker Ansys, as advances put EDA in the spotlight toward the end of 2026. Even with platform-specific flexibility, Nvidia remains the common ground, with its open model family and sandbox being the standard across the big three.

As it stands in 2026, the agents exist, and there are real roadmaps and customer evaluations. The framework hinges on existing technology already worthy of trust. The overall trend is toward harness engineering and, as Knoth told us, the implementation of “an array of specialized engines” to fuel the workflow end to end. Improvements, although currently lacking the independent measurement and precision we would like to see, are real and accelerating, according to vendors and their customers. It will become increasingly important to have proper evaluation of the different agents as they approach Level 5, “L5,” or some equivalent marker that denotes autonomous action.

What we would like to see by the end of the year is some customers named to actually be using the highest level of agent. Specifically, these agents must live outside of a trial or early access mode. This enables oversight and comparison in what will become an incredibly important field. We also anticipate Siemens’ forthcoming releases, which may demonstrate the self-verifying loop. Cadence is worth a close watch to see whether a Level 5 early-access customer is named before the end of the year. The baseline, though, is at production: real customers, real workflows, real products, and a measured improvement.

OpenAI’s Jalapeño ASIC is a seismic shift for the industry, not because of its efficiency or performance, but because of how it was designed. The company was clear from the jump that AI played a big role in the design process of Jalapeño, not only for the hardware itself, but also in the co-design with OpenAI’s software stack, allowing the ASIC to go from initial register-transfer level (RTL) to tapeout in a matter of just nine months. From concept to reveal, the timeline was less than two years. Richard Ho, head of hardware at OpenAI, says the timeline “established a new baseline,” and that the industry is already knocking on OpenAI’s door to learn how the company pulled it off.

“The way I like to think about it is, we’ve established a new baseline. In the old baseline, you’re talking 18 months to two years, roughly. Often that’s even with some existing IP or some more legacy architecture design,” Ho told Tom’s Hardware Premium in an interview. “We’re starting from scratch here. We had nothing. There’s not a line of code here to refer to. What we’ve established is that there’s a new baseline that you can do with a very talented team with the help of AI. Now, does it get shorter? It depends on what you’re trying to do.”

AI usage in chip design is nothing new, predating the era of LLMs entirely. The largest Electronic Design Automation (EDA) companies, Cadence and Synopsys, have a portfolio of AI-assisted chip design tools that have been around for several years. The models OpenAI used were its own internal models, however, and it leveraged both existing EDA tools and its new AI-assisted engineering workflow.

The engineering team used OpenAI’s agentic coding platform, Codex, for the Jalapeño design. “But we think that every engineering team in chip design should be able to use this as a new baseline, because it’s a proof point that the models that are in use — the AI models for us is mostly Codex, Sol, the one before Sol, and now we’re moving on to Astra. These are super capable. Even from when we started that work, back in November 2025, to when we taped out, the models improved enormously. Even from that moment to when we started doing the kernel optimization in May, when the chips were first coming online, we ourselves were shocked at how much better Codex was and what it could do,” Ho said.

Although AI was used during the entire development process, not only for design itself but also in writing and optimizing kernels, Ho continually reiterated the importance of talented engineers guiding those systems. The development story of Jalapeño is one of the few clear examples of AI bolstering a team of human workers, not displacing them.

Ho described the development cycle as a “good model” of how engineering teams should operate in the AI era. “This is how AI should be used. We didn’t replace our engineers; they just became super productive. With a smaller team of really good engineers with a lot of this AI stuff, you could do things faster and better than you could otherwise. I think that’s a good model of how engineering should be approached in the AI age.”

Although OpenAI managed to get working silicon much faster than a traditional development cycle, it wasn’t free of issues. For starters, OpenAI’s B0 stepping of Jalapeño reportedly delivers up to a 25% improvement in performance per watt over the original A0 stepping. That’s closer to a generational improvement than stepping optimization, suggesting that, at least for a brand new hardware team, there may have been design oversights with the original stepping. Attributing that to AI or humans is anyone’s guess.

Other frontier labs are circling for a slice of the pie, as well. Clive Chan, a key engineer on Jalapeño and the second-ever hardware hire at OpenAI, left the company in June to join the hardware team at Anthropic. Ho says there’s already been “a lot of interest in the industry” for OpenAI’s AI-assisted chip design process, and says that “we’ll see more about that quite shortly.”

“I’m not going to preempt anything here. I can tell you that there’s a lot of interest in the industry, and I would also tell you that we feel that there is a lot of benefit in industry generally that we want to enable,” Ho said. “I think that’s something that we’ll see more about quite shortly, to be honest.”

Ho referenced the dozens of AI-first chip design startups in Silicon Valley, suggesting OpenAI may eventually introduce tools of its own to aid other firms with AI chip development. “We have our take on that, and I think at some point we want to tell the world, “Here’s our take on it.” Fundamental to that is Codex and GPT-6 Astra coming out. Those are fundamental, and we can basically point to it; it’s not going to be slideware or vaporware. We can point to it and say, “Here’s what we did, here’s how we did it, and here’s what we got.” It’s going to be very concrete.”

What exactly the “it” Ho is referring to here remains a mystery, though given the context, it sounds like OpenAI may explore some way to productize its AI chip design workflow. Ho says Astra is a big step toward that, and we’ve already seen the model in action performing impressive feats, such as completing Portal autonomously.

Although OpenAI leveraged its own models heavily for Jalapeño's design and validation, it didn’t completely break the mold of traditional EDA workflows, particularly at the end of the design process. Before tapeout, tools from companies like Synopsys and Cadence perform a series of tests for signoff, including static timing analysis and signal integrity analysis. Ho says that OpenAI used this typical EDA flow for Jalapeño.

“But for sign-off, you need to use the standard EDA flows, and we did, because you want to make sure those results are good and correct. There’s no real alternative today. Part of it is this combination of standard flows optimized with AI, optimized by really good engineers,” Ho said.

OpenAI shared a multi-generational roadmap for accelerators. It says its second-gen ASIC is approaching tape-out, and its third generation is already in development. Although Ho said that the Jalapeño development cycle establishes a new baseline for chip design timelines, he was cautious about calling that cycle and cadence.

“Our projects and tape-outs will be dependent on the maturity level of the technologies. We can do very fast execution. Will we do those types of executions back-to-back? I doubt it, because the technology will not be ready for that, and I don’t want to tape out something that is 2% better than what I taped out before, because it’s not worth it to change a fleet,” Ho told us.

The executive was also clear that the Jalapeño timeline isn’t necessarily the same timeline all chips will follow. There were some “pragmatic trade-offs” in the early architecture design, with the team avoiding emerging, complex design points like 3D stacking and co-packaged optics. “Will it take longer? Will it take nine months? I won't say it will take nine months… but I think it will go faster than if you didn't have AI models.”

You can read the full transcript of the interview, which covers a wide range of topics, at Tom's Hardware Premium.

In late August, Architect Labs claimed it had designed a chip that was almost entirely developed by AI, an industry-first achievement. AI is already used to optimize floorplans, placement and routing, verification, and other stages of semiconductor development. Generative AI can assist engineers with RTL code, whereas emerging agentic systems can operate electronic design automation (EDA) tools, analyze results, identify problems, modify designs, and repeat the process with increasingly less human intervention. Meanwhile, human engineers still define and develop architectures and make fundamental design decisions that determine what a chip does and how it works.

This creates a curious feedback loop. Today's AI models run on processors designed by human engineers with growing assistance from AI; those models can then help design more capable processors for the next generation of AI systems. As EDA vendors and semiconductor companies give AI control over progressively larger portions of the design process, the industry is gradually moving from humans using AI tools to design chips toward AI systems participating in the design of the hardware on which their successors will run.

Can machines indeed design machines today? Probably not. But will they be able to do so in the future? That's a big question with important ramifications — and engineers have been pondering it for longer than you might think.

A brief history of AI in chip development

Cadence, Synopsys, and Siemens EDA, all leading developers of EDA software, alongside Ansys — a leading designer of simulation software — rolled out AI-enhanced versions of their tools in the early 2020s, before the generative AI boom took the world by storm.

The first generation of AI-enhanced EDA software primarily used machine learning (ML) and reinforcement learning (RL) to tackle well-defined optimization problems. Given an existing design, a set of constraints, and particular targets, these tools could explore numerous implementation options to optimize placement and routing, and therefore power, performance, and area (PPA), while shrinking development time. Essentially, AI could find a better way to implement a design, but the design itself and its goals were still defined by engineers.

One of the key advantages of these tools was their ability to learn from previous runs and use accumulated data to guide subsequent design-space exploration, something which could reduce the number of iterations needed to meet PPA targets and, in some cases, produce results that would have required considerably more engineering time using conventional methods. Yet the autonomy of these tools is limited, as engineers define constraints, configure flows, run individual tools, analyze their output, and decide what to try next. AI accelerates or optimizes particular stages of chip development, but humans still control the overall design flow. And that's changing with newer generations.

The latest AI-enhanced EDA tools are considerably more ambitious. Generative AI can write or modify RTL and verification code, analyze reports, identify potential points of failure, and even suggest fixes. Meanwhile, emerging agentic systems can operate multiple EDA tools and execute sequences of engineering tasks with very limited human intervention. Such an agent can analyze results, modify a design or its parameters, launch another simulation or implementation run, evaluate the outcome, and repeat the process until it reaches specified targets. As a result, AI is gradually moving from optimizing individual steps inside EDA tools to automating parts of the chip development workflow itself.

From big bang to architectures

In 2023 – 2024, both Cadence and Synopsys announced that hundreds of chip designs have been completed using their AI-enhanced Cadence.ai DSO.ai/VSO.ai/TSO.ai tools. Moreover, leading high-tech companies revealed details about how they used AI to complete their projects. Yet putting Google, Nvidia, OpenAI, and Architect Labs into the same bucket is not right, as they represent different degrees of AI involvement in chip development.

Google, which was among the first high-tech giants to announce the use of AI to develop its AI accelerators, seems to be the least radical. Google's AlphaChip uses reinforcement learning mostly for physical floorplanning: it places circuit blocks and optimizes layouts, but it does not invent the entire design or the architecture itself. Google DeepMind said in 2024 that AlphaChip had been used for the previous three generations of TPUs, meaning Google was well ahead of the general EDA industry with its tools. (The company has not shared AlphaChip's progress in detail since then.)

Nvidia is more interesting because its internal AI systems tend to automate work traditionally performed by hardware engineers. The important distinction is that Nvidia trains specialized models on its own RTL, documentation, and unique accumulated engineering knowledge, something a merchant EDA vendor cannot access. This makes Nvidia an example of a chip designer that turns the engineering data behind its proprietary GPU and, more recently, AI accelerator, CPU, DPU, and network cards into training data for AI. Nonetheless, Nvidia itself draws a clear line between its automation and autonomous chip design.

OpenAI's Jalapeño is probably the strongest real-silicon example we currently have. OpenAI says AI was directly involved in implementation, design-space exploration, verification loops, and arithmetic-circuit optimization, which enabled the company to go from initial design to tapeout in nine months. At Hot Chips, OpenAI disclosed some concrete PPA advantages: Compared with human baselines, AI-assisted designs improved a BF16 multiplier by 56%, an FP4 dot-product block by 21%, and an FP32 accumulator by 10%, while reducing the area of matrix and SIMD units by 10% and 8%, respectively.

OpenAI has not said that AI invented Jalapeño's architecture, so humans have indeed remained responsible for it. But AI was extensively used to turn that architecture into silicon and optimize it ... which brings us to Architect Labs.

Indeed, Architect Labs' Redwood is qualitatively different. Two human architects defined the specification, after which Architect Labs says its AI autonomously generated and verified the logic, generated RTL, verified it, and produced firmware. To top it off, AI also assisted software development, including drivers and kernels. Meanwhile, unlike Google, Nvidia, and OpenAI, the company explicitly describes its system as one that performs machine learning co-design and says it can explore architectures, though without elaboration.

Redwood was 'produced' in under two weeks and runs billion-plus-parameter models, but there is a huge caveat: It has not been taped out. It has never actually been produced as an ASIC; the accelerator runs on an FPGA, and the claimed 3.4X performance-per-watt advantage over Nvidia's Jetson Orin Nano is based on a projected Samsung 8LPP design.

Final words

Just a few years ago, AI in semiconductor development was largely an optimization technology that helped engineers find better ways to implement designs created by humans. Today, it can generate RTL, verify designs, operate EDA tools, and even explore architectural choices, although humans still define what ultimately gets built.

We are therefore considerably closer to machines designing machines, but nowhere near the singularity quite yet. For now, chips are helping design their successors. But they aren't even close to deciding what those successors should be.

Synopsys announced its AgentEngineer solutions, a portfolio of “domain-specific long-horizon agents” built on its new Autopilot Platform. As the company details in a blog post, the portfolio covers six named domains: verification, system validation, implementation, analog and mixed-signal (AMS) design, manufacturing, and simulation and analysis. More than 50 customer engagements are underway, according to the company, and Synopsys confirmed to Tom’s Hardware Premium that general availability is planned for the end of 2026. This follows July, when the company showed agentic AI workflows developed with Nvidia and with Microsoft at DAC, the Design Automation Conference.

The launch brings Synopsys’ plans into focus with a named product line and a target date. The platform’s agents are clearly named and delineated, the engagement count points to customer interest, and a goal for general availability anchors a roadmap for autonomous agents in production. Two of the headline performance figures are restated from July, and the only named customer figure is one company’s range. While Synopsys describes the agents as autonomous, the approval checkpoints remain with humans, the company said.

For companies designing and producing chips who want to leverage the potential efficiency gains of AI, this technology allows them to “accelerate their shift from AI-assisted design to autonomous engineering,” said Ravi Subramanian, chief product management officer at Synopsys.

In a blog post published alongside the release, Anand Thiruvengadam, executive director of product management at Synopsys, detailed three layers: long-horizon AgentEngineers are “domain-specific super agents that orchestrate task agents,” task agents “complete specific, bounded engineering tasks” and can be orchestrated by an AgentEngineer or invoked directly by an engineer, and the tool layer’s engines “execute the requested work” but do not set goals or make decisions. Unlike long-running agents, which may perform one activity for hours or days, long-horizon agents address “goal complexity,” pursuing objectives that can take hundreds or thousands of reasoning steps.

The platform covers everything from orchestration to telemetry, with a “cognitive model” powering what Synopsys calls context intelligence. Access controls, encryption, and runtime guardrails protect customer, partner, and Synopsys IP, which is particularly important when third-party agents share the workflow. Customers can choose commercial, open-source, or fine-tuned language models and deploy on Synopsys Cloud, their own cloud, or on-premises infrastructure. In other words, customers can “bring their own LLMs and data and infrastructure,” Thiruvengadam told Tom’s Hardware Premium.

The blog outlines the verification loop — the agent plans, orchestrates task agents, checks what they return, and adjusts whenever an intermediate result falls short. When a test finds a bug, a root-cause analysis (RCA) agent reads logs, clusters errors, forms a hypothesis, and inspects waveforms to confirm it. The agent then makes “local rewrites of the RTL to prove that the bugs have indeed been fixed” and produces a bug fix manifest. When intermediate results drift from the objective, the agent will “course correct, adapt, react,” he said.

The performance numbers in Synopsys’ release are heady: up to 50x faster verification closure, 20% higher coverage, a 30% productivity boost, 2x better token efficiency, and lower latency. The 50x and 20% figures are not new. Synopsys told Tom’s Hardware Premium that they come from its July work with Nvidia, measured against its own verification workflows without AgentEngineer. The 30% number is at the top of the 10% to 30% range Fujitsu reported for its RTL code generation.

Those productivity gains are measured “compared to what the human experts would have done otherwise or are doing today,” Thiruvengadam said. The 2x token efficiency, meaning fewer tokens for a given task, is customer-reported: an unnamed customer compared Synopsys’ agents with its own, built on commercial agentic harnesses. No figure exists for the latency claim; the release and blog credit it in part to context intelligence, which suggests less time spent waiting on model calls.

Another engagement with results is AheadComputing, whose Vice President of Verification, Alon Mahl, said the Implementation AgentEngineer helped reduce manual engineering effort from RTL handoff through signoff, without giving a number. Intel, MediaTek, and Samsung also endorsed the technology. None gave hard results, but all supported the technology as promising. Today's launch is the portfolio and platform, without production details. Synopsys’ earlier AI tool from 2020, DSO.ai, has passed 100 production tape-outs, while the new agents are still in engagements.

How autonomous are these agents? Each vendor defines autonomy on its own scale, and Synopsys introduced its L1-to-L5 framework last year. “The original vision of L5 was fully autonomous execution. But not just fully autonomous execution, but also complexity,” Thiruvengadam told us, describing L5 as executing a complex workflow autonomously within human guardrails. “That was the idea, and that’s exactly where we are.” Synopsys confirmed that it characterizes the agents as L5. Cadence also claimed Level 5 on its own scale at Computex in June.

Earlier this year, Nvidia chief scientist Bill Dally said AI cut a 10-month, eight-engineer task, porting a standard cell library for GPU design, to one night, but that Nvidia is still “a long way” from having AI design a new GPU end to end.

Human engineers remain in the loop, but the amount of oversight varies. “The guardrails are still going to be defined by the humans, the crucial approval checkpoints are still going to be human-driven,” Thiruvengadam said. “Our customers will have to learn to trust these autonomous systems.” The blog adds that teams can set checkpoints where people inspect results, validate decisions, and redirect the workflow, then “reduce intervention” as confidence grows. No vendor has yet described when its agents stop retrying or escalate to an engineer.

Synopsys says the capabilities are already there; its next goal is general availability. Eyes will be on whether Synopsys reaches general availability by the end of 2026, and names a customer in production when it does. Cadence expects Level 5 early access in the second half of 2026, and Siemens has promised self-verifying capabilities in forthcoming releases. The product exists and works in customers’ hands, and the speedup claims, if they can be realized beyond internal evaluations, and especially if backed by independent testing, appear to be extremely promising.

Intel's 14A (1.4nm-class) process technology is expected to deliver performance 'within 5%' of TSMC's A14 (1.4nm-class) production node, Naga Chandrasekaran, the chief technology and operations officer as well as general manager of Intel Foundry, told investment banking firm KeyBanc (via @Alex_Intel_). Given TSMC's track record of delivering steady performance, power, and area (PPA) gains with every new node, this might sound like entirely good news. However, the statement deserves a closer examination.

Delivering 'within 5%' performance is an ambiguous statement that may mean that 14A will be 5% faster than A14, or that 14A will be 5% slower than A14. While 'within 5%' performance compared to the direct rival of the same class may sound like a good competitive position, in recent years Intel's process technologies trailed TSMC's nodes in transistor density and remained competitive in performance or power. This was, to a large degree, attributed to Intel's historic focus on CPU performance, but not necessarily transistor density, as its own fabs have offset additional costs associated with larger dies.

In fact, actual shipping processors suggest Intel's 18A is at least competitive with TSMC's N2 in maximum achievable CPU frequency as Intel's Core Ultra X9 388H 'Panther Lake' can hit 5.10 GHz (at an 80W max turbo power), AMD's EPYC 9586F has the highest single-core clock of 5.0 GHz (at a default 500W CPU power), Apple's A20 Pro can achieve 4.93 GHz, whereas Apple's M6 can hit 4.78 GHz. These numbers should not be converted directly into a statement such as '18A is X% faster than N2,' because the processors use different architectures, voltages, standard-cell libraries, thermal envelopes, and physical implementations. However, they do provide a useful real-world reference point: the available N2 processors do not show a substantial frequency advantage over 18A. If anything, the highest observed CPU frequencies favor Intel's process.

Based on internal estimates, Intel officially states that compared to its already fast 18A, its 14A is expected to provide 15% – 20% higher performance at the same power, or 25% – 35% lower power at the same frequency and transistor count. By contrast, TSMC expects its A14 to be 10% - 15% faster than N2 at the same power, or 25% - 30% lower power at the same clocks and transistor count.

Combining the observed 18A and N2 CPU frequencies of Intel's 18A and TSMC's N2 with Intel's stated 15% – 20% 14A gain and TSMC's assumed 10% – 15% A14 gain would ordinarily suggest a modest 14A performance advantage of A14 even in most conservative scenarios for Intel. Therefore, Intel's new expectation that 14A will be 'within 5%' of A14 is notably less ambitious than one might infer from the company's published process specifications, even though the 'within 5%' statement does not tell us which process Intel expects to lead.

In fact, advantages of Intel's 14A over TSMC's A14 can be calculated using the highest observed 18A and N2 CPU clocks combined with Intel's and TSMC's official iso power performance projections.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 5.00 GHz (EPYC 9586F).

With Intel’s Core Ultra X9 388H and AMD’s EPYC 9586F as the starting points, the official iso-power performance projections imply a 2% – 11.3% potential performance advantage for 14A over A14, depending on the combination of process-performance assumptions.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 4.78 GHz (Apple M6).

Using Apple's M6 as the real-world N2 reference, a similar calculation gives Intel 14A a 6.5% – 16.2% implied advantage over TSMC A14. Even the worst possible combination for Intel — 14A achieves only +15% while A14 achieves the full +15% — puts Intel's node well beyond the 'within 5%' estimate given by Naga Chandrasekaran.

It should be clearly noted that our calculations do not predict 14A or A14 CPU frequencies, as we use clocks from current CPU architectures with improvement claims for upcoming process technologies. The calculation is useful primarily for illustrating what the companies' published numbers imply relative to today's products.

Intel's 'within 5%' assessment raises an interesting question: why does Intel expect 14A and A14 to be so close when the companies' published process gains appear to suggest a larger gap? Perhaps Intel's assessment incorporates factors that these simple calculations do not capture. Or perhaps the head of Intel Foundry took a page from his boss Lip-Bu Tan's book and now prefers to underpromise.

As the world's only supplier of EUV lithography systems, ASML is Europe's largest company by market capitalization, currently valued at around $660 billion. But it earned almost nothing in Europe this year, down from 1% of total profits in 2025 and 5% in 2024. Why? European chipmakers bought no lithography equipment from ASML in 2026 — and the company is calling on EU authorities to help create demand for European chips.

"We are selling absolutely nothing in Europe," said Frank Heemskerk, executive vice president of public affairs at ASML, while speaking at a panel discussion from the Dutch political and cultural center De Balie. "Because Europe is not investing and because no chip factories are being built in Europe. That is genuinely worrying. […] [Our revenue share in Europe is 0%], it used to be 1%."

Indeed, Europe accounted for 1% of ASML's revenue share in 2025, 5% in 2024, 4% in 2023, and 2% in 2022, based on the company's presentations for investors. In the first two quarters of 2026, however, Europe accounted for 0% of ASML's revenue, according to ASML's earnings reports.

"There simply is no demand here for these kinds of highly specialized machines," Heemskerk said. "That is the problem. So apart from trying to attract investment with capital on the supply side, we should do much more to create demand. […] So, we at ASML are also making an enormous effort, and we are talking with Ursula von der Leyen in Europe, saying: 'try to harness the market power and dynamism that ultimately do exist in Europe in a number of areas.'"

So far, the European Union has been keen on subsidizing building new fabs in Europe (something that did not help to lure Intel in). But ASML is calling on European governments to help aggregate and guarantee demand for European-made chips — which will encourage major European chip consumers to source locally, giving semiconductor manufacturers an economic reason to build or expand fabs in Europe.

"We need to make sure that some of those buyers — the customers of our customers — start talking much more closely with European manufacturers again. In areas such as artificial intelligence for industry, for example, there are still plenty of opportunities that Europe can seize. But you have to organize this collectively."

New fabs are being built…

That said, the ASML EVP may be too pessimistic about Europe's semiconductor industry.

Intel runs its massive Fab 34 near Leixlip, Ireland, and recently announced plans to invest €5 billion in the facility to expand production of CPUs on Intel 4 and Intel 3 process technologies. While the new investment dwarfs Intel's plans to invest roughly €80 billion in its Magdeburg, Germany, fab complex, with two first fabs alone accounting for over €30 billion, it still represents Intel's commitment to its Ireland campus.

In addition, ESMC — which is backed by TSMC, Bosch, Infineon, and NXP — is building a brand-new fab near Dresden that will cost around €15 billion. The fab will be capable of producing chips using 12nm/16nm-class FinFET and 22nm/28nm planar transistor-based process technologies used in a wide range of automotive applications. The same nodes are also used for various consumer electronics and edge applications.

Infineon also opened its new €5 billion Smart Power Fab in Dresden in July 2026, which marked the largest single investment in the company's history and effectively doubled its manufacturing capacity at the site. The 300mm facility produces power semiconductors as well as analog and mixed-signal chips for automotive, industrial, renewable-energy, and AI data-center applications.

Last but not least, GlobalFoundries officially broke ground on the latest major expansion and upgrade of Fab 1 in Dresden this March to increase capacity for its specialty process technologies, including 22nm FD-SOI (22FDX), embedded non-volatile memory (eNVM), and the BCD (bipolar-CMOS-DMOS) node for power management ICs. To some degree, the upgrade was forced by headwinds that GlobalFoundries faced when building the €10.4 billion joint fab with STMicroelectronics in the Grenoble, France, region.

With numerous semiconductor fab projects in place in Europe, ASML will continue to sell its tools to companies in the EU for years to come; the semiconductor industry is far from dead in the bloc. Of course, the important detail is that all of these production facilities are built by multinational corporations (sometimes in collaboration with local companies) — but this is largely a global trend rather than a major issue.

…But there's a catch

Although the fab projects in Europe are large in terms of investment, they pale in comparison with those being built in Taiwan, South Korea, the U.S., and Japan, where tens or even hundreds of billions of dollars are being invested in new semiconductor production facilities.

What is perhaps more important from ASML's standpoint is that none of the ongoing fab projects in Europe are leading-edge fabs set to use EUV and eventually High-NA EUV lithography scanners. The tools that European fabs use today and that new facilities are set to use in the future are mature tools that cost considerably less than advanced EUV or immersion DUV scanners. This is perhaps a concern for ASML, as the company is naturally interested in selling its more sophisticated and expensive equipment.

Another concern is that even advanced silicon produced in Ireland or at ESMC is then shipped to other regions for packaging, meaning that European companies have largely lost their ability to produce sophisticated chips entirely in Europe. In turn, this means that, for now, there is hardly any strategic point for European authorities to create demand for chips that are 'Made in Europe' because they are either not assembled in Europe, not produced in Europe, or not developed in Europe. We have no idea whether this is eventually going to change, but there are currently no signs that it will.

In an unexpected turn of events, Terafab has faced an odd roadblock as a small U.S.-based company called Tera-Print sent a cease-and-desist letter to SpaceX and Tesla back in May to stop using the Terafab name. The company with tera-scale ambitions has run into a tabletop-sized problem because the Tera-Fab name has already been used for about a decade by Tera-Print, according to PCMag.

As it turns out, Tera-Print sells tabletop-sized Tera-Fab-branded beam pen lithography (BPL) tools primarily aimed at bioengineering and prototyping of microfluidic devices and has used the brand for about a decade. The U.S. Department of Defense appears to be a client of Tera-print, which uses Tera-Fab.

While Tera-print claims that the Terafab name could be confused with its Tera-Fab product family, Tesla, SpaceX, and SpaceXAI counter that the operations are fundamentally different: Terafab is set to produce chips in extremely high volumes to serve AI, automotive, robotics, and eventually (at least some) space applications, whereas Tera-print's Tera-Fab is a compact lithography tool that can be used for bioengineering or prototyping of electronic or optical devices.

Formally, the trademark coverage puts both names into the same semiconductor technology bucket, albeit with different descriptions:

• Tesla's Terafab covers 'custom manufacture of semiconductor chips, memory chips, integrated circuits, and wafers' (IC 040) as well as 'distribution services, namely, delivery of semiconductor chips, chip carriers, namely, semiconductor chip housings, memory chips, integrated circuits, semiconductors, and microchips' (IC 039).
• Tera-print's Tera-Fab covers 'Polymer pen and beam pen lithography instruments in the nature of 3D micro-printers and 3D nano-scale printers' (IC 007); 'Polymer pen and beam pen lithography instruments in the nature of 2D micro-scale molecular and material printers and 2D nano-scale molecular and material printers' (IC 009), 'Light-directed photochemical synthesis tools; Industrial advanced materials synthesis tools; Advanced light projection systems; High precision force-feedback sample alignment modules; Environmental control sample chambers' (IC 009); as well as 'training services in the field of AI design and development, electronics, computer science, biology, and material science' (IC 042).

The two companies reportedly entered settlement talks, which included an offer from Tesla, but Tera-Print alleges that Tesla expressed interest in continuing negotiations instead of taking the dispute to court. Tera-Print says it will now defend its registered trademark and argues that the companies operate in related fields, which could lead to confusion.

Even as chipmakers race to build the most advanced chips inside the United States, experts are saying that their efforts are facing one monumental challenge: a massive shortage of skilled workers to run the fabs and factories. According to CNBC, global consulting firm McKinsey and the SEMI Foundation suggest the industry will have up to 157,000 positions that could remain unfilled by 2030.

“I’m concerned,” Samsung semiconductor division EVP Jon Taylor told CNBC in an interview. “We just don’t see that there’s enough technical people in the pipeline.” The McKinsey report says that only 3% of U.S. engineering graduates end up working in the semiconductor industry, and that 73% of chip companies are finding it hard to fill engineering roles. This is a huge contrast to other tech jobs, which saw record layoffs by June of this year, when over 40,000 positions were axed, ostensibly largely due to AI.

The massive demand for memory and storage chips driven by the AI boom, combined with Washington’s efforts to bring semiconductor manufacturing back to the United States, has led to the buildup of multiple fabs and facilities dedicated to it. TSMC was one of the first companies to kick off this building spree, when it started construction on its Arizona campus in 2021. The site started churning out chips last year, with the company committing another $100 billion in July 2026 to build four more 2nm fabs. Intel’s Ohio One plant, which was, at one point, America’s largest fab complex, is also underway, with the site expected to start production between 2030 and 2031.

The big three memory makers — Micron, Samsung, and SK hynix — are also planning or have recently completed major expansions in the U.S. Samsung is starting advanced semiconductor manufacturing in the U.S., with its Taylor, Texas, fab entering risk production this year. The fab is targeting an output of 50,000 wafer starts per month, and it is expected to create 3,500 jobs. “We’re hiring engineers, we’re hiring technicians, we’re hiring people in the supply chain,” Taylor told the publication. “Everybody wants and needs the same thing, and it’s a bit of a race against time right now as everything is starting to come online.”

Micron is also currently building its Boise, Idaho, memory chip fab, which began construction in 2022 and is projected to begin wafer production by 2027. The company has also formally broken ground on its $100-billion New York “megafab,” with aims to produce 40% of its global output within the U.S. by the 2040s. Aside from these massive manufacturing sites, it has also committed $10 billion toward new research labs in the U.S., to be built near the global Micron R&D center in Boise.

Finally, SK hynix also started construction of its first HBM plant in the U.S., with its West Lafayette, Indiana, campus dedicated to packaging these crucial components for AI data centers. There have also been rumors that the South Korean company is in talks with Intel to either lease space at its Ohio One factory or launch a joint venture alongside other AI hyperscalers to build memory chips in the U.S.

All these construction projects, plus the requisite supply chains, will necessitate thousands of workers. Local universities like Purdue University and Arizona State University are already investing millions of dollars to help prepare a capable workforce, with the former launching degrees in 2022 focused on semiconductors. Samsung and Intel are also investing in various programs, including internships and scholarships, to help secure a future workforce for the companies.

However, salary is one major concern listed by the SEMI Foundation. U.S. chip fabs typically pay $127,000 to $187,000, with senior staff getting $238,000 or more. While this is a more-than-competitive salary in the U.S., it’s dwarfed by the bonuses recently offered by Samsung and SK hynix in South Korea, which have reached hundreds of thousands of dollars. With the projected worker shortfall, we should expect the job offers from these semiconductor companies to catch up with their eastern counterparts if they want to secure and maintain talent here in the U.S.

One of the key challenges with the development of extreme ultraviolet (EUV) lithography scanners is building a powerful and reliable light source. ASML, which is the only company to manufacture EUV lithography tools, uses rather complicated laser-produced plasma (LPP) technology to generate EUV light. By contrast, numerous companies propose to use a free-electron laser (FEL), which relies on a particle accelerator, for EUV generation. While FEL has its advantages and is even endorsed by Elon Musk, ASML is unlikely to adopt it, according to JPMorgan.

"Given laser advances, ASML sees no reason to try new 'FEL' light source favored by Musk," reports Semi Doped, citing a JPMorgan note for clients.

Modern EUV lithography systems use laser-produced plasma light sources that fire powerful CO₂ laser pulses at tiny droplets of molten tin, around 30 microns in diameter, which turns them into ionized plasma with electron temperatures of several tens of electron volts that emits 13.5-nm EUV radiation. The light is then collected by a roughly 0.5-meter elliptical collector mirror coated with multiple layers of molybdenum and silicon, which selectively reflects as much 13.5-nm radiation as possible and directs it toward the intermediate focus at the entrance to the scanner.

Since virtually all materials absorb EUV radiation — even specialized multilayer mirrors absorb a substantial portion of it — the entire optical path must operate in vacuum and use reflective rather than conventional refractive optics, which is one reason why generating sufficient EUV source power remains challenging.

Despite major challenges, ASML has gradually increased the source power of its LPP light sources from around 250W to around 500W and plans to increase it to 1000W in the coming years. In addition, the company plans to almost double the number of generated tin droplets to 100,000 every second.

A free-electron laser (FEL) generates EUV light by accelerating electrons to nearly the speed of light and passing the electron beam through an undulator, a series of alternating magnets that force electrons to oscillate and emit radiation. Interaction between the electrons and their radiation causes them to form microscopic bunches and emit light with a 13.5-nm wavelength. This approach eliminates tin droplets and associated debris (that require usage of protective pellicles on photomasks) as well as potentially provides substantially higher EUV power than LPP sources. Furthermore, one FEL can potentially replace multiple LPP sources with a single FEL and a large EUV beam-distribution system.

Yet, there is a major tradeoff: instead of a relatively compact LPP, FEL requires a highly complex particle accelerator, an electron source, a long undulator, electron-beam control, radiation shielding, and an extremely complex distribution system featuring mirrors capable of handling and distributing very high EUV power without losing too much of it along the way. The whole machine must achieve semiconductor fab levels of availability, efficiency, and cost, something that took ASML and the rest of the industry years to achieve.

So, while there is a great enthusiasm surrounding FEL in China, the U.S., and Japan, it will likely take a decade, if not more, before FEL will be able to rival LPP in real semiconductor production facilities. The technology will likely devour billions of dollars in the meantime, so not all entities currently pursuing FEL will live that long.

PieceMakers, a Nanya-backed DRAM designer, began trading on Taiwan’s Emerging Stock Board on September 16 at a NT$740 reference price, Cnyes reported ahead of the debut. PieceMakers is not an HBM company. Instead, it bets that inference memory diverges from training memory, President Lee Hsiao-wen told Cnyes, and that DRAM stacked directly on the processor with hybrid bonding can sit between Nvidia’s SRAM-only Groq LPU and HBM. As it stands, design fees, not chips, carry the company's profit, with AI custom-design work accounting for around 40% of the company's revenue in the first half of 2026. Piecemakers Chairman Joseph Ting told TechNews that its first volume customer program will not contribute to the company's financials until 2027 at the earliest.

At roughly 60.4 million shares outstanding, that price values the company at around NT$44.7 billion (around $1.4 billion). Taiwan's Emerging Board is the Taipei Exchange's pre-listing market, not a main-board IPO, so shares trade through market makers ahead of any formal listing application. The stock ended its first session at NT$915, 23.6% above the NT$740 reference price, after opening at NT$1,035 and trading as high as NT$1,205.

Nanya Technology is the largest holder of Piecemakers, at 33.96%, after selling 715,000 shares at NT$740 to seed the float, a disposal it disclosed in a Sept. 9 exchange filing reported by Knews.

What PieceMakers sells

PieceMakers was founded in January 2006 in Hsinchu, Taiwan, led by chairman Joseph Ting and president Lee Hsiao-wen. Historically, the company has designed standard SDR/DDR DRAM and known-good-die (KGD) parts through representatives in China, Japan, France, Turkey, and Israel. Now, the company seeks to shift from direct product sales to custom design services, paid as non-recurring engineering (NRE) fees, and then to IP licensing, royalties, and turnkey production from 2027, the company said at its Sept. 7 briefing, UDN reported.

Revenue from the AI custom design unit has risen from around 4% in 2024 to almost 40% in the first half of 2026. The products behind that increase are HBLL (High Bandwidth, Low Latency RAM), a 2D die rated at 144 GB/s that was taped out in 2016 for Intel’s HPC line and published at ISSCC in 2017, and HiBaLL, the 3D-stacked version rated at more than 1 TB/s, the company claims.

The company described its customers to Cnyes as developers of cloud AI inference accelerators, international semiconductor players, and North American customers, with some programs in design and verification, and none named. Qualcomm CEO Cristiano Amon’s Computex keynote backdrop in June listed PieceMakers among Taiwan ecosystem partners, although neither company has defined the relationship. The takeaway is that the profit is in design fees and not chips. The margin curve matches a pre-royalty Non-Recurring Engineering (NRE) business, rather than a traditional memory vendor.

Why Nanya is chasing this instead of HBM

Nanya’s AI-memory strategy is custom and edge rather than HBM3E. PieceMakers is the first half of a strategy laid out in 2024. On Aug. 7, 2025, Nanya announced a joint venture with Etron Technology, a Hsinchu-based chip designer, capitalized at NT$500 million, with 80/20 ownership. The venture was envisioned to design custom high-bandwidth memory for edge AI devices rather than for data center accelerators. Nanya president Pei-Ing Lee said earlier in 2025 that the company would not compete in HBM3 or HBM3E, TrendForce reported.

Both halves of the strategy rely on Formosa Advanced Technologies, the Formosa Plastics Group’s test and assembly affiliate, for packaging. It is building the through-silicon-via (TSV) and die-stacking processes that both need. The surge in DRAM pricing has made commodity memory Nanya’s real business, which leaves PieceMakers a cheap side bet that has become a windfall. Nanya took advantage of this by selling around 3% of its stake in a move that suggests it is acting more as an investor than a parent building a memory stack.

The inference gap

Groq is an AI inference startup that Nvidia struck a $20 billion licensing-and-talent deal for on Dec. 24, 2025. Nvidia announced its first chip built from that, the Groq 3 LPU (language processing unit), Nvidia’s SRAM-based inference chip, at GTC, its annual developer conference, in San Jose earlier this year.

There is no HBM or DRAM on the Groq 3 LPU. Instead, it uses 512MB of SRAM on the die to deliver 150 TB/s of bandwidth against 22 TB/s from the 288GB of HBM4 on each Rubin GPU. It’s a decode-only co-processor with Rubin handling the prompt prefill, displacing Nvidia’s Rubin CPX from the roadmap.

At Hot Chips 2026, Nvidia’s Igor Arsovski, Groq’s former chief architect, said the rack is in production and published the first third-party benchmark: 3,431 tokens per second on a 100K-context, 31B-parameter model, at about four times the next-fastest public endpoint, in a single-request test that we noted isn’t directly comparable to the shared endpoints it was measured against. The cost is capacity: at 512MB per chip, a 256-LPU rack holds 128GB, with the model needing 62 chips at FP8 just to hold the benchmark weights. Nvidia accepted that trade for decode speed, which supports Lee’s point that the market leader’s newest inference product contains no HBM.

At Hot Chips, Samsung’s Sangwook Han laid out a three-phase HBM roadmap that ends in zHBM, which is DRAM stacked directly on top of the processor rather than beside it on an interposer. Samsung projects about 70% less I/O power usage than HBM5 with roughly 2.3x the bandwidth of a four-stack HBM4E system, with zHBM’s stacks limited to about four-high due to heat, at around 100W less. This would require wafer-on-wafer hybrid copper bonding and tight co-design between DRAM and SoC teams. SK hynix’s Jaesik Lee, VP of package engineering, said on Aug. 23 that hybrid bonding won’t be ready for HBM4E, leaving HBM5 as the earliest point. Counterpoint Research expects full-scale HBM production with the technique around 2029–2030.

PieceMakers offers a different version. Instead of the GPU-plus-HBM 2.5D layout, it bonds the DRAM stack directly onto the processor, wafer-on-wafer, with hybrid bonding instead of microbumps. This fits far more connections with the finer pitch, improving bandwidth, and the shorter path reduces both latency and power consumption. The company puts its wafer-on-wafer product at more than 2 TB/s per layer with latency under 20ns, the company figures, but the target is more capacity than SRAM at a lower cost and power than HBM. PieceMakers is not doing the TSV or hybrid bonding itself, as this is handled by the customer’s logic wafer foundry, Ting added. This custom service promises a 2027 date against Samsung's undated roadmap end and SK hynix's HBM5-at-the-earliest timing. Nvidia and Samsung have each, in their own way, settled the architecture question, with the open question being the customer.

Yield is the product

Lee also said that yield is the biggest hurdle to wafer-on-wafer mass production. The repair architecture has to be designed in, with testing before bonding, after bonding, and then after logic integration. Lee’s own example was 80% yield per layer, at which four layers come out at about 41% and eight at 17%. Our recently-published hybrid bonding state of play covers the process side in more detail.

This better puts into perspective why the company sells repair and known-good-die IP as much as it does bandwidth. It’s also why an IP-and-royalty model fits the strategy — yield IP is portable across customers while a bandwidth number is not.

What to watch

For PieceMakers, AI revenue remains primarily NRE until there is a first named customer, with the first volume program expected in 2027 at the earliest. Ting said that Nanya’s Q3 2026 results, which come in late October, will gauge the PieceMakers gain and reveal further financial information. SK hynix’s hybrid-bonding timing, which targets HBM5 at the earliest, is the current benchmark, although its 16- and 20-layer memory stacks are a separate problem from a few DRAM layers on a logic wafer. Qualcomm may also describe its relationship with PieceMakers more formally.

PieceMakers is likely to end up as an IP licensor with a small number of accelerator customers and turnkey volume through Nanya and Formosa Advanced Technologies. The technology risk is the foundry’s and the customer’s, which is why PieceMakers’ design-fee model works. PieceMakers is expected to benefit from a 2027–2028 ramp, later than Ting’s 2027. If the largest HBM maker won’t bond its own memory this way before HBM5, PieceMakers’ own 2027 date is the one it must meet.

China's progress toward technological self-sufficiency in recent years is undeniable, but there is one thing that the country has so far failed to develop: lithography tools that are on par with those offered by ASML. That shortcoming has greatly hampered its domestic semiconductor industry. But Nvidia CEO Jensen Huang believes China will develop its own advanced lithography systems in just three or four years.

"They are going to get there by 2030," Huang said in an interview with The All-In Podcast (at 43:43). "2030 is just around the corner. The way to think about China is that it is really good at high-volume production. It is just a matter of time[...] so two or three years is just a click; it is nothing. So as far as they are concerned, they are already there."

Huang tends to look optimistically at China's technological development. Specifically, he is known for calling China's AI industry as being 'right behind' American frontier labs, which may well be correct, given how much capital China is investing in AI. But when it comes to the Chinese semiconductor industry in general and its lithography sector in particular, Huang may be too optimistic.

At present, China's leading producer of lithography tools — Shanghai Micro Electronics Equipment — can mass-produce a 193-nm ArF dry scanner that can be used to build chips on 90nm-class process technology. While the company has reportedly developed a 28nm-capable ArF immersion scanner, there is no public evidence that such systems are produced in volume and are used for high-volume chip production.

Although there are reports that Shanghai Aishengna Electronic Technology Group (a unit, or an affiliate of SMEE) has delivered its first immersion scanner that may be capable of printing chips using 28nm-class process technology, these tools will require extensive qualification before they can be used for high-volume manufacturing of semiconductors, so if deployment follows standard timelines, it will take years before this unit will be used for mass producing chips.

Even assuming that the first scanners are delivered to Chinese chipmakers in 2026, widespread production use before 2028–2029 appears unlikely. Furthermore, matching the capabilities of an early-generation ASML immersion scanner would still leave Chinese lithography suppliers considerably behind ASML's contemporary systems, which makes technological parity in ArF immersion lithography by 2030 highly unlikely.

China is considerably further behind in extreme ultraviolet (EUV) lithography. While there are reports that Chinese scientists have managed to develop a laser-produced plasma source that can generate the 13.5-nanometer wavelength light required for the technology, it does not look like China is close to assembling even a prototype EUV scanner itself.

Even if China can assemble an EUV experimental exposure platform without having mastered production-quality immersion DUV, it is hard to imagine a Chinese company producing EUV scanners without solving the hardest problems common to both DUV and EUV technologies. A production lithography scanner requires extraordinary capabilities in wafer and reticle stages, alignment, overlay, projection optics, and metrology, just to name a few.

If China is still struggling to industrialize these capabilities for immersion DUV, there is little reason to assume it has somehow solved them at the substantially more demanding EUV level. But given the potentially existential stakes of the AI race, and the determination of the Chinese government to achieve technological self-sufficiency, it may just indeed be a matter of time.

South Korean memory chip manufacturer SK hynix is in talks with Intel to start manufacturing inside the U.S., according to Reuters. The company is reportedly considering multiple options, including leasing space at the under-construction Intel Ohio One site and forming a joint venture with Intel and other AI hyperscalers desperate for HBM.

This move could help alleviate the memory shortage. It would also complement the company’s expansion in Indiana, where it recently broke ground on an HBM packaging plant a few weeks after its historic $26.5-billion Nasdaq listing. It’s unclear yet if these talks are part of the results of the South Korean president’s visit to Silicon Valley in an effort to expedite negotiations between its top tech companies and their U.S. counterparts, but SK Group chairperson Chey Tae-won told reporters in July, “I think we need to build a factory in the United States. If possible, I believe we should build it.”

However, there are also concerns that Seoul might object to such investment. The South Korean government just unveiled a $520 billion investment plan to increase chipmaking capacity within its shores and keep the country competitive in the AI race; at the same time, it’s also in talks with the U.S. to finalize its $350 billion investment commitment to Washington to reduce tariffs on South Korean goods, $200 billion of which is still undecided on which projects it will be deployed on. Meanwhile, the Commerce Department has threatened to impose more tariffs on South Korean and Taiwanese tech companies if they fail to invest in U.S. manufacturing. This potentially puts SK hynix at a precarious position, especially as it balances the demands from the White House and the Blue House.

Neither company has confirmed these rumors, though. SK hynix told Reuters that it’s “reviewing various measures, including establishing additional production bases, to strengthen the competitiveness of its memory business,” but “no matters have been determined at this stage.” On the other hand, Intel called them speculation and declined to comment on the matter, only saying that it was continuing to invest in the Ohio project, which is expected to come online between 2030 and 2031.

Micron has announced a one-time cash appreciation bonus of NT$1 million (US$31,650) as part of a broader compensation/reward package for its employees based in Taiwan. According to a Reuters report, the full package — which comes amidst ongoing disputes between the U.S. memory giant and its Taiwanese workforce — will see each employee earn a minimum of NT$1.7 million ($53,809.39).

The company called the payouts the largest rewards package in company history, confirming that more than 60,000 employees globally will receive scaled rewards for fiscal year 2026, “following an extraordinary year for the company.” Across the last four quarters, Micron’s cumulative net income from sales of high-demand memory chips has crossed a staggering $50.47 billion, with its Q3 earnings representing a 346% year-over-year increase. After the announcement, the union representing workers at Micron's Taoyuan plant officially rejected the company's bonus proposal, calling the package a distraction.

Under the announced payout, every Taiwan-based employee who joined the company on or before August 29, 2025, is eligible for the flat NT$1 million cash bonus. Those hired during fiscal year 2026 will receive a prorated amount. For direct manufacturing and production-line workers, the total bonus rewards are equivalent to 35 to 68 months of basic salary. Direct labor employees will receive a minimum total cash compensation of NT$1.7 million (US$53,809), while the average total compensation for junior engineers is projected to reach NT$3.4 million (roughly US$106,250), comprising NT$2.9 million in cash and the remainder in equity grants.

The announcement — which mirrors bonus payouts by Samsung and SK Hynix amid the soaring profits from the AI boom — comes after local unions in Taoyuan and Taichung, representing 10,000 of Micron's 15,000 Taiwan workforce, began threatening a strike on September 1, demanding packages similar to the payouts that will see Samsung employees receive over $300,000 in bonuses. The Taiwanese government stepped in to force a mediation. However, unlike in Samsung's case, which also involved government intervention that narrowly averted a potential strike, the talks fell through on September 4 after both parties failed to reach a consensus, leading Micron to announce the NT$1 million bonus package a week later.

In an official statement following Micron's announcement, the union said the new package "sidestepped" the real discussion about a transparent bonus system. The union is pushing for structural change, including a permanent profit-sharing model in which 15% of the company's operating profits are allocated directly to workers and distributed quarterly. They are also demanding a larger one-off payment equivalent to roughly 83 months of salary for fiscal year 2026. Last September, South Korea’s SK Hynix reached a settlement with its union to allocate 10% of annual operating profit directly to employees as performance bonuses for the next decade, eliminating bonus caps.

Similar incidents have played out across the semiconductor industry as companies continue to pull in unprecedented profits from the AI boom. Workers in these industries believe they should share in profits and are requesting concrete institutional safeguards to ensure they are fairly compensated during high-profit AI booms, rather than relying on arbitrary, opaque bonuses decided solely by management. Samsung's unions were ready to strike before reaching an agreement with the company and even held a demonstration attended by over 30,000 Samsung union members.

In the case of Micron — which announced a record-breaking GAAP net income of $28.24 billion in just Q3 2026 — the threat of a strike continues to loom following the Union’s rejection of its proposed payout. A critical second round of mediation is officially scheduled for September 21, 2026. If that upcoming meeting falls apart, the union plans to hold a vote allowing members to strike. In an earlier internal survey, 80% of union members voted in favor of a strike.

Jiangsu Pacific Quartz, a high-purity quartz (HPQ) producer from China, is already supplying its HPQ material to leading domestic and overseas producers of chipmaking tools, including Lam Research and Tokyo Electron. More recently, the company's materials/components have passed certification by a domestic DRAM manufacturer. Analyst TP Huang, who hosts the China Tech Talk podcast, believes that the DRAM maker is CXMT.

While Pacific Quartz's achievements are significant, the company's components are used in semiconductor production equipment after the silicon wafer has been made. Meanwhile, Ingots for semiconductor wafers are grown in crucibles made from high-purity fused quartz, typically over 99.999% SiO₂ (5N+), with much tighter limits on individual critical contaminants. For now, such quartz can only be obtained in significant volumes from Sibelco and The Quartz Corp., which operate in Spruce Pine, North Carolina, and from Russian Quartz LLC, which can produce modest volumes.

Pacific Quartz has supplied Lam Research and Tokyo Electron with ultra-high-purity quartz consumables, such as LPCVD diffusion tubes, wafer boats, quartz ingots, quartz plates, and high-purity quartz tubes, since 2019–2020. Typically, quartz used for process equipment is 4N5 – 5N purity (~99.995–99.999% SiO₂). So Pacific Quartz's products are good enough for semiconductor tools.

More recently, Pacific Quartz said its quartz products manufactured from its own high-purity quartz sand passed qualification at a leading Chinese DRAM manufacturer, apparently CXMT, for use in 300-mm wafer production. This is particularly significant because it demonstrates a largely domestic supply chain for Chinese quartz that starts with Pacific Quartz's purified high-purity sand, which is then processed into semiconductor furnace-tube material that goes to a DRAM fab. While CXMT certainly uses equipment from Lam Research and Tokyo Electron, we cannot say for sure that all the quartz consumables that these tools use are made by Pacific Quartz.

Semiconductor furnace tubes are typically made from roughly 5N-class high-purity fused quartz, with stringent limits on electrically active and mobile contaminants, as they can migrate onto/into hot silicon wafers and alter transistor characteristics, ultimately creating defects and lowering yield.

While China-based Pacific Quartz can produce components for semiconductor production equipment, it still cannot produce crucibles good enough to grow silicon wafers with 9N–11N purity. Will it change in the foreseeable future? Only time will tell.

ABF substrates, the specialized insulating and wiring bases that connect tiny silicon chips above them to the much larger printed circuit boards below, sit beneath most high-end CPUs, GPUs, and AI accelerators. Featuring the Ajinomoto build-up film (ABF), these substrates have been critical to the semiconductor industry since the late 1990s, with personal computers, workstations, servers, and networking silicon driving steady demand for decades.

The artificial intelligence boom has multiplied that demand exponentially. Training and inference for frontier models now run across data centers, each housing hundreds of thousands of accelerators and providing hundreds of megawatts of compute. Nvidia alone shipped an estimated 3.2 million Blackwell GPU packages through the end of 2025, with every one of those accelerators packaged on an ABF substrate. Meanwhile, the industry is already entering the gigawatt era with humongous data center buildouts, each expected to house millions of AI accelerators.

This edifice rests on a remarkably narrow supply chain. Practically every advanced logic and AI chip made today by Intel, AMD, and Nvidia depends fundamentally on ABF substrates. These substrates are the conventional default for high-performance packaging. They are made by a small group of specialists, including Unimicron, Ibiden, Kinsus, Shinko Electric Industries, Samsung Electromechanics, and Nan Ya PCB. The upstream supply chain gets much tighter.

The one common denominator across ABF substrates, regardless of manufacturer, is the Ajinomoto build-up film itself. Each substrate maker laminates its build-up layers using dielectric film supplied by Japan's Ajinomoto, which controls a reported 95% or more of the global market. A single company, better known for food seasoning than microelectronics, sits at the base of one of the most concentrated supply chains in computing, almost singlehandedly supplying a material for hundreds of millions of semiconductor devices. Not surprisingly, demand is now growing beyond what the supply chain can comfortably supply.

Compounding this crunch, modern AI accelerators now pack multiple compute, memory, and supporting components onto a single board. As a result, the substrate is getting larger across the X-Y footprint to accommodate the expanding package. Manufacturers are also adding more build-up layers to the substrate to route the growing number of signals and power connections. Each additional layer requires another ABF layer, further multiplying demand across millions of accelerators and extending manufacturing times.

Unfortunately, the complications don't stop there. Beyond further straining the supply chain, expanding the substrates is creating technical problems, such as warpage, yield issues, and electrical losses within the component itself. This leaves the ABF substrate ecosystem facing two related challenges: producing enough advanced substrates for a rapidly expanding fleet of AI accelerators, while simultaneously re-engineering these substrates so they can continue to scale without becoming unmanufacturable or impractical.

The ABF substrate roadmap is consequently as much about supply-chain capacity as it is about the hardware itself, with suppliers such as Ajinomoto and Ibiden outlining plans to expand material and manufacturing capacity, respectively. At the same time, the wider industry — Intel, Samsung, and SK's Absolics among them — is exploring glass-core substrates and other material technologies to push past the limits of organic ABF.

ABF substrates

Silicon dies, including CPUs and GPUs, cannot communicate directly with the printed circuit board beneath them. The connection pads on a die are spaced micrometers apart, while the traces on a motherboard are spaced hundreds of micrometers to millimeters apart. Every high-performance chip, therefore, sits on an intermediary package substrate — a dense, multilayer board that fans the ultra-fine connections on the die outward into connections large enough for the motherboard to handle, while also providing signal routing, power and ground distribution, and mechanical support for the package.

ABF substrates used in AI accelerators typically consist of a rigid, glass-reinforced resin core sandwiched between successive build-up layers of copper wiring and insulating film. The core provides much of the mechanical rigidity, while the layers provide the increasingly dense wiring required close to the silicon.

To create the substrate, the manufacturer laminates the ABF dielectric onto the structure, forms microscopic vias — commonly with a CO2 laser — and then uses lithography and copper deposition to create a new wiring layer. High-end substrates typically use a semi-additive process (SAP), in which fine copper traces are plated up from a thin conductive seed layer. Another ABF layer is then laminated over it, and the process repeats. The film electrically separates successive copper layers, while plated microvias connect them vertically.

Ajinomoto developed the film in the 1990s, after which it gradually became the industry default for its low dielectric loss, fine-line capability, and smooth lamination. The company reportedly accounts for roughly 95% of the substrate film market, with its nearest competitor, Sekisui Chemical, holding only a low-single-digit share.

The manufacturing tier above the film is more populated but still concentrated. Unimicron, Ibiden, and Shinko together account for roughly three-quarters of the substrate market by most estimates, with AT&S and Nan Ya PCB rounding out the leading group. These companies take ABF and other materials and manufacture the finished multilayer substrate. Semiconductor packaging companies, such as TSMC and Amkor, then integrate those substrates into packages containing the processor, memory, and other components.

AI accelerators are pushing substrates outward and upward

To deliver the compute and memory bandwidth that frontier models demand, the industry is packing ever more silicon onto each AI accelerator. Designers now place multiple large logic dies alongside a growing number of high-bandwidth memory stacks on a single package. Nvidia's Blackwell generation mounts two reticle-sized GPU dies and eight HBM3E stacks on a single package, with its upcoming Rubin and Rubin Ultra parts pushing it further still. TSMC's CoWoS packaging is scaling from around 3.3 reticles — each roughly 830 square millimeters of silicon — a generation ago to 5.5 reticles in volume production in 2026, with a roadmap reaching 9.5 reticles in 2027 and beyond 14 reticles by 2029, when a single package is expected to carry roughly ten compute dies and twenty or more memory stacks.

This expansion of the accelerator package is driving the substrate’s expansion on two physical levels. The first expansion is the substrate's footprint in the X-Y axes. The base has to get wider and longer to accommodate the larger package footprint. Ibiden's current roadmap puts its cutting-edge substrate size at 90 × 90mm (3.54 x 3.54 inches) in 2026, 110 × 110mm (4.33 x 4.33 inches) in 2028, and 130 × 130mm (5.12 x 5.12 inches) and larger from 2030 onward. Ajinomoto independently expects the representative advanced AI packages its film goes into to grow from roughly 100 mm² in 2026 to about 120 mm² for 3D AI packages from 2031.

The second expansion is along the Z axis through additional layers. An expanded collection of compute dies and memory creates more signals to route, while the corresponding increase in power draw requires extensive power and ground distribution, all of which must be carried in a growing number of layers. Ibiden's roadmap targets a 10-X-10 buildup structure in 2026, 12-X-12 in 2028, and 14-X-14 from 2030. Here, the numbers represent the build-up layers on either side of the central substrate core: “10-X-10” means 10 build-up layers per side of the core — which is represented by the “X” — each comprising one dielectric layer (ABF) plus one patterned copper layer, working as a pair.

Nan Ya PCB's roadmap points in the same direction. From an 11+N+11 baseline, it targets 24-layer substrates in 2026 and more than 24 layers in the first half of 2027, while tightening line and space from a 9/12 µm baseline to 8/8 µm and then to 6/7 µm by early 2027. Layer-counting conventions differ between vendors, so a per-side figure and a total layer count don't necessarily line up directly.

The substrate’s expansion in both directions creates several challenges. Increasing the X-Y area makes the package harder to keep flat. Silicon, copper, the substrate core, and the polymer build-up materials that make up the substrate expand by different amounts when heated. As the package is bonded during assembly at around 250⁰C and then cooled, these mismatches cause the layers to pull against one another, leading to warping — a problem that becomes harder to control as package dimensions increase.

Excessive warpage can undermine solder-joint formation, layer-to-layer alignment, and reliability, while a larger substrate also occupies more manufacturing-panel area and exposes more area to potential defects. Organic substrates are reported to lose usable flatness once packages exceed roughly 120mm per side, a threshold that the largest AI accelerators are now reaching and that Ibiden's own roadmap — climbing toward 130mm and beyond — is set to cross.

The growing layer count along the z-axis also creates manufacturing challenges around yield, capacity, and time. Every new substrate layer requires a full manufacturing sequence of several steps, all held to sub-ten-micron tolerances. Each added layer increases the chance of a defect or alignment error that can scrap the whole substrate.

Additionally, layer count consumes manufacturing capacity and time in proportion. This is why Ibiden frames future demand in terms of semi-additive processing load rather than a simple substrate count, as a single advanced substrate now consumes far more of a line's capacity than a finished-unit tally would suggest.

Overall, the simultaneous expansion in substrate area and layer count means ABF consumption is rising much faster than processor shipments alone suggest. Ajinomoto illustrated this in its 2025 integrated report with a larger AI substrate that had about 3.5 times the board area and three times as many ABF layers as a conventional design — 18 layers against six — consuming roughly ten times as much ABF overall. This surging material consumption, set against an extremely concentrated supply base, extends the ABF substrate story beyond a technical problem into a supply-chain constraint.

The supply chain constraint

Like many components in the semiconductor industry chain before the AI boom, demand for ABF substrates periodically swung both ways. A severe bottleneck through 2020-2022 — driven by pandemic-era PC and server demand — was followed by an oversupply in 2023, as substrate manufacturers expanded capacity. However, that capacity was built for low-layer-count, smaller consumer substrates, not the large-body, multi-layer packages AI demands.

These advanced products require sufficiently large manufacturing formats, fine SAP wiring, tight layer registration, acceptable warpage, and high yields across much larger structures. Ibiden captures this by measuring demand not in finished substrates but in semi-additive-process load — the actual processing work each part imposes on a line. Indexing 2024 at 1.0, it expects the SAP load of a single AI-server substrate to reach 1.8 times that in 2026 and 2.5 times in 2028, with the company stating that substrate expansion will push total SAP demand beyond industry supply capacity, indicating a constraint in the manufacturing process itself.

The bottleneck is even tighter at the ABF material level. Ajinomoto's film capacity was already running at full load in the second quarter of 2026, at a reported two million square meters per month, although the company has outlined plans to increase capacity. A near-monopoly supplier at full capacity while consumption surges paints a clear picture of the bottleneck’s severity.

Unsurprisingly, prices have moved accordingly. Ajinomoto notified substrate manufacturers in May 2026 that it would raise ABF film prices by approximately 30%, effective in the third quarter. The hike is coming alongside comparable increases in copper-clad laminates from Resonac and Mitsubishi Gas Chemical, compounding pressure across the whole stack. Further tightening the squeeze, Ajinomoto recently cut shipments of the critical ABF film to China by 30%.

The growing ABF substrate problem cannot simply be attributed to Ajinomoto running out of film. In fact, while it's running at full capacity, the company says it has no concerns about its overall supply chain. The constraint stretches across the entire chain containing ABF, glass cloth, and other materials, SAP equipment, large-format substrate factories, yield, and customer-qualified production capacity.

The immense industry demand is progressively tightening the crunch. Several supply-chain analyses converge on an ABF supply-demand shortfall of roughly 10% in the second half of 2026, widening to around 21% in 2027 and potentially exceeding 40% by 2028, with demand for substrate area projected to grow at a compound annual rate near 39% from 2025 to 2028 as accelerators integrate more components.

The roadmap to recovery: more capacity, better materials

The industry is responding to ABF substrates' multifaceted constraints on multiple fronts: expanding manufacturing capacity to relieve near-term supply pressure while qualifying new materials and substrate architectures to break through the technical limits. Capacity expansion is already underway across the supply chain.

Ibiden is executing ¥500 billion ($3.1 billion) in capital investment across fiscal years 2026 to 2028 — the largest single substrate expansion on record — targeting 2.8 times its 2024 capacity for ASIC and AI-server substrates by 2028. Unimicron raised its 2026 capital spending to a record NT$34 billion ($1.07 billion), with a focus on ABF substrates. Meanwhile, Samsung Electro-Mechanics, Samsung's substrate arm, has committed $1.2 billion to expand ABF substrate production, with volume production expected by the third quarter of 2027.

Pegatron's substrate unit, Kinsus, has approved NT$23.5 billion ($722 million) for ABF equipment over three years and now focuses its most advanced lines almost entirely on AI clients, aiming to lift monthly output at its Taoyuan plant by roughly 25% by 2027. While these projects address the shortage directly, their lead times mean the crunch may continue for a while, as supply cannot respond instantly to the AI demand spike.

Ajinomoto is expanding upstream as well. A new plant in Gunma entered full operation in 2025. The company has invested roughly ¥25 billion ($157 million) in ABF production since 2023 and has said it will invest at least as much again by 2030, targeting a capacity increase of more than 50%. It is also adding a third Japanese base for varnish production — envisioned to provide capacity comparable to Gunma — with construction planned for 2028 and operations to begin in 2032.

However, capacity only solves the problem if the current substrate architecture can continue to scale. The material roadmap — aimed at addressing the physical constraints of ABF substrates — is therefore advancing parallel to the factory roadmap. Ajinomoto says present and future ABF generations are being engineered for larger, more multilayered substrates, high-bandwidth I/O, lower transmission loss, and improved resistance to warpage and humidity. The company expects newer, higher-value ABF grades to take an increasing share of its portfolio through 2030.

Substrate makers are addressing the problem from the process side. Nan Ya plans to move beyond 150 mm body sizes and 24 layers while shrinking copper line/space geometry toward 6/7 microns in the first half of 2027. Its materials roadmap includes an ultra-low-CTE core material with a CTE below 3 ppm/°C, alongside low-Dk, low-Df, and low-CTE dielectrics. Finer wiring allows a substrate to support more connections without relying solely on additional area or layers, while low-expansion materials help keep the growing structure flat.

Eventually, the substrate's central core itself may change to glass. Organic substrate cores are increasingly difficult to keep dimensionally stable as packages approach and surpass 100 mm. Glass can be matched more closely to silicon's thermal expansion — providing dimensional stability — and offers substantially lower dielectric loss for high-speed links. It has therefore emerged as one of the industry's main solutions to warpage.

As we detailed in our glass substrate roadmap, the move to a glass core is drawing a broad field, as it sits at the intersection of substrate-making, glass manufacturing, and advanced packaging, pulling in chip-and-packaging houses, display and glass specialists, and the incumbent substrate makers alike. Intel demonstrated a package that combines EMIB with a glass substrate at NEPCON Japan in January 2026, although the company still places commercial glass-substrate deployment in the latter half of the decade.

SK Group subsidiary Absolics is operating a low-volume glass-substrate manufacturing facility in Covington, Georgia — backed by $100 million in US CHIPS Act funding — producing prototype and qualification samples for customers, such as AMD for its MI400-series accelerators, while Samsung Electro-Mechanics is producing prototypes on a pilot line in Sejong and now plans mass production through its glass-core joint venture after 2027.

TSMC, meanwhile, is pursuing panel-level packaging through its chip-on-panel-on-substrate (CoPoS) platform, moving to a 310 x 310mm panel format, with a pilot line at its VisEra subsidiary, trial production targeted for 2027 and mass production for the second half of 2028. Glass-core substrates are a separate, later step on TSMC's roadmap, with commercial scale projected after 2030. Ibiden also puts “glass core” on its substrate technology roadmap around 2030 as a solution for warpage control.

The glass core — most likely a late-2020s-to-2030s technology — is positioned as a solution to the warpage wall. It replaces the organic core, not the ABF itself, which would remain the buildup material. A glass core may soften ABF demand per package, as glass's flatness allows finer routing and potentially fewer buildup layers, but it does not remove the material or the dependency. There's the possibility that a future dielectric material will eventually replace ABF, although that doesn't seem to be the industry's main focus currently.

Regardless, the near-term roadmap centers on more advanced SAP capacity, rapidly expanding factories, improved materials, and increased supply. Through the late 2020s, finer wiring, lower-loss ABF, lower-CTE materials, and better warpage control will enable organic substrates to stretch toward 110 mm and beyond. Around 2030, glass cores offer a path toward the 130 mm-plus packages that Ibiden and others already have on their roadmaps.

ASML, Intel, Samsung, and TSMC are teaming up to drive the industry transition to 6×12-inch photomasks (reticles). This shift is paramount for High-NA EUV lithography, as the larger stencil would enable printing large chips in a single pass, instead of having to stitch smaller designs together, as ASML explained in a press release this week.

This kind of collaboration between chipmakers isn't entirely unheard of, but it is rare. But when they face an industry-wide challenge, they set aside their rivalry and join forces to move the industry forward. This happened several times in recent decades, first with the failed transition to 450-mm wafers co-funded by GlobalFoundries, IBM, Intel, Samsung, TSMC, and New York State, then with the EUV transition, which was spearheaded by Intel, TSMC, and Samsung.

Higher resolution comes with a nuance

High-NA EUV lithography is a major step forward from today's Low-NA EUV tools. With a numerical aperture of 0.55, High-NA systems can achieve an 8nm single-exposure resolution, compared with 13nm for 0.33-NA EUV scanners. The higher resolution enables chipmakers to pattern smaller, denser features in a single exposure, replacing complex Low-NA EUV multipatterning schemes with a single High-NA exposure. This can reduce the number of masks and process steps, shorten manufacturing cycle times, and potentially improve pattern fidelity and yields, especially on critical layers of next-generation process technologies.

However, this improvement comes with a significant tradeoff. Conventional 0.33-NA EUV uses 4X reduction optics in both directions, which enables a 26×33 mm exposure field with standard 6×6-inch photomasks. By contrast, High-NA EUV uses 4X/8X anamorphic optics, so the same mask can only expose a 26×16.5 mm half-field, which is hardly a problem for client-oriented designs that are barely larger than 429 mm². However, large dies that fit within a conventional 26×33 mm EUV field must now be patterned using two High-NA exposures stitched together, or split into a multi-chiplet design.

Stitching is a workable near-term solution that all chipmakers, including Intel, Samsung, and TSMC, use, but it comes with multiple drawbacks. First, it reduces the throughput of ASML's Twinscan EXE:5200B scanner from up to 175 wafers per hour for half-field exposures to around 125 wafers per hour when stitching is used. Secondly, chip designers must account for the stitching boundary, which means additional design rules and reduced floor planning freedom.

Finally, the two exposures must be aligned with extreme precision so that features crossing the boundary connect properly. Even tiny alignment errors can distort lines and vias, or compromise interconnects and thus potentially create defects and lower yields. Such yield loss is very expensive in the context of large CPUs and GPUs produced using Low-NA EUV systems. If yield is lost on more expensive High-NA EUV tools, the costs will be even higher, which greatly lowers the appeal of using these scanners.

New photomasks are needed

To eliminate the need for stitching, the industry is exploring larger orthogonal 6×12-inch photomasks to compensate for anamorphic optics. By doubling the reticle dimension corresponding to High-NA's 8X reduction direction, these masks are set to restore the traditional 26×33 mm full exposure field and enable even reticle-sized dies to be patterned without stitching.

However, 6×6-inch photomasks have been an industry standard for around three decades since the 1990s. Even the transition from DUV to EUV did not change the basic mask dimensions: EUV replaced transmissive masks with reflective multilayer masks but retained the 6×6-inch substrate form factor. As a result, the adoption of 6×12-inch reticles would require the industry to change the entire mask-making, mask handling, and lithography infrastructure built around the existing format.

Mask-blank suppliers like AGC and Hoya would need new or modified equipment to produce larger substrates and deposit uniform reflective EUV multilayers across a much larger area. Mask shops would need new or modified writers and etch tools to pattern the larger masks, as well as inspection and metrology systems capable of precise characterization of the new format. Cleaning equipment, pellicles, and pellicle-mounting devices would also require modifications.

The mask handling infrastructure would have to change as well. Suppliers would need larger mask pods, while fabs and mask shops would require compatible storage, transport, and automated handling systems. At the same time, they would have to retain support for existing 6×6-inch masks since existing and future Low-NA EUV and DUV scanners will continue to use the established format.

Perhaps the biggest changes would be required from ASML. Its High-NA EUV scanners would need modifications or a redesign to accept, clamp, move, and position the substantially larger reticles with the extreme precision required for EUV lithography.

Intel, Micron, Samsung, SK hynix, TSMC, and other chipmakers planning to adopt High-NA EUV lithography would then have to qualify the new masks, scanners, and other tools for their process flows and ensure that the full-field exposure capability works as intended.

As a result, the adoption of 6×12-inch masks would require a coordinated effort and significant investments from chipmakers, ASML, mask makers, and numerous equipment and materials suppliers.

To make matters more complicated, 6×12-inch masks will not replace the existing 6×6-inch format altogether, as noted above. The industry would therefore have to manufacture, inspect, transport, store, and handle two mask formats in parallel, which will add cost and complexity to an already expensive transition.

Timeline

The transition to 6×12-inch reticles is an industry effort currently supported by ASML, Intel, Samsung, and TSMC. It is going to take years and will happen well after High-NA EUV enters high-volume manufacturing with today's 6×6-inch photomasks, as the semiconductor industry prefers to adopt new technologies gradually.

Intel already uses High-NA EUV scanner(s) for select Intel 18A layers (patterned at Fab D1X) and supports both floorplanning within the half-field and stitching; Samsung plans to introduce High-NA EUV into DRAM high-volume manufacturing by 2028, and TSMC intends to deploy the technology for advanced-node production starting in 2030. All three companies plan to start High-NA EUV adoption with 6×6-inch masks.

Intel seems to be leading the pack with 6×12-inch reticles as it has been working for three years to make them a reality, but the company remains tight-lipped about the timing of its adoption of the new photomasks. Meanwhile, the ASML-TSMC initiative targets a 6×12-inch photomask pilot line by 2031, which should provide the foundry with a platform to develop and qualify the new mask format and associated manufacturing infrastructure. The ultimate target is full lithography-system readiness for advanced-node production by 2033.

That said, 6×6-inch and 6×12-inch photomasks for High-NA EUV patterning will likely co-exist on the market at least for some time rather than undergo an abrupt transition. At the end of the day, square 6×6-inch reticles that enable High-NA EUV scanners to expose fields as large as 26×16.5 mm (or 429 mm²) should be sufficient for the vast majority of client processors produced in the coming years. Larger 6×12-inch masks will matter primarily for much bigger designs, such as high-end AI accelerators, data center CPUs, DPUs, high-end GPUs, and FPGAs, where the ability to expose a full 26×33 mm field without stitching becomes considerably more valuable.

For years, TSMC has tried to avoid making public comments about its plans to use EUV lithography with a 0.55 numerical aperture optics, or High-NA EUV, because the company's developers had a good idea how to keep advancing process technologies without using $400 million scanners. However, TSMC cannot rely on Low-NA EUV systems forever, so this week the company announced plans to use High-NA EUV starting from 2030.

TSMC did not formally reveal which fabrication technology will be the first to adopt High-NA EUV, though the year 2030 points to a few candidates. What TSMC did say is that it expects the number of layers processed using High-NA EUV to eventually increase as its fabrication technologies become more complex, driven by increasing complexity of transistor architectures, which is probably an implication for more sophisticated implementations of gate-all-around (GAA) transistors as well as complementary field-effect transistors (CFETs) later on.

TSMC plans to start using High-NA EUV lithography tools for high-volume manufacturing in 2030 using conventional 6×6-inch photomasks. The company then plans to build a pilot line that uses 6×12-inch photomasks in 2031 with the goal of bringing 6×12-inch High-NA lithography systems into advanced node production by 2033.

High-NA EUV lithography tools can achieve an 8nm single-exposure resolution, as opposed to a 13nm single-exposure resolution offered by today's Low-NA EUV litho systems. However, when used with conventional 6×6-inch photomasks, High-NA EUV scanners have only half the exposure field of their Low-NA counterparts, which creates challenges for manufacturing very large dies. As a result, chipmakers building massive AI accelerators must either stitch multiple exposure fields together or adopt multi-chiplet designs, two approaches that have their own other challenges, such as tool productivity and power consumption. To circumvent the 6×6-inch photomask limitations, TSMC is working with ASML to set the stage for 6×12-inch photomasks.

Changing the size of photomasks is not a trivial endeavor as it requires changing everything from EDA software to tools that produce and write masks as well as systems that handle them, which essentially means that the entire industry must work on this change. ASML seems to be optimistic about the transition as it is supported not only by Intel and TSMC, but also by Samsung.

"We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips," said Christophe Fouquet, president & CEO, ASML. "We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative."

Perhaps the biggest intrigue about TSMC's usage of High-NA EUV lithography is which process technology will be the first to use the new systems. Based on what we know about TSMC's roadmap, A10 or A11 (1/1.1nm-class) seems to be by far the strongest candidates to use High-NA EUV scanners for the most critical layers. TSMC's latest strategy separates its roadmap into annual client-oriented nodes (N2, N2P, N2X, A14, A13) and roughly biennial high-performance nodes (A16 in 2027, then A12 in 2029). The company has already confirmed that A12 and A13, due in 2029, will continue to rely on conventional EUV lithography.

Since A13 is an optical shrink of A14 that increases transistor density by only 6%, with performance and power improvements yet to be disclosed, its successor in 2030 will likely have to deliver considerably more substantial gains. It is therefore reasonable to expect A13’s successor — whether it is called A11 or A10 — to adopt more advanced lithography and/or TSMC's 3^rd Generation nanosheet GAA transistors to deliver significantly higher transistor density as well as meaningful performance and power improvements over its predecessor. Yet, we are of course speculating.

A 52-year-old Belgian-Chinese man has been arrested on suspicion of espionage for allegedly transferring specialized semiconductor intellectual property and trade secrets from Belgian chipmaker BelGaN, where he worked, to China. According to an AP News report citing details released by Belgium's federal prosecutor’s office on September 7, the Beijing-born Belgian resident was taken into custody on May 10 at a Brussels airport while attempting to board a flight to China.

The suspect — identified by Belgian media only as H.L. — previously held a senior research position at the now-defunct BelGaN, which specialized in gallium nitride (GaN) semiconductors. Investigators suspect he was concurrently leading a Chinese chip firm, GanKool, which was developing the exact same specialized gallium nitride chip technology as BelGaN. The company was established only a few months after H.L. joined BelGaN and was financed by a Chinese investment fund. The suspect now faces charges of industrial espionage, membership in a criminal organization, misuse of company assets, and unlawful disclosure of business secrets.

The espionage allegations emerged from an investigation into BelGaN's collapse. When the company collapsed into bankruptcy in the summer of 2024, Belgian authorities launched a routine financial probe into the failure. Investigators eventually uncovered highly unusual corporate activity. Instead of trying to keep BelGaN financially viable, the managers and the researcher may have actively tried to make the Belgian company “disappear” after transferring its proprietary knowledge. This led to further investigations that revealed GanKool’s existence and its connections to BelGaN.

In addition to the researcher’s role, the investigators also found evidence linking BelGaN's last CEO, a Chinese national, to the same Chinese rival. The prosecutors have said a second suspect remains at large, with Belgian media speculating that the CEO is the suspect.

The incident highlights the increasingly intense competition over technology and intellectual property in the semiconductor industry, particularly as China pushes to reduce its reliance on foreign chip technology while the U.S. continues to restrict its access to advanced processors and semiconductor manufacturing equipment. Just last month, South Korean court documents accused Chinese memory maker CXMT of using a detailed “Project Hefei” roadmap to obtain Samsung's proprietary DRAM technology, including a 620-step process recipe. A former Samsung engineer has already been sentenced to seven years in prison over the scheme.

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.

One million High-NA wafers

Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.

Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.

Sticking to stitching

Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.

Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.

6×12 mask effort progressing

To avoid using stitching, the industry — led by Intel — plans to shift to larger 6×12 masks, which will enable a 26×33 mm full field in one exposure. While this looks easy on paper, make the mask twice as long, changing the mask represents an enormous ecosystem change.

Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.

It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.

Being the world's largest contract chipmaker has its advantages for TSMC when it comes to negotiations with suppliers, as it naturally buys far more than others. However, it also has its difficulties because its requirements are dramatically larger than those of other foundries, and when they grow further, it gets exceedingly hard to source what it needs. Especially when its requirements increase nearly 2X in less than a year.

TSMC has nearly doubled its projected requirements for semiconductor production equipment since the end of last year as the foundry expands manufacturing capacity to address surging demand from the AI sector, said Cliff Hou, TSMC's deputy co-chief operating officer, during a fireside chat at Semicon Taiwan, reports FocusTaiwan. The world's largest foundry admits that it cannot meet all demand from all customers, though it is trying to catch up, according to Bloomberg.

TSMC makes projections about the number of tools it needs to purchase over the following year as well as its spending. After making that assessment late last year, the company discovered that by the end of the first quarter, the requirement had increased to 1.5 times that projection, and by July it had climbed to 1.9 times the original estimate, which means that TSMC's equipment needs had almost doubled in about six months.

TSMC itself attributes its increased needs to the number of new fabs that it is building in Taiwan and the U.S., though it should be noted that in addition to brand-new fabs, the company is also upgrading existing ones, which also need new machinery.

Interestingly, tool count does not seem to be proportional to tool cost. While TSMC increased its 2026 capital expenditure (CapEx) budget significantly in the recent eight months, it increased nowhere near 90%. Back in January, it guided 2026 CapEx to be from $52 billion to $56 billion. By April, it moved its estimate towards the high end of the original guidance, but in July it officially increased it to the range between $60 billion and $64 billion, or by around 15% if we only consider midpoints.

How exactly TSMC makes assessments about the number of tools it needs to buy the following year is something that remains to be seen, but perhaps a more pressing question for the industry is how it plans to acquire that equipment considering shortages of wafer fab tools due to massive demand from virtually all chipmakers.

Hybrid bonding, the copper-to-copper joining technique that replaces solder microbumps in 3D chip stacks, is in high-volume production on logic chips and has just been postponed for use with memory. TSMC has scaled its SoIC bond pitch from 9 microns to 6 and laid out a path to 4.5 by 2029; Intel began shipping Foveros Direct hybrid bonding in its Clearwater Forest server CPU in the first half of 2026, and AMD has used the technology in volume since the first 3D V-Cache parts. However, a JEDEC decision earlier this year to raise the HBM stack-height limit lets HBM4 stay on the less sophisticated and expense microbump technology, deferring hybrid bonding's arrival in high-bandwidth memory, and is now set to debut in HBM4E and HBM5 at the end of the decade.

The technique works by polishing two dies flat, then bonding their copper pads and surrounding dielectric directly under heat and pressure, with no solder bump in between. Because there’s no bump to collapse, the connections can be packed far tighter. AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking, and figures presented at TSMC's 2026 technology symposium put face-to-face hybrid bonding at around 14,000 signals per square millimeter against roughly 1,500 for face-to-back through-silicon-via stacking.

Wafer-to-wafer, die-to-wafer, and throughput

Microbumps have historically run at pitches around 40 microns, tightening toward 10 for the latest memory. Hybrid bonding, however, starts where microbumps end and keeps scaling: the leading edge is at 6 microns now, with 4.5- and 3-micron generations in development and sub-micron pitches demonstrated in research. Each step down multiplies the number of vertical connections between stacked dies, allowing a cache die or a compute tile to behave as if it were part of the chip rather than a separate component wired across a package.

The method is split into two different approaches: wafer-to-wafer and die-to-wafer. Wafer-to-wafer bonding joins two full patterned wafers face-to-face and dices them afterward, which allows the tightest pitch and fastest production because alignment happens once at the wafer scale. Imec and EV Group demonstrated a 200-nanometer wafer-to-wafer pitch with post-bond overlay below 40 nanometers at ECTC in May. The constraint here is that both wafers must carry identically sized dies, and every die gets bonded, including defective ones, so a single bad die on either wafer ruins the pair.

In contrast, die-to-wafer bonding places individual, pre-tested dies onto a wafer — which is what chiplet and HBM stacks require — because it allows known-good-die selection and the mixing of different die sizes and process nodes. There’s a penalty in terms of throughput with die-to-wafer as each die is picked, aligned, and placed in sequence rather than in one wafer-scale step.

The best die-to-wafer pitch shown at ECTC 2026, from CEA-Leti, was 1 micron, roughly five times looser than the wafer-to-wafer record. Because the dies are placed one at a time, the speed the bonder runs at sets the limit on how many chips it can produce. Applied Materials and Besi cite around 1,600 die placements per hour on the Kinex platform, and Besi's Chameo bonders are rated near 2,000 chips per hour, with the next generation aiming for 50-nanometer placement accuracy to reach finer pitches.

Hybrid bonding is difficult to achieve, as two surfaces have to be almost perfectly flat and clean. The dielectric holds on contact through van der Waals forces, so the polished surface can vary by no more than around 0.2 nanometers, and the copper pads have to sit a few nanometers below it, close enough that they swell into contact when the stack is heated to 200 to 300℃. A single particle smaller than a micron holds the surfaces apart and leaves a gap spanning many pads at once. So keeping the wafer clean and flat through the polishing step (known as chemical-mechanical planarization) is critical for good yields.

TSMC SoIC and Intel Foveros Direct

In terms of who’s leading hybrid bonding, TSMC’s System on Integrated Chips (SoIC) platform leads in terms of volume. At its 2026 North American Technology Symposium, the company laid out a pitch roadmap moving from 9 microns in 2023 to 6 microns in 2025 and 4.5 microns by 2029, with second-gen SoIC adding face-to-face bonding on top of the face-to-back stacking that the first generation supported. The node-stacking roadmap runs in parallel, from N3P-on-N4 today toward N2P-on-N2P by 2028 and A14-on-A14 by 2029.

With SoIC, the hybrid-bonded stack is built first as a vertical block, then placed into a CoWoS module alongside HBM on a silicon interposer, a combination the industry calls 3.5D. AMD's MI300 is the reference case, stacking compute and I/O dies by hybrid bonding before the assembly is mounted in CoWoS with its memory. SoIC handles the front-end vertical density; CoWoS handles the back-end lateral integration with memory.

Capacity is slowly growing, with TSMC building out its Chiayi AP7 site as its largest advanced-packaging campus. Output is targeted for 2026, and analysts at TrendForce have estimated SoIC capacity roughly doubling year on year from a few thousand wafers a month in 2024. Customers include AMD, whose 3D V-Cache and MI300 accelerators were the first volume SoIC products, and the Broadcom-built Fujitsu Monaka CPU.

Meanwhile, Intel's hybrid-bonding implementation, Foveros Direct, reached high volume with Clearwater Forest, the Xeon 6+ server processor built on the 18A node and demo’d at MWC back in March. The design uses a 9-micron copper-to-copper pitch to bond compute and I/O tiles onto base tiles that act as an active interposer, and Intel has described a second generation targeting a 3-micron pitch. Enabling that on a leading-edge logic node required a dedicated process variant, 18A-PT, which adds the through-silicon vias (TSVs) and bonding support that standard 18A doesn’t carry. The shift from Intel's earlier Foveros, which used solder microbumps across the Ponte Vecchio GPU's chiplets, to direct copper bonding is a generational change now playing out across its server offerings.

The unexpected HBM delay

The widely held assumption was that HBM, the stacked DRAM that sits beside every AI accelerator, would be hybrid bonding's largest market by volume. That changed back in January when JEDEC raised the HBM package height limit from 720 to 775 microns, and the extra room means 16-high HBM4 stacks can be assembled with microbumps after all. With HBM4 pad pitch at 10 microns, reporting from SemiEngineering noted that moving to hybrid bonding at that pitch wouldn’t yet make economic sense.

SK hynix has reflected that logic in its own planning, reportedly sticking with advanced mass-reflow molded underfill for 16-high HBM4 while keeping hybrid bonding as a backup and continuing to validate 12-high hybrid-bonded samples for later generations. The company demonstrated a 16-layer HBM4 sample at CES 2026, built without the all-hybrid bonding many expected the generation to require. The result pushes hybrid bonding's HBM debut toward HBM4E and HBM5, expected around 2027 to the end of the decade, where taller stacks and tighter pitches finally make the older bonding methods run out of room.

Meanwhile, the memory makers are building the packaging capacity regardless. SK hynix is investing $3.87 billion in an advanced-packaging plant in Indiana, with production targeted for 2028, and Micron broke ground on a $7 billion HBM advanced-packaging facility in Singapore early last year, with output expected around 2027. Those plants are sized for the volumes hybrid bonding will eventually carry, even as the first HBM4 generation ships on the older interconnect, meaning the equipment commitments are running ahead of the technology's confirmed deployment date in memory.

Samsung is doing the same thing from the memory side. Its SAINT packaging family includes SAINT-D, which stacks DRAM directly on a logic die, and the company has discussed a bufferless HBM4 design that removes the separate base die, with custom HBM logic dies reportedly moving to its 2nm foundry process for 2027 samples. At GTC in March, Samsung claimed hybrid bonding cuts thermal resistance by more than 20% against thermocompression bonding.

Another drag on the timeline is intellectual property. Adeia, which holds a large portfolio of bonding patents, sued AMD last year, alleging that the hybrid bonding behind 3D V-Cache infringes 10 of its patents.

China is pursuing the technique as a way around its lack of access to cutting-edge lithography. With SMIC limited to 14nm-class production and cut off from next-gen EUV, domestic researchers have identified 3D hybrid bonding as a route to competitive performance by stacking older logic and DRAM, with public claims of 14nm parts paired with domestic DRAM aimed at rivaling far newer GPUs. Given that it’s China we’re talking about here, those claims remain claims, and no foundry has demonstrated mass production of hybrid-bonded logic memory in China.

A scramble for tools

In terms of tooling, Applied Materials and Besi, partners on hybrid-bonding equipment since 2020, launched their Kinex die-to-wafer bonding system late last year, billed as the first fully integrated die-to-wafer hybrid bonder combining surface preparation, bonding, and metrology. Applied Materials has taken an equity stake in Besi, and reports from March placed Besi at the center of takeover interest from both Lam Research and Applied Materials, an indication of how important the bonding-tool market has become as logic adoption ramps and memory adoption is staged behind it.

Analyst tracking put Besi’s hybrid-bonding revenue on a path toward roughly €476 million by 2026, up from about €36 million in 2023, with second-half 2025 orders rising more than 60% against the first half on early HBM4 production-line bookings. Competing tool vendors are moving in alongside it: ASMPT has partnered with EV Group on hybrid bonding, and SK hynix is working with Hanwha Semitech on bonders targeting a commercial HBM launch in 2027. The sheer scale of this equipment build-out is a clear demonstration that the industry is treating hybrid bonding as an inevitability, even where the products that’ll use it are still years out.

Hybrid bonding is already in volume production, but its capability is outpacing its adoption. TSMC offers 6-micron pitch while its newest disclosed customer ships at 9; Intel ships at 9 with 3 on the roadmap; and the memory market that was meant to consume it in quantity has bought itself one more generation on microbumps. Two things will show where it goes next — whether any leading logic product drops below 9 microns in volume, and whether HBM4E marks hybrid bonding's first real use in memory before the end of the decade.

China's ability to produce lithography tools is comparable to that of market leader ASML sometime in 2004, an analyst with UBS wrote in a note to clients. The situation may change in the next two or five years when Chinese companies start producing immersion DUV lithography systems in mass quantities, and Chinese chipmakers begin to deploy them for production of actual chips. However, China's semiconductor industry will remain well behind Western industry. "They seem to be at a similar stage to ASML in 2004," wrote Francois-Xavier Bouvignies, an analyst with UBS, in a note for clients, reports Bloomberg.

For years, China's pursuit of semiconductor self-sufficiency stemmed from its ability to produce mainstream chips on trailing nodes using fairly advanced, though not the latest, tools from leading producers such as ASML, KLA, and Lam Research. In recent years, China found itself in a new reality in which it could no longer obtain the latest chipmaking tools and had to build them domestically. Although companies like ACM Research, AMEC, and Naura have developed world-class chemical wafer deposition, cleaning, etching, and oxidation/diffusion tools that are now mass-produced and used by Chinese chipmakers, none of the Chinese companies have managed to develop a competitive lithography machine that can be used to make chips on more or less modern nodes and initiate its mass production.

Photolithography is generally considered the most technologically complex and demanding individual process in advanced semiconductor manufacturing. Firstly, lithography systems themselves are extraordinarily complex and contain tens of thousands of individual components. Secondly, the required positional accuracy is extraordinary, as a modern lithography scanner needs excellent resolution, overlay, focus control, scanner-to-scanner matching, CD uniformity, and line edge roughness, just to name some of the requirements. Finally, a competitive litho system must guarantee predictable uptime, defect density, and performance. Perhaps the key thing here is that all of the required features must be achieved without compromises, as, for example, a machine with high resolution and ideal uniformity that can process one wafer per hour cannot be used for mass production.

Historically, over a dozen companies produced lithography tools. However, as they became more complex, only ASML, Canon, and Nikon survived, with ASML being the undisputed market leader and the only maker of EUV lithography scanners.

As China is essentially developing a parallel semiconductor ecosystem, there have been reports of multiple entities working on lithography systems, including Shanghai Micro Electronics Equipment (SMEE), AMIES (which seems to be a SMEE spin-off that includes Aishengna and Yuliangsheng units), SiCarrier (reportedly controlled by Huawei), and even Naura (which denies that it is developing litho tools). SMEE, which was established in 2002, is by far the most important established Chinese manufacturer of litho tools. Meanwhile, so far none of China-based makers of lithography have established mass production of immersion DUV scanners capable of producing chips at 45nm and below.

SMEE reportedly formally introduced its first immersion DUV lithography system called SSA/800-10W and capable of making chips on nodes down to 28nm back in 2023. However, there have been no evidence that SMEE has indeed started mass production of the SSA/800-10W and that it has been adopted by a single manufacturer for mass production of chips. While it is conceivable that not all chipmakers announce deployment of breakthrough tools, especially keeping in mind that Chinese vendors like SMEE have plenty of foreign suppliers, we would have seen at least some indirect evidence (starting from procurement/acceptance records as well as component orders all the way to job postings and scientific papers) that SMEE started shipments of the SSA/800-10W in 2023 – 2024 by now, assuming of course that there were any shipments.

Interestingly, but the reports about China-made immersion DUV scanners now mass-produced by Shanghai Aishengna Electronic Technology Group (a unit, or an affiliate of SMEE) re-emerged this July, again, without any evidence. This time around, the reports did not even mention targeted nodes or throughput capabilities. To make matters even more suspicious is the lack of reports about shipments of evaluation tools to chipmakers (like ASML does this with its High-NA EUV machines) as well as preliminary results of their process qualifications (like Intel does with ASML's High-NA EUV machines).

For a first-ever Chinese immersion scanner, it is reasonable to expect Chinese chipmakers to use it on engineering wafers, characterize it against ASML machines, develop recipes, identify drawbacks, and pass that information back to SMEE, something that should take about a year. Only once that first machine performs adequately does it make sense to order and qualify multiple SSA/800-10W units for mass production. In fact, such qualification will likely take another year for a single layer and more time for additional layers. To that end, an insertion of an all-new lithography scanner into an existing flow will take at least two years, but likely more. To that end, once SMEE (or its business units) and its customers figure out how the first Chinese immersion scanner should work, these scanners will still be far from mass deployment.

In any case, without any real indicators that Chinese makers of wafer fab tools can produce and ship immersion lithography scanners to customers, we can only state what the UBS analyst did: China's lithography industry is in a position where ASML was in the mid-2000s.

Samsung has unveiled a three-phase roadmap to progressively transform high-bandwidth memory (HBM) into an integrated memory-and-compute system, culminating in the company's zHBM architecture, which places the processor directly beneath the DRAM stack and eliminates the conventional 2.5D interposer link between the two. Detailing the roadmap at Hot Chips 2026, Samsung's Sangwook Han, of the company's DRAM design team, identified the base die as the key enabler of the evolution, which began with the company’s decision to manufacture the HBM base die on an advanced logic process.

In conventional HBM, the base die (B-die) was fabricated on the same DRAM process node as the core dies (C-dies) in the stack above. Starting with HBM4, Samsung moved the base die to a 4nm logic process, primarily to reduce power draw and minimize die area. Additionally, it gave Samsung a much more capable piece of silicon.

The company contends that a die built on the same class of logic process as XPUs could do much more than serve as a data interface. Samsung now plans to progressively offload more functions into the base die, eventually removing the physical gap between memory and the XPU entirely.

The current state of HBM and its growing constraints

The current HBM architecture comprises multiple DRAM core dies stacked vertically on a base die and connected through thousands of TSVs. The stack sits beside an XPU on an interposer, with the base die bridging the memory and compute silicon.

Bandwidth has been the main driver of HBM’s evolution. The current HBM4 stack has roughly 1 to 5 TB/s of bandwidth obtained through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each. These figures are expected to rise with upcoming HBM generations. The problem is that conventional ways of scaling bandwidth present significant challenges.

TSV signaling speed is difficult to increase, so HBM generations have added more TSVs instead. However, this consumes area and forces tighter TSV pitches. The PHY has also grown more demanding. HBM4 doubled the data I/O count from 1,024 to 2,048 DQs, and signaling speed keeps rising. Power is an even bigger issue. While energy per bit is improving, total HBM power continues to rise as bandwidth is scaling faster. Samsung says this is why HBM4 moves the base die to an advanced logic process, as the denser, more efficient logic reduces power draw.

This move underpins and enables the three-phase plan. An advanced logic node shrinks the interface circuitry while enabling the HBM base die to perform functions previously handled by the processor. Samsung calls this direction custom HBM, or cHBM, which keeps the conventional DRAM stack but customizes the logic underneath it for a specific accelerator.

Phase 1: Reclaim XPU area

The first phase is about handing processor area back to compute in what Samsung calls “XPU area reclamation.” AI accelerators are hitting familiar scaling walls, such as slowing process scaling and dies pressing against reticle and interposer limits. To expand compute, Samsung plans to evict non-compute blocks, moving their functions to the base die’s underutilized silicon.

The first target is the HBM Physical Interface (PHY), one of the largest blocks on the base die. Samsung proposes replacing the traditional interface with a much smaller die-to-die (D2D) link. On an 11 × 12.8mm HBM4 base die, the conventional PHY occupies more than 8 × 4mm, while the custom HBM D2D block is about 8.5 × 1.5mm, with channel depth cut from 5.5mm to 2mm. Because the matching interface on the XPU shrinks too, Samsung also reclaims processor silicon.

Conversely, shrinking the same power into less silicon increases power density and creates hotspots. Samsung’s answer is a Heat Path Block (HPB) that provides an alternative route for heat to exit the concentrated interface region. The company says an HPB covering more than half of the PHY can slash peak temperature by more than 35%.

The bigger Phase 1 change is moving the memory controller from the XPU to the custom HBM base die. Han estimated controllers account for 5 to 10% of an XPU's area — space that, refilled with compute, could yield a 10–20% performance gain. Moving the controller next to memory also enables a new SRAM-based repair scheme in which failed C-die addresses can be redirected to SRAM on the base die, avoiding the need to sacrifice an entire spare row or column for a single defective cell.

Phase 2: Making the die a more useful smart memory subsystem

Even with the controller moved in, Samsung says a substantial portion of the base-die area remains unused. Phase 2 fills that space with more functions, first with some relatively straightforward additions. The company proposes SoC-like telemetry and reliability features, including thermal, voltage, process, and aging sensors, as well as more advanced self-test hardware.

It also wants to use the edge of the base die for direct memory expansion, arguing that capacity is becoming as important as bandwidth. Dedicated controllers and PHYs could connect a secondary tier of external memory directly to custom HBM, rather than going through conventional PCIe expansion. Han said that extra memory could be LPDDR or even HBM, offering higher bandwidth and lower latency than PCIe-based memory extension.

Last in Phase 2 is compute — right on the base die. Samsung wants to place selected processing elements (PEs) under the DRAM, offloading memory-bound work while compute-heavy operations remain on the GPU. It calls this broader 2.5D architecture advanced HBM (aHBM), citing benefits such as less traffic across the interposer and reduced latency and I/O power draw.

Phase 3: zHBM goes fully 3D, placing the processor underneath the memory

Phase 3 appears to be Samsung's most radical step, with the company halting HBM architecture optimization and rebuilding it instead. Introducing zHBM, Samsung's “ultimate solution” for maximizing bandwidth under future AI's brutal power limits.

The zHBM concept eliminates the conventional side-by-side arrangement of XPU and HBM across an interposer. Instead, the processor sits directly beneath the DRAM stack in a true 3D structure. This architecture allows Samsung to replace the large edge PHY with distributed I/Os spread across the die. Data no longer has to travel laterally across an interposer, thereby shortening the physical path and eliminating the need for conventional HBM PHY and D2D link interfaces.

Samsung says the biggest payoff is power. Its projections show zHBM cutting I/O power by around 70% compared with HBM5. In another example, Samsung models roughly 2.3X more DRAM bandwidth while reducing memory power by about 100W compared to a four-stack HBM4E system.

On the flip side, thermals are the obvious complication. Han said Samsung is targeting roughly four-high zHBM stacks, compared with the much taller 12-high or 16-high configurations possible with conventional HBM, specifically because of heat. Distributed I/O helps by spreading the circuitry rather than concentrating it into hotspots, but zHBM is a balancing act involving capacity, bandwidth, heat, and physical integration.

Manufacturing zHBM will also require advanced wafer-on-wafer bonding and hybrid copper bonding to meet the required I/O density, with a much tighter co-design process between the DRAM and SoC teams. Samsung did not provide a firm launch date or timeline for the phases. However, HBM4’s 4nm logic base die is the concrete starting point, while cHBM and aHBM are nearer-term extensions, with zHBM as the long-term endpoint.

A team of scientists in Germany and Japan has demonstrated a solid-state cooling system that uses heat to generate the mechanical work required for refrigeration, potentially opening a route to processors and data centers that recycle some of their own waste heat for cooling. Developed by researchers at the Karlsruhe Institute of Technology (KIT) and the University of Tsukuba, the system — detailed in Nature Energy on August 28 — replaces the electrically powered actuator normally required for elastocaloric cooling with a heat-responsive shape-memory alloy, allowing the cooling cycle to run from an external heat source rather than a motor.

The prototype combines two ultra-thin metal films that serve as an actuator and a refrigerant. A 22-micrometer titanium-nickel (TiNi) shape-memory film contracts when heated, converting thermal energy into mechanical motion. This motion stretches and releases a 26.5-micrometer titanium-nickel-iron (TiNiFe) refrigerant film, triggering a reversible phase transition that produces cooling. In laboratory tests, Joule heating the actuator to 86°C produced a 12.9 K temperature span across the refrigerant film — the difference between its hottest and coldest states during the cooling cycle — and a 4.0 K span across the assembled cooling device, measured between its hot and cold sides. When the researchers replaced the resistance heating with an external 130°C heat source, the prototype still maintained a 2.2 K device-level temperature span, demonstrating that an external thermal source could drive the cooling mechanism.

Conventional refrigeration and air conditioning systems mostly use vapor-compression cooling. A compressor raises the pressure and temperature of a refrigerant, which then dumps heat in a condenser before expanding and evaporating at low pressure to absorb heat from the space being cooled. The technology is mature and efficient, but requires an electrically driven compressor and relies on refrigerants with significant global warming potential.

Solid-state cooling moves heat without the conventional compressor-and-refrigerant loop. Thermoelectric coolers, for example, use electrical current to create a temperature difference across semiconductor materials and are already common in compact electronics. However, the researchers note that thermoelectric devices typically reach only 10% to 15% of the theoretical reversed-Carnot efficiency limit, roughly one-quarter that of modern vapor-compression systems.

Elastocaloric cooling takes a different route. Certain shape-memory alloys change crystal structure when mechanically loaded and unloaded. Applying stress induces a phase transition that releases latent heat and warms the material. Once that heat is rejected, releasing the load reverses the transition, causing the material to absorb heat and cool. The solid alloy effectively becomes the refrigerant.

The problem is that the material still has to be repeatedly stretched and released. Existing elastocaloric systems generally use motors, hydraulic systems, or electromechanical actuators to provide the required force, adding electrical consumption, bulk, and mechanical complexity — particularly troublesome for miniature coolers. Instead, the KIT-Tsukuba team made one shape-memory alloy drive another. Heating the TiNi actuator film causes it to recover its original shape and contract. Mechanically coupled to the TiNiFe refrigerant film, that contraction supplies the force required for the cooling cycle. As the actuator heats and cools, it loads and unloads the refrigerant without an electric motor.

Broken down further, the system works as follows: the researchers take a shape-memory alloy (TiNiFe refrigerant film) that cools when released after being stretched. Instead of using a mechanical system to repeatedly stretch and release that alloy, they use another shape-memory alloy (TiNi) that contracts when heated and mechanically couple it to its cooling counterpart. When the TiNi is heated, it contracts, stretching and “loading” the refrigerant film. Once the heat is removed, the TiNi relaxes, releasing the film and triggering the phase transition that causes it to cool. Under cyclic heating, the TiNi alloy therefore provides the repeated stretching and releasing motion the TiNiFe requires for elastocaloric cooling.

The thermal actuator delivered a force-to-displacement ratio of 14.5 N/mm, compared with 1.1 N/mm for a commercial electromechanical actuator the researchers used as a reference. The thin films also provide a high surface-to-volume ratio for rapid heat transfer. Under Joule-heated actuation, the integrated device reached a steady 4.0 K temperature span after 20 cycles and a specific cooling power of 4.43 W/g. When driven from the external heat source, those figures fell to 2.2 K and 3.32 W/g, respectively.

This external-heat result is the real proof of concept. While the technology is still an early-stage laboratory experiment, a scaled, perfected version could have interesting implications. Typically, the heat the system needs to operate is generated from electricity or another form of energy. However, an ideal scenario would be to repurpose existing waste heat — a setup already attainable in data centers. Therefore, the technology has the potential to cool processors using the heat they generate!

However, applying it as a data center cooling technology is far from the technology's current state. The prototype produced just 2.09 milliwatts of cooling power at zero temperature lift. That is nowhere near the heat loads of modern processors, much less AI accelerators or data-center racks. The researchers also cite relatively slow actuation, limited strain rate, and the current heat-exchanger geometry among the factors constraining performance. There also needs to be a way to make the heating cyclical.

The team is now working to connect multiple films in parallel to increase cooling capacity. Further progress will require scaling the active material, improving heat transfer and operating frequency, and proving long-term durability. For now, the researchers have demonstrated the underlying energy chain in which heat can be converted into mechanical motion, and that motion can be turned into useful cooling without an electric motor driving the refrigeration cycle.

Micron Taiwan faces a potential strike as support for this labor action is increasing among its workers. Local media reports that a preliminary survey showed 80% of the people involved support such a move, with its labor union demanding that the current bonus system be replaced with a profit-sharing scheme, similar to what SK hynix employees receive. Micron, alongside Samsung and SK hynix, have been raking in a lot of cash because of the AI-driven memory chip shortage, and its workers want a piece of the action.

“Unions say peers offer far higher profit-based bonuses, with Samsung paying out 10.5% of profits and SK Hynix 10%,” Dan Nystedt said on X. “Formal mediation talks are expected to begin by mid-September at the latest, a mandatory requirement before an official strike vote can be held under Taiwan law.”

Earlier this year, Samsung narrowly avoided a strike after it agreed to a deal that gave its foundry workers bonuses that could go as high as $400,000 per employee. It seems that Micron Taiwan’s labor union is following suit, especially as the company’s last earnings call reported a revenue of $41.46 billion and a net income of $28.24 billion, with its Cloud Memory Business Unit, which provides high-bandwidth memory (HBM) to data center customers, accounting for more than 33% of the total revenue.

It’s unclear if Micron workers from other parts of the world will be affected by any deal made in Taiwan, but 60% of its global production capacity is centered around the island, with most of its HBM output coming from its facilities there. With the two sides beginning talks in September, we have yet to see what kind of deal they will reach. But given how lucrative the data center boom has been for the memory industry and the precedent set by workers at Samsung and SK hynix, it’s likely that they will have comparable demands.

While we’re unsure how much bonuses the workers in Taiwan will get, it’s likely that management will negotiate as production disruptions could mean massive losses for the company. Nevertheless, it would also raise complications for workers in other countries, as it could build jealousy and resentment among other workers who will not be part of the bargain, similar to what some Samsung workers are experiencing with the recently closed labor deal.

Intel's confidence in its 14A (1.4nm-class) fabrication process is rising as defect density drops. The company's own design teams are at work developing products that will use the technology, while external customers are now asking about 14A volumes Intel can get them, according to David Zinsner, chief financial officer of Intel, who spoke at Deustche Bank's 2026 Technology Conference. The CFO went as far as saying that 14A is Intel's best process since 22nm technology from the 2010's. But while the comment is optimistic, there is a caveat.

"When you look at the defect density, 14A is tracking better than the target curve we had for 14A," Zinsner said at Deutsche Bank's 2026 Technology Conference. "It is also doing better than any of the previous nodes in terms of how quickly we are bringing down the defects. In fact, we have not seen this performance since 22nm, which is arguably one of the best nodes Intel has ever put out."

Intel intends to begin risk production of its own products on 14A fabrication process in the second half of 2027 and then initiate its high-volume manufacturing in 2028, so 14A is two years away from mass production. So, what Intel's CFO said at the conference is that at this point in 14A's development, its defect reduction trajectory looks at least as healthy as the trajectory of the company's exceptionally successful 22nm process at a comparable point in its development (i.e., in 2010). There are a couple of catches with such phrasing, though. Firstly, the defect density on 14A now is not necessarily equivalent to a defect density on 22nm two years away from mass production. Secondly, due to advances of wafer processing and inspection equipment, what Intel counts as a defect now may not be the same thing as what it counted as a defect 16 years ago. Furthermore, defect density itself does not directly equal product yield.

Intel's 22nm was the company's first manufacturing process to rely on FinFET transistors and at the time was the most advanced process technology in the world; the rest of the industry moved to FinFET devices only with their 14nm and 16nm-class nodes in 2014 and 2015. By contrast, 14A will use second-generation gate-all-around (GAA) RibbonFET transistors, second-generation backside power delivery called PowerDirect, and will be able to use High-NA EUV lithography due to extremely complex patterning. Keeping all of that in mind, Intel's claim that 14A defect density reduction is progressing unusually well this far ahead of HVM is certainly good news.

Meanwhile, comparing 14A to 22nm's successors should be quite comforting for Intel as 14nm mass production was delayed by a year due to insufficient yield, the first-generation 10nm node was a failure, 20A was cancelled, 18A defect density was high even as it hit HVM milestone, while the company did not share almost any information about the progress of its Intel 4 and Intel 3 nodes.

There are good signs for 14A though: external customers are already developing products for this node, whereas the interest from external customers is now practical rather than theoretical.

"We are now seeing demand from our internal customers on 14A [and] they are actually probably the most cynical bunch out of anybody," Zinsner said. "The fact that they are now designing products on 14A was a good confidence boost for us as well. Then, engagements with customers externally, from a foundry perspective has significantly increased. Lip-Bu and the team are now meeting on weekly basis with customers. They are moving away from just looking at data to thinking about 'how much capacity can I get?' 'what does that supply look like?' So, we are now at a point where we have conviction around customers on 14A externally as well."

Intel initiated mass production of its 22nm-based Ivy Bridge processors in late 2011 and early 2012 and released them commercially in late April 2012. The product was highly successful (though overclockers did not like it because of inefficient thermal interface material between the die and integrated heatspreader), and 22nm fabrication technology served the company for many years, first for CPUs in 2012 through 2016, then for other products. Intel's 14A also promises to be a long-lasting node for Intel.

Glass-core substrates, the replacement for organic chip packaging that Intel promised in September 2023 with more than $1 billion behind it, are now in final qualification. However, the product is still not in a single commercial product. SKC, a material manufacturer and chemical affiliate of the SK Group, said on its July 27 earnings call that embedded glass substrate samples from its Absolics plant in Covington, Georgia, are undergoing package-level reliability evaluation in Taiwan, with results possible before year-end.

Samsung Electro-Mechanics formalized a 482.1 billion won ($310 million) glass-core joint venture with Sumitomo Chemical's Dongwoo Fine-Chem on July 2, targeting first production in the second half of 2027. Intel, which started the race, has shifted to licensing its patents and showing demo vehicles, with its own deployment now pointed at around 2030. However, and rather predictably, every timeline in the segment has slipped. Absolics originally planned mass production for the first half of 2024, and reported claims that AMD would adopt glass substrates for CPUs between 2025 and 2026 have come and gone unfulfilled.

Why glass?

The technical case for glass core substrates leans heavily on numbers Intel published a while back, such as 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion. Glass cores can be tuned to a thermal expansion coefficient of roughly 3 to 10 ppm per degree Celsius against silicon's 2.6, which cuts warpage by about half compared with organic cores, and rectangular panels in the emerging 510mm x 515mm format use more than 75% of their area for large die against roughly 50% for round 300mm wafers. Through-glass vias have been demonstrated at six microns in diameter with aspect ratios beyond 15:1 at ECTC 2025, and Georgia Tech has shown stacked glass running at 220 GHz with 0.3 dB of loss.

Glass also chips and cracks at the edges during drilling and dicing, and MIT Technology Review reported in March that early Absolics production runs broke hundreds of panels every couple of days during early testing days. Edge-coating work has cut measured edge stress from 95 MPa to 49 MPa, and low-temperature dielectrics that cure below 180°C have been developed to reduce thermal stress during build-up, but metallizing vias below 10 microns and holding nanometer-scale flatness across half-meter panels remain open manufacturing problems.

Intel's program

Intel demonstrated a working system booting Windows on a glass-core substrate in early 2025, and Rahul Manepalli, Intel's VP of module engineering, told MIT Technology Review that the benefits of glass cores are "undeniable" and that Intel wants "to be one of the first ones who do it." The commercial plan around that engineering has changed shape, however. DigiTimes reported in late July that Intel is in early-stage talks with Chinese cover-glass maker Lens Technology about a packaging partnership, but there has been no solid agreement made to date.

At NEPCON Japan in January, Intel Foundry showed its first thick-core glass substrate with two EMIB bridge dies embedded directly in the glass: a 78mm x 77mm package with two 800-micron-class glass layers, 10 redistribution layers on each side, and around 1,716 mm2 of silicon on top, roughly two full reticles, with no micro-cracking reported in testing.

There’s currently no production time to this, however, with TrendForce placing Intel’s commercialization somewhere around 2030, alongside co-packaged optics prototypes built on glass at its Rio Rancho, New Mexico site. Meanwhile, Amkor, Intel's packaging partner on the optics work, put commercialization within three years at an industry event in Seoul in April.

Korea aiming for 2027

Samsung Electro-Mechanics moved its glass program from advanced R&D into a business-execution unit in February and has been sampling from a pilot line at its Sejong plant since late 2024. The GLASEM joint venture announced on July 2 splits ownership: 66% to Samsung Electro-Mechanics and 34% to Dongwoo Fine-Chem, with site production in Pyeongtaek, and targets an operating plant in the second half of 2027, with the joint venture making the drilled and metallized glass core that feeds Samsung's substrate line. Korean industry reporting says samples have gone to AMD and Broadcom, and also puts Samsung's overall glass maturity at 40 out of 100, a gap between marketing dates and process readiness worth keeping in mind.

Absolics' $600 million plant in Covington, Georgia, backed by $75 million in CHIPS Act funding plus a further $100 million through the government's advanced packaging R&D program with Georgia Tech, has a Phase 1 capacity of 12,000 m² of substrate per year, enough for roughly two to three million H100-sized packages. The company produced mass-production samples in the first quarter, began customer qualification that reportedly includes AMD and AWS, and is targeting mass production by the end of 2026. LG Innotek runs a third Korean program from its Gumi plant, with prototypes delivered in 2024 and production targeted for 2027 to 2028.

TSMC and Japan

TSMC's CoPoS line in Chiayi, built around 310mm x 310mm rectangular panels, received tools in February, completed its pilot line around June, and is aiming for pilot production in 2027, with mass production in the second half of 2028. Equipment supplier SCHMID has described glass integration in that platform as under review, not committed, and TrendForce puts TSMC's commercial-scale glass-core production after 2030, meaning that the industry's biggest packaging operation is going panel-level first and glass later, if at all. TSMC revived glass substrate research a couple of years ago after earlier deprioritizing it, reportedly under pressure from Nvidia, whose accelerator packages are the main thing outgrowing current packaging.

Japan’s Dai Nippon Printing began phased operation of a TGV glass-core pilot line at its Kuki plant in Saitama in December 2025 on 510mm x 515mm panels, with sample shipments from early 2026 and full mass production targeted for fiscal 2028. Toppan's pilot line for glass cores and interposers at its Ishikawa plant was scheduled for commissioning in July, and Nippon Electric Glass has scaled its ceramic-reinforced GC Core panel to 515mm x 510mm at 1mm thickness. Rapidus is studying panel-level packaging on 600mm x 600mm glass as part of its 2nm program, with viability put at the late 2020s. China has its own entrants, led by display maker BOE, whose pilot line is sampling.

TrendForce estimates Nvidia's Rubin Ultra package at roughly 7,470 mm², about nine reticles' worth of silicon and memory, against around 2,739 mm² for Blackwell, and CoWoS interposer wafers cost on the order of $10,000 each, comparable to a processed 7nm wafer.

Organic substrates warp and lose dimensional stability at those sizes, and round interposer wafers waste a growing share of their area, which is what glass panels are meant to fix. SEMI's first dedicated market report on glass cores, published in May with Global Net, projects initial production around 2028 in select high-performance applications and a 67.2% compound annual growth rate from 2028 to 2040, while Yole puts the advanced IC substrate market at $31 billion by 2030 with glass cores among the drivers.

At the moment, no production design exists, and all customers that have been named or otherwise attached to the tech, including AMD, Broadcom, AWS, and Nvidia, come from wider industry reporting. Nothing has been confirmed officially. As for whether we might see more substantial progress next year, Absolics will need to publish some solid package-level reliability results by the end of this year, or a first officially named customer at any of the Korean manufacturers. We also need to hear from TSMC on whether glass cores will go into CoPoS or remain under review into the 2030s.

The Environmental Protection Agency (EPA) has recently given two new chemicals approval for use within the U.S., but the non-profit organization Earthjustice is suing the agency for not doing its job. According to a lawsuit reported by The Guardian, these chemicals are photoacid generators used for semiconductor manufacturing, but they’re also quite toxic for humans. Exposure to them could allegedly lead to “sudden death,” as well as various health risks like cancer, eye corrosion, neurological damage, and reproductive harm. It is alleged that the approvals are "part of a broader pattern around data centers."

The current administration wants to bring semiconductor manufacturing back into the United States, with President Donald Trump issuing an executive order last year to fast-track the approval of chemicals needed for data centers. It’s unclear if these two chemicals are related to the order, but Atty. Jonathan Kalmuss-Katz, who works with Earthjustice, said that the EPA “does not know the level at which the chemicals are ‘acutely lethal’ or cause other serious health damage.” It also said that “the chemicals may present an ‘unreasonable risk’ to workers and the public.” Nevertheless, the agency allegedly approved them for import and use in the U.S. with minimal and non-protective restrictions.

“If a chemical may present an ‘unreasonable risk,’ then the Toxic Substances Control Act requires the EPA to ‘prohibit or limit the manufacture, processing, distribution in commerce, use, or disposal of such substance or to prohibit or limit any combination of such activities to the extent necessary to protect against an unreasonable risk,” Kalmuss-Katz told The Guardian. He also added, “This is turning the new chemical review process on its head. You have a situation where the EPA has failed at its most fundamental obligation when it comes to new chemicals, and that is to protect the public from unreasonable risk.” Aside from the health and environmental risks posed by the photoacid generators, these chemicals also appear to be PFAS or per- and polyfluoroalkyl substances. These are synthetic chemicals with unusually strong bonds that could last a long time, even if they’re exposed to the environment, which is why they’re often referred to as “forever chemicals.”

The semiconductor industry has long been known for its use of PFAS, and researchers are working hard to find ways to help clean up these chemicals used to make chips. So, the approval of new chemicals without rules and regulations that require them to be removed from discharges is potentially disastrous for the environment. This is the same concern that a lawsuit against Micron’s planned New York fab raises, which says that the approved wastewater and air permits that the company received could still allow these “forever chemicals” to leak into the Oneida River. Environmental groups acknowledge that domestic chip production requires the use of these potentially harmful chemicals, but the EPA must ensure that these do not find their way into the water system and that the people working with them are protected from exposure.