AMD said Friday that over the next five years it will invest approximately $400 million in India. The company will greatly expand its presence in the country and will open its largest design center in Bengaloru, India, already in 2023, reports Reuters. The significant investment indicates that the company may be planning to expand its product line-up in the coming years. 

AMD's new design center campus is set to open in Bengaluru, the country's tech hub, later this year and is expected to create 3,000 engineering jobs within the next five years. The company disclosed that its India teams will be crucial in developing its high-performance (CPUs and GPUs) and adaptive (FPGAs) solutions for its global clientele. With this new investment, AMD will expand its office presence in India to a total of 10 locations, where it already employs over 6,500 people.

In total, AMD is committed to invest $400 million in India by 2028, Mark Papermaster, AMD's chief technology officer, revealed at a semiconductor conference in Gujarat.

India is well known for its talented software developers, but in the last couple of decades it became a major hub for chip designs. Companies like AMD develop plenty of chips in the country and there are also numerous contract chip designers in India.

Establishing its largest design center and investing $400 million in India over the next five years indicates that AMD not only intends to capitalize on the country's potential as a chip design hub, but it plans to significantly expand its chip design design prowess going forward. Meanwhile, for now it is impossible to make guesses how exactly it intends to spend the money.

AMD's move aligns with the Indian government's efforts to attract investment in the semiconductor sector and solidify its position in the global chip industry.

It is noteworthy that last month AMD also announced plans to invest $135 million in its Xilinx FPGA operations in Ireland over the next four years.

Just like other large chip designers, AMD has already started to use artificial intelligence for designing chips. In fact, Lisa Su, chief executive of AMD, believes that eventually AI-enabled tools will dominate chip design as the complexity of modern processors is increasing exponentially.

Su, believes that AI will dominate certain areas of chip design, she said at the 2023 World Artificial Intelligence Conference (WAIC) held in Shanghai. She also emphasized the need for interdisciplinary collaboration to enable better hardware design in the future, reports DigiTimes.

Previously both Jensen Huang, chief executive of Nvidia, and Mark Papermaster, chief technology officer of AMD, noted that chip development is an ideal application for AI. AMD is already utilizing AI in semiconductor design, testing, and verification. The company also has the intention to leverage generative AI more broadly in future chip design applications.

At AMD, AI is already in chip design, particularly in the 'place and route' stage, where sub-blocks of chip designs are positioned and optimized for better performance and lower energy consumption, Papermaster told Tom's Hardware in May. AI's ability to continuously iterate and learn from patterns greatly accelerates the process of achieving an optimized layout, thereby increasing performance and energy efficiency. Papermaster said that AI will even expand into more important aspects of chip design, like microarchitecture designs, particularly after certain hurdles are overcome to protect IP.

AI is also already employed in verification suites to reduce the time needed to detect bugs during the chip's development process, from conception to the verification and validation phases. Furthermore, AI assists in generating test patterns. With billions of transistors in a chip design, ensuring comprehensive test coverage is essential to guarantee that the product is flawless upon leaving the manufacturing floor. AI's ability to learn from each successive run, identify gaps in test coverage, and adjust the testing focus accordingly, significantly speeds up the process and enhances test coverage.

Artificial intelligence (AI) is increasingly playing a pivotal role in supporting and assisting chip designs. All three leading makers of electronic design automation (EDA) tools — Ansys, Cadence, and Synopsys — offer AI-enabled software to their clients, although Synopsys seems to be a bit ahead of its competitors when it comes to AI-enabled tools.

Earlier this year Synopsys launched Synopsys.ai, the first end-to-end AI-driven EDA solution. This enables developers to use AI throughout all stages of chip development, from architecture to design and manufacturing.

During Computex 2023, I had a chance to visit AMD's towering offices in Taipei, Taiwan, to see the company's Ryzen AI demo and speak with David McAfee, the Corporate VP and GM of the Client Channel Business. Most of our conversation centered on AMD's efforts in the consumer AI space, but I also squeezed in a few questions about AMD's take on hybrid CPUs. McAfee told me AMD has a different vision of hybrid processors than Intel that would avoid the complexity that forced Intel to remove AVX-512 support from its chips. 

I interviewed AMD CTO Mark Papermaster two weeks ago in Antwerp, Belgium. He told me that we would "see high-performance cores mixed with power-efficient cores mixed with acceleration" in future AMD client [consumer] processors, signaling that, like Intel before it, AMD would adopt a hybrid CPU execution core design in the future. That wasn't too surprising -- we saw the first signs of two different CPU core types in AMD's software manuals months ago. Besides, AMD is already laying the foundation with its coming EPYC Bergamo chips with dense Zen 4c cores akin to efficiency cores.

AMD's current Ryzen 7040 laptop chips already feature a hybrid design, but not with two different types of CPU cores. Instead, the Ryzen 7040 has just one type of CPU core paired with an in-built AI accelerator engine that operates independently of the CPU and GPU cores. This engine provides advantages for certain types of AI inference workloads, but the CPU and GPU cores are better for other types of inference. So, the trick is to direct the different AI workloads to the correct type of cores to extract the best performance and power efficiency. 

Throwing separate performance and efficiency CPU cores into that mix would introduce yet another compute option for AI inference workloads, and I asked McAfee if, conceptually, it would be feasible that efficiency cores would be better for AI than a dedicated piece of silicon (the AI engine). McAfee explained that the AI engines' strict focus on AI-specific operations would give it an efficiency advantage over any general-purpose CPU compute -- even an efficiency core.

Then we shifted to discussing Intel's hybrid chips, which have two types of cores, each with its own unique microarchitecture. That's created interesting problems: Intel's performance cores support AVX-512, but the smaller efficiency cores do not. That led Intel to disable AVX-512 support entirely (forcibly in the end), thus de-featuring its own chip and wasting precious die area. 

I asked McAfee how AMD felt about that approach to hybrid designs. 

"What I will say is this, I think the way that we think about it, the approach of two very different performance and efficiency cores with very different ISA support and IPC and capability is not necessarily the right approach," McAfee responded. "I think it invites far more complexity around what can execute where, and as we've looked at different options for core design, that's not the approach that we're taking.

"I think as we roll more of this out over time, what you'll see from us is an approach that takes into consideration the advantages that different core targeting can provide, but doing it in a way that's much more, from an application perspective, much more homogeneous."

We already know that AMD's Zen 4C efficiency cores, which it will use in the upcoming Bergamo server chips, will support the same instructions, like AVX-512, as the full-featured performance cores. However, they'll have a cut-down cache hierarchy to reduce die area consumption. The goal of both core types having the same IPC with the performance and efficiency cores is important. In contrast, Intel's efficiency cores have lower IPC than its performance cores (that could result in tradeoffs in its other e-core aspirations, like Sierra Forest). 

"ISA, first of all, keeping that consistent to where a workload can operate on any core, has dramatic advantages," McAfee said. "And even when you look at a Ryzen desktop CPU today, the way that the Windows scheduler is plumbed, the ability to identify cores that are faster, slower, etc., and steer threads to different cores depending on the ranking or capability within a CPU; That's a well-established technique that we've used for quite some time. This then leads to, in our opinion, using a mechanism where the capability of the cores is more consistent.

"This is a far more tried and true way to look at bringing multiple different core targeting types into a design. I think the Intel approach invites a lot of complexity into the way that it operates. And I think our analysis has been that. I don't think you'll see us go down that path in the same way they have, if and when it comes to a Ryzen processor." McAfee concluded. 

Unlike Papermaster, McAfee was noncommital on if or when hybrid would come to Ryzen, and we don't know where AMD would first introduce a hybrid architecture with Ryzen, be it with a monolithic APU or one of its chiplet-based models. However, it is clear that AMD envisions a hybrid future that would avoid the tradeoffs we've seen with Intel's design decisions behind the Alder and Raptor Lake processors.

Some of AMD's own decisions might be informed by analyzing Intel's missteps, or it may have just been the common sense of IP reuse with the existing core architecture -- it's a far lighter lift to tweak a microarchitecture than embarking upon a clean-sheet design. In either case, the ability to preserve support for AVX-512 would likely give AMD the performance advantage in vectorized workloads, provided Intel doesn't follow suit. 

Conversely, one could argue that Intel's approach of having a separate microarchitecture tuned for lower-power operation is a better approach, albeit if it were paired with uniform ISA support across both types of cores. If Intel has corrected its ISA mismatch with Meteor Lake and maintained support for AVX-512 across both core types, it could also prove to be a potent combo.

In either case, it's clear that while AMD would be second to market with a hybrid design, it will take a much different approach. Only time will tell how the two techniques stack up in the benchmarks.

AMD's Instinct MI300 is shaping up to be an incredible chip with CPU and GPU cores and a hefty slab of high-speed memory brought together on the same processor, but details have remained slight. Now we've gathered some new details from an International Super Computing (ISC) 2023 presentation that outlines the coming two-exaflop El Capitan supercomputer that will be powered by the Instinct MI300. We also found other details in a keynote from AMD's CTO Mark Papermaster at ITF World 2023, a conference hosted by research giant imec (you can read our interview with Papermaster here).

The El Capitan supercomputer is poised to be the fastest in the world when it powers on in late 2023, taking the leadership position from the AMD-powered Frontier. AMD's powerful Instinct MI300 will power the machine, and new details include a topology map of a MI300 installation, pictures of AMD's Austin MI300 lab, and a picture of the new blades that will be employed in the El Capitan supercomputer. We'll also cover some of the other new developments around the El Capitan deployment.  

As a reminder, the Instinct MI300 is a data center APU that blends a total of 13 chiplets, many of them 3D-stacked, to create a single chip package with twenty-four Zen 4 CPU cores fused with a CDNA 3 graphics engine and eight stacks of HBM3 memory totaling 128GB. Overall the chip weighs in with 146 billion transistors, making it the largest chip AMD has pressed into production. The nine compute dies, a mix of 5nm CPUs and GPUs, are 3D-stacked atop four 6nm base dies that are active interposers that handle memory and I/O traffic, among other functions.

Papermaster's ITF World keynote focused on AMD's "30x25" goal of increasing power efficiency by 30x by 2025, and how computing is now being gated by power efficiency as Moore’s Law slows. Key to that initiative is the Instinct MI300, and much of its gains come from the simplified system topology you see above.

As you can see in the first slide, an Instinct MI250-powered node has separate CPUs and GPUs, with a single EPYC CPU in the middle to coordinate the workloads.

In contrast, the Instinct MI300 contains a built-in 24-core fourth-gen EPYC Genoa processor inside the package, thus removing a standalone CPU from the equation. However, the same overall topology remains, sans the standalone CPU, enabling a fully-connected all-to-all topology with four elements. This type of connection allows all of the processors to speak to each other directly without another CPU or GPU serving as an intermediary to relay data to the other elements, thus reducing latency and variability. That's a potential pain point with the MI250 topology. The MI300 topology map also indicates that each chip has three connections, just as we saw with MI250. Papermaster's slides also refer to the active interposers that form the base dies as the 'fourth-gen infinity fabric base die."

As you can see in the remainder of these slides, the MI300 has placed AMD on a clear path to exceeding its 30X25 efficiency goals while also outstripping the industry power trend. We also threw in a few pictures of the Instinct MI300 silicon we saw firsthand, but below we see how the MI300 looks inside an actual blade that will be installed in El Capitan.  

AMD Instinct MI300 in El Capitan

At ISC 2023, Bronis R. de Supinski, the CTO for the Lawrence Livermore National Laboratory (LLNL), spoke about integrating the Instinct MI300 APUs into the El Capitan supercomputer. The National Nuclear Security Administration (NNSA) will use El Capitan to further military uses of nuclear tech.

As you can see in the first image in the above album, Supinski showed a single blade for the El Capitan system. This blade, made by system vendor HPE, features four liquid-cooled Instinct MI300 cards in a slim 1U chassis. Supinksi also showed a picture of AMD's Austin lab, where they have working MI300 silicon, thus showing that the chips are real and already under testing — a key point to be made considering some of the recent missteps with Intel-powered systems.

Supinksi often referred to the MI300 as the "MI300A," but we aren't sure if that is a custom model for El Capitan or a more formal product number.

Supinski said the chip comes with an Infinity Cache but didn't specify the capacity available. Supinski also cited the importance of the single memory tier multiple times, noting how the unified memory space simplifies programming, as it reduces the complexities of data movement between different types of compute and different pools of memory.

Supinski notes that the MI300 can run in several different modes, but the primary mode consists of a single memory domain and NUMA domain, thus providing uniform access memory for all the CPU and GPU cores. The key takeaway is that the cache-coherent memory reduces data movement between the CPU and GPU, which often consumes more power than the computation itself, thus reducing latency and improving performance and power efficiency. Supinksi also says it was relatively easy to port code from the Sierra supercomputer to El Capitan.

The remainder of Supinski's slides includes information AMD has already disclosed, including performance projections of 8X the AI performance and 5X the performance-per-watt of the MI250X.

HPE is building the El Capitan system based on its Shasta architecture and Slingshot-11 networking interconnect. This is the same platform that powers both of the DOE's other exascale supercomputers, Frontier, the fastest supercomputer in the world, and the oft-delayed Aurora that's powered by Intel silicon.  

The NNSA had to build more infrastructure to operate the Sierra supercomputer and El Capitan simultaneously. That work included bolstering the power delivery dedicated to compute from 45 MW to 85 MW. An additional 15 MW of power is available for the cooling system, which has been upgraded to 28,000 tons by adding a new 18,000-ton cooling tower. That gives the site a total of 100 MW of power, but El Capitan is expected to consume under 40 MW, though the actual value could be around 30 MW — the final numbers won't be known until deployment.

El Capitan will be the first Advanced Technology System (ATS) that uses NNSA's custom Tri-lab Operating System Software (TOSS), a full software stack built on RHEL. 

El Capitan's Rabbit Program for Storage 

The LLNL is using smaller 'EAS3' systems to prove out the software that will be deployed on El Capitan when it becomes operational later this year. LLNL is already testing new Rabbit modules that will host a plethora of SSDs for near-node local storage. Above, you can see the block diagrams of these nodes, but be aware that they don't use the MI300 accelerators — instead, they have standard EPYC server processors for storage orchestration and data analytics tasks. These fast nodes appear to serve as burst buffers that absorb massive amounts of incoming data quickly, which will then be shuffled off to the slower bulk storage system.

AMD Instinct MI300 Timeline

With development continuing on a predictable cadence, it's clear that El Capitan is well underway to being operational later this year. The MI300 forges a new path for AMD's high-performance compute offerings, but AMD tells us these halo MI300 chips will be expensive and relatively rare -- these are not a high-volume product, so they won't see wide deployment like the EPYC Genoa data center CPUs. However, the tech will filter down to multiple variants in different form factors.

This chip will also vie with Nvidia's Grace Hopper Superchip, which is the combination of a Hopper GPU and the Grace CPU on the same board. These chips are expected to arrive this year. The Neoverse-based Grace CPUs support the Arm v9 instruction set, and systems come with two chips fused together with Nvidia's newly branded NVLink-C2C interconnect tech. In contrast, AMD's approach is designed to offer superior throughput and energy efficiency, as combining these devices into a single package typically enables higher throughput between the units than when connecting to two separate devices like Grace Hopper does.

The MI300 was also supposed to compete with Intel's Falcon Shores, a chip that was initially designed to feature a varying number of compute tiles with x86 cores, GPU cores, and memory in numerous possible configurations. Intel recently delayed them to 2025 and redefined the chips to feature a GPU and AI architecture only — they will now not feature CPU cores. In effect, that leaves Intel without a direct competitor for the Instinct MI300.

Given the rapidly approaching power-on date for El Capitan and AMD's reputation for getting supercomputers done on time, we can expect AMD to begin sharing much more information about its Instinct Mi300 APUs soon. AMD will host the company's Next-Generation Data Center and AI Technology livestream event on June 13, and we expect to learn more there. We'll be sure to bring you the latest from that event when it arrives. 

I met with AMD CTO Mark Papermaster on the sidelines of ITF World, a conference hosted by semiconductor research firm imec in Antwerp, Belgium, for an interview to discuss some of AMD’s plans for the future. The highlights of the interview include Papermaster’s new revelation that AMD will bring hybrid architectures to its lineup of consumer processors in the future, a first. These types of designs use larger cores designed for performance mixed in with smaller efficiency cores, much like Intel’s competing 13th-Gen chips. Papermaster also spoke about AMD’s current use of AI in its semiconductor design, testing, and verification phases, and about the challenges associated with the company’s plans to use generative AI more extensively for chip design in the future. We have the full conversation further below.

Mark Papermaster has served as AMD’s Chief Technical Officer (CTO) and SVP/EVP of Technology and Engineering since 2011. He's directed AMD's technology development for over a decade, laying the cornerstones of technology that powered the company’s resurgence against industry stalwart Intel, giving him incredible insight into the company's past, present, and future.

Imec’s ITF World 2023 conference featured a string of keynotes from powerful luminaries in the semiconductor industry, like AMD’s Mark Papermaster, Intel’s Ann Kelleher, Nvidia’s Jensen Huang, imec’s Luc Van de hove, and ASML’s Christophe Fouquet.

Papermaster’s presentation centered on the fact that computing is now being gated by power efficiency as Moore’s Law slows. We’ll cover that and many of the other highlights of the event over the coming days. First, here’s our interview with Papermaster before his keynote:

More Cores, With a New Twist

Paul Alcorn: I interviewed you back in 2019 at the Supercomputing conference and we talked about increasing CPU core counts. You said at the time that you see a runway for more cores, and that you don't see a saturation point in the foreseeable future. At the time AMD was at a peak of 64 cores [Rome data center chips], and now you're at 96 for Genoa. AMD was also at 16 cores for Ryzen [3000] for desktop PCs, and now you're still at 16 cores for Ryzen [5000] - so two generations of 16-core chips for client [PCs].

So now, today, do you still see a runway for more cores in data center chips? Additionally, do you see the need for more cores in the client space [PCs] now that it's at 16 cores? It's been two generations with 16, is that going to be a sweet spot moving forward?

Mark Papermaster: What you're going to see in PCs, as well as in the data center, is more bifurcation of tailored SKUs and processers coming out. Because it's really now where one size doesn't fit all; we're not even remotely close to that. You're going to have a set of applications that actually are just fine with today's core count configurations because certain software and applications are not rapidly changing. But what you're going to see is that you might need, in some cases, static CPU core counts, but additional acceleration.

So, if you look at what we've done in desktop for Ryzen, we've actually added a GPU with our CPU. And that's because it really creates a very dense and power-efficient offering, and if you don't need a high-performance GPU, you can save energy with that sort of tailored configuration. If you do need tailored, extensive acceleration, you can still bolt on a discrete GPU. And the other example in PCs is the Ryzen 7040; we've actually added AI acceleration right into the APU.

But what you'll also see is more variations of the cores themselves, you'll see high-performance cores mixed with power-efficient cores mixed with acceleration. So where, Paul, we're moving to now is not just variations in core density, but variations in the type of core, and how you configure the cores. It's not only how you've optimized for either performance or energy efficiency, but stacked cache for applications that can take advantage of it, and accelerators that you put around it.

When you go to the data center, you're also going to see a variation. Certain workloads move more slowly [...] You might be in that sweet spot of 16 to 32 cores on a server. But many businesses are indeed adding point AI applications and analytics. As AI moves from not only being in the cloud, where the heavy training and large language model inferencing will continue, but you're going to see AI applications in the edge. And it's going to be in enterprise data centers as well. They're also going to need different core counts and accelerators.
Paul Alcorn: So, it's probably safe to say that a hybrid architecture will be coming to client [consumer PCs]?

Mark Papermaster: Absolutely. It's already there today, and you'll see more coming.

AMD Already Using AI to Design Chips, Moving Into Generative AI

Paul Alcorn: We're starting to see a lot of AI used in chip design, a lot of use of AI and machine learning for certain things like macro placement, which is where most of the public-facing research and developments are happening. Can you tell me a little bit about AMD's design efforts? Is AMD using any type of AI or exploring that area for certain functions of chip design?

Mark Papermaster: We absolutely are. [...] How we think about it internally at AMD is, we need to practice what we preach. So we are applying AI today in chip design. We're using it in 'place and route,' both in how we position and optimize our sub-blocks of each of our chip designs to get more performance and to lower the energy [consumption]. AI does an amazing job of having an infinite appetite to iterate, iterate, and iterate until you have a truly optimal solution. But it's not just iterating; we could do that before. It's iterating and learning. It's looking at what patterns created the most optimal design, and so it's actually speeding the rate of having an optimized layout of your chip design elements, and therefore giving you higher performance and lower energy, just like we're doing with how we optimize our chiplet partitioning and chiplet placement.

We're also using it across our verification suites to drive a reduction in the time it takes to find any bugs in the typical iterative process of bringing a chip from concept through the whole verification and validation phase. And we're even using it in test pattern generation. So, when you have many billions of transistors in a chip design, getting the test coverage to make sure that when you test your product is flawless as it leaves your manufacturing floor. It turns out you can leverage AI to look at the learning; How did I get test coverage? Where are the gaps? What's the most effective? And get the controllability and observability to maximize test coverage, AI can really speed the times by building off of each successive run, learning from it, and shortening the time to adjust where you are going after any remaining holes in test coverage.

Paul Alcorn: Do you see a future where it could design microarchitectures, or certain chip functions?

Mark Papermaster: There's no question that we're just at such an early phase where you can start thinking about generative AI to actually create new approaches and build upon existing designs you have. We're doing that today with software. So, who would have thought the GitHub Copilot application could get such rapid adoption? Usually, new design tools take quite some time to permeate, but we're already experimenting with Copilot and looking at how it could best be deployed.

We, like everyone else in the industry, when you think about code generation, you have to first assure yourselves that you're protecting IP. That if you're drawing upon an existing knowledge base that you're protected - is that code safe to use? Is that protected from an IP reuse standpoint? So the biggest barriers to adoption right now are, frankly, ensuring that you have the right model, that the source of data that was used to train that model has you in the clear, and that the iterations that you do with generative AI to create next designs, that it's your IP. That it's your learnings of your company, and your engineers are using to iterate to [garbled].

It is absolutely capable today. But you have to make sure that you have an environment where you're protecting the ideas that you have, that creation process. If you use public models and you build upon them, you're actually donating your creative process back to the community. So, you actually have IP considerations as well in how you deploy.

The short answer to your question is, we're going to solve all of those constraints and you'll see more and more generative AI used in the very chip design process. It is being used in point applications today. But as an industry, over the next couple of years, next really one to two years, I think that we'll have the proper constraints to protect IP and you're going to start seeing production applications of generative AI to speed the design process.

Paul Alcorn: And even create designs.

Mark Papermaster: It won't replace designers, but I think it has a tremendous capability to speed design. It's no different than when you think about the broader creative process. Will generative AI replace artistry? Will it replace novels? No. But can it assist the process? Can it speed a student in creating some of the base elements, and they can then add their own thinking on top of it? Will it add to the artists' and novelists' creative process? Yes. And will it speed future chip designs? Absolutely. But we have a few hurdles that we have to get our arms around in the short term.

Sustainable Chip Manufacturing

Paul Alcorn: There's a big focus on power efficiency, and everyone focuses on reducing the carbon footprint when the chips are actually operating, and that is extremely important. But there's also a carbon footprint that can be substantial, and probably becoming more substantial as time goes on, associated with actually manufacturing and creating the chips. There’s EUV’s higher power consumption, a lot of new materials involved, and more processes, more steps, and it's becoming increasingly energy intensive. How does AMD deal with that, to minimize that? Is that something you do, or is that entirely up to TSMC? Or is this a collaborative effort?

Mark Papermaster: We’re supportive of those efforts, and I think they'll grow over time. Today, we are largely reliant on our foundry partners who are the experts in driving the best use of materials and the manufacturing processes. But we work with them to understand those techniques and we're constantly asking what we can do with our design approaches to help reduce the carbon footprint.

In addition, we are members of imec, right here in Belgium, so it's a tie-in to the conference here. And imec actually spans the disciplines. So, if you look at what imec does, it's usually five to 10 years in advance of mass production. So it's able to intercept the industry while the new technology nodes are in development and all the key players that are doing both the silicon, or the materials and the equipment, or the packaging, are involved in imec, as are the fabless design houses such an AMD. So they're in a perfect spot to intercept in that early ideation phase and help drive more sustainable solutions, and they are doing that.

Imec has kicked off a sustainable design initiative across its members. Stay tuned, I can't say more on that, but you might hear more than that at tomorrow's conference. And when you do, know that it is just kicking off, but through our design efforts we intend to be supportive of imec as a central point to help share across the semiconductor ecosystem where there are levers that we can drive more sustainable solutions and reduce the carbon footprint of our industry.

{Papermaster was referring to this announcement: GlobalFoundries, Samsung Electronics, and TSMC Join Imec’s “Sustainable Semiconductor Technologies & Systems” (SSTS) Program]

The Impact of Increased Power Consumption on Chip Cooling

Paul Alcorn: Power consumption has become quite the challenge - the power consumption of the latest Genoa chips jumped up quite a bit. And while some people look on the surface and say, 'wow, that's so much power,' it's actually very power efficient and very dense - and that's good. You're getting more [work] done in a smaller space. But that has created some cooling challenges.

I was really impressed with some of the custom coolers that were made for the Genoa servers to deal with that and the innovations around that. Do you see future generations of chips requiring even more robust cooling solutions? Are we reaching that point where with air cooling, there's pretty much an effective limit, or will we need to start going to like a liquid or maybe immersion cooling?

Mark Papermaster: We don't see that limit yet. At AMD, we're going to continue to offer air-cooled solutions. But what you're going to see more and more is a subset of customers that really want the highest compute density, really leveraging the efficiency and the core density we have. They'll be optionally choosing to do closed-loop cooling solutions. We see that already today with Genoa-based systems. 

I think what you'll see in the future is a real choice based on how you're choosing to optimize your data center. Are you legacy; do you want to leverage the legacy infrastructure you have? If so, we absolutely will support that, we're going to have air-cooled solutions for that. Are you building a new data center, and do you want to have it outfitted for the highest density that you can achieve? If so, you're going to adopt closed-loop cooling solutions.

At a recent financial conference, AMD CTO Mark Papermaster was asked about a report of a memory bug with the company's EPYC Genoa processors that would ostensibly require a lengthy redesign/respin process to fix. His answer was a bit vague, so we followed up with AMD for more details. The company repudiated the claims of a memory bug, telling Tom's Hardware that all fourth-gen EPYC processors shipped to date fully support the 2DPC memory configuration and that no respin is needed. Additionally, the company has already issued BIOS updates to its OEM partners to enable the promised support for 2DPC configurations by the end of Q1 2023, and one supporting platform is already listed for sale. AMD also shared other details we'll cover below. But first, a bit of background info.

As you can see in our EPYC Genoa review, AMD's new data center chips exhibit market-leading performance and come with several new interfaces, with support for 12 channels of DDR5 memory being one of the most important. However, Genoa only launched with support for DDR5 memory in a one DIMM per channel (1DPC) configuration. This type of configuration supports only one memory stick connected to each of the twelve DDR5 memory controllers inside the processor.

At launch, AMD said it would release a BIOS update in the first quarter of 2023 to enable support for two memory DIMMS per channel (2DPC), thus allowing two memory sticks to be connected to each memory channel to boost capacity. AMD said it was further characterizing and tuning the 2DPC memory configurations, so it would release the spec for the supported 2DPC memory speeds when the update became available.

In the interim, SemiAccurate (partially paywalled) reported a purported problem with AMD's Genoa processors last month. The report cited unnamed industry sources that claim Genoa has a bug in the memory subsystem, so AMD had to embark on a costly respin of the processors to support 2DPC memory configurations. This would inevitably lead to delays of several months as the new chips worked their way through the redesign and manufacturing process.

Naturally, a bug in the memory subsystem for the shipping chips would mean that the currently-shipping Genoa processors would not support the forthcoming 2DPC spec. So to determine if a new respin was needed, we asked AMD if all of the Genoa processors already in circulation would support the 2DPC memory configuration when launched, which the company assured us is the case.

Additionally, AMD went on the record to say that no respin is required for 2DPC support. Instead, the company says 2DPC support only requires the BIOS update it has already issued to its OEM customers. As a result, they are already designing motherboards with enough slots to support the feature. In fact, Tyan has already listed the Transport CX GC68A-B8056 that supports a 2DPC configuration.

Due to the normal step-down in speeds with 2DPC configs, Intel's 8-channel Sapphire Rapids drops from DDR5-4800 in 1DPC to DDR5-4400 in a 2DPC config. We can also expect Genoa's 2DPC speeds to be less than the 1DPC speed when the company releases the final spec, but it remains to be seen how much of a penalty it will incur. The Tyan server lists memory speeds at DDR5-4000 for the 2DPC config, but we're told this could vary by system. Overall, this is a 10% reduction in speeds compared to Intel's 2DPC config, but that isn't too bad given the 12-channel Genoa's support for 50% more memory slots.  

AMD also clarified Papermaster's comments at the recent Morgan Stanley investor conference, which have been misinterpreted. At the conference, Papermaster said, "And the 2 DIMM per channel, which is I think what you're referring to is following. So that is for a targeted – a much smaller targeted set of customers. Those speeds will be announced later this quarter, and that will ramp as well, but this number of customers for 2 DIMMs per channel is much smaller." AMD says the "ramp" comment is in reference to systems that support 2DPC configurations (they need more physical slots), not to a newer revision of the processor.

Genoa's support for 12 channels of DDR5 is the highest on the market for an x86 processor. Genoa has 50% more channels than Sapphire Rapids' eight channels, and both chips support a peak of DDR5-4800 memory in a 1DPC configuration. Intel has specced its 2DPC configuration at DDR5-4400, but as mentioned, AMD hasn't finished qualifying its 2DPC transfer rates. We're told that these could vary by platform.

AMD's decision to launch Genoa before it had finalized 2DPC support is sound — it is rational to expect that the demand for 2DPC configs will be dramatically less than we've seen in the past. The 2DPC config is typically used to access increased capacity (there can be small performance improvements with certain rank configs). But with 12 memory channels in a 1DPC configuration, AMD can already support up to 3TB of memory per chip with 256 GB sticks. That's plenty for the broadest cross-section of users. Support for 2DPC boosts that capacity to 6TB of DDR5 per socket, but AMD is already running into space constraints packing in 12 channels of memory into regular two-socket servers.

As you can see in the above image of our Genoa test server, cramming in 24 total DIMM slots for a 1DPC config already creates plenty of issues due to space constraints. Frankly, it's hard to imagine packing in twice the number of pictured slots for a 2DPC configuration — a dual-socket server would need 48 total slots. As such, we believe that most 2DPC configs will likely either be for single-socket servers or use a reduced number of channels in dual-socket servers. In fact, the Tyan server that lists 2DPC support only has a single socket.

There are already plenty of challenges enabling the pictured 1DPC config. In fact, AMD had to use special 'skinny' memory slots for Genoa motherboards to help pack 12 slots into the chassis. AMD cautioned us that, due to the skinny slots and other accommodations for the denser arrangement, it has had several incidents where lateral pressure when installing the DDR5 DIMMs had stripped the DIMM socket off the board. This is an edge case and not indicative of an issue with the platform, but it does point to the challenges AMD already faces with 'just' 12 memory slots.

The challenges for 2DPC expand beyond just the space needed for more slots. As we've seen with DDR4 memory, adding more DIMMs per channel results in reduced memory speeds, and more channels results in even more complexity. Additionally, even having extra empty slots can result in lower peak memory speeds, as seen with the complicated DDR4 and DDR5 support matrix for the consumer platforms. Those problems become even more vexing with DDR5, as it has much higher tolerances and requires more complex motherboard designs with more layers and better materials, which adds cost. This will become even more challenging with the higher transfer rates needed for next-gen memory — market insiders have even predicted that support for 2DPC could end with the DDR6 standard.

AMD says it will release further details about Genoa's 2DPC support this month, and we'll update once we receive the details.

Mark Papermaster, chief technology officer of AMD, said at a conference that the company's next-generation Instinct MI300 accelerated processing unit for data centers and high-performance computing is already up and running in AMD's labs. The APU uses AMD's Zen 4 and CDNA 3 architectures and will power the El Capitan supercomputer that is expected to break the 2 ExaFLOPS barriers sometimes in 2024.

"But with what we announced and have rolled out with our next-generation Instinct that we already have back in the labs, the MI300, it is a true datacenter APU," said Papermaster at the Wells Fargo 2022 TMT Summit (via SeekingAlpha). "It is a CPU and a GPU acceleration that is leveraging the Infinity architecture to share the same memory fully coherently. It is all sharing high-bandwidth memory."

AMD's Instinct MI300 is a multi-chiplet APU carrying Zen 4 general-purpose x86 cores, and CDNA 3-based compute GPU that share a unified on-package pool of memory comprising of Infinity Cache as well as HBM. AMD will use TSMC's N5 (5nm-class) fabrication process to produce CPU/GPU chiplets for the MI300, but the company has yet to disclose how many CPU cores and GPU stream processors are set to be packed into the hybrid processor.

Putting CPU cores and GPU accelerators into one package and making them use unified memory is the Holy Grail of supercomputing as it not only combines the best of both worlds (general purpose processing and highly parallel acceleration), but it also dramatically simplifies programming and makes it easier to get all performance potential out of execution engines.

The Instinct MI300 APU is set to power the U.S. Department of Energy's El Capitan supercomputer, which will be installed at the Lawrence Livermore National Laboratory (LLNL) sometime in 2023 and will become fully operational in mid-2024. 

AMD plans to roll out its Instinct MI300 sometime in 2023, which is why it is not surprising that the processor is already up and running in its labs. Meanwhile, it is unclear whether the company will supply the MI300 to any clients outside the supercomputer world in mass quantities next year.

Since AMD's Instinct MI300 will be the industry's first data center and HPC-grade APU, there will be a lot of interest in it in the supercomputing community. Meanwhile, AMD's Instinct MI300 will not be the only hybrid processor for data centers packing x86 and GPU resources that will be available in the coming years. For example, Intel is working on its codenamed Falcon Shores product with x86 and Xe-HPC cores in the same package and expects to make it available in 2024.

AMD CEO Lisa Su and a host of other executives will take to the stage tonight at 7 PM ET to announce the Zen 4 family of Ryzen 7000 processors during the company's "together we advance_PCs" livestream. These new chips bring several big advancements, including support for DDR5 memory and the PCIe 5.0 interface, not to mention blisteringly-high clock speeds that are rumored to top out at 5.7 GHz. In addition, AMD has also added integrated graphics to its mainstream Ryzen lineup for the first time.

We expect AMD to make several key announcements, including pricing, availability, and the full specifications of the Ryzen 7000 lineup, along with other new details about the new Socket AM5 motherboard ecosystem. We added updates as the show progressed, but you can also watch the video yourself in the embed above.

You can also see our other coverage with the full lineup and details in the AMD Launches Zen 4 Ryzen 7000 CPUs article. 

• $699 Ryzen 9 7950X, 16 cores, 32 threads, 4.5 / 5.7 GHz base/boost
• $549 Ryzen 9 7900X, 12 cores, 24 threads, 4.7 / 5.6 GHz base/boost
• $399 Ryzen 7 7700X, 8 cores, 16 threads, 4.5 / 5.4 GHz base/boost
• $299 Ryzen 5 7600X, 6 cores, 12 threads, 4.7 / 5.3 GHz base/boost

AMD CEO Lisa Su began the show by describing how the company touches billions of users' lives every day. That will continue with four new architectures that the company will launch over the next several quarters. That includes Zen 4, Zen 4C, RDNA3, and its XDNA architecture. 

Lisa Su outlined the company's goals for its Ryzen 7000 processors, including support for PCIe 5.0 and DDR5 memory. AMD exceeded its goals for the Zen 4 core, so the company is revising its initial projection of up to 10% IPC improvement to 13%. 

AMD has also increased peak clock speeds to 5.7 GHz, an 800 MHz improvement over the prior generation processors. 

Lisa Su says the Ryzen 9 79750X is the fastest gaming CPU in the world and that it delivers up to 60% more compute performance. 

Lisa Su demoed the Ryzen 9 7950X running the vray rendering benchmark 62% faster than Intel's flagship Core i9-12900K, but at 47% better performance per watt. 

Su also announced three other processors: the Ryzen 9 7900X, Ryzen 7 7700X, and the Ryzen 5 7600X.

AMD says the Ryzen 5 7600X delivers up to 5% more gaming performance than the Core i9-12900K. Here we can also see the full lineup of Ryzen 7000 processors. 

AMD CTO Mark Papermaster has taken to the stage. 

Papermaster outlined several new improvements, including 13% IPC increase, new front-end design, support for AVX-512, and the 5nm process node. 

AMD tuned the Zen 4 architecture to expose the higher frequencies available with the TSMC 5nm process node. AMD also worked with TSMC to develop a semi-custom N5 process node that delivers enhanced performance. 

AMD measured the 13% IPC improvement with a wide range of workloads, including gaming. Naturally, the IPC improvement varies by workload, but it measures at 13% overall. 

Zen 4 is an iterative improvement over Zen 3. AMD widened the front end and improved branch prediction, delivering up to 60% of the IPC gain. AMD also doubled the L2 cache and the op-caches. 

AMD added support for AVX-512, but made special accommodations to prevent this from resulting in reduced frequencies. To combat that problem, AMD uses a 'double-pumped' AVX-256 implementation. 

AMD worked closely with TSMC to tune its architecture for the TSMC 5nm node. The result is an N5 node that has several advantages, including a more robust 15-layer metal stack. 

AMD also reduced the die area despite these enhancements. 

AMD touted 62% lower power consumption gen-over-gen and 49% more performance at the same power. 

AMD has improved performance and power efficiency significantly. The N5 process delivers even larger performance gains with the lower-power 65W models.

The AMD Zen 4 core is 54% smaller than Intel's Alder Lake chips. It is also 47% more efficient. 

AMD will bring its 3D V-Cache models to market later this year. The company also has its stripped-down Zen 4c core coming to market for data centers early next year.

Zen 5 is a new ground-up redesign; it will arrive in 2024.  

AMD says Zen 4 remains on schedule and proves the company can execute to schedule. Papermaster says there will be no letup in AMD's cadence of innovation. 

AMD's David McAfee has come to the stage. He's here to talk about the AM5 platform, but started by recapping the successes of the AM4 ecosystem. 

AM4 has supported five CPU architectures across four nodes. Overall, it has supported 125 processors and 500 had different motherboard designs. 

The AM5 platform takes over with its 1718-pin LGA socket. AMD has increased power delivery to 230W to deliver improved performance in threaded applications. It also supports PCIe 5.0 and DDR5. 

The X-series motherboards arrive in September, while the value-centric B-series boards arrive in October. AMD also announced new B650 Extreme motherboards that have more PCIe 5.0 connectivity than the standard B650 models. 

PCIe 5.0 SSDs will come to market in October. 

AMD is moving to DDR5 with AM5, and it will no longer support DDR4. AMD feels that the higher performance and capacity are worth the upgrade. 

EXPO DDR5 modules have new profiles that enable one-click overclocking. This is much like XMP. There will be 15 kits available at launch. Speeds top out at DDR5-6400. 

Motherboards will start at $125. AMD will support the AM5 platform through at least 2025. That means it will be long-lived like AM4. 

Lisa Su is back on stage, giving an overview of the performance claims. But there's more...

Lisa shared pricing for the Ryzen 7000 processors, ranging from $699 to $299. The chips are available on September 27. 

Lisa Su teased a GPU with the RDNA 3 architecture. The GPU has 5nm chiplets and delivers 50% more performance per watt than the existing Radeon GPUs.

Su showed a demo of the RDNA 3 GPU running with a Ryzen 9 7950X. There are no performance metrics, but the demo shows the GPU running the highly anticipated title Lies of P from Neowiz.

Lisa Su wrapped up the livestream and thanked the audience. 

An AMD Ryzen 7 7700X is the latest CPU benchmarked in Cinebench R20 by Chinese leaker Extreme Player. The upcoming Ryzen 7000 chip appears to perform 23% better than the Ryzen 7 5800X in the 1T test, and 32% faster in the multithreaded test. 

Note that this is an unverified leak, and the tester admits the Ryzen chip is an Engineering Sample (which seems correct based on the CPU image), so things could get better by launch/availability. 

The alleged 7700X (codename: Raphael) chip will feature AMD's latest Zen 4 cores and be manufactured on TSMC's N5 process, in 8C /16T configuration. In the video, Extreme Player helps put some of the benefits of the Ryzen 7000 chip’s new technologies into comparable performance data.

Here's how the alleged 7700X Cinebench R20 scores stand up against other chips that have been put through Extreme Player's lab (and a 5800X from Anandtech), from Twitter user Harukaze :

*Based on Tom's Hardware testing 

In the above tabulated results we've included a Cores / Threads column to help clarify what's behind the great nT test scores from Intel CPUs. 

A screenshot of the Cinebench R20 results tab in Extreme Player's video shows that the AMD Ryzen 7 7700X ran all eight SMT cores at 4.5 GHz during the benchmarking session.

AMD has scheduled its Together We Advance_PCs event for Monday, August 29. At this event, AMD CEO Dr. Lisa Su and CTO Mark Papermaster will discuss the Ryzen 7000 series and "present details on the latest Zen 4 architecture."  

Based on a product library slip earlier this summer, we expect the launch lineup will consist of the Ryzen 9 7950X, Ryzen 9 7900X, Ryzen 7 7700X, and Ryzen 5 7600X.

In the meantime, check out everything we know about AMD's upcoming Ryzen 7000 processors — benchmarks, price listings, and more. 

AMD has officially named the date for the launch of its next-generation Ryzen 7000 processors in a press release published today. AMD will detail the highly anticipated Ryzen 7000 series processors at the event starting 7pm ET on Monday, August 29. AMD CEO Dr. Lisa Su and CTO Mark Papermaster will present the live-streamed event and be joined by several other AMD executives.

The upcoming event has been dubbed “together we advance_PCs” by AMD’s marketing department. AMD has used the “together we advance_” theme since early summer, and you might have seen _automotive, _AI, _data centers, _entertainment, _supercomputers, and _gaming suffixes during other recent PR blitzes.

Though we refer to the next-gen Ryzen processors as ‘Ryzen 7000 processors’, interestingly, AMD doesn’t use this naming scheme anywhere in its press release. Rather it says that the AMD executive team “will present details on the latest ‘Zen 4’ architecture.” That doesn’t mean AMD will surprise us with a new naming convention, though, as it has previously shared stacks of slides mentioning that the “Ryzen 7000 Series” would come this Fall.

AMD didn't give away a lot in its event announcement; it is short and highlights only a couple of technical advances that will turn up alongside the first Zen 4 processors. Specifically, it mentions the Zen 4 architecture, AM5 socket, DDR5, and PCIe 5.

We already enjoyed an extensive official AMD AM5 motherboard event, where all the important partners revealed considerable detail about their upcoming X670 and X670E motherboards. So please follow that link for a hefty slice of motherboard tech coverage with specifics from AMD partners like Asus, Gigabyte, and MSI.

For all we know about AMD’s upcoming Ryzen 7000 Series processors – a mix of official info, leaks, and spills – you should head over to our frequently updated AMD Zen 4 Ryzen 7000 Specs, Release Date, Benchmarks, and More feature. We have all sorts of information about the Ryzen 7000 series processors there, including a table of expected SKUs pitted against Intel’s upcoming Raptor Lake CPUs.

Purported pricing has also recently emerged via a Canadian retailer. PC components are often very price sensitive due to fierce competition unless something distorts the market (e.g., cryptomining), so pricing will be key. 

You can watch AMD’s “together we advance_PCs” event live on the AMD YouTube channel. In addition, a replay of the livestream will be made available a few hours after the event concludes at both AMD.com/Ryzen and on YouTube.

AMD is extending its custom chip design services even as it aims to offer a portfolio that's close and personal to its client's requirements. During its latest analyst day meeting, AMD Chief Technical Officer (CTO) Mark Papermaster spoke of recent advancements in semiconductor fabrication and chip interconnect technologies that would enable a modular future for the company's chip design. It seems that AMD might be looking at carving another strategy for the decades to come: something like "The Future is Custom."

Building upon work that started with custom silicon designs for the Xbox 360 and PlayStation 4, AMD's Semi-Custom Solutions Division has quickly become one of the company's main strengths. AMD adapted its mainstream architectures according to Microsoft and Sony's power, performance, and cost requirements. Even Steam's runaway success, the handheld Steam Deck, has embraced AMD chip designs. But the company wants to take it further.

"We are focused on making it easier to implement chips with more flexibility," said Papermaster, who then expanded on the new philosophy by adding that customers would be invited to bring their own choice of chips towards a tile-like, manufacturable chip structure that can incorporate multiple chiplets wrapped up in a custom chip package. This means AMD customers would be able to pick and choose amongst the company's impressive IP portfolio - ranging from x86 CPUs, GPUs, Arm-based FPGAs through its merge with Xilinx, and even Arm-based networking chips from its Pensando acquisition - while also being able to deploy their own intellectual property.

The new strategy builds upon the recently-introduced Universal Chiplet Interconnect Express (UCIe) standard, which has garnered support from AMD, Intel, Arm, Google, Meta, and others. These companies see the future as an amalgamation of disparate, complementary IPs rather than what each player can singularly offer in-house. UCIe enables a standardized connection between chiplets, like cores, memory, and I/O, in both an in-die and off-die manner that enables performance and latency specifications that are high enough for HPC scaling while relying on well-known protocols like PCIe and CXL.

This makes sense considering the increasing prevalence of custom chip design - bolstered by royalty-free architectures such as RISC-V. Interestingly, RISC-V still hasn't integrated the UCIe standard. Nvidia hasn't either, but the company likely wants to push its proprietary NVLink interconnect as much as possible.

"We're going to make it much easier to add third-party IP as well as customer IP to that chiplet platform," said AMD CEO Lisa Su during the conference. "We've gotten a lot of positive customer engagement so far when you think about hyperscalers, when you think about 5G in automotive," she added. "These are big opportunities where people want to customize and we want to be their partner of choice."

AMD's chiplet-based approach to custom manufacturing is based on its strong relationship with TSMC and leverages the Taiwanese foundries' CoWoS (Chip-on-Wafer-on-Substrate) technology. The same is true for Apple's CoWoS-derivative UltraFusion interconnect. Nvidia's own Hopper GPU is also rumored to be based around that particular bit of TSMC's tech. AMD, naturally, will also be looking to leverage its Infinity Fabric 4.0 architecture, which has been developed for on-die connectivity and hyperscaling in HPC environments.

In what might be one of the most interesting tidbits regarding the future of computing, saying that the company is happy to be ISA (Instruction-Set Architecture) agnostic. Of course, it's easier to be agnostic when a company has the resources, licenses and engineering capabilities to have its feet firmly planted in both dominating and emerging architectures all at once. AMD is capable of this feat thanks to its nearly immaculate execution since Su became CEO.

It does mark a difference in stance compared to the walled garden approach historically preferred by chipmakers. To be fair, there's still a wall - there's a reason only AMD and Intel manufacture high-performance X86-x64 chips. But the gates are now ever so slightly ajar. In the meantime, we await the arrival of AMD's Ryzen 7000 processors and other new products on its consumer CPU roadmaps. 

UPDATE: AMD has shared all the details now, and you can see our full coverage in our AMD Teases 5nm Ryzen 7000 ‘Raphael’ Zen 4 CPUs, Unveils Ryzen 7 5800X3D with 96MB of L3 Cache and AMD Unveils 6nm Ryzen 6000 ‘Rembrandt’ Chips With Zen 3+, RDNA2 and DDR5 articles. 

Original Article:

AMD's Lisa Su is set to present the company's plans for 2022 during its CES 2022 Product Premiere presentation that will kick off at 7am PT on January 4, 2022. You can pull up a seat and watch the presentation live in the embedded video below, and we'll follow up with all of our news and analysis from the event. 

Oddly enough, last night the agency behind CES (the CTA) inadvertently tipped us off about one of AMD's possible announcements at the show. The inadvertent unveiling of the Ryzen 6000 "Rembrandt" mobile processors came via a new Honoree award posted to the CTA's website.  

As we predicted last month, we also expect to hear news about AMD's upcoming processors with 3D V-Cache, and the event description also teases that Su will “highlight innovations and solutions featuring upcoming AMD Ryzen processors and AMD Radeon graphics,” meaning GPUs announcements are also on the menu. 

AMD also recently unveiled its Zen 4 roadmap for its data center products, and given that AMD CTO Mark Papermaster said very clearly to expect more news on Zen 4, we expect to hear more about the Zen 4 chips for desktop PCs, too.  

The CTA's AMD award listing confirms the new Rembrandt chips come with the RDNA2 graphics architecture, a massive step forward from the Vega graphics on the current-gen Ryzen 5000 Mobile 'Cezanne' chips. The new chips also support "DDR5 technologies,' another nice step forward from the DDR4/LPDDR4X support with the previous-gen chips. As with all of AMD's mobile processors, these chips will eventually come to the desktop PC, too, much as we see with the impressive Cezanne-powered Ryzen 7 5700G and Ryzen 5 5600G. 

Naturally, we expect that many more details about these chips, along with other new and exciting announcements, will emerge during the live stream. Grab a seat!

Information on AMD's next-gen processors may be closer than we expected: AMD has announced that it will begin to share details on its 5nm "Zen 4" Ryzen chips at CES 2022. AMD chief technology officer Mark Papermaster teased its inclusion in the chipmaker's presentation in an interview with Forbes contributor Anthony Leather.

"We're excited to be revealing some additional details on our new product launches that will deliver phenomenal experiences, and as we've said, later in the year as it progresses we'll share more detail on Zen 4, with some mentioned at CES and more announcements on it over the course of 2022," Papermaster said in the interview. "It will be a very exciting year for AMD."

AMD has its CES presentation scheduled for Jan. 4, 2022, at 10 a.m. EST, where CEO Lisa Su is expected to discuss its notebook-class Ryzen 6000-series processors, AMD Radeon graphics, and its Ryzen 3D V-Cache technologies. However, we'll only know for sure once the announcements are made on stage. Based on Papermaster's statements, it seems that any mention of Zen 4 is likely to be a tease that kicks off a 2022 marketing campaign before a launch later in the year.

Zen 4, often known as "Raphael" on AMD's artist-themed roadmap, is rumored to offer better thermal and power management and max out at a total of 16 cores. The desktop chips are also expected to bring a new design with a thicker integrated heat spreader than current Zen 3 processors.

AMD showed off the Zen 4 roadmap for its EPYC processors in November, including a 96-core "Genoa" model and a 128-core Bergamo processor.

We'll be covering AMD's CES 2022 event as it happens, so check back for more information on the company's latest, including Zen 4, as it happens.

AMD will unveil its EPYC 7003 Milan processors during a live webcast that you can watch here on March 15, 2021, at 11am ET (8am PT), marking the company's first release of processors for the data center based on the Zen 3 architecture. The live stream will include presentations from AMD CEO Lisa Su, CTO Mark Papermaster, and SVP and GM of the data center group, Forrest Norrod.

Update: The NDA has expired. You can see our full breakdown and analysis here, which covers the finer details of the live stream below.

Beyond an accidentally-posted presentation in 2019, AMD hasn't officially revealed many details around its Milan lineup. However, it recently teased a performance benchmark at CES 2021, and a vendor recently posted specifications and pricing for several models.

Early indications suggest that, as with the current-gen EPYC Rome processors, AMD fabs the EPYC Milan chips with the 7nm process, and they top out at 64 cores. The most significant change to the series comes with the infusion of the Zen 3 microarchitecture that lends a 19% in instruction per cycle (IPC) throughput improvement through several changes, like a unified L3 cache and better thermal management that allows the chip to extract more performance within any given TDP range.

Even though we've seen shortages on the consumer side of AMD's business, it has obviously prioritized server chips production. As a result, it has continued to slowly whittle away at Intel's commanding lead in the data center. Faced with unrelenting pressure from a surprisingly nimble competitor, Intel has significantly reduced gen-on-gen pricing with the debut of its Cascade Lake Refresh Xeon models, by 60% in some cases, by slightly adjusting the capabilities of the chips in a way that largely results in a price reduction that comes in the guise of new chips.

To counter, AMD bulked up its EPYC Rome lineup with its workload-optimized 7F and 7H parts, which come with higher power consumption and thermals than the standard 7002 series chips but feature higher frequencies, allowing AMD to challenge Intel's traditional lead in per-core performance.

But now the landscape will change once again. The Milan launch, not to mention Intel's pending 10nm Ice Lake launch, promises to reignite the heated data center competition. You can watch the presentation here live, but be sure to check out our full analysis after the announcement. 

AMD announced today that it would unveil its EPYC 7003 Milan processors via a live webcast on March 15, 2021, at 8am PT, marking the company's first release of processors for the data center based on the Zen 3 architecture. The live stream will include presentations from AMD CEO Lisa Su, CTO Mark Papermaster, and SVP and GM of the data center group, Forrest Norrod.

Beyond an accidentally-posted presentation last year, AMD hasn't officially revealed many details around its Milan lineup, though it did recently tease a performance benchmark at CES 2021 and a vendor recently posted specifications and pricing for several models. 

Early indications suggest that, as with the current-gen EPYC Rome processors, AMD fabs the EPYC Milan chips with the 7nm process and they top out at 64 cores. The most significant change to the series appears to come with the infusion of the Zen 3 microarchitecture that lends a 19% in instruction per cycle (IPC) throughput improvement through several changes, like a unified L3 cache and better thermal management that allows the chip to extract more performance within any given TDP range. 

AMD has obviously prioritized the production of its EPYC chips to continue its assault on Intel's vaunted Xeon platform. As a result, AMD has continued to slowly whittle away at Intel's commanding lead in the data center, a trend that still continues today despite supply constraints that have slowed the company's advance in other segments.

Faced with unrelenting pressure from a surprisingly nimble competitor, Intel has significantly reduced gen-on-gen pricing with the debut of its Cascade Lake Refresh Xeon models, by 60% in some cases, by slightly adjusting the capabilities of the chips in a way that largely results in a price reduction that comes in the guise of new chips. To counter, AMD bulked up its EPYC Rome lineup with its workload-optimized 7F and 7H parts, which come with higher power consumption and thermals than the standard 7002 series chips but feature higher frequencies, allowing AMD to challenge Intel's traditional lead in per-core performance.

The Milan launch, not to mention Intel's pending 10nm Ice Lake launch, promises to reignite the heated data center competition once again. AMD has reiterated that EPYC Milan processors are on track for the formal launch in the first quarter of the year, and today's announcement indicates those plans are on track. It's noteworthy that the EPYC Milan chips already began shipping to select cloud and HPC customers in the last quarter of 2020, while the formal launch will mark availability for Tier 1 OEMs. 

AMD’s early Milan shipments to HPC partners are critical: Milan has already enjoyed explosive uptake in the supercomputer space and is slated to power the world’s soon-to-be-fastest supercomputer, the exascale-class Frontier, along with the Perlmuter supercomputer, among many others.

The EPYC Milan Tier 1 OEM launch comes soon, but the competitive landscape will undoubtedly change entirely over the course of the next few months - Intel’s 10nm Ice Lake data center processors are also slated for release this quarter. 

AMD CEO Lisa Su and several of the company's famous past-and-current architects, like Jim Keller and Mike Clark, receive much of the public recognition for the company's amazing resurgence. But Mark Papermaster has served as the company's CTO and SVP/EVP of Technology and Engineering since 2011. He's been at the helm of developing AMD's technology throughout its David versus Goliath comeback against industry behemoth Intel, giving him incredible insight into the company's past, present, and future.  

We sat down with Papermaster during the Supercomputing 2019 conference to discuss the company's latest developments, including shortages of Ryzen processors, what we can expect from future CPUs, the company's new approach of enabling a mix of faster and slower cores, thoughts on SMT4 (quad-threaded processor cores), and the company's take on new Intel technologies, like Optane Persistent Memory DIMMs and OneAPI. 

Given AMD's success in the data center, we also discussed if EPYC Rome is impacting industry interest in competing x86 alternatives, like ARM. 

How Many Cores Are Enough?

It takes a lot of engineering wizardry to enable, but a big part of AMD's success stems from the rather simple concept of delivering more for less. For enthusiasts and data center architects alike, that starts with more cores. AMD's Zen has spurred a renaissance in core counts, boosting the available compute power we can cram into a single processor, forcing Intel to increase its core counts in kind. That incredible density started with the EPYC lineup that now stretches up to 64 cores, besting Intel's finest in the data center. 

On the consumer side, the Ryzen 9 3950X brings an almost-unbelievable boost to 16 cores on mainstream platforms, a tremendous improvement over the standard of four cores just a mere two years ago. As AMD moves forward to smaller processes, that means we could theoretically see another doubling in processor cores in the future. That makes a lot of sense for the data center, but begs the question of how many cores an average consumer can actually use. We asked Papermaster if it would make sense to move up to 32 cores for mainstream users: 

"I don’t see in the mainstream space any imminent barrier, and here's why: It's just a catch-up time for software to leverage the multi-core approach," Papermaster said. "But we're over that hurdle, now more and more applications can take advantage of multi-core and multi-threading.[...]"

"In the near term, I don’t see a saturation point for cores. You have to be very thoughtful when you add cores because you don’t want to add it before the application can take advantage of it. As long as you keep that balance, I think we'll continue to see that trend."

Are Processors Going to Get Slower as they Shrink?

Over the years, we've become accustomed to higher clock speeds with smaller nodes. However, we've reached the point where smaller nodes that enable more cores can also suffer reduced frequencies, like we've seen with Intel's Ice Lake family. As potent as TSMC's engineering team is, there's possibly a diminishing point of frequency returns, if not frequency declines, on the horizon as it moves to the smaller 5nm process. Papermaster is confident in AMD's ability to offset those challenges, though.

"We say [Moore's Law] is slowing because the frequency scaling opportunity at every node is either a very small percentage or nil going forward; it depends on the node when you look at the foundries. So there's limited opportunity, and that's where how you put the solution together matters more than ever," Papermaster said. 

"That's why we invented the Infinity Fabric," he explained, "to give us that flexibility as to how we put in CPU cores, and how many CPU cores, how many GPU cores, and how you can have a range of combinations of those engines along with other accelerators put together in a very efficient and seamless way. That is the era of a slowed Moore's Law. We’ve got to keep performance moving with every generation, but you can't rely on that frequency bump from every new semiconductor node."

AMD will also evolve its Infinity Fabric to keep up with higher-bandwidth interfaces, like DDR5 and PCIe 5.0. "In an era of slowed Moore's Law where you are getting less frequency gain, and certainly more expense at each technology node, you do have to scale the bandwidth as you add more engines going forward, and I think you're going to see an era of innovation of how in doing so you design to optimize the efficiency of those fabrics," Papermaster said.

Ryzen 3000 Shortages

AMD's boosted core counts come as a byproduct of TSMC's denser 7nm process, but the company initially suffered from nagging post-launch shortages of its high-end SKUs and had to delay its flagship desktop processor, leading to questions about AMD's ability to satiate demand. Those questions are exacerbated by reports that TSMC has extended lead times for its highly-sought-after 7nm process, and because AMD competes for wafer output with the likes of Apple and Nvidia. 

"We're getting great supply from our partner TSMC." Papermaster said, "Like any new product, there is a long lead time for semiconductor manufacturing, so you have to guess where the consumers are going to want their products. Lisa [Su] talked about the demand simply being higher than we anticipated for our higher-performance and higher-ASP [products], the Ryzen 3900 series. We've now had time to adjust and get the orders in to accommodate that demand. That's just a natural process; in a way, it’s a good problem to have. It means the demand was even higher than we originally thought."

As a natural result of semiconductor fabrication, each wafer has dies with different capabilities, which are then binned (sorted) according to their capabilities. AMD's faster processors require the cream-of-the-crop dies, and the company simply wasn't receiving enough of those premium dies. We asked if getting more high-end die is simply a function of ordering more wafers:

"We work closely with the foundry to get the right mix on any chip. You have various speed ranges that come out of the manufacturing line. You have to decide in advance what you think is the distribution of chips and work with the foundry partner to make sure you call the demand right," Papermaster elaborated.

Unlocking Faster Performance With New Boost Technology

The looming frequency scaling challenges can be addressed through a range of techniques, but AMD already has a new innovative technology that helps wring out the utmost performance from every core. 

Just like the capabilities of each die harvested from a wafer will vary, every core on a chip has differing capabilities. Like all processors, AMD's chips come with a mix of faster and slower cores, but we discovered that the company uses an innovative technique to extract higher frequencies from the faster cores, which stands in contrast to the standard approach in the PC industry of adjusting to the lowest common denominator. We asked Papermaster about the rationale behind the new technology:

"There's typically a fairly small variation of the performance across cores," Papermaster responded, "but what we enable on our chips is the opportunity to boost and maximize the performance of any given chip. We're enabling these boost technologies to the advantage of our end customers, to make sure that we are optimizing power, yet delivering the best performance."

Does SMT4 Make Sense?

There have been persistent rumors and reports in the media that AMD will adopt SMT4, which involves enabling each core of the processor to run four threads as opposed to the standard dual-thread implementations. Knowing that AMD won't reveal direct information about its forthcoming chips, we asked Papermaster about his opinion of the technology coming to the desktop:

"We've made no announcements on SMT4 at this time," Papermaster responded. "In general, you have to look at simultaneous multi-threading (SMT): There are applications that can benefit from it, and there are applications that can't. Just look at the PC space today, many people actually don’t enable SMT, many people do. SMT4, clearly there are some workloads that benefit from it, but there are many others that it wouldn’t even be deployed. It's been around in the industry for a while, so it's not a new technology concept at all. It's been deployed in servers; certain server vendors have had this for some time, really it's just a matter of when certain workloads can take advantage of it."

Papermaster's Thoughts of Persistent Storage (Optane) on the Memory Interface

Intel lists Optane Memory among its technological advantages over its peers, but like all processors that use standardized interfaces, AMD's EPYC also supports Optane when used as a storage device.

However, Intel also offers its Optane Persistent Memory DIMMs that are used as memory after dropping them into memory slots. Intel has a proprietary interface that enables the functionality, so AMD's EPYC platforms don’t support the feature. We asked Papermaster about AMD's take on persistent memories, and if we could see similar DIMM support from AMD in the future using Optane memory from its ally Micron.

"Eventually, the way the industry is heading is to enable storage class memory to be off the I/O bus." Papermaster said, "That's where they really want to be because that's where it is more straightforward from the software stack to leverage these dense storage class memories (SCM). So, you're seeing an evolution there, you're seeing the industry working on SCM solutions. There's been a number of industry standards to align on that interface, and now CXL has taken off. We've joined it along with many other members of the industry, and so you're starting to see convergence on that interface for these types of devices. It's going to take a little time because they're going to have to get out there, and then the applications have to be tuned and qualified to run and really leverage this."

We dove in a bit deeper, asking if Papermaster thinks there is more interest in the industry for standards-based I/O interfaces (like NVMe) as opposed to using the memory bus, to which he responded, "I believe so. I think that's where you're really going to see SCM become pervasive in the industry."

Would AMD Adopt Intel's OneAPI?

Intel's OneAPI is a collection of libraries that enable programmers to write code that is portable between different architectures, thus allowing programs that run on CPUs to seamlessly transfer over to other architectures, like GPUs, FPGAs, and AI accelerators. 

Interestingly, Intel recently announced that OneAPI will work with other vendors' hardware and that they are free to adopt the technology. We asked Papermaster if AMD would consider adopting OneAPI.

"We've already been on a heterogeneous software stack strategy and implementation for some time. We already released the Radeon Open Compute stack at a production level two years ago, so we have a path that is open and allows a very straightforward path to compiling workloads that are heterogeneous across our CPUs, our GPUs, and also interface with standards like OpenMP so you can then create high performance compute cluster capabilities." 

"This is a path that we've already been on in AMD for some time, and we're glad to see the endorsement from our competitor that they see it the same way."

Is EPYC Sucking the Oxygen out of ARM?

As we've seen with Intel's recent shortages, a monopoly-like hold on the processor market isn’t good for pricing or sourcing stability. As such, the industry has long pined for alternative processors, but in reality, it really isn't searching for an x86 alternative. Rather, the industry wants an Intel alternative.

ARM and other architectures require expensive and time-consuming re-coding and validation of existing software, while AMD's EPYC Rome is plug-and-play with the x86 instruction set, thus reducing the additional expenses associated with moving to a different architecture.

Many have opined that EPYC Rome is sucking the oxygen out of industry interest in other architectures, like ARM, due to those advantages. We asked Papermaster for his take:

"x86 is the dominant architecture for computing today, and there's just such a massive amount of software code for x86, and such a massive toolchain that makes it easy for developers on this platform. So, we just see such a long and healthy opportunity, and frankly for AMD, with the strength of our roadmap, a tremendous share gain opportunity for us," Papermaster said.

"We're very focused on our strategy to ensure that every generation we have brings tremendous value to our customers, and in doing so, I do think it makes it harder for new architectures to enter. You'll see specialized applications that are less architecture-dependent. Because they’re specialized, they don’t care as much about that broad x86 base. So I do think, as you already see today, a small market for specialized architectures that'll continue, but we couldn’t be more excited about the future prospects for x86, and for our AMD roadmap in that market."

AMD to Support BFloat 16

The industry has broadly adopted the Google-inspired BFloat16, a new class of numerical format that boosts performance for certain AI workloads. The industry is inexorably shifting to AI-driven architectures, and large hyperscalers have signaled that they require hardware that supports the new format. Papermaster revealed that AMD would support BFloat16 in future revisions of its hardware.

"We're always looking at where the workloads are going. BFloat 16 is an important approximation for machine learning workloads, and we will definitely provide support for that going forward in our roadmap, where it is needed."

On a Personal Note...

In a turnaround of fortunes that hardly anyone could have predicted several years ago, AMD has taken the process lead from Intel and has an innovative architecture that is pressuring its competitor in every segment the company competes in. We asked Papermaster if he personally thought the plan would be this successful when it was laid out four years ago. 

"We set out a roadmap that would bring AMD back to high performance and keep us there. It is independent of our competitors roadmaps and semiconductor node execution on 10nm. And we'll continue to drive our roadmap in that way. We called a play, we've been executing as we called it, and that's what you're going to see at AMD, just tremendous focus on execution. If we do that, then it is less about focusing on our competition, and about being the very best we can be with every single generation."

Papermaster has been at the helm of developing nearly all of AMD's newest technologies, so we asked what makes him the proudest about the turnaround: 

"It's the team at AMD. The AMD commitment to win is unsurpassed. We're a smaller player in the industry, and the company as a whole just punches above its weight class, if you were to make a boxing analogy. It's so exciting to be a part of that team and to see that personal dedication, that willingness to really listen to customers, understand what problems they want solved, and then go to the drawing boards and innovate and really surprise the industry."

"And then the other piece I'm proud of is that focus on that execution. It’s the ability to be a street-fighter, and then focus and hunker down and execute and deliver what we promised."

AMD on Thursday announced it has joined the Compute Express Link (CXL) consortium, the consortium for the PCIe 5.0-based cache-coherent interconnect, whose 1.0 specification Intel released in March with eight other founding members.

AMD is also a member of CCIX, Gen-Z and OpenCAPI.

In a blog post, Mark Papermaster, CTO and EVP of technology and engineering at AMD, said: “As a long-standing supporter of open standards, we’re excited to join CXL and the possibilities presented as we work with other ecosystem leaders to address challenges we face as an industry.”

With the addition of AMD, the CXL site now shows 55 public members of the consortium. Some of the most notable ones besides AMD include Alibaba, Broadcom, Cisco, Dell EMC, Facebook, Google, Mellanox (acquired by Nvidia), Microsoft, Western Digital and SK Hynix. Most surprising, perhaps, is the membership of Arm, which has its own CCIX interconnect.

With AMD being the 55th public member after roughly four months, this represents the fastest growth among the interconnect fabrics. It indicates that CXL is seeing strong adoption, at least on paper. This equals the member count of CCIX, which was announced in 2016. The Gen-Z consortium is still a bit ahead, listing 70 companies as member. However, it should be noted that not all companies might have publicly announced their membership. At least for CXL, Serve The Home noted in early May that 38 members were announced, but in fact had 57 members at the time. The 1.0 Specification of CCIX and Gen-Z were released in the first half of 2018. CCIX had 22 members after six months, while it took Gen-Z a year to reach nearly 50 members.

Intel announced CXL in March as its open cache-coherent interconnect, using the PCIe 5.0 physical link. The first announced product to support CXL was Intel’s Agilex FPGA. A few days ago, WikiChip's David Schor tweeted that start-up Ayar Labs, (which is also a CXL member), was collaborating with Intel to integrate its photonics chiplets with Agilex.

The consortium has also made available a Specification 1.1 Evaluation Copy.

Linux publication Phoronix spotted a few patches to the AMDGPU Linux graphics driver that are related to AMD's next-generation Arcturus graphics cards.

When AMD announced its latest Radeon DNA (RDNA) graphics card architecture at Computex 2019, the chipmaker made it very clear that it would co-exist along with the existing Graphics Core Next (GCN) architecture. The general consensus is that AMD would probably base its future gaming products around the RDNA architecture while relegating the GCN architecture exclusively to its workstation products. Therefore, Arcturus, not Navi, was Vega's successor all along.

Current AMD professional-grade offerings, such as the Radeon Pro Vega II, Radeon Instinct MI60 and Radeon Instinct MI50 employ the Vega 20 silicon, which TSMC produces for AMD on the 7nm manufacturing process. There's a high possibility that Arcturus will probably use a variation of the Vega silicon, and there is some evidence to support the rumor.

Phoronix previously discovered mentions of an unreleased AMD graphics card going by the "GFX908" ID. GFX9 is Vega and GFX10 is Navi. The Vega 20 die, in particular, has two IDs: GFX906 and GFX907. Assuming that GFX908 is Arcturus, it's definitely based on Vega, but with a small twist. We know from AMD's 2017 Financial Analyst Day slide presented by Mark Papermaster that the chipmaker's post-Navi graphics products will be fabricated under the 7nm+ process node. Up to this point, Arcturus seems to be a rewarmed Vega chip coming out of the 7nm+ microwave.

The Linux code shows up to three different device IDs so we could see at least three Arcturus models at launch. Twitter user 0x22h dug deeper into the Linux code and found out that Arcturus lacks display IP blocks, which means it's a pure compute graphics card making it akin to the Radeon Instinct models. We can expect the graphics card's feature set to include a benevolent amount of HBM2 memory, ECC (Error-Correcting Code) support, among other goodies. AMD currently utilizes Fiji, Polaris and Vega silicons for its Radeon Instinct graphics cards. Why the chipmaker is still selling Fiji-based products in 2019 is beyond us. Our guess is that Arcturus will most likely knock of the lower bound.

AMD could announce Arcturus at SIGGRAPH 2019 in July or Hot Chips in August. Either convention would be a great place to reveal an enterprise graphics card. As hinted in the AMD PowerPoint slide, Arcturus could launch next year.

AMD demoed its 7nm third-gen Ryzen chips and new 7nm Radeon VI gaming GPU at CES, but as with many new product announcements, we weren't given many details beyond the demos.

Luckily, we caught up with AMD Chief Technology Officer Mark Papermaster after the event. As expected, Papermaster couldn't share many of the fine-grained details we're searching for, but he did give us some insight into the basic design of the third-gen Ryzen processors and assured us that existing software will work fine with the new design.

AMD's first-gen Ryzen processors landed with a revolutionary new core design that initially led to lower-than-expected performance in some applications. Latency-sensitive applications (like games) suffered the most, but AMD made a concerted effort to arm software developers with the knowledge to tailor their code for the unique Zen microarchitecture, largely correcting the issue with the mainstream desktop chips. We asked Papermaster if those optimizations would carry over to the new third-gen Ryzen products that appear to have a more unique architecture.

"The optimization that we worked with the industry as we first rolled out Ryzen was our core complex," Papermaster said, "We very successfully worked across the OS, with Windows and Linux, so there is a recognition of AMD’s core complex, and so you can really have your workloads leverage that organization. As we go forward into this next-generation with Zen 2-based products, we actually just make it easier because as you have cores going into a common I/O die, it is the same core complex approach that we had before, and you actually just have a very centralized path. In our server implementation all the way through the Ryzen implementation we showed today, it adds no complication whatsoever for the software providers. All the work we did with first-gen Ryzen will carry right over. All those optimizations carry right over."

Papermaster's comments confirm that the company is still utilizing a core complex approach for the compute die, and although the company could have made adjustments to the architecture, his statement could give us a clearer image of the new design.

Third-Gen Ryzen Chip

As a quick refresher, the third-generation Ryzen processor comes with a multi-chiplet arrangement. This modular design consists of an eight-core 7nm chiplet (upper right) connected to a 14nm I/O die (left). The I/O die contains the memory controllers, Infinity Fabric links, and I/O connections. Aside from support for PCIe 4.0, AMD is still keeping details about the chips' resources close to the chest.

AMD is now using a second-gen Infinity Fabric to connect the compute die to the I/O die. This design helps AMD keep the areas of the chip that don’t scale well, like the memory controllers and I/O, on a proven and mature node, while also leveraging the performance, density and economic advantages of the 7nm node for the important compute functions.

We know that the new 7nm Ryzen compute die has eight cores, but it is logical to assume that it will be optimized to remove the resources that have moved to the new I/O die.

Here we see the current arrangement of AMD's Core Complex. AMD arranged the CPU complex (CCX) into four cores connected to a centralized 8MB L3 cache split into four slices. Each core also has a private 512KB L2 cache. AMD connects multiple CCXs together to create higher chips with higher core counts, such as the 8-core/16-thread (2 x CCX) first-gen Ryzen processors.

It's possible that AMD has increased the capacity of some of the caches, such as L1, L2, and L3, on the third-gen Ryzen chips, and/or adjusted the associativity of the caches, but we'll have to wait for further information. 

Zooming out, here we can see how AMD currently arranges the two Core Complexes onto a single Zeppelin die. Two CCXes (orange blocks in the center) come together to create an eight-core Zeppelin die, and they communicate via AMD’s Infinity Fabric interconnect. The CCXes also share the same memory controller. This is basically two quad-core CPUs talking to each other over the dedicated Infinity Fabric interconnect that also handles northbridge and PCIe traffic.

In the image above we can see a block diagram of the first-gen die, courtesy of WikiChip. With third-gen Ryzen, the DDR4 memory controllers, USB, SATA, and platform I/O units have now all migrated to the I/O die. Those adjustments should provide AMD with more density benefits on its small 7nm compute die as more of its area can be dedicated specifically to the eight cores. However, it remains to be seen if AMD will still use two separate four-core Core Complexes inside a single eight-core die, or if it will expand the core complex design to eight cores. AMD hasn't listed PCIe resources on its I/O die, implying those controllers could also remain on the eight-core compute die.

We also know that at least some form of the IFOP (Infinity Fabric On-Package) SerDes will have to be present on the new die, as these units facilitate communication with other die. Papermaster also told us that the company's next-generation Infinity Fabric would have improvements to its protocol and efficiency, with bandwidth and bandwidth-per-watt being key focus areas.

It's encouraging to hear that AMD's next round of Ryzen chips will not need specific new software enhancements to accommodate the design, as that was a key concern when the first-gen chips arrived. AMD has said that it will release the new third-gen Ryzen processors in mid-2019, which lines up nicely with Computex. As with AMD's previous big launches, we expect more information to come to light slowly in the intervening months as the company builds the hype for its newest round of processors.

AMD Radeon RX 590 8GB Review

AMD is finally echoing something we’ve been saying for months in our Best Graphics Cards for Gaming column: there’s a gaping hole between Radeon RX 580 and the Radeon RX Vega 56 in its line-up. The company’s Radeon RX 590 8GB is designed to fill that space using its first 12nm mainstream gaming GPU. Although this sounds promising, the new Radeon RX 590 is still based on AMD’s aging fourth-gen Graphics Core Next architecture. It sports the same list of on-board resources as last year’s Radeon RX 580 and 2016’s Radeon RX 480. In other words, all of the 590’s gains come from a higher core clock speed.

Cranking the dial on Polaris’ operating frequency isn’t free, though. Radeon RX 590’s official board power is 225W compared to the older 580’s 185W rating. At least on paper, that’s a 22 percent power consumption increase, enabling a 15 percent overclock, for what AMD claims is an up to 12 percent performance boost. Clearly, we’re at a point of diminishing returns for Polaris’ ability to scale up.

That doesn’t mute the significance of squeezing another couple hundred megahertz out of a mature graphics processor. Back when Radeon RX 480 launched, the chip had a boost specification of 1266 MHz. Today, the XFX Radeon RX 590 Fatboy 8GB OC+ we’re testing boosts up to 1580 MHz—a 25 percent increase from essentially the same chip. The one notable difference is a transition from GlobalFoundries’ 14nm FinFET process to a 12nm FinFET node.

Although AMD explicitly refused to discuss manufacturing beyond its mention of 12nm, CTO Mark Papermaster divulged the company’s plans to shift graphics and client products from 14nm LPP to 12nm LP in 2018 as far back as the GlobalFoundries Technology Conference in September of 2017. Then, in our Ryzen 7 2700X review, we noted that “…AMD's 2000-series CPUs are not manufactured on GlobalFoundries' 14nm LPP node, but rather its 12nm LP process technology. The ported-over design helps boost transistor performance, but does not affect die area or transistor density.”

This is consistent with Radeon RX 590’s Polaris GPU: despite its tweaked process, the official die size remains 232 mm². AMD claims this is to maintain compatibility with third-party motherboard and cooler designs. However, the deeper truth is that reoptimizing for an iterative manufacturing process would be prohibitively expensive, and not worth the potential gains. As such, we're probably seeing GlobalFoundries' 12nm LP process using the same 9T library as 14nm (rather than the new 7.5T library that the foundry says can lower power use by 16 percent at a given frequency). 

For now, enthusiasts must be satisfied with a minor manufacturing tweak that enables higher clock rates, overall better performance, but increased power consumption. And with a board power rating of 225W (higher than GeForce RTX 2080), performance per watt metrics won’t be pretty.

AMD is aiming the Radeon RX 590 at budget-minded gamers who missed the boat on add-in cards with 14/16nm GPUs, such as Radeon RX 480 and GeForce GTX 1060. That’d make their graphics subsystems more than two years old, and likely attached to 1920x1080 monitors. The company says cards should start in the $280 (£250) range, representing a $50 increase versus Radeon RX 580 last year. For a purported 12 percent speed up, that 22 percent price premium doesn’t scream value to us. But compared to the $700+ (£300) many Radeon RX 580s were selling for a year ago, $280 (£250) is downright palatable for smooth performance at 1920x1080 and playable frame rates at 2560x1440. What’s more, AMD has a launch bundle that includes Devil May Cry 5, Tom Clancy’s The Division 2 and Resident Evil 2. As far as bundles go, this is one of the better ones we’ve seen, though it’s unique in that none of those games will be available until early 2019.

The Polaris GPU, Reviewed

At its heart, the XFX Radeon RX 590 Fatboy 8GB OC+ we were sent for review sports some very familiar specifications. Its Polaris GPU contains 36 Compute Units, each CU encompassing 64 IEEE 754-2008-compliant shaders split between four vector units, a scalar unit and 16 texture fetch load/store units. Each CU also hosts four texture units, 16KB of L1 cache, a 64KB local data share, and register space for the vector and scalar units. A number of tweaks made back in 2016 carry over to the Radeon RX 590, yielding up to 15 percent more performance per CU than the Radeon R9 290X’s Hawaii GPU, which was based on a second-gen GCN architecture. Those improvements include the addition of native FP16 (and INT16) support, tuned cache access, and better instruction prefetching.

Nine CUs are organized into a Shader Engine, and Polaris boasts four such SEs, consistent with what we know to be the architecture’s maximum. The math (64 shaders * nine CUs * four SEs) adds up to 2304 Stream processors and 144 texture units.

Each Shader Engine is associated with a Geometry Engine, which AMD improved in the Radeon RX 480 days by adding a primitive discard accelerator for tossing primitives that won't rasterize to a pixel prior to scan conversion, thus increasing throughput. This is an automatic function of the graphics pipeline's pre-rasterization stage. There's also an index cache for instanced geometry, though we're not sure how large this is, or how significant its impact is when instancing is used.

Polaris is capable of up to four primitives per cycle. And of course, this latest iteration of Polaris has a base clock rate of 1469 MHz and a boost rating of 1545 MHz. Those amped-up frequencies compensate for lost on-die resources compared to previous high-end AMD GPUs. Whereas Radeon R9 290X offered 5.6 TFLOPS of single-precision floating-point performance and RX 480 reached up to 5.8 TFLOPS using its boost specification, Radeon RX 590 stretches up to 7.1 TFLOPS. Our XFX Radeon RX 590 Fatboy 8GB OC+ even shipped with a 1580 MHz boost setting, extending peak single-precision performance to 7.3 TFLOPS.

Approaching that theoretical ceiling requires sustaining aggressive clock rates, not hitting them and throttling back. On an open test bench, the Radeon RX 590 maintains its aggressive frequency thanks to cool ambient air. But as we'll see, once the card is buttoned up into a case, it bleeds off much of its advantage over Radeon RX 580.

AMD’s Vega GPU has four render back-ends per Shader Engine, capable of 16 pixels per clock (or 64 across the GPU). Polaris cut that figure in half. Two render back-ends per SE, each with four ROPs, total 32 pixels per clock. To compound matters, Polaris employs a 256-bit memory bus (versus Vega’s 2048-bit HBM2 interface). The 8GB model we’re testing today utilizes 8 Gb/s GDDR5 memory, driving up to 256 GB/s of throughput. That’s a long way from Radeon RX Vega 56’s 410 GB/s.

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Meet the XFX Radeon RX 590 Fatboy 8GB OC+

XFX uses technology from its Radeon RX 580 GTS Black Edition, saving the company from having to rework the Radeon RX 590 Fatboy 8GB OC+.

The new card weighs in at 1.89lb (856g). From the edge of its slot panel to the end of its fan shroud, we measure 10.6 inches (26.8cm). The heat sink assembly is 1.7 inches (4.3cm) deep. However, you have to add another 0.2in (0.5cm) to account for the backplate. This is a true 2.5-slot card, meaning it takes up three expansion slots on your motherboard. A 4.8-inch (12.2cm) measurement from where the card sits in a PCIe slot to the cooler’s top edge is actually pretty tall, dwarfing our Founders Edition GeForce and reference Radeon RX Vega cards.

From the bottom, it’s easy to see that XFX’s heat sink employs aluminum fins oriented horizontally. We approve, since heated air isn’t pushed down toward your motherboard and out against a case wall. Rather, some is exhausted out the expansion slot cover.

We also catch a glimpse of four heat pipes that sit flat over a copper plate and dissipate thermal energy through the sink’s fins.

Up top, there’s an eight- and six-pin power connector, cluing us in that a shrink to 12nm doesn’t translate to power-savings from Radeon RX 590. Again, AMD’s board power rating is 225W compared to Radeon RX 580’s 185W specification.

XFX loads the slot bracket with five display outputs: three DisplayPort 1.4-ready connectors, HDMI 2.0, and one DVI-D port. Although we appreciate copious connectivity, the DVI output does take up room that could have been freed up for exhaust.

With its heat sink removed, the Radeon RX 590 Fatboy 8GB OC+ looks almost identical to the Radeon RX 580 GTS Black Edition. Again, XFX uses six power phases for the GPU and one phase for memory.

There are hardly any components on the back side, except for two BIOS chips.

The following table lists the most important components on XFX’s PCB:

VRM6x IR3578 International Rectifier PowIRstage (High-side, Low-side, Schottky diode, driver)

Coils6x XL Ultra Low Noise Coils

Memory Power SupplyMemory Modules8x MT51J256M32HF-80:B Micron 8Gb GDDR5 Module (256Mb x32) 8.0 Gb/s at 1.5V

VRM1x IR3578 International Rectifier PowIRstage (High-side, Low-side, Schottky diode, driver)

Coils6x XL Ultra Low Noise Coils

Other ComponentsBIOS2x FM25Q02 EEPROM Dual BIOS

DIP SwitchPrimary/secondary BIOS

Smoothing1x 470mH coil per 12V supply connection

Cooler and Backplate

The hull-shaped backplate made of dark aluminum makes no contact with the board and doesn’t play a role in cooling. There are ventilation holes throughout, though, so at least the plate doesn’t trap heat underneath. The plate’s only purpose is to look good.

Because the backplate is screwed in from the PCB’s top side, the only way to remove it is disassembling the entire heat sink.

The cooler itself is a simple affair based on two 8mm and two 6mm heat pipes made of copper composite material. The pipes dissipate heat away from AMD’s Polaris chip and into a fin stack that spans both ends of the PCB. Underneath them is a thin copper plate that contacts the GPU die. A small frame surrounds the plate, sandwiching thermal pads between the metal and all eight memory modules.

This small thermal solution is tasked with removing as much as 250W from the board underneath. It’s more capable than AMD’s reference Radeon RX 480, but does reach its limit under load in a closed chassis.

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How We Tested the Radeon RX 590 and Ashes of the Singularity

Although we’re in the process of building up an Intel Core i7-8086K-based platform for high-end graphics card testing, the Radeon RX 590’s mainstream gaming status convinced us to let the old Intel Core i7-7700K at 4.2 GHz on the MSI Z170A Gaming M7 motherboard ride once more. The processor is complemented by G.Skill’s F4-3000C15Q-16GRR memory kit. Crucial’s MX200 SSD remains, joined by a 1.4TB Intel DC P3700 loaded down with games.

As far as competition goes, the Radeon RX 590 is preceded by AMD’s Radeon RX 580 (8GB) and AMD Radeon RX 570 4GB, so we test both of those models. Radeon RX Vega 56 is the next-fastest card from AMD, so we logically include it as well. The Radeon RX 580 already traded blows with Nvidia’s GeForce GTX 1060 6GB, so that board, along with GeForce GTX 1070 8GB make it into the test pool, too.

AMD didn’t create its own reference version of the Radeon RX 580 or 570, and it doesn’t have a reference Radeon RX 590 either. In their place, we’re forced to use Asus’ ROG Strix RX570 04G Gaming, Sapphire’s Nitro+ Radeon RX 580 8G and XFX’s Radeon RX 590 Fatboy 8GB OC+. The Radeon RX Vega 56 is AMD’s own design with a centrifugal fan, and the GeForce GTX 1060/1070 are both Founders Edition cards. Whenever possible, we use reference designs to avoid the varying shades of overclocking applied to partner cards. In this case, however, we have to fold in a few samples we wouldn’t normally include.

Our benchmark selection now includes Ashes of the Singularity: Escalation, Battlefield 1, Destiny 2, Far Cry 5, Grand Theft Auto V, Metro: Last Light Redux, Shadow of the Tomb Raider, Tom Clancy’s The Division, Tom Clancy’s Ghost Recon Wildlands, The Witcher 3, Wolfenstein II, and World of Warcraft: Battle for Azeroth.

The testing methodology we're using comes from PresentMon: Performance In DirectX, OpenGL, And Vulkan. In short, these games are evaluated using a combination of OCAT and our own in-house GUI for PresentMon, with logging via GPU-Z.

All of the numbers you see in today’s piece are fresh, using updated drivers. For Nvidia, we’re using build 416.81 for GeForce GTX 1060 6GB and 1070 8GB. AMD’s Radeon RX 570 4GB and 580 8GB utilize Radeon Software Adrenalin Edition 18.11.1, while the 590 8GB requires a special press build.

Ashes of the Singularity (DX12): 1920x1080 Results

Ashes of the Singularity (DX12): 2560x1440 Results

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Battlefield 1, Destiny 2, and Far Cry 5

Battlefield 1 (DX12): 1920x1080 Results

Battlefield 1 (DX12): 2560x1440 Results

Destiny 2 (DX11): 1920x1080 Results

Destiny 2 (DX11): 2560x1440 Results

Far Cry 5 (DX11): 1920x1080 Results

Far Cry 5 (DX11): 2560x1440 Results

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Grand Theft Auto V, Metro: Last Light Redux, and Shadow of the Tomb Raider

Grand Theft Auto V (DX11): 1920x1080 Results

Grand Theft Auto V (DX11): 2560x1440 Results

Metro: Last Light Redux (DX11): 1920x1080 Results

Metro: Last Light Redux (DX11): 2560x1440 Results

Shadow of the Tomb Raider (DX12): 1920x1080 Results

Shadow of the Tomb Raider (DX12): 2560x1440 Results

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Tom Clancy's The Division, Tom Clancy's Ghost Recon Wildlands, and The Witcher 3

Tom Clancy's The Division (DX12): 1920x1080 Results

Tom Clancy's The Division (DX12): 2560x1440 Results

Tom Clancy's Ghost Recon Wildlands (DX11): 1920x1080 Results

Tom Clancy's Ghost Recon Wildlands (DX11): 2560x1440 Results

The Witcher 3 (DX11): 1920x1080 Results

The Witcher 3 (DX11): 2560x1440 Results

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Wolfenstein II: The New Colossus and World of Warcraft

Wolfenstein II: The New Colossus (Vulkan): 1920x1080 Results

Wolfenstein II: The New Colossus (Vulkan): 2560x1440 Results

World of Warcraft (DX12):2560x1440 Results

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Power Consumption

This board’s 238W of power consumption in a gaming workload almost reaches the level of AMD’s Radeon RX Vega 56.

The 245W we measure during FurMark is ultimately only constrained by XFX’s power limit and the cooler’s inability to keep up. Spikes as high as 300W are downright unbecoming of a mainstream graphics card.

Voltage readings averaging 1.18V during our gaming sequence are right about what we expected. They remain consistent so long as the card isn’t thermally bottlenecked.

Load distribution between the rails is good, as our motherboard’s PCIe slot never even comes close to the maximum-allowed 5.5A. Compared to the first Polaris-based cards, which violated that limit, AMD clearly learned its lesson and is now configuring power consumption correctly.

The following graphs illustrate power consumption and current flow over time at idle, during a gaming test, and in FurMark.

Power Consumption Over Time

Current Over Time

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Temperatures, Clock Rates, and Infrared Measurements

Although the card’s clock rates on an open test bench look good, they break down once we install XFX's Radeon RX 590 Fatboy 8GB OC+ in a closed case. Our charts make it easy to see the connection between frequency and temperature in a real-world gaming sequence and FurMark.

For the power consumption we measured, XFX’s cooler really does seem to be a limiting factor. Something larger (and quieter) would have certainly helped. To be sure, a constant 1580 MHz is only possible in a really well-ventilated case.

Here’s what our results look like in table form:

The following images include infrared measurements from our gaming and FurMark loops, both on an open test bench and in a closed case. Differences between the two environments are readily apparent, especially since the cooler is operating at its upper limit.

Temperatures During Gaming

Temperatures During FurMark

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Fans and Noise

XFX’s semi-passive mode works as advertised. When the fans do spin up, they start in the 700 rpm range.

Faced with a real-world gaming workload, the fans gradually ramp up over 15 minutes to just under 2,000 rpm, maintaining a temperature just over 80 degrees Celsius. They don’t need to spin nearly as fast in an open case, where temperatures level off around 79 degrees Celsius.

There are no reserves to adjust the fans down a bit. Rather, you may feel compelled to turn them up for more cooling. Unfortunately, noise becomes an issue not long after.

Spectrum Analysis

The 38.1 dB(A) we measured is based on fans set to spin at 1700 rpm in a closed case.

To generate these images, we recreate the same conditions from our closed-case testing on an open test bench in a test chamber. Although the results don’t look bad, we’re able to identify several points along the spectrum with activity. First, we can see and hear the fans’ motor and bearing noises. Then, there’s high-pitched coil whine up at the top of the spectrum.

Since FurMark coaxes higher temperatures from the Polaris GPU using a more constant load, fan noise in the middle of our range is naturally quite a bit louder. Interestingly, there’s also a lot less buzzing from the coils.

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Conclusion

AMD launched its Radeon RX 480 as a 150W graphics card back in 2016. Pressure from Nvidia’s GeForce GTX 1060 just weeks later forced the company to repackage its Polaris GPU as Radeon RX 580, bumping power consumption up to 185W in the process.

More than a year later, motivated by the large price gap between Radeon RX 580 and Radeon RX Vega 56, AMD is re-repackaging Polaris as Radeon RX 590 to occupy some of that space. The company says it transitioned from GlobalFoundries’ 14nm FinFET manufacturing node to 12nm FinFET but won’t go into any more depth on the technology or its implications.

What we can see, however, are the benchmark results, power consumption measurements, value comparison, and efficiency calculation. Radeon RX 590 may benefit from a tuned process, but it’s still being flogged for a few percentage points of additional performance and sold at a higher price. It’s sucking down GeForce RTX 2080 power to generate frame rates between GeForce GTX 1060 and 1070. As a result, the Radeon RX 580 and 590 both look bad when we look at performance per watt.

Sure, $280 (£250) for Radeon RX 590 remains a relative bargain to shell-shocked gamers still reeling from the cryptocurrency bonanza that saw mainstream graphics cards selling for two or three times their original worth. In that context, you’re basically getting a great (guaranteed) overclock at a 25 or 30 percent premium over Radeon RX 580 8GB. But we’d just as soon save some money and buy the cheaper Polaris card for high-detail gaming at 1920 x 1080. After all, RX 580s are readily available for less than the price point AMD launched them at back in 2017.

It would have been super cool to see some sort of die-harvested Vega 48 with 3072 Stream processors for somewhere in the $300 range. Unfortunately, AMD’s Vega GPU and its expensive HBM2-equipped package presumably make such a project implausible.

And so, we’re left with Radeon RX 590 instead. It’s faster than GeForce GTX 1060 6GB across our suite at 1920 x 1080 and 2560 x 1440, which seems to have been AMD’s goal. However, when we comb over graphics card prices and compare their performance, the real winner today is Radeon RX 580 8GB. Ample performance for cranking up quality at 1920 x 1080 and post-crypto-crazy pricing combine for some of the best deals we’ve seen on mainstream gaming hardware in 2018.

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AMD and Xilinx partnered to create high-performance inference systems for data centers that Xilinx this week claimed breaks the world record for inference performance. The new systems include Xilinx’s new machine learning accelerator cards, called Alveo, which promise real-time machine learning inference, as well as video processing, genomics and data analytics.

A New Inference World Record

AMD and Xilinx created a new system for data centers that includes a 32-core EPYC 7551 CPU and eight Alveo U250 accelerator cards. The cards will be powered by Xilinx’s ML Suite, which also supports ML software frameworks, such as TensorFlow.

The two companies said that their system reached an inference throughput of 30,000 images per second on the GoogLeNet convolutional neural networks. Such high inference performance is seemingly being requested these days by companies that need to analyze massive amounts of data.

After joining Xilinx CEO Victor Peng onstage at a Xilinx event showcasing this, Mark Papermaster, AMD CTO and senior vice president of technology and engineering, said that new workloads can take advantage of the whole system and not just the CPU.

Xilinx Alveo Accelerator FPGA

Xilinx introduced two new FPGA cards (Alveo U200 and U250), which for the first time are optimized to “accelerate” real-time machine learning inference. The focus here seems to be “real-time” inference because the Alveo cards promise three times lower latency than GPUs with four times the throughput for low-latency applications.

The Alveo cards also promise 20x the performance of a CPU for inference tasks, reaching up to 90x the performance for database searches. They start at $8,995 each, and Xilinx said that it’s now working with OEMs, including Dell EMC, Fujitsu, Hewlett Packard Enterprise and IBM, to qualify them for data centers.

AMD has finally issued a full response to CTS Labs’ report that Ryzen and EPYC processors contain a total of 13 security flaws. Here’s the short version of the chipmakers’ response:

Exploitation of the vulnerabilities requires admin accessThe vulnerabilities have to do with firmware and chipsets, not the x86 architecturePatches are coming in the form of BIOS updates and firmware patches only--no microcode updates are required--via OEMs and ODMsAll issues will be addressed within “weeks,” but we strongly infer that AMD is aiming for 90 days or lessThere is no expected performance impact

The whole story was strange from the beginning. CTS Labs issued a red-alert type of report stating that AMD’s Ryzen and EPYC processors had numerous vulnerabilities, but it gave AMD just 24 hours to respond instead of the industry-norm 90 days. The firm also refused to release the full details of its findings, so only one entity--a security firm--was able to evaluate the assertions independently.

Some of the surrounding coverage that landed immediately after the report was issued made the whole thing feel like a hit piece on AMD’s stock price. Further, no one had ever heard of CTS Labs before. Subsequent interviews that CTS Labs gave the press (including Tom’s Hardware and AnandTech) seemed to cloud things even more.

Having only CTS Labs’ own whitepaper on the subject to work from, we broke down the security flaws as much as we could here.

Although we still do not have access to the actual details of the vulnerabilities, we now, at least, have AMD’s response. It’s short and to the point.

In the post, AMD’s Mark Papermaster wrote in part:

The security issues identified by the third-party researchers are not related to the AMD “Zen” CPU architecture or the Google Project Zero exploits made public Jan. 3, 2018. Instead, these issues are associated with the firmware managing the embedded security control processor in some of our products (AMD Secure Processor) and the chipset used in some socket AM4 and socket TR4 desktop platforms supporting AMD processors.

Papermaster also addressed the access issue--that is, in order for the vulnerabilities to be exploitable, one would need metal access. He stated:

Further, all modern operating systems and enterprise-quality hypervisors today have many effective security controls, such as Microsoft Windows Credential Guard in the Windows environment, in place to prevent unauthorized administrative access that would need to be overcome in order to affect these security issues.

CTS Labs has made it seem as though an enterprise-level threat is a real possibility, but when AnandTech pressed the issue, CTS Labs clarified:

To be honest with you, in that particular situation [running a virtual machine on a server], the vulnerabilities do not help you very much. However if a server gets compromised and the cloud provider is relying on secure virtualization to segregate customer data by encrypting memory, and someone runs an exploit on your server and breaks into the SP, they could tamper with this mechanism and this mechanism.

Note that in AMD’s response, it condensed CTS Labs’ four threat categories into three. In all three, AMD stated that admin access is required, and all the attacks would require that the system’s security has already been compromised.

Expect all patches to arrive via AMD’s ODM and OEM partners within the next 90 days.

At the Global Foundries Technology Conference, AMD’s CTO Mark Papermaster announced that the company will be transitioning “graphics and client products” from the Global Foundries 14nm LPP FinFET process it uses today to the new 12nm LP process in 2018. Global Foundries also announced that 12LP will begin production in 1Q18.

We followed up with Papermaster in person and confirmed directly that the company will transition both Vega GPUs and the Ryzen line of processors to the 12nm LP process. However, it’s still not clear whether or not he meant that 12nm LP will be a shrink of Ryzen in 2018 (a "tick" equivalent if you will) or if Zen+/Zen 2 will also be using the 12LP process. Previously, AMD has implied that Zen 2 will use the 7nm process. The company has used both "Zen+" and "Zen 2" to refer to its next-generation die.

We expected AMD's next-generation 7nm Zen products to slug it out with Intel's 10nm Ice Lake processors next year, but it appears we will see 12nm LP against Intel's 10nm instead.

Earlier, we learned from Raja Koduri's letter to his team that we should expect "new wave of product excitement" in early 2018, which implies that is when we might see the first news of Vega with the 12nm LP process to emerge.

Nvidia’s Volta architecture is already shipping on TSMC’s 12nm FFN process this year, so on the GPU side Nvidia seems to be ahead on adopting new process technology right now. Of course, on the CPU side we also have Intel, which promised “real” 10nm chips for next year that should also be significantly ahead in performance and power efficiency compared to the 12LP process.

However, this is nothing really new, as Intel has been ahead in process technology for quite some time, and if anything, third-party foundry companies such as Samsung/Global Foundries and TSMC have closed the gap a little once they adopted the FinFET structure for their transistors. AMD's relatively quick transition to the 12nm LP processor is vital for the company as it seeks to compete with Intel's Coffee Lake processors and Nvidia's Volta GPUs.

MORE: Everything Zen: AMD Presents New Microarchitecture At Hot Chips

The transition to 12nm LP also reaffirms AMD's commitment to its partnership with Global Foundries. The companies signed a five-year wafer supply agreement recently, but there has been speculation that AMD might seek other partners for its forthcoming product generations.

We're digging in deeper for more information and will follow up as required.

AMD announced the acquisition of Nitero, a fabless semiconductor company based out of Austin, TX that developed a phased-array beamforming millimeter wave chip for VR headsets.

Although the terms of the acquisition were not made public, we do know that the deal not only includes Nitero’s wireless virtual reality IP, but all its employees as well. The company's co-founder and CEO, Pat Kelly, will join AMD as Corporate Vice President, Wireless IP.

Demand for wireless VR and AR headsets is on the rise, so it only makes sense that a company as heavily invested in virtual reality as AMD would make a move like this. Mark Papermaster, AMD’s chief technology officer and senior vice president, said in a press release:

Unwieldly headset cables remain a significant barrier to drive widespread adoption of VR. Our newly acquired wireless VR technology is focused on solving this challenge, and is another example of AMD making long-term technology investments to develop high-performance computing and graphics technologies that can create more immersive computing experiences.

The press release went on to state that, by using high-performance 60GHz wireless, Nitero's phased-array beamforming millimeter wave chip has the potential to enable multi-gigabit transmit performance with low latency in room-scale VR environments without the line-of-sight requirement associated with traditional high-frequency millimeter wave systems.

There is no question that the industry is moving away from traditional tethered VR HMDs. You could look no further than John Carmack's comments at OC3 paired with Oculus' wireless Rift protoype, but there's plenty more happening. Late last year, we reported on a company called Quark VR that is building a wireless system for the Vive, and we also spent some time with the wireless upgrade kit from TPCAST back in November. DisplayLink is working on wireless HMD technology, and so is KwikVR. We recently spent time with Sixa's wireless Rivvr HMD kit, too. Even MIT is in on the action.

Let us not forget that Intel, one of AMD’s largest rivals, is also experimenting a wireless VR headset system.

Although AMD hasn’t shared its plans for its newly acquired IP, it’s safe to say that it will be interesting to see how the company integrates this technology into future products.

AMD announced that three of its top executives are leaving the company, a few months after new CEO Lisa Su took over and started reorganizing. The departing execs include John Byrne, former General Manager for AMD's computing and graphics group; Colette LaForce, the company's Chief Marketing Officer; and Rajan Naik, the Chief Strategy Officer.

An AMD spokesperson said in a statement that the three executives are simply looking for new opportunities, although it seems like the new AMD CEO wants some fresh thinking that can turn AMD around.

“These changes to the leadership team reporting into our CEO are a part of implementing an optimal organization design and leadership team to drive AMD's future growth."

AMD's revenue has been declining for the past few quarters, even though AMD managed to win contracts for the chips inside the Playstation 4 and the Xbox One consoles a little more than a year ago, which should have brought the company a significant increase in sales. However, AMD's PC and server businesses are not doing so well lately and are dragging the company's total revenue down.

AMD saw a 65 percent profit drop in its third quarter last year, followed by a 13 percent revenue drop in the next quarter, while Wall Street analysts were expecting the company's revenue to be flat or slightly higher than before.

Lisa Su, the new CEO, has already started hiring new executives such as Forrest Norrod from Dell and James Clifford from RF Micro Devices. AMD has also given two of its Senior VPs, Mark Papermaster (former Senior VP for Devices Hardware Engineering at Apple) and Devinder Kumar, its current CFO, retention stock awards to keep them around.

AMD suffers from multiple problems that work against the company's success, from having a less powerful single-thread CPU micro-architecture than Intel, to using much older process nodes to build its chips, to having financial troubles that don't allow the company to invest in the research it needs to catch up to (or even surpass) Intel.

Turning the company around would be difficult for any CEO. AMD does have a new CPU micro-architecture in the pipeline, along with a new GPU architecture, and it may even start using more cutting-edge process nodes soon that should shrink the gap in performance and power consumption between its processors and Intel's chips.

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AMD has confirmed that it has hired on Raja Koduri, a former director of graphics architecture at Apple. He will be rejoining AMD after leaving the company four years ago, and will assume a role in AMD's graphics business as corporate vice president, Visual Computing. He will be reporting to Mark Papermaster.

“Maintaining AMD’s position as a leader in visual computing is the key to our long-term success. As one of the industry’s foremost experts in developing leading-edge visual computing solutions, Raja brings exceptional vision and strength to AMD’s world-class engineering leadership team,” said Papermaster. “Given his past record of success, Raja will help AMD lead the way in visual and accelerated computing and ensure we continue developing the industry-leading graphics IP that forms the foundation for our future growth.”

Koduri began his career serving as Director and Engineering Manager at S3 Inc., and then moved on to ATI Technologies as the Director of Advanced Technology Development in 2001. Naturally he was assimilated into the AMD collective when the company acquired ATI in 2006, and eventually moved up the corporate ladder as the chip giant's Chief Technology Officer of the Graphics Product Group before leaving in 2009.

Apple reportedly hired Koduri as part of the company’s push to build up its own chip operations. Rather than rely on partners like Intel to design SoC's for its tablets and smartphones, the company began creating its own chips.

After departing Apple earlier this year, Koduri served as Technical Advisor to the Board of Directors at Makuta VFX. This company is described as "a fully-fledged visual effects facility covering a full gamut of requirements from active on-set visual effects supervision through to immersive digital set extension, digital matte painting, high-end feature animation and effects work, clean-up, motion tracking and final compositing."

AMD and Apple have seemingly been tossing executives back and forth over the past few years. In August 2012, AMD named Jim Keller as its Corporate Vice President and Chief Microprocessor Architect. He previously served as a director in Apple's platform architecture group, and even worked for AMD prior to that. Keller now reports to former Apple hardware chief Mark Papermaster. The previous hardware chief was John Bruno who left AMD for Apple.

According to the report, AMD had courted Koduri for some time, wanting him to return to the company. Koduri and Keller efforts at Apple complimented each other, and will likely continue with both under the same AMD roof. Their expertise will reportedly help accelerate AMD's System-On-A-Chip strategy of cramming all the features it can onto a single central chip.

AMD reported a narrower first-quarter loss on Thursday, but its revenue dropped a huge 31-percent in a year-over-year comparison. To combat the slump in sales, the company has laid off a large portion of its staff and restructured its relationship with Globalfoundries. However in its report the company highlighted the announcement of Sony's APU-powered PlayStation 4, the Never Settle: Reloaded program, Radeon Sky Graphics, among others.

We’ve just received word from AMD that Eric Demers, the company's former corporate vice president and CTO of its graphics business unit, has decided leave his post to pursue other opportunities.

AMD CTO Mark Papermaster, who has bounced from IBM to Apple to AMD, assumes interim responsibility for the graphics business unit role until a replacement is found.

"AMD remains fully committed to our critical graphics IP development and discrete GPU products.  We have a tremendous depth of talent in our organization, a game plan that is resonating with our customers and our team, and we are continuing to bring graphics-performance-leading products to market.  We will attract the right technology leader for this role," AMD said in a statement. "We thank Eric for his contributions to the business and wish him well in his future endeavors."

_{Read more from @MarcusYam on Twitter.}