Lumentum CEO Michael Hurlston told an audience at the RAISE Summit in Paris earlier this month that indium phosphide, the compound semiconductor behind every laser in an AI data center, is heading into a supply squeeze worse than what we've already seen with DRAM / NAND, and that Nvidia's decision to fund Lumentum and its biggest competitor at the same time was a response to exactly that.

In his remarks, Hurlston said that telecom customers bought lasers in the hundreds, while Nvidia and the hyperscalers are asking for hundreds of millions. While Lumentum runs five indium phosphide fabs, it's still shipping more than 30% below what customers want. Nvidia's answer, in March, was to write $2 billion checks to Lumentum and Coherent, the two suppliers that, between them, make most of the world's high-speed datacom lasers, with purchase commitments and future capacity access attached to both.

"Between the two of us, I don't think we can service the demand that Nvidia and others are now putting on us to solve this resistance problem in the data center," Hurlston added.

Silicon doesn't emit light

Indium phosphide has a direct bandgap of roughly 1.34 eV, which lets it convert electrical current into photons efficiently. Silicon's bandgap is indirect, so it can guide, split, and modulate light but can't generate it. Every silicon photonics platform in production, including those of Nvidia, Broadcom, Marvell, and Cisco, still needs an indium phosphide laser somewhere in the package to supply the light for silicon to manipulate. Moving from pluggable transceivers to co-packaged optics changes where that laser sits and how it's mounted, but it doesn't remove it from the bill of materials.

Nvidia's marketing claims its photonics switches use four times fewer lasers than an equivalent pluggable deployment, alongside 3.5 times better power efficiency and ten times better network resiliency, all of which are vendor figures. Those savings are per port, and it's that port count that's exploding.

The high-end Spectrum-X Photonics configuration runs 512 ports at 800 Gb/s for 400 Tb/s of switching, and Quantum-X Photonics InfiniBand runs 144 ports at 800 Gb/s. Co-packaging also shifts the laser type toward high-power continuous-wave sources and external laser modules that feed multiple channels, which are harder to build than the electro-absorption modulated lasers inside a conventional pluggable. Coherent's Nvidia agreement covers that category of high-power CW lasers, external laser source modules, and fiber array units.

Capacity at Lumentum and Coherent

Lumentum posted record revenue of $808.4 million in its fiscal third quarter, up 90% year over year, with components revenue of $533 million and pump laser shipments up 80%. On the May earnings call, Hurlston told analysts the company expects its supply line to increase 50% measured from one December quarter to the next, and in the same breath said the supply-demand imbalance on EMLs had widened from the 25% to 30% given a quarter earlier to "somewhere greater than 30%," with pump lasers tighter still. A supplier growing output by half a turn per year and losing ground anyway is a clean measure of how steep the demand curve is.

Coherent's 6-inch indium phosphide line yields more than four times as many devices as its 3-inch line at less than half the cost, CEO Jim Anderson told investors on the company's fiscal Q3 call. Anderson said EMLs, CW lasers, and photodiodes are all in production on the 6-inch line with yields above the legacy 3-inch lines, and that internal capacity would double by the end of the June quarter, one quarter ahead of plan, then more than double again by the end of 2027. Coherent's revenue hit a record $1.8 billion, up 21%, with data center and communications now 75% of the total against roughly 41% a year earlier, and backlog stretching into 2028.

Logic and memory moved to 300mm wafers in the early 2000s. Indium phosphide is a brittle, expensive, small-boule material where the industry-wide upgrade currently underway is 3-inch to 6-inch, roughly the transition silicon completed in the 1980s. Lumentum's fifth fab, announced in March, is a converted Qorvo gallium arsenide plant in Greensboro, North Carolina, described as 4-inch and 6-inch compatible and ramping around 2028.

Running through China

Indium is recovered as a byproduct of zinc refining, so its output can't be scaled independently of zinc economics, no matter how much laser demand there is. The USGS Mineral Commodity Summaries 2026 put China at an estimated 760 tonnes of roughly 1,100 tonnes of global primary refined indium in 2025, about 69%, and recorded a 72% year-over-year fall in unwrought indium exports between September 2024 and September 2025 after Beijing placed the metal under export controls in February last year. The U.S. warehouse price averaged about $390 per kilogram in 2025 against $340 in 2024.

AXT's Chinese subsidiary Tongmei had to obtain Ministry of Commerce export permits, granted in June and August 2025, before it could resume shipping indium phosphide substrates out of China. The fabs Nvidia is funding sit downstream of that licensing regime, and the wafers going into them aren't made in the United States in meaningful volume.

DRAM contract prices rose 90% to 95% quarter over quarter in Q1 2026, the largest quarterly increase TrendForce has recorded, and the firm forecast a further 58% to 63% in Q2 with NAND up 70% to 75%. HBM is sold out for 2026. Hurlston is measuring his warning against a genuinely historic crunch, which makes it a strong claim rather than a throwaway one, and he runs a company whose valuation depends on the shortage persisting.

LightCounting's April 2026 market forecast puts current transceiver demand about 30% above supply, matching Lumentum's own figure, but states that the shortages should be gone by the end of 2026 and cuts expected Ethernet transceiver growth to 65% for the year after 82% in 2025 and 93% in 2024. Coherent, hitting its capacity doubling a quarter early, points the same way. The distinction from memory is that the fix here is a wafer-size transition already running in production with yields ahead of the old node, not a new fab that takes three years to build.

Tower Semiconductor has announced a dual-track expansion of its 300mm silicon photonics, silicon germanium, and advanced packaging operations in Japan, committing up to $3 billion net of grants with backing from the country's Ministry of Economy, Trade and Industry (METI). Alongside the announcement, the Israeli specialty foundry raised its 2028 business model to approximately $3.6 billion in revenue and $1.2 billion in net profit, and it says those targets rest entirely on the first of the plan's two tracks: reviving the shuttered Arai fab it inherited from Panasonic and maximizing its running 300mm fab in Uozu, Toyama Prefecture.

Two tracks, one committed

Track One converts the former Arai facility, designated Fab 6, into a 300mm silicon photonics and advanced optical packaging plant while expanding output at Fab 7 in Uozu, with full production readiness expected during the fourth quarter of 2027. The Arai plant ceased operations in July 2022 because it exclusively served Nuvoton Technology Corporation Japan (NTCJ) rather than Tower's foundry customers, according to Tower's SEC filings, leaving an intact fab shell sitting idle for four years.

Track Two calls for constructing a new 300mm fab adjacent to Fab 7, which Tower says would deliver a multi-fold increase in silicon photonics and silicon germanium capacity and become "highly accretive beginning in 2029." The company hasn't signed definitive agreements for it, however, and none of the new 2028 targets depend on it.

A restructuring of the TPSCo joint venture, announced in March 2026, cleared the way for all this. Tower entered Japan in 2014 by buying 51% of Panasonic's three-fab semiconductor manufacturing operation, and Panasonic sold its remaining stake to Nuvoton in 2020. Under the March agreement, Tower takes full ownership of the 300mm Fab 7, while NTCJ absorbs the 200mm operations and pays Tower $25 million, with closing expected on April 1, 2027. Sole ownership of Fab 7 removed the joint-venture structure that would have complicated a $3 billion buildout.

Tower CEO Russell Ellwanger contrasted the approach with greenfield construction and fab acquisitions, which he said typically require years of process development, customer qualification, and financial stabilization while ramping from zero revenue against high fixed costs. Reusing a dormant building next to a qualified, cash-generating photonics fab is why Tower can achieve production readiness roughly 18 months ahead; Rapidus, by comparison, broke ground on its greenfield Chitose site in September 2023 and doesn't expect mass production until 2027.

29% increase in revenue

Tower reported $1.566 billion in revenue and $220 million in net profit for 2025, up from $1.436 billion and $208 million in 2024. The new 2028 model more than doubles 2025 revenue and implies a net margin of around 33%, against roughly 14% today. Measured against the prior 2028 model of $2.8 billion in revenue and $750 million in net profit, which Tower reaffirmed in its Q1 2026 report in May, the new targets add 29% to revenue and 60% to net profit.

Silicon photonics revenue is doing most of the heavy lifting, with Ellwanger telling analysts on the company's Q4 2025 earnings call in February that silicon photonics revenue reached $228 million in 2025, up from $106 million in 2024, and hit a $380 million annualized run rate in the fourth quarter, a figure he noted includes some non-wafer engineering revenue. In May, Tower disclosed $1.3 billion in contracted silicon photonics revenue for 2027 from its largest customers, backed by $290 million in prepayments already collected.

Tower's photonics customer roster includes Innolight, which builds 400G, 800G, and 1.6T optical transceivers on Tower's PH18 platform family, and Marvell, which said in June it had shipped more than five million coherent photonic ICs manufactured with Tower. The company claims more than 50 active silicon photonics customers and supplies foundry capacity for 200 Gb/s-per-lane devices used in 1.6T transceivers.

Tower's forward-looking disclosures flag construction delays, equipment lead times, permitting, and METI grant covenants that "may result in loss of a portion or all of the grant funds." The implied margin expansion also assumes sustained AI and data center optics demand from a concentrated group of very large customers through 2028, a dependency Tower acknowledges.

Tower’s position in the photonics foundry race

GlobalFoundries paid $453 million in cash for Singapore's Advanced Micro Foundry in November 2025, according to its annual report, a deal the company said made it one of the largest silicon photonics manufacturers. TSMC's COUPE co-packaged optics platform is tracking Nvidia's optical interconnect roadmap, with 1.6 Tb/s optical engines arriving in 2026 products.

Tower occupies a different lane from TSMC, as a merchant foundry serving dozens of transceiver makers and chip designers, rather than a packaging platform aligned with one customer's rack-scale plans. GlobalFoundries competes with Tower far more directly, and the two are also in court, with GlobalFoundries pursuing patent infringement claims against Tower.

MarketsandMarkets estimates the silicon photonics market at $2.65 billion in 2025, growing to $9.65 billion by 2030 at a 29.5% compound annual growth rate. Demand for optical data movement in AI clusters underpins those forecasts, as interconnects shift from copper to light at 800G and 1.6T speeds.

METI's support for Tower joins a Japanese subsidy program that has committed up to ¥1.2 trillion to TSMC's JASM fabs in Kumamoto, roughly ¥536 billion to Micron's Hiroshima operations, and around ¥2.9 trillion in planned funding for Rapidus. Tower's award appears to be the program's first at this scale for a dedicated silicon photonics foundry.

Intel agreed to buy Tower for $5.4 billion in 2022, but abandoned the deal in August 2023 after Chinese regulators declined to approve it, paying Tower a $353 million termination fee. The Japan program is the largest capital commitment in Tower's history, well beyond the up-to-$300 million arrangement it struck with Intel in September 2023 for 300mm capacity in New Mexico. Three years after nearly becoming an Intel subsidiary, Tower is building its own flagship instead.

Researchers from Osaka Metropolitan University have developed a programmable thermal device that can control where heat is radiated while remembering its configuration even after power is removed, a capability that could one day contribute to smarter thermal management in high-performance chips, silicon photonics, infrared sensors, and energy-harvesting systems. The work, published in Laser & Photonics Reviews, overcomes two longstanding obstacles that have prevented the practical realization of nonreciprocal thermal devices.

The device combines a magneto-optical material — a material that changes its optical properties in the presence of a magnetic field — with a phase-change material known as germanium-antimony-tellurium (GST) to independently control how a surface absorbs and emits infrared radiation. Unlike previous designs that lost their functionality once power was removed or only worked when light struck the surface at extreme angles, the researchers say their device operates almost straight on while retaining its programmed state without continuous energy input.

Under normal circumstances, materials follow a principle stating that if a surface efficiently absorbs heat at a particular wavelength and direction, it must also emit heat equally well under the same conditions. This relationship, defined by Kirchhoff's law of thermal radiation, holds for conventional materials and limits how precisely engineers can manipulate heat. Rather than directing thermal energy where it is most useful, these materials simply emit heat based on how they absorb it.

Circumventing this relationship has become an active area of research, as it could give engineers an entirely new way to control thermal energy. Devices capable of independently steering absorption and emission could improve radiative cooling, thermophotovoltaic systems that convert heat into electricity, infrared sensing, thermal communication, and other photonic technologies where controlling heat is just as important as controlling light.

Researchers have explored several ways to achieve this by breaking Lorentz reciprocity, the physical principle that links incoming and outgoing electromagnetic waves. Most approaches rely on magneto-optical materials, magnetic Weyl semimetals, or actively modulated metasurfaces. However, these designs have generally encountered two major problems. First, they require light to strike the surface at very oblique, or grazing, angles to produce strong directional behavior. While this works experimentally, it significantly reduces the amount of usable thermal radiation and produces broad, inefficient emission patterns. Second, many existing designs are volatile. Their behavior disappears as soon as the magnetic field, electrical signal, or heating source controlling them is removed, making continuous power necessary simply to maintain their operating state.

The Osaka Metropolitan University team tackled both limitations by combining two materials that perform complementary roles. The first is indium arsenide (InAs), a magneto-optical semiconductor whose interaction with infrared light changes in the presence of a magnetic field. Rather than allowing light to behave identically in all directions, the material introduces a directional asymmetry that enables nonreciprocal thermal behavior. The second ingredient is GST, a phase-change material that can reversibly switch between amorphous and crystalline states, dramatically changing its optical properties while retaining whichever state it is written into, even after power is removed.

The researchers patterned GST into a microscopic grating above the InAs layer, forming what they describe as a magneto-optical metagrating. The InAs provides the directional control needed to separate heat absorption from heat emission, while the GST layer acts as a non-volatile switch that stores the device's operating mode. Applying a magnetic field tunes how infrared radiation interacts with the structure, while changing the phase of the GST permanently alters that behavior until it is intentionally rewritten. In effect, the device can be programmed to emit heat differently and retain that configuration without requiring continuous energy.

According to the researchers, the prototype achieved a nonreciprocity factor approaching 0.9 while operating at an incidence angle of just three degrees, much closer to normal incidence than the steep angles typically required by previous designs. The system also supports continuous tuning via changes in the magnetic field or incident angle, as well as digital on-off switching via the GST phase transition. The team further analyzed why the nonreciprocal effect weakens when GST changes state, concluding that the reduction results from a combination of optical field redistribution and increased damping rather than simple absorption losses alone.

Although the technology remains an early-stage research demonstration, the ability to program thermal radiation could eventually become valuable in computing hardware as processors continue to pack more transistors, chiplets, and photonic components into increasingly compact packages. Future thermal metasurfaces could give engineers another tool for directing heat away from hotspots, reducing thermal interference between neighboring chiplets, or stabilizing silicon photonic devices whose optical characteristics shift with temperature.

Beyond computing, the researchers also envision applications in radiative cooling, thermophotovoltaic energy conversion, infrared emitters, thermal communication systems, and photonic memory technologies. For now, however, the work remains a laboratory demonstration rather than a deployable technology. Considerable engineering challenges remain before programmable thermal emitters find their way into commercial electronics.

This article is part of a series documenting quantum computing technologies and their ecosystem – the differing approaches, the key players behind them, and the key technologies that are driving us towards a quantum future. Part one looked at superconducting qubits (materialized in key industry giants such as IBM and Google) and trapped ion qubits (through IonQ and Quantinuum).

In this second part, we’ll be looking at quantum photonics – a light-based technique of defining the quantum unit of computation, the qubit. We’ll take a brief look at the what and the why of quantum photonics, and then materialize it by focusing on two particular companies, their roadmaps, and their technologies: Toronto-based Xanadu Quantum Technologies (which is making a play for public Nasdaq listing this first quarter of 2026 at an estimated 3.6B$ enterprise valuation through a SPAC deal); and the Palo Alto, California-headquartered PsiQuantum (PSIQ.PVT, with an estimated 7B$ valuation buoyed by a 1$ billion worth Series E funding round in late 2025).

Like our previous roadmap analysis, this won’t be a technical article; it’s a technology and roadmap analysis that brings understandable bites on the underlying technologies, their roadmap evolution, current state, and expected next steps. For a better understanding of what quantum computing is all about, Tom’s Hardware has a more explanatory quantum computing article you can familiarize yourself with first.

What is Quantum Photonics?

To answer what quantum photonics actually is, we have to start with the most basic: photonics is the use of light to transmit encoded information. The most widespread application of photonics that’s already a part of our infrastructure today materializes through fiber optic cables: within them, light travels at its speed (which matters for latency) and crucially, without energy losses to electrical resistance.

Because light can contain multiple wavelengths (think colors, ranging through the visible spectrum and beyond), information in fiber optic cables can be encoded in multiple paths within the same ray (a technique known as multiplexing) for increased bandwidth.

This classical approach to photonics uses billions of photons (the essential unit of light) in coherent beams, using other elements such as phase and polarization as data carriers. Classical photonics is already a well-known quantity, with multiple applications in both intercontinental information transit, data center interconnects, and more specifically, inter-chip communication.

The transition towards the quantum realm occurs when you stop looking at light as a beam and focus on the singular elements that compose it: photons. Quantum photonics, then, makes use of single-photon sources and single-photon detectors to encode and decode information through the specific strengths of quantum properties: entanglement (where two entangled photons become a coherent system) and superposition (where the universe of possible information values can be contained in a single qubit until interfered with).

This brings us to the great differentiator in current quantum photonics: the way operations are run on individual photons, and how information is encoded within them. PsiQuantum uses what’s known as a dual-rail encoding approach: informational states are derived from looking at a photon’s “choice” between path A (0) and path B (1) (these paths being known as waveguides). Xanadu approaches it through the lens of continuous-variable encoding: instead of looking at the photon itself, it looks at the photon’s light field and how it’s distributed (across properties like amplitude and phase), ‘squeezing’ them (reducing uncertainty in the amplitude variable at the cost of increased uncertainty in phase) to encode data.

These are two fundamentally different ways of obtaining the result of a photonics-based, large-scale, error-corrected quantum computer, each with its own set of engineering problems. The end-goal, however, is the same: when you can generate, manipulate, and measure individual photons, light stops being a mere transmission medium, and individual particles become the computational substrate itself.

Advantages, challenges, and the mechanics of photonic qubits

Quantum photonics is claimed to have some operational advantages over other approaches: unlike superconducting qubits, photons can be operated on at room temperature, theoretically reducing both installation, running, and maintenance costs.

The natural physical makeup of photons also means that photonic qubits are less susceptible to environmental interference, such as electromagnetic noise and thermal fluctuations. Scaling-wise, photonics-based chips can leverage semiconductor manufacturing infrastructure, and the natural speed of light means that gate times (gate operations being the result of inter-qubit operations towards a useful result) should have a higher operational limit compared to other approaches, such as trapped ions.

There’s always an opportunity cost in each quantum approach, however. In PsiQuantum’s dual-rail approach, identical photons that can be reliably entangled are very hard to generate: minute differences in wavelength, polarization, and spatial modes destroy systemic equilibrium and reliability. Photon generation (which is usually accomplished by shining a laser through a crystal) is a probabilistic operation: sometimes no photon is generated; sometimes, one is; and sometimes, more than that.

All of this leads us to the harsh truth that in quantum photonics - particularly in its dual-rail design - it’s easy to lose more than 90% of the generated photonic qubits (at generation or collection) before they ever get a chance to perform a useful computation. This means that to generate a 100-qubit photonic system, upwards of 10,000 photons must be generated. Everything else is lost.

PsiQuantum’s way of operating on individual photons means there’s no informational backup, such as what you’d get when operating on classical light beams: when the photon is lost, everything is. You can amplify billions of photons when they are a beam, but you can’t do the same for a single photon (a quirk of quantum mechanics known as the no-cloning theorem). And being incredibly small particles, a minute error in the photon’s directionality means that the emitted particle can easily fail to be detected on the other end (think of how a small angular difference at a bullet’s exit compounds on missing the bullseye).

Xanadu’s approach, on the other hand, sidesteps the requirement for photonic “perfection” at generation and is more tolerant to photon loss (the light fields don’t completely vanish on individual photon loss). But it does introduce different error correction challenges – errors are continuous (noise is present in amplitude and phase measurements), while PsiQuantum’s issues are discrete (photon present vs photon absent, resulting in discrete bit flips in calculations).

Clearly, the base technology of photonics can serve very different approaches. PsiQuantum bets that silicon photonics manufacturing can overcome the drawbacks of their dual-rail approach through scale and engineering precision to reduce errors and improve photon measurement reliability, while Xanadu’s intrinsically higher tolerance to process imperfections enables a faster timeline to quantum advantage, or so they hope.

Xanadu's approach

Founded in 2016, Xanadu’s declared mission is to build a fault-tolerant photonic quantum computing datacenter in the early 2030s. To do that, the company has been developing a particular qubit concept pioneered as early as 2001 – GKP qubits. Xanadu is seemingly keeping its cards close to its chest when materializing expectations in roadmap form.

What Xanadu does is declare its innovations through scientific publications and post-facto announcements on executed milestones, defining its fault-tolerant target architecture design as early as 2020. This happened in tandem with the company’s first quantum device demonstration, which occurred by Fall 2020 with its X8 photonic chip – a 4mm x 100mm 8-qubit device fabricated on a silicon nitride process. The blueprint for their fault-tolerant quantum future was thus laid out.

By June 2022, the company introduced Borealis – their first fully programmable photonic processor (across 1200 parameters), which leverages 216 squeezed-state photon qubits, enabling the company to claim quantum advantage through a peer-reviewed, Nature-published paper.

The problem this advantage was demonstrated in is a very specific application – namely, Gaussian Boson Sampling (GBS). Xanadu claimed that top-of-the-line supercomputers and the available state-of-the-art algorithms towards solving that problem space would take around 9,000 years to complete on classical hardware – Borealis did it in 36 microseconds. Alongside this scientific success claim, Xanadu also managed to offer the first photonic quantum computer available on cloud through Amazon Web Services’ Braket, with quantum operations being handled through Xanadu’s PennyLane open-source, quantum hardware-agnostic software stack.

In early 2025 (again through a peer-reviewed, Nature-published paper), Xanadu demonstrated its progress towards its fault-tolerant computing datacenter with Aurora – a room-temperature operated (barring the cryogenic photon detector system), modular scaling vehicle harnessing 12 physical qubits across 35 integrated photonics chips. These were integrated across 4 modular server racks with fiber optic interconnects and over 13km of optical fiber across components (which include required loops for photon timing matching).

Aurora is the company’s milestone in demonstrating all the required architectural elements of its 2020 blueprint for a fault-tolerant architecture operating together. If X8 was a proof of concept and Borealis the company’s demonstration of achievable quantum advantage through their quantum approach, Aurora is the vehicle that proved their modular integration aspirations as achievable.

Progress has fast-tracked since then: by June 2025, Xanadu was demonstrating the world’s first on-chip generation of GKP states (their error-resistant photonic qubits), with silicon manufacturing processes handling their required silicon nitride waveguides on 300mm wafers. Perhaps even more impressively, the company demonstrated its ability to integrate error-correction at the chip level, while significantly improving its photon detection efficiency.

The principal issue to still be solved, as the company identified it, relates to the quality of the GKP state photonic qubits themselves, which materializes in optical loss issues. This identified bottleneck directly relates to Xanadu’s July 2025 announcement of a strategic partnership with HyperLight and its TFLN (thin-film lithium niobate) chiplet platform technology, which replaces the silicon nitride waveguide design with HyperLight’s lithium niobate solution, significantly reducing waveguide losses and electro-optic chip losses while retaining high-volume manufacturing through semiconductor manufacturing technologies. Another angle relates to another strategic collaboration announced in August 2025 with DISCO Corporation, a developer of ultra-precision grinding and polishing machinery for photonic components, aiming to improve the quality of GKP photon generation on laser interactions.

Looking to the future, the company’s goal is to achieve up to 1,000 logical qubits by 2029; barring unexpected breakthroughs, the company expects to achieve that at a 100:1 ratio, with a requirement of around 100,000 physical qubits to do so. Besides pure qubit count, applications are the name of the game; in December 2025, Xanadu announced a breakthrough application in photodynamic cancer therapy, a medical application that joins their ongoing partnership with AstraZeneca (molecular simulations, protein folding, drug-protein binding affinity, and optimization of molecular conformations). Additionally, the company has developed quantum applications for machine learning (including classification and neuronal network implementations).

PsiQuantum

Founded in 2016 (Palo Alto, California), PsiQuantum has grown in scale in the intervening nine years, reaching its 7B$ valuation while expanding its facilities across Chicago, Australia, and the United Kingdom. The company hit the ground running with a particular vision: to skip the current era of Noisy Intermediate Scale Quantum (NISQ) computers while focusing its funding and developmental efforts on tackling the architectural, error-correction, and manufacturing problems for its choice of quantum computing architecture. The goal: to deliver a 1 million-plus qubit design as soon as feasible.

This decision flies in the face of most other quantum industry players, who have elected to develop proof-of-concept vehicles all the way through platform development and incremental, step-by-step scaling.

PsiQuantum’s ethos informed their technology choice of pursuing a photonic quantum architecture, which, as we’ve seen, can find an important common ground within semiconductor techniques, leveraging decades of already-funded and problem-solved manufacturing research and development.

PsiQuantum worked in the shadows between its 2016 founding and 2021 – the moment the company materialized a very public partnership through GlobalFoundries’ Fab 8, one of the world’s leading CMOS and – yes – photonics manufacturing players. And even as early as 2021, PsiQuantum knew exactly what it required out of GlobalFoundries’ facilities: manufacturing of its Omega quantum devices.

One year later, the company was already testing GlobalFoundries’ output through testing and validation of single photon sources, photonic switches, waveguide-integrated on-chip photon detectors, and demonstrations of quantum entanglement.

Then, silence – up until 2025, when PsiQuantum finally revealed its work through the publication of the paper “A manufacturable platform for photonic quantum computing” in Nature. It finally shed light on what Omega is all about, and the engineering systems designed around its scaling up to 1 million-plus qubits: compatibility with 300mm wafer platforms; silicon-nitride waveguides; telecom-band (1550nm) single-photon sources, guaranteeing compatibility with existing fiber infrastructure; and its arguably most important development in the world’s first Barium Titanate (BTO) manufacturing process on 300 mm wafers, the demonstrably highest-performance electro-optic material known and a breakthrough in switching performance.

The paper claimed state-of-the-art performance in key metrics, conditional (as we’ve discussed before) on photon detection: if there’s no photon to detect, there’s no fidelity to measure. It’s an interesting way to expound on a quantum system and components reaching “beyond state-of-the-art-performance", as PsiQuantum put it, even if it leaves the question open on how good the photon hit rates are that are necessary for actual computational work to occur.

The confidence and planning are there: PsiQuantum places its achievement of a large-scale, error-corrected quantum computer somewhere between the 2027-2029 timeframe, which is ahead of most other quantum players, who tend to settle expectations around 2029-and-beyond.

But first, PsiQUantum still needs to showcase actual full-system integration through its Alpha system program (whose housing facilities covering a 120,000 square foot manufacturing and testing facility in Milpitas, California, are still under construction). Only then should the company be able to execute on the next phase: execution on its 1 million-plus qubit system is dependent not only on technological development but also on a relatively more mundane requirement: finishing the actual facilities where the system is to be housed, which saw groundbreaking at the Illinois Quantum and Microelectronics Park (IQMP) in Chicago in late 2025.

What lies ahead?

The complex reality of quantum mechanics means that there are two severe bottlenecks any company must face. First, the intellectual bottleneck, as there are very few people in the world capable of working and designing such systems. The second being the economic bottleneck, due to how research, development, and manufacturing of quantum-related technologies are simply very, very capital-intensive.

Xanadu’s lack of an official, public roadmap seems to be a strategic, science-first choice (compare it to IBM’s own extremely detailed roadmap for its superconducting qubits we explored in our previous article) – especially considering the way Xanadu has announced and executed on their plans for a large-scale, fault-tolerant quantum computer.

The one-two combo of announcing key milestones as they are executed while also moving them through peer-reviewed scientific publications shows the company is confident in their planned architecture, and the strategic partnership announcements align well with their identified bottlenecks.

Across the board, quantum is still a bet: no current quantum-related revenue can sustain development costs for pure-play quantum companies (something Google, Microsoft, and IBM don’t have to contend with), which helps explain the decisiveness of funding rounds and is perhaps a measure of their behind-closed-doors progress.

The bet is that when the tomorrow of quantum advantage comes, so too will the investment be justified. Like IBM, IonQ, and the other companies on our previous roadmap article, both PsiQuantum and Xanadu are also looking beyond the 2029 timeframe towards delivering large-scale, error-corrected quantum computers. Also like IBM, Quantinuum, and IonQ, Xanadu has made it to DARPA’s Quantum Breakthrough Initiative (QBI) Stage B.

PsiQuantum specifically hasn’t been a part of DARPA’s QBI, but is still involved with DARPA in a different capacity, being one of two companies (the other being Microsoft) to qualify for the Agency’s Underexplored Systems for Utility-Scale Quantum Computing (US2QC) Stage C program in February 2025. Beyond that, the company has seen both Australian and U.S. government backing; perhaps these government-corporation programs are one of the best ways to evaluate the feasibility of any given quantum solution, considering the validation work required for inclusion.

Nvidia has pledged to invest a combined $4 billion in two photonic manufacturing firms, Lumentum and Coherent. As Reuters reports, this continues Nvidia's plans to expend capital investment with its expansive cash reserves to help build the AI ecosystem and improve the output of its models. The quiet part is that it also helps keep Nvidia on the cutting edge.

Both companies develop optical and semiconductor technologies, enabling future networking hardware and AI chip designs that utilize light to transfer data, rather than electricity. With Nvidia looking to continue providing the digital shovels in this AI gold rush, leveraging forward-looking technologies like photonics may be one way it maintains its edge in the range of hardware spaces it now occupies in the global AI buildout.

“AI has reinvented computing and is driving the largest computing infrastructure buildout in history,” said Nvidia CEO Jensen Huang. “Together with Lumentum, NVIDIA is advancing the world’s most sophisticated silicon photonics to build the next generation of gigawatt-scale AI factories.”

Jim Anderson, CEO of Coherent, spoke on their deal, stating: “This strategic relationship underscores Coherent’s role as a key enabler of next-generation AI data center infrastructure. We are proud to expand our 20-year relationship with NVIDIA by increasing their access to include multiple product families to help them build the AI data centers of the future.”

Cash, access, capacity

Nvidia has been working with both of these companies for some time on its own networking hardware and to develop a strong supply chain for these key components. These new deals only enhance that cooperation.

As with most of the deals within and without the AI industry over the last year, Nvidia's investment in these firms is a mixture of hard currency, future purchase orders, and secured access to key technologies. With Lumentum, Nvidia's $2 billion investment will support its R&D and manufacturing expansion in the U.S. with a new fabrication facility. It also includes a "multibillion purchase commitment" from Nvidia, and "future capacity access rights for advanced laser components."

The Coherent deal reads almost identically. There, Nvidia and Coherant talk up the "multiyear strategic agreement" between the two companies, which includes "an Nvidia multibillion-dollar purchase commitment and future access and capacity rights for advanced laser and optical networking products." In addition, Nvidia will also invest $2 billion to support R&D and fab. expansion for its U.S.-based manufacturing facilities.

Considering the number of bottlenecks that have appeared since the memory supply shortage began in 2025, from glass cloth to PCB drill bits, Nvidia's investment in expanding photonics development and fabrication in America may be a way to get ahead of future supply constraints, too.

Hedging its bets

With the similarities between these two investment vehicles for Nvidia, and the near identical nature of the deals and subsequent press releases, it very much feels like Nvidia is hedging its bets. Arguably, that's what Nvidia has been doing since the advent of this major AI revolution.

Nvidia is the one major company making money hand over fist in this new era, and instead of hoarding it, or using it exclusively for stock buybacks, or corporate bonuses, it's been reinvesting in the AI industry that put a rocket up its balance sheets and stock price.

It invested in Coreweave, OpenAI, Oracle, Intel, Synopsys, and Nokia, all of which are heavily involved in the AI industry or are adjacent to it. It's keenly aware that even as the king of the AI pile, it needs those other economic and industry pillars to keep the whole house of cards standing.

If Nvidia were bold enough, it could try to buy out Lumentum and Coherent entirely. Their company valuations are a fraction of Nvidia's profits from even the past quarter. But it didn't. It secured capacity, but not exclusive rights. Nvidia isn't looking to eat the AI industry and supply chain, but bolster its output.

It's not a one horse race

As much as Nvidia is the clear market leader when it comes to AI hardware, it is far from the only player in the game. China has used Nvidia's absence to heavily invest and fuel its domestic inference chip industry. AMD recently signed a $60 billion deal with Meta to power its next-generation AI-powering data centers, and there are small startup companies looking to build out ASIC chips that could prove far more powerful for future AI workloads when fully developed.

Marvell's Celestial AI acquisition highlights that other companies see optical technologies as a key future technology for next-generation networking hardware. Meanwhile, the Bill Gates-backed Neurophos is developing AI chips that use photonics to accelerate even beyond what the best GPUs can do.

Nvidia made itself the king of the AI hill by having the best hardware at the right time, and as far as training goes, that doesn't seem likely to change any time soon. But if Nvidia doesn't keep developing its hardware, other contenders would emerge. And the competition is ramping up in the inference space, leaving no guarantee that Nvidia will retain its premier position forever.

Perhaps getting ahead of the pack when it comes to photonics will be one way it can maintain its lead. But even if it doesn't, $4 billion is a drop in the bucket for a company that made close to 20 times that in the past three months alone.

Taara, a company specializing in free-space optical communication, just released the Beam — a shoebox-sized device that uses its proprietary Photonics Platform to deliver up to 25 Gbps of bidirectional throughput. More than that, the company says that it has a range of 10 kilometers and claims that it has ultra-low latency, making it ideal for AI applications.

This isn’t the first optical transceiver developed by the company, as it has been working on the technology since 2017 at Google’s X development lab. In fact, Taara says that its Lightbridge device has already been deployed in over 20 countries alongside carriers including T-Mobile, Vodafone, Airtel, and Digicel. While this offers a longer range of 20 km, it has a slightly lower 20 Gbps throughput and uses mechanical parts to keep the beam aligned.

On the other hand, Beam uses silicon photonics to deploy an optical phased array with more than a thousand miniature emitters to track, shape, and steer the beams without requiring any moving parts. The company promotes this as an alternative to expensive and time-consuming fiber deployments or the complicated spectrum licensing requirements of radio frequency communications. Its compact size and relatively low power consumption mean that it can easily be deployed in hours instead of weeks or months, and you can install it practically anywhere — from existing towers and cell sites to rooftops and mountain tops — as long as the two transceivers retain line of sight (LOS).

Aside from the compact size brought by silicon photonics, the company also says that using this technology would allow it to build more capable and more efficient generations of its optical communications transceivers in the future. This makes it similar to how semiconductors have evolved in the past, where Moore’s Law stated that transistors would have doubled in number on a particular chip every other year. While Taara did not give any details on how it expects to achieve this, other firms are working on this tech, with one startup even saying that it developed an optical transistor that’s 10,000 times smaller than existing tech and capable of handling 1,000 x 1,000 multiplication matrices.

The only drawback to this technology is that it’s affected by weather conditions, like fog and heavy rain, and other disruptions, such as smoke, that can reduce visibility or cut line of sight altogether. Nevertheless, the company advertises the Beam as a part of a light mesh network, allowing communication to continue through different nodes. Aside from that, it also introduced the Lightbridge Pro, which adds an automatic radio frequency or fiber backup to the original Lightbridge, ensuring seamless switching in case suboptimal atmospheric conditions interfere with its optical communication.

The voracious appetite of the generative AI revolution has overhauled any number of industries so far in its three-year history. First, it upended demand for high-end chips, pushing companies like Nvidia to record high valuations and putting pressure on all parts of the manufacturing process to churn out chips to meet that need. Then it began to make power grids break and buckle, requiring the need for a rethink about how we send energy to data centers. And those data centers are also facing the strain as they’re needed more often for AI training and inference, even eking out extra demand for commodities like copper that are integral to their operations.

Those data centers need to respond to that demand for more capacity and the challenges of copper shortages, argues Vaysh Kewada, CEO and co-founder at Salience Labs, a silicon-photonics company focused on networking bottlenecks in AI data centers. The bigger and more intensive AI models that continue to roll out, alongside the shift away from chatbots to agentic AI, are pushing those within the sector towards photonics.

“We're targeting the scale up domain of AI data centers, where we're seeing that they're increasingly limited by not just the bandwidth, but the latency of predictability, especially as we scale to larger workloads and agentic workloads,” she said in an interview with Tom’s Hardware Premium. For that reason, “there’s a lot of attention at the moment around photonics.”

Others agree: 2026 is “the year of increasing visibility into design wins and building momentum for silicon photonics,” wrote Aaron Rakers, equity analyst at Wells Fargo Securities, in a recent research note. Wells Fargo estimates that the total addressable market for photonics could end up being $10-12 billion by 2030, thanks to the industry’s shift to bigger capacity.

That sounds like good news, but it comes with a catch. Behind the bullish forecasts, those within the photonics industry warn that, like all those sectors that have been eaten up and spat out before, the next set of constraints, including reliability, packaging, manufacturing capacity, and how data is actually routed once it hits fibre, could become the next hard limit on AI scaling.

Data is the new choke point

The boom in photonics might come as a surprise to some. “Photonics is something that already exists within the data centre today,” said Vivek Raghunathan, CEO and co-founder at Xscape Photonics, in an interview with Tom’s Hardware Premium. “Optical cables and the silicon photonics technology already exist when it comes to connecting different switches as part of a pluggable transfer ecosystem.”

But now that section of optics is being pushed out of there and into ultra-fast links that link large numbers of GPUs into a single compute fabric. “Ultimately, the network is the bottleneck for these workloads, because they're just far too large to run on a single GPU,” Kewada said.

Using photonics means you can get between 10 and 100 times more information back and forth from the memory before they output a single stream of reference, Raghunathan explained. That’s important because what AI systems do now is changing, requiring that extra information shifting. The average AI user is moving from asking single prompts of a model to running chains of tasks, and Kewada said that the hardware is already struggling under current AI use. “If it’s a problem now, it becomes an even bigger problem when it comes to agentic workloads, and that's heavily latency- and balance-sensitive,” she explained.

Photonics also matters because “fundamentally, the current copper-based interconnects just cannot meet that bandwidth requirement,” explained Raghunathan. He warns that “the current approach is going to break down sooner than later.” The solution is the photonics approach, where you can “squeeze a lot of bandwidth in a single strand of fiber, which is extremely small,” Raghunathan added. Kewada points out that dedicated AI data centers want to move from 200‑gigabit‑per‑second (Gb/s) links to 400 Gb/s links as AI clusters behave less like traditional IT and more like large distributed machines.

The photonics push inside AI data centres is increasingly being shaped by TSMC. Its COUPE (Compact Universal Photonic Engine) platform has become a key reference point for integrating photonic and electronic circuits on a wafer, following rumors, years beforehand, with an eventual unveiling at SEMICON in Taiwan in September 2025, and first mocked up in December. Other companies, including Marvell, Broadcom, and Nvidia, are all also engaged in the sector, with Nvidia helping define the performance requirements that become standards by default.

But Nvidia isn’t the only voice in the space. Broadcom has been leading the debate on co-packaged optics (CPO), betting that moving optics closer to silicon is the only realistic way to get past copper’s limits when scaled up. Marvell has also pushed photonics-heavy designs in bigger AI clusters, as well as spending cash on investments, including buying photonics startup Celestial AI for up to $5.5 billion.

Tackling the routing problem

Most of the focus has recently been on solving the problems of getting optics away from chip switches and onto fiber. But once the data is there, it still has to be routed around a cluster. “All billions of dollars has been spent onto the I/O, but less has been thought about of what you do once the data is there,” Kewada said.

Salience Labs is betting on optical circuit switching. “Rather than it being an OEO [optical-electrical-optical] switch, it's a purely optical switch; we're never transforming that data into the electronic domain,” Kewada explained. That matters because every optical-to-electrical-to-optical hop costs power and, crucially for AI, adds delay. The company is seeing huge interest from those trying to scale up to meet the current needs of AI.

But there’s a broader problem within the photonics sector. “I would say that it is mentally ready for it, but practically not ready for it,” Raghunathan explained.

Part of the issue is in capacity. Many photonics components rely on III-V semiconductors (compound semiconductors made from the associated groups in the periodic table), which aren’t produced in the same numbers as mainstream silicon. Raw materials supply is also tight, said Kewada. And that’s before you get to packaging. “This requires sub-micron alignment,” Raghunathan said. “They are typically glued onto that die. So now the industry has started thinking about, how do I make that interface detachable?” It’s one of many questions the industry is being asked — and asking itself — to address the challenges ahead.

The push towards photonics feels inevitable, but just because it’s inevitable, it doesn’t mean the sector is ready. Manufacturing scale, raw materials, packaging, and reliability are still unanswered issues. And if the industry doesn’t get ahead of those constraints, it risks replaying the same shortages it has already lived through with chips, copper, and power — but this time the choke point could be the network itself. “The volume here is going to be two orders of magnitude higher than what the industry has seen so far,” said Raghunathan. “The entire optics industry has never seen such a volume ever before.”

It's something on the mind of Kewada, too. “We’re in for some interesting times if we see the attention on photonics continue to grow, and especially for next-generation bandwidth,” she said, “if people look towards larger-scale deployment.”

Neurophos, an AI chip started based in Austin, Texas and backed by Bill Gates’ Gates Frontier Fund, says that it has developed an optical processing unit (OPU) that the company claims is ten times more powerful than Nvidia’s latest Vera Rubin NVL72 AI supercomputer in FP4 / INT4 compute workloads, while still consuming a similar amount of power. According to The Register, the company achieves this by using a larger matrix and a much higher clock speed.

“On chip, there is a single photonic sensor that is 1,000 by 1,000 in size,” Neurophos CEO Patrick Bowen told the publication. This is about 15 times larger than the usual 256 x 256 matrix used in most AI GPUs. Despite that, the company was able to make its optical transistor around 10,000 times smaller than what’s currently available. “The equivalent of the optical transistor that you get from Silicon Photonics factories today is massive. It’s like 2 mm long,” Bowen added. “You just can’t fit enough of them on a chip in order to get a compute density that remotely competes with digital CMOS today.”

The company’s first-generation accelerator will have "the optical equivalent" of one tensor core, at around 25 square mm in size. This pales in comparison with Nvidia’s Vera Rubin chip, which is reported to have 576 tensor cores, but the difference is how Neurophos is using the photonic die. But aside from its larger 1,000 x 1,000 Matrix tile size, the startup’s first OPU, which it calls the Tulkas T100, will operate at a cool 56 GHz — much higher than the 9.1 GHz world record achieved on an Intel Core i9-14900KF and the 2.6 GHz boost clock on the Nvidia RTX Pro 6000. This allows it to beat Nvidia’s AI GPUs despite appearing to be underpowered on paper.

More importantly, Bowen says that it built its optical transistors using current semiconductor fabrication technologies, so it could potentially tap fabs like Intel or TSMC to mass produce them. Nevertheless, the chips are still in the testing phase and are not expected to enter volume production until 2028. It also needs to address challenges, like the need for massive amounts of vector processing units and static memory (SRAM).

Photonics is a new frontier that many companies are paying attention to. Nvidia already uses Spectrum-X Ethernet photonics switch systems in its Rubin platform, while AMD is set to develop a $280 million hub, specifically geared toward researching silicon photonics. Either way, it appears that this latest development is just a new wrinkle on the photonics frontier, and we should expect many more developments to come as the technology matures.

Researchers have built a prototype that paves the way for enabling light-powered processor caches that can run at up to 60 GHz in the future, or roughly 20 times faster than some modern processor caches. The functional regenerative "photonic memory latch," fabricated on the commercially available GlobalFoundries’ 300mm Fotonix photonics platform, is designed as an optical counterpart to a standard SRAM bit, and the team positions it as a missing component for fully photonic processors. However, further density improvements will be needed before the tech can be fully integrated into optical processors.

The prototype addresses two bottlenecks that plague modern high-performance systems — interconnect delay and the cost of repeatedly converting information between light and electricity.

Photonic accelerators and optical interposers can move data at extremely high speeds, but they still depend on electronic memory to store and refresh bits. That forces every data path to cross into the electrical domain before returning to light. In this research, the USC and UW engineers tackled that gap by building a memory system that stores, stabilizes, and outputs data entirely as light.

Their device uses a cross-coupled, differential architecture that parallels the behavior of an SRAM cell. The research team, led by Ajey Jacob at USC ISI and Akhilesh Jaiswal at UW-Madison, describes it as a latch that can be written optically and retain its state without drifting. Simulation studies exploring how the latch architecture could be scaled into a complete photonic SRAM system, with the latch acting as the optical equivalent of a single SRAM bit, have already been published by the authors.

The UW-Madison study describes the performance the team expects from the design, namely write speeds approaching 20 GHz, while modeled read speeds reach 50-60 GHz. Those figures sit well above the clock rates of electronic SRAMs used in today’s CPUs and accelerators, which usually top out at 2-3 GHz.

These higher speeds come with footprint trade-offs, though, with photonic components remaining orders of magnitude larger than nanoscale CMOS transistors; this massively limits density. Instead, the researchers point to applications where size is less of a restrictive factor, such as high-bandwidth links inside data centers and HPC systems.

The decision to fabricate the latch on GlobalFoundries’ Fotonix platform means that the technology can be replicated and scaled more easily than if it relied on specialized materials or custom fabrication steps, as is often the case in optical memory research.

The researchers from the University of Southern California Information Sciences Institute and the University of Wisconsin-Madison presented their work at the International Electron Devices Meeting in San Francisco between December 6 and 10.

At TSMC's European OIP forum this week, Alchip and Ayar Labs demonstrated a fully integrated, in-package optical I/O engine built on TSMC's COUPE platform that enables optical connectivity for next-generation AI accelerators. The solution — which combines Ayar's silicon-photonics TeraPHY IC with Alchip's electrical interface die and a detachable fiber connector — can deliver up to 100 Tb/s of bandwidth per accelerator and connect to other chips using the industry-standard UCIe interface. The solution is aimed at hardware developers who need optical connectivity but cannot build their own optical subsystem from scratch.

When TSMC introduced its Compact Universal Photonic Engine (COUPE) framework in 2024, the company primarily targeted large chip developers like AMD or Nvidia that can afford to build their own electronic integrated circuits (EICs) and photonic integrated circuits (PICs), and then order TSMC to build them.

However, many designers of custom accelerators do not have resources for vertical integration (unlike Nvidia, which controls the whole stack of technologies — from compute to scale-out connectivity — with its NVL72, NVL144, and NVL576 platforms) tend to license everything they can and then focus on developing IPs that differentiate their solution from others. This is where the production-ready optical subsystem from Alchip and Ayar Labs comes into play, enabling smaller chip designers to add optical connectivity to their chips relatively easily without investing tens of millions of dollars upfront.

The solution jointly developed by Alchip and Ayar Labs is a three-chiplet co-packaged optical I/O subsystem that consists of an Alchip UCIe-A to UCIe-S protocol-converter chiplet that terminates the accelerator's UCIe-A interface and implements scale-up protocols (UALink, PCIe, Ethernet, SUE) over UCIe-S (streaming), an Alchip EIC that provides low-power SerDes, modulation drivers, clocking, and control, and an Ayar Labs TeraPHY PIC that performs the optical modulation and detection using silicon photonics.

The Alchip protocol converter can also carry non-UCIe protocols encapsulated over the UCIe physical interface, so it can work with compute dies that use proprietary protocols. The PIC uses a microring architecture and is delivered with detachable fiber connectors for manufacturability and offers two link options: PAM4 CWDM (100–200 ns per hop, BER < 10⁻⁶) and a DWDM fast-follower (20–30 ns per hop, BER < 10⁻¹²).

The optical subsystem can achieve extreme scale-up, supporting 100+ Tb/s of bandwidth per accelerator and 256+ optical ports per device to connect hundreds of processors across multiple racks and operate them as a single large processor. Alternatively, the companies envision that their solution could be used for memory extenders as well.

The reference design (a mockup) includes two full-reticle accelerator dies, eight HBM stacks, four protocol-converter chiplets, and eight Ayar Labs TeraPHY optical engines, all mounted on a single substrate with integrated passive devices for power integrity. Alchip's system diagrams demonstrate the platform connecting XPU-to-XPU, XPU-to-switch, and switch-to-switch, and even enabling optical memory expansion.

By using the subsystem from Alchip, which will be sold in the form of chiplets, almost any developer of AI accelerators can enable ultra-high-bandwidth, low-latency, and energy-efficient rack-scale and even multi-rack-scale connectivity for their accelerators, which is too costly to develop in-house for a small company.

GlobalFoundries just announced its acquisition of Advanced Micro Foundry, a Singapore-based silicon photonics maker, a purchase the company says makes it the largest manufacturer of the technology, as reported by Reuters. Silicon photonics uses light instead of electrical pulses to transmit data, and it can be used for communication within chips, between components, and even across servers.

Nvidia is already planning to implement silicon photonics for its next-generation AI servers, which would reduce power consumption while simultaneously increasing data transfer speeds. This is crucial for the company, as it could enable clusters with millions of GPUs within data centers. AMD is also jumping on this technology, reportedly spending nearly $300 million to open a research and development center in Taiwan that focuses on said tech. It acquired Enosemi, another silicon photonics firm, earlier this year, to help compete against Nvidia.

Silicon photonics’ ability to reduce power consumption while increasing data transmission speeds is crucial for the future of AI computing. This is especially true now that the AI data center build-out is straining the electricity grid with the unprecedented increase in power demand. “As data moves faster and workloads grow more complex, the ability to move information with greater speed, precision, and power efficiency is now fundamental to AI data centers and advanced telecom networks,” said GlobalFoundries CEO Tim Breen in a statement.

Aside from its use with AI, silicon photonics is a pivotal technology in quantum computing. The use of light instead of electrical signals could allow for systems that do not require cryogenic cooling, making quantum computers much more practical and less costly to operate.

While big names like AMD, Nvidia, and GlobalFoundries are investing in silicon photonics, other startups are also entering the fray. Firms like Ayar Labs, Celestial AI, and Lightmatter are developing their own technologies and photonic-based chips, especially as it’s seen as the future of computing.

While we don’t expect to see consumer-grade CPUs, GPUs, and motherboards come with this technology anytime soon, it’s already being applied to large-scale servers that deal with terabytes of data every second. And with the continued investment in AI data centers, we anticipate that research and development on this promising tech would move forward as well.

According to a new report, AMD has made the decision to establish two new R&D centers in Taiwan, focusing on silicon photonics, heterogeneous integration, and AI-related technologies, reports the Liberty Times. Both heterogeneous integration of system-in-packages (SiPs) and silicon photonics with co-packaged optics (CPO) are crucial technologies for current and next-generation AI and HPC components, as performance scaling via traditional methods is too slow to meet market requirements.

AMD's new R&D facilities will reportedly be established in Tainan and Kaohsiung, according to Taiwan’s Ministry of Economic Affairs (MOEA), but have not yet been officially confirmed by AMD. The R&D center in Kaohsiung would join forces with National Sun Yat-sen University and other academic and industrial institutions to accelerate talent development and research in AI-related fields such as heterogeneous integration and silicon photonics.

The total investment in two R&D facilities reportedly exceeds $280 million (NT$8.64 billion), with $170 million (NT$5.33 billion) provided by AMD, and the remaining $110 million (NT$3.31 billion) covered by the government funding.

AMD and silicon photonics: The story so far

Optical interconnects provide higher speeds, longer distances, and higher energy efficiency than traditional copper interconnects, making them suitable for next-generation AI and HPC data centers. Silicon photonics integrates optical and electronic functions on a single platform, establishing optical interconnections without using complex and power-hungry adapters, which typically increase latency.

Just like Intel and Nvidia, AMD is working to integrate silicon photonics into its platforms. But the reported establishment of an R&D center in Taiwan is not the first of AMD's efforts to get into the silicon photonics game.

Earlier this year, the company acquired Enosemi, which was its external development partner in photonics. AMD hopes to accelerate its silicon photonics and co-packaged optics solutions — from foundational silicon to systems-level integration — for its next-generation AI systems.

AMD's takeover of Enosemi strengthened the company's position in silicon photonics and optical interconnects by adding a specialized team experienced in combining light-based communication with traditional silicon. The small startup had single-chip Rx and Tx 16x112G chiplets, along with various IP at the time of acquisition, and AMD will likely integrate some of these components into future products.

By bringing Enosemi's engineers and intellectual property in-house, AMD gains the ability to design its own optical interconnects moving forward, instead of relying on external vendors. This enables the company to control a crucial piece of its technology stack: the communication fabric, which ties its CPUs and GPUs together inside data centers.

AMD's mid-term plan is likely to build vertically integrated rack-scale AI solutions — similar to Nvidia's NVL72 or NVL144 — that rely on copper, then offer optical interconnects, as well as develop optical connectivity solutions for AI data centers. Longer-term plans could include making inter-chip communication optical to boost performance and reduce power consumption, as well as enabling the connection of millions of processors across a single data center.

In May, Enosemi added a missing optical interconnection/silicon photonics piece to AMD's set of data center-grade technologies and expertise, which now includes CPUs, GPUs, DPUs, FPGAs, network solutions, and rack-scale system integration (via ZT Systems). The company now has the experienced specialists, proprietary IP, and early production expertise to avoid teething problems with its own silicon photonics products.

Moving closer to TSMC

AMD's U.S. R&D teams will develop elements like transceiver architectures, signaling protocols, and packaging topology to fit AMD's system needs. However, the company needed R&D close to manufacturing facilities (i.e. TSMC's most advanced fabs and packaging operations), and the ecosystem at large. To that end, the establishment of additional R&D centers focused on silicon photonics and integration is a highly strategic move aimed at streamlining the development of silicon photonics products.

On the silicon photonics side of things, TSMC has COUPE — Compact Universal Photonic Engine — a hybrid optical platform that integrates photonic and electrical dies using SoIC-X and CoWoS packaging. The first-generation solution delivers up to 1.6 Tb/s on-package optical bandwidth, with the second generation delivering up to 6.4 Tb/s by 2026 – 2027, and up to 12.8 Tb/s with the third generation, which is expected to land before 2030.

As AMD produces all (or almost all) of its products at TSMC, it is reasonable for the company to adopt COUPE as the foundational platform for its upcoming silicon photonics products. This is not dissimilar to Nvidia's approach with ASICs for its Quantum-X and Spectrum-X switches, which are due in 2026 and 2027, respectively.

Assuming that AMD adopts TSMC's COUPE (not that it has much choice), it will follow the COUPE roadmap, and its Taiwanese R&D facilities will work closely with the contract chipmaker to optimize AMD's silicon photonics developments with TSMC's COUPE platforms (e.g., align photonics layouts with AMD's high-speed electrical fabrics), prototype the company's silicon photonics silicon, and perhaps bring up actual platforms together with engineers from TSMC.

Since AMD will team up with universities, expect the company to conduct material research focused on silicon photonics and heterogeneous integration in Taiwan, again, close to TSMC's primary R&D facilities. By doing so, local engineers will also be able to work closely with the global data center ecosystem, which is still predominantly based in Asia.

Another step towards the future

As bandwidth demands rise, optical interconnections and silicon photonics will be mandatory for future AI clusters, first at the cluster scale and eventually at the rack scale as well.

Nvidia's roadmap clearly shows that the company expects optical interconnects to be a part of its NVL144 Rubin and NVL576 Rubin Ultra rack-scale offerings. So, if AMD plans to compete, it needs to develop its own platforms with silicon photonics and CPO.

Enosemi and the Taiwan R&D centers will give AMD both the intellectual property and local engineering talent to optimize its IP with TSMC's COUPE to match Nvidia’s silicon-photonics trajectory. Whether AMD's 2027 rack-scale platform, based on the Verona CPUs and Instinct MI500-series accelerators, will use in-house-developed optical technologies for scale-out connectivity remains to be seen, but the firm's 2028 rack-scale solution is likely to enjoy the fruits of the Enosemi acquisition.

AMD is looking to strengthen its position in the race against Nvidia with a new acquisition. The company purchased Enosemi, a company developing photonic integrated circuits. Silicon photonics is seen as a crucial next step into the next era of computing, with many leading tech companies and fabs making steps into photonics over the past year.

Enosemi is a Silicon Valley-based company that has worked with AMD and companies like GlobalFoundries to license, build, and ship photonic integrated circuit IP since 2023. A blog post from AMD SVP Brian Amick claims that the Enosemi team "will help [AMD] immediately scale our ability to support and develop a variety of photonics and co-packaged optics solutions across next-gen AI systems."

Photonics refers to a newer technology in semiconductors, based on the use of light rather than electrons to send information. Photonics has already been deployed in network switches, inter-chiplet interconnects, and a host of other applications to assist and one day perhaps replace electronic integrated circuits. Light-based ICs have higher speeds, more bandwidth, and better power efficiency than electronic ICs, making them a highly attractive new frontier in chip design.

AMD's move to acquire a leading photonics firm like Enosemi shows a commitment to matching Nvidia's own push into photonics. Nvidia has already released a 400 TB/s network switch platform built on silicon photonics for the datacenter, with more plans to incorporate the tech into its stack of AI solutions.

In AMD's press release for the acquisition, the company shares, "This acquisition strengthens AMD's position as a provider of full-stack AI solutions, combining its leading CPUs, GPUs, and adaptive SoCs with enhanced networking, software, and system integration expertise."

AMD's goal of becoming a full-stack supplier to compete with Nvidia has so far also included the acquisitions of ZT Systems, Mipsology, and Silo AI, plus partnerships across the enterprise solution stack. Nvidia has cemented itself as a true provider across the entire datacenter, with competitors Intel and Arm also seeking to build up similar positions.

Speculators have long claimed that China is at risk of changing lanes and surpassing the Western tech sphere through the study and application of silicon photonics, with China's research on next-gen compute technologies more than doubling the U.S.'s over the last five years. AMD does not seem content to let either Nvidia or Chinese competition surpass it in this field anytime soon.

The challenges facing multi-chiplet processors are the performance and power consumption of inter-chiplet interconnects, which may eventually limit their performance. Lightmatter, a startup that has worked on various optical interconnects for several years now, this week introduced a possible solution: its Photonic M1000 high-performance photonic interconnect platform that promises to enable large multi-chiplet processors with optical interconnects supporting bandwidth of up to 114 Tbps (14.25 TB/s).

Lightmatter's Passage M1000 is a multi-reticle eight-tile active 3D interposer enabling die complexes of 4,000 mm^2, which by far exceeds the sizes of today's multi-chiplet solutions. The device includes eight connected chip sections in one package and integrates 1,024 serial data channels. Each of these supports 56 Gbps transmission using a straightforward modulation method. For external connections, the M1000 incorporates 256 fiber-optic lines with eight wavelengths per signal line, each offering 448 Gbps.

The Passage M1000 comes in a 7,735 mm^2 package that can deliver up to 1,500W of power to its chiplets, which is more or less in line with expectations for next-generation AI processors.

In addition to the Passage M1000 — which can serve as base for ultra-high-performance multi-chiplet AI processors — Lightmatter also unveiled its Passage L200.

The Passage L200 is a 3D optical chiplet that replaces traditional copper interconnects with ultra-high-speed photonic links. It offers 32 Tbps (L200) and 64 Tbps (L200X) of total bandwidth, supporting over 200 Tbps per chip package when integrated. Unlike conventional designs limited to edge I/O, L200 enables edgeless connectivity, enabling data channels to be placed anywhere on the die surface for better performance.

The L200 users chiplet IP from Alphawave with a UCIe die-to-die interface and Lightmatter's photonic circuits that support supports 320 multi-protocol SerDes, 16-wavelength WDM per fiber for up to 1.6 Tbps per fiber.

"Passage M1000 is a breakthrough achievement in photonics and semiconductor packaging for AI infrastructure," said Nick Harris, founder and CEO of Lightmatter. "We are delivering a cutting-edge photonics roadmap years ahead of industry projections. Shoreline is no longer a limitation for I/O. This is all made possible by our close co-engineering with leading foundry and assembly partners and our supply chain ecosystem."

Being a fabless chip designer, Lightmatter orders silicon from GlobalFoundries (which used its Fotonix silicon photonics platform that integrating photonics with CMOS logic) and then packaging services from Amkor and ASE. The M1000 will be available in summer 2025, whereas L200 will be available in 2026.

GlobalFoundries announced that it will build an advanced packaging and testing facility at its Malta, New York fab to support the growing demand for silicon built entirely within the United States. GlobalFoundries said that this extension will also provide assembly and testing for silicon photonics, a tech that combines optical and electrical components to deliver better efficiency and performance than chips that rely just on silicon and copper.

This facility is projected to cost $575 million to construct, and GlobalFoundries needs another $186 million for research and development costs over the next decade. However, New York state will provide up to $20 million to support this project, which is in addition to the $550 million it has already spent to support GlobalFoundries. The U.S. Department of Commerce will also give $75 million in direct funding in addition to the $1.5 billion it received from the CHIPS and Science Act.

“We’re proud to partner at the state and federal level on this new center, which is a direct response to our customers asking for more geodiversity in their supply chains and additional support with advanced packaging solutions for GF silicon photonics, Trusted, and 3D/HI offerings,” says Global Foundries CEO and President Dr. Thomas Caulfield. “The New York Advanced Packaging and Photonics Center will be unique in our industry and will play a vital role in the continued growth of the Empire State’s world-class semiconductor manufacturing and innovation ecosystem.”

The construction of an advanced packaging facility within the United States is crucial for the country’s target of silicon independence. Currently, most of these activities happen in Asia; for example, TSMC is already producing 4nm chips at its Arizona fab, but it still needs to ship them back to Amkor in Taiwan for packaging until the latter completes its own nearby facility.

A GlobalFoundries packaging facility in New York helps ensure chip security because the silicon wafers never leave American borders. More importantly, it is an American company and a trusted U.S. Department of Defense supplier. This makes it a great candidate for producing the advanced chips that the U.S. military needs to maintain global technological supremacy.

JFS Laboratory, a Chinese government-backed company, has developed a silicon photonics chip, a first for the country, reports the South China Morning Post. Processors with laser-based I/O are expected to have particular advantages over traditional chips with copper interfaces in high-performance applications like AI and HPC.   

Neither JFS nor SCMP disclose what exactly was achieved and how the silicon photonics chip connects to the processor, so we can only wonder about its characteristics in terms of data transfer rates and power. In fact, the only thing that we know about JFS Laboratory is that it is based in Wuhan and was established in 2021 with 8.2 billion yuan ($1.2 billion) in funding from the government. Therefore, it has taken the company three years to successfully integrate a laser light source into a silicon-based chip. 

Silicon photonics is crucial for AI and HPC processors, and infrastructure, because it addresses key limitations of traditional copper-based interconnections. Particular benefits of a successful implementation will be seen in terms of bandwidth, latency, and energy efficiency, just like typical optical interconnects. 

Given the context of China amid sanctions and the inability to produce high-performance processors for AI and HPC akin to Nvidia's H100 or AMD's Instinct MI300-series, scalability is perhaps the most important feature enabled by optical interconnects. 

The ability to scale up and out computing power without increasing power consumption caused by copper-based interconnects is key for hyperscale AI and HPC datacenters, particularly in Chinese realms. Silicon photonics provides a path for scalable chip designs that can meet the growing computational demands while maintaining efficiency, making it an essential technology for future advancements in artificial intelligence and supercomputing. 

Latency is a major factor in scalability. In AI realms, minimizing latency is critical for real-time processing and decision-making. The high-speed, low-latency nature of optical data transfer in silicon photonics allows for faster communication between different parts of the computing system, improving overall performance in applications like AI inference and large-scale simulations. In commercial space, AI-based recommendations software and hardware can also benefit from low latency. 

Speaking of commercial AI and HPC applications, we surely should mention power consumption. One of the biggest challenges in AI and HPC is managing the power consumption of datacenters. Silicon photonics is more energy-efficient than copper interconnects, as optical signals generate less heat and require less power to transmit over long distances. As a result, optical interconnects greatly reduce the total cost of ownership (TCO) for datacenters. 

In general, JSR seems to have made a breakthrough. However, without actual performance numbers, we can only wonder how significant this breakthrough is.

HBM's future isn't just bright: it's also lightspeed, ultra-bandwidth, and super low-power. At this year's Open Compute Project (OCP) Global Summit, Samsung's Advanced Packaging Team Yan Li presented us with a glance at a more integrated future than we might expect: one where thermal and transistor density issues with further High Bandwidth Memory (HBM) development could be solved through photonics. 

Photonics is based on a technology that can encode information on single photons (particles/waves of light), which means that it improves (almost) everything we care about in our current computing environment. There's both incredibly reduced power consumption (you're beaming particles of light instead of a flow of electrons) and improved processing speeds (with latencies achieving femtoseconds and propagation speed, well, approaching the lightspeed limit). Getting there is just a matter of engineering, quantum physics, and human ingenuity.

As it stands, the industry has made recognizable inroads in integrating photonics and HBM via two methods. One sees a photonics interposer being sandwiched between the base packaging layer and a top layer holding both logic (a GPU, for instance) and HBM itself, serving as the communications layer between them. This future seems expensive – there's the need for that interposer, as well as the need for both local logic and HBM to be configured with photonics I/O as well.

Another approach is to decouple the HBM memory banks from the chip package entirely. Instead of dealing with the chip packaging complexities (including logistics) of dealing with an interposer, you shift the HBM banks away from the chiplet itself and connect them (via photonics) to the logic. This simplifies chip manufacturing and packaging costs for both HBM and logic and does away with complex, in-circuitry, local conversion from digital to optical.

From this vantage point, that approach sounds most sensible. But then, it also means a deeper rethinking of server specifications and would also likely result in "HBM memory cubes" being a thing - HBM memory banks pre-loaded onto a specified photonics interface. Because you've decoupled HBM from the chip itself, and assuming you keep a standard optical communications interface, you can then look at an "upgradeable" product - one that's handled as if it were a stick of the best RAM kits.

The presentation also goes into additional details on Samsung's HBM packaging, which is already offered in 2.5D and 3D solutions, and presents a brief overview of the racing horses that are Moore's Law and the increasing costs of semiconductor miniaturization in order to explain why photonics is indeed a part of our future. How far away into the future is hard to tell, but the road disappears far into it.

EDIT 11/05/2023 7:05am PT: Corrected miscalculations of the performance values stated in the article.

Original Article:

A new paper from Tsinghua University, China, describes the development and operation of an ultra-fast and highly efficient AI processing chip specialized in computer vision tasks. The All-analog Chip Combining Electronic and Light Computing (ACCEL), as the chip is called, leverages photonic and analog computing in a specialized architecture that’s capable of delivering over 3.7 times the performance of an Nvidia A100 in an image classification workload. Yes, it’s a specialized chip for vision tasks – but instead of seeing it as market fragmentation, we can see it as another step towards the future of heterogeneous computing, where semiconductors are increasingly designed to fit a specific need rather than in a “catch-all” configuration.

As noted in the paper published in Nature, the simulated ACCEL processor hits 4,600 tera-operations per second (TOPS) in vision tasks. This works out to a 3.7X performance advantage over Nvidia’s A100 (Ampere) that's listed at a peak of 1,248 TOPS in INT8 workloads (with sparsity). According to the research paper, ACCEL can has a systemic energy efficiency of 74.8 peta-operations per second per watt. Nvidia’s A100 has since been superseded by Hopper and its 80-billion transistors H100 super-chip, but even that looks unimpressive against these results.

Of course, speed is essential in any processing system. However, accuracy is necessary for computer vision tasks. After all, the range of applications and ways these systems are used to govern our lives and civilization is wide: it stretches from the wearable devices market (perhaps in XR scenarios) through autonomous driving, industrial inspections, and other image detection and recognition systems in general, such as facial recognition. Tsinghua University’s paper says that ACCEL was experimentally tried against Fashion-MNIST, 3-class ImageNet classification, and time-lapse video recognition tasks with “competitively high” accuracy levels (at 85.5%, 82.0%, and 92.6%, respectively) while showing superior system robustness in low-light conditions (0.14 fJ μm−2 each frame).

In the case of ACCEL, Tsinghua’s architecture operates through diffractive optical analog computing (OAC) assisted by electronic analog computing (EAC) with scalability, nonlinearity, and flexibility in one chip – but 99% of its operation is implemented within the optical system. According to the paper, this helps in fighting constraints found in other vision architectures such as Mach–Zehnder interferometers and diffractive Deep Neural Networks (DNNs).

That 99% number is relevant to explaining at least the disparity in energy efficiency between ACCEL and other non-analog approaches: Nvidia’s GPU is 100% digital, meaning that its operation is based on the continuous flow of electrons (and produces waste heat as a result).

A photonic, optical system, however, leverages non-electrical ways of transferring, operating on, and encoding information. This can be done via laser pulses at specific wavelengths (we explored this in our recent article on China’s Quantum Key Distribution [QKD] satellite system, also photonic-based) being used to extract and communicate features of visual data (an image) and operating on that light (changing it) virtually on-transit. As a result of this optical processing system, there are fewer energy requirements and electrons wasted in thermal dissipation. Getting rid of the high energy and latency cost of ADCs (Analog-to-Digital Converters) goes a long way toward the performance improvements unlocked by photonics. It’s also why photonics systems are used across quantum computing and HPC (High-Performance Computing) installations.

Simultaneously, we reap speed benefits from moving away from the orderly but messy movement of electrons across semiconductors and unlock operating speeds limited only by light itself. As a result, the research paper claims in-house tests of the chip showcased a low computing latency of each frame at 72ns – resulting in a throughput of approximately 13,000 frames generated per second, more than enough to make any Doom player lose track of reality. It also seems like there would be enough frames for a co-processor to analyze a selection of those images in any computing-vision task. It hardly seems like the deep learning processing of these images through ACCEL would be the bottleneck.

ACCEL seems to be an analog rendition of an Application-Specific Integrated Circuit (ASIC) design. That’s precisely the role of the electronic analog computing (EAC) unit, as it can reconfigure the analog pathways within it to accelerate specific tasks. Think of these as pre-programmed algorithms within the chip, with the EAC coordinating which configuration should be applied to which task.

Dai Qionghai, one of the co-leaders of the research team, said, “Developing a new computing architecture for the AI era is a pinnacle achievement. However, the more important challenge is to bring this new architecture to practical applications, solving major national and public needs, which is our responsibility.”

The new ACCEL chip being photonic and analog may bring to mind the recent IBM announcement of another analog AI-acceleration chip (Hermes). It’s perhaps interesting to witness how even with all sanctions being applied to China, the country’s research and development is allowing it to catch up – and in some ways, apparently improve upon – whatever it was that they were being impeded of. Being able to go around limitations is undoubtedly the way China is thinking about sanctions.

It’s also important to understand that this generation of photonics-based analog chips is being worked on at extremely relaxed lithography levels. ACCEL, for instance, was manufactured on a standard 180-nm CMOS technology for the Electronic Analog Computing unit (EAC) – the brains of the operation. Naturally, further efficiency improvements could be gained from further miniaturizing the process towards lower CMOS nodes (Nvidia’s H100 is fabricated at a 4 nm process). It’s unclear what further work can be done to miniaturize the Optical Analog Computing (OAC) module.

It seems that implementing analog computing systems such as ACCEL at scale is more of a question of fabrication throughput and industry adaptation rather than of physical impossibility. But there’s a reason high-performance AI analog chips still haven’t been deployed at scale: their manufacturing is currently too low to serve anything other than research efforts and prototypical work. We now don’t have the throughput nor the available capacity to add these chips to the already-commited-through-2025 manufacturing commitments at companies such as TSMC – but these experimental results are always needed before committing to scale anything. And the markets meant for chips such as these would very much like to have them. Ultimately, it’s all a matter of planning, spending, and time.  

Achieving higher-orbit quantum communications remains an objective for all institutional and private players with enough expertise and funding to consider it. And while quantum computing and the capability to communicate in unbreakable, unsnoopable channels is of interest to most entities, only China has manifested a low-orbit satellite — Micius — that enables two-way research and quantum information traffic between space and the surface. This was back in 2016 — the US doesn’t have a publicly-known, operational Quantum Key Distribution satellite system, and Europe’s is only expected to launch next year.

Not one to rest on its laurels, China is nonetheless aiming to take QKD (Quantum Key Distribution) communication to new heights, and is plotting out the ways to break its current, 310-mile (~500 km) geostationary orbit limit towards an impressive 6,200 mile (10,000 km) radius.

"Low-orbit quantum key satellite networking and medium- and high-orbit quantum science experiment platforms are the main development directions in the future," said Wang Jianyu, dean of the Hangzhou Advanced Research Institute of the Chinese Academy of Sciences (CAS). While timelines weren’t given for medium or high-orbit QKD, work is underway in understanding what problems need to be solved to get there.

Of course, satellites sitting at higher orbits could cover larger portions of the surface and additional ground stations, enabling a wider and more resilient quantum network coverage. But distance isn’t exactly helpful in increasing the survival of information-carrying qubits, and high-orbit satellites will require improved on-board micro-vibration suppression technology so spacecraft can send precise optical or laser signals. Fortunately, photons within the 1550nm band (used in our day-to-day fiber optics communications) can be leveraged for this, facilitating a number of implementation and adaptation steps.

Current satellite-based quantum communications leverages the entanglement susceptibility of photons — individual light particles that can be quantized — towards using them as information carriers. Much like the binary system of information, a single photon can be polarized in one way or another — in being able to discern more than one state, they can be encoded into information.

Due to this ability to encode useful information within photons, QKD leverages the property of entanglement to make it so that two separate photons become a qubit pair — a single system, where to describe one of them requires describing the other. Because they’re light-based, photonic qubits showcase a higher resilience to outside interference, placing them as the prime candidates towards ferrying sensitive information across long distances — and specifically between the Earth, its atmosphere, and space.

At this stage, the information (the entangled photon) reaching its destination or not becomes dependent on the absence of interference that could lead to a collapse of its entangled state. This collapse would also lead to the loss of all in-transit information.

What light-speed quantum key distribution and quantum-key-encrypted communications will lead to is to a future where certain communications streams will become unhackable but, up to a point, blockadeable (up to a point) by savvy-enough opponents. This has implications in the design of quantum communications systems for higher reliability and redundancy, as interrupted communications can have just as dire consequences as it being unencrypted.

Micius was recently used to successfully distribute quantum keys between the cities of Delingha and Nashan (756 miles apart) and, in 2018, between the Austrian city of Braz and the Chinese city of Xinglong — an intercontinental quantum key distribution separated by some 4,700 miles (7,600 kilometres). Meanwhile, Europe’s own QKD system as orchestrated by the European Space Agency (ESA) expects to see the first European QKD satellite — Eagle-1 — in space from 2024.

It’s clear that China is looking to capitalize on the years of experience it has low-orbit QKD system, and plans to increase its resiliency and redundancy. Considering the limited throughput of current QKD systems, however, it’ll likely be decades before these applications become pervasive — and even more before they’re used for communications in non-critical systems.

For the first time, a research team with the University of York has managed to send unhackable quantum information between Ireland and the UK. Leveraging ultra-low-loss fiber infrastructure capable of carrying "multiple terabits" of information, the researchers demonstrated how photonic qubits can already cover the 224 kilometers between the Irish Sea.

The feat - which included the collaboration of The Quantum Communications Hub and infrastructure provider euNetworks -  simultaneously set a new record for longest-distance subsea quantum communication. 

It's perhaps sometimes easy to get carried away with the details of new and more powerful Quantum Processing Units (QPUs), or clever new ways of using quantum engineering to use the subatomic world as our calculators. But perhaps the best measure of a technology lies in how it's actually applied, rather than idealized; and the reality is that quantum communication is already being tested over commercial-grade optical fiber infrastructure. And if there's something we know from our own PC world, it's that compatibility too can be key. 

Quantum communications takes advantage of the property of quantum entanglement - where two qubits become linked across distance, and where you can't describe one without also describing the other. The issue with entangled quantum states, however, is that they're fickle and prone to failure - their useful states can be collapsed through any outside interference, including any attempts at pulling data from them. This instability is why a qubit traversing a partly underwater, 224 kilometer distance within a high-tech fiber-optics cable is so impressive. Back in 2021, quantum communication had already been shown across 660 kilometers - but there were no high-pressure water bodies in the way.

The research serves as a reminder of how far along quantum communications already are towards commercialization. The cable bit should be one of the lesser problems: Rockabill, whose fiber optics elements are composed of Corning glass, was installed back in 2019. At the time, it was indeed among the latest and greatest available, but technology has since advanced. Considering how it took only eight months for Rockabill to be installed, however, it doesn't seem that quantum-compatible infrastructure will be the bottleneck - it's simply the case that we are already using it for other purposes. 

Rockabill being a fraction of the euNetworks' Super Highway web of fiber-optics connections means that infrastructure is already ahead of the quantum curve. It's more likely that any bottleneck will lie at the ends of the fibre optics, in the field of sensors, their sizes, reliability, ease of manufacturing, and ultimately, cost.

“Many large companies and organizations are interested in quantum communications to secure their data, but it has limitations, particularly the distance it can travel,” said research lead Professor Marco Lucamarini. “The longer the distance, the more likely it is that the photon – the particles of light that we use as carriers of quantum information – are lost, absorbed or scattered in the channel, which reduces the chances of the information reaching its target. This presents a problem when organizations need to send private digital information to other cities or other countries, where the additional challenge could also be an ocean between the communications’ start and end point.”

Researchers with the Nippon Telegraph and Telephone Corporation (NTT) and the Hokkaido National University Organization Kitami Institute of Technology have succeeded in breaking the record for the longest-distance power delivery through a single fiber optics cable. Previously only achieved for a distance up to two kilometers (due to optical intensity limits within the fiber itself), the results open up venues for disaster relief/recovery and power delivery in remote locations without the need for complex electrical infrastructure to be built (or rebuilt). The researchers managed to deliver in excess of 1 W (in addition to the high-speed data exchange allowed by fiber optics) across a 10km distance.

The feat makes use of NTT's multicore optical fiber (MCF) — a technology that keeps compatibility with existing fiber optics infrastructure through its standard glass diameter of 125 μm. But due to it being multi-core (meaning that there are a number of individual optical strands within the standard glass), each of these cores can be leveraged for their own purpose. In order to maximize power delivery, however, using multiple cores for power transmission may be required. 

That's exactly what the research team did, however. The scientists pushed a light source with a wavelength of 1,550 nm into all four optical cores. For data transmission, two of the cores were injected with an additional wavelength around 1,310 nm, where both downlink and uplink data (with a transmission speed of 10 Gbps) could piggyback on. In the end, the researchers managed to send approximately 1 W of power across a 14 kilometer distance, achieving a world-record 14 W/km for their optical power supply system.

There's been a number of advances in photonics technology in the last few years, and this particular research now enables long-range energy delivery while also enabling wired communications. It's an incredibly simple and cost-effective solution for low-power delivery across distances and lacking electrical infrastructure, and one that's sure to see applications in the future.

Today at the Forum for Future Technologies in Russia, President Vladimir Putin was shown through the country's current state in quantum computing — and it might be more developed than many would initially believe. Rosatom, the Russian State Nuclear Energy Corporation that's the main governmental body responsible for coordinating national efforts relating to technological innovation, showcased what it says is a 16-qubit trapped-ion-based quantum computer. And according to Rosatom's own press release on the matter, they've already run useful, molecule-simulating computations on it. The Russian processor is said to use the same quantum annealing technology that's been shown to be impressively useful for military applications.

There's quite a bit to digest here, assuming we don't have another "quantum, but not really" situation on our hands - one that mirrors Iran's recent attempt to shine a light on its quantum computing capabilities that, amusingly, backfired. (Perhaps someone in Iran should have read our "What is Quantum Computing" article.)

Developed by Russia's Lebedev Physical Institute of the Russian Academy of Sciences (LPI) and the Russian Quantum Center, the quantum computer seems to make use of trapped ion qubits with integrated photonics - an approach leveraged by marquee quantum computing companies such as Quantinuum (the child fathered by the merger of Honeywell and Cambridge Quantum) and IonQ to achieve higher qubit count scalability while also reducing the impact of noise. In quantum computing, noise refers to changes in the qubits' environment (such as vibrations, electromagnetic interference, temperature, and others) that destroy qubits' processing capabilities by collapsing the qubits' entanglement and state (and as such, the information they were processing as well).

Rosatom's push for Russia's quantum advances started at least from November 7th, 2019, when it launched Russia's program for the development of quantum computing and algorithmic solutions. Just one year later, Russia announced an investment of around $790 million in the country's quantum computing capabilities, covering quantum research funding for the next five years. More recently, as early as February 2022, ROSATOM announced the creation of the National Quantum Laboratory (NQL), which aims to consolidate national quantum knowledge within one roof, with teams hailing from a number of state and private entities across Russia (and some contributions from foreign specialists as well).

All this work, and today's quantum computer demonstration, however, started long before 2019. Ilya Semerikov, a researcher at the LPI Laboratory of Optics of Complex Quantum Systems, explained that work on trapped ions started as early as 2015. The team's efforts were vindicated when they built a quantum clock for GLONASS (the Russian geo-sat system that's equivalent to our Global Positioning System (GPS). That win led Rosatom to include trapped ion technology in its quantum computing roadmap as one possible technology to exploit.

"There was a big discussion about whether to include our ion platform in it [Rosatom's quantum plan]. And I am grateful to Rosatom, who believed in us then," Ilya Semerikov emphasized. According to Rosatom, the scientists have been living within the laboratory for over three years until today's delivery. "Our quantum computer, which is important, is already doing useful things - modeling molecules, and not doing scientific abstraction," said Ilya Semerikov.

Rosatom quotes a joking Vladimir Putin as saying that "the main thing is that the participants do not retire" (machine translation). So perhaps the scientists being cooped in their labs for the better part of three years isn't that out of the blue.

Those sacrifices have seemingly paid off, at least according to Rosatom's press release. But it seems that Russia's showcased quantum computer isn't one built out of the same clout as IBM's Quantum Processing Units (QPUs), which have achieved a 127-qubit count already, despite being in the quantum gate and superconducting qubits' class. Instead, it seems that Rosatom's demonstrated quantum computer is of the quantum annealing type. These quantum computers don't offer the same flexibility or general performance as their gate-based counterparts, so they won't crack the "quantum advantage" equation any time soon. 

But... quantum annealing systems such as these are already delivering results outside the lab, as they're much easier to scale while being extremely focused on what they attempt to do: solving optimization problems such as BMW's 3,854-variable problem, solved by QCI (Quantum Computing Inc.) in a quantum annealing system.

Quantum annealing exploits a well-known physics principle: systems prefer to remain at their lowest-possible energy configuration. Luckily, this maps perfectly onto optimization problems that seek to find the optimal solution out of a range of possible ones, as the best solution is essentially the one with the lowest energy expenditure. Here, D-Wave shows their quantum annealing technology finding the best military solution to defend Honolulu. The program ran 67 million possibilities and excluded sixty-six thousand, nine hundred and ninety-nine others - in a mere 13 seconds.

Optimization solutions are the low-hanging fruit of quantum, but they're also highly valuable ones: there's no business, state, or military that would say no to the possibility of optimizing resource allocation, product design, logistics, and... Well, anything that offers itself to a number of possible solutions. And due to the number of variables, it'd take a linear, standard supercomputer an impractically long amount of time to sift through all of them.

It's perhaps not a coincidence that Russia's showcased quantum computer (despite only possessing 16 qubits) is of the quantum-annealing type. It's not only the lowest-hanging fruit (even if the quantum tree is an overly tall one); it's also the one that can bring the fastest turnaround on optimizing solutions that are especially impactful on the battlefield. Considering the length, horror, and expense of the Russia-Ukraine war (which has no end in sight), Russia prioritizing optimizations doesn't sound so out there. Does it?

The world's fastest data transmission speed record has been broken yet again, paving the road for increasingly instantaneous transmission of the world's entire knowledge repository. The team who achieved this feat are researchers from Technical University of Denmark (DTU) and Chalmers University of Technology in Gothenburg, Sweden. Their novel technique leverages a single laser and a single, custom-designed optical chip enabling throughputs to the tune of 1.8 Pbit/s (Petabits per second) — double today's global internet traffic.

For scale, the same data transmission record had been previously broken back in August 2020 with a then-astonishing 178 Tbit/s (Terabits per second) — enough to download Netflix's then-existing catalog in less time than you could count a single Mississippi. But that speed is only around 10% of today's maximum throughput announcement, meaning that in less than three years we've improved the technology tenfold.

Some of the secret sauce behind the record hails from the proprietary optical chip, which can take the input from a single infrared laser to create a spectrum of many colors. Each color represents a frequency that's not unlike the teeth of a comb, perfectly and equally distinguishable from one another (this is exactly the process through which we distinguish colors, by detecting the different frequencies of light materials reflect towards us). And since these multiple frequencies are perfectly distinguishable from one another, with a set separate distance between each, that information can be transmitted across each of these frequencies (or channels). The more colors/frequencies/channels, the more data can be sent, which led to the establishment of the new 1.8 Pbit/s transmission speed world record.

Today's optical technology would require around 1,000 different lasers to produce the same amount of wavelengths capable of transmitting all of this information. That in itself is a problem; each additional laser increases energy consumption, multiplies the number of failure points, and makes the setup harder to manage.

Victor Torres Company, professor at Chalmers University of Technology and head of the research group that has developed and manufactured the chip, explained something of the team's work:

“What is special about this chip is that it produces a frequency comb with ideal characteristics for fiber-optical communications – it has high optical power and covers a broad bandwidth within the spectral region that is interesting for advanced optical communications,” he said.

Interestingly, like many other scientific "missteps", the initial design purpose wasn't to break the world's transmission throughput record:

“In fact, some of the characteristic parameters were achieved by coincidence and not by design,” Victor Torres Company added. “However, with efforts in my team, we are now capable to reverse engineer the process and achieve with high reproducibility microcombs for target applications in telecommunications.”

The research has practical applications that should be scaled out of the lab, as well - the idea isn't for this technology to grab a headline and become abandoned to the corridors of vaporware. According to professor Leif Katsuo Oxenløwe, Head of the Centre of Excellence for Silicon Photonics for Optical Communications (SPOC) at DTU, the technology shows tremendous potential for being scaled up:

“Our calculations show that—with the single chip made by Chalmers University of Technology, and a single laser—we will be able to transmit up to 100 Pbit/s. The reason for this is that our solution is scalable—both in terms of creating many frequencies and in terms of splitting the frequency comb into many spatial copies and then optically amplifying them, and using them as parallel sources with which we can transmit data. Although the comb copies must be amplified, we do not lose the qualities of the comb, which we utilize for spectrally efficient data transmission.”

It's mind-blowing to think about so much information that it could strain a 100 Pbit/s connection — around 100 times the traffic flow of today's internet. But build the highways, as they say, and the traffic will come.

A team of researchers with the Network Research Institute of the National Institute of Information and Communications Technology (NICT, Japan) have achieved a new bandwidth world record over a single, standard-diameter optical fiber. 

The researchers achieved a bandwidth of around 1.53 petabits per second by encoding information across 55 different light frequencies (a technique known as multiplexing). That's enough bandwidth to carry the entire world's Internet traffic (estimated at less than 1 Petabit per second) through a single fiber optics cable. That's a far cry from the gigabit connections we mere mortals have at our disposal (in the best scenarios): to be precise; it's a million times higher.

The technology works by taking advantage of the different frequencies of light available across the spectrum. Since each "color" within the spectrum (of visible and invisible light) has its own frequency that's distinct from all others, it can be made to carry its own independent information stream. The researchers managed to unlock a spectral efficiency of 332 bits/s/Hz (bits per second per Hz). That's a three-times higher efficiency than their best previous attempt, back in 2019, which achieved a spectral efficiency of 105 bits/s/Hz.

The researchers managed to transmit information on the C-band throughout 184 different wavelengths - the separate, non-overlapping frequencies that were made to carry information within the fiber cable simultaneously. Before being sent through the fiber optics cable, the light was modulated to transmit 55 separate data streams (modes). After modulation (and like most fiber optics cables currently deployed), it needed a single glass core to transmit all that data. When data is sent (across 184 wavelengths and 55 modes), the receiver decodes the different wavelengths and modes to gather their data. In the experiment, the distance between sender and receiver was set at 25.9 kilometers.

More attentive readers might remember that we recently covered a similar development - a prototype photonics relay that achieved a bandwidth of 1.84 petabits per second. That's higher than this research managed to achieve, but the problem with that solution is that it emplys a photonic chip that's still in the experimental design stages. As such, this particular research is likely to be deployed much sooner (it only requires that the fiber optics infrastructure be slowly upgraded to its design). It would also seem that it already makes more financial sense, as the difference between the entire world's traffic and the 1.54 petabits/s transmission rates (I have to reinforce that it happens over a single, standard diameter fiber optics cable) still leaves that much bandwidth on the table. And considering the number of wavelengths the researchers employed in past experiments (but not this one), there's a clear way to scale bandwidth further into the future.

For further information about the record 1.53 petabits/s data transfers, you can check out the official NICT press release, which is filled with technical details close to the bottom of the page.

Scientists from the Technical University of Denmark in Copenhagen have achieved 1.84 petabits per second data transfers using a single photonic chip connected via a single optical fiber cable. The feat was accomplished over a distance of 7.9 km (4.9 miles). For some perspective regarding this achievement, at any time of day, the average internet bandwidth being used by the whole world’s population is estimated to be about 1 petabit/s.

With the ever increasing amounts of data shifted across the internet for business, for pleasure, and software downloads or updates - infrastructure firms are always on the lookout for new ways to increase the available bandwidth. The 1.84 petabits/s over a standard optical cable using a compact single chip solution will therefore hold much appeal.

Photonic chip technology holds great promise for optical data transfer purposes – as the processor and the transfer medium both work with light waves. The New Scientist explains in simple terms how the Danish scientists, led by Asbjørn Arvad Jørgensen, managed to deliver such bandwidth with the resources at hand.

Firstly, the data stream used in the trial was split into 37 lines, with each one sent down a different optical thread in the cable. Each of the 37 data lines were split into 223 data chunks corresponding to zones of the optical spectrum. What this allowed is for creating a "frequency comb" where data was transmitted in different colors at the same time, without interfering with other streams. In other words a “massively parallel space-and-wavelength multiplexed data transmission” system was created. Of course, this splitting, and re-splitting massively increased the potential data throughput supported by a fiber optic cable.

It wasn’t easy to test and verify 1.84 petabits/s bandwidth – as no computer can send, or receive, never mind store, such a humungous amount of data. The research team used dummy data over individual channels to verify what would be the full-on bandwidth capacity. Each channel was tested individually to ensure data received matched what was transmitted.

In action, the photonic chip splits a single laser into many frequencies and some processing is required to encode light data for each of the 37 data optical fiber streams. A refined fully capable optical processing device should be possible to build at approximately the size of a match box, according to Jørgensen. This is a similar size to current single color laser transmission devices used by the telecoms industry.

Ut is reassuring that we will be able to keep the same fiber optical cable infrastructure, but replace matchbox-sized optical data encoders / decoders with the similar sized photonic chip powered devices, potentially delivering an effective 8,251x increase in data bandwidth. The researchers say there is enough potential shown in their work to inspire “a shift in the design of future communications systems.”

For further information about the record 1.84 petabits/s data transfers you can check out the Petabit-per-second data transmission using a chip-scale microcomb ring resonator source paper.

Fujitsu today announced it cracked Tbps+ speeds on fiber networking communication, unlocking the ability to transfer the equivalent to six 25GB Blu-ray discs in a single second. 

The company announced its most recent photonics technology (which is expected to have market availability by early 2023) unlocks up to 1.2 Tbps per wavelength, while enabling four times longer signal reach before the signal begins to decohere. With the roll-out of 5G tech and the development of even faster communication protocols, there'll be a greater and greater need to efficiently and rapidly shuffle data around — something photonics is particularly keen at.

Fujitsu claims breakthroughs across the board; not only are the signal reach and bandwidth per wavelength figures unheard of, but the company also managed to cut power consumption down to an industry-leading 120mW per transmission capacity (Gbps). 

The approach is an integrated one, and isn't limited to materials breakthroughs. Fujitsu designed its new optical networking solution in parallel with the world's first liquid-cooling solution for optical networking. A state-of-the-art digital signal processing LSI (DSP) is also deployed in the self-contained solution, which even pairs a low-level machine learning capability that aims to optimize power consumption and traffic. 

This last point is crucial as, according to Fujitsu, an optical networking system is rarely optimized to its implementation environment, and can't easily adapt to changing circumstances (such as signal or equipment degradation). The company says implementation of its machine learning system makes it possible to automatically capture and analyze the status of optical network components such as optical fibers and optical transmission systems with a high degree of accuracy, allowing for on-the-fly adjustments according to operating conditions.

All the innovations have led to a system that isn't limited to breaking records in the amount of data it can transmit. Fujitsu's networking solution also occupies a third of the space of a conventional air-cooled optical networking solution and has a greater operational capacity due to the improved cooling system. 

According to the company, all these improvements have led to a severely cut-down CO2 footprint for their networking solution (the company quotes a 70% reduction across manufacturing, logistics, and operation), which is definitely more than a simple checkmark on the "environmental sustainability" book.

The death of Moore's Law has been punted back and forth between engineers and pundits any number of times at this point. And as silicon-based transistors become smaller and smaller, manufacturers have had to grapple with increased temperature densities (more transistors in a smaller area, generating more heat), not to mention other issues that naturally arise from closely packing smaller, faster transistors. 

And even as chiplet technologies such as TSMC's InFO_LI and Intel's Foveros 3D technology have enabled increased functionality and the ability to pair multiple chips in the same substrate, connecting those chips to each other still requires electrical wires carrying electrons around. Flying electrons means both increased temperatures (from traveling through semiconductor's resistance) and increased power consumption. As covered by The Register, startup Lightmatter has another idea: connect chips without electrical wiring altogether. The company took to HotChips with its alternative: photonics.

"Arrays of electrically interconnected chiplets suffer fundamentally from issues, including concatenating power consumption,” Nicholas Harris, founder and CEO of Lightmatter said in the company's HotChips presentation.

The issue is clear and has already been well-identified: The more chiplets connected in a single package, the more interconnections those chiplets must have with each other in order to trade the data required for computation. While electricity is a fast medium, it's not the fastest available--that prize is reserved for light. The company's Passage technology thus aims to bring photonics to the chiplet era, by allowing different chips to be interconnected through nano-photonic wave guides. These essentially use photons (instead of the more ubiquitous electrons) to ferry information, with extremely low signal loss and much increased bandwidth. 

Interestingly, AMD itself has been exploring photonics designs that could allow for information transfer for its architectures as well. For its part, Intel has a whole research center dedicated to it.

“Passage is diced from a 300mm Silicon Photonics wafer that includes lasers, optical modulators, photo detectors, and transistors all side-by-side integrated in the platform,” Harris continued.

Chiplets to be interconnected (such as ASICs, CPUs, GPUs or memory chips) are then laid on top of this photonics-powered 'sandwich.'

“Because Passage has integrated lasers and transistors, the co-packaged chips don’t have to deal with any of the complexity of the transmit, receive, or circuit switching photonics elements,” Harris said. “Each Passage tile can house an array of heterogeneous chips. For example, a tile might contain two different types of ASICs and maybe two HBM stacks.”

The company claims its approach brings sub-2 nanosecond hop times between the information's exit and entry point, irrespective of distance between points (so the farthest chiplets will communicate as fast as the closest ones). The nano-photonic waveguides used by Lightmatter have advantages over traditional fiber optic interconnects in that they're much smaller: The company says it can fit as many as 40 waveguides in the space of a single optical fiber. 

According to Lightmatter, this allows them to provide 96 TBps of bandwidth to each die. Compare that to AMD's Infinity Fabric maximum theoretical bandwidth of 800 Gbps. Off-chip communication--from Passage through to other systems via fiber arrays--peaks at around 16 TBps.

Furthermore, since Passage is a fully customizable interconnect-on-a-package, manufacturers no longer have to design their own interconnect designs (such as AMD's Infinity Fabric or Intel's EMIB). They can simply drop their devices into a photonics-powered Passage that can accommodate up to 48 full-reticle chips (full reticle meaning that these chips can occupy as much area as manufacturing processes allow them to), and provides an already-existing interconnect between them.

Despite this being photonics through and through, chips planted on Passage will be of the more traditional, silicon-based transistor type, which means they still require electrical communication. This is also supported by using Through Silicon Vias (TSVs), which also deliver power to the dies and support the PCIe and CXL standards.

Moore's Law isn't dead, but only because of chip designer's ingenuity. Lightmatter's approach is just another in a series of steps that aim to sustain computing's acceleration today and tomorrow. The only question is, how willing will major chip companies be to adopt Lightmatter's tech when they are also spending large amounts of money and engineering resources to develop their own?

Researchers from Simon Fraser University may have just released the photonic springs that accelerate the quantum internet. In a paper published in Nature, the researchers demonstrated an emergent capacity in silicon qubits to produce a "photonic link" between each other. Furthermore, this same photonic capability may be easily integrated with the existing fiber optic infrastructure that already carries data across a reasonable (yet still insufficient) portion of society. That is bound to provide immense savings on deploying a quantum internet - and as we all know, the cost is (mostly) king.

The authors' paper describes observations carried on particular types of qubits: "T-center" photon-spin qubits, a kind of qubit that takes advantage of a specific luminescent defect in silicon - more specifically, InGaAs (Indium gallium arsenide), also explored in CPU manufacturing technologies. Silicon qubits have already shown remarkable coherence times - which relate to how resistant qubits are to outside interferences that would cause them to collapse and lose their information in the process, becoming unusable for the workload at hand.

And with more fantastic coherence times - and the comparative ease with which these "T center" qubits can be linked - comes the capability to perform more and more significant calculations. In their experiment, the researchers observed the effect in over 1,500 T Center qubits, ensuring they can replicate it - a healthy indicator for the potential scalability of their solution.

"This work is the first measurement of single T centers in isolation, and actually, the first measurement of any single spin in silicon to be performed with only optical measurements," said Stephanie Simmons, Canada Research Chair in Silicon Quantum Technologies.  

"An emitter like the T center that combines high-performance spin qubits and optical photon generation is ideal to make scalable, distributed, quantum computers," she continued, "because they can handle the processing and the communications together, rather than needing to interface two different quantum technologies, one for processing and one for communications."

Some qubit solutions in the market already use photonics to enable scaling between individual Quantum Processing Units (QPUs) - such as the diamond-based qubits from Quantum Brilliance. However, others don't naturally possess the ability to send information through photonics without coupling a complementary system. It, in turn, adds one more step in the quantum information chain, introducing variables in a technology that is erratic enough to any variations in its environment. The cost of pairing both technologies is also another factor to consider.

"T Center" photon-spin qubits, on the other hand, already emerge from a light-based phenomenon. Furthermore, they emit light at the same wavelength today's fiber communications and telecom networking equipment use - while retaining a >99% fidelity.

"With T centers, you can build quantum processors that inherently communicate with other processors," Simmons says. "When your silicon qubit can communicate by emitting photons (light) in the same band used in data centers and fiber networks, you get these same benefits for connecting the millions of qubits needed for quantum computing."

There's another inherent advantage towards silicon-based qubits: manufacturability. The tech industry has been manufacturing silicon-based transistors for decades already, and we're now reaching the point where even silicon manufacturing has to consider quantum effects. As a result, the quantum and silicon industries could converge and bring benefits of scale - and importantly, cost - towards a sector expected to be worth a cool $4531.04 billion by 2030.

"By finding a way to create quantum computing processors in silicon, you can take advantage of all of the years of development, knowledge, and infrastructure used to manufacture conventional computers, rather than creating a whole new industry for quantum manufacturing," Simmons concluded. "This represents an almost insurmountable competitive advantage in the international race for a quantum computer."

And indeed, it may very well be.

A Quantum Processing Unit (QPU) developed by Toronto, Canada-based Xanadu, has outrageously outperformed a classical system in a computing task. We say outrageously because that's one of the few adjectives that encapsulates the performance difference between both systems: the QPU, named Borealis, completed the computing task revolving on gaussian Boson sampling (GBS) in just 36 microseconds. According to the paper published in Nature, today's algorithms and supercomputers - the highest-performing classical computing systems - would take an inhuman scale of 9,000 years to accomplish the same task. Nevertheless, it is enough for the team to claim the coveted quantum advantage badge of honor.

Remember that the basic unit of quantum computation, the qubit, can simultaneously represent 0 or a 1. The orders-of-magnitude higher performance in specific tasks than their classical counterparts comes from quantum computers not working on exact computation methods. Instead, they describe how probable a solution is - before making a measurement.

Sadly, there's no practical use for the GBS workload; it's one of the possible benchmarks for testing the performance of quantum processing solutions against classical computers, a space that's still teeming with benchmark standardization attempts from players such as IBM. 

Xanadu's Borealis is based on the increasingly relevant photonics field as it applies to computing. Specific quantum computing chips use qubits borne from silicon quantum dots, topological superconductors, trapped ions, and other technologies, with some already employing photonics as scaling mechanisms to create interconnected QPUs.The Borealis QPU is photonics-based through and through, unlocking lightspeed-esque operations through its photon-based qubits. The researchers expect photonics-based quantum computing solutions to ultimately provide the most effective way to scale quantum computers' performance. It is mainly due to the advantages of time-domain multiplexing, which allows for multiple, independent data streams to travel simultaneously masked as a single, more complex signal.

The researchers managed to squeeze as many as 219 photon-based qubits onto the Borealis QPU - although the programmable nature of the gates means that that number isn't fixed, and the mean active number of photons was 129. That's still more than IBM's current Eagle QPU, which features 127 qubits - but the company's roadmap does lay out plans to introduce its Osprey QPU, which packs as many as 433 of IBM's superconducting transmon qubits, later this year.

Another element that allowed for the increased quantum performance of Xanadu's Borealis is that the researchers have designed their system with dynamic programmability on all implemented quantum gates. This base circuitry allows for quantum operations to be performed, employing varying numbers of qubits. The programmable aspect of Borealis' quantum gates thus unlocks an FPGA-like architecture that one can reconfigure according to the task.

The researchers further ensured that the computed solutions to the GBS task were correct, which should settle the debate on whether or not quantum advantage was achieved. Xanadu is now bound to continue developing its solution, showcasing very promising results. 

Ultimately, they'll also have to convert Borealis into a commercially-available solution. However, researchers can already take the QPU for a spin through Xanadu's cloud and Amazon Braket. But the results bode well not only for the future of photonics but also for photonics-based quantum computing and should be one of the technologies to look at until the anticipated explosion in quantum computing capability currently expected by 2030.

Scientists from the University of Pennsylvania claim to have designed a photonic chip which can recognize an image in under 0.57 nanoseconds. The test chip was just 9.3mm square, and is said to be the first deep neural network implemented entirely on a scalable integrated photonic device.

It is worth emphasizing the sheer speed of image classification that the new photonics chip affords. If run continuously, the 0.57 nanosecond recognition time means the chip could classify a remarkable 1.75 billion images per second. In other words it is recognizing images at a rate of 1.75GHz.

Tom's Hardware reported on advances in optical chip and photonics technology on multiple occasions. This kind of technology is increasingly popular in super high-frequency applications where light-based components don't suffer from the resistance/heat problems that would affect traditional microelectronics with their wire interconnects. Thus we have seen photonic chip development examples cluster around solutions like high speed networking.

The scientists at the University of Pennsylvania are using both photonic technology and neural networks for their impressive image processing achievements. Traditionally, silicon chips like CPUs and GPUs have been used to process neural nets, and firms like Nvidia boast about the speeds at which their processors can run AI systems to recognize images (e.g. faces, objects), sounds, and video.  However, the University of Pennsylvania scientists are the first to simulate neurons using an optical chip, with all the benefits this technology can deliver - such as very high speeds and low power consumption.

The research paper reveals that the scientists trained their optical neural net with letters of the alphabet and achieved a successful recognition rate for hand drawn characters of roughly 90%. This isn't the most complex of neural net AI tasks, which helped with the breathtaking speeds claimed. Moreover, the texts were limited to a 6x5 pixel grid, making things even simpler for the neural net to learn, and to accurately recognize.

With the scientists claiming scalability, it is reasonable to assume subsequent developments will make this photonic chip more useful in computer vision, 3D object classification, medical diagnosis, and other tasks. As for speed, the scientists say that they could up the recognition rate of the current chip to 0.1 nanoseconds using the best contemporary fabrication processes. That would mean the potential to classify 10 billion images per second, all else being equal.

Above we mentioned the use of neural nets to classify videos and 3D objects, and the Pennsylvania team intends to train their sub-1cm square photonic chips for recognition tasks with these inputs. Furthermore, they confirm that they will work on photonic chips with more pixels and neurons for classifying more complex and higher resolution images.

A team of researchers with Japan's NTT Corporation, the Tokyo University, and the RIKEN research center have announced the development of a full photonics-based approach to quantum computing. Taking advantage of the quantum properties of squeezed light sources, the researchers expect their work to pave the road towards faster and easier deployments of quantum computing systems, avoiding many practical and scaling pitfalls of other approaches. Furthermore, the team is confident their research can lead towards the development of rack-sized, large-scale quantum computing systems that are mostly maintenance-free.

The light-based approach in itself brings many advantages compared to traditional quantum computing architectures, which can be based on a number of approaches (trapped ions, silicon quantum dots, and topological superconductors, just to name a few). However, all of these approaches are somewhat limited from a physics perspective: they all need to employ electronic circuits, which leads to Ohmic heating (the waste heat that results from electrical signals' trips through resistive semiconductor wiring). At the same time, photonics enable tremendous improvements in latency due to data traveling at the speed of light. 

Photonics-based quantum computing takes advantage of emerging quantum properties in light. The technical term here is squeezing — the more squeezed a light source is, the more quantum behavior it demonstrates. While a minimum squeezing level of over 65% was previously thought required to unlock the necessary quantum properties, the researchers achieved a higher, 75% factor in their experiments. In practical terms, their quantum system unlocks a higher than 6 THz frequency band, thus taking advantage of the benefits of photonics for quantum computing without decreasing the available broadband to unusable levels.

The researchers thus expect their photonics-based quantum design to enable easier deployments — there's no need for exotic temperature controls (essentially sub-zero freezers) that are usually required to maintain quantum coherence on other systems. Scaling is also made easier and simplified: there's no need to increase the number of qubits by interlinking several smaller, coherent quantum computing units. Instead, the number of qubits (and thus the performance of the system) can be increased by continuously dividing light into "time segments" and encoding different information in each of these segments. According to the team, this method allows them to "easily increase the number of qubits on the time axis without increasing the size of the equipment." 

All of these elements combined allow for a reduction in required raw materials while doing away with the complexity of maintaining communication and quantum coherence between multiple, small quantum computing units. The researchers will now focus on actually building the photonics-based quantum computer. Considering how they estimate their design can scale up towards "millions of qubits," their contributions could enable a revolutionary jump in quantum computation that skips the expected "long road ahead" for useful qubit counts to be achieved.

LightOn, a company specializing in photonics processing, has announced the world's first integration of its "Appliance" Optical Processing Unit (OPU) in France's Jean Zay supercomputer. This marks the first time that a photonics coprocessor (which transmits and processes information via light instead of electrical current) is integrated in a High Performance Computing (HPC) scenario - and in a Top500 machine (currently ranked 105th), no less.

LightOn's photonics products were first deployed in a data center four years ago, integrating the technology into already-existing computing infrastructure. With data processing requirements booming on account of recent advancements in Machine Learning and AI applications, computing is becoming more and more heterogeneous - and more specialized. This opens the door to ecosystems featuring multiple architectures and accelerators (CPUs, GPUs, TPUs, OPUs...), all working in tandem to deliver the best performance. System complexity does increase, but so does performance and efficiency. One area that photonics processing excels in is COVID research - specifically in Molecular Dynamics Studies, an area of computing which is particularly performant on photonics accelerators due to their incredibly low latency times.

LightOn's Appliance is an integrated computing unit that's built into a 2U form factor for quick and easy integration. Powered by LightOn's Aurora 2 OPU, the Appliance can reach a peak performance of 1.5 PetaOPS at 30 W TDP. In certain scenarios, that means the Aurora 2 is capable of processing up to 1,900 dense matrix-vector multiplications per second.

LightOn claims its Appliance coprocessor can deliver performance that's 8 to 40 times higher than GPU-only acceleration. However, other photonics products such as Lightelligence's PACE (still in demo stages) have claimed performance uplifts that are hundreds of times that of conventional semiconductor hardware. And because photonics doesn't use electrical current for information processing, there's no Ohmic heating - this means higher efficiency and more palatable running costs.

This is but the first such integration of photonics in an HPC scenario, but it sure won't be the last. It seems AMD was right: heterogeneous is the future. It's just that the future sometimes comes later than expected.

Intel today announced a new breakthrough for co-packaged silicon photonics optics Ethernet switches. The company has integrated next-generation 1.6Tbps silicon photonics engines with the 12.8Tbps programmable Tofino 2 Ethernet switch Intel acquired from Barefoot Networks last year.

With the emergence of hyperscale cloud data centers, demand for data bandwidth has become practically limitless. To provide cost-effective interconnect solutions, Intel has been on a path to increase the bandwidth of its silicon photonics, which has been available in a 100Gbps pluggable optics form factor since 2016. Last year, Intel announced it would start production of 200Gbps and 400Gbps in the first half of 2020 and has used the present demonstration to reiterate this. Intel disclosed it has shipped over 3 million 100G pluggable transceivers to date.

Simultaneously, Intel has also been looking to further integrate its silicon photonics technology. In the common pluggable topics (QSFP28) form factor, the optics are installed in the switch faceplate, which in turn is connected to switch SerDes ports using an electrical trace. However, Intel says that as bandwidth grows, connecting the pluggable optics to the SerDes becomes more complex and consumes more power.

This is where co-packaged optics come in, which Intel said is an industry-first. In this methodology, the optical port is placed near the switch, within the same package. This reduces power and enables the continued scalability of switch bandwidth, Intel described. The integrated switch package “features a combination of co-packaged optical ports and copper ports supporting front-plate cages for optical modules or copper cables.”

It appears Intel used a future version of its silicon photonics technology, as it uses 1.6Tbps silicon photonics engines from Intel’s Silicon Photonics Product Division. The engines are “realized as 4 ports of 400GBase-DR4 interfaces”, and are designed and manufactured in the Intel silicon photonics platform, according to Intel. For comparison, the current 100Gbps silicon photonics uses four 25Gbps ports. In silicon photonics, the laser is integrated on-chip and manufactured on Intel's 300mm wafer CMOS technology.

For the switch, Intel has leveraged the 12.8Tbps Tofino 2 switch ASIC from Barefoot Networks. The Tofino 2 switch consists of a multi-die package that makes the co-packaging easier as well as upgrading the SerDes. This is reminiscent of Intel’s chiplet approach with its 10nm Agilex FPGA.

Intel notes that the technology is “ready” and represent a first step towards optical I/O with silicon photonics:

“Our co-packaged optics demonstration is the first step to making optical I/O with silicon photonics a reality”, said Hong Hou, Intel corporate vice president and general manager of the Silicon Photonics Products Division. “We share the industry belief that co-packaged optics offers power and density advantages for switches at 25 Tbps and higher, and ultimately is a necessary and enabling technology for bandwidth scalability in future networks. The timing of this demonstration shows the technology is ready to support our customers’ requirements.”

Intel acquired Barefoot Networks last year. We speculated at the time that it would integrate both technologies and was a major reason for the acquisition. Today’s announcement of Intel’s integrated switch package seems to confirm this. Intel said it is currently demonstrating the technology to customers, but did not provide a timeline for a commercial release.