Raja Koduri, a legendary GPU architect from ATI Technologies, AMD, Apple, and Intel, on Tuesday said he had founded a new GPU startup that emerged from stealth mode today. Oxmiq Labs is focused on developing GPU hardware and software IP and licensing them to interested parties. In fact, software may be the core part of Oxmiq's business as it is designed to be compatible with third-party hardware.

Another RISC-V-based 'GPU' for AI

Oxmiq develops a vertically integrated platform that combines GPU hardware IP with a full-featured software stack aimed at AI, graphics, and multimodal workloads where explicitly parallel processing is beneficial. On the hardware side, Oxmiq offers a GPU IP core based on the RISC-V instruction set architecture (ISA) called OxCore, which integrates scalar, vector, and tensor compute engines in a single modular architecture and can support near-memory and in-memory compute capabilities.

Oxmiq also offers OxQuilt, a chiplet-based system-on-chip (SoC) builder that enables customers to create their own SoCs that integrate compute cluster bridge (CCB, which probably integrates OxCores), memory cluster bridge (MCB), and interconnect cluster bridge (ICB) modules based on specific workload requirements in a rapid and cost-efficient manner. For example, an inference AI accelerator for edge applications can pack a CCB and an ICB or two, an inference SoC requires more CCBs, MCBs, and ICBs, whereas a large-scale SoC for AI training can pack dozens of chiplets. Oxmiq does not disclose whether its OxQuilt enables building only multi-chiplet system-in-packages (SiP), or is designed to assemble monolithic processors too.

Software is the key

Oxmiq's software stack is perhaps an even more important product that the company has to offer. The software package is designed to abstract the complexity of heterogeneous hardware and enable deployment of AI and graphics workloads across a range of hardware platforms, not just those using the company's IP. The core of the software stack is OXCapsule, a unified runtime and scheduling layer that manages workload distribution, resource balancing, and hardware abstraction. The layer encapsulates applications into self-contained environments, which the company calls 'heterogeneous containers.' These containers are designed to operate independently of the underlying hardware, enabling developers to target CPUs, GPUs, and AI accelerators without modifying their codebase or dealing with low-level configuration.

A standout component of this stack is OXPython, a compatibility layer that translates CUDA-centric workloads into Oxmiq's runtime and allows Python-based CUDA applications to run unmodified on non-Nvidia hardware without recompilation. OXPython will first launch not on Oxmiq's IP, but on Tenstorrent's Wormhole and Blackhole AI accelerators. In fact, Oxmiq's software stack is fundamentally designed to be independent from Oxmiq hardware, and that is a core part of its strategy.

"We are excited to partner with Oxmiq on their OXPython software stack," said Jim Keller, CEO of Tenstorrent. "OXPython's ability to bring Python workloads for CUDA to AI platforms like Wormhole and Blackhole is great for developer portability and ecosystem expansion. It aligns with our goal of letting developers open and own their entire AI stack."

What about graphics?

Having developed graphics processors at S3 Graphics, ATI Technologies, AMD, Apple, and Intel, Raja Koduri is primarily known as a GPU developer. In fact, he even positions Oxmiq as the first GPU startup in Silicon Valley in decades.

"We may be the first new GPU startup in Silicon Valley in 25+ years," wrote Koduri in an X post. "GPUs are not easy."

However, it should be noted that Oxmiq is not building a consumer GPU like AMD Radeon or Nvidia GeForce. In fact, it does not develop all the IP blocks necessary to build a GPU, unlike Arm or Imagination Technology: it does not support full consumer graphics features out-of-the-box (such as texture units, render back ends, display pipeline, ray tracing hardware, DisplayPort or HDMI outputs), so Oxmiq licensees must implement them in silicon themselves, if they plan to build a GPU.

Asset low strategy

Raja Koduri continues to push his high bandwidth vision for computing, but this time it's flash, namely HBF (High-Bandwidth Flash) from Sandisk. On Wednesday, the former graphics architect at S3, Apple, AMD (twice), and Intel, announced that he had joined Sandisk’s HBF Technical Advisory Board to guide development and strategy for High-Bandwidth Flash memory technology. Sandisk also shared a press release confirming Koduri’s new role, as well as the appointment of Professor David Patterson to the board.

In case you missed it, Sandisk outlined its newest flash memory innovation back in February this year. Dubbed HBF, the key feature of this flash would be the enabling of GPU packing up to 4TB of VRAM – with more to come in future revisions.

Of course, this isn’t for enthusiasts (yet), but the proponents of HBF want to unleash this huge memory pool attached to a GPU for AI inference workloads. When it was announced, we learned that HBF would weave its magic using multiple high-capacity, high-performance flash core dies, interconnected using through-silicon vias (TSVs), on top of a logic die that can access flash arrays (or rather flash sub-arrays) in parallel. Thus, it would “deliver 8-16X [VRAM] capacity at similar cost.” It relies on BICS 3D NAND using the CMOS directly bonded to Array (CBA) design that bonds a 3D NAND memory array on top of an I/O die made using logic process technology.

TensorWave, a cloud-platform for AI workloads powered by AMD's MI Instinct accelerators, is kicking off the Beyond CUDA Summit starting today. The event focuses on the concept of the 'CUDA moat,' and how developers can optimize their AI-centric workloads using other alternatives. Attendees can expect to see demonstrations, hot takes, panels, and expert opinions from influential leaders in the AI field including computer architect icons like Jim Keller and Raja Koduri.

It's no secret that Nvidia-built GPUs constitute the majority of hardware in the AI space. Although AMD's Instinct accelerators offer performance comparable to Nvidia hardware, the already-established and mature CUDA ecosystem is indispensable to some users / organizations. Nvidia realized the potential of parallel computing on its GPUs early on and developed a proprietary platform dubbed CUDA, which is now the de facto standard for GPU-accelerated computing.

Through continuous efforts, optimizations, and the sudden rise of AI which coincidentally is powered by GPUs, Nvidia has positioned itself as a leading solution provider. In fact, 90% of Nvidia's revenue is now driven by its data-center offerings, with CUDA being a central selling point. This creates a vendor lock-in situation, where CUDA (software) effectively confines the industry to Nvidia's hardware, limiting innovation and competition.

The industry is shifting gears to a more open-source and hardware-agnostic future, but that's easier said than done. We have OpenCL, ROCm, oneAPI, and Vulkan as alternatives, however, each trails Nvidia in one or many aspects. Enter Beyond CUDA, where key figures in the AI field have rallied up to congregate and develop a more diverse and heterogeneous future. Hosted by TensorWave, the Beyond CUDA Summit will address the many challenges the AI computing industry faces, such as hardware flexibility, cost efficiency, and exploring the available alternatives to CUDA.

Platforms like ROCm require significant developments to achieve parity with CUDA. Even now, ROCm only supports a small selection of modern GPUs while CUDA maintains compatibility with hardware dating back to 2006. AMD's latest RDNA 4 GPUs are still not officially supported by ROCm. Developers have long bemoaned AMD's slow adoption of new features and support on new hardware. On the positive side, Strix Halo is now ROCm-compatible, though only on Windows.

If you live in San Jose, buckle up as the summit takes place at The Guildhouse, which is with notable irony just three blocks away from the McEnery Convention Center, the site of Nvidia's GTC, which also commences today. Participants have the opportunity to win an AMD Instinct MI210 GPU with 64GB of HBM2e memory. The event runs from 12 PM to 10 PM PDT, with four time slots for various sessions. You can learn more details about the summit here.

Nvidia caught the imaginations of many technology enthusiasts on Tuesday with its show-closing, 'just one more thing'- style reveal of the Project Digits AI supercomputer. But seasoned graphics chip designer Raja Koduri and disruptive AI server startup Tiny Corp were not enchanted by the small golden box or blinded by Jensen's shimmering jacket. Both have publicly scorned Nvidia's Grace Blackwell AI Supercomputer.

At first glance, the purported provision of 1 PFLOPS of performance in such a tiny device might seem like a vision of the future, even if it is priced at $3,000. As told by the Nvidia CEO, we might believe that Project Digits is akin to AI alchemy in a box. But all that glistens isn’t gold. The spec of the headlining GB10 Superchip, the “1 PFLOP FP4 AI Compute,” is a somewhat deceptive hint to Raja Koduri and Tiny Corp (founded by American security hacker George Hotz, AKA geohot).

Koduri’s Project Digits takedown is what you probably could describe as a gentle geeky joke with a sprinkling of cynicism. The graphics chip design icon posted, “Divide flops by 4 and multiply dollars by 2. A CES (20+25)² tip for staying grounded,” poking fun at the green team.

Koduri later elaborated that - in contrast to the big FP4 claims - by his calculations, the FP16 performance of the Project Digits AI supercomputer wasn’t that impressive. Koduri estimated that the FP16 performance of the upcoming GeForce RTX 5070 and even the $250 Intel Arc B580 “seems close” to what a Project Digits machine could muster.

You may remember last year's news coverage involving Tiny Corp and its TinyBox project. In brief, Tiny Corp and its founder were very publicly displeased with AMD’s drivers. However, its plan to democratize AI acceleration by using (AMD) gaming GPUs instead of even more costly pro/enterprise alternatives was perhaps too bold. The firm managed to grab the attention of AMD publicly, and even Dr. Lisa Su and the red team were quite gracious despite the startup’s abrasive posturing and demands.

An AI swindle?

Fast forward to CES 2025, and Tiny Corp hasn’t lost its abrasive edge. “People are begging to get swindled by a $3,000 box that says AI on the side. We always get asked if we'll launch something at that price point. We won't,” grumbled Tiny Corp before advising its casual followers to “Just buy a gaming PC.”

Earlier in the day, Tiny Corp had become seemingly irritated by the Project Digits announcement. “This is marketing. FP4 is unusable, it's 500 TFLOPS of FP8. tinybox green has 4 PFLOPS of FP8, 8x more powerful.”

Nvidia’s Project Digits won’t be available until May when it is expected to roll out for around $3,000. TinyBox computers, starting from $15,000, are available for the ‘red’ model with 738 FP16 TFLOPS and “mediocre” driver quality (another barb cast at AMD).

Intel's project Endgame, a network-based solution that aimed to bring the processing power of cloud based Intel ARC GPUs to local systems, seems to be on an indefinite hold. Announced by Intel through Twitter, the news means that the timeline for users looking to increase their available GPU grunt through the cloud has become even more blurry than it already was. Hat-tip to Bionic_Squash.

Project Endgame was meant to be available in Beta form by the end of 2022, but that time has come and gone and Intel's accelerated computing dreams seem to have faded away. Unfortunately, the tweet from Intel didn't provide any updates on the how or the why of Project Endgame's apparent hold.

Project Endgame was announced by Intel back in 2022, at a time when Raja Koduri still served as Intel’s Senior Vice President and General Manager of Intel Graphics group (Raja himself having been poached by Intel from a similar position at AMD). At the time, Raja showcased the potential of the service by piloting a low-power laptop running Epic Games’ impressive "Matrix Awakens" demo.

With that particular demo's performance demands, however, frame-rates on the low-power local computer were low and choppy; a situation rapidly corrected by activating Endgame and its "continuous compute" option, which enabled Raja's laptop to leverage a network-connected ARC GPU to accelerate the workload.

While Intel didn't confirm the scenarios where Endgame would be a feasible way to access more performance, it's believed that the company wanted to extend it from general computing to even Edge Computing and IoT - allowing even low-power, remote installations to process graphics and compute workloads (including gaming, generative AI, video encoding, and similar) so long as their network had the necessary bandwidth.

Endgame could be a truly invisible performance boost option; unlike services like GeForce Now, which generate a cloud-based OS instance where all the processing happens, Endgame would allow users to bring ARC's performance to their own installations. The project's cryptic delay is unfortunate, but considering its potential, it's likely that Intel will eventually push forward with the project - whether it remains an Endgame or not.

Deepak Patil will replace Raja Koduri as the CVP and GM of the restructured Accelerated Computing Systems and Graphics (AXG) group. Jeff McVeigh served as the interim leader for AXG after Koduri departed to head an AI gaming software start-up.

Koduri, who previously led AMD’s Radeon Technologies Group, arrived at Intel in 2017. During his time at Intel, Koduri oversaw the chipmaker’s GPU and accelerator projects, including Intel Xe, Ponte Vecchio, and Arc Alchemist. In addition, he was the Executive Vice President of the AXG group until a recent reorganization put him back into the position of Intel Chief Architect. McVeigh, the CVP and GM of the Super Compute Group (SCG), kept the AXG seat warm while Intel searched for a suitable replacement for Koduri.

“Intel will deliver competitive accelerated computing products and build scalable systems with easy-to-program software on a predictable cadence. Deepak Patil will serve as the CVP and General Manager of the Accelerated Computing Systems and Graphics (AXG) group.

Deepak recently held the position of DCAI Chief Technology and Strategy Officer. Having held senior engineering leadership positions across the high-tech industry, including being a founding member of Microsoft Azure and leading Dell’s APEX as-a-service business, he understands the important role that software and open ecosystems play in enabling application developers and service providers to bring innovative solutions to market, at scale. His rich systems, software and services experience will build on the deep silicon and graphics architecture and engineering expertise in AXG, to accelerate the growth of Intel’s position in the AI, HPC and client graphics markets.

Jeff McVeigh will return to leading the Super Compute Group while also helping Deepak ramp in his new role.”

Patil worked for Microsoft for over 15 years and was one of the founding members of Microsoft Azure. He also has a lot of engineering leadership roles under his belt: before Intel, he was the SVP of Dell's Cloud Platforms and Solutions Group. With his ample experience in cloud computing, it's easy to see why Intel hired Patil as the Chief Technology and Strategy Officer of the Datacenter and AI Group (DCAI).

AXG can be a challenge. Intel formed the group in 2021, and it has seen a fair share of challenges. Remember the Ponte Vecchio delays? Intel has killed off many non-core businesses under CEO Pat Gelsinger's direction, including Optane, SSDs, 5G modems, and — most recently — prebuilt servers, and despite many predictions to the contrary, AXG continues to soldier on after its reorganization. It will be interesting to see whether Patil can turn the group around as CVP and GM of AXG.

Just two weeks after retiring from Intel, Raja Koduri joined the board of directors of Tenstorrent, an AI and high-performance RISC-V CPU company that intends to challenge the blue giant in the coming years, as noticed by @SquashBionic. A renowned developer of GPUs for graphics and compute, Raja Koduri will be joining his former colleagues from AMD, ATI, and Intel.

Tenstorrent is developing datacenter solutions comprising of RISC-V-based AI/ML accelerators as well as high-performance RISC-V general purpose processors. The company was established in 2016 by Ljubisa Bajic, and it is presently led by Jim Keller, a renowned CPU architect who has spearheaded the creation of revolutionary processor architectures at companies such as Apple, AMD, and DEC. (We recently outlined Tenstorrent's short and mid-term plans.)

Truth to be told, a position in the board of directors does not imply that Raja will be able to influence development of CPUs or AI accelerators. Yet, he will have his word when setting Tenstorrent's strategic goals and strategic roadmap, something that is particularly important. Being developer of AI accelerators and high-performance RISC-V CPUs, Tenstorrent is essentially travelling in uncharted watersm since AI-related technologies are changing rapidly, whereas the open-source RISC-V microarchitecture is poised to change fast in general. 

To a large degree, development of AI and RISC-V hardware these days resembles development of GPUs back in the 1990's and 2000's when companies tried a variety of approaches and usually changed microarchitectures radically once in a year or two. That's something that we barely see these days in the fields of x86 and Arm CPUs as well as GPUs from companies like Arm, AMD, Nvidia, and Intel.

Koduri has already worked both with Jim Keller and Ljubisa Bajic while at AMD (with both), Intel (Keller), and Apple (Keller). Most recently Koduri and Keller worked together at Intel developing high-performance compute GPUs and CPUs, respectively. While the two have very different backgrounds and fields of expertise, both have plenty of experience in building high-performance hardware, something that Tenstorrent can certainly take advantage of. 

TSMC has reportedly won some very large production orders from Intel. The orders are not only for the next-generation Battlemage graphics processing units, but also for the follow-up Celestial architecture GPUs. Taiwan’s Commercial Times cites industry sources for its insider info, which also includes some tantalizing news nuggets regarding processes, timings and volume.

Whether Intel’s first-generation consumer GPUs have been a success is open to some interpretation. The Intel Arc Alchemist graphics cards (using TSMC 6nm silicon) were terribly late, but are now widely available and appear to be heavily discounted to shift inventory. We have reviews of Intel's Arc A770 16GB, Arc A750, and Arc A380, and thanks to the competitive pricing, some of these even rank among the best graphics cards. Intel offers a well-known brand and a third GPU architecture choice for enthusiasts who don’t blindly follow brands. Most positively, the driver team has been beating expectations with the rate and quality of updates over recent months.

Taiwanese insiders say that Intel is continuing its next-generation GPU R&D programs as previously planned. You may be eager to hear when these generations of GPUs might become available. According to the source, “Intel will launch the second-generation Battlemage graphics chip with the Xe2 architecture in the second half of 2024, and the third-generation Celestial graphics chip with the Xe3 architecture in the second half of 2026.” It is also claimed that Battlemage GPUs will be fabricated on TSMC 4nm, and Celestial on 3nm processes at TSMC.

There have been some Intel naysayers and Intel doomsters — and the recent departure of Raja Koduri doesn’t look very positive. Nevertheless, the Commercial Times insiders claim Intel has clear sight of strong demand for graphics. From the consumer side, gaming / eSports continues to be strong, and in business / enterprise there is still a growing need for accelerators for AI and other intensive computing tasks.

The last official information we got regarding Battlemage was earlier this year, via a tech press interview with Intel Fellow Tom Peterson. He made it clear that Intel had learned from several mistakes with Alchemist, and where that generation had four targeted microarchitectures, the second-gen will focus on two: Xe2-LPG and Xe2-HPG. It is hoped this focus will prevent delays and streamline driver development, as well as being more economical.

Intel has quite a lot of time to fill between now and the rumored H2 2024 launch of Battlemage. With new Intel hardware seemingly a long way off, new AMD and Nvidia products are sure to emerge in the meantime. So Intel’s driver team will have to keep working hard pushing updates and tuning performance to get the most performance possible from existing silicon. Hopefully that means when Battlemage does arrive, drivers will be the last thing potential buyers have to worry about.

Intel CEO Pat Gelsinger announced on Twitter today that Raja Koduri, the company's current Chief Architect, is leaving the company to found a generative AI gaming software startup. Koduri's exit comes five years after he joined the company in November 2017 and on the heels of a restructuring of Intel's AXG graphics unit that was announced at the end of last year. 

Koduri had assumed his position as leader of AXG last year but stepped back to be a Chief Architect after the restructuring, returning him to a position he originally held when he arrived at Intel in 2017 after a five-year stint at AMD. 

"Thank you @RajaXg for your many contributions to Intel tech & architecture-especially w/high-performance graphics that helped bring 3 new product lines to market in ‘22. Wishing you success as you create a new software co. around generative AI for gaming, media & entertainment," Gelsinger posted on Twitter. 

Raja Koduri responded, thanking Gelsinger and Intel for his time at the company. Koduri also promised to share more details about his newest adventure in the coming weeks. 

Intel has already restructured the graphics unit, so the company tells us there are no pending organizational changes due to Koduri's exit. Intel's Jeff McVeigh will continue to serve in his current role as the interim leader of the AXG team as Intel searches for a permanent leader.

Koduri joined Intel in the same time frame as fellow ex-AMD'er Jim Keller. In tandem with Keller and Murthy Renduchintala, Koduri helped design and align Intel's silicon portfolio under a new six pillar strategy that played to the strengths of the company's IP. Unfortunately, that initiative lost steam after Keller, and then Renduchintala left the company in 2020 in the wake of the delays around the company's 7nm process node.

Koduri soldiered on as the head of the Architecture, Software, and Graphics group, eventually receiving a promotion to the position of Executive Vice President in April 2022.

During his tenure, Koduri helmed the creation and launch of Intel's Arc graphics cards and Ponte Vecchio GPUs. He was also responsible for developing Intel's first Bitcoin-mining 'Blockscale' ASICs that are currently shipping. On the one hand, considering it was the first major company in 25 years to enter the space, Intel's entry into the discrete GPU market has been mostly successful. However, Intel's long-awaited Ponte Vecchio arrived late, and the company recently decided to axe its Rialto Bridge successor.

Meanwhile, the Intel Arc graphics cards for the desktop PC also arrived late, putting them in a less favorable position relative to competing AMD and Nvidia GPUs. Intel has steadily dropped pricing while improving drivers and performance after the launch, efforts that will now carry on in Koduri's absence.

Koduri has completed a four-year stretch at Apple, two stints at AMD totaling roughly 13 years, and five and a half years at Intel. He is now off to found a generative AI startup. We'll be sure to have coverage when we learn more details about his newest venture. 

Intel announced today that it would split its AXG graphics group to separately address the gaming and data center markets by placing it under two other business units. Raja Koduri, currently the Executive Vice President of the AXG business unit, will return to his previous role as an Intel Chief Architect:

“Discrete graphics and accelerated computing are critical growth engines for Intel. With our flagship products now in production, we are evolving our structure to accelerate and scale their impact and drive go-to-market strategies with a unified voice to customers. This includes our consumer graphics teams joining our client computing group, and our accelerated computing teams joining our datacenter and AI group. In addition, Raja Koduri will return to the Intel Chief Architect role to focus on our growing efforts across CPU, GPU and AI, and accelerating high priority technical programs.”

We spoke with Intel, and the company assures us that it remains fully committed to its existing roadmap of Arc consumer discrete GPUs, meaning it intends to launch the second-gen Battlemage and third-gen Celestial gaming GPUs as planned. Those GPUs will join the recently launched Alchemist series, which will also continue to be supported.

Intel’s Raja Koduri led AXG but will now return to his previous role as an Intel Chief Architect. Koduri will work on high-performance technical programs with an eye on driving the integration of GPU, CPU, and AI architectures, a key initiative considering products like Falcon Shores and Intel’s Zettascale ambitions.

Koduri assumed his current position as leader of AXG last year, but the new role sounds similar to his original position when he arrived at Intel in 2017 after a five-year stint at AMD (and a short hiatus). As Koduri shared on Twitter yesterday, he is currently recovering from an unplanned back surgery in India and will remain there for a month before he returns to work.

The new alignment places the consumer-focused portion of the Accelerated Computing Systems and Graphics (AXG) business unit under Intel’s Client Compute Group (CCG). Intel’s CCG is responsible for developing consumer computing platforms around the company’s CPU products. Lisa Pearce, most known for her work leading the GPU teams’ software and driver divisions, will lead the AXG unit that slots in under CCG. Pearce will report to Michelle Johnston Holthaus, the current head of CCG.

The teams responsible for data center and supercomputing GPUs, like the Ponte Vecchio and Rialto Bridge products, will move to the Data Center and AI (DCAI) business unit. The GPU SoC and IP design teams will also fall under the DCAI umbrella, but they will continue to support the client graphics team. Jeff McVeigh, currently the VP & GM of the Super Compute Group, will serve as the interim leader of this AXG team as Intel searches for a permanent leader. McVeigh will report to the current head of DCAI, Sandra Rivera.

In Q1 of this year, Intel reorganized its financial reporting into six business units. Despite the hierarchical adjustments, AXG will continue to report its revenue as one of the six Intel business units in the upcoming January earnings call.

Naturally, this realignment of the GPU group will raise concerns that Intel plans to sunset its consumer gaming GPU business. The bar for a new GPU maker is high — Intel is the first new discrete GPU player in 25 years — and it’s no secret that the Arc gaming GPUs arrived to market later than expected, so they face a tough competitive environment that finds them trailing Nvidia and AMD’s products and unable to take a place among the best GPUs. Much of that disparity has been blamed on lackluster launch-day drivers, but that has improved in recent months. The market conditions also aren’t favorable because of a GPU oversupply that comes after several years of crypto-driven shortages.

These factors have all contributed to a recent wave of speculation that claimed Intel would axe the consumer GPU division. Still, the company tells us it remains fully committed to its existing and future lineup of gaming graphics cards. In addition, Pat Gelsinger has communicated a long-term desire to develop GPUs, recently saying, “When I left Intel 12 years ago, it was the only major 'not done' on my list of things that I wanted to finish. Well, I’m back, and we are now going to get it done” during his announcement of the launch of the company’s Arc gaming GPUs.

Intel says its consumer GPU teams are now fully engaged in getting Battlemage finished and released. Considering the delays with Alchemist, we could potentially see Arc B-series (Battlemage) release as early as 2023.

However, Intel's Tom Petersen has avoided giving any firm release details, stating that it "learned its lesson" with the initial Arc rollout. While the Arc A770, A750, and A380 had a rough launch, things have improved, but, at best, they still compete with products that came out two years ago. There’s plenty of speculation that Battlemage could be the make-or-break point for Intel's consumer GPU division, and it's reasonable to think it could be tough for Intel to justify continued investment if it doesn’t reach an inflection point in the near future.

Despite the seeming uncertainty surrounding Intel’s gaming GPU business, there's no doubt that the company’s data center and HPC-geared GPUs will remain a key strategic asset to address the AI market. Data centers are the land of high margins, and supercomputers have been opting for increased numbers of GPUs over CPUs for some time. As such, Intel needs a competitive data center GPU solution to compete with the likes of Nvidia and AMD, and the underlying IP to power future architectures like Falcon Shores.

This year, Intel made a noteworthy entry into the low-to-mid range discrete GPU market with its A750 and A770 cards, but don't expect the company to start challenging the RTX 4090 or Radeon RX 7900, both of which require a lot of wattage, any time soon. According to Intel Graphics Head Raja Koduri, the company is squarely focused on squeezing as much performance as it can out of a 200 to 225W power limit -- often with a single power connector -- and hopefully enough to compete with the best graphics cards. 

Priorities

"My priority at this point is getting that core audience, with one power connector," Intel Graphics Head Raja Koduri said in an interview with Gadgets360, an Indian tech site. "And that can get you up to 200W – 225W. If you nail that, and something a little above and a little below, all that falls into the sweet spot." 

Modern high-end graphics cards consume incredible amounts of power as companies like AMD and Nvidia tend to squeeze every bit of performance out of their GPUs. This naturally increases the prices of those advanced graphics cards to levels not accessible by many gamers. However, Intel, which just released its first mainstream discrete GPUs this year, is apparently focused more on power efficiency and affordability than raw speeds. And Raja believes that loads of consumers just want something that's affordable and doesn't require a huge power supply and a ton of cooling

The company's recently-released Arc A750 and A770 cards, priced at between $289 and $349, fall somewhere between the RTX 3060 and RTX 3060 Ti, both of which cost more, on the GPU benchmark hierarchy.  Intel's cards already fall into the 200 to 225W power range, though for what it's worth, they still have two power connectors where Nvidia is able to have a single connector on some of its cards.

Possibilities

Now, while a plan to build a high-end graphics board that would consume around 200W may sound like an unachievable dream given today's standards for gaming-grade graphics cards (maximum performance at whatever cost), it perhaps should be considered from a GPU architecture point of view. After all, Raja Koduri is a GPU architect rather than an engineer who implements those graphics processors in silicon or another engineer who figures out how to build a graphics cards to make a GPU run at its max. 

Building a discrete GPU architecture — that would provide decent performance in say a 4K resolution in a circa 200W power envelope — would be an achievement by itself. Nvidia and AMD cards that can play smoothly at 4K use a ton of power.  Building a GPU in a set power envelope is another challenge and succeeding would be an undisputed achievement.  

Sweet Spot

If this sweet spot architecture scales both up and down in terms of power, then it is possible to build something considerably more powerful or less power hungry. In the former case, Intel would compete against mighty GPUs from AMD and Nvidia. Whether such an architecture is part of the public Intel Arc roadmap is something that remains to be seen, but at least Raja Koduri expresses such a goal.

Addressing mass market buyers is perhaps Intel's course of action for its Arc discrete GPUs for now as the company is only just entering the standalone GPU market and yet has to gain market share. To that end, its main goals at this point (probably) are to make GPUs that provide good performance for notebooks (where Intel has an indisputable lead on the CPU side of things) at low power as well as desktops aimed at mainstream gamers who do not tend to spend $1000 per graphics card. This is a business goal though.  

Battlemage

In the meantime, Koduri expresses confidence of Intel's Arc roadmap in general and the next generation of the company's standalone GPUs codenamed Battlemage due in 2023 in particular. "The interest level is very, very high," the Intel graphics and accelerated computing boss said. "And [we're working on] landing more partners in India who can ship good volumes here at good price points. So, expect to see a lot more Arc in 2023 and more variations of Arc." 

Intel has been hyping up Xe Graphics for about two years, but the Intel Arc Alchemist GPU will finally bring some needed performance and competition from Team Blue to the discrete GPU space. This is the first 'real' dedicated Intel GPU since the i740 back in 1998 — or technically, a proper discrete GPU after the Intel Xe DG1 paved the way last. The competition among the best graphics cards is fierce, and Intel's current integrated graphics solutions basically don't even rank on our GPU benchmarks hierarchy (UHD Graphics 630 sits at 1.8% of the RTX 3090 based on just 1080p medium performance).

The latest announcement from Intel is that the Arc A770 is coming October 12, starting at $329. That's a lot lower on pricing than what was initially rumored, but then the A770 is also coming out far later than originally intended. With Intel targeting better than RTX 3060 levels of performance, at a potentially lower price and with more VRAM, things are shaping up nicely for Team Blue.

Could Intel, purveyor of low performance integrated GPUs—"the most popular GPUs in the world"—possibly hope to compete? Yes, it can. Plenty of questions remain, but with the official China-first launch of Intel Arc Alchemist laptops and the desktop Intel Arc A380 now behind us, plus plenty of additional details of the Alchemist GPU architecture, we now have a reasonable idea of what to expect. Intel has been gearing up its driver team for the launch, fixing compatibility and performance issues on existing graphics solutions, hopefully getting ready for the US and "rest of the world" launch. Frankly, there's nowhere to go from here but up.

The difficulty Intel faces in cracking the dedicated GPU market can't be underestimated. AMD's Big Navi / RDNA 2 architecture has competed with Nvidia's Ampere architecture since late 2020. While the first Xe GPUs arrived in 2020, in the form of Tiger Lake mobile processors, and Xe DG1 showed up by the middle of 2021, neither one can hope to compete with even GPUs from several generations back. Overall, Xe DG1 performed about the same as Nvidia's GT 1030 GDDR5, a weak-sauce GPU hailing from May 2017. It was also a bit better than half the performance of 2016's GTX 1050 2GB, despite having twice as much memory.

The Arc A380 did better, but it still only managed to match or slightly exceed the performance of the GTX 1650 (GDDR5 variant) and RX 6400. Video encoding hardware was a high point at least. More importantly, the A380 is potentially about a quarter of the performance of the top-end Arc A770, so there's still hope.

Intel has a steep mountain to ascend if it wants to be taken seriously in the dedicated GPU space. Here's the breakdown of the Arc Alchemist architecture, a look at the announced products, some Intel-provided benchmarks, all of which give us a glimpse into how Intel hopes to reach the summit. Truthfully, we're just hoping Intel can make it to base camp, leaving the actual summiting for the future Battlemage, Celestial, and Druid architectures. But we'll leave those for a future discussion. 

Intel's Xe Graphics aspirations hit center stage in early 2018, starting with the hiring of Raja Koduri from AMD, followed by chip architect Jim Keller and graphics marketer Chris Hook, to name just a few. Raja was the driving force behind AMD's Radeon Technologies Group, created in November 2015, along with the Vega and Navi architectures. Clearly, the hope is that he can help lead Intel's GPU division into new frontiers, and Arc Alchemist represents the results of several years worth of labor.

Not that Intel hasn't tried this before. Besides the i740 in 1998, Larrabee and the Xeon Phi had similar goals back in 2009, though the GPU aspect never really panned out. Plus, Intel has steadily improved the performance and features in its integrated graphics solutions over the past couple of decades (albeit at a slow and steady snail's pace). So, third time's the charm, right?

There's much more to building a good GPU than just saying you want to make one, and Intel has a lot to prove. Here's everything we know about the upcoming Intel Arc Alchemist, including specifications, performance expectations, release date, and more.

Potential Intel Arc Alchemist Specifications and Price

We'll get into the details of the Arc Alchemist architecture below, but let's start with the high-level overview. Intel has two different Arc Alchemist GPU dies, covering three different product families, the 700-series, 500-series, and 300-series. The first letter also denotes the family, so A770 are for Alchemist, and the future Battlemage parts will likely be named Arc B770 or similar.

Here are the specifications for the various desktop Arc GPUs that Intel has revealed. All of the figures are now more or less confirmed, except for A580 power.

These are Intel's official core specs on the full large and small Arc Alchemist chips. Based on the wafer and die shots, along with other information, we expect Intel to enter the dedicated GPU market with products spanning the entire budget to high-end range.

Intel has five different mobile SKUs, the A350M, A370M, A550M, A730M, and A770M. Those are understandably power constrained, while for desktops there will be (at least) A770, A750, A580, and A380 models. Intel also has Pro A40 and Pro A50 variants for professional markets (still using the smaller chip), and we can expect additional models for that market as well.

The Arc A300-series targets entry-level performance, the the A500 series goes after the midrange market, and A700 is for the high-end offerings — though we'll have to see where they actually land in our GPU benchmarks hierarchy when they launch. Arc mobile GPUs along with the A380 were available in China first, but the desktop A580, A750, and A770 should be full world-wide launches. Releasing the first parts in China wasn't a good look, especially since one of Intel's previous "China only" products was Cannon Lake, with the Core i3-8121U that basically only just saw the light of day before getting buried deep under ground.

We now have an official launch date for the A770 and presumably A750 as well, though we're not clear if the A580 will also be launching on that date or what it might cost. Intel did reveal that the A770 will start at $329, presumably for the 8GB variant — unless Intel is feeling very generous and the A770 Limited Edition made by Intel will also start at $329? (Probably not.)

Also note that the maximum theoretical compute performance in teraflops (TFLOPS) uses Intel's "Game Clock," which is supposedly an average of typical gaming clocks. AMD and Nvidia sort of have that as well but call it a boost clock, and in practice we usually see gaming clocks higher than the official values. For Intel, we're not sure what will happen. The Gunnir Arc A380 has a 2450 MHz boost clock for example, and in gaming it was pretty much locked in at that speed, though it also used more power than the 75W Intel gives for the reference design. It sounds like "typical" gaming scenarios will probably run at higher clocks, which would be good.

Real-world performance will also depend on drivers, which have been a sticking point for Intel in the past. Gaming performance will play a big role in determining how much Intel can charge for the various graphics card models.

As shown in our GPU price index, the prices of competing AMD and Nvidia GPUs have plummeted this year. Intel would have been in great shape if it had managed to launch Arc at the start of the year with reasonable prices, which was the original plan (actually, late 2021 was at one point in the cards). Many gamers might have given Intel GPUs a shot if they were priced at half the cost of the competition, even if they were slower.

That takes care of the high-level overview. Now let's dig into the finer points and discuss where these estimates come from.

Arc Alchemist: Performance According to Intel

Intel has provided us with reviewer's guides for both its mobile Arc GPUs and the desktop Arc A380. As with any manufacturer provided benchmarks, you should expect the games and settings used were selected to show Arc in the best light possible. Intel tested 17 games for laptops and desktops, but the game selection isn't even identical, which is a bit weird. It then compared performance with two mobile GeForce solutions, and the GTX 1650 and RX 6400 for desktops. There's a lot of missing data, since the mobile chips represent the two fastest Arc solutions, but let's get to the actual numbers first.

We'll start with the mobile benchmarks, since Intel used its two high-end models for these. Based on the numbers, Intel suggests its A770M can outperform the RTX 3060 mobile, and the A730M can outperform the RTX 3050 Ti mobile. The overall scores put the A770M 12% ahead of the RTX 3060, and the A730M was 13% ahead of the RTX 3050 Ti. However, looking at the individual game results, the A770M was anywhere from 15% slower to 30% faster, and the A730M was 21% slower to 48% faster.

That's a big spread in performance, and tweaks to some settings could have a significant impact on the fps results. Still, overall the list of games and settings used here looks pretty decent. However, Intel used laptops equipped with the older Core i7-11800H CPU on the Nvidia cards, and then used the latest and greatest Core i9-12900HK for the A770M and the Core i7-12700H for the A730M. There's no question that the Alder Lake CPUs are faster than the previous generation Tiger Lake variants, though without doing our own testing we can't say for certain how much CPU bottlenecks come into play.

There's also the question of how much power the various chips used, as the Nvidia GPUs have a wide power range. The RTX 3050 Ti can ran at anywhere from 35W to 80W (Intel used a 60W model), and the RTX 3060 mobile has a range from 60W to 115W (Intel used an 85W model). Intel's Arc GPUs also have a power range, from 80W to 120W on the A730M and from 120W to 150W on the A770M. While Intel didn't specifically state the power level of its GPUs, it would have to be higher in both cases.

Switching over to the desktop side of things, Intel provided the above A380 benchmarks. Note that this time the target is much lower, with the GTX 1650 and RX 6400 budget GPUs going up against the A380. Intel still has higher-end cards coming, but here's how it looks in the budget desktop market.

Even with the usual caveats about manufacturer provided benchmarks, things aren't looking too good for the A380. The Radeon RX 6400 delivered 9% better performance than the Arc A380, with a range of -9% to +31%. The GTX 1650 did even better, with a 19% overall margin of victory and a range of just -3% up to +37%.

And look at the list of games: Age of Empires 4, Apex Legends, DOTA 2, GTAV, Naraka Bladepoint, NiZhan, PUBG, Warframe, The Witcher 3, and Wolfenstein Youngblood? Some of those are more than five years old, several are known to be pretty light in terms of requirements, and in general that's not a list of demanding titles. We get the idea of going after esports competitors, sort of, but wouldn't a serious esports gamer already have something more potent than a GTX 1650?

Keep in mind that Intel potentially has a part that will have four times as much raw compute, which we expect to see in an Arc A770 with a fully enabled ACM-G10 chip. If drivers and performance don't hold it back, such a card could still theoretically match the RTX 3070 and RX 6700 XT, but drivers are very much a concern right now.

On that note, our own Arc A380 review has a slightly different result. We tested eight standard games at 1080p medium, 1080p ultra, and 1440p ultra. Here's what our testing looks like, which came a month or two after Intel's initial tests and used newer drivers.

Where Intel's earlier testing showed the A380 falling behind the 1650 and 6400 overall, our own testing gives it a slight lead. Game selection will of course play a role, and the A380 trails the faster GTX 1650 Super and RX 6500 XT by a decent amount despite having more memory and theoretically higher compute performance. Perhaps there's still room for further driver optimizations to close the gap.

Arc Alchemist: Beyond the Integrated Graphics Barrier 

Over the past decade, we've seen several instances where Intel's integrated GPUs have basically doubled in theoretical performance. Despite the improvements, Intel frankly admits that integrated graphics solutions are constrained by many factors: Memory bandwidth and capacity, chip size, and total power requirements all play a role.

While CPUs that consume up to 250W of power exist — Intel's Core i9-12900K and Core i9-11900K both fall into this category — competing CPUs that top out at around 145W are far more common (e.g., AMD's Ryzen 5900X or the Core i7-12700K). Plus, integrated graphics have to share all of those resources with the CPU, which means it's typically limited to about half of the total power budget. In contrast, dedicated graphics solutions have far fewer constraints.

Consider the first generation Xe-LP Graphics found in Tiger Lake (TGL). Most of the chips have a 15W TDP, and even the later-gen 8-core TGL-H chips only use up to 45W (65W configurable TDP). Except TGL-H also cut the GPU budget down to 32 EUs (Execution Units), where the lower power TGL chips had 96 EUs. The new Alder Lake desktop chips also use 32 EUs, though the mobile H-series parts get 96 EUs and a higher power limit.

The top AMD and Nvidia dedicated graphics cards like the Radeon RX 6900 XT and GeForce RTX 3080 Ti have a power budget of 300W to 350W for the reference design, with custom cards pulling as much as 400W. Intel doesn't plan to go that high for its reference Arc A770/A750 designs, which target just 225W, but we'll have to see what happens with the third-party AIB cards. Gunnir's A380 increased the power limit by 23% compared to the reference specs, so a similar increase on the A700 cards could mean a 275W power limit.

Intel Arc Alchemist Architecture 

Intel may be a newcomer to the dedicated graphics card market, but it's by no means new to making GPUs. Current Alder Lake (as well as the previous generation Rocket Lake and Tiger Lake) CPUs use the Xe Graphics architecture, the 12th generation of graphics updates from Intel.

The first generation of Intel graphics was found in the i740 and 810/815 chipsets for socket 370, back in 1998-2000. Arc Alchemist, in a sense, is second-gen Xe Graphics (i.e., Gen13 overall), and it's common for each generation of GPUs to build on the previous architecture, adding various improvements and enhancements. The Arc Alchemist architecture changes are apparently large enough that Intel has ditched the Execution Unit naming of previous architectures and the main building block is now called the Xe-core.

To start, Arc Alchemist will support the full DirectX 12 Ultimate feature set. That means the addition of several key technologies. The headline item is ray tracing support, though that might not be the most important in practice. Variable rate shading, mesh shaders, and sampler feedback are also required — all of which are also supported by Nvidia's RTX 20-series Turing architecture from 2018, if you're wondering. Sampler feedback helps to optimize the way shaders work on data and can improve performance without reducing image quality.

The Xe-core contains 16 Vector Engines (formerly or sometimes still called Execution Units), each of which operates on a 256-bit SIMD chunk (single instruction multiple data). The Vector Engine can process eight FP32 instructions simultaneously, each of which is traditionally called a "GPU core" in AMD and Nvidia architectures, though that's a misnomer. Other data types are supported by the Vector Engine, including FP16 and DP4a, but it's joined by a second new pipeline, the XMX Engine (Xe Matrix eXtensions).

Each XMX pipeline operates on a 1024-bit chunk of data, which can contain 64 individual pieces of FP16 data or 128 pieces of INT8 data. The Matrix Engines are effectively Intel's equivalent of Nvidia's Tensor cores, and they're being put to similar use. They offer a huge amount of potential FP16 and INT8 computational performance, and should prove very capable in AI and machine learning workloads. More on this below.

Xe-core represents just one of the building blocks used for Intel's Arc GPUs. Like previous designs, the next level up from the Xe-core is called a render slice (analogous to an Nvidia GPC, sort of) that contains four Xe-core blocks. In total, a render slice contains 64 Vector and Matrix Engines, plus additional hardware. That additional hardware includes four ray tracing units (one per Xe-core), geometry and rasterization pipelines, samplers (TMUs, aka Texture Mapping Units), and the pixel backend (ROPs).

The above block diagrams may or may not be fully accurate down to the individual block level. For example, looking at the diagrams, it would appear each render slice contains 32 TMUs and 16 ROPs. That would make sense, but Intel has not yet confirmed those numbers (even though that's what we used in the above specs table).

The ray tracing units (RTUs) are another interesting item. Intel detailed their capabilities and says each RTU can do up to 12 ray/box BVH intersections per cycle, along with a single ray/triangle intersection. There's dedicated BVH hardware as well (unlike on AMD's RDNA 2 GPUs), so a single Intel RTU should pack substantially more ray tracing power than a single RDNA 2 ray accelerator or maybe even an Nvidia RT core. Except, the maximum number of RTUs is only 32, where AMD has up to 80 ray accelerators and Nvidia has 84 RT cores. But Intel isn't really looking to compete with the top cards this round.

In our testing of the Arc A380, we found ray tracing performance was relatively weak, which is understandable considering its eight RTUs. However, thanks to the architecture and likely the 6GB of VRAM, ray tracing performance did tend to match or even exceed AMD's RX 6500 XT. Again, the high-end cards could end up being quite decent, and Intel claims the A750 can more than match the RTX 3060 in DXR performance while the A770 should be closer to the RTX 3060 Ti or even RTX 3070.

Finally, Intel uses multiple render slices to create the entire GPU, with the L2 cache and the memory fabric tying everything together. Also not shown are the video processing blocks and output hardware, and those take up additional space on the GPU. The maximum Xe HPG configuration for the initial Arc Alchemist launch will have up to eight render slices. Ignoring the change in naming from EU to Vector Engine, that still gives the same maximum configuration of 512 EU/Vector Engines that's been rumored for the past 18 months.

Intel includes 2MB of L2 cache per render slice, so 4MB on the smaller ACM-G11 and 16MB total on the ACM-G10. There will be multiple Arc configurations, though. So far, Intel has shown one with two render slices and a larger chip used in the above block diagram that comes with eight render slices. Given how much benefit AMD saw from its Infinity Cache, we have to wonder how much the 16MB cache will help with Arc performance. Even the smaller 4MB L2 cache is larger than what Nvidia uses on its GPUs, where the GTX 1650 only has 1MB of L2 and the RTX 3050 has 2MB.

While it doesn't sound like Intel has specifically improved throughput on the Vector Engines compared to the EUs in Gen11/Gen12 solutions, that doesn't mean performance hasn't improved. DX12 Ultimate includes some new features that can also help performance, but the biggest change comes via boosted clock speeds. We've seen Intel's Arc A380 clock at up to 2.45 GHz (boost clock), even though the official Game Clock is only 2.0 GHz. A770 has a Game Clock of 2.1 GHz, which yields a significant amount of raw compute.

The maximum configuration of Arc Alchemist will have up to eight render slices, each with four Xe-cores, 16 Vector Engines per Xe-core, and each Vector Engine can do eight FP32 operations per clock. Double that for FMA operations (Fused Multiply Add, a common matrix operation used in graphics workloads), then multiply by a 2.1 GHz clock speed, and we get the theoretical performance in GFLOPS:

8 (RS) * 4 (Xe-core) *16 (VE) * 8 (FP32) * 2 (FMA) * 2.1 (GHz) = 17,203 GFLOPS

Obviously, gigaflops (or teraflops) on its own doesn't tell us everything, but nearly 17.2 TFLOPS for the top configurations is nothing to scoff at. Nvidia's Ampere GPUs still theoretically have a lot more compute. The RTX 3080, as an example, has a maximum of 29.8 TFLOPS, but some of that gets shared with INT32 calculations. AMD's RX 6800 XT by comparison 'only' has 20.7 TFLOPS, but in many games, it delivers similar performance to the RTX 3080. In other words, raw theoretical compute absolutely doesn't tell the whole story. Arc Alchemist could punch above — or below! — its theoretical weight class.

Still, let's give Intel the benefit of the doubt for a moment. Arc Alchemist comes in below the theoretical level of the current top AMD and Nvidia GPUs, but if we skip the most expensive 'halo' cards, it looks competitive with the RX 6700 XT and RTX 3060 Ti. On paper, Intel Arc A770 could even land in the vicinity of the RTX 3070 and RX 6800 — assuming drivers and other factors don't hold it back.

XMX: Matrix Engines and Deep Learning for XeSS 

We briefly mentioned the XMX blocks above. They're potentially just as useful as Nvidia's Tensor cores, which are used not just for DLSS, but also for other AI applications, including Nvidia Broadcast.

Theoretical compute from the XMX blocks is eight times higher than the GPU's Vector Engines, except that we'd be looking at FP16 compute rather than FP32. That's similar to what we've seen from Nvidia, although Nvidia also has a "sparsity" feature where zero multiplications (which can happen a lot) get skipped — since the answer's always zero.

Intel also announced a new upscaling and image enhancement algorithm that it's calling XeSS: Xe Superscaling. Intel didn't go deep into the details, but it's worth mentioning that Intel hired Anton Kaplanyan. He worked at Nvidia and played an important role in creating DLSS before heading over to Facebook to work on VR. It doesn't take much reading between the lines to conclude that he's likely doing a lot of the groundwork for XeSS now, and there are many similarities between DLSS and XeSS.

XeSS uses the current rendered frame, motion vectors, and data from previous frames and feeds all of that into a trained neural network that handles the upscaling and enhancement to produce a final image. That sounds basically the same as DLSS 2.0, though the details matter here, and we assume the neural network will end up with different results.

Intel did provide a demo using Unreal Engine showing XeSS in action (see below), and it looked good when comparing 1080p upscaled via XeSS to 4K against the native 4K rendering. Still, that was in one demo, and we'll have to see XeSS in action in actual shipping games before rendering any verdict.

XeSS also has to compete against AMD's new and "universal" upscaling solution, FSR 2.0. While we'd still give DLSS the edge in terms of pure image quality, FSR 2.0 comes very close and can work on RX 6000-series GPUs, as well as older RX 500-series, RX Vega, GTX going all the way back to at least the 700-series, and even Intel integrated graphics. It will also work on Arc GPUs.

The good news with DLSS, FSR 2.0, and now XeSS is that they should all take the same basic inputs: the current rendered frame, motion vectors, the depth buffer, and data from previous frames. Any game that supports any of these three algorithms should be able to support the other two with relatively minimum effort on the part of the game's developers — though politics and GPU vendor support will likely factor in as well.

More important than how it works will be how many game developers choose to use XeSS. They already have access to both DLSS and AMD FSR, which target the same problem of boosting performance and image quality. Adding a third option, from the newcomer to the dedicated GPU market no less, seems like a stretch for developers. However, Intel does offer a potential advantage over DLSS.

XeSS is designed to work in two modes. The highest performance mode utilizes the XMX hardware to do the upscaling and enhancement, but of course, that would only work on Intel's Arc GPUs. That's the same problem as DLSS, except with zero existing installation base, which would be a showstopper in terms of developer support. But Intel has a solution: XeSS will also work, in a lower performance mode, using DP4a instructions (four INT8 instructions packed into a single 32-bit register).

DP4a is widely supported by other GPUs, including Intel's previous generation Xe LP and multiple generations of AMD and Nvidia GPUs (Nvidia Pascal and later, or AMD Vega 20 and later), which means XeSS in DP4a mode will run on virtually any modern GPU. Support might not be as universal as AMD's FSR, which runs in shaders and basically works on any DirectX 11 or later capable GPU as far as we're aware, but quality should be better than FSR 1.0 and might even take on FSR 2.0 as well. It would also be very interesting if Intel supported Nvidia's Tensor cores, through DirectML or a similar library, but that wasn't discussed.

The big question will still be developer uptake. We'd love to see similar quality to DLSS 2.x, with support covering a broad range of graphics cards from all competitors. That's definitely something Nvidia is still missing with DLSS, as it requires an RTX card. But RTX cards already make up a huge chunk of the high-end gaming PC market, probably around 90% or more (depending on how you quantify high-end). So Intel basically has to start from scratch with XeSS, and that makes for a long uphill climb.

Arc Alchemist and GDDR6

Intel has confirmed Arc Alchemist GPUs will use GDDR6 memory. Most of the mobile variants are using 14Gbps speeds, while the A770M runs at 16Gbps and the A380 desktop part uses 15.5Gbps GDDR6. The future desktop models will use 16Gbps memory on the A750 and A580, while the A770 will use 17.5Gbps GDDR6.

There will be multiple Xe HPG / Arc Alchemist solutions, with varying capabilities. The larger chip, which we've focused on so far, has eight 32-bit GDDR6 channels, giving it a 256-bit interface. Intel has confirmed that the A770 can be configured with either 8GB or 16GB of memory. Interestingly, the mobile A730M trims that down to a 192-bit interface and the A550M uses a 128-bit interface. However, the desktop models will apparently all stick with the full 256-bit interface, likely for performance reasons.

The smaller Arc GPU only has a 96-bit maximum interface width, though the A370M and A350M cut that to a 64-bit width, while the A380 uses the full 96-bit option and comes with 6GB of GDDR6.

The A380 didn't look particularly impressive in our testing, but the larger chips combined with substantially more memory bandwidth look far more competitive — assuming Intel also competes on price and availability. If the A770 can indeed match or exceed the performance of Nvidia's RTX 3060, and AMD's RX 6650 XT as well, the starting price of $329 will make it worth considering.

Arc Alchemist Die Shots and Analysis 

Intel will partner with TSMC and use the N6 process (an optimized variant of N7) for Arc Alchemist. That means it's not technically competing for the same wafers as AMD uses for its Zen 2, Zen 3, RDNA, and RDNA 2 GPUs. At the same time, AMD and Nvidia could also use N6 as well — it's design is compatible with N7, so Intel's use of TSMC certainly doesn't help AMD or Nvidia production capacities.

TSMC likely has a lot of tools that overlap between N6 and N7 as well, meaning it could run batches of N6, then batches and N7, switching back and forth. That means there's potential for this to cut into TSMC's ability to provide wafers to other partners. And speaking of wafers...

Raja showed a wafer of Arc Alchemist chips at Intel Architecture Day. By snagging a snapshot of the video and zooming in on the wafer, the various chips on the wafer are reasonably clear. We've drawn lines to show how large the chips are, and based on our calculations, it looks like the larger Arc die will be around 24x16.5mm (~396mm^2), give or take 5–10% in each dimension. Other reports state that the die size is actually 406mm^2, so we were pretty close.

That's not a massive GPU — Nvidia's GA102, for example, measures 628mm^2 and AMD's Navi 21 measures 520mm^2 — but it's also not small at all. AMD's Navi 22 measures 335mm^2, and Nvidia's GA104 is 393mm^2, so ACM-G10 is larger than AMD's chip and similar in size to the GA104 — but made on a smaller manufacturing process. Still, putting it bluntly: Size matters.

This may be Intel's first real dedicated GPU since the i740 back in the late 90s, but it has made many integrated solutions over the years, and it has spent the past several years building a bigger dedicated GPU team. Die size alone doesn't determine performance, but it gives a good indication of how much stuff can be crammed into a design. A chip that's 406mm^2 in size suggests Intel intends to be competitive with at least the RTX 3070 and RX 6700 XT, which is perhaps higher than some were expecting.

Besides the wafer shot, Intel also provided these two die shots for Xe HPG. The larger die has eight clusters in the center area that would correlate to the eight render slices. The memory interfaces are along the bottom edge and the bottom half of the left and right edges, and there are four 64-bit interfaces, for 256-bit total. Then there's a bunch of other stuff that's a bit more nebulous, for video encoding and decoding, display outputs, etc.

The smaller die has two render slices, giving it just 128 Vector Engines. It also only has a 96-bit memory interface (the blocks in the lower-right edges of the chip), which could put it at a disadvantage relative to other cards. Then there's the other 'miscellaneous' bits and pieces, for things like the QuickSync Video Engine. Obviously, performance will be substantially lower than the bigger chip.

While the smaller chip appears to be slower than all the current RTX 30-series GPUs, it does put Intel in an interesting position. The A380 checks in at a theoretical 4.1 TFLOPS, which means it ought to be able to compete with a GTX 1650 Super, with additional features like AV1 encoding/decoding support that no other GPU currently has. 6GB of VRAM also gives Intel a potential advantage, and on paper the A380 ought to land closer to the RX 6500 XT than the RX 6400.

That's not currently the case, according to Intel's own benchmarks as well as our own testing (see above), but perhaps further tuning of the drivers could give a solid boost to performance. We certainly hope so, but let's not count those chickens before they hatch.

 Will Intel Arc Be Good at Mining Cryptocurrency? 

This is hopefully a non-issue at this stage, as the potential profits from cryptocurrency mining have dropped off substantially in recent months. Still, some people might want to know if Intel's Arc GPUs can be used for mining. Publicly, Intel has said precisely nothing about mining potential and Xe Graphics. However, given the data center roots for Xe HP/HPC (machine learning, High-Performance Compute, etc.), Intel has certainly at least looked into the possibilities mining presents, and its Bonanza Mining chips are further proof Intel isn't afraid of engaging with crypto miners. There's also the above image (for the entire Intel Architecture Day presentation), with a physical Bitcoin and the text "Crypto Currencies."

Generally speaking, Xe might work fine for mining, but the most popular algorithms for GPU mining (Ethash mostly, but also Octopus and Kawpow) have performance that's predicated almost entirely on how much memory bandwidth a GPU has. For example, Intel's fastest Arc GPUs will use a 256-bit interface. That would yield similar bandwidth to AMD's RX 6800/6800 XT/6900 XT as well as Nvidia's RTX 3060 Ti/3070, which would, in turn, lead to performance of around 60-ish MH/s for Ethereum mining.

There's also at least one piece of mining software that now has support for the Arc A380. While in theory the memory bandwidth would suggest an Ethereum hashrate of around 20-23 MH/s, current tests only showed around 10 MH/s. Further tuning of the software could help, but by the time the larger and faster Arc models arrive, Ethereum should have undergone 'The Merge' and transitioned to a full proof of stake algorithm.

If Intel had launched Arc in late 2021 or even early 2022, mining performance might have been a factor. Now, the current crypto-climate suggests that, whatever the mining performance, it won't really matter.

Arc Alchemist Launch Date and Future GPU Plans

The core specs for Arc Alchemist are shaping up nicely, and the use of TSMC N6 and a 406mm^2 die with a 256-bit memory interface all point to a card that should be competitive with the current mainstream/high-end GPUs from AMD and Nvidia, but well behind the top performance models.

As the newcomer, Intel needs the first Arc Alchemist GPUs to come out swinging. As we discussed in our Arc A380 review, however, there's much more to building a good graphics card than hardware. That's probably why Arc A380 launched in China first, to get the drivers and software ready for the faster offerings as well as the rest of the world.

Alchemist represents the first stage of Intel's dedicated GPU plans, and there's more to come. Along with the Alchemist codename, Intel revealed codenames for the next three generations of dedicated GPUs: Battlemage, Celestial, and Druid. Now we know our ABCs, next time won't you build a GPU with me? Those might not be the most awe-inspiring codenames, but we appreciate the logic of going in alphabetical order.

Tentatively, with Alchemist using TSMC N6, we might see a relatively fast turnaround for Battlemage. It could use TSMC's N5 process and ship in 2023 — which would perhaps be wise, considering we expect to see Nvidia's Lovelace RTX 40-series GPUs and AMD's RX 7000-series RDNA 3 GPUs in the next few months. Shrink the process, add more cores, tweak a few things to improve throughput, and Battlemage could put Intel on even footing with AMD and Nvidia. Or it could arrive woefully late (again) and deliver less performance.

Intel needs to iterate on the future architectures and get them out sooner than later if it hopes to put some pressure on AMD and Nvidia. Arc Alchemist already slipped from 2021 to a supposed hard launch date of Q1 2022, which then changed to Q2 for China and Q3 for the US and other markets. Intel really needs to stop the slippage and get cards out, with fully working drivers, sooner rather than later if it doesn't want a repeat of its old i740 story.

Final Thoughts on Intel Arc Alchemist 

The bottom line is that Intel has its work cut out for it. It may be the 800-pound gorilla of the CPU world, but it has stumbled and faltered even there over the past several years. AMD's Ryzen gained ground, closed the gap, and took the lead up until Intel finally delivered Alder Lake and desktop 10nm ("Intel 7" now) CPUs. Intel's manufacturing woes are apparently bad enough that it turned to TSMC to make its dedicated GPU dreams come true.

As the graphics underdog, Intel needs to come out with aggressive performance and pricing, and then iterate and improve at a rapid pace. And please don't talk about how Intel sells more GPUs than AMD and Nvidia. Technically, that's true, but only if you count incredibly slow integrated graphics solutions that are at best sufficient for light gaming and office work. Then again, a huge chunk of PCs and laptops are only used for office work, which is why Intel has repeatedly stuck with weak GPU performance.

We now have hard details on all the Arc GPUs, and we've tested the desktop A380. We even have Intel's own performance data, which was less than inspiring. Had Arc launched in Q1 as planned, it could have carved out a niche. The further it slips into 2022, the worse things look.

Again, the critical elements are going to be performance, price, and availability. The latter is already a major problem, because the ideal launch window was last year. Intel's Xe DG1 was also pretty much a complete bust, even as a vehicle to pave the way for Arc, because driver problems appear to persist. Arc Alchemist sets its sights far higher than the DG1, but every month that passes those targets become less and less compelling.

We should find out how the rest of Intel's discrete graphics cards stack up to the competition in October. Can Intel capture some of the mainstream market from AMD and Nvidia? Time will tell, but we're still hopeful Intel can turn the current GPU duopoly into a triopoly in the coming years — if not with Alchemist, then perhaps with Battlemage.

Intel CEO Pat Gelsinger is shutting down rumors that Intel is closing its GPU development. In a tweet, Gelsinger wrote that he has received his own personal A770 from Intel graphics head Raja Koduri and that the company is "now getting [the] first batch of A770 cards ready for retail[.]"

(Click "See more" below to expand the tweet.)

Once the A770 hits the market, it will mark an important step for Intel. The company has shipped mobile Arc GPUs in laptops, though they're only in a few models. The Arc 380 shipped first in China, and it was plagued with driver issues and faced poor reviews.

This led to rumors that Intel would drop GPUs on the back of news that Intel may exit more businesses in 2023. Last week, Koduri shrugged off the scuttlebut, and now Gelsinger is promising the A770 will ship.

What's not clear is where the A770 will ship. The A380 was only in China, and we haven't heard whether or not the A770, the first card Intel will ship with gamers in mind, will follow suit, or whether Intel will bring its Alchemist GPUs to the United States, Europe, and other international markets. That should be the plan, but is it still the plan?

Intel also doesn't have the best timing here. When Intel announced it was getting serious about GPUs, we were in the middle of a massive component shortage that made a third competitor in the space seem like a necessity. Getting one of the best graphics cards meant constantly refreshing online stores or waiting outside of brick and mortar retailers to avoid paying scalpers.

This tweet comes as GPU prices from Nvidia and AMD are normalizing, often dropping below the suggested retail price as mining operations that focused on Ethereum are unloading their cards following the Merge. Furthermore, Nvidia is expected to announce at least some of the RTX 40-series graphics cards tomorrow during the fall GTC 2022 keynote.

Still, more competition in the space could be good. Intel has previously suggested the Arc A770 delivers stronger ray tracing performance than a GeForce RTX 3060 at 1080p on ultra settings. Combined with Intel's XeSS upscaling, it seems Intel won't be competing at the top-end, but may be able to balance between price and performance in the middle of the pack.

Robert Hallock, AMD's director of technical marketing, is departing the company after 12 years, he announced on LinkedIn.

Hallock was a public-facing figure at the company, working with the AMD fan community on Reddit, Discord, YouTube and other platforms while also briefing the press.

"Over the years, I've had the honor and privilege of publicly teaching others about some truly stellar innovation: the Zen core family, 3D V-Cache, chiplet packaging, HBM memory, FreeSync, low-overhead graphics APIs, and much more," Hallock wrote in his post. "After working in both graphics and processors for roughly 6 years each, I've learned so much."

Hallock hasn't detailed where he'll be going next. On LinkedIn, he wrote that he would be traveling while he thinks about his next move. Hallock is one of several high-profile employees at AMD to leave in recent years.

In 2017, then Radeon chief Raja Koduri left AMD and now heads up the graphics group at Intel, including Arc. In 2018, Chris Hook, then senior director of global product marketing, left after 17 years from a career that started at ATI. That's the same year that Jim Anderson, the general manager and senior vice president of the computing and graphics group, left. (Anderson now serves as president and CEO of Lattice Semiconductor.) In 2019, another public-facing communications employee announced his departure with a tweet.

It's unclear who will take Hallock's place at AMD. AMD didn't respond to a request for comment before publication, but we'll update if we hear back. He's leaving just before the launch of AMD's Ryzen 7000 desktop processors powered by the 5 nm Zen 4 architecture. Those chips will launch on September 27, so if AMD wants a public face to explain what PC builders will get out of those chips, it will have to find someone to fill his shoes fast.

A popular TechTuber released an explosive-if-true vlog over the weekend, claiming simply that “Intel Arc is over,” with a thumbnail showing an Arc graphics card sinking like the Titanic. Arc so far hasn't cracked our list of the best graphics cards, but we're only dealing with the lowest tier offering. Today, Raja Koduri, EVP and GM of the Accelerated Computing Systems and Graphics (AXG) Group at Intel Corporation, responded to the idea that Intel would fold its Arc graphics card development activities with a shrug.

The video in question comes from Moore’s Law is Dead (MLID), titled “Intel’s Xe Odyssey is Over: Discrete Arc is Effectively Cancelled.” There are 'sources' for the speculation, and the difficulties Intel has faced with launching the Arc Alchemist graphics cards are well-known, but... let's just say MLID doesn't have the best track record. Let's not forget his breakout video claiming RX 5700 XT would launch at $249 while delivering RTX 2080 performance either, a video that has long since been delisted.

The video contains a quartet of what are allegedly direct quotes from MLID sources, but it only needs a cursory glance over the lines to see that there is a degree of hedging going on. Words and phrases like “effectively” in the video title, ”isn’t a lot of optimism,” and “from what I am seeing.” However, source three and four look more definitive.

MLID ends his video by citing a report by Tom’s Hardware, where Intel CEO Pat Gelsinger says the company will likely exit more businesses while it attempts to focus efforts on core competencies. Intel recently began to wind down Optane memory, for example, but it has areas much further removed from core business than discrete graphics. Moreover, no hint has been given to the public or investors that Arc graphics cards might be on the chopping block.

Raja and the lost Arc?

Earlier today, Koduri was promoting the upcoming release of the Arc A770 graphics card with a photo from Intel’s Toronto validation labs. An enterprising Tweeter asked about the hot gossip regarding the demise of Arc and garnered quite a full answer.

Raja says he's unaware of how and why these rumors start circulating. He characterized the chitter-chatter as unhelpful for the PC graphics community, though he admitted that first gen Arc had put up more obstacles than expected “but we persisted.”

Koduri didn’t issue a categorical denial about discrete Arc graphics card developments winding down, but very possibly didn’t want to engage with any rumor spreaders with a direct rebuff. With all the hedging in the MLID Vlog, despite the arresting headline, we are tempted to classify the demise of Arc rumors as a tempest in a teapot for the time being.

All indications are that Intel will very shortly announce retail availability of its Arc A770, A750, and A580 desktop graphics cards, joining the Arc A380 that we already reviewed (using a sample acquired from China). Driver updates continue to come at a fast pace, and several issues that we encountered during testing have since been addressed (like our Acer XB280HK 4K display only running at 640x480 in Windows).

Pricing and performance will have a lot to do with how well Arc GPUs might be received. The ASRock Arc A380 Challenger remains backordered on Newegg, perhaps because of curious tech people wanting one for review, and no doubt helped by its aggressive pricing. We can't rule out limited supply either, but if the higher performance Arc GPUs rate significantly higher on our GPU benchmarks hierarchy and come with similarly aggressive pricing coupled with improved drivers, it's far too early to claim this ship has sailed.

Raja Koduri, the head of Intel's Accelerated Computing Systems and Graphics, has been promoted to the position of Executive Vice President, according to an internal company memo seen by The Register. Penned by Intel CEO Pat Gelsinger on Tuesday, the memo acclaimed Koduri for his numerous contributions to the company over the past four years.

During the last four years, the division headed by Koduri has pushed Intel's GPU capabilities well past those of the company's integrated graphics. He was also exceptionally positioned to do so: Koduri moved to Intel directly from his role as head of arch-rival AMD's own Radeon Technologies Group, which has developed these types of accelerators for decades.

This promotion follows Raja Koduri's work in essentially rebuilding Intel's graphics division to position it for the high-stakes, multi-billion-dollar market of high performance GPUs in the last four years. That effort has, for now, culminated with the launch of Intel's Arc A350M and A370M discrete GPUs, mobile-oriented graphics cards that are the slowest of Intel's complete Arc Alchemist lineup.

While Intel's Arc performance so far hasn't been as good as the company initially hoped, its chances of ever doing so were miniscule from the outset. There's a reason only AMD and NVIDIA provide GPU accelerators for HPC. GPUs are some of the biggest, most complex pieces of silicon that ever come out of the world's leading foundries. AMD's only other competitor in this space, Nvidia, has a market capitalization that's twice as high as that of even giant Intel. The stakes are immense.

In the internal memo, Pat Gelsinger wrote that the world could now count on a third player in the high-performance GPU game, a critical segment for Intel's growth. The CEO lauded the execution on Intel's multi-generation roadmap for its Xe high-performance GPUs, spinning it as a pivotal technology for the enablement of the so-called Metaverse and Zetta-scale supercomputing.

Intel knows (or at least estimates) the ultimate performance if its upcoming graphics products better than anyone. As such, Koduri's promotion bodes well for the future GPU market. And that market looks much better divided by three players, at least for us consumers. Arc Alchemist may not be as potent as the competing solutions from AMD and Nvidia, especially once Nvidia's Ada and AMD's RDNA 3 architectures launch later this year, but it will hopefully serve as the springboard for significantly better architectures with the future Battlemage, Celestial, and Druid architectures.

According to a new job posting, Intel is setting up a GPU development center in the UK. The company is looking for experienced hardware design engineers to develop low-power GPU architectures for portable computing devices.  

"We are building a brand-new team in the UK to focus solely on class-leading low power GPU architectures and designs to enable the next generation of portable computing," reads the job description posted by Intel's Xe Architecture and IP Engineering (XAE) Low Power Group. "This requires proven skills in a range of engineering disciplines from architecture, hardware design, software driver design all with low power as the key focus."

The new GPU R&D center will be located in Swindon, UK, which is roughly 125 miles away from Cambridge, the country's largest technology hub, and around 90 miles away from London. 

At present, there are two major GPU developers in the UK: Arm's Mali development team and Imagination Technologies' PowerVR development team. Both specialize in low-power GPU architectures and have extensive experience designing energy-efficient GPU blocks used by Apple, MediaTek, NXP, Samsung, and Renesas, to name a few. 

With this in mind, there are enough engineers to poach in the UK if you want to develop a low-power GPU architecture. Meanwhile, many of Arm's Mali developers still reside in Trondheim, Norway, which is why codenames of Mali architectures originate from Norwegian mythology. 

At present, Intel uses Xe-LP architecture for notebook processors and should continue doing so for a while. But it looks like the company feels that it will need a brand-new low-power GPU architecture for its processors due in five to six years from now. 

It is noteworthy that Raja Koduri, who is responsible for all GPU activity at Intel, has extensive experience with ImgTec's PowerVR architecture from his days at Apple. Furthermore, the word 'portable' may indicate that Intel is looking beyond notebooks with its next-generation low-power GPU architecture. 

Intel has been meticulously expanding its GPU development team since it hired Koduri in November 2017. Last year the company hired Vineet Goel, a veteran GPU architect from AMD, after employing multiple high-profile GPU engineers, architects, and technologies from Team Red. 

Intel's Raja Koduri penned a blog post that officially announces the company's plans to enter the cryptomining/blockchain market with a roadmap of specialized energy-efficient accelerators. Intel will begin delivering the new chips, comprised of the Bonanza Mine ASICs that we recently unearthed, this year to several large customers as it enters the Bitcoin mining market that it expects to grow by $2.8 billion from 2021-2025. Intel's first customers include BLOCK (formerly known as Square and helmed by CEO Jack Dorsey of Twitter fame), Argo Blockchain, and GRIID Infrastructure. We'll provide a bit more detail on those relationships below.

Intel also announced that it had created a new Custom Compute Group, folded under Koduri's Accelerated Computing and Graphics (AXG) Business Unit, to design and build its blockchain hardware. The group will also build other unspecified custom accelerated supercomputing hardware based on Intel's existing IP blocks. It's unclear if those products could address other types of cryptocurrency mining, or if the unit will also serve as an adjunct to Intel Foundry Services (IFS). 

Intel shared an image of its new blockchain accelerator, but Koduri's missive is light on technical details. However, we already know quite a bit about the company's upcoming Bitcoin-mining hardware. We first discovered Intel's Bonanza Mine chips in a listing for a presentation at the upcoming ISSCC conference, but the company has already moved on to its second-gen 'Bonanza Mine' ASIC, known as BZM2. This chip has a specialized architecture designed specifically to accelerate SHA-256 (a cryptographic algorithm) processing for Bitcoin mining at ultra-low voltage. These energy-efficient chips produce what Intel characterizes as "over 1000x better performance per watt than mainstream GPUs for SHA-256-based mining."

However, GPUs aren't often used for SHA-256 / Bitcoin mining, so that isn't the best comparison. Instead, Bitcoin is typically mined on ASICs, which are specialized processors specifically designed to execute one type of workload. ASICs afford efficiency and performance advantages over more complex types of chips, like CPUs and GPUs, that can perform the same task.

Intel's Bonanza Mine will compete with other ASIC-based devices from companies like Bitmain (which has a quasi-monopoly on high-end miners) and MicroBT. These companies suffer from long lead times and charge prohibitively high pricing (often based on Bitcoin's valuation) for their chips. They also have to rely on third-party design houses and foundries for manufacturing. Foundries like TSMC don't tend to give these companies preferential status in their fabs due to the uncertainty of the demand and sporadic nature of cryptomining; instead, they prioritize longer-term steady business from bigger chip designers.

Intel has tremendous production capacity of its own, but it isn't clear if it will fab the BZM2 ASICs in its own internal fabs or outsource production to TSMC (BZM2 is rumored to use TSMC's 5nm). However, Intel has traditionally outsourced roughly 25% of its silicon production and will drastically increase that amount over the next few years as it moves its GPU and some CPU production to TSMC, meaning it has more purchasing power than competing mining hardware firms. Additionally, Intel has tight control over its supply chain and has its own production, including packaging and test (OSAT) capacity, a critical step in the manufacturing process that has proven to be one of the major contributors behind the ongoing semiconductor shortages.

Intel says that its mining hardware consists of tiny pieces of silicon (the first-gen BZM1 chip measures a mere 14.2mm^2), so this new foray shouldn't impact its supply of current products. However, much like you can see in the image of half of a Bitmain S19's hashboard above, mining ASICs are deployed en masse. We expect Intel's solution will have a similar arrangement, so it will consume a non-trivial amount of silicon in aggregate. However, the smaller die size boosts yield and maximizes wafer area usage (up to 4,000 die per wafer), thus helping maximize production capacity (though it does require more wafer dicing/packaging capacity). 

Intel's First Bitcoin Mining Customers

Intel has announced three of its first customers, BLOCK (formerly known as Square), Argo Blockchain, and GRIID Infrastructure, but it's possible that the company has other large customers that wish to remain unnamed. The Bitcoin mining industry has been plagued by hardware shortages and excessive pricing for the last few years. Considering that analysts predict 1.5 to 2 million Bitcoin miners will ship this year, that will likely continue. As such, Intel could prove to be a disruptive force in this market segment given its scale, more predictable pricing, and likely more predictable supply.

We can see some of those aspects come into play with Intel's deal with its first publicly known customer, GRIID computing, which will soon go public at an estimated $3.3 billion valuation. Intel has guaranteed GRIID that it will sell it a minimum of 25% of its overall mining ASIC supply through 2025 at fixed pricing (until 2023), which is far more desirable than the fluctuating pricing from competing firms like Bitmain that assign pricing based on Bitcoin valuation. GRIID considers Intel's pricing assurance to be a considerable competitive advantage over other mining firms, noting that hardware costs are the largest expenditure for any mining deployment.

GRIID's supply agreement with Intel has plenty of redactions to protect sensitive information, but it also heavily references Intel's Reference Design Materials, which are a series of documents that customers use as guidance when they integrate the Bonanza Mine chips into their own custom systems.

This implies that Intel will supply the silicon to some of its customers, who will then create their own systems. This also meshes well with Jack Dorsey's plans for BLOCK, which he says will create a “bitcoin mining system based on custom silicon and open source for individuals and businesses worldwide.” Intel could also manufacture complete mining systems and bring them to market through partners, but we'll have to wait to learn more details about its go-to-market strategy.

Intel's listing for the upcoming ISSCC conference notes that Bitcoin mining is currently estimated to consume 91TW-hour of power annually, which is greater than the country of Finland, but points out that customized accelerators can optimize energy efficiency. Koduri acknowledges that blockchains require tremendous amounts of energy, but says that Intel aims to provide scalable and energy-efficient solutions to "promote an open and secure blockchain ecosystem and advance this technology in a responsible and sustainable way."

Intel's publicly-acknowledged customers all say they focus on sustainable energy sources. Notably, GRIID claims that approximately 74% of its power consumption is carbon-free, with a goal of being 90% carbon-free by the end of 2023 — all without carbon offsets or credits. GRIID hasn't released firm projections of the number of machines it plans to deploy, but it intends to operate three industrial-scale facilities totaling 734 megawatts of power by 2023.

The publicly-traded Argo Blockchain, which recently purchased 20,000 Bitmain Antimer machines for its West Texas data center, says it is climate-positive and focuses on hydropower for most of its facilities, though it will use a combination of wind and solar for its Texas plants.

Finally, BLOCK (formerly known as Square), also has a heavy focus on renewable energy sources. The company recently partnered with Blockstream Mining to build an open-source solar-powered Bitcoin mining farm in the United States.

More To Come

Intel's Bonanza Mine chips could give it a solid beachhead in the lucrative Bitcoin mining market where its new competitors, like Bitmain and MicroBT, have long dominated. Intel will also not limit the mining performance of its standard Arc Alchemist GPUs that will come to market soon, allowing it to compete with its old rivals AMD and Nvidia in other types of cryptocurrency mining (like Ethereum).

This provides Intel with a dual-pronged strategy of ASICs and GPUs for the rapidly-growing blockchain/cryptomining market that it hasn't participated in before (at least not publicly). Plugging those products into Intel's global production and supply chains could help the company grow quickly and sidestep some of the production shortfalls we've seen with other mining hardware providers. 

Intel will present its first-gen Bonanza Mine chips at an industry event later this month, and its claimed 137 GH/s performance and 18.2 W/TH efficiency rivals the best mining ASICs on the market. That sets a promising tone for the company's second-gen Bonanza Mine chips. However, there are still plenty of unknowns about the technical details, like performance, efficiency, pricing, power consumption, the process node, foundry used, and so on. We also don't know the company's plans for its future roadmap.

One thing is clear, though: If Intel can deliver enough silicon with competitive efficiency, performance, and pricing, its entrance into the Bitcoin hardware market could disrupt the status quo and touch off a new performance/efficiency arms race. We're sure to learn more during the company's investor event next week and the ISCC presentation at the end of the month. Stay tuned. 

Update: Intel's Bonanza Mine chip has now appeared in a contract with a mining startup, confirming that Intel is entering the cryptomining hardware business. 

Original Article:

It appears that Intel could enter the Bitcoin-mining hardware business, but not with its new upcoming GPUs. The ISSCC conference is a yearly gathering of the best and brightest minds in the chip industry. This year, Intel has a presentation scheduled in the 'Highlighted Chip Releases' category to outline a new "Bonanza Mine" processor, a chip described as an "ultra-low-voltage energy-efficient Bitcoin mining ASIC." That means Intel could soon compete with the likes of Bitmain in the market for specialized ASICs for Bitcoin mining. Intel also commented on the new chip to Tom's Hardware, saying "Intel has done design work around SHA 256 optimized ASICs for several years beginning with pathfinding work done in Intel Labs. We will share more details in the future."

The presentation comes on the heels of comments from Intel's GPU Chief Raja Koduri during a live stream last December, indicating that the company is working on specialized hardware for blockchain/cryptocurrency technologies. 

Bitcoin is typically mined on ASICs, which are specialized processors specifically designed to execute one type of workload. ASICs afford efficiency and performance advantages over more complex types of chips, like CPUs and GPUs, that can perform the same task. As a result, the overwhelming majority of Bitcoin mining occurs on ASICs, with companies like Bitmain providing the specialized silicon to miners at hefty premiums.

The first signs of Intel's interest in mining hardware surfaced in 2018 in the form of a patent for a specialized processing system that uses an optimized SHA-256 datapath (a cryptographic algorithm) for high-performance Bitcoin mining. As with all patents, the end product takes some time to come to market, but Intel has a wealth of experience in hardware-assisted SHA-256 algorithms due to the use of these instructions in its CPU products. Paired with its silicon production capabilities, Intel could be a particularly competitive entrant into the Bitcoin hardware market, especially given the focus on low-power, high-efficiency operation.  

Fast forward to December 29, 2021, and Intel's Systems and Graphics Architect, Senior Vice President and GM Raja Koduri appeared on popular streamer Dr. Lupo's show to promote the company's launch of its first gaming GPUs, the Arc Alchemist lineup that will launch this year.

Intel has signaled very clearly that it will not limit the mining performance of its upcoming discrete gaming GPUs, but the company still doesn't want its GPUs used for that purpose. Naturally, GPUs are used for Ethereum mining and other types of coins — not Bitcoin — but the topic led Koduri to make a few interesting statements about blockchain technology, which is the fundamental underlying tech behind crypto.

Koduri explained that Intel doesn't have an install base as a newcomer to the discrete gaming GPU market. As such, Intel would rather its GPUs be used by gamers than miners. However, Koduri's further comments are telling (28:20 in the above video):

"The other part of the answer is that we do think that this whole blockchain, as you call it, which coins are good  [...], I think blockchain is a transaction thing that is run much more efficiently than the burning of hardware cycles, is something that we are working on." Koduri said, "And that's not a GPU thing, so don't try to confuse that as a GPU thing. GPUs will do graphics, gaming, and all those wonderful things. But being able to do much more efficient blockchain validation at a much lower cost, much lower power, is a pretty solvable problem. And you know, we are working on that, and at some point in time, hopefully not too far into the future, we will kinda share some interesting hardware for that."

Given the timing of the ISSCC presentation, and the subject matter, it appears that Intel will share that information about the new hardware on Wednesday, February 23rd at 7 am PST. The 'DS1' moniker in the presentation listing denotes that Intel will have a video demo of the chip.

For now, it isn't clear if Intel will release the Bonanza Mine chip as a product for the public or if it remains confined to a research project. However, given that the chip is in the "Highlighted Chip Releases: Digital/ML" track and Koduri's comments, it's logical to expect that these chips, or some variant thereof, could be offered to customers in the future.

The primary bitcoin ASIC manufacturers, like Bitmain, suffer from long lead times and charge prohibitively high pricing for their chips, largely because they have to rely on third-party foundries to make the chips. Additionally, foundries like TSMC tend to not give these companies preferential status in their fabs due to the uncertainty of the demand and sporadic nature of cryptomining — instead, the fabs prioritize longer-term steady business from bigger chip designers. All of this is to say that Intel could make a meaningful and lucrative entry into this high-margin market backed by its incredible production capacity, giving it a leg up over competitors. Whether or not that will happen remains to be seen. 

We'll be there at ISSCC to learn more about the new chips. Stay tuned.  

Update 1/18/2022, 11am PT: Added Intel's statement to the article.  

Intel shared plans with employees earlier this month on how it will keep reinvesting into its existing talent. As competition in the semiconductor and general engineering markets increases, Intel seems to have identified one way to simultaneously bolster employee retention and attract new talent: better salaries.

The additional $2.4 billion expense to Intel's bottom line will be distributed to its employees in either cash ($1 billion) or shares ($1.4 billion). Wages across the company will benefit from the extra $2.4 billion infusion at the start of 2022. Intel took this decision to "reignite our culture and drive our business strategy."

Intel isn't taking a "spray and pray" approach with this multi-billion dollar fund. Instead, the company will structure the pay increases according to employee performance and the value of their skillset to Intel and possible competitors looking to snag talent. This, of course, is a strategy that Intel itself knows all too well. AMD lost GPU chief Raja Koduri (and countless others) to Intel's graphics group.

"These updates are designed to enable Intel to win the fierce battle for talent in today's competitive market while strengthening our execution," Intel said in a written statement. "These plans include, but are not limited to, updates to our salary structure, increases to our global merit budget, differentiated bonuses for top performers, increased stock targets, and more frequent vesting for restricted stock units."

Poaching talent from competing companies at the semiconductor industry level is nothing extraordinary in itself. There's a limited pool of professionals to contract, and those that gain visibility through their excellence do so not only in their companies but in the industry perception at large. It would seem that Intel feels the need to better insulate itself from "aggressive" acquisitions other companies could make from their employee ranks. Interestingly, while Intel is generally perceived to pay lower wages than comparable companies, it currently stands at a 75% "salary satisfaction rate" according to Indeed, which is above AMD's 64% but below Nvidia's 78%.

Intel currently employs around 110,000 professionals all across the globe. The company's payroll for Oregon alone (where it has its most advanced facilities and headquarters) took some $4.6 billion from Intel's bottom line in 2021. That is an average of around $150,000 per worker, considering the company employs about 30,000 professionals in that region alone. If the whole $2.4 billion dollars were evenly distributed across its 110,000 employees, each would receive an extra ~$21,000 per year.

The company wants to hire several hundred more professionals in the Oregon region for its 1DX cutting-edge research factory upgrade. However, only time will tell whether this financial boost will be enough to secure all the sought-after talent Intel employs and will be looking to employ in its future.

After radically changing its approach to GPUs and hiring Raja Koduri in 2017, Intel has been rather aggressively hiring GPU engineers from various companies in general and from Raja Koduri's former company, AMD, in particular. Last month the company poached Vineet Goel, a graphics technology veteran from AMD.

At Intel, Vineet Goel will serve as Vice President and General Manager of Xe GPU Architecture and IP Engineering at Intel and will be responsible for development of the company's Xe architectures. An Intel spokesperson confirmed to CRN that Goel will head a group of architects and engineers that will be 'architecting, designing and verifying Intel’s Xe IP road map.' Since the first two or three Xe architecture generations have already been defined (or at least named) Goel will have an impact on Intel's Xe GPUs that are years down the road. 

Vineet Goel is has had quite a career in the graphics industry. Most recently he served as Corporate Vice President of GPU Architecture at AMD and before that (from August 2016 to June 2019) was responsible for GPU architecture development at the company. Given the timeline, Vineet Goel played a key role in development of AMD's latest RDNA and RDNA 2 as well as CDNA and CDNA 2 architectures. Furthermore, he also contributed strongly to development of upcoming RDNA 3 and CDNA 3 architectures as well as their successors.

Goel he started his career at Real3D in the late 1990s and continued it at ATI Technologies Orlando division after Real3D was sold to Intel in 1999. He worked at ATI and then at AMD till 2011, when he joined his former colleague Eric Demers at Qualcomm and worked on ultra-low-power Adreno GPUs for Snapdragon system-on-chips. He spent about five years at Qualcomm and then re-joined AMD in mid-2016.

Over his career Goel was granted dozens of graphics related patents, but avid readers might remember him for his work on ATI's TruForm and other tessellation technologies (for Microsoft's Xbox 360, ATI's Terascale/Terascale 2 architectures) supported by the company's GPUs over the years. His more recent inventions include FidelityFX Super Resolution, multi-instance GPUs, and chiplet-based machine learning accelerators. 

Vineet Goel is a yet another ex-AMD graphics engineer or executive that Intel has hired in the recent years. The company has also hired multiple people from Nvidia. Among Intel's noteworthy hires in the recent years are  Masooma Bhaiwala, Tom Petersen, Jon Carvill, Antal Tungler, Darren McPhee, Devon Nekechuk, Damien Triolet, and many others. Intel also recently boosted its game developers relations team with four highly-experienced executives.

Update 9/21/21 5:30am PT: Intel reached out to clarify Raja's response, which was misquoted in the referenced article. We have amended the text accordingly: 

Raja Koduri, Intel's Senior Vice President and General Manager of the Accelerated Computing Systems and Graphics (AXG) Group, recently shed some light on its decision to contract TSMC to manufacture its ARC GPUs on its 6nm process. 

"It is necessary to first determine the process that can be assumed at the start of design," said Raja. "Other features, such as how much operating frequency can be used are also important factors. Cost is also an issue. These three, that is, the cost-performance-capacity, is taken into consideration when deciding which process to use. " 

Intel concluded that the first product, Alchemist, happened to find the best balance on TSMC's N6 node. And of course, it can't be understated that due to Intel's series of process delays, competing with AMD or NVIDIA with a new product on a not-leading-edge node could certainly bite into the performance potential for ARC.

The semiconductor manufacturing market has been hit repeatedly over the last 18 months with supply issues, stemming mostly from the complexity of its long supply chain. However, Intel seems to have escaped relatively unscathed, mostly owing to its vertical strategy. Intel designs and manufactures its CPUs fully in-house, giving it more flexibility than so-called "fabless" manufacturers (such as AMD) to prioritize its manufacturing lines and adapt to shifting market conditions.

The complex equation to choose a certain node also encompasses other aspects. For example, the CPU cores for AMD's Ryzen 7 5800X CPU (8-cores, 16-threads) feature a roughly 80.7 mm² surface area on TSMC's 7 nm process for a total of 4.15 billion transistors. AMD's top GPU offering, the RX 6900XT, manufactured on the same process, absolutely dwarfs that at more than six times the die size (520 mm²) and 26.8 billion transistors. In other words, GPUs are in another league, in general, when it comes to silicon manufacturing simply because they are larger, resulting in fewer chips per wafer.

Of course, opting for TSMC also means there's less capacity for its rivals to produce GPUs and CPUs on the best manufacturing nodes available, as well. So moving GPU production to TSMC means Intel will be able to produce more devices in a silicon-hungry market while simultaneously assuring its competition can't make as many chips as they could sell. That's one way to beat the competition. 

Intel announced several changes to its leadership today as it restructured one of its most critical groups and formed two new business units. As a result, long-time Intel veteran and one-time CEO candidate Navin Shenoy will leave the chipmaker on July 6 after 26 years with the company. In contrast, Chief Architect Raja Koduri will see a promotion to a newly-formed AXG graphics group.

Pat Gelsinger,  who recently passed the 100-day mark as Intel CEO, has restructured the Data Platform Group (DPG), one of the company's largest revenue generators that's responsible for other key segments, like the Data Center Group (DCG). The changes see the formation of two new groups. Intel veteran Sandra Rivera will lead the Datacenter and AI group, with this new group now being responsible for Xeon CPUs, FPGA, and AI products. She previously served as the head of Intel's Human Resources, and before that ran the Network Platforms Group.

Nick McKeown will helm a new Network and Edge Group that will merge the Network Platforms Group, Internet of Things Group (IOTG) and Connectivity Group into one unit.

Navin Shenoy, the now-former executive vice president and GM of DPG, will stay on with the company to manage the transition until July 6, 2021. Shenoy had a long 26-year tenure at Intel, having also run the Client Computing Group and Intel Asia Pacific. Intel filed an 8K on the matter that states "[..]Intel Corporation (“Intel”) determined that Navin Shenoy, Intel’s Executive Vice President and General Manager, Data Platforms Group (“DPG”), will separate from Intel effective as of July 6, 2021."

Intel is also creating two new business groups, with the aforementioned promotion of Koduri to the Accelerated Computing Systems and Graphics Group, now known as "AXG." This group will focus on HPC and graphics for integrated and discrete GPUs in all facets of Intel's empire. However, it's unclear if that results in the dissolution of the current Architecture, Graphics and Software group helmed by Koduri.

Industry veteran Greg Lavendar, Gelsinger's SVP and CTO at VMware, also joins Intel as the new CTO and SVP and GM of a new Software and Advanced Technology group. Intel Labs will also fall under Lavendar's remit.

All four executives will report directly to Gelsinger. “Since re-joining Intel, I have been impressed with the depth of talent and incredible innovation throughout the company, but we must move faster to fulfill our ambitions,” said Gelsinger. “By putting Sandra, Raja, Nick and Greg – with their decades of technology expertise – at the forefront of some of our most essential work, we will sharpen our focus and execution, accelerate innovation, and unleash the deep well of talent across the company.”

These changes come on the heels of a larger as-yet unconfirmed effort to restructure the company's Manufacturing and Operations and separate Global Supply Chain groups into one Manufacturing, Supply Chain and Operations group, as previously reported by CRN.

Intel has also brought on Samsung's former head of its North American foundry business, Hong Hau, to lead its shift to its own third-party foundry company, Intel Foundry Services, as part of its IDM 2.0 initiative. Here's the breakdown of today's changes from Intel's press release:

• Sandra Rivera will take on a new role as executive vice president and general manager of Datacenter and AI. Rivera will lead this organization's focus on developing leadership data center products for a cloud-based world, including Intel Xeon and field programmable gate array (FPGA) products. She will also drive the company's overall artificial intelligence (AI) strategy. Rivera has a deep history in data center technology and a track record of integrating Intel's silicon and software portfolios to drive customer value. Prior to her role serving as Intel's chief people officer, she led Intel's Network Platforms Group. (Sandra Rivera's biography)
• Nick McKeown will join Intel full-time on July 6 as senior vice president and general manager of a new Network and Edge Group. This brings Intel's Network Platforms Group, Internet of Things Group and Connectivity Group into a single business unit chartered to drive technology and product leadership throughout the network to the intelligent edge. Renown in the networking technology industry and recipient of the 2021 IEEE Alexander Graham Bell Medal, McKeown was previously a part-time Intel Senior Fellow who joined the company with its 2019 acquisition of Barefoot Networks, which he co-founded. (Nick McKeown's biography)
• Greg Lavender has joined Intel as chief technology officer (CTO) and senior vice president and general manager of the new Software and Advanced Technology Group. This group will drive Intel's unified vision for software, ensuring it remains a powerful competitive differentiator for the company. As CTO, Lavender will also be responsible for driving Intel's technical innovation and research programs, including Intel Labs. He brings more than 35 years of experience in software and hardware product engineering and advanced research and development to Intel, most recently serving as senior vice president and CTO of VMware. He has also held key leadership roles at Citigroup, Cisco and Sun Microsystems. (Greg Lavender's biography)
• Raja Koduri, a well-known innovator in GPU computing technology, will lead the Accelerated Computing Systems and Graphics Group, a newly formed business unit that will increase the company's focus in the key growth areas of high performance computing and graphics. AXG is chartered with delivering HPC and graphics solutions for integrated and discrete segments across client, enterprise and data center. Koduri previously served as Intel's general manager of Architecture, Graphics and Software. (Raja Koduri's biography)

AMD's FidelityFX SuperResolution technology works not only on the company's Radeon graphics processors, but also on Nvidia's GeForce GPUs so developers can support it across all the best graphics cards. For Nvidia's, which has its own deep learning super sampling (DLSS) technology, ensuring compatibility with AMD's FSR is not a priority, but Intel, which is quarters away from launching its gaming GPUs, is looking at AMD's FidelityFX SuperResolution.  

AMD's FidelityFX SuperResolution is a typical upscaling technology that generates the final image, based on multiple frames as a point of reference using linear and nonlinear processing techniques, according to an AMD patent. Unlike Nvidia's DLSS, AMD's FSR does not really use deep learning, something that has its advantages and disadvantages. Meanwhile, the technology promises tangible performance improvements without quality degradation, so game developers should be interested in supporting it. 

Since AMD's FidelityFX SuperResolution is hardware agnostic, it also makes sense for Intel to support it and optimize drivers for it. As a result, Intel's graphics chief Raja Koduri said in a Twitter post that Intel could support the technology developed by AMD.  

"Definitely looking at it — the deep learning capabilities of Xe-HPG architecture do lend to approaches that achieve better quality and performance," said Raja Koduri. "We will definitely try to align with open approaches to make ISVs job easier." 

At present AMD's FidelityFX SuperResolution is supported by Gearbox Software's Godfall title, which supports a number of other AMD-designed technologies too. But making AMD's FSR technology an industry-standard is not impossible. AMD's FidelityFX technologies are available not only on PCs, but also will be available on the latest game consoles that use AMD's GPUs. Therefore, over time these technologies will be adopted pretty widely and AMD's rivals Intel and Nvidia will have to optimize their drivers for games that use AMD's technologies.  

Intel's graphics chief Raja Koduri published the first 'official' image of Intel's upcoming gaming graphics processor based on the Xe-HPG architecture. Koduri also confirmed that at least one of the company's DG2 GPUs will feature 512 EUs. 

"Xe-HPG (DG2) real candy – very productive time at the Folsom lab couple of weeks ago," Raja Koduri wrote in a Twitter post."[…] Lots of game and driver optimization work ahead for Lisa Pearce's software team. They are all very excited and a little scared." 

Intel's Xe-HPG architecture employs energy-efficient processing blocks from the Xe-LP architecture, high frequency optimizations developed for Xe-HP/Xe-HPC GPUs for data centers and supercomputers, high-bandwidth internal interconnections, hardware-accelerated ray-tracing support, and a GDDR6-powered memory subsystem. The DG2 family GPUs are set to be manufactured at TSMC and are projected to hit the market in late 2021 or early 2022.

At present, Intel's highest-performance discrete GPU is based on the Xe-LP architecture and features 96 EUs. Therefore, an Xe-HPG-powered graphics processor with 512 EUs will offer significantly higher performance than Intel's existing standalone GPU. Rumor has it that the performance of Intel's graphics processor with 512 EUs will be close to that of Nvidia's GeForce RTX 3080.  

A star engineer, Raja Koduri is one of the Intel executives who tends to reveal development progress of upcoming products via social media. A couple of months ago, he announced that the first GPU based on Intel's Intel's Xe HPG architecture had powered on, and this week, he seemingly teased the bring-up process of Intel's upcoming entrant into the best gaming graphics card race.

"From 2012 to 2021 — same Intel Folsom lab, many of the same engineers with more grey hair," Raja Koduri, general manager of Architecture, Graphics, and Software at Intel, wrote in a Twitter post Thursday. "I was at Apple back then, getting hands on with pre-production Crystalwell, nine years later playing with a GPU that is >20x faster!"

The two pictures Koduri included show him running some tests on two development systems: one based on Intel's Haswell with Iris Pro 5200 graphics equipped, a 64MB eDRAM package (Crystalwell) from 2012 and another powered by an upcoming Intel Xe. He didn't specify the GPU as Xe HPG specifically, but the running of 3DMark, as well as the video outputs point toward the gaming-focused GPU.

The second image partly reveals the Xe bring-up board. Such boards are designed to provide maximum flexibility in terms of GPU configuration and power delivery, so while they have display outputs, they do not look like graphics cards at all. That said, it's not surprising to see the Xe HPG development board come with a cooling system that looks like it belongs with a server CPU. 

It's also interesting to see Koduri says that the Xe GPU was over 20 times faster than Intel's Iris Pro 5200 from 2013. Of course, an upcoming discrete graphics processor should be an order of magnitude faster than an eight-year-old integrated GPU. And ">20x  faster" could mean a range of things (not that we would expect Koduri to share performance numbers at this stage).

For some comparison, Intel's Iris Pro 5200 with 40 execution units (EUs) and 128MB of eDRAM scores 1,426 graphics points in 3DMark FireStrike. By contrast, the latest Intel Iris Xe G7 integrated GPU with 96 EUs scores between 5,800 and 5,900 graphics points, making it over four times faster than its ancestor in  said benchmark. 

Modern discrete graphics cards, such as Nvidia's GeForce RTX 3060 Ti, score around 31,000 graphics points in 3DMark FireStrike, so they are, indeed, over 20 times faster than Intel's Iris Pro 5200. Meanwhile, Nvidia's top-of-the-range GeForce RTX 3090 scores between 52,000 and 53,000 graphics points in 3DMark Firestrike (37 times faster than the Iris Pro 5200). 

We can't draw any firm conclusions on Intel Xe HPG's performance based on Koduri's tweet. But if by over 20 times faster, the exec meant something close to 20 times faster, then we can expect the GPU to compete against products like the GeForce RTX 3060 Ti. We'll have to wait for much more information to see. 

Intel's Chief Architect, Raja Koduri, Tweeted out an image showcasing Xe HPG running an unreleased version of 3DMark with a new mesh shader feature test, demonstrating that the Xe HPG architecture is now at a fully functional state.

It's cool to see Xe HPG, which is designed to compete directly with the best graphics cards from AMD and Nvidia, already working with the mesh shader feature set, which was just released with DX12 ultimate and allows greater optimization of the rasterization pipeline. You can read more about it here. Unfortunately, we don't know anything about this new 3DMark mesh shader test specifically, but presumably, it will come out soon if it's already working on Intel's GPUs.

Intel's Xe HPG is the gaming-centric variant of Intel's new Xe GPU architecture. It will come with GDDR6, and full hardware ray tracing support. There's also a possibility Intel will be outsourcing the silicon for its Xe HPG chips to TSMC (or even Samsung). Unfortunately, these are all the details we know for the architecture as most of Intel's Xe HPG architecture remains a secret, for now.

It's great to see Intel's gaming GPUs are close at hand. Hopefully, they'll provide good competition for AMD and Nvidia if the graphics card shortage doesn't hinder sales.

We've known about Intel Xe Graphics for ages, and the integrated Xe LP variant has been shipping in Tiger Lake laptops since last fall. Raja Koduri, Intel's senior VP of Architecture, Graphics, and Software, has tweeted various images of Xe HP chips in the past. Today, he posted a die shot of the upcoming Xe HPC version, presumably meaning 7nm Ponte Vecchio. Specs are sort of unknown, though we have plenty of clues about what the final product will have in terms of specs.

The above image is the dual-chiplet variant, with the two halves connected via EMIB (Embedded Multi-die Interconnect Bridge). Around the outside of the two main GPU blocks are a bunch of supporting chips, and that's where things get interesting. The rectangles aren't all the same size, and there are five chips for each GPU. What are these chips, and what are the specs for each? It's hard to say.

Raja mentions "7 advanced silicon technologies in a single package." Some of these are easier to guess at than others; Foveros, EMIB, SuperFIN, Rambo Cache, HBM, and Compute Tiles have all been mentioned as being part of Xe HP. That's six items, so we're missing one, and it's entirely possible Raja's list is slightly different.

The two chips are inverted versions of each other in the die shot, mostly, but the blocks on the right are more square-shaped (200x216 pixels) than the blocks on the left (174x216 pixels). Then we have the top-left chip (186x138 pixels) and the bottom-right chip (218x138 pixels). Perhaps Intel is doing some creative image editing to obscure the chip dimensions, but then why post the image in the first place?

We do know that Intel is using its Foveros 3D chip stacking technology with Ponte Vecchio. Given the asymmetrical chip sizes, there are probably three different chips that contain one or more of the "tiles" that Intel has previously mentioned. Each chip could contain one or more of: HBM2, Rambo Cache, or Compute. But right now, we don't know how Intel is distributing things.

As for the main GPU block, the die is blacked out, but we have a decent idea of what to expect, and the blocked out sections are easier to guess at. The center strip of four rectangles on each GPU is probably the fabric for routing data between the execution units. To the left and right of the center are eight identically sized blocks that likely each contain 64 EUs (Execution Units), with eight ALUs (aka, GPU cores) per EU. That gives 512 EUs per chip, and 1024 EUs for the entire package, with potentially 8196 "cores" if we're trying to compare things with AMD and Nvidia GPUs.

The remaining six rectangles on the left and right sides are likely for memory and other interfaces to the HBM, Rambo Cache, and Compute tiles — or maybe just memory interfaces. Six memory controllers suggest a potential 6144-bit interface. That's the same overall bus width as Nvidia's A100, though Nvidia allows for one disabled interface and HBM2 chip per package. There are two smaller rectangles near where the two dies connect.

Even though we can't say for certain what each of the blocks is doing, it's clear that Intel has packed a lot of compute power into a single package. Previously, Raja showed off this package shot of Xe HP with a AA battery for scale. Whether that's the same package we see in today's die shot isn't certain, but it seems likely. What any of this means for the consumer-focused Xe HPG, aka DG2, is anyone's guess. 

Jim Keller, a famed chip architect with notable stints at Intel, AMD, and Tesla, has joined AI chip startup Tenstorrent as President, CTO, and board member. Keller previously worked with Tenstorrent founder Ljubisa Bajic at AMD and personally provided the first funding for the startup.     

Keller is known as a leader of transformational efforts during his storied past at several leading semiconductor firms, with his most recent position at Intel following the same trajectory. Keller joined Intel in 2018 and, in tandem with Raja Koduri and Murthy Renduchintala, was responsible for designing a new six pillar strategy meant to help the company recover from an extended period of roadmap delays. 

In a move seen by many as a sign that Intel's efforts to get back on track had stalled, Keller left Intel for personal reasons in June 2020 with plans to serve a six-month stint as a consultant to help the company transition to a new leadership team. Shortly thereafter, Intel announced that its 7nm process was delayed to such an extent that, for the first time, the company might have to turn to outside foundries to help produce its core logic devices. Keller's former boss, Murthy Renduchintala, was ousted a few days later.  

With Keller's six-month consulting agreement with Intel now apparently over, he has now joined the Tenstorrent team. The AI chip startup, based in Toronto, Canada, is designing new Grayskull inference processors for image recognition and voice processing tasks. Tenstorrent's approach melds high-performance inference processors with a new approach that uses AI to optimize low-level software functions, thus unlocking higher levels of speed and efficiency in an approach known as Software 2.0. 

“Software 2.0 is the largest opportunity for computing innovation in a long time. Victory requires a comprehensive re-thinking of compute and low level software,” Keller said. “Tenstorrent has made impressive progress, and with the most promising architecture out there, we are poised to become a next gen computing giant.”

Keller had previous jobs at Tesla, where he served as the Vice President of Autopilot and Low Voltage Hardware, helped architect the Zen microarchitecture while he was AMD's corporate vice president and chief cores architect, and is also famous for designing AMD's successful K7 (Athlon) and K8 architectures. AMD's canceled K12 uArch was another of Keller's more famous projects, and he has also worked for Apple, helping develop the A4 and A5 processors.

Keller is known for relatively short tenures at companies, typically leading turnaround efforts for roughly three years before moving on to other challenges. His time at Intel, where he served as Intel's senior vice president in the Technology, Systems Architecture and Client Group and general manager of the Silicon Engineering Group, was notably shorter at roughly two years. 

Intel's Chief Architect Raja Koduri tweeted the first images of the company's new Xe HP GPUs that that are currently sampling to Intel's customers. The cards, built on the 10nm SuperFin process, are also being used as the software development vehicle for the Aurora Supercomputer. The exascale-class supercomputer has been delayed due to Intel's struggles with the 7nm node used in its Ponte Vecchio GPUs, but due to similarities between the cards, the new Xe-HP cards can be used to develop software for Aurora. The image above shows the already-announced XG310 Intel data center GPU flanked by the new Xe-Hp models. 

The variant on the left is clearly a traditional PCIe 3.0 x16 add-in card (AIC) with a full-height, 3/4 length form factor, just like the XG310 model next to it. As a quick reminder, the Intel-powered XG310 GPU consists of four separate Iris Xe Max discrete graphics chips, formerly codenamed DG1, that are also used as discrete GPUs in laptops. Instead of the typical use case for server GPUs, like machine learning workloads, the four processors work in tandem to process cloud gaming and media transcode and encode workloads for real-time video streaming. 

Given the similarities between the two cards, we can expect the Xe HP GPUs to employ a similar architecture based on multiple Xe graphics die, but paired with HBM memory tied to the GPUs via Intel's EMIB packaging technology. Intel is expected to offer different models with either 1, 2, or 4 tiles (GPU die) to satisfy various workload requirements.

The Xe-HP cards' execution units (EU) also support different data formats tailored for data center and HPC usage, like bfloat16 for AI workloads, DP4A convolution instructions for deep learning and Intel's AMX instructions. 

Given the slim size of the two Xe HP variants, it's clear the passively-cooled single-slot designs have a relatively tame TDP limit. On the right, we can see a single auxiliary 8-pin power connector for the card. A single 8-pin can deliver up to 225W safely, and the PCIe slot can deliver 75W; we're looking at a possible 300W maximum power draw for the card. 

Intel didn't share further details of the cards pictured, but we expect more details to filter out as they ship to customers.   

Intel's Raja Koduri is slated to present a "1000X More Compute for AI by 2025" presentation at Samsung's Advanced Foundry Ecosystem (SAFE) Forum next week, which comes as Intel mulls its strategy for outsourcing some of its production to third-party fabs. The presentation comes after Raja Koduri tweeted an image of a visit to Samsung's Giheung plant in Korea last year, sparking rumors that Intel would use Samsung to produce components for its Xe graphics solutions. Those rumors seemed spurious in the past, but Intel's recent announcement that it will outsource some chip production, and this week's revelation that the company still hasn't decided just what or where it will outsource, makes Koduri's latest interaction with Samsung's foundry all the more interesting. 

Intel is certainly at a crossroads. After a decade of dominance fueled by the company's own process tech, the company announced that problems with its 7nm node had forced it to consider outsourcing some components built on leading-edge process tech to third-party foundries, a first for the company. But the company still hasn't developed an outsourcing strategy, as evidenced by Intel CEO Bob Swan's comments in the company's Q3 2020 earnings call. Hence, it's possible we could see the company use either TSMC or Samsung foundries to produce its next-gen flagship chips, or even both.  

Swan said that even though Intel will now engage third-party foundries as strategic partners, it will continue to develop its own leading-edge nodes and has deployed a "fix" for its own 7nm node (though that fix has led to an untenable delay). For now, Intel's problem is deciding just where it will build its chips that will come to market in 2023. 

Swan said that Intel hasn't decided which chips it will use external foundries for, but did note that "we feel confident in the ability of us being able to port to TSMC," marking the first time the company has mentioned a specific third-party foundry in the context of using it for leading-edge production. That makes it clear that Intel is already working with TSMC, at least in some form.

But there are still plenty of questions to be answered, and that uncertainty is crystal clear in the snippet above from Intel's Q3 earnings deck. Intel says that it is "confident in 2023 product leadership on either Intel 7nm or an external foundry or mix of both." 

Intel will likely leverage its packaging tech to reduce the number of externally-sourced components required to build a full chip. Swan says that Intel will decide if it will turn to outside foundries as a stop-gap or invest in its own 7nm equipment, and also where and what to outsource, by "really early next year." 

Even though Intel's chips built with externally-sourced components won't come to market until 2023, long lead times require Intel to make a decision soon so it can allow its future partners to build enough production capacity. 

But therein lies the problem - any third-party foundry that accepts a contract will likely have to build out significant capacity just for Intel. TSMC is already capacity-constrained and tends to command a premium for leading-edge wafers. Swan also noted that Intel is confident that it can "port back in" from TSMC to Intel's own process tech, meaning the company could move back to its own foundries once it has fixed its own 7nm node. (We imagine those architectures would still require significant re-tuning that wouldn't necessarily classify as a traditional 'port.')

The idea of Intel moving back to its own 7nm probably doesn't seem like an attractive possibility to TSMC, which already has plenty of demand for its 7nm tech. It likely isn't interested in short-term or sporadic business – especially given the large upfront investments required. That means Intel will likely have to commit to procuring a significant amount of capacity from TSMC to secure a contract, much like AMD did with its wafer supply agreement (WSA) with GlobalFoundries.

Meanwhile, Samsung's wafers are relatively less expensive. The company also currently doesn't have as much demand as TSMC, meaning it could have more available production capacity – or at least be willing to dedicate more capacity to Intel's orders. 

That leaves plenty of room for Intel to secure at least some of its future chips from Samsung. It certainly doesn't have to be a TSMC "or" Samsung decision: Targeted designs can defray some of the disadvantages of using Samsung's nodes, which are generally less performant than TSMCs, and not all chips have to be on the highest-performing node. 

Intel could also seek a licensing deal that allows it to build chips based on an external foundries' process, but in its own facilities. GlobalFoundries employed a similar strategy when it licensed Samsung's 14nm process technology back in 2014, and it's possible the company would be open to a similar deal in the future. Conversely, Intel could also approach TSMC with a similar request, so anything remains possible.  

The one thing we do know for sure is that Intel will announce its decision early next year, and it certainly has several options at its disposal. In fact, that's the beauty of embracing the third-party foundry approach: The ability to source different nodes from different vendors based on each product's specific needs affords plenty of flexibility. If Intel fully embraces the third-party model, we could likely see the company source from both TSMC and GlobalFoundries.

Over the past several months, Intel's Raja Koduri has been slowly revealing portions of the upcoming Xe Graphics architecture and lineup. The Xe family will span everything from low power integrated and entry level graphics solutions under the Xe LP Graphics brand, up through data center multi-chip solutions with die stacking. The latter is we're talking about.

As discussed last week, Intel's Xe HP Graphics will come in three variants. The base model, which has been shown several times, has a single tile with 512 EUs (Execution Units) and most likely two HMB2e stacks. Intel hasn't confirmed exact specs, but it did show performance scaling for a computational workload of the 1-tile, 2-tile, and 4-tile variants:

The scaling from the additional tiles might look almost too perfect, but it's important to note that this is not a real-time graphics workload. Splitting work between GPUs for technologies like SLI and CrossFire is far more difficult to do and scaling from additional GPUs usually only nets gamers 50-80% more performance at best. For computational workloads, however, tasks are often independent and can thus hit perfect scaling.

Lest anyone doubt that the 4-tile GPU doesn't actually exist and is merely a publicity stunt, Raja whipped out the large package and briefly flashed it at the camera during his Hot Chips presentation. And yes, it's really big — much bigger than any other chip package we've seen.

Whether the 4-tile Xe HP will ever be put into production, or if it's merely a test product while Intel prepares Xe HPC, aka Ponte Vecchio, is a different matter.

Xe HP only uses EMIB to scale to multi-tile configurations. Xe HPC will also include a Rambo Cache tile, Foveros die stacking, and Co-EMIB with additional enhancements. Ponte Vecchio is planned for use in the upcoming Aurora supercomputer, and it was supposed to be manufactured on Intel's now-delayed 7nm lithography.

In the meantime, Intel now has 1-tile, 2-tile, and 4-tile Xe HP silicon in its labs. As you'd expect, the EMIB linking means the packages for the latter two are basically 2x and 4x the size of the base design, so the GPUs require three separate sockets.

The 4-tile implementation of Xe HP Raja showed off is capable of around 42 TFLOPS of FP32 compute. However, that's not actually the maximum capability. Raja also mentioned that the 4-tile chip is capable of reaching "petaflops scale computing," or >1000 TFLOPS. That's thanks to the presence of tensor cores, though we don't know the exact configuration.

Like Nvidia's A100 architecture and Google's TPUv4, Xe HP supports tensor cores. We assume these are capable of 128 operations per cycle, with one tensor core per EU. With 2048 EUs, that gives us:

2048 × 128 × 2 (FMA) = 524,288

We're missing clock speed, which would suggest either a 2GHz baseline for one petaflop, or potentially a different tensor core arrangement that can do more than 128 ops per clock. Either way, it should make it much easier for supercomputers to reach the level of exascale computing.

The reveal of the Intel Xe HPG during Intel's Architecture Day 2020 was part of the virtual firehose of information on a ton of upcoming products and technologies. We've covered Tiger Lake and Xe LP Graphics elsewhere, and we have new details on Xe HP / HPC and the newly christened 10nm SuperFin process. But one of the products we're most interested in seeing and testing isn't coming until 2021. We've speculated on what Intel's Xe Graphics would bring to the dedicated GPU since we first heard about Team Blue's aspirations back in 2018. The latest details are far more promising than what we were previously expecting, so a delay until (hopefully earlier rather than later) 2021 isn't necessarily a bad thing. Intel's dedicated GPU plans are definitely going to be more potent than the DG1 demo at CES back in January.

Intel originally had plans for a single graphics architecture with two micro-architectures back in 2018. Two years later, the number of microarchitectures has doubled to four. Xe LP is for integrated graphics and entry-level solutions, Xe HP is for high-end compute and data center workloads, and Xe HPC is basically Xe HP on steroids (and possibly with a shrink to 7nm, sort of), targeting supercomputing exascale solutions. That leaves the fourth and final microarchitecture that Intel just announced during its Architecture Day briefings: Intel Xe HPG.

Given what we know of Xe HP, the bifurcation into two different parts makes a lot of sense. First, Xe HP of necessity has FP64 (64-bit floating point) support, along with tensor cores. These are common features in data center compute, deep learning, and AI environments, but they're also extra bloat that's not needed for a gaming GPU. Second, Xe HP will use HBM2e memory.

Intel's Raja Koduri joked about having scars on his back from trying to launch two different HBM (high bandwidth memory) GPUs into the consumer market, referring to his time at AMD with the Fiji / R9 Fury X and Vega 10 / RX Vega 64 product launches. Both performed okay, but the adoption of HBM inflated costs and the resulting prices of both GPU families, ultimately leading to less than optimal prices and performance. For data center workloads, the additional bandwidth that HBM2e brings to the table makes sense — Nvidia uses HBM2 in its Nvidia P100, V100, and A100 products — but for consumers, it's still too expensive.

Intel Xe HPG will address both of these items by removing the FP64 support (or at least trimming it way down) and by adopting GDDR6 memory. That's not the only change, however. Dumping FP64 (possibly tensor cores as well) and HBM gives Intel room to add in other features. Specifically, Intel confirmed that Xe HPG will support hardware ray tracing. That's a critical move, considering the AMD Big Navi / RDNA 2 and Nvidia RTX 3080 Ampere will both arrive in the next month or two with ray tracing, and in November the Sony PlayStation 5 and Microsoft Xbox Series X will launch with AMD GPUs that also support the feature. Trying to break into the dedicated graphics card market with a product that lacks features the established players support wouldn't go over well.

There are still plenty of unknowns. How many EUs will Xe HPG support? Xe HP appears to have up to 512 EUs per tile, or the equivalent of 4096 shader cores (ALUs) if we're comparing it with AMD and Nvidia GPUs. AMD's Big Navi meanwhile is expected to support up to 5120 shader cores, while Nvidia's Ampere could go as high as 8192 CUDA cores (but will probably come in below that mark). With the reworking of features, Xe HPG could certainly increase the number of EUs to stay competitive, and a configuration with 640 EUs (5120 ALUs) isn't out of the question.

The other major bombshell that Intel dropped is that it plans to utilize a third party for fabrication of Xe HPG. That means it won't have to use up its limited 10nm SuperFin capacity making gaming GPUs, and it will perhaps join AMD and Nvidia by using TSMC to manufacture Xe HPG. It's either that or Samsung; either way Intel gets access to 7nm fabrication technology, though 10nm SuperFin is perhaps similar or even superior in practice — the nanometer numbers are certainly prone to being used as marketing rather than indicating true feature sizes.

Despite everything we don't yet know about Xe HPG and Intel's enthusiast gaming aspirations, don't count Team Blue out just yet. Intel demonstrated 1-tile, 2-tile, and 4-tile variants of Xe HP running a compute workload, with almost perfect scaling based on the number of tiles. The test used early drivers, running at non-final clocks of 1300 MHz. Intel was able to deliver 10.6 TFLOPS (FP32) with a single tile and up to 42.3 TFLOPS with a 4-tile implementation.

Obviously, this isn't the same thing as playing a game. Still, strip the extra stuff out of Xe HP, add some more EUs, and clock it at 1.7 GHz and we're talking serious firepower. If Intel can do that with Xe HPG (and we're not saying it will, but merely that it could) and Intel would have a gaming graphics card capable of 17.4 TFLOPS. That's far more than Nvidia's current RTX 2080 Ti, and it could end up being competitive with even Big Navi and Ampere — assuming drivers, ray tracing performance, and everything else fall into place.

The drivers experience with Intel has certainly improved, at least, as we discuss further in the Xe LP article. We recently tested Ice Lake Gen11 graphics as well as other integrated graphics solutions on Intel (and AMD) CPUs from the past several years. While the older HD 4600 (Gen7) graphics failed to run several titles (it lacks DX12 and Vulkan support) and had very poor performance, UHD 630 and Iris Plus worked properly. Scaling to 20 times as many EUs as UHD 630 should do wonders for performance, naturally.

Intel's ability to scale to a 2-tile solution linked via EMIB might also solve the scaling problem we've seen with SLI and CrossFire. The two tiles would simply appear as a single GPU (maybe), meaning there's even potential for a 2-tile Xe HPG solution that could theoretically crush any current GPU. It wouldn't be cheap, and scaling in games probably wouldn't be nearly as good as what Intel showed with the compute demo above, but we'll wait and see.

We're not saying any of this will happen, of course, but even a 512 EU Xe HPG solution could be competitive. Maybe. The proverbial proof is in the eating of the pudding — ray traced pudding, naturally. The good news is that, whatever happens, the next year of GPUs is shaping up to be far more exciting than the past year. New products from AMD, Nvidia, and Intel are coming to market, all with ray tracing support, and any one of the big three could come out on top.

Update 8/5/2020 1:15pm PT: Intel has confirmed via its Investor Relations website that the live streamed virtual event on September 2 will in fact be the launch of the Tiger Lake processors. The company also added Raja Koduri's Hot Chips presentation to its calendar for August 13, 2020.

Original Article:

Intel has notified the press via email that it will hold a virtual event on September 2 because "we have something big to share." Given the timing of the virtual event, we expect it to cover the company's 11th-Gen Tiger Lake CPUs along with the long-anticipated Xe Graphics DG1, a discrete mobile GPU that will mark the debut of Intel's new graphics processors. 

Intel teased both products at its keynote during CES 2020, and the timeline fits within our general expectations for a launch in Q3. It would also help for Intel to have something new to parry AMD's 7nm Renoir chips that have proven to be potent contenders in the mobile space, but Intel's pending chips don't appear to be a paper tiger. 

From what we already know, the 10nm+ Tiger Lake-U chips will feature a 50% increase in L3 cache capacity, going from 8MB to 12MB, for a total of 3MB per core. The chips also support AVX-512 and are expected to come with Intel's Willow Cove cores and Intel's Gen12 Xe graphics. The new chips also support faster DL boost and inference engines, including hardware acceleration for INT8, to tackle AI workloads. 

If Intel does tease the pending Tiger Lake chips, we can expect more details like launch dates and a few details about the new laptops that will arrive later in the year. Intel also has multiple other projects in flight, so we could hear more about its Rocket Lake chips for the desktop or other upcoming processors, but those details would probably be slight for now – just enough to keep us guessing, much like the invite you see above. 

Remember two months ago when Intel tweeted an image of a huge, mysterious chip? Well, we still don't know exactly what that chip is, but Intel is back again teasing something even bigger. Well, rather, Intel's Raja Koduri is here, showing off his (we quote) "big 'fabulous' package."

Of course, we still don't know exactly what this chip is, but there is room to speculate. Nor the last chip, nor this one are at all likely to be products that could also show up in non-socketed consumer graphics cards, competing with AMD and Nvidia in the ultra-high-end space of the best graphics cards. With chips this big, they're bound to be HPC products aimed at scientific and data center use, where performance vs. cost becomes a carefully balanced equation that absorbs extreme costs for individual parts. 

It looks to measure about 80 by 80 mm (with a margin of error), and we would expect a huge GPU, along with numerous HBM2 or HMB2e stacks to be lurking on the interposer, underneath the heatspreader.

This huge chip is undoubtedly a creation based on Intel's Xe graphics architecture (as proven by this tweet showing the huge chip under water). The amount of silicon underneath that heatspreader would be so huge, it would no longer be economically viable for consumers in any way, shape, or form -- not that Xe graphics is meant to compete in the consumer space anyway.

Looking at the image of the GPU under water, you’ll notice the sheer number of springs keeping the cold plate pressed against the die surface. This shows that bowing becomes a huge issue when chip packages get this big. The cooler also mentions ATS-4T at the top (as spotted by Komachi Ensaka), possibly referring to Arctic Sound - 4 tiles.

Rumor has it that the big HPC Xe GPUs will come with tiled layouts, featuring either one, two, or four performance tiles. Based on the sizes, we reckon this is the biggest Xe GPU of them all with all four tiles, with Koduri's last tease showing off the two-tile product.

Nevertheless, only time will tell what this massive, socketed GPU really is, and who it is for. For all we know, Intel is simply showing off what it can build, instilling fear in both AMD and Nvidia.

For the past 13 years, Ali Ibrahim has worked at AMD as a Senior Fellow, working on cloud and Xbox related projects, among other things. Now, Ibrahim has been poached by Intel, where he has become VP of Platform Architecture and Engineering of discrete GPUs department, as reported by CRN.

"We are thrilled that Ali has joined Intel as Vice President, Platform Architecture and Engineering – dGPUs to be part of the exciting Intel Xe Graphics journey," a spokesperson told CRN.

Intel's poaching of AMD's executives started in 2017, when Intel hired AMD's Raja Koduri at the start of Intel's plans for discrete graphics—though at that time we didn't know exactly what Intel was cooking. 

Now, it's no longer a secret that Intel has been building its own discrete graphics card, but they're not directly aimed at competing with AMD and Nvidia in the gaming segment—rather, the Xe GPUs are expected to be targeted at scientific and data center use. Here is all we know about Xe Graphics so far.

Next to Koduri and Ibrahim, Intel has also poached Masooma Bhaiwala for the discrete graphics projects, Jim Keller, Mark Hirsch, Balaji Kanigicherla, and Joseph Facca  But, AMD also fired back by hiring Intel's Daniel McNamara to help grow AMD's Epyc business.

Intel teased more information about its forthcoming Xe Graphics Architecture, which it will use in a tiered model to attack every facet of the graphics landscape spanning from desktop PC gaming and mobility uses to the data center. The new architecture scales to thousands of execution units (EUs) and comes with several new memory enhancements, like a new Rambo Cache and XEMF interface. 

Datacenter use-cases also equate to the bleeding edge high-performance computing (HPC) and supercomputing realm, so Intel made the announcements here at its Intel HPC Developer Conference in Denver, Colorado, on the cusp of the annual Supercomputing tradeshow. 

Intel also shared more information about its data center roadmap (including Sapphire Rapids processors) and its new OneAPI programming model.

We're here at the HPC Developer Conference to listen to Raja Koduri's keynote, and we'll add more information as it is revealed. We already have plenty to discuss, so let's dive in.

Intel's Xe Graphics "Ponte Vecchio" Architecture 

The first iteration of the Xe Graphics Architecture comes in the form of Intel's new 7nm "Ponte Vecchio" graphics card for general-purpose compute workloads, with this model designed specifically for HPC and AI workloads. Intel bills this card as its first "exascale graphics card," but that level of compute will require multiple cards working together over a fast and flexible fabric. This new card will debut in the Aurora Supercomputer at Argonne National Laboratory in 2021, which will be the world's first exascale-class supercomputer. 

Intel splits the Xe Architecture up into three designs that each address different segments: Data center, consumer graphics cards, and AI use-cases (HP); integrated graphics on its processors (LP); and the high-tier Xe HPC for high performance computing, with the latter being designed specifically for compute. The consumer version of the Xe Graphics card for gaming will lead the way in 2020, likely on the 10nm process. 

Intel will fab Ponte Vecchio on the 7nm process, signaling that it is well on track to the next node beyond its notorious 10nm process. Intel's CEO Bob Swan recently announced the company had completed power-on testing of its prototype, the DG1, and that version is largely thought to be fabbed on Intel's 10nm process. 

Intel isn't following the graphics industry's trend of using a single large monolithic die for its graphics card, though, as it will use an MCM (Multi-Chip Module) design that consists of multiple compute units tied together via a fabric (as you can see in the image above). Given that Intel will spread the graphics workload over multiple chips, the recent surfacing of Xe Graphics drivers that support multiple GPUs takes on a whole new meaning: These drivers likely serve as a key component for addressing the multi-die architecture within each discreet GPU.

The fact that Ponte Vecchio lands as the first 7nm product from Intel makes sense, even though this is a drastic departure from Intel's established norm. GPUs have many repeating structures that inherently tolerate defects easily, and designing in additional redundancy in some areas, like critical pathways, can further defray the risk of manufacturing the die on the early revisions of the node. It's also noteworthy that Intel uses small chiplets, which improves yields. 

These modules employ Intel's latest packaging technology, such as the Foveros 3D chip packaging technology, which consists of a 3D stacked die design that allows the company to use larger process nodes for non-compute elements (like I/O) or even mix-and-match CPU, GPU or AI processors. The company will also use EMIB (Embedded Multi-Die Bridge) technology (deep dive here) to tie the HBM packages to the compute die.

The cards can scale to thousands of execution units (EUs), though those obviously wouldn't be in a single chiplet, and Intel says that each EU offers a 40X increase in double-precision floating point performance.

The new scalable XEMF  (XE Memory Fabric) ties the units (compute and memory) together with a coherent memory interface, and Intel says the fabric can scale to thousands of Xe nodes. A large unified "Rambo" cache, packaged together with Foveros technology, provides what Koduri termed as massive amounts of memory bandwidth that is available to both the GPUs and CPUs simultaneously. 

The cards support both SIMT (GPU) and SIMD (CPU) vector widths, or it can process SIMT and SIMD simultaneously for maximum performance. The inclusion of SIMD processing will add AVX-type processing capabilities to data center accelerators, which is likely a move to make code more portable via OneAPI, which we'll cover shortly. 

Intel surely has plenty of IP for GPU SIMD processing due to its history with Larabee, which used SIMD processing entirely. Melding the two approaches would give Intel a nice blend of the two processing techniques. The ability to run both concurrently is a nice extra benefit. 

Intel isn't divulging key specifications of the graphics card yet, like the number of execution units per chiplet or clock rates, but the EMIB connection will provide the fastest possible data transfer rates, and at the best power efficiency, over the relatively short distances between the compute die and HBM memory. 

Intel also divulged that the cards would use the Compute Express Link (CXL) interconnect in an Intel-branded "Xe Link" implementation that provides memory coherency between both the numerous units on the graphics card and the CPU. This is aided by a small SoC that sits at the nexus of the fabric that connects multiple compute packages, which is required for the CXL interface. Memory coherency reduces data transfers, which often consume more time and energy than the actual compute workload.

Most importantly, the CXL interface requires the PCIe 5.0 connection, so Ponte Vecchio will land the new standard. As we know from previous disclosures, CXL-infused devices can communicate over both the CXL interface and the standard PCIe interface, but it isn't yet clear how Intel will stratify that type of dual functionality, meaning we may not see the CXL interface in the consumer-level gaming graphics cards, at least not as an external interface. Instead, the cards might simply operate over the PCIe 5.0 interface.

The PCIe 5.0 interface lines up well with Intel's plans for its Sapphire Rapids data center chips that it will deploy in tandem with the cards for the Aurora supercomputer. According to leaked information, those chips will bring PCIe 5.0 and DDR5 to the table, and today Intel divulged that the chips would debut in 2021 (more on that later).

Ponte Vecchio's compute units consist of a data-parallel vector-matrix engine paired with an undisclosed variant of high bandwidth memory (HBM), and are designed to deliver fast double-precision floating point throughput. Intel has also worked in many new RAS (Reliability, Availability, and Serviceability) features inspired by its Xeon CPU lineup, like ECC for memory and caches. 

Intel Xe Ponte Vecchio Graphics in Aurora Supercomputer

The DOE and Intel's announcement that the Xe Graphics architecture and Intel's host processors would power the Aurora supercomputer marked a significant win for the company, especially as it also tied in the company's "future generation" of the Optane DC Persistent Memory DIMMs that serves as one of Intel's key "data center adjacencies."

The original announcement was light on details, though we do know that Aurora will be the world's first exascale supercomputer and will be delivered in 2021. This is actually the second iteration of the Aurora design after Intel famously missed the 2018 design target with its Xeon Phi Knights Hill processors, which have now been retired.

Today Intel disclosed the node architecture, which consists of two Sapphire Rapids processors paired with six Ponte Vecchio graphics units. Each card will house 16 compute units. 

Data throughput is key here, so the design features an all-to-all architecture within the node to guarantee data delivery to the compute units via eight fabric endpoints per node. This scheme uses a combination of the CXL interface to create a unified memory pool between all tiers of memory, including the HBM in the graphics cards, the Sapphire Rapids processors, the DRAM in the system (undisclosed amount), and the Optane Persistent DIMMs. 

The overall system will feature "more than" 200 racks of servers, but Intel didn't disclose if these will be 1U or 2U racks, so it's impossible to reverse-engineer the numbers to determine the amount of server nodes. All told, the system will have 230 petabytes of storage and "more than" 10 petabytes of memory. 

Intel Data Center Roadmap

Intel's lack of public-facing roadmaps has long been a sore point for its customers, as it doesn't engender much faith in Intel's future plans, especially in light of the company's failed transition to the 10nm node. The company unveiled a new roadmap here at the event, which comes as an update to the roadmap it shared in 2018. 

The new roadmap confirms the Sapphire Rapids processors in 2021, but doesn't divulge many other details, like the process node. Given that Intel will use 7nm for Ponte Vecchio in 2021, it's safe to assume the data center processors will use the same node. Intel says the chips will provide an unprecedented amount of scalability for both scale-up and scale-out implementations. 

As mentioned, extremely credible leaks (from Huawei) have indicated that Sapphire Rapids will support PCIe 5.0 and come with eight-channel DDR5 memory. Those chips will drop into the Eagle Stream platform. 

Intel OneAPI

Using this radically new architecture will require specialized coding, so Intel and the DOE are using the company's new OneAPI programming model, which Intel designed to simplify programming across its GPU, CPU, FPGA, and AI accelerators. The software goes by the tagline of "no transistor left behind," and given its goals, that's an accurate statement. 

OneAPI provides unified libraries that will allow for applications to move seamlessly between Intel's different types of compute. If successful, this could be a key differentiator that other firms will not be able to match with as many forms of compute, so the DOE's support here is key to Intel's long-term goals. Interestingly, OneAPI will also work with other vendors' hardware, marking yet another milestone in Intel's changing view of fostering industry-standard interfaces and models, as opposed to its long-held tradition of using proprietary solutions. 

Intel says it designed the software to provide "choice without compromising performance and eliminating the complexity of separate code bases, multiple-programming languages, and different tools and workflows. oneAPI preserves existing software investments with support for existing languages while delivering flexibility for developers to create versatile applications." The software is now in public beta on the Intel Developer Cloud. Intel has also created a migration tool that converts CUDA code to OneAPI, which is a clear shot across Nvidia's bow, as the CUDA programming language serves as its primary moat. 

In a conspicuous Twitter post on Friday, Intel’s chief architect Raja Koduri seemingly hinted at a June 2020 announcement or release of the company’s forthcoming Intel Xe Graphics cards.

It is common knowledge by now among hardware enthusiasts that Intel will enter the discrete graphics market, as the company has been public about ever since taking Raja Koduri on board. In 2018, the company committed to a 2020 release schedule for the first of those Xe graphics card(s), which eventually will span from entry-level mobile all the way up to the data center, including gaming GPUs, and even exascale supercomputers with a Xe-based GPGPU that will serve as the launch vehicle for Intel's 7nm process.

As a refresher, Xe is another name for the Gen 12 graphics architecture, which will come in two micro-architecture variants, one optimized for consumers and one optimized for the data center.

However, so far Intel has not been willing to provide any more specific guidance beyond "first availability by end of 2020," although some rumors have placed the Xe-powered Tiger Lake CPUs in the first half of 2020. With the latest tweet from Raja Koduri, this might have changed.

The picture shows the backside of a Tesla Model S, whose custom license plate unambiguously reads ‘THINKXE.’ ("Think Xe.") Given Intel’s previous disclosures, also seeing ‘2020’ on the plate does not come as a surprise, and indeed gets one to think.

Most conspicuous is the June month on license plate. The June 2020 date seems too specific to be a coincidence. Intel might have an announcement, and perhaps even a release, planned for Computex in June 2020.

Meanwhile, another Twitter post on Thursday, from an unverified source, suggested that Lakefield-R will be another product based on Xe (based on some source code). The tweeter also says that the driver requirements for Lakefield-R and Ryefield are the same.

Intel Architecture Day

Intel's new heads of silicon development, led by Raja Koduri, the Senior Vice President of Core and Visual Computing, and Jim Keller, the Senior Vice President of Silicon Engineering, hosted its Architecture Day here in Santa Clara to outline the company's broad new vision for the future. Dr. Murthy Renduchintala, Intel's chief engineering officer and group president of the Technology, Systems Architecture & Client Group (TSCG) also presented at the event, which was held in the home of Intel co-founder Robert Noyce.

Highlights included the unveiling of the company's new Sunny Cove CPU microarchitecture, its new Gen11 integrated graphics, 'Foveros' 3D chip stacking technology, a teaser of the company's new Xe line of discrete graphics cards, and a new "One API" software designed to simplify programming across Intel's entire product stack. We also caught a glimpse of the first 10nm Ice Lake processor for the data center.

Intel has amassed a treasure trove of new technologies over the last several years as it has diversified into new areas like AI, autonomous driving, 5G, FPGAs, and IoT, and other areas. It's even added GPUs to the list. Intel's process technology touches every segment of all that tech, as well as the chips that power them, but its delayed 10nm process has slowed the company's progress.

To help get back on track, Intel brought in Raja Koduri and Jim Keller to outline a new cohesive vision that spans all facets of its operations. Together with the company's leadership, the pair identified six key building blocks that the company will focus on over the coming years. Those pillars include process technology, architectures, memory, interconnects, security, and software. The company hopes that focusing on these key areas will accelerate its pace of innovation and help it regain its competitive footing.

The event was a wide-ranging affair with an almost overwhelming amount of information and insight into the company's plans for the future, but a few new key technologies stood out as particularly promising. Let's take a look at some of the most interesting new technologies Intel is working on.

3D Chip Stacking With Foveros

Foveros (Greek for "awesome") is a new 3D packaging technology that Intel plans to use to build new processors stacked atop one another. The concept behind 3D chip stacking is a well-traveled topic that has been under development for decades, but the industry hasn't been able to circumvent the power and thermal challenges, not to mention poor yields, well enough to bring the technology to high-volume manufacturing.

Intel says it built Foveros upon the lessons it learned with its innovative EMIB (Embedded Multi-Die Interconnect Bridge) technology, which is a complicated name for a technique that provides high-speed communication between several chips. That technique allowed the company to connect multiple dies together with a high-speed pathway that provides nearly the same performance as a single large processor. Now Intel has expanded on the concept to allow for stacking die atop each other, thus improving density.

The key idea behind chip stacking is to mix and match different types of dies, such as CPUs, GPUs, and AI processors, to build custom SOCs (System-On-Chip). It also allows Intel to combine several different components with different processes onto the same package. That lets the company use larger nodes for the harder-to-shrink or purpose-built components. That's a key advantage as shrinking chips becomes more difficult.

Intel had a fully functioning Foveros chip on display at the event, that it built for an unnamed customer. The package consists of a 10nm CPU and an I/O chip. The two chips mate with TSVs (Through Silicon Via) that connect the die through vertical electrical connections in the center of the die. The channels then mate with microbumps on an underlying package. Intel also added a memory chip to the top of the stack using conventional a PoP (Package on Package) implementation. The company envisions even more complex implementations in the future that include radios, sensors, photonics, and memory chiplets.

The current design consists of two dies. The lower die houses all of the typical southbridge features, like I/O connections, and is fabbed on the 22FFL process. The upper die is a 10nm CPU that features one large compute core and four smaller 'efficiency' cores, similar to an ARM big.LITTLE processor. Intel calls this a "hybrid x86 architecture," and it could denote a fundamental shift in the company's strategy. The company later confirmed that it is working on building a new line of products based on the new hybrid x86 architecture, which could be the company's response to the Qualcomm Snapdragon processors that power Always Connected laptops. Intel representatives did confirm the first product draws less than 7 watts (2mW standby) and is destined for fanless devices but wouldn't elaborate further.

The package measures 12x12x1mm, but Intel isn't disclosing the measurements of the dies. Stacking small dies should be relatively simple compared to stacking larger dies, but Intel seems confident in its ability to bring the technology to larger processors. Ravishankar Kuppuswamy, Vice President & General Manager of Intel's Programmable Solutions Group, announced that the company is already developing a new FPGA using the Foveros technology. Kuppuswamy claims Foveros technology will enable up to two orders of magnitude performance improvement over the Falcon Mesa FPGAs.

Intel Xe Discrete Graphics and Gen11 Graphics

Intel also unveiled its new Gen11 integrated graphics engine and presented a demo of Tekken 4 playing amazingly well using the new graphics architecture. The demo ran on a 10nm processor, marking the company's first public demo of a graphics engine running on a 10nm processor.

Intel cautioned that the diagrams it used for the presentation aren't entirely to scale, but they do give us a close look under the hood of the new graphics engine. The Gen11 engineering team focused heavily on creating a dramatic performance improvement over its previous-gen graphics engine, stating that the goal was to cram 1 teraflop of 32-bit and 2 teraflops of 16-bit floating point performance into a low power envelope.

Intel employed the familiar modular arrangement with sub-slices that house eight execution units (EU). Intel brought the design up to eight sub-slices, or 64 execution units (EUs). That's a big improvement from Gen9's 24 EUs. The revamped engine also processes two pixels per clock.

The new design features support for tile-based rendering in addition to immediate mode rendering, which helps to reduce memory demands during some rendering workloads. The engineers also improved the memory subsystem by quadrupling the L3 cache to 3MB and separated the shared local memory to promote parallelism. The new design also has enhanced memory compression algorithms.

Other improvements include a new HEVC Quick Sync Video engine that provides up to a 30% bitrate reduction over Gen9 (at the same or better visual quality), support for multiple 4K and 8K video streams within a lower power envelope, and support for Adaptive Sync technology. 

Intel Xe Graphics Technology, Now Including a Discrete GPU

Intel shocked the enthusiast community earlier this year when it announced that it would enter the discrete graphics market. Intel is quick to remind us that it "lights up quintillions of pixels across the planet every day," which is a true statement based on the fact that, courtesy of its integrated graphics chips in its CPUs, Intel is the world's largest GPU producer. Now the company is bringing that experience to the discrete GPU market, and yes, that means it is bringing gaming-focused GPUs to market.

Translating that experience in integrated graphics to its new lineup of discrete GPUs isn't going to be an easy task: Their last successful entry into the GPU space occurred 25 years ago. But Intel has an IP war chest (at one point it owned more graphics patents than the other vendors combined) and has been on a full-court press recruiting the right talent for the task.

Intel presented a slide outlining its new Xe architecture that will come after the Gen11 graphics engine. Intel says the next generation of its graphics architecture will denote a transition from the "Gen" naming convention and will scale from integrated on-chip graphics up to discrete GPUs that will span the mid-range, enthusiast, and data center markets. That means it will scale from teraflops of performance integrated into a standard processor up to petaflops of performance with discrete cards.

This announcement certainly hints that both the integrated graphics and discrete cards will share the same underlying architecture, but Intel wouldn't answer further questions. Intel is also on track to deliver on its previously-announced timeline, saying the Xe graphics cards will debut in 2020.

CPU Core Roadmap, Sunny Cove Microarchitecture, 10nm Ice Lake

Intel also took the wraps off its new CPU core roadmap and "Sunny Cove" microarchitecture at the event. The company's dominance in the chip market has long been predicated on process and microarchitecture leadership, but Intel's approach to designing new processor cores has been inextricably tied to its onward march to smaller process nodes. That means that its new CPU core designs (microarchitectures) have traditionally required a move to new, smaller manufacturing processes.

That approach became a liability as Intel encountered massive delays with its 10nm process. Instead of bringing out new core designs, the company was mired on the 14nm process for four years as it constantly refined the process through a cadence of "+" iterations. Each new iteration of the 14nm process found the company offering higher frequencies, and thus more performance, as it marched from 4.2 GHz up to 5.1 GHz. These improvements delivered up to 70% more performance since 14nm's debut in 2014, but the lack of a new microarchitecture, which typically improves the processors' instruction per clock (IPC) throughput, slowed its progress.

After learning a hard lesson exacerbated by the resurgent AMD nipping at its heels, Intel tells us that the company will now design new microarchitectures to be portable between nodes. That will allow the company to move forward even if it encounters roadblocks on its path to smaller transistors.

The Sunny Cove microarchitecture is the first new design that can be used on multiple nodes, and even though Intel has stated the new core will debut on the 10nm node, it hasn't verified that it will come with the Ice Lake chips. In line with its new design ethos, Intel also tells us that it will select different nodes for different products based on the needs of the segment. That's similar to the approach taken by third-party fabs like TSMC and Global Foundries, and it means Intel could choose to use Sunny Cove with 14nm processors as well.

Intel's CPU Core Roadmap

Intel has typically used the same naming convention for its microarchitectures as it does for its processors. Hence, Skylake processors came with the Skylake architecture, and Kaby Lake processors came packing the Kaby Lake architecture. That old paradigm changes now that Intel has decoupled its architectures from the end products, so the company debuted a new roadmap specifically for CPU cores.

Intel presented its new roadmap for both its Core and Atom lineups. As usual, the Core series addresses the company's bread-and-butter high-performance chips, while the Atom chips serve the low power segment.

Intel's Sunny Cove will debut in 2019, bringing with it higher performance in single-threaded applications, a new instruction set architecture (ISA), and a design geared for scalability. Willow Cove will follow with an improved cache hierarchy, security features, and transistor optimizations. The Golden Cove microarchitecture will debut in 2021 with a focus on yet more single-threaded performance, AI performance, networking improvements, and new security features. Atom will receive a slower cadence of improvements, with Tremont debuting in 2019 and Gracemont in 2021. 'Next' Mont will arrive before 2023.

Intel plans for general performance improvements through three key design tenets of going deeper, wider, and smarter, but it is also improving what it calls 'special purpose' use cases, like AI, cryptography, and compression/decompression workloads.

A Refresh On Skylake (Refresh)

Intel presented us a quick refresh on its Skylake architecture that underpins its Skylake, Kaby Lake, Coffee Lake, and Cascade Lake processors. The design (left) processes operations through two reservation stations (RS). It can process seven operations simultaneously and propel them to the integer (INT), vector (VEC), store data, and address generation units (AGU).

Deeper

The new Sunny Cove design features improvements in every level of the pipeline. Key improvements to the front end include larger reorder, load, and store buffers, along with larger reservation stations. This allows the processor to look deeper into the set of incoming instructions to find operations that are independent of each other but can run simultaneously. The operations are then executed in parallel to improve IPC.

Intel increased the L1 data cache from 32KB, the same capacity it has used in its chips for a decade, to 42KB. The L2 cache is also larger, but the capacity is dependent upon each specific type of product, such as chips designed for either the desktop or server market. Intel also expanded the micro-op cache (UOP) and the second-level translation lookaside buffer (TLB).

Wider

A key facet of improving performance is to increase parallelism. That starts with the deeper buffer and reservation stations we covered above, but it also requires more execution units to process the operations.

Intel moved from a four-wide allocation to five-wide to allow the in-order portion of the pipeline (front end) to feed the out-of-order (back end) portion faster. Intel also increased the number of execution units to handle ten operations per cycle (up from eight with Skylake). The Store Data unit can now process two store data operations for every cycle (up from one). The address generation units (AGU) can now also handle two loads and two stores every cycle. These improvements are necessary to match the increased bandwidth from the larger L1 data cache, which now does two reads and two writes every cycle. Intel also tweaked the design of the sub-blocks in the execution units to enable data shuffles within the registers.

Smarter

Intel reiterated that just increasing the size of the buffers and the number of execution units requires smart algorithmic management to strike a balance between performance and the power budget. That revolves around improving branch prediction accuracy and reducing latency under load conditions. The net effect is a 'significant' increase in IPC. Intel didn't provide specific measurements. but promises to share more information as products come to market. 

Specialization

Intel also designed Sunny Cove to address specific use cases, like cryptography, AI, and compression/decompression workloads. The company accomplished these goals by creating new instructions and features to improve performance.

Exploding Memory Capacity

Intel also improved the amount of memory the processor can address, which is a key consideration given its goal of boosting memory capacity with Optane DC Persistent Memory DIMMs. The speedy Optane memory modules provide up to 512GB of memory-addressable storage per DIMM, meaning memory capacity is set to explode as more data centers transition to the technology.

Intel's Sunny Cove moves to a five-level paging structure (up from a four-level structure). That increases the virtual address space up to 57 bits and the physical address space up to 52 bits, meaning it supports up to 4 petabytes of memory. That's up from 64 TB of addressing capability with Skylake.

Intel's New Course with OneAPI

Intel's Sunny Cove is an innovative design that looks promising, but as with all designs, we won't know the true benefits until we see the silicon in our labs. Intel's new vision to decouple its CPU core designs from its process improvements is the real advance that will help the company remain competitive in the future. Intel surely can't afford another period of stagnation like we've seen during its struggles with the 10nm process.

Third-party fabs have proven to be Intel's greatest competitor. TSMC has taken the process lead with its pending 7nm node, and as a result, new 7nm chips will soon flow from the stalwarts of the semiconductor space, like AMD, Apple, Qualcomm, and Nvidia. These companies work together with TSMC to bring their new designs to market, meaning that Intel isn't just competing with one company -- it faces the combined might of several of the behemoths in the chip market.

Intel does have a plan to outmaneuver its rivals by leveraging its wide-ranging product stack, but it surprisingly revolves around software. Intel is working on its new "One API" software, which is designed to simplify programming across its GPU, CPU, FPGA, and AI accelerators. The software goes by the tagline of "no transistor left behind," and given its goals, that's an accurate statement. The new software provides unified libraries that will allow for applications to move seamlessly between Intel's different types of compute. If successful, this could be a key differentiator that other firms will not be able to match with as many forms of compute.

10nm Ice Lake

The company does have its own plans for its resurgence on the process front, though, as evidenced by the brief display of its 10nm Ice Lake data center chip. The company didn't share any details about the new processor.

Questions And Answers

Intel has been notoriously silent on its roadmap and future plans, but its Architecture Day event seems to signal a new level of openness and disclosure from the company. Several executives from Intel's executive management team were present for the event and were willing to answer our questions openly and frankly. The company also plans to hold future events to drill down more on these topics as it comes closer to delivering products to market. 

Intel held roundtable discussions at the event, where Raja Koduri (R) and Jim Keller (J), and Dr. Murthy Renduchintala (M) fielded questions during the last session. Here are some of the questions and answers:

Q: A lot of the CPU microarchitecture at Intel has been hamstrung by delays on process node technology. What went wrong, and what steps have been made to make sure it doesn't happen again?

R/J: Our products will be decoupled from our transistor capability. We have incredible IP at Intel, but it was all sitting in the 10nm process node. If we had had it on 14nm then we would have better performance on 14nm. We have a new method inside the company to decouple IP from the process technology. You must remember that customers buy the product, not a transistor family. It’s the same transformation AMD had to go through to change the design methodology when they were struggling. At Apple it was called the ‘bus’ method.

M: This is a function of how we as a company used to think about process node technologies. It was a frame tick (limiting factor) for how the company moved forward. We've learned a lot about how this worked with 14nm. We now have to make sure that our IP is not node-locked. The ability to have portability of IP across multiple nodes is great for contingency planning. We will continue to take aggressive risks in our designs, but we also will have contingency. We need to have as much of a seamless roadmap as possible in case those contingencies are needed, and need to make sure they are executed on ASAP if needed to keep the customer expectations in line. You will see future node technologies, such as 10/7, have much more overlap than before to keep the designs fluid. Our product portfolio on 14nm could have been much better if our product designs were not node-locked to 10nm.

R: In the future there will be no transistor left behind, no customer left behind, and no IP left behind.

Q: Will we ever see a 10nm monolithic desktop CPU at the high end?

R: Yes.

Q: How is 10nm? Has it changed?

R: It is changing, but it hasn't changed. There are a lot of lessons learned in how Intel approached it to begin with. We are established a much better model between manufacturing and design. We want good abstractions in product and process node going forward. When everything was going well, this issue didn't manifest and so wasn't an issue. There's complexity here when something bad happens on process, so the whole pipeline clogs up -- the rest of the world solves this with abstraction. We need to make sure it won't happen again, and we have a desire to build resilience in the roadmap.

Q: Are there plans for mixed SoCs, combining CPU / GPU / AI / FPGA ?

R: In our roadmap there will be scalable vector/matrix combinations. What our customers want are very scalable solutions. Customers want similar programming models regardless of the silicon.

Q: What has been the effect of hiring Raja/Jim and bringing outsiders to Intel?

M: Intel is very innovative. We want to add to that chemistry and make sure we bring in people who understand Intel but also bring in good ideas. It's about respecting the rest of the market and make sure Intel is competitive. It's balancing the center of internal debates by making sure we are challenging internal beliefs and the status quo by bringing in people who have done this sort of thing before. It shows to Intel's strengths in its ability to absorb interesting ideas from the outside. We went for the very best on the outside because that was what required to join with the very best on inside.

Q: What is Intel’s current approach to 5G, given the topics discussed today?

M: We think about 5G from the datacenter to the network to the edge and to the device. We at Intel believe the transition to 5G and its implications on the network, in terms of accelerating data and catalyzing a software-defined network where bespoke silicon gets replaced by containers, is as transformative as the jump from analogue to digital. It will accelerate the "cloudification" of the network. The edge is important, especially to minimize latency for new services. Sub-millisecond latency for these services is critical. The over-the-air interface is important too. The intelligent cloud domain is going to be the flywheel about how fast the industry evolves. We mentioned in November that our XMM 5G modem will be in the hands of partners in the second half of 2019 with products in early 2020. It is a multi-mode 5G LTE architecture from day one, supporting all 3 mmWave bands, and sub-6 GHz frequencies.

Q: As Thunderbolt 3 requires additional chips, how do you see future OEM adoption?

M: Integrated Type-C Thunderbolt 3 is the first generation. We will refine it in the future - that's the natural genealogy of the technology. We constantly think about how much we integrate into the chip and how much we leave on the board.

R: This is a big IP challenge, not only for TB3, but for other IP. Integrated PHYs are important. For example, by dis-aggregating the transceiver in our FPGA lineup, it has allowed us to focus on that decoupled IP a lot.

Q: In the demo of FOVEROS, the chip combined both big x86 cores built on the Core microarchitecture and the small x86 cores built on the Atom microarchitecture. Can we look forward to a future where the big and little cores have the same ISA?

R: We are working on that. Do they have to have the same ISA? Ronak and the team are looking at that. However I think our goal here is to keep the software as simple as possible for developers and customers. It's a challenge that our architects have taken up to ensure products like this enter the market smoothly. We’ll also have a packaging discussion next year on products like this. The chip you see today, while it was designed primarily for a particular customer to begin with, it’s not a custom product, and in that sense will be available to other OEMs.

M: We've made the first step on a journey. That first step is a leap, and the next step is incremental. As we've said about One API strategy – if we homogenize the API then it'll go into all our CPUs. Foveros is also a new part/product that shows that we had a gap in our portfolio – it has helped us create technologies to solve an issue and we expect to expand on this in the future with new IP.

Q: Are you having fun with Foveros?

J: Because Raja deals in GPUs, he’s having fun with high bandwidth communications between compute elements. It's a new technology and we're having some experimentation with it. What is frustrating is that as an industry we hit a limit for current flux density a year before stacking technology became viable, so for high performance on stacking we're trying a lot of things in different areas. There's no point having to make thermal setbacks if it also removes the reason why you're using the technology. But we're having fun and trying a lot, and we'll see Foveros in a number of parts over the next 5 years. We will find new solutions to problems we don't even know exist yet.

Q: When is Manufacturing Tech Day?

M: We will tell you when it happens! I'm sure you all have opinions on Intel 10nm right now and yes we are looking at what we're doing, eating an amount of humble pie, but we're re-adjusting our process to make sure that we can take the best process no matter what the product is.

Intel has announced a new version of its integrated graphics driver that supports Blizzard Entertainment’s highly anticipated World of Warcraft expansion, Battle for Azeroth.

The new driver, version 24.20.100.6226, adds support for the new MMORPG (massively multiplayer online role-playing game) title, and Intel stated that players looking to dive into the World of Warcraft expansion are required to download the updated software. Intel even created a dedicated site to help gamers optimize their settings for Battle for Azeroth, but the tool still seems to be under construction at the time of this writing (all of our CPU searches resulted in “Coming Soon” pages). Presumably, the recommended settings will be there when the game launches on August 14.

The driver also comes loaded with game optimizations for Battle for Azeroth, in addition to Yakuza 0, Ys: Memories of Celceta, StoneHearth, Adventure Time: Pirates of the Enchiridion, The Walking Dead: The Final Season, This Is the Police 2 and Overcooked 2 with Intel UHD 620 Graphics or better. Other features include visual improvements with Dell HDR displays and various security and bug fixes.

Although an integrated graphics solution may not provide the best details and framerates for PC gaming (or Battle For Azeroth in particular), it’s interesting to see Intel increasing its focus on its graphics driver releases. With the company’s acquisition of former AMD graphics architect Raja Koduri and, with him, a rededication to entering the dedicated graphics market, Intel appears to be gearing up for a battle of its own against the likes of AMD and Nvidia, and it already seems to be keeping up with the pack with its game-ready graphics driver releases.

You can download the new Intel graphics driver from the company’s website.

Intel has added another famous player to its discrete-graphics dream team. Chris Hook, who recently left AMD after 17 years leading the company's global marketing efforts, announced via his Facebook page that he has joined Intel (statement below). His arrival fuels speculation that the CPU maker will be coming out with its own line of gaming GPUs to compete with Nvidia and AMD.

Hook will lead Intel's marketing for visual technologies and discrete graphics products. As such, Hook appears to be Intel's first dedicated marketer for discrete graphics cards. Hook joins ex-AMD'ers Raja Koduri, who is leading Intel's graphics design teams, and Jim Keller, who joined Intel last week to head up its silicon engineering.  

Intel's re-entry into the discrete graphics card market came as shocking news earlier this year. Intel has made two prior attempts to bring a discrete gaming GPU to market, but it eventually shuttered both programs. The chip-maker hasn't confirmed that it will target the gaming market with its new products, instead saying the GPUs are designed for "a broad range of computing segments.”

Given Hook's history, his hire will certainly fuel speculation that Intel is developing gaming GPUs, which would make sense from a broader perspective. 

Intel is focusing on increasing sales in its "data-centric" businesses, which doesn't include desktop PCs. Overall, those segments accounted for 46 percent of Intel's revenue last quarter, with the high-margin Data Center Group leading the charge. The data center is rapidly transitioning to AI-heavy workloads due to power efficiency and performance gains, and GPUs are used for a broad range of those workloads.

Intel has multiple products for AI workloads, but data centers use GPUs for many of those same tasks. For example, Nvidia claims it can replace up to 300 Xeon processors, which consume 15 racks of space, with a single DXG-2 server. That certainly threatens to chip away at Intel's Xeon sales, so developing GPUs for the data center is a no-brainer.

Much like Nvidia does with its GPUs and Intel does with its desktop CPUs, sales to the broader desktop PC market drive up production volume and build the economy of scale that lowers costs. In turn, that assures low pricing and high margins. Intel will likely need to build GPU production volume in the PC market to compete with Nvidia's pricing, so we doubt that Intel will reinvent the wheel with its production model.

Intel's maneuvering comes after it has made some structural changes to its hierarchy, which is likely to deal with production challenges with the 10nm process. The company is obviously bringing in some of the industry's top guns to expand into GPUs at the same time, which is a smart tactic. It's helpful to have experienced hands at the helm when you're testing new waters.

We're sure to learn more about Intel's future discrete graphics cards in the coming months. Here is Hook's statement (via Facebook):

Friends, I’m exhilarated and energized to be starting a new marketing leadership role at Intel in Santa Clara, CA.Intel is a company I’ve long admired and is without a doubt the finest silicon engineering company in the world. It also has a rich history of processor innovation dating back to the Intel 4004, which was released the year I was born. It has an equally rich history in marketing innovation, having succeeded what was once the unthinkable - turning what started as an unassuming 16-pin black ceramic integrated circuit into a household name and notable consumer brand.As many of you know, it was recently announced that Intel is embarking on a journey to expand its leading position in integrated graphics for PC with high-end discrete graphics solutions for a broad range of computing segments, and will be growing its technology portfolio across computing, graphics, media, imaging and machine intelligence for clients and data centers, AI, and edge computing.That’s a pretty exciting journey, and one I personally want to be part of. So starting tomorrow, I’ll be assuming a new role in which I’ll be driving the marketing strategy for visual technologies and upcoming discrete graphics products.I’m also excited to meet the Intel team. The folks I’ve met there so far are the best in the world at what they do; they’re laser-smart and driven to win. And there are also a few good Intel folks that I’ve had the privilege of working with in the past at AMD, world-class engineering leaders Ari Rauch, Raja Koduri and Jim Keller, who at multiple points in their careers have architected and engineered some of the most respected software and silicon in history.So here’s to the future – one with competition, choice and incredible technology.Cheers,Chris

Raja Koduri's departure from AMD was one of the most surprising stories of 2017, but largely because he left AMD for rival Intel. Now AMD has appointed two new graphics industry veterans to run the Radeon Technologies Group (RTG).

Earlier this year, Intel and AMD announced that AMD's Radeon Graphics were worming their way into Intel's eighth-generation H-Series processors. A day later, Raja Koduri, AMD's former senior vice president and chief architect of the RTG, announced he had left the company. Twenty-four hours after that, Intel announced that it had brought on Koduri to head its newly formed Core and Visual Computing Group business unit with the intention of developing high-end discrete graphics cards for a "broad range of computing segments."

AMD CEO Dr. Lisa Su took the RTG helm after Koduri's departure, but the company announced that it was actively seeking to fill Koduri's role. Now AMD has selected two industry veterans to lead RTG. AMD has also folded its semi-custom business unit into RTG because of its heavy reliance upon graphics IP. AMD representatives told us that the RTG restructuring means the new executives are not a one-to-one replacement for Koduri. Mike Rayfield is now the senior vice president and general manager, and David Wang is now the senior vice president of engineering. The two executives will report directly to Su, who will no longer handle the day-to-day business of RTG.

“Mike and David are industry leaders who bring proven track records of delivering profitable business growth and leadership product roadmaps,” said Su. “We enter 2018 with incredible momentum for our graphics business based on the full set of GPU products we introduced last year for the consumer, professional, and machine learning markets. Under Mike and David’s leadership, I am confident we will continue to grow the footprint of Radeon across the gaming, immersive, and GPU compute markets.”

Rayfield has 30 years of experience in the industry with extended tenure at Micron as the senior vice president and general manager of the Mobile Business Unit and as general manager of the Mobile Business Unit at Nvidia. Rayfield was in charge of the team that developed Nvidia's Tegra.

Rayfield will be responsible for strategy and business management for consumer and professional graphics. He will also serve in the same role for the semi-custom business.

David Wang most recently hails from Synaptics, where he was senior vice president of Systems Silicon Engineering. Wang also previously served as corporate vice president at AMD, where he was responsible for SoC development for AMD's processors, including GPUs, CPUs, and APUs. Wang has a rich history with AMD, beginning with ArtX and ATI, where he helped develop several game consoles along with every generation of GPU from the R3000 series to the HD 7000. Wang has a storied 25-year career in the industry that also includes time at SGI, Axil Workstations, and LSI Logic.

The Challenge Ahead

Due to the mining boom, AMD's Vega GPUs are selling as fast as the company can manufacture them. However, many in the enthusiast community were underwhelmed by AMD's latest graphics cards, and Nvidia still holds the performance crown. Nvidia's performance lead is a prime contributor to its much larger market share, so AMD will need a more competitive graphics architecture to expand beyond its current 30% share.

Nvidia also has a dominant lead in the data center with its Tesla Volta GV100 GPUs. The explosion of ML/AI in the data center is a catalyst for massive expansion, so this segment represents the biggest predictable growth and margin opportunity for both Nvidia and AMD. The most important revenue battles will undoubtedly be won and lost in the data centers.

Nvidia may be the big fish in both client and data center graphics, but Intel has also recently begun to develop its own discrete graphics cards. That poses yet another threat to AMD's market share. Intel will likely target the low-to-mid range of the desktop graphics market first, which poses more of a threat to AMD than Nvidia. The blue team will also undoubtedly try to press the advantage of its overwhelming presence in the data center to sell its graphics products. That adds yet another player with deep pockets that AMD has to contend with.

Finally, AMD recently unveiled its GPU roadmap at its pre-CES event. The roadmap transitions from the 14nm Vega directly to the 7nm Vega architecture, which is a big surprise. AMD had expressed its intentions to shift both its CPUs and GPUs to the 12nm process in 2018, which AMD CTO Mark Papermaster confirmed to us directly. The lack of a 12nm GPU in AMD's roadmap undoubtedly raises questions.

All of these factors mean that RTG needs experienced leadership that can grapple with Nvidia and the looming threat of Intel while steering development of Navi and the next-generation graphics architecture.

AMD also moved the semi-custom business into RTG, which means it removed the unit from the Enterprise, Embedded and Semi-Custom group. AMD's Semi-Custom unit isn't know for high margins, but it is thriving, as evidenced by Intel as a new customer and the long-time Sony and Microsoft game console business. The move also expands upon AMD's "Radeon Everywhere" initiative as it pushes further into the embedded graphics space.

AMD representatives also told us the Semi-Custom group has other new unannounced customers and projects, but it did not elaborate further. We debunked the initial rumors that Tesla was working directly with Global Foundries for AI chips, but that is actually good news for AMD. We suspect that Tesla is one of AMD's unannounced Semi-Custom customers, as Elon Musk recently commented at an industry party that the company is working with AMD to develop its own custom AI processors. It also helps that Jim Keller, formerly the chief architect for AMD's microprocessors, is now VP of autopilot hardware at Tesla.

It's tempting to say that it takes two industry veterans to fill Koduri's shoes, but now RTG has more responsibilities because it absorbed the Semi-Custom group. AMD representatives are quite emphatic that this move represents an increase in investment in the RTG unit and that two leaders will help boost its efforts. That's welcome news as the company has already made amazing inroads with its Ryzen processors and has strong momentum in the data center. Adding a more competitive RTG to the mix would obviously help further its other initiatives, such as the budding Radeon Instinct lineup.

We're sure to learn more details of the restructuring in AMD's financial report later this month.

AMD has confirmed that Raja Koduri, head of AMD's Radeon Technologies Group is leaving the company. For now, Lisa Su, AMD's CEO will run RTG until a replacement is found.

Hexus.net first broke the news by publishing an internal AMD memo, purportedly drafted by Koduri. In it, Koduri said goodbye to the Radeon Technologies Group team members. Although AMD would not confirm the authenticity of an internal memo, sources close to the matter tell us that it is indeed the real deal.

The full internal memo reads:

“To my AMD family,Forty is a significant number in history. It is a number representing transition, testing and change. I have just spent forty days away from the office going through such a transition. It was an important time with my family, and it also offered me a rare space for reflection. During this time I have come to the extremely difficult conclusion that it is time for me to leave RTG and AMD.I have no question in my mind that RTG, and AMD, are marching firmly in the right direction as high-performance computing becomes ever-more-important in every aspect of our lives. I believe wholeheartedly in what we are doing with Vega, Navi and beyond, and I am incredibly proud of how far we have come and where we are going. The whole industry has stood up and taken notice of what we are doing. As I think about how computing will evolve, I feel more and more that I want to pursue my passion beyond hardware and explore driving broader solutions.I want to thank Lisa and the AET for enabling me to pursue my passion during the last four years at AMD, and especially the last two years with RTG. Lisa has my utmost respect for exhibiting the courage to enable me with RTG, for believing in me and for going out of her way to support me. I would also like to call out Mark Papermaster who brought me into AMD, for his huge passion for technology and for his relentless support through many difficult phases. And of course, I want to thank each and every one of my direct staff and my indirect staff who have worked so hard with me to build what we have now got. I am very proud of the strong leaders we have and I'm fully confident that they can execute on the compelling roadmap ahead. I will continue to be an ardent fan and user of AMD technologies for both personal and professional use.As I mentioned, leaving AMD and RTG has been an extremely difficult decision for me. But I felt it is the right one for me personally at this point. Time will tell. I will be following with great interest the progress you will make over the next several years.On a final note, I have asked a lot of you in the last two years. You've always delivered. You've made me successful both personally and professionally, for which I thank you all from the bottom of my heart. I have these final requests from you as I leave:. Stay focused on the roadmap!. Deliver on your commitments!. Continue the culture of Passion, Persistence and Play!. Make AMD proud!. Make me proud!Yours,Raja”

We reached out to AMD's Drew Prairie (corporate communications) for comment. His full statement reads:

"Earlier today, we announced two unrelated updates for our Radeon Technologies Group: 1) Raja Koduri has decided to leave AMD and 2) we are taking the next steps in our work to strengthen RTG by further focusing the organization on key growth areas. I wanted to also make sure you understood these updates do not impact our plans or the strategic direction we are driving our graphics business. We appreciate the contributions Raja has made helping establish our dedicated graphics focus and strong team that is capable of accomplishing the ambitious goals we have set for this part of our business. Also want to make sure it is clear that there are no changes to our public product or technology graphics roadmaps, and we remain on track to deliver on our commitments in 2018 and beyond. Lisa will continue to lead RTG on an interim basis while we complete our search for a new leader. We have made significant progress across AMD these past two years delivering the first wave of our high-performance products, best exemplified by our improved financial performance and year-over-year market share gains across all of our client, graphics and server products. Today’s changes are designed to allow us to better take advantage of the significant growth opportunities in front of us."

AMD created Radeon Technologies Group in 2015, and heads turned when it was announced that he would be taking a leave of absence from AMD shortly after the anticipated debut of Radeon Vega graphics cards. Koduri indicated that he would return in December, but now it is apparent the AMD figurehead will no longer be at the RTG helm.

Raja's Legacy

During his time as the head of RTG, Raja Koduri and his team set a fast pace for AMD, creating the roadmap for the GPU that would come to be known as Vega. Some have speculated that Radeon RX Vega 56 was the catalyst to Nvidia's GeForce GTX 1070 Ti.

The roadmap AMD recently shared at its financial analyst day in May takes RTG past two versions of Vega, to Navi (on 7nm), and then "Next Gen" by 2020. All of this while AMD has also been hyper-focused on becoming competitive in the CPU marketplace with Ryzen and Threadripper.

Only yesterday, AMD announced a semi-custom GPU for an upcoming Intel multi-chip package for mobile PCs, yet another surprising feather for Koduri's cap, and perhaps a fitting end to his tenure at AMD.

At the Global Foundries Technology Conference, AMD’s CTO Mark Papermaster announced that the company will be transitioning “graphics and client products” from the Global Foundries 14nm LPP FinFET process it uses today to the new 12nm LP process in 2018. Global Foundries also announced that 12LP will begin production in 1Q18.

We followed up with Papermaster in person and confirmed directly that the company will transition both Vega GPUs and the Ryzen line of processors to the 12nm LP process. However, it’s still not clear whether or not he meant that 12nm LP will be a shrink of Ryzen in 2018 (a "tick" equivalent if you will) or if Zen+/Zen 2 will also be using the 12LP process. Previously, AMD has implied that Zen 2 will use the 7nm process. The company has used both "Zen+" and "Zen 2" to refer to its next-generation die.

We expected AMD's next-generation 7nm Zen products to slug it out with Intel's 10nm Ice Lake processors next year, but it appears we will see 12nm LP against Intel's 10nm instead.

Earlier, we learned from Raja Koduri's letter to his team that we should expect "new wave of product excitement" in early 2018, which implies that is when we might see the first news of Vega with the 12nm LP process to emerge.

Nvidia’s Volta architecture is already shipping on TSMC’s 12nm FFN process this year, so on the GPU side Nvidia seems to be ahead on adopting new process technology right now. Of course, on the CPU side we also have Intel, which promised “real” 10nm chips for next year that should also be significantly ahead in performance and power efficiency compared to the 12LP process.

However, this is nothing really new, as Intel has been ahead in process technology for quite some time, and if anything, third-party foundry companies such as Samsung/Global Foundries and TSMC have closed the gap a little once they adopted the FinFET structure for their transistors. AMD's relatively quick transition to the 12nm LP processor is vital for the company as it seeks to compete with Intel's Coffee Lake processors and Nvidia's Volta GPUs.

MORE: Everything Zen: AMD Presents New Microarchitecture At Hot Chips

The transition to 12nm LP also reaffirms AMD's commitment to its partnership with Global Foundries. The companies signed a five-year wafer supply agreement recently, but there has been speculation that AMD might seek other partners for its forthcoming product generations.

We're digging in deeper for more information and will follow up as required.

Raja Koduri, AMD's senior vice president and chief architect of the AMD Radeon Technologies Group (RTG), has announced that he is taking leave for through the fourth quarter of this year. Koduri recently went on "radio silence" immediately following the launch of the company's Vega lineup, which spawned a rash of theories on Reddit and enthusiast forums.

AMD's RTG group has faced quite a bit of criticism following the Vega launch, largely due to pricing and shortages, and the lack of a cohesive response from the company has been a bit frustrating for the enthusiast community. Many in the enthusiast community attributed Koduri's absence to the delayed AMD response. Koduri later responded with a series of tweets explaining that he was attending a wedding in India. He also addressed many of the questions raised by the community. 

Last night, TweakTown reported that Koduri had taken leave through the end of the fourth quarter, which was later confirmed by PC Perspective. PC Perspective also got its mitts on Koduri's internal letter to his team outlining his reasons for taking leave, which you can find below.

AMD CEO Dr. Lisa Su will step into Koduri's role during his absence, so it's obvious that RTG is in good hands. As noted in his letter, Koduri will return in December. Notably, Koduri cites a "new wave of product excitement" in early 2018 as one of the key reasons for the timing of his extended vacation, so we might have something to look forward to early next year.

Here's the full text from Koduri's memo:

RTG Team, You haven’t heard from me collectively in a while – a symptom not only of the whirlwind of launching Vega, but simply of the huge number of demands on my time since the formation of RTG. Looking back over this short period, it is an impressive view. We have delivered 6 straight quarters of double-digit growth in graphics, culminating in the launch of Vega and being back in high-performance. What we have done with Vega is unparalleled. We entered the high-end gaming, professional workstation and machine intelligence markets with Vega in a very short period of time. The demand for Vega (and Polaris!) is fantastic, and overall momentum for our graphics is strong. Incredibly, we as AMD also managed to spectacularly re-enter the high-performance CPU segments this year. We are all exceptionally proud of Ryzen, Epyc and Threadripper. The computing world is not the same anymore and the whole world is cheering for AMD. Congratulations and thanks to those of you in RTG who helped see these products through. The market for high-performance computing is on an explosive growth trajectory driven by machine intelligence, visual cloud, blockchain and other exciting new workloads. Our vision of immersive and instinctive computing is within grasp. As we enter 2018, I will be shifting my focus more toward architecting and realizing this vision and rebalancing my operational responsibilities. At the beginning of the year I warned that Vega would be hard. At the time, some folks didn’t believe me. Now many of you understand what I said. Vega was indeed hard on many, and my sincere heartfelt thanks to all of you who endured the Vega journey with me. Vega was personally hard on me as well and I used up a lot of family credits during this journey. I have decided to take a time-off in Q4 to spend time with my family. I have been contemplating this for a while now and there was never a good time to do this. Lisa and I agreed that Q4 is better than 2018, before the next wave of product excitement. Lisa will be acting as the leader of RTG during by absence. My sincere thanks to Lisa and rest of AET for supporting me in this decision and agreeing to take on additional workload during my absence. I am looking to start my time-off on Sept 25th and return in December. Thank you, all of you, for your unwavering focus, dedication and support over these past months, and for helping us to build something incredible. We are not done yet, and keep the momentum going! Regards, Raja

AMD gathered press and partners late last year to talk about a hectic 2017 roadmap that includes Ryzen for the desktop in Q1; FreeSync 2, new server and laptop platforms launching later in the year; a big push into machine learning; and of course Vega, the hotly-anticipated successor to its third-generation Graphics Core Next (GCN) design.

Let’s cut right to it: Products based on AMD’s high-end Vega GPU architecture aren’t ready yet, but they’re expected sometime between now and the end of June.

In the meantime, AMD is milking this one for all it’s worth. We have early details that the company is willing to disclose, plus a promise that there will be a lower-level tech day closer to Vega’s launch. So let’s dig in (as far as we’re able to go).

Raja Koduri, senior vice president and chief architect of the Radeon Technologies Group, stood onstage at AMD’s Tech Summit and excitedly held up a newborn Vega-based GPU, making a point of the 200+ changes that went into creating Vega. This may be a revision to GCN, but AMD clearly wants the world to consider it a fresh endeavor. Any why not? As DirectX 12-based games surface with increasing frequency, the architecture’s previously under-utilized strengths become more apparent. Match-ups that previously favored Nvidia under DX11 are more commonly turning up even or going the other way in DX12. Despite all of those modifications, though, Koduri narrowed his presentation down to just four main points.

A Scalable Memory Architecture Based on HBM2

As a lead-in to Vega’s first architectural upgrade, Koduri presented slides showing the rapidly increasing sizes of game installs on desktop PCs, petabyte-class professional graphics workloads, and exabyte-plus training set sizes applicable to machine learning. He also mapped the growth of compute performance versus memory capacity.

Both AMD and Nvidia are working on ways to reduce host processor overhead, maximize throughput to feed the GPU, and circumvent existing bottlenecks—particularly those that surface in the face of voluminous datasets. Getting more capacity closer to the GPU in a fairly cost-effective manner seemed to be the Radeon Pro SSG’s purpose. And Vega appears to take this mission a step further with a more flexible memory hierarchy.

It’s no secret that Vega makes use of HBM 2; that information was on roadmaps through 2016. But we now know that AMD wants to call this pool of on-package memory—previously the frame buffer—a high-bandwidth cache. Got it? HBM2 equals high-bandwidth cache now. Why? Because AMD says so.

No really, why? Well, according to Joe Macri, corporate fellow and product CTO, the vision for HBM was to have it be the highest-performance memory closest to the GPU. However, he also wanted system memory and storage available to the graphics processor, as well. In the context of this broader memory hierarchy, sure, it’s logical to envision HBM2 as a high-bandwidth cache relative to slower technologies. But for the sake of disambiguation, we’re going to continue calling HBM2 what it is.

After all, HBM2 in and of itself represents a significant step forward. An up-to-8x capacity increase per vertical stack, compared to first-gen HBM, addresses questions enthusiasts raised about Radeon R9 Fury X’s longevity. Further, a doubling of bandwidth per pin significantly increases potential throughput. If AMD uses the same 4-hi (four HBM dies) stacks of 700 MHz HBM2 that Nvidia introduced with the Tesla P100 accelerators last year, it would have a 16GB card pushing up to 720GB/s. There’s room for more capacity and bandwidth from there.

That’s the change we expect to have the largest impact on gamers as far as Vega's memory subsystem goes. However, AMD also gives the high-bandwidth cache controller (no longer just the memory controller) access to a massive 512TB virtual address space for those large datasets Raja discussed early in his presentation. Clearly, there’s some overlap between this discussion and the Radeon Instinct lineup AMD announced back in December.

We came away from this presentation with plenty of questions about how the Vega architecture’s broader memory hierarchy will be utilized, but Scott Wasson, senior product marketing manager at AMD, helped add clarity to the discussion by describing some of what the high-bandwidth cache controller can do. According to Wasson, Vega can move memory pages in fine-grained fashion using multiple, programmable techniques. It can receive a request to bring in data and then retrieve it through a DMA transfer while the GPU switches to another thread and continues work without stalling. The controller can go get data on demand but also bring it back in predictively. Information in the HBM can be replicated in system memory like an inclusive cache, or the HBCC can maintain just one copy to save space. All of this is managed in hardware, so it’s expected to be quick and low-overhead.

A New Programmable Geometry Pipeline

The Hawaii GPU (Radeon R9 290X) incorporated some notable improvements over Tahiti (Radeon HD 7970), one of which was a beefier front end with four geometry engines instead of two. The more recent Fiji GPU (Radeon R9 Fury X) maintained that same four-way Shader Engine configuration. However, because it also rolled in goodness from AMD’s third-gen GCN architecture, there were some gains in tessellation throughput, as well. Most recently, the Ellesmere GPU (Radeon RX 480) implemented a handful of techniques for again getting more from a four-engine arrangement, including a filtering algorithm/primitive discard accelerator.

AMD’s backup slides tell us that Vega’s peak geometry throughput is 11 polygons per clock, up from the preceding generations' four, yielding up to a 2.75x boost. That specification comes from using a new primitive shader stage being added to the geometry pipeline. Instead of using the fixed-function hardware, this primitive shader uses the shader array for its work.

Mike Mantor, AMD corporate fellow, described this as having similar access as a compute shader for processing geometry in that it’s lightweight and programmable, with the ability to discard primitives at a high rate. AMD’s Wasson clarified further that the primitive shader’s functionality includes a lot of what the DirectX vertex, hull, domain, and geometry shader stages can do but is more flexible about the context it carries and the order in which work is completed.

The front-end also benefits from an improved workgroup distributor, responsible for load balancing across programmable hardware. AMD said this comes from its collaboration with efficiency-sensitive console developers, and that effort is now going to benefit PC gamers, as well.

The Vega NCU (Next-Generation Compute Unit)

Using its many Pascal-based GPUs, Nvidia is surgical about segmentation. The largest and most expensive GP100 processor offers a peak FP32 rate of 10.6 TFLOPS (if you use the peak GPU Boost frequency). A 1:2 ratio of FP64 cores yields a double-precision rate of 5.3 TFLOPS, and support for half-precision compute/storage enables up to 21.2 TFLOPS. The more consumer-oriented GP102 and GP104 processors naturally offer full-performance FP32 but deliberately handicap FP64 and FP16 rates so you can’t get away with using cheaper cards for scientific or training datasets.

AMD, on the other hand, looks like it’s trying to give more to everyone. The Compute Unit building block, with 64 IEEE 754-2008-compliant shaders, persists, only now it’s being called an NCU, or Next-Generation Compute Unit, reflecting support for new data types. Of course, with 64 shaders and a peak of two floating-point operations/cycle, you end up with a maximum of 128 32-bit ops per clock. Using packed FP16 math, that number turns into 256 16-bit ops per clock. AMD even claimed it can do up to 512 eight-bit ops per clock. Double-precision is a different animal—AMD doesn’t seem to have a problem admitting it sets FP64 rates based on target market.

The impetus for this flexibility may have very well come from the console world. After all, we know Sony’s PlayStation 4 Pro can use half-precision to achieve up to 8.4 TFLOPS—twice its performance using 32-bit operations. Or perhaps it started with AMD’s aspirations in the machine learning space, resulting in products like the upcoming Radeon Instinct MI25 that aim to chip away at Nvidia’s market share. Either way, consoles, datacenters, and PC gamers alike stand to benefit.

AMD claimed the NCUs are optimized for higher clock rates, which isn’t particularly surprising, but it also implemented larger instruction buffers to keep the compute units busy.

A Next-Generation Pixel Engine

The fourth topic of AMD’s early Vega disclosures is actually a two-parter. First up is the draw stream binning rasterizer, attached to the traditional rasterization hardware, which Koduri said is able to improve performance and save power. At a high level, an on-chip bin cache allows the rasterizer to fetch data only once for overlapping primitives, and then shade pixels only once by culling pixels not visible in the final scene.

Second, AMD is fundamentally changing its cache hierarchy by making the render back-ends clients of the L2. In architectures before Vega, AMD had non-coherent pixel and texture memory access, meaning there was no shared point for each pipeline stage to synchronize. In the example of texture baking, where a scene is rendered to a texture for reuse later and then accessed again through the shader array, data has to be pulled all the way back through off-die memory. Now, the architecture has coherent access, which AMD said particularly boosts performance in applications that use deferred shading.

Although much of what Koduri presented requires development effort on the software side to utilize, he still wrapped his slide deck with a demo of Doom running at 4K under its most taxing detail settings on an early Vega board in the 70+ FPS range. Based on the numbers we were seeing in our Titan X review, that’s somewhere in between a GTX 1080 and Titan X.

As AMD's driver team gets its feet wet with Vega, we expect to see those performance numbers increase. We just hope it doesn't take the company another six months to feel comfortable giving us the full story. By then, its principal competition will be over a year old.

The Radeon Technologies group celebrated its one-year anniversary by hosting a conference call to tout its freshman accomplishments, including increased market share; strides in immersive computing and machine intelligence; and its investment in the GPU Open, DirectX 12, and Vulkan communities. However, after a mostly uneventful birthday party, the subject of FreeSync-capable TVs was briefly discussed, with company representatives all but confirming that the variable refresh rate technology would soon be making its way to the living room.

That raised the question: Are consoles about to get FreeSync?

FreeSync is an open-source variable refresh rate technology that matches the refresh rate of the GPU to the display, eliminating screen tearing and other artifacts, making the experience smoother at framerates that would otherwise be considered unenjoyable. The feature is particularly useful with less-powerful GPUs, and it's already available on over 100 different PC displays. However, the current FreeSync screens on the market aren’t sized to be the centerpiece of the living room.

When asked if the company was doing anything specific to get TV manufacturers interested in launching FreeSync-enabled TVs, Sr. Vice President and Chief Architect Raja Koduri gave a mixed-bag reaction that essentially confirms the existence and development of FreeSync TVs:

“We are definitely working with the entire display community on getting FreeSync to more places,” said Koduri, who seemed to hesitate before continuing. “I think this is something we should follow up...on what we can share at this point on FreeSync TVs.”

As the call shifted back to rank-and-file orders of business, our collective spider senses were tingling with the sensation that something big was just mistakenly revealed, so we followed up by reaching out to Radeon. The company has yet to respond.

If this slip of the tongue has any truth to it, FreeSync-enabled televisions could very well be on the way to market in the near future. The inclusion of the variable refresh rate technology in a display suited for the living room could cement AMD as the go-to company for gaming console GPUs, a market in which the company already holds the majority share. The visual benefits of FreeSync could reinvent the typical console experience with smoother gameplay, and it plays into the notion that consoles are quickly becoming more like their PC overlords.

AMD’s Radeon Technology Group held its second Capsaicin event at Siggraph 2016 and revealed a new lineup of affordable workstation GPUs. The company also announced a Radeon that’s probably not so affordable but is far more unbelievable.

Raja Koduri, Radeon Technology Group’s Chief Architect and most senior executive, revealed an incredible new GPU called the Radeon Pro SSG. Koduri suggested that SSG will be a disruptive technology that will change Hollywood film production, and after seeing the company’s live demonstration, we’re inclined to believe that.

Koduri called Radeon Pro SSG technology a “fundamental change in workstation architecture.” The Radeon Pro SSG has an unprecedented 1TB of GPU memory. This massive frame buffer allows the Radeon Pro card to store and work with large data sets locally, rather than relying on transferring the data from system memory to the GPU. AMD said this results in 10x lower memory access latency.

The Radeon Pro SSG is designed to handle the type of workloads you’d find in a Hollywood film production. AMD set up two top level workstations on stage to demonstrate the rendering power of the Radeon PRO SSG live to the audience. Koduri said that each machine featured the fastest workstation components available on the market, including the most powerful CPUs and fastest SSD drives available. One of the workstations was equipped with a Radeon Pro SSG, and the other was not.

AMD showed the workstation without the Radeon Pro SSG rendering a raw 8K video live on stage. The PC was able to render the feed at approximately 17 frames per second, which is pretty respectable for 8K video. The company then switched to the machine with the Radeon Pro SSG inside, which was rendering the footage much quicker.

The Radeon Pro SSG was managing a steady 30Hz, which appeared buttery smooth. Koduri noted that the render was being limited to 30Hz, but it could go much faster. With the limitation disabled, the video render accelerated upwards of 90Hz. Sure, these demos always favor the product being shown, but assuming there are no games being played here, let that 90Hz sink in for a second.

The Radeon Pro SSG appears to be capable of faster-than-real-time rendering of 8K raw footage. The card was rendering 4.5GB/s at that pace. That amount of data processing will also let you scrub through hours 8K video footage in real-time. How’s that for a productivity boost?

AMD said that the hardware is “very early,” but the company is accepting applications for Radeon Pro SSG dev kits immediately.

AMD announced a new line of professional-grade GPUs at Siggraph 2016. The WX series is based on the company’s Polaris architecture and promises to lower the cost of pro-level rendering performance below $1,000.

AMD’s Raja Koduri took to the stage during the Radeon Technologies Capsaicin event at Siggraph 2016 and revealed a whole new lineup of professional-grade workstation GPUs based on the company’s Polaris GPU architecture. Koduri announced the Radeon Pro WX series, which will launch with three affordable products.

The Radeon Pro WX7100 is the top of the WX series. Koduri said that every product that the company releases is designed to fit a specific need. The WX7100 is meant to bring the cost of professional-grade rendering performance down for the entry level. Previously, you’d have to spend over $3,000 to get a Radeon Pro workstation card, but the WX7100 will be available for less than $1,000 and is designed to be ideal for VR content creators.

The Polaris-based workstation card features 32 AMD Compute units delivering upwards of 5TFLOPS of single precision floating point performance. It will include 8GB of GPU memory on a 256bit memory bus.

The WX5100 includes 28 Compute units that deliver more than 4TFLOPS of single precision performance. This card will also feature 8GB of memory on the same 256bit memory bus as the WX7100. AMD said this card is the ideal solution for immersive real-time design and manufacturing with CAD and CAM software.

The third WX series Radeon Pro option is designed for small form factor workstation machines. The WX4100 is a half-height GPU with 16 AMD Compute units and 4GB of memory on 128bit memory bus. The compact card is capable of 2TFLOPS of single precision floating point performance.

All three WX series workstations cards are capable of powering up to four 5K displays through four Display Port 1.3 ports. Each workstation card is cooled by a single-slot blower solution. The WX series will also be covered by an incredible 10-year warranty. AMD is standing by this product in a big way.

You’ll notice that AMD has strayed away from its traditional red color scheme for the new Radeon Pro series. Koduri said that he is very passionate about the color blue (even going so far as to name his daughter "blue" in Sanskrit). After taking control of the Radeon Technologies Group last year, he set on a mission to change the color of the Radeon Pro. The company researched different color pigments and decided on Yinmn Blue for its special properties. Yinmn blue is the only non-toxic blue pigment known to man. The color does not fade, it is highly reflective, and it's highly energy efficient. Koduri said the entire Radeon Pro WX series will be painted in this color.

AMD said that all Radeon Pro GPUs are designed in-house. The company doesn’t allow third party designs so that it can control the quality. AMD also provides 24/7 customer support for Radeon Pro customers.

AMD did not say when the Radeon Pro WX series would be available, but you can sign up to the company’s mailing list to be notified when it's available.

AMD is making some big changes in its graphics business. First it created the Radeon Technologies Group and appointed Raja Koduri as senior vice president and chief architect of the group, and then earlier today, the company launched the first iteration of the Radeon Software Crimson driver package. Radeon Software Crimson has received much media attention, but another announcement was made by AMD today that likely affects more than a few of our readers.

AMD announced that it has discontinued support for legacy GPUs that pre-date the company's switch to Graphics Core Next technology. The last driver for non-GCN GPUs has been released, and the company will not be dedicating any more resources on these legacy devices. Instead, AMD will be shifting its efforts entirely towards developing new features for GCN cores and enhancing existing features.

The affected products include AMD Radeon HD 8400 and lower 8000-series cards, and Radeon HD 7600 and below. The entire line of Radeon HD 5000 and HD 6000 cards have also been added to the legacy support list.

AMD said that it has released an "As is" beta version of Radeon Software Crimson that will work with these cards, but there will be no further updates for this driver. AMD said the Crimson Beta was released as a courtesy to its valued customers so they can use the new interface, but the last WHQL driver for these products is Catalyst Software Suite 15.7.1, which was released in late July, and there won't be any further updates to the Crimson beta for legacy hardware.

The beta version of Radeon Software Crimson that supports the HD 5000 series and up is available from AMD's website.

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