A “routine” update for a Samsung smart fridge model in South Korea has broken the refrigerators for thousands of users, with the incident happening ahead of a major holiday. According to Seoul Shinmun [machine translated], the company pushed an erroneous update to some customers during testing, which resulted in the refrigerators getting stuck while updating.

Unfortunately, several customers only found out about the issue hours after the process had started (and, subsequently, gotten stuck). One customer said in a Samsung Members forum that when she arrived at 7 pm, she noticed that the fridge’s auto-open feature refused to work, the light inside it didn’t turn on, and the temperature inside the unit was starting to warm up. She even tried resetting the power to the fridge, to no avail. Another user lamented the same problem, noting that they'd owned the unit for less than a year, while others complained about food spoiling.

Even worse, this happened just a couple of days before a major South Korean holiday. Chuseok, also known as "Korean Thanksgiving," is a three-day mid-autumn harvest festival set from Sept. 24 - 26. The holiday, which lands partially on a weekend, meant that service was going to be delayed. There were multiple reports that technicians couldn’t visit the affected customers until Oct. 1, with another user saying that they wouldn’t get serviced until Oct. 7.

This is a big problem as many families have stocked up on food for the celebration. One consumer said that this has ruined the holiday for customers who used these fridges, while others said, “All my Chuseok food is going to spoil,” “What am I supposed to do with the eel and premium beef?” and “I stocked up on food for the holiday, but it’s all melting.” One user claimed, “I threw away 20kg of spoiled food today — how am I supposed to spend the holiday now?”

Samsung soon recognized the gravity of the situation and promised that all affected customers would have their refrigerators restored by Sept. 24. The company also said that it would deploy emergency on-site services to attend to urgent issues such as refrigerator and freezer malfunctions. As for the spoiled food, Samsung said it is reviewing whether it will offer compensation.

Samsung said in 2023 that it plans to put AI chips in all its home appliances, which will supposedly make them smarter and run more efficiently. However, this incident raises the question of whether we really need these features. While it may offer marginal quality of life improvements for some users, the fact that a software update could break your AI fridge (or any other home appliance, for that matter) raises red flags for users. Faulty updates aside, there have also been privacy and security concerns — which we’ve previously seen on robot vacuums after one user accidentally gained control of over 6,700 units, and was also noticed on an LG washing machine that was allegedly sending almost 3.7GB of data daily.

Memory prices are at record highs due to demand from the AI sector and are not going to drop any time soon. In fact, the cost of manufacturing memory chips on a per-area basis can be higher than the price of silicon processed using TSMC's N2 and N3 fabrication technologies, which are used to make compute chips, according to an observation made by Kurnal Insights. While the comparison has merit, it has an important caveat.

Based on media leaks, Kurnal from Kurnal Insights considers that a 300-mm wafer processed using TSMC's N3 technology costs $20,000, which translates to approximately $0.283 per mm² when the wafer price is divided by its area. For TSMC's N2, the analyst assumes a considerably higher wafer price of $30,000, or around $0.424/mm². These calculations are based on unofficial information and do not account for unusable wafer edges, dicing, test structures, defects, or yield, so they should be viewed as nominal wafer-area prices rather than the actual price of usable silicon.

The calculation for DRAM works differently. Kurnal assumes a DRAM price of $1.50 per Gb and then multiplies it by the bit density of different generations. At 0.219 Gb/mm², 1y DRAM works out to $0.329/mm², whereas 1z DRAM with its 0.273 Gb/mm² density reaches $0.410/mm². Finally, 1b DRAM at 0.436 Gb/mm² produces a figure of $0.654/mm², considerably higher than the nominal $0.424/mm² calculated for an N2 wafer.

There is an important distinction here. The N2 and N3 numbers represent assumed prices charged by TSMC for processing a wafer, whereas the DRAM figures represent the potential selling value of the memory contained within a square millimeter of silicon, thus illustrating how much revenue a DRAM maker can theoretically get from a given die area at the assumed memory price.

Interestingly, Kurnal Insights' $1.50/Gb assumption is almost exactly in line with the current spot price of DDR5 eTT memory. According to DRAMeXchange, 16Gb DDR5 eTT chips carried a session-average price of $24.80 on September 21, equivalent to $1.55/Gb. At that price, 1b DRAM with a density of 0.436 Gb/mm² would be valued at approximately $0.676/mm², just 3% above Kurnal's $0.654/mm² estimate.

It goes without saying that producing DDR5 memory is considerably cheaper than making logic chips using TSMC's N3 process technology. However, with DRAM in short supply, memory makers are getting considerably more money for their silicon than they did historically.

There are a few important caveats that make the comparison somewhat less straightforward. The calculations do not account for packaging costs, with logic requiring more expensive techniques. Additionally, TSMC manufactures chips on a contract basis, and the actual price of a processed wafer depends on the volumes, customer, and other commercial terms. Thus, comparing estimated TSMC wafer prices with DRAM spot prices is not exactly an apples-to-apples comparison. Even TrendForce notes that DDR5 spot procurement remains limited and transactions are sporadic, which means spot prices do not necessarily reflect the prices at which Micron, Samsung, and SK hynix sell the bulk of their DRAM.

Therefore, contract DRAM prices would provide a considerably better basis for an economically meaningful comparison. However, we do not know contract prices, and while they are clearly higher than historical memory prices, they may not be as high as spot prices. To that end, we cannot state for sure that DRAM makers get more money for their wafers than TSMC does for its logic wafers.

The Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) has developed an experimental process flow for building stacked-nanosheet gate-all-around (GAA) transistors using immersion DUV lithography and demonstrated functional devices. The flow is intended for eventual use with 3nm-class and smaller process technologies by Chinese chipmakers that do not have access to EUV scanners, reports DigiTimes.

While IMECAS has demonstrated functional GAA devices, it has not disclosed the critical geometrical parameters that would allow comparisons to 3nm-class transistors from other chipmakers. Furthermore, the experimental process flow for building transistors is not even a defined process flow for building research chips, much less a complete 3nm-class manufacturing process.

Nonetheless, the achievement is quite important as it demonstrates that China is capable of developing its own branch of semiconductor evolution without using leading-edge tools from Western companies.

Early process integration complete

Ye Tianchun, chief engineer of China's National Major Special Project 02, said at the IC World conference in Beijing that IMECAS had completed 'early process integration' for stacked nanosheet-channel GAA transistors fabricated with DUV lithography. The researchers from IMECAS obtained devices with Ion/Ioff ratios of 9.7×10⁵ and 7.6×10⁵, both exceeding the 5×10⁵ threshold, which means gate control of the stacked sheets is working. These figures indicate that the experimental transistors can distinguish between their conducting and non-conducting states, but they say little about transistor density or whether their physical dimensions correspond to those expected from commercial 3nm-class technologies.

In particular, IMECAS has not disclosed gate pitch, metal pitch, nanosheet dimensions, transistor density, SRAM density, or other geometrical characteristics that could put its devices into perspective against 3nm-class production nodes from Intel, Samsung Foundry, or TSMC. Therefore, the achievement should be viewed as validation of a stacked-nanosheet GAA process flow based on DUV lithography rather than evidence that China has developed a 3nm process without EUV.

The most important part of the experiment is that IMECAS is investigating how GAA devices intended for future 3nm-class and more advanced technologies can be fabricated without using EUV lithography, something that nobody has done before in volume production.

GAA transistors have succeeded FinFET devices at leading-edge nodes because placing the gate around nanosheet channels provides better electrostatic control as transistor dimensions shrink. IMECAS has been developing technologies required for this transition since 2020, and its particular focus was on nodes below 3nm, which is why it now mentions 3nm as part of its announcement.

Reducing China's dependence on advanced foreign tools

It goes without saying that IMECAS' work in recent years has been focused on reducing China's dependence on tools, software, and other technologies that are designed by Western companies and therefore subject to export restrictions imposed by American, Japanese, or European countries.

Among other things, Ye mentioned architectural innovation, design-technology co-optimization (DTCO), system-technology co-optimization (STCO), and 'extracting more value' from mature fabrication technologies. For now, IMECAS' result demonstrates a DUV-based route for researching stacked-nanosheet GAA transistors intended for future 3nm-class technologies, but not a China-developed 3nm process ready for manufacturing even in the long-term future.

Even if IMECAS eventually demonstrates appropriately scaled GAA devices using DUV, or discloses critical geometry parameters of the current work, this would still be far from a production-ready 3nm-class technology. Commercial manufacturing requires integration of lithography with deposition, etching, cleaning, metrology, process control, materials, temperatures, and many other steps and parameters. For now, IMECAS has not demonstrated such a manufacturing flow.

Even as chipmakers race to build the most advanced chips inside the United States, experts are saying that their efforts are facing one monumental challenge: a massive shortage of skilled workers to run the fabs and factories. According to CNBC, global consulting firm McKinsey and the SEMI Foundation suggest the industry will have up to 157,000 positions that could remain unfilled by 2030.

“I’m concerned,” Samsung semiconductor division EVP Jon Taylor told CNBC in an interview. “We just don’t see that there’s enough technical people in the pipeline.” The McKinsey report says that only 3% of U.S. engineering graduates end up working in the semiconductor industry, and that 73% of chip companies are finding it hard to fill engineering roles. This is a huge contrast to other tech jobs, which saw record layoffs by June of this year, when over 40,000 positions were axed, ostensibly largely due to AI.

The massive demand for memory and storage chips driven by the AI boom, combined with Washington’s efforts to bring semiconductor manufacturing back to the United States, has led to the buildup of multiple fabs and facilities dedicated to it. TSMC was one of the first companies to kick off this building spree, when it started construction on its Arizona campus in 2021. The site started churning out chips last year, with the company committing another $100 billion in July 2026 to build four more 2nm fabs. Intel’s Ohio One plant, which was, at one point, America’s largest fab complex, is also underway, with the site expected to start production between 2030 and 2031.

The big three memory makers — Micron, Samsung, and SK hynix — are also planning or have recently completed major expansions in the U.S. Samsung is starting advanced semiconductor manufacturing in the U.S., with its Taylor, Texas, fab entering risk production this year. The fab is targeting an output of 50,000 wafer starts per month, and it is expected to create 3,500 jobs. “We’re hiring engineers, we’re hiring technicians, we’re hiring people in the supply chain,” Taylor told the publication. “Everybody wants and needs the same thing, and it’s a bit of a race against time right now as everything is starting to come online.”

Micron is also currently building its Boise, Idaho, memory chip fab, which began construction in 2022 and is projected to begin wafer production by 2027. The company has also formally broken ground on its $100-billion New York “megafab,” with aims to produce 40% of its global output within the U.S. by the 2040s. Aside from these massive manufacturing sites, it has also committed $10 billion toward new research labs in the U.S., to be built near the global Micron R&D center in Boise.

Finally, SK hynix also started construction of its first HBM plant in the U.S., with its West Lafayette, Indiana, campus dedicated to packaging these crucial components for AI data centers. There have also been rumors that the South Korean company is in talks with Intel to either lease space at its Ohio One factory or launch a joint venture alongside other AI hyperscalers to build memory chips in the U.S.

All these construction projects, plus the requisite supply chains, will necessitate thousands of workers. Local universities like Purdue University and Arizona State University are already investing millions of dollars to help prepare a capable workforce, with the former launching degrees in 2022 focused on semiconductors. Samsung and Intel are also investing in various programs, including internships and scholarships, to help secure a future workforce for the companies.

However, salary is one major concern listed by the SEMI Foundation. U.S. chip fabs typically pay $127,000 to $187,000, with senior staff getting $238,000 or more. While this is a more-than-competitive salary in the U.S., it’s dwarfed by the bonuses recently offered by Samsung and SK hynix in South Korea, which have reached hundreds of thousands of dollars. With the projected worker shortfall, we should expect the job offers from these semiconductor companies to catch up with their eastern counterparts if they want to secure and maintain talent here in the U.S.

ASML, Intel, Samsung, and TSMC are teaming up to drive the industry transition to 6×12-inch photomasks (reticles). This shift is paramount for High-NA EUV lithography, as the larger stencil would enable printing large chips in a single pass, instead of having to stitch smaller designs together, as ASML explained in a press release this week.

This kind of collaboration between chipmakers isn't entirely unheard of, but it is rare. But when they face an industry-wide challenge, they set aside their rivalry and join forces to move the industry forward. This happened several times in recent decades, first with the failed transition to 450-mm wafers co-funded by GlobalFoundries, IBM, Intel, Samsung, TSMC, and New York State, then with the EUV transition, which was spearheaded by Intel, TSMC, and Samsung.

Higher resolution comes with a nuance

High-NA EUV lithography is a major step forward from today's Low-NA EUV tools. With a numerical aperture of 0.55, High-NA systems can achieve an 8nm single-exposure resolution, compared with 13nm for 0.33-NA EUV scanners. The higher resolution enables chipmakers to pattern smaller, denser features in a single exposure, replacing complex Low-NA EUV multipatterning schemes with a single High-NA exposure. This can reduce the number of masks and process steps, shorten manufacturing cycle times, and potentially improve pattern fidelity and yields, especially on critical layers of next-generation process technologies.

However, this improvement comes with a significant tradeoff. Conventional 0.33-NA EUV uses 4X reduction optics in both directions, which enables a 26×33 mm exposure field with standard 6×6-inch photomasks. By contrast, High-NA EUV uses 4X/8X anamorphic optics, so the same mask can only expose a 26×16.5 mm half-field, which is hardly a problem for client-oriented designs that are barely larger than 429 mm². However, large dies that fit within a conventional 26×33 mm EUV field must now be patterned using two High-NA exposures stitched together, or split into a multi-chiplet design.

Stitching is a workable near-term solution that all chipmakers, including Intel, Samsung, and TSMC, use, but it comes with multiple drawbacks. First, it reduces the throughput of ASML's Twinscan EXE:5200B scanner from up to 175 wafers per hour for half-field exposures to around 125 wafers per hour when stitching is used. Secondly, chip designers must account for the stitching boundary, which means additional design rules and reduced floor planning freedom.

Finally, the two exposures must be aligned with extreme precision so that features crossing the boundary connect properly. Even tiny alignment errors can distort lines and vias, or compromise interconnects and thus potentially create defects and lower yields. Such yield loss is very expensive in the context of large CPUs and GPUs produced using Low-NA EUV systems. If yield is lost on more expensive High-NA EUV tools, the costs will be even higher, which greatly lowers the appeal of using these scanners.

New photomasks are needed

To eliminate the need for stitching, the industry is exploring larger orthogonal 6×12-inch photomasks to compensate for anamorphic optics. By doubling the reticle dimension corresponding to High-NA's 8X reduction direction, these masks are set to restore the traditional 26×33 mm full exposure field and enable even reticle-sized dies to be patterned without stitching.

However, 6×6-inch photomasks have been an industry standard for around three decades since the 1990s. Even the transition from DUV to EUV did not change the basic mask dimensions: EUV replaced transmissive masks with reflective multilayer masks but retained the 6×6-inch substrate form factor. As a result, the adoption of 6×12-inch reticles would require the industry to change the entire mask-making, mask handling, and lithography infrastructure built around the existing format.

Mask-blank suppliers like AGC and Hoya would need new or modified equipment to produce larger substrates and deposit uniform reflective EUV multilayers across a much larger area. Mask shops would need new or modified writers and etch tools to pattern the larger masks, as well as inspection and metrology systems capable of precise characterization of the new format. Cleaning equipment, pellicles, and pellicle-mounting devices would also require modifications.

The mask handling infrastructure would have to change as well. Suppliers would need larger mask pods, while fabs and mask shops would require compatible storage, transport, and automated handling systems. At the same time, they would have to retain support for existing 6×6-inch masks since existing and future Low-NA EUV and DUV scanners will continue to use the established format.

Perhaps the biggest changes would be required from ASML. Its High-NA EUV scanners would need modifications or a redesign to accept, clamp, move, and position the substantially larger reticles with the extreme precision required for EUV lithography.

Intel, Micron, Samsung, SK hynix, TSMC, and other chipmakers planning to adopt High-NA EUV lithography would then have to qualify the new masks, scanners, and other tools for their process flows and ensure that the full-field exposure capability works as intended.

As a result, the adoption of 6×12-inch masks would require a coordinated effort and significant investments from chipmakers, ASML, mask makers, and numerous equipment and materials suppliers.

To make matters more complicated, 6×12-inch masks will not replace the existing 6×6-inch format altogether, as noted above. The industry would therefore have to manufacture, inspect, transport, store, and handle two mask formats in parallel, which will add cost and complexity to an already expensive transition.

Timeline

The transition to 6×12-inch reticles is an industry effort currently supported by ASML, Intel, Samsung, and TSMC. It is going to take years and will happen well after High-NA EUV enters high-volume manufacturing with today's 6×6-inch photomasks, as the semiconductor industry prefers to adopt new technologies gradually.

Intel already uses High-NA EUV scanner(s) for select Intel 18A layers (patterned at Fab D1X) and supports both floorplanning within the half-field and stitching; Samsung plans to introduce High-NA EUV into DRAM high-volume manufacturing by 2028, and TSMC intends to deploy the technology for advanced-node production starting in 2030. All three companies plan to start High-NA EUV adoption with 6×6-inch masks.

Intel seems to be leading the pack with 6×12-inch reticles as it has been working for three years to make them a reality, but the company remains tight-lipped about the timing of its adoption of the new photomasks. Meanwhile, the ASML-TSMC initiative targets a 6×12-inch photomask pilot line by 2031, which should provide the foundry with a platform to develop and qualify the new mask format and associated manufacturing infrastructure. The ultimate target is full lithography-system readiness for advanced-node production by 2033.

That said, 6×6-inch and 6×12-inch photomasks for High-NA EUV patterning will likely co-exist on the market at least for some time rather than undergo an abrupt transition. At the end of the day, square 6×6-inch reticles that enable High-NA EUV scanners to expose fields as large as 26×16.5 mm (or 429 mm²) should be sufficient for the vast majority of client processors produced in the coming years. Larger 6×12-inch masks will matter primarily for much bigger designs, such as high-end AI accelerators, data center CPUs, DPUs, high-end GPUs, and FPGAs, where the ability to expose a full 26×33 mm field without stitching becomes considerably more valuable.

OpenAI is expanding its relationship with Samsung beyond memory supply and enterprise software as the AI giant plans to outsource production of at least some of its processors to Samsung Foundry, Harrison Kim, General Manager of OpenAI Korea, revealed this week. If the information is accurate, then OpenAI will source its AI accelerators from both TSMC and Samsung Foundry, which suggests massive volume requirements.

"One of the areas where we have made the most progress and gained the most recognition with Samsung Electronics is our joint production and ​research on the next-generation chips we are developing," said Harrison Kim, General Manager of OpenAI Korea, at ​a press conference in Seoul, Reuters reports.

OpenAI already has its own AI ASIC program that relies on Broadcom's design services as well as TSMC's wafer processing and advanced packaging services. So far, the company has introduced its first inference AI accelerator called Jalapeño that was defined by the company's engineers, then co-designed with Broadcom, then made by TSMC, all in less than 18 months.

OpenAI did not explain whether Samsung's participation concerns a second production source for Jalapeño, another processor under development by OpenAI, a chip jointly developed by Samsung and OpenAI, or some other aspect of chip production and development. Samsung and SK hynix already supply memory for OpenAI's Stargate data center initiative, though joint chip development and production barely have a relation to DRAM supply.

OpenAI's 1^st Generation Jalapeño will unlikely be double-sourced from TSMC and Samsung because the chip is already in mass production at TSMC and OpenAI is talking about 'next-generation chips,' not the ones that are in mass production at the moment. Furthermore, development of Jalapeño's successor is well underway and is approaching tapeout, which means that its mass production is not far away either. Since OpenAI's claim clearly involves 'next-generation chips,' it is entirely possible that OpenAI will indeed produce its 2^nd Generation inference ASIC at Samsung Foundry.

Back in late July, Samsung Electronics and Broadcom announced a strategic partnership valued at over $200 billion through 2030 to collaborate on advanced foundry, memory, and packaging technologies for AI infrastructure. Hence, as OpenAI has an agreement with Broadcom to procure 10GW of custom AI accelerators, it will be able to produce these accelerators at both Samsung and TSMC. Of course, if it needs silicon produced at Samsung, and pays Broadcom for appropriate design porting.

Perhaps, OpenAI will take a page from Tesla's book and will double-source Jalapeño's successor from TSMC and Samsung to get higher volumes. However, Tesla's volume requirements may be different from those of OpenAI.

Tesla needs extraordinary AI5 volumes because it intends to use the processor across three very different high-volume applications: AI data centers, vehicles, and Optimus robots. Therefore, Tesla could potentially need millions of AI5 chips for cars alone, on top of robots and data-center deployments. Therefore, paying for separate TSMC and Samsung physical implementations gives Tesla not only supply-chain resilience but also aggregate capacity necessary to supply several product categories.

Yet, data center accelerators tend to be vastly more silicon-intensive per unit compared to ASICs for vehicles or robots. If OpenAI/Broadcom's next ASIC is a large leading-edge processor with multiple dies and OpenAI wants gigawatts of these processors, wafer requirements could still become too high for TSMC alone (which is fully booked by the likes of AMD and Nvidia). In that situation, OpenAI may need another foundry to get enough ASICs. Still, we are speculating.

When it comes to high-speed storage, SSD prices have been at an all-time high due to the ongoing turbulence in the memory market. However, if you are looking for a speedy drive with plenty of capacity, Samsung’s freshly launched 990 PCIe Gen 4 SSD with 2TB capacity is already selling at a discount. You can grab the drive at $339.99 at Amazon, down from its usual price of $529.99.

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The Samsung 990 series was launched earlier this year, right in the midst of the RAMpocalypse. The SSD is essentially a QLC-based version of the 990 EVO Plus. QLC SSDs can be a good choice for gaming, as it mostly involves reading data rather than writing it. QLC drives are slower than TLC, but frequently used data can stay in the faster pSLC cache if the drive has enough free space. The Samsung 990 also features the company’s PiccoloQ controller with V9 QLC Flash memory and is capable of full PCIe Gen 4 throughput.

In our testing, we found the drive to offer similar results to Samsung’s 990 Evo Plus and the 990 Evo in latency testing, while beating the 990 Evo drive in bandwidth and 3DMark overall score. It also managed to stay competitive with the Crucial P310, which is one of the best QLC-based drives on the market. The Samsung 990 is also a solid option for consoles, delivering bandwidth that puts it ahead of the 990 Evo and on par with or better than most budget PCIe 4.0 drives.

The Samsung 990 at $339.99 is a compelling option for those who are looking for plenty of fast storage without paying more during the current SSD price surge. The 1TB model is also selling at a discount if you do not require this much storage. Do keep in mind that this sale price is available for a very limited time. If you need a high-capacity PCIe 4.0 SSD, it may be worth grabbing before the discount disappears.

The saga involving Chinese DRAM maker CXMT's alleged theft of Samsung's trade secrets is going strong. The South Korean court case already includes multiple convictions, two of which carry prison sentences for ex-Samsung engineers. The latest chapter is a doozy, though. Korean publication NoCut News spilled the chips on Project Hefei, a purported CXMT roadmap outlining long-term planning about said technology "acquisitions," personnel poaching, and production tape-out — all key pieces that may have directly led to CXMT's ascension to 10% of the global DRAM market.

According to leaked court documents, the prosecution says that Project Hefei was CXMT's entire DRAM development plan and was spearheaded by the firm's head of development (formerly Samsung's DRAM development lead), around August 2016 — not much longer after CXMT itself was created in June 2016.

In brief, the purported plan was to nab Samsung's Process Recipe Plan (PRP) by September 2016, poach key Samsung engineers by October 2016, have R&D complete in July 2017, and start making DRAM wafers by August 2018 at a rate of 10,000 a month. NoCut says the PRP dataset comprises 620 steps in DRAM manufacturing and includes data on equipment, consumables, and production methods.

The report states that in August 2016, CXMT first attempted to make wafers of 18nm chips by relying on the collective memories of the Samsung engineers it had hired away. Those recollections apparently proved insufficient, so after allegedly gaining illicit access to Samsung's PRP, CXMT prepared its own document in September 2016. The leaked data even included specific equipment suppliers and model numbers.

CXMT's "new" PRP was then handed out to key specialists, many of them ex-Samsung engineers, whom the prosecution says ought to have immediately recognized the data as originating from the Korean firm. The document apparently included notation and notes on process developments that were all unique to Samsung. A convicted ex-Samsung researcher with the surname Jeon, previously sentenced to 7 years in prison for manually copying parts of the PRP before leaving for CXMT, testified in this case as a witness.

The whole CXMT debacle has been playing out in South Korean courtrooms since January 2024 and is arguably far bigger than just "a company stole some tech from another." A decade ago, most of the DRAM market was taken by the Big Three: Samsung, Micron, and SK hynix. CXMT was created in June 2016 in Hefei (hence the project name), with a modest government investment of around $1.9 billion USD, allegedly with no R&D facilities whatsoever or any plan for research.

Going from zero facilities and institutional expertise to DRAM wafer production in little over two years would be an unprecedented feat, and presumably nigh impossible without the alleged IP theft; getting just the memory fab up and running usually takes two to four years, let alone any time for research. The firm claimed in 2019 that it designed its then-new 8 Gb DDR4 chips entirely in-house as a "leapfrog, independent" technology and began selling DRAM chips locally.

Then the AI locusts charged in and ate every chip on the planet. This demand resulted in explosive growth for CXMT, from an estimated 4% of the global DRAM market in Q2 2025 to around 10% in Q2 2016, marking the first time in over a decade that the Big Three held less than 90% of the pie.

Production capacity expanded to three 12" wafer fabrication facilities, expected to churn out a collective 350,000 wafers until the year is done — close to the same figure that Micron produces, of 375,000 to 385,000. CXMT is also planning to open a second fab in Beijing, aiming to produce over 600,000 wafers per month once it's online.

Furthermore, CXMT's gains aren't coming just from its DRAM market share. Revenue grew 716% in Q2 2026 alone, and its IPO on the Shanghai STAR Market in July 2026 saw its stock climb 466%, netting the firm a cool $8.6 billion USD and making it the most valuable chipmaker in the Chinese stock market.

About 70% of that money is reportedly going towards further expansion of DRAM production, rather than pricier, more complicated HBM. However, the firm has supplied HBM3E samples to Alibaba's T-Head and Cambricon, even as Samsung and SK hynix enter HBM4 production.

As of the South Korean prosecution's last tally in December 2025, Samsung's damages due to CXMT's alleged machinations ascended to "at least tens of trillions of won." A back-of-the-envelope extrapolation, considering quite a while has passed, might suggest a figure in the range of ₩40 trillion, or $29.5 billion, and rising exponentially.

The lasting impact on the memory market and technology in general is going well beyond plain number descriptors, though. All things considered, if the allegations are true, then CXMT's machinations resulted in a geopolitical-scale economic event. Dr. Evil would be proud.

The goal of next-generation HBM5 memory specification is to double performance and increase power efficiency compared to HBM4E, Samsung announced at the 'Memory Executive Summit,' an event that precedes 'Semicon Taiwan 2026.' Considering that it is barely realistic to double the data transfer rate of HBM4E in just one generation, the comment made by Samsung may imply that HBM5 will double the number of interface pins to boost bandwidth.

The goal of HBM5, which is currently under development, is to double the performance and improve the performance per watt by 20% compared to the HBM4E generation, according to Choi Jang-seok, the head of the product planning team of the memory business department of Samsung Electronics DS division. Previously, Samsung announced that its HBM5 memory stacks will feature a heat path block (HPB), which will reduce thermal resistance by 20% and simplify cooling of HBM5 modules.

Doubling HBM5’s per-stack memory bandwidth would result in peak bandwidth of around 4 TB/s per stack already in 2028 – 2029. TSMC expects AI accelerators to get to 20 – 24 HBM5/HBM5E per package configurations by the end of the decade, which means that these systems-in-packages will get a whopping 80 TB/s – 96 TB of memory bandwidth just several years down the road.

Although both DRAM makers like Micron, Samsung, or SK hynix as well as developers of HBM controllers and PHYs like Cadence, Rambus, or Synopsys already offer HBM4/HBM4E controllers and interfaces rated for 16 GT/s data transfer rates, the official JEDEC transfer rate for HBM4E will be around 12 GT/s.

If Samsung expects HBM5 to deliver twice the bandwidth of HBM4E, the HBM5 specification must either double the per-pin data transfer rate from 12 GT/s to 24 GT/s, double the interface width from 2,048 to 4,096 bits, or combine a wider interface with a higher data transfer rate. Increasing HBM5 memory stack interface width to 4,096 bits has so far been envisioned by KAIST and Marvell; however, this is certainly not an even semi-official confirmation of the specification's target.

From a performance-per-watt perspective*, widening the interface is generally easier than doubling the per-pin signaling rate. Higher per-pin speeds require faster drivers, receivers, clocks, equalization, tighter timing margins, and a more sophisticated PHY since maintaining signaling integrity at speeds well beyond 20 GT/s is not easy. But while a wider HBM interface moves more bits in parallel at a lower speed per wire, going from 2,048 to 4,096 pins means twice as many TSV/I/O paths, drivers, receivers, bumps, more complicated routing, and extremely complicated base die. So while a 4,096 I/O at moderate speed is probably best for pJ/bit, the interface/package complexity gets so extreme that it may offset the gains. Furthermore, such a wide interface Perhaps a 3,072-bit interface combined with a moderate increase in data transfer rate would be a reasonable engineering compromise, though engineers involved in JEDEC’s decision-making process may think otherwise. In any case, for now, any discussion of HBM5 specifications remains speculative.

Nonetheless, the target to double the bandwidth of HBM4E (2 TB/s per stack) within one generation is clearly a very aggressive one.

*It should be noted that achieving a 20% higher energy efficiency can be achieved not only by increasing performance, but by improving DRAM process technology, optimizing base die, lowering TSV I/O voltages, architectural changes, or power management.

Fast refresh curved gaming monitors often cost a pretty penny, so it’s always a good idea to snag one if you see one go on sale. That’s why you should check out the Samsung Odyssey G55C if you want to get your hands on one, as it’s currently at 39% off on Amazon. This limited-time deal brings that price of the monitor from $329.99 to just $199.99, saving you $130 off sticker.

• Grab this deal on Amazon.

The Samsung Odyssey G55C is a 32-inch VA gaming monitor that comes with a 1000R curvature for better immersion during gaming. Aside from that, it also gives you 1440p QHD resolution, a 165 Hz refresh rate, and a 1 ms response time for that sharp and smooth gameplay. Of course, since this display is designed for gaming and entertainment, it also has AMD FreeSync to avoid screen tearing and is HDR10-compliant to give you incredibly vibrant scenes. If you plan to game for several hours at a time, you’ll also appreciate its Eye Saver Mode, which cuts screen flicker to reduce eye strain and distraction.

This display offers both HDMI and DisplayPort, allowing you to simultaneously plug your gaming PC and gaming console into it. Although it doesn’t have built-in speakers, it does come with a 3.5mm headphone jack, allowing you to attach your headphones or speakers directly, reducing cable clutter on your desk. The monitor comes with a fixed base that with thin legs to save space, but if you need more flexibility, you can also mount it to a monitor arm via the standard VESA mounting points at the back of the display.

Some of the drawbacks of this monitor is that Samsung doesn’t share its DCI-P3 coverage and color accuracy stats. It also only limited to just 300 nits, so it might struggle if you plan to use it in brighter locations. If you need a more capable monitor, you should consider options from our best gaming monitors list. But if you’re only looking for a display to satisfy your gaming needs, this monitor is more than enough for most of your requirements. So, if you’re looking for a new gaming monitor, you should get the Samsung Odyssey G55C right now for just $199.99. Don’t hesitate as this is a limited-time deal, so you should get it while you can.

While SSD pricing isn't quite as bad as RAM, buying more storage for your PC is tough these days. Samsung recently released a new 'budget' version of its 990 M.2 SSD, and it just got a decent discount at Amazon. The 990 2 TB SSD is now $339 instead of $529, a 36% saving.

● Grab this deal at Amazon

The 990 SSD is an interesting product because it is one of the few SSDs released after the AI pricing crunch sent storage prices into orbit. As such, we know what Samsung thinks this drive is worth in the current climate, namely $529. While 2TB of storage would have been much cheaper a year ago, a 36% discount on a new SSD is not to be sniffed at, especially given all signs point to these drives getting more expensive, not cheaper, in the future.

We reviewed this drive at launch last month and liked its full-fledged Gen 4 throughput, decent power consumption, and good all-around performance. The 990 is essentially a QLC-based 990 EVO Plus, featuring Samsung's PiccoloQ controller and V9 QLC Flash memory.

As you can see from our testing data, it scores very close to the 990 EVO Plus in latency testing, while beating the 990 Evo drive in bandwidth and 3DMark overall score.

This drive also scored well in our PS5 test, so this drive could serve as an expansion drive for your PlayStation if you so choose. At its list price, this drive makes no sense as a purchase up against the 990 Pro or Samsung's Gen 5 9100, but at this price it is a good chunk cheaper than both of those options. Amazon does have a 39% discount on the 990 Pro 2TB, now $389 instead of $639 if you want to spend a bit more on that slightly more performant drive. Or, if your motherboard supports Gen 5, you might want to eat the $60 jump for the 9100 Pro 2TB, currently $399 at Amazon. This regular 990 also has a 1TB model on sale, but that discount is just 13%, so its $199.99 price tag makes it poorer value compared to the 2TB model.

As always with storage deals, these prices are tough to stomach, but they aren't going to improve any time soon. In fact, all signs point to the AI pricing crunch continuing to make things worse going forward, meaning leaving it too long could make storage even more expensive in the future.

Glass-core substrates, the replacement for organic chip packaging that Intel promised in September 2023 with more than $1 billion behind it, are now in final qualification. However, the product is still not in a single commercial product. SKC, a material manufacturer and chemical affiliate of the SK Group, said on its July 27 earnings call that embedded glass substrate samples from its Absolics plant in Covington, Georgia, are undergoing package-level reliability evaluation in Taiwan, with results possible before year-end.

Samsung Electro-Mechanics formalized a 482.1 billion won ($310 million) glass-core joint venture with Sumitomo Chemical's Dongwoo Fine-Chem on July 2, targeting first production in the second half of 2027. Intel, which started the race, has shifted to licensing its patents and showing demo vehicles, with its own deployment now pointed at around 2030. However, and rather predictably, every timeline in the segment has slipped. Absolics originally planned mass production for the first half of 2024, and reported claims that AMD would adopt glass substrates for CPUs between 2025 and 2026 have come and gone unfulfilled.

Why glass?

The technical case for glass core substrates leans heavily on numbers Intel published a while back, such as 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion. Glass cores can be tuned to a thermal expansion coefficient of roughly 3 to 10 ppm per degree Celsius against silicon's 2.6, which cuts warpage by about half compared with organic cores, and rectangular panels in the emerging 510mm x 515mm format use more than 75% of their area for large die against roughly 50% for round 300mm wafers. Through-glass vias have been demonstrated at six microns in diameter with aspect ratios beyond 15:1 at ECTC 2025, and Georgia Tech has shown stacked glass running at 220 GHz with 0.3 dB of loss.

Glass also chips and cracks at the edges during drilling and dicing, and MIT Technology Review reported in March that early Absolics production runs broke hundreds of panels every couple of days during early testing days. Edge-coating work has cut measured edge stress from 95 MPa to 49 MPa, and low-temperature dielectrics that cure below 180°C have been developed to reduce thermal stress during build-up, but metallizing vias below 10 microns and holding nanometer-scale flatness across half-meter panels remain open manufacturing problems.

Intel's program

Intel demonstrated a working system booting Windows on a glass-core substrate in early 2025, and Rahul Manepalli, Intel's VP of module engineering, told MIT Technology Review that the benefits of glass cores are "undeniable" and that Intel wants "to be one of the first ones who do it." The commercial plan around that engineering has changed shape, however. DigiTimes reported in late July that Intel is in early-stage talks with Chinese cover-glass maker Lens Technology about a packaging partnership, but there has been no solid agreement made to date.

At NEPCON Japan in January, Intel Foundry showed its first thick-core glass substrate with two EMIB bridge dies embedded directly in the glass: a 78mm x 77mm package with two 800-micron-class glass layers, 10 redistribution layers on each side, and around 1,716 mm2 of silicon on top, roughly two full reticles, with no micro-cracking reported in testing.

There’s currently no production time to this, however, with TrendForce placing Intel’s commercialization somewhere around 2030, alongside co-packaged optics prototypes built on glass at its Rio Rancho, New Mexico site. Meanwhile, Amkor, Intel's packaging partner on the optics work, put commercialization within three years at an industry event in Seoul in April.

Korea aiming for 2027

Samsung Electro-Mechanics moved its glass program from advanced R&D into a business-execution unit in February and has been sampling from a pilot line at its Sejong plant since late 2024. The GLASEM joint venture announced on July 2 splits ownership: 66% to Samsung Electro-Mechanics and 34% to Dongwoo Fine-Chem, with site production in Pyeongtaek, and targets an operating plant in the second half of 2027, with the joint venture making the drilled and metallized glass core that feeds Samsung's substrate line. Korean industry reporting says samples have gone to AMD and Broadcom, and also puts Samsung's overall glass maturity at 40 out of 100, a gap between marketing dates and process readiness worth keeping in mind.

Absolics' $600 million plant in Covington, Georgia, backed by $75 million in CHIPS Act funding plus a further $100 million through the government's advanced packaging R&D program with Georgia Tech, has a Phase 1 capacity of 12,000 m² of substrate per year, enough for roughly two to three million H100-sized packages. The company produced mass-production samples in the first quarter, began customer qualification that reportedly includes AMD and AWS, and is targeting mass production by the end of 2026. LG Innotek runs a third Korean program from its Gumi plant, with prototypes delivered in 2024 and production targeted for 2027 to 2028.

TSMC and Japan

TSMC's CoPoS line in Chiayi, built around 310mm x 310mm rectangular panels, received tools in February, completed its pilot line around June, and is aiming for pilot production in 2027, with mass production in the second half of 2028. Equipment supplier SCHMID has described glass integration in that platform as under review, not committed, and TrendForce puts TSMC's commercial-scale glass-core production after 2030, meaning that the industry's biggest packaging operation is going panel-level first and glass later, if at all. TSMC revived glass substrate research a couple of years ago after earlier deprioritizing it, reportedly under pressure from Nvidia, whose accelerator packages are the main thing outgrowing current packaging.

Japan’s Dai Nippon Printing began phased operation of a TGV glass-core pilot line at its Kuki plant in Saitama in December 2025 on 510mm x 515mm panels, with sample shipments from early 2026 and full mass production targeted for fiscal 2028. Toppan's pilot line for glass cores and interposers at its Ishikawa plant was scheduled for commissioning in July, and Nippon Electric Glass has scaled its ceramic-reinforced GC Core panel to 515mm x 510mm at 1mm thickness. Rapidus is studying panel-level packaging on 600mm x 600mm glass as part of its 2nm program, with viability put at the late 2020s. China has its own entrants, led by display maker BOE, whose pilot line is sampling.

TrendForce estimates Nvidia's Rubin Ultra package at roughly 7,470 mm², about nine reticles' worth of silicon and memory, against around 2,739 mm² for Blackwell, and CoWoS interposer wafers cost on the order of $10,000 each, comparable to a processed 7nm wafer.

Organic substrates warp and lose dimensional stability at those sizes, and round interposer wafers waste a growing share of their area, which is what glass panels are meant to fix. SEMI's first dedicated market report on glass cores, published in May with Global Net, projects initial production around 2028 in select high-performance applications and a 67.2% compound annual growth rate from 2028 to 2040, while Yole puts the advanced IC substrate market at $31 billion by 2030 with glass cores among the drivers.

At the moment, no production design exists, and all customers that have been named or otherwise attached to the tech, including AMD, Broadcom, AWS, and Nvidia, come from wider industry reporting. Nothing has been confirmed officially. As for whether we might see more substantial progress next year, Absolics will need to publish some solid package-level reliability results by the end of this year, or a first officially named customer at any of the Korean manufacturers. We also need to hear from TSMC on whether glass cores will go into CoPoS or remain under review into the 2030s.

Remember back at CES when Samsung showed off a huge suite of Odyssey gaming monitors? The vast majority of those screens are now shipping, but arguably the most interesting monitor among them, the Odyssey G6 (G60H), still hasn't launched. Back at CES, Samsung was touting a 1,040-Hz refresh rate for that screen; now at Gamescom 2026, Samsung has shared the finalized specification, which is a nice and round 1,100 Hz. That's right; this monitor refreshes vertically at 1.1 KHz.

It's a fascinating display because aside from that specification, it's actually a bit of a pedestrian gaming monitor. You've got a 27" Fast IPS LCD in 2560×1440 (QHD) resolution, and at its native sharpness, it tops out at "only" 600 Hz. Surely that should satisfy anyone, but if you really feel the need for speed, you can drop the resolution to one-quarter of native, bringing you to 1280×720 (HD), and then refresh the panel at 1.1 KHz. That means each frame is displayed for less than one millisecond.

With its Fast IPS LCD panel and one millisecond response time, this new monitor will have its work cut out keeping up with those claimed performance figures. It's surely still going to be incredibly sharp and clear in motion (assuming your system can put out the requisite 1,100 frames per second), but it does seem like an OLED would have been the more appropriate technology for this feature.

Indeed, the rest of the displays that Samsung is showing off at Gamescom 2026, comprising its next-generation Odyssey family, are all OLEDs. Starting from the OLED G7 (G75SJ), we have what Samsung says is "the world's first 42-inch 16:9 curved OLED gaming monitor," which might be true. A 42-inch screen area is absolutely massive, and as you'd expect, to keep DPI up to reasonable levels, it's 3840×2160 (4K UHD) resolution.

The Odyssey OLED G7 G75SJ has a 1000R curvature, which is quite tight for a display of this size. It also has a 165-Hz refresh rate and a rated 0.03-ms response time, although it's an OLED, so you already knew that. Samsung doesn't really share any other specifications for this screen, but the firm does say that this monitor includes "Glare Free technology" to help reduce reflections for "clearer daytime play." That's very helpful on an SDR OLED because the peak brightness of this display is probably low enough that it becomes hard to see in daylight.

The next step up from the G7 is the Odyssey OLED G8 (G80SJ). This beautiful beast sports a 32-inch 3840×2160 (4K UHD) QD-OLED panel that tops out at 360 Hz and features "triple mode" support, meaning that you can drop the resolution to QHD for a 520-Hz refresh rate, or all the way down to 1920×1080 (FHD) for a blistering 680 Hz refresh rate. That's not as fast as the 720-Hz OLED that ASUS announced, but it's also a higher resolution, as that screen has to drop to 720p HD to hit 720 Hz.

The Odyssey OLED G8 (G80SJ) has a few other tricks up its sleeve, too. It supports FreeSync Premium Pro (and is G-SYNC Compatible as a result), and it is spec'd for VESA DisplayHDR TrueBlack 600, which should result in a pretty decent HDR experience, especially in darkened rooms. Notably, its USB Type-C port supports up to 98W of power delivery, meaning it can very rapidly charge whatever device you connect to it.

Finally, the star of the show, the Odyssey OLED G9 (G95SJ), is a 49-inch "DQHD" gaming monitor. DQHD is "Double Quad High Definition", and if you can do arithmetic, you already know that the resolution of this 32:9 monitor is 5120×1440. The super-ultrawide uses a fifth-gen (latest) OLED with "Penta Tandem" technology, meaning that it has a five-layer panel structure that Samsung says lasts twice as long as older OLEDs. It also uses an RGB stripe subpixel layout that should mostly eliminate the text fringing which plagues older-gen OLED monitors.

You've already heard me whinging about the brightness of OLEDs; that won't be a problem on the Odyssey OLED G9 because this thing apparently supports a peak brightness of 1,300 nits. That's admittedly only on a 3% window at 4K resolution, but it's a high enough value that it should mean HDR highlights are nice and vibrant on this screen, although Samsung curiously doesn't list a DisplayHDR cert for this one. Other critical specs include the 360-Hz refresh rate, dual mode support (meaning 720Hz at 2560×720), and the usual 0.03ms response time rating.

Unfortunately, there's no pricing or specific availability for any of these displays. Samsung says that the 1,100-Hz Odyssey G6 will be available globally in "the second half of 2026", which basically means "any day now." Meanwhile, the other displays are explicitly noted as 2027 monitors, where "availability will vary by market," and pricing is anybody's guess in today's tech market.

Earlier this month, Samsung introduced the industry's first LPDDR5X-PIM memory, adding in-memory logic to the low-power memory standard, and at Hot Chips 2026, it dove into the memory technology that we've previously seen at play through HBM stacks.

PIM, or Processing-in-Memory, is a technology Samsung demoed as early as 2021, piloted through HBM stacks in AMD accelerators. It's a small bit of logic that sits alongside DRAM cells, allowing basic calculations to happen directly in-memory. By handling those basic calculations locally, Samsung is able to eliminate the processor as a bottleneck and speed up, in particular, AI inference. In inference tasks, Samsung says its LPDDR5X-PIM is 2.28x faster than standard LPDDR5X, in fact.

The reason for adding in-memory processing to LPDDR5X is pretty clear: HBM is too damn expensive. Micron warned just a day earning at Hot Chips that the HBM wafer demand is only getting worse, and Samsung opened its presentation with something we're all well aware of. Memory makes up the bulk of AI chip costs, and its share of the pie continues to grow. Add on top of that the power demands of DDR5, much less HBM, and LPDDR5X seems like an ideal target for PIM.

Samsung introduced HBM-PIM in 2023, and at the time, introduced the concept of LPDDR5X-PIM. What it shared at Hot Chips is a real product, taking the concept of LPDDR5X-PIM and putting it through validation. Samsung is also looking ahead for LPDDR6X-PIM, and the company says it hopes to have an initial specification from JEDEC this year.

Bringing in-memory processing to Samsung LPDDR5X

Above, you can see a basic layout of how Samsung integrated PIM into LPDDR5X. Each memory bank has its own PIM, which is an advancement over HBM-PIM, where Samsung had to cut banks to fit the logic. The memory bank, scale register file, and source register file feed parallel MAC trees. Once calculated, the output (either integer or floating point output) is written to a vector register file.

Samsung says its LPDDR5X can operate in two modes: single-bank (traditional DRAM) or multi-bank (PIM). Traditional DRAM controllers work, with commands switching between standard read/write or a PIM read/write depending on the mode. The challenge, according to Samsung, was reordering with conventional DRAM.

Samsung uses what it calls Address Align Mode (AAM) to get around the reordering issue. It maps DRAM addresses to MAC instructions, assigning the VRF/SRF address based on the RA/CA address, respectively, and not the Instruction Register File.

To demonstrate how data moves through the memory cells and calculations are performed, Samsung provided an example of a MAC operation, assuming weight parameters for the data are already written into the cell, and the memory is operating in multi-bank (PIM) mode.

Storing 512 bytes of FP8 activation data, it's first broken down into 16, 256-bit packets, which are written into each of the banks in and noted in the Source Register File.

A PIMX_RD reads the weight data from the DRAM bank, feeding into the MAC trees alongside the data from the SRF. Once the calculation is done, the output vector from each operation is written into the Vector Register File.

Once the calculation is done, a PIMX_WR command transfers the output data back to the DRAM bank. Samsung noted there doesn't need to be a 1:1 relationship between reads and writes, but it's useful for this example. With a VRF size of 1 kbit, a maximum of four calculations can be written to the VRF.

With the output written back to memory banks, the host just needs to read the data from memory. The host switches to single-bank (conventional DRAM) mode and executes 16 reads to gather the output from all of the memory banks.

Samsung LPDDR5X specs and preliminary performance

Samsung's LPDDR5X-PIM looks a lot like LPDDR5X. It uses a standard 561-ball array for packaging, just like LPDDR5X, and Samsung uses two 64-bit ranks with 16 GB modules. The critical number here is bandwidth. With LPDDR5X-9600, peak bandwidth is 76.8 GB/s, but that's increased by eightfold with PIM to 614 GB/s by reducing data movement and keeping basic logic local.

Samsung uses four dies per rank, for a total of eight dies. Not the various registers above, as well, as they're important for the illustration of data flow through Samsung's LPDDR5X-PIM memory.

In Samsung's preliminary benchmarks, LPDDR5X-PIM is impressive. In model run time, Samsung say a 2.28x improvement with PIM, and in tokens per second (TPS), PIM offered a 3.01x increase in performance.

The slide above shows what happened behind the scenes to gather these numbers, with Samsung using an edge AI accelerator — we're not sure which, but perhaps an early Gaia SoC — and testing Llama 3.1 with 8 billion parameters. Notably, the output is different, which one attendee pressed Samsung about. The company says optimizations are ongoing to improve accuracy, but it expects the performance benefit to remain the same.

One of the main advantages of LPDDR5X is right there in the name: low power. With PIM, power consumption becomes more of a concern, but Samsung says it doesn't expect higher power consumption overall compared to conventional DRAM. The presenter noted that peak power consumption will be "much higher" due to the bursty power draw of the PIM, but Samsung still expects overall power draw to be lower than conventional DRAM.

That comes down to extra reads/writes. Although PIM represents a power increase, decreasing the number of times data needs to move between DRAM and the host will lead to overall lower power consumption. "We're not having significant power increase," as Samsung's Karam Hwang put it.

LPDDR5X has, until recently, only had applications in consumer products. However, SOCAMM2 serviceable modules allowed Nvidia to use LPDDR5X as the memory of choice with its Vera CPU. And Intel uses LPDDR5X with its new Crescent Island AI accelerator.

Even with PIM, LPDDR5X doesn't come remotely close to the bandwidth with available with HBM, but it has a lot of applications elsewhere. Samsung's targets of server, client, and mobile are telling, with LPDDR5X-PIM accelerating edge AI on mobile and client devices, as well as arriving in lower-scope accelerators like Crescent Island.

Full Samsung Hot Chips 2026 presentation

Nvidia has told some of its largest customers that the prices of servers containing its AI chips will rise by more than 15% in many cases, Bloomberg reported on Saturday. The increases will take effect on Grace Blackwell and Vera Rubin systems shipping early next year, according to people familiar with the matter, who commented on communications that have not yet been made public. The size of each increase will depend on the chip generation and the memory configuration involved. Companies that build servers under contract for large data center operators, including Microsoft, Google, and Oracle, have recently notified their customers of the forthcoming increases, the people told Bloomberg.

This is another example of the so-called "RAMageddon" that's gripping the DRAM market, with contract prices having risen at record rates this year. Analysts projected that conventional DRAM contract prices would climb 58% to 63% quarter-over-quarter in Q2 2026, following a Q1 surge of 90% to 95%, as suppliers reallocated capacity toward HBM and server products. SK hynix said in October last year that it had already sold out its entire 2026 memory production capacity, and Samsung and SK hynix raised 2026 HBM3E supply prices by close to 20% before the year began.

AI systems carry enormous memory loadouts, with Nvidia's Rubin GPU shipping with up to 288GB of HBM4 per package, and the NVL72 rack-scale system combines 72 of those GPUs, putting more than 20TB of HBM in a single rack before accounting for the LPDDR attached to its Vera CPUs. With HBM production consuming roughly four times the wafer area of equivalent conventional DRAM, memory has become one of the largest line items in an AI server's bill of materials, and it's continuing to rise at a stratospheric pace.

Ironically, the supply crunch that's now inflating Nvidia's systems is the same one its demand helped to create. The three major memory makers spent this and last year shifting advanced nodes and new capacity toward HBM and high-capacity server DRAM, starving commodity markets in the process. Consumer DDR5 pricing has more than doubled since late 2025 as a result, with a mainstream 32GB DDR5-6000 kit selling for around $392 in August against $110 to $140 a year earlier, according to our RAM price tracker.

Nvidia has already passed rising costs through to consumers, raising prices on GeForce graphics cards earlier this month. The Bloomberg report indicates the same unrelenting pressure has now reached the top of the Nvidia stack, where hyperscalers as well as PC builders will be absorbing the increase. A 15% rise on rack-scale systems that sell for several million dollars each adds hundreds of thousands of dollars per rack across deployments that run to thousands of racks.

Nvidia runs a gross margin of roughly 75% non-GAAP, among the highest in the semiconductor industry, and the reported hikes indicate the company intends to pass memory cost inflation on to customers rather than absorb it, which it can more than afford to do. Meanwhile, supply of its accelerators from TSMC still can't meet demand, which limits buyers' immediate leverage.

Whether the increases push hyperscalers further toward AMD's accelerators or their own custom silicon will depend on how quickly those alternatives can absorb displaced demand, and all of them draw HBM from the same three constrained suppliers.

This week, Tom's Hardware Premium published a swath of new features, new roadmaps, and deep industry insights. And if you haven't subscribed to Tom's Hardware Premium yet, you'll have the opportunity to access our Hot Chips 2026 content for free for a limited time with a free Tom's Hardware account, no payment required.

With that out of the way, here's what you've been missing out on.

First off, PC components expert Joe Shields lays down the law when it comes to shopping for a new motherboard. Unless you've been living under a rock, you know component pricing has skyrocketed over the past 12 months. If your current motherboard has recently kicked the bucket, or if you're looking to change platforms, you don't want to overpay on a component that, in all likelihood, you'll never use to its full extent. With memory pricing the way it is, overspending on other components that are less crucial for juicing performance is a one-way ticket to spending too much on stuff you just don't need.

Within the article, Joe details exactly what you might want to pay for — and the things you don't need to focus on, like fancy 20+ phase MOSFET VRMs, or that slick RGB shroud, which pretty much just sits there looking pretty while other components do the real work. So if you're in the market for a new motherboard, or if you want to learn more about them in general, Joe's article is a fantastic, detailed read on exactly what you should be looking for, more important the reasons you shouldn't be splashing over $500 in the current market.

• How to choose a new motherboard without overpaying — scoping out the features you need, and what you might never use as component costs soar

With all of the hubbub around AI and massive gigawatt-scale data centers, focus has shifted from the not-so-humble supercomputer. In June, China's Lineshine officially became the world's fastest ... but does that really matter anymore, in an era where AI systems built for training and inference exist? That's the question columnist Chris Stokel-Walker poses for us in his latest Special Report, where he interviewed Julian Kinkel, professor of high-performance computing at the University of Göttingen and deputy head of high-performance computing at GWDG, and Jack Dongarra, one of the TOP 500 founders and emeritus professor at the University of Tennessee.

The outlook for traditional supercomputers, which are benchmarked using the High Performance Linpack benchmark (HPL), remains mixed, as compute workloads continue to diversify amid shifting trends and demands, splintering the supercomputer race.

• The supercomputer race no longer means what it used to, as rankings lose relevance in the AI era

This week's hardware roadmap examines the status of Samsung's global foundries, from the long-delayed Taylor, Texas, facility, all the way to the flagship Pyeongtaek facility and associated R&D complexes. We examine the status of each of the locations, in addition to what processes and products each focuses on. But all that glitters is not gold: We also review the foundry's yield woes and the pressure to deliver on its lucrative deal with Tesla to manufacture the company's AI6 chips.

The company remains a distant second to TSMC — at least in terms of foundry revenue — but the AI era is accelerating Samsung's products and roadmaps as the South Korean chaebol continues its efforts in the semiconductor fabrication market.

• Samsung's fab roadmaps examined — Taylor, Pyeongtaek, and the yield woes behind a $16.5 billion Tesla deal

In the news

The regular slate of analysis pieces on Tom's Hardware Premium this week has been dominated by headlines covering China, trade, and Chinese-made chips. While the blockade on Nvidia H200 chips has officially lifted, we explore how it might be too little, too late for Nvidia, whose market share in the region has plummeted as a result of relentless export controls.

In the company's place instead are homegrown suppliers, according to new reports. Both Western and Chinese companies are in a heated battle to develop the most powerful, most intelligent AI models. To that end, China's domestic heroes are poised to corner the market, according to new market intelligence.

To that end, SMIC, China's premier chipmaker, has posted a record $3 billion quarter and expects to hike wafer prices to contend with insatiable regional demand. Keep in mind, these successes come not from GPUs but other parts like logic ICs, BCD power management devices, and optical transceiver components.

• H200 AI GPUs finally reach China under case-by-case import licenses, but it's already too late for Nvidia
• China's homegrown AI accelerators to supply 90% of the country's domestic market, analysts suggest
• SMIC posts record $3B quarter and hikes wafer prices — US sanctions hand Chinese foundry a captive AI market

Speaking of optical components, which are one of the hottest commodities in the chipmaking industry, the market is set to explode, estimated to reach an eye-watering $144.4 billion by 2030. Driving those figures, according to China Insights Consultancy, is a hunger for co-packaged optics, photonics chips, transceiver modules, and new techniques, as copper traces and cables begin to reach their natural bandwidth limits.

• AI data center optical interconnect market to hit $144 billion by 2030, an over ten-fold increase from 2024 figures, according to new projections

This week, LG reportedly entered the chip packaging business, shipping a Laser Direct Imaging (LDI) tool, a maskless machine especially designed for patterning interconnects. This marks LG's first foray into the advanced packaging arena. The LDI machine trades resolution for pure throughput, which is incredibly welcome. While the LDI machine has reportedly been shipped to an OSAT, it remains new to the arena, and it'll likely take the South Korean company years to firmly establish itself as a reliable toolmaker.

• LG enters chip packaging arena with Laser Direct Imaging machine, as TSMC's CoWoS remains constrained

With that, we'll see you next week for a bumper Hot Chips edition of this digest. I've seen the schedules and anticipate some incredibly insightful pieces coming out of the show. For now, if you'd like to read any of the articles above and to gain access to Bench, you'll need to purchase a subscription. Your support goes a long way in helping us to publish deeper, more insightful stories that might otherwise fall outside of our regular areas of coverage.

ChangXin Memory Technologies (CXMT), China's largest maker of dynamic random access memory (DRAM), planned to obtain Samsung's IP related to its memory process technologies in a bid to develop its own production nodes, according to testimony given in a South Korean criminal case involving leaked Samsung technology, reports Maeil Business. The company's managers allegedly had no intention to develop an in-house process technology from scratch, so obtaining IP from Samsung was a strategic decision.

The intention was a key part of CXMT's business plan rather than an opportunistic attempt to acquire Samsung's technology after the start of its own DRAM process development, according to the testimony of a former Samsung engineer identified as Jeon, who worked at Samsung for 28 years before jumping ship to CXMT sometimes around 2016. This April, Jeon was sentenced to seven years in prison for illegally obtaining a 600-step Process Recipe Plan (PRP) information concerning Samsung's DRAM fabrication processes in general and the 18nm-class node in particular.

"From the beginning, CXMT CEO and CTO tried to develop DRAM by stealing Samsung Electronics' Process Recipe Plan (PRP) information," Jeon told the court this week, according to Maeil Business. "CXMT had no research institutes or facilities at the time of its establishment, and had no intention of developing technology through its own research."

Copying the recipe does not automatically give you a working process. Nonetheless, a detailed process recipe can dramatically shorten development of any production node because it reveals things like the sequence of steps, deposition or etch conditions, anneals, cleans, implant parameters, temperatures, pressures, tool types, and so on. For a memory process, a ready process recipe can remove a huge amount of trial-and-error and reveal how the process integration is supposed to work. Meanwhile, even to ensure that the recipe works as intended, one needs to obtain the same or compatible tools as well as adjust their characteristics accordingly.

However, while a process recipe can potentially help to ramp any fabrication technology, a process recipe itself does not necessarily reveal the complete transistor architecture or physical design. For that, perpetrators also want things like cross-sectional structures, masks/layout information, design rules, device dimensions, capacitor geometry, process window, and so on. Such details are not easy to get for a brand-new fabrication technology, but they can be obtained by reverse engineering of shipping products. By combining process recipe with reverse engineering, experienced DRAM engineers can reconstruct much of the technology. Meanwhile, process integration engineers can save years of trial-and-error with actual fab tools.

Normally, it takes DRAM companies around 3 – 5 years to design a process node from device development to yield ramp. For a new player, development time from scratch will probably be around five years rather than three unless pre-competitive IP is licensed or certain heavy-lifting is done elsewhere. In fact, the Maeil Business report claims it took Samsung five years to develop its 18nm-class node.

Meanwhile, CXMT began mass production of DDR4 SDRAM in 2019 using a 22nm-class node. Mass production of memory using a 18nm-class process technology began in 2023. Such a timeline raises a question of whether CXMT's 22nm-class G1 was derived/adapted from the knowledge of Samsung's process technologies and/or their process recipes, the more advanced 18nm-class node, or did the allegedly obtained Samsung IP primarily help CXMT develop the later 18nm generation? In any case, there is a court ruling that CXMT stole IP from Samsung to boost its own memory production capability.

Samsung raised prices on new orders across its 4nm, 5nm, and 8nm foundry processes in July, with increases reaching 15% for customers in China and the U.S., Reuters has reported, citing two people familiar with the matter. Chinese chip designers, cut off from advanced chipmaking tools by U.S. export controls, are accepting the largest hikes, and Samsung's 4nm line at Pyeongtaek has reportedly been running at full capacity since late last year. The increases come not too long after Samsung cut its 2nm wafer price to $20,000 in a reported attempt to undercut TSMC by roughly a third.

Customers in China and the U.S. saw quotes for the 4nm SF4 process climb 10% to 15% from June, while customers in Taiwan saw smaller increases of 5% to 10%, one source said. Wafers on the 5nm SF5 process rose 10% to 15%, and the 8nm node went up by close to 10%. Samsung declined to comment on the report.

Chinese orders now exceed what Samsung can take on because U.S. customers get served first and a slice of capacity stays reserved for Samsung's own silicon. This captive demand situation isn't new, with the Financial Times reporting last year that Samsung's chip exports to China grew 54% between 2023 and 2024, including a deal that supplied Baidu's Kunlun with more than three years' worth of logic dies for AI accelerators.

The Pyeongtaek SF4 line builds logic chips for Qualcomm alongside the base dies underneath Samsung's own HBM stacks, meaning external foundry customers compete for wafer starts with Samsung's memory division, the business that drove its record profits.

Counterpoint put Samsung at 7% of global foundry revenue in Q1 2026 against more than 70% for TSMC, but that gap is doing Samsung a favor on pricing: TSMC's leading-edge capacity is booked out by AI orders, and the market leader notified customers of 5% to 10% increases across all sub-5nm nodes starting in January, with some services reportedly rising around 25% in 2027. Samsung is raising prices beneath that umbrella and still landing below where TSMC's quotes are headed.

Samsung's foundry division has been loss-making since 2022, and Lee Min-hee, an analyst at BNK Investment & Securities, told the wire service that if Samsung keeps raising prices, "its foundry business could potentially become profitable as early as next year." The customer list backing that forecast has grown over the past year, spanning Tesla's $16.5 billion AI chip contract, an Apple manufacturing deal, a Broadcom AI chip agreement, and Nvidia's inference processor.

Divided across two countries and four campuses, Samsung's foundry roadmap runs from the Korean bases at Pyeongtaek, Hwaseong, and Giheung to the new U.S. site at Taylor. Samsung began mass-producing its first-gen 2nm process in 2025, moved equipment into its long-delayed Taylor, Texas fab in April this year, and lined up Tesla's AI6 processor under a $16.5 billion contract signed in July 2025, yet none of it has closed the gap with TSMC.

Samsung confirmed the 2nm milestone in its fourth-quarter 2025 results, the same release in which it returned its foundry unit toward profitability on the back of HBM4 logic-die orders. The unit still trails TSMC roughly 11:1 by revenue, and 2nm yields are reported to be sitting near 55%, below the threshold the business needs to run advanced nodes at a profit.

What separates Samsung from TSMC isn't fabs or customers but yield, and Samsung has been able to absorb the cost of that gap because its foundry unit sits inside the Device Solutions division alongside a memory business posting record profits. The company reports no standalone foundry P&L, which has given the operation years of runway that a pure-play foundry wouldn't have the benefit of.

Taylor, Texas

Samsung's Taylor project is both the centerpiece of its roadmap and the company's longest-running headache. The full campus, covering two fabs, an advanced packaging facility, and an R&D center, has been reported at around $44 billion, with the portion tied to U.S. funding set at over $37 billion. Samsung's CHIPS Act award was revised down from up to $6.4 billion to up to $4.745 billion as the project's scope narrowed, with Texas adding roughly $250 million in state incentives in September last year.

Construction stalled through 2024 and into 2025, with reporting at the time attributing the halt to an absence of committed customers and yield problems on the node the fab was meant to run. Samsung held an equipment move-in ceremony in April, and the site is now set to install a third-gen SF2P+ variant of its 2nm process, with trial production targeted by the end of 2026, full mass production in 2027, and a capacity goal of around 50,000 wafer starts per month. The facility's anchor tenant is Tesla, whose AI6 chip Samsung will build at Taylor under the eight-year deal running through 2033. Tesla's AI6 has reportedly slipped by around six months, tied to a delayed engineering run on Samsung's 2nm line, pushing volume toward late 2027.

Pyeongtaek

Pyeongtaek remains Samsung's largest production base, built out across a series of lines designated P1 through P5. In the near term, activity at Pyeongtaek centers on P4, where Samsung has pulled forward equipment move-in and is reported to be installing an HBM4 base-die line on its 1c-class DRAM, and on P5, the final planned fab at the site, where construction had been halted and is now reviving on the strength of AI memory demand. The P5 buildout carries a reported total investment of nearly 90 trillion won and a 2029 production target, according to Korean trade press.

The Korean expansion runs against a backdrop of capex restraint. Through 2024 and 2025, Samsung was reported to have cut foundry investment sharply and to have reviewed pausing both Pyeongtaek and Taylor work as losses mounted, with foundry utilization sitting around 50% in the second half of 2024 before recovering as clients returned.

Hwaseong and Giheung R&D

Process development runs out of Hwaseong's EUV line. The newer Giheung NRD-K research complex, a roughly 20 trillion won investment running to 2030 and dedicated to advanced-node R&D. Samsung deployed an ASML High-NA EUV research tool, the Twinscan EXE:5000, at Hwaseong for process development, and was understood to be buying two mass-production-class EXE:5200 systems — with the second originally being due to arrive in the first half of this year — aimed at the SF1.4 node and next-generation DRAM.

On the logic side, that plan has since shifted: Samsung's updated roadmap keeps SF1.4 on Low-NA tooling and reserves High-NA for the 1nm generation. Given that this research base feeds the production fabs, its output will now set the pace for how quickly Samsung can stabilize 2nm and move to 1.4nm.

The processes

Samsung's 2nm family runs from the first-generation SF2, now in mass production, through SF2P this year, the SF2P+ variant headed to Taylor, and SF2Z, which adds backside power delivery and is planned for mass production in 2027. The 1.4nm node, SF1.4, was originally targeted for 2027 mass production when Samsung announced it at the 2022 Foundry Forum. That date is now officially 2029, per an updated roadmap Samsung presented at the 2026 Next-Generation Lithography + Patterning Conference in August, which commits the company to three more years of refining the SF2 family before moving down a node.

The same presentation gave Samsung's first confirmation of where High-NA EUV enters production: not at 2nm or 1.4nm, but with the 1nm-class SF1A node around 2030. "We believe High-NA EUV will become necessary from A10 and below," Chang Min Park, Master VP of Technology at Samsung Electronics, told the conference, saying the tooling needs further improvement before it can carry mass production at larger nodes. SF1A is slated to run alongside SF1.4+, an enhanced 1.4nm variant that stays on proven Low-NA flows, so customers wary of High-NA's smaller exposure field and higher cost will have a fallback on familiar tooling.

As always, roadmaps live and die by their yields, and Samsung's is no exception. The company's first-gen 2nm yields were reported as climbing through 2025, but as of April, they still sat near 55%, below the level the business needs for profitable high-volume output, with reporting suggesting Qualcomm could route work back to TSMC as a result. These figures are obviously estimates rather than Samsung disclosures, and they've varied across sources, but they're consistent enough to say that yield — not capacity or customers — is Samsung's biggest constraint with 2nm.

To compensate, Samsung has been pulling back aggressively on price to stay competitive. The company is reported to have cut its 2nm wafer price to around $20,000, undercutting TSMC by roughly 33%, a discount that'll no doubt win price-sensitive work but compress the margin on a node already running below break-even yields. Undercutting on price while trailing on yield is a difficult combination to fund, which is why the unit's losses have set the pace of its recovery.

Exynos and external customers

Samsung's anchor customer on 2nm is its own mobile chip unit. The Exynos 2600, built on SF2, is the node's first commercial product and powers the standard Galaxy S26 and S26+. However, the Galaxy S26 Ultra runs Qualcomm's Snapdragon SoCs worldwide, and the Exynos reportedly covers only around a quarter to a third of S26 builds because yields cap how many it can supply.

A successor, the Exynos 2700 on SF2P, is in development for the Galaxy S27, with mass production targeted for the second half of this year. Samsung using its own processor to prove a node before committing to external customers is the same play we saw the company run at 3nm.

Externally, 2nm customers remain thin. The clearest to date is Japanese AI firm Preferred Networks, which Samsung confirmed as a turnkey customer for SF2 plus 2.5D packaging on AI accelerators. Tesla's AI6 is obviously the biggest name, and there are reports of a 2nm CPU order from a North American fabless customer identified as AMD and of advanced-stage talks with Qualcomm over Snapdragon work, though neither is confirmed.

HBM4

The strongest case for Samsung's integrated model sits in memory rather than logic. The company said it shipped the industry's first commercial HBM4 in February this year, running at 11.7 Gbps per pin against the 8 Gbps JEDEC baseline and extendable to 13 Gbps, with per-stack bandwidth up to 3.3 TB/s. The logic base die under that stack is built on Samsung's own 4nm foundry process, which lets the company source the base die in-house rather than buying it from TSMC as some rivals must, and it's reported to be moving the base die for custom HBM to its 2nm process for samples in 2027.

That capability has translated into qualification, with Nvidia CEO Jensen Huang confirming in June that Samsung, SK hynix, and Micron had all passed certification to supply HBM4 for the Vera Rubin platform. Samsung is still the smaller supplier, with analysts putting SK hynix at roughly two-thirds of Nvidia's HBM4 allocation and Samsung in the mid-20% range. Still, qualification of all three vendors ends the period when Samsung was locked out of Nvidia's top memory tier.

Samsung has also moved early on the next step, having begun shipping HBM4E samples around May, claiming roughly 3.6 TB/s of bandwidth, and is positioning custom HBM with logic-based dies tailored to individual accelerator customers, including Nvidia, AMD, Broadcom, and hyperscalers, with samples due in 2027. SK hynix followed with its own HBM4E samples weeks later, so although the lead is measured in weeks rather than generations, memory is the part of Samsung's business where it competes at the front rather than from behind.

Firmly in second place

Samsung has reshuffled its foundry leadership twice in a year, naming Han Jin-man to head the business in November 2024 and restoring a dual-CEO structure over the Device Solutions division in November 2025, with Jun Young-hyun over the DS division and Roh Tae-moon added as co-CEO.

The reshuffles followed a stretch in which foundry and System LSI losses were put by analysts at 3.18 trillion won for 2024, before reportedly narrowing below 1 trillion won by the third quarter of 2025 as utilization recovered from around 50% in late 2024 toward roughly 80% in early 2026. Chairman Jay Y. Lee has publicly ruled out spinning the foundry off to address the conflict that running it alongside the Exynos design unit creates for fabless customers, saying the company intends to grow the business rather than separate it.

The spending behind that recovery is massive, with Samsung having guided to more than 110 trillion won in combined facilities and R&D investment for 2026. The Device Solutions division is taking the bulk of a 10.2 trillion won first-quarter capital outlay, and Taylor ramp investments are set to rise from the second quarter onward. Ultimately, the company is funding an advanced-node buildout on both sides of the Pacific while the unit that runs those fabs is only now climbing back toward break-even.

In Q4 2025, TrendForce put TSMC's foundry revenue at $33.7 billion against roughly $3.4 billion for Samsung's foundry unit, leaving Samsung second with around 7% of the market. By Q1 2026, the same source had TSMC at $35.86 billion and Samsung near $3.2 billion, a gap of roughly 11 to one. Samsung is reported to be targeting foundry profitability by 2027, and a 20% market share, and its own 2026 guidance promises double-digit revenue growth and improved profitability driven by advanced nodes. The company is also reported to be reviewing a second Taylor fab and moving foundry leadership closer to its U.S. customers, a sign it's planning for the demand it hasn't yet converted.

Whether that holds depends on the same metric that has dogged the Taylor launch and the Tesla schedule. SF2 mass production and a marquee customer are both in place; what closes the distance to TSMC, or fails to, is yield reaching the level that makes a $44 billion fab and a $16.5 billion contract pay for themselves.

Since the advent of fixed-pixel flat panel displays, the quest for greater pixel density has not subsided. In times past, a high-res display was 1280x1024 with a 4:3 aspect ratio. Now the gold standard is 4K, 3840x2160. So, where do we go from here?

Traditionally, resolution increases in whole multiples like 1920x1080 to 3840x2160. And there are a few 8K 7680x4320 screens out there. But in the realm of the best gaming monitors, you can have any resolution you want, so why not 6K?

Samsung’s Odyssey G80HS is a 32-inch IPS panel with 6144x3456 pixels at 165 Hz and 3072x1728 pixels at 330 Hz along with Adaptive-Sync, HDR10, and wide gamut color. Pixel density is an impressive 224 or 112 ppi. Let’s take a look.

Samsung Odyssey G80HS Specs

I’ll start with the caveat: the G80HS requires the latest port specification, DisplayPort 2.1 or HDMI 2.1, to run in 6K at 165 Hz. You’ll also need an HDMI cable rated for 48 Gbps, or a DisplayPort cable rated for 80Gbps. You’ll also need a GeForce RTX 5090 to even dream of running over 120fps in 6K. That’s where the dual mode function comes in. Though 3072x1728 is unusual, it is a realistic task for an RTX 5090 or an RTX 4090 to move things along at 240 fps or more. That 330 Hz refresh rate is handy to have.

The panel uses Fast IPS technology with a claimed 1ms response time. It includes Adaptive-Sync and overdrive, but you can’t have both at the same time. I’ll talk more about that later. The good part is that input lag is extremely low, so gamers will get a responsive experience. And running at the higher refresh rate eliminates nearly all motion blur.

The panel doesn’t employ Quantum Dots but manages to cover just over 90% of DCI-P3 with solid out-of-box accuracy. With a few tweaks, I saw reference-level color, gamma and grayscale tracking. The G80HS also has an equally accurate sRGB mode for graphics pros, photographers, and users who want the correct BT.709 color space for SDR content. HDR10 signals are supported as well with expanded contrast and peak white levels around 480 nits.

The G80HS is clearly a gaming monitor with extras like LED lighting, aiming points and game-specific picture modes. You get all the latest video ports too with DisplayPort 2.1 and two HDMI 2.1 inputs. There are USBs for peripherals and a 3.5mm headphone jack. The only thing missing are internal speakers.

Bleeding-edge resolution doesn’t come cheap, but the G80HS isn’t super pricey either at $1,599 to start. Let’s see how it performs.

Assembly and Accessories

The G80HS arrives packed in crumbly foam with a base, upright, and panel that assembles easily, no tools needed. A medium-sized power brick with right-angled cords provides the alternating current, and you get very thick HDMI and DisplayPort cables which are rated for 48 and 80 Gbps respectively.

Product 360

The G80HS has a minimalist aesthetic with only a tiny Samsung logo on the front bezel. The rest of the frame is flush and thin. Coupled with a very slim side profile, one might think they’re looking at an OLED. Internal bits are packed into a central bulge which has generous ventilation. The stand’s fulcrum is ringed by an LED that can play a variety of effects and colors.

The stand is substantial with firm movements and generous adjustments. You get a five-inch height range plus 2/25 degrees tilt and 30 degrees swivel. There’s a 90-degree portrait mode as well. The base has a medium footprint and brings plenty of stability. I noted that the fulcrum had a little wobble when adjusting tilt and rotation.

The screen has an effective anti-glare coating with a matte finish. It is grain-free and provides excellent clarity for the extreme 224ppi pixel density. You’ll need a magnifying glass to see any dot structure from any distance. Sharp and smooth is almost an understatement.

The I/O panel includes a DisplayPort 2.1 and two HDMI 2.1 ports. All of them can manage 6K resolution at 165 Hz if your video card has DisplayPort 2.1 or HDMI 2.1 outputs. USB 3.2 ports are also included, one upstream and two downstream.

OSD Features

The G80HS has a super-efficient OSD that’s controlled by a joystick. A quick menu pops up on the first press, then you click up and select to see the full menu.

Samsung’s gaming monitors all have this cool control-panel-looking menu with signal info at the top in little portholes and a tree-style menu. The G80HS has four sub-menus starting with game options. You can toggle Adaptive-Sync, which is good because if you want overdrive, it must be turned off. This is an unusual choice because at 165fps, you’re going to want both things. The choice is less motion blur or no frame tears. And that will depend on game type. I’ll talk more about that below.

The Dual Mode option switches between 6K at 165 Hz and 3K at 330 Hz. Given my experience, users will be using the 3K mode more often for twitchy shooters and the 6K mode for less frenetic titles. For aiming help, you get two different reticles. And the lighting, called Infinity Core, can play different colors and effects through the LED ring in the back. CoreSync lets you sync the light show with what’s happening on the screen.

The Picture menu starts with 10 picture modes, with Graphic being the default and best choice for all-around gameplay and productivity. It leaves calibration controls accessible and has an Auto color space option which selects sRGB for SDR and DCI-P3 for HDR. This is something I wish more wide-gamut monitors had. For adjustments, you get gamma presets and a very precise set of RGB sliders.

To enhance contrast, there are three different options: Local Dimming, Contrast Enhancer, and Dynamic Brightness. Local Dimming is a bit misleading because the G80HS is not a full-array panel. And tests showed me that it doesn’t do zone-edge dimming either. The best of the three for expanding dynamic range is Dynamic Brightness. That will deliver almost 15,000:1 contrast versus the panel’s native ratio of around 1,700:1. In HDR mode, you can opt for dynamic tone mapping, which improves the image in most cases. I noted that in testing, the Static mode produced reference-level accuracy. You can read more about that on page five.

Samsung Odyssey G80HS Calibration Settings

The G80HS is close to standard out of the box and will display its full native color gamut, 90% of DCI-P3, for both SDR and HDR content. The Picture menu has a single-point RGB control which is very precise. I used it to tighten up grayscale tracking. Gamma is nearly perfect on the zero setting. If you want sRGB for SDR content, change the Color Space option to Auto. Then the monitor will switch back and forth automatically. My recommended settings are below. I noted that I could adjust the RGB sliders independently for HDR mode, and as it turned out, the same settings worked. This is something very few HDR monitors allow.

Gaming and Hands-on

Gaming on the G80HS was a unique experience. On the positive side, it’s the first dual-refresh monitor that I can call truly useful because its resolution only reduces to 3072x1728, which equates to 112 ppi, a tad more than a 27-inch QHD screen. And my GeForce RTX 4090 ran it at around 250 fps, which eliminated any need for Adaptive-Sync or overdrive.

This was fortunate because, as I discovered, playing in HDR mode grays out both options. In essence, you get no video processing with dual mode engaged, but don’t be dismayed. Motion resolution was superb, and the G80HS was super responsive to control inputs. You’ll see why when you read the input lag test results on the next page.

Playing in 6K was not as fun with my setup. An RTX 4090 is fine for 4K where I can get speeds over 200fps. But at full resolution, I could barely crack 100 fps. And with Adaptive-Sync and overdrive out of the picture, motion was just too blurry. There was no hit to input lag; control response was instantaneous. But it was hard to aim precisely at distant targets because unless I stopped moving, enemies were too difficult to make out.

Gameplay experiences aside, the G80HS is gorgeous to look at. With 224 ppi, the picture is uncannily smooth. I could not see the pixels even with my nose next to the screen. Though 4K looks very film-like and realistic, 6K is even more so. It amps up my anticipation and desire for 8K, which will inevitably be a thing within my lifetime.

Working on documents and graphics is such a pleasure when detail and clarity are this high. Though I usually crow more about contrast… Oh wait, the G80HS has a good deal of that. True that it’s IPS, but it delivers around 1,700:1 natively and almost 15,000:1 with Dynamic Brightness engaged. Though it isn’t quite in OLED territory, it is visibly superior to the average LCD panel, and that includes Mini LED monitors with their full-array backlights. The G80HS’s HDR is particularly excellent with balanced color, perfect luminance tracking, and peak highlights around 480 nits.

Takeaway: Though the G80HS’s resolution is somewhat of an “in-between” proposition, there’s no denying its appeal. 224ppi is serious pixel density, and it manifests itself as a super smooth and lifelike picture. Coupled with excellent contrast and pro-level color accuracy, it delivers a truly useful dual-refresh feature where you can play at 330fps at 3K resolution, which equates to 112ppi. So, if you can’t drive it at 6K/165 Hz yet, you can still enjoy it until the next generation of premium video cards comes to market.

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To compare the G80HS’s performance, I’ve mined the highest resolution gaming monitors in my database. They are AOC’s U27G4XM and U32G4, ViewSonic’s VX2730D-4K, KTC’s H27P3, and Asus’ XG27JCG. None are 6K, but the KTC and Asus are 5K (5120x2880) and the rest are 4K (3840x2160).

Pixel Response and Input Lag

Click here to read up on our pixel response and input lag testing procedures.

The Asus was tested before my acquisition of the Nvidia LDAT, so it has been omitted from the response chart. The remaining screens are very close in speed except for the 60 Hz KTC, which is slower for obvious reasons. The G80HS is slightly behind the top three but not enough to make a visible difference. The only consideration is that you’ll need to choose either overdrive or Adaptive-Sync; you can’t have both at once. Overdrive has a tad less motion blur, but there are some frame tears.

In the lag test, the G80HS takes the crown by a significant margin at 165 Hz. Surprisingly, 330 Hz is actually slower. I can only conclude that there is some processing overhead from scaling down to a non-native resolution. Again though, this is an invisible difference. The benefit from 330 Hz is that you get almost no motion blur and you can use Adaptive-Sync because overdrive is unnecessary.

Test Takeaway: The G80HS is a very quick monitor at either 165 or 330 Hz. Running at 6K comes with some motion blur since you can’t use overdrive when Adaptive-Sync is turned on. It also takes more horsepower than a GeForce RTX 4090 provides to even approach 165 fps in a game. 330 Hz comes with decent pixel density and much smoother motion resolution because you don’t need the overdrive, which leaves Adaptive-Sync available. Either way, input lag is lower than other 4K and 5K monitors running at 120 to 160 Hz.

Viewing Angles

The G80HS shows its IPS roots with a slight green tint in the 45-degree horizontal view. This is offset by excellent gamma and brightness retention, as in there is no change in luminance. It’s one of the best IPS panels I’ve seen for off-axis image quality. The top view retains most of its brightness, but gamma is reduced, and there’s a green tint.

Screen Uniformity

To learn how we measure screen uniformity, click here.

My G80HS sample showed minor hotspots in the corners of the screen, which took its average deviation above the 10% threshold. This was difficult to spot in most content, but I could see a little glow in the darkest material. This is a sample-specific issue.

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To read about our monitor tests in-depth, please check out Display Testing Explained: How We Test PC Monitors. We cover brightness and contrast testing on page two.

Uncalibrated – Maximum Backlight Level

Many of the G80HS’s closest competitors have Mini LED backlights and are capable of high peak brightness. But 431 nits is nothing to complain about for SDR content. This was measured from a full field pattern with all dynamic contrast options turned off. Trying different combinations of the three settings, I found that turning Dynamic Brightness on produced the highest peak from a 25% window pattern, 470 nits with a contrast ratio around 14,500:1. But the native ratio of 1,662.8:1 is well above the IPS average. This is excellent performance.

After Calibration to 200 nits

The G80HS has a very low black level after calibration, and I saw a small increase in contrast to 1,706.1:1. The IPS average is 1,000:1, so all the screens except the U27G4XM are overachievers.

The ANSI result is reasonably consistent at 1,308:1. This is partially affected by the corner glow I noted earlier, so other G80HS samples might have a higher intra-image result. This is still excellent performance that is above the IPS average.

Test Takeaway: The G80HS has more contrast than most IPS monitors with around 1,700:1 after calibration. Dynamic Black can take that to over 14,000:1 with peaks of 470 nits if you’re looking for extra punch for games and video. My sample showed slight uniformity errors, so its ANSI score was a bit lower but still above the IPS average.

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The G80HS ships in its Graphic mode, which is backed by a factory calibration report. It doesn’t need to be calibrated, though some slight gains will come from a few tweaks.

Grayscale and Gamma Tracking

Our grayscale and gamma tests use Calman calibration software from Portrait Displays. We describe our grayscale and gamma tests in detail here.

Only the 90 and 100% brightness steps crack the 3dE threshold. That’s the point where errors become visible, though there are very few users who would spot a problem in either test patterns or actual content. Gamma is almost perfectly aligned with the 2.2 reference. This is excellent out-of-box performance.

Calibration of the very precise RGB sliders brings all grayscale errors to below 2dE, which is as good as it gets, even in the pro-monitor category. Gamma remains almost perfect at 2.23. It doesn’t get much better than this.

For the sRGB test, I had already calibrated the G80HS, so it measured just as excellently. This is one of the rare displays that lets you calibrate outside its native gamut mode. Just set Color Space to Auto and it will use sRGB for SDR and native (DCI-P3) for HDR. This is something that all wide gamut monitors should do, but most will gray out the RGB sliders in sRGB mode.

Comparisons

With a score of 1.98dE out of the box, the G80HS does not need to be calibrated. It’s ahead of many other gaming monitors in this test. With a few tweaks of the precise RGB sliders, the error drops to 0.99dE, pro monitor territory. That’s impressive, as is the score of the four other monitors, which are even lower. This is more for ego than anything else. Visually, you won’t be able to tell a difference between any of the six screens once they’ve been calibrated.

The G80HS is a poster child for gamma accuracy. Grayscale can be fixed, but nearly all computer monitors only allow wholesale changes to gamma; there’s rarely a way to fix errors at specific luminance points. When you have only a 0.10 range of values, and the average is 2.23 (1.36% deviation), you’ll see clear detail and texture in all parts of the image. And it improves gamut accuracy too because hue and saturation points are closer to their targets.

Color Gamut Accuracy

Our color gamut and volume testing use Portrait Displays’ Calman software. For details on our color gamut testing and volume calculations, click here.

The G80HS achieves decent gamut accuracy out of the box in Graphic mode. You can see slight undersaturation in red and green, which lets you know that Quantum Dots are not present. But there’s a little bonus blue which makes the sky a little more brilliant. Only slight hue errors in magenta mar an otherwise solid chart.

Calibration not only aligns the magenta hue, but it also improves red saturation. Though the change to grayscale is invisible in neutral patterns, it has a visible effect on color, so it’s worth making the adjustments.

On the sRGB chart, you can see a bit of over-saturation in red, magenta, and blue, but not enough to take the G80HS out of contention as a color-critical-qualified display. With a low 1.15dE error, it can work in a video post-production or photography editing suite.

Comparisons

All the screens score well in the color test, with the G80HS coming in fifth place at 1.91dE. This is well below the visible threshold, so in a side-by-side comparison, all the monitors will look similar. The difference is more one of color volume rather than accuracy. The top three screens have visibly more color, which is most visible in the brightest red and green hues. If you view a lot of HDR content, you can’t have too much color volume. But the G80HS does well without the added expense of Quantum Dots at 90.32% coverage of DCI-P3. And its 102% score for sRGB is near-ideal.

Test Takeaway: The G80HS is accurate enough to be used without calibration, but there are some gains to be had from a grayscale adjustment. Gamma is nearly perfect in either case. There are more colorful screens in the category, but among non-QD displays, the G80HS is very competitive.

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Our HDR benchmarking uses Portrait Displays’ Calman software. To learn about our HDR testing, see our breakdown of how we test PC monitors.

The G80HS supports HDR10 signals with an automatic switch. Unusually, in a good way, it leaves the RGB sliders accessible so you can create an independent calibration if you wish

HDR Brightness and Contrast

Without the advantage of a full-array Mini LED backlight, the G80HS isn’t as bright as some others, but it is brighter than average. Most edge-lit screens manage around 400 nits for HDR content. The G80HS gives you a couple of options for dynamic range. Natively, it will render around 1,700:1, but with Dynamic Brightness on High, it tickles the underside of 15,000:1, a nearly tenfold increase. I measured this with a 25% window pattern in, oddly enough, the HDR Eco mode. Trying the other modes brought no increase in output. In the comparison chart, the Asus shuts the backlight off in its brightest HDR mode when a 0% signal is input, so I couldn’t measure its contrast. The G80HS is one of the better edge-lit LCDs I’ve tested for HDR contrast.

Grayscale, EOTF and Color

The G80HS’s HDR color accuracy is even more impressive. Though I give a free pass to nearly every HDR monitor with over-saturated color, because they look good anyway, I must commend Samsung on its ultra-precise HDR. The grayscale chart is excellent with no visible errors. I did make a couple of tweaks to the RGB sliders, but the default test also had no visible errors. The EOTF is also spot-on with only tiny variations from the reference line.

In the color test, every point on the DCI-P3 chart is on target except for the 100% saturations of green, blue, and cyan, which are off by around 5%. This isn’t surprising given the lack of Quantum Dots. On the BT.2020 chart, the G80HS runs out of color at 85% red, 70% green, and 95% blue. While one might think this approach would be less colorful, it is more balanced and detailed than a monitor that simply pushes everything 5-10% higher. This is excellent performance.

Test Takeaway: The G80HS has some of the best and most accurate HDR color I’ve ever experienced, both in tests and in actual content. The balance is such that pushing saturation points as other monitors do becomes unnecessary. It isn’t as bright as a full-array Mini LED screen, but it is a bit brighter than most edge-lit displays. The Dynamic Brightness option delivers a nice contrast bump from 1,700:1 to almost 15,000:1 without any loss of detail.

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The quest for higher resolution and pixel density is unlikely to end any time soon. We might have been satisfied with Full HD for a time, but the lure of 4K, 5K, 6K and 8K is strong. 8K is still an exotic technology that will someday be more common on the desktop, but not today. For now, we have the in-between.

Since PCs and Macs can render any resolution the user wishes, monitors like Samsung’s Odyssey G80HS will be relevant. Greater pixel density is always a good thing, and this screen boasts 224ppi at 6K and 112ppi at 3K. And that dual refresh feature is super important because this monitor’s capabilities go beyond those of the current crop of top-shelf video cards. Though I found too much motion blur at 6K and 100fps, the experience in 3K and 300fps was excellent.

I was a bit dismayed that Adaptive-Sync and overdrive couldn’t be used together. But playing in 3K mode negated any need for either feature. The G80HS has impressively low input lag, so its gaming prowess is equal to the best competition monitors I’ve reviewed. I was also impressed by its accurate color, both out of the box and after calibration. The ability to switch color spaces automatically between SDR and HDR was a major plus. And though it uses an IPS panel rather than an OLED, it boasts impressive contrast of 1,700:1 native and almost 15,000:1 with an effective set of dynamic options.

Since 8K is still something of a unicorn, I can easily recommend a 6K monitor like the G80HS. It delivers superb imagery, speedy game performance, flexibility, and Samsung’s usual solid build quality. If you want to venture into the realm of extreme pixel density, definitely check it out.

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The PCIe 6.0 specification was ratified in early 2022, but its actual implementation was delayed for years. Now, the spec is almost ready, with the first PCIe Gen6 platforms finally approaching, as are actual storage devices. Micron was the first with a PCIe 6 SSD in mid-2025, and Samsung caught up this July. Meanwhile, independent makers of SSD controllers — Marvell, Phison, and Silicon Motion — are also prepping their PCIe 6 SSD platforms.

For a full roadmap of PCIe, you can check out our dedicated page. In this article, we'll specifically focus on PCIe 6.0 controllers and devices and how they're soon becoming commercial products. For additional reading, you can also find our interview with Solidigm VP Avi Shetty, which covers the subject of PCIe 6.0 SSDs.

Per ardua ad astra

PCIe 1.0 through 5.0 used simple NRZ signaling (one bit per signal) with 128b/130b encoding, which was relatively simple to implement at the controller level. However, it required some complicated methods to ensure signal integrity at 32 GT/s per lane.

PCIe 6.0 now adopts PAM4 signaling (which encodes two bits per symbol using four voltage levels), which keeps the physical signaling rate at 32 Gbaud. However, it also doubles the effective transfer rate to 64 GT/s by transmitting two bits per signal instead of one. As a result, transmitter and receiver design became considerably more complicated, as it required sophisticated DSPs, equalization, FEC, and CRC-based retry mechanisms, which complicated the development of PCIe 6.0 controllers. Furthermore, PCIe 6.0 often requires retimers where PCIe 5.0 did not, which complicated the development of actual servers.

To make matters even more complicated, every new PCIe generation requires interoperability testing among CPUs, GPUs, SSDs, network cards, switches, retimers, and other devices from dozens of vendors. Since PAM4 behaves very differently from NRZ, PCI-SIG had to develop entirely new compliance procedures, test equipment, and interoperability programs. The development of those programs themselves slipped, which greatly delayed any commercial deployment. The very first PCIe 6 interoperability testing at 64 GT/s took place in late July.

Despite formidable implementation hurdles and interoperability program challenges, PCIe 6 is finally making its way into commercial platforms. AMD's 6^th Generation EPYC 'Venice' and Nvidia's Vera CPUs fully support PCIe Gen6, so companies from the adjacent industry sectors are catching up with their PCIe 6 products, and storage makers are among them.

For storage, PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link without the protocol's overhead (which is not that big with the 1b/1b 242B/256B FLIT encoding featured by PCIe 6). The new interconnect does not improve flash operation on its own. Meanwhile, PAM4 introduces Forward Error Correction (FEC), which slightly increases latency, but it also enables doubling throughput without doubling the signaling frequency to 64 Gbaud.

As a result, PCIe Gen6 generally delivers better bandwidth-per-watt than what an equivalent 64 Gbaud Non-Return-to-Zero (NRZ) implementation would have required. Given that modern data center deployments (particularly for AI) tend to be large, a greater bandwidth-per-watt metric should always be welcome.

In this story, we will summarize what the first breed of merchant enterprise-grade PCIe Gen6 controllers from three popular vendors will offer, and what we already have on the market from Micron and Samsung.

Marvell Bravera SC6: 500TB or more of speedy storage

Matt Murphy's appointment as Marvell CEO in 2016 marked one of the most dramatic strategic shifts in the semiconductor industry. Marvell transitioned from being a large merchant chip supplier to a company almost exclusively focused on data infrastructure, and that transformation had significant implications for its storage controller business. Storage still complements the broad data-center portfolio alongside networking, custom silicon, switching, compute, and optical connectivity. However, gone are the days when storage was a major priority for Marvell. Yet, Marvell's Bravera SC6 (MV-SF1410) looks to be quite a significant contender for the PCIe 6 storage market.

The Bravera SC6 controller is powered by 15 Arm cores in total, including 12 Cortex-R82 cores arranged in two six-core clusters, three Cortex-M7 cores, and a dedicated Cortex-M3 secure processor. The controller is NVMe 2.2 compliant and features a PCIe 6.0 x4 host interface, thus potentially offering a maximum of 30.25 GB/s of throughput.

The MV-SF1410 controller features 16 NAND channels, eight chip enables (CE) per channel, and support for SLC, MLC, TLC, and QLC 3D NAND with an up to 3600 MT/s interface. The part also supports Marvell's sixth-generation NANDEdge technology with LDPC error correction, a hardware RAID engine, end-to-end data protection, 5 MB of SRAM, and a 64-bit DDR5 interface with ECC. The security subsystem of the Bravera SC6 supports AES, SHA, RSA, and elliptic-curve cryptography (which seems to be among the industry's firsts), enabling compliance with Trusted Computing Group (TCG) security standards.

One of the things that strikes the eye about the Bravera SC6 is that its interfaces support data transfer rates of up to 3600 MT/s. While this speed bin seems a bit outdated now that 4800 MT/s devices have been announced, in eight- or 16-channel configurations, a 3600 MT/s transfer rate with raw bandwidth of around 3.6 GB/s per channel (38.8 GB/s and 57.6 GB/s in total, respectively) is more than enough to saturate a PCIe 6.0 x4 interface (30.25 GB/s without the overhead).

Another notable thing is that Marvell has not publicly disclosed the controller's maximum addressable NAND capacity or logical unit number (LUN) it can support within each CE, so we cannot derive an actual maximum addressable capacity or maximum usable capacity from the public specification we have at hand*. But we can make some useful estimates. The SC6 has 16 NAND channels and eight chip enables per channel, or up to 128 CE positions in total.

With upcoming 2 Tb 3D QLC NAND dies, each die stores 256 GB. Kioxia/Sandisk formally announced such devices last week, but did not disclose their availability timeframe. Since BiCS10 is aimed specifically at data center applications, Kioxia has indeed described this generation as suitable for very highly stacked packages, without disclosing the maximum number of NAND devices per package. Typical NAND packages carry between 1 and 16 NAND devices (though Kioxia/Sandisk probably meant more than 16 devices), though packages aimed at high-capacity drives tend to feature 8 or 16 devices. 16 2-Tb devices give 32Tb (or 4 TB) per NAND package.

If an SC6 implementation could populate 128 such package positions, that gives 512 TB of raw NAND memory. Of course, actual drives will have to reserve plenty of NAND for overprovisioning and other techniques required for reliability and longevity, so actual commercial SSDs will offer a lower capacity. However, they will remain in a 500TB-class. Meanwhile, if the SC6 can address 32-die packages, then we are talking about petabyte-class SSDs. Yet, 32-die NAND packages may require something other than formal controller support.

Marvell says that it will start sampling its Bravera SC6 (MV-SF1410) with its partners sometime in Q4 2026, which means that the first drives featuring the chip will hit the market in late 2027, but more likely in 2028. Given that actual SSDs featuring the controller are so far away, Marvell even refrained from disclosing the expected performance of these products and only told us to expect "multi-gigabyte-per-second throughput, millions of random IOPS, deep queue parallelism, and highly efficient DMA-based data movement."

*A CE may select a package containing many dies, and each die may contain multiple LUNs. To address all those dies and LUNs efficiently, the controller must be architected appropriately. If the number of supported LUNs is lower than the number of LUNs featured by all-flash devices in all-flash packages, this will affect performance and parallelism, which will lower the appeal of such drives for data center operators.

Phison X3: Up to 2PB of storage at 28.8 GB/s

Phison has yet to make a big formal announcement of its X3 — aka PS5303 — SSD controller, but it was demoed at both CES and Computex this year. At CES, the company only showcased concepts of its PCIe Gen6-based drives, whereas at Computex it showed off reference drives, clearly suggesting that it is in the final stages of development.

The Phison X3 (PS5303) is the company's first-generation PCIe 6.0 x4 enterprise SSD controller, and it happens to be specifically aimed at data center applications, which include AI, cloud, and hyperscale deployments. Normally, Phison would introduce an eight-channel controller that would target both high-end desktop, workstation, and server applications. But such controllers have not yet surfaced.

The X3 is a 16-channel and NVMe 2.3-compliant controller, which Phison rates for up to 28 GB/s sequential read and write performance, 6.8 million random read and write IOPS, and approximately 4 GB/s per watt, which doubles the performance and efficiency of the company's PCIe 5.0 enterprise controller. Keeping in mind that its current-generation controller is made on TSMC's N12 manufacturing technology, whereas the X3 is produced on the N4 fabrication process, this improvement is expected.

Perhaps the most intriguing specification is support for SSD capacities of up to 2 Petabytes, which likely suggests that the controller has been designed with multiple future generations of dense 3D NAND flash memory in mind.

The controller supports OCP Datacenter NVMe SSD Specification v2.6, advanced enterprise security features including TCG Opal 2.3, DOE, IDE, Caliptra, and CNSA 2.0, as well as 64 SR-IOV physical functions for storage virtualization.

Phison has indicated that reference designs — E3.S, E1.S, etc. — are expected to sample this November, while volume production is anticipated in 2027, if everything proceeds in accordance with the plan. If the company succeeds, the X3 (PS5303) will be one of the first merchant PCIe 6.0 SSD platforms intended for next-generation storage infrastructure in 2027. Then again, it usually takes a year before sampling and availability of the actual drives.

Silicon Motion's SM8466: A mystery at 28 GB/s

Silicon Motion was probably the first company to reveal many of its details about its PCIe Gen6 plans in an interview with Tom's Hardware in June '25, then a leak with some details about its PCIe 6.x SSD controller emerged in July '25. After then, SMI kept it pretty much close to the chest about the SM8466 unit, but let us recall what we know about the controller both from our interviews and from the leaks.

Silicon Motion's MonTitan SM8466 is the company's 2nd-generation enterprise-grade controller that is projected to support 16 NAND channels, next-generation TLC and QLC 3D NAND, NVMe 2.x, OCP enterprise SSD specifications, and enterprise security technologies such as TCG Opal, Secure Boot, and SR-IOV virtualization, based on our interviews with the company as well as leaks.

Just like its direct rival from Phison, the SM8466 is rumored to offer 28 GB/s of sequential throughput and 7 million random IOPS, though no official claims have been made so far. Just like the Marvell controller, the SM8466 supports SCA and other features of modern enterprise-grade SSD platforms.

Perhaps the most surprising part of the specification is support for SSD capacities of up to 512 TB, which clearly falls short of the 2 PB capacity advertised by Phison's competing PCIe 6.0 controller. Then again, this is based on leaks and rumors, rather than official information.

Now that we know something about PCIe Gen6 SSD platforms from Marvell, Phison, and Silicon, let us recall what is already on the market, or about to hit it.

Micron's 9650: First and furious

Micron's 9650 is the industry's first PCIe 6.0 x4 SSD that is based on an in-house controller and the company’s 276-layer G9 3D TLC NAND with a 3600 MT/s interface. The drive delivers up to 28 GB/s sequential reads, 14 GB/s sequential writes, 5.5 million random read IOPS, and 900,000 random write IOPS. Depending on the exact SKU, the drive offers up to 25.6 TB of storage.

Since the 9650 is aimed purely at AI servers based on Nvidia hardware, Micron has optimized the SSD for peer-to-peer PCIe 6.0 communication with Nvidia Blackwell GPUs using retimers and switches to enable storage to feed accelerators without CPU involvement.

Micron started sampling its 9650 back in Q3 2025, so by now this drive is likely already available to interested parties.

Samsung's PM1763: 16 TB at 28 GB/s

Samsung has never announced sampling of its first-gen PCIe 6.0 x4 SSD, but it officially began mass production of its PM1763 drive this July. The PM1763 drive is based on a proprietary controller made using Samsung Foundry's 4nm-class fabrication technology as well as Samsung's ninth-generation V-NAND.

When it comes to capacity, the PM1763 is offered in 4TB, 8TB, and 16TB capacities. The flagship 16 TB model delivers up to 28.4 GB/s sequential read and 21.9 GB/s sequential write speeds, though the company hasn't disclosed the random performance of either SSD. Then again, to maximize performance, the drive's design is optimized for direct-to-chip (D2C) liquid-cooled servers (Samsung has not divulged details, though).

When it comes to power efficiency, Samsung claims the drive delivers more than 1.8X higher power efficiency than its predecessor and enables it to sustain peak performance during prolonged AI training and inference workloads. Unfortunately, without hard numbers, we can only take Samsung at its word.

In addition, the SSD supports post-quantum cryptography (PQC) algorithms to help protect against future quantum computing attacks, as well as the TEE Device Interface Security Protocol (TDISP) to secure data movement in virtualized server environments.

According to Samsung, the PM1763 has completed validation for next-generation AI platforms and is positioned as a storage solution for an AI data center near you.

Almost across the line

After years of delays caused by the transition to PAM4 signaling and the resulting ecosystem-wide validation effort, PCIe 6-class storage is finally approaching commercialization.

While Micron and Samsung already offer PCIe 6.0 SSDs, merchant controller suppliers —Marvell, Phison, and Silicon Motion — are prepping their next-generation enterprise platforms with up to 16 NAND channels, throughput approaching 28–30 GB/s, and support for capacities ranging from 512 TB to as much as 2 PB.

Samsung Foundry presented its updated fabrication technologies roadmap at the 2026 Next-Generation Lithography + Patterning Conference (NGL 2026) this week, revealing some major changes compared to the 2024 roadmap, reports ZDNet Korea. Instead of rushing its SF1.4 node (1.4nm-class) to the market, Samsung will focus on refining its SF2 (2nm-class) manufacturing processes in the next three years. And starting with its SF1A (1nm-class) fabrication node, Samsung intends to adopt High-NA EUV lithography tools, the first time the company confirms the plan.

Before moving on to 10-angstrom (or 1nm-class) node around 2030, Samsung will refine its SF2-series manufacturing technologies (which includes SF2P, SF2X, SF2A, and SF2Z with backside power delivery) and introduce its SF1.4 process in 2029.

The delay of SF1.4 from 2027 to 2029 indicates that the company is slowing its leading-edge cadence to focus resources on making its SF2 family more commercially competitive from yields and volumes point of view. Keeping in mind that Samsung has signed a long-term supply agreement with Tesla to supply AI5 and AI6 processors through 2033, the company's priority is to ensure that its major customer is happy.

Another reason for a long SF2 lifespan is the company's reported plan to finally adopt pellicles for EUV photomasks, which changes the usual routines at Samsung and likely forces it to reconsider process recipes for some of its future nodes.

Interestingly, but Samsung's 1nm-class node is said to co-exist with SF1.4+, an enhanced version of SF1.4 that uses an unusual nomenclature for Samsung. Such an approach indicates that the company will have both an "innovative" 1nm-class process that uses High-NA EUV lithography and a technology that relies on proven Low-NA EUV flows and materials.

Although Samsung has purchased an ASML Twinscan EXE:5000 EUV lithography scanner with 0.55 numerical aperture projection optics and has been using it for research purposes for well over a year, the company is not in any rush to adopt High-NA EUV lithography for its 2nm-class and 1.4nm-class fabrication technologies. Samsung only plans to insert such a tool for its 1nm-class process sometime in 2030.

"We wanted to apply High-NA EUV to mass production at nodes such as 2nm and 1.4nm, but the technology still requires further improvements," said Chang Min Park, Master VP of Technology at Samsung Electronics, at the conference. "We believe High-NA EUV will become necessary from A10 and below, and we are conducting joint development with various partners."

For chipmakers, the main challenge with ASML's High-NA EUV tools are substantially higher costs compared to Low-NA EUV systems used today, which greatly increases costs of fabs and can affect costs of chips. Meanwhile, High-NA EUV scanners introduce a smaller exposure field, which can require die stitching for large chips and complicate designs, which largely diminish their performance advantage over regular Low-NA EUV systems that stems on reducing the need for using multipatterning.

In addition, High-NA EUV needs improved photoresists, different masks, pellicles, metrology, inspection, and computational lithography, just to name some of the requirements. As a result, chipmakers must determine when it makes sense for them to use expensive single-patterning on High-NA EUV tools and when they can live with increasingly mature 0.33-NA EUV multi-patterning. For example, Intel intends use High-NA EUV tools with some of its 14A technologies, whereas TSMC looks at High-NA EUV lithography as on technology for the 2030s.

Apple used to be among a few companies willing to buy memory and other components worth billions of dollars under long-term supply contracts at fixed prices. But the artificial intelligence era represents a new reality with new purchasing champions, marking a tectonic shift in the high-tech world. Alphabet, Microsoft, Meta, and Amazon have purchase commitments totaling about $2 trillion, and a significant portion of these commitments are for memory, according to estimates by analyst Claus Aasholm. While the commitments are approximate, span many years, and should be generally taken with a grain of salt, they still reflect the direction the industry is moving.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

SpaceX and Tesla on Thursday formally unveiled plans for the initial phase of their Terafab project. The first stage of the plan — which is expected to use Intel's 14A process technology — is expected to require $16.8 billion in investment, while the completed campus is planned to encompass more than 100 million square feet of manufacturing space. The massive semiconductor manufacturing complex will be built in Grimes County, Texas, at a location that belongs to SpaceX.

According to SpaceX and Tesla, their combined demand for semiconductors is projected to exceed 1 terawatt (TW) of compute per year, which significantly exceeds today's global supply. In fact, SpaceX, Tesla, and xAI already consume a significant portion of contract chipmaking services available today, and can potentially justify building a dedicated fab that will exclusively serve Elon Musk's companies. In particular, Terafab is envisioned to exclusively produce AI inference processors for Tesla Optimus humanoid robots and Cybercab autonomous vehicles, as well as 'high-power' processors intended for SpaceX's space-based data centers. Meanwhile, SpaceX and Tesla have not disclosed when their combined demand for compute per year will hit the 1 TW benchmark.

Unlike a conventional semiconductor fab, Terafab is envisioned as a vertically integrated manufacturing campus where advanced logic devices, memory chips, packaging, and testing operations are housed together. Normally, logic and memory are produced at different fabs using different process technologies, whereas packaging and testing services are performed at different facilities. However, the companies believe that consolidating logic, memory, packaging, and testing in one location will not only shorten the production cycle but will also shorten time-to-yield by enabling faster iterative improvements.

Given the description and the goal of the project, this will be a massive facility. Yet, SpaceX and Tesla have said little about its capabilities; The only thing they have disclosed is that the current facility in Grimes County will feature '100 million square feet of manufacturing space.' The 100 million square feet (9.3 million square meters) figure immediately stands out because it is far beyond anything ever announced for a semiconductor manufacturing facility. For example, the total area of Samsung's Pyeongtaek campus is approximately 2.89 million square meters, or 31.1 million square feet. A single Samsung fab occupies about 120,000 square meters, or 1.29 million square feet. However, the key wording is important: '100 million square feet of manufacturing space' does not mean 100 million square feet of cleanroom space.

Based on an image published by SpaceX, the Terafab facility will occupy four massive buildings. It is unclear whether these buildings will be four phases of the project (i.e., logic, memory, and packaging will be made under one roof) or will serve different purposes (i.e., one building makes logic, another produces memory, yet another does testing and packaging). In any case, when fully built, Terafab will be a massive semiconductor production campus that will require significantly more than $16.8 billion.

The announcement claims that the Terafab facility will employ at least 3,000 people, and that between 60% and 80% of them will be Grimes and nearby Brazos County residents.

Terafab is expected to use water from Gibbons Creek Reservoir instead of local groundwater and feature on-site wastewater treatment as well as water recycling and conservation measures.

The announcement follows Tesla's groundbreaking earlier this year on a research semiconductor facility at the North Campus of Tesla's Giga Texas campus, which the companies describe as a precursor to Terafab.

This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.

Here's a breakdown of each type of technology that the company announced.

• zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
• zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
• BV-NAND (aka Samsung’s 10^th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).

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zHBM: Placing HBM stack on top of logic

Around the time we first heard about HBM4's 2,048-bit interface, we read a 'semi-official' report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung's zHBM appears to be a continuation of that effort.

Samsung's zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the 'performance of HBM5', while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.

While Samsung's claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a 'next-generation interface system incorporating zHBM' will deliver 'approximately eight times the performance of HBM5,' it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as '8x higher bandwidth.'

Instead, the general term 'performance' may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn't reveal which die stacking/bonding technology it will use for zHBM.

In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.

For now, Samsung hasn't disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.

zNAND-O(on-device): Put storage close to compute

Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company's V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.

Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.

Since the technology is in development, Samsung hasn't shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions 'improved I/O performance and low-latency,' it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.

BV-NAND: Good old V-NAND gets a new treatment

With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.

Samsung formally announced its 400-layer-class V-NAND (aka 10^th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm² with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung's 10^th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk's BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.

Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.

Samsung's new brand strategy

As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.

Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company's new tech, like zHBM and zNAND-O, is years away.

The requirements of AI clusters have made optical interconnections practical for scale-out connectivity, but as bandwidth needs increase, optical connectivity is becoming viable for scale-up connections as well. As a result, the industry is moving optical interfaces closer to CPUs and GPUs, from the front-panel transceiver to the package itself through co-packaged optics (CPO) — and eventually directly into the processor package.

Optical connectivity has been used for decades, since electrical links cannot efficiently and reliably transmit data over long distances at high data transfer rates. But the cost and complexity of optical components limited their use to long-reach connections.

Today, the importance of CPO is rising: Electrical interconnects are no longer scaling as quickly as AI processors, and feeding thousands of accelerators within a data center requires an exponential increase in communication bandwidth. In a traditional optical networking architecture, the processor or switch ASIC communicates electrically with a pluggable optical transceiver located at the front panel of a server or switch. As signaling speeds climb to 200 – 400 Gb/s per lane and beyond, however, transmitting electrical signals over long copper PCB traces on a motherboard becomes increasingly inefficient, causing higher insertion loss, greater power consumption, and tighter signal integrity requirements.

While technically possible, it demands the use of better materials, re-timers, complex compensation processing, and equalization circuitry, which increases the cost of server infrastructure and its power consumption. CPO moves optical engines next to the processor or switch ASIC to shorten the electrical path before signals are converted into light, which means lower power consumption per transmitted bit, increased bandwidth density, and predictable scalability. As a result, CPO is increasingly viewed as a necessary technology for next-generation AI infrastructure.

Because AI is viewed as a major megatrend, CPO is set to become ubiquitous; there are dozens of companies working in the CPO ecosystem, including foundries, OSATs, optical I/O startups, laser manufacturers, fiber suppliers, packaging houses, and networking vendors.

As there are so many vendors pursuing different goals with different strategies, for this story, we are going to limit ourselves only to companies that actually produce things and whose roadmaps reflect their technological capabilities. So far, only four foundries have publicly articulated meaningful CPO manufacturing strategies: Intel Foundry, GlobalFoundries, Samsung Foundry, and TSMC.

The four companies each represent four different CPO strategies and have very distinct plans for the future, so their visions and capabilities may not be directly comparable. Nonetheless, reviewing their offerings gives us an idea about where the industry is going from the perspective of actual foundries.

TSMC: COUPE for everything

TSMC has historically been absent from the optical connectivity market as a product supplier. But having worked on silicon photonics for many years, it now has the broadest ecosystem and manufacturing roadmap with its Compact Universal Photonic Engine (COUPE).

TSMC's silicon photonics technology roadmap currently has three stages that span from a 1.6 Tbps optical engine with conventional pluggable optics to a 12.8 Tbps optical engine located within a processor package. The COUPE roadmap is tightly coupled with the company's advanced packaging technologies and the evolution of the company's micro-ring modulators (MRMs) that adjust light and directly impact performance. As a result, several TSMC customers (e.g., Nvidia) plot their silicon photonics strategies around the evolution of COUPE.

The first phase of the roadmap — called COUPE on PCB — relies on a COUPE that bonds a 65nm electronic integrated circuit (EIC) with a photonic integrated circuit (PIC) using the company's SoIC-X bonding technology. The initial implementation targets OSFP (Octal Small Form-factor Pluggable) optical modules and delivers 1.6 Tbps of bandwidth (2x the throughput of copper Ethernet solutions, along with 2x the power efficiency). Therefore, the first-gen COUPE is out of the scope of this article. TSMC says the SoIC-X interface features very low impedance and enables lower power consumption at high signaling speeds.

The second generation — dubbed COUPE on substrate — marks TSMC's transition from conventional pluggable optics to co-packaged optics (CPO). In this stage, COUPE is integrated with the company's chip-on-wafer-on-substrate (CoWoS) advanced packaging technology and co-packaged with a network switch ASIC. This architecture enables motherboard-level optical interconnects with aggregate bandwidth up to 6.4 Tbps, 2x power efficiency, and 10x lower latency than existing pluggable solutions, which is fantastic for a variety of applications, such as NVLink, Ethernet, and InfiniBand switches.

The third phase — called COUPE on interposer — pushes silicon photonics even closer to compute dies: A 12.8 Tbps optical engine is integrated directly into the processor package to enable ultimate bandwidth and scalability. Beyond doubling bandwidth again, the company expects the architecture to offer 5x power efficiency and 20x lower latency than today's pluggable solutions. That will make it particularly attractive for hyperscalers that build clusters with thousands of accelerators. Unfortunately, TSMC characterizes this phase as exploratory and has not disclosed its commercialization timeline.

The main agenda of COUPE is to move the optical engine as close to compute as possible. There is another dimension in TSMC's silicon photonics strategy, however: the evolution of the photonic devices themselves, the MRMs integrated into PICs. The company plans to bring the world's first 200 Gbps/lane (wavelength) micro-ring modulator into production in 2026 and then continue scaling the technology with 400 Gb/s MRMs, additional optical wavelengths, and denser fiber-array integration. This evolution is expected to increase COUPE’s bandwidth density from 0.5 Tb/s/mm in 2026 to 4 Tb/s/mm by 2030, providing an 8x improvement over four years.

It is noteworthy that TSMC presents the MRM roadmap separately from the evolution of COUPE packaging, which suggests that advances in micro-ring modulators represent an independent technology roadmap for the photonic integrated circuit (PIC), rather than being tied to a specific packaging generation. This potentially means that future COUPE products could adopt newer generations of MRMs regardless of whether the optical engine is mounted on a PCB, package substrate, or silicon interposer — although the latter will probably deliver the greatest system-level benefits by minimizing the electrical distance between compute dies and optical interfaces.

Intel: Optics for CPUs, GPUs, DPUs, and accelerators

Intel has been shipping various products with optical interconnections for decades and even attached its silicon photonics solutions to Xeon and Xeon Phi processors in the mid-2010s. Today, Intel's public CPO roadmap is less explicit than TSMC's, but its direction is fairly clear: move optical I/O directly next to CPUs, GPUs, accelerators, and eventually other compute chiplets. Meanwhile, so far, Intel has not unveiled plans to use its CPO technology for switches.

Intel's CPO strategy is largely focused on its Optical Compute Interconnect (OCI) chiplet, which is a self-contained optical I/O subsystem packing both EIC and PIC that can be co-packaged with any compute device using a PCIe interface to enable high-performance optical connectivity. Intel demonstrated the first OCI in 2024. That prototype implementation used 64 PCIe 5.0 lanes at 32 GT/s in each direction to connect to the host and provided 4 Tbps of bidirectional optical bandwidth over eight fiber pairs over a distance of up to 100 meters. Each fiber carried eight DWDM wavelengths spaced at 200 GHz, and every wavelength (lane) transported about 32 Gbps (8 FPs × 8 WLs × 32 Gbps = 2,048 Gbps in each direction).

The 2024 OCI implementation is good for testing the technology, but with rather slow 32 Gbps lanes, it has not been adopted commercially. Meanwhile, this technology has already been proven and demonstrated. Intel is currently working on its next-generation OCI with 200G/lane PICs to support 800 Gbps and 1.6 Tbps applications, though it is unclear when it is set to be available, as Intel has not yet disclosed an equivalent to TSMC's MRM roadmap.

It should be noted that future OCI implementations supporting bandwidth of 10s of terabits per second could interface with compute dies using next-generation PCIe 6.0 interfaces or even native die-to-die UCIe links when integrated into commercial products. Furthermore, Intel can naturally integrate OCI chiplets using its advanced packaging technologies to ensure high performance and low power.

As noted above, Intel's focus with OCI has always been its integration with CPUs, GPUs, DPUs, accelerators, or other compute devices, but not necessarily switches. It remains to be seen whether Intel's next-generation AI hardware roadmap will include switching silicon, but for now, it does not seem that the company is targeting optical switches with its OCI chiplets. Since OCI is protocol-agnostic, limiting it to compute devices seems like an artificial limitation, though we have little indication about Intel's reasoning behind the decision.

Samsung Foundry: Addressing everything

Samsung Foundry's silicon photonics strategy is arguably the most comprehensive among leading foundries. Unlike Intel, whose CPO roadmap is focused on its OCI chiplet for integration with compute devices, or TSMC, whose COUPE optical engine is another major ingredient of its foundry platform, Samsung intends to offer all types of optical connectivity devices, starting from pluggable transceivers in 2026, to switch CPO later on, and all the way to optical engines on the interposer of a processor package in 2030. Unfortunately, Samsung does not publicly provide a lot of information about its plans, so our main source of information will be SF's slide from a conference published by SemiVision.

This year, Samsung Foundry intends to offer a merchant PIC platform that relies on an EIC and a PIC mounted side by side on a PCB for conventional pluggable optics. The PIC will support 100 Gbps-class optical interfaces using CWDM technology, which is good enough for traditional pluggable optical transceivers (though Samsung does not specify the exact implementation), so there's no indication of CPO here.

In 2027, Samsung Foundry intends to catch up with TSMC's first-gen COUPE and offer an optical engine that stacks an EIC on top of a PIC using thermo-compression bonding (TCB). Samsung expects energy efficiency of this generation to improve from approximately 10 pJ/bit for its initial PIC platform to 5 pJ/bit, though Samsung has said nothing about bandwidth or latency. Samsung's TCB-based OE seems to be an intermediate product between merchant PICs and true CPO, so it will generally address onboard optics and pluggable transceivers.

By 2028, SF intends to move optical engines to the substrate of Ethernet or InfiniBand switch ASICs, which will be its first true CPO. The company intends to adopt hybrid copper bonding (HCB) with 10 µm pitches for its OEs to improve bandwidth density. Based on the slide from the roadmap, to address next-generation switches, Samsung is poised to increase optical lane speeds from 100 Gbps to 200 Gbps and ultimately 400 Gbps, although the company does not disclose when exactly each speed bin will be introduced (though it looks like 400 Gbps will come in 2029 – 2030) as well as the underlying modulator technology or other device-level details behind this scaling.

In 2029, Samsung Foundry will finally integrate its optical engine on an interposer next to CPU/GPU/XPU or other compute device, which will reduce energy consumption to 2 pJ/bit while providing extremely high bandwidth. Samsung calls this 'CPO Turnkey,' which implies that such integration will require its own packaging technologies. The next step in Samsung's roadmap is called 'next-generation CPO Turnkey,' and it integrates virtually the entire optical subsystem — including lasers — alongside compute and memory, which will be its ultimate CPO offering expected by 2030 and onwards.

While Samsung Foundry's ultimate goal to offer highly integrated turnkey CPO solutions is clear, the company also intends to offer two merchant platforms for pluggable optical transceivers, perhaps to de-risk development of its future products and to capitalize on the high demand for optical connectivity that exists today and will continue going forward.

GlobalFoundries: A bespoke vendor-agnostic OCI-MSA CPO platform

Unlike Intel Foundry, Samsung Foundry, and TSMC, GlobalFoundries does not produce or intend to produce AI processors, switch ASICs, or advanced packages. Instead, it aims to become a merchant co-packaged optics provider that will produce and sell bespoke CPO solutions that enable optical connectivity (including OCI MSA connectivity) for processors made by other chipmakers.

GF's silicon photonics effort dates back to the IBM Microelectronics acquisition in 2015, which brought IBM's silicon photonics technology and engineering teams into the company. Over the years, GlobalFoundries has expanded its silicon photonics capabilities into what eventually became the GF Fotonix platform and, more recently, the company acquired AMF and InfiniLink to further strengthen its production and design capabilities.

The key element of GlobalFoundries' CPO strategy is its Silicon photonics Co-packaged Advanced Light Engine (SCALE) platform that combines photonic IP, advanced packaging technologies, and a reference optical engine architecture that includes EIC and PIC. Unlike Intel's OCI chiplet, SCALE allows GF's clients to customize optical engines in accordance with their needs and have them manufactured by GF.

Under the program, GlobalFoundries manufactures the PIC and EIC using its own process technologies and then packages them into an OCI MSA-compliant optical engine using its methods. If the EIC requires a leading-edge node that GF does not have, it could instead be fabricated by another foundry and then integrated by GF. Customers then co-package the optical engine alongside their own switch ASICs or AI accelerators.

For now, SCALE supports both CWDM and DWDM transmission using qualified 50 Gbps and 100 Gbps MRMs, integrated photodiodes, and coupled-ring resonators. The platform has demonstrated bidirectional operation with up to 16 DWDM lanes per fiber, which theoretically opens doors to optical links with up to 1.6 Tb/s of bandwidth per direction. On the integration side of things, it supports advanced 2.5D and 3D integration using TSVs and copper bonding with pitches ranging from 110 µm to below 45 µm, which is good enough for integration using CoWoS-S and CoWoS-L technologies.

Just like Intel with its OCI, GlobalFoundries does not necessarily tie its SCALE CPO customers to its silicon or packaging technologies. Furthermore, the company allows its clients to customize their optical engines while retaining compatibility with the OCI-MSA requirements.

The future of CPO

Co-packaged optics (CPO) is set to become a key technology for next-generation AI infrastructure as conventional electrical interconnects struggle to keep pace with the bandwidth demands of rapidly developing AI processors.

Among foundries, TSMC, Intel, Samsung Foundry, and GlobalFoundries have each developed distinct CPO strategies that range from merchant optical engines to optical I/O chiplets and vertically integrated CPO platforms.

Given the different capabilities of the contract chipmakers, their roadmaps differ significantly in both scope and implementation, with some companies trying to lock in customers with a proprietary platform and others offering different degrees of freedom.

However, they all share the same objective: move optical interfaces progressively closer to compute dies to reduce power consumption, increase bandwidth density, and lower latency for the next generation of AI systems that will require considerably more bandwidth than today's clusters.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

Samsung and SK Hynix, South Korean memory giants, are set to announce major deals involving “very large sums” with leading U.S. tech companies, according to a July 24 Bloomberg report, citing comments from the country's presidential policy chief Kim Yong-beom. According to the report, Kim did not disclose the financial details of the deal but said the announcements would likely cover strategic partnerships, memorandums of understanding, and long-term supply deals on memory chips.

The deals are set to be announced during South Korean President Lee Jae Myung’s visit to Silicon Valley for the high-profile San Francisco AI submit — beginning today, Friday July 24 — which is bringing together industry leaders, such as Samsung Chief Lee Jae-yong, SK groups chairman Chey Tae-won, Nvidia CEO Jensen Huang, as well as the CEOs of Open AI, Anthropic, and Broadcom among others.

South Korea announced an $880 billion investment plan last month — backed by SK Hynix, Naver, and Samsung — aimed at strengthening the country's AI leadership through aggressive chip production expansions, data center buildouts, and physical AI. Kim said the South Korean President’s visit and involvement in the summit will serve as a catalyst to seal several long-running negotiations between the country's top tech entities and their U.S. counterparts, while also turning a significant portion of last month's planned investment into concrete projects.

The president is set to hold separate meetings with Huang, OpenAI's Sam Altman, Anthropic’s Dario Amodei and Broadcom Inc.'s Hock Tan, all U.S. companies. The U.S. has also urged Samsung and SK Hynix to expand their chip production in the country, but Kim stated that there had been no formal requests from Washington. According to Kim, much of South Korea's domestic expansion is driven by strong demand from U.S. companies, which accounted for 80% – 90% of underlying orders.

Samsung has cut jobs across its U.S. consumer electronics business as it prepares to move Samsung Electronics America's headquarters from New Jersey to Texas by the end of the year, with a WARN notice listing 739 affected roles at its Englewood Cliffs offices and roughly 100 workers let go at its Plano, Texas, site, according to a Reuters report.

Samsung told the outlet on Sunday that a majority of the affected New Jersey employees received relocation offers, while others were let go. SEA runs U.S. sales and marketing for Samsung's smartphones, TVs, displays, and home appliances, and doesn't include the company's semiconductor operations. The Plano figure, which covers workers in the mobile division among others, came from one laid-off employee who spoke to Reuters anonymously.

SEA employs about 1,200 people in New Jersey, according to U.S. Rep. Josh Gottheimer's office, which said the Englewood Cliffs campus opened last September, replacing the Ridgefield Park headquarters Samsung had occupied since 1992. The WARN notice covers over 60% of that workforce, roughly 10 months after the site opened. Internal documents reviewed by Reuters show employees were notified of an “enterprise-wide reduction in force” on June 30.

Samsung said in its statement that the relocation is intended to foster "stronger collaboration and optimize the organization," and that there's currently no broad global restructuring underway in its consumer products business. A current SEA employee told Reuters that workers are nonetheless worried about further cuts and a possible consolidation of the appliance, home entertainment, and mobile divisions as the company concentrates resources on chips.

Samsung's chip division booked a preliminary $58.5 billion in second-quarter operating profit, a 19-fold year-on-year jump that passed Nvidia's most recent quarter and put Samsung on track to out-earn its entire 40-year semiconductor history in 2026. Its mobile division is expected to post its first-ever quarterly loss over the same period, squeezed by competition from Apple and by the memory price increases its own chip unit is charging. Conventional DRAM contract prices rose 58% to 63% in Q2, and smartphone makers are raising handset prices to offset persistently high memory costs.

The consumer arm's relocation puts it alongside Samsung's existing chip footprint in Texas, which includes two fabs in Austin, the delayed Taylor fab, and a mobile hub in Plano. Samsung employed 11,770 people in the U.S. at the end of 2025, including its chip division. Samsung's IT services affiliate, Samsung SDS America, warned in a separate June notice that 179 roles could be cut in Ridgefield Park, New Jersey.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

Samsung is back with another solid-state drive, and this time it's something a little bit different. The 990 is a QLC-based 990 EVO Plus, positioned as a budget drive that can still push a lot of bandwidth. It’s a little late to the game and not quite what was rumored for the 990 QVO, but it does bring some new technology to the table. We’re always interested in seeing what Samsung puts out, and this time is no different. It should not be confused as being part of Samsung’s Pro line or, for that matter, the EVO line, so keep that in mind.

The drive has its ups and downs, but in this challenging market, and for a budget drive, that’s to be expected. Samsung is still well-regarded for its name and reliable hardware, even as there has been a massive push towards enterprise, away from the consumer side. Samsung has, in fact, given some ground in the SSD space for many years, even as it produces some of the most common OEM drives. So while this is not a Crucial situation, it’s best to jump into this review with the right expectations about what this drive is and isn’t. It’s a budget drive with full Gen 4 throughput that hits the most common capacities with sufficient performance and power efficiency. It’s not meant to be a throne-taker.

It’s also thankfully not another 990 EVO situation – that drive felt somewhat underwhelming by the time it arrived, even when pitted against budget drives – but the 990 is also not a QLC rallying call. It’s a competent drive that mostly hits the right notes, as intended. Given how scarce Samsung QLC drives have been, and how much demand its QLC flash surely has elsewhere, it can feel like Samsung is throwing consumers a bone, though it would be crass to put it that way. We instead think this is smart positioning by the company as it knows the future is with QLC and the technologies used in this flash (even if first shown two years ago at ISSCC) point firmly at an ambitious future. The 990 just lets you own a piece of that.

Samsung 990 Specifications

The Samsung 990 is only available at 1TB and 2TB capacities, with MSRPs of $269.99 and $529.99, respectively. These prices are very high, as you can get competing drives like the Crucial P310 for substantially less, and in fact even the TLC-based WD Black SN7100 costs less. But Samsung has historically launched with MSRPs well above actual market price. You should be able to get the drive at significantly lower prices after launch, but the “Samsung tax” may still apply. We’ll get into what that means throughout the review.

This limited capacity range is unfortunate, but enables Samsung to pack the flash into just one package, which reduces PCB space so that any OEM variant can be used in multiple M.2 form factors and will always be single-sided. Less than 1TB is also not enough for these denser dies if you want good performance. That leaves 1TB and 2TB as the target capacities, which also makes sense in a market where 4TB+ is getting exceptionally expensive. We’ll eventually see 2Tb dies to make single-package 4TB a reality, but that’s further along in Samsung’s roadmap.

The drive can reach 7,250 / 6,450 MB/s for sequential reads and writes and up to 850K / 1,200K random read and write IOPS. Peak performance is attained at 2TB, where you have the optimal amount of interleaving or parallelization: Sixteen 1Tb dies means four dies for each of four flash channels, the typical ceiling. However, as these are four-plane dies, you still get 32-way interleaving at 1TB with eight dies, which is enough to get good performance with just two dies per channel. Less than that is much less ideal, and more than that introduces additional overhead, especially for budget controllers. The math changes with six-plane and 2TB dies, but for this flash, 1TB is the reasonable minimum, with 2TB offering the best performance.

The drive is rated for approximately 4W of power draw across the two capacities, when looking at both reads and writes. Check our power results below to see how accurate that is. The drive is rated for 400TB of writes per TB capacity, which is high for QLC flash – we would typically see maybe 300TB, which is one-half of the TLC standard – but also indicates a very high drive writes per day (DWPD) rating. This is due to the warranty only covering three years rather than the normal five, so the amount of writes per year is significantly higher. This is atypical, so requires further explanation.

For those who live for TBW and write endurance, this illustrates why TBW often looks better on paper. Spreading 400TB over three years works out to roughly double the daily write allowance of a typical 300TBW / five-year QLC drive. Most people will never approach either number, and they will live with the shorter coverage window. However, if you intend to hammer the drive with writes to the point of exceeding TBW within the three-year warranty period, then this could be good. Although you really shouldn't use a budget DRAM-less QLC-based drive for that type of workload. However, that option exists and is rarely the case with a QLC-based drive. As a final note, the drive does support TCG Opal 2.0 for encryption.

Samsung 990 Software and Accessories

Samsung’s Magician software is the gold standard for consumer SSDs. This is an SSD toolbox with all the features you need. It displays system and drive health information, including SMART, and checks whether your drive is legitimate. You can also benchmark your drive and use any optional features, such as encryption. The software is also essential for keeping the drive’s firmware up to date, although you can also download that from the first link.

Samsung 990: A Closer Look

The 990 has an SSD controller, a single NAND flash package, and power management circuitry. There is no DRAM package present. This is a single-sided drive, which is ideal for compatibility and cooling. There is a lot of free space on the PCB, and by putting distance between the controller and flash, there is separation to mitigate component heat generation. This would also help if a heatspreader or heatsink were to be added. Without this space, the drive could be sold in a shorter form factor, which is particularly useful for OEM drives.

The label has information about the drive, such as the date of manufacture (DOM), model, serial, the PSID, and the power rating. We always caution that you not take certain drive information as being conclusive about the hardware. For example, you should not assume TLC or QLC flash from a drive’s TBW. Likewise, you shouldn’t rely on the labeled power rating – and this is done more often on M.2 2230 drives for portable devices – as any indication of drive power efficiency. Here we have 3.3V / 1.85A, which indicates potential power draw over 6W. Now, the power ratings given on spec sheets will often be average and not peak, and will be separated as read or write rather than mixed. In fact, this drive’s load power states can reach a peak of 5.90W via SMART, which is much above the rated average ~4W. We track both peak and average in our testing.

We always enjoy reviewing Samsung drives with a focus on the technicals, as the manufacturer remains a leader in many ways. The 990, in particular, requires some extra description to be fully appreciated. Simply looking at the benchmark results might make the technology seem underwhelming – to be honest, this is very much a budget drive, even taken in the best light – but that doesn’t mean Samsung phoned this one in. In fact, there are signs of deliberate design here, and some of the decisions could help sell this drive. Samsung still has to get the pricing right, of course, but what else is new?

Let’s start with the controller. The 990 is using the PiccoloQ, which is the QLC flash version of the Piccolo. The Piccolo is utilized on the 990 EVO and 990 EVO Plus, two TLC-based drives. In all cases, it’s a four-channel, DRAM-less design, which limits performance and capacity. In both cases, the controller takes up to 2,400 MT/s flash – this is more than enough to saturate PCIe 4.0 – and the interior design is the same. This means it’s a Samsung 5nm part with multiple ARM Cortex-R8 cores and a single R5 core. If the Piccolo stands out in any way, it’s that it offers a PCIe 5.0 x2 option in addition to the standard 4.0 x4 interface. This option or mode has limited usefulness, though, and nothing in the 990 would change that if enabled for the PiccoloQ.

So, not much new on the controller front, but the use of this controller at the 990’s rated speeds does give us some more information. Namely, we know the 990 EVO runs more slowly because it’s using flash slower than 2,400 MT/s, 1,600 MT/s Samsung V6P TLC, to be precise. If we look at Samsung’s V7 QLC flash, it can run at that same speed. This is why the originally speculated 990 QVO with that flash was targeted at the same speeds as the 990 EVO. Things have changed since then. This drive could have been the 990 QVO, but with the EVO and EVO Plus lines going DRAM-less this generation, we suspect the QVO tier was “promoted” to the plain 990 name, and the 990 now targets the 990 EVO Plus's specs

The evidence to back this up, which also supports the loose 990 QVO rumor, is that Samsung does have a V7 QLC OEM drive: the BM9C1. This is the cousin to the PM9C1 line with OEM 990 EVO and 990 EVO Plus (PM9C1b) variants. The BM9C1 is available down to M.2 2230 and uses the same PiccoloQ as the 990 (the QLC version of the 990 EVO/EVO Plus’s Piccolo). It’s just limited to the same speeds as the 990 EVO, as it’s running at 1,600 MT/s. We have to be careful here, though, as Samsung’s V9 QLC press release indicates a 60% I/O improvement, which, with the V9 being 3,200 MT/s, suggests a 2,000 MT/s ceiling for the V7 QLC. Since there is an OEM TLC-based drive in between the 990 EVO and 990 EVO Plus (the PM9C1a) at 2,000 MT/s, the possibility for a ~6 GB/s 990 or 990 QVO with V7 QLC existed.

Before we dive more deeply into the flash, since we haven’t seen the new Samsung QLC in a while and there is some neat tech here, let’s decode the module. “K9” tells us it’s Samsung NAND flash memory. “YYG” indicates it’s a QLC flash package with sixteen dies (HDP) in a 2TB configuration, which confirms 1Tb dies. “Y8” means it’s 8-bit, J tells us the voltage, “5” tells us the number of chips enabled and ready/busy signals, and “D” tells us the generation. With V7 being “C” and V8 skipped, this suggests V9. The second part of the code tells us how the flash is packaged and that it’s commercial / consumer-grade. While you aren’t expected to know how to read codes on your SSD, knowing how it works can be useful, especially with Samsung drives, even if it’s just a matter of trying to figure out if you have a counterfeit product.

So let’s talk about the flash. This is a 286-Layer part, technically, but is sold as 280-Layer once accounting for source/ground and dummy lines. Dummy lines are usually at stack edges, as the physics of flash can make these lines otherwise unusable. A higher layer count – Samsung’s V7 is only 176-Layer, although technically 191 layers – generally means higher bit density. Bit density is key to scaling NAND flash, which is acting as capacious, non-volatile storage media. This can be disappointing to some because it means you don’t always see any real performance scaling as the layer count progresses.

Fitting more flash into the same space can mean less room for charge in each cell, which makes it harder to optimize for performance if you’re trying to maintain the same endurance level. That is certainly the case with this flash, as the performance only manages to match that of last-generation 176-Layer QLC flash from competitors, which is why we want to go out of our way to point out Samsung’s design decisions and why it leans innovative in ways you won’t see in, say, your game load times.

For one, when we talk about the layer count difference – reported versus actual – you also get an efficiency number that is the ratio between usable and total word lines. Samsung is a leader here, with high layer efficiency. Samsung also has held off using three decks or stacks of flash and is still at two, due to having superior channel etching – it’s able to drill down more layers with a higher aspect ratio. It’s also possible to run lines through the flash itself rather than rely largely on masked steps, which sets the stage for Samsung scaling to extremely high layer counts. One issue with high layer counts is that you start losing uniformity from layer to layer, and Samsung accounts for this with optimized word line spacing, too. So, as we’ve said in the past, it often feels like Samsung is falling behind on layer count, but in reality it has a very focused strategy and the best technology in the business, and we can see this with the 990’s flash.

For the consumer, though, the 990 is a little bit weird. This is presumably 3,200 MT/s flash that is being “wasted” with a 2,400 MT/s controller. This flash has amazing bit density, but having a single sixteen-die package at 2TB is nothing new. What about performance? Samsung has made optimizations to improve performance on this flash, but nothing amazing. This QLC is only comparable to the competition in performance terms, particularly at 2,400 MT/s. Samsung is playing catch-up, but we also think this is a case of designing for enterprise rather than consumer.

QLC flash is now highly sought after in enterprise for its density, and Samsung’s optimizations all benefit that kind of environment. In fact, from a consumer’s perspective you could look at this V9 QLC as being focused on higher bit density – but no 2Tb dies – and you would largely be correct. Samsung’s V9 QLC is 86% more dense generationally and about 94% more dense than the competition’s 176-Layer QLC flash.

We’ll take a look at one new technology in the V9 QLC flash to illustrate. One important consideration is flash power interruption leading to data loss, which, without power loss protection (PLP) means you are looking at protecting data at rest. This is on the non-volatile media or flash, not the volatile memory like DRAM. When folding from the pSLC cache to the native flash, data loss is not an issue because you don’t invalidate the original pSLC copy until the write has been verified. However, when writing to native QLC, you are writing multiple pages where the upper pages will require higher levels of sensitivity for proper reading. There are different methods of writing to QLC flash, but generally multi-bit flash has multiple write passes that go from fuzzy (coarse) to precise (fine), and lower pages write faster and may be complete first. Therefore, it’s important not to ruin existing lower-page data if you lose power while still adjusting voltage for the upper pages.

Micron has a unique way of dealing with this using a differential engine that can predict values from partial shifts, but a more common method is simply to back up or buffer the values in nonvolatile flash. QLC stores four bits per cell, so a full backup means writing four bits of pSLC per cell. pSLC is used because its writes are fast, whereas QLC's upper-page writes, in particular, are an order of magnitude slower. Samsung reduces the buffer to a single parity bit by using an odd/even algorithm, creating a sensing window that’s more like TLC (8-state) than QLC (16-state). This improves performance, endurance, and bit density. Some of that performance is still lost for higher bit density. For consumers, the direct benefit is higher TBW, but we speculate the higher density is aimed more at enterprise and future flash generation products. This is in part a response to Solidigm’s floating-gate design, a different technology than charge trap, with tighter charge placement.

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Comparison Products

The Samsung 990 enters a crowded market with a lot of good options, at least in theory. If we’re looking at QLC-based drives, this means the Crucial P310 and Sandisk WD Blue SN5100 at the very top. Both of these drives perform incredibly well. Below that, we have the older wave of drives represented by the TeamGroup MP44Q. That drive in particular remains a budget favorite with a fast controller and good QLC flash.

We would put the rest below that, even though the hardware is not always worse. This would include the Biwin M350, the Kingston NV3, and the Seagate FireCuda X1070. These drives are using alternative controllers – SMI, SMI, and TenaFe, respectively – that are roughly comparable, and the flash is not particularly old, either. However, these drives tend to be more budget-focused with reduced performance and (ideally) reduced cost.

We’ve also thrown in Samsung’s 990 EVO and 990 EVO Plus for comparison. The 990 should be closer to the latter, but with QLC flash, it would be okay landing somewhere in between. On the whole, we would expect the drive also to be between the two main categories of drives – that is, above the budget ones, below the two fastest, and closer to the middle MP44Q and its MAP1602-equipped alternatives, but with Samsung’s name recognition. The technology is here to make this a reliable drive, which is also a factor to consider, but being this late to the game puts the 990 at a general disadvantage.

Trace Testing — 3DMark Storage Benchmark

Built for gamers, 3DMark’s Storage Benchmark focuses on real-world gaming performance. Each round in this benchmark stresses storage based on gaming activities including loading games, saving progress, installing game files, and recording gameplay video streams. Future gaming benchmarks will be DirectStorage-inclusive and an evaluation for future-proofing is included where applicable.

We start by looking at 3DMark because, frankly, QLC-based drives make a lot of sense for gaming. Aside from large installs and updates, you’re mostly doing reads, which do not favor TLC drives as much. While it’s true that QLC flash is still slower, often-accessed data might be left in the pSLC cache – if you leave enough space free – and QLC is also optimized for random reads. Games do involve a lot of sequential reads and often at larger block sizes than you’d expect, but as long as the drive has sufficient interleaving (it’s sufficiently large) you are going to get pretty good performance.

For 3DMark, which is a synthetic test, we might expect the drives to perform as they do under ideal, cached circumstances. This means the 990 should perform closely to the 990 EVO Plus and better than the 990 EVO, even though both of those latter two are TLC-based. It does. The 990 gets pretty close to the P310, which is one of the best QLC drives out there, aside from the Blue SN5100. We tend to look at ~45µs as a good cutoff point for all-around performance – gaming doesn’t need to be super responsive – which is roughly around the popular budget NV3. The 990 is significantly faster than that, which is all you could ask for here.

Trace Testing — PCMark 10 Storage Benchmark

PCMark 10 is an industry standard trace-based benchmark that uses a wide-ranging set of real-world traces from popular applications and everyday tasks to measure the performance of storage devices. The results are particularly useful when analyzing drives for their use as primary/boot storage devices and in work environments.

PCMark 10 performance usually, but not always, follows 3DMark. There is speculation that some drives or firmware may be optimized for benchmarks like PCMark 10, but taken within a greater suite of tests it’s still useful to get a feel for application performance. For us, that means for a primary drive – your boot or OS drive where your apps live – or for your everything drive, if you work and game on a single drive in your system. This isn’t too unusual with laptops where M.2 slots are limited.

The 990 again ends up roughly where we’d expect – above the 990 EVO, and close to the 990 EVO Plus. It’s not on the level of the P310 or Blue SN5100, but it’s clearly above the budget drives. This is a strong result with good latency. For instance, we would take the 990 over the NV3 any day, every day. On the other hand, the P310 and Blue SN5100 are frankly better drives. These two drives are better optimized and performance-oriented. The 990 is more of a gap filler that’s late to the scene.

We have to say, though, that we’re glad Samsung didn’t push out a 990 QVO that was more like the 990 EVO, even if it would have arrived earlier. Such a drive would have used older QLC flash and performed more slowly simply due to the lower interface speed.And frankly we’d rather have density-optimized flash that can run at the 990 EVO Plus level. That’s what the 990 delivers, even if it feels a little underwhelming. However, it makes perfect sense given the current market, enterprise demand, OEM demand, etc. The drive is still very fast and of a superior quality to a great many budget drives out there, and that makes it worthwhile.

Console Testing — PlayStation 5 Transfers

The PlayStation 5 is capable of taking one additional PCIe 4.0 or faster SSD for extra game storage. While any 4.0 drive will technically work, Sony recommends drives that can deliver at least 5,500 MB/s of sequential read bandwidth for optimal performance. Based on our extensive testing, PCIe 5.0 SSDs don’t bring much to the table and generally shouldn’t be used in the PS5, especially as they may require additional cooling. Check our Best PS5 SSDs article for more information.

Our testing utilizes the PS5’s internal storage test and manual read/write tests with over 192GB of data, both from and to the internal storage. Throttling is prevented where possible to see how each drive operates under ideal conditions. While game load times should not deviate much from drive to drive, our results can indicate which drives may be more responsive in long-term use.

You know our PlayStation 5 line by now: just about any drive will do. The 990 can push more bandwidth than the 990 EVO, which arguably makes it a better pick. It’s on par with, or better than, most budget drives out there. At least, for the things you will usually be doing on the PS5. It’s clear from our one bandwidth test that the drive ran out of cache, and it has the typical slow QLC flash write state. This is not indicative of real-world performance if you do normal installs/updates with mostly reads. If you are freshly installing the drive and moving a ton of games onto it, then yes, this could be an issue, but the QLC write speeds are still significantly faster than 1GbE if you’re intending only to download a ton of games at once. Otherwise, you can check the cache size in the relevant testing section.

Transfer Rates — DiskBench

We use the DiskBench storage benchmarking tool to test file transfer performance with a custom 50GB dataset. We write 31,227 files of various types, such as pictures, PDFs, and videos to the test drive, then make a copy of that data to a new folder, and follow up with a reading test of a newly-written 6.5GB zip file. This is a real-world type workload that fits into the cache of most drives.

We also see some write performance issues in DiskBench. This is dependent on cache size and speed, but for the most part should be limited by the interface speed. However, there are cases where copy speed will simply be slower, whether due to the controller or other optimization trade-offs. We can see that the 990 EVO, with TLC flash, is not exactly doing great here, and the 990 EVO Plus does much better. However, the 990 lags behind, and is very far behind the P310 and Blue SN5100.

So, we can put some of this slow speed on the Piccolo/PiccoloQ controller. To avoid getting too technical on this, we suspect it is partially architectural. This is reflected in power efficiency, as both the P310 and Blue SN5100 – with the Phison E27T and a proprietary Sandisk controller, respectively – are significantly more power-efficient than the 990 EVO, 990 EVO Plus, and as we’ll discover, the 990 as well. We also know that Samsung’s V9 QLC flash is not particularly inefficient.

As for the controller, there are reasons to design it differently. Reliability is one reason, especially if you sell a lot of OEM and enterprise drives that share the technology. Scaling is another, as you may use similar technology across your stack. You might want to optimize for a different sort of performance baseline; you may have unique endurance requirements, and you also might have to keep capacity in mind – enterprise drives, in particular, could make better use of this flash’s interface speed when scaling for capacity. Therefore, DiskBench results for our specific testing may not really be what Samsung is optimizing for, in which case the 990’s performance more or less hits expectations based on the 990 EVO and 990 EVO Plus. It just disappoints against drives like the NV3, which are otherwise inferior.

And to put a cap on it, yes, this is a consumer drive, but if you go back and read our 990 EVO review – and other recent Samsung SSD reviews, for that matter – you will see we underlined the idea that Samsung has been late to the party with less-than-leading performance recently. The fact is, Samsung has and has had bigger fish to fry, and its technology is sound but no longer looks amazing on the standard consumer benchmarks. That makes its products less relevant if you just want the fastest drive, although we’d argue there are secondary effects like drive reliability that still keep Samsung in the fight, certainly as an OEM option. It’s also true that consumer use has a lower bar – any halfway-decent NVMe drive is fast enough for daily driving – which means, sometimes you’re just buying the Samsung name.

Synthetic Testing — ATTO / CrystalDiskMark

ATTO and CrystalDiskMark (CDM) are free and easy-to-use storage benchmarking tools that SSD vendors commonly use to assign performance specifications to their products. Both of these tools give us insight into how each device handles different file sizes and at different queue depths for both sequential and random workloads.

ATTO gives us a clear image of how a drive performs over a range of block sizes. This can relate to different file sizes, for example, you probably have many files at or below 4KiB in size for various things but larger files, archives, and media files will usually be in units of MiB. Depending on what you’re using the drive for you may want to pay attention to how a drive performs within a certain range. For the quickest comparison, we show the results on a logarithmic scale and, there, the 990 shows significant dips for reads between 64KiB and 1MiB.

What you need to know is that flash is interleaved to improve performance, which means that larger I/O sizes will show higher throughput. A single, four-plane die, with modern 16KiB pages, can interleave up to 64KiB internally. If you have one die per each of four channels, that’s 256KiB. If you parallelize that over four dies per channel – which is the ideal amount and what we have with the 2TB 990 – then you reach 1MiB. While alignment here can impact performance, for example we sometimes look at six-plane flash these days, in general you will see a gradual throughput increase as you go. You’ll see this beyond 1MiB as data can and will be cached in volatile memory, either system-side or in a small cache on the drive. If you’re looking at higher queue depths, which we do with CrystalDiskMark, performance saturates even further as the controller is able to optimize data placement and retrieval with knowledge of what’s coming.

What this usually means is that QD8 is enough to get drives close together, while there will be more disparity at QD1. QD1 is much closer to real-world, as most operations will be at low queue depth, the vast majority at our below QD4 and the majority at QD1 or QD2.

We see that the 990 matches the P310 with QD1 reads, while some drives, like the X1070, do surprisingly well. We can assume that the controller plays at least a partial role here. The X1070 is a good example because, let’s be real, it’s not a drive a lot of reviewers liked. Yet, it has pretty good performance in this instance, indicating it could be a solid secondary storage drive. Fair enough. The 990 just doesn’t really have the response we like to see for that, but it’s fast enough to remain relevant. We got the impression in our X1070 review that its controller was chosen for cost savings and that was plenty for daily use, but we don’t think Samsung cheaped out on the PiccoloQ. Rather, Samsung is looking at the bigger picture, as it also sells drives with the Piccolo controller, including its OEM offerings.

Random latency seems much more important to a lot of people. We generally find that sub-50µs is one bar and another is sub-45µs. The 990 manages the former, which puts it above last-gen drives and some earlier Gen 4 drives, and budget drives like the X1070. It’s in the same ballpark as the NV3, too. It’s sufficiently far behind more popular budget drives, though, to draw our interest. In most cases you won’t notice it, but if you’re using this as your only drive and are sensitive to that, it’s not your best option. On the other hand, we think you have to balance that against pricing and some management of expectations. Any modern SSD is going to be very fast, and with current pricing it might be worth putting more weight on reliability, for example.

Sustained Write Performance and Cache Recovery

Official write specifications are only part of the performance picture. Most SSDs implement a write cache, which is a fast area of pseudo-SLC (single-bit) programmed flash that absorbs incoming data. Sustained write speeds can suffer tremendously once the workload spills outside of the cache and into the "native" TLC (three-bit) or QLC (four-bit) flash. Performance can suffer even more if the drive is forced to fold, the process of migrating data out of the cache in order to free up space for further incoming data.

We use Iometer to hammer the SSD with sequential writes for 15 minutes to measure both the size of the write cache and performance after the cache is saturated. We also monitor cache recovery via multiple idle rounds. This process shows the performance of the drive in various states including the steady state write performance.

Samsung’s TurboWrite 2.0 caching technology utilizes a fixed, static portion of pSLC combined with a much larger dynamic portion. These two zones have unique characteristics which, when taken together, ideally keep the drive feeling fast across a variety of workloads. The static portion ensures the drive always has some cache for random writes, while the dynamic portion varies with drive usage so that you always have ample cache. While the 990 EVO had 108GB total regardless of capacity, it’s more typical for Samsung to increase both caches in absolute terms as capacity goes up. This is the case with the 990 EVO Plus, which has a 216GB cache at 2TB. But we know from our 9100 Pro review that Samsung is quite capable of going with a larger cache. The general trend for consumer SSDs has been to go that way, especially for QLC-based and DRAM-less SSDs, as it better hides weak performance states.

Therefore, it’s not too surprising that the 990’s cache is pretty large. In its fastest state, it writes at almost 6.1 GB/s for over 57 seconds, for a cache in excess of 350GB. This is larger than the 2TB 990 EVO Plus’s but smaller than the 2TB 9100 Pro’s. Our suspicion is that the 990 follows the newer, larger scheme, but we’re dealing with QLC rather than TLC flash. QLC flash to pSLC is 4 bits to 1, while TLC is 3 bits to 1, so in relative terms the 990 lines up with the 9100 Pro. That’s all fine and good. As for how fast it writes, Samsung markets the 990 as having over 50% faster write performance than the 990 EVO, which is accurate simply because we’re moving from 1,600 to 2,400 MT/s, with newer flash and firmware.

Once the cache is exhausted, the drive has to write to the native QLC flash directly or fold data over from pSLC to QLC. The latter is slower but can reduce wear in some cases – folding uses predictable, sequential writes – and reduces the likelihood of errors in transmission. Considering the technology we mentioned above and how Samsung avoids problems with power loss, it makes sense that going slower is by design. In fact, given we know the expected speed of the flash – rated at 41 MB/s per die – we can reasonably assume the firmware wants this outcome. It’s not that the flash can’t handle higher speeds, even at the risk of endurance. It’s simply that for a consumer drive of this type, the response is reasonable and measured. Going faster would require reducing the cache size potentially, which tends not to be a good trade-off for this type of drive.

One interesting thing about the V9 flash is that it can operate in a pTLC caching mode. We don’t see that here. Honestly, that’s not too surprising: Solidigm’s 5-bit PLC flash effectively was designed to run as QLC/pQLC for enterprise, so it’s possible this pTLC mode was for cases where you might need that higher level of performance or endurance. After all, this is extremely dense flash even in such a mode, which points more at enterprise use.

We’ve seen QLC flash from Kioxia also optionally have this mode – and for that matter, Solidigm’s PLC can do pTLC, too – in the past, but that mode doesn’t appear to be designed for consumer use. There may be other reasons for not using it in a consumer product, such as power optimization, as consumer workloads probably benefit more from a straight pSLC and native/QLC hybrid.

Power Consumption and Temperature

We use the Quarch HD Programmable Power Module to gain a deeper understanding of power characteristics. Idle power consumption is an important aspect to consider, especially if you're looking for a laptop upgrade as even the best ultrabooks can have mediocre stock storage in terms of capacity and performance. Desktops are often more performance-oriented with less support for power-saving features so we show the worst-case for idle.

Some SSDs can consume watts of power at idle while better-suited ones sip just milliwatts. Average workload power consumption and max consumption are two other aspects of power consumption but performance-per-watt, or efficiency, is more important. A drive might consume more power during any given workload but accomplishing a task faster allows the drive to drop into an idle state more quickly, ultimately saving energy.

For temperature recording we currently poll the drive’s primary composite sensor during testing with a ~22°C ambient. Our testing is rigorous enough to heat the drive to a realistic ceiling temperature but real-world temperatures will vary due to the environment and workload factors.

Is the 990 power-efficient? Samsung markets the drive as being 38% more efficient than the 990 EVO – or that it cuts power consumption by 38% – which, technically, works with our numbers. It’s not a huge bar to hit as the 990 EVO was not very power-efficient. Even the X1070 is significantly more efficient! The 990, unfortunately, really doesn’t do well against other drives in its class, regardless of flash. We can’t chalk this up as being fully due to the controller because the 990 EVO Plus does well enough for itself.

This is actually expected since, for example, the Blue SN5100, which is using BiCS8 QLC, is less efficient than its BiCS8 TLC sibling, the Black SN7100. QLC and TLC flash of the same generation often have significant differences. TLC flash saw six planes first while QLC tends to be optimized for density. While it’s true that pSLC performance between the two is often comparable, behind the scenes the drive still has to deal with wear-leveling, garbage collection, and other maintenance with block granularity. QLC is slower, with larger blocks and pSLC taking more bits. So all else being equal, TLC often outshines it in power efficiency.

Our impression here, as is the case elsewhere in the review, is that this flash is basically V7 QLC with twice the density. Samsung uses impressive tricks to get it there; the flash is technically a bit faster and more efficient, and it has some neat changes that mostly apply to enterprise. This means you can have the 990 doing worse than the 990 EVO Plus with its V8 TLC. This is not perplexing. QLC flash is made for bit density, and Samsung intends to scale flash for a very long time. It also skipped V8 QLC for a reason. This doesn’t endear it to people wanting to buy this drive for laptops, although we assure you that this does use some cutting-edge technology, and we do think it should be very reliable. It’s just not going to be as efficient as you might expect.

Samsung is cognizant that its drives will end up with OEM variants in laptops and in many cases, shorter form factors. The 990 EVO wasn’t a great laptop drive due to its heat generation, but it works. The 990 is significantly better, so it, too, will work as a laptop drive. We think this drive deserves a heatsink in a desktop or PS5, and probably should have heatspreading of some sort anywhere else, if at all possible.

The question is, will it overheat? In our testing, we found that it got closer than we prefer to that point. Our maximum reported controller temperature was high relative to the initial throttling temperature, but a true composite value would be lower. Even so, the controller did get warm. On the other hand, our Iometer testing is far from real-world. We push our drives hard. This is not the sort of drive for a desktop replacement or high-end laptop in our opinion, although we think with typical workloads it’s perfectly fine. After all, the results here are better than the SK hynix Gold P31, which is a laptop staple. By all means, in a Gen 3 slot this thing will fly. If you’re hammering it at Gen 4 speeds, though, yeah, it’s not the coolest drive in town.

Test Bench and Testing Notes

We use an Alder Lake platform with most background applications, such as indexing, Windows updates, and anti-virus, disabled in the OS to reduce run-to-run variability. Each SSD is prefilled to 50% capacity and tested as a secondary device. Unless noted, we use active cooling for all SSDs.

Samsung 990 Bottom Line

The Samsung 990 is bound to be underwhelming for some, but none of our results should surprise. We know what this technology is and we’ve seen Samsung’s entries in recent years with the 990 EVO, the 990 EVO Plus, and the 9100 Pro. You could even put the 980 and 990 Pros into that mix. The move away from DRAM on the EVO Plus series, in particular, was a sign of the times. It’s not surprising to see the raw 990 – the 980 was TLC-based – go to QLC without the “QVO” addendum. The original speculation of the 990 QVO being a QLC 990 EVO, with the EVO itself being a surprisingly “slow” drive, was probably correct given the OEM evidence, and the 990 being a step up lets it command the 990 name by itself. To reiterate, this is exactly what we expected.

Skipping over the 990 QVO and V7 QLC flash is only sidestepping, and that’s likely because the market has changed so much over the last year or two. Bringing out a QLC-based 990 EVO equivalent just wouldn’t sell and might even make the brand look bad. It could certainly be done, and even still done, as an affordable SKU with better yields. But any 990 was going to be exactly what we got, instead. You need the faster flash to saturate PCIe 4.0 with a DRAM-less drive, and this was always going to be DRAM-less. Using a new or licensed controller with TLC flash would be weird, as it’d be going up against the existing 990 EVO Plus. Frankly, the 990 is a good 990 EVO replacement from retail and OEM perspectives, with one caveat: endurance. Samsung saves itself some headaches by reducing the warranty to three years, and as this flash is robust, it can just nudge up the TBW as a distraction.

We think that’s an important part of the message here. This flash seems designed for enterprise and has technological changes to back that up, with the main consumer benefits being the potential for increased reliability. But memory is still in high demand, and this has to be a budget part, so here comes the three-year warranty. Performance is not bad – it certainly beats earlier Gen 4 QLC-based drives and would beat the rumored 990 QVO as well. It’s just not really performance-focused. It’s also a much more efficient design, but that’s in comparison to Samsung’s own hardware. It’s merely mediocre there in the current landscape. Samsung seems to be building for the future with higher layer counts and bit density, so this lays the groundwork. A client drive seems almost like an afterthought. Users shouldn’t take that personally, but also shouldn’t underestimate this drive as it’s more than effective enough for its purpose.

In fact, in the era of Gen 3 drives returning and so many “box of chocolates” SSDs with random names and hardware, a reliable Samsung SSD is a nice option. Even with QLC flash. If you only need a budget drive to throw into a build or to upgrade an old PC, you get Gen 4 performance and a TLC-like experience for most things. We also feel this drive should be reliable and, although it runs hotter than we’d like, it’s not going to be molten like some other drives. It’s just a polished design by Samsung that fills a micro niche, and clearly it thought a response was needed. It’s not a lot different than our reaction has been to Samsung’s last few new drives, which have all been competent but largely never the strtong leader. That’s okay with us, as we can tell the manufacturer has a longer-term perspective; it just means a little less awe when you finish a build using a Samsung drive.

If you really want the best experience with a QLC-based drive, we still recommend the Crucial P310 – which is going away – or the Sandisk WD Blue SN5100. These offer incredible performance for QLC flash. Otherwise, there are some MP44Q-like drives out there that continue to be budget leaders. The 990 fits somewhere along there as a known-brand alternative. If you’re looking for Gen 5, DRAM, or TLC, then you’re also looking at a higher price tag. Frankly, QLC costs more than it should, in part due to enterprise demand. On the other hand, a modern QLC drive will provide an equivalent experience 99% of the time. The priorities are up to you. For us, the 990 is a fine primary drive for normal builds and OK for laptops, although we’d go cheaper for the PS5 and higher-end for an enthusiast machine.

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Tesla's AI5 chip is about to enter mass production at Samsung Foundry using the company's 2nm-class process technology, a principal engineer at Samsung Foundry disclosed in a LinkedIn post, as noticed by Sawyer Merritt. As it turns out, the chip has been taped out recently.

"The Tesla-Samsung Al5 chip has reached tape-out," James Kim, a principal engineer at Samsung Foundry, wrote in the LinkedIn post. "It is scheduled to be manufactured at the Taylor fab using our latest 2nm process and will soon be integrated into Tesla's newest products. It has been an honor to collaborate with the outstanding engineers at Tesla Palo Alto and Austin over the past several months."

Elon Musk demonstrated the first sample of Tesla's AI5 in mid-April and revealed that the processor will be concurrently made both at TSMC and Samsung Foundry. Apparently, AI5 implemented in a TSMC process technology reached taped out several months ahead of AI5 implemented using a Samsung Foundry.

Tesla’s AI5 processor module that Elon Musk demonstrated in April integrates a relatively compact accelerator die — roughly half a reticle in size, based on Musk's earlier remarks — alongside 12 SK hynix memory packages that appear to be standard GDDR6 or GDDR7 devices. The package relies on an organic substrate, and the memory components are labeled similarly to conventional discrete DRAM chips.

Tesla has not revealed the width of AI5's memory subsystem, but the presence of 12 memory packages points to a relatively broad external memory interface. Assuming the module indeed uses 12 GDDR6 or GDDR7 ICs, the processor would feature a 384-bit memory bus. Depending on the memory technology and transfer rates employed, this would translate into memory bandwidth ranging from 768 GB/s all the way to 1.536 TB/s.

The company has not disclosed AI5's peak compute performance, or other detailed performance specifications, but Musk has previously claimed that, in certain workloads, AI5 can deliver performance improvements of up to 40X compared to its predecessor.

Musk expects AI5 to be one of the most produced chip ever, which is why Tesla plans to use two foundries to make it. AI5 is projected to be used in Tesla cars, Tesla robots, and in Tesla's data centers.

Samsung is reportedly sampling its dedicated AI processor for next-generation AI PCs with leading PC makers, such as HP and Lenovo. The chip, codenamed Gaia, was developed by the company's System LSI business unit, and it is designed to offload AI-related workloads from the CPU and GPU, reports Chosun.

Samsung's Gaia is designed to accelerate generative AI workloads on PCs and is made using the company's 4nm-class fabrication process. The chip, which is essentially a neural processing unit (NPU), is currently being evaluated by HP in the U.S. and Lenovo in China to verify its performance and evaluate whether it makes sense to integrate Gaia into their systems due in late 2027 or early 2028.

The report does not detail how Gaia differs from NPUs that are integrated into AMD's Ryzen, Intel's Core, or Qualcomm's Snapdragon X processors as well as whether it can offer significant performance advantages. Meanwhile, the report implies that the NPU (or perhaps its derivatives based on the same architecture) could be used for Samsung's next-generation implementations of its processing-in-memory (PIM) technology.

Samsung's original PIM was designed to embed compute logic directly within the HBM memory array and reduce data movement between HBM memory modules and host processors. PIM was aimed to accelerate select workloads, but did not take off because AI and HPC GPUs became very efficient and were supported by mature ecosystems, unlike PIM.

Perhaps if Samsung's upcoming Gaia NPU gains support from hardware makers and ecosystem partners, then this will give a boost to Samsung's next-generation PIM implementation as well. However, standalone NPUs and PIM are so fundamentally different that we can barely imagine that they can share a common architecture. Yet, PIM logic can be a subset of an NPU in terms of supported instructions and data formats and they can certainly share a common software framework.

One of the interesting things to note about Gaia is that it was reportedly developed by Samsung's LSI division, the same business unit at the company that is responsible for Exynos processors, automotive solutions, connectivity chips, ISPs, DSPs, display drivers, and image sensors. Given the multi-faceted nature of Samsung's LSI unit, as well as its strategic importance for the company, Samsung must be pinning some hopes on Gaia.

We have contacted Samsung and asked for a comment about the report, but we yet have to hear back from the company.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

South Korean President Lee Jae-myung announced a ₩1,350 trillion (roughly $880 billion) 10-year public-private plan for semiconductors, AI data centers, and robotics on June 29. At the televised address in Seoul, he was flanked by Samsung Executive Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won.

The ₩1,350 trillion total combines a $520 billion semiconductor program with AI data center and robotics spending, most of it corporate capital expenditure rather than direct state funding. Samsung's Device Solutions division booked ₩53.7 trillion in first-quarter operating profit and expects 2026 to out-earn its entire prior semiconductor history. Samsung and SK hynix have pulled fab completion dates forward by as much as 12 years, while the transmission lines and water pipelines that those fabs depend on remain years behind.

Gigawatts of power deficit

The Yongin Semiconductor National Industrial Complex, the Samsung and SK hynix megacluster in Gyeonggi Province, is estimated to require 15 to 16 GW at full operation, close to 25% of total Seoul-metropolitan power demand, against local supply of about 1.9 GW, according to a National Assembly Research Service report. As of a January briefing, however, about 6 GW of the roughly 15 GW the complex needs had no finalized supply plan, with Samsung reportedly needing 9 GW (6 GW secured) and SK hynix 6 GW (3 GW secured).

Power in South Korea is generated on the coasts, from nuclear and liquefied natural gas (LNG) on the east coast and renewables in the southwestern Honam region, while the fabs sit inland, near Seoul. Closing that distance falls to state utility KEPCO, which is pursuing a ₩37 trillion, roughly 1,153-km 345 kV network to move east-coast and Honam power to Yongin, targeted for 2036. KEPCO's track record on long-distance lines is problematic, though; its losses from delays on the Bukdangjin-Sintangjeong line reached ₩1.17 trillion ($810 million), and that single project took 22 years to complete, with site selection alone running past a decade.

The east-coast link that's supposed to carry about 8 GW toward the capital region has its own history of local opposition, too. The Donghaean-Dongseoul high-voltage direct current line, a 280-km run from Uljin to Hanam requiring 436 towers, has faced repeated delays, and Hanam's 2024 rejection of a KEPCO substation expansion threatened the plan outright. Meanwhile, SK hynix pulled the completion of its fourth Yongin fab forward by 12 years, from 2045 to 2033, as announced in the recent $712.5 billion SK hynix commitment, meaning fabs are arriving faster than the power lines that feed them.

KEPCO and the government plan six LNG plants inside the Yongin complex, starting at about 3 GW and scaling toward 10 GW, to bridge the supply gap until the transmission network is finished. Both Samsung and SK hynix hold RE100 commitments to reach 100% renewable electricity by 2050, and the ruling Democratic Party's own carbon-neutrality committee has demanded the LNG plan be cancelled.

Water shortages

Aside from power, a large memory fab consumes upwards of 100,000 tons of water per day, and the Yongin national complex is projected to need around 800,000 tons per day once fully built. The plan to supply this runs in phases: roughly 200,000 tons per day from about 2031, drawn from Paldang Dam surplus and treated wastewater, followed by new intake facilities and pipelines to reach 600,000 tons per day by 2034. However, SK hynix's accelerated fourth fab is now due in 2033, a year before the integrated pipeline that's being built to serve it.

Local water disputes have already delayed the buildout, with objections from Yeoju City and Hanam City stalling pipeline permits, and one groundbreaking was cancelled outright. The friction is worse for the new southwestern cluster near Gwangju, where water may prove harder to secure than power, because the Yeongsan and Seomjin river basins hold only about half the water of the Han basin that supplies Yongin. Meanwhile, existing Seomjin and Juam dam supply contracts are already fully allocated, and the four planned southwestern fabs are estimated to need around 430,000 m³ per day of industrial water. Government projections put the Yeongsan basin at an annual shortfall of roughly 219 million m³ by 2030, before any of the fabs draw a single drop.

Financed by the memory boom

Samsung reported preliminary second-quarter 2026 operating profit of ₩89.4 trillion ($58.4 billion) on ₩171 trillion in revenue on July 7, a roughly 19-fold year-on-year jump and a record for any tech company. Its Device Solutions chip division booked ₩53.7 trillion of the company's ₩57.2 trillion first-quarter operating profit, and DS president Kim Yong-kwan told a July 3 town hall that 2026 chip profit will exceed the cumulative total the division has earned across roughly 40 years in the business. SK hynix, meanwhile, posted a record ₩47.21 trillion operating profit for 2025, overtook Samsung as South Korea's most valuable listed company in June, and filed to raise about $29 billion in a Nasdaq listing whose proceeds are earmarked for Yongin, Cheongju packaging, and EUV tools.

Those numbers rest on contract prices that have run sharply higher through 2026, with commodity DRAM up around 90% in the first quarter and 50% to 60% in the second, as memory makers tilted wafer capacity toward HBM. The same dynamic underpins the government's confidence and its exposure. Bank of America has argued that fears of a memory-cycle peak are premature, noting the industrial cluster won't produce meaningful output until 2033 at the earliest. Morgan Stanley cautioned — also on July 7 — that the memory industry is nearing a peak in its rate of change, while stressing that this doesn't indicate a downturn. A plan financed by a price surge inherits the risk that the surge doesn't last until the fabs it funds come online.

The plan is ultimately the flagship of a president who took office nine months ago, in a country that removed and jailed his predecessor. Yoon Suk Yeol declared martial law in December 2024, was impeached within days, and was removed by the Constitutional Court the following April. A snap election last June brought Lee Jae-myung to office, and in February this year, Yoon was sentenced to life in prison for insurrection. Industrial policy has held across the turnover, with the Semiconductor Special Act passing the National Assembly with bipartisan support in May, but its dedicated ₩2 trillion account doesn't begin operating until 2027.

South Korea caps the workweek at 52 hours, and a proposed exemption for chip R&D staff was cut from the Semiconductor Special Act before passage. Industry and the conservative opposition backed the carve-out, citing TSMC's three-shift operations and longer hours at Chinese competitors, while the ruling party and a coalition of labor organizations opposed it as corporate favoritism.

A stopgap now lets firms run R&D staff up to 64 hours per week for limited periods with labor-ministry approval. Samsung's foundry holds about 7% of the contract chipmaking market against TSMC's 72%, and SK hynix supplies most of the HBM feeding Nvidia's AI accelerators, so the plan directs its capital toward memory and leaves Korea's weaker logic position largely untouched. Lee's single five-year term ends in 2030, three years before the plan's fabs are due to reach meaningful output.

Samsung announced stellar results last night, noting a 19x quarterly increase in operating profit, allowing the firm to pass Nvidia as the most profitable in the world. Kim Yong-Kwan, president and head of corporate management, strategy, and operations for Samsung Electronics' Device Solutions (DS) division, said that the semiconductor unit's 2026 operating profit will exceed everything it has earned across roughly 40 years in the chip business at a company town hall last Friday, according to a report published Monday by Korea JoongAng Daily.

Brokerage consensus puts Samsung's full-year 2026 operating profit near 300 trillion won ($196 billion), and its second-quarter figure at about 84.6 trillion won ($55.1 billion). Samsung easily beat the consensus with $58.5 billion when it posted preliminary results on July 7, overtaking Nvidia's most recent quarterly operating profit of $53.54 billion and becoming the most profitable technology company in the world for the period, on the back of AI-driven memory demand.

Samsung's DS division booked 53.7 trillion won ($35.1 billion) of the company's 57.2 trillion won in total operating profit during the first quarter of 2026, roughly 94% of the total, which is why the division's projection sits so close to Samsung's full-year consensus.

"This year's profit will exceed the cumulative profit generated over the past 40 years since we entered the semiconductor business," Kim Yong-Kwan told staff, scoping the claim to the chip business rather than the wider conglomerate.

Samsung entered the semi space by acquiring Korea Semiconductor in 1974 and shipped its first 64Kb DRAM in the mid-1980s. SamMobile estimates the division's cumulative operating profit from 1985 to 2025 at under 300 trillion won. Samsung's smartphone, display, and appliance businesses have earned far more than that over the same period, so the record applies to memory and logic chips, not to Samsung overall.

Contract prices for DRAM and NAND have risen steeply through 2026 as AI server demand outran supply, pushing memory makers toward 40% to 50% operating margins on NAND in the first half of the year. Prices for 12 GB LPDDR5X modules have reached about $145, and Samsung is negotiating further commodity DRAM increases for the third quarter. The DS division's earnings move with those contract prices, and Samsung has told customers to expect tight supply through at least 2027.

Samsung is releasing preliminary second-quarter figures on July 7, so these record projections are still estimates. The reported profit will also absorb a profit-sharing agreement that pays chip workers 10.5% of DS operating profit as stock, worth as much as $26.6 billion this year. SK hynix is due to report its own second-quarter results on July 29, and analysts expect the two companies to post combined operating profits near 150 trillion won for the quarter.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

South Korean President Lee Jae Myung on Monday, June 29, announced an 800 trillion won ($520 billion) public-private investment plan alongside Samsung Electronics and SK Hynix to expand the country's chipmaking capacity, a move the government framed as essential to keeping South Korea competitive in the global artificial intelligence race. Lee unveiled the plan in a televised state address at his office in Seoul, flanked by Samsung Electronics Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won, the leaders of the world's two largest memory chipmakers.

"Right now is truly a decisive moment, as the landscape of the global economy is being reshaped," Lee said in televised remarks. "Major countries, including the U.S. and China, are engaged in all-out competition with massive stakes." He added that only through cooperation between the private and public sectors could South Korea hope to triumph. Industry Minister Kim Jung-kwan said the plan would let the country rapidly expand production by sharply shortening the timeline from licensing to construction.

The centerpiece of the partnership is the construction of four production facilities, with Samsung and SK Hynix each building two. According to the government, the new plants will be built in the southwestern part of the country, near the city of Gwangju, a mostly rural area far from the existing semiconductor base south of Seoul, where both companies operate major clusters. Samsung will also build packaging facilities for high-bandwidth memory (HBM) chips in Chungcheong as demand for the advanced components soars.

"HBM, which is indispensable for the training and inference of AI models, requires cutting-edge technology for stacking semiconductor chips," the Samsung chairman said. "We will focus our investment on HBM fabs, which require main-fab-level processes, alongside existing semiconductor back-end fabs in the Chungcheong region, including Cheonan and Onyang."

One detail the government did not provide was the split between public and private money, as the project is a combined public-private commitment rather than a government spending program. While it is not immediately clear how much of the 800 trillion won would come from the state versus the two chipmakers, the disclosed line items are comparatively modest.

Industry Minister Kim Jung-kwan said the government and industry would jointly invest more than 30 trillion won over 15 years across the semiconductor value chain, while President Lee said Gwangju and South Jeolla province would contribute a further 5 trillion to 20 trillion won. Kim put another 81 trillion won toward the Chungcheong packaging hub, though he did not say how much of that is public.

The balance of the headline number is widely expected to be company capital expenditure, with the state's role concentrated in subsidies, faster permitting, and infrastructure. Kim said the government would streamline approvals and bring fab construction forward by up to 12 years, from the mid-2040s to the mid-2030s.

The plan also absorbs and accelerates projects already underway. The government said it would help Samsung and SK Hynix speed up construction of their existing capital-region clusters, with SK Group pulling forward the ramp of its Yongin memory site from 2045 to 2033, part of a stated goal to double the country's memory output within five years. SK Hynix supplies the bulk of the HBM that Nvidia depends on for its AI accelerators, the very strain this expansion is meant to relieve. While semiconductors are the focus of the investment, with the priority being a decisive lead in memory chips, the companies will also work on AI robots, physical AI, and AI data centers.

The investment partnership appears to be the latest piece of a broader strategy. SK Hynix had already committed $15 billion to new semiconductor facilities in February, a figure that now reads as an early piece of the larger national framework. Earlier iterations of the country's cluster plan had pegged long-term investment at around $471 billion, stretching to 2047, so the new figure represents a substantial expansion as AI demand projections have climbed. The fabs are targeted for completion in the mid-2030s.

The announcement caps an extraordinary stretch for both firms. SK Hynix overtook Samsung in June to become South Korea's most valuable listed company for the first time in more than 25 years, lifted by its commanding lead in HBM, while Samsung's chip division alone booked 53.7 trillion won in first-quarter operating profit as AI-driven memory shortages are expected to strain the companies' capacity past 2027.

The scale of the investments also invites inevitable comparison. At roughly $520 billion, South Korea’s plan dwarfs the United States' CHIPS Act, which provided about $52 billion in direct subsidies, by a factor of ten. Although the comparison is imperfect, since the U.S. figure is a government subsidy while the Korean number appears to be mostly private investment that the state is coordinating.

The strategic logic is the same on both sides of the Pacific: secure domestic capacity for the chips that underpin AI, at a moment when the U.S., China, Japan and the EU are all pursuing their own semiconductor industrial strategies. For Seoul, the specific prize is memory, the segment where its two companies already hold a commanding global position, with the goal being to extend that lead rather than merely defend it.

Samsung, SK hynix, and Micron were sued on June 25th in the U.S. District Court for the Northern District of California, where 17 plaintiffs accuse the three memory makers of illegally coordinating to restrict DRAM supply and inflate prices that the complaint says have risen roughly 700% over four years. The class action, filed as Garciaguirre v. Samsung Electronics and assigned to Judge Noel Wise, invokes Section 1 of the Sherman Act and targets companies that together hold around 90% of the global DRAM market. Samsung and SK hynix have pleaded guilty to criminal DRAM price fixing once before, with the latter paying a $185 million fine in April 2005.

The complaint argues that the three companies used a coordinated shift toward high-bandwidth memory (HBM), the stacked DRAM that feeds AI accelerators, as a cover to curtail production of older DDR3 and DDR4 modules. That contraction in commodity DRAM, the plaintiffs argue, pushed prices to record highs while no rival could step in: building a new DRAM fab costs tens of billions and takes years, leaving the incumbents free to cut output without fear of being undercut.

The named plaintiffs include 14 individuals and three small PC businesses, among them Troy's Computers and Florida repair outfit My Florida PC, and they cite Apple's recent iPad and Mac price increases as evidence of the squeeze. They’re seeking class status, an injunction, and treble damages as a result.

However, this case revisits a precedent that was already established in the same courthouse. A 2018 class action brought by law firm Hagens Berman made similar claims about parallel production cuts, and the district court dismissed it in 2020. The Ninth Circuit upheld that dismissal in 2022, ruling the trio's conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by an illegal agreement.

It was held at the time that the plaintiffs’ eight “plus factors” didn’t clear Section 1’s threshold, which demands evidence of an actual agreement rather than the conscious parallelism common in a three-supplier market. The new complaint leans on the pivot to HBM as the additional evidence that this earlier lawsuit lacked.

The three memory makers have publicly stated they’re operating independently while redirecting capacity to HBM, and senior executives have warned the shortage could run for years. Investment bank Jefferies expects DRAM prices to rise another 40% to 50% in the third quarter and a further 30% to 40% in the fourth, with no meaningful relief before 2028. The allegations remain unproven, and the defendants have not yet responded in court.

We're keeping a close eye on all the best SSD discounts and keeping a constantly updated list here. Buying SSDs is not as cheap as it used to be, but there are still savings to be had, especially on newer drives.

External factors, such as tariffs and geopolitical issues, along with chip shortages, are pushing prices upward. In fact, it appears that shortages driven by AI data centers could persist for several years. That means prices will go up significantly in the foreseeable future. Luckily, for now, there are discounts available on some SSD models.

As always, you'll need to stay alert when you're choosing SSDs, as not every drive is born equal and worthy of your money or a place of honor in your PC or PS5. We're constantly combing through the best deals across multiple retailers, selecting the best of them based on the in-depth knowledge we've gained from our thorough reviews, extensive benchmarks, and comprehensive historical price analysis.

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• SATA or NVMe: SSDs either use the SATA or NVMe interface, with the latter being as much as six times faster (or more). All 2.5-inch drives are SATA, but M.2 drives could be either NVMe or SATA interface, though the latter is now rare. If you have a desktop or laptop that was built in the last 5 years, it almost certainly supports NVMe, which is faster. As SATA is old news, most of the best SSD deals are on NVMe drives.
• 2.5-inch or M.2: Most internal SSDs are either 2.5-inch or M.2 form factor. 2.5-inch drives connect to SATA ports and can replace old-school mechanical hard drives. M.2 drives look like RAM sticks and plug into dedicated M.2 ports. You won't find that many deals on 2.5-inch drives, but they can be useful for bulk storage, as many motherboards have a ton of SATA ports but only two M.2 slots.
• PCIe 3, 4, or 5: If you're buying an NVMe SSD, you can choose among PCIe 3, 4, or 5 interfaces with speeds increasing from a maximum of around 3,500 MBps sequential reads and writes to 8,000 MBps and 14,000 MBps. At this point, PCIe 4 drives are mainstream and offer the best value. PCIe 5 drives are extraordinarily expensive, require a newer-gen platform that supports them, and also generate a fair amount of heat. We're seeing the best SSD deals on PCIe 4 drives, which is the best standard for most people.
• Capacity: Price increases have upended the market in recent months, so it's going to be tricky to find a decent 2TB NVMe drive for less than $140, with high-performance models going for even more. 4TB drives are an even worse proposition, costing $250+, with some reaching over $400. If you really need to save money, a decent 1TB drive can still be found for $70 or $80.

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SK hynix overtook Samsung Electronics on Monday to become South Korea's most valuable listed company, the first time Samsung has surrendered the top spot on the KOSPI index since November 2000, according to Reuters. SK hynix shares closed up 5.6% to lift its market capitalization to 2,080.4 trillion won ($1.35 trillion), edging past Samsung's 2,066.7 trillion won excluding preferred shares, after a rally of more than 340% this year built almost entirely on demand for the high-bandwidth memory it supplies to Nvidia and other AI chip buyers. The company held 61% of the global HBM market in 2025, against 17% for Samsung and 21% for Micron.

SK hynix is one of the few pure-play memory makers, while Samsung spans smartphones, displays, contract chipmaking, and home appliances, among many other markets. Investors value the focus on pure-play memory higher because HBM carries the industry's fattest margins and ties suppliers to specific AI accelerators, unlike commodity DRAM that buyers can swap between vendors.

SK hynix built its lead by continuing to invest in HBM through the 2023 downturn, when a memory price collapse pushed it to a 7.73 trillion won annual operating loss. Samsung, by contrast, reportedly hit yield and qualification delays on its HBM3E chips that slowed major Nvidia orders, the proximate reason for a 61% share against a 17% one.

Samsung's remaining stronghold is conventional DRAM, but even that margin is shrinking. Bank of America estimates put SK hynix's monthly DRAM output at roughly 589,000 wafers this year against Samsung's 691,000. SK hynix is projected to expand output by about 38% between 2025 and 2028, compared with 17.5% at Samsung, which would cut the production gap to under 10% by 2028 from around 23% in 2025. The capacity both companies are pouring into HBM is not going into the commodity chips behind the memory shortage they've warned could run past 2027, and SK hynix has pledged to double its memory wafer output within five years.

Samsung, meanwhile, disputes the ranking, telling Reuters that its market cap should include preferred shares, which would lift its value to 2,246.4 trillion won. The gap also reflects the HBM3 and HBM3E generations rather than what comes next. Nvidia CEO Jensen Huang confirmed earlier this month that Samsung, SK hynix, and Micron all passed HBM4 certification for the Vera Rubin platform, and Samsung shipped the industry's first 12-layer HBM4E samples on May 29th.

SK Group Chairman Chey Tae-won, who pushed through the original Hynix acquisition despite internal opposition, explained the strategy in a book published in January. "What I really wanted to accomplish when we acquired Hynix was to transform it from a commodity memory producer into a mainstream semiconductor company whose products are indispensable," Chey said.

SOLD OUT: This deal has proven popular and is now out of stock at Amazon. A good alternative is the same Corsair Vengeance i7500 PC, but with an RTX 5080 and 32GB DDR5 RAM instead, for $3,299.99. That's still plenty of serious power for you to play games at 4K, but for $1,500 less than the sold-out model here.

If you're trying to build the best gaming PC that money can buy, right now, a pre-built is foten a better option. That's true of this Corsair Vengeance i7500. This RTX 5090 monster is currently 25% off at Amazon, and costs $4,799. That's cheaper than buying the GPU ($4,199) and 64GB of RAM ($913) all by itself.

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At the heart of this PC is the Intel Core i9-14900KF. Despite its age, this is still one of the fastest CPUs around, and in our testing, it's the best Intel CPU you can buy right now for gaming. While it can't quite match the heady heights of AMD's coveted X3D range, it's the perfect partner for the RTX 5090 GPU, which is the real star of the show here, and the fastest gaming GPU on the market by a country mile. Couple that with 64GB of RAM and a 2TB SSD, and you've got yourself what constitutes a bargain in 2026.

The Core i9-14900K (the KF version doesn't have integrated graphics) is Intel's Raptor Lake Refresh flagship. It features 24 cores and 32 threads, comprising eight performance cores and 16 efficiency cores. Base clock speeds are 3.2 GHz, with boosted speeds of up to 6GHz.

As mentioned, the real star of the show here is the 5090 GPU, which is simply the best gaming GPU money can buy. It blows the competition out of the water thanks to its 32GB of GDDR7 VRAM, 21,760 CUDA cores, and hefty power draw.

These premium parts are complemented by 64GB of DDR5-6000 Corsair Vengeance RAM (worth $913 in the current economy) and a 2TB SSD. The PC is housed in Corsair's 3500X case, featuring wraparound tempered glass and fans aplenty to keep everything cool. A Corsair Nautilus RS ARGB liquid cooler cools the CPU, and all of the fans come with RGB for a sleek gaming aesthetic.

As noted, the GPU and RAM in this build are currently priced at over $5,000, so this is a pretty incredible deal if you want to get a gaming PC that should last you for several years to come.

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If you've got a Nintendo Switch 2 and need more storage, the Samsung P9 Express microSD Express Card is now just $39.99 at Amazon, down from $79.99.

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With sequential read speeds of up to 800 MB/s and write speeds of 200 MB/s, the P9 is much faster than your average microSD card. This unique format for Switch 2 means you can store more games on the go, without needing to install and uninstall titles whenever you want to play them.

Flash storage is suffering from the AI shortage, but this $39.99 deal is just $7.50 shy of the best-ever price we've seen on this drive, which was $31.50 in March.

As you can see from our testing data, the Samsung P9 Express isn't the fastest microSD Express card on the market, but that's because this is a budget card that won't break the bank. It's a good bit cheaper than many other options, especially thanks to this discount.

The P9 is our best budget microSD Express card pick in the 256GB category, offering reliable performance and strong durability. It also comes with a pretty generous three-year warranty, where most rivals only offer one year. Samsung offers protection against water immersion, temperature changes, and even X-ray exposure (we're looking at you, airport scanners).

The card also features a Host Memory Buffer to boost data transfer speeds, as well as Dynamic Thermal Guard to prevent overheating and throttling.

This is the best price we've seen on this drive in a while, and it isn't likely to improve as Prime Day continues, so grab yourself a bargain and boost your Switch 2 storage before it disappears.

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Pricing for the best gaming monitors has generally been trending downward, particularly the 1440p high-refresh segment which continues to be the sweet spot for most gamers. Take for instance the Samsung Odyssey G5 G55C curved gaming monitor. Originally launched at $349.99, it is now available at its lowest-ever price of $189.99 on Amazon just days ahead of Prime Day, representing a discount of roughly 46%.

• Check out this deal on Amazon

The Samsung Odyssey G5 G55C gaming monitor offers a 32-inch 1000R curved VA panel offering a 165 Hz refresh rate and 1440p QHD resolution. This monitor is suitable for gamers with mid-range systems, especially if they are looking for a curved screen for increased immersion. It is also HDR10-compliant, which should result in vivid colors, although the peak brightness levels are limited to 300 nits.

The Samsung Odyssey G5 G55C gaming monitor offers a 32-inch 1000R curved VA panel offering a 165 Hz refresh rate and 1440p QHD resolution. This monitor is suitable for gamers with mid-range systems especially if you are looking for a curved screen for increased immersion. It is also HDR10-compliant, which should result in vivid colors, although the peak brightness levels are limited to 300 nits.

The 1ms MPRT response time achieved using backlight strobing, should help in reducing any sort of blurring while support for AMD FreeSync should ensure that the monitor and GPU stay in sync for a smooth and tear-free experience. In terms of connectivity, the monitor comes with HDMI 2.0 and DisplayPort 1.2 inputs allowing one to connect more than one device. There are no inbuilt speakers, however, the 3.5mm audio jack allows you to plug in headphones or external speakers.

At its discounted price of $189.99, the Samsung Odyssey G5 G55C offers compelling value. It may not offer the best color accuracy or HDR performance when compared to IPS or OLED displays, but it is definitely worth considering for gamers who are looking to step up from a 1080p monitor. With Prime Day just around the corner, it may be worth keeping an eye on similar deals, although this discount already represents solid value for anyone planning a gaming monitor upgrade.

If you're looking for more savings, check out our Best PC Hardware deals for a range of products, or dive deeper into our specialized SSD and Storage Deals, Hard Drive Deals, Gaming Monitor Deals, Graphics Card Deals, gaming chair, or CPU Deals pages.

The Bank of Korea has named performance bonuses at Samsung Electronics and SK hynix as a risk to the country's inflationary stability, warning in a price-stability report on June 17th that payouts worth several hundred thousand dollars per worker could push wages higher across the wider economy. The central bank found that special pay in the IT sector increased by 60.6% year over year in the first quarter, while wage growth elsewhere ran at just 2.1%, a gap wide enough that two chipmakers are now featured in national monetary policy. The bank held its benchmark rate at 2.50% in May and projects full-year inflation of 2.7%, above its 2% target.

SK hynix agreed last September to set aside 10% of its operating profit for worker bonuses, and Samsung committed 10.5% of its semiconductor operating profit after its union threatened an 18-day strike in May. These figures mean that a memory worker on a base salary of 80 million won ($52,400) stands to collect roughly 626 million won ($410,000) this year, while SK hynix staff could receive more than 700 million won ($454,851) if the company reaches 250 trillion won in annual profit. SK workers could see close to $900,000 next year on top of this year's haul.

In its price-stability report, the Bank of Korea modeled how concentrated payouts move prices. When the share of firms paying top-10% bonuses rises, consumer prices climb 0.05 percentage points roughly five months later, a lag effect that broad, even wage increases don’t produce.

Governor Shin Hyun-song has said that consumer prices should stay on a high upward path, with second-half headline inflation near 3%. The bonuses have already spilled into other areas, with labor groups citing them in next year's minimum wage talks, and card spending has risen fastest in the Gyeonggi Province districts around the two firms' fabs, where luxury sales have surged.

The payouts can of course be traced back directly to the AI-driven memory supercycle that has sent DRAM and NAND contract prices climbing through 2025 and 2026. HBM demand for AI accelerators has handed Samsung and SK hynix record operating profits, with profit-linked bonus deals converting that windfall for the companies into bags of cash for workers in the companies’ microchip divisions.

Senior South Korean policymaker Kim Yong-beom spooked markets last month when he floated the idea of a “national dividend” in a Facebook post, writing that gains from the AI infrastructure era were built on an industrial foundation the entire nation accumulated over half a century. Seoul officials later said it had no such plans, however.

Portable storage for your files and data isn't getting cheaper, thanks to the AI boom, which is why it's important to pick up a bargain while you can. Luckily, this microSD card could be a good option for your portable devices, from laptops to handhelds, along with cameras, drones, consoles, and more. This 256GB Samsung P9 Express microSD card is down to just $47.99 right now, reduced from $79.99, and saving you 40% in the process.

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You can expect maximum sequential read speeds of up to 800 MB/s, with write speeds of 200 MB/s. Those speeds make this Samsung P9 Express card up to four times faster than a typical UHS-I microSD card. It also features Host Memory Buffer (HMB) functionality to help improve data transfer speeds, with Dynamic Thermal Guard (DTG) support to help stop the card from overheating and limiting its performance.

Durability is important with microSD cards, and Samsung reckons this model is well protected against water immersion, extreme temperature variations, and even X-ray exposure. Ultimately, though, if you get it a bit wet, or drop it, you shouldn't lose your data. It comes with a 3-year limited warranty, and also supports Samsung's Magician software, which can help you monitor the card's health and to double-check that it's a genuine product.

There are a good set of reasons why you might want to pick up a card like this, especially if you're on the go a lot, but it's a firm recommendation if you're looking for a microSD card specifically for the Nintendo Switch 2. The Switch 2 is one of the first consoles to offer microSD Express support, meaning it can use this Samsung P9 Express card's faster storage speeds compared to older UHS-I cards. For gaming on a handheld, expect faster load times and smoother performance, especially in the more demanding games.

Whether it's a Switch 2, laptop, or camera, the Samsung P9 Express is a great option for fast, future-proofed expandable storage. You'll want to grab this 256GB version for just $47.99 right now before it sells out or the price goes up.

If you're looking for more savings, check out our Best PC Hardware deals for a range of products, or dive deeper into our specialized SSD and Storage Deals, Hard Drive Deals, Gaming Monitor Deals, Graphics Card Deals, Gaming Chair, Best Wi-Fi Routers, Best Motherboard, or CPU Deals pages.

Are you stuck with just one monitor or a display under 27 inches? How about you treat yourself to this rather large and luxurious Samsung monitor for your gaming setup? This large 49-inch ultrawide gaming monitor has a resolution of 5120 x 1440 pixels, which is the same as putting two QHD monitors next to each other. Or you could go the other way and use this ultrawide monitor to condense multiple screens into one visual display, remove any bezels in your view, and make it the focal point of your battlestation. Samsung's Odyssey G9 (G95C) is currently reduced to just $664.99 at Amazon, down 34% in price from its original $999.99 tag, a saving of $335.

• Check out this deal at Amazon

The Samsung Odyssey G9 G95C gaming monitor is a massive ultrawide display that features a 49-inch SVA panel with a 1000R curve for extra immersion when gaming. It has a dense 109 PPI resolution, thanks to a 5120 x 1440 pixel display, paired with a fast refresh rate of 240Hz and a short response time of just 1ms. It also supports AMD FreeSync Premium Pro, for adaptive sync in games to match in-game frame rates to your monitor to eliminate screen tearing.

When we reviewed the Samsung Odyssey G9 G95C monitor, we were impressed by the performance of Samsung's monitor. It has impressively high brightness, a stellar response time for an SVA panel, and other features that helped us to easily reward it with a rating of 4.5 out of 5 stars, and an Editor's Choice. Our main concern was the original price of the monitor, but with this discount, that price is a mere shadow of its initial release price.

In testing, the Samsung Odyssey G9 G95C had the fastest response times for full black to white transitions, compared to other similar spec monitors that we had also reviewed.

The Odyssey G9 G95C has impressively high brightness with 1000 HDR support. It comes with multiple USB ports thanks to a USB hub with three USB Type-A ports to connect peripherals and a 3.5mm jack for audio. There are multiple video input connectivity options to take advantage of, including two DisplayPort 1.4 inputs and one HDMI 2.0 port.

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Samsung displayed its first physical mockup of HBM5 memory at Computex 2026 in Taipei. Tom's Hardware dropped by to see its pairing of the eighth-generation AI memory with a new in-package cooling structure it calls Heat Path Block, or HPB. Just last week, rival SK hynix unveiled its own iHBM thermal design, meaning both companies are now focusing on the same heat bottleneck in the die-to-die interface that connects memory to the processor. Samsung also confirmed that it’ll fab HBM5’s base die on its in-house 2nm process, down from the 4nm node used for HBM4 and HBM4E.

Rather than letting heat escape outward through the core dies, HPB builds a separate set of thermal pillars that pull heat from inside the stack and carry it to a spreader sitting above or beside the package, according to Samsung at Computex.

The design concentrates on the D2D PHY layer, the high-speed link between the HBM base die and the GPU, where power density and temperatures increase exponentially as stacks grow taller and run quicker. Samsung said it has already implemented and verified HPB on HBM4E, the generation whose first 12-layer samples it began shipping last month at 14 Gbps, scaling to 16 Gbps, with 3.6 TB/s of bandwidth per stack.

Samsung runs both a memory business and a logic foundry, letting it build the HBM5 stack and the 2nm die beneath it in-house. "AI systems are becoming more powerful and densely integrated, making heat management, data-processing efficiency, and packaging stability just as important as memory performance itself," Song Jai-hyuk, president and CTO of Samsung's Device Solutions division, told reporters at Computex, according to the Korea Herald. Song said the company would keep building its competitiveness in next-generation memory through cooperation with partners, including Nvidia.

Last year, a roadmap from KAIST projected HBM5 reaching a 4,096-bit interface, roughly 4 TB/s per stack, and about 100 watts of per-stack power, a thermal load that goes a long way in explaining why both Korean memory giants are reworking their packaging now rather than at launch.

SK hynix faced the same problem via a different route. Its iHBM design embeds cooling elements made of electrically non-conductive, thermally conductive silicon into the D2D PHY layer, which the company said cuts thermal resistance by more than 30% against current products.

SK hynix has opted to place a cooling element directly at the hotspot, while Samsung has built a route to evacuate heat away from it. Both methods are slated to debut with HBM5, but it’ll be a little while before we see either in action, as neither company expects it to reach mass production before 2028.

We’ve seen numerous announcements from major players in the gaming monitor space over the past few days, including Alienware, Asus, and Gigabyte. Not to be left out, Samsung also has five new gaming monitors in 27-inch and 32-inch screen sizes across the Odyssey G8, OLED G8, and Odyssey OLED G7 product families.

The Odyssey G8 is available in 27-inch (G80HF) and 32-inch (G80HS) sizes, both featuring IPS panels. The 27-inch model features a 5K resolution (5120 x 2880), which results in 218 pixels per inch (PPI). The monitor supports dual-mode operation, so at native resolution it maxes out at 180 Hz. At 2560 x 1440 resolution, the maximum refresh rate jumps to 360 Hz.

The 32-inch model bumps the resolution to 6K (6,144 x 3,456) and 224 PPI. This monitor also supports dual-mode operation, with a 165 Hz refresh rate at 6K, and a 330 Hz refresh rate at 3K (3,072 x 1,728).

Both monitors have a typical brightness of 350 nits (400 nits peak), support G-Sync and FreeSync, and include two HDMI 2.1 ports and one DisplayPort 2.1 port.

There are also two new additions to the Odyssey OLED G8 family, the 27-inch and 32-inch G80SH, which feature QD-OLED panels. Specs-wise, the monitors primarily differ in screen size and brightness (while both peak at 1,000 nits, the 27-inch model has a typical brightness of 250 nits versus 300 nits for the 32-incher).

With that said, both offer a 4K resolution (3,840 x 2,160), a maximum refresh rate of 240 Hz, and a 0.03 ms response time. AMD FreeSync Premium Pro is supported, although there is no mention of Nvidia G-Sync compatibility. You'll find two HDMI 2.1 ports, a DisplayPort 2.1 port, and a USB-C port (96-watt Power Delivery) for your video needs.

Finally, there's the Odyssey OLED G7 (G73SH), which is a dual-mode 32-inch OLED panel. It's another 3,840 x 2,160 panel, this time with dual-mode capabilities: it operates at 165 Hz at 4K and 330 Hz at 1080p. The monitor boasts a 1,500,000:1 aspect ratio, 275-nit typical brightness, and 1,300-nit peak brightness (1.5 percent window). The Odyssey OLED G7 has one HDMI 2.1 and one DisplayPort 1.4 port.

The 27-inch and 32-inch Odyssey G8 are priced at $949.99 and $1,599.99, respectively. The 27-inch and 32-inch Odyssey OLED G8 come in at $1,099.99 and $1,299.99, respectively, while the Odyssey OLED G7 costs $1,099.99. Samsung is also currently offering up to a $300 E-Certificate when purchasing these monitors from its online store.

South Korean media has noted a surge in spending on luxury goods following big bonus payouts to semiconductor workers. For example, the Chosun Daily (machine translation) reports that luxury consumption in southern Gyeonggi Province, where the nation’s 'Semiconductor Belt' is located, has rocketed. In one local department store, some luxury goods category sales are up nearly 150%. The flood of cash and spending shows that towns in Gyeonggi Province are now enjoying their own 'Gangnam Style.'

The Korean news source provides some interesting stats showing the rapid increase in conspicuous consumption since the fab workers at Samsung and SK hynix earned their envy-inducing bonuses. At a department store/mall called Shinsegae South City, located in Yongin, Gyeonggi Province, luxury jewelry sales in May were up 146.3%, it says. Moreover, luxury watch sales rose 85.3%.

Chosun Daily also shared some retail stats for the Lotte Department Store Dongtan Branch (also in Gyeonggi Province). It says that from Jan 1 to May 27, 2026, luxury sales were up 40% compared to the same period last year. A breakdown of these figures shows customers didn’t just target luxury brands but big-ticket home appliances (a category up 30%). A statement from this department store shows they are aware of the economic driving force behind the spending on luxury goods. "Sales of high-end goods such as luxury and home appliances have increased due to the boom in semiconductor companies, the creation of advanced industrial clusters, and the move-in of new large apartment complexes," said a store statement.

It was a similar story at The Hyundai Department Store, Pangyo Branch (also in Gyeonggi Province). Here, luxury goods sales were up 46.1% in May. That compares with an increase observed across all Hyundai Department Store stores nationwide of about 32%. High-end watches and jewelry (66%) and high-end clothing brands (36.9%) were major contributors to the sales boom.

With locals snapping up luxury goods like kids picking up candy, the semiconductor boom in South Korea looks like it will be highly beneficial to mostly European brands like Chanel, Hermès, Prada, Gucci, Rolex, Cartier, etc.

Recent reports suggest the good times are rolling at SK hynix, where workers are tipped to receive bonuses of up to $900,000 next year, on top of $447,000 this year. It's good to see the huge influx of RAM and NAND cash not just going to Samjeon Nix (Samsung Electronics, SK hynix) corporate accounts, or one or two billionaires, but that the good times are being shared with those at the coal face.