Intel announced at its Vision 2024 event that the next-gen Granite Rapids and Sierra Forest processors will be branded ‘Xeon 6,’ thus dispatching with its old nomenclature that used generational designators, like the preceding ‘Fifth-Gen Xeon Scalable’ models. This new branding somewhat mirrors Intel's new simplified branding for its consumer chips, which it announced last year. Intel also provided an update on the launch schedule, indicating the Sierra Forest and Granite Rapids chips remain on track. The company also briefly mentioned new software support for the MXFP4 data format, which the company says allows the CPUs to run 70 billion parameter Llama-2 models and reduce next-token latency by up to 6.5x compared to fourth-gen Xeon. 

Intel’s existing 'Emerald Rapids' Fifth-Gen Xeon models won’t see a rebrand, so the new branding nomenclature will apply only to Xeon 6 and newer processors. The company says the new branding makes it “easier to tell a unified Intel Xeon story, eases customer navigation with intuitive organization, and amplifies the performance signals.”

As you can see in this table that outlines the current-gen Xeon product stack, Intel’s branding can be more than a little confusing. Intel says this new branding will be simpler and easier to understand, and it will discard some of the sub-brands, though the company didn’t provide further details.

Intel’s current product stack has 32 models divided into six primary swim lanes (second slide). These include processors designed for the cloud, networking, storage, long-life use, single-socket models, and processors designed specifically for liquid-cooled systems. The stack is also carved into Platinum, Gold, Silver, and Bronze sub-tiers. 

It isn’t yet clear how Intel will arrange the Xeon 6 lineup to reduce confusion, but with plans to launch Sierra Forest this quarter, we expect to learn more details soon.

Intel says its Xeon 6 Sierra Forest processors, the company’s first data center chips to have an architecture comprised entirely of efficiency cores (E-cores), will arrive as scheduled this quarter. To that effect, Supermicro also announced the early availability of Sierra Forest chips in its Early Ship program and free remote access for testing and validation through its JumpStart program. 

Intel has already detailed both its Sierra Forest and Granite Rapids processors. The Sierra Forest chips have an E-core-based architecture designed to deliver the ultimate threaded heft for scale-out, cloud-native, and containerized environments. You can read the deep-dive architectural details here. The chips employ CPU chiplets with the Intel 3 process combined with twin I/O chiplets based on the Intel 7 node to provide a flexible architecture that can scale to higher core counts by adding more chiplets.

As before, Intel claims Sierra Forest delivers a 2.4X improvement in performance per watt and a 2.7X improvement in performance per rack. Intel also claims that 72 Sierra Forest server racks will provide the same amount of performance as 200 server racks equipped with the aging second-gen Xeon models, thus saving a megawatt of power. The company has also announced a 288-core Sierra Forest model that will arrive later this year.

Intel's Granite Rapids processors slot in for general-purpose workloads and feature a more standard performance-core (P-core) based design. Intel's press release mentions that the processors now support the MXFP4 data format, a new narrow-precision format that's championed by OCP with broad support from other vendors, like Nvidia, AMD, and Arm, among many others. 

Intel says MXFP4 software support enables Granite Rapids to reduce next token latency by up to 6.5x over its older fourth-gen Xeon using FP16, and that it allows the CPU to run a 70 billion parameter Llama-2 model. Intel hasn't shared any more detail about this caveat beyond a bullet point on the press release, but we'll be sure to follow up as more details emerge.

Intel says the Granite Rapids processors will follow ‘soon after’ Sierra Forest but hasn’t committed to delivering them in a specific quarter.

When Intel's Xeon processors -- codenamed Sierra Forest -- were formally announced last year, the company even disclosed their maximum number of 288 cores, but Intel has never revealed its performance expectations. At this year's Mobile World Congress, Intel disclosed that its upcoming 144-core CPU would increase per-rack performance by 2.7X compared to its 2021 platform while consuming around 30% less power. 

Intel's Xeon 'Sierra Forest' processors come with up to 288 e-cores are designed primarily for cloud data centers as well as various infrastructure workloads, such as handling 5G core networks, that can benefit from high core count and relatively low per-core power consumption. 

Intel says that when compared to a dual-socket 2021 Xeon Scalable platform with a total of 48 cores (6252N), machines based on the 144-core Xeon 'Sierra Forest' processors (a total of 288 cores per dual-socket server) will offer up to 2.7X higher performance per rack for 5G core workloads while consuming less power, up to 30% when used with Intel Infrastructure Power Manager (IPM) Software while maintaining performance networks. Intel says that its choice of comparing two 24-core processors against two 24-core models is to highlight a widely deployed telco config. 

Intel's IPM software seems to be as important as the 144-core Sierra Forest processor itself, as it is designed to help 5G core operators reduce CPU power usage without compromising key performance metrics by using the built-in telemetry of Intel's Xeon processors. The program is said to be compatible with existing and future Xeon-based network infrastructure, so it should work on a variety of platforms. 

Without any doubt, a 2.7 times performance increase over a three-year-old platform is an impressive improvement, but we do have to take the extra cores into account.

Intel did not disclose which workloads were impacted. 5G core workloads encompass various tasks and processes crucial for the functionality of a 5G telecommunications system's core network. These workloads include managing data movement, controlling network functions, creating separate virtual networks, and ensuring that different services get the right level of quality, such as fast data speeds, low delay, and connecting many devices. 

In addition to disclosing some of the advantages of its Sierra Forest processors due in 2024, Intel also said that it would launch its Granite Rapids-D CPUs in 2025. These Granite Rapids-D processors will address edge computing, networking and communications, and storage servers, among other workloads.

Edit 2/28/24 8:40am PT: Clarified Intel's test configuration. 

Intel Clearwater Forest processors made an appearance in a Linux kernel patch which was shared earlier today. This is significant, as Phoronix notes, because it is the first patch addressing Clearwater Forest, an upcoming all E-Core Xeon processor family that is expected to launch sometime in 2025. Moreover, in the patch notes, we see that Clearwater Forest chips will use Atom Darkmont cores.

As a first patch, the support for Clearwater Forest delivered in this release is extremely limited. This is typically the way things happen, though, and it is still pleasing to see information at such an early stage. Specifically, all the developers have added to this new Linux kernel patch concerning Clearwater Forest is the new 0xDD (221) model number for these CPUs. Additionally, the patch appears to confirm that Clearwater Forest Xeons will use Intel’s Atom Darkmont (18A) cores.

If an all E-Core Xeon sounds familiar, it is because Intel is busy getting Sierra Forest ready for launch. Sierra Forest will be the firm’s first all E-Core (Atom Crestmont) Xeon processor family and is due sometime this summer. Intel's Open-source Linux software engineers have already laid the groundwork for Sierra Forest, enabling hardware support in the OS as well as related open-source projects.

Sierra Forest is an interesting server processor product that appeared on Intel roadmaps last March, and was first officially detailed last August with up to 144 E-Cores, but the product family was extended in September with the announcement of CPUs packing up to 288 E-cores.

We have seen some unofficial benchmarks from what appears to be a system packing a 144 core Sierra Forest CPU. If the Geekbench scores we saw in December were genuine and representative, the upcoming Xeons will pack a big punch in multi-threaded workloads, and they should do so efficiently. Meanwhile, single-core performance was predictably lackluster, but it shouldn’t matter for the intended workloads. It will be interesting to see how Intel steers the performance of Clearwater Forest on 18A to be a worthy second-generation release.

We hope to see some more leaks, spills, and sideways glances at both Sierra Forest and Clearwater Forest Xeons in the coming weeks and months as representatives of a new breed of server chips from Intel’s stables.

Along with introducing its IDM 2.0 paradigm in 2021, which involves using both internal and external production capacities, Intel also outlined its impressive plan for 'five nodes in four years,' now dubbed '5N4Y.' The culmination of that impressive project is supposed to be the company's 18A (1.8nm-class) technology, which is scheduled to become production-ready in "early 2025." Little is known about the company's plans beyond 18A, but now it says it will reveal its new roadmap in February. 

Intel plans to host its IFS Direct Connect event on February 21, where Intel Foundry Services will discuss its roadmap beyond 5N4Y. Featured speakers at the event are Pat Gelsinger, Chief Executive of Intel; Stu Pann, General Manager of IFS; Keyvan Esfarjani, General Manager of Intel's Supply Chain and Operations, as well as Ann Kelleher, Executive Vice President responsible for Process Technology Development at Intel.

If you're interested in the process technologies that are set to come after 18A, Ann Kelleher's presentation is the one to watch. What to expect from Intel beyond 18A is up in the air, but we expect the company to continue building on its latest innovations. Intel's 20A introduces RibbonFET gate-all-around (GAA) transistors and PowerVia backside power delivery network (BSPDN), and 18A refines both technologies. At the recent IEDM event, the company outlined a further evolution of BSPDN, so expect one of Intel's process technologies after 18A to use this feature. GAA will obviously evolve as well, so we expect Intel to innovate in this realm, too.

Meanwhile, the disparity in the requirements of chips for different applications necessitates Intel to specialize in various process technologies, something that Intel does already. For example, Intel 3 offered a denser high-performance library and increased drive current, which is just what the doctor ordered for data center-class processors. Whether this approach will be extended and Intel will offer other specialized nodes remains open to question.

Intel describes the IFS Direct event as follows:

"Hear from Intel leaders, technologists, and partners as they share details of our strategy, process technology, advanced packaging, and ecosystem. Learn how Intel Foundry Services can help you build your silicon designs leveraging Intel’s resilient, security, and sustainably oriented, source of supply." 

The career profiles of the event speakers indicate that Intel plans to disclose both the technical and executive directions of Intel and IFS. However, the nature of the event implies that its focus will be squarely on Intel Foundry Services operations.

An image of an unknown socket presumably designed for Intel's processors has been published by @Yuuki_Ans, a renowned hardware leaker. The socket in question is called LGA4710 and might be destined for special-use processors from Intel or custom 'off roadmap' system-on-chip designs. 

The published images depict a socket entitled 'LGA4710-2' and 'LGA-4677 LGA-4710.' Lotes, a major maker of CPU sockets and other connectors, manufactured the socket.

Modern Intel 4th Generation Xeon Scalable 'Sapphire Rapids' processors use the LGA4677 package, and 5th Generation Xeon Scalable 'Emerald Rapids' CPUs will keep using this form factor. Meanwhile, 6th Generation Xeon Scalable 'Granite Rapids' processors will use the LGA7529 socket, just like their 144-core Sierra Forest counterparts aimed at cloud data centers. As a result, it is unclear what the LGA4710 package is for. 

Given that the LGA4710 socket is physically the same as LGA4677, perhaps the main question is why Intel would design a new socket for a new processor form factor aimed at the same applications as existing processors. While we are not exactly in the business of guesses, we can provide a few possibilities for Intel's LGA4710 package.  

Typically, new sockets are made to enable new processors with different power and connectivity requirements. Therefore, LGA4710 can just enable higher thermal design power, or the support of different connectivity features, such as a newer version of PCIe or CXL. Since the new processor form factor is physically the same as Intel's LGA4677 and it is possible to install an LGA4677 processor into a 4710-pin socket and vice versa, power requirements of LGA4710 processors should not be too different because otherwise, chips might end up damaged. 

An attentive reader has probably noticed by now that we purportedly avoided calling products in an LGA4710 form factor a CPU, which is for a reason: Intel sells a boatload of data center and workstation products, so it may use the LGA4710 form factor for a next-generation workstation or special-purpose server system-on-chips, CPUs, FPGAs, or even GPUs. For example, the company is working with Ericsson on custom chips for RAN applications. In addition, Intel also makes custom processors for Meta's Facebook, which runs vast data centers that cost about a billion dollars each.  

For now, it is hard to say what LGA4710 is. The number of possibilities is vast, but we assume that the answer should be quite simple.

With the multi-tile designs of its client CPUs, Intel can improve its built-in graphics cores and bring their capabilities and performance closer to those of standalone GPUs. Starting from Arrow Lake processors due next year, its new built-in Xe-LPG Plus GPUs will gain eXtended Matrix Extensions (XMX) support, a technology for advanced XeSS upscaling features as well as for acceleration of artificial intelligence workloads, reports Coelacanth Dream.

Intel is set to start rolling out its Xe-LPG GPU microarchitecture, starting with Meteor Lake processors. Xe-LPG represents the company's 2nd Generation low-power Xe architecture that is further enhanced for gaming and is therefore closer to the Xe-HPG microarchitecture used for discrete GPUs. But as it turns out, even the Xe-LPG does not support XeSS. This is not going to substantially hurt the product as XeSS can work without XMX, and Meteor Lake has a built-in AI accelerator, which Intel aggressively promotes among independent software vendors (IHVs) anyway.

But Intel will still add XMX to its Arrow Lake processors and Xe-LPG Plus GPUs. XMX extensions are designed for matrix multiplication operations in FP64, FP32, FP16, and bfloat16 formats, which are crucial in many AI algorithms, including neural networks. Neural networks are used both for AI workloads as well as graphics enhancements, so the addition of XMX to Arrow Lake will play a positive role in graphics processing.

Perhaps an even more important thing about the addition of XMX to a mass-market client CPU is that XMX will be supported on hundreds of millions of PCs within a year, which will greatly popularize the technology and will offer significant incentives for software developers to take advantage of it. 

Although Intel's Xe-branded built-in GPU cores are quite capable, the company still made some efforts to reduce its silicon footprint to cut costs. As a result, Intel's Xe-LP and Xe-LPG GPUs lack XMX, which is important for advanced XeSS upscaling and AI capabilities. As it turns out, with a multi-tile Arrow Lake processor design, the company can finally add XMX to its built-in GPUs. The only question that remains is whether XMX will also be supported by the Lunar Lake MX platform, which again places GPU into the same piece of silicon with CPU.

Intel's x86 chips are now forging into new territory — leaked slides published by prominent hardware leaker @YuuKi_AnS (yet quickly removed) indicate that the compute tile of the Lunar Lake MX processors will be made using TSMC's N3B fabrication technology, marking the first time Intel has used outsourced process node tech for its highest-end x86 cores. Intel's Lunar Lake processors are set to feature an all-new microarchitecture designed from the ground up to offer breakthrough performance-per-watt efficiency, primarily for mobile devices, but it is unclear how old the slides are — these could reflect an older plan for the series.

According to the slides, Intel's Lunar Lake MX platform lineup will offer processors with up to eight general-purpose cores (four high-performance Lion Cove and four Skymont energy-efficient cores), 12MB cache, up to eight Xe2 GPU clusters, and up to a six-tile NPU 4.0 AI accelerator. Depending on the power target, the platform will support 8W fanless as well as 17W – 30W fanned designs.

The compute tile will purportedly be produced on TSMC's 3nm-class N3B process technology. Meanwhile, Intel itself indicated that its Lunar Lake CPUs will use its own 18A (1.8nm-class) fabrication process. 

Intel's Lunar Lake MX platform will retain Intel's multi-chiplet Foveros3D-interconnected design approach. Still, to reduce its physical footprint, Intel plans to pack the CPU, GPU, and memory controller into the same tile while putting everything else into the SoC tile, according to the slides.

In addition, Intel's Lunar Lake MX is aimed primarily at laptops, and it is set to come with 16GB or 32GB of LPDDR5X-8533 memory-on-package, which will further reduce the platform's footprint and improve performance.  

Based on Intel's estimates presented in the slides, its Lunar Lake MX design will save 100 to 250mm^2 of space compared to typical designs with memory outside the CPU package.  

While it is odd to see Intel using TSMC's N3B process technology to build its Lunar Lake MX processors, it is not completely unexpected. Since the company wants to put CPU and GPU cores into the same piece of silicon, it might just make more sense to build everything on TSMC's N3B because GPUs tend to be bigger than CPUs and re-architecting Xe2 GPU for Intel's 18A node could take more time than the company would like to spend on its low-power mobile processor. 

Nonetheless, this is the first time Intel will use a third-party process technology for one of its flagship CPUs, highlighting the flexibility of its IDM 2.0 approach to design and manufacturing.

It is not uncommon for server processors to support instructions that are not supported by client CPUs. But it looks like Arrow Lake S processors for desktops will support instructions that will not be supported by Arrow Lake CPUs for laptops, as noticed by @InstLatX64.

As it turns out, Arrow Lake processors in LGA1851 packaging will support such instructions as AVX-VNNI-INT16, SHA512, SM3, and SM4. In addition, the CPU will support an LBR Event Logging feature. The exact reasons why Intel decided not to implement these features into mobile parts is unclear, but it is possible that the company could not add support because ultra-low-power x86 cores in the SoC die do not support these instructions and therefore they will not be enabled on the compute die as well. 

Meanwhile, the new instructions may actually be missed on the mobile parts. Intel's AVX-VNNI-INT16 are Vector Neural Network Instructions with 16-bit integer data types designed specifically to accelerate convolutional neural network (CNN) and deep learning workloads, which should be quite handy for generative AI applications.

As for other instructions, SHA512, SM3, and SM4 are cryptographic technologies meant to accelerate appropriate algorithms, and given that there are always security concerns, these additions will also be welcome. It should be noted, though, that SM3 and SM4 are primarily used in China.

As far as Intel's Last Branch Record (LBR) feature is concerned, this is a debugging and performance tuning feature supported by some of its processors. LBR keeps a record of the processor's recently executed branches, including addresses of the branch and target instructions. This information helps developers understand program execution flow, identify performance bottlenecks, and analyze speculative execution side-channel attacks like Spectre and Meltdown.

Although mobile Arrow Lake CPUs may not support these instructions supported by desktop versions of these processors, it is likely that eventually, Intel's mobile processors will gain support for things like AVX-VNNI-INT16, SHA512, SM3, and SM4, after more software makers start using them.

Dynatron tends to be among the first makers of coolers to introduce cooling systems for upcoming datacenter platforms. In line with its traditions, on Wednesday the company quietly added its L38 all-in-one liquid cooling system for Intel's upcoming 6th Generation Xeon Scalable 'Granite Rapids' processors in LGA7529 packaging to its lineup, which did not go unnoticed.

Dynatron's L38 is a closed-loop liquid cooling system for Intel's LGA7529 CPUs aimed at 2U and larger servers. The device has a water block with a water pump that flows liquid at 1.7 liters a minute and a radiator equipped with three high-pressure 80-mm fans. These fans spin at up to 8000 revolutions per minute to produce an airflow of over 115 CFM while generating noise level of around 57 dBA. The cooling system is rated for up to 700W. 

Intel's upcoming 6th Generation Xeon Scalable 'Granite Rapids' processors are set to emerge this year and target heavy-duty servers that handle complex workloads. The CPUs will be based on dozens of high-performance Redwood Cove and will feature up to 12 DDR5 memory channels. The processors were rumored to have a processor base power of around 500W, but it looks like there will be SKUs that will consume even more power, which is why all-in-one liquid cooling solutions will be required for such CPUs.

Dynatron specifically positions its L38 for Granite Rapids SP CPUs, not for Sierra Forest processors that use the same LGA7529 packaging, but are based on up to 144 energy-efficient Crestmont cores. These CPUs aimed at cloud datacenters will also be quite power hungry, though their exact PBP are unknown. 

Since the L38 is listed, it is plausible to assume that Dynatron is sampling the units with its partners among server OEMs and ODMs, who might eventually use them for machines running Intel's Xeon Scalable 'Granite Rapids' processors.

Intel has started sampling of its codenamed Arrow Lake-S processors in LGA1851 form-factor and supporting motherboard among its customers. Arrow Lake CPUs could launch as early as the second half of 2024. A leak from @leaf_hobby, a prominent hardware leaker who tends to have access to confidential information alludes that the LGA1851 platform will continue its evolution till 2026. Take the news with a pinch of salt for now. 

Intel is seemingly distributing Arrow Lake-S ES1 and ES2 samples with six Lion Cove high-performance cores and eight Skymont energy-efficient cores, a configuration which resembles that of a mobile processor. Meanwhile, Core i9-grade Arrow Lake-S processors for desktops could feature eight high-performance cores and 16 energy-efficient cores, reports IT Home. Compute tiles of the upcoming processors are set to be made on Intel's 20A (2 nm-class).

We already know from unofficial information that Lion Cove high-performance cores of Intel's Arrow Lake-S processors are set to increase capacity of L2 cache to 3 MB. Meanwhile we have no idea about the destiny of the Adamantine L4 cache that was expected to show up in the Meteor Lake processor. There is a speculation that the forthcoming Arrow Lake-S processors might use Adamantine for GPU tile, but this is only a guess at this point since CPUs and GPUs work with caches differently and we do not know whether Adamantine can address both types of applications.

Intel's Arrow Lake-S processors are set to use LGA1851 platform that is set to support successor of Arrow Lake-S (which is presumably called Panther Lake-S). Arrow Lake-S's I/O tile is set to increase the number of supported PCIe Gen5 lanes to 16+4 and also support four PCIe Gen4 lanes. Furthermore, Intel's Z890 platform is set to support 24 PCIe Gen5 lanes.  

Meanwhile, the LGA1851 platform is expected to lose DDR4 compatibility (which is not surprising as we are dealing with 2nm-based CPUs and DDR4's 1.2V may be too high for such parts). 

Intel's Arrow Lake CPUs for desktops, which once were rumored to show up in the first half of 2024, are now expected to launch in the second half of the year. Meanwhile, it is speculated that the LGA1851 platform will be used till 2026, which suggests support for at least two generations of CPUs. Then again, we are dealing with unofficial information here and plans tend to change.

Intel and Synopsys this week extended their EDA and IP partnership to the company's Intel 3 and Intel 18A manufacturing technologies. In line with the agreement, Synopsys is set to develop its standardized interface IP for Intel's 3nm and 1.8nm-class production nodes, which will be beneficial for Intel Foundry Services (IFS) customers adopting these fabrication processes. Meanwhile, a standout aspect of this announcement is Intel's intention to extend its 3nm-class node to a wider array of external clients.

While chip designers tend to invest a lot into differentiating their IP, most of them tend to license IP-like interfaces and memory controllers. To that end, the availability of an industry-standard IP portfolio of interfaces from Synopsys is crucial for the success of new process technologies, such as the upcoming Intel 3 and Intel 18A, as it enables chip developers to streamline their work and shrink the time-to-market. Unfortunately, it is unclear when exactly Synopsys is set to be ready with its IP for Intel 3, even though that is set to be ready for manufacturing this year. Intel 18A has a bit more time, as it's set to be ready for production in 2H 2024.

The intriguing part is that Intel is now extending its IFS offerings to the Intel 3 fabrication process, which is a major refinement of its Intel 4 node and does not use any of the company's ambitious innovations like gate-all-around RibbonFET transistors or the backside power rail called PowerVia. Compared to its predecessor, Intel 3 promises a 18% higher performance per watt, a denser high-performance library, reduced via resistance, and increased intrinsic drive current, which is beneficial primarily for datacenter system-on-chips. Indeed, Intel has announced zero Intel 3-based client products so far, but three datacenter SoCs: Xeon-branded Granite Rapids and Sierra Forest processors, as well as a custom SoC for a major cloud datacenter provider.

The extension of the IP partnership with Synopsys will enable Intel to make its Intel 3 node — a fabrication technology that Intel barely advertised as an offering for IFS customers — more accessible to a wider range of interested parties. That also implies that there are potentially such interested parties.

As for the Intel 18A node, this is a superior version of the company's Intel 20A process technology that promises up to a 10% improvement in performance per watt, a refined RibbonFET architecture, and line width reduction, which implies a higher transistor density. It will be crucial for Intel 18A to have industry-standard interface IP readily available as soon as possible, as developing things like memory or PCIe controllers and PHY on a 1.8nm node is both expensive and time consuming.

Intel intends to increase the L2 capacity of its upcoming codenamed Arrow Lake processors to 3 MB per core, according to Golden Pig Upgrade (via @9550pro), a renowned leaker who tends to have accurate information about future Intel products. If the information is accurate, then Arrow Lake CPUs will offer higher performance in memory bandwidth-dependent applications.

Intel's 13th Generation Core 'Raptor Lake' processor features a 2 MB L2 cache per high-performance Raptor Cove core and 512 KB L2 cache per energy-efficient Greacemont core, thus has 32 MB of L2 cache in total as well as 36 MB of L3 cache in total (3 MB L3 cache per P core, 3 MB per four E cores).

Assuming that Intel's Arrow Lake processors will retain eight high-performance cores, its total L2 capacity for performance cores will increase to a sizeable 24 MB. Meanwhile, it is unclear whether Intel also plans to expand the size of the L3 cache of Arrow Lake's performance cores. Keeping in mind that Arrow Lake CPUs will be made on Intel's 20A (2nm-class) fabrication process, the company might increase the size of all caches as it may not have a significant impact on die size and cost. Yet, only Intel knows what makes sense to do to increase performance without significantly affecting costs. 

Increasing the L2 cache capacity for high-performance cores is done to boost performance. One of the primary benefits of increasing cache size is to improve the hit rate. If the working set of a given workload fits better within the enlarged L2 cache than it did before, this will reduce the need to access the slower L3 cache or main memory. This potentially leads to a reduction in average memory access time and potential energy savings, especially beneficial for workloads whose data sets can better fit within the enlarged L2 cache.

On the downside, a larger L2 cache can introduce slightly longer access latency. Keeping in mind that Intel's processors already have large L3 caches increasing L2 cache size gets diminishing returns on performance benefits. Additionally, a large L2 cache might consume more power, produce more heat, and increase die area. 

While Intel has revealed that its codenamed Lunar Lake processor due in 2024 will be based on a brand-new microarchitecture that will deliver unprecedented performance-per-watt efficiency, it never disclosed anything else about the CPU. Yet, the latest update of Intel's PerfMon software (discovered by @InstLatX64) fills some gaps. 

As it turns out, Intel's Lunar Lake will pack Lion Cove high-performance cores as well as Skymont energy-efficient cores. The software does not disclose core count or peculiarities of the Lion Cove and the Skymont microarchitectures, but it clearly reveals that the upcoming Lunar Lake processor will indeed use all-new microarchitectures and, at least based on Intel's claims, will deliver unprecedented performance efficiency.

Intel's Lunar Lake will inherit disaggregated multi-chiplet design from Meteor Lake and Arrow Lake client CPUs, but it is expected (based on the schematic images that Intel is publishing) bring it to a new level and split the things up a bit further. Also, Intel's Lunar Lake will use the company's 18A (1.8nm-class) fabrication process for its compute tile, which will enable Intel pack in more RibbonFET transistors and improve performance thanks to backside power delivery. 

For now, it is hard to estimate performance advantages enabled by the new Lion Cove and Skymont microarchitectures as well as Intel 18A process technology over Arrow Lake CPU, but Intel itself sets pretty high expectations for its 2024 CPU part.

Intel's 3nm-class process technology has met its defect density and performance targets, the company announced this week. The Intel 3 fabrication technology is on track to be used for high-volume manufacturing of Intel's upcoming codenamed Granite Rapids and Sierra Forest processors next year, according to Intel.

"Intel 3 met defect density and performance milestones in Q2, released PDK 1.1, and is on track for overall yield and performance targets," said Pat Gelsinger, chief executive of Intel, at the earnings call with analysts and investors. "We will launch Sierra Forest in the first half of 2024 with Granite Rapids following shortly thereafter, our lead vehicles for Intel 3."

Intel 3 (previously known as 5nm) is the company's 2nd-gen process technology that uses extreme ultraviolet lithography and is generally a refined Intel 4 production node (previously known as 7nm). Compared to Intel 4, Intel 3 promises an 18% higher performance per watt efficiency, denser high-performance library, reduced via resistance, and increased intrinsic drive current. 

Intel's 3nm-class node is particularly suitable for data center-grade products that tend to use large monolithic dies and consume a lot of power (so reduced via resistance is a huge benefit). So far, Intel has announced only two processors set to be made on its 3nm-class node — the server-class Granite Rapids and Sierra Forest. Furthermore, the company's Intel Foundry Services division is set to make a custom data center product for a hyperscaler on Intel 3 process technology. 

Intel 3 meeting defect density and performance goals is good news for Intel's data center division as it will enable it to offer competitive products in 2024.

Intel does not seem to be planning to use its 3nm-class process technology for client products; at least the company has not announced any so far. At present, the company is ramping up its codenamed Meteor Lake CPU for notebooks and desktops on the Intel 4 process and is gearing up for mass production of its codenamed Arrow Lake CPU on Intel 20A (20 Angstroms, 2nm-class) manufacturing technology in the coming quarters.

"On Intel 20A, our first node using both RibbonFET and PowerVia, Arrow Lake, a volume client product, is currently running its first stepping in the fab," said Gelsinger.

Renowned hardware leaker YuuKi_AnS has published the first photos of Intel's 6th Generation Xeon Scalable 'Granite Rapids-AP' processor, expected to hit the market in 2024 or 2025. The CPU uses Intel's LGA7529 packaging and will share a platform with the company's codenamed Sierra Forest processor.

Engineering samples of Intel's Xeon Scalable 'Granite Rapids' look different than contemporary Xeon Scalable CPUs, which is not particularly surprising as these processors are considerably larger than existing ones. Meanwhile, the fact that these CPUs are already in the wild is not particularly surprising, as the product is less than two years away, so server makers are already testing it. 

Intel's upcoming 6th Generation Xeon Scalable processors, code-named 'Granite Rapids,' are expected to offer an increased core count that will surpass that of Sapphire Rapids and Emerald Rapids CPUs. The new processors are projected to feature an advanced 12-channel DDR5 memory subsystem that will be able to use both conventional DDR5-6400 modules as well as higher-performance DDR5-8000 MCR DIMMs. This high-end memory subsystem, when fully populated, can deliver an impressive 614.4 GB/s – 768 GB/s bandwidth, which is a substantial enhancement from the 307.2 GB/s bandwidth of Sapphire Rapids processors.

Furthermore, Intel's next-generation data center processors will reportedly feature up to 96 PCIe Gen 5 lanes, with the CXL protocol on top to support upcoming accelerators/co-processors, storage devices, memory expanders, and other PCIe-enabled devices. The processors are also expected to support six sets of 24 UPI links, to enable efficient CPU-to-CPU communication.

Intel is gearing up a platform dubbed 'Avenue City RP' to support the new Granite Rapids and Sierra Forest processors. This motherboard will facilitate critical CPU features, along with PFR 4.0 root of trust, a novel RunBMC AST26000 module, and OCP 3.0 network cards.

Intel is on track to release its codenamed Meteor Lake-S processors for desktops in the coming quarters, but there's a catch. The company will only address entry-level and mainstream systems with these CPUs, whereas performance-demanding PCs will have to use Raptor Lake Refresh or Arrow Lake-S processors.

It looks as though Intel's Meteor Lake-S processors will only exist in Core i3 and Core i5 models rated for 35W and 65W, which is good enough for compact and standard entry-level and mid-range desktops. This information is based on an excerpt from a slide from an alleged Intel presentation published by @SquashBionic, a renowned hardware leaker with frequent access to confidential information.

Meteor Lake-S will share Intel's Socket V1 (for LGA1851 CPUs) and Intel's 800-series chipset platform with Intel's Arrow Lake-S processors. Meanwhile, motherboards aimed at Arrow Lake-S, which will exist in Core i7 and Core i9 variants for gamers and enthusiasts, will feature considerably more advanced voltage regulating modules to offer maximum performance. You can expect it will be priced accordingly.

Intel's Meteor Lake and Arrow Lake processors are set to be the company's initial processors for client applications that rely on disaggregated multi-tile designs. The compute tile for Meteor Lake will be produced on the Intel 4 node that extensively uses extreme ultraviolet (EUV) lithography, while Arrow Lake's compute tile will be made using the company's 2nm-class fabrication process called Intel 20A. Both CPUs will also feature a graphics tile produced by TSMC on its N3E manufacturing technology.

Intel's 20A node is unique as it will incorporate the company's RibbonFET gate-all-around transistors with PowerVia backside power delivery. The RibbonFET and PowerVia technologies promise to offer significant benefits for high-performance client and datacenter CPUs, which explains why Intel wants to use 20A sooner rather than later, given the intense competition against AMD. Meanwhile, it's unclear why Intel does not want to introduce an Intel 4-based part for higher-end desktops.

While it is somewhat surprising that Intel does not want to address performance demanding PCs with its first client processors featuring a multi-tile design, this isn't particularly unusual. Intel never offered its 5th Generation Core 'Broadwell-C' processors for the mass desktop market. In fact, the company only released two of such CPUs in socketed LGA1150 form-factor — Core i5-5675C and Core i7-5775C. Those were quickly superseded by the Skylake Core i7-6700K launch just a few months later.

As always with leaks of this nature, bear in mind that the information comes from an unofficial source and not directly from Intel. Plans are also subject to change, so what Intel intends to do now may not be the same what the company actually does in 2024, when Meteor Lake-S for desktops are set to enter the scene.

Intel's PerfMon software has gained support for yet-to-be announced processors, codenamed Grand Ridge and Sierra Forest, and revealed some additional details about these CPUs per Twitter user @InstLatX64. In addition, PerfMon got support for Intel's Granite Rapids processors, which is an indicator that development of the CPU is proceeding.

As it turns out, both 144-core Sierra Forest and Grand Ridge processors will feature Intel's next generation energy-efficient cores based on the Crestmont microarchitecture, which will further increase performance and feature set of Atom-class cores. The same technology will be used for the company's Meteor Lake processors, though these CPUs will be aimed at completely different market segment.

Intel's Sierra Forest is of course the company's first Xeon processor based on energy-efficient cores that will use up to 144 Crestmont cores and will be made on Intel 3 (3 nm-class) fabrication process. The system-on-chip will share LGA7529 form-factor with Granite Rapids processor featuring high-performance Redwood cores, but will target primarily cloud applications that need huge core counts and energy efficiency rather than single-threaded performance. 

When it comes to Grand Ridge CPUs, not everything is that simple. Judging by the codename, this one will succeed Snow Ridge, Intel's special-purpose Atom-branded SoC for communications market. The first details about Grand Ridge processor emerged three years ago and revealed that the chip will indeed serve specialized applications, which is why it will rich built-on networking and I/O capabilities as well as Intel's QuickAssist Technology (QAT) accelerator. 

One interesting thing about Grand Ridge is that it will support such instructions as AVX-NE-CONVERT (converts values from BF16 to FP32, from FP16 to FP32, and from single-precision floating-point to BF16) and AVX-VNNI-INT8 (which looks to be an INT8 variant of the AVX-VNNI instructions present in Golden Cove). Both instructions are designed to enhance deep learning capabilities of Intel CPUs and will make Crestmont-based products more competitive for edge applications. 

One thing to note about the Grand Ridge rumors from 2020 is that back then it was supposed to be made on Intel's 7nm (HLL+).  Now the company not only renamed its nodes, but accelerated their rollout. Therefore, it is likely that Grand Ridge will now be made on Intel 3 fabrication process. Whether or not this means that it will gain cores and/or features is something that remains to be seen.

You thought that Intel's LGA4677 socket for 4th Generation Xeon Scalable 'Sapphire Rapids' processors was massive? A detailed image of Intel's next-generation LGA7259 socket emerges (courtesy of Marvin Sevilla aka @SprayOnCopper) and demonstrates that this future socket is far larger than the current design. In fact, LGA7259 can probably challenge AMD's SP5 socket with 6,096 contacts.

Measuring 61 × 82mm without retention mechanism, Intel's LGA4677 for Xeon Scalable 'Sapphire Rapids' and 'Emerald Rapids' CPUs is already quite a massive socket. Yet, as the image published by Marvin Sevilla shows, it is considerably smaller than the company's upcoming LGA7259 socket for Intel's Granite Rapids and Sierra Forest CPUs that will pack more cores and will consume more power than Intel's previous offerings. 

The actual dimensions of Intel's LGA7259 are not publicly known (they are available to developers, of course), but based on what we know about the dimensions of Intel's current 4th Gen Xeon Scalable CPU, it looks like we are dealing with a socket that measures approximately 66 × 92.5mm including retention mechanism. Yet, AMD's 6,096-pin SP5 socket for EPYC 'Genoa' and 'Bergamo' processors has a footprint of 93.4mm × 120.3mm with retention mechanism so it dwarfs both Intel's LGA4677 and LGA7259. 

Intel's 4th Generation Xeon Scalable 'Sapphire Rapids' processors have a thermal design power of up to 350W, yet the peak power delivery limit for an LGA4677 socket is 764W, according to media reports. Intel's next generation CPUs in LGA7259 package are said to feature a TDP of around 500W, so their peak consumption will likely top 1 kW.  

If you expand the above tweet, you can see a picture of the gargantuan socket with a consumer processor added to scale. 

In addition to more power, Intel's LGA7259 socket will enable a 12-channel DDR5 and DDR5 MCR memory subsystem and some additional I/O, so far it seems that not all extra lanes are going to be used for power. 

What remains to be seen is how much Intel's LGA7259 socket will cost. Modern sockets with thousands of contacts with tiny pitches (Intel's LGA4677 features a grid spacing of 0.81389 × 0.9398mm) are hard to make and therefore expensive. Depending on where you buy, they cost between $101 and $124 per unit in 10,000-units quantities. Intel's LGA7259 is considerably larger and has more contacts, so it is reasonable to expect that this socket will be even more expensive than its predecessor.  

Socket costs only account for a tiny part of a server bill-of-materials, so the 7259-pin socket itself will hardly have a substantial influence on next-generation server prices. Yet, keeping in mind that CPU power consumption grows with the number of pins, server platform makers have to use not only more expensive sockets, but more advanced voltage regulating modules with more durable components, more capable cooling systems, and higher wattage power supplies, among other things. 

Intel's next-generation datacenter platform, supporting 'Granite Rapids' and 'Sierra Forest' processors will offer massive improvements in terms of memory bandwidth and input/output capabilities. That's according to a slide published by well-known hardware leaker YuuKi_AnS. But increased performance and throughput will come at a price: next-generation Xeon processors will have a thermal design power of up to 500W.

Intel's 6th Generation Xeon Scalable 'Granite Rapids' processors will increase high-performance core count compared to Sapphire Rapids and Emerald Rapids CPUs, whereas Intel's Xeon 'Sierra Forest' processors based on energy-efficient cores designed for high-density cloud datacenters will feature an even higher core count. These processors will use Intel's LGA7529 socket, and will have a TDP of up to 500W. So expect their peak power consumption under high loads to be significantly higher than previous-gen parts. 

To feed those cores, the new CPUs will need a very sophisticated memory subsystem, and indeed the new CPUs will feature 12 DDR5 memory channels supporting both conventional DDR5-6400 memory modules (one DIMM per channel) as well as DDR5-8000 MCR DIMMs. When all channels are fully used, such a memory subsystem will provide up to 614.4 GB/s – 768 GB/s of bandwidth, a significant increase from Sapphire Rapids's 307.2 GB/s. 

The new datacenter processors from Intel will also sport up to 96 PCIe Gen5 lanes, with the CXL protocol on top for high-performance accelerators/co-processors, storage devices, memory expanders, and other devices that use PCIe. Also, the CPUs will support 6x24 UPI links for CPU-to-CPU communications. 

One of the platforms that Intel is prepping for its Granite Rapids and Sierra Forest processors is called 'Avenue City RP.' The motherboard will support key capabilities of the CPUs, as well as PFR 4.0 root of trust, a new-generation RunBMC AST26000 module, and OCP 3.0 network cards.

The slides do look like Intel's slides and are dated 2023. But since they come from an unofficial source, their contents should of course be taken with a grain of salt regardless of the leaker's track record.

Intel has canceled its codenamed Meteor Lake-S processor for desktops and is set to pull in the introduction of Arrow Lake-S to the first half of 2024, according to a new rumor published by BenchLife. However, some market observers believe the rumor is incorrect, and Intel's Meteor Lake-S is on track to hit desktops in the first half of 2024.

Curious Desktop Roadmap

Intel has been discussing the advantage of its disaggregated Meteor Lake processor for mobile computers for a couple of years and is expected to launch notebook versions of these CPUs in 2023. But instead of releasing Meteor Lake-S processors along with its 800-series chipsets in 2H 2023 or 1H 2024, the company intends to introduce codenamed Arrow Lake-S CPUs compatible with the same platform controller hub (PCH) family (Intel Z890, W880, Q870, B860, and H810) in the first half of next year, BenchLife suggests. 

Since the information comes from an unofficial source, it should be taken with a grain of salt. However, there might be a rationale behind the rumor. Intel's desktop and workstation roadmap leaked late last year, indicating that the company plans to introduce Raptor Lake-S Refresh for client PCs in Q3 2023. The Meteor Lake-S platform was not set to be released in 2023.  

Intel's Meteor Lake and Arrow Lake processors are the company's first CPUs for client PCs that use disaggregated multi-tile designs. Intel's Meteor Lake's compute tile is set to be produced on Intel 4 node (previously known as Intel 7nm, the company's first technology to use extreme ultraviolet lithography). In contrast, Arrow Lake's compute tile is set to be made using the company's Intel 20A (2nm-class) fabrication process. In addition, the CPUs are expected to feature a graphics tile produced by TSMC on its N3E manufacturing technology. 

Meteor Lake-S and Arrow Lake-S processors are expected to use Intel's LGA1800 socket (also referred to as LGA1851 sometimes) and 800-series chipsets. In theory, Intel could substitute the former with the latter, but that may not be possible. While Intel's 20A node is set to be production ready in the first half of 2024, this does not mean that Intel will be prepared to support a high-volume 20A-based product launch in the first half of next year.  

This is perhaps why hardware spotter @SquashBionic does not believe Intel can pull in Arrow Lake to 1H 2024. Instead, the blogger implies that Meteor Lake-S is still on track for 1H 2024. 

So far, Intel has not disclosed anything about configurations of Meteor Lake's and Arrow Lake's compute tiles. However, BenchLife asserts that Arrow Lake-S processor's compute tile will comprise eight high-performance cores and 16 energy-efficiency cores, which aligns with the number of general-purpose cores Raptor Lake has. Meanwhile, 6P+16E Meteor Lake will never be released for desktop, BenchLife asserts. Meanwhile, Intel has never offered 6P+nE configurations for socketed desktops whatsoever. As for memory support, both Meteor Lake and Arrow Lake processors are expected to support DDR5-6400 memory, improving their performance considerably.

Rushing 20A-Based Product?

Producing 24-core silicon on Intel 4 and Intel 20A node should be more beneficial from a costs perspective than making a highly integrated monolithic 24-core Raptor Lake-S CPU on Intel 7 process technology (formerly called 10nm Enhanced SuperFin), assuming that yields are similar. Therefore, Intel should be very inclined to introduce both Meteor Lake processors sooner rather than later. 

However, rushing 20A-based Arrow Lake CPUs to the market may not be the best idea. Intel's 20A is a rather revolutionary node as it is set to introduce the company's RibbonFET gate-all-around transistors with PowerVia backside power delivery. Usually, the company begins to roll out new nodes with desktop parts, but it is not used to pull in CPUs made on a brand-new node to market by at least half a year. 

While it would be good to see Intel's Arrow Lake-S on the market ahead of schedule, there are way too many things that do not add up with the report. Therefore, consider the information about Arrow Lake-S in H1 2024 as a rumor that has a high probability of being false.

Pat Gelsinger, chief executive of Intel, this week addressed rumors that the CPU giant was delaying products made using the company's own Intel 3 and TSMC's N3 (both are 3nm-class) fabrication technologies. The CEO re-emphasized that all 3nm projects announced so far were set to be released in 2024. 

"The 3nm programs are on track, both that with TSMC as well as our internal Intel 3 programs Granite Rapids and Sierra Forest in particular," said Gelsinger at the company's Intel Capital Allocation Update conference call. "I am somewhat amazed by some of these rumor mill discussions that come out. You might notice there were similar ones on Intel 4 a few months ago, and also with some of our other TSMC programs, which were patently false at the time as well." 

So far, Intel has disclosed three products set to be made using 3nm class manufacturing technologies.

 Internally, the company is set to produce its datacenter-oriented Granite Rapids (based on high-performance cores) and Sierra Forest (based on energy-efficient cores) processors on its Intel 3 node (previously known as 5nm). This fabrication process is essentially a refined version of Intel 4, but with improved performance per watt, higher drive currents, decreased via resistance and denser high-performance libraries. All of these features are particularly beneficial for datacenter-class processors, though reduced via resistance should be good for mobile CPUs too. Meanwhile, so far Intel disclosed only two products set to be made on its 3nm-class node internally. 

With external 3nm projects, things are a little more complicated. Officially, Intel is set to use TSMC's N3 for a graphics tile of its client processors codenamed Meteor Lake and Arrow Lake due in 2023 and 2024, according to a slide that Intel has shown a number of times. In August, 2022, a market research firm said that Intel decided to postpone production of Meteor Lake's graphics tile on TSMC's N3 process. Back then, Intel did not comment on any 3nm-based projects specifically, but said that Meteor Lake was on track to be released in 2023.  

Now, the company says that its Arrow Lake product comprising of a compute tile produced on Intel's 20A (2nm-class) node and a graphics tile made on TSMC's N3E is on track for 2024. Keeping in mind that by the time Arrow Lake CPUs are set to hit the market TSMC will have rather vast experience with its 3nm-class process technologies, it is unlikely that Intel might decide to delay Arrow Lake because of issues with TSMC's N3/N3E itself. 

"So, no changes in the programs as have indicated," said Gelsinger. "Good solid execution on both the client, the  server, and AXG [accelerated graphics] side. We are gaining momentum with foundry customers as well. So, I feel good that we have turned the corner on many of the execution challenges. You know, these rumors, like many others, will be proven by our execution to be firmly false."

Intel on Wednesday said that its board of directors had reset its dividend policy to reduce quarterly dividend payments in a bid to maintain spending on new manufacturing capacity that is set to be deployed in the coming years, something that the company considers critically important. The decision is meant to ensure that the company will have enough financial flexibility amid dropping revenue and profits. 

Starting from June 1, 2023, Intel will pay $0.125 per share quarterly on the company's common stock, which means that the company will pay investors $2 billion instead of $6 billion this year. The company has reconsidered its dividend policy for the first time since 1992 amid major challenges that it faces in the short term and long-term future.  

Intel said on Wednesday that it would prioritize investment in strategic capital and alter the timing of near-term capacity expansion in response to lower demand for its products in the short term. Essentially, this means that Intel will prepare for future expansions (i.e., build fab shells) and delay procurement of certain wafer fab equipment if possible. 

"Prudent allocation of our owners’ capital is important to enable our IDM 2.0 strategy and sustain our momentum as we rebuild our execution engine," said Pat Gelsinger, CEO of Intel. "We remain on track to deliver five nodes in four years and continue to expand the IFS (Intel Foundry Services) customer base." 

In recent years Intel has lost its manufacturing technology leadership to TSMC due to overly aggressive goals with its 10nm fabrication process that led to major delays for high-volume manufacturing. These delays and management missteps led to delays of major products, which is why Intel lost some of its datacenter CPU performance leadership to AMD.  

After Pat Gelsinger became chief executive of Intel in 2021, he introduced the company’s IDM 2.0 strategy that is meant to bring back product and process technology leadership back to Intel. Under the new strategy, Intel plans to aggressively introduce new process technologies, expand its manufacturing capacity to offer foundry services to other companies, and outsource some of its production to contract chipmakers when and if it makes sense.  

But modern process technologies are expensive to develop, which is why Intel needs to produce more chips — including chips for others — to invest enough in new nodes. As a result, IDM 2.0 requires a lot of capital — tens of billions of dollars over the next few years — as Intel needs to ensure that it has enough capacity for its own products as well as for its foundry customers. To ensure that it has enough capital to build out required capacity, Intel introduced its Semiconductor Co-Investment Program (SCIP) — though so far the latter has generated only one major deal. 

Due to soft demand for PCs and lower margins of its datacenter division, Intel's revenue and profits suffered major declines in the recent quarters and are unlikely to rebound this year. Therefore, Intel needs to reduce all of its spendings, including dividend. Intel's abilities to invest declined and now the company is looking at around $20 billion CapEx in 2023. 

Intel's management re-emphasized today that the company was on track to 'launch' the next generations of its client and server processors in 2023 and 2024. 

"We are well into the ramp of 13th Gen Intel Core and 4th Gen Intel Xeon Scalable processors, and we look forward to the launch of Meteor Lake and Emerald Rapids in 2023 and Granite Rapids and Sierra Forest in 2024," said Gelsinger.

The first picture of Intel's LGA7529 socket for its upcoming codename 'Sierra Forest' processors powered by energy-efficient cores has been published by hardware leaker @YuuKi_AnS. The CPUs will use small Atom-class energy-efficient cores, and it will plug into a massive 7529-pin socket.

Intel's Xeon 'Sierra Forest' processor and the Birch Stream platform are designed for high-density cloud datacenters. These are for running workloads that benefit mostly from core count rather than from single-threaded performance. To that end, the core count of Sierra Forest system-on-chips will be significantly higher than regular Xeon processors based on high-performance cores, such as Emerald Rapids as well as Granite Rapids.

To feed those cores with data and power, Sierra Forest will use loads of pins, which explains the LGA7529 form-factor with a massive number of pins. Meanwhile, it does not look like Intel's LGA7529 socket is significantly bigger than the company's LGA4677 for Xeon Scalable 'Sapphire Rapids' processors and their successors, at least if we compare sizes of both sockets to the DDR5 memory slots located nearby. 

Unfortunately, the published image doesn't reveal many new details about Sierra Forest CPUs, such as the number of cores or memory channels. Still, if there are LGA7529 motherboards in the wild, it means server makers are likely (or will soon be) testing the future CPUs.

Intel's Xeon 'Sierra Forest' processor is set to be made on Intel 3 process technology and is set to become available in 2024.

Intel's major next-generation processor families are on schedule in accordance with the company's previously released roadmaps, says chief executive Pat Gelsinger. 

While Intel's disappointing Q4 FY2022 financial results were primarily a result of the weakening economy, datacenter product delays also plagued the company's bottom line. However, Gelsinger used the earnings call to reaffirm the company's roadmap and show that all the products are on track for release. On the client side, Intel's Meteor Lake is set to ramp in 2023, whereas Lunar Lake has completed its planned tape out. On the datacenter front, Emerald Rapids will start production this year, whereas its successor Granite Rapids is slated for 2024.

Client Side

Meteor Lake is an important milestone for Intel for two reasons: it is the company's first client CPU to rely on a disaggregated multi-tile design, and it is the first to use the Intel 4 process technology (aka 7nm), which is Intel's first node to use extreme ultraviolet (EUV) lithography. The system-in-package will consist of four tiles: the compute tile (CPU cores), the graphics tile produced by TSMC (presumably using its N3 or N5 node), the SoC tile, and the I/O tile. The tiles are interconnected using Intel's Foveros 3D technology. 

“On Intel 4, we are ready today for manufacturing and we look forward to the MTL (Meteor Lake) ramp in the second half of the year,” said Gelsinger.

For now, it is not completely clear whether Intel plans to release Meteor Lake into the desktop space, or leave it as a mobile-only product, something it did with Ice Lake and Tiger Lake a few years ago. Considering unofficial information about Raptor Lake-S Refresh for desktops, Meteor Lake may well remain a part for laptops and compact desktops, but Intel has yet to confirm this. Meanwhile, Intel will start production of Meteor Lake CPUs this year. 

Intel's next disaggregated (multi-chiplet) design is codenamed Lunar Lake. It is based on a brand new microarchitecture (as we suspected last year) which Intel hopes will regain the performance-per-watt crown. The CPU completed its tape out in late 2022, as planned, so it is on track for "production readiness in 2024."

“With MTL progressing well, it is now appropriate to look forward to Lunar Lake, which is on track for production readiness in 2024, having taped-out its first silicon,” said the head of Intel. “Lunar Lake is optimized for ultra-low power performance, which will enable more of our PC partners to create ultra-thin and light systems for mobile users.”

Datacenter Side

Intel's 4th Generation Xeon Scalable "Sapphire Rapids" for datacenters officially launched on January 10 and will be succeeded by Emerald Rapids processors. The CPU giant once said that Emerald Rapids was set to "compete" (i.e., hit the market) in 2023. However, Intel changed its tune late last year and said that the processor family will be mass-produced in 2023, with a release set for 2024. For now, there are no changes to Emerald Rapids plans. 

Meanwhile, Intel's next-generation Xeon processors based on high-performance Granite Rapids cores and the company's first Xeon CPU powered by energy-efficient Sierra Forest cores are on track for 2024. However, it appears that Gelsinger is referring to production in 2024 rather than when the processors will actually launch. 

“Emerald Rapids is sampling and has completed power-on with top OEM (original equipment manufacturer) and CSP customers, and it remains on track to launch in the second half of 2023,” said Gelsinger. “Granite Rapids, our next performance core addition to the Xeon portfolio is on track to launch in 2024, running multiple operating systems across many different configurations. Further, our first efficient-core product, Sierra Forrest, is also on on-track for 2024.”