The head of the SK Group, which owns SK hynix, said in a press briefing that memory semiconductor prices are “abnormally high,” and that the industry must take steps to increase supply and help lower prices. The Chosun Daily writes that SK Group Chairman Chey Tae-won delivered this statement during a press briefing at an industry forum, where he also noted that the group is looking at building a memory chip plant in the U.S. to increase production.

“Memory prices are currently at an abnormally high level. While AI companies can absorb increased costs through investments, PC and smartphone manufacturers have no choice but to pass rising semiconductor costs onto product prices,” Chey told the media. “Since most customers for these products are individuals, there are limits to how much prices can be raised. To prevent 'chipflation'—where rising chip prices drive up finished product costs—supply must be expanded.”

Aside from expanding supply and easing memory prices for consumer products, extremely high memory prices brought about by limited supply could negatively impact the big three companies. That’s because the high margins could lead to the entry of new players or give smaller manufacturers the opportunity to grow their presence and challenge the established firms. We’re already seeing this, as some Chinese brands have ditched them for domestically produced CXMT and YMTC chips. While this could be driven by Beijing, even major multinational brands like Corsair and Lenovo have started sourcing from these companies just to get chips. Even Apple is asking permission from Washington to buy memory chips from CXMT. Aside from that, he also cited Elon Musk’s interest in building his own fab as a potential threat to existing memory semiconductor companies.

This isn’t a problem at the moment as there is more than enough demand to go around for incumbent memory and storage chip manufacturers and new entrants. In fact, memory companies can use this as a defense against price-fixing lawsuits, with the massive AI demand and the higher margins it offers standing as a plausible reason why memory chip companies focused on HBM production and reduced DRAM output. But before the AI boom, the memory industry was actually suffering from one of the worst memory downturns to hit the industry for over a decade. So, if and when the memory shortage is over and the memory industry resumes its boom-and-bust cycle, more manufacturers jockeying to find customers in a tight market would make it that much harder for these companies to survive and thrive.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based in-memory computing (IMC) system-on-chip (SoC) for AI edge devices. The device is designed to accelerate neural network inference in lightweight AI models while consuming a fraction of the power that higher-end GPUs or NPUs would. To a large degree, the SoC is a proof-of-concept chip, as its performance would peak at around 2.54 TOPS in a theoretical best-case scenario, which is 16X below Microsoft's Copilot+ requirements.

A DWC-optimized IMC architecture

Memristor-based in-memory computing (IMC) accelerates neural networks by performing analog computations directly inside memory arrays, which reduces data movement and power consumption. However, depthwise convolution (DWC) — a core operation in lightweight networks such as MobileNet — performs independent per-channel filtering with limited data reuse and therefore maps poorly onto conventional crossbar arrays. To address this limitation, researchers from SK hynix, TetraMem, and USC developed an SoC that features both conventional IMC crossbars and a memristor-based IMC architecture specifically optimized for DWC.

The jointly developed SoC is based on an embedded RISC-V processor that schedules workloads and features 10 neural processing units (NPUs). One NPU out of 10 is dedicated to depthwise convolution, while the remaining nine execute pointwise and dense operations. Nine out of 10 NPU include a 256 × 256 memristor crossbar that performs the analog vector-matrix multiplication (VMM), 256 8-bit DACs that convert digital activations into analog voltages, 256 8-bit ADCs that convert the analog outputs back into digital values, and additional peripheral circuitry for reading, writing, programming, and controlling the crossbar.

The DWC-optimized NPU replaces its conventional array with eight specialized 252 × 28 zig-zag crossbar blocks, but retains DACs and ADCs. SK hynix developed and fabricated the memristor devices and integrated the resistive switching cells on top of the 65 nm CMOS circuitry using its back-end process.

That DWC-optimized NPU is the key feature of the whole SoC. To accelerate depthwise convolution, TetraMem replaced the straight selection lines used in conventional 1T1R crossbars with a zig-zag topology. As a result, the NPU contains eight 252 × 28 crossbar blocks whose diagonal selection lines activate 252 memory cells across 28 columns, which enables 28 independent 3 × 3 convolutions to run in parallel while using 100% of the array for weight storage. The remaining nine NPUs retain conventional 1T1R crossbars for 1×1 pointwise and dense layers and preserve the throughput and energy efficiency of traditional in-memory computing.

Great efficiency, low performance overall

To demonstrate the architecture, the researchers deployed a customized MobileNetV1Small neural network for the Visual Wake Words benchmark. The network contains approximately 36,000 parameters; all depthwise layers were mapped to the dedicated NPU, and pointwise layers were mapped to the remaining NPUs.

Because the memristor-based IMC hardware natively performs unsigned analog vector-matrix multiplication, inputs and weights are quantized to unsigned 8-bit values before execution. Since each memristor device can be programmed with only slightly more than 2 bits of effective precision, the design uses a two-subarray compensation technique that boosts effective weight precision to roughly 4 bits.

Conceptually, the approach is somewhat analogous to Nvidia's NVFP4 philosophy, in that both seek to achieve higher effective precision from low-precision hardware. However, the implementations are fundamentally different: NVFP4 relies on a digital floating-point representation and scaling factors, whereas the memristor SoC improves precision by compensating for analog programming errors using two programmed subarrays.

When it comes to accuracy, the SoC achieved an end-to-end inference accuracy of 80.36%, which matches the corresponding 4-bit software model. As for performance, the SoC delivers a peak throughput of 0.254 TOPS per NPU and reaches an energy efficiency of 21.3 TOPS/W at 100 MHz and 11.9 TOPS/W at 400 MHz. According to the authors, this compares favorably with published SRAM-based compute-in-memory accelerators despite being manufactured on an older 65 nm process. The SoC also exceeds Nvidia's A100 INT8 energy efficiency by an order of magnitude, the joint paper claims. Yet, these claims are largely unsubstantiated.

First up, the MobileNet demonstration does not even use all 10 NPUs. It uses one dedicated DWC NPU, five standard NPUs for pointwise layers, and leaves four standard NPUs idle. The demonstration thereby does not reveal total SoC throughput (TOPS), sustained throughput running a real network, and throughput with all 10 NPUs simultaneously saturated. In fact, the paper does not even reveal whether all 10 NPUs can be used at the same time. To that end, the 2.54 TOPS figure we mentioned earlier in the story is highly theoretical.

Validated approach

SK hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based IMC SoC featuring a novel depthwise convolution accelerator that improves crossbar utilization for lightweight AI workloads. The partners have managed to fabricate it using an outdated 65nm process technology and make it work, achieving a 21.3 TOPS/W energy efficiency and inference accuracy comparable to a 4-bit software model despite the fact that memristors can be programmed with a circa 2-bit accuracy. While the architecture validates that the approach works, the paper does not disclose the full performance of the SoC, and it is not clear whether the chip's 10 NPUs can be saturated at all.

SK hynix has completed the largest-ever foreign company IPO in U.S. history, raising $26.5 billion in its Nasdaq debut today, July 10. The South Korean memory giant sold 177.9 million American depositary receipts (ADRs) — a U.S.-listed stand-in for a foreign share — at $149 apiece, each representing a tenth of a Seoul-listed share. The offering was more than seven times oversubscribed and drew demand from more than 500 investment firms, according to Financial Times. Temporary Nasdaq trading is underway under the ticker SKHYV before regular-way trading begins as SKHY on Monday, July 13.

The offering was led by Bank of America, Citigroup, Goldman Sachs, and JPMorgan, with nine additional firms rounding out a 13-bank syndicate. Anchor demand came from heavyweight institutions including Baillie Gifford, Coatue Management, and Situational Awareness Partners, which together signaled interest in as much as $7 billion of stock, according to people familiar with the matter cited by Financial Times.

SK hynix is the world's leading maker of high-bandwidth memory (HBM), the vertically stacked DRAM that has become critical infrastructure for AI accelerators. The company has said it will steer the proceeds toward boosting its AI-memory manufacturing capacity. Confirmed build-outs include the first-phase fab at the massive Yongin semiconductor cluster, a new P&T7 advanced-packaging line in Cheongju, and EUV lithography equipment slated for delivery by the end of next year. Separately, SK hynix is constructing its first U.S. production site, a $4 billion advanced-packaging plant in West Lafayette, Indiana, targeted for completion around 2028. The facility is eligible for up to $458 million in CHIPS Act grants and up to $570 million in federal loans.

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SK hynix is seeing sensational growth thanks to the ongoing AI boom. The company is reportedly on track to post over 200 trillion won ($133 billion) in operating profit this year, a record-breaking figure that would see SK hynix employees earn around $400,000 each in bonuses. The company’s Seoul-listed stock is up roughly 220% year-to-date and has climbed more than sixfold over the past year.

In late June, SK hynix briefly surpassed Samsung as South Korea's most valuable company, closing at around 2,080 trillion won (about $1.35 trillion), a meteoric rise for a company that almost declared bankruptcy in 2001 and, more recently, recorded an annual operating loss of 7.73 trillion won in 2023. That rise doesn't seem like it will be slowing down any time soon. SK hynix has said its entire 2026 output of HBM, DRAM, and NAND is already sold out, with the crunch expected to extend into 2027.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

South Korean President Lee Jae-myung announced a ₩1,350 trillion (roughly $880 billion) 10-year public-private plan for semiconductors, AI data centers, and robotics on June 29. At the televised address in Seoul, he was flanked by Samsung Executive Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won.

The ₩1,350 trillion total combines a $520 billion semiconductor program with AI data center and robotics spending, most of it corporate capital expenditure rather than direct state funding. Samsung's Device Solutions division booked ₩53.7 trillion in first-quarter operating profit and expects 2026 to out-earn its entire prior semiconductor history. Samsung and SK hynix have pulled fab completion dates forward by as much as 12 years, while the transmission lines and water pipelines that those fabs depend on remain years behind.

Gigawatts of power deficit

The Yongin Semiconductor National Industrial Complex, the Samsung and SK hynix megacluster in Gyeonggi Province, is estimated to require 15 to 16 GW at full operation, close to 25% of total Seoul-metropolitan power demand, against local supply of about 1.9 GW, according to a National Assembly Research Service report. As of a January briefing, however, about 6 GW of the roughly 15 GW the complex needs had no finalized supply plan, with Samsung reportedly needing 9 GW (6 GW secured) and SK hynix 6 GW (3 GW secured).

Power in South Korea is generated on the coasts, from nuclear and liquefied natural gas (LNG) on the east coast and renewables in the southwestern Honam region, while the fabs sit inland, near Seoul. Closing that distance falls to state utility KEPCO, which is pursuing a ₩37 trillion, roughly 1,153-km 345 kV network to move east-coast and Honam power to Yongin, targeted for 2036. KEPCO's track record on long-distance lines is problematic, though; its losses from delays on the Bukdangjin-Sintangjeong line reached ₩1.17 trillion ($810 million), and that single project took 22 years to complete, with site selection alone running past a decade.

The east-coast link that's supposed to carry about 8 GW toward the capital region has its own history of local opposition, too. The Donghaean-Dongseoul high-voltage direct current line, a 280-km run from Uljin to Hanam requiring 436 towers, has faced repeated delays, and Hanam's 2024 rejection of a KEPCO substation expansion threatened the plan outright. Meanwhile, SK hynix pulled the completion of its fourth Yongin fab forward by 12 years, from 2045 to 2033, as announced in the recent $712.5 billion SK hynix commitment, meaning fabs are arriving faster than the power lines that feed them.

KEPCO and the government plan six LNG plants inside the Yongin complex, starting at about 3 GW and scaling toward 10 GW, to bridge the supply gap until the transmission network is finished. Both Samsung and SK hynix hold RE100 commitments to reach 100% renewable electricity by 2050, and the ruling Democratic Party's own carbon-neutrality committee has demanded the LNG plan be cancelled.

Water shortages

Aside from power, a large memory fab consumes upwards of 100,000 tons of water per day, and the Yongin national complex is projected to need around 800,000 tons per day once fully built. The plan to supply this runs in phases: roughly 200,000 tons per day from about 2031, drawn from Paldang Dam surplus and treated wastewater, followed by new intake facilities and pipelines to reach 600,000 tons per day by 2034. However, SK hynix's accelerated fourth fab is now due in 2033, a year before the integrated pipeline that's being built to serve it.

Local water disputes have already delayed the buildout, with objections from Yeoju City and Hanam City stalling pipeline permits, and one groundbreaking was cancelled outright. The friction is worse for the new southwestern cluster near Gwangju, where water may prove harder to secure than power, because the Yeongsan and Seomjin river basins hold only about half the water of the Han basin that supplies Yongin. Meanwhile, existing Seomjin and Juam dam supply contracts are already fully allocated, and the four planned southwestern fabs are estimated to need around 430,000 m³ per day of industrial water. Government projections put the Yeongsan basin at an annual shortfall of roughly 219 million m³ by 2030, before any of the fabs draw a single drop.

Financed by the memory boom

Samsung reported preliminary second-quarter 2026 operating profit of ₩89.4 trillion ($58.4 billion) on ₩171 trillion in revenue on July 7, a roughly 19-fold year-on-year jump and a record for any tech company. Its Device Solutions chip division booked ₩53.7 trillion of the company's ₩57.2 trillion first-quarter operating profit, and DS president Kim Yong-kwan told a July 3 town hall that 2026 chip profit will exceed the cumulative total the division has earned across roughly 40 years in the business. SK hynix, meanwhile, posted a record ₩47.21 trillion operating profit for 2025, overtook Samsung as South Korea's most valuable listed company in June, and filed to raise about $29 billion in a Nasdaq listing whose proceeds are earmarked for Yongin, Cheongju packaging, and EUV tools.

Those numbers rest on contract prices that have run sharply higher through 2026, with commodity DRAM up around 90% in the first quarter and 50% to 60% in the second, as memory makers tilted wafer capacity toward HBM. The same dynamic underpins the government's confidence and its exposure. Bank of America has argued that fears of a memory-cycle peak are premature, noting the industrial cluster won't produce meaningful output until 2033 at the earliest. Morgan Stanley cautioned — also on July 7 — that the memory industry is nearing a peak in its rate of change, while stressing that this doesn't indicate a downturn. A plan financed by a price surge inherits the risk that the surge doesn't last until the fabs it funds come online.

The plan is ultimately the flagship of a president who took office nine months ago, in a country that removed and jailed his predecessor. Yoon Suk Yeol declared martial law in December 2024, was impeached within days, and was removed by the Constitutional Court the following April. A snap election last June brought Lee Jae-myung to office, and in February this year, Yoon was sentenced to life in prison for insurrection. Industrial policy has held across the turnover, with the Semiconductor Special Act passing the National Assembly with bipartisan support in May, but its dedicated ₩2 trillion account doesn't begin operating until 2027.

South Korea caps the workweek at 52 hours, and a proposed exemption for chip R&D staff was cut from the Semiconductor Special Act before passage. Industry and the conservative opposition backed the carve-out, citing TSMC's three-shift operations and longer hours at Chinese competitors, while the ruling party and a coalition of labor organizations opposed it as corporate favoritism.

A stopgap now lets firms run R&D staff up to 64 hours per week for limited periods with labor-ministry approval. Samsung's foundry holds about 7% of the contract chipmaking market against TSMC's 72%, and SK hynix supplies most of the HBM feeding Nvidia's AI accelerators, so the plan directs its capital toward memory and leaves Korea's weaker logic position largely untouched. Lee's single five-year term ends in 2030, three years before the plan's fabs are due to reach meaningful output.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

South Korean President Lee Jae Myung on Monday, June 29, announced an 800 trillion won ($520 billion) public-private investment plan alongside Samsung Electronics and SK Hynix to expand the country's chipmaking capacity, a move the government framed as essential to keeping South Korea competitive in the global artificial intelligence race. Lee unveiled the plan in a televised state address at his office in Seoul, flanked by Samsung Electronics Chairman Lee Jae-yong and SK Group Chairman Chey Tae-won, the leaders of the world's two largest memory chipmakers.

"Right now is truly a decisive moment, as the landscape of the global economy is being reshaped," Lee said in televised remarks. "Major countries, including the U.S. and China, are engaged in all-out competition with massive stakes." He added that only through cooperation between the private and public sectors could South Korea hope to triumph. Industry Minister Kim Jung-kwan said the plan would let the country rapidly expand production by sharply shortening the timeline from licensing to construction.

The centerpiece of the partnership is the construction of four production facilities, with Samsung and SK Hynix each building two. According to the government, the new plants will be built in the southwestern part of the country, near the city of Gwangju, a mostly rural area far from the existing semiconductor base south of Seoul, where both companies operate major clusters. Samsung will also build packaging facilities for high-bandwidth memory (HBM) chips in Chungcheong as demand for the advanced components soars.

"HBM, which is indispensable for the training and inference of AI models, requires cutting-edge technology for stacking semiconductor chips," the Samsung chairman said. "We will focus our investment on HBM fabs, which require main-fab-level processes, alongside existing semiconductor back-end fabs in the Chungcheong region, including Cheonan and Onyang."

One detail the government did not provide was the split between public and private money, as the project is a combined public-private commitment rather than a government spending program. While it is not immediately clear how much of the 800 trillion won would come from the state versus the two chipmakers, the disclosed line items are comparatively modest.

Industry Minister Kim Jung-kwan said the government and industry would jointly invest more than 30 trillion won over 15 years across the semiconductor value chain, while President Lee said Gwangju and South Jeolla province would contribute a further 5 trillion to 20 trillion won. Kim put another 81 trillion won toward the Chungcheong packaging hub, though he did not say how much of that is public.

The balance of the headline number is widely expected to be company capital expenditure, with the state's role concentrated in subsidies, faster permitting, and infrastructure. Kim said the government would streamline approvals and bring fab construction forward by up to 12 years, from the mid-2040s to the mid-2030s.

The plan also absorbs and accelerates projects already underway. The government said it would help Samsung and SK Hynix speed up construction of their existing capital-region clusters, with SK Group pulling forward the ramp of its Yongin memory site from 2045 to 2033, part of a stated goal to double the country's memory output within five years. SK Hynix supplies the bulk of the HBM that Nvidia depends on for its AI accelerators, the very strain this expansion is meant to relieve. While semiconductors are the focus of the investment, with the priority being a decisive lead in memory chips, the companies will also work on AI robots, physical AI, and AI data centers.

The investment partnership appears to be the latest piece of a broader strategy. SK Hynix had already committed $15 billion to new semiconductor facilities in February, a figure that now reads as an early piece of the larger national framework. Earlier iterations of the country's cluster plan had pegged long-term investment at around $471 billion, stretching to 2047, so the new figure represents a substantial expansion as AI demand projections have climbed. The fabs are targeted for completion in the mid-2030s.

The announcement caps an extraordinary stretch for both firms. SK Hynix overtook Samsung in June to become South Korea's most valuable listed company for the first time in more than 25 years, lifted by its commanding lead in HBM, while Samsung's chip division alone booked 53.7 trillion won in first-quarter operating profit as AI-driven memory shortages are expected to strain the companies' capacity past 2027.

The scale of the investments also invites inevitable comparison. At roughly $520 billion, South Korea’s plan dwarfs the United States' CHIPS Act, which provided about $52 billion in direct subsidies, by a factor of ten. Although the comparison is imperfect, since the U.S. figure is a government subsidy while the Korean number appears to be mostly private investment that the state is coordinating.

The strategic logic is the same on both sides of the Pacific: secure domestic capacity for the chips that underpin AI, at a moment when the U.S., China, Japan and the EU are all pursuing their own semiconductor industrial strategies. For Seoul, the specific prize is memory, the segment where its two companies already hold a commanding global position, with the goal being to extend that lead rather than merely defend it.

Samsung, SK hynix, and Micron were sued on June 25th in the U.S. District Court for the Northern District of California, where 17 plaintiffs accuse the three memory makers of illegally coordinating to restrict DRAM supply and inflate prices that the complaint says have risen roughly 700% over four years. The class action, filed as Garciaguirre v. Samsung Electronics and assigned to Judge Noel Wise, invokes Section 1 of the Sherman Act and targets companies that together hold around 90% of the global DRAM market. Samsung and SK hynix have pleaded guilty to criminal DRAM price fixing once before, with the latter paying a $185 million fine in April 2005.

The complaint argues that the three companies used a coordinated shift toward high-bandwidth memory (HBM), the stacked DRAM that feeds AI accelerators, as a cover to curtail production of older DDR3 and DDR4 modules. That contraction in commodity DRAM, the plaintiffs argue, pushed prices to record highs while no rival could step in: building a new DRAM fab costs tens of billions and takes years, leaving the incumbents free to cut output without fear of being undercut.

The named plaintiffs include 14 individuals and three small PC businesses, among them Troy's Computers and Florida repair outfit My Florida PC, and they cite Apple's recent iPad and Mac price increases as evidence of the squeeze. They’re seeking class status, an injunction, and treble damages as a result.

However, this case revisits a precedent that was already established in the same courthouse. A 2018 class action brought by law firm Hagens Berman made similar claims about parallel production cuts, and the district court dismissed it in 2020. The Ninth Circuit upheld that dismissal in 2022, ruling the trio's conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by an illegal agreement.

It was held at the time that the plaintiffs’ eight “plus factors” didn’t clear Section 1’s threshold, which demands evidence of an actual agreement rather than the conscious parallelism common in a three-supplier market. The new complaint leans on the pivot to HBM as the additional evidence that this earlier lawsuit lacked.

The three memory makers have publicly stated they’re operating independently while redirecting capacity to HBM, and senior executives have warned the shortage could run for years. Investment bank Jefferies expects DRAM prices to rise another 40% to 50% in the third quarter and a further 30% to 40% in the fourth, with no meaningful relief before 2028. The allegations remain unproven, and the defendants have not yet responded in court.

Solidigm is arguably one of the most mysterious storage companies in the industry today. The company is a wholly owned subsidiary of SK hynix, yet unlike its parent company, which produces charge-trap flash memory, it uses floating-gate 3D NAND memory that it develops and manufactures internally at a dedicated fab in Dalian, China.

Solidigm originates from Intel's Non-Volatile Memory Solutions Group (NSG), the company's NAND and SSD business unit, which used to have a unique technology strategy that differed from that of other flash and drive producers. To that end, it is not surprising that Solidigm also has a unique positioning as it only offers data center drives, most of which are based on floating-gate memory and proprietary in-house designed controllers. Furthermore, Solidigm is a fully vertically integrated company.

At Computex 2026, we sat down with Avi Shetty, who is vice president of AI ecosystem, Solutions & Market Enablement at Solidigm. Before his current position at Solidigm, he spent 14.5 years at Intel's storage division, so he has deep knowledge both about technology and the market. During our conversation, we discussed how Solidigm keeps evolving, including floating-gate NAND memory, advanced packaging technologies, next-generation SSDs, liquid-cooled SSDs, and more.

Anton Shilov: Could you introduce yourself to our readers and describe what do you do at Solidigm?

Avi Shetty: My name is Avi Shetty. I work at Solidigm, where I help lead AI solutions and ecosystem initiatives. My team works with global platform providers, software ISVs, and ODMs to ensure Solidigm solutions are validated, benchmarked, and included in reference designs at both the device and cluster levels, enabling customers to fully utilize our products.

A part of SK hynix that acts independently

Anton Shilov: You were previously a part of Intel. How is the integration going? Are you now fully integrated part of SK hynix, or do you operate independently?

Avi Shetty: Let me provide some background. While Solidigm was established in December 2021, our history goes back decades. Many of us came from Intel's Non-Volatile Memory Solutions Group (NSG), which developed Intel’s NAND SSDs for both client and data center markets.

In 2021, SK hynix acquired Intel’s NAND and SSD business and established Solidigm. Since December 2021, we have operated as a wholly owned U.S. subsidiary of SK hynix, headquartered in Rancho Cordova, California.

Anton Shilov: So, you are part of SK hynix, but still maintain a degree of independence?

Avi Shetty: Absolutely. We operate as an independent subsidiary of SK hynix. Our strategy is focused entirely on enterprise SSDs. Every bit of [floating gate] NAND [at our fab in Dalian, China] we produce goes into enterprise storage solutions.

This is one of the ways we differentiate ourselves from competitors such as Samsung and Micron, which also serve mobile and client markets. We made a deliberate decision to focus exclusively on enterprise storage and AI.

We are also fully vertically integrated. We manufacture our own NAND, develop our own controllers, write our own firmware, and design our own SSDs. While we work with manufacturing partners to build products, we control the entire technology stack.

I also believe we are the only company with access to two different NAND architectures. Through SK hynix we have access to charge trap flash (CTF) technology, and we continue to develop floating gate NAND technology for our high-density QLC SSD products.

Anton Shilov: What is Solidigm's current share of the enterprise SSD market?

Avi Shetty: Approximately 24%. That is enterprise SSDs only. We do not participate in any other NAND markets. As of the first quarter of 2025, plus or minus a few percentage points, our measured enterprise SSD market share is approximately 24%. We evaluate market-share data quarterly and semiannually, and that is the latest figure we’ve publicly discussed.

Anton Shilov: How much of your business today is concentrated in high-capacity SSDs versus higher-performance products?

Avi Shetty: High-density SSDs now represent a significant portion of our business. Because Solidigm is privately held, we do not publicly disclose that breakdown. We report our financial metrics through our parent company, SK hynix.

What I can tell you is that both our 61TB-class and 122TB-class products became customer favorites almost immediately after launch. Demand for high-density storage has been extremely strong.

Anton Shilov: I assume you also work directly with hyperscalers?

Avi Shetty: We work with a broad range of customers globally. That includes U.S. cloud service providers, Chinese cloud service providers, OEMs around the world, NeoCloud providers, software ISVs, and channel partners. We maintain customer support, engineering, and sales organizations globally. Our business spans the Americas, EMEA, China, and the rest of Asia-Pacific.

Anton Shilov: Which customer segment represents the largest opportunity for growth right now? Traditional cloud providers or something else?

Avi Shetty: We intentionally maintain a diversified customer base.

What is interesting is how quickly new segments emerge. For example, the NeoCloud market has existed for some time, but AI-focused infrastructure providers such as CoreWeave, Lambda, Crusoe, and Nebius have become much more important over the last two years.

Before the AI boom, these companies represented only a small portion of demand. Today, they are becoming a meaningful part of the market.

As AI infrastructure continues to expand, Solidigm is adapting both its customer strategy and product portfolio to support these emerging deployments while continuing to serve our traditional customers.

Floating gate NAND in 2026

CTF NAND used by major memory makers has approached 276 - 286 active layers, whereas Solidigm's floating gate flash is still at 192 layers, meaning that the company is somewhat behind some of its rivals in terms of active layers as of mid-2026. It is set to catch up with its next generation that will have over 200 layers, but only in the second half of this year. However, floating gate NAND memory still has a number of advantages over CTF, particularly for applications that Solidigm targets.

Floating gate uses a conductive polysilicon island to store charge, which provides excellent cell isolation — charge stays well-contained and is less likely to spread to or interfere with neighboring cells — and this is particularly important for 3D QLC NAND with very high layer counts. In addition, Solidigm claims that floating gate gives a strong voltage threshold window and better cell isolation, which enables the company to keep scaling QLC more while maintaining good reliability.

Anton Shilov: Are you still producing floating gate NAND, and do you intend to continue?

Avi Shetty: Absolutely. We introduced our first QLC foating gate NAND product in 2018, and today we are on our fourth generation of QLC NAND.

Our flagship high-capacity product currently ships with 192-layer floating gate NAND technology and powers our 122TB SSD.

Anton Shilov: Haven't you also announced a larger drive?

Avi Shetty: We have announced a higher-capacity product and expect it to become available later this year.

Anton Shilov: The 256TB-class drive?

Avi Shetty: Correct. Approximately 245TB usable capacity.

Anton Shilov: So you are going to have a roughly 245TB SSD available this year?

Avi Shetty: Correct.

Anton Shilov: What advantages does Floating-Gate NAND provide?

Avi Shetty: Floating gate NAND gives us scalability. We have consistently been first in the industry to push storage density in standard form factors. We were the first to introduce a 30TB SSD, then a 60TB SSD, and later a 122TB SSD.

We have been shipping the 122TB drive for nearly five quarters. We launched it in the fourth quarter of 2024, and it has since become our flagship product. It is probably our most popular product of 2025.

The reason customers like the 122TB drive is efficiency. When you look at AI data centers, customers want low power consumption, scalability, and performance. While this particular product is a PCIe Gen4 solution, our roadmap continues to increase both density and bandwidth. You will see future products based on PCIe Gen5 and PCIe Gen6.

The real attraction of the 122TB SSD is scale. In a 1U server, you can install 24 of these drives and get nearly 3PB of storage in a single rack unit.

If you look at the AI data pipeline — from training to archiving — the first and last stages require massive datasets. That is where these high-capacity SSDs are being deployed today.

Now we are also seeing growing demand from inference deployments. Inference can run in core data centers or in edge and back-office environments. Those deployments require storage that can efficiently feed GPUs and support workloads such as context storage and KV cache management. High-density SSDs help provide the capacity required for those applications.

Next-generation SSDs: PCIe Gen6 drives with liquid cooling

Anton Shilov: You mentioned PCIe Gen5 and Gen6 [next-generation drives]. I assume you are referring both to next PCIe generations and future NAND generations?

Avi Shetty: Both.

We maintain separate technology and product roadmaps. Earlier, I mentioned that our current QLC NAND is our 4^th Generation technology based on 192 layers. We will continue investing in future NAND generations as well.

On the product side, we are talking about PCIe generations. We currently ship both PCIe Gen4 and PCIe Gen5 SSDs. All of our TLC products are PCIe Gen5 today, while our QLC lineup currently remains PCIe Gen4.

Future QLC products will move to PCIe Gen5, and eventually, we will introduce PCIe Gen6 SSDs as platform vendors such as AMD, Intel, and Nvidia adopt PCIe Gen6 in their systems.

Anton Shilov: You mentioned PCIe Gen6 SSDs. You have not shipped one yet, correct?

Avi Shetty: Correct. PCIe Gen6 products are part of our future roadmap.

Anton Shilov: How close are they?

Avi Shetty: We are not making product announcements at Computex, but you will hear more from us soon.

Anton Shilov: At the moment there is really only one platform that can take advantage of them anyway. Well, two, if you consider Nvidia Vera.

Avi Shetty: That is part of the equation. When we evaluate our roadmap, we consider demand, platform readiness, and overall value to customers.

For example, we have what we call a refresh philosophy. We may introduce a PCIe Gen4 refresh or a PCIe Gen5 refresh that lowers cost or improves efficiency rather than immediately moving to a new PCIe generation.

The question is whether customers gain more value from Gen6 today or from a more mature, lower-cost Gen5 product. Those are the kinds of decisions our planning teams evaluate.

What I can say is that Solidigm maintains a full roadmap covering PCIe Gen4, Gen5, and future Gen6 SSDs across all major form factors, including U.2, E1.S, E3.S, and other EDSFF variants. Our portfolio spans capacities from 2TB all the way to 122TB.

Anton Shilov: Launching an all-new product early still gives you time to validate products with platform vendors.

Avi Shetty: Absolutely. We already work closely with platform providers to validate prototypes long before products are launched. Our engineering teams participate in interoperability events and PCI-SIG workshops to ensure products are ready when platforms become available.

Anton Shilov: That is actually interesting because PCIe Gen6 interoperability workshops have been delayed multiple times. Back in 2024, people expected the ecosystem to move much faster and interoperability workshops to start in 2024, with the list of compatible products emerging in 2025.

Avi Shetty: That is true. A lot depends on platform readiness and ecosystem scaling. PCIe Gen6 by itself is not enough. This is my personal opinion, but to fully benefit from Gen6 storage performance, the industry must also address cooling. That is one reason we invested heavily in liquid-cooled storage.

Last year, we introduced what we believe was the world's first liquid-cooled storage solution for Nvidia environments. It used E1.S PCIe Gen5 SSDs with direct liquid cooling. Historically, liquid cooling was focused on CPUs and GPUs. We extended it to storage by allowing coolant to flow through a cold plate attached to the SSD. The cold plate removes heat directly from the drive. To fully exploit PCIe Gen6 performance, the ecosystem must develop those kinds of technologies as well.

Anton Shilov: So you believe PCIe Gen6 SSDs will require liquid cooling?

Avi Shetty: At least in high-performance AI environments, particularly Nvidia-based deployments, we believe liquid cooling will be necessary.

Next-generation SSDs: PLC NAND

Anton Shilov: Will future NAND generations include both TLC and QLC? And what about PLC?

Avi Shetty: Never say never. We demonstrated PLC technology using floating gate NAND at the Flash Memory Summit several years ago. However, this business requires factory optimization and maintaining a manageable number of SKUs to maximize utilization and profitability.

That said, there absolutely will be opportunities for PLC. We have not announced any specific products or timelines, but there is active PLC development underway inside Solidigm.

Anton Shilov: That is interesting. However, PLC by itself only increases capacity by about 20% compared to QLC and at the same time requires significantly more sophisticated controllers and error correction.

Avi Shetty: That is true. However, those same concerns existed during every previous transition: from SLC to MLC, MLC to TLC, and TLC to QLC.

We were the first company to commercialize QLC NAND. Initially, many competitors questioned its value. Today, the industry increasingly recognizes the total-cost-of-ownership advantages that QLC provides, and multiple vendors now offer QLC products. I think the same process will occur with PLC.

It is also important to consider the broader market. Roughly 80% of storage capacity worldwide is still deployed on hard drives. PLC does not necessarily need to replace QLC on a one-to-one basis. Instead, it can create new opportunities where the advantages of solid-state storage — lower power consumption, higher density, smaller physical footprint, and lower total cost of ownership — become compelling.

You will likely see future solution development involving software partners that help address some of the limitations you are describing.

Anton Shilov: Do you expect retention characteristics to become a major challenge with PLC NAND?

Avi Shetty: Of course. PLC is a new technology, and retention characteristics will differ from what we see with QLC today.

The same is true across all NAND types. SLC, MLC, TLC, QLC, and eventually PLC all have different retention characteristics based on the underlying technology. The existence of those challenges does not mean we stop exploring future solutions. We will continue investing in that area.

Advanced packaging for NAND

Anton Shilov: As I mentioned, PLC only increases capacity by about 20%. Advanced packaging may ultimately have a much larger impact on SSD capacity. Could you discuss where packaging technology stands today and where it is headed?

Avi Shetty: Absolutely. Let me use our current products as an example. The 122TB SSD represents a significant packaging achievement. It is a U.2 drive with 48 NAND packages. Each package contains a 22-die stack. Each die is a 1.33Tb QLC device. Those 22-die stacks are what enable us to reach 122TB in a standard form factor.

Packaging technology remains one of our core investments. We continue developing technologies that allow us to place more dies into each package and deliver higher capacities to customers.

Anton Shilov: What about increasing the number of dies per package?

Avi Shetty: That is one of the primary ways to increase density. You can either increase die capacity or increase the number of dies per package. We intend to pursue both approaches.

Anton Shilov: How many dies per package do you think remain practical?

Avi Shetty: Today we are at 22. Future products will go beyond that, although I cannot discuss specific numbers.

Anton Shilov: What did previous generations use?

Avi Shetty: Depending on capacity requirements, previous products used 4-, 8-, or 16-die stacks. Of course, we are talking about a single NAND package in each case.

Storage-Class Memory, Optane, and Nvidia's Storage Next

Anton Shilov: What about storage-class memory?

Avi Shetty: Like Optane?

Anton Shilov: Not necessarily Optane itself, but something similar — something faster than NAND flash, yet capable of offering significantly higher density than DRAM at a lower cost.

Avi Shetty: Understood. Let me frame it from the perspective of the problem we are trying to solve. If you are asking whether Solidigm is developing a storage-class memory technology similar to Optane, then the answer today is no.

What we are focused on is addressing the requirements emerging from Nvidia's Storage Next initiative. The fundamental challenge is bandwidth. HBM is extremely fast, but it is also expensive and difficult to scale economically. As AI systems continue to grow, the industry needs additional memory and storage tiers that provide greater capacity at lower cost. That creates demand for NAND-based solutions that remain non-volatile while delivering improved latency and bandwidth characteristics.

We have not made any public announcements regarding storage-class memory technologies, but we continuously evaluate future technologies and architectural approaches.

Anton Shilov: So you are exploring concepts that could potentially bridge the gap between traditional NAND and memory?

Avi Shetty: We are evaluating a wide range of technologies that could help us continue delivering leadership products to our customers. When and if we have something to announce, we will do so publicly. At this point, however, we have nothing to disclose.

Anton Shilov: So storage-class memory is not currently a product category that Solidigm is actively pursuing?

Avi Shetty: If you are specifically referring to something similar to Optane, then no.

Optane was based on a fundamentally different technology. It was not NAND. It relied on a phase-change-memory-derived architecture and represented a completely different storage medium. We are not pursuing that type of technology today. What we are investing in is future NAND technology.

Anton Shilov: You think that future NAND technologies could eventually move closer to that space?

Avi Shetty: Exactly. Future NAND innovations could help narrow the gap between HBM, DRAM, and the next storage tier. That’s certainly one of the directions the industry is evaluating as AI systems continue to demand larger memory pools and greater bandwidth.

SK hynix filed a securities registration statement with South Korea's Financial Supervisory Service and the U.S. SEC on Wednesday to raise up to 45.45 trillion won ($29.43 billion) through an American depositary receipt listing on the Nasdaq Global Select Market scheduled for July 10th — and the company said the whole lot would go toward investments in factories and equipment.

The offering covers 17.79 million newly issued common shares and would rank among the largest ADR sales ever completed. SK hynix earmarked the proceeds for its first fab in the Yongin cluster, an advanced packaging plant in Cheongju, and chipmaking equipment that includes EUV scanners.

None of the funded projects will produce memory in time to ease the shortage that’s still driving up prices. SK hynix holds about 57% of the HBM market and 32% of global DRAM, and chairman Chey Tae-won has said repeatedly that AI demand will keep supply tight until 2030.

The filing names three target projects that SK has already committed to and is now financing via public markets. The first fab in the Yongin Semiconductor Cluster, designated Y1, carries a 31 trillion won ($21.5 billion) commitment for its initial phase and is due for completion around February 2027, with equipment installation to follow in the second quarter. The Cheongju P&T7 advanced packaging plant, a 19 trillion won ($12.9 billion) site dedicated to HBM assembly and testing, broke ground in April and should be completed at the end of 2027. EUV lithography is needed in both, and SK hynix placed a record $7.9 billion order with ASML in March covering roughly 30 scanners through 2027.

10 ADRs will represent one common share, with the final per-ADR price to be set through bookbuilding shortly before the July 10th debut, and SK hynix said the total raise could change from the 45.45 trillion won ceiling. BofA Securities, Citigroup, Goldman Sachs, and JP Morgan are managing the sale, and the regulatory review is expected to conclude by July 3rd, with the new shares registering on the Korea Exchange on July 29th.

Both the Yongin fab and the Cheongju packaging plant reach volume output in 2027, near the back end of that window. The company confirmed the ADR plan in early June alongside a pledge to double wafer capacity within five years, a timeline Chey acknowledged would do little to shorten the squeeze. DRAM contract prices have run higher through 2026 as the three memory makers tilt wafer capacity toward HBM, which consumes around three times the silicon per gigabyte of standard DDR5.

Just two days ago, SK hynix passed Samsung Electronics to become South Korea's most valuable listed company, ending a 26-year run at the top. Its Korea-listed shares rose 5.5% in after-hours trading following the disclosure.

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SK hynix overtook Samsung Electronics on Monday to become South Korea's most valuable listed company, the first time Samsung has surrendered the top spot on the KOSPI index since November 2000, according to Reuters. SK hynix shares closed up 5.6% to lift its market capitalization to 2,080.4 trillion won ($1.35 trillion), edging past Samsung's 2,066.7 trillion won excluding preferred shares, after a rally of more than 340% this year built almost entirely on demand for the high-bandwidth memory it supplies to Nvidia and other AI chip buyers. The company held 61% of the global HBM market in 2025, against 17% for Samsung and 21% for Micron.

SK hynix is one of the few pure-play memory makers, while Samsung spans smartphones, displays, contract chipmaking, and home appliances, among many other markets. Investors value the focus on pure-play memory higher because HBM carries the industry's fattest margins and ties suppliers to specific AI accelerators, unlike commodity DRAM that buyers can swap between vendors.

SK hynix built its lead by continuing to invest in HBM through the 2023 downturn, when a memory price collapse pushed it to a 7.73 trillion won annual operating loss. Samsung, by contrast, reportedly hit yield and qualification delays on its HBM3E chips that slowed major Nvidia orders, the proximate reason for a 61% share against a 17% one.

Samsung's remaining stronghold is conventional DRAM, but even that margin is shrinking. Bank of America estimates put SK hynix's monthly DRAM output at roughly 589,000 wafers this year against Samsung's 691,000. SK hynix is projected to expand output by about 38% between 2025 and 2028, compared with 17.5% at Samsung, which would cut the production gap to under 10% by 2028 from around 23% in 2025. The capacity both companies are pouring into HBM is not going into the commodity chips behind the memory shortage they've warned could run past 2027, and SK hynix has pledged to double its memory wafer output within five years.

Samsung, meanwhile, disputes the ranking, telling Reuters that its market cap should include preferred shares, which would lift its value to 2,246.4 trillion won. The gap also reflects the HBM3 and HBM3E generations rather than what comes next. Nvidia CEO Jensen Huang confirmed earlier this month that Samsung, SK hynix, and Micron all passed HBM4 certification for the Vera Rubin platform, and Samsung shipped the industry's first 12-layer HBM4E samples on May 29th.

SK Group Chairman Chey Tae-won, who pushed through the original Hynix acquisition despite internal opposition, explained the strategy in a book published in January. "What I really wanted to accomplish when we acquired Hynix was to transform it from a commodity memory producer into a mainstream semiconductor company whose products are indispensable," Chey said.

The Bank of Korea has named performance bonuses at Samsung Electronics and SK hynix as a risk to the country's inflationary stability, warning in a price-stability report on June 17th that payouts worth several hundred thousand dollars per worker could push wages higher across the wider economy. The central bank found that special pay in the IT sector increased by 60.6% year over year in the first quarter, while wage growth elsewhere ran at just 2.1%, a gap wide enough that two chipmakers are now featured in national monetary policy. The bank held its benchmark rate at 2.50% in May and projects full-year inflation of 2.7%, above its 2% target.

SK hynix agreed last September to set aside 10% of its operating profit for worker bonuses, and Samsung committed 10.5% of its semiconductor operating profit after its union threatened an 18-day strike in May. These figures mean that a memory worker on a base salary of 80 million won ($52,400) stands to collect roughly 626 million won ($410,000) this year, while SK hynix staff could receive more than 700 million won ($454,851) if the company reaches 250 trillion won in annual profit. SK workers could see close to $900,000 next year on top of this year's haul.

In its price-stability report, the Bank of Korea modeled how concentrated payouts move prices. When the share of firms paying top-10% bonuses rises, consumer prices climb 0.05 percentage points roughly five months later, a lag effect that broad, even wage increases don’t produce.

Governor Shin Hyun-song has said that consumer prices should stay on a high upward path, with second-half headline inflation near 3%. The bonuses have already spilled into other areas, with labor groups citing them in next year's minimum wage talks, and card spending has risen fastest in the Gyeonggi Province districts around the two firms' fabs, where luxury sales have surged.

The payouts can of course be traced back directly to the AI-driven memory supercycle that has sent DRAM and NAND contract prices climbing through 2025 and 2026. HBM demand for AI accelerators has handed Samsung and SK hynix record operating profits, with profit-linked bonus deals converting that windfall for the companies into bags of cash for workers in the companies’ microchip divisions.

Senior South Korean policymaker Kim Yong-beom spooked markets last month when he floated the idea of a “national dividend” in a Facebook post, writing that gains from the AI infrastructure era were built on an industrial foundation the entire nation accumulated over half a century. Seoul officials later said it had no such plans, however.

Intel has appointed Seok-Hee Lee, the former chief executive of memory maker SK hynix and battery maker SK On, as executive vice president of Intel Foundry, handing the semiconductor veteran control of advanced packaging, system integration, and all back-end technology development and manufacturing. Lee reports directly to CEO Lip-Bu Tan, and his arrival comes with a structural change at the foundry: Intel is splitting advanced packaging out as a dedicated business, with Naga Chandrasekaran narrowing his focus to front-end work on the Intel 18A and 14A nodes. Longtime executive Navid Shahriari is retiring after 37 years, the company announced.

Lee spent roughly a decade at Intel earlier in his career before holding leadership roles across the Korean chip industry, including the top job at SK hynix, one of the world's two largest suppliers of high-bandwidth memory. Tan credited Lee with "deep expertise in leading complex, high-scale technology and manufacturing organizations," and said the hire would help Intel "tightly couple leading-edge logic, memory, networking, and other components" for foundry customers.

Putting a former memory chief over packaging aligns with where Intel's back-end ambitions are. HBM stacks sit alongside logic dies inside the same package on every modern AI accelerator, and it’s joining those two components together that Lee now oversees. Last month, it was reported that SK hynix was testing Intel's EMIB packaging for HBM integration, sending both companies' shares higher.

Tan named EMIB-T and HBI as the technologies Intel intends to ramp to high volume under Lee. EMIB-T adds through-silicon vias to Intel's embedded bridge for higher power delivery and HBM4-class bandwidth, and is rolling out in production fabs this year. Intel has positioned the EMIB family against TSMC's CoWoS, whose lines have been oversubscribed for more than two years, and is reportedly in talks with Google and Amazon to package their custom AI chips.

It goes without saying, then, that the stakes for the unit Lee’s inheriting are huge. Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and CFO David Zinsner has said packaging revenue could exceed $1 billion at gross margins near 40%, with prepaid hyperscaler commitments reaching into the billions. Korean trade press, including the Seoul Economic Daily, has spun Lee's appointment around Intel's difficulty securing yields on its proprietary back-end processes, the kind of high-volume manufacturing problem he managed for decades in memory.

The hire follows Intel's April recruitment of Samsung foundry veteran Shawn Han. Lee resigned from SK On on May 28th, citing health reasons, according to Korean outlets, only to return to the industry three weeks later.

Wired has identified SK Telecom as the South Korean telecom company whose access to Anthropic's Claude Mythos model the White House ordered revoked over alleged ties to China, days before the Trump administration imposed the export controls that pulled Anthropic's most advanced AI models offline.

SK Telecom, South Korea's largest wireless carrier, was among roughly 150 organizations added to Anthropic's Project Glasswing in early June, the program through which Anthropic distributes Mythos for vulnerability detection. The White House asked Anthropic to revoke the carrier's access shortly after that expansion, and the company complied immediately. No export controls were threatened at that point, according to Wired.

SK Telecom’s footprint in China is minimal, generating roughly $1.9 million in Chinese revenue in 2024 and employing seven people in the country, according to its annual report. The national-security concern attaches instead to its parent, SK Group, whose affiliates hold extensive interests in Chinese semiconductors, energy, and other sectors.

Despite that relatively small footprint, the carrier has a deeper history within the country, having formed a wireless joint venture called UNISK with state-owned China Unicom in 2004. It then invested $1 billion in China Unicom convertible bonds in 2006 that converted into a roughly 6.6% stak, which was sold in 2009 for $1.3 billion. SK Telecom has kept a residual interest since then, listing a UNISK investment worth roughly $17 million in its 2025 filing with the U.S. Securities and Exchange Commission.

SK hynix belongs to the same SK Group, and it received Mythos access in the same expansion, as did Samsung. The two rank among the largest suppliers of the memory and logic silicon that underpins AI hardware, and both joined Anthropic's funding round as strategic investors.

The export controls followed a separate dispute, however, when Amazon, Anthropic's largest investor with a cumulative stake of about $13 billion, flagged a guardrail bypass in Fable 5 to the White House after researchers prompted the model to read a codebase and fix its flaws, turning it into a vulnerability-discovery tool. Amazon CEO Andy Jassy reportedly raised the findings with administration officials directly, which then led to the Commerce Department’s order on June 12 barring all foreign nationals — including immigrants inside the U.S. — from accessing Fable 5 and the underlying Mythos 5.

Rather than filter users by nationality, Anthropic disabled both models for everyone. The company said the demonstration it reviewed surfaced only a small number of previously known, minor vulnerabilities, and that banning a capability common to other frontier models would halt deployments across the industry.

About 100 cybersecurity professionals, including former Facebook security chief Alex Stamos and Luta Security's Katie Moussouris, signed an open letter arguing that while Mythos-class models are “quite good” at finding and weaponizing software flaws, they “are not uniquely good,” calling for the controls to be lifted.

Mythos 5 and Fable 5 remain offline as Anthropic and the White House continue negotiations over restoring access. Anthropic opened a Seoul office on June 17 and signed a memorandum of understanding with South Korea's Ministry of Science and ICT (Information and Communication Technology), naming SK Telecom among its local partners. SK Telecom has denied the allegations, telling a Korean newspaper that the anonymous claims in foreign media “lack verified facts,” and that it has no ties to China.

Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

A coalition of nine US trade associations has urged the Trump administration to take immediate action on what it describes as an emerging memory chip shortage driven by the explosive growth of AI data centers. In a June 3 letter sent to US Commerce Secretary Howard Lutnick and Treasury Secretary Scott Bessent shared with Tom's Hardware, the organizations — representing telecommunications providers, automakers, medical device manufacturers, and major retailers — warned that AI infrastructure deployments are consuming an outsized share of global memory production, creating supply constraints and price increases that could ripple across large segments of the US economy.

The coalition warned that the AI data center expansion, which has consumed an unprecedented share of global memory capacity, has led to a memory chip shortage that could lead to higher prices for consumer electronics, increased costs for broadband and telecommunications infrastructure, disruptions to automobile and medical device production, and delays affecting federal contractors attempting to fulfill government procurement obligations. The letter argues that these risks are emerging despite billions of dollars of US investment intended to strengthen domestic semiconductor supply chains.

The signatories acknowledged AI's importance but argue it shouldn't come at the expense of the rest of the economy. "While recent developments in AI offer the promise of generational technological advances and are important for US tech leadership, we must also ensure other key industries are not negatively impacted by this disruption in the marketplace," the coalition said.

The organizations are asking the administration to work directly with memory suppliers and major chip buyers to address the imbalance. Their recommendations include accelerating expansion of memory manufacturing capacity in the United States and allied nations, using trade agreements to strengthen supply-chain resilience, ensuring adequate memory supply for non-AI industries, leveraging CHIPS Act programs where possible, and reducing regulatory barriers that may slow capacity growth.

"We urge the Administration to work with memory chipmakers and chip buyers to assess steps that can be taken to address this imbalance in the memory market and protect against harm to consumers, workers, and businesses of all sizes," the letter states.

The warning arrives as memory manufacturers increasingly prioritize high-bandwidth memory (HBM), the specialized memory used in AI accelerators from companies such as Nvidia and AMD. Demand for HBM has surged over the past two years as hyperscalers race to deploy larger AI clusters, prompting memory suppliers to devote an increasing share of their production capacity to AI-oriented products.

Samsung and SK Hynix — which together with Micron control over 95% of global DRAM production — have been diverting wafer capacity toward high-margin HBM for AI accelerators, starving the commodity DRAM and NAND markets in the process. Both companies warned in April that significant shortages will continue through at least 2027. IDC, meanwhile, has already revised its 2026 PC market forecast downward by up to 9% as a direct consequence of memory scarcity and rising prices.

Industry analysts have repeatedly warned for months that AI demand is reshaping the economics of the memory market. While memory shortages have historically been cyclical, the coalition argues that AI infrastructure spending is creating a structural shift large enough to affect industries far removed from data centers. The letter marks the first coordinated, multi-industry push for federal intervention. Whether the administration will respond — and how — remains to be seen.

South Korean media has noted a surge in spending on luxury goods following big bonus payouts to semiconductor workers. For example, the Chosun Daily (machine translation) reports that luxury consumption in southern Gyeonggi Province, where the nation’s 'Semiconductor Belt' is located, has rocketed. In one local department store, some luxury goods category sales are up nearly 150%. The flood of cash and spending shows that towns in Gyeonggi Province are now enjoying their own 'Gangnam Style.'

The Korean news source provides some interesting stats showing the rapid increase in conspicuous consumption since the fab workers at Samsung and SK hynix earned their envy-inducing bonuses. At a department store/mall called Shinsegae South City, located in Yongin, Gyeonggi Province, luxury jewelry sales in May were up 146.3%, it says. Moreover, luxury watch sales rose 85.3%.

Chosun Daily also shared some retail stats for the Lotte Department Store Dongtan Branch (also in Gyeonggi Province). It says that from Jan 1 to May 27, 2026, luxury sales were up 40% compared to the same period last year. A breakdown of these figures shows customers didn’t just target luxury brands but big-ticket home appliances (a category up 30%). A statement from this department store shows they are aware of the economic driving force behind the spending on luxury goods. "Sales of high-end goods such as luxury and home appliances have increased due to the boom in semiconductor companies, the creation of advanced industrial clusters, and the move-in of new large apartment complexes," said a store statement.

It was a similar story at The Hyundai Department Store, Pangyo Branch (also in Gyeonggi Province). Here, luxury goods sales were up 46.1% in May. That compares with an increase observed across all Hyundai Department Store stores nationwide of about 32%. High-end watches and jewelry (66%) and high-end clothing brands (36.9%) were major contributors to the sales boom.

With locals snapping up luxury goods like kids picking up candy, the semiconductor boom in South Korea looks like it will be highly beneficial to mostly European brands like Chanel, Hermès, Prada, Gucci, Rolex, Cartier, etc.

Recent reports suggest the good times are rolling at SK hynix, where workers are tipped to receive bonuses of up to $900,000 next year, on top of $447,000 this year. It's good to see the huge influx of RAM and NAND cash not just going to Samjeon Nix (Samsung Electronics, SK hynix) corporate accounts, or one or two billionaires, but that the good times are being shared with those at the coal face.

SK hynix will double its memory wafer capacity within five years, SK Group chairman Chey Tae-won told reporters at Computex in Taipei on June 2nd, while repeating his forecast that the AI-driven shortage gripping the memory market will run until 2030. As reported by Bloomberg, Chey declined to put an exact dollar figure on the expansion, saying instead that the company's 2026 spending would climb well above the 30.2 trillion won (roughly $20 billion) it spent in 2025, and confirmed SK hynix has filed to list American depositary receipts in New York this year.

On its own timeline, the pledge will do little to shorten the squeeze. Chey put the lead time for a greenfield fab at more than five years, placing fresh output near the tail end of the shortage window that he’s predicting. This new stance is also a significant departure from his March comments at Nvidia’s GTC conference, where he said a new fab wasn’t planned and that capacity couldn’t be added on demand.

Chey also said the cost of the buildout is difficult to pin down because prices for land, equipment, and electricity keep moving, which is likely why no figure accompanied the announcement. With the company's existing lines already saturated, customers have offered to buy SK hynix's EUV scanners and prefund fab lines as available capacity has fallen to near zero. "Until 2030, there's still some shortage," Chey told reporters

Ultimately, it’s HBM that’s driving the massive gap between wafer supply and demand. HBM consumes far more wafers per bit than standard DRAM and carries the industry's highest margins, so capacity keeps tilting toward them. SK hynix holds about 57% of the HBM market and 32% of global DRAM, and Chey has said he wants the company to become a major HBM supplier for Nvidia's Vera Rubin platform and is seeking more manufacturing partnerships in Taiwan beyond TSMC.

But buyers aren’t waiting on new fabs for relief. TrendForce projected DRAM contract prices to rise 63% in the second quarter after climbing roughly 95% in the first, and DDR4 spot pricing ran up around 2,200% over 12 months before a recent decline. Even with capacity doubling, outlooks across the next five years are unchanged, and the market is likely to stay tight for the rest of the decade as things currently stand with AI demand.

Thousands of SK hynix employees fled their factory stations earlier today as a fire broke out in a room where fluorine gas was used. Yonhap News reports that seven of the workers have been hospitalized, five are being treated for eye irritation, and two are under observation (machine translation). At the time of writing, a cleanup operation appears to be continuing at SK hynix’s Cheongju 4th campus, with all 3,600 employees evacuated. A company official told Yonhap, “There are no issues with equipment operation, so there will be no production disruption.”

Reports indicate that the fire began at around 10.23 am Korean time today. An unintentional fire is probably not a great thing anywhere in an advanced semiconductor fab, even in the burgers and cigars wing. However, in “the gas room on the 6th floor connecting the M15 and M15X factories at SK Hynix's Cheongju 4th campus,” it could have been a particularly nasty incident. This room includes equipment/canisters/pipelines holding highly toxic fluorine gas.

According to the Korean news source, the fire in the gas room was extinguished immediately by sprinklers, but fluorine escaped into the room at a concentration estimated to be 5 ppm. This is where the seven hospitalized workers had been situated.

Fluorine gas is used in various industrial processes, but it is a highly reactive gas that can cause spontaneous combustion or explosions if it comes into contact with common materials. It is also quite deadly to humans. Wikipedia states that “significant irritation of the eyes and respiratory system as well as liver and kidney damage occur above 25 ppm… The eyes and nose are seriously damaged at 100 ppm… and inhalation of 1,000 ppm fluorine will cause death in minutes.”

Official insists there will be “no production disruption”

With the immense demand and pressure on memory-making titans like SK hynix, some may be concerned that a facility like Cheongju closing even for a few hours could impact supplies, schedules, pricing, and more. However, an official insisted, “There are no issues with equipment operation, so there will be no production disruption.” It was also suggested that the fire/leak occurred in the gas pipeline, but that fact had yet to be determined.

At the time of writing, there may still be environmental purification and repair work to do. If and when that’s completed, operatives will begin safety inspections, including air quality measurements. After the all-clear, “we plan to return the employees,” the official told Yonhap. We’ve linked to the latest report on this incident available at the source.

SK hynix announced iHBM today, a memory heat management technology designed to enhance AI system performance. The thermal packaging solution improves heat dissipation by integrating ICEs (integrated cooling elements) directly into the HBM package. SK hynix says the result is an over 30% reduction in thermal resistance, “ensuring stable operating characteristics even in high-temperature and high-load environments.”

The iHBM architecture embeds non-conductive silicon cooling elements directly into the Die-to-Die Physical Layer (D2D PHY), the critical, high-speed connection interface between the HBM base die and the AI processor, which is prone to high temperature spikes as a result of extreme data traffic. By placing cooling elements in this layer, SK hynix mitigates the severe thermal throttling that cripples AI system performance during heavy computational workloads.

The company believes that structurally preventing thermal throttling will enable next-generation memory layers (targeted for future generations like HBM5) to scale to higher stack heights and sustain maximum data transfer speeds under the heavy computational loads of AI data centers.

“iHBM is the optimal solution for minimizing heat generation developed by combining memory design capabilities and advanced packaging technology,” said SK hynix Vice President Lee Kang-wook. “We will proactively provide the value customers need in the AI environment and further solidify our leadership in AI memory.”

SK hynix plans to apply iHBM technology from next-generation products, such as HBM5, to meet the thermal management requirements of high-performance computing (HPC), AI data centers, and other ultra-high-density and ultra-high-bandwidth environments, thereby improving overall system stability and efficiency.

Heat management is one of the biggest challenges facing HBM (High-Bandwidth Memory) technology. Unlike conventional memory, HBM achieves massive bandwidth by vertically stacking multiple DRAM dies, dramatically shortening the distance data must travel and enabling far higher transfer speeds with better power efficiency.

To minimize latency and feed AI processors fast enough to avoid bottlenecks, HBM is placed extremely close to the GPU or AI accelerator on the same package, connected through a high-speed silicon interposer. However, this dense arrangement also creates severe thermal problems.

The Die-to-Die Physical Layer (D2D PHY) — the ultra-high-speed interface linking the processor and HBM stacks — continuously moves terabytes of data per second. As thousands of signaling lanes and billions of transistors switch at extremely high frequencies, switching losses, leakage current, and electrical resistance generate substantial heat.

The problem is compounded by the processor itself, which already produces enormous amounts of heat. With the HBM stacks packed tightly around the processor, heat accumulates rapidly in a very small area. When temperatures exceed safe limits, the system automatically reduces clock speeds and voltages through thermal throttling to prevent physical damage, lowering overall performance.

SK hynix's new iHBM approach attempts to tackle the problem at the structural level. Unlike conventional HBM cooling designs that primarily dissipate heat indirectly through the core die and surrounding package structures, the company's iHBM architecture instead places Integrated Cooling Elements (ICEs) directly around the D2D PHY region — the exact zone where thermal concentration is most severe. This approach creates a dedicated dissipation path at the source, reducing overall thermal resistance by 30% and allowing the chip to maintain stable operation under the high-temperature, high-pressure conditions that dense AI workloads demand.

SK hynix says the technology can be manufactured at scale using its existing Wafer Level Packaging (WLP) process, which is built on its Mass Reflow Molded Underfill (MR-MUF) packaging technology already used in commercial HBM products. The design is also architecturally compatible with existing System-in-Package configurations, meaning customers can integrate the new thermal capability without major redesigns.

Samsung and SK Hynix employees are reportedly rejecting overseas training programs in favor of bonuses while seeing their matchmaking grades rise on online dating sites. According to the Korean Media outlet Chosun, discussions on Samsung Electronics’ internal bulletin board indicate that employees are considering choosing potential bonuses over hard-earned, typically coveted training programs. The sentiments come amid projections that the company plans to distribute “record-high” performance bonuses due to profit surges from the AI-driven semiconductor boom, with the company’s policies restricting eligibility.

According to the report, Samsung Electronics has exempted employees currently undergoing overseas training from bonus eligibility. This stance is reportedly seeing a number of employees terminating their training to return to their roles. Samsung runs a highly sought-after training program that provides employees around their 7th year at the company with financial and operational support to pursue postgraduate degrees at prestigious institutions both in and outside Korea. For example, in addition to their annual salaries, the company provides employees pursuing an MBA in the US with 500 million Korean won (~$333,000) in tuition and living expenses over two years. The support varies across institutions and countries.

The program is typically highly competitive, with only 1 in 70 applicants succeeding. Now, following projections that the electronics giant could distribute an average of 600 million (~$400,000)won in bonuses to employees in the semiconductor division, interest in the training programs has dropped. Reports suggest that even those currently undergoing training are considering halting midway to be eligible for performance bonuses, as these are likely to outweigh the financial benefits of the training program.

According to the Chosun report, sources from Samsung Electronics stated, “There have been inquiries to the HR team about whether trainees can withdraw mid-program and if they must repay previously received company support.” indicating that despite potential repayment obligations, some employees are willing to return regardless.

These reports are coming even as Samsung Electronics employees are planning industrial action to compel the company to extend continuous performance bonuses to employees outside the semiconductor division. The company says only employees in the semiconductor division will receive ongoing bonuses, while others in other divisions will receive a one-time payment. The strike is scheduled for the 21st of May.

At Samsung’s competitor, SK Hynix, similar reports of employees abandoning training in favor of bonuses are emerging. Despite the fact that SK Hynix takes a softer stance by offering partial bonuses to training beneficiaries, anonymous posts on its internal board reportedly include comments like, “If next year’s bonus reaches 700 million Korean won (~$466,000), not abandoning the training might make me a sudden pauper overnight” and “Seeing the projected bonuses for next and the following year, I want to cut off the hand that applied for the training.”

These comments follow projections of even bigger bonuses in the coming years, as SK Hynix paid out 140 million Korean won (~$93,000) in performance bonuses early this year, which, unlike at Samsung, was distributed across the entire company. Analysts predict a dip in the popularity of overseas training programs at Samsung Electronics and SK Hynix over the next few years, as the appeal of performance bonuses grows. SK hynix bonuses are tipped to hit $477,000 this year and as much as $900,000 next year.

Beyond strikes, life-changing decisions, and financial gain, these massive performance bonuses stemming from AI-driven profit surges are influencing quite unexpected areas of life in South Korea. Reports from Chosun indicate that SK Hynix employees are ranking higher on matchmaking companies’ eligibility scales due to bonuses and increased income, with employees reportedly being flooded with blind-date offers.

"In the past, if we matched a partner for an SK hynix employee at about a B+ grade, now it's unconditionally 'A-grade.' As the overwhelming bonus system has become known, we're seeing a trend where female members are seeking out SK hynix employees first,” said Son Dong-gyu, CEO of the matchmaking company Bien Aller.

However, on the flip side, because bonuses are paid in direct proportion to days worked, there has been an uptick in aversion to taking extended leave, such as parental leave, as these are reportedly perceived as forfeiting income. These reports all underscore the massive influence of the AI boom on almost every aspect of humanity.

A senior South Korean policymaker has proposed redistributing tax revenue generated by the country's AI semiconductor boom to ordinary citizens as a “dividend,” rattling stock markets on the same day that Samsung's union bonus talks showed no sign of resolution, according to Bloomberg.

Kim Yong-beom, presidential chief of staff for policy, floated the idea of a "national dividend" in a Facebook post late Monday, writing that gains from the AI infrastructure era were built on an industrial foundation the entire nation accumulated over half a century. The benchmark Kospi index fell as much as 5.1% before recovering to close down 2.3% after Kim clarified he was referring to excess tax revenue rather than a new windfall levy on corporate profits. A government official confirmed to the outlet that the government is not considering any such plans, and that the comments were Kim's personal opinion.

The post came during the final stretch of government-mediated talks between Samsung and its largest labor union. Negotiations entered a second day on Tuesday at the National Labor Relations Commission in Sejong after 11 hours of talks on Monday produced no agreement, the Korea Herald reported.

The union is demanding 15% of operating profit as performance bonuses, removal of the existing payout cap, and a 7% base pay increase. Samsung management has reportedly offered terms exceeding rival SK hynix's 10% profit-sharing, but the union rejected those proposals because it wants the ratio institutionalized as a permanent system.

Samsung is forecast to post roughly 330 trillion won ($220 billion) in operating profit this year, while SK hynix is projected at 239 trillion won. If the two companies hit those marks, their combined corporate tax bill alone could exceed 100 trillion won, which would surpass the roughly 100 trillion won the Korean government estimated for total national corporate tax collection in 2026, per KB Securities analyst Lim Jae-kyun.

The union has set May 21st as the start of an 18-day general strike running through June 7th if talks collapse. Seoul Economic Daily reported earlier today that the negotiations were heading toward failure, with the Korea Herald noting that the Labor Relations Commission left open the possibility of extending mediation past its scheduled close if necessary.

A one-day walkout in April cut Samsung's contract foundry output by 58% on the affected night shift, and analysts have estimated that an 18-day stoppage could cost $6.9 billion to $11.7 billion in direct production losses.

The government does have a rarely used nuclear option: Under Article 76 of South Korea's labor law, the labor minister can issue an emergency arbitration order suspending strike activity for 30 days. The mechanism has been invoked only four times since 1969, and the Labor Ministry said Tuesday it has not begun reviewing the option.

Share prices of both Intel and SK hynix have surged following a ZDNet Korea report claiming that SK is conducting R&D with Intel on 2.5D packaging using Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology, with the intention of integrating high-bandwidth memory (HBM) and logic semiconductors. Citing unnamed industry sources, ZDNet Korea reports that the company is also evaluating the materials and components required for production.

SK hynix shares have hit an all-time intraday high of $1,320 (1,946,000 Korean Won) on the Korea Exchange, climbing as much as 14.5% and pushing the company's market cap past $900 billion. Likewise, Intel's share price is up nearly 14% at the time of publication, marking a rise of 229% in the last six months, and 91% in the last month alone.

EMIB connects multiple semiconductor dies using small silicon bridges embedded directly in the package substrate, rather than relying on the large silicon interposer that underpins TSMC's Chip-on-Wafer-on-Substrate (CoWoS) platform. The approach is less expensive per package and avoids some of CoWoS's thermal complexity, though the two technologies target different segments of the market.

Intel Foundry has been actively marketing EMIB and its next-gen variant, EMIB-T, to external customers. Intel CFO Dave Zinsner told the Morgan Stanley TMT conference in March that the foundry division is "close to closing some deals that are in the billions per year in terms of revenue" on advanced packaging alone. EMIB-T, which adds through-silicon vias to the bridge for HBM4 compatibility and higher bandwidth, is expected to enter production fab rollout this year.

TSMC's CoWoS lines, meanwhile, have been massively oversubscribed for more than two years. Nvidia alone is expected to account for roughly 60% of global CoWoS demand this year, with Broadcom and AMD absorbing another 26%. That leaves limited capacity for custom ASIC vendors and smaller AI chip developers, creating an opening for alternative packaging providers.

Intel has already confirmed that some customer designs originally scoped for CoWoS have been ported to EMIB or Foveros, with reports last month that Google and Amazon are among the hyperscalers showing interest in Intel Foundry's advanced packaging capabilities, no doubt at least driven in part by limited access to CoWoS.

SK hynix is already building its own 2.5D packaging facilities independently of Intel. The company recently broke ground on a $3.87 billion advanced packaging plant in West Lafayette, Indiana, which is expected to begin operations in 2028, and approved a ₩19 trillion ($12.9 billion) packaging and test facility in Cheongju, South Korea, in January. If the Intel EMIB partnership materializes, it would give SK hynix an additional packaging pathway alongside its own in-house facilities and its longstanding reliance on TSMC's CoWoS.

Neither SK nor Intel has confirmed the rumors.

Major tech companies have begun offering to directly invest in SK hynix's new chip production lines and bankroll purchases of advanced manufacturing equipment, Reuters has reported, in what sources described as an unprecedented escalation of efforts to secure memory supply during a global shortage. SK is weighing the proposals cautiously, concerned that accepting could leave it beholden to individual buyers.

The offers go well beyond standard long-term supply agreements. Some customers have proposed funding dedicated memory production lines at SK hynix's facilities, according to people familiar with the discussions who spoke to Reuters, while others have offered to cover the cost of ASML EUV lithography machines, which are used to pattern circuits on silicon wafers and individually cost hundreds of millions of dollars.

Arrangements where customers fund dedicated production capacity are common in logic chipmaking, but they have no precedent in the memory industry, where DRAM and NAND have historically been produced speculatively and sold into an open market.

One proposal targeted the first phase of SK hynix's upcoming Yongin DRAM fab in South Korea. SK told Reuters that it’s “comprehensively reviewing various approaches and structural alternatives that differ from conventional long-term agreements," but declined to delve into the specifics. The company, now Asia's third most valuable by market cap behind TSMC and Samsung, has seen its share price rise 154% this year.

"Regardless of the type of offer, available capacity is essentially zero right now," said another source to Reuters. "There isn't even a small portion that can be designated for a specific customer."

The proposals are especially striking given the shift in the supply dynamic. As recently as February, Samsung and SK hynix were moving in opposite directions, shortening contract terms and adopting post-settlement pricing mechanisms that allowed them to capture rising spot prices. Customers are now attempting to bypass that pricing power by co-investing in the production infrastructure itself

SK hynix and its rivals, Samsung and Micron, have all acknowledged holding discussions with customers about multi-year supply deals, but those being considered by SK are entirely different. Among the mechanisms under consideration are price-band agreements that would set annual floor and ceiling prices, eliminating the quarterly negotiations that have historically defined memory pricing. Separate discussions have reportedly involved prepayment structures requiring customers to put up 30% to 40% of the contract value in cash upfront.

Samsung told Reuters that its recently signed long-term agreements with customers are "binding," though it didn’t elaborate. Suppliers are also being careful about how they distribute limited capacity, with one source telling Reuters they want to avoid the appearance of favoring specific customers during the AI buildout.

SK Group chairman Chey Tae-won said in March that he expects the memory shortage to persist through 2030, and both Samsung and SK hynix warned investors last month that supply constraints would continue through at least 2027. One source told Reuters that chipmakers don't want to "pick a horse" in the AI race and end up backing the wrong one.

The AI chip supercycle is generating such extraordinary profits at South Korea's two largest memory manufacturers that individual employee bonuses at SK hynix could average roughly 700 million won ($477,000) this year, and almost $900,000 next year, according to Korea JoongAng Daily. Samsung Electronics' labor union, meanwhile, has threatened a general strike from May 21st to June 7th after rejecting management's compensation offer.

SK hynix agreed last September to remove its previous bonus cap and allocate 10% of annual operating profit directly to employees as performance-based payouts. With analyst forecasts of some 250 trillion won ($169 billion) in operating profit for 2026, the resulting bonus pool of 25 trillion won would be split among roughly 35,000 workers. It’s understood that the company already paid profit-sharing bonuses averaging about 140 million won (roughly $95,000) per employee in February.

At Samsung, things aren’t looking quite so rosy, as disputes rage on surrounding what percentage of earnings should flow to workers. The company’s union is pushing for 15% of operating profit, which market analysts project will reach roughly 298 trillion won ($202 billion) this year. At that level, the semiconductor division alone would owe approximately 580 million won (~$396,000) per employee across its 77,000-person workforce.

Samsung management countered with a 10% allocation matching SK’s framework, but that proposal was rejected, with the union instead opting to plan a large rally at the company’s Pyeongtaek fab scheduled for April 23rd. Samsung Electronics asked a court last Thursday to block what it called “illegal activities” during a strike. Union chairman Choi Seung-ho says that roughly 200 employees have left for SK hynix over the last four months, according to the Korea Herald.

The scale of these payouts marks a huge reversal of what we’ve seen in recent years. In 2024, Samsung paid no performance bonuses at all after the chip unit posted operating losses throughout 2023’s memory downturn, while SK’s own bonus rate collapsed during the same period. The turnaround has obviously been driven almost entirely by surging demand for HBM and other AI-oriented memory products.

This potential windfall for SK and Samsung employees has sparked unusual public backlash in South Korea, with posts on the anonymous workplace forum Blind arguing that companies benefiting from state infrastructure spending and the K-Chips Act’s 20% tax credits should share their profits more broadly. The combined tax benefits received by both companies over the last two years total an estimated 20 trillion won, which is roughly $13.6 billion.

Looking ahead, the potential bonuses could climb higher still, with investment bank Macquarie having forecasted SK’s operating profit at 447 trillion won ($304.5 billion) for next year, which would push average employee bonuses beyond 1 billion won under the existing 10% profit-sharing agreement.

SK hynix disclosed in a regulatory filing on Tuesday that it will purchase 11.9 trillion won ($7.9 billion) worth of EUV lithography equipment from ASML by the end of 2027, as reported by Bloomberg. The deal is the largest single EUV order ever publicly disclosed by an ASML customer, and it runs through December 2027. SK hynix said the tools are intended for mass production of next-gen products as the company races to expand capacity for AI-driven memory demand.

Bernstein analyst David Dao estimates that the order covers approximately 30 new EUV machines over two years, slightly above his prior forecast of 26. The scanners will be deployed across two facilities: SK hynix's M15X plant in Cheongju, which is focused on producing HBM chips, and the new Yongin Semiconductor Cluster, which will handle advanced DRAM. Ryu Young-ho, a senior analyst at NH Investment & Securities, told Reuters that the equipment is expected to serve both HBM and advanced DRAM production.

SK hynix accelerated the Yongin timeline earlier this year, moving the first cleanroom opening from May to February 2027. The company committed a total of 31 trillion won ($21.5 billion) to the Yongin Phase 1 fab, which will eventually house two building shells and six cleanrooms. M15X, meanwhile, began deploying wafers in February after its first clean room opened in October of last year.

ING analyst Marc Hesselink noted in a client note that the order contains a "pull-in element" designed to lock down ASML equipment supply ahead of competitors. SK hynix is likely to increase spending on the less advanced DUV lithography machines separately, where lead times are shorter at three to six months, Hesselink added.

ASML, which announced plans to cut some 1,700 managerial roles back in January, reported a €38.8 billion order backlog at the end of 2025. Samsung and TSMC are also major buyers of EUV equipment, and all three major memory makers are expanding capacity as AI infrastructure buildout continues to strain global DRAM and HBM supply.

SK hynix currently holds more than 60% of the global HBM market and is a primary supplier to Nvidia, but Samsung is ramping its own EUV-based HBM production aggressively. SK hynix announced a separate $13 billion advanced packaging facility in Cheongju earlier this year to handle the downstream assembly of HBM chips produced at M15X.

QatarEnergy has not restarted helium production at its Ras Laffan complex — one of the largest concentrations of helium production infrastructure globally — nine days after Iranian drone strikes forced the facility offline. The ensuing disruption to supply has sparked concerns for South Korea's chip industry, Nikkei reports.

The facility went offline on March 2 following drone strikes, removing approximately 30% of global helium supply from the market. QatarEnergy declared force majeure on existing contracts on March 4, freeing it from supply obligations to customers, and industry outlet Gasworld reported on March 7 that no imminent restart is planned.

Helium consultant Phil Kornbluth, speaking at a Gasworld webinar on March 4, said that if the outage extends beyond roughly two weeks, industrial gas distributors could be forced to relocate cryogenic equipment and revalidate supplier relationships, a process that could stretch over months regardless of when Qatari output resumes.

South Korea is among the most exposed countries, which, according to the Korea International Trade Association, imported 64.7% of its helium from Qatar in 2025. The country relies heavily on helium imports to cool silicon wafers during fabrication and is understood to have no viable substitute.

The country's Ministry of Trade, Industry and Resources has reportedly launched an investigation into supply and demand for 14 semiconductor materials and equipment types with high dependence on Middle Eastern sources, Nikkei reported on Wednesday. Bromine, which is used in circuit formation, is another big concern, with South Korea sourcing 90% of its imports from Israel, also party to the ongoing conflict in Iran.

South Korean memory giant SK hynix has since said it had diversified supplies for helium and secured sufficient inventory. Meanwhile, TSMC said that it doesn’t currently anticipate a notable impact following Ras Laffan going offline, but that it’s monitoring the situation. South Korea and Taiwan each account for 18% of global semiconductor production capacity, according to Boston Consulting Group and the Semiconductor Industry Association.

The situation echoes a 2022 shortage of helium and neon, which was triggered by Russia's invasion of Ukraine. That event prompted South Korea to pursue supply diversification and domestic production of those gases, which are used in lithography to transfer circuit patterns onto wafers

Typical NAND chips present in SSDs have steadily evolved in speed and capacity over time, with contemporary server-grade units capable of reaching 28 GB/s per unit. Somehow, that's still not enough for the AI world. In turn, SK Hynix and SanDisk have jointly announced HBF, or High Bandwidth Flash, for the inference servers of tomorrow.

The official press release is exceedingly light on details, but it mentions that HBF is specifically poised to act as a layer between HBM DRAM and flash SSDs. Given that a stack of current-gen HBM3E is good for around 1.2 TB/s, we can hypothesize that HCF chips could be gunning for speeds of at least 10 GB/s each, if not more, for combined speeds in the hundreds of GB/s. After all, going to the trouble of creating an entirely new standard wouldn't make much sense otherwise.

Power efficiency is apparently a concern for the standard-bearers, a pretty understandable notion in this day and age, where datacenters have massive wattage needs. A high-end Micron 9650 SSD pulls 25 W at full tilt, a figure that gets really ugly really fast when you think in exabyte-scale deployments with tens of thousands of drives.

There are no specifics on how this new HBF is meant to interact with systems, but the vague wording of "supporting layer" could mean it would be analogous to an on-SSD cache, but much bigger. It could also be a really fast block storage device a la Optane that applications and/or operating systems would have to be tweaked to use efficiently.

The announcement offers no target date, but it mentions that "demand of complex memory solutions, including HBF, will pick up around 2030", so that's as a good estimate as any for a production release date. The standard will be under the purview of the Open Compute Project. The companies are targeting HBF at inference servers, given that the outputs that bots users produce needs to be stored somewhere, and that storage need is projected to grow exponentially.

Memory pricing cycles are nothing new, but the way it’s being sold is changing. Over the past several months, Samsung and SK hynix have begun moving away from long-term, fixed-price supply contracts, replacing them with shorter agreements and post-settlement pricing mechanisms that allow prices to be adjusted after delivery. Micron is also understood to be following a similar path.

According to reporting cited by DigiTimes, these newer contracts are appearing at the same time as the sharp upswing in DRAM and NAND pricing we’ve been watching unfold with relentless escalation, driven primarily by AI infrastructure demand and constrained supply at advanced nodes. Memory makers are expected to make over $551 billion in revenue in 2026.

Where buyers once locked in prices for six to 12 months at a time with limited scope for renegotiation, suppliers are now favoring contracts measured in quarters or even months, with pricing that’s particularly exposed to market movements, which shifts the risk back onto buyers.

Post-settlement pricing reflects supplier confidence

Under traditional agreements, DRAM and NAND prices are set at the time of signing. Even if spot prices move sharply, quarter renegotiation typically adjusts pricing within a narrow band of roughly 10%. These arrangements gave the market’s largest buyers cost predictability and insulated them from short-term instability.

Post-settlement pricing does the opposite. While products are delivered at the agreed price during the contract term, the final payment is adjusted at the end of the term to reflect prevailing market prices. If prices rise materially — as with DRAM in recent months — customers pay the difference. On the other hand, suppliers absorb the loss if prices fall.

Now, according to industry sources cited by Digitimes, Samsung, SK hynix, and Micron have all signed such contracts, primarily with large North American technology companies. One source noted that, for major customers, securing memory supply has become a higher priority than locking in price certainty, even if that means paying more later. This is nothing more than fundamental supply and demand dynamics that were bound to come into play given the state of the market in recent months.

It’s important to note that these post-settlement pricing arrangements only work if suppliers are confident that prices will remain elevated, because why would they push for them otherwise? The willingness of all the big three memory makers to adopt post-settlement pricing, unfortunately, suggests they are.

Contract lengths shrink alongside price flexibility

Pricing is not all that's changing — contract durations are also getting shorter. Memory buyers, particularly hyperscalers, are understood to have pushed for longer-term agreements to guarantee supply as demand for high-capacity memory accelerates while supply tightens. Suppliers are obviously starting to push back against those terms, opting instead for contracts lasting mere months. DigiTimes, citing Korean-language publication ET News, gave the example of a North American data center operator failing to secure a two-year supply deal from one memory vendor, subsequently sourcing capacity from another supplier under a shorter contract that included post-settlement pricing.

These supplier-favoring terms are expected to persist at least through the second half of the year, when the pace of memory price increases is projected by some analysts to plateau somewhat. Even then, few expect a return to the long, fixed-price contracts that dominated during the initial post-pandemic years, and who's to say that pricing will start to slow down in any case?

The current state of the memory market is without precedent, strangled tighter and tighter with each passing day by the unrelenting demands of an out-of-control AI bubble. While we have seen some levelling off in recent weeks, it’s borderline impossible to make any meaningful predictions in good faith about where memory pricing may or may not be even next month; we can forget about where it might be six months or more from now because there’s simply no telling.

Operating margins now at 40-50%

Recent analysis from ZDNet shows just how favorable this market has become for suppliers. It projects that Samsung and SK hynix could post NAND operating margins of 40-50% for the first half of 2026, levels that would have seemed implausible during the oversupply conditions we saw in 2022 and early 2023. Those margins are predicated not just on higher prices, but disciplined supply management and a willingness to walk away from unfavorable contracts.

ZDNet notes that the industry expects that NAND products will reach record profitability for the first time since 2017, adding that its margins are estimated to have climbed into the 20% range in Q4 2025. NAND prices are expected to rise in stages across Q1 and Q2 of this year, with conservative capital spending continuing to tighten supply and contribute to what is becoming a chronic shortage.

Not all buyers are feeling the effects of this equally, though. Apple is one company that, according to TF International Securities analyst Ming-Chi Kuo, has shifted its memory price negotiations from a six-monthly to quarterly cadence. He expects LPDDR prices to rise in Apple’s first fiscal quarter of 2026, with further increases likely in the following quarter. NAND price increases are expected to be more modest.

Kuo also notes that many smartphone brands are struggling to secure sufficient memory supply even when they’re willing to pay higher prices. Some Chinese vendors have reportedly delayed product launches or reduced hardware specifications as a result. But Apple’s position is different: While higher memory costs could pressure gross margins in the near term, Kuo suggests the iPhone maker is willing to absorb those costs to protect shipment volumes, adding that Apple is considering keeping its starting prices for its planned iPhone 18 lineup largely unchanged.

All these factors together demonstrate that there’s a structural shift taking place in how memory is allocated and sold. The balance of power has moved firmly back toward suppliers, and that’s causing contract terms to adjust accordingly.

This doesn’t mean that prices will rise indefinitely. Memory remains a cyclical, capital-intensive industry, and periods of high profitability tend to attract overinvestment. But the current contract changes suggest that suppliers are prioritizing margin discipline and pricing flexibility over volume stability, and will continue to do so in at least the medium term.

The artificial intelligence supercycle is reshaping the semiconductor and electronics industries, as the scale of the AI infrastructure buildout strains the entire supply chain. While developers of AI accelerators like Nvidia are cashing in on the AI boom, it's memory makers that will earn the most cash, according to estimates from TrendForce. Arguably, this is a result of the different business models and expansion strategies memory makers use compared to foundries, in addition to the behavior of the commodity market.

Demand outstrips supply

The company projects that while global foundry revenue is expected to total $218.7 billion, 3D NAND and DRAM revenue will reach $551.6 billion, which means that the total market for memory is more than twice as large as contract chip production. TrendForce attributes this to structural market changes caused by AI buildouts. The latter creates elevated demand for specific types of memory, creating shortages of all types of memory, and therefore affecting prices across the industry. As a consequence, while the AI industry does not need low-capacity commodity memory devices, they also become substantially more expensive amid tight supply. This creates the perfect conditions for memory makers to capitalize upon.

Indeed, the spot price of a 16 Gb DDR5 chip at DRAMeXchange was $38 on average, with a daily high of $53 and a daily low of $25. By contrast, the very same chip used to cost $4.75 on average just one year ago ($3.70 session low, $6.60 session high). Similar changes occurred to the prices of 3D NAND memory in recent quarters.

Fundamental differences

Just like some other analyst firms, TrendForce calls the AI megatrend a 'supercycle,' indicating its overwhelming ubiquity, which affects multiple industries, and its potential length.

There were two periods in the last few decades when revenue of memory makers grew significantly year-over-year for two years in a row: in 2017 – 2018, when hyperscalers built their vast data centers (+62% in 2017 and +27% in 2018), and in 2020 – 2021, when people increased purchases of PCs amid the COVID-19 pandemic. In both cases, memory makers increased capacity to meet demand and maintain their market share, which caused sharp drops in revenue back in 2019 and 2022.

The foundry industry — which is much more capital-intensive than the 3D NAND or DRAM industries — uses fabs that are harder and longer to build, and only suffered a year-over-year revenue decline in 2023.

The situation today is vastly different. On the one hand, leading developers of frontier AI models need the most powerful clusters to train their models, therefore creating demand for leading-edge hardware with expensive HBM3E memory and plenty of storage. On the other hand, these companies and their clients need more powerful inference systems to use those models. Therefore, demand for CPUs, AI accelerators, memory, and storage does not decline over time. Meanwhile, buyers like cloud service providers (CSPs) tend to be less sensitive to price increases, which is why 3D NAND and DRAM suppliers are expected to raise average selling prices more aggressively than in the past cycles.

Foundry vs. Commodity

3D NAND and DRAM are commodities, so their prices behave like prices of commodities, almost immediately reacting to tightening supply, increasing demand, or sentiment among buyers. While large PC makers purchase their memory at prices agreed upon every six months, a significant portion of memory is sold on the spot market.

This dynamic is reflected in TrendForce's projections that show memory revenue growth accelerating after the downturn of 2022 – 2023, including an expected 80% increase in 2024, followed by 46% growth in 2025, and a projected 134% surge in 2026.

By contrast, foundries tend to operate under long-term agreements that smooth price fluctuations, which prevents sharp swings that characterize memory markets. Even during periods of strong demand, foundry pricing adjustments occur gradually, which means slower revenue growth compared to memory vendors.

TrendForce models that following a 19% year-over-year revenue increase in 2024, the foundry market grew 25% in 2025 and will grow another 25% this year.

As a result, boosted by the AI supercycle and not constrained by long-term agreements, memory vendors will earn more than two times more this year alone compared to producers of logic, which have to adhere to their long-term contracts.

The biggest question

With HBM4 memory devices using four times more silicon than typical DRAM ICs, it is obvious that memory makers cannot meet all the demand that exists because of insufficient capacity, which results in price adjustments. However, the biggest question is how significantly current commodity 3D NAND and DRAM prices are influenced by insufficient supply, and how significantly they are influenced by typical commodity memory market behavior that dictates that customers buy more memory when it is getting more expensive, as it may get even more expensive in the future?

In one of the most hotly competitive and profitable tech industries, the three major memory makers, Samsung, SK Hynix, and Micron, are individually investigating their customers to prevent memory hoarding, according to Nikkei Asia. They’re asking customers to disclose their own customers and order volumes to ensure that no one is hoarding more memory than they need, exacerbating memory supply problems.

The immediate impact of this may well be to accelerate price increases for consumer devices. After all, if a company can’t buy cheaper memory now, it could be more expensive to buy it later. But this may help give memory makers the confidence they need to effectively invest in increased production, and it might just give smaller customers a chance to compete fairly.

Fool me twice… you can’t fool me again

Since memory demand started skyrocketing in 2025, memory makers have been inundated with calls to increase supply while brands panic-bought what was available. Ramping up production lines and retooling fabs is required, but it’s not that easy. NAND flash, particularly the newest and most capable chips, uses cutting-edge facilities, and those manufacturing lines take years to bring online.

Production can and is being increased, but the required investment for such an endeavour is enormous. Though the potential upsides are excellent – increased supply should mean the memory makers can sell more in turn – the potential downsides are there too. Most notably, if supply and demand equalize, any industry changes could swing the ratio in the other direction, leaving the memory companies oversupplied and competing with each other to sell what they have.

This isn’t some theorized scenario, either. It’s already happened, which is why Samsung, SK Hynix, and Micron are twice shy about increasing production.

During the pandemic, as everyone rushed to buy desktops and laptops to work from home, memory was once again in short supply, and the memory makers scrambled to catch up. They invested in new facilities, taped out new production lines, and pivoted the enterprise to adjust to a new world where memory wasn’t plentiful.

But it wasn’t to last. Just a few years later, as demand started to fall, problems arose. Because during those pandemic months and years, customers of the major memory manufacturers overbooked and built up stockpiles of their own, they didn’t continue to replace them when their own orders dwindled. By the end of 2022, memory sales had dropped by almost a third, and revenue was crashing right behind it as the going price for memory cratered.

This led to companies like Samsung actually cutting production of its 3D NAND and DRAM products. Although it claimed to be continuing R&D expansion and infrastructure building, it wasn't on the same scale as it would have been had orders remained strong. SK Hynix followed suit several months later, and those cuts continued throughout 2023 across a range of companies.

Which brings us back to 2026. This time, the memory makers are looking to ensure that the memory hoarding doesn’t happen, so that if and when demand and supply are realigned, there’s less chance of the swing continuing into oversupply, under-demand territory.

That’s good for them, because it means demand should remain stable even if there are wobbles in the AI industry, or even an eventual bubble burst and collapse. If memory customers don’t have their own stockpiles, they’ll still need at least some memory, even if demand falls dramatically.

But won’t this just keep memory prices permanently high? Won’t it help prevent a big pricing correction if and when that bubble bursts, just keeping us all paying over the odds for memory forever?

Perhaps.

A boon to consumers

In the near term, it might actually stop memory prices from rising as quickly. If customers of Micron, Samsung, and SK Hynix have been overbuying – and why wouldn’t they, if they can afford it – then preventing that immediately should curb demand. That could help slow the current parabolic price rises for memory specifically. While that might mean the major customers who had planned on stockpiling cheaper memory end up raising their prices sooner than they had planned, the overall effect should see a slowdown.

Similarly, cutting the overbooked orders should make it easier for smaller memory customers to gain access to orders. If they aren’t trying to compete with not only major companies but also major companies overbuying, they should find it easier to get stock of memory at fairer prices. That has the potential to stabilize industries and prevent smaller brands from being pushed out of markets entirely, keeping competition healthier, which is always good for customers.

It could also help give the memory manufacturers the confidence they seek to build out production faster and more effectively. Whereas previously their efforts in boosting supply ended up with them having to reduce supply down the line, this way they can be more confident of a longer tail for their business.

We just had a flurry of new investment announcements from Micron, SK Hynix, and Samsung, all of which are building new fabrication lines and packaging facilities. They won’t really come online until 2027-2028, but that at least gives us some time frame for when memory supply and demand could stabilize, with or without an AI bubble collapse.

Here’s hoping

What Micron, SK Hynix, and Samsung are doing in looking over the books of their customers feels like them expanding their influence even beyond being one of the most important technological bottlenecks facing the world right now. It feels intrusive, and even a little oppressive. They’re looking to control not only this limited supply of incredibly important hardware, but what their customers do with it, too.

But what’s good for them may be better for us, too. Demand policing doesn’t create new chips, but in reducing the phantom demand, they do lower overall demand, and bring back a little more predictability to an industry that has been racing ahead of everyone’s best guesses as the world panic bought what was available in a rush against one another.

Now, maybe the smaller buyers can compete because they aren’t trying to compete against capital and stockpiles. The memory makers can commit to capacity expansion without fearing a post-AI cliff face, as they did with the pandemic aftermath.

None of that is guaranteed, and the bigger buyers will continue to outweigh their smaller contemporaries and garner the priority they seek. But if it can slow things down just a little, it might make the next hard year ahead a little softer while we wait for that new capacity to come online in the years to come. Cutting that overbuying now is one of the few levers the industry can pull to prevent this cycle from getting far worse before it may get better.

Update 17/02/2026 9:30am PT: Article introduction amended to reflect that the memory makers are operating independently of one another.

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

Memory chip giant SK Hynix is investing $10 billion in a new AI solutions company in the U.S, tentatively named AI Company. The new firm will have full access to this new investment and will be able to deploy it as it sees fit to promote the AI industry, bolster new AI startups and developments, and encourage its own strength and competitiveness in memory chip development, the company detailed in a press release. Such investment could even mean granting easier access to key SK Hynix technologies, like High Bandwidth Memory (HBM).

“Leveraging its unparalleled chip technologies, such as HBM, the memory chipmaker will try to play a pivotal role in delivering optimized AI systems for its customers in the AI datacenter sector,” SK Hynix said in a statement.

“The company will also continue making strategic investments in and collaborating with AI firms to strengthen its competitiveness in memory chips and provide a range of AI datacenter solutions.”

The new firm will be established by restructuring the California-based SSD manufacturing subsidiary, SK hynix NAND Product Solutions Corp, also known as Solidigm. It will retain its name under AI Company, but the new parent company will serve as its AI investment arm moving forward.

Following Nvidia's lead

One of the starkest stories of the past year in technology has been the sheer scale of investments in AI. Alongside the hundreds of billions in investment for data center projects, we’ve also seen Nvidia leveraging its vast stockpiles of cash to prop up other companies that are key to its ambitions for the AI industry and its ability to supply the hardware for it.

Nvidia invested heavily in OpenAI, in Intel, in CoreWeave, and in a range of European companies, too. It announced $1.5 in Nscale, $600 million in Quantinuum, $300 million in Black Forest Labs, $100 million in CuspAI, $20 million in PhysicsX – and the list goes on.

Although SK hynix can’t quite offer the levels of investment Nvidia is throwing around, the AI Company certainly sounds like that kind of investment vehicle. If SK hynix can help build up a range of companies developing AI software and hardware, it may encourage the industry as a whole to keep growing, ensuring that it has more customers for its memory products for years to come.

That kind of industry confidence could allow it to build up its own fabrication production without risking that capacity being wasted down the line if there’s an AI industry contraction or bubble-bursting effect.

A signal to Washington

Alongside making the foundations of its own business dominance firmer with targeted investment, SK hynix’s new AI Company is also a very public signal to the Trump Administration that it is investing in American companies. President Trump recently floated the idea of applying 100% tariffs to memory companies if they didn’t fabricate their chips in the U.S. While such an idea would effectively cripple the American tech industry by eliminating its access to cutting-edge memory, the industry has nonetheless responded.

Micron recently broke ground on a new fabrication facility in New York, with plans for it to produce some of the most cutting-edge memory products in America – and a huge portion of it by 2040. For its part, Samsung has been keen to highlight that it does already operate a semiconductor plant in Taylor, Texas, though whether that’s enough to hold off any punitive actions from the government remains to be seen. It’s not a NAND Flash fab, which is what the Trump Administration seems most keen on bringing to U.S. shores.

SK hynix is building an advanced packaging facility in West Lafayette, Indiana, but doesn’t actually fabricate memory in the U.S. It’s quite possible that this latest AI investment initiative may be a way to claim that it plans to produce memory inside America, or at least to cement its interest in American investment.

If either Samsung or SK hynix were to be hit with trade restrictions, but Micron was exempt, the effect on the memory industry would be dramatic to say the least.

Bolstering sustained growth

SK hynix may well find it easy to find new investment opportunities for its AI Company once it’s established. It said in its announcement that it will leverage its “unparalleled chip technologies, such as HBM,” to help it deliver “optimized AI systems for its customers.” That sounds an awful lot like gaining SK hynix investment could give a faster pipeline to access the latest HBM technologies.

In an environment where critical components and material shortages are bottlenecks to AI growth, having the backing of one of only three key memory producers in the world could be hugely beneficial.

SK hynix is making hay while the sun shines, too. It just posted forecast-beating profits in the recent quarter, increasing 137% year on year. That’s off the back of similarly impressive results this time last year, too. It’s using this new financial muscle to invest $13 billion in a new chip packaging plant in South Korea.

This latest $10 billion AI Company fund is just one more example of that. Like Nvidia and many other top tech companies, SK hynix is investing in the future of AI to give its current trajectory as long a tail as possible before any eventual contraction curtails it.

SK hynix, the world's biggest supplier of high-bandwidth memory (HBM), this week approved a ₩19 trillion ($12.896 billion) investment to build P&T7, a new advanced packaging and test facility in South Korea, dedicated solely to HBM. The plant will likely be the biggest HBM assembly and test facility in the world, but it will almost certainly not be the last HBM packaging and test facility of the same scale and cost going forward, considering the booming demand for memory, which has caused DRAM pricing to skyrocket.

Being the world's largest supplier of any type of product means you need to stay ahead of the whole industry, in terms of technology and production capacity, and the devil is in the details.

A massive facility

The company plans to construct what it calls P&T7 (Packaging & Testing 7) facility at the Cheongju Technopolis Industrial Complex, on a site measuring approximately 70,000 pyeong (approx. 231,405 square meters or 2,490,822 square feet). Construction is scheduled to begin in April 2026, and completion is targeted for the end of 2027, which is when the building will be finished, and is when SK hynix will begin installing equipment. Due to the equipping phase, expect the plant to come online toward the end of the decade on time for HBM4E, HBM5, and HBM5E types of memory.

The facility's dimensions are massive, resulting in a campus-scale site, rather than a back-end factory plot. For packaging and testing, the Fab P&T7 plot is unusually large; this may reflect the importance of HBM (and other exotic types of memory) assembly for the AI industry specifically, and the memory industry as a whole.

To put the scale into context, Intel's Ocotillo Campus near Chandler, Arizona, spans over 362,727 square meters, but it houses multiple front-end fab buildings, such as Fab 12, Fab 22, Fab 32, Fab 52, and Fab 62. Both Fab 52 and Fab 62 are expected to be capable of processing up to 40,000 wafer starts per month each when fully ramped, which makes them bigger than typical logic fabs run by TSMC.

While HBM packaging is a back-end activity, it still requires complex techniques like etching, lithography, hybrid bonding, and many other steps and tools used in logic production. This explains why HBM testing and packaging facilities are larger than typical back-end facilities.

Nonetheless, HBM packaging is inherently simpler than producing logic, so the scale of SK hynix's P&T7 plant is enormous, even by HBM standards. Its dimensions and investments dwarf SK hynix's HBM testing and assembly plant in West Lafayette, Indiana, which will cost the memory maker $4 billion and will span 39,948 square meters. Yet, keeping in mind that SK hynix expects the compound annual growth rate (CAGR) of HBM to be 33% from 2025 to 2030, it needs all the front-end DRAM and back-end packaging facilities it can build.

A strategic location

A key element of the project is its operational linkage with Fab M15X, a major SK hynix semiconductor manufacturing facility currently located in Cheongju that is currently being equipped with fab tools. The company expects the combined operation of M15X and P&T7 to create a tightly coupled manufacturing ecosystem capable of building HBM dies (which are three to four times larger than commodity DDR5). Therefore, SK hynix can test and package HBM in close proximity, essentially creating a vertically integrated manufacturing facility for HBM or other exotic types of memory that use multi-chip packaging.

The adjacency of Fab M15X and P&T7 is intended to elevate Cheongju into a new core base for SK hynix's AI memory operations, which will optimize production and packaging and can potentially enable the company to respond to market demand for HBM faster than it can today.

As a bonus, the close proximity of the front-end memory fab and the advanced packaging and testing facility will shorten feedback loops between engineers at both facilities, which might positively affect yields and/or performance. In fact, as the industry transits to more sophisticated types of memory for AI accelerators — such as HBM4 with a 2,048-bit interface — the bigger and more sophisticated assembly and testing plants for high-bandwidth memory located close to front-end DRAM fabs make sense.

From a strategic planning perspective, SK hynix says it had evaluated multiple domestic and international locations before selecting Cheongju for P&T7. The decision reflects multiple objectives. Firstly, the vast majority of SK hynix's memory is produced in South Korea, so it is reasonable to build its most advanced testing and packaging facility for AI DRAM nearby. Secondly, P&T7 working in proximity with M15X will reinforce the overall competitiveness of South Korea's semiconductor industry. Thirdly, a large project also supports regional development, a policy promoted by the government.

SK hynix notes that the site selection decision was not purely cost-driven; the company evaluated proximity to existing fabs, infrastructure readiness, and long-term supply-chain resilience. Cheongju was ultimately chosen as the location that balanced industrial efficiency best.

Although SK hynix never mentions it, there is one more factor that likely affected its decision to build its biggest HBM packaging facility in South Korea. Because the vast majority of AI accelerators are made in the region, not only in South Korea, but in Taiwan by TSMC.

Since SK hynix and TSMC share a lot of customers, the two companies work closely with one another. However, due to geopolitical and regional competitive reasons, SK hynix isn't likely to build a major facility in Taiwan, making South Korea the next-best option.

Technological importance

Building an extremely big HBM testing and packaging facility is important for SK hynix, not only from strategic and logistical points of view, but also from a technology development point of view.

Advanced packaging is as critical to HBM as the DRAM front-end fab because of HBM's inherent characteristics — extreme bandwidth, power efficiency, and density. These elements are enabled by the DRAM itself and packaging technology. A single DRAM die does not expose a 1,024-bit or 2,048-bit interface: it's enabled by stacking 8 – 16 dies, each featuring a 128-bit I/O, interconnected with Through Silicon Vias (TSVs), and routed through base dies and Redistribution layers (RDLs). To make everything work properly and according to specification, packaging must ensure bonding accuracy, optimal TSV resistance, and RDL integrity.

Power efficiency and thermals are also largely determined by packaging, as they define things like TSV and RDL parasitics, micro-bump or hybrid-bond quality, and interposer losses. Some packaging technologies have increased I/O voltage requirements and higher switching losses, which force manufacturers to reduce data transfer rates compared to offerings from their rivals.

Heat-extraction is also a big deal, and it entirely depends on packaging process technology (underfill and mold materials, as well as package-level thermal paths), as the better heat dissipation is between memory dies, the easier it is to cool the whole stack. SK hynix leads the industry with its mass reflow-molded underfill (MR-MUF).

Yield economics also increase the importance of packaging technology: even if a front-end DRAM fab achieves a 99% good die yield, if yield loss during packaging is significant (due to TSV defects, bond misalignment, and/or RDL defects), it hits margins across both the expensive DRAM fab and relatively inexpensive back-end packaging facility. Reliability qualification — burn-in, thermal cycling, and long-duration stress testing — is also performed at the package level and cannot be handled by generic back-end lines.

As HBM scales toward more dies per stack, wider interfaces, tighter pitches, and hybrid bonding, packaging complexity and costs of packaging and testing facilities will rise to logic-fab-class levels, which is probably what we are dealing with here.

Eventually, advanced packaging facilities — which already have costs similar to logic fabs from 2010 to 2015 — will become considerably more expensive, and DRAM makers will have to be willing to spend $20 billion or more on such facilities, as this will be the only way to enhance the bandwidth, efficiency, yields, and reliability of HBM memory going forward.

Packaging is a crucial process

Although HBM packaging is a back-end process, its reliance on lithography, etching, hybrid bonding, and other steps common in front-end fabs explains the cost of modern packaging facilities like logic fabs from the previous decade. Furthermore, increasingly complex next-generation types of HBM, starting from HBM4 and onwards, will encourage memory makers to build facilities like P&T7 costing tens of billions of dollars and located adjacent to DRAM fabs.

Avid readers of Tom’s Hardware have read a lot about the upcoming HBM4 and GDDR6 memory technologies, but as neither is used on mass production devices, few of us get to see actual HBM4 and GDDR6 memory packages. Good news, SK Hynix demonstrated them at CES, and our own Matt Safford has managed to grab some pictures.

SK Hynix demonstrated the industry’s first 16-Hi HBM4 memory package at the trade show, highlighting both the density that could not be achieved without its MR-MUF molding technology as well as HBM4’s 2,048-bit interface. SK hynix's HBM4 memory stacks are said to operate at 10 GT/s, which is 25% faster than the official JEDEC specification. Meanwhile, adopters like Nvidia want to have headroom for both extra performance in scale-up deployments (if customers are willing to) and for performance efficiency in hyperscaler applications.

HBM3/HBM3E and HBM4 share the same ~10.5 × 12.0 mm footprint, but HBM4 allows taller stacks — up to ~950 µm for 16-Hi versus ~750 µm for 12-Hi HBM3 — while packing far denser I/O and power bumps. When it comes to packaging, the company continues with its advanced mass Reflow molded underfill (MR-MUF) approach: multiple memory dies are mounted on a base substrate and bonded in a single reflow step, then encapsulated with mold material between DRAM layers, the base die, and the substrate.

Looking at the backsides of HBM4 and HBM3E, the difference between them becomes obvious, even taking the general pin count aside. HBM3E and HBM4 feature the same dimensions/footprint, so the backside indeed shows a much denser and more uniformly packed BGA pin field with noticeably higher bump density across the entire footprint. This is not particularly surprising as the jump from a 1,024 to a 2,048-bit I/O takes its obvious toll and requires substantially more signal bumps as well as additional power and ground pins to support higher bandwidth and tighter signal integrity margins. By contrast, HBM3E's backside has a sparser bump layout with more visible separation between regions, which is consistent with its 1,024-bit interface and lower aggregate I/O demand.

Meanwhile, HBM4's power delivery and ground contacts are also visibly different compared to the less advanced type of memory. Perhaps HBM4 allocates a larger fraction of its backside area to power and ground bumps; they are arranged more evenly across the package, something that could reduce noise and IR drop at data rates that are as high as 8 GT/s per standard or 10 GTs, given the listed capability.

Yet, we may be speculating here purely based on the fact that HBM3E features fewer power pins and shows clearer zoning between I/O and power regions. In fact, even without precise specs, the backside alone shows that HBM4 is designed for much higher I/O bandwidth and power delivery requirements.

In any case, these HBM4 modules use custom DRAM dies manufactured on the proven 1b-nm (5th-generation 10-nm-class) process to wed a large DRAM die with low defect density, reduced variability, and eventually high yield, something that makes them cheaper, yet it is hard to estimate how that lower cost could translate to the end user.

Sandisk is on track to double the price of its high-capacity 3D NAND memory devices for enterprise-grade solid-state drives this quarter in anticipation of strong demand for server-class storage in the coming quarters, reports Nomura Securities (via @jukan05). It is unclear to what degree the price increase of high-capacity 3D NAND will affect quotes on mainstream flash memory used in client devices, but normally, 3D NAND for smartphones and PCs follows enterprise-grade chips as they are made at the same fabs.

"Channel checks indicate that several memory suppliers continued to push prices higher, with enterprise-grade NAND facing especially aggressive increases," a note to clients by Nomura Securities reads. "SanDisk’s NAND used in enterprise SSDs is cited as potentially rising by more than 100% quarter over quarter in the March period."

Nomura Securities, which is among the prominent financial analyst firms with good contacts in the high-tech industry, attributes plans of memory suppliers to increase prices of enterprise-grade 3D NAND both to short-term shortages and to mid-term growth of demand driven by AI in general and changes to AI storage in particular.

Nomura names Nvidia's Inference Context Memory Storage Platform (ICMSP) — which is based on the BlueField-4 DPU equipped with a 512 GB SSD that carries KV cache — among the demand drivers for enterprise storage this year. Every compute tray in the VR NVL144 rack is equipped with a BlueField-4 data processing unit with a 512 GB drive, making it 18 DPUs with 9.216 TB of 3D NAND per rack. Assuming that Nvidia ships 50,000 VR NVL144 racks per annum, the company will have to get roughly 0.439 EB of 3D NAND somewhere. Its partners supplying their versions of VR NVL144 racks with BlueField-4 DPUs will also increase their consumption of 3D NAND memory this year with the Vera Rubin platform.

While Nvidia's ICMSP can consume around an exabyte of 3D NAND per annum in 2026 ~ 2027 in the best case scenario, it cannot really be a reason for 3D NAND price doubling overnight, as the industry produces over 800 EB of NAND every year. Meanwhile, we still do not know how much 3D NAND a typical VR NVL144 machine carries, so we cannot estimate storage demands for Rubin-based platforms in general.

Nonetheless, as demand for AI systems for storage is skyrocketing in general, they will inevitably drive up demand, and once it outpaces supply, prices will get higher, which is exactly what we are seeing today.

The U.S. Department of Commerce has issued a permit to Taiwan Semiconductor Manufacturing Company (TSMC) to import U.S.-made chip-making equipment into China for its Nanjing fab. According to Reuters, Samsung and SK hynix were also given import licenses to bring in specialized equipment that used American-made components into their Chinese factories. These three chipmakers used to enjoy validated end-user status, meaning they could freely import restricted items into China without asking for individual licenses. However, this privilege has expired at the end of 2025, meaning they now have to seek annual approval from Washington, D.C., to continue receiving advanced tools.

“The U.S. Department of Commerce has granted TSMC Nanjing an annual export license that allows U.S. export-controlled items to be supplied to TSMC Nanjing without the need for individual vendor licenses,” the company said in a statement to Reuters. It also said that this “ensures uninterrupted fab operations and product deliveries.” This move to require annual licenses for the Chinese factories of these chipmakers is a part of the White House’s effort to keep advanced chipmaking tools out of China.

Beijing has been working hard to achieve “semiconductor sovereignty,” just as the U.S. has been trying hard to prevent it from acquiring the latest chips. Aside from that, ASML, the only manufacturer of cutting-edge chipmaking tools, has been banned from exporting its products to China and servicing those that are already installed. Because of this, we’ve seen reports that the country is covertly working on reverse engineering EUV lithography tools, and that it has even come up with a “Frankenstein” EUV chipmaking tool, but has yet to produce a single chip.

The U.S. does not allow EUV lithography machines with U.S. technology to be exported to China, even to companies like TSMC and Samsung that have Chinese factories. This means that these fabs are only limited to mature nodes of 16-nm and up. The revocation of the validated end-user status for the China-based fabs of these companies shows that Washington is tightening its grip on chipmaking machines, even older DUV tech, to make it difficult for Beijing to create its own technology.

Despite this, the East Asian nation is pushing hard to develop its own equipment. The central government has even told its chipmakers to use homegrown tools for half of new capacity. And while the country is still years behind cutting-edge tech from ASML and other Western companies, it’s slowly taking steps in the right direction.

SK hynix is bringing its HBM ambitions to U.S. soil with a $3.9 billion plan to build its first domestic manufacturing facility — a 2.5D advanced packaging plant in West Lafayette, Indiana. The site, developed in partnership with Purdue University, is aimed at producing turnkey HBM modules for AI accelerators by 2028.

In bringing manufacturing to the U.S., SK hynix aims to vertically integrate its HBM supply chain, which currently relies on outside firms, to handle the delicate process of mounting HBM stacks to logic dies via interposers. That assembly work is increasingly a bottleneck for high-end GPUs, especially as demand for AI silicon continues to outstrip available packaging capacity. By owning both the memory and the interconnects, the company is clearly trying to target the kind of leverage that TSMC holds over the likes of Nvidia.

The Indiana facility, which is partially funded by $458 million in CHIPS Act grants and loans, is SK hynix’s first U.S. production site and part of a broader effort to bring critical semiconductor infrastructure closer to U.S. customers. It comes alongside the company’s new R&D outpost near Seattle, built in part to deepen ties with Nvidia and other domestic hyperscalers. When complete, the plant will package HBM chips with silicon interposers and integrate them with partner dies into a single, thermally optimized 2.5D module ready for use in AI servers or supercomputing clusters.

According to filings, SK hynix plans to operate a full mass-production line at the site, supported by a dedicated talent pipeline from Purdue. That puts it in direct competition with TSMC’s CoWoS platform, which has been the de facto standard for high-end HBM packaging since Nvidia’s Pascal era. And with TSMC’s CoWoS capacity effectively sold out through 2027, customers are already searching for alternatives.

Turnkey HBM

The biggest problem with HBM is that it’s a packaging challenge. HBM stacks multiple memory dies vertically using through-silicon vias (TSVs), all of which must be mounted on a large interposer next to a host processor. That assembly must account for thermal expansion, routing complexity, and thousands of microbumps, resulting in a tightly coupled chiplet module with massive I/O bandwidth and low power draw, ideal for AI training or HPC workloads.

Until now, HBM suppliers like SK hynix and Samsung have typically sold raw memory stacks, leaving GPU vendors to rely on foundry partners for packaging. Nvidia’s H100 and AMD’s MI300X, for instance, use HBM2e and HBM3 mounted via TSMC’s CoWoS process. But with demand for accelerators reaching historic highs — and HBM4 promising even more aggressive stack designs — the need for in-house packaging has become a priority.

SK hynix’s stated goal is to deliver a “turnkey” solution: HBM stacks already integrated with silicon interposers and, potentially, host dies from customers. That would allow hyperscalers or chip designers to skip TSMC entirely for final assembly, receiving ready-to-mount modules instead. It’s a fundamental shift in how HBM enters the supply chain, positioning SK hynix as a full-stack supplier rather than a component vendor.

This type of setup already has some precedent. TSMC has steadily expanded its role from foundry to integrator over the past decade, using its packaging platforms (CoWoS, InFO, SoIC) to create customer lock-in beyond wafer fabrication. SK hynix has obviously drawn inspiration from that playbook, starting from memory and working outward. It also places pressure on Samsung, which is reportedly evaluating its own U.S. packaging line to support future Tesla and AMD accelerator deployments.

The timing of all this is no accident. HBM demand is projected to be worth tens of billions by 2030, driven by AI model scaling and architectural shifts toward high-bandwidth chiplets. Nvidia’s Rubin platform — expected to launch late 2026 — will reportedly use HBM4E stacks with bandwidth over 1.2TB/s per module. That’s not achievable with standard memory interfaces or traditional DRAM. If SK hynix can offer a high-yield, pre-packaged solution at scale, it could become indispensable to Nvidia, AMD, and a whole host of other companies.

A national security priority

Advanced packaging has become a national security and industrial policy priority, and Washington is funding it accordingly. The Commerce Department’s CHIPS for America program set aside about $3 billion for the National Advanced Packaging Manufacturing Program to expand U.S. advanced packaging R&D and manufacturing capacity under the Biden administration in 2023, which remains under the incumbent Trump administration.

While TSMC and Intel have U.S. fabs in Arizona and Ohio, neither currently offers high-volume 2.5D packaging on U.S. soil. SK hynix's Indiana site will be the first to do so, and potentially the only one with dedicated capacity for third-party AI customers.

See, packaging isn't just about putting chips together; it determines yield, thermals, and even chip performance. Interposer routing, power distribution, and heat dissipation can make or break an accelerator, so by integrating packaging with memory production, SK hynix gains tighter control over thermal budgets and mechanical tolerances, reducing failure rates in multi-die modules. And by keeping the entire process in the U.S., it aligns with growing customer pressure to onshore AI supply chains.

TSMC is responding in kind, expediting its own Arizona-based packaging line with a target completion window of late 2027. But TSMC’s U.S. capacity is largely reserved for captive customers and its own Arizona wafer output. That leaves a vacuum for customers seeking independent packaging partners. SK hynix could fill that role, especially if its turnkey model proves more predictable than the fragmented flow of wafers and memory stacks across the Pacific.

This isn’t just about fabs versus packages, but rather, where the AI supply chain converges. The raw silicon may still come from Korea or Taiwan, but the modules that power large language models, scientific simulations, and autonomous workloads will increasingly be built where the compute is deployed. And if SK hynix succeeds, it won’t be the last memory maker to cross the packaging threshold.

Micron has already announced plans to co-locate HBM packaging at its Virginia site. Meanwhile, Samsung is in talks with U.S. partners, and Intel is integrating Foveros with its own internal chiplets. But with a turnkey HBM solution provided via a 2.5D packaging plant in the U.S., SK hynix could easily take the lead.

The U.S. government has approved annual export licenses allowing Samsung Electronics and SK hynix to ship chipmaking equipment to their manufacturing facilities in China throughout 2026, according to people familiar with the decision cited by Reuters. The approvals arrive just one day before a long-standing waiver system expires on December 31, forcing foreign-owned fabs in China onto a more restrictive licensing framework.

Under the previous regime, Samsung, SK hynix, and TSMC benefited from so-called validated end-user status, which allowed qualifying factories in China to receive U.S.-controlled semiconductor tools without seeking individual export licenses for each shipment. That status will lapse on December 31, after which shipments of U.S.-origin manufacturing equipment require explicit authorization from Washington.

The newly granted licenses cover Samsung and SK hynix for the calendar year 2026 and are issued on an annual basis. One source told Reuters that Washington has formally moved to this annual approval system for chipmaking tool exports into China, replacing what U.S. officials had increasingly viewed as overly permissive waivers inherited from earlier policy decisions.

These approvals are critical for both South Korean giants because China remains at the core of their memory production businesses. Samsung operates its large NAND flash facility in Xi’an, while SK hynix runs a major DRAM fab in Wuxi and a NAND plant in Dalian. Collectively, those sites account for a substantial share of global memory output, particularly for mature-node DRAM and NAND products. And because memory pricing has risen sharply over the past year as AI data center demand tightened supply, this has only increased the operational importance of keeping fabs running smoothly, regardless of where they are.

It’s understood that the annual licenses under the new scheme are designed to allow continued operation and maintenance rather than unrestricted expansion. U.S. officials have repeatedly said that export controls are intended to prevent China from accessing advanced manufacturing capabilities; even under the old system, the most sensitive tools, including EUV, remained off-limits.

At the same time, the shift to yearly approvals introduces a new layer of uncertainty for chipmakers. Each renewal gives the U.S. leverage to adjust conditions or withhold approvals altogether, depending on the broader trade and national security climate. It has been speculated that U.S. officials expected the tighter framework to weigh on sales for American toolmakers such as Applied Materials, Lam Research, and KLA, which supply a wide range of systems used in memory fabs, such as etch and deposition.

For now, the approvals ensure that both companies can continue importing essential manufacturing equipment into China in 2026, even as Washington looks to change how closely those flows are scrutinized year by year.

SK hynix is expanding its U.S. presence with a new office in the Seattle metropolitan area, placing the world’s leading HBM supplier within minutes of Nvidia, Amazon, and Microsoft.

According to industry sources cited by DigiTimes, the South Korean company has leased approximately 5,500 square feet at City Center Bellevue, just east of Seattle. While modest in size, the location and timing make the expansion far more consequential than a routine regional office opening.

SK hynix is sitting squarely in the middle of the ongoing AI hardware boom, supplying the majority of the HBM used in Nvidia’s data center accelerators and increasingly serving hyperscale customers building their own AI silicon. Establishing a physical foothold in the Pacific Northwest puts the company closer to the customers driving its fastest-growing and most important business.

Moving closer to the center of AI development

SK hynix has spent the past two years transforming itself from a cyclical commodity DRAM vendor into a leading supplier for AI infrastructure. That's visible in High Bandwidth Memory (HBM), where SK hynix was first to mass-produce HBM3 and has remained ahead in yield and volume as customers transitioned from HBM2E. In August 2025, the company overtook Samsung in global DRAM revenue for the first time, a change largely attributed to HBM shipments for Nvidia’s H100 and H200 AI accelerators.

Seattle and its surrounding suburbs have become one of the densest concentrations of the AI industry ecosystem outside of Silicon Valley. While Nvidia maintains a significant engineering presence in the region, Amazon’s AWS Skills Center is based nearby, and Microsoft’s Azure silicon and systems groups are spread across Redmond and Bellevue.

HBM is not a plug-and-play component. Memory stacks are co-designed with GPUs and AI accelerators, and performance, power, and reliability targets are refined through repeated cycles of joint validation. Physical proximity will allow faster iteration when issues arise, whether related to signal integrity, thermals, or packaging tolerances.

Amazon’s recent launch of its Trainium3 AI accelerator, which integrates 144GB of HBM3E, shows how quickly hyperscalers are increasing their reliance on stacked memory. Microsoft and Google are following similar paths with custom accelerators. Each of those programs depends on close coordination between the silicon designer and the memory supplier; a Seattle-area office gives SK hynix a seat at that table.

Broader U.S. localization

The Bellevue office also fits into a wider U.S. expansion that extends beyond customer support. In 2024, SK hynix announced plans for a $4 billion advanced packaging facility in Indiana, its first manufacturing investment in the United States. That site is intended to handle advanced HBM packaging and testing, with production targeted for 2028. While the Indiana project focuses on manufacturing, it appears the Seattle office will be oriented toward R&D, applications engineering, and customer engagement.

Taken together, these moves suggest SK hynix is deliberately localizing more of its AI-related operations in the U.S., where the bulk of demand is being generated. Advanced packaging has become as important as wafer fabrication for AI accelerators, and the ability to package memory near customers reduces both logistical complexity and geopolitical risk. It also aligns with U.S. industrial policy aimed at securing domestic supply chains for critical technologies.

There has been periodic speculation that SK hynix could eventually build a full DRAM fab in North America, though the company has not committed publicly to such a plan. Even without a fab, expanding engineering and packaging capabilities in the U.S. strengthens SK hynix’s position with American customers at a time when memory supply is extremely tight, thereby making long-term capacity planning a competitive differentiator.

The race to HBM4

SK hynix’s Seattle expansion also reflects intensifying competition in the HBM market. Samsung remains a formidable rival with deep manufacturing resources and its own U.S. investments, including advanced packaging capacity tied to its Texas operations. Micron, the sole U.S.-based DRAM manufacturer, is pursuing high-end server and automotive markets and sampling its own HBM4 designs, though its near-term capacity expansion is more constrained.

Meanwhile, SK hynix has already completed development of HBM4 and is understood to have delivered samples to Nvidia. Early engagement is particularly important with HBM4 because the transition involves higher stack counts, tighter power budgets, and more complex thermal challenges. Winning those designs early could easily lock in multi-year supply relationships.

Ultimately, with its Seattle expansion, SK hynix is telling Samsung and Micron that it intends to be embedded in the AI ecosystems of its largest customers rather than a distant component supplier. Being physically close to Nvidia and Amazon’s engineering teams during the transition to HBM4 will greatly improve the company’s odds of maintaining its lead, while also supporting adjacent efforts such as joint work with Nvidia on AI-optimized SSDs.

As we detailed in October, the memory and storage markets were expected to face significant supply constraints. In the months following, DDR5 prices have skyrocketed. Kits that had sold comfortably below $100 months earlier were surging into the hundreds by early December. CyberPowerPC, one of the largest system builders in North America, warned in November that contract DRAM prices had jumped 500% since early October, while another report indicated that they had risen 171.8% year over year.

The disruption is being driven not by demand from gamers or device makers, but by artificial intelligence. Specifically, by the way hyperscalers are soaking up wafer starts and advanced packaging lines for high-bandwidth memory (HBM) used in AI accelerators.

The consequence is that anyone or anything that’s not part of that ecosystem — PC builders, laptop OEMs, and even phone makers — is fighting over the scraps of a shrinking pool of commodity DRAM. And with new fabs still years from coming online, the shortage is expected to last well into the second half of the decade.

RAM kits up 2-4x in a quarter

The most visible impact can be seen with retailers. A Corsair Vengeance DDR5-6000 32GB (2x16GB) cost $134.99 in September before reaching more than $420 in early December. G.Skill, TeamGroup, and Kingston all adjusted channel pricing by double digits across Q3, citing tightening availability.

That translated to a whopping 2-4x price swing for enthusiasts buying RAM, depending on capacity and bin. The G. Skill Trident Z5 Neo RGB DDR5-6000, our tried-and-tested best RAM for gaming, is now only available via third-party sellers through Amazon, with 64GB kits attracting prices beyond $500, with one seller listing them for a whopping $881.87 as of December 18.

Suppliers and distributors have sharply tightened allocation of DDR5 memory, with some channel partners reporting severely limited quotes and rollovers on orders as capacity is diverted to AI-driven demand. Reports from Taiwan and broader market tracking show memory modules selling out or being bundled to secure placement, indicating that mainstream buyers are being deprioritized.

That squeeze quickly filtered into GPUs, where memory is a major cost driver. AMD board partners raised card prices by around $10 per 8GB of VRAM starting in November. A rumor suggests AMD could increase Radeon RX graphics card prices with 8 GB models up by about $20 and 16 GB models up by about $40 in response to climbing GDDR6 spot prices and memory costs. SSD pricing has also reversed direction. 2TB Gen 4 NVMe drives that had been available for $80 in the summer were back at $130 by November. Contract pricing on NAND rose 60% in November, and module-level spot prices followed.

Framework was forced to increase its pricing on the DDR5 memory configurable in Framework Laptop DIY Edition orders by 50% in response to “substantially higher costs” they are facing from suppliers and distributors. Meanwhile, Dell and HP have both flagged component pricing, with HP’s CEO stating that memory costs in particular were affecting margin on consumer systems and Dell COO Jeff Clarke saying he’s “never seen memory-chip costs rise this fast.” Raspberry Pi also raised prices on its 4GB and 8GB boards, citing supply constraints on LPDDR4X.

Starving the market

All this is not being caused by insufficient demand for DDR5, but by wafer and packaging capacity being redirected to high-margin, high-volume AI parts. High Bandwidth Memory (HBM) is the main pressure point.

HBM differs from conventional DRAM in both structure and cost. Instead of planar dies mounted on PCBs, HBM stacks multiple DRAM dies vertically, linked with through-silicon vias (TSVs), and mounts them on an interposer alongside compute logic. These stacks offer enormous bandwidth and proximity advantages for AI accelerators, but they are incredibly expensive in terms of materials, tooling requirements, and especially wafer area.

Each gigabyte of HBM consumes roughly three times the wafer capacity of DDR5. That reflects both yield loss from stacking and the fact that many DRAM dies in HBM stacks are smaller or binned lower than equivalent RAM sticks. The TSV process and wafer thinning introduce additional steps that lengthen production cycles, leading to a catch-22 situation that, even when yields are strong, means the vertical integration of HBM requires advanced packaging lines that remain globally scarce.

SK hynix, the largest supplier of HBM to Nvidia, has told investors that its advanced packaging lines are at capacity through 2026. Micron, which supplies HBM3E to Nvidia and other U.S. clients, is in a similar position. Samsung has HBM capacity reserved through its Foundry and Memory business lines for tier-1 cloud clients. These lines are not interchangeable with conventional DRAM; tools, masks, and equipment for HBM production occupy space that would otherwise produce DDR5 or LPDDR5.

With wafer starts flat and packaging lines locked, every wafer pushed into HBM removes capacity from commodity DRAM and NAND. And the volume committed to AI is enormous.

The Stargate effect

In July, OpenAI and Microsoft finalized plans for Project Stargate, a multi-site hyperscale AI infrastructure program, with Samsung and SK hynix together committing to up to 900,000 DRAM wafer starts per month to support the buildout “at an accelerated capacity,” according to OpenAI.

That deal alone represents roughly 35-40% of global DRAM wafer capacity. The wafers will be used not just for HBM stacks, but for LPDDR and ECC DRAM used in adjacent server memory. Nvidia has its own multi-year agreements in place, reportedly accounting for the majority of SK hynix's HBM output through 2026. These allocations are inflexible, with contracts fixed, volumes tiered, and, in many cases, wafers fronted at favorable prices in exchange for capacity guarantees.

Naturally, memory vendors are reaping the rewards. Micron posted a record $11.3 billion quarter in Q4 2025, driven by HBM and enterprise DRAM margins. It subsequently announced plans to exit the Crucial consumer brand by early 2026. Executives stated that winding down Crucial would free up wafer supply for strategic accounts. “The AI-driven growth in the data center has led to a surge in demand for memory and storage. Micron has made the difficult decision to exit the Crucial consumer business... to improve supply and support for our larger, strategic customers in faster-growing segments,” said Sumit Sadana, EVP and Chief Business Officer.

Meanwhile, Samsung has raised its memory chip prices by up to 60% since September, driven almost entirely by the high demand for building new AI-focused data centers.

No new fabs until 2027

Memory makers are responding to surging demand by building new fabs, but the leadtime on greenfield facilities is long, and — of course — virtually all capex is going to go to HBM lines first, because that’s where the money is. Among the most notable investments is Micron’s $9.6 billion Hiroshima HBM facility, announced in partnership with the Japanese government. Construction of this fab is expected to begin around May 2026, with its first output expected in 2028.

Samsung is also committing billions in investments to new DRAM capacity in Pyeongtaek and Taylor, Texas. These sites will include HBM packaging and DRAM wafer lines, but company executives have cautioned that HBM and high-margin enterprise DRAM will receive priority through 2027. The company recently accelerated Phase 4 of its Pyeongtaek expansion in a renewed effort to reclaim leadership in the AI memory space. As for SK hynix, it’s expanding in Icheon — where it was the first memory maker to assemble ASML’s High-NA EUV lithography system — and Cheongju, with new DRAM output slated for 2026-2027.

Unfortunately, there’s no sign of the DRAM supply shortfall easing up before 2027. TrendForce has cautioned time and time again that capacity growth is limited relative to demand as AI and server requirements absorb a disproportionate share of wafer starts and production resources, and its pricing outlook shows DRAM contract rates continuing to rise through 2026 with constrained supply conditions. A leaked SK hynix internal analysis forecasts PC DRAM supply trailing demand until at least late 2028, and general industry consensus is that meaningful relief for DDR5 and LPDDR5 supply — at prices suitable for consumer SKUs — will not come until 2028 or 2029 at the earliest.

The situation is similar for NAND, with wafer investment having lagged since the 2022 price collapse. Most new NAND lines being built now are intended for enterprise SSDs or embedded memory for AI accelerators; client SSDs will see higher costs and tighter supply through 2026.

Consumers are now an afterthought

The effects of this reallocation are already locked into the next generation of consumer hardware, because memory decisions are made years in advance. Laptop platforms shipping in 2026 and 2027 are being finalized now, at a moment when DRAM and NAND supply are both constrained and volatile. That will have consequences that go beyond pricing.

Memory configurations that require large, predictable allocations of DRAM are riskier in a market where suppliers are prioritizing AI contracts and spot pricing can move sharply month to month. These conditions favor fewer SKUs and longer reuse of validated configurations rather than aggressive spec increases. Meanwhile, DDR4, which was expected to fade out quickly after DDR5 adoption ramped, is now likely to persist far longer in entry-level and midrange systems simply because its supply chain is more stable.

GPUs are in a similar bind. GDDR6 and GDDR6X, while not interchangeable with HBM, compete for wafer capacity and backend resources at the same suppliers. That makes large VRAM increases expensive at exactly the moment when software requirements are rising. This won’t necessarily mean fewer GPUs, but it could lead to slower movement at the top end of memory configurations, with vendors prioritizing yield and availability over aggressive capacity scaling.

NAND is under comparable pressure as investment in new client-focused capacity slowed down after oversupply and subsequent pricing collapse in 2022. What capacity is coming online is disproportionately aimed at enterprise SSDs and embedded storage tied to accelerators, where margins are higher, and contracts are longer. That leaves consumer SSDs exposed to price swings and supply tightening, particularly at higher capacities, even as PCIe generations continue to advance.

The problem is that none of these pressures are transient shocks that can clear in a quarter or two. The fabs that would meaningfully expand DRAM and NAND supply are not scheduled to come online until 2027 at the earliest, and even then, priority will remain with HBM and enterprise products. Consumer markets are now an afterthought among memory makers and, given the current state of AI, it’s difficult to see that changing.

SK hynix on Thursday said that its range-topping 256 GB DDR5 RDIMM based on 32 Gb memory devices has passed the Intel Data Center Certified process, the industry's first memory module at this capacity to do so. Normally, certification of a memory module by Intel would be mundane, but this module is special; it combines capacity, low power consumption, and performance, thus potentially saving data center operators millions of dollars.

AI servers not only consume plenty of premium high-bandwidth memory (HBM) used on AI accelerators like Nvidia B300, but also tons of commodity server DDR5 SDRAM that connect to x86 processors. A single high-capacity DDR5 memory module can consume up to 15W or even 25W (depending on performance, capabilities, and workloads), so a fully equipped 12-channel Xeon 6 memory subsystem can draw between 180W and 300W, comparable to the CPU's power consumption.

A 32 Gb memory chip made on SK hynix's 1b process technology (5^th Generation 10nm-class DRAM process) consumes significantly less power than two 16 Gb memory ICs made on the company's 1a production node (4^th Generation 10nm-class DRAM node), so using a 256 GB DDR5 RDIMM based on the latest DRAMs leads to significant energy savings.

SK hynix claims that these new 256 GB DDR5 RDIMMs "achieve up to approximately 18% lower power consumption than previous 256 GB products."

Offering 32.4W lower power consumption per single-CPU Xeon 6 machine translates into significant savings for modern AI or hyperscale cloud deployments that typically use tens of thousands of machines.

As a result, a relatively simple Intel certification to earn the Intel Data Center Certified badge could drive success for SK hynix in the data center market, particularly in the Xeon 6-based AI server space.

"We are now able to respond more swiftly to customer needs, solidifying our leadership in the server DDR5 DRAM market," said Sangkwon Lee, head of DRAM Product Planning & Enablement at SK hynix. "As a full-stack AI memory creator, we will actively address the growing demand for high-performance, low-power, and high-capacity memory solutions to further enhance customer satisfaction."

A growing body of forecasts from AMD, Nvidia, Broadcom, and major research firms now points toward a semiconductor market that passes the trillion-dollar threshold before the decade closes, driven by an AI infrastructure buildout several times larger than any previous expansion in the industry’s history.

New analysis from Creative Strategies is calling this shift a "giga cycle," arguing that the unprecedented scale of AI demand is restructuring the economics of compute, memory, networking, and storage simultaneously. Global semiconductor revenue was roughly $650 billion in 2024, yet multiple outlooks now place the trillion-dollar mark in 2028 or 2029. AI is responsible for most of that upward revision.

AMD CEO Lisa Su recently lifted the company’s own long-term expectations, describing the AI hardware market as a $1 trillion opportunity by 2030 while projecting 35% compound annual growth for AMD overall and around 60% for its data-center business. She also spoke out against AI bubble talks that have dominated in recent months.

Meanwhile, Nvidia has set even broader expectations, describing the coming five years as a $3 trillion to $4 trillion AI infrastructure opportunity during the company’s Q2 2026 earnings call. This figure is based on system-level deployments across hyperscalers, sovereign AI projects, and enterprise clusters.

The broader implication is that every major category of silicon is expanding at once. Creative Strategies expects data-processing silicon to exceed half of total semiconductor revenue by 2026. AI accelerators, which accounted for under $100 billion in 2024, are projected to reach the $300 billion to $350 billion range by 2029 or 2030. That growth pushes system spending sharply higher. The AI server market is forecast to climb from about $140 billion in 2024 to as much as $850 billion by 2030, a trajectory that will reshape chip demand even before accounting for custom silicon.

This environment has elevated ASIC development to a central role in hyperscaler roadmaps. Broadcom expects its custom-silicon business to exceed $100 billion by decade’s end. The company has already disclosed a $10 billion AI infrastructure order from a customer thought to be OpenAI.

Memory and packaging remain the tightest constraints. HBM revenue is forecast to grow from roughly $16 billion in 2024 to more than $100 billion by 2030. Each HBM generation consumes a larger share of wafer supply than conventional DRAM, pushing the broader memory market upward as AI clusters scale. Advanced packaging faces similar pressure as CoWoS capacity is projected to expand by more than 60% from the end of 2025 to the end of 2026.

"The defining characteristic of the semiconductor giga cycle is that the market expansion is large enough to create greenfield opportunities across every segment of the value chain," says Creative Strategies, presenting the combined effect as a moment where every segment is growing in unison rather than a cycle concentrated in any particular area.

The ongoing structural change of the DRAM market caused by the shift of manufacturing capacities to production of high bandwidth memory (HBM) for AI accelerators has already caused a massive price hike of commodity DDR and LPDDR memory — but the worst is yet to come.

According to the general manager of Chinese memory giant TeamGroup, contract prices of DRAM and NAND products have almost doubled recently. Supply of commodity memory is set to worsen in early 2026, and normalization is unlikely before 2027 – 2028 when more production capacity emerges, reports DigiTimes.

December contract prices of some categories of DRAM and 3D NAND increased 80% to 100% month-on-month, according to Gerry Chen, general manager of TeamGroup, a prominent maker of memory modules, solid-state drives, and products based on 3D NAND. Spot prices tell a similar story. A 16Gb DDR5 chip was priced at $6.84 on average at DRAMeXchange on September 20. On November 19 average spot price was $24.83, but on December 1 average spot price of a 16 Gb DDR5 IC increased to $27.2 (session low was $19, session high was $37).

Essentially, memory alone for a 16 GB memory module costs around $217.6. A PCB, assembly, and testing, additional parts like PMIC will add $8 – $10, so a 16 GB memory module now costs $225 – $228 without manufacturer premiums, logistics, and taxes.

Chen expects availability of DRAM and NAND to worsen in the first and second quarters of 2026 once distribution stockpiles are exhausted. At that point, he cautions, obtaining allocation could become difficult regardless of willingness to pay. In his view, relief would not come quickly: he projects the current shortages to extend into late 2027 and potentially beyond.

The reason for shortages of commodity memory is well known: DRAM makers reallocate their production capacities to HBM (which uses larger DRAM dies than commodity types of memory) that is consumed by AI accelerators, like Nvidia's B300 or custom accelerators by large cloud service providers, such as AWS, Google, and Microsoft. These companies tend to book supply years in advance, so at some point, DRAM makers will not have enough capacity to meet demand for commodity DRAMs.

Building a new greenfield fab takes at least three years, so even if companies like Micron, Samsung, or SK hynix made a decision to build a memory fab today, it would come online in late 2028 at the earliest and would be fully ramped only sometime in 2029.

When it comes to NAND, NAND suppliers also prioritize large customers, which happen to be makers of AI servers. Chen does not expect capacity to swing back to PCs, smartphones, and other consumer devices in 2026, which will affect the prices of these devices.

The effects are clear to see. Enthusiasts are seeing RAM prices for custom-built PCs increase by orders of magnitude week on week, with 64GB of DDR5 RAM now costing more than a PS5 in some cases. This week's Black Friday and Cyber Monday RAM deals might be the last chance to buy RAM before prices skyrocket even further.

The DRAM supply chain is choking, and server memory is taking the first hit. According to DigiTimes, major U.S. and Chinese hyperscalers are now receiving just 70% of the server DRAM they order. That’s despite agreeing to contract price increases of up to 50% for Q4, well above the 30% hike many buyers had budgeted for earlier this year.

Naturally, AI sits at the core of all this. While it’s HBM that gets the headlines, demand for conventional DDR5 RDIMMs is also outpacing supply, particularly at advanced nodes where Samsung and SK hynix have diverted capacity toward parts bound for AI acceleration. Samsung’s recent pricing adjustments confirm the reprioritization, with the company having raised server SSD prices by up to 35% and RDIMM contract rates by as much as 50%, citing sustained demand from enterprise and cloud customers.

What’s left is a market where even the largest buyers can’t secure enough memory. Spot prices have surged since late September, and several top-tier suppliers are reportedly refusing to quote for October allocations. DDR5 16 GB modules that traded at $7 to $8 last month are now hovering around $13, with availability tightening further into November. Module makers are bracing for out-of-stock situations by the end of the quarter.

The rest of the market fares worse. Channel players and smaller OEMs are seeing order fulfillment rates closer to 35% to 40%. With hyperscalers locking in fixed allocations, lower-priority customers are pushed to the spot market or told to wait until capacity opens up in 2026.

Micron warned of this in its most recent earnings call, telling investors that DRAM is a “tight industry” and that bit supply growth will lag demand through the end of next year. TrendForce also flagged a potential quote freeze across certain modules, as suppliers shift to day-to-day pricing in China and avoid locking themselves into bad deals.

This is causing retail DDR5 prices to creep upward, with no sign of stabilization before year’s end. DDR4, meanwhile, is in slow decline. China's Nanya Technology recently said standard DDR4 makes up just 20% of the total DRAM market, and it’s no longer being prioritized for volume production. Unless demand unexpectedly cools or yields improve sharply, DRAM allocation for everyone outside the top buyers will be constrained into 2026.

SK hynix last week used the 2025 Global Summit to reveal its AI NAND strategy and AIN storage products aimed at artificial intelligence applications. While AI systems have historically used storage devices designed for enterprise servers, SK hynix believes that purpose-built NAND-based storage solutions — AIB P, AIN B, and AIN D — will better serve the needs of AI servers and clusters and will enable higher performance efficiency.

Going forward, SK hynix will offer three distinct product lineups tailored for the specific needs of AI clusters and servers: AIN D for high-density storage, AIN P for high-performance storage, and AIN B — based on High Bandwidth Flash (HBF) technology — for emerging ultra-high-performance storage devices that can be installed along HBM memory. Each product family is designed to address its own set of workloads with their own set of technologies while balancing capabilities and costs to improve every stage of AI, from ingestion and archiving to training and inference.

SK hynix's AIN D (Density) solution will use 3D QLC NAND to store massive AI datasets at the lowest cost per bit when it comes to NAND flash memory. The company expects AIN D to be designed to reach petabyte-level density, far beyond today's terabyte-scale SSDs, which retain key benefits of solid-state drives, such as fast access time and high throughput. SK hynix plans to replace nearline HDDs with these products.

By contrast, AIN P (Performance) will address performance needs of AI inference applications with redesigned SSD controllers and 3D NAND flash memory to maximize input-output operations (IOPS) with a 512B granularity for AI workloads, such as vector database searches and fine-grained random reads. Indeed, SK hynix expects samples of its AIN P SSDs to deliver around 50 million 512B IOPS with a PCIe 6.0 interface and up to 100 million IOPS with a PCIe 6.0* interface by 2027.

"The architecture can deliver up to 50 million IOPS with the 512-byte access for PCIe 6.0, which is seven times higher than conventional PCIe Gen6 enterprise SSD," said Chunsung Kim, vice president of SK hynix. "It is not just built for AI workloads, AIM P can also deliver high IOPS and throughputs for conventional storage applications as well. The proof of concept sample will be available in the E3 form-factor by the end of next year and 100 million IOPS over Gen6, the mass production capable product will be available by the end of 2027.

*A single PCIe 6.0 x4 SSD cannot physically sustain 100 million 512-byte IOPS. The link bandwidth caps out around 31 GB/s vs. around 48 GB/s such performance would require. Reaching that figure would need PCIe 6.0 x8 or x16, PCIe 7.0 x4, or a custom interconnect.

The most advanced element of SK hynix's AI NAND family will be AIN B (Bandwidth) — solid-state storage devices based on the HBF technology developed by SanDisk and co-standardized now by SanDisk and SK hynix. The architecture promises to combine HBM-like bandwidth with NAND density, enabling AI systems to handle more inference batches or longer token sequences without adding AI accelerators or HBM. Given that there is no HBF standard, SK hynix does not talk about actual performance numbers or when it expects AIN B to become available. At the summit, both companies hosted the 'HBF Night' event, where they called for collaborative effort to accelerate NAND innovation.

Both firms co-hosted an 'HBF Night' during the summit, gathering engineers and architects from major global tech players to coordinate ecosystem development.

"Through OCP Global Summit and HBF Night, we were able to showcase SK hynix's present and future as a global AI memory solution provider, thriving in a rapidly evolving AI market," Ahn Hyun, President and Chief Development Officer, said. "In the next generation NAND storage market, SK hynix will collaborate closely with customers and partners to become a key player."