Hot Chips 2026: IBM's first dual-ISA core natively executes ARM and z/Architecture in the same core; all cores run at 5.7 GHz base frequency — next-gen mainframe AI processor is built on 2nm node with 11 cores

IBM's next-gen AI processor is the first time it has supported dual ISA execution natively within the same core. Born out of a collaboration between IBM and Arm that was announced in April, the chip is designed to bring the software support available across the Arm ecosystem to IBM's mainframes, allowing businesses to unify deployment rather than relying on separate Arm/x86 servers and z/Architecture mainframes for different purposes.

The approach here isn't a heterogeneous CPU with separate Arm cores packaged on the same chip; IBM has built a core that can execute either z/Architecture or AArch64 instructions, and can switch between them dynamically "within nanoseconds," according to the company. During the Hot Chips 2026 reveal, IBM says it believes this is the first processor to treat both ISAs as "first-class citizens."

IBM relies on Linux Kernel-level Virtual Machine (KVM) to support AArch64 instructions, the same mechanism that allows IBM to support Linux on Z mainframes. Standard z/Architecture instructions bypass KVM. The idea is to ensure that mainframe reliability isn't sacrificed for broader software support, with IBM claiming 99.999999% uptime, even further than traditional high-availability claims. IBM says that equates to just 0.032 seconds of downtime per year.

Much of the development in the software world, particularly around AI, happens with x86 and/or Arm targets in mind, leaving the mainframe behind to figure out its own solution. IBM could, and has, worked to port this software to s390x, but that's not a long-term solution. "We would never be able to work with all of them," Tina Tarquinio, chief product officer at IBM for IBM Z and LinuxONE, told VentureBeat. IBM's dual-ISA core can execute Arm software without modifications, according to the company, allowing Arm-based virtual machines to run as if they were operating on native-Arm silicon. And that's because, well, they are operating on native-Arm silicon, just in a different way.

A high-level look at IBM's dual-ISA processor and next-gen Spyre accelerator

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The processor that presumably will live in z18 mainframes comes with 11 high-performance cores, built on a 2nm process, that can operate at a base frequency of 5.7 GHz. Even on those specs, and ignoring dual-ISA execution, it's a considerable step up over the current Telum II processor that IBM introduced in 2024. That chip features eight cores operating at up to 5.5 GHz. Otherwise, IBM's dual-ISA processor comes with the same 36 MB of private L2, as well as virtual L3 and L4. These caches are larger than Telum II at 432 MB of virtual L3 and 3.5 GB of virtual L4.

Also carried forward is an on-chip DPU, as well as hardware accelerators for AI, compression, and cryptography workloads, same as Telum II. Outside of more cores and higher clocks, much of the work on IBM's dual-ISA processor happened, naturally, in the core itself, which we'll dig into in the next section.

The core supports simultaneous multithreading, which is available to both ISAs.

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Alongside the processor, IBM teased its next-gen AI accelerator at Hot Chips 2026. It's considerably more capable than the current Spyre accelerator, which makes sense, given IBM's new capabilities with Arm. The new accelerator comes with 16 cores that include optimizations for newer AI data formats, including FP4/MXFP4.

The big change comes in memory, however, with IBM moving off LPDDR5 to lower-capacity but significantly higher-bandwidth HBM3e. Each accelerator comes with 96 GB of HBM3e, offering up to 4TB/s, 20x that of what IBM is able to deliver with LPDDR5.

IBM core changes to support z/Architecture and ARM

Much of the work on IBM's next-gen processor happened in the core itself in order to support native execution of AArch64 instructions. The chip has a full hardware implementation of AArch64 v9.3 with Scalable Vector Extension (SVE) support, supporting 2,792 AArch64 instructions.

Starting at the top of the core, the branch prediction area uses the existing Telum II design without any changes.

In the fetch engine, IBM leverages virtual cache tags to fetch data quickly with cache to avoid translation overhead.

IBM built automation tools to consume the ARM XML and understand how to move instructions through the core. IBM says this is the biggest area of silicon expansion in the core in order to support decoding AArch64 instructions.

In dispatch, IBM repurposed general purpose register rename in banked general registers 16 through 31.

In the arithmetic and load/store units, much of the major data flow is shared; addition is addition, as IBM put it. However, IBM implemented new hardware structures for SVE and special data types like FP16. IBM also says there was some non-obvious reuse of its existing CISC, such as memory copy and clear.

The X-Late, or translation, engine reuses the Translation Lookaside Buffer (TLB) but leverages a new page walk.

As opposed to a heterogeneous chip, which accomplishes mixing ISAs on the same die by leveraging different cores, IBM says the driving force behind a dual-ISA core was to deliver the scale of Arm software on a mission-critical platform. Mainframes are still the bedrock of vital data movement in financial institutions, governments, and more.

IBM generally ships new mainframes every two and a half to three years, with z17 mainframes revealed in 2024 at Hot Chips. We expect this mainframe to follow a similar timeline. As usual with deep mainframe infrastructure, however, the actual rollout largely depends on the institution's individual needs.

Full IBM Hot Chips 2026 presentation

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