Intel reportedly adding two new 22-core SKUs with game-boosting cache to Nova Lake-S lineup — 125W unlocked and 65W locked part rumored to be part of single-tile Core Ultra 5 tier

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Midrange offerings with a lot of cache.

Intel Core Ultra
(Image credit: Intel)

Intel's next-gen desktop family, Nova Lake, is expected to take a generational leap in terms of performance, and a big part of that is the rumored introduction of bLLC (Big Last Level Cache). It would be the company's answer to AMD's X3D chips, but implemented even more aggressively, from what we can tell so far. Now, a new leak from Jaykihn says Intel has added two new Core Ultra 5 SKUs with bLLC to the lineup, both featuring 22 cores in total.

The leaker accidentally tweeted out the wrong specs at first, so we've only embedded their correction post. According to the leak, each chip features a 22-core config comprising 6 P-Cores, 12 E-Cores, and 4 LP-E cores on a single tile. That would access to up to 144MB of bLLC. The rumor indicates one unlocked SKU with a 125W TDP and a locked SKU with a 65W TDP; there are seemingly no other differences between the two.

Dual-tile variants of Nova Lake-S could push the cache count up to 288MB, but those will likely be reserved for truly high-end SKUs. The Blue Team still offering a competitive midrange option with a lot of cache to help with gaming performance would be a welcome development. As a reminder, Nova Lake will likely use the Coyote Cove architecture for its P-cores and the Arctic Wolf architecture for its E-cores, according to leaks and rumors.

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Nova Lake-S Rumored SKUs

SKU

Core Config (P+E+LP-E)

bLLC

TDP (Unlocked/Locked)

52 Cores (dual-tile)

(8+16)+(8+16)+4

288MB

175W

44 Cores (dual-tile)

(8+12)+(8+12)+4

264MB

175W

28 Cores

8+16+4

144MB

125W

28 Cores

8+16+4

-

125W / 65W

24 Cores

8+12+4

132MB

125W

24 Cores

8+12+4

-

125W / 65W

22 Cores

6+12+4

108MB

125W / 65W

22 Cores

6+12+4

-

125W / 65W

16 Cores

4+8+4

-

65W / 35W

12 Cores

4+4+4

-

65W / 35W

8 Cores

4+0+4

-

65W / 35W

6 Cores

2+0+4

-

65W / 35W

Previously, we covered how the alleged 42-core Nova Lake-S silicon could actually have 44 cores, combining 2x 8P+12E tiles, perhaps freeing up 6P+12E tiles that could be used for cheaper bLLC-equipped chips. At the time, we predicted that a Core Ultra 7 SKU with 22 cores could be the recipient of this silicon, but now this leak points toward it being used for Core Ultra 5 SKUs instead. Of course, the prospect of bLLC being limited to unlocked K-series models seems to have withered away at this point.

Nova Lake-S is shaping up to be a vast and expansive family for Intel with several SKUs that might not even make it to market by the time it launches as the Core Ultra 400 series next year. It remains to be seen how the company will name all these different models. So far, rumors indicate a CES 2027 announcement is imminent for Intel's next-gen family, but the ongoing component crisis could throw things off.

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Hassam Nasir
Hassam Nasir
Contributing Writer

Hassam Nasir is a die-hard hardware enthusiast with years of experience as a tech editor and writer, focusing on detailed CPU comparisons and general hardware news. When he’s not working, you’ll find him bending tubes for his ever-evolving custom water-loop gaming rig or benchmarking the latest CPUs and GPUs just for fun.

8 Comments Comment from the forums
  • JRStern
    I'll take the 12 cores especially if it can run fanless.
    Reply
  • usertests
    This is a positive development, but from a previous leak, the budget bLLC SKUs could feature less L3 cache, similar to most other Intel CPUs tying cache slices to cores/clusters.

    So AMD could put out a budget X3D CPU with 8-10 cores and the full 144 MiB, while Intel's version has 108 MiB. I think it's 12 MiB per P-core or E-core cluster, so 108 MiB for 6P + 12E.

    Edit, it was also a Jaykihn leak: https://videocardz.com/newz/intel-core-ultra-400d-400dx-nova-lake-s-skus-to-feature-up-to-288mb-of-cache
    Technically, it's 24 MiB per two P-cores, since Jaykihn is claiming those are clustered with shared 4 MiB L2 cache: https://www.tweaktown.com/news/111118/intels-nova-lake-will-unify-l2-cache-and-feature-new-d-and-dx-lines-for-enthusiasts-claims-leaker/index.html
    Reply
  • Gururu
    So we already know that the bLLC is best with high end GPUs. Has anything been demonstrated that the 5080/5090 only can utilize a certain amount, or is it always a case that these and faster GPUs to come will always use as much as they are given?
    Reply
  • usertests
    Gururu said:
    So we already know that the bLLC is best with high end GPUs. Has anything been demonstrated that the 5080/5090 only can utilize a certain amount, or is it always a case that these and faster GPUs to come will always use as much as they are given?
    L3 cache in the CPU is utilized by the CPU, not GPU.

    If it lifts a CPU bottleneck too high then you'll need a high-end GPU like 5090 to get the higher FPS.

    However, there can be subtle benefits that don't need the fast GPU, like higher 1% lows, or better power efficiency. Some types of games tend to get an outsized benefit, like simulation titles.

    Then there are professional workloads that will benefit from big L3 cache, but not too many. Most reviewers don't have test suites large enough to identify these, so you have to go to the GOAT... Michael Larabel at Phoronix.
    Reply
  • TerryLaze
    usertests said:
    L3 cache in the CPU is utilized by the CPU, not GPU.

    If it lifts a CPU bottleneck too high then you'll need a high-end GPU like 5090 to get the higher FPS.

    However, there can be subtle benefits that don't need the fast GPU, like higher 1% lows, or better power efficiency. Some types of games tend to get an outsized benefit, like simulation titles.

    Then there are professional workloads that will benefit from big L3 cache, but not too many. Most reviewers don't have test suites large enough to identify these, so you have to go to the GOAT... Michael Larabel at Phoronix.
    His point was "is there really going to be any difference between 108-144Mb" ...
    Once you have a big enough cache for your cores (or his point for the game since that is what the GPU is displaying) are the benefits still increasing.

    Did anybody do any testing on a x3d cpu limiting the cache in say 10mb steps?
    Reply
  • usertests
    TerryLaze said:
    His point was "is there really going to be any difference between 108-144Mb" ...
    Once you have a big enough cache for your cores (or his point for the game since that is what the GPU is displaying) are the benefits still increasing.

    Did anybody do any testing on a x3d cpu limiting the cache in say 10mb steps?
    There are clearly diminishing returns, already seen by moving from 32 MiB to 96 MiB, and it's highly game-specific. Average uplift from tripling your L3 cache is what, 15%? It was more like 30% in Tom's 9800X3D review but that is probably on the high side and for 1080p. There will be games that "tap out" the amount they can use between 32-96, or 96-144.

    If anyone has done that step testing, I haven't seen it. But there will suddenly be a large variety of different cache levels available to compare in the coming generations:

    32 MiB Zen 3/4/5 CCD
    36 MiB Raptor/Nova Lake 8P + 16E
    48 MiB Zen 6 CCD
    64 MiB Zen 7 CCD (16-core)
    96 MiB Zen 3/4/5 X3D
    108 MiB Nova Lake bLLC 6P+12E
    132 MiB Nova Lake bLLC 8P+12E
    144 MiB Zen 6 X3D, Nova Lake bLLC 8P+16E
    224 MiB Zen 7 X3D

    Notably, 48/64 from AMD filling that big gap we've had, 108/132 from Intel filling the new gap, and Zen 7 X3D delivering a stupidly high amount of L3 cache. (Dual variants can hit 192/288/448 total, but are unlikely to be exploited by game engines anytime soon.)
    Reply
  • cp0x
    I am planning to build a high end 52-core gaming machine using this CPU and 4GB of RAM (or even 8GB RAM if I get a raise and a large tax refund and I manage to save up enough money by then). I should be able to afford a 3060 GPU by then.

    Welcome to 2027.
    Reply
  • rluker5
    usertests said:
    There are clearly diminishing returns, already seen by moving from 32 MiB to 96 MiB, and it's highly game-specific. Average uplift from tripling your L3 cache is what, 15%? It was more like 30% in Tom's 9800X3D review but that is probably on the high side and for 1080p. There will be games that "tap out" the amount they can use between 32-96, or 96-144.

    If anyone has done that step testing, I haven't seen it. But there will suddenly be a large variety of different cache levels available to compare in the coming generations:

    32 MiB Zen 3/4/5 CCD
    36 MiB Raptor/Nova Lake 8P + 16E
    48 MiB Zen 6 CCD
    64 MiB Zen 7 CCD (16-core)
    96 MiB Zen 3/4/5 X3D
    108 MiB Nova Lake bLLC 6P+12E
    132 MiB Nova Lake bLLC 8P+12E
    144 MiB Zen 6 X3D, Nova Lake bLLC 8P+16E
    224 MiB Zen 7 X3D

    Notably, 48/64 from AMD filling that big gap we've had, 108/132 from Intel filling the new gap, and Zen 7 X3D delivering a stupidly high amount of L3 cache. (Dual variants can hit 192/288/448 total, but are unlikely to be exploited by game engines anytime soon.)
    I like where you are going with this. As far as I know only Intel will limit the cache on cut down SKUs, but doesn't necessarily have to. If you can disable cores and not cache on the higher SKUs then maybe we can get a real apples to apples comparison (like they did with Skylake arch SKUs with varying cache) of 6p+12e from base, disabled 8p+12e, disabled 8p+16e, bllc 6p+12e, bllc,d 8p+12e, bllc,d 8p+16e. Which would give steps of 27, 33, 36, 108, 132, 144MB (with 6p+12e at same clocks)if my arithmetic is correct. Still leaves a giant hole between 36 and 108MB, but at least there are nice steps above 108. All it will take is for some reviewer to buy all of those CPUs and run the tests.
    It would be really nice if there were a way for a dual compute chip NVL, with the compute cores on one disabled, for the enabled cores to use the cache on the disabled cores chiplet as another level between it's cache and ram, but I believe that takes extra hardware resources to do which NVL wouldn't have.
    Reply