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AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap
AMD has announced that its 6th Gen EPYC processor, codenamed Venice, has entered production ramp on TSMC's N2 (2nm-class) process technology in Taiwan. The chip, which packs up to 256 Zen 6 cores and claims a 70% compute performance gain over the current EPYC Turin lineup, is the first high-performance computing product in the industry to reach production on N2. AMD also announced a follow-on processor called Verano and said it plans to eventually produce Venice at TSMC's Arizona campus as well.
TSMC began volume production on its N2 node late last year, and the foundry is ramping five separate 2nm fabs this year to meet what it has described as record demand. Apple reportedly secured the lion’s share of initial N2 capacity for consumer silicon, but it’s AMD with Venice that’ll be the first HPC product on the node. Server and data center dies are larger and architecturally more complex than smartphone SoCs, and getting them through yield qualification on a brand-new process is a much bigger challenge.
"As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster," said Dr. Lisa Su, chair and CEO of AMD, in the company's press release.
Venice brings the new SP7 socket, up to 16 memory channels delivering 1.6 TB/s of per-socket bandwidth, and doubled CPU-to-GPU bandwidth that likely indicates PCIe 6.0 support. AMD previewed these specs at its Advancing AI event last year and at CES in January, but this announcement puts the chip on track for commercial shipments later this year.
AMD could face limited next-gen competition in the server market right now, with Intel’s Diamond Rapids — the P-core Xeon 7 family that would be Venice's direct counterpart — rumored to be delayed to mid-2027. Intel's only new server product expected this year is Clearwater Forest, an E-core design built on Intel 18A with up to 288 cores. Clearwater Forest is optimized for high-density deployments at scale, not the high single-thread and general-purpose performance segment that Venice is targeting.
AMD already holds a record 46% server CPU revenue share as of Q1 2026, according to Mercury Research, up from roughly 40% at the company's Financial Analyst Day in November last year. Venice will likely extend that momentum into a segment where Intel will be relying on its existing Granite Rapids Xeon 6 lineup for at least another year.
AMD also confirmed Verano, another 6th Gen EPYC processor built on TSMC 2nm and optimized for performance-per-dollar-per-watt. AMD also says it plans to ramp Venice production at TSMC’s Arizona facility. That’s likely referring to Fab 21 Phase 3, which broke ground last April and is slated for N2 and A16 processes. Volume 2nm production isn’t expected before 2028 at the earliest here, however.
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Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
