SK hynix doesn't expect hybrid bonding to be ready for HBM4E, Jaesik Lee, VP of package engineering at SK hynix America, said during a presentation at Hot Chips 2026 on August 23, pushing the industry's most anticipated memory packaging transition out to HBM5 at the earliest.
The problem, as he describes it, is that HBM cubes are capped at a total thickness of 775 microns — the standard thickness of a 300mm logic wafer — so every additional DRAM layer must come from thinner dies and narrower gaps. 16-Hi HBM4, now in customer qualification at 48GB per cube while 12-Hi is in mass production, thins its core dies to around 50 microns and halves the gap between them compared with 12-Hi. Lee's session also went into detail about the company's iHBM cooling architecture three months after its May unveiling. Attaching a constraint to it, Lee explains that the heat blocks can't be applied to any HBM generation already in design.
(Image credit: SK Hynix)
The 775-micron limit
The JEDEC HBM4 standard raised the package thickness ceiling from 720 microns, which held through HBM3E, to 775 microns, easing the pressures associated with adopting hybrid bonding. When a GPU package gets its cold plate attached, both the logic die and the memory stacks are ground back to expose bare silicon, Lee said, and because logic wafers are 775 microns thick, a memory cube that grew any taller would stand proud of the processor beside it. "That's the kind of limit that we can go up so far, because the logic wafer thickness is also 775 microns," Lee said.
Thinner dies leave the stack with proportionally more oxide, which conducts heat poorly compared with silicon, while pin speeds that have risen from 1 Gbps in early HBM to 8 Gbps in HBM4 concentrate more power in the same footprint. SK hynix's own figures put the thermal burden at 2.2 times higher across the HBM generations shown, while stack counts double every two generations.
(Image credit: SK Hynix)
The company's mass reflow-molded underfill (MR-MUF) process, which stacks all dies via pick-and-place and joins them in a single reflow, already trades away margin here: filling gaps that have shrunk by half while controlling warpage on sub-50-micron dies is, per Lee, the main manufacturing challenge of 16-Hi.
Hybrid bonding keeps slipping
Samsung publicly committed to hybrid bonding for HBM4 in May last year, with SK hynix holding the copper-to-copper technique as a backup behind advanced MR-MUF. The JEDEC thickness relaxation then removed the immediate need, and industry discussions now weigh a further move to 825 to 900 microns for 20-Hi stacks, which would push the copper-bonding crossover out again.
Back in March, it was claimed by industry sources that SK hynix placed its first mass-production hybrid bonding order, a single inline system pairing Applied Materials and Besi tools worth around 20 billion won ($15 million), and Counterpoint Research expects the technique to enter full-scale HBM production with HBM5 around 2029 to 2030.
Hybrid bonding remains at the research stage for stacks of 20 layers and above, per the deck's roadmap, and SK hynix is still deciding which product gets it first. Lee didn't name a target generation, but ruling out HBM4E leaves HBM5 as the earliest slot. The technique joins flattened copper pads and oxide surfaces at room temperature, then relies on copper's thermal expansion during a cure step to form the bond.
(Image credit: SK Hynix)
"This is a very simple process, but in reality it's really challenging," Lee said. "We are talking about 16 layers and 20 layers that we need to make the hybrid bonding, so it's very different from the one-layer stacking." Removing micro-bumps entirely lets core dies grow up to 24% thicker at 20-Hi, cuts thermal resistance by roughly 35% versus MR-MUF at that height, and takes bump pitch below 18 microns, per the deck, against the 30 microns where MR-MUF is today. At HBM4's bump pitch, conventional micro-bumps still work, and each time JEDEC has raised the thickness ceiling, MR-MUF has stayed viable for another generation.
iHBM
The iHBM concept embeds thermally conductive, electrically insulating blocks into the base die's die-to-die PHY region, the interface hotspot where power density peaks, for a claimed thermal resistance reduction of more than 30%.
Lee's slides benchmarked it directly against Samsung's Heat Path Block approach, which routes heat out of the stack through dedicated pillars, and Micron's base-die circuit redesign, which claims over 20% better energy efficiency. All three are vendor claims measured on different metrics, and the SK hynix and Samsung designs are bothslated for HBM5, with neither expected in mass production before 2028. Because the blocks sit inside the package alongside the D2D PHY, they need optimization with the customer's design and can't be applied to generations already in design, Lee said, which makes iHBM a co-design effort. "It's a kind of good option that we can do, but this is not something that we can apply [to] the generation that we already [have] in design."
(Image credit: SK Hynix)
During Q&A, Tanj Bennett of SemiAnalysis argued that stacking taller dilutes the silicon's own throughput. DRAM operating at the cell level delivers on the order of 20 TB/s per square centimeter; a 20-Hi stack tops out around 4 TB/s, and HBM takes far more manufacturing capacity than equivalent DDR5 or LPDDR. "As you get to 20 high, the average speed of that memory is slower than DDR5," Bennett said. "Why is it better to be using the height of the HBM stack instead of intelligently placing cheaper memory around it?"
Lee answered that training workloads demand both bandwidth and capacity, then added that inference may split the difference, keeping the KV cache in high-bandwidth memory while offloading to LPDDR. That split already exists in products like Nvidia's Vera Rubin platform, which pools LPDDR5X with HBM4 over NVLink-C2C for exactly this purpose, and the High Bandwidth Flash spec that SK hynix co-developed with Sandisk extends the tiering idea to NAND.
"That's a kind of question that we need to also look at in the future," Lee said of the tiered approach. SK hynix holds around 70% of Nvidia's HBM orders for the Vera Rubin generation, according to reporting from January, and all of it will be stacked with MR-MUF. Which product moves off it first, Lee says, is a decision that the company hasn't made.
Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
