In the current climate, choice has been severely limited when it comes to upgrading or building a new PC. You can’t just pick the best components to build a high-powered gaming rig, as many components are out of stock or at eye-watering prices. The same goes for trying to construct a budget PC build, as there just aren’t any cheap components anymore, apart from certain parts like AM4 CPUs, which are tied to limited upgrade paths. Just take a look at the price and availability of Nvidia’s RTX 5090, for example; at the time of writing, the cheapest RTX 5090 gaming GPU available online is $6,549.99, and that’s from a third-party seller on Amazon, not directly from a large first-party retailer or manufacturer. There are even reports that the RTX 5090 has been effectively discontinued in favor of making AI GPUs, which means pricing will only get worse over the coming months.

If you’re anything like me, when I’m even remotely considering spending that kind of money, I’m not willing to risk buying from a suspicious retailer or a seller that can’t refund or replace the product should there be a fault, or if it gets damaged in transit. The original MSRP for the RTX 5090 at launch was just $1999.99. I remember balking at that price; now I wish I’d made the leap, as the next generation of GPUs is likely not coming before 2028, discounting pricing and availability.

So, where does that leave us, in a climate that feels actively hostile to enthusiasts? There is one place that seems to be a small bastion of defiance amongst the doom and gloom of the price-rising apocalypse, and that’s Micro Center. Should you be lucky enough to live near a store, or at least within driving distance, then you have another option open to you for finding PC components at prices that are often much cheaper than both Amazon and Newegg. Unfortunately, apart from a small marketplace storefront on Amazon, Micro Center does not do business online.

Having a quick look at some in-store offerings at one particular store location, I can find several RTX 5090s: the Asus GeForce RTX 5090 ROG Astral and MSI GeForce RTX 5090 Suprim, both priced at $5,029.99, over $1,500 cheaper than the cheapest available RTX 5090 found online at Amazon. That’s a considerable difference, but again, these prices are only available to those willing to make the trek to their local Micro Center store, and that’s a major caveat for the majority of Americans.

It’s not just the RTX 5090 either. I check for the best prices and deals on tech products daily, often finding some of the best value in component bundles from Newegg, where the high prices of RAM and SSD storage can be offset against the savings you typically make from bundling a bunch of deals together. Micro Center often undercuts these bundles with similar offerings at a significantly reduced price, but the issue is the ability to take advantage of the deal. The reason I don’t just highlight Micro Center deals more often is the limited availability to the majority of our readers.

Bundle breakdown

Let’s break down an example of one of Micro Center’s DDR5 component bundles. This gaming-oriented bundle features an AMD Ryzen 7 9800X3D processor, an MSI B850 Gaming Pro WiFi6E AM5 motherboard, and 32GB of G.Skill Flare X5 Series DDR5-6000 memory. The total for these three components in a bundle is $899.99, with the cheapest price listed on PC Part Picker for the 9800X3D at $449, the MSI B850 Gaming Pro WiFi6E listed as $189, and the 32GB of G.Skill RAM costing $479 for a combined total of $1,117.

How much is a similar component bundle from Newegg? Well, the closest comparable combo bundle on offer features the same 9800X3D processor, a slightly better Asus TUF Gaming X870E-Plus WIFI7 motherboard, and the same amount of memory with very similar speeds from Corsair. The total for this bundle is $1,109.

Comparing the two bundles directly, even with a slight difference in components, there is a large $200 price difference. Some of that is tied up in the higher-tier motherboard, but even taking that into account, Micro Center's price is still lower. So it’s definitely worth exploring the idea of heading to a brick-and-mortar store over simply buying online. Just remember to factor in the price of the gas, and your time, on your way there.

Micro Center

Newegg

Even with Micro Center managing to offer consumers another choice in the PC component landscape and undercutting the pricing of the bigger retailers, the underlying problem of PC component prices skyrocketing remains. Memory and NAND prices continue to rise with no end in sight; major component manufacturers like Micron, which owns the Crucial brand, have pulled out of the consumer market, meaning even less choice in stores and ending any ongoing support for consumers who have purchased products previously. Stock is running low or has expired on the best-value products, and consumer choice is being strangled.

If you currently own a DDR4 system, the cost of upgrading to DDR5 is astronomical; the same goes for upgrading your graphics card to the latest Nvidia 50-series GPUs. Nothing is available anywhere near the original MSRP launch prices, and the more affordable budget-to mid-range card SKUs only offer 8GB of VRAM, which is not great for modern gaming, as resolutions over 1080p can easily demand more. So, if you’re near a Micro Center location and you want an upgrade, they are more than likely going to offer you the best value for money in the current market. For the rest of us who don’t live near a Micro Center, keep checking our coverage for the best possible prices on PC components.

Although Intel's advanced packaging saga began in 2017 with the Kaby Lake-G CPUs and Stratix 10 FPGAs, packaging technologies weren't quite the hot topic they are today. However, both Intel and its industry peers were working relentlessly to advance these technologies, so Intel was among the first companies to outline a detailed roadmap for multi-chiplet processors featuring its 2.5D and 3D integration technologies — EMIB and Foveros — back in 2020. Following the fiasco with its initial 10nm process technology, the company made it clear that its multi-chiplet strategy is a sustainable way to deliver performance and feature enhancements cost-efficiently and at a predictable cadence. While we certainly cannot say that all of Intel's multi-chiplet projects were a success, it is safe to say that the majority of Intel's client and data center CPU products launched in recent years use multiple chiplets and rely on EMIB and Foveros advanced packaging technology.

In fact, as Intel's advanced packaging roadmap evolves, EMIB and Foveros not only become more sophisticated to address the demands, but they also become simpler to cover cost-sensitive products. Another peculiarity about Intel's packaging duo is that they no longer seem to be two mostly separate technologies. In many cases, they complement each other and Intel's upcoming process technologies, thereby becoming key building blocks of the company's future products. The ultimate goal is to build system-in-packages (SiPs) the size of 12 reticles using both EMIB and Foveros Direct 3D, but Intel is not quite there yet, so let's take a look at where we are today and what's on the horizon.

EMIB: Fantastic bridges and where to find them

Intel's EMIB has evolved dramatically since entering high-volume manufacturing in 2017. What started as a relatively straightforward way to connect adjacent chiplets without using an expensive silicon interposer has become a sophisticated packaging technology used for data center processors and is set to enable massive AI accelerators 12 times the size of a reticle with dozens of silicon bridges, more than 24 HBM stacks, and advanced power delivery.

The basic idea behind EMIB remains unchanged almost a decade after its first introduction. Instead of placing compute and memory dies on a large silicon interposer, Intel embeds tiny silicon bridges into an organic package substrate only where high-density die-to-die connectivity is required (try to find those bridges!). This reduces silicon usage and allows the rest of the package to use conventional substrate wiring and relaxed bump pitches. Early EMIB implementations used a 55-µm first-layer-interconnect (FLI) bump pitch, which Intel subsequently reduced to 45 µm. Intel's recent roadmaps indicate further reductions to around 36 µm and ultimately 25 µm, which dramatically increases the number of connections that can fit along a chiplet's edge (shoreline density).

In addition to shrinking FLI bump pitches and increasing connection density, Intel is also adding functionality to the bridges themselves. EMIB-M incorporates metal-insulator-metal (MIM) capacitors into the bridge to improve power delivery and suppress voltage fluctuations close to compute dies. The newer EMIB-T takes this concept considerably further by adding through-silicon vias (TSVs), which enable power to travel vertically through the bridge instead of taking longer paths around it. This becomes increasingly important for multi-kilowatt system-in-packages (SiPs) and HBM4-class memory subsystems, where both current density and power integrity are major packaging constraints.

Such SiPs are not only complex, but they are physically large, so Intel's EMIB has evolved to support larger designs. Firstly, a finer FLI pitch increases the interconnect density required to build bigger SiPs. Secondly, EMIB-M addresses the power-integrity problem created by big processors, such as Intel's Xeon 6 'Granite Rapids.' Thirdly, EMIB-T simplifies power routing, lowers impedance, and reduces noise, which will get more important when faster versions of UCIe (32 GT/s and higher) become commonplace. Intel's consistent EMIB technology development has enabled the company to move from an SiP of 4X reticle size on an 80×80 mm package earlier this decade, to something closer to 8X reticles on a 120×120 mm package today, and even larger 12X SiPs on a 120×180 mm package in the future.

Eventually, Intel plans to combine finer-pitch EMIB technology with glass-core substrates. Glass offers better stability and reduced warpage compared with organic materials, which becomes increasingly important as packages grow to enormous sizes. Glass will likely be one of EMIB's biggest advancements, as it will enable improvements in multiple directions, including performance and dimensions.

Intel says EMIB-T is on track for mass production in 2027 and its yields and reliability are meeting its targets. If those ramps proceed as planned, EMIB will have evolved from an alternative to a silicon interposer into one of Intel Foundry's key technologies for building massive AI systems.

"Customer interest in EMIB-T continues to be very high – the technology is compelling, providing capabilities for advanced AI silicon solutions which are not possible with today's mainstream offerings," said Lip Bu Tan, chief executive of Intel, in an August 2026 earnings call. "We continue to have a growing EMIB-T backlog, yield and reliability are hitting targets, and we are focused on ramping the technology into high volume and high quality to support customer ramps in 2027."

Intel is scaling EMIB along several directions simultaneously: finer interconnect pitch, more bridges, larger substrates, denser power delivery, faster memory interfaces, and dramatically larger SiPs. Intel formally positions EMIB as a cost-effective advanced packaging technology that uses local silicon bridges for logic-to-logic and logic-to-HBM connections in an organic substrate instead of large silicon interposers used by solutions like TSMC's CoWoS-S. Meanwhile, there are applications that can benefit from large, rigid interposers or flexible organic redistribution layer interposers. To address these applications, Intel's Foveros portfolio includes Foveros-S, Foveros-R, and Foveros-B, which more directly mirror TSMC's CoWoS-S, CoWoS-R, and CoWoS-L packaging technologies, respectively.

Foveros 2.5D: A fistful of packages

Intel's Foveros packaging technology is evolving from its original chip-on-wafer implementation that emerged in 2019 with the Lakefield processor into a broad family of 2.5D and 3D integration technologies designed to address everything from cost-sensitive client processors to large HPC and AI systems.

The original Foveros technology used an active 22FFL-based silicon base die, or interposer, with through-silicon vias (TSVs) and active dies attached using face-to-face bonding. Intel's Lakefield and Ponte Vecchio used active base dies and 36 µm microbump pitches, whereas Meteor Lake, Arrow Lake, and Panther Lake implementations use a passive base with a 36 µm microbump pitch. Since the introduction of Foveros with active and passive base dies in 2019 – 2023, Intel has also diversified Foveros to address different cost and integration requirements. The latest Foveros 2.5D roadmap — which mentions -S, -R, and -B variants with similar characteristics — presented in mid-2025, takes Foveros considerably further from its original capabilities: it targets pitches below 25 µm, bump density increase from 772 to 1,600 connections per mm², and chip-to-chip interconnect power of 0.15 pJ/bit.

For now, the most advanced and yet production-proven Foveros 2.5D technology is Foveros-S. This packaging technology places multiple chiplets on a silicon interposer and currently supports packages up to four reticles in size, which is below what TSMC offers with CoWoS-S (up to 5.5X reticles). Since Foveros-S is essentially an evolution of the original Foveros from 2019, Intel legitimately says that it has been in volume production since 2019. Yet, going forward, Foveros-S will be evolving in multiple directions, which includes larger package sizes, interconnect density, and interconnect power efficiency.

Foveros-R removes the silicon interposer altogether and uses fan-out RDL technology to optimize cost and interconnect density. Intel says the implementation can use up to three redistribution layers. The method is designed to offer a balance between cost and interconnect density and enable heterogeneous integration of chiplets from different sources through UCIe. Like the other members of Intel's current Foveros 2.5D family, the technology uses 36 µm microbump pitches, but is designed to support pitches below 25 µm as well as bump density scaling from 772 to 1,600/mm² and chip-to-chip interconnect power of 0.15 pJ/bit. Intel says Foveros-R will be production-ready in 2027.

Foveros-B extends the concept toward larger and more complex AI/HPC designs. Instead of relying on a full silicon interposer, the technology combines RDLs with local active or passive silicon bridges that provide high-density connections only where they are needed. This potentially gives Intel an intermediate option between an RDL-only implementation and a large silicon interposer, as well as a direct competitor for TSMC's CoWoS-R.

Note that Intel does not explicitly say that Foveros-B uses EMIB bridges, though given similar microbump pitch sizes and the plan to use active local bridges in the future, Foveros-B's bridges are likely to closely resemble EMIB-M and EMIB-T bridges. If Foveros-B can indeed use EMIB bridges, future Foveros-B designs could also incorporate cache disaggregation, integrated voltage regulators (IVRs), or MIM capacitors.

As for interconnection densities and power, Foveros-B is listed as designed to support pitches below 25 µm, bump density scaling up to 1,600/mm², and chip-to-chip interconnect power of 0.15 pJ/bit. Meanwhile, Intel has not disclosed when Foveros-B will be ready for commercial production, so its actual specifications remain to be seen.

With EMIB and the Foveros 2.5D portfolio, Intel can address a broad range of applications, but Intel's scaling is not stopping. In addition to 2.5D lateral scaling enabled by EMIB or Foveros 2.5D, it can stack chiplets on top of each other using its Foveros 3D and EMIB 3.5D packaging technologies.

Foveros Direct 3D: There will be copper (and no bumps)

Unlike simple package-on-package stacking, which has existed for decades, densely interconnected 3D stacking essentially turns separate dies into parts of the same tightly coupled chip, increasing bandwidth, reducing latency, cutting interconnect power, and shrinking footprint. The challenge is manufacturing thousands of extremely fine connections between dies while maintaining yield, power delivery, signal integrity, and — perhaps most importantly — removing heat from chips buried inside the stack.

The biggest architectural step in Intel's Foveros roadmap is Foveros Direct 3D, which moves from microbump-based connections toward direct copper-to-copper hybrid bonding. Conventional microbumps cannot shrink forever, as solder bumps need sufficient dimensions to maintain manufacturing yield and reliability, while the solder itself introduces additional resistance and parasitic effects. Foveros Direct 3D eliminates solder altogether and directly bonds copper pads on one die to those on another, which enables an interconnect pitch below 10 µm — up to 10 times finer than conventional microbump technology.

Intel claims that Foveros Direct 3D can offer bonding pitch of sub-10 µm, interconnect density of up to 10,000 connections per mm², and chip-to-chip interconnect power below 0.05 pJ/bit. Such dense connectivity shortens signal paths between stacked dies, increases bandwidth, reduces latency, and cuts the energy required to move data. In addition to electrical advantages, direct bonding creates more continuous thermal paths between dies, which Intel says improves heat dissipation compared with conventional packaging, which is crucially important as vertically stacked logic pushes power density dramatically higher.

Intel's Foveros Direct 3D bonding interface supports both face-to-back and face-to-face stacking. In addition, Intel has described chip-to-wafer as well as wafer-to-wafer bonding.

As Intel's schematic drawing of a Foveros Direct 3D-based system-in-package shows (and Intel confirms), the technology is much more flexible than simply placing one logic die on top of another. The method can support different die sizes, multiple stacking levels, and can combine dies manufactured using different process technologies in one SiP.

Intel's Xeon 6+ 'Clearwater Forest' processor is the first product to use Foveros Direct 3D copper bonding in volume to attach Intel 18A compute chiplets to active base dies. The CPU uses the 1^st Generation Foveros Direct 3D with 9 µm copper bonding pitch. Meanwhile, Intel plans to shrink bonding pitch to 3 µm with its 2^nd Gen Foveros Direct 3D. To put these numbers into perspective, TSMC's 1^st Gen SoIC from 2023 supports pitches of 9 µm (AMD's 2^nd Gen 3D V-Cache uses this version), whereas the latest generation that entered volume production in 2025 features bonding pitches of 6 µm. TSMC expects to shrink SoIC's interconnection pitch to 4.5 µm by 2029.

EMIB 3.5D: Everything everywhere all at once

Finally, Foveros and EMIB do not have to operate independently. Intel can combine Foveros 2.5D or Foveros Direct 3D with substrate-embedded EMIB bridges to create what it calls EMIB 3.5D in a bid to build its ultimate products. In this architecture, Foveros provides dense local 2.5D or 3D connectivity within individual chiplet assemblies, while EMIB provides high-bandwidth horizontal connections between these modules, essentially building a massive system-in-package out of smaller SiPs. Intel says the individual SiPs can be identical to scale performance, or distinctive, to enable different functionality.

The combination of EMIB and Foveros is particularly useful because it enables Intel to scale both horizontally and vertically without placing the entire system on one massive silicon interposer. Intel says EMIB 3.5D can achieve a total silicon surface area considerably larger than what its existing silicon-interposer-based technologies can accommodate. Intel first used EMIB 3.5D to build its Ponte Vecchio compute GPU that integrated 47 active tiles manufactured on five process nodes and contained more than 100 billion transistors. Although Intel's Data Center GPU Max can hardly be called a smashing success, it certainly demonstrated what Intel can do with its advanced packaging technologies.

Going forward, the EMIB 3.5D architecture becomes considerably more promising when combined with Foveros Direct 3D. Using both will enable Intel to build tightly coupled compute modules using ultra-dense vertical copper-to-copper connections, and then link multiple modules laterally using EMIB, essentially scaling complex processors both vertically and horizontally. However, surprisingly, Intel decided not to use EMIB 3.5D for its next-generation Xeon 'Diamond Rapids' processor: while the CPU uses Foveros Direct 3D for vertical integration, UCIe-S connections are used for lateral interconnects.

Multi-die another day

While Intel's EMIB and Foveros technologies emerged to serve different kinds of scaling, the company is evolving them into a complementary platform that can scale complex processors both horizontally and vertically.

EMIB is progressing toward finer interconnect pitches, vertical power delivery, glass substrates, and packages exceeding 12 reticles with more than 24 HBM stacks, while the expanding Foveros family spans from 2.5D integration all the way to ultra-dense Foveros Direct 3D hybrid bonding. In fact, Foveros Direct 3D already enables sub-10-µm copper-to-copper connections and is headed toward even finer pitches.

Meanwhile, EMIB 3.5D combines vertically stacked modules with lateral EMIB links to create large heterogeneous system-in-packages for ultimate AI and HPC applications without using enormous silicon interposers.

What is perhaps interesting to note is that, for now, Intel lacks a system-on-wafer platform to enable Cerebras WSE and Tesla Dojo-like wafer-scale processors, though this is explainable, as demand for such technologies is too limited today and may not pick up significantly tomorrow.

In 2025, during the release of the RTX 5000 series graphics cards, one Australian student was watching a Digital Foundry interview with Nvidia engineers, where the team was showing off Multi Frame Generation (MFG), a feature locked to Blackwell GPUs. During the podcast, the idea of MFG running on older RTX 4000 series hardware was floated, but the feature was never released for Ada Lovelace hardware. “Every few months, I would do a Google search to see if it ever happened or not,” said Dashdogy, a Physics Major studying Mathematics and Space Science.

“A few weeks ago now, the perfect storm arrived. Mid-semester break had just started, and I did the same Google search as I always do. But thought, maybe I’ll look into it. How hard could it be?”

One AWS instance, and a week of late nights later, he unlocked “true” MFG on Ada Lovelace hardware, a feat previously believed to be impossible due to incompatible instructions and a black screen that blocked the progress of modders before them. We’ve tested the mod extensively, and the results stand out. Multi Frame Generation has unofficially arrived for non-Blackwell hardware.

Dashdogy isn’t the only modder that’s been hard at work unlocking features for older-gen GPUs. Several weeks ago, when DLSS5’s Neural Rendering DLL first found its way onto the internet, RTX Remix modder Uncle Burrito set their sights directly on it. “I had no idea of telling [if running DLSS 5 on Ada] was even possible,” they said. Given the previous performance claims of requiring multiple RTX 5090s to run on its initial reveal, Uncle Burrito knew DLSS 5 would be computationally expensive, but that didn’t stop him from trying to get into the DLL itself.

“Once I reverse-engineered it, with the help of Claude, it became obvious that this was possible on Ada. Not only was most of the code compatible, but to me, it looks like Ada support was simply left behind as a work in progress, not as a hard limit.”

And so, less than a day after the DLL had been released in an early access version of NBA 2K27, Uncle Burrito had successfully ported the technology to Ada hardware. In the weeks since the release of Uncle Burrito’s initial unlock for DLSS 5 NR on Ada GPUs, Nvidia has clarified that Neural Rendering would indeed be supported by RTX 4000 series GPUs, lending credence to the idea that implementation on Ada GPUs was merely unfinished in the initial shipping versions of the DLSS 5 DLL.

These two foundational mods by Dashdogy and Uncle Burrito now serve as the baseline for endless numbers of forks and integrations of both Neural Rendering and MFG for older hardware, which have now allowed for ports all the way back to 2018’s Turing architecture, and in DLSS 5 NR’s case, ports to AMD hardware. It’s now as simple as using one of many tools to click-and-install both into hundreds of games.

Unlocking MFG (Dashdogy)

Dashdogy’s experience in modding spans years, having created Stellaris mods while still in High School, making compatibility scripts to patch multiple mods together. But porting DLSS MFG to Ada devices was a different beast entirely. Blackwell and Ada use entirely different ISAs, despite their software similarities. “When this [running Blackwell instructions on Ada] happens, the frames will generate, but the GPU graphs an error and returns a black screen,” he explains.

Underpinning Nvidia’s implementations of DLSS in shipping titles are two pieces of software: a package named Streamline, which usually includes a suite of DLSS software, and is a universal translator that allows games to run various upscaling technologies like DLSS. Used in tandem with Streamline is a Neural Graphics Framework (NGX), Nvidia’s proprietary software that underpins its AI-powered efforts like Super Resolution and Frame Generation. As a game calls for tools, NGX cooks the computation, and Streamline serves them to a given game’s engine.

As Dashdogy explored how to make MFG compatible with Ada, the modder targeted Streamline and NGX directly. “I specifically spoof the Streamline and NGX calls in memory that define how many frames the GPU is allowed to generate.” This approach allowed an Ada-based GPU to think it was allowed to generate more frames than it ordinarily would. “It’s a pretty simple interception, and on 40-series turns 1 into a 5. Now the GPU knows ‘I am a 4080 and I’m allowed to generate five frames,'" which successfully swerved the black frame issue that other earlier modders encountered, thereby unlocking higher frame generation multipliers.

Dashdogy quickly packaged things up as a Cyberpunk 2077 mod, and shipped it off to Nexus Mods. This was the canary in the coal mine for a more mature integration, but things weren’t quite perfect yet. Dashdogy and other modders reported a problem — when using anything more than 2X MFG in Cyberpunk 2077 on Ada, things felt sluggish. Latency wasn’t great, and with the help of another modder, they believed that this was the work of the fabled “Hardware Flip Metering,” which smooths out MFG's outputs, and is a primary reason Nvidia offers as the reason the feature doesn’t work on older graphics cards.

Armed with a cloud instance that uses an RTX 6000 Pro Blackwell GPU, Dashdogy quickly went to work improving the MFG mod. “I conducted a kernel dump whilst the GPU was running MFG.” Dashdogy was also equipped with OpenAI’s Daybreak Blue AI model, a modified version of GPT 5.6-Sol with safeguards adjusted to allow for defensive cybersecurity tasks and vulnerability discovery. Using the model and his know-how, he analyzed the RTX 6000 Pro’s kernel dump to check where things might be going wrong for his MFG mod, directly comparing it to his native RTX 4000 Series integration.

“For 6X frame generation, the GPU will render two real frames, then generate five frames and place them between those two real frames,” he told Tom’s Hardware Premium. Without copying this integration, frame pacing in his existing solution felt odd and disjointed.

“The 40-series-generated frames were all compacted around the middle of the two-frame interval. As you can see [in the image above], what we would expect, and what I measured from the [RTX Pro 6000 Blackwell], was five frames, neatly positioned at separate intervals. However, the 40-series GPU was forcing all of these around the same interval as 2X frame gen would put its one single frame.”

This caused the frame pacing of the MFG frames in the initial mod to feel sluggish, weird, and have poor responsiveness, as frame pacing is crucial in making a title feel smooth, especially when any frame generation tool is involved. “I discovered that the 40-series kernel responsible for motion processing was hardcoded to output a midpoint scaling for 2x only,” Dashdogy described. “With multiple generated frames, that compressed their represented motion toward the middle. With the fix, they spread out much more like the Blackwell reference.”

“The mod can work anywhere normal frame generation is implemented in any game,” Dashdogy told us, with additional telemetry for users to see exactly what’s changing. “The kernel is the same for both 40-series and 50-series; [it’s] just architecture-specific functionality [which blocks MFG on Ada]. 50-series has a number of Blackwell-specific optimizations that I’ve backported as well, and they contribute to better latency overall.”

The modder explains that the frame pacing fix was the most difficult part of the now-universal MFG port to Ada. But after its release, it now sits as a loadable ASI in a game’s directory and controls up to 6X frame generation in supported titles. The project has since been forked by other authors, which plugs the logic Dashdogy wrote into ReShade, a popular graphics mod tool.

Unlocking DLSS 5 NR (Uncle Burrito)

“I’ve been working with 3D art and graphics for many years now,” explains Uncle Burrito, a graphics enthusiast who implemented Path Tracing into Need For Speed Underground 2 using RTX Remix several years ago. “Over the years, I’ve stayed in the RTX Remix community to learn a lot more about real-time rendering and the techniques used for it.”

After hanging out in Nvidia’s RTX Remix Discord channel, news of the emergence of DLSS 5’s nvngX_dlssnr.dll spread like wildfire. According to Uncle Burrito, mods quickly clamped down on discussion of the DLL, and modders flocked to private channels and alternative servers, such as the RenoDX Discord server, to discuss development and integration. The DLL itself was written specifically for Blackwell, but the Ada architecture shares the ability to read FP8 instructions, which is what the DLL uses to load DLSS 5 Neural Rendering’s model weights.

Using that as a starting point, Uncle Burrito quickly went to work. “The model itself is just weights. These weights need code to be executed. The code was only written for Blackwell. CUDA binaries, right?” he explained. But despite this, and the aforementioned difference in ISAs between Blackwell and Ada, certain instructions could not be read by the humbler RTX 4000 series GPUs.

“Four of the 15 CUDA binaries [contained within nvngx_dlssnr.dll] would not run on Ada.” But this wasn’t an impossible task, as Uncle Burrito previously explained. The integration for Ada appeared unfinished and therefore, not entirely impossible. “I simply needed to patch the replacement compiled binaries”, meaning that it only took patching four affected CUDA binaries to get things up and running for RTX 4000 series graphics cards, Uncle Burrito told Tom’s Hardware Premium.

Uncle Burrito, alongside Ghidra, a reverse engineering tool, and an instance of Claude Code, set out to recompile the incompatible binaries to design a patch, but fell into a roadblock made by Claude itself. “I’m not too familiar with reverse engineering myself [...] Claude made the decision to use the incorrect version of the CUDA SDK to compile the replacement [binaries].” And so, the patched DLL ran, but instead output a black screen. “I could see the NR debug banner, and it did affect my framerate, but the output was completely black.”

“This is one of the many pitfalls of vibe coding,” Uncle Burrito said. “You can’t make anything good if you don’t understand what you’re working on. Usually, I don’t give the model any room to gaslight or make a wrong decision. If you don’t know what you’re doing, then don’t expect miracles.”

After realizing the mistake and recompiling with the correct CUDA SDK, the results were quickly posted to the RenoDX Discord server. “Ada performance is about as good as it can get. It has native FP8 support, so the hardware is doing its best. The rest can be attributed to simply not [having] enough horsepower in the chips.”

The simplicity of the patch might appear to be surprising, but the DLL leans on the same information that’s standardized between games and platforms, similar to how Streamline works in most game engines. “Motion vectors and depth buffer are [two] of the few things in graphics programming that we’ve standardized. Almost every modern game produces motion vectors, and rasterization isn’t possible without a depth/z buffer,” Uncle Burrito told us. Therefore, the DLL becomes a drop-in replacement for the officially distributed one, which unlocks the functionality on Ada.

Uncle Burrito’s methodologies were since picked up by RenoDX’s ShortFuse, who then worked on porting the DLSS 5 NR DLL to Ampere and Turing generation graphics cards. That porting work is more involved, since it also includes the translation of the model to be read by FP16 instructions. Following the release of Uncle Burrito’s work, a new DLL has emerged, with universal compatibility between Turing, Ampere, and Ada generations.

Unblocking the software lockouts

Between the MFG unlocker from Dashdogy and the patched Neural Rendering DLL created by Uncle Burrito, the community-made mods both unlock functionality that would not have come to older-generation cards or would have otherwise been added at a later date. According to Dashdogy, “40-series has no excuse” when it comes to support for Multi Frame Generation. “It’s a very small change that allows [the mod] to work,” noting that additional work is being done to recompile things for Turing and Ampere, with the caveat that latency and overheads get higher the further you go back.

“It always comes down to performance,” Uncle Burrito said. “It’s fair for [Nvidia] to not include Ada until they can get the optimization part sorted.” The modder further adds that the situation can be read in both ways, as a method for Nvidia to sell more RTX 5000 series graphics cards, and to have more time to optimize Neural Rendering for older RTX 4000 series GPUs.

Everyone wants to make the most out of their available hardware, especially at a time when consumer graphics pricing has firmly rocketed past the moon, with RTX 5090 GPUs now approaching north of $9,000. “I personally think [the MFG mod] is really important in the current market,” Dashdogy adds. “... many are just getting priced out of the new generation entirely, so giving people the ability to hang on to their GPUs for a little bit longer is going to help a lot of people stay invigorated and connected to the hobby.”

If a single Australian student can unlock DLSS MFG for older GPUs, Nvidia’s claims of hardware exclusivity appear less like a technical limitation and more like artificial lockout. For those unafraid to modify a few simple files within a game, those features are all readily available, albeit unofficially. There’s an irony in how both MFG and Neural Rendering were ported to older GPUs — the development of both mods relied on cutting-edge AI models — powered by the same ecosystem that’s driving Nvidia’s earnings. Now, the very same AI revolution Nvidia champions is being used to tear down its own walled garden.

Average power usage effectiveness (PUE) has barely changed for six successive years, according to the Uptime Institute’s 2025 survey. PUE can show whether cooling and power systems are wasteful, but doesn’t account for whether the software running on the servers is doing useful work. And given servers account for around 60% of electricity demand in a modern data center, while cooling ranges from about 7% in an efficient hyperscale site to more than 30% in a less-efficient enterprise facility, focusing on eking out more efficiency from the software side of the equation seems sensible.

“The answer to what seems to be the core question – ‘Can software or algorithms meaningfully help with power and energy?’ – is yes, 100%,” said Jae-Won Chung, a PhD candidate in computer science and engineering at the University of Michigan and researcher with the ML.Energy initiative, in an interview with Tom’s Hardware Premium.

Chung suggests computing systems should be seen as a stack with hardware at the bottom, backed up by systems software, algorithms and applications. The hardware end of that equation is the hardest bit to tackle: chips are slow and costly to replace. But the other three layers are easier to change, and any gains in efficiency made there can compound.

ML.Energy’s tests of the Alibaba Qwen 3 235B A22B Thinking model suggest that running inference in FP8 – a slightly lower-precision format – consumed a third less energy than bfloat16 versions on problem-solving tasks. Chung’s own Perseus training optimiser identifies parts of a large-model training job that have less work to do, then slows them so they finish alongside busier parts. The system cut training energy by up to 30% without reducing throughput or changing the hardware.

This isn’t a tweak around the edges being made by tinkerers: some of the biggest GPU firms are doing something similar. Nvidia’s Blackwell power profiles fine-tune everything from GPU compute and memory frequencies, power limits, NVLink states and cache settings to fit the workload. Nvidia believes that can save up to 15% of energy while retaining 97% or more of overall performance, allowing power-constrained facilities to run more GPUs, raising throughput by as much as 13%.

‘The loudest rack in the room’

Chetan Visrolia, business development manager for data center infrastructure at SHI, said in an interview with Tom’s Hardware Premium that the most obvious waste he encounters is often legacy equipment supporting old code. “It is always the lowest-hanging fruit for quick savings,” he said. “It can easily be found in any data center, as it is the loudest rack on the floor.”

Cloud instances can also be made a smarter size, and AI prompts that are repeatedly used can be stored in cache rather than recomputed on the fly. There are also efficiencies to be made by getting small models to handle routine requests while holding back the larger ones for harder tasks. At the same time, better batching and compilers can raise accelerator utilisation, and crunching down prompts while throwing limits on outputs can also tamp down the number of tokens processed.

Software can also change when and where electricity is drawn. Sophie Hall, a doctoral student at ETH Zurich’s Automatic Control Laboratory who has studied workload shifting across Google’s global data-center fleet, argues in an interview with Tom’s Hardware Premium that electricity consumption isn’t necessarily the main problem.

“It’s more like: when do they use it, where do they use it, and how is it interacting with the grid?” she said. If batch jobs aren’t time-sensitive, they could be delayed until local demand falls or routed to a region with spare capacity and lower-carbon electricity. Hall’s research uses day-ahead planning and real-time scheduling to respond to grid signals while preserving performance guarantees.

Taking that kind of action was less necessary when hyperscalers built way more capacity than they actually needed and the grid wasn’t a bottleneck, Hall said. But the massive demand for AI has changed the equation.

There are limits, though: individual countries’ data sovereignty rules can prevent a workload from crossing borders, while moving large datasets across networks is something that inference providers may be wary of in case things go wrong. “The data needs to literally, physically, geographically move to a different location,” Hall said. “That’s not that easy.”

The scale of the data center demand powered by AI means that software isn’t a silver bullet or a substitute for better chips and new electricity infrastructure. But it can act as a control layer that squeezes out every last drop from those increasingly expensive assets, while also helping shift demand to places where there is more capacity.

Jevons ’ paradox is also at play, and needs to be considered when thinking about making systems run better. Efficiency doesn’t reduce a facility’s electricity use if each watt saved gets used up generating even more tokens. “Power is the core bottleneck in AI data centers,” said Chung. “We really want to make the best use of every watt we consume.”

And while Black Friday is typically a shopping window associated with consumer tech, it’s also a great time for businesses to snap up a good deal to upgrade their business laptops.

TL;DR

• Black Friday deals promise big cost savings, but if you pick the wrong devices you may end up with a product ill-suited to your needs
• Knowing what you want and need from a laptop before buying is key to getting a good deal, even on Black Friday
• The Dell Pro 3 and Dell Pro 5 offer a strong mix of performance and connectivity, with excellent displays, long battery life, and strong security credentials
• With laptops catering to lightweight workloads and more demanding tasks, the Dell Pro lineup is well suited to a range of business needs and sizes

As tempting as the cheapest models are, they rarely offer the best long-term value for growing businesses. In fact, Microsoft research shows almost a quarter (24%) of IT decision-makers said choosing cheaper hardware ultimately led to higher long-term costs through breakdowns and inefficiencies.

For small and medium-sized businesses (SMBs) concerned about making the right laptop decision, there are several key considerations:

• Performance needs: Choose devices that can handle the unique workloads of you and your employees.
• Battery life: Choose laptops that provide employees with juice to last a full working day, whether traveling, in meetings, or off-site.
• Security features: SMBs are just as vulnerable as large enterprises. Protect company data and employee credentials with built-in security.
• Ports selection: Make it easy for employees to connect monitors, peripherals, or other everyday equipment.
• Display: Choose a display that suits your team’s unique needs, from everyday office tasks to creative work, and data analysis to customer presentations.
• Wireless and cellular connectivity: Give your people reliable ways to stay connected in the office, at home, or while traveling.

Dell Pro 3 and Dell Pro 5 laptops bring together the performance, battery life, security, connectivity, and display options businesses need to support their teams.

What CPU and memory does your business need?

The CPU and memory are two of the most important components of any professional laptop, but the right ones for your business depend on the kind of work you're going to do with them. Both the Dell Pro 3 and Dell Pro 5 are available with Series 3 Intel® Core™ Ultra and AMD Ryzen™ AI PRO 400 Series CPUs, making them excellent for multitasking, even on the more affordable Pro 3.

For everyday tasks like email, web browsing, and office apps, a Dell Pro 3 configured with standard DDR5 memory is plenty. But for more demanding video editing, 3D design work, or heavy multitasking, the Dell Pro 5's optional expandable LPCAMM2 memory, with configurations up to 64GB, can give you a real boost.

How do you choose the right display?

For standard office work, the default non-touch, WUXGA LCD panels on Dell Pro 3 and Dell Pro 5 laptops are ideal. They offer a bright and responsive display, along with smart technologies that help preserve battery life. Optional built-in privacy panels on select Dell Pro 5 configurations help maintain organizational security and personal privacy too, enabling secure, flexible working conditions without the need for additional accessories.

If you're planning some color-intensive or creative work, the Dell Pro 5 also comes with high-definition display options, including WUXGA OLED panels that can help reduce eye strain and offer an accurate image of whatever photos or video you're working with, ideal for creatives.

Dell Pro 3 vs Dell Pro 5 at a glance

What laptop requirements do SMBs need for working on the go?

The two key features you need to consider when you're away from the office are battery life and portability. Both the Dell Pro 3 and Dell Pro 5 range feature some of Dell’s longest-lasting batteries yet, with the Dell Pro 5, specifically, able to last well over 22 hours on a single charge for mixed-use workloads.*

The Dell Pro 3 and Dell Pro 5 are built with mobility in mind, offering a lightweight design that's easy to carry between meetings, client sites, or home working setups.

When comparing configurations, consider:

• Battery life that can cover a full working day
• Weight and portability for commuting, meetings and client visits
• Fast charging for quick top-ups when necessary
• Cellular connectivity for working away from reliable Wi-Fi
• A durable design that can cope with long-term use

How secure are the Dell Pro 3 and Dell Pro 5 laptops?

Dell Pro 3 and Dell Pro 5 laptops feature a range of security features to keep company data safe, and the devices themselves secure from tampering. Quantum-resistant BIOS and TPM 2.0 support keep your workers protected against contemporary malware and theoretical future attack vectors, while the Dell Pro 5 additionally offers Dell SafeID with ControlVault3+ for added protection of passwords, biometric login data, and security codes.

What ports and connectors are the most important?

USB-A and USB-C ports are the most useful, everyday ports you’ll need providing support for legacy peripherals, high-speed data transfers, and device charging. Dell Pro 3 and Dell Pro 5 laptops come with a range of USB ports of both types, ensuring you have plenty of I/O for various accessories and adapters.

For external displays, HDMI 2.1 ports offer support for up to 4K resolution at 60Hz, while RJ45 Ethernet at Gigabit speeds delivers easy connectivity options for business networks.

What about webcams?

Both the Dell Pro 3 and Dell Pro 5 feature high-definition webcams, with the Dell Pro 3 offering up to an FHD (1080p) HDR camera and the Dell Pro 5 providing an upgraded option up to an 8MP (1440p) RGB HDR camera. High-quality video paired with optimized audio can help deliver a professional presence in virtual meetings, ensuring crisp, clear sound for all participants—even when sharing a single laptop.

Do the Dell Pro 3 and Dell Pro 5 keyboards have backlighting?

Yes, both the Dell Pro 3 and Dell Pro 5 laptops feature a backlit keyboard, which makes it much easier to work late into the evening or in dimmer environments.

Can you connect without Wi-Fi?

When you're away from a secure Wi-Fi network, select Dell Pro 3 and Dell Pro 5 configurations can keep employees connected with optional WWAN capability, including 5G, for high-speed internet access wherever they go. Availability varies by configuration and region.

If you think Dell laptops are the right call for your business, find out more on the Dell website: US readers click here.

* Based on testing using the Mobile Mark 30 battery life benchmark comparing Dell Pro 5 14 and Dell Pro 14 Plus, April 2026. Dell Pro 5 14 was tested with Intel® 336H vPro® CPU, UMA graphics, 32GB LPCAMM2 memory, WUXGA Non-Touch OLED display (dark mode) and 70 Whr battery. Dell Pro 14 Plus was tested with Intel® U5 236V vPro® CPU, UMA graphics, 16GB LPDDR5x memory, WUXGA Non-touch Super Low Power display, and 55Whr battery. For more information about this benchmark test, visit www.bapco.com. Actual battery life may be significantly less than the test results and varies depending on product configuration and use, software, usage, operating conditions, power management settings and other factors. Maximum battery life will decrease with time. The stated Watt-hour (Whr) is not an indication of battery life.

This week, Synopsys announced a suite of AgentEngineer tools capable of carrying out long-running tasks that could verify and implement chips, as well as planning analog design and manufacturing. The company said it had more than 50 customer engagements already underway, and planned to offer the tech for general availability by the end of the year.

Synopsys isn't alone in discovering the ability of AI to do such tasks. Competitor Cognichip says its ACI platform can generate specifications and RTL, then automatically produce verification plans and testbenches. And in China, Empyrean Technology recently claimed an AI agent reduced the time taken to complete one circuit layout task from four weeks to one. Even the big AI labs are getting in on the act: OpenAI says its models helped it and Broadcom develop Jalapeño, its first custom inference chip, from initial design to tape-out in just nine months.

It all poses difficult questions for the chip design industry – though not just about whether the sector will remain strong. It’s also about whether AI is a suitable replacement for human ingenuity. The industry relies heavily on intellectual property, and it’s not yet clear what happens when an AI designs something that somebody else already owns. Rather than designing every component of a chip from scratch, companies routinely license processor architectures, controllers, and other memory technologies rather than reinvent the wheel. Arm alone generated nearly $5 billion in its 2026 financial year, which came roughly half from licensing and other revenue and half from the royalties on that. Synopsys makes money that way too, selling a substantial portfolio of "silicon-proven" IP alongside its chip design software.

The AI copied my homework

But by putting AI to the task, some of those blocks could become far easier to create – and working out where they came from far harder. "It mostly amplifies existing problems," said Domenec Forte, professor of electrical and computer engineering at the University of Florida, whose research includes AI-enabled chip-design tools and semiconductor IP protection, in written comments to Tom’s Hardware Premium. "AI can spread a copied design or infringed patent across thousands of chips before anyone notices and without anyone even intending it,” he said.

Copying wouldn’t be as blatant as feeding an Arm core or another piece of proprietary RTL directly into a model. Instead, AI’s skill is in ingesting huge amounts of literature from academic papers and patent applications, then constructing lookalike designs. And in a space where power constraints, performance challenges, and a limited physical area all combine alongside mandated standards all have to follow, there are only a finite number of feasible designs that AI can reach quicker – inadvertently copying others’ homework. "Even a circuit that adds two numbers draws from a well-documented catalogue of textbook designs," said Forte. "Ask for the fastest one, and you'll likely land on a design someone has already published."

That creates a provenance problem for chips, because human engineers generally document and can explain where their ideas came from and which IP was licensed. AI might not have that same traceability. Existing tools can identify close copies, Forte said, but designs can be rewritten or run through synthesis tools that transform their implementation while leaving the underlying function intact.

Forte suggests IP owners could eventually deposit encrypted versions of their designs into a shared repository, allowing trusted agents to check whether newly generated hardware overlaps with existing IP without exposing the originals. He’s less convinced by watermarking, which he argues could be removed or forged. International standards could help somewhat: IEEE 1735 defines methods for encrypting electronic-design IP and managing the rights attached to it. But Forte argues standards like it may now need to go further, defining what AI agents can access, retain, and learn from while operating inside electronic design automation tools.

An abundance of caution

That all might suggest there’s a free-for-all when it comes to AI designing new chips, and potentially ripping off – advertently or not – other designs. But that’s not the case, for a simple reason. The semiconductor industry is unusually cautious about new design techniques because software can be patched, whereas fabricated silicon can’t. “Once you ship the chip, you ship the chip, and you can't change the transistors,” said Simon Moore, professor of computer engineering at the University of Cambridge, said in an interview with Tom’s Hardware Premium.

Moore estimates verification now accounts for more than half of the effort involved in getting many chips out of the door, while established verification tools can tell engineers whether an AI-generated test actually improves coverage. Getting that AI to conduct tests, probe possible failure points, and check results at scale is “a bit of a no-brainer," said Moore. However, allowing AI to make architectural decisions, which are much harder to undo, is where most manufacturers are drawing the line.

That same caution explains why licensed IP may survive the onslaught of AI-generated content, even if the tech is capable of generating technically similar blocks. Buying a block from Arm, Synopsys, or another established vendor comes with the history of the companies, and the assurance that it’s gone through the relevant verification and standards compliance checks.

So could AI reduce reliance on licensed IP? “For routine building blocks, probably yes,” said Forte. “But a licensed IP block is much more than its design files.”

And if engineers increasingly have to ask not only whether a design works, but where it came from and whether somebody else already owns part of it, provenance may become something semiconductor companies are all the more willing to pay for. “I'd treat an AI designer like a brilliant new hire,” said Forte. “Fast and talented, but everything it produces gets checked.”

Synopsys said its spec-to-RTL (Register Transfer Level) workflow shown on March 11 reached “L4,” and the company told Tom’s Hardware Premium it now claims L5 capabilities for its long-horizon agents. Siemens’ agent launched March 16 with “self-verifying” loops announced on July 26. Meanwhile, outside these big three, Empyrean’s chairman, Liu Weiping, stated on Sept. 9 that its agent cut a layout task from four weeks to one, according to the South China Morning Post.

While the claims about what these agents do are specific and now known, what they have measured is not. All of the claimed improvements to speed are the vendors’ or their customers’ own figures, with many “up to” or “early evaluation” caveats. These figures often measure different things against different baselines, and the only evaluator Synopsys named in July, AMD, has not provided analysis beyond an endorsement.

From copilot to closure

In an evolving field, it can be difficult to hit a moving target, especially when the reported numbers measure different things. Some clarity is possible by following the distinct stages from human-only to human-reviewed agent autonomy. The agents fundamentally rely on existing technologies with known desired outputs for accurate evaluation.

Progress has so far followed three distinct generations. At Synopsys, by DSO.ai and reinforcement learning in 2020, generative AI capabilities with Synopsys.ai in 2023, and finally an open agentic AI stack from 2025–2026. All decisions must be validated by proven EDA engines, with the agent focused on evaluating intermediate results and determining subsequent actions. A model’s proposal is examined by an existing deterministic engine such as Xcelium, Jasper, Questa, Calibre, or Fusion Compiler within an iteration loop until final verification.

Measuring progress here does not follow a standard, but there are autonomy ladders with a general rating from Level 1 or L1 to Level 5 or L5 or, in Siemens’ case, no numbered level. Cadence, which uses levels, moves from optimization AI to conversational LLM, complex reasoning, agentic workflows, and then finally full autonomy, defined as taking a design from spec to verification “with minimal human intervention.”

Synopsys’ L framework goes from actions of single agents on a single design step to more complex ones with multiple agents, with further development focusing on adaptive learning and, ultimately, the agent’s ability to make decisions autonomously. The critical part for Synopsys is that “human engineers will and must always be in the loop.” Given the claims of progress, it’s clear that ladders, where they exist, are a form of marketing scaffolding that describes the same underlying architecture or loop.

Specification to verified RTL

The greatest claimed gains thus far are in the front-end design and verification stages, taking a specification from RTL to a verified design. This part of the process is a natural fit for LLMs, as the RTL, testbenches, and assertions are code. Where the loop used to wait on human analysis and input, the agents can run simulations in parallel and make decisions with fast, concrete pass-or-fail answers. These loops already existed and are prime real estate for agents to speed things up, with claimed orders-of-magnitude improvements by moving from human to agent on what is often the slowest part of the process, triage.

Getting from the chip specification to verified RTL code involves generating the code from natural language and formal specification, according to Synopsys’ March release. From there, the agents generate unit-level testbenches and engage in a verification loop. In July, Synopsys claimed RTL validation could be up to 50x faster with a 20% improvement in coverage, compared with its own non-agentic flow.

For Cadence’s ChipStack from February, the scope includes “autonomous RTL design, verification, and debug.” Named early users include Altera, Nvidia, and Qualcomm. ChipStack started as a Seattle startup that was acquired in November of last year after a multi-year integration with Xcelium and Jasper. In June, Cadence said RTL validation could happen over 40x faster, with each engineer using ChipStack agents “to run hundreds of dynamic simulations with Cadence Xcelium ... reducing a typical five-week verification loop to less than a day.”

Siemens’ Questa One Agentic Toolkit, detailed in February, has five separate agents: RTL Code Agent, Lint Agent, CDC Agent, Verification Planning Agent, and Debug Agent. These work with mainstream AI coding applications including Claude Code, Cursor, and Siemens’ own Fuse. Akshay Aggarwal, senior director of engineering for MediaTek, noted “immediate and significant” gains. The numbers from Synopsys and Cadence should be read as the vendor’s own ratio comparison to the old loop, as regression loops are already automated. All three companies are now focusing on the decision-making process. For details on specific claims, refer to the table below.

The back end

Things are tougher when you move from RTL verification to implementation. Outside of specific tasks that look like front-end loops, claimed gains are harder to come by. This phase deals with geometry and physics, not code, and the pace is limited by compute. Some tool runtimes are “days to weeks … just running the tool itself,” and a tool call that takes “hours to days” to return a value “really gives the AI industry a much different problem to solve,” Knoth said. Complex trade-offs remove singular pass-or-fail judgments, and mistakes later in the process become much more expensive. Earlier AI integration also already exists for this flow, so the agentic touch is more on experiment-running. This makes things cloudier.

Cadence’s InnoStack runs parallel experiments from synthesis to ECO execution. ViraStack, which is for custom and analog solutions, handles the design flow from drawing to simulation, optimization, and layout porting, with some customers “reporting 3–10x productivity improvements,” according to a report from Futurum in April.

Synopsys’ looping implementation agents, driving Fusion Compiler directly or through other platforms, help “reduce manual engineering effort,” according to AheadComputing, and Synopsys said they improve quality of results, including timing, power, and area.

Siemens Fuse, meanwhile, coordinates at least nine named tools, including Solido for custom IC design and verification, Aprisa for physical implementation, Calibre for signoff verification, and design-for-test with Tessent. Improvements vary, with Solido mentioned as improving characterization turnaround times by more than 10x and token costs by 5x to 10x, according to Siemens. One third party, STMicroelectronics, mentions that the Solido Layout Analyzer is helping “cut down the time we spend debugging complex design blocks by weeks,” according to Non-Volatile Memory Design manager Gianbattista Lo Giudice.

Empyrean, according to the SCMP’s September reporting, is shifting from “humans operating tools” to “humans commanding agents” with its agentic EDA platform. This platform would work with its partners’ agents. One claim is that 3D verification went “from two to three months to less than a month,” according to TrendForce reporting. Empyrean is the largest domestic EDA vendor in China and is state-controlled as of December 2024.

Self-checking agents

What we inevitably keep coming back to with agentic EDA is one simple term: trust. The agents must be trusted to varying degrees to check their own work. Important checkpoints are still verified by a human: “The crucial approval checkpoints are still going to be human-driven,” Anand Thiruvengadam, executive director of product management at Synopsys, told Tom’s Hardware Premium. Inside the loop, the use of reliable tools such as deterministic engines allows for results that can largely be trusted. Outside of this, trust is based on evaluation, and internal verification is only as good as the tests. There remains reliance on what the vendors claim, and that depends on exactly how each defines the self-checking loop and goals.

The Siemens Agent loop, put simply, is: Plan, Act, Reflect, Iterate, over “Develop, Publish, Execute, Refine.” “Self-verifying” in Siemens’ case means that agents “continuously validate decisions against deterministic, physics-based EDA engines.” According to SemiWiki’s Bernard Murphy, describing the Fuse launch, “the orchestrator can trigger repair agents, then re-run validation. This may resolve most errors,” although we were unable to get any comment on specific triggers.

Cadence’s description is that “every action the super agent takes is anchored” in its own proven design and verification engines, to ensure accurate results. These, like Siemens’ solution, can run “within a secure Nvidia OpenShell sandbox” to enforce guardrails and ensure predictability. This allows engineers to “inspect, guide and collaborate as needed” even at Level 5. The human engineer works from their own runtime environment, then “once the super agent finishes that loop … the auto-run environment can interpret, understand, and then fire off that next message, right, that next iteration,” Knoth said.

Synopsys also retains the human element, with the debug workflow’s output as root-cause analysis and resolution through engineers. The flow iteratively runs checks against generated, unit-level testbenches, with the agent handling design and the tests themselves. When a check fails in Synopsys’ Verification AgentEngineer, the logs are consulted, and errors are aggregated to paint a picture of the most likely cause, checked against simulation waveforms. When applying the fix, the agent must prove that the bug has actually been fixed and should be able to produce a bug-fix manifest. Beyond this, the quantity of checkpoints is determined by customers’ trust and desired flexibility, and over time, “they might relax and take away those checkpoints,” Thiruvengadam said. The internal process, such as the specifics on retry limits, the definition of unfixable, and states requiring escalation, remains murky.

Early access everywhere

All of the numbers and roadmaps in the world don’t replace actual value to the customer, or actual customers with a released product. Thus far, the agentic platforms have been in early access and evaluation. Engagements have been listed, and major customers exist, but none are confirmed with a generally available product. General availability hasn't arrived yet, but it has been promised by the end of 2026 by Synopsys, with Cadence’s AuraStack, its PCB and advanced-packaging agent, also due this year. Usable products and workflows exist, but the efforts remain nascent, despite relatively rapid claimed gains over the last year or so.

Cadence ChipStack has been in early access since February. In June, this extended to the promise of Level 5 capabilities with early access for customers in the second half of 2026. Synopsys has debug and implementation workflows, announced in July, available for evaluation on Microsoft Discovery, if requested. Microsoft’s platform is designed to assist in the construction and management of agentic AI workflows related to scientific and engineering fields. Siemens has the Questa One Agentic Toolkit, announced in February, and the Fuse Agent as of March, with promises made in July surrounding self-verifying capabilities in forthcoming releases. Empyrean is also developing its own platform as of the time of writing.

The current stacks largely run on Nvidia’s Nemotron and its OpenShell sandbox. Nemotron is a reasoning model family. OpenShell is an open-source runtime that keeps the agent contained with kernel-level isolation, protecting customer IP and guarding against rogue actions. Nemotron and OpenShell are open, so nothing on record prevents Empyrean from using them, but without announcements, it appears to be the outside case. What each EDA vendor does with this technology and the flexibility it offers its customers are the defining differences.

Earlier this week, Nvidia announced its Open Agent Safety Platform, a combination of OpenShell and the Sentry reference design, an “out-of-band watchdog” that runs on BlueField-4 DPUs to “continuously monitor agent behavior” and can quarantine an agent in milliseconds. Cadence, Synopsys, and Siemens are named among the more than 100 organizations working with Nvidia on the platform. Cadence’s Knoth told Tom’s Hardware Premium that OpenShell “helps ensure the agents are well behaved ... don’t go rogue and start accessing data they’re not supposed to,” as agents need to become productive and trusted. Thiruvengadam from Synopsys echoed these sentiments, with both companies aware of the dangers of rogue agent actions.

Cadence and Synopsys, at least, needed licenses as of May 2025 for EDA sales to China, but the requirement was rescinded as of July of that year. EDA is expected to be critical for the industrial software space “toward the high end of the global value chain” by 2030, according to ChinaTechNews. According to Liu, as reported by the SCMP, Empyrean is trending away from traditional software licenses to a token-consumption pricing model with agentic EDA.

Startups in this space include ChipAgents, Cognichip, Agentrys, Silimate, and Ricursive Intelligence, most funded since December 2025. The big three buy other companies, from startups such as ChipStack to simulation software maker Ansys, as advances put EDA in the spotlight toward the end of 2026. Even with platform-specific flexibility, Nvidia remains the common ground, with its open model family and sandbox being the standard across the big three.

As it stands in 2026, the agents exist, and there are real roadmaps and customer evaluations. The framework hinges on existing technology already worthy of trust. The overall trend is toward harness engineering and, as Knoth told us, the implementation of “an array of specialized engines” to fuel the workflow end to end. Improvements, although currently lacking the independent measurement and precision we would like to see, are real and accelerating, according to vendors and their customers. It will become increasingly important to have proper evaluation of the different agents as they approach Level 5, “L5,” or some equivalent marker that denotes autonomous action.

What we would like to see by the end of the year is some customers named to actually be using the highest level of agent. Specifically, these agents must live outside of a trial or early access mode. This enables oversight and comparison in what will become an incredibly important field. We also anticipate Siemens’ forthcoming releases, which may demonstrate the self-verifying loop. Cadence is worth a close watch to see whether a Level 5 early-access customer is named before the end of the year. The baseline, though, is at production: real customers, real workflows, real products, and a measured improvement.

The following article is a full transcript of our interview with Richard Ho, which has been edited for flow and clarity. You can also read additional interview transcripts we produced earlier in the year, featuring Intel, AMD, Nvidia, Valve, and more. This transcript is free to access for a limited time as part of Tom's Hardware Premium's AI Chip Design Week.

Jake Roach, Senior CPU Analyst, Tom's Hardware: It was quite the ending to Hot Chips when you dropped this. I want to start at a high level. There are a lot of reasons for OpenAI to develop its own ASIC, but was there one thing that you could point to more specifically that was a driving force? Whether it’s performance, efficiency — what was it that really drove that decision?

Richard Ho, VP Hardware, OpenAI: It is efficiency. I think that’s the main thing that we’re aiming for, because obviously, as Sam [Altman] has been saying, we are going to be compute-limited, and a compute limitation is really how much power we can get into data centers.

What we want to do is be as efficient as we can with the limited compute and limited power that we’re going to be able to get, and make the most of it. Because what we really care about is how much intelligence we can deliver to the users, and having a more efficient inference device is very useful. That’s why we focus on inference, because training happens, and you do a lot of compute with the pre-training, but really the cost to the user is on the inference side, and their perception of intelligence is going to be there. Their user experience in terms of how fast ChatGPT responds, or how fast Codex responds, or how fast the agents respond — the latency really matters.

You can see all of those things in the ingredients of what we announced. You can see that we have both a very good low-latency device for those who really care about it, and we can very easily just turn the knob and get very good throughput, so you can reduce the cost of that inference. Really, that’s the thing that we were aiming for. I’m very happy that the team managed to deliver that.

The benefits of building in-house

Roach: Developing your own ASIC versus going with something that’s currently on the market— were you just not satisfied with the efficiency of current offerings?

Ho: Well, I wouldn’t say that. The way to really think about it is we wanted to take advantage of the co-design opportunity that we had. It’s something that you can’t do with a third-party silicon merchant really well, because there’s a lot of research IP in the models. You just can’t share that widely because it will leak. It will get out there no matter how many NDA’s you put in place.

Ho: Having an internal team being able to work with our researchers, who are able to have full visibility into the full stack, and take care of that: “Should we do this in the software? Should we do it in the model? Or should we do this optimization in the hardware?” We can make those trade-offs intelligently because we have that full visibility, and I think that’s where it comes from.

A lot of the benefit of Jalapeño is that visibility that we had and [we were] able to see exactly what hardware was needed to make those trade-offs. Be intelligent, put whatever we need to put back into the compiler, back into the stack, but really make the hardware fly for this particular application here, which is the outcome of this full-stack co-design opportunity of being inside OpenAI.

Roach: I did want to clarify some points here, because there’s been various quotes floating around about optimizing for this specific workload, and I think that has been maybe misattributed to optimizing specifically for OpenAI’s workloads.

Ho: Yeah, it’s misattributed. The whole point of using the InferenceX benchmark from SemiAnalysis was that it was (using) open-source models, and they’re different models. The architecture is different, and their sizes are different. What we really wanted to demonstrate, to put to rest, the misperception in the industry that our custom inference chip was only for OpenAI models — we’ve shown with the Hot Chips results that it flies on open-source models, flies on any LLM, in a sense. All transformer-based LLM models will be very performant.

The thing we also wanted to show was just how easy it was to program. Taking these models, which we did not even look at until after we got the chip back, and getting them up and being performant in two months, roughly, and being able to present the results, shows it’s programmable, it’s general-purpose, and it’s not hard-coded for OpenAI models.

Roach: It leads me to wonder: Jalapeño is obviously for OpenAI’s inference workloads. Is that all it’s for, or are you considering external customers? What is the plan with OpenAI hardware?

Ho: You could use it for anybody, honestly. But we have such a strong demand for compute within the company. It’s going to take us a good long time to even fill our own demand, which is growing all the time.

With the growth of the daily active users and weekly active users, with the new models, with the new capabilities of Codex, and all the other reasoning things that are going on — and there’s new announcements coming that [are] not out yet, but we kind of know internally — I think that we’re going to have our hands full just providing compute for OpenAI for a good long time. That’s not to say that it can’t be used elsewhere. I believe it could be, but I think our priority is to make sure that OpenAI’s compute needs are met first and foremost.

Inside the tools and timeline

Roach: Moving to the timeline, it’s remarkable that — what, nine months, I think it was, to initial RDL the tape-out? Really remarkable. Assisted by AI. Does that get faster? Is this kind of ground zero of what we can do with an AI-assisted design process? Are you able to move quicker as you ramp up your roadmap?

Ho: The way I like to think about it is, we’ve established a new baseline. In the old baseline, you’re talking 18 months to two years, roughly. Often that’s even with some existing IP or some more legacy architecture design. We’re starting from scratch here. We had nothing. There’s not a line of code here to refer to.

What we’ve established is that there’s a new baseline that you can do with a very talented team with the help of AI. Now, does it get shorter? It depends on what you’re trying to do.

With Jalapeño, we made some, I consider to be, smart and pragmatic trade-offs on the architecture, the microarchitecture, to hit a very fast time to market because the compute need was so high. It’s like, “Okay, how fast can you get this device for us?” There were some pragmatic trade-offs.

If you were to make a much more complex device — and technology is coming along, with 3D stacking, with co-packaged optics, and stuff like that — will it take longer? Will it take nine months? I won’t say it will take nine months. I think it will go faster than if you didn’t have AI models. If you’re doing a derivative design of Jalapeño, it should go much faster than that. We should be able to do that really, really fast.

What we’re saying is that I think we’re establishing a new baseline: nine months from scratch. Then you’re going to have your usual engineering ups and downs from there. But we think that every engineering team in chip design should be able to use this as a new baseline, because it’s a proof point that the models that are in use — the AI models for us is mostly Codex, Sol, the one before Sol, and now we’re moving on to Astra. These are super capable.

Even from when we started that work, back in November 2025, to when we taped out, the models improved enormously. Even from that moment to when we started doing the kernel optimization in May, when the chips were first coming online, we ourselves were shocked at how much better Codex was and what it could do.

I’ll be honest with you: We were actually a little bit surprised at the performance we were able to squeeze out in those two months of sprinting on the benchmark, because we just didn’t realize just how good the models were at doing kernel optimization.

That’s something that everybody can learn from, to be honest. It’s a proof point that it can be done. This is how AI should be used. We didn’t replace our engineers; they just became super productive. With a smaller team of really good engineers with a lot of this AI stuff, you could do things faster and better than you could otherwise. I think that’s a good model of how engineering should be approached in the AI age.

Roach: I appreciate that insight. I know for at least some of our readers at Tom’s Hardware, the idea is, “Make me a CPU” in ChatGPT, and then it spits something out. But obviously, a lot more has gone on.

During the development process, are you using standard EDA tools from Cadence and Synopsys? And where are those?

Ho: I think this is super important. In general, my team is very open-source-pilled in many ways. We actually put stuff back into open source, and we were open-source-pilled before we got here.

But for sign-off, you need to use the standard EDA flows, and we did, because you want to make sure those results are good and correct. There’s no real alternative today. Part of it is this combination of standard flows optimized with AI, optimized by really good engineers.

Interest from the wider industry

Roach: Obviously, you guys work with hardware vendors across the industry. I’m curious if you’ve had conversations with them post-Jalapeño reveal about this AI-assisted process, and if you’ve heard anything from them.

Ho: Yeah, we engaged with them before the reveal as well because we knew the results were there, so we started talking with some of them. Post-review, we did get a lot more communication with them.

I’m not going to preempt anything here. I can tell you that there’s a lot of interest in the industry, and I would also tell you that we feel that there is a lot of benefit in industry generally that we want to enable.

This is not something that, “Hey, we have this, and we’re going to keep it to ourselves.” It’s not one of those things. We want to make the industry more productive in general because better compute from everybody helps us as well, and so we want to make sure everyone gets it. I think that’s something that we’ll see more about quite shortly, to be honest.

Roach: Just to clarify, when you’re saying you’re seeing interest from the industry, that is for the design flow, how you built the chip, not necessarily, “Hey, we’re going to throw out a bunch of Jalapeños to everyone.”

Ho: Right, exactly. What we did to make those timelines, what we did to get the performance boost at the end. How did we do it? What did we use? I think those are learnings that we want to bring out to the industry as well.

As you probably are aware, there is a pretty active startup scene around AI for chip design, and it’s good. There’s a lot of smart people thinking about it and trying to do it. We have our take on that, and I think at some point we want to tell the world, “Here’s our take on it.”

Fundamental to that is Codex and GPT-6 Astra coming out. Those are fundamental, and we can basically point to it; it’s not going to be slideware or vaporware. We can point to it and say, “Here’s what we did, here’s how we did it, and here’s what we got.” It’s going to be very concrete.

Roach: So it was a proof of concept that ended up being quite a bit faster than expected?

Ho: Yeah. To be honest, the way it worked — and I’ll give you a little bit of insight — our engineers were just like, “Oh, we have these models, and they’re kind of cool. Should we try them?”

They tried them. There was no real “This is what we’re gonna do, and here’s how we’re gonna do it.” They just tried it at a grassroots level. Then they’re like, “Oh my God, it’s so good. Hey, come over here, have a look at this.” Then slowly the whole team got, “Oh man, this is really useful and really good, and here’s how we’re gonna do it.”

The researchers helped us. The researchers we have in the company helped us when we ran into some, “Oh, it doesn’t quite do it this way,” and we’d ask them, “Is there any way we can fine-tune it or something like that?” Then they would come back with replies.

It was really a collab between the chip team and the research team. We do sit with them. The chip team is actually considered part of that research-adjacent organization here within OpenAI. The collab has been really close, because that’s how we got the co-design to start with.

But then this part was almost a bonus. We didn’t set out necessarily to do this as a target for what we did. It just turned out that, “Oh yeah, this is really useful.” The engineers loved it, and now we have a way to do this.

Roach: I want to zoom out a little bit here, because one of the concerns with everyone right now is supply, just in general. Not only supply, but even space to do anything. Where are you with that? I’m assuming you’ve anticipated this situation and have secured your supply.

Ho: It’s a hard situation because supply is very limited. I don’t want to say, “I told you so,” but two years ago, Sam (Altman) and I were doing a tour around all the different fabs and suppliers. I went to say, “Please, please, please build more, build more. We’re gonna need it.” And they were like, “Hey, trust us. We’ve seen the cycle before.”

But I think it’s now become evident to everybody that, just like we were talking about, there’s a new baseline for how to do chip design. There’s a new baseline for supply and what we need in terms of memory, in terms of logic wafers, in terms of all the rest of the components that go into it, SSDs and everything else. The supply chain is responding, but it takes years to get that going.

We’ve seen this for a while, and so we’ve been active in trying to make sure that we have our supplies established and set up. We think we are in good shape for that.

Using Turing over Vera, and OpenAI's north star

Roach: I cover chips broadly at Tom’s Hardware, primarily focused on CPUs. We have someone who focuses more on graphics, and it was interesting to me to see — I was reading the SemiAnalysis article about it, about the Turing rack that goes alongside a Jalapeño rack.

What was the decision there for Turing and not Vera? I would have expected, given the close working relationship between Nvidia and OpenAI over the years, I would have expected Vera. What makes Turing the right fit?

Ho: The way we approached that design was really in terms of de-risking and being able to do that design fast. Vera, as a standalone, is a little bit behind on that maturity level. The Turing device is strong. It did what we needed to do, and partly our partners had some experience with it.

It wasn’t necessary for us to take a huge risk on that, and so we didn’t. As I said earlier, for the Jalapeño program, we were trying to make very pragmatic decisions. We wanted to be aggressive on the goals of the performance and the cost, but we didn’t want to take unnecessary risks. That felt like a good design decision that would fit within the parameters of how we make these design decisions.

Roach: I’m curious internally: Is the scope of Jalapeño right now — you have a huge compute need. It may not even be able to satiate that. Would the idea be, “Hey, if we can run everything on our own accelerators one day, that’s great”? Is that the ultimate pie-in-the-sky goal?

Ho: I think the ultimate goal is to use the best device in terms of performance and cost. If it turns out that it’s our own internal device because we can do the co-design, because we can do the rest of it, and we then get the performance benefit per watt, then yeah, let that be the case.

But if it’s not, if there is another chip that’s provided by a silicon merchant or another partner, I’m more than happy to put those in the fleet. Our goal is to lower the cost of infrastructure. That’s what our goal is. Whatever the best way to do it is, we’ll do it.

Now, we’ve taken a bet that we can do better than merchant silicon because of this co-design benefit, and it seems to be paying off with Jalapeño. Will it continue paying off? I believe so. But am I going to say that’s our north star? No. I’m going to say our north star is the lowest cost of infrastructure we can get.

Roach: I wanted to ask you the question because I know we’re going to get comments about, “Oh, they’re still using Nvidia. They’re still using AMD.” Obviously, you guys use everything at this point.

Ho: We use everything at this point. But as you know, it’s a constant — you can’t imagine — it’s a constant evaluation. We’ll constantly be evaluating as we continue to deploy, and so the ratios might change.

But as long as we keep that North Star in mind, what is the best device, and not have this attitude of, “Well, we built it, so it has to be there” — and that’s not the way we think about it — then I think we’ll be doing the right thing for both ourselves and our end customers.

Speculative decode and performance on Jalapeño

Roach: Drilling down a bit more into the technical weeds — I know we’re running up close here — speculative decode is currently not implemented on Jalapeño. Do you plan to implement it on Jalapeño?

Ho: It’s implemented in the hardware. The only reason we didn’t benchmark it is that we didn’t have the time to train those draft models to do the speculative decode with Jalapeño. We have internal models that do it. That’s the only reason we did that benchmark again.

Just to give you the background on that one. We did not plan on doing this benchmark until after we got the chip back. We saw it was working; it was working really well. They said, “How are we gonna tell the world about this?” And we said, “Oh, that benchmark. Let’s go for it.”

It was crazy. It was two months until the paper deadline — the presentation deadline. Just like, “Can we do that? And how many of these models can we get done?” We just went for it, and we said, “Well, there’s no time to do the multi-token prediction, but hey, it looks like our single-token prediction might be better than the multi-token prediction. So let’s just publish those results, because that gives you an indication.”

The multi-token prediction is going to be 3-5x performance. That’s in our pocket. We have that available, and we’re going to roll that out in our own models. When we put it into production, we’re going to have that available.

But it didn’t seem necessary to do that for the benchmark, because if your single-token prediction is better than the current state-of-the-art multi-token prediction, you know that your multi-token prediction is going to be much better. That was the reason behind that.

Roach: So you’re saying you get the chip back. You have two months. You weren’t even planning to show off benchmarks originally?

Ho: No. The Hot Chips organizers were actually very flexible and nice. They asked us, “Do you want to present this year?” And we said, “We’re not sure. How late can we tell you?”

They had this last slot, and they kept it there. And if not, the program would have just ended earlier or something like that. Then finally, very late, after we got the chip back, we were like, “Can we have it?” And they said, “Yeah, go for it.” And we went for it.

Roach: Another question I had is looking at longer context windows. If I’m not mistaken, all of them are 8K/1K on the SemiAnalysis InferenceX benchmark. I know you haven’t shared those. I’m assuming you’ve looked at longer context windows internally.

Ho: Yeah, internally, of course. Like we said, I think we said this somewhere in one of the slides, is that on internal models, the gap gets even wider. Yes, with longer context, with even bigger models, Jalapeño seems to perform even better than the existing benchmark from some of the other devices that are available.

I would also highlight that we did a lot of comparisons against Grace Blackwell, but that’s because those were the best published results that we could find. Obviously, by the time we deploy, it’ll be Vera Rubin, maybe even Vera Rubin Ultra in some parts of the deployment schedule.

We’ve done our internal ones, but obviously we don’t publish those. Those have to come from Nvidia and other people who are able to do that. We won’t publish those results ourselves.

Ramping and the future

Roach: I believe this is right — Jalapeno has a slow ramp-up through the rest of the year, but 2027 is when the ramp really...

Ho: 2027. Yeah. I think we want to get some amount in there if we can, a very small volume, just to make sure that everything’s working well and we can test in the production environment. Then 2027 is when the ramp is going to really show up.

Roach: Going back to your roadmap here, you wanted to set a new baseline. You’ve obviously announced two more generations [...]Gen 2 is approaching tape-out. Is that the same cadence moving forward? Is it around Hot Chips next year when we should expect to learn more about Jalapeño 2?

Ho: Let me be clear about that. I’m not of the opinion that you should just tape out on a calendar schedule.

We want to tape out when the device that we have in mind makes some kind of step-function improvement in some way, like performance per watt, raw or latency. A lot of that is dependent on when technology becomes available.

Whether it be which generation of HBM you’re using, which type of SerDes you’re using, or whether you can get optical communication closer to the silicon. Our projects and tape-outs will be dependent on the maturity level of the technologies.

We can do very fast execution. Will we do those types of executions back-to-back? I doubt it, because the technology will not be ready for that, and I don’t want to tape out something that is 2% better than what I taped out before, because it’s not worth it to change a fleet. But what I’ve been seeing is the technology does improve at a cadence which is pretty reasonable, and we’ll be able to do our execution fast within that.

The most important thing is building the right device. You've got to spend enough time to build the right device. Know what that device is. Then when you build it, just build it fast. Get it out as fast as you can.

But you need to spend enough time to know what’s the next best device, and it’s not just a routine on the treadmill type of thing. That’s the thing I don’t think we want to be on the treadmill for, just for the sake of it. We want to really make a step improvement with every device we do.

Roach: One of the most interesting slides to me is really early in the presentation, where you’re listing out goals, and not only goals, but you listed out the non-goals. I thought that was really telling, because you got to define what you’re not trying to do.

Ho: Exactly. We want to be very thoughtful about our program here because we are a very small team. The things that we do, we want to make a really high impact, and the impact is for the north star: enabling more intelligence, more cheaply for our customers. That’s the thing we’re trying to do.

We want to be very thoughtful about what it would take to do that. As I said, if something can be provided by the ecosystem, and we can’t do better than that, then we just take the ecosystem.

We’re going to always do something that we think is taking advantage of our co-design, taking advantage of our knowledge of where things are going, and being able to use that intelligently.

[Session Ends]

Old parts get a new life, with some patient tweaking

First off, we recently tested AMD’s BC-250, a 2021-era APU that started off as defective or cut-down PS5 silicon, repurposed as a cryptomining card. But more recently, a community-developed BIOS and drivers have turned this custom hardware into a Linux-based competitor to Valve’s much-hyped Steam Machine, while costing roughly half the price of a similarly configured system, once you source the power supply and other necessary parts. It even comes with 16GB of shared GDDR6, sidestepping the current RAM pricing issue altogether.

Now, this is more of a project than a PC. You have to source the card (from places like AliExpress, eBay, or Etsy), then research and figure out how to flash the board so that it will even boot, followed by getting Linux and the requisite drivers installed, before you can even think about playing games. But depending on your sample, you might also be able to unlock extra CPU cores and compute units for even better performance.

It’s far from a simple setup. But this kind of community-led hardware repurposing and enhancement reminds me of two distinct hardware eras: The very early days of PC kits (which I wasn’t really around for), and the early 2000s, when you could unlock AMD Athlon and Duron multipliers with a pencil (or later, conductive silver lacquer). Unlocking higher clocks and extra performance without paying for a much pricier chip is exactly the kind of achievable dream that the PC enthusiast hobby was founded on, and it’s good to see it making a comeback – even if it’s with this one very specific piece of hardware.

But as AI hardware development continues — and especially if (or when) specific areas of the hardware bubble pop or deflate – I expect to see more situations where communities of tinkerers figure out how to get discarded hardware to run games and other compute tasks, giving budget buyers hope for acceptable performance at reasonable prices. Ironically, AI tools like Claude Code will almost certainly make breakthroughs in hardware repurposing much easier.

To boldly go (to price brackets) where no PC has gone before

On the other end of the PC price spectrum, I recently assembled a PC using parts from Asus’ ROG Edition 20 line. The anniversary hardware, which debuted earlier this year at Computex, ignores affordability concerns entirely. Asus instead opted to celebrate two decades of its Republic of Gamers sub-brand by taking several of its already expensive parts and peripherals, adding a few (mostly aesthetic) features and some gold accents, and charging even more for them.

How much more? The finished PC, with about $2,000 worth of peripherals, a $3,300 motherboard and cooler combo, and a $6,000 RTX 5090, costs roughly $15,000 – and that’s with a modest 2TB SSD and 32GB of RAM. If you opt for a more fitting 128GB kit with tight timings and 8TB of solid-state storage, you could easily spend $20,000 on a build like this.

As tough as it is for many of us to swallow, there’s likely a large enough customer base of gamers and PC enthusiasts who can and will pay whatever it takes to own high-end, high-performance PCs to keep options like this afloat. Because while the cost of individual parts has certainly increased, the luxury PC market has existed for decades. I know because in the years before I joined Tom’s Hardware, I reviewed several PCs with custom cooling loops and multiple graphics cards (up to quad-SLI) from the likes of Digital Storm and Maingear. That market isn’t going away; it’s just getting more expensive.

The murky future of mainstream desktop gaming PCs

So what about the mainstream PC gaming market? Things are tougher there, and I suspect that space will continue to shrink due to, well, everything I linked to up top. Those looking for gaming options in the sub-$2,000 range that “just work” without much tinkering are more likely to make do with consoles (which are, of course, also getting more expensive), gaming laptops or handhelds, or console-like PCs like Valve’s Steam Machine.

Intel and AMD are reviving or extending the lifespan of chips and platforms that support last-gen DDR4, but older memory isn’t getting any cheaper either. And our own testing has shown that DDR4 is increasingly holding back gaming performance.

There was a brief hope that Chinese memory makers like CXMT might help bring down DDR5 prices. But U.S. approval for that seems unlikely, especially as the FCC is busy banning humanoid robots and robot vacuum cleaners built overseas. And, of course, companies like CXMT aren’t looking to be PC saviors. They want to sell their RAM to AI hyperscalers for the same high prices as SK hynix, Micron, and Samsung. And even if DDR5 somehow suddenly became more affordable, GPU prices are also continuing to climb, and storage (SSDs and hard drives) faces similar pricing issues.

Can software save the day?

Like it or not, we’ll certainly see further advancements in AI upscaling and other VRAM tweaks and tricks that make modern gaming possible on older and current-gen cards with 8GB or even 4GB of VRAM before the price of RAM, storage, and GPUs drop significantly.

Will it be enough to keep PC gaming enticing and affordable enough to prop up the mainstream PC gaming market? That’s tough to say with any certainty at this point, but if being a PC enthusiast since the 1990s (and a PC gamer since the late 1980s) has taught me one thing, it’s that this hobby is resilient. Some will pay what they need to pay for high-end hardware. Some will find suitable solutions by tinkering with repurposed silicon. And others will forge a middle ground that works for them.

I transitioned from a PC enthusiast to a full-time professional covering the PC and related hardware space in 2008. Even back then, people were telling me that the desktop was dead or dying. Instead, it has evolved and survived for nearly 20 years, through the smartphone revolution, past soldered-on laptop components, through two cycles of Steam Machines, and the death of physical game media. Meanwhile, game stores like Steam rake in record profits, indicating that the demand for PC gaming remains high. All this tells me that PC building and PC gaming will need to continue to evolve, but it’s not quite on the endangered hardware list yet.

But despite being a world away from GPUs, the price of these often overlooked chips is skyrocketing, thanks to the all-encompassing memory price crisis caused by the AI boom.

While public and press attention has focused on the expensive chips, there’s an equally large impact beginning to be felt on older, less attractive memory chips. HBM is vital for AI accelerators, while DRAM and high-capacity NAND are being swallowed up by rapidly expanding data centres. A June report from Morgan Stanley reckons memory prices have risen more than sixfold over the last year, breaking with decades in which memory became steadily cheaper as production increased.

It’s not just HBM and DRAM that’s being affected. The crunch is also spreading down into much older forms of memory, including NOR flash and single-level cell, or SLC, NAND. Morgan Stanley expects NOR flash to remain undersupplied through 2026, while JPMorgan has warned its forecasts don’t fully capture a potential supply crunch in SLC NAND. The effects are already showing up in prices. TrendForce says contract prices for both NOR flash and SLC NAND rose by more than 100% during the first half of 2026, while it expects SLC NAND prices to rise another 120% to 170% in the second half of the year compared with the first half.

Picking winners

An increase in prices will have an impact on the tech we use day in, day out. NOR flash is commonly used to store boot and program code, and is a core part of automotive, industrial, and networking equipment. SLC NAND is deployed across a number of uses because of its reliability and endurance when placed in embedded hardware with long lifespans.

Both are vital. And both are being overlooked in favour of higher-margin chips — pushing the supply crunch to tech that previously never faced any issues. “The SLC NAND market is probably under a billion dollars a year,” said Jim Handy, a semiconductor and SSD analyst at Objective Analysis, in an interview with Tom’s Hardware Premium. That tiny scale adds up to a big problem, because it disincentivises any new investment.

“What you've got going on is a purely economic phenomenon,” said Handy. Hyperscalers and cloud providers are “all trying to outspend each other”, pouring unprecedented sums into semiconductors to build AI infrastructure. That willingness to spend big means the most profitable customers naturally move to the front of the queue.

Companies including Nvidia, Broadcom and Marvell need huge amounts of semiconductor manufacturing capacity for chips destined for AI systems. “They’re sucking up all of the wafers,” says Handy. “And then the companies who make NOR flash and SLC are having a hard time getting wafers to build their product, and so they have to raise prices.”

The problem is even starker in the NAND market. Bryan Ao, research manager at TrendForce, told Tom’s Hardware Premium in an interview that major NAND manufacturers, including Micron, Kioxia and SK Hynix, have been cutting the wafer capacity devoted to SLC because they can make considerably more money using it for newer NAND technologies. Ao estimates that a 12-inch wafer devoted to mainstream NAND can ultimately generate close to $20,000 in revenue. Use the same space to produce SLC and the figure is closer to $6,000 to $8,000.

Even if they wanted to, smaller SLC suppliers in China and Taiwan can’t just spin up new production. Lead times for some semiconductor manufacturing equipment have stretched to between 12 and 15 months, said Ao. The result is what he calls “severe undersupply”.

Big prices, big returns

BNP Paribas forecasts the average NAND price will hit $279.50 per terabyte during 2026, up from $73.10 in 2025. JPMorgan expects the memory shortage to persist for at least another two years, with customers getting just 70% to 80% of their orders fulfilled. TrendForce says manufacturers are shifting capacity towards advanced, higher-value memory products, with mature processes increasingly squeezed as a result.

There are some alternatives available. Kioxia says its serial SLC NAND is an alternative to NOR flash. But moving an existing industrial or networking product onto a different chip can itself require engineering work and qualification. Nor is there much incentive for memory manufacturers to fix the problem by building new SLC capacity – which means manufacturers are unlikely to invest billions in capacity whose useful market may disappear. That creates an unusual trap: there may not be enough demand to justify new factories, but there is still more demand than the shrinking supply can satisfy.

Hardware manufacturers can eat the higher component bill and accept lower margins, or pass it on. “We'll just have to either have lower margins, or we'll have to raise the prices to the consumer,” Handy said.

An ongoing issue

The problem is one that seems to have no solution – at least in the short term. Ao expects memory prices to remain high over the next five years and does not expect them to return to 2023 or 2024 levels. That broadly fits with the structural nature of the shortage identified by TrendForce, which says there are no significant capacity expansion plans for NOR flash or SLC NAND.

Handy sees one possible way out, but it is hardly reassuring. “As long as the race between the hyperscalers keeps up to spend, then it will continue to be an issue,” he said.

Handy compares the AI buildout to the internet infrastructure boom of the late 1990s. Rather than enough capacity eventually arriving to restore balance, he thinks spending may simply overshoot what the market can economically support.

“I'm expecting the same kind of a thing to happen here that we've got too many people spending too much money on AI, and not really making any return on it yet,” he said.

Until then, the least exciting memory chips in a computer may become some of the hardest to replace. Or, as Ao put it: “Pretty much we have to get used to this high price, no matter which segment of memory.”

Like previous Valve launches, you can also read transcripts of our interviews with the company on the Steam Machine and Steam Controller.

The transcript below has been lightly edited for clarity.

Brandon Hill, Tom's Hardware: What were your goals in creating the Steam Frame and providing the framework necessary to support it, compared to legacy hardware like the Index?

Jeff Leinbaugh, Software Developer, Valve: Yeah, so the work started on Steam Frame basically as soon as we shipped the Index. And so we did a lot of exploration into technologies and features and use cases to try to answer that question. And the goals that we aligned on for what became the Steam Frame was to make [it] much easier to use, which to us meant a lighter, more comfortable, easier to get into and out of VR headset.

That was a better way to interact with your whole Steam library than the goals we had for the Index. Where the Index was just: we wanted to make the best possible VR headset that we could make. And that came with a lot of compromises, which were worth it because they allowed us to have this really great VR headset and see what that was capable of.

But this time around we thought we could achieve something that was a lot more comfortable, a lot more accessible. And so streaming technology was a big part of that. So the headset can be wireless so that there's not a lot of complicated setup to get to the game, whether that's playing on the headset or streamed.

And then the other big part of that accomplishing that goal was making it possible to interact with Steam just like you would on a Steam Deck and to be able to play games that don't even support VR in a virtual display. So what we want to be possible is for somebody to put on the headset, browse their Steam library, and then just pick something that they want to play and not worry about too much else.

And that's kind of where all the user experience goals, at least, came from around this. And then there's a lot of other technical goals that support that we can get into if you're interested in any of those.

Hill: So, that leads into my next question: what were the engineering challenges in making the Steam Frame a standalone device and one that can also stream? And I know you've got the wireless dongle to help with the networking offload.

Leinbaugh: Yeah, a lot of the engineering challenges were around making sure that we had the right kind of compute, and enough compute on the headset to both support a really good streaming experience, but also to be able to run games on the headset.

So we picked the Qualcomm 8650 chip. It had a lot of capability, but in order to make use of that, we had to solve a lot of engineering challenges around thermal management and power delivery.

So really treating this like making a really capable PC that just happens to run this particular [...] mobile hardware was how a lot of the engineers approached that problem.

And then from there, we kind of tied that into a lot of the work that we did for Steam Deck and Steam Machine running Steam OS now on ARM, but it's the same Steam OS.

So at some point we got to kind of meet in the middle and leverage Proton and Steam OS and a lot of things there to start getting games running.

Standalone mode & software support

Hill: And what kind of performance levels are you targeting for games using the Steam Frame when it's in the standalone mode?

Pierre-Loup Griffais, Software Developer, Valve: I guess it's hard to pinpoint a specific segment there because there are so many games on Steam that keep coming out that are running great on there, right? Sure, games that are trying to push the boundaries on the AAA stuff that's very graphically intensive. Most of those recent ones won't run very well because it's a smaller compute envelope, right?

But there's a ton of stuff that is coming out that is a great experience on the Frame. For example, I think last week the Metal Gear Solid Collection Part 2 released. And, you know, MGS4 is a game that I haven't played in, I don't know, 20 years at this point, but it's great from there.

And even at the higher resolution, 60 FPS is locked. So it's really cool to see games that are coming out right now that are great experiences on there. I think there's a ton of indie games and things that run really well too. And if you go down the back catalog, there's a ton of stuff from a little bit ago, even AAA stuff that runs great as well.

So I think the point is that you're able to engage with your whole library, right? And then have kind of a similar thing as the deck where you're going to try and figure out if some games are maybe a little bit below the bar in terms of what you would like for performance. And then off to stream those from another PC instead, or the Steam machine.

Hill: And building on that, how's the reception been to the Steam Frame Verify program from developers for the standalone games?

Griffais: I mean, I think we have a lot of developers that are pretty eager to get their games working well. And so we've seen it approached from different ways. Some folks do tweaks to their existing PC version and then get to a very good point with that.

But just the same kind of tweaks as you would expect from Steam Deck, where some surface-level tweaks for the user experience, like changing controller bindings a little bit or changing default settings in a way that really makes the game better for everyone and not just for Steam Frame.

And we're doing the same for Half-Life Alyx, where we're doing a lot of work to support the Frame more natively and trying to remove performance barriers that are induced by some of the translation, the emulation there that you get on normal and modified PC games.

And that's yielding great results to get to the next level of performance there. And so we expect that some developers will be doing some of that work or maybe adapting some of that existing work that they've already done on an Android version of their game and then adapting that through Lepton as well. So I think everyone's kind of engaging with it at a different pace there. But overall, I think like we're talking to a bunch of VR devs that are excited to get their games to be labeled as verified or playable.

Foveated streaming and technical hurdles

Hill: Could you go into a little more detail on foveated streaming and how it enhances the gaming experience with Steam Frame?

Leinbaugh: Yeah, so the Steam Frame has eye-tracking cameras on the inside of the headset that know where your eyes are looking. And when you have that, there's a lot of potential use cases, but the one that we're using most consistently is foveated streaming, which really means when you're streaming, especially VR content, there's a lot of video data that you have to send.

And so you're therefore very sensitive to how much available bandwidth that you have available for not just transmitting it over a wireless link, or whatever kind of link, but also just encoding and decoding that data. All of that takes from a pool of finite resources and your network stack or your graphics card.

But because we know, with eye-tracking cameras, what part of the image you're looking at at any time, we can refocus some of those resources to make sure that the important parts of the image are treated as first-class bits. And then the rest gets the last part of the resource pool, which is the part of the image that you can't see, and you won't notice the image degradation.

So instead of kind of evenly focusing all of the encoding and network resources around this entire immersive, all-encompassing VR image where you're not seeing most of it, we make sure that the part that you're looking at is encoded differently in a way that's a much, much higher equivalent bit rate.

So the best analogy really is [that] it's almost as if the part that you're looking at is using about 10 times as much bandwidth and encoding bit rate as it actually is for the entire image, because we just squished it all into that part that follows where you're looking.

Hill: Switching gears slightly, how are you compensating for temporary losses in connection or signal strength when gaming wirelessly? Is there a fallback mechanism?

Leinbaugh: Yeah, there are a few different levels of what we'll do, and we've made sure to do something in response to all these things happening. So the first thing is if you're using the wireless adapter, if you also are connected to your home WiFi, for example, which a lot of people just naturally will be, then the streaming, VR streaming will take advantage of both of those connections.

And so you'll have the adapter and your WiFi both active at the same time; we call it multi-link streaming. And what that means is that those two connections are competing against each other constantly, every single packet.

So there's a fallback mechanism built into that, which, if you have two links active and one of them drops out because of interference, or you walked out of range, or all the many reasons that wireless interference can happen. If something happens to one of those links, the other one will immediately pick up and cover the gap. And it's just very unlikely that a lot of those sources of interference will hit both links at the exact same time. So that's kind of the first line of defense that we have.

If you still don't, if you still have an interruption or maybe you only have one link active, then the headset has strategies to fill in those gaps. So if you have a short interruption, just like a latency spike or something, then a previous frame will get reprojected and replayed. And that works pretty convincingly for covering small gaps like that.

A lot of people won't even notice that it's happened. If you have an extended dropout where the video is just not arriving at all for whatever reason, then at that point, the video stream is not going to recover.

If it's a very extended dropout, but the headset will fade you back into the construct environment so that you're at least not getting stuck with a really unexpected experience or something that might confuse you or disorient you.

So the worst-case scenario is you'll just kind of fall back to the default environment and have a chance to either wait for it to recover or do something. Maybe you unplugged your Wi-Fi router or something that you need to go do.

Pricing and market conditions

Hill: When the Steam Machine arrived, there was a little bit of sticker shock with the price when it launched. And the Steam Frame is also around $1,000, close to $1,300 bucks in top trim. Surely Valve is sensitive to the realities of the marketplace with RAM and storage prices. How do you appease the gamers out there that are begging for some relief in hardware pricing?

Griffais: Oh, yeah, I think as far as memory prices and those kinds of conditions, we're really in it like everyone else. Like, there's not really anything special that we can do.

We've been working hard on trying to get the parts that we can get at the best price possible. But I think everyone's affected. [...] The fact that our price was affected by that compared to what we were hoping for is definitely true. But I'd say that it's trending along the reality of the market. And there's not really any sort of the kind of distortion compared to just the price of the parts in there.

And it's an unfortunate situation all around. We wish that gaming hardware was cheaper, but we're definitely trying to be on the cheapest side that we can get despite all those conditions.

It's not just memory and all that too, right? Even just things like motherboards, copper, anything; even shipping anything worldwide right now is way more expensive than it was last year and two years ago. So every part of the sticker price is affected there.

Hill: Final question: Are you planning to implement the same reservation system that you used for the Steam Machine with Steam Frame?

Griffais: Yeah, I think that's the plan.

[Interview ends]

There are machines that are below $800 with 8GB of RAM, and there are machines that are multiple thousands of dollars with anywhere from 128GB to 192GB of memory. Want something in between? Good luck.

The MacBook Neo's long shadow

When Apple announced the MacBook Neo in March, other laptop OEMs jumped to compete. Devices like the Dell XPS 13 and Chuwi UniBook came quickly (with varying degrees of success), packing Intel's budget-focused Wildcat Lake processors. But it took until IFA for those companies to finally reveal something truly designed to take on the MacBook Neo. The Lenovo IdeaPad Vibe laptops come in seven colors, up from the Neo's four, ranging from "lowkey gray" to "spicy gold," with optional color keyboards and two screen sizes. Unlike other Neo competitors, Lenovo is opting for a mix of Qualcomm Snapdragon X and AMD Ryzen AI 400 chips rather than flocking to Intel.

Dell's new 14S also has four colors, including a surprisingly bold "velvet green." But its biggest iteration is that it also adds ports. While the XPS 13 had just two USB-C ports, the 14S also has HDMI and a headphone jack. Acer also debuted a 16-inch version of its Swift Air (also in three colors). These laptops were widely considered some of the best from the show. Colors have been a rarity in the Windows PC market, and now that these companies are chasing Apple, they're back.

On the bright side, this means that the spur of affordable, more premium laptops wasn't just a blip following the MacBook Neo. It's still going six months later, and given that Apple is rumored to be releasing a follow-up next year, nicer, colorful laptops may be a permanent fixture of the market.

Agentic AI computers: Laptops or furniture?

The other computers at IFA were all largely focused on running agentic AI. There are finally systems getting ready to ship with AMD's Ryzen AI Max+ Pro 495, with up to 192GB of unified memory. Those include the Lenovo ThinkCentre X along with options from smaller names like Minisforum and GMKtec. The companies that are listing prices have them as high as $7,000. (When Strix Halo launched, entry-level configurations could be found under $2,000 with 64GB of memory, so these high-end systems with more memory aren't a shock given rising prices.)

Those were on display while Nvidia continued to hype its RTX Spark N1X platform, which will launch in October in two configurations. Two new devices, one from Acer and one from Lenovo, debuted at IFA, though we're still waiting on pricing for every RTX Spark device we've seen so far.

AMD's systems were portrayed as workstations in most cases, while others, like an AI NAS from Minisforum, gave us a look into what having some sort of AI furniture — dedicated AI hardware with access to your files that's not connected to a screen — could look like. Nvidia's laptops, all running Windows, are a mix of workstation, gaming PC, and agentic AI PC, though those demos were behind handlers, and we weren't able to try them ourselves.

All of these systems were shown running some sort of AI agent. Nvidia's bounced between Hermes and OpenClaw, while the many vendors showing AMD systems often had their own software, typically with the word "Claw" in there somewhere, running a variety of models locally.

These are all a swing away from what the industry called an "AI PC" just a few years ago. Now, with way more memory and far more compute (and less talk about NPUs), Nvidia, AMD, and the companies making the hardware are betting that you or your company are ready to set up agents and have them run workflows, and that you'll pay a pretty penny to do so.

Two extremes, but what about the rest of us?

There are clearly two visions of computing now: one with the power for local AI models to run tasks on your device (though how easy those will be to set up is an open question), and another where you do basic tasks on cheap computers. What about the rest of us? The people who are happy to spend $800 - $1,500 on a laptop or mini PC to get a bit of extra RAM and storage, the most premium build quality, higher-resolution displays, better speakers, and, of course, a bit more performance? Other than Dell recently adding Intel's Core Ultra Series 3 processors to the XPS 13 (which itself isn't the most premium), it's been quiet on that front.

Perhaps we have to wait for Intel to drop Nova Lake mobile, or for AMD to move forward with Medusa Point, to see these types of systems. Word on those has been quiet, but maybe next year, at CES, we'll see a return of the performance laptop. (Apple is likely to bring its M6 to the MacBook Air, but the company doesn't really do trade shows.) Or maybe memory prices mean something has to give ... and the laptop for everyone else is what is giving. But without new silicon aimed at that market, it seems that the Windows world is happy to be split into two extremes.

The artificial intelligence boom has multiplied that demand exponentially. Training and inference for frontier models now run across data centers, each housing hundreds of thousands of accelerators and providing hundreds of megawatts of compute. Nvidia alone shipped an estimated 3.2 million Blackwell GPU packages through the end of 2025, with every one of those accelerators packaged on an ABF substrate. Meanwhile, the industry is already entering the gigawatt era with humongous data center buildouts, each expected to house millions of AI accelerators.

This edifice rests on a remarkably narrow supply chain. Practically every advanced logic and AI chip made today by Intel, AMD, and Nvidia depends fundamentally on ABF substrates. These substrates are the conventional default for high-performance packaging. They are made by a small group of specialists, including Unimicron, Ibiden, Kinsus, Shinko Electric Industries, Samsung Electromechanics, and Nan Ya PCB. The upstream supply chain gets much tighter.

The one common denominator across ABF substrates, regardless of manufacturer, is the Ajinomoto build-up film itself. Each substrate maker laminates its build-up layers using dielectric film supplied by Japan's Ajinomoto, which controls a reported 95% or more of the global market. A single company, better known for food seasoning than microelectronics, sits at the base of one of the most concentrated supply chains in computing, almost singlehandedly supplying a material for hundreds of millions of semiconductor devices. Not surprisingly, demand is now growing beyond what the supply chain can comfortably supply.

Compounding this crunch, modern AI accelerators now pack multiple compute, memory, and supporting components onto a single board. As a result, the substrate is getting larger across the X-Y footprint to accommodate the expanding package. Manufacturers are also adding more build-up layers to the substrate to route the growing number of signals and power connections. Each additional layer requires another ABF layer, further multiplying demand across millions of accelerators and extending manufacturing times.

Unfortunately, the complications don't stop there. Beyond further straining the supply chain, expanding the substrates is creating technical problems, such as warpage, yield issues, and electrical losses within the component itself. This leaves the ABF substrate ecosystem facing two related challenges: producing enough advanced substrates for a rapidly expanding fleet of AI accelerators, while simultaneously re-engineering these substrates so they can continue to scale without becoming unmanufacturable or impractical.

The ABF substrate roadmap is consequently as much about supply-chain capacity as it is about the hardware itself, with suppliers such as Ajinomoto and Ibiden outlining plans to expand material and manufacturing capacity, respectively. At the same time, the wider industry — Intel, Samsung, and SK's Absolics among them — is exploring glass-core substrates and other material technologies to push past the limits of organic ABF.

ABF substrates

Silicon dies, including CPUs and GPUs, cannot communicate directly with the printed circuit board beneath them. The connection pads on a die are spaced micrometers apart, while the traces on a motherboard are spaced hundreds of micrometers to millimeters apart. Every high-performance chip, therefore, sits on an intermediary package substrate — a dense, multilayer board that fans the ultra-fine connections on the die outward into connections large enough for the motherboard to handle, while also providing signal routing, power and ground distribution, and mechanical support for the package.

ABF substrates used in AI accelerators typically consist of a rigid, glass-reinforced resin core sandwiched between successive build-up layers of copper wiring and insulating film. The core provides much of the mechanical rigidity, while the layers provide the increasingly dense wiring required close to the silicon.

To create the substrate, the manufacturer laminates the ABF dielectric onto the structure, forms microscopic vias — commonly with a CO2 laser — and then uses lithography and copper deposition to create a new wiring layer. High-end substrates typically use a semi-additive process (SAP), in which fine copper traces are plated up from a thin conductive seed layer. Another ABF layer is then laminated over it, and the process repeats. The film electrically separates successive copper layers, while plated microvias connect them vertically.

Ajinomoto developed the film in the 1990s, after which it gradually became the industry default for its low dielectric loss, fine-line capability, and smooth lamination. The company reportedly accounts for roughly 95% of the substrate film market, with its nearest competitor, Sekisui Chemical, holding only a low-single-digit share.

The manufacturing tier above the film is more populated but still concentrated. Unimicron, Ibiden, and Shinko together account for roughly three-quarters of the substrate market by most estimates, with AT&S and Nan Ya PCB rounding out the leading group. These companies take ABF and other materials and manufacture the finished multilayer substrate. Semiconductor packaging companies, such as TSMC and Amkor, then integrate those substrates into packages containing the processor, memory, and other components.

AI accelerators are pushing substrates outward and upward

To deliver the compute and memory bandwidth that frontier models demand, the industry is packing ever more silicon onto each AI accelerator. Designers now place multiple large logic dies alongside a growing number of high-bandwidth memory stacks on a single package. Nvidia's Blackwell generation mounts two reticle-sized GPU dies and eight HBM3E stacks on a single package, with its upcoming Rubin and Rubin Ultra parts pushing it further still. TSMC's CoWoS packaging is scaling from around 3.3 reticles — each roughly 830 square millimeters of silicon — a generation ago to 5.5 reticles in volume production in 2026, with a roadmap reaching 9.5 reticles in 2027 and beyond 14 reticles by 2029, when a single package is expected to carry roughly ten compute dies and twenty or more memory stacks.

This expansion of the accelerator package is driving the substrate’s expansion on two physical levels. The first expansion is the substrate's footprint in the X-Y axes. The base has to get wider and longer to accommodate the larger package footprint. Ibiden's current roadmap puts its cutting-edge substrate size at 90 × 90mm (3.54 x 3.54 inches) in 2026, 110 × 110mm (4.33 x 4.33 inches) in 2028, and 130 × 130mm (5.12 x 5.12 inches) and larger from 2030 onward. Ajinomoto independently expects the representative advanced AI packages its film goes into to grow from roughly 100 mm² in 2026 to about 120 mm² for 3D AI packages from 2031.

The second expansion is along the Z axis through additional layers. An expanded collection of compute dies and memory creates more signals to route, while the corresponding increase in power draw requires extensive power and ground distribution, all of which must be carried in a growing number of layers. Ibiden's roadmap targets a 10-X-10 buildup structure in 2026, 12-X-12 in 2028, and 14-X-14 from 2030. Here, the numbers represent the build-up layers on either side of the central substrate core: “10-X-10” means 10 build-up layers per side of the core — which is represented by the “X” — each comprising one dielectric layer (ABF) plus one patterned copper layer, working as a pair.

Nan Ya PCB's roadmap points in the same direction. From an 11+N+11 baseline, it targets 24-layer substrates in 2026 and more than 24 layers in the first half of 2027, while tightening line and space from a 9/12 µm baseline to 8/8 µm and then to 6/7 µm by early 2027. Layer-counting conventions differ between vendors, so a per-side figure and a total layer count don't necessarily line up directly.

The substrate’s expansion in both directions creates several challenges. Increasing the X-Y area makes the package harder to keep flat. Silicon, copper, the substrate core, and the polymer build-up materials that make up the substrate expand by different amounts when heated. As the package is bonded during assembly at around 250⁰C and then cooled, these mismatches cause the layers to pull against one another, leading to warping — a problem that becomes harder to control as package dimensions increase.

Excessive warpage can undermine solder-joint formation, layer-to-layer alignment, and reliability, while a larger substrate also occupies more manufacturing-panel area and exposes more area to potential defects. Organic substrates are reported to lose usable flatness once packages exceed roughly 120mm per side, a threshold that the largest AI accelerators are now reaching and that Ibiden's own roadmap — climbing toward 130mm and beyond — is set to cross.

The growing layer count along the z-axis also creates manufacturing challenges around yield, capacity, and time. Every new substrate layer requires a full manufacturing sequence of several steps, all held to sub-ten-micron tolerances. Each added layer increases the chance of a defect or alignment error that can scrap the whole substrate.

Additionally, layer count consumes manufacturing capacity and time in proportion. This is why Ibiden frames future demand in terms of semi-additive processing load rather than a simple substrate count, as a single advanced substrate now consumes far more of a line's capacity than a finished-unit tally would suggest.

Overall, the simultaneous expansion in substrate area and layer count means ABF consumption is rising much faster than processor shipments alone suggest. Ajinomoto illustrated this in its 2025 integrated report with a larger AI substrate that had about 3.5 times the board area and three times as many ABF layers as a conventional design — 18 layers against six — consuming roughly ten times as much ABF overall. This surging material consumption, set against an extremely concentrated supply base, extends the ABF substrate story beyond a technical problem into a supply-chain constraint.

The supply chain constraint

Like many components in the semiconductor industry chain before the AI boom, demand for ABF substrates periodically swung both ways. A severe bottleneck through 2020-2022 — driven by pandemic-era PC and server demand — was followed by an oversupply in 2023, as substrate manufacturers expanded capacity. However, that capacity was built for low-layer-count, smaller consumer substrates, not the large-body, multi-layer packages AI demands.

These advanced products require sufficiently large manufacturing formats, fine SAP wiring, tight layer registration, acceptable warpage, and high yields across much larger structures. Ibiden captures this by measuring demand not in finished substrates but in semi-additive-process load — the actual processing work each part imposes on a line. Indexing 2024 at 1.0, it expects the SAP load of a single AI-server substrate to reach 1.8 times that in 2026 and 2.5 times in 2028, with the company stating that substrate expansion will push total SAP demand beyond industry supply capacity, indicating a constraint in the manufacturing process itself.

The bottleneck is even tighter at the ABF material level. Ajinomoto's film capacity was already running at full load in the second quarter of 2026, at a reported two million square meters per month, although the company has outlined plans to increase capacity. A near-monopoly supplier at full capacity while consumption surges paints a clear picture of the bottleneck’s severity.

Unsurprisingly, prices have moved accordingly. Ajinomoto notified substrate manufacturers in May 2026 that it would raise ABF film prices by approximately 30%, effective in the third quarter. The hike is coming alongside comparable increases in copper-clad laminates from Resonac and Mitsubishi Gas Chemical, compounding pressure across the whole stack. Further tightening the squeeze, Ajinomoto recently cut shipments of the critical ABF film to China by 30%.

The growing ABF substrate problem cannot simply be attributed to Ajinomoto running out of film. In fact, while it's running at full capacity, the company says it has no concerns about its overall supply chain. The constraint stretches across the entire chain containing ABF, glass cloth, and other materials, SAP equipment, large-format substrate factories, yield, and customer-qualified production capacity.

The immense industry demand is progressively tightening the crunch. Several supply-chain analyses converge on an ABF supply-demand shortfall of roughly 10% in the second half of 2026, widening to around 21% in 2027 and potentially exceeding 40% by 2028, with demand for substrate area projected to grow at a compound annual rate near 39% from 2025 to 2028 as accelerators integrate more components.

The roadmap to recovery: more capacity, better materials

The industry is responding to ABF substrates' multifaceted constraints on multiple fronts: expanding manufacturing capacity to relieve near-term supply pressure while qualifying new materials and substrate architectures to break through the technical limits. Capacity expansion is already underway across the supply chain.

Ibiden is executing ¥500 billion ($3.1 billion) in capital investment across fiscal years 2026 to 2028 — the largest single substrate expansion on record — targeting 2.8 times its 2024 capacity for ASIC and AI-server substrates by 2028. Unimicron raised its 2026 capital spending to a record NT$34 billion ($1.07 billion), with a focus on ABF substrates. Meanwhile, Samsung Electro-Mechanics, Samsung's substrate arm, has committed $1.2 billion to expand ABF substrate production, with volume production expected by the third quarter of 2027.

Pegatron's substrate unit, Kinsus, has approved NT$23.5 billion ($722 million) for ABF equipment over three years and now focuses its most advanced lines almost entirely on AI clients, aiming to lift monthly output at its Taoyuan plant by roughly 25% by 2027. While these projects address the shortage directly, their lead times mean the crunch may continue for a while, as supply cannot respond instantly to the AI demand spike.

Ajinomoto is expanding upstream as well. A new plant in Gunma entered full operation in 2025. The company has invested roughly ¥25 billion ($157 million) in ABF production since 2023 and has said it will invest at least as much again by 2030, targeting a capacity increase of more than 50%. It is also adding a third Japanese base for varnish production — envisioned to provide capacity comparable to Gunma — with construction planned for 2028 and operations to begin in 2032.

However, capacity only solves the problem if the current substrate architecture can continue to scale. The material roadmap — aimed at addressing the physical constraints of ABF substrates — is therefore advancing parallel to the factory roadmap. Ajinomoto says present and future ABF generations are being engineered for larger, more multilayered substrates, high-bandwidth I/O, lower transmission loss, and improved resistance to warpage and humidity. The company expects newer, higher-value ABF grades to take an increasing share of its portfolio through 2030.

Substrate makers are addressing the problem from the process side. Nan Ya plans to move beyond 150 mm body sizes and 24 layers while shrinking copper line/space geometry toward 6/7 microns in the first half of 2027. Its materials roadmap includes an ultra-low-CTE core material with a CTE below 3 ppm/°C, alongside low-Dk, low-Df, and low-CTE dielectrics. Finer wiring allows a substrate to support more connections without relying solely on additional area or layers, while low-expansion materials help keep the growing structure flat.

Eventually, the substrate's central core itself may change to glass. Organic substrate cores are increasingly difficult to keep dimensionally stable as packages approach and surpass 100 mm. Glass can be matched more closely to silicon's thermal expansion — providing dimensional stability — and offers substantially lower dielectric loss for high-speed links. It has therefore emerged as one of the industry's main solutions to warpage.

As we detailed in our glass substrate roadmap, the move to a glass core is drawing a broad field, as it sits at the intersection of substrate-making, glass manufacturing, and advanced packaging, pulling in chip-and-packaging houses, display and glass specialists, and the incumbent substrate makers alike. Intel demonstrated a package that combines EMIB with a glass substrate at NEPCON Japan in January 2026, although the company still places commercial glass-substrate deployment in the latter half of the decade.

SK Group subsidiary Absolics is operating a low-volume glass-substrate manufacturing facility in Covington, Georgia — backed by $100 million in US CHIPS Act funding — producing prototype and qualification samples for customers, such as AMD for its MI400-series accelerators, while Samsung Electro-Mechanics is producing prototypes on a pilot line in Sejong and now plans mass production through its glass-core joint venture after 2027.

TSMC, meanwhile, is pursuing panel-level packaging through its chip-on-panel-on-substrate (CoPoS) platform, moving to a 310 x 310mm panel format, with a pilot line at its VisEra subsidiary, trial production targeted for 2027 and mass production for the second half of 2028. Glass-core substrates are a separate, later step on TSMC's roadmap, with commercial scale projected after 2030. Ibiden also puts “glass core” on its substrate technology roadmap around 2030 as a solution for warpage control.

The glass core — most likely a late-2020s-to-2030s technology — is positioned as a solution to the warpage wall. It replaces the organic core, not the ABF itself, which would remain the buildup material. A glass core may soften ABF demand per package, as glass's flatness allows finer routing and potentially fewer buildup layers, but it does not remove the material or the dependency. There's the possibility that a future dielectric material will eventually replace ABF, although that doesn't seem to be the industry's main focus currently.

Regardless, the near-term roadmap centers on more advanced SAP capacity, rapidly expanding factories, improved materials, and increased supply. Through the late 2020s, finer wiring, lower-loss ABF, lower-CTE materials, and better warpage control will enable organic substrates to stretch toward 110 mm and beyond. Around 2030, glass cores offer a path toward the 130 mm-plus packages that Ibiden and others already have on their roadmaps.

Totaling around 17GB for four-bit quantized weights and offering built-in multimodal capabilities on top of its general aptitude, Qwen 3.8 27B immediately grabbed the attention of everybody with an RTX 5090, RTX 4090, or RTX 3090 (as well as a Radeon RX 7900 XTX, Radeon AI Pro R9700, or Arc Pro B70).

Were we on the verge of frontier-level intelligence from a four-bit quant on a single graphics card? Could everybody with a capable enough local AI setup go and cancel their Claude or ChatGPT subscriptions?

The answer, of course, as with every open-weight AI model hype cycle, is more complicated than just eyeballing the size of the model weights and comparing it to your available VRAM pool. Does the card or system you're using to host the model have enough VRAM left over to provide useful amounts of space for the model's context once everything is running? Do your host system and LLM inference engine deliver acceptable time-to-first-token, as well as high throughput beyond just bench-racing from an empty context window?

It's one thing if you just want to chat with a model and see what happens; it's another entirely if you want to put it to work, especially as impatient agents take the limits of human perception out of the picture.

We wanted to see what hardware and software stack Qwen 3.8 27B really wants in order to deliver solid performance, so we ran it on systems ranging from a desktop PC with discrete GPUs to systems with unified memory architectures like the DGX Spark, Mac Studio, and Ryzen AI Halo.

Our discrete GPU AI testbed includes the following components:

Where it was possible to do so, we tested performance with Qwen 3.8 27B’s built-in multi-token prediction capabilities both enabled and disabled. Not all of the model runners we tested were able to support MTP within the amount of VRAM available to us on some of our platforms. We note where MTP was and wasn’t possible in our analysis of each platform, as well as in our charts.

RTX 5090 performance

We started with the RTX 5090, whose 32GB of GDDR7 and 1.8 TB/s of memory bandwidth would seem to make it an absolute no-brainer for getting the best local inference performance with this dense model. (Mixture-of-experts models tend to be friendlier to performance on lower-end hardware like the DGX Spark and AMD's Strix Halo, as their limited numbers of active parameters mean less data movement during inference).

As a baseline, we followed our usual local AI benchmarking approach: grab the latest build of llama.cpp from GitHub, build it, grab an Unsloth quantization of the model from Hugging Face, and run it. But our testing quickly ran into a speed bump.

Although llama.cpp will happily allocate the full 262K context length with this model on an RTX 5090, its processing speeds at long contexts on this card are dire.

Time-to-first-token with a single 5090 stretches to roughly 30 minutes, suggesting that something is just broken here. And tokens-per-second throughput drops far, far below what you would expect for having one of the world's fastest graphics cards at your disposal. No matter how you slice it, llama.cpp is not the right model runner for this hardware right now.

Next, we tried vLLM, a production-grade inference engine that's more at home in the data center than it is on the desktop, although it can comfortably serve in both roles—at least if your host system is up to its requirements. Even with 64GB of main memory in our test rig, we had to allocate another 64GB of swap just to let vLLM load Qwen 3.8 27B successfully for the first time. A lightweight stack this is not.

The vLLM maintainers provide an NVFP4 quantization of Qwen 3.8 27B and deployment recipes for both one and two RTX 5090s. We just so happen to have two RTX 5090s in the TH labs, so we were able to try out both configurations.

Serving Qwen 3.8 27B on one 5090 with vLLM certainly works in a pinch, but it's not ideal for long-context inference because the base recipe for it limits you to just a 32K context. To get the full 262K context, you really want a single card with more memory (like an RTX Pro Blackwell card with 48 or 72GB of RAM) or two 5090s, as we were able to test.

And a single card doesn't have enough memory to enable Qwen 3.8 27B’s built-in multi-token prediction (MTP), which is super helpful in getting faster decode performance from this setup. 20 tokens per second across the board without MTP is not an impressive baseline for a card of this caliber.

Get two 5090s into the picture, though, and decode speeds rocket upwards for vLLM (albeit at a high cost to prefill). 70-80 tokens per second across the context depth sweep is a fantastic result for a local setup, and TTFT remains fairly reasonable. But we can go faster.

Enabling MTP with vLLM gets us to 100-110 tokens per second on the decode side for only a small hit to prompt processing speed. This setup provides consistent performance at prompt processing speeds that don’t make you question whether something has gone seriously wrong. But it ought to be fast, because our dual RTX 5090 platform as tested here would currently ring in at over $13,000.

We also tried the SGLang inference engine on the RTX 5090 across similar configurations as we did with vLLM.

SGLang is much faster on a single 5090 for some reason – almost 3x faster than vLLM’s single-5090 recipe – and also ekes out a bit more context (37,740) versus vLLM. But if you want to get the full 262K that the model natively supports, you still need a second card or a different one with more VRAM.

Like vLLM, SGLang supports tensor parallelism across multiple GPUs, so enabling dual-GPU inference is as simple as adding another launch flag. And as with vLLM, there are a number of speculative decoding strategies you can add to the recipe to enhance output performance.

The takeaway from this first phase of testing: if you have a single RTX 5090 and don't need long-context inference from it, you can certainly get usable performance from one with this dense model. But you need to choose your model runner carefully.

And if you want the full context window, reasonable prompt processing times, and high throughput from Qwen 3.8 27B all at once, you really want a graphics card with more than 32GB of VRAM as a starting point (or multiples).

RTX 3090 and RTX 4090 performance

With the RTX 5090’s behavior settled, we turned to some older consumer cards to see how they handle Qwen 3.8 27B. The 24GB RTX 4090 and 3090 are evergreen favorites among local LLM fans thanks to their relatively large VRAM pools and relatively affordable prices on the used market, but as we've already emphasized, just being able to load the model weights is far from the whole picture.

These cards can fit the Q4_K_M GGUF of Qwen 3.8 27B with llama.cpp just fine, but they require using the Q8_0 quantization of the KV cache to fit the results in their smaller VRAM pools from the get-go, and they also require limiting the context depth to well under the model’s 262K native limit. We found that a context length of about 112K tokens was about the most we could get away with before running out of VRAM.

And unlike the 32GB RTX 5090, which can usually get away with having the Linux desktop window manager running next to the LLM and its infrastructure, these GPUs need every last byte of VRAM for the AI workload and nothing else. So you really want a separate graphics card at hand for these two cards if you're not running a headless server, which can introduce some setup headaches of its own as you discover how your particular motherboard handles PCIe slot bifurcation and enumeration of the primary graphics device.

Once you overcome those obstacles and get Qwen 3.8 27B up and running on these cards, llama.cpp exhibits the same performance cliff at long contexts on the RTX 4090 that we saw with the RTX 5090. But the RTX 3090 is oddly not affected. This suggests a bug somewhere.

We didn’t have time to dig into SGLang or vLLM behavior on these products, but given that you’re already tight for context on an RTX 5090, we’re doubtful that either of those inference engines would be an awesome way to run the model on these 24GB cards, unless you’re somehow ready to roll with multiple 3090s or 4090s from past acquisitions.

DGX Spark performance

Hardcore local LLM enthusiasts will scoff at the DGX Spark’s mere 27 GB/s of memory bandwidth for a dense model like Qwen 3.8 27B, and indeed, we've found that this platform isn't the fastest with dense models in our past testing.

But now that models like Qwen 3.8 27B support MTP with nothing more than a server launch flag, you can often get a major free boost to the decode speeds of platforms with limited memory bandwidth.

In our actual tests, the Spark's solid prefill processing performance means that it will often end up finishing inference turns at longer context lengths well before the RTX 5090 does with llama.cpp.

And beyond llama.cpp, the Spark is also well supported by SGLang and vLLM, so you can take advantage of those inference engines if they’re more to your taste. Consider also that a single Spark is still available for about $5000, and it’s a turnkey system that can be expanded into a handy cluster down the line if you want. So it shouldn’t be ruled out, even for serving this dense model.

Apple Mac Studio with M4 Max performance

The M4 Max-powered Mac Studio in our labs has the most memory bandwidth of any of the unified memory systems we have available, but as we've described in previous testing, that's only one metric that matters for local AI inference.

Prompt processing on this platform is slower than on Spark, so even if the Mac Studio can turn out more tokens than GB10 in the decode phase, it still ends up spending more time per inference turn than Nvidia's platform at longer contexts because that’s where it has to spend most of its processing time.

And at least in llama.cpp, using MTP on the Mac Studio actually causes a performance loss at shorter contexts for decode in exchange for a small boost at longer contexts, where it generally leads to improvements for other platforms. This demonstrates the value of actual benchmarking rather than spec-racing.

Ryzen AI Halo (Strix Halo) performance

AMD’s Ryzen AI Halo presents the worst-case performance scenario for this dense model: relatively low memory bandwidth and low prompt-processing performance.

Although MTP wakes up tokens-per-second throughput a bit on this system with llama.cpp, it can’t make up for the lengthy prompt processing times required for longer contexts. You can certainly run this model if a Strix Halo is the only box you have, but we’d seek out something more capable if you’re trying to do interactive long-context work.

Bottom line

When I first set out to explore Qwen 3.8 27B's performance, I figured this would be a relatively straightforward series of tests: plug in a single graphics card, load the model, get tokens, done. In practice, our experience required a lot more tinkering. And systems we might have initially written off as being not up to the task of running a dense model like this proved surprisingly useful.

In general, breathless claims of hundreds of tokens per second of throughput from an empty context window do not account for the full range of behavior one might see from an LLM on a given inference setup.

For just one example, whether it's down to a problem with (or just the expected behavior of) llama.cpp or something else about our software stack, the notion that you'd want to wait as much as 30 minutes or more for a response from Qwen 3.8 27B at long context lengths on an RTX 5090 is outrageous. But if you naively load Qwen 3.8 27B using llama.cpp right now, this is the experience you'll get.

Changing up inference engines is a natural next step, but there are trade-offs with that approach, too. You can load Qwen 3.8 27B on one 5090 using vLLM or SGLang, but those inference engines are much more conservative about the amount of usable context they’ll give you. The recipes we used only resulted in a context window of 32K tokens on a single 5090.

To enable the full 262K context length, we had to grab another RTX 5090 from the TH testing arsenal, at which point we got both great throughput and a TTFT sweep that could be considered interactive all the way out to the maximum context length from both model runners. But the price of replicating such a setup would exceed $13K right now.

You also might expect that a DGX Spark and its 273 GB/s of memory bandwidth wouldn't be useful for this dense model, but the prefill speed of the Spark ends up being fast enough that the TTFT remains relatively interactive even with a decode throughput of just 20 or so tokens per second with MTP, and that behavior holds out to the model's full native context length.

The M4 Max-powered Mac Studio has plenty of memory bandwidth on tap for decode, but its prompt processing speed means that the total time of an inference turn is dominated by that activity on this older Apple Silicon chip. The newer M5 Max and brand-new M5 Ultra would doubtless perform better, but we didn’t have those chips handy for this testing. And AMD’s Ryzen AI Halo gets the worst of it, with both low prompt processing speeds and relatively low TPS due to its memory bandwidth.

For all this, we really need to take a step back and consider the economics of local AI once again. $5K, $10K, or $15K or more for local AI hardware is a lot of tokens from leading-edge models at Anthropic or OpenAI (and even more from providers serving the recent slate of Chinese open-source models). A lot. And if time is money for you, barring compute constraints, those tokens will get back to you or your agent faster than anything you can run at home short of a DGX Station with its GB300 GPU.

So unless you’re working with sensitive data that requires on-premises processing, you’re an enthusiast who just wants to tinker, or you’re worried about the fate of open model distribution and inference more generally for some reason, you probably don’t need to rush out and build a box just for this model.

But if you do, be aware that delivered performance is more than just VRAM capacity or memory bandwidth, and that you might not get the best performance from your setup with the most common model runners like llama.cpp. Let experimentation and careful benchmarking lead you to the best results for your specific config.

The technique works by polishing two dies flat, then bonding their copper pads and surrounding dielectric directly under heat and pressure, with no solder bump in between. Because there’s no bump to collapse, the connections can be packed far tighter. AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking, and figures presented at TSMC's 2026 technology symposium put face-to-face hybrid bonding at around 14,000 signals per square millimeter against roughly 1,500 for face-to-back through-silicon-via stacking.

Wafer-to-wafer, die-to-wafer, and throughput

Microbumps have historically run at pitches around 40 microns, tightening toward 10 for the latest memory. Hybrid bonding, however, starts where microbumps end and keeps scaling: the leading edge is at 6 microns now, with 4.5- and 3-micron generations in development and sub-micron pitches demonstrated in research. Each step down multiplies the number of vertical connections between stacked dies, allowing a cache die or a compute tile to behave as if it were part of the chip rather than a separate component wired across a package.

The method is split into two different approaches: wafer-to-wafer and die-to-wafer. Wafer-to-wafer bonding joins two full patterned wafers face-to-face and dices them afterward, which allows the tightest pitch and fastest production because alignment happens once at the wafer scale. Imec and EV Group demonstrated a 200-nanometer wafer-to-wafer pitch with post-bond overlay below 40 nanometers at ECTC in May. The constraint here is that both wafers must carry identically sized dies, and every die gets bonded, including defective ones, so a single bad die on either wafer ruins the pair.

In contrast, die-to-wafer bonding places individual, pre-tested dies onto a wafer — which is what chiplet and HBM stacks require — because it allows known-good-die selection and the mixing of different die sizes and process nodes. There’s a penalty in terms of throughput with die-to-wafer as each die is picked, aligned, and placed in sequence rather than in one wafer-scale step.

The best die-to-wafer pitch shown at ECTC 2026, from CEA-Leti, was 1 micron, roughly five times looser than the wafer-to-wafer record. Because the dies are placed one at a time, the speed the bonder runs at sets the limit on how many chips it can produce. Applied Materials and Besi cite around 1,600 die placements per hour on the Kinex platform, and Besi's Chameo bonders are rated near 2,000 chips per hour, with the next generation aiming for 50-nanometer placement accuracy to reach finer pitches.

Hybrid bonding is difficult to achieve, as two surfaces have to be almost perfectly flat and clean. The dielectric holds on contact through van der Waals forces, so the polished surface can vary by no more than around 0.2 nanometers, and the copper pads have to sit a few nanometers below it, close enough that they swell into contact when the stack is heated to 200 to 300℃. A single particle smaller than a micron holds the surfaces apart and leaves a gap spanning many pads at once. So keeping the wafer clean and flat through the polishing step (known as chemical-mechanical planarization) is critical for good yields.

TSMC SoIC and Intel Foveros Direct

In terms of who’s leading hybrid bonding, TSMC’s System on Integrated Chips (SoIC) platform leads in terms of volume. At its 2026 North American Technology Symposium, the company laid out a pitch roadmap moving from 9 microns in 2023 to 6 microns in 2025 and 4.5 microns by 2029, with second-gen SoIC adding face-to-face bonding on top of the face-to-back stacking that the first generation supported. The node-stacking roadmap runs in parallel, from N3P-on-N4 today toward N2P-on-N2P by 2028 and A14-on-A14 by 2029.

With SoIC, the hybrid-bonded stack is built first as a vertical block, then placed into a CoWoS module alongside HBM on a silicon interposer, a combination the industry calls 3.5D. AMD's MI300 is the reference case, stacking compute and I/O dies by hybrid bonding before the assembly is mounted in CoWoS with its memory. SoIC handles the front-end vertical density; CoWoS handles the back-end lateral integration with memory.

Capacity is slowly growing, with TSMC building out its Chiayi AP7 site as its largest advanced-packaging campus. Output is targeted for 2026, and analysts at TrendForce have estimated SoIC capacity roughly doubling year on year from a few thousand wafers a month in 2024. Customers include AMD, whose 3D V-Cache and MI300 accelerators were the first volume SoIC products, and the Broadcom-built Fujitsu Monaka CPU.

Meanwhile, Intel's hybrid-bonding implementation, Foveros Direct, reached high volume with Clearwater Forest, the Xeon 6+ server processor built on the 18A node and demo’d at MWC back in March. The design uses a 9-micron copper-to-copper pitch to bond compute and I/O tiles onto base tiles that act as an active interposer, and Intel has described a second generation targeting a 3-micron pitch. Enabling that on a leading-edge logic node required a dedicated process variant, 18A-PT, which adds the through-silicon vias (TSVs) and bonding support that standard 18A doesn’t carry. The shift from Intel's earlier Foveros, which used solder microbumps across the Ponte Vecchio GPU's chiplets, to direct copper bonding is a generational change now playing out across its server offerings.

The unexpected HBM delay

The widely held assumption was that HBM, the stacked DRAM that sits beside every AI accelerator, would be hybrid bonding's largest market by volume. That changed back in January when JEDEC raised the HBM package height limit from 720 to 775 microns, and the extra room means 16-high HBM4 stacks can be assembled with microbumps after all. With HBM4 pad pitch at 10 microns, reporting from SemiEngineering noted that moving to hybrid bonding at that pitch wouldn’t yet make economic sense.

SK hynix has reflected that logic in its own planning, reportedly sticking with advanced mass-reflow molded underfill for 16-high HBM4 while keeping hybrid bonding as a backup and continuing to validate 12-high hybrid-bonded samples for later generations. The company demonstrated a 16-layer HBM4 sample at CES 2026, built without the all-hybrid bonding many expected the generation to require. The result pushes hybrid bonding's HBM debut toward HBM4E and HBM5, expected around 2027 to the end of the decade, where taller stacks and tighter pitches finally make the older bonding methods run out of room.

Meanwhile, the memory makers are building the packaging capacity regardless. SK hynix is investing $3.87 billion in an advanced-packaging plant in Indiana, with production targeted for 2028, and Micron broke ground on a $7 billion HBM advanced-packaging facility in Singapore early last year, with output expected around 2027. Those plants are sized for the volumes hybrid bonding will eventually carry, even as the first HBM4 generation ships on the older interconnect, meaning the equipment commitments are running ahead of the technology's confirmed deployment date in memory.

Samsung is doing the same thing from the memory side. Its SAINT packaging family includes SAINT-D, which stacks DRAM directly on a logic die, and the company has discussed a bufferless HBM4 design that removes the separate base die, with custom HBM logic dies reportedly moving to its 2nm foundry process for 2027 samples. At GTC in March, Samsung claimed hybrid bonding cuts thermal resistance by more than 20% against thermocompression bonding.

Another drag on the timeline is intellectual property. Adeia, which holds a large portfolio of bonding patents, sued AMD last year, alleging that the hybrid bonding behind 3D V-Cache infringes 10 of its patents.

China is pursuing the technique as a way around its lack of access to cutting-edge lithography. With SMIC limited to 14nm-class production and cut off from next-gen EUV, domestic researchers have identified 3D hybrid bonding as a route to competitive performance by stacking older logic and DRAM, with public claims of 14nm parts paired with domestic DRAM aimed at rivaling far newer GPUs. Given that it’s China we’re talking about here, those claims remain claims, and no foundry has demonstrated mass production of hybrid-bonded logic memory in China.

A scramble for tools

In terms of tooling, Applied Materials and Besi, partners on hybrid-bonding equipment since 2020, launched their Kinex die-to-wafer bonding system late last year, billed as the first fully integrated die-to-wafer hybrid bonder combining surface preparation, bonding, and metrology. Applied Materials has taken an equity stake in Besi, and reports from March placed Besi at the center of takeover interest from both Lam Research and Applied Materials, an indication of how important the bonding-tool market has become as logic adoption ramps and memory adoption is staged behind it.

Analyst tracking put Besi’s hybrid-bonding revenue on a path toward roughly €476 million by 2026, up from about €36 million in 2023, with second-half 2025 orders rising more than 60% against the first half on early HBM4 production-line bookings. Competing tool vendors are moving in alongside it: ASMPT has partnered with EV Group on hybrid bonding, and SK hynix is working with Hanwha Semitech on bonders targeting a commercial HBM launch in 2027. The sheer scale of this equipment build-out is a clear demonstration that the industry is treating hybrid bonding as an inevitability, even where the products that’ll use it are still years out.

Hybrid bonding is already in volume production, but its capability is outpacing its adoption. TSMC offers 6-micron pitch while its newest disclosed customer ships at 9; Intel ships at 9 with 3 on the roadmap; and the memory market that was meant to consume it in quantity has bought itself one more generation on microbumps. Two things will show where it goes next — whether any leading logic product drops below 9 microns in volume, and whether HBM4E marks hybrid bonding's first real use in memory before the end of the decade.

Samsung Electro-Mechanics formalized a 482.1 billion won ($310 million) glass-core joint venture with Sumitomo Chemical's Dongwoo Fine-Chem on July 2, targeting first production in the second half of 2027. Intel, which started the race, has shifted to licensing its patents and showing demo vehicles, with its own deployment now pointed at around 2030. However, and rather predictably, every timeline in the segment has slipped. Absolics originally planned mass production for the first half of 2024, and reported claims that AMD would adopt glass substrates for CPUs between 2025 and 2026 have come and gone unfulfilled.

Why glass?

The technical case for glass core substrates leans heavily on numbers Intel published a while back, such as 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion. Glass cores can be tuned to a thermal expansion coefficient of roughly 3 to 10 ppm per degree Celsius against silicon's 2.6, which cuts warpage by about half compared with organic cores, and rectangular panels in the emerging 510mm x 515mm format use more than 75% of their area for large die against roughly 50% for round 300mm wafers. Through-glass vias have been demonstrated at six microns in diameter with aspect ratios beyond 15:1 at ECTC 2025, and Georgia Tech has shown stacked glass running at 220 GHz with 0.3 dB of loss.

Glass also chips and cracks at the edges during drilling and dicing, and MIT Technology Review reported in March that early Absolics production runs broke hundreds of panels every couple of days during early testing days. Edge-coating work has cut measured edge stress from 95 MPa to 49 MPa, and low-temperature dielectrics that cure below 180°C have been developed to reduce thermal stress during build-up, but metallizing vias below 10 microns and holding nanometer-scale flatness across half-meter panels remain open manufacturing problems.

Intel's program

Intel demonstrated a working system booting Windows on a glass-core substrate in early 2025, and Rahul Manepalli, Intel's VP of module engineering, told MIT Technology Review that the benefits of glass cores are "undeniable" and that Intel wants "to be one of the first ones who do it." The commercial plan around that engineering has changed shape, however. DigiTimes reported in late July that Intel is in early-stage talks with Chinese cover-glass maker Lens Technology about a packaging partnership, but there has been no solid agreement made to date.

At NEPCON Japan in January, Intel Foundry showed its first thick-core glass substrate with two EMIB bridge dies embedded directly in the glass: a 78mm x 77mm package with two 800-micron-class glass layers, 10 redistribution layers on each side, and around 1,716 mm2 of silicon on top, roughly two full reticles, with no micro-cracking reported in testing.

There’s currently no production time to this, however, with TrendForce placing Intel’s commercialization somewhere around 2030, alongside co-packaged optics prototypes built on glass at its Rio Rancho, New Mexico site. Meanwhile, Amkor, Intel's packaging partner on the optics work, put commercialization within three years at an industry event in Seoul in April.

Korea aiming for 2027

Samsung Electro-Mechanics moved its glass program from advanced R&D into a business-execution unit in February and has been sampling from a pilot line at its Sejong plant since late 2024. The GLASEM joint venture announced on July 2 splits ownership: 66% to Samsung Electro-Mechanics and 34% to Dongwoo Fine-Chem, with site production in Pyeongtaek, and targets an operating plant in the second half of 2027, with the joint venture making the drilled and metallized glass core that feeds Samsung's substrate line. Korean industry reporting says samples have gone to AMD and Broadcom, and also puts Samsung's overall glass maturity at 40 out of 100, a gap between marketing dates and process readiness worth keeping in mind.

Absolics' $600 million plant in Covington, Georgia, backed by $75 million in CHIPS Act funding plus a further $100 million through the government's advanced packaging R&D program with Georgia Tech, has a Phase 1 capacity of 12,000 m² of substrate per year, enough for roughly two to three million H100-sized packages. The company produced mass-production samples in the first quarter, began customer qualification that reportedly includes AMD and AWS, and is targeting mass production by the end of 2026. LG Innotek runs a third Korean program from its Gumi plant, with prototypes delivered in 2024 and production targeted for 2027 to 2028.

TSMC and Japan

TSMC's CoPoS line in Chiayi, built around 310mm x 310mm rectangular panels, received tools in February, completed its pilot line around June, and is aiming for pilot production in 2027, with mass production in the second half of 2028. Equipment supplier SCHMID has described glass integration in that platform as under review, not committed, and TrendForce puts TSMC's commercial-scale glass-core production after 2030, meaning that the industry's biggest packaging operation is going panel-level first and glass later, if at all. TSMC revived glass substrate research a couple of years ago after earlier deprioritizing it, reportedly under pressure from Nvidia, whose accelerator packages are the main thing outgrowing current packaging.

Japan’s Dai Nippon Printing began phased operation of a TGV glass-core pilot line at its Kuki plant in Saitama in December 2025 on 510mm x 515mm panels, with sample shipments from early 2026 and full mass production targeted for fiscal 2028. Toppan's pilot line for glass cores and interposers at its Ishikawa plant was scheduled for commissioning in July, and Nippon Electric Glass has scaled its ceramic-reinforced GC Core panel to 515mm x 510mm at 1mm thickness. Rapidus is studying panel-level packaging on 600mm x 600mm glass as part of its 2nm program, with viability put at the late 2020s. China has its own entrants, led by display maker BOE, whose pilot line is sampling.

TrendForce estimates Nvidia's Rubin Ultra package at roughly 7,470 mm², about nine reticles' worth of silicon and memory, against around 2,739 mm² for Blackwell, and CoWoS interposer wafers cost on the order of $10,000 each, comparable to a processed 7nm wafer.

Organic substrates warp and lose dimensional stability at those sizes, and round interposer wafers waste a growing share of their area, which is what glass panels are meant to fix. SEMI's first dedicated market report on glass cores, published in May with Global Net, projects initial production around 2028 in select high-performance applications and a 67.2% compound annual growth rate from 2028 to 2040, while Yole puts the advanced IC substrate market at $31 billion by 2030 with glass cores among the drivers.

At the moment, no production design exists, and all customers that have been named or otherwise attached to the tech, including AMD, Broadcom, AWS, and Nvidia, come from wider industry reporting. Nothing has been confirmed officially. As for whether we might see more substantial progress next year, Absolics will need to publish some solid package-level reliability results by the end of this year, or a first officially named customer at any of the Korean manufacturers. We also need to hear from TSMC on whether glass cores will go into CoPoS or remain under review into the 2030s.

The gap for the supercomputer sits depending on who's ranking it, showing how what used to be a simple race for supremacy has actually become several overlapping competitions. It also highlights how "fastest" has different definitions depending on what is measured, how it is measured, and which operators publish their results.

We previously reported how LineShine uses 13.79 million cores built around China's domestic LingKun platform, 304-core LX2 processors, the proprietary LingQi interconnect, and Kylin operating system. It's also the first CPU-only machine on the TOP500 to sustain more than two exaflops, reaching around 80% of its theoretical peak while drawing 42.2 megawatts. That makes it impressive enough – but it’s also a big win on a geopolitical stage.

China rising

LineShine is the first Chinese system to lead the TOP500 since 2017, ending a period in which China stopped submitting its most advanced machines to the public ranking. Jack Dongarra, emeritus professor of computer science at the University of Tennessee and one of the TOP500's founders, has previously said that two unreported Chinese systems may already have been faster than the then-leading US machine, Frontier.

The TOP500 has used the High Performance Linpack benchmark, or HPL, since the ranking began in 1993. In the test, computers have to solve a dense web system of linear equations using double-precision arithmetic. Like many tests, the regularity of it can be heavily tuned, producing a clean output that invites long-run comparisons across architectures and decades.

It’s tempting to look at rankings like this as the be-all and end-all, but even TOP500 says its result doesn’t reflect a machine's overall performance, because no single number can. But HPL remains valuable because it tests whether millions of processor cores and the links between them can be corralled into one tightly coordinated calculation. "It shows you can go 400 kilometres per hour with your Porsche," said Julian Kunkel, professor of high-performance computing at the University of Göttingen and deputy head of high-performance computing at GWDG, in an interview with Tom’s Hardware Premium. "This is the maximum speed. TOP500 does not tell us anything other than we have an instrument that could go that far."

That speed matters because supercomputers are as much scientific instruments as anything else, used to simulate climate systems, aircraft engines, nuclear accidents and prospective fusion reactors. Scientists want answers relatively quickly. "Imagine I do the weather prediction for tomorrow, and you need 25 hours to calculate it," says Kunkel. By the time the answer arrives, so has tomorrow, rendering it useless.

A mixed picture

The HPCG test and its sparse calculations make less efficient use of processors while putting greater strain on memory bandwidth, latency, and communication between nodes – the sorts of things that scientific applications really need. LineShine's first-place score of 22 petaflops on this measure suggests that its memory and interconnect systems are as powerful as its CPUs. "Those results describe different capabilities, not a contradiction," said Dongarra, responding to Tom’s Hardware Premium’s questions by email.

But another ranking looks at performance in a different way. The way HPL-MxP is designed favors GPUs and dedicated tensor or matrix engines. On this one, LineShine nabbed fourth place globally with 7.92 exaflops, a 3.6-fold increase over its HPL result. But the published HPL and HPL-MxP lists show the accelerator-heavy El Capitan achieved a 9.2-fold improvement, Aurora 11.5-fold and Frontier 8.4-fold.

Dongarra said the different results on different checks show a trade-off in specialization, rather than a universal weakness. LineShine's CPU-centered design has less dedicated low-precision throughput, so other machines do better on mixed-precision workloads – but he said it would be churlish to say LineShine is less capable overall. And the IO500 – which Kunkel co-founded — tests storage bandwidth and metadata performance, while Green500 divides HPL performance by power consumption.

The different metrics by which supercomputers can be measured mean that those procuring them often overlook the rankings in favor of things like time-to-solution and reliability or energy use.

What about AI?

The race for public supercomputing has been disrupted by the rise of private AI infrastructure. Although Microsoft's Eagle system appears at number seven in the latest TOP500, most frontier AI clusters publish only GPU counts, theoretical FP8 performance, or tokens-per-second claims – and some don’t really disclose much at all publicly, worried that their competitors might pick up on it.

There are some AI-based testing regimes out there, including MLPerf, which offers standardized AI training and inference tests, including new DeepSeek-V3 and GPT-OSS 20B workloads in its 2026 training suite. However, submissions to the scoring system remain voluntary, and AI labs might not want to submit them in case they score badly, torpedoing their public perception — meaning we know very little about some of the world's most consequential computing systems.

It’s also a distraction, said the experts. "There is no sense for any private AI system to run HPL," said Kunkel. Doing so would take thousands of expensive accelerators away from commercial work and require days of tuning a result their customers don’t use, and probably don’t care about.

Dongarra reckons LineShine probably isn’t best at everything, even though among those systems that are submitting public results, it showed the strongest measured double-precision and HPCG performance. That, he believes, makes it good enough to say this is a very good supercomputer. Any credible assessment, he said, "requires a portfolio of measurements" — covering time-to-solution, sustained performance under mixed workloads, reliability, ease of programming, cost and power alongside the headline benchmarks.

So while LineShine's HPL victory is significant and technically impressive, it also highlights how there is no longer one supercomputer race. Systems whose results are never disclosed may be faster for particular AI workloads, "but without comparable public evidence,” said Dongarra, “that remains a claim rather than a ranking".

Samsung confirmed the 2nm milestone in its fourth-quarter 2025 results, the same release in which it returned its foundry unit toward profitability on the back of HBM4 logic-die orders. The unit still trails TSMC roughly 11:1 by revenue, and 2nm yields are reported to be sitting near 55%, below the threshold the business needs to run advanced nodes at a profit.

What separates Samsung from TSMC isn't fabs or customers but yield, and Samsung has been able to absorb the cost of that gap because its foundry unit sits inside the Device Solutions division alongside a memory business posting record profits. The company reports no standalone foundry P&L, which has given the operation years of runway that a pure-play foundry wouldn't have the benefit of.

Taylor, Texas

Samsung's Taylor project is both the centerpiece of its roadmap and the company's longest-running headache. The full campus, covering two fabs, an advanced packaging facility, and an R&D center, has been reported at around $44 billion, with the portion tied to U.S. funding set at over $37 billion. Samsung's CHIPS Act award was revised down from up to $6.4 billion to up to $4.745 billion as the project's scope narrowed, with Texas adding roughly $250 million in state incentives in September last year.

Construction stalled through 2024 and into 2025, with reporting at the time attributing the halt to an absence of committed customers and yield problems on the node the fab was meant to run. Samsung held an equipment move-in ceremony in April, and the site is now set to install a third-gen SF2P+ variant of its 2nm process, with trial production targeted by the end of 2026, full mass production in 2027, and a capacity goal of around 50,000 wafer starts per month. The facility's anchor tenant is Tesla, whose AI6 chip Samsung will build at Taylor under the eight-year deal running through 2033. Tesla's AI6 has reportedly slipped by around six months, tied to a delayed engineering run on Samsung's 2nm line, pushing volume toward late 2027.

Pyeongtaek

Pyeongtaek remains Samsung's largest production base, built out across a series of lines designated P1 through P5. In the near term, activity at Pyeongtaek centers on P4, where Samsung has pulled forward equipment move-in and is reported to be installing an HBM4 base-die line on its 1c-class DRAM, and on P5, the final planned fab at the site, where construction had been halted and is now reviving on the strength of AI memory demand. The P5 buildout carries a reported total investment of nearly 90 trillion won and a 2029 production target, according to Korean trade press.

The Korean expansion runs against a backdrop of capex restraint. Through 2024 and 2025, Samsung was reported to have cut foundry investment sharply and to have reviewed pausing both Pyeongtaek and Taylor work as losses mounted, with foundry utilization sitting around 50% in the second half of 2024 before recovering as clients returned.

Hwaseong and Giheung R&D

Process development runs out of Hwaseong's EUV line. The newer Giheung NRD-K research complex, a roughly 20 trillion won investment running to 2030 and dedicated to advanced-node R&D. Samsung deployed an ASML High-NA EUV research tool, the Twinscan EXE:5000, at Hwaseong for process development, and was understood to be buying two mass-production-class EXE:5200 systems — with the second originally being due to arrive in the first half of this year — aimed at the SF1.4 node and next-generation DRAM.

On the logic side, that plan has since shifted: Samsung's updated roadmap keeps SF1.4 on Low-NA tooling and reserves High-NA for the 1nm generation. Given that this research base feeds the production fabs, its output will now set the pace for how quickly Samsung can stabilize 2nm and move to 1.4nm.

The processes

Samsung's 2nm family runs from the first-generation SF2, now in mass production, through SF2P this year, the SF2P+ variant headed to Taylor, and SF2Z, which adds backside power delivery and is planned for mass production in 2027. The 1.4nm node, SF1.4, was originally targeted for 2027 mass production when Samsung announced it at the 2022 Foundry Forum. That date is now officially 2029, per an updated roadmap Samsung presented at the 2026 Next-Generation Lithography + Patterning Conference in August, which commits the company to three more years of refining the SF2 family before moving down a node.

The same presentation gave Samsung's first confirmation of where High-NA EUV enters production: not at 2nm or 1.4nm, but with the 1nm-class SF1A node around 2030. "We believe High-NA EUV will become necessary from A10 and below," Chang Min Park, Master VP of Technology at Samsung Electronics, told the conference, saying the tooling needs further improvement before it can carry mass production at larger nodes. SF1A is slated to run alongside SF1.4+, an enhanced 1.4nm variant that stays on proven Low-NA flows, so customers wary of High-NA's smaller exposure field and higher cost will have a fallback on familiar tooling.

As always, roadmaps live and die by their yields, and Samsung's is no exception. The company's first-gen 2nm yields were reported as climbing through 2025, but as of April, they still sat near 55%, below the level the business needs for profitable high-volume output, with reporting suggesting Qualcomm could route work back to TSMC as a result. These figures are obviously estimates rather than Samsung disclosures, and they've varied across sources, but they're consistent enough to say that yield — not capacity or customers — is Samsung's biggest constraint with 2nm.

To compensate, Samsung has been pulling back aggressively on price to stay competitive. The company is reported to have cut its 2nm wafer price to around $20,000, undercutting TSMC by roughly 33%, a discount that'll no doubt win price-sensitive work but compress the margin on a node already running below break-even yields. Undercutting on price while trailing on yield is a difficult combination to fund, which is why the unit's losses have set the pace of its recovery.

Exynos and external customers

Samsung's anchor customer on 2nm is its own mobile chip unit. The Exynos 2600, built on SF2, is the node's first commercial product and powers the standard Galaxy S26 and S26+. However, the Galaxy S26 Ultra runs Qualcomm's Snapdragon SoCs worldwide, and the Exynos reportedly covers only around a quarter to a third of S26 builds because yields cap how many it can supply.

A successor, the Exynos 2700 on SF2P, is in development for the Galaxy S27, with mass production targeted for the second half of this year. Samsung using its own processor to prove a node before committing to external customers is the same play we saw the company run at 3nm.

Externally, 2nm customers remain thin. The clearest to date is Japanese AI firm Preferred Networks, which Samsung confirmed as a turnkey customer for SF2 plus 2.5D packaging on AI accelerators. Tesla's AI6 is obviously the biggest name, and there are reports of a 2nm CPU order from a North American fabless customer identified as AMD and of advanced-stage talks with Qualcomm over Snapdragon work, though neither is confirmed.

HBM4

The strongest case for Samsung's integrated model sits in memory rather than logic. The company said it shipped the industry's first commercial HBM4 in February this year, running at 11.7 Gbps per pin against the 8 Gbps JEDEC baseline and extendable to 13 Gbps, with per-stack bandwidth up to 3.3 TB/s. The logic base die under that stack is built on Samsung's own 4nm foundry process, which lets the company source the base die in-house rather than buying it from TSMC as some rivals must, and it's reported to be moving the base die for custom HBM to its 2nm process for samples in 2027.

That capability has translated into qualification, with Nvidia CEO Jensen Huang confirming in June that Samsung, SK hynix, and Micron had all passed certification to supply HBM4 for the Vera Rubin platform. Samsung is still the smaller supplier, with analysts putting SK hynix at roughly two-thirds of Nvidia's HBM4 allocation and Samsung in the mid-20% range. Still, qualification of all three vendors ends the period when Samsung was locked out of Nvidia's top memory tier.

Samsung has also moved early on the next step, having begun shipping HBM4E samples around May, claiming roughly 3.6 TB/s of bandwidth, and is positioning custom HBM with logic-based dies tailored to individual accelerator customers, including Nvidia, AMD, Broadcom, and hyperscalers, with samples due in 2027. SK hynix followed with its own HBM4E samples weeks later, so although the lead is measured in weeks rather than generations, memory is the part of Samsung's business where it competes at the front rather than from behind.

Firmly in second place

Samsung has reshuffled its foundry leadership twice in a year, naming Han Jin-man to head the business in November 2024 and restoring a dual-CEO structure over the Device Solutions division in November 2025, with Jun Young-hyun over the DS division and Roh Tae-moon added as co-CEO.

The reshuffles followed a stretch in which foundry and System LSI losses were put by analysts at 3.18 trillion won for 2024, before reportedly narrowing below 1 trillion won by the third quarter of 2025 as utilization recovered from around 50% in late 2024 toward roughly 80% in early 2026. Chairman Jay Y. Lee has publicly ruled out spinning the foundry off to address the conflict that running it alongside the Exynos design unit creates for fabless customers, saying the company intends to grow the business rather than separate it.

The spending behind that recovery is massive, with Samsung having guided to more than 110 trillion won in combined facilities and R&D investment for 2026. The Device Solutions division is taking the bulk of a 10.2 trillion won first-quarter capital outlay, and Taylor ramp investments are set to rise from the second quarter onward. Ultimately, the company is funding an advanced-node buildout on both sides of the Pacific while the unit that runs those fabs is only now climbing back toward break-even.

In Q4 2025, TrendForce put TSMC's foundry revenue at $33.7 billion against roughly $3.4 billion for Samsung's foundry unit, leaving Samsung second with around 7% of the market. By Q1 2026, the same source had TSMC at $35.86 billion and Samsung near $3.2 billion, a gap of roughly 11 to one. Samsung is reported to be targeting foundry profitability by 2027, and a 20% market share, and its own 2026 guidance promises double-digit revenue growth and improved profitability driven by advanced nodes. The company is also reported to be reviewing a second Taylor fab and moving foundry leadership closer to its U.S. customers, a sign it's planning for the demand it hasn't yet converted.

Whether that holds depends on the same metric that has dogged the Taylor launch and the Tesla schedule. SF2 mass production and a marquee customer are both in place; what closes the distance to TSMC, or fails to, is yield reaching the level that makes a $44 billion fab and a $16.5 billion contract pay for themselves.

Modern motherboards range in price from under $100 for the most basic, to well over $1,000 for flagship/Halo-type boards from the ‘Big 4’ (Asus, ASRock, Gigabyte and MSI). But more expensive doesn’t always mean a better experience, especially if you’re likely not to use the hardware and features you’re paying for.

Several factors drive motherboard pricing. From the PCB layer count and copper content at your most basic level, chipset (some, like X870E, have two chips), power delivery, to controllers and premium components, they all increase the Bill of Materials (BOM). So what do you actually gain by spending more? It depends on the board, but outside of more robust power delivery, you tend to get additional, improved, or faster everything. Be it storage with M.2 sockets and SATA ports, USB ports, wired or wireless networking, the audio solution, or PCIe slots and bifurcation. And you can’t forget about the aesthetics. In general, the more you spend, the better the specs and the better they look. Some even include integrated screens. But it goes beyond just the hard specifications.

In addition to the hardware, motherboard partners attempt to inject value with DIY-friendly innovations such as toolless M.2 sockets and heatsinks, larger BIOSes with integrated drivers, or even quick-connect Wi-Fi antennas. All things that make building or swapping parts out easier on your PC. They’re even including “AI” features designed to help with overclocking and other functions like networking, or even local AI work, to make getting the most out of your system easier. And while some of those features can be valuable, their true worth is measured by the individual and whether they can get any use out of it.

The real question you need to ask yourself is what you need (and want) for how you use your PC today and in the near future, as every PC user is different. Whether you use your PC primarily for gaming, work purposes, or breaking overclocking records, needs will vary. The point of this article is to help users navigate through a dizzying array of options, determine what’s actually too much versus what you need, and perhaps save money by focusing on the right parts for your usage.

The cost of a motherboard

What, outside of marketing forces, drives motherboard pricing? First, there’s the BOM. Everything you see on the board has a cost. Starting with the PCB itself, it comes in layers like a sandwich, allowing all of the connectivity to reach where it needs to go without electrical interference. Budget boards tend to use fewer PCB layers and less copper, think 6-layer and 1 Oz, while mid-range and higher use 8/10 layers and 2 Oz of copper as selling points. Of course there’s validation and engineering costs that go into it, too.

On top of the PCB, you have various bits like the VRMs, which can range from downright anemic and a hindrance to performance, to overkill for anyone except extreme overclockers. Cheap boards tend only to give you the basics: fewer VRM phases and lower-rated MOSFETs (think 50A/60A), chokes, and capacitors. More expensive boards use a higher phase count and higher-rated MOSFETs, around 80A-110A.

For example, the popular 80A Intersil ISL99380 MOSFET can be found for around $2.72 apiece (@ 100 qty), while the less capable Vishay SIC623 50/60A is $1.69 per (@ 3,000 qty). Now, these prices are just what we can find online in lower quantities. If you need 100,000 units, prices will drop, and we don’t know what price the board partners contracted at. But the point is the difference in cost. The idea that the power bits on a 12-phase board with 50A MOSFETs will cost less than a 24-phase board with high-end 110A SPS MOSFETs should be clear, and we haven’t even touched on the chokes and capacitors that make up the VRMs.

Other onboard items such as network chips, USB controllers/hubs, SATA controllers, audio solutions with DACs and/or amplifiers, PCIe switches, BIOS chips, and more all add up (and that’s just the hardware/ICs). For example, a Marvell Aquantia AQC113 is around $27 apiece for 1,000 units, while the 2.5 GbE Realtek RTL8125BG can be found as low as $2 apiece for 30 units. Pricing isn’t publicly disclosed for many items to compare; for instance, we can’t find pricing for the ASmedia ASM4242 USB4 chip, but you can expect it to fetch a premium over most other supplemental, slower USB controllers. On the other side of the tracks, Intel’s JHL8540 Thunderbolt 4 chip costs a bit over $13 apiece for 2,000 units.

DIY-friendly features such as toolless M.2 sockets and PCIe latches likely also cost more than the basic M.2 socket with screws and PCIe slots without those features, but that’s something more tangible, even if it’s only used for installation and upgrade purposes, and likely not a significant part of the BOM cost.

You also can’t forget the appearance. From basic boards with minimal heatsinks and no RGBs to massive decorative heatsinks and shrouds, RGB lighting, and integrated screens, it all adds up. And of course, you have to factor in R&D to get these boards and all of their features created and to market in the first place. Just remember that not every additional dollar translates into something you’ll notice in everyday use.

Where does the value end?

Unfortunately, we don’t have a black-and-white answer to this question, as it depends on the person making the purchase and their needs, or how they plan to use the PC. Speaking generically, very few people need incredibly robust, 20-plus-phase, 110A MOSFET VRMs, even with a high-power flagship-class processor. Most users with any processor will be fine with a 12-18 phase board with 60-80A MOSFETs. There’s almost no point in paying the premium for a more-capable design so long as what it has can handle your processor without throttling it. And as you can see from our motherboard benchmarks below, performance is generally price-agnostic among these tightly grouped results.

Unless you plan to overclock and use extreme cooling methods, those monster 20-plus-phase 110A MOSFET power systems are overkill. Items like onboard buttons to adjust BCLK, voltage, or the multiplier are useless for all but the most extreme overclocking, used at the brink of stability. 99.9% of users who overclock can do so in the BIOS or use Windows tools without these extra features, which add cost. For example, the ASRock Z890 Taichi OCF with all of the overclocking bells and whistles for ~$400 isn’t the right choice unless you’re overclocking competitively.

Popular processors like the AMD Ryzen 7 9800X3D and other X3D derivatives won’t need anything close to that and work just fine with 10-12 phase 50-60A MOSFETs. The same goes with Intel. You’ll need a better motherboard for a Core Ultra 285K than for a 250K Plus, especially if you plan to overclock.

10 GbE, or even 5 GbE, networking is another item that, chances are, you don’t need for most PC activities. With average download speeds in the US hovering just over 300 Mbps, you don’t need to worry about faster wired connectivity unless you need the bandwidth for your internal network, like a NAS or transferring among devices on your internal network. For example, I have 1 Gbps (sequential) fiber, which is the fastest my area offers currently. In this case, 1 GbE is enough, but leaves no room for upgrades. A good sweet spot for wired networking is 2.5 GbE, so anything over that is overkill for anyone who doesn’t need a fast LAN connection.

Wireless networking is another story. 2025 and 2026 brought Wi-Fi 7 to the masses, supplanting Wi-Fi 6/6E. The problem here is that few have Wi-Fi 7 wireless devices in the first place. Your motherboard, and perhaps your new phone or laptop, may have it, but that’s about it. This also means you need a Wi-Fi 7-capable router, and if you don’t have a capable adapter, buy one, which increases the total cost of ownership. Chances are you’ll be fine on Wi-Fi 6E or even the ‘slower’ Wi-Fi 7 (160 MHz instead of 320 MHz), depending on your device count and bandwidth needs. The more you have of both, the more 320 MHz Wi-Fi 7 can be beneficial.

PCIe lane switches (read: bifurcation) are also something that not many users need unless you have PCIe add-in cards. This is something you’ll need to dig into the specifications to find, as it’s not typically listed as a feature. It generally happens automatically due to lane sharing anyway, but that ability can add cost to the bottom line. You also need to watch out for lane sharing so you get what you pay for with your chosen hardware. Be it M.2 sockets and PCIe, or USB and M.2 sockets, chances are you’ll experience lane sharing in some form or another on Intel and AMD chipsets, more so on the mainstream and high-end boards. And while money doesn’t prevent this occurrence, there are only so many lanes to go around; the more features you try to add to a limited number of lanes, the more it has to share.

Take, for example, the flagship MSI MEG X870E Godlike and Godlike X we reviewed. Even though this is a $1,000 motherboard, it’s still limited to the lanes and bandwidth the chipset offers. In this case, the rear USB4 ports share bandwidth with the second PCIe 5.0 x4 M.2 socket (M2_2). Here, because the board supports bifurcation, there are a few ways that setup plays out. If you want all of the bandwidth for the M.2, the USB4 port(s) are disabled. You can split them and share bandwidth, or you can get all the bandwidth for the USB4 ports, disabling the M.2 socket. On the same board, the third PCIe slot and fourth M.2 socket share the chipset's PCIe 4.0 lanes.

If we drop down to the X870 chipset, which uses only one Prom 21 chip and has fewer available lanes for sharing, we see a lot of the same thing. On the X870 Tomahawk Wifi (a $229 board), the rear USB4 port doesn’t share with anything but also only uses one PCIe 5.0 M.2 socket. Lane sharing on it is the same as the $1,000 Godlike between a PCIe slot and an M.2 device. In this case, the M.2 device doesn’t even receive the full x4 bandwidth, no matter what hardware is connected. The moral of the story here is to make sure you check the specifications and see what, if any, lane sharing occurs with your specific hardware configuration.

Who should buy what?

When selecting a motherboard, there are a few basic tenets I look at before purchasing, regardless of how I use the PC:

• CPU compatibility - You can’t fit square pegs into round holes. Intel doesn’t work with AMD, AM4 boards don’t work with AM5 processors, and so on. Make sure the board you want supports the processor you plan to purchase.
• Form Factor - Pick a size that fits your chassis: Mini-ITX, MicroATX, ATX, E-ATX.
• RAM Support - DDR4 or DDR5; again, you can’t fit square pegs into round holes. You can even save some money using DDR4 and not lose much performance.
• Storage - How many M.2 sockets do you need, and at what speeds? How many SATA ports?
• Expansion slots - How many do you need, and at what speeds? PCIe 5.0 or PCIe 4.0?
• Rear I/O and connectivity - Make sure you have enough USB ports and the speeds you need for the usage.
• Networking - How fast for the wired solution? Do I need two? Is Wi-Fi 7 an absolute need or a want?

At a high level, we can say motherboards that cost:

• Under $150: have basic functionality, fewer high-speed connections, weaker VRM designs
• $150-250: additional connectivity, the sweet spot for most users
• $250-400: even more connectivity, storage, and premium features, a sweet spot for enthusiasts
• $400+: enthusiast-class features, extreme VRMs, aesthetics, and diminishing returns
• $1,000+: Halo products where you pay for everything, not necessarily for better performance

Basics aside, how many and what speed you need for each feature varies depending on the person and how they plan to use the PC. Currently, I have seven USB devices, three M.2 drives, and one SATA-based HDD, along with a 9900X3D. By day, my workflows are generally light, with a dozen or two Chrome tabs up at one time along with Google Docs and a messaging application. By night, when my work is done, the kids are taken care of, and my wife goes to sleep, it’s a gaming PC.

A gamer’s needs are different than someone who uses the PC for content creation, for example, or a workstation user (powerful multi-core processors and a lot of RAM), or even a competitive overclocker. You don’t need a ton of or the fastest of anything to get the most out of your CPU, graphics card, and RAM. In other words, each type of user/functionality moves different features up and down on the priority list.

For example, as a budget-conscious gamer planning to use an X3D chip, I’d look at AMD and the B650E or B850 chipset-based motherboards, as they offer the best balance of price and features for a high-end gaming CPU without the tax of unnecessary enthusiast features. If you need advanced connectivity like USB and multiple PCIe 5.0 connections, that’s fine. The same goes for Intel; the B860 boards will do most users just fine.

Content creators often need a well-balanced system with high-speed connectivity such as Thunderbolt 4/5 or USB4, multiple M.2 storage slots, and fast networking to handle large media files and heavy workflows. You tend to see those features in X870/Z890 motherboards, specifically those with “Creator” in the title.

Extreme overclockers should look for boards with robust power delivery and overclocking features, such as integrated buttons on the motherboard or 2-DIMM slots that benefit memory overclocking. Boards like the ASRock X870E Taichi OCF ($499.99) or the Asus ROG Crosshair X870E Apex ($726.50) are good examples with features dedicated to overclocking and getting every last MHz out of your system. They are also overkill for just about everyone who doesn’t have a Dewar full of liquid nitrogen.

Final thoughts

So how much is actually too much? The takeaway is that it depends on the situation. Most of us don’t require overkill power delivery and massive VRM heatsinks. Nor do we need 4-5 M.2 sockets or a dozen USB ports, and we can easily get away with less. Most motherboards in the $250-$400 range in the mainstream and enthusiast segment offer enough of everything to be a ‘good enough’ solution for most users. That said, they can also be overkill. It’s when you get into the budget chipsets (think A620 for AMD and Q870/H810 for Intel) that you may run into problems with VRM capability when using high-end processors, as well as connectivity shortcomings.

It seems counterintuitive, and you do get more features on higher-tier motherboards, but buying a more expensive motherboard doesn’t let you bypass the platform's hard limits. It often adds more lane/bandwidth sharing. For the most part, this isn’t a bad thing. You just have to know what hardware you plan to use and what you need from it. Drawing on the examples above, do you need the USB4 port(s) and that bandwidth for external devices (like storage), or the second PCIe 5.0 M.2 socket and its 128 Gbps of bandwidth? Or do you need the last PCIe expansion slot for an add-in card?

If you can answer these questions, you’re most of the way to avoiding overbuying on your motherboard and can then put that extra cash toward something you can actually benefit from. The best motherboard isn’t the one with the most features: it’s the one with the features you actually need. If you still need some assistance buying a new motherboard, check out our best motherboard list, which covers a wide variety of platforms, form factors, and price points. You can also check out our curated best motherboard deals to stretch your dollar even further.

The following is a transcript of our interview with Hallock, which has been lightly edited for flow and clarity. We hope you enjoy this unredacted look, exclusively available to Tom’s Hardware Premium subscribers. You can also catch session transcripts from earlier in the year, featuring Intel, AMD, Nvidia, Valve, and more.

Jake Roach (Senior CPU Analyst, Tom’s Hardware): I appreciate you doing this outside of a typical product cycle.

Robert Hallock (VP & GM Enthusiast Channel Business, Intel): Of course.

Roach: I really just wanted to get your read on a lot of things because things are crazy in the enthusiast desktop space right now.

Hallock: They are.

Roach: So, how are things going in enthusiast desktop land given memory shortages, NAND shortages, everything going on right now?

Hallock: I think the market's experiencing a tale of two kingdoms. Yeah. For the folks who have a significant amount of discretionary budget, they can absorb the cost impacts of what's going on in the industry, and most other people cannot. Right? And that's having a very different impact, as you can imagine, on different parts of the market. Low-end mainstreams really taking a beating. Enthusiast and premium, not so bad. You could, depending on the device class, maybe even be growing positive. So it's a very starkly divided market at the moment.

Roach: I guess I hadn't heard that kind of take on it before. I guess it makes sense that you have more discretionary spending, or if you already were kind of invested in a certain ecosystem. I haven't heard that before.

Intel’s flexibility in the consumer market

Roach: I'm curious about the position of Intel right now. There's AMD, Intel, and Nvidia, right? And you've seen a kind of big shift for AMD and NVIDIA. Nvidia doesn't even break out gaming as a business category anymore; it's embedded now, and I think AMD is now coming up on close to double the data center revenue that they have from their client business. But for Intel, the majority of your revenue still comes from the client business. Does that put you in kind of a unique position right now with so much focus on the data center?

Hallock: I think that it does. I like to believe that it does, and I'm hoping, selfishly for myself, that it does. One of the things that I believe that Intel, that people truly sleep on about Intel when talking about the big fight of this company versus that company, just how big Intel is, how many resources Intel has. As I look at, for example, you know our desktop enthusiast roadmap, I don't have to trade supply with a data center part; I don't have to worry about it. I don't have to think about it.

I can build a roadmap and a plan for the market that is sized against purely what is going on in the client market. And that kind of freedom is very empowering when you're trying to run an enthusiast desktop business for enthusiasts, and it doesn't mean that we're immune to what's going on in the market. It doesn't mean we're immune to supply fluctuations upstream of us. That happens too, right? But at a fundamental level, I can sit down with my team and my partners and build a plan for a product for the year, and not have to worry about what's going on with Xeon, as an example, and vice versa, right? That's their luxury too, right? I can do my thing in client land, and they can do theirs in data center land, and it's okay. And so the size of Intel is what allows that to happen. And at it is at its best, it allows us to maximize the investment and the return on multiple product categories. It's a nice one that works out that way.

Roach: I think it's been maybe a few earnings calls back. There were some mentions in a couple of earnings calls about wafer allocation moving toward the data center to meet demand for Xeon. But you're saying that's not really a concern when it comes to future launches.

Hallock: No, and so, just to give a little inside baseball. It depends on what era you're talking about. If we're just coming into the sudden AI boom, where prices are multiplying very, very rapidly. That was a surprising moment for everyone in the industry. Like we kind of felt it coming.

We heard the rumors, but the size and scale were very abrupt. It was immediate. That is still surprising. It was immediate, and in those cases, yeah, you’re probably going to have to trade some supply around. But once you’re in, like once you’re in it, now you know the plan for it.

Roach: Okay, so that was a temporary measure, gotcha.

On Intel’s enthusiast roadamps

Roach: So, shifting back to the desktop, I know you've mentioned several times about this ambitious enthusiast roadmap, presumably that centers around 18A and Nova Lake. So far, what we've seen out of 18A has been more premium offerings. Obviously, we have Panther Lake; we have Wildcat Lake. Wildcat Lake [is] not a premium offering, but it makes some pretty big concessions to reach that budget price point of single-channel memory and all of that. So I'm curious, given that there is such a large divide between this enthusiast premium category, this budget category, do you think that the DIY PC market can be served by a single product stack, especially on this kind of cutting-edge node?

Hallock: I truly believe that what the market is going to see going forward, and this is just an industry-level comment, is, and I want to stress this is not just Intel...You're probably going to see a split. You'll have a premium socket and a mainstream socket from everybody. If you're playing in desktop space, that is probably what you'll do because the supply chain costs, the upstream costs, have the same costs that are currently harming the entry-level and mainstream market; I don't see those abating anytime soon, right? And so it means that in order to continue providing affordable computer hardware, you're going to have to make some design concessions.

You're going to have to make some concessions in your product stack, and that's purely to control costs and give people an option that they can actually afford. Otherwise, if you don't do it, the other alternative is it just disappears because it's unaffordable. So, seeing a split is likely the outcome for everybody.

Roach: I was telling Thomas yesterday when Gamer Days first came out, I think there was a day when the Core Ultra 250K Plus was $150. I’m like, ‘Man, at that price, that is one hell of a deal.’

Hallock: Hell of a CPU? Yes, it is.

Roach: So obviously we have Arrow Lake Refresh. Arrow Lake Refresh is great, very positive reception. But we've also seen this… One of the stories we really heard a lot from the motherboard guys at Computex was spinning up older DDR4 boards with LGA 1700. I think Gigabyte just reintroduced one a few days ago, and that's great to see because there weren't a ton of those boards even when Alder Lake launched.

But, one of the things that has been concerning for me – covering CPUs – is a lot of volatility in pricing on 13th- and 14th-gen processors, oftentimes selling for much more than comparables from AMD or even for certainly from from Arrow Lake. I'm wondering: are there any plans to maybe improve supply, or some sort of effort to stabilize the pricing of those so it's a bit more consistent?

Hallock: Well, I think what you're seeing is the fact that those 10nm parts are still phenomenally good. We don't spend a lot of time talking about them in the media or at Intel. It's old stuff, and we've all moved on. But they're still phenomenally good CPUs. And if you look at the sort of bucket of options that you can buy for these older DDR4 platforms, it is very likely that Alder Lake or Raptor Lake are the fastest of the bunch in that mix.

Roach: They are. I just recently did a whole DDR4 vs DDR5 article.

Hallock: And so what you're seeing is just like if people are going to go to more affordable hardware, they still want the fastest available for their money, and that happened to be Alder Lake and Raptor Lake. So there was a sudden inrush of demand into these parts that was certainly not anticipated when you start your wafers and your builds long before that moment ever happens. So it's very hard to predict. But going forward, 10-nanometer products like Raptor Lake – that is a core part of the portfolio that I want to offer to people for years to come. LGA 1700 is still a good socket. Lots of people are still interested in DDR4, so keep offering. And you'll see it smooth out over time. It'll come back to normal. That's the plan.

Roach: Yeah, it was really interesting going back because obviously with Alder Lake’s launch, there was a bunch of discussion about DDR4 versus DDR5, but seeing how it scaled all the way up to 14th-gen. You have the 14700K with DDR4 at parity with a 5800X3D in gaming, and obviously much faster in applications. So yeah, I’ve been hoping for a $300 14700K that I can recommend to people.

On Intel's approach to AI in the enthusiast segment

Roach: I wanted to shift a little bit away from desktop. I know that is your, well. I guess maybe not desktop, but the kind of traditional view of just a single-socketed processor. Intel has this kind of breadth of IP, great graphics IP, lots of experience with memory and advanced packaging. And honestly, it's been surprising to me that we haven't seen what I like to call the 'big chip’ out of Intel yet, a consumer 'big chip' out of Intel. Between Strix Halo, I guess Gorgon Halo now, the M-series from Apple, and of course RTX Spark. I appreciate that that's not directly under your purview, but do you think that's an important area of the market, or is this a way to kind of capitalize on this sudden rush in demand for kind of these AI developer workstations?

Hallock: Tricky to say. I'm not sure about that part of the roadmap, but it's an interesting place because in a before time, a big integrated graphics device would have been pitched for gaming, right? It would have been pitched for gaming.

And the market has not always responded positively to that sort of setup, like whether or not the performance is right or the power is right, and oftentimes it's better than the CPU plus discrete option you can get for the same price and the same power. It's better.

Just, there's something about it people just don't take it, and then this whole AI thing came along in a real way – the agentic AI component of it – and certainly renewed demand for that kind of hardware. Now, does that sustain? I don't know. Do people come out of this seeing the value for gaming again – that I also don't know. But you know, we are looking at it, we are exploring it. It's certainly an interesting part of the market. A lot of excitement. People love to talk about it. But interestingly, I don’t think the actual run rate is all that high. So, it’s something we’re cautious about.

Roach: I will tell you every single event I have been to where they've had one of these agentic 'buy your box and run an agent forever’ demos, I don't think I've ever seen a single person actually sitting and watching one of those demos. I don't know what that says, but interesting to note.

Hallock: Just on AI software in general… It's an evolutionary process. Businesses can absolutely benefit now, like Intel has. I personally have agents running for me at work to do processes that honestly took a lot of my time. Sure. And now they're completely automated, and I just have to fact-check them, and that's great. I've saved a lot of time doing this, but you know, the transition to an average consumer – I don't know if we're there yet, right? We're not there yet, and I suspect that's probably informing the demo interest. But it is also a bit of a chicken-and-egg thing.

If you are not AI-aware or AI-ingrained, if you haven't just been dunked in the AI bucket because of your job or your profession or whatever, it is difficult to imagine what you could use it for, right? So now you're caught in this trap, 'well, I've heard about it, I don't know what I could use it for, but then I can get my hands on it, and now I don't know what to do with it.' It's like learning a search engine when we all had to do that, right? But on steroids.

Roach: It’s funny having conversations with friends and people who aren’t in this world because… recording and transcription, right? Like, that’s a super great use case of just, I mean, it’s not even an agentic or an advanced thing. I’ll explain that to them. They’re like, ‘Oh, that’s a great use case.’ I mean, for most people, AI is the sloppy AI images and things like that. That’s AI. They see no other use case for it.

Hallock: That's the great injustice in this industry, right? There are so many things that we all call AI. They all have the same name. And some of them are just like a sticker on a toaster, and some of them are legitimately useful, and they run on your computer, and you have custody over your information and your privacy. That's not bad, but that's quite a spectrum. Yeah, one word, and it's such a shame.

Roach: It is a shame too. With the hardware advancements, it's a bummer being at Tom's Hardware, being mostly a consumer-facing brand, and talking about things like Vera, things like Venice. I'm sure later this month, things like Diamond Rapids. You know, and all that stuff is very interesting from a hardware perspective.

Challenging AMD with new consumer hardware

Roach: I was interested to hear your perspective on this. I was at Advancing AI last month for the Venice launch, and I don't know how long it's been, but it's certainly been since Ryzen, since the original Zen, that AMD's leading with Zen 6 in the data center instead of on client. I just wanted to get your reaction to that.

Hallock: I think it's a natural reaction for them. Makes a lot of sense. What I would say is, as we think about our own roadmap, I have a new core. *chuckles* It's coming to desktop first. I hope enthusiasts do the math about that one, and… That's all I'm going to say.

Roach: Okay, perfect. I would expect no less of a diplomatic response, but I appreciate the response nonetheless. That is, it is exciting to hear that there's still a focus on consumers, because I know for GPUs especially, but even some questions with CPUs about, are we even going to get new hardware? Like, is that a thing?

And I think this goes to a bit of an extreme that all of our local compute's going to wither away, and then it's all going to be cloud instances or whatever that we rent from some data center somewhere. I don't think that's the case, but it is encouraging to hear that there is at least some focus on launching new enthusiast products. I'm wonderi–

Hallock: Not just some focus; I have new CPUs all the way out to 2030. I have a back-to-back-to-back-to-back cadence for gamers, for desktop built for that purpose. Obviously I can’t go into what any of that is, but I’m accelerating for the gaming market. We are moving faster than we ever have in product and release cadence. We’re very serious about this.

Yeah, I understand people are skeptical after the last couple of years. I truly get that. But the signal Intel is trying to send is like… We’re gearing up for one of the most significant desktop CPU launches we have ever had.

We took a team that was time-shared with other businesses. And now this slice of the market has a full org structure inside Intel, and if you're not in corporate America, what that means is the company is so serious about it. They're putting real people, with a lot of budget behind it, right? And having an owner, a sponsor, people that care about it, looking after it – custodians of that work – it makes a real difference.

Just... The difference between Arrow Lake and Arrow Lake Refresh. That’s the difference.

Roach: Oh man, that was a big difference. Oh. Different teams on those? Okay, I hadn’t realized because when we talked about Arrow Lake Refresh, it was… You had made mention of like ‘Hey, we’ve updated our roadmap, and this is our first, maybe peace offering after Arrow Lake.’

But I didn’t realize it was a completely different, or not completely different, but a different team.

Hallock: Yeah, well. Pretty much completely different. Marketing people, different product managers, different business people, and simply, we have a different philosophy on how this market should run, and what people should get for their dollar. And I’m glad that people appreciate it.

A post-Arrow Lake shakeup

Roach: Okay, so there was a big shakeup after. That was one of the questions I had. What were the key takeaways from Arrow Lake? But it sounds like those takeaways were addressed immediately.

Hallock: A couple takeaways that you saw manifest in the [Arrow Lake] refresh launch: The software experience for DIYers, which nobody likes to admit that we all need software for our CPUs because they all have a lot more cores than any game typically expects these days. And so the resilience of that software experience. How do people obtain it? How do they install it? How can they validate your performance? How can they verify that they're getting what you are promising? All of that was kind of open-loop in the Arrow Lake original timeframe.

We had some aspects coming from motherboard vendor websites, some from Windows updates, some from Intel.com. It's too complicated for people, so that directly led into the Intel platform performance package- like, kind of crazy- but put all your useful bits in one spot and tell people to download it.

Well, when you lose sight of this enthusiast DIY space and how people consume software and hardware in this part of the market, it's easy to get turned around. OEMs have a very different strategy. They go through these massive validation efforts and have huge QA labs and can set up a system image with point releases, and… Normal people don't have those resources.

You have to make it very easy for them. So, software resilience was a big one. And then when you look at a pile of IP, some engineer says, ‘Hey, your CPU can do this to this.’ That's your range of capability, and inside you open the box. You've got some stuff you can smudge around, like frequencies or voltage or core counts or specs on and off. You can decide to remix those very differently too. You decide to price it differently.

So what you're seeing is Intel got healthy on its software foundations for DIYers. Intel got healthy on its respect for performance per dollar for customers. We set up some really healthy internal processes for future platforms. Arrow Lake was a tough, tough lesson to learn, but a good one, because it drove some really, really useful changes inside Intel.

The importance of CPU software optimization

Roach: You've really beaten the drum on the importance of software; software is just as important as hardware. Just this past week I was testing out the BC-250. If you're familiar.

Hallock: Yeah.

Roach: The PS5 APU that was repurposed. And if you need a crash course in the importance of software to a gaming experience, just boot up one of those things. But can you explain, from your view, what the importance of software is, especially given Intel's… This is pretty ancient history at this point, but you know, use of specific compilers and things like that. What is your view about the importance of software to an overall performance package?

Hallock: I am scared to open this box, lest I get misinterpreted. So, here’s the deal. From the perspective of a software developer, it's actually really tough to be a professional software developer, especially if you are not self-publishing, especially if you have a publisher breathing down your neck. Because it means that your publisher is picking the release time, not you.

That's time crunch number one. Time crunch number two is… What hardware are we targeting? What CPU do I have at my desk as a developer? What does our QA lab have? What has the publisher allowed us to buy with our budget for QA? What does my historical install base look like for other games? And every time you open the box on any of those, you find more subdivision of compatibility that you need to worry about. That's time crunch number two.

Time crunch number three is, did you start on a console, or did you start on PC? Which were you targeting first? Probably console. So now you have to do a port, which is a time crunch. Some publishers outsource this. There are companies that all they do is console ports to PC.

Roach: A lot of Sony games.

Hallock: You know, I’m thinking of Nixxes. What a great developer! They've been amazing over the years at doing these kinds of ports. So all you're really doing is budgeting a decreasing amount of time as a dev, and then you're like, okay, well, my game has to run on a CPU anywhere from four cores to, gosh, like 32 threads, 24 threads, depending on the vendor. It's a lot.

And so what ends up happening is they just draw a line in the sand. This is the hardware we have in QA. This is what's on my desk. This is what's in the console, and that's what we have time to look at. And maybe we'll look at other stuff later. And a lot of the time, one thing that many gamers still don't quite understand is, like, it's not even really the Windows scheduler or the OS scheduler that's determining how these CPUs get used when you're running a game-they have their own layer.

It's called an affinity mask, and they tell the OS how to use the CPU. So the game is in control of how to do the scheduling, sending all these hints to the operating system. What if those hints are wrong? What if those aren't the right hints for the CPU you have in the socket? What if the game is newer than your hardware, or substantially older than your hardware? Or the developer never looked at your combination?

These are all moments where the game can easily give up huge chunks of performance, or just not run. And everybody has to deal with this, right? Every CPU vendor has to address these challenges somehow. We call it the Intel Platform Performance package; AMD calls it the chipset driver.

Right, we've all got this, and it's so important because it can reach into the operating system, or reach into the application, or reach into the firmware of the CPU itself, and make those real-time adjustments to get the performance back. Gamers would not like how this industry looks without this software from the CPU vendors. It would be a much, much less performant, much slower, higher frame time, more stuttering, sort of environment.

Roach: Yeah, it’s already quite surprising to deal with.

Hallock: Yeah, software cannot replace the CPU, and that is not what we're proposing, right? We're not saying, 'hey, I'm going to give up 10% on the hardware and give you 10% back on the software because it's cheaper.' No, I want 10% of both.

That it’s not trade; it’s both. And that is why we’re interested in pursuing it, and why I think it’s so important, because I’ve now spent serious time at two processor companies and have seen the performance gains that come from this kind of software, and what they contribute to the experience, including my own gaming system that I’m talking to you on right now.

And so, that’s why I’m big on software, because the performance would be much, much worse without it – not insurmountably, but it would functionally limit the kind of hardware that you can produce if everything has to fit in this lowest common denominator of software. That’s the other outcome, and that would be even worse. We cannot have the hardware be stagnant because of the software.

Roach: Gotcha. Yeah. That’s certainly giving up. It’s not the 10% hardware for 10% software. Leaving stagnant software gives up a lot more.

Hallock: That’s right.

Roach: Yeah. You know, we did a story probably a couple of days ago. This guy who, we call him a hardware researcher, but he really just does memes. He made a C compiler that would compile completely with Move and Assembly, and then he made a leaderboard of… it was the x86 Hall of Shame, where he tried to find a single assembly instruction, how to make it run as slow as possible, and he got one up to 189 billion cycles.

Yeah, it was ridiculous. He basically found the two slowest areas in the fabric, the two highest-latency areas in the fabric. Ran the instruction on one of them, and then had the other one make a bunch of frivolous four-byte reads, and like lock it up. Yeah. Anyway, just a great example of how you can make hardware–

Hallock: What people don't understand, every CPU architecture is like the fine art of intelligent compromise, and it's like, okay, well, just as like a random example, could you make the read and write link the same size? Sure.

But what if the reads are like 10 times more common than the writes? Do you really need them to be bidirectionally the same size? Like it's going to show up on a micro benchmark. Someone's going to complain about it, but in real performance, day-to-day, do you actually need it? Yeah, probably not. And there's stuff like that all over a modern CPU based on decades of just, like, learning how people are likely to use this thing; it actually does shape the microarchitecture itself somewhat, like a reflexive principle, right? We speak it into existence by using our processors in a certain way. It's fun.

Checking in on IBOT

Roach: On software, I think I'm probably much higher on IBOT personally than you know. We've seen some interest in it. We did some testing for it. I think it's this thing that probably becomes more important as time goes on. I'm just wondering how it's going. We've had one update, I believe, one game update. I just wanted to check in on how IBOT’s coming along.

Hallock: Going well. You know, we continue to work on multiplayer support, which was kind of in the initial scope. It's taking, I think, longer than the public may have expected, because we certainly do not want people to get in trouble using this technology. And that means you have to talk to a lot of people to do it. We're actively working on non-gaming workloads.

We are working on another upcoming release. I don't have the exact date for this, but we're working on the bits for the next update. And then we're also thinking about, for Nova Lake, you know, what is version 2.0, for lack of a better phrase? What do we want to build into that release based on the new hardware capabilities? Which I know is both some details and not a lot of details, but it's very important to us; it is a long-term, permanent aspect of our roadmap.

Roach: Yeah, I think the game selection has been interesting to see. Obviously, when we spoke around Arrow Lake refresh, you had mentioned, ‘Hey, there's going to be a lot of games where there's no benefit whatsoever, or a lot of workloads in general where there's no benefit whatsoever. We just want to improve where we can.’

I'm curious how you go about finding those improvements, because surely it can't be just throwing everything at the wall and seeing what sticks.

Hallock: No, well, sometimes it is. Okay. Sometimes it is. It’s a multi-part process. We do have a team that proactively goes out and evaluates things that are very popular, high profile in the community. Just because it's so obvious to go grab those and take a look. We also have automated systems that go through workloads and try to find opportunities. That does a lot of heavy lifting. Dirty word, but we have AI tools that can also help us analyze and find opportunities. So it's one part manual and a lot of automation to find these, and we go from there.

Adressing Nova Lake rumors

Roach: I wanted to ask something a little bit more direct about Nova Lake because speculation around Nova Lake has been going on for a while. I wanted to focus on the high-end, there's been kind of these endless rumors about a 52-core part. You have teased previously scaling up Thread Director to deal with these higher core-count CPUs. I'm wondering right now: What does something like this ultra-high core count, or like a high-end desktop processor, what is that offering right now to the market, in your view?

Hallock: My view has always been that the market will initially go. ‘Ah, what am I going to do with this kind of hardware?’ And then they figure it out. And my most recent example of this comes from my time at AMD. I was sitting at Computex, and at the time we were unveiling our first 12-core CPU. So that would have been the 5900X, I think, maybe the 3900x. It's been a while, and I was sitting in the room with a bunch of journalists who – 18 months ago – had been like, "Why eight-core in consumer? What are you even talking about? Why? Why does this exist?” Same people sitting in front of me. I'm talking about a 12-core CPU, and they're like, "Where's your 16-core?" Like a poorly, poorly kept secret at that point, right? Like it was only like a week away from getting announced, and everybody knew it existed.

How quickly perspectives change. Suddenly, we went from four-core to eight-core, to 12, to 16 in three years. And man, how quickly people’s opinions changed about the value of [higher] core counts. I don’t think, in the history of the PC industry, [that] bigger bar better, more performance better. Never a bad answer. And that does inform my thinking about the roadmap, and Intel’s thinking about the roadmap going forward. It’s never a bad idea to offer more hardware to people.

Roach: The irony. About that, I think it was Zen...It must have been Zen 2. The irony about that is that the 12-core SKUs are always significantly worse than the eight-core and the 16-core. I guess there are some workloads where it makes sense, but yeah, it's interesting to hear.

I think, you know, one of the big hopes for Nova is a competitor to V-Cache. I know this is something you're well aware of, and you know has been brought up numerous times. I watched some previous interviews that you did, I believe, with a recent one with PC Games Hardware, and you had mentioned ways to improve cache locality as something like, ‘Hey, we don't just need to stack a bunch more cache on the chip. We have other levers we can pull to find this performance or to offer something that the X3D chips offer.’

I'm curious what those levers are, because you've made reference to them before, and I just wanted to get a little bit more of a technical explanation.

Hallock: We will have to wait for the fullness of time, won’t we?

Roach: Yes, we will. Hey. You can’t knock me for trying.

Hallock: No, you have to try, and I appreciate and respect that. You know, my bottom line is this is going to be both an answer and a non-answer. Sorry. But I want to try to answer the question for the public more generally. We understand and appreciate there is a like a lot of hope, a lot of expectation, and a lot of desire surrounding Nova Lake. We get it.

And in some ways... selfishly. We’ve lived through it. Every negative comment, every bad tweet, every crappy article. It wears on you. It really does. And we want to deliver a product with Nova Lake that meaningfully addresses these criticisms.

Yeah, just pick one [CPU from Intel or AMD]. I’m not going to confirm anything else, but pick one. I think the Nova Lake product will do the job.

Roach: Okay. Well, that's good to hear. I have to imagine, especially with Nova Lake in particular, given how much they're, you know… There's probably a story on Videocardz or WCCFTech, probably a lot on Tom's Hardware every two or three days. So, yeah, it's a lot.

Hallock: Well, I think it’s reflective of how excited people are, how much anticipation, how much demand is pent up for this moment.

Roach: I know we're almost out of time, but I did want to share with you real quick. It was a big thing that we talked about this year at CES. Actually, I was talking to AMD PR, and they were getting reactions [to AMD’s new announcements]. And I told them, I was like, man, there is a Dark Knight sentiment. You live long enough to see yourself become the villain…happening right now in the industry. I think there's certainly a lot of that reaction that we've seen at least. So, for what that's worth…

Hallock: I have read those comments. Yeah. You know, a product like Nova Lake cannot address every single slice of the market. It just can't, given the current market that we're in. But I, I do hope and do believe that people will look back and go, ‘damn, you know, that was pretty, pretty freaking good.’ Yeah, that's what we were hoping for. And if Intel just keeps going, we're gonna be okay. And that's the trajectory we're on. That's who I want to be, as a business for gamers.

Roach: Yeah, I've heard you say that numerous times, which is encouraging to hear. So I appreciate it, and yeah, thank you so much for taking the time to do this. You know, I always enjoy talking with you, and I'm excited to see what comes next.

[Session ends]

First, we have the Steam Machine. Valve’s long-awaited console-like PC is here and much more expensive than anyone expected at over $1,000. You can easily put together a BC-250 build for around $400 or $500, and even less if you have a power supply and SSD lying around. If you can get in the realm of Steam Machine performance for half the price (and the BC-250 can, based on our testing), that’s pretty compelling.

There have also been some significant developments among the BC-250 community. The board only works in the first place due to a community-developed BIOS and GPU driver, and developers have continued to experiment with what’s possible with the hardware. Now, there are tools that enable all 40 Compute Units (CUs) on the board (it defaults to 24 CUs), as well as tools to enable the two disabled Zen 2 cores, taking the six-core CPU to an eight-core CPU.

Now, the BC-250 isn’t a cut-down PS5 APU, at least from a hardware perspective. It actually patches two more graphics CUs compared to the PS5. Though, as should become clear throughout this story, relating the BC-250 to the PS5 on anything but the silicon on the board isn’t the best idea.

All in, we spent about $350 on the BC-250, with around $200 of that going toward the board (it’s currently listed for around $175 on eBay) and the additional budget going toward a 3D-printed case, fans, and a power supply. You could spend as little as the cost of the board if you can 3D print a case, bring your own fans, and repurpose an old PSU and NVMe SSD. If you’re starting from scratch, you’ll spend between $400 and $500.

Even for “full” price, the BC-250 is significantly cheaper than what you can get elsewhere. The PS5 digital edition is now $600, while the Pro will run you $900. The newly-released Steam Machine starts at $1,050, and that’s with just 512 GB of storage. The BC-250 is significantly cheaper and offers performance that can rival these platforms. What you save in money, however, you spend in time.

The BC-250 is a great project if you like tinkering, but it’s not a set-it-and-forget-it gaming device, even after the initial setup. After a few weeks of using the board, that much became clear.

A PS5 APU, not a PS5: BC-250 specifications

The BC-250 is described as a cut-down PS5 APU, and that’s exactly what it is, but the “cut-down” portion of the description carries a lot of weight. It comes with eight Zen 2 cores, but two of them are disabled, and a 40-CU RDNA 2 GPU, though only 24 of those CUs work out of the box.

The community has been able to unlock all 40 CUs with good success. Ultimately, your mileage with unlocking all 40 CUs will vary; some boards will work just fine with all 40, others with 32 or 36, and some with the base 24. As I’ll dig into more later, I was able to unlock all 40 CUs and run them stably up to 1,850 MHz, much higher than the recommended 1,500 MHz max frequency.

Out of the box, both the CPU and GPU run at locked frequencies of around 3.5 GHz and 1,500 MHz, respectively. You’ll need to separately install a GPU and CPU governor for dynamic frequency scaling (a necessity in the case of the GPU, though optional for the CPU). Achievable frequency on the CPU and GPU is entirely determined by your thermals. Both governors allow for overclocking, but the BC-250 is thermally constrained, even with active airflow, so don’t expect to push far beyond the stock frequency, particularly on the CPU.

Unfortunately, storage is a big bottleneck for the BC-250, and one of the biggest points of divergence compared to a PS5. The M.2 runs at just PCIe 2.0 x2 speeds, delivering about 1 GB/s of maximum performance with an NVMe SSD. The good news is that, due to how slow the interface is, you can save some money and get a less-performant but larger drive for storage.

As of a few days ago, at the time of writing, some initial fixes to unlock the extra two CPU cores have rolled out, which I was able to get working after a bit of trial and error. Outside of the GPU and CPU, the BC-250 has a bit less L3 cache. The APU, from a hardware perspective, is very similar to the PS5. Though that ignores the complex I/O system present in the PS5, not to mention the various layers of software that Sony runs on the APU.

Given that the BC-250 wasn’t designed for gaming, it’s important to keep that context in mind. You could just as easily describe it as a crypto mining board that’s been repurposed for gaming as you could a PS5 APU that’s been repurposed for mining. The BC-250 is a mining board, and the only reason it works is due to a large number of enthusiasts trying to get the damn thing to work and sharing their advancements along the way.

Although Linux gaming broadly has made a ton of advancements over the past few years, the BC-250 has unique hurdles you need to overcome. It needs fixes to scale the frequency on both the CPU and GPU; otherwise, it’s locked at a fixed frequency. It needs a custom BIOS image to even boot, and a specific configuration in the BIOS to avoid immediately crashing. Those are all steps you need to take to get the BC-250 to work in the first place, let alone start optimizing it to squeeze out the best performance.

There is extensive community documentation for the BC-250, which I referenced ad nauseam throughout this process. It’s an excellent resource, but even still, I had to search out solutions outside of the documentation. This is cobbled together from community fixes, and the documentation seeks to cover as many distros as possible. But it’s nigh impossible to have complete documentation on the BC-250, as valiant as the effort linked above is.

Expect a bumpy (but rewarding) road. It’s better to think of the BC-250 as a project, rather than a commodity like the PS5. Yes, you can play games on it and get surprisingly good performance, but you’ll spend a good amount of time simply tinkering with the machine, at first to get it to work, and later to optimize it. And you will inevitably run up against games that either don’t work or have poor performance, prompting another investigation and optimization cycle. I find the process rewarding; others will find it frustrating.

Setting up and configuring the BC-250

Getting the BC-250 is only one part of the process here. At the least, you need a power supply that can deliver at least 20A on the 12V rail. A standard PSU will work, but FlexATX power supplies are a better fit. I ended up purchasing a 3D-printed case, along with a power supply, from eBay. The BC-250 documentation includes several PSU recommendations, along with case designs, if you want to go about choosing your parts piecemeal.

Here’s what I’d recommend at minimum:

• BC-250
• 300W+ PSU (at least 20A on 12V rail)
• 2x Arctic P12 high-pressure fans (if using CU unlock)

Regardless of the route you choose, double-check fan mounting points (there aren’t any mounts on the BC-250 itself) and case/PSU compatibility. Many small form factor BC-250 designs you can 3D print are designed around a FlexATX PSU. Before booting, verify your 8-pin pinout against the community documentation. If the 12V pins are in the wrong position, you can fry your board.

With the board ready, the first step is to flash a new BIOS from the shell. It’s straightforward enough, though without the modern conveniences of firmware flashback in the event of a failure. If you lose power, you’ll brick your board and need a hardware controller to reset it, so I recommend connecting to a UPS during the flashing process. You can grab the correct files from the documentation.

From there, you need to clear your CMOS by removing the battery and configure a few BIOS options to force the integrated graphics, set the UMA frame buffer size, and disable IOMMU. From there, you need to choose which Linux distro you’re going to use, which is very important. I’d recommend experimenting with a few different distros, especially if you’re new to Linux.

For gaming, the go-to options are Bazzite and CachyOS, the former of which I originally went with. There are some “optimized” images floating around for the BC-250 that supposedly rope in all of the configuration and fixes you need into a fresh OS image. I wouldn’t recommend using those. Setting up the BC-250 is getting easier by the day (I have found new fixes and scripts that automate installing several fixes just in the time I’ve been testing the board), so these optimized images are, at best, out of date, and at worst, not actually optimized at all. Tread carefully.

You don’t need an optimized image because, at least for Bazzite and CachyOS, scripts exist that can automate the entire setup process. Strictly speaking, the only thing you need is the GPU governor. Previously, you would need a kernel patch, but a GPU governor via an SMU now exists and is what I used. The governor is what allows dynamic frequency scaling on the GPU, as well as overclocking.

You’ll also need a compatible kernel, which is easier to manage on rolling distros like CachyOS. 6.18.18 LTS is the recommended kernel at the time of writing, but 6.17.11+ works, along with 6.12.x to 6.14.x LTS. Other kernels may work, though some (such as 6.15.0) are broken and will trigger a kernel panic.

With your distro chosen and a correct kernel working, here are the optimization steps I took:

• Install GPU and CPU governor
• Unlock 40 CUs
• Setup Zswap with 32GB swap page
• Install ACPI fix
• Configure PWM sensors

Again, scripts exist for these patches, the most critical of which don’t even require kernel patching any longer. The exact fixes you need and the method to install them will depend on the distro you choose, however, so make sure to keep the setup documentation handy.

The list above is in order of importance. Once you have the GPU governor, the next step is to try to enable the full GPU. Previously, you would need a kernel patch, but the bc250-cu-live-manager utility can enable the CUs via a User Mode Register (UMR) without the need for a kernel patch. Not only is this easier to do, but it also persists across updates, unlike a kernel patch, where new kernels will force you to go through the unlock process again. The end result is identical regardless of the path you choose.

I spent a good deal of time testing the 40 CUs before doing any other optimizations, and I’d recommend you do the same. Just because the board has 40 CUs doesn’t mean you can use all of them. I was able to unlock all 40, though not at the frequencies some others have reported. And some users aren’t able to use all 40, rooting out bad clusters for a 32-CU or 36-CU configuration. Overclocking-like trial and error is necessary here, though, as we’ll get to in the performance section later, experimenting is worth the hassle. Using all 40 CUs, even at suboptimal clock speeds, offers much better performance.

Although setting everything up on Bazzite should be easy, I ran into issues numerous times. It’s an immutable OS image, which can cause problems depending on the fixes you’re trying to apply. It’s a great choice if you want to quickly set up the BC-250, but it became clear that an immutable image isn’t optimal if you want to get the best performance. Further, some newer fixes simply wouldn’t work, such as unlocking the extra two CPU cores.

The CachyOS pivot

After a few days of optimizing, testing, and troubleshooting Bazzite, I made the hard decision to wipe the machine and start fresh with CachyOS. In hindsight, I should have started with CachyOS from the beginning for numerous reasons, but mainly because it’s a rolling Arch-based distro. Bazzite is a Fedora Atomic-based distro. It’s immutable, adding guardrails to make it difficult to break anything, but in the process, making it much more difficult to apply low-level changes like kernel patches.

If you’re not familiar with Linux and don’t care to become familiar, Bazzite is your best bet. It’s convenient, and it includes a ton of small community fixes right in the startup menu, such as the LSFG-VK project for Lossless Scaling. It became clear, however, that you’re trading performance for convenience with Bazzite. CachyOS is more hands-on, but it’s much easier to actually accomplish what you need to with the BC-250.

Most notably, CachyOS (and other rolling release distros) allow you to easily manage your kernel. There are alternative methods for critical setup items like the GPU governor and CU unlock that don’t require a kernel patch. However, having the ability to easily patch your kernel helps when you run up against compatibility or performance issues, allowing you to try alternative installation methods or community fixes.

Further, CachyOS has access to yay, or Yet Another Yogurt, the simple command-line call to search and install packages from the Arch User Repository (AUR). It takes some time getting used to living in the command line as often as you do on any Arch-based distro. But even knowing just a few basic commands allows you to accomplish what you want much faster than fumbling around with flatpaks, at least in my experience.

Getting set back up was simple thanks to a community script that automates nearly all of the configuration and optimization for the BC-250. The BC250-Toolkit script brings together all of the various community patches, including optional optimizations, and it just worked. Coming off of Bazzite, it was a treat not to run up against the immutable walls of the distro. I was able to accomplish in a few hours what took me more than a day with Bazzite.

CachyOS specifically has a few optimizations for gaming, as well. First, there’s the BORE, or Burst-Oriented Response Enhancer, scheduler that, as the name implies, is optimized for bursty workloads (Michael Larabel over at Phoronix has a great writeup on that). CachyOS also includes packages for x86-64 v3 and v4, the former of which is relevant to the BC-250.

These optimizations represent a substantial performance improvement. In Forza Horizon 6, for example, I went from 61 FPS at 4K with the Low preset to 72 FPS on CachyOS after it was configured properly (with 40 CUs in both cases). In Cyberpunk 2077, I went from 74.7 FPS on Bazzite to 82.2 FPS at 1080p with the Steam Deck preset, and perhaps more impressively, from 47.8 FPS to 56.5 FPS at 1440p.

I saw higher peak performance on Bazzite in Unigine Superposition, though that’s likely due to more thermal headroom for the GPU, as I wasn’t able to enable the extra CPU cores on Bazzite. I mainly wanted to show this chart to bring the “optimized” Bazzite image into the fold, which was supposedly an image that was already configured for the BC-250. Using a script to automate the installation of several tools (like the one available for CachyOS) is one thing. Using an entirely custom image is another. I’d suggest starting with a clean, official image regardless of the distro you choose.

Testing performance on the BC-250

The best touchstone for comparisons with the BC-250 is the Steam Machine. The Steam Machine is more powerful simply based on the spec sheet. I ran a truncated list of benchmarks to see how the BC-250 stacks up, as well as several additional benchmarks on the BC-250 alone. Performance here is tough to compare fairly. Even just with CachyOS and Bazzite above, we see large performance differences. And, as will become clear in this section, there were numerous tests that either showed performance issues inconsistently or simply failed to run at all.

Our best point of comparison between the Steam Machine and BC-250 comes in Cyberpunk 2077. Neither machine is capable of achieving a playable frame rate at 4K, but the fully-optimized BC-250 is just 6.7% behind at 1440p. At 1080p, however, the performance drop is 16.1%, exposing perhaps the biggest performance issue with the BC-250.

Forza Horizon 6 also highlights this issue; the CPU in the BC-250 is very weak. It’s not only weak because it’s using the aging Zen 2 architecture, but it also has only six cores (or eight, if you can enable them). It’s such a hurdle because the clock speed is severely limited to just 3.5 GHz, the same as the PS5. We are completely CPU-bound at 1080p and even 1440p in Forza Horizon 6, and then miraculously, at 4K, the larger GPU of the BC-250 is able to take over and actually beat the Steam Machine.

A system so hamstrung by the CPU makes sense in the context of a console. Sony has a performance target, and it makes sense to opt for a weaker CPU and a more powerful GPU. The CPU can reach that performance target. But in the context of a PC where you’re given more options, resolutions, and performance-enhancing features, the limitation of the CPU becomes clear. There’s an obvious performance wall you’ll run into with the BC-250 that no amount of tweaking can solve.

For a clear view of the CPU limitation here, look at the Forza Horizon 6 benchmark above. Running at 1080p with Low graphics is going to induce a CPU bottleneck in most systems, but the gap between GPU render performance and CPU render performance here is massive. According to the game’s benchmark, we were bottlenecked by the CPU entirely throughout the run.

Even at 4K, you can see that the CPU is still a significant influence on performance in this game, showcasing just how unbalanced this system is. Again, that imbalance makes sense for the PS5, but it’s a critical caveat with the BC-250.

In the gallery above, you can browse our other comparative results to get an idea where the BC-250 lands. I’m going to move past comparisons and look at the BC-250 in isolation. An apples-to-apples comparison really isn’t possible (nor fair) with the BC-250. That’s not only due to the wide performance window depending on your specific board and software stack, but also the clear performance limitations of the BC-250 that require certain workloads that wouldn’t make sense with other machines.

Chief among those limitations is VRAM, and memory in general. You have just 16 GB of GDDR6 for the whole system, which is much less of an issue on the PS5 where there’s careful memory management. As you can see in the chart above, I don’t have 4K results for Spider-Man 2 or Doom: The Dark Ages, and that’s due to a lack of VRAM.

In both cases, the games crashed at 4K, but worse, they wouldn’t start back up. I made the mistake of flipping to 4K before turning FSR on, which locked me out of starting the game until I manually edited the settings file prior to launch. 4K is possible on the BC-250, though it has a very narrow performance window considering the VRAM limitations and CPU performance.

Although FSR Performance mode is ideal for 4K (50% scaling, 1080p input resolution), I opted for Balanced to avoid the CPU bottleneck we can see present in other games (you can even see it here in some games, such as Spider-Man 2). However, turning up the input resolution also puts a greater strain on VRAM. You’ll need time and patience to experiment with these more demanding titles to find the ideal balance of settings on the BC-250; of course, if you’re just playing Silksong, none of this matters much.

The VRAM limitation is also relevant for frame generation. With such a narrow memory footprint, you’ll struggle to use frame generation at 4K if you’re already pushing the VRAM to its limits (those buffered frames need to live somewhere). Thankfully, Lossless Scaling is an option on Linux with LSFG-VK, which doesn’t strain your VRAM like in-engine tools.

An important aspect of performance with the BC-250 is cooling. Most governor profiles cap temperature at 80 degrees for multiple reasons. First, the heatsink of the BC-250 is closed on top. You can sit and rip apart the top of the heatsink for direct airflow with a pair of tweezers, but I left the heatsink on my board intact for now, using two Arctic P12 fans to assist with cooling.

Cooling is all the more important with the 40CU unlock and enabling the extra two Zen 2 cores. Stress-testing in Furmark over a 20-minute run, you can see how quickly the GPU throttles from 1,850 MHz back down to 1,500 MHz as it reaches the temperature cap of 80 degrees.

Remember, however, that Furmark is a stress test. I wasn’t thermal throttling in games, with the CPU and GPU settling around 70 degrees in Doom: The Dark Ages. I’ve included CPU and GPU power in the chart above, as well, and you can see that, combined, they rarely poked over 100W. Keep in mind that we’re exclusively looking at GPU and CPU power here, not whole system power. Whole system power can peak above 225W.

The stock heatsink and dual Arctic P12S do a good job keeping the BC-250 chugging along, even with all of the silicon unlocked and a moderate overclock on the GPU. However, Furmark makes it clear that this current iteration of the system can’t sustain its performance over long periods of time. It would take longer for that drop to show up in the most demanding games, unlike in Furmark, where we can see the drop in just 20 minutes. But I plan on revisiting the cooling solution in this BC-250 build. Maybe I can even raise the temperature limit closer to the 100-degree TJmax.

The bad and the ugly of BC-250 gaming

Although the BC-250 offers compelling performance for the price, I’d be remiss if I didn’t highlight the numerous quirks I ran into while testing. There are performance issues and limitations with the board that you can explain with hardware, and further compatibility issues that you can explain away with Linux. Then, there’s everything else: the weird bugs, quirks, and oddities that pop up when running a largely community-developed software stack on unofficial hardware that wasn’t built for this purpose.

The above image of Resident Evil 9 is a microcosm of what I’m talking about. The RE Engine is remarkably scalable, and that was on full display with my BC-250 testing. Requiem offered excellent performance, even all the way up to 4K. It didn’t feel like I was compromising much of anything with the BC-250. But then I turned on the “hair strands” setting, and the result is what you can see above.

No, it’s not due to the CU unlock, any overclock, or even the overlay you can see. It’s just something with this set of hardware, this software stack, and the hair strands setting in Resident Evil Requiem.

Similarly, in Doom: The Dark Ages, any resolution change I would apply necessitated a restart of the game. Otherwise, I’d get the ghostly streaking you can see in the image above. On one of these reboots, the game suddenly stopped rendering reflective surfaces, resulting in the strange black voids you can see below.

This isn’t a criticism of the BC-250, and certainly not of the remarkable work of the passionate developers and enthusiasts who’ve created fixes and workarounds for the hardware. The fact that this board boots at all and runs games is a minor miracle. The context of what the board is, however, is important.

You will, inevitably, run into strange issues that aren’t documented anywhere. These are two examples, but I also ran into strange problems elsewhere. The widely used MangoHUD overlay, for example, didn’t pull in my GPU’s clock speed correctly after an update, even after ensuring I applied the community fix through the GPU governor to map the reporting correctly. And once you add external devices, compatibility gets even more complex. The board doesn’t have Bluetooth or Wi-Fi, for example, and an external adapter should work (this UGreen Wi-Fi 6 adapter I purchased does), but it’s just as likely that a driver for another adapter doesn’t work or isn’t available.

I don’t have an issue with these quirks, but the BC-250 also isn’t my primary gaming machine. You should just be aware of them. And, if you’re going to invest in a BC-250 build of your own, be ready to encounter some strange issues that you might not be able to easily troubleshoot.

What’s next?

The BC-250 is a project, and like any good project, it isn’t done here. Now that I’ve messed around with the configuration, tried out different distros, got the critical mods working, and measured performance, I want to actually use the BC-250 long-term. Maybe I can find some additional optimization steps I can take, or workarounds for some of the strange issues that I noticed during testing. Regardless of what it is, I’m confident that I’ll mess around with the BC-250 more outside of just playing games on it.

My clear next step is to work on cooling. I kept things conservative here in order to get valid data in a timely manner, but I want to dig deeper into what I can do on the thermal front, not only to raise the temperature limit, but also to push the GPU overclock further. That may involve some CU tinkering, as well; if I can get similar performance at 36 CUs and better thermal headroom, I may be able to push higher overall performance.

The manufacturer was named as Shanghai Aishengna Electronic Technology Group by Reuters the following day, a state-owned company established in August 2023 with 7 billion yuan (around $1 billion) in registered capital that absorbed engineering teams from Huawei-affiliated startup Yuliangsheng and state scanner maker SMEE. The first units are due at SMIC, Hua Hong, and CXMT this year for production-line validation rather than volume output, but the machines are far from matching ASML's models and still require further testing.

Five machines represent about 3.8% of the roughly 130 immersion systems ASML deploys in a typical year (a class of lithography machines that put a super thin layer of liquid over the wafer during processing), with the European giant holding an estimated 98.7% of the total immersion market. The Chinese tool reportedly prints 28nm-class features in a single exposure and reaches 7nm, and theoretically 5nm, through multipatterning, the same route SMIC already runs on its installed ASML fleet. Neither company has confirmed the report, no machine has been shown publicly, and no throughput or overlay figures have been disclosed, against the 330 wafers per hour and 2.5nm overlay of ASML's current flagship immersion tools.

SMIC’s scanner

SMIC has been running a domestic immersion scanner, developed under the codename Mount Everest, since September last year, when the Financial Times reported that China's largest foundry had begun testing the Yuliangsheng tool with production-line integration targeted from 2027 after qualification.

FT compared the machine against ASML's Twinscan NXT:1950i, a system that entered the market in 2008, which puts the design roughly a decade and a half behind the tools ASML sells today. Yuliangsheng, founded in Shanghai in 2022 with 1 billion yuan (around $149 million) in registered capital, is understood to have delivered three lithography machines to fabs for testing by late last year, but this hasn’t been officially confirmed.

Many of the critical components needed for the machines are still imported from Japan, and delays at those local suppliers are what have capped 2026 output at around five units. The 2027 target of 20 machines is therefore an ambitious target that assumes a domestic component base that hasn't been established yet, and the imported parts remain within reach of any future export-control round.

18% litho localization

SMEE's most advanced shipping product remains the SSA600 series, a 90nm-class dry ArF scanner that was in mass production as of May last year. The 28nm-capable SSA/800 immersion tool the company announced in 2023 has never been deployed, and a state-media claim of its successful development was deleted shortly after publication. In December last year, SMEE won a roughly RMB 110 million ($16 million) single-source government contract for a KrF scanner specified at 110nm resolution and 15nm overlay, a useful indicator of where its production-grade capability is at the moment.

Domestic equipment took 35% of Chinese fab purchases in 2025, beating Beijing's 30% target and up from about 10% three years earlier, according to figures from China's semiconductor industry association. Etch and thin-film deposition passed 40% localization, and metrology reached 25%, while lithography managed just 18%, most of it in trailing-edge and packaging tools. From the end of 2025, new fab capacity additions are required to source at least half their equipment domestically, a mandate that guarantees the new scanners a customer base, whatever their specs turn out to be.

Etch, deposition, and everything else

Naura Technology became the world's fifth-largest chip equipment maker by 2025 sales, trailing only ASML, Applied Materials, Lam Research, and Tokyo Electron, and moving ahead of KLA. The company booked RMB 27.14 billion ($4 billion USD) in revenue in the first three quarters of 2025 against RMB 6.05 billion ($589 million USD) for all of 2020, holds an order backlog stretching into 2027, and has started developing lithography tools for the first time. AMEC grew revenue and net profit by more than 30% in 2025, while cleaning specialist ACM Research posted $901.3 million for fiscal 2025 and guided to as much as $1.18 billion for 2026.

SiCarrier, the Shenzhen firm widely linked to Huawei, debuted around 30 tools at SEMICON China in March 2025, spanning etch, deposition, metrology, and test, and was reportedly valued at RMB 65 billion ($9.63 billion USD) by September 2025 with more than RMB 10 billion ($1.48 billion USD) in orders. The U.S. added it to the Entity List in December 2024.

The sector's own leadership is less triumphant than the numbers suggest. In March, SMIC co-founder Wang Yangyuan and the heads of YMTC, Naura, and EDA firm Empyrean jointly described China's tool industry as "small, fragmented, and weak" and called for national consolidation, with Big Fund III's $47.5 billion being redirected toward lithography and EDA. The Aishengna venture, which merged the Yuliangsheng and SMEE teams into one state-owned vehicle, looks like the first product of that pressure to consolidate. China spent a record $49.5 billion on wafer fab equipment in 2024, per SEMI, and remains the world's largest buyer through 2027, even after a pullback in 2025.

EUV lithography

A Reuters investigation in December 2025, dubbed China’s “Manhattan Project,” described an operational prototype EUV light-source machine in a high-security Shenzhen lab, completed in early 2025, that generates EUV photons but hasn't yet exposed a wafer. More than 3,000 researchers are said to work across the program, with Huawei playing the coordinating role and SMEE handling system integration.

Two teams are chasing the light source: one led by Lin Nan, a Beihang University professor who worked at ASML from 2015 to 2021, has a solid-state laser-produced-plasma design running at 3.42% conversion efficiency against the roughly 5.5% commercial viability required, while Zhao Yongpeng's laser-assisted discharge plasma group at Harbin Institute of Technology has reached around 100W of EUV output against the roughly 600W that ASML's production sources deliver.

Beijing's target is chip output from the machine by 2028, with Reuters' sources calling 2030 more realistic. A separate strand of reporting described a reverse-engineered prototype built around an intercepted Cymer light source that has likewise produced nothing. Earlier claims of a Huawei EUV trial production in 2025 and mass production in 2026, which circulated via Chinese media in March 2025, were never confirmed by any primary source. Tsinghua University's accelerator-based SSMB concept, which would need a synchrotron of a staggering 100 to 150 meters in circumference, remains an academic project.

Export controls

The MATCH Act, introduced in the House and Senate in early April, would ban not only sales of immersion DUV tools to SMIC, Huawei, Hua Hong, CXMT, and YMTC but also the servicing of machines already installed, and would give the Netherlands and Japan 150 days to align.

At this stage, it remains a bill, not a law, but servicing restrictions would strike directly at the installed ASML base that produces every advanced chip China currently makes, including SMIC's N+3 node in Huawei's Kirin 9030. Chinese fabs have been preparing for exactly that scenario by using third-party engineers and gray-market parts to Frankenstein older ASML machines.

ASML's China exposure is already shrinking on schedule, with the country representing 20% of system sales compared to 41% in 2024 and 33% last year, even as the company raised full-year guidance to €43 to €45 billion in July. Likewise, Applied Materials expects to lose $600 to $710 million in China revenue this fiscal year.

Ultimately, three markers will indicate whether China’s domestic DUV program is a legitimate rival or yet more state-sanctioned hot air. The main one would be validated production wafers from an Aishengna tool at SMIC, Hua Hong, or CXMT with published throughput and yield, followed by delivery of anything close to the 20 machines planned for 2027, and a first exposed wafer from the Shenzhen EUV prototype before the 2028 target set by Beijing.

Optical connectivity has been used for decades, since electrical links cannot efficiently and reliably transmit data over long distances at high data transfer rates. But the cost and complexity of optical components limited their use to long-reach connections.

Today, the importance of CPO is rising: Electrical interconnects are no longer scaling as quickly as AI processors, and feeding thousands of accelerators within a data center requires an exponential increase in communication bandwidth. In a traditional optical networking architecture, the processor or switch ASIC communicates electrically with a pluggable optical transceiver located at the front panel of a server or switch. As signaling speeds climb to 200 – 400 Gb/s per lane and beyond, however, transmitting electrical signals over long copper PCB traces on a motherboard becomes increasingly inefficient, causing higher insertion loss, greater power consumption, and tighter signal integrity requirements.

While technically possible, it demands the use of better materials, re-timers, complex compensation processing, and equalization circuitry, which increases the cost of server infrastructure and its power consumption. CPO moves optical engines next to the processor or switch ASIC to shorten the electrical path before signals are converted into light, which means lower power consumption per transmitted bit, increased bandwidth density, and predictable scalability. As a result, CPO is increasingly viewed as a necessary technology for next-generation AI infrastructure.

Because AI is viewed as a major megatrend, CPO is set to become ubiquitous; there are dozens of companies working in the CPO ecosystem, including foundries, OSATs, optical I/O startups, laser manufacturers, fiber suppliers, packaging houses, and networking vendors.

As there are so many vendors pursuing different goals with different strategies, for this story, we are going to limit ourselves only to companies that actually produce things and whose roadmaps reflect their technological capabilities. So far, only four foundries have publicly articulated meaningful CPO manufacturing strategies: Intel Foundry, GlobalFoundries, Samsung Foundry, and TSMC.

The four companies each represent four different CPO strategies and have very distinct plans for the future, so their visions and capabilities may not be directly comparable. Nonetheless, reviewing their offerings gives us an idea about where the industry is going from the perspective of actual foundries.

TSMC: COUPE for everything

TSMC has historically been absent from the optical connectivity market as a product supplier. But having worked on silicon photonics for many years, it now has the broadest ecosystem and manufacturing roadmap with its Compact Universal Photonic Engine (COUPE).

TSMC's silicon photonics technology roadmap currently has three stages that span from a 1.6 Tbps optical engine with conventional pluggable optics to a 12.8 Tbps optical engine located within a processor package. The COUPE roadmap is tightly coupled with the company's advanced packaging technologies and the evolution of the company's micro-ring modulators (MRMs) that adjust light and directly impact performance. As a result, several TSMC customers (e.g., Nvidia) plot their silicon photonics strategies around the evolution of COUPE.

The first phase of the roadmap — called COUPE on PCB — relies on a COUPE that bonds a 65nm electronic integrated circuit (EIC) with a photonic integrated circuit (PIC) using the company's SoIC-X bonding technology. The initial implementation targets OSFP (Octal Small Form-factor Pluggable) optical modules and delivers 1.6 Tbps of bandwidth (2x the throughput of copper Ethernet solutions, along with 2x the power efficiency). Therefore, the first-gen COUPE is out of the scope of this article. TSMC says the SoIC-X interface features very low impedance and enables lower power consumption at high signaling speeds.

The second generation — dubbed COUPE on substrate — marks TSMC's transition from conventional pluggable optics to co-packaged optics (CPO). In this stage, COUPE is integrated with the company's chip-on-wafer-on-substrate (CoWoS) advanced packaging technology and co-packaged with a network switch ASIC. This architecture enables motherboard-level optical interconnects with aggregate bandwidth up to 6.4 Tbps, 2x power efficiency, and 10x lower latency than existing pluggable solutions, which is fantastic for a variety of applications, such as NVLink, Ethernet, and InfiniBand switches.

The third phase — called COUPE on interposer — pushes silicon photonics even closer to compute dies: A 12.8 Tbps optical engine is integrated directly into the processor package to enable ultimate bandwidth and scalability. Beyond doubling bandwidth again, the company expects the architecture to offer 5x power efficiency and 20x lower latency than today's pluggable solutions. That will make it particularly attractive for hyperscalers that build clusters with thousands of accelerators. Unfortunately, TSMC characterizes this phase as exploratory and has not disclosed its commercialization timeline.

The main agenda of COUPE is to move the optical engine as close to compute as possible. There is another dimension in TSMC's silicon photonics strategy, however: the evolution of the photonic devices themselves, the MRMs integrated into PICs. The company plans to bring the world's first 200 Gbps/lane (wavelength) micro-ring modulator into production in 2026 and then continue scaling the technology with 400 Gb/s MRMs, additional optical wavelengths, and denser fiber-array integration. This evolution is expected to increase COUPE’s bandwidth density from 0.5 Tb/s/mm in 2026 to 4 Tb/s/mm by 2030, providing an 8x improvement over four years.

It is noteworthy that TSMC presents the MRM roadmap separately from the evolution of COUPE packaging, which suggests that advances in micro-ring modulators represent an independent technology roadmap for the photonic integrated circuit (PIC), rather than being tied to a specific packaging generation. This potentially means that future COUPE products could adopt newer generations of MRMs regardless of whether the optical engine is mounted on a PCB, package substrate, or silicon interposer — although the latter will probably deliver the greatest system-level benefits by minimizing the electrical distance between compute dies and optical interfaces.

Intel: Optics for CPUs, GPUs, DPUs, and accelerators

Intel has been shipping various products with optical interconnections for decades and even attached its silicon photonics solutions to Xeon and Xeon Phi processors in the mid-2010s. Today, Intel's public CPO roadmap is less explicit than TSMC's, but its direction is fairly clear: move optical I/O directly next to CPUs, GPUs, accelerators, and eventually other compute chiplets. Meanwhile, so far, Intel has not unveiled plans to use its CPO technology for switches.

Intel's CPO strategy is largely focused on its Optical Compute Interconnect (OCI) chiplet, which is a self-contained optical I/O subsystem packing both EIC and PIC that can be co-packaged with any compute device using a PCIe interface to enable high-performance optical connectivity. Intel demonstrated the first OCI in 2024. That prototype implementation used 64 PCIe 5.0 lanes at 32 GT/s in each direction to connect to the host and provided 4 Tbps of bidirectional optical bandwidth over eight fiber pairs over a distance of up to 100 meters. Each fiber carried eight DWDM wavelengths spaced at 200 GHz, and every wavelength (lane) transported about 32 Gbps (8 FPs × 8 WLs × 32 Gbps = 2,048 Gbps in each direction).

The 2024 OCI implementation is good for testing the technology, but with rather slow 32 Gbps lanes, it has not been adopted commercially. Meanwhile, this technology has already been proven and demonstrated. Intel is currently working on its next-generation OCI with 200G/lane PICs to support 800 Gbps and 1.6 Tbps applications, though it is unclear when it is set to be available, as Intel has not yet disclosed an equivalent to TSMC's MRM roadmap.

It should be noted that future OCI implementations supporting bandwidth of 10s of terabits per second could interface with compute dies using next-generation PCIe 6.0 interfaces or even native die-to-die UCIe links when integrated into commercial products. Furthermore, Intel can naturally integrate OCI chiplets using its advanced packaging technologies to ensure high performance and low power.

As noted above, Intel's focus with OCI has always been its integration with CPUs, GPUs, DPUs, accelerators, or other compute devices, but not necessarily switches. It remains to be seen whether Intel's next-generation AI hardware roadmap will include switching silicon, but for now, it does not seem that the company is targeting optical switches with its OCI chiplets. Since OCI is protocol-agnostic, limiting it to compute devices seems like an artificial limitation, though we have little indication about Intel's reasoning behind the decision.

Samsung Foundry: Addressing everything

Samsung Foundry's silicon photonics strategy is arguably the most comprehensive among leading foundries. Unlike Intel, whose CPO roadmap is focused on its OCI chiplet for integration with compute devices, or TSMC, whose COUPE optical engine is another major ingredient of its foundry platform, Samsung intends to offer all types of optical connectivity devices, starting from pluggable transceivers in 2026, to switch CPO later on, and all the way to optical engines on the interposer of a processor package in 2030. Unfortunately, Samsung does not publicly provide a lot of information about its plans, so our main source of information will be SF's slide from a conference published by SemiVision.

This year, Samsung Foundry intends to offer a merchant PIC platform that relies on an EIC and a PIC mounted side by side on a PCB for conventional pluggable optics. The PIC will support 100 Gbps-class optical interfaces using CWDM technology, which is good enough for traditional pluggable optical transceivers (though Samsung does not specify the exact implementation), so there's no indication of CPO here.

In 2027, Samsung Foundry intends to catch up with TSMC's first-gen COUPE and offer an optical engine that stacks an EIC on top of a PIC using thermo-compression bonding (TCB). Samsung expects energy efficiency of this generation to improve from approximately 10 pJ/bit for its initial PIC platform to 5 pJ/bit, though Samsung has said nothing about bandwidth or latency. Samsung's TCB-based OE seems to be an intermediate product between merchant PICs and true CPO, so it will generally address onboard optics and pluggable transceivers.

By 2028, SF intends to move optical engines to the substrate of Ethernet or InfiniBand switch ASICs, which will be its first true CPO. The company intends to adopt hybrid copper bonding (HCB) with 10 µm pitches for its OEs to improve bandwidth density. Based on the slide from the roadmap, to address next-generation switches, Samsung is poised to increase optical lane speeds from 100 Gbps to 200 Gbps and ultimately 400 Gbps, although the company does not disclose when exactly each speed bin will be introduced (though it looks like 400 Gbps will come in 2029 – 2030) as well as the underlying modulator technology or other device-level details behind this scaling.

In 2029, Samsung Foundry will finally integrate its optical engine on an interposer next to CPU/GPU/XPU or other compute device, which will reduce energy consumption to 2 pJ/bit while providing extremely high bandwidth. Samsung calls this 'CPO Turnkey,' which implies that such integration will require its own packaging technologies. The next step in Samsung's roadmap is called 'next-generation CPO Turnkey,' and it integrates virtually the entire optical subsystem — including lasers — alongside compute and memory, which will be its ultimate CPO offering expected by 2030 and onwards.

While Samsung Foundry's ultimate goal to offer highly integrated turnkey CPO solutions is clear, the company also intends to offer two merchant platforms for pluggable optical transceivers, perhaps to de-risk development of its future products and to capitalize on the high demand for optical connectivity that exists today and will continue going forward.

GlobalFoundries: A bespoke vendor-agnostic OCI-MSA CPO platform

Unlike Intel Foundry, Samsung Foundry, and TSMC, GlobalFoundries does not produce or intend to produce AI processors, switch ASICs, or advanced packages. Instead, it aims to become a merchant co-packaged optics provider that will produce and sell bespoke CPO solutions that enable optical connectivity (including OCI MSA connectivity) for processors made by other chipmakers.

GF's silicon photonics effort dates back to the IBM Microelectronics acquisition in 2015, which brought IBM's silicon photonics technology and engineering teams into the company. Over the years, GlobalFoundries has expanded its silicon photonics capabilities into what eventually became the GF Fotonix platform and, more recently, the company acquired AMF and InfiniLink to further strengthen its production and design capabilities.

The key element of GlobalFoundries' CPO strategy is its Silicon photonics Co-packaged Advanced Light Engine (SCALE) platform that combines photonic IP, advanced packaging technologies, and a reference optical engine architecture that includes EIC and PIC. Unlike Intel's OCI chiplet, SCALE allows GF's clients to customize optical engines in accordance with their needs and have them manufactured by GF.

Under the program, GlobalFoundries manufactures the PIC and EIC using its own process technologies and then packages them into an OCI MSA-compliant optical engine using its methods. If the EIC requires a leading-edge node that GF does not have, it could instead be fabricated by another foundry and then integrated by GF. Customers then co-package the optical engine alongside their own switch ASICs or AI accelerators.

For now, SCALE supports both CWDM and DWDM transmission using qualified 50 Gbps and 100 Gbps MRMs, integrated photodiodes, and coupled-ring resonators. The platform has demonstrated bidirectional operation with up to 16 DWDM lanes per fiber, which theoretically opens doors to optical links with up to 1.6 Tb/s of bandwidth per direction. On the integration side of things, it supports advanced 2.5D and 3D integration using TSVs and copper bonding with pitches ranging from 110 µm to below 45 µm, which is good enough for integration using CoWoS-S and CoWoS-L technologies.

Just like Intel with its OCI, GlobalFoundries does not necessarily tie its SCALE CPO customers to its silicon or packaging technologies. Furthermore, the company allows its clients to customize their optical engines while retaining compatibility with the OCI-MSA requirements.

The future of CPO

Co-packaged optics (CPO) is set to become a key technology for next-generation AI infrastructure as conventional electrical interconnects struggle to keep pace with the bandwidth demands of rapidly developing AI processors.

Among foundries, TSMC, Intel, Samsung Foundry, and GlobalFoundries have each developed distinct CPO strategies that range from merchant optical engines to optical I/O chiplets and vertically integrated CPO platforms.

Given the different capabilities of the contract chipmakers, their roadmaps differ significantly in both scope and implementation, with some companies trying to lock in customers with a proprietary platform and others offering different degrees of freedom.

However, they all share the same objective: move optical interfaces progressively closer to compute dies to reduce power consumption, increase bandwidth density, and lower latency for the next generation of AI systems that will require considerably more bandwidth than today's clusters.

While AI-powered 3D generation has made it possible to create detailed models in minutes, turning those models into successful prints still requires significant technical work. From mesh repair and model splitting to print optimization and multi-color workflow management, many AI-generated models never make it beyond the screen.

Hi3D was built to close that gap between AI creation and physical manufacturing. Over the past year, the company has expanded beyond AI model generation, developing an end-to-end workflow designed specifically for 3D printing.

Today, Hi3D has established partnerships across the digital fabrication ecosystem, including Creality, MakerWorld within the Bambu Lab ecosystem, and xTool. These collaborations enable deeper integrations for printable model generation, AMS multi-color workflows, enhanced 3MF output, and broader digital manufacturing applications.

With its anniversary release, Hi3D takes another step forward. Automated part separation, multi-color optimization, color cleanup, material-saving algorithms, intelligent model orientation, and print parameter generation are now unified into a single AI-driven workflow.

The result is simple: tasks that once required multiple software tools and hours of manual work can now be completed automatically—helping creators move from image to printable object faster than ever before.

Hours to 2 Minutes: Auto Character Split with Built-In Print-Ready Tolerances

For makers printing large models—or working with smaller build volumes such as the A1 mini—model splitting is often one of the most time-consuming steps. Traditional workflows require manually cutting meshes, creating connection structures, and adjusting tolerances, often resulting in assembly issues after printing.

Hi3D’s Auto Character Split automates the entire process:

1. Intelligent Topology Recognition – Automatically identifies heads, torsos, limbs, and other structural components, generating optimized printable segments.
2. Watertight Mesh Generation – Every separated part is exported as a closed, watertight mesh ready for slicing and printing.
3. One-Click Joint Creation – Users can instantly add snap-fit connectors, mortise-and-tenon structures, or articulated ball joints for movable figures.
4. AI-Optimized Assembly Tolerances – Mechanical clearances are automatically calibrated for FDM printing, enabling reliable assembly directly off the build plate with minimal post-processing.

Tasks that previously required hours of manual modeling and adjustment can now be completed in just a few minutes.

Deep Integration with the Bambu/AMS Ecosystem: From AI Model to Print-Ready 3MF

Multi-color printing often requires extensive manual color painting and parameter adjustments, especially for complex AI-generated models. Color data can be lost during export, and preparing a print-ready file typically involves multiple software steps.

Hi3D streamlines this process through deep integration with the Bambu Lab ecosystem, featuring an official filament library, automatic color mapping, and enhanced 3MF generation.

Once a model is created, Hi3D automatically maps on-screen colors to official Bambu Lab filament profiles and exports an optimized 3MF file containing print settings such as temperatures, layer heights, infill density, wall parameters, and support configurations.

Instead of manually preparing files in a slicer, users can send the generated 3MF directly to Bambu Studio or OrcaSlicer and start printing immediately.

Reduce Multi-Color Waste by Up to 50% with AI Color Cleanup

For users of Bambu AMS and other multi-material systems, excessive filament purging remains one of the biggest challenges in multi-color printing. AI-generated textures often contain tiny color fragments and gradient noise, triggering unnecessary filament swaps that increase print time and material waste.

Hi3D addresses this with its Color Cleanup algorithm:

• Noise-Aware Color Merging – Automatically detects and removes insignificant color fragments generated by AI textures.
• Reduced Filament Swaps – Minimizes unnecessary color changes during slicing.
• Lower Cost, Faster Prints – Reduces purge waste by up to 50% while improving print efficiency by 30–50%.

Smart Build Plate Layout for Higher Print Success Rates

Model orientation is often the deciding factor in print quality and reliability. Hi3D’s Smart Build Plate Layout system automatically analyzes geometry, center of gravity, and support requirements to optimize model placement.

• Surface-First Mode – Prioritizes visible surfaces to reduce support marks and post-processing.
• Eco-Support Mode – Minimizes support usage while maximizing bed adhesion and print stability.

By automating decisions that traditionally rely on maker experience, Hi3D helps users achieve better print quality with less trial and error.

Bridging the Gap: From Beginner-Friendly Creation to Advanced Manufacturing

Beyond advanced tools for model splitting, multi-color optimization, and print preparation, Hi3D also lowers the barrier to entry through its Maker Templates. Users can upload a photo to generate printable figurines, pet models, or custom keycaps that are automatically optimized for 3D printing.

With its anniversary release, Hi3D is expanding beyond AI model generation into a complete AI-powered workflow built specifically for physical manufacturing. By combining AI creation, print optimization, and hardware-aware automation in a single platform, Hi3D helps creators move from idea to finished object with significantly less manual work.

As AI 3D technology continues to mature, the industry is shifting from simply generating models to generating manufacturing-ready models. Hi3D’s latest update represents another step toward that future, making 3D printing more accessible for beginners while providing greater efficiency for experienced makers.

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“Moore's Law is deader than a doornail, absolutely just toast,” said Nick Harris, chief executive of photonics firm Lightmatter, in an interview with Tom's Hardware Premium. The way to make a processor faster used to be to pack in more silicon, but there is a physical limit to how big a single chip can be – so performance now depends on networking dozens, then hundreds, of chips together. “Ultimately, networking is the future of computing,” Harris said. “The performance of these AI systems is completely hamstrung and bottlenecked by your ability to achieve low latency and very, very high bandwidth.”

It all comes down to scale-up and scale-out. Scale-up is the ultra-low-latency interconnect inside a single server, rack, or pod that makes many accelerators behave like one giant machine. Scale-out is the wider network, combining those machines into clusters. There is a third factor, called scale-across, that links whole data centers together. As Polina Bayvel, professor of optical communications and networks at University College London, told us, the hyperscalers are "on a drug which says that the more you put in, the better is the answer" – and between 72 and 144 GPUs now go into a single scale-up rack before it needs to reach outward.

Copper was sufficient within racks for years, but it has hit a wall, and a supply shortage. “Your arm reach, my arm reach, is about two metres – the copper cable is a little shorter than that,” Harris explained, “and we’ve already hit the limit.” Thus, optical interconnects are becoming more important, and moving from rack-to-rack cabling toward the accelerator package itself. Earlier this month, Elon Musk made moves to purchase Mesh Optical, as part of TeraFab and SpaceX's ongoing AI ambitions.

Moving light towards the chip

Today, optical signals usually arrive through pluggable transceivers, the standard modules that sit around 18 inches from the switch. The next step is near-package optics, which brings that down to roughly six inches. After that comes co-packaged optics, or CPO, where optical chiplets sit around the GPU or switch. The most ambitious version puts the optics on an interposer beneath the chip itself. “As you progress, you increase the speed and you reduce the energy consumption with each one of those leaps,” said Harris.

For now, the industry’s attention is on the step before the really radical one. “I think 2027 and 2028 are going to be very, very big years for near-package optics,” Harris said. He describes it as the test bed: the last stop before the optical transceiver effectively ships as part of the accelerator or switch, rather than as a separate component bolted on nearby.

Lightmatter is already building CPO parts at TSMC and GlobalFoundries, which it expects to ship in 2028. At the same time, it is working with customers on the more integrated interposer approach – the one for companies that, in Harris’s words, “realise they’d like to have an advantage in the market.”

The reason is power. Bayvel says about 20 percent of a data center’s energy goes into networking: The business of connecting GPUs and CPUs across racks, rooms and data centres. The other 80 per cent is consumed by the GPUs themselves. But she is clear-eyed about what happens to any savings. “Whatever energy you save through optics isn’t going to be there for saving the world,” she said. “It’s to stick another 1,000 GPUs in.”

Warring standards

Nvidia has a vertically integrated answer spanning both domains, from NVLink and NVSwitch for scale-up to Spectrum-X Ethernet and InfiniBand for scale-out. The rest of the industry, including AMD, Broadcom, Cisco, Arista, Marvell, Meta, Microsoft and OpenAI, is trying to prise that open through UALink, Ultra Ethernet and a new optical specification.

The sense that a standards war is building is becoming obvious. At Computex, AMD showed its Helios MI455X platform, a 72-GPU rack meant to rival Nvidia's Vera Rubin NVL72. But its scale-up fabric runs UALink-over-Ethernet rather than native UALink – a stopgap forced by the fact that dedicated UALink switching silicon from partners such as Astera Labs and Marvell was not ready in time. Engineering samples are due in the second half of 2026, with mass production slipping to Q2 2027, while AMD's next-generation MI500-series rack is expected to follow quickly.

Bayvel says the wider contest is one between CPO and linear-drive pluggable optics (LPO). CPO integrates lasers and optics alongside the processing and is probably more power-efficient, “but probably less reliable –so if your laser fails, you need to replace the whole board.” LPO keeps things in conventional pluggable slots and is more serviceable. “There’ll be a brave person who will bet their house on which will win,” she said. She guesses that they coexist, split by application, with a rough 60/40 lean towards CPO.

The laser bottleneck

The problem is that silicon can do almost everything except the one thing this industry increasingly needs it to do: shine.

Silicon is cheap, abundant, and brilliant for electronics. It is why the modern chip industry exists. But it is terrible at emitting light. “Silicon doesn’t emit light at all — that’s a big problem,” said Frederic Gardes, professor of silicon photonics at the University of Southampton, in an interview with Tom’s Hardware Premium.

For decades, the industry has worked around that by using so-called III-V materials such as indium phosphide and gallium arsenide, which are much better at producing light. But that fix brings its own problem. Those materials sit in a much tighter, more geopolitically exposed supply chain, with China controlling around 80 percent of supply. Getting lasers onto silicon is, Gardes said, “one of the key problems” the field now has to solve.

But it’s also where the money is. “Half of the revenue opportunity for this industry is lasers,” Harris said. “It’s a freaking power supply, but it turns out that it’s half of the revenue opportunity.” The irony is that the bit everyone needs most is also the bit that may prove most fragile. Gardes calls lasers “the weakest link.”

That weakness is already showing up in the supply chain. Laser makers Lumentum and Coherent are booked out for years. And the industry is starting to standardise. In March, AMD, Broadcom, Meta, Microsoft, Nvidia and OpenAI founded the Optical Compute Interconnect (OCI) Multi-Source Agreement, a hyperscaler-led effort to define a common optical physical layer for scale-up — one that can carry both NVLink and UALink, starting at 200Gbps per direction and scaling towards 3.2Tbps per fibre.

Whichever route wins, Bayvel worries the industry is fixating on the data center while neglecting the networks that must carry all this AI-generated traffic across land, sea and space. “Really, nobody’s looking at that,” she said, “and I think that's going to be a big problem down the line.”

USB4 Version 2.0, Thunderbolt 5, and a refreshed certification program converge around higher throughput, expanded power delivery, and an attempt to simplify a standard that has accumulated layers of optionality over nearly three decades, which we've explained in our USB decoded explainer.

So, what's next? In 2026, USB4 Version 2.0 and Thunderbolt 5 are now actively being implemented in the premium laptop and desktop segments, shifting from the long-running 20 Gbps and 40 Gbps era toward links that can deliver 80 Gbps bidirectional bandwidth and 120 Gbps asymmetric modes for display-heavy workloads.

From 12 Mbps to 80 Gbps

USB began in the mid-1990s to replace a sprawl of legacy connectors — serial, parallel, PS/2 — with a single, self-configuring interface. USB 1.0 launched in 1996 at just 12 Mbps, fast enough for keyboards, mice, and early webcams.

The 2000 release of USB 2.0 raised that to 480 Mbps, enabling external optical drives and the first wave of consumer flash storage. But it was USB 3.0 in 2008 that marked the transition to high-bandwidth, general-purpose peripheral buses, pushing 5 Gbps over a new SuperSpeed signaling layer. USB 3.1 and 3.2 followed, expanding bandwidth to 10 Gbps and then 20 Gbps with dual-lane signaling, but also introducing a tangle of naming conventions that made it difficult for users to identify what a port or cable could actually do.

Throughout this evolution, USB retained backward compatibility by design. A USB 2.0 flash drive could still work when plugged into a USB 3.2 Gen 2x2 port, and a modern USB-C charger could power an old USB 3.0 hard drive. This interoperability helped USB become the default connector for consumer computing. That said, it also left the standard fragmented beneath the surface. Features such as power delivery, alternate modes for video output, and PCIe tunneling were added incrementally, and not all devices implemented them uniformly.

The introduction of USB-C in 2014 began to consolidate physical connectors, and the debut of USB4 in 2019 marked the start of a new architecture focused on integrated high-speed transport. But many of USB4’s promises, such as 40 Gbps throughput and universal power, depended on how thoroughly a given device implemented the spec. That complexity is still being worked through, even as USB4 v2 and Thunderbolt 5 push bandwidth and capability well beyond what USB 3.x ever attempted.

The state of USB4

USB4 has been positioned as the unifying successor to the fragmented USB 3.x family, but the reality of this is more nuanced. USB4 is a modular architecture built atop the Thunderbolt 3 transport specification that Intel contributed to the USB Promoter Group. The standard defines a tunnel capable of carrying DisplayPort, PCI Express, and USB packets simultaneously, distributing bandwidth dynamically across workloads. All USB4 ports use USB-C as the physical connector and require USB Power Delivery for negotiation, but beyond that baseline, implementations vary widely.

Most more budget-conscious laptops and PCs ship with USB4 20 Gbps rather than the full 40 Gbps mode. Many omit PCIe tunneling, which restricts the use of external NVMe enclosures, capture cards that require direct PCIe links, and eGPU housings. Others support only single-lane DisplayPort tunneling, capping multi-monitor configurations even when total bandwidth appears sufficient.

Thunderbolt 4 remains the most complete expression of USB4 Version 1.0, because it mandates 40 Gbps operation, PCIe tunneling with at least 32 Gbps of sustained throughput, dual 4K displays, DMA protection, and 15W of minimum port power. Intel platforms consistently meet this bar. Meanwhile, AMD systems vary by OEM and chipset, with only a subset of designs offering full USB4 40 Gbps with PCIe tunneling.

This implementation variability reflects the flexibility of USB4’s architecture. The specification allows device makers to scale features based on cost and power constraints, especially in thin-and-light systems. For users, however, the USB4 label alone does not guarantee any particular performance characteristic without checking controller documentation or certification badges.

USB-C’s role has grown alongside this transition. The connector now consolidates power, data, and display signaling, and it is the required physical interface for USB4, Thunderbolt 3, Thunderbolt 4, and Thunderbolt 5. With Power Delivery 3.1, USB-C can negotiate up to 240W via 48V Extended Power Range modes across fixed 28V, 36V, and 48V power profiles. A single cable can power a high-end notebook, drive a high-resolution display, and host multiple data devices simultaneously because power negotiation occurs on the separate Configuration Channel, rather than the high-speed lanes.

Enter USB4 Version 2.0 and the shift to 80 Gbps

USB4 Version 2.0 marks the largest technical jump in USB signaling since the transition from USB 2.0 to USB 3.0. Instead of adding more lanes, the new specification doubles throughput by replacing NRZ signaling with PAM3 modulation. PAM3 encodes three amplitude levels per symbol, enabling 40 Gbps per lane across the same physical wires that carried 20 Gbps in previous generations. With two bonded lanes in each direction, USB4 v2 reaches 80 Gbps symmetrical bandwidth. An asymmetric mode increases this to 120 Gbps in one direction for display-oriented workloads, while the reverse direction can be reduced.

The transport layer receives several upgrades. PCIe tunneling now supports PCIe Gen4, which doubles per-lane throughput for external SSDs and eGPU boxes, relative to Gen3 tunneling in USB4 v1. DisplayPort tunneling advances to DisplayPort 2.1 with UHBR20 signaling, enabling dual 8K or a single 12K display with full chroma and high refresh rates. Backward compatibility with USB4 v1, Thunderbolt 3, and Thunderbolt 4 devices is retained, although those devices fall back to older signaling modes when connected.

Many certified passive USB-C cables up to one meter will support 80 Gbps, but anything longer typically requires active retimers. These active cables include embedded signal processing and sometimes operate directionally, which introduces design considerations for things like hubs and monitors. The USB-IF’s new labeling scheme identifies cables explicitly as USB 40 Gbps, USB 80 Gbps, or USB 240W to mitigate the long-standing ambiguity that accompanied earlier USB 3.x naming.

Thunderbolt 5 rides alongside USB4 v2 as its highest-fidelity implementation, with Intel’s specification guaranteeing features that USB4 v2 only defines as optional. These include mandatory 80 Gbps symmetrical operation, 120 Gbps asymmetric display mode, PCIe Gen4 tunneling with at least 32 Gbps of sustained throughput, and support for 240W charging. Thunderbolt 5 also mandates lane symmetry and strict latency targets to support high-bandwidth, low-jitter peripherals such as external GPUs, docked workstations, and multi-display gaming setups. We can see that in higher-end systems in mid-2026, the full-fat Thunderbolt 5 spec is rolling out, with our recently reviewed Razer Blade 16 (2026) coming fully equipped with the port.

Because Thunderbolt 5 builds directly atop the USB4 v2 physical layer, its cables and controllers are interoperable across the USB4 family, but with stricter certification criteria. In practice, Thunderbolt 5 functions as the version of USB4 v2 that guarantees complete feature exposure, similar to how Thunderbolt 4 served as the reference point for the USB4 v1 era.

The next decade of universal connectivity

There has been some discussion among users and industry analysts about what the future of USB might look like. A likely future USB5 standard might see schemes beyond PAM3, if USB-C’s electrical characteristics prove capable of sustaining higher speeds. PAM4 could be a candidate here. Meanwhile, copper links are approaching practical limits at these data rates, prompting the active commercialization of optical USB-C cables that embed fiber transceivers inside standard connectors. While expensive today, optical links could carry future USB4 v3 or USB5 signaling across tens of meters, without electromagnetic interference or the attenuation challenges of copper.

Power delivery beyond 240W is another open question. The 48V EPR ceiling aligns well with current mobile workstations and most gaming laptops, but heavier categories such as portable displays, desk-dock hybrids, and workstation replacements may increase pressure for higher wattage tiers. Whether USB-C remains the long-term vehicle for that expansion or yields to a successor connector will depend on thermal constraints and cable reliability at elevated voltages.

The USB-IF’s renewed emphasis on clear labeling may ultimately define how smoothly the transition unfolds. The shift from version-based branding to explicit “USB 40 Gbps,” “USB 80 Gbps,” and “240W Certified Cable” identifiers is intended to eliminate the ambiguity that has characterized the standard for nearly a decade. Adoption will, of course, depend on consistent enforcement by manufacturers and retailers.

USB has moved far beyond its origins as a peripheral interconnect. The convergence of USB4 v2, Thunderbolt 5, and expanded Power Delivery turns the USB-C port into a high-bandwidth, multi-protocol backplane for modern systems.

A single connector can now supply workstation-class PCIe bandwidth, high-resolution video, and sustained charging for devices that previously required dedicated power bricks. The next steps in the roadmap take USB into signaling regimes that challenge copper’s limits while retaining full backward compatibility with the ecosystem that grew around USB 2.0 and USB 3.x.

As the 80Gbps era proliferates, users will encounter hardware that behaves less like a simple peripheral port and more like an external extension of a system’s internal fabric. As we move through the second half of the decade, OEMs are now starting to standardize full-feature implementations rather than the partial configurations that marked the early years of USB4.

If that consolidation takes place, the connector that started as a replacement for serial and parallel ports will continue its evolution into one of the most capable physical interfaces in computing.

Like its predecessors, this is a technology and roadmap analysis rather than a technical deep-dive. We'll give you enough context to understand why neutral atoms have recently captured the attention of both the scientific community and major industry players, then look at what three of its key companies – QuEra, Atom Computing, and Pasqal – are building and planning.

What is Neutral Atom Quantum Computing?

Where superconducting qubits build their quantum systems from engineered Josephson junctions on chips, and trapped ions use electromagnetic fields to suspend individual atoms in vacuum, neutral atom quantum computing uses tightly focused laser beams – called optical tweezers – to trap individual neutral atoms in precisely controlled spatial arrangements.

Each trapped atom acts as a qubit: information is encoded in the atom's internal electronic states, and operations between qubits are performed by briefly exciting atoms into what are known as Rydberg states (the neutral atom mechanism for two-qubit logic gates). These are high-energy orbitals where electrons sit far from the nucleus, enabling long-range interactions between neighboring atoms when triggered. Switching a Rydberg excitation on and off is, in functional terms, the quantum analog of a logic gate – laser on, interaction happens; laser off, atoms return to isolated, quiet stability.

The atoms are laser-cooled to microkelvin temperatures during operation, but unlike superconducting systems – which require the entire chip and most surrounding hardware to be cooled to around 10-20 millikelvin – the surrounding hardware operates near room temperature. The cooling infrastructure is limited to a vacuum chamber and optical components, rather than a laboratory-filling dilution refrigerator.

The core quantum hardware is a vacuum cell that, in isolation, is about the size of a science experiment: a small glass chamber housing the atom array, surrounded by the optical tweezers. Pasqal has specifically cited total system power consumption of 4 kilowatts – a figure that would fit comfortably inside a standard server rack allocation.

Neutral atom systems require extremely stable laser sources across multiple wavelengths, precise spatial light modulators or acousto-optic deflectors to steer individual tweezer beams, high-resolution cameras for atom readout, and classical control electronics fast enough to execute real-time feedback loops during computation. The laser stack for a modern neutral atom system is substantial – a different beast from cryogenic engineering, but no less demanding of specialist expertise.

The majority of neutral atom companies – QuEra, Pasqal, and Infleqtion (a fourth player not covered here) - use rubidium-87 as their qubit atom. Rubidium is the well-trodden path: Its laser-cooling requirements are well understood; the required laser wavelengths fall in mature commercial product ranges, and decades of atomic physics research have produced a deep ecosystem of techniques and tooling around it.

Qubits are encoded in rubidium's hyperfine states – two specific energy levels in the ground state separated by a 6.8 GHz microwave transition – which are the same transitions used in atomic clocks, hence their extraordinary stability and coherence in the second-scale range.

Atom Computing elected a harder path: strontium atoms. Strontium's qubit transitions are more weakly coupled to environmental magnetic field fluctuations than rubidium's electron-based hyperfine states – which is technically significant because magnetic field noise is one of the dominant coherence killers in the rubidium qubit. This advantage comes at a cost: Alkaline earth atoms require more complex multi-wavelength laser systems, including ultraviolet laser sources, and the control techniques needed to isolate specific qubit transitions are more technically demanding. Coherence times up to tens of seconds have been demonstrated on strontium-based platforms, compared to the seconds-scale coherence of rubidium – a tangible advantage for deep circuits.

Why only Atom Computing? Part of the answer is expertise: CEO and founder Dr. Ben Bloom came from the NIST and JILA optical atomic clock community, where strontium is a well-developed tool. The research foundations were already in place. For most teams building neutral atom computers, rubidium is the faster, lower-overhead choice; the marginal coherence improvement from strontium doesn't justify the additional laser complexity unless you already have that expertise. It's a choice that illustrates a broader pattern in quantum computing: The optimal qubit technology isn't universal; it's relative to what your team knows how to build and maintain.

Advantages, challenges, and the mechanics of neutral atom quantum computing

Neutral atom systems carry two structural advantages that are difficult to replicate in other modalities.

The first is atomic identity: Every rubidium-87 atom is, by the laws of physics, identical to every other rubidium-87 atom. Superconducting qubits are manufactured devices with individual fabrication imperfections, requiring per-qubit calibration to achieve consistent performance. Neutral atoms need no such process – uniformity is a physics guarantee rather than an engineering achievement.

The second is reconfigurability. Unlike superconducting chips, where qubit connectivity is determined by physical wiring at fabrication time and cannot be changed, neutral atom arrays can be dynamically reprogrammed mid-computation. Atoms can be physically shuttled from one region of the array to another, placing them in proximity for gate operations and returning them to isolated storage afterwards. The processor's connectivity is software-defined rather than hardware-fixed: Any qubit can interact with any other. Readers of part one of this Quantum Roadmaps series will recognize the framing – this is the structural answer to the interconnectivity constraints we noted in superconducting architectures, where routing a gate between non-adjacent qubits requires threading through intermediate qubits (each step adding potential for error). Here, the qubit comes to the operation.

The reconfigurability described above is a result of modern, gate-based neutral atom processors implementing what is known as a zoned architecture, which partitions the atom array into three distinctly functional regions.

Storage zones hold atoms that are not currently being operated on. Because neutral atoms don't interact with each other unless deliberately brought close together, atoms sitting in storage zones remain isolated.

Entangling zones are regions where selected atoms are moved into close proximity, the Rydberg excitation is activated, and two-qubit gates are performed. Multiple entangling operations can proceed simultaneously in different parts of the array, as long as they don't spatially interfere – an equivalent to parallel gate execution in different lanes.

Readout zones are isolated areas where ancilla qubits – the backbone of error correction – are measured using optical fluorescence, without disturbing atoms in the storage and entangling zones.

This spatial separation is what makes mid-circuit measurement practical: You illuminate one region of the array while the rest of the computation continues undisturbed. This measurement occurs repeatedly throughout a computation to offset errors in real time, helping preserve the stability of the quantum state you're trying to compute – an architecturally non-trivial achievement.

One of the main challenges in neutral atom quantum computing relates to atom loss - neutral atoms are held in their tweezer traps by the focused laser beam. If a stray gas molecule drifts into the vacuum and collides with the trapped atom (or if thermal energy fluctuations become large enough), the atom can absorb enough kinetic energy to drift away into the vacuum chamber. Gone, simply – along with whatever quantum state was encoded in it.

This is called an erasure error, and while a whole-atom loss may sound dramatically impactful for any quantum computation you are trying to perform, it is actually easier to handle than most other types of quantum errors: You know exactly where it happened. A detection system continuously images the array, so a missing atom at a specific position is immediately flagged. Knowing the error location is roughly equivalent to knowing which memory address failed in a chip, rather than discovering that a subtly wrong value in the middle of your calculation chain threw the entire result out the proverbial window.

When this happens, a fresh atom is loaded in from a reservoir - a magneto-optical trap that continuously captures and cools background atoms adjacent to the main array. When it replaces the lost atom, it naturally has no memory of its predecessor's quantum state and is essentially a blank slate (called its electronic ground state). What preserves the logical computation is the error-correcting code: By distributing a single logical qubit's information across many physical qubits simultaneously, the code can tolerate the known loss of one physical qubit and reconstruct the logical state from the remaining ones.

The classical computing analogy is perhaps an ASIC versus an FPGA: a superconducting chip's fixed wiring is like an application-specific integrated circuit – high performance in the tasks it was designed for, but its capabilities are determined at manufacture. A neutral atom array's software-defined connectivity is more like a field-programmable gate array – somewhat slower per individual operation, but reconfigurable to whatever a task demands, including tasks the ASIC's architecture simply wasn't built to handle efficiently.

Where classical processors are measured partly by clock speed, quantum’s analogue to processing capability lives and dies by two metrics: coherence times (the window where calculations can be performed, which run to seconds in neutral atom quantum computing), and gate speed (how quickly individual operations execute). This places neutral atom solutions between trapped ions (seconds to minutes) and superconducting qubits (hundreds of microseconds).

Two open engineering questions balance the advantages described above. Rydberg gate operations run at approximately one to ten microseconds – slower than superconducting gates (tens of nanoseconds) and comparable to trapped ions. For very deep circuits requiring millions of gate operations, this matters. And while atom loss is now manageable via replenishment, maintaining the fidelity of the replenished qubit's reintegration into an ongoing error-correcting computation remains an active area of refinement.

QuEra

QuEra was spun out of Harvard and MIT in 2021, built on foundational research from Professor Mikhail Lukin's group and the MIT-Harvard Center for Ultracold Atoms. The company has raised over $507 million in total funding – including a $230 million Series B in December 2025, backed by Google Quantum AI, SoftBank Vision Fund, and NVIDIA NVentures – and operates from Boston, Tokyo, and the United Kingdom.

Its first commercial system, Aquila – a 256-qubit analog processor – launched on Amazon Braket in 2022 and remains the most-accessed neutral atom system by external user hours. From there, QuEra has consistently executed on its commitments. A 2023 Harvard-MIT-QuEra-NIST collaboration published a demonstration of 48 logical qubits in Nature, a result that remains the field's most-cited paper, and it established neutral atoms as the quantum error correction leader. A January 2026 follow-up pushed that to 96 logical qubits from just 448 physical atoms – the current verified world record, doubling the prior best - and the clearest demonstration yet of the gate-based, zoned architecture described above.

In June 2026, QuEra and AWS announced an expanded partnership to bring Libra – QuEra's first named fault-tolerant system – to Amazon Braket in 2028. Libra targets 256 error-corrected logical qubits at "megaquop scale," or one million reliable logical quantum operations at a 10⁻⁶ logical error rate. A follow-on generation – loosely termed "gigaquop-scale" (one billion reliable logical operations) – is described as the threshold for first commercial applications, suggesting a post-2028 system already in architectural planning.

It's worth noting Google's decision to both invest in QuEra’s $230M Series B and simultaneously launch its own neutral atom program in Boulder, Colorado, in early 2026 – while its superconducting Willow chip remains its production system – constitutes one of the strongest external validation signals that the modality has received. Google placing a parallel bet on its superconducting qubits doesn’t necessarily mean higher faith in one over the other, but it does mean something.

Atom Computing

Atom Computing was founded in 2018 in Berkeley, California by Dr. Ben Bloom, and has raised over $300 million in total funding, including $100 million in Series C and a $100-million Letter of Intent from the U.S. Department of Commerce, contingent on development milestones – both announced in June 2026.

The company's commercial strategy is tightly coupled to a strategic partnership with Microsoft, whose Azure Quantum platform provides the error-correction software stack that sits between the Atom's physical hardware and the application layer. The significance of this co-design arrangement is visible in the results: In October 2023, the company set a world record with a 1,225-site, 1,180-qubit array – the first gate-based quantum platform of any modality to exceed 1,000 qubits. A November 2024 joint demonstration with Microsoft produced 24 entangled logical qubits at 99.6% two-qubit gate fidelity, and 28 logical qubits running a benchmark algorithm with real-time error correction.

The company's most commercially significant development is Magne – currently being installed at QuNorth, a Nordic quantum initiative funded by Denmark's EIFO and the Novo Nordisk Foundation, expected to be operational in early 2027. Magne targets approximately 50 logical qubits from 1,225 physical qubits. It is, per Atom Computing's description, the world's first commercial quantum computer delivered with logical qubits as its primary specification – not a physical qubit headline count, but error-corrected logical qubits as the unit of sale. That shift in the commercial framing – from physical to logical – matters as a signal of where the industry is moving.

Atom Computing has not published a formal public roadmap. From available statements and a 2025 whitepaper, the company plans roughly a 10x qubit count increase per generation (a seemingly Moore’s Law-coded roadmap), placing next-generation systems in 2028 at approximately 10,000 physical and 100+ logical qubits. A June 2026 collaboration with UK company Nu Quantum will explore photonic networking between separate atom array modules – the interconnect approach that would allow scaling beyond single-array limits. Microsoft's own benchmarking framework anchors the targets: 50 logical qubits represents "general simulation advantage"; 100, "scientific advantage for classically intractable problems"; 1,000, "industrial advantage in catalysis and chemistry."

Pasqal

Pasqal was founded in 2019 in Paris, emerging from the Institut d'Optique Graduate School and co-founded by Professor Alain Aspect – awarded the 2022 Nobel Prize in Physics for foundational work on quantum entanglement. The company has raised over $300 million in funding, employs 275+ people, and serves more than 25 clients. A SPAC business combination with Bleichroeder Acquisition Corp. II signed in March 2026 at approximately $2 billion pre-money equity value, would bring Pasqal to public markets with roughly $649 million in cash, post-merger.

If QuEra is the scientific pace-setter and Atom Computing's distinguishing move is its Microsoft co-development model, Pasqal's differentiator is commercial and infrastructural: The company has deployed neutral atom processors directly inside high-performance computing centers as co-processors. Systems are installed at GENCI in France, Forschungszentrum Jülich in Germany, and CINECA in Italy. Revenue in 2025 reached 16.5M€ in commercial bookings, with clients that include Crédit Agricole CIB (portfolio optimization and derivatives pricing), Thales (satellite constellation planning), EDF (energy systems optimization), and CMA-CGM (maritime logistics routing). In early 2026, the company announced a demonstrated quantum advantage over classical methods in a materials science simulation of magnetic materials – a result being watched for peer-reviewed publication.

Pasqal maintains one of the most transparent public roadmaps in the space. Named hardware generations progress from Vela (2026, 256+ qubits) through Centaurus (2028, ~10,000 physical qubits, early fault-tolerant operation) to Lyra (2029, 100 high-fidelity logical qubits), with a 2030 target of 200+ logical qubits. The company also recently acquired Aeponyx – a Canadian photonic integrated circuit developer – to replace bulk laser optics with chip-scale photonic components, addressing both control precision and the manufacturing scalability of its control systems.

The difference in Pasqal's approach compared to that of Atom Computing and QuEra is that the company isn't yet deploying a digital, gate-based quantum architecture, but an analog one. Rather than executing discrete sequences of qubit operations, Pasqal's deployed systems evolve the entire atom array as a continuous quantum system — programming the physics directly, rather than translating a problem into circuit instructions.

If the earlier ASIC-versus-FPGA analogy held for the configurability question, this is the deeper version of it: Pasqal is currently selling the quantum equivalent of a dedicated hardware accelerator, purpose-matched to specific problem classes like materials simulation and combinatorial optimization, rather than a general-purpose quantum processor. That distinction helps explain both the commercial traction — analog quantum systems excel at exactly the optimization and simulation problems enterprises are already paying to solve — and the roadmap logic: Vela, the 256-qubit system launching in 2026, is where Pasqal begins the transition toward full gate-based digital operation.

Beyond Qubit counts

Raw physical qubit counts have dominated quantum computing headlines for years. But as we've touched on in parts one and two of this series, the metric that increasingly defines the fault-tolerance race is the ratio of physical qubits required to produce one logical qubit – the reliably error-corrected unit of computation that can actually be chained together to solve real problems.

The ratio depends on two things: the physical error rate of individual gates, and the connectivity of the hardware (which determines which error-correcting codes can be efficiently implemented). The ratios between the technologies we’ve already explored in part one (superconducting qubits and trapped ions) stand at around 1,000:1 physical to logical qubits and approximately 2:1 in terms of Quantinuum’s ion trap. Photonics quantum approaches, as explored in part two, are a different beast: Photon loss rates push physical-to-logical toward the 100:1 range or beyond – depending on where in the photon-to-qubit hierarchy you start counting.

For neutral atom quantum computing, QuEra’s approach currently sits at around 5:1. The numbers are more akin to apples-to-oranges than we’d like, but that’s the name of the game across these approaches. Improvements in error correction algorithms can and will change these ratios, but it’s a good approximation of where the technologies currently stand.

The neutral atom field has moved with unusual speed. The modality went from a 256-physical-qubit research system on AWS in 2022 to a 96-verified-logical-qubit world record in early 2026, a first commercial logical-qubit sale being installed in Denmark, and a named 256-logical-qubit fault-tolerant cloud system announced for 2028. That pace was not widely anticipated even two years ago.

As with the previous articles in this series, the convergence point is the same: fault-tolerant, error-corrected systems around the late 2020s to early 2030s, as the horizon for computers that genuinely outperform classical ones on commercially meaningful problems. What distinguishes the neutral atom path is the combination of software-defined connectivity enabling efficient error-correcting codes, coherence times in the seconds, and hardware that – for the first time across the three modalities we've examined – begins to look like something deployable in a conventional data center environment rather than requiring a specialized facility built around it.

DARPA's Quantum Benchmarking Initiative – our recurring external validation metric across this series – has selected QuEra for both Stage A and Stage B, and Atom Computing for its Stage B. That puts the neutral atom field in the same validated bracket as IBM, IonQ, and Quantinuum from part one, and Xanadu from part two. Whether neutral atom eventually takes the lead or the actual answer lies in a multi-modal quantum computing system is a question that the next few years will answer.

Sberbank, Russia’s largest lender and the driving force behind Russia's push into AI, is seeking to secure Chinese chips because Western sanctions continue to block its access to advanced hardware from abroad. Tom’s Hardware’s own reporting suggests the most likely candidate to power Sberbank’s systems is Huawei's Ascend 950 family, the most advanced silicon China currently produces.

Sberbank may well want chips, but getting hold of them from Huawei will be easier said than done. The Chinese chipmaker already has enormous orders to fulfill from ByteDance, Alibaba, and Tencent, with ByteDance alone committing $5.6 billion to the Ascend 950PR earlier this year. Huawei is targeting 750,000 units of that chip in 2026 and expects to earn $12 billion in AI chip revenue throughout this year.

But it highlights how U.S. sanctions are pushing China to develop its own chips, which in turn attract other controversial states. That potentially allows China to extend its reach across an entire parallel supply chain.

A sanctions-busting Sino-Russian alliance

“Economic restrictions are pushing Russia toward Chinese compute solutions,” said Allen Maggard, a senior analyst at C4ADS, the Washington, DC-based global security nonprofit, in comments to Tom’s Hardware Premium. But Russia doesn’t need much pushing, Maggard argued. “I don't see a scenario in which Russia can economically scale its domestic compute capacity using Western solutions alone,” he explained. In part, that’s down to the country’s constrained economy. “Its defence industry can afford Western chips for individual weapon systems – for now – but its civilian tech sector cannot. That leaves China's electronics and computing sectors as Russia's most economical option going forward."

Sberbank is not an isolated case in this way. Tramplin Electronics, a Russian sovereign IT company set up just over a year ago, is already marketing a processor called Irtysh based on a design from China's Loongson Technology. At the same time, Element, Russia's biggest chipmaker, in which Sberbank acquired a 41.9% stake in January, has reportedly begun producing microchips inside China for the Chinese automobile market. “A shift is clearly underway,” Maggard said, “but toward greater mutual access between the Chinese and Russian electronics sectors, probably skewed in China's favour.”

All that adds up to less of a meeting of equals than Russia becoming a dependent customer of a still-developing semiconductor ecosystem – though Maggard points out that under Vladimir Putin, the Kremlin will likely resist a total surrender of sovereignty. “Moscow would certainly prefer, and likely intends, to build a parallel technology bloc with Beijing,” he said.

Are actions backfiring?

The irony is that Western policy, which was designed to try and slow or stymie the development of China and Russia’s high-tech economy, may well have helped manufacture exactly the kind of trading bloc it set out to prevent.

The issue is compounded by uncertainty in Washington DC, where the inhabitant of the White House seemingly can’t decide what he wants from the situation. In the space of 12 months, the Trump administration banned Nvidia's H200, unbanned it, slapped a 25% tariff on it, and created a licensing framework that experts immediately called contradictory. On 13 January, the Commerce Department published a regulation permitting the sale of advanced AI chips to China – a move described by the Council on Foreign Relations as "strategically incoherent" – that, if implemented strictly, would block most exports, but if implemented loosely, would fail to address any of the concerns that motivated the controls in the first place.

Then, a day after the rule cleared Nvidia to sell, Chinese customs officers were reportedly told not to let the chips into the country at all.

China is capitalizing on the chaos. Beijing's drive toward self-sufficiency long predates anything Washington has done, said Mishel Kondi, a senior analyst with C4ADS's Human Security and Conflict Prevention team in comments to Tom’s Hardware Premium. "The PRC announced Made in China 2025 in 2015,” she points out. “That precedes export controls.”

Her analysis of Chinese government documentation over that period shows China has maintained a state-directed strategic priority of breaking from U.S. and friend-shored technologies. “In other words,” she said, “China's goal of building a more self-contained AI chip ecosystem predates U.S. export controls.”

Kondi said that it’s too early to judge whether the export controls are a triumph or a failure. "U.S. export controls have created real challenges for China's compute and limited its ability to scale and innovate," she explained, even as Chinese actors exploit loopholes through university procurement, transshipment via Southeast Asian jurisdictions, and corporate diversion through shell companies in secrecy jurisdictions such as the Cayman Islands. But there is a risk in feeding the beast. “The risks of accelerated domestication grow if China has greater access to advanced chips,” she warned, “and it would be a mistake to interpret that strategy as a response to export controls.” (It’s worth noting that China has reportedly gained access to an EUV machine that it was never meant to get its hands on.)

China’s growing chip dominance

China has been keen to bolster its chip sector for years, and it’s starting to reap dividends. Lisuan Tech – a Shanghai start-up founded in 2021 that nearly went bankrupt in 2024 – has begun shipping the LX 7G100, China's first fully homegrown gaming GPU, built on a 6nm process using an in-house architecture the company calls TrueGPU. It sells for roughly $480. Despite pre-launch claims that it rivaled Nvidia's RTX 4060, it’s still a stage behind Western designs. Independent benchmarks on Bilibili placed it closer to an RTX 3060. But it exists, it is wholly Chinese… and is being sold into a captive domestic market.

Beyond China’s border, the captive market increasingly includes Russia. The Russian market for GPU-based AI accelerators reached 62.7 billion rubles in 2025, according to Russia-based analysts TAdviser, up roughly 20% on the year before. Nvidia-based cards still account for around 84% of sales in volume terms, with the RTX 4060 the single most popular model. Russian customers are increasingly forced to look at Chinese cards as an alternative. Nvidia chips arrive through grey channels routed through China, Turkey, the UAE, and India at a premium.

In late May, the European Commission proposed a nine-month derogation on dealings with Yangzhou Yangjie Electronic, a Chinese chipmaker it had added to its 20th Russia sanctions package barely a month earlier, after EU automakers warned that chip stocks could run dry within weeks. That was because European carmakers needed access to the chips after the Nexperia crisis disrupted supply across the continent. Both Russia and China will have noticed the expediency with which Europe is willing to drop sanctions when needed.

By that point, China may be competing on the global stage. In late May, Huawei said its high-end chips would reach transistor density equivalent to 1.4nm processes within five years, unveiling a "Tau Scaling Law" focused on shortening interconnects and improving data movement rather than shrinking transistors. TSMC plans to begin 1.4nm mass production in 2028, meaning Huawei would still be three years behind, but the gap is closing.

That has experts like Kondi watching on carefully. “The risks of accelerated domestication grow if China has greater access to advanced chips,” she said, “and wider PRC access to these chips also empowers China's defence capabilities and enables it to expand its pervasive and repressive surveillance apparatus.”

Since opening the IIM-1 pilot line in April last year, the company has run wafers through Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached its expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike said the same month that more than 60 companies are in talks over 2nm capacity, but not one has yet signed a volume agreement. Given that its entire production base is the single IIM-1 facility, this leaves Rapidus with no diversification and no fallback site if the node doesn’t go ahead as planned.

However, the fab has the hopes of an entire nation pinned on it, and its plans are promising. Here's the breakdown.

A ticking clock on IIM-1

IIM-1, short for Innovative Integration for Manufacturing, broke ground in September 2023 at Bibi in Chitose, with the cleanroom completed in 2024. ASML delivered a TWINSCAN NXE:3800E in December 2024, the first mass-production-grade EUV system installed in Japan, and the tool completed its first exposure on April 1st last year. The pilot line also began operating that month.

Rapidus is currently targeting 2027 for mass production, but the company has given that date without any further qualification, with its business plan simply pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The same plan sets out a capacity ramp from roughly 6,000 wafer starts per month at the outset to around 25,000 within the first year, a fourfold increase that Rapidus is counting on to bring per-wafer costs down.

IIM-1’s siting in Chitose offers the abundant water that wafer cleaning demands, a cool climate that eases cooling loads, and some of Japan's strongest renewable-energy potential across wind, solar, and hydro. Local and prefectural authorities have organized around the project under a “Hokkaido Valley” initiative that aims to build a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.

The 2nm process

Rapidus’s 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to learn the node, with roughly 80 later returning to Chitose to transfer and tune the process for production, according to IBM.

The differentiator the company is leaning on is manufacturing flow, with IIM-1 running single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. It’s understood that the 2nm Process Design Kit (PDK) reached early customers in Q1 this year. Still, Rapidus hasn’t yet published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.

The program extends beyond the wafer, with Japan’s New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus providing funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also floated panel-level glass-substrate packaging as part of its longer-term roadmap. Building that back-end capability in Chitose rather than outsourcing it would mirror the integrated approach Intel and Samsung take.

Japan’s government as a shareholder

Rapidus’s February funding round closed at ¥267.6 billion, or about $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment, the first made possible by a 2025 revision to Japan's subsidy law permitting government equity in Rapidus, made Tokyo the largest single shareholder, with a golden share giving it veto power over major decisions, including share transfers and technology partnerships.

That round sits on top of a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, taking Rapidus’s combined capital and capital reserves to around ¥425 billion. The shares the state holds are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates, a clause that pairs with the golden share to give Tokyo both upside alignment and a downside lever.

Rapidus’s buildings and equipment are also currently owned by Japan's New Energy and Industrial Technology Development Organization (NEDO) and leased back, with the company previously obligated to buy them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.

The customer conundrum

Koike said in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10 of them. The names attached to those talks in reporting by TrendForce are IBM and the Canadian RISC-V accelerator startup Tenstorrent, with Fujitsu, a founding investor, separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, the firm led by chip architect Jim Keller and currently being considered for takeover by Qualcomm, agreed back in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center (LSTC) project, with Tenstorrent handling the CPU and Rapidus' AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.

Neither of these amounts to the committed high-volume order that Rapidus needs, and fast. Koike has described interest as growing “like a runaway steam engine,” but interest is not the same as allocation. Rapidus’s cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan’s current mainstream parts, a premium that’ll only narrow with volume.

Japan's two-track strategy

Rapidus is the leading half of a national plan that’s running on two tracks. The other is TSMC's JASM venture in Kumamoto, on the southern island of Kyushu, where a first fab backed by Sony, Denso, and Toyota began mass production in December 2024 on mature 12nm, 16nm, 22nm, and 28nm nodes aimed at automotive and industrial chips.

A second Kumamoto fab broke ground in 2025, and its planned node was upgraded twice, first to 4nm and then to 3nm, with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north. The Kumamoto plants carry far less technical risk and are already shipping; Rapidus carries nearly all of the program's execution risk and none of its proven output.

Even as the 2nm line ramps, Rapidus plans to begin 1.4nm process development in 2026, start construction on a 1.4nm fab in 2027, and reach mass production around 2029. The node leans on the company's research ties: Rapidus joined imec's core partner program in April 2023, giving it access to the Belgian institute's pilot line, and imec's position is that 1.4nm single-patterned layers require High-NA EUV, the 0.55 numerical-aperture tool that resolves the most critical metal layers in one exposure rather than several. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production, according to figures cited by both TrendForce and Nikkei.

Rapidus’ financials highlight how far all this is from being self-sustainable, having posted a ¥375 million loss for fiscal 2025 with total assets of ¥749.5 billion, while still aiming to raise around ¥1 trillion from private investors. The ASEAN+3 Macroeconomic Research Office has been cited as estimating that committed funding still falls short of the roughly ¥5 trillion needed for stable production, dependent on a private investor base that has yet to materialize at scale.

Meanwhile, TSMC moved its N2 node to volume production in late 2025, and Samsung began first-generation SF2 mass production the same year, which puts Rapidus roughly two years behind both on a node that customers can already buy elsewhere with proven yields. There’s also something of an adversarial backdrop developing: TSMC employees were reportedly accused last year of taking 2nm trade secrets said to be destined for Rapidus, an allegation a Japanese government official later characterized as non-critical. The episode has no confirmed bearing on Rapidus’s process, which is built on IBM IP.

Rapidus is targeting operating profitability around fiscal 2030 and an IPO in fiscal 2031, a timeline that assumes the 2027 ramp lands on schedule and that the customers now in talks convert into committed volume. Three milestones will indicate whether those targets are possible: a named customer with a committed volume order, evidence that 2nm yields are tracking toward the levels TSMC and Samsung already run at, and confirmation that the capacity ramp is hitting its 25,000-wafer target.

This transcript has been lightly edited for clarity.

Andrew E. Freedman, Tom's Hardware: I think I'd be remiss if I didn't talk about the elephant in the room, which of course is pricing. The Steam Machine starts at $1,049 in the U.S. for the 512GB option. How do you think that price is going to hit, and how do you think it reflects the vision of the Steam machine when you were building it?

Pierre-Loup Griffais, engineer, Valve: I think we'd be hard-pressed to make predictions on how exactly the market's going to respond to it. I think it's very different than what it looked like last year. And so in terms of what appetite people have to buy a gaming PC at a certain price, everyone's going to have a different opinion on whether it's a good value or whether the product makes sense for them. So I don't know if we're hazarding any predictions there.

But it's definitely the case that our original design, of course, was based on memory and storage prices from two years ago or so, and so we were in a different segment than we were hoping to be, but I think it's more of a reflection of where the market as a whole is than Steam Machine itself, right? So, I think if you're looking at building a PC from parts, either comparable horsepower or more horsepower, you know, you're probably looking at a similar price point here. At least that would be our expectation, right? That if you're, if you're looking at a trade-off of, "I want something that's about as powerful," you're still looking at a price that's roughly what we're offering there. And then you have all the things that you can't really build, like the form factor, the quietness, the CEC integration, the dedicated Bluetooth antenna for controller support. All that stuff is not really something that you can put in your own gaming PC and are still strong reasons that people might want to get the Steam Machine.

Freedman: Some of that definitely tracks. I've been going through our database, and things that were around the price point of the Steam Machine now are not the price of the current Steam machine anymore.

Yazan Aldehayyat, engineer, Valve: Yes, yes.

Valve speaks on Steam Machine compared to traditional consoles

Freedman: You're very much calling the Steam machine a PC. You haven't been calling it a console. Do you see that as a totally different audience, because the PlayStation 5 Pro is $899 right now, which is higher than it used to be? Do you see that as a competitor inside Valve, or are you looking at this like this is specifically a PC for a PC audience for people who already have Steam libraries?

Griffais: Yeah, I think it's a pretty different offering, right? I feel like if you're playing on PC, you're not looking at something like a console system and comparing just the price and the specs, because you have a bunch of games on PC, and you would have to buy those games on the other platform, or you would have to factor in whatever subscription cost there is to play online. There's a lot of factors there where it's not really apples to apples, right? And so I think it's an offering for folks that want to play on PC by definition or have some use for a PC that's around that powerful, it's probably quite a different decision than figuring out if something like a console is for you. There's a lot of trade-offs there.

Aldehayyat: I think the value of the Steam Machine is inherently tied to the value of your Steam library in a lot of ways. The more games you have on Steam, the more valuable the Steam machine is to you, and the Steam Machine makes your existing library even more valuable. So, those two kinds of decisions are very much intertwined, and I think at least early on, for sure, we suspect that it's for people who already have a big Steam library. The Steam Machine is just going to make a lot of sense to them.

Griffais: Yeah, and folks also have a lot of stuff on PC that's not necessarily on Steam, right? Like, there's a lot of different libraries on different stores, there's downloaded games, there's MMOs, all this stuff is also there, right, including productivity apps. There's some desktop use you can do with it. So, I guess the value of it is a little bit harder to express than just, like, you have that price and you have that library.

Freedman: Do you see Steam Machine as a possible entry point for someone who's just getting into Steam, or would you sort of advise those people to be starting elsewhere?

Griffais: For sure. Yeah, I think it could be. Usually, I guess it's hard for us to reason around what someone that's not on PC might or might not do, just because we're not really used to talking to those users. But I think we've seen some people use something like Steam Deck as an entry point for PC, and it seems to have worked for a bunch of people. I would think that Steam Machine is the same between the verification program and the SteamOS experience, that, you know, whose sole aim is to basically get out of the way, so that you can get to your games as easily as possible. I think that it's a good kind of niche for that.

Aldehayyat: I think it's like just to emphasize that point, it's we think it's a good entryway in big part because of how easy it is to set up and play games, right, like if somebody who's curious about PC gaming, and you're interested in getting into it, but you're a little intimidated by all the information that you need to know to build your own PC, or tinker with drivers, or whatever. The Steam Machine could be a really compelling offering for you, because then you can play those games with a lot less work, and maybe after you really get into it, you decide to build your own PC, and that's cool, that's great, that's awesome. But if you're a little bit intimidated, or maybe you're a PC gamer. Your life got a lot busier, you don't have as much time, that could be another way for you to get back into it. So the ease of use is something that we really cared a lot about was really important to us.

Griffais: We've heard that a lot for Steam Deck. People that are like, "I used to play on PC, I might have games on Steam, I might not, but I used to be a PC gamer, and you know, I have a family now, I have kids or something. I've been wanting to get back into it, but it seems complicated, or a time sink, or something." A bunch of people seemed to have found Steam Deck as a good way to address that, and I expect it might be the same.

Freedman: I mean, I can tell you, I have a toddler. I just finished Resident Evil Requiem, and I played the majority of it on a Steam Deck, because I was able to do it after her bedtime in a place in our apartment, far away from her room.

Aldehayyat: Great.

Griffais: First-person or third-person with Grace?

Freedman: For Grace, first-person. So I've got one more price question, and we'll get on to some engineering stuff.

Subsidizing hardware & the VRAM conundrum

Freedman: So you're not subsidizing the Steam Machine, which Valve said would make the PC a more closed platform, I guess maybe more similar to some consoles. but it's been said a lot that Valve subsidized the Steam Deck. I'm not sure I've actually found any definitive sources that say that. Did Valve subsidize the Steam Deck?

Griffais: Not really. If you look at certain SKUs at certain points of time, you know, it might be below or above cost by a small margin. I think there's some comments that we made around it, you know, being painful and all that early on, that was more about being as close as possible to cost than anything. Same thing here, right? If you look at where we thought Steam Machine was going to be in terms of pricing, and where we are now, and where Steam Deck used to be, and what it is now, you know, as we've had to announce some price changes recently, we're actually quite a bit more aggressive now, because we understand that the higher price is less accessible to people.

I guess we're able to be very aggressive with margin, right? And so we're even more aggressive now, trying to be as close as possible to the actual cost of the parts that we're shipping up.

Aldehayyat: But it's important that the Valve hardware is a self-sustained program; it's not subsidized by software sales, so that's kind of the piece to get across.

Freedman: So, on the hardware, one big worry back from the announcement was some of the hardware choices, which aren't, for lack of a better term, current gen, either in terms of AMD's technologies or in some cases compared to other modern graphics cards. The GPU specifically has 8GB of VRAM. How is Valve handling this internally, both your feedback and what you're doing with SteamOS?

Griffais: So there's a few aspects to that. One comes down to the system design when we picked the parts for it, and the GPU, and the amount of memory that was going to be available for the GPU specifically. I think we are very aware that, you know, eight gigs is kind of aggressive and could be kind of in the middle of what you would need there. But we made a lot of calculations on "what are you able to play with things like that?" and our conclusion was that for the stuff that you would want to play, and the level of details, and everything that you would want for that level of performance, you won't be in the spots where you're running out of VRAM.

The cases where you're running out of VRAM are actually cases that you would not want to be playing on a system like that. It'd be too slow. It's possible that there's some games in the future where that calculus is going to be a little bit different, right? Like, they take more VRAM at the same performance or something. But right now I think we're doing pretty good there. The cases where you're exercising the VRAM limits are actually cases that you wouldn't want to play as a real user, in my opinion. But that being said, between the Steam Deck release and now, we have done a ton of work on SteamOS to teach it about discrete VRAM.

We only used to support APUs, where we didn't have that problem — we had a whole other set of different memory management problems instead — and then improve the handling of VRAM under stress, under load conditions, and trying to get to the best outcome. So we're still rolling out updates there, but I think in practice the experiences improved rapidly around those cases. And we're continuing to do a bunch of work there.

Aldehayyat: I also want to just say that everybody sees that upgrade cycle for PCs have been slowing down dramatically. And more importantly, the new games coming out are able to scale generations of CPUs and GPUs a lot more gracefully than they used to. So, again, for us, the metric that we care about is, can you play the games on Steam? Can you play every game on Steam? And we think the Steam Machine absolutely can, right now, and we think the longevity for it is actually quite good, given the current reality of the upgrade cycles. I mean, maybe 10 years ago, a device like this wouldn't last as long, wouldn't have the legs to be competitive for as long. But given where we at now, even as of today, it can play your Steam library pretty well, and given what the market is doing right now, and the upgrade cycles, it still has the longevity to be a good device for people for many years to come.I think that one of the great things about the PC ecosystem is that games are not designed with a fixed performance target, they're able to come up and down, and you can tune them to be a great experience on a variety of hardware,

Griffais: And in a way, things like Steam Deck, and the new-ish, you know, segment of growing PC handhelds has been helping with that too, because people have scalability more in mind, I think. And there's been, there's been games, you know, that have made adjustments to have you know different level details or different presets for lower-end configs that I think you know that same effect will happen in the future and will pay dividends for all of PC as well. You have people that you know are probably playing on old laptops and things like that that maybe don't have to upgrade as much now because the developers, you know, have more scalability in mind, which is, I think, a good development for everyone.

4K capable, 1080p optimized

Freedman: I found that you know you can largely get playable frame rates on this thing. I mean, I'm someone willing to turn down settings.

But there was the 4K with FSR comment that had turned some heads initially in my testing. I found that's largely true, that you know, if you're willing to turn some settings down, you can get somewhere around 4K 60 with FSR. But why call it 4K capable, as opposed to really marketing it as a really solid 1080p or 1440p machine, rather than using FSR in the measurements, which kind of depends on which version of FSR the game is using?

Aldehayyat: A big part of that messaging actually came because we found a lot of people who are not as familiar with tuning their gaming settings want to just make sure that it's compatible with their 4K TV. So, basically, it's just our way of telling people that yes, if you have a 4K TV, you'll be able to use your Steam Machine with it. Not everybody understands the difference between render resolution and your TV resolution, so yes, for a lot of games, rendering a 1080p or 1440p is definitely the sweet spot, but we kind of wanted to make sure people understand that it still can work with your 4K TV, and you have the ability to upscale your content to that resolution, basically.

Griffais: And I think generally it's broadly true for the catalog as a whole, right? For sure, if you're looking at the current segment of games and what's coming out, then that's going to be what's stressing it out the most in terms of performance. Steam has a lot of games that extend decades into the past, as well. There's a ton of games that are playing that are coming out right now that are going to play just fine at 4K native on the Machine. There's there's a wide variety of different performance targets that games have, but in general, I think there's a ton of good experiences that you can have at 4K natively on the Machine. But for sure, for things that are coming out, or more recent games, I would personally probably pick, you know, 1080p render resolution, or 1440p, depending on how scalable it is.

Freedman: Speaking of 1080p, I noticed early on in the testing that 1080p seems to be the default resolution set across SteamOS on the Steam Machine. I was actually kind of surprised by it. I was going through, first on a per-game basis, boosting it up, so I could, you know, test multiple resolutions on my monitor. And I think very much like the sort of like the Steam Controller, there's not a huge on-ramp, not a lot of hand-holding on how to work this type of thing, so is there going to be any sort of messaging or sort of tutorials from Valve elsewhere that explain how to adjust these settings so you can get exactly what you're looking for?

Griffais: Yeah, I think we want to make that more visible and make it pretty obvious to folks that know what it is that this is happening. There's also different work that I think we want to do around that system. Another one is that when we're testing the games, we can also flag them for different default resolutions. So for an indie game or a game that's a little bit lower spec, or an old game, we should have the ability to say that game is actually just fine at 4K, or you know, other resolutions, so that you don't have to go change that setting. A

The thing we're trying to avoid is that some games, the way that they detect settings, you know, is all different. Games do that very differently, right? And it's possible for some games to start at 4K very high ray tracing. And the experience with that is not great. You don't want to start a game and have that sort of experience as a user, especially when you're trying to get to a point where most people can run a game and expect, you know, to be able to play it and not tinker with it. So we're trying to make sure the baseline is on the safe side, where you're going to have a fine experience. But for the folks that want more detail, more definition, they can access those settings, and they know what they're doing, right?

So I think that it could definitely use a little bit more visibility, so that you are very aware of what the OS is doing behind the scenes, and very aware of how you can go change that setting in a way that right now maybe is not as visible as it could be.

The verified program deepens

Freedman: Speaking of all this, there's the verified program. I mean, obviously, the verified program made it very clear if you could play something on Deck. On Steam Machine, assuming you turn off that 1080p flag, you get into more resolutions, more potential settings that are supported, really, just more options and games all around, because you have more powerful hardware. So, when something is verified on the Steam machine, is that specifically verified at 1080p, or is it going to be more like a modular thing where you explain where it's verified?

Griffais: The only thing that we want to make sure that a verified game gets at is that by default it's above 1080p 30, right? So that's really what we're shooting for, and again, it's all about the default experience, because I think all those things that you said are broadly true for the Deck as well. Like you can actually load up a game on deck, uncheck the resolution settings, set it to 4K, and set very high ray tracing. Look into all that stuff, and we're not trying to have the verified system tell you, like, hey, if you do that, then you need to change the settings to X and Y to get to a certain frame rate. We're just saying, oh, you're changing settings — at that point, you're outside of the realm of what the verified system is designed to do, because it's for those users that are not really doing that., and we expect the same to be true for the Machine Similarly as the deck, I think we'll see an effect where more and more games also pick settings that were intended for the Machine as time goes, as developers are putting those presets in, which will further make the default experience match the expectations of those users that are working from the verified system.

Freedman: I very clearly remember, I think one of those was Cyberpunk 2077. That was the first game where I saw that they had a Steam Deck setting. I was like, "Well, I know which one to pick."

Griffais: And, of course, most users never had to pick that, because it was selected by default, right? And if someone can have played the game and never seen that settings menu, that's a win in our book, right? But we also want to make sure that people that want to tinker with that can also do that, and every step of the way, we're messaging to developers, like, hey, even if you know you're running on a Steam Deck, even if you know you're running on a Steam Machine, do not disable settings, do not hide settings, that's not what people want to see. There's a lot of users that you might not be aware of that are all going to have very different opinions on what settings make sense on the device that you're playing, and we're really trying to make sure that you know the SteamOS experience upholds that core principle of PC gaming.

Freedman: I know that quite a handful of places have resources online — all they do is go through Steam Deck settings, tinker, and try to make it the best they can.

Hardware design, repairability and limitations

Freedman: So, I want to move this a bit more towards the hardware design. So every major component is cooled by one big heat sink with the 120 millimeter fan. I'm curious, how did you choose that kind of design? What are the benefits of that?

Aldehayyat: There's actually a couple of reasons. I mean, obviously, the first thing is that it's the most compact design you could come up with, right? Like, if you have one thermal module, then you know you could make the device as small as possible. So that was the number one sort of factor that made us go into that path. But the other thing that is interesting about this is that if you have two separate thermal modules, then each one has to be designed for the absolute worst case for each one, so you end up with a combined volume that is larger than the device is ever going to be. But if you have one, then it can share, basically, right? So, if the CPU is not eating up its entire thermal budget, the GPU can use that, or if the GPU is not eating its entire thermal budget, the CPU can share that. So that's one of the advantages, is that your ability to kind of allocate thermal headroom back and forth between the CPU and the GPU, and all that kind of stuff, independently.

To be clear, it was very, very challenging to make that design work, because when you're trying to touch off of different things, tolerances really eat you up, so you have to come up with, because you know, good thermal module design requires you to have the absolute minimum gap between whatever you're trying to cool and the thermal module itself, and the GPU die to the thermal module, the CPU die to the thermal module, they both have to basically have the smallest gap possible. Nut then in reality, like things vary and the CPU is tall and the GPU is taller and the motherboard bows and the thermal module has tolerances, so actually getting the design to have enough compliance in the right places to accommodate all those tolerances was by far the hardest challenge we had to overcome. But by overcoming it, I think we ended up at the most compact design, cost-effective design.

Griffais: It's also the quietest. Having one big module lets us have a big fan, which then can spin lower and, or, you know, lower RPMs. So we're pretty happy to have been able to make that work, because it turned out really good in terms of the ratio between how quiet it is and its normal performance.

Freedman: I opened it up to take a look, and I was able to take the whole thing out of the case with a single Torx T9 screwdriver. I don't think this was built with the idea that a ton of people were going to open it, but was repairability like a serious consideration of the design?

Aldehayyat: I mean, yeah, absolutely. We care about repairability a lot, and we tried our best to make the device as repairable as possible while still making it compact. I mean, those two things, generally speaking, fight each other. The more compact something is, the harder it is to take apart. So, we think we found a good balance. It's just kind of part of our philosophy, right? We think it's your device, so you get to do whatever you want with it. We definitely did not put any artificial barriers for people to do this, but we actually go a step further and try our best to make it as easy as possible. There's limitations to that, but things like the fact that the SSD is on the FPC that loops around to make the SSD accessible, that was not by accident, nor was it the easiest way to do this. We could have buried it under the thermal module, and that would be actually way easier, but we chose not to do that. It's just kind of a part of our philosophy, even though it's not necessarily the easiest or cheapest way to do things, we still think it's the right way to do things.

Griffais: Yeah, there's a few things that we generally try to have. You know, we can't hit them all the time, but I think we've, we've done, you know, a pretty good job of it ever since Steam Deck OLED, especially, making sure that, all screws use the same type, that they're machine screws, so you can take them apart and put them back without damaging some plastic or some wood receiver there. Also labeling stuff, right? Like, there's a lot of labels on the little connectors on the boards that we could easily have removed in production, but it's actually really useful; We're also taking them apart, right? It's useful for us, but I think you know, we definitely are not intending that most people will open this, like you say, but we want to make sure the people who do are not going to run into barriers.

Freedman: Yeah, I mean, there's an awful lot of Steam Deck mods. I'm sure a lot of those same types of people will be very interested in this. So a lot of the ports — this is probably by the design of making it so compact — they're attached via daughter boards and ribbon cables. Will those components be made available either for tinkerers or repair shops?

Aldehayyat: Yeah, so similar to how we did it with the Steam Deck, we're going to work with iFixit to make the parts available. We're going to basically try and make as many parts available as possible. I don't know for sure the full list of components that will be available, but I believe all the FPCs, daughter boards, and ports will be available through iFixit. I'm not sure which ones they decide to sell, or whatever. But yeah, our goal is to make those parts available as widely as possible.

Freedman: Is it any more difficult to make those parts available because of just the general component shortage, or are you stacked up on those ones?

Griffais: It's actually easier because they're on daughter boards, right? If that stuff wasn't the main board, then you'd be in trouble because there's some soldered-down memory, the VRAM, right, is the only soldered-down; the system RAM isn't, it's SO-DIMMs. If anything, it's a little easier for things like ports, and yes,

Aldehayyat: Believe it or not, right now, even things like the FR4, like the raw PCB material, it has shortages. But it just so happens that the memory shortage is way worse, so yeah, it's not really a major challenge to make those parts available at this point.

Freedman: And I'm assuming if you work with iFixit, that also means I'll be publishing maintenance manuals of some sort, right?

Aldehayyat: Yes, we're going to partner with them too, and they're going to create a lot of the repair manuals, replacement parts instructions, and things like that.

Freedman: Because opening it is super simple, but getting to the RAM, to the SO-DIMMs, that's got a lot of ribbon cables.

Aldehayyat: Yeah, we're aware of that, and I'll be honest, it is something that we really wanted to improve, and we tried to make the RAM more accessible, but there was just no real way to. I don't say it was impossible; it was just given the time and engineering resources we have, we just could not come up with a solution that worked. With the SSD, we were able to put on the flex and just read it around. With memory, you just can't do that because of signal integrity reasons. And trying to make an access hatch through the power supply just wasn't possible for safety reasons. So there's really no way. We couldn't come up with a solution, but maybe in the future we can come up with something,

Reckoning with hardware shortages and pricing

Freedman: I know in the blog post it says that there were some components you were barely able to source at all. Outside of memory, which components have been the most difficult to get for the Steam Machine?

Aldehayyat: Storage, obviously,

Freedman: You mentioned PCB, PCB materials.

Aldehayyat: Yeah. I mean, honestly, it's a little shocking right now. There are some shortages in plastics. There are some shortages in FR4, some capacitors. But all of those kind of pale in comparison to the memory and storage shortage. If this was a normal time, people would be concerned about these things, but given the memory and the supply shortage, this just doesn't really crack the top ten of problems. It's just kind of to show that really everything is constrained, but the memory and shortage overtake all of them. So that's really the primary focus.

Freedman: And the other interesting thing I found in sort of sourcing and building a design is that the blog post suggests you started sourcing parts somewhere in 2022, which suggests you've been at the Steam Machine for a few years. Are you able to talk about the general timeline of product development for the Steam Machine?

Griffais: The process starts very early. I mean, in terms of specific time frames, it's a little hard, you know, just because our memory is fried from working hard on trying to ship this thing. But you know, the design process, I think, probably started like three years ago, or so, when we were building machines from parts, trying to get at the right performance target. And then we started progressively moving to the next step, building it up as, like, a whole all-in-one thing, and then refining the form factor and all that. But from that point on, you're already starting to test the waters and getting in touch with suppliers, making sure that you're going to have multiple suppliers for the things that you're sure you're going to have, so it's definitely a long pipeline. But I would say plans for full-scale production of the object that you're looking at now is probably like a year or so.

Aldehayyat: I also think that the research and development, I guess we take more seriously here at Valve, and potentially some other places. Things don't go from "here's a presentation for a device," and then we start planning to make it. We first start by making some prototypes to convince ourselves that this actually makes sense, and there's an actual research phase that it's like, "OK, here are the technologies that we need to prove out, here are some prototypes we need, we think we need to make to make us believe that this device makes sense." There was never, during that phase, there was never really a plan to make a product. It was just kind of like gathering information, doing prototyping of critical technologies, proving them out, stuff like that, so that takes a while. And then after you do all that, you decide, OK, we want to make this thing happen. Let's start actually doing the development part of that, then that takes a year and a half, or something like that. So, depending on which, how you want to count things, it could have been three, four, five years, it could have been a year and a half, you know. But I would say it's just that we're constantly investigating different things, so it's kind of hard to put a timeline on it.

Griffais: For us, working on these things is very incremental and very gradual. So, in a sense, this all started 15 years ago when we got into hardware, because Steam Machine is actually one of the first things we worked on. The work on SteamOS that we started back then, you can draw a straight line through from that to where we are now: the work on inputs, even you know, the work on Steam Machine with OEMs, they taught us a bunch of stuff that we're leveraging right now. We're always trying to make sure that when we build something, we can reuse it in the future, and we don't have to start from scratch. And so, even back then, everything we were doing with SteamOS is fully represented in the current experience, and we're just building from here.

Windows support incoming

Freedman: Is Windows support still the same on Steam Deck? Will you be issuing new drivers?

Griffais: That's our goal. Right now, we're still working on certain drivers, you know, around Bluetooth and stuff, but that's definitely our goal. And we've been talking to AMD about the best way for users to get the graphics drivers as well, because I think it's pretty important that they can get at the latest fixes.

Aldehayyat: Yeah, but the model will be very similar to the way the Steam Deck Windows drivers work. It's going to take us a little bit of time after launch to get all the drivers lined up, but the general process of us publishing the drivers on our website will probably be the same.

Freedman: Is Valve still working on dual boot with Windows 11? I mean, the Windows resources page I just mentioned, it says the Steam Deck is capable, the OS installer wasn't ready yet.

Griffais: So it's something we're working towards. We don't have dual boot, an easy dual boot wizard plumbed right now. There's a few ways that you go about it, but right now, most of them include some manual steps where you repartition your disks and resize stuff by hand. We want to make that process easier in the future. But the thing that we're doing right now with SteamOS is we want to make sure that if someone builds a PC like a Steam machine, so something that has an AMD discrete GPU, and then whatever other parts they pick, they can choose whatever segment of GPU they want.

We're going to have a SteamOS USB install drive that they can just install SteamOS onto, so that they can have basically the same experience as the Steam Machine. It's pretty similar to how you would re-image a Steam Deck. But we want to make sure that if you're building from parts, that you have that option. So, we'll also be making that available at the same time.

Freedman: Will that mean at the same time as the Windows drivers, or—

Griffais: Just the product launch.

There's already SteamOS images out there that will work there, but we just want to make sure that we have one that has all the latest OS components that we're shipping at launch with Steam Machine, so that everything is ready from the get-go for that sort of experience.

Valve's new reservation system

Freedman: The reservation system you're using, I think it's the most radical one I've ever seen from Valve. I totally get why you're doing it. How'd you come up with that internally?

Griffais: Just lots of discussion. The reservation system that we originally came up with for the Steam Deck was also born of the same sort of discussion. We're talking about, "OK, here's the situation: how many units we have, what the user experience is going to be on purchase. Working back from that, how can we improve the user experience?" We see a lot of users stressed out about trying to secure supply for other products. We just see what's happening in the wild, and how people are frustrated with, like, not knowing where to get something, or having to periodically just recheck online retailers, trying to figure out.

I mean, my experience trying to buy PS5 kind of painted a lot of that stuff, in a sense. But the current iteration on the reservation system here, was just similar. We worked from, OK, we think the broad strokes of the system are good, but there's still an effect where people are rushing at the door, trying to refresh. Our websites might have problems, and then that seems unfair to people that run into that, right? We want to make sure that there's an even playing field initially, and then work from there. So, yeah, it's all I think based on discussions and user feedback.

Freedman: The blog post says that the people who get on the reservation queue, separate from the waitlist, could last through the end of the year. Is that all the first production run?

Griffais: We're constantly producing and trying to secure additional parts and stuff. There's not really discrete, you know, different runs and different segments, so it's a very linear thing. But for sure, depending on how many people sign up, it might extend into time frames that we're not really even sure of, because supply is so interesting.

Aldehayyat: It was just six months, as far as we were willing to make a prediction. As Pierre-Loup said, if there's more demand, we obviously are planning to make more, and so maybe there'll be another waitlist or something. But six months, we felt, is the appropriate amount of time to kind of put a cap on the waitlist, essentially,

Griffais: The interesting and I guess hard thing is that getting supply right now also means getting a wide variety of different prices, right? So it's possible that you would be able to make more, but in a way that the pricing ends up being different. And so we're still trying to figure that out, because if there's ever a bunch of people that want the machine, but the supply is not there on the back end, we'll have to make hard decisions about what are we doing to secure more supply, and does it still result with the product at this price, or would we have to rethink that.

Because we don't really know how the situation is going to continue to evolve. You know, maybe things are going to go back down, and then it's all good, and it can continue to go like that. But maybe not, and so I guess what we're trying to convey with this blog post is that it seems like all bets are off, and we're going to work through it just with the users as well.

[Interview ends]