With no new GPUs or major mobile CPU platform launches surrounding the show, the laptop announcements at Computex this year fell into two disparate categories, appealing to users with very different budgets. There were devices trying to compete with the MacBook Neo, like Dell’s attractive XPS 13 ($599 to start, with a limited-time student discount) and Qualcomm’s Snapdragon C platform, which promises laptops as low as $300 (we saw it in person in the as-yet-unpriced Acer Aspire Go 15). Both of those, like Apple’s competing Neo, will start with just 8GB of RAM (actually, Acer says “up to 8GB”), thanks to the ongoing AI-driven memory crisis.

On the opposite end of the Computex laptop spectrum, there was, of course, Nvidia’s long-anticipated Windows-on-Arm announcement: RTX Spark Superchip for laptops (formerly N1X), which pairs a 20-core Arm CPU with 6,144 CUDA cores. And since Nvidia and its partners (both laptop makers and Microsoft) are pitching RTX Spark as the agentic computing platform of the future, Spark laptops get all the RAM that portable, local AI PCs could ask for – up to 128GB of LPDDR5X.

The specs sound impressive, but let’s just say I am curious to see how Microsoft and Nvidia’s partnership will implement local agents into Windows 11 in the coming months, and how much useful and intuitive functionality will exist specifically for RTX Spark laptops by the time they actually launch. It’s not like Microsoft has the best track record when it comes to Copilot features, both in Windows and elsewhere. At Build, Microsoft focused on running OpenClaw in Windows with execution containers that create boundaries, such as certain files or programs.

And while we don’t yet know pricing for the RTX Spark laptops, with similarly configured DGX Spark desktops selling for close to $5,000, it’s a safe bet that high-end RTX Spark laptops are going to be well out of the price range of most consumers – although lesser versions based on N1 silicon (and with far less RAM) may slip below the $2,000 mark. While gaming performance on top-end Spark laptops is expected to be roughly similar to an RTX 5070, I suspect pricing will make the platform a tough sell for those primarily interested in gaming, just as it is for AMD’s Strix Halo – and AMD’s x86 silicon doesn’t have the gaming complications that Spark’s Arm CPU will have to navigate.

So it feels like AI developers (and I suppose well-heeled AI tinkerers) will be the primary early adopters of RTX Spark laptops when they begin shipping (this fall, according to Nvidia). By then, we’ll also likely know more about both Qualcomm’s Snapdragon C SoC and Dell’s Intel Wildcat Lake-powered XPS 13 (including how much it will cost to configure it above the baseline 8GB of RAM or with a Panther Lake processor). But as limiting and backward-looking as an 8GB laptop may be in 2026, so far I find these more traditional, more affordable laptops more interesting than RTX Spark – in part because while I don’t know exactly how they will perform, I do know generally what I will and won’t be able to do with them when they arrive.

And given how expensive seemingly everything is these days, it’s nice to see a few companies focused on making things look and feel nice while remaining relatively affordable. It may have taken a big push from Apple and its MacBook Neo. But if Windows wants to remain relevant as a platform, it needs both forward-looking options like RTX Spark and affordable options that still look and feel great, like Dell’s XPS 13. I just wish the latter could happen with more RAM than the laptop I bought in early 2019.

xTool launched its 01 Omni Printer today at a special event in Berlin that we attended. The digital-to-physical hardware firm claims this device is the “world’s first 4-in-1 printer,” and said it was ready for makers who want to “print it all.”

So, what are the four things this device can replace, exactly? It “natively combines UV, DTG (direct-to-garment), DTF (direct-to-film) and UV DTF technologies within a single desktop ecosystem,” says xTool. Pricing starts from $1,699 for the single UV edition, rising to $2,699 for the Dual UV edition, and peaks at $2,799 for the UV and DT Fabric Edition.

At the launch presentation, xTool CEO Jason Wang introduced his firm as a business established 10 years ago to build better digital tools for makers. Wang reckons xTool has now established itself as the No. 1 laser cutter maker and is leveraging the knowledge and software it has developed to expand into other tools, which will be valuable to makers.

Last year, xTool took its first steps into the printing market with a laser DTF, as well as the versatile but flawed M1 Ultra. This year, it has improved features and capabilities with the new M2 color craft laser (review soon) and today’s announcement, the 01 Omni Printer.

Both of the newest xTool products use the firm’s excellent xTool Studio software, which makes tackling a blank canvas very easy with its access to a cornucopia of online ideas and templates from xTool / Atomm and the associated community. Then there are built-in AI generators for logos, designs, illustrations, whole projects, and more.

After the presentation, I saw this software handle a single job between xTool machines. The workflow printed some bright glossy designs on the new 01 Omni Printer, then the powerful P3 laser accepted the work as input to accurately cut them all out. I also saw one computer handling multiple 01 Omni machines.

Why get a 4-in-1 UV printer?

The attraction of the 01 Omni Printer is the humongous range of materials you can print on with good results. Suitable mediums include wood, acrylic, glass, and metal, as well as customizing garments directly or producing complex UV DTF transfers. But, in practice, the system “can print on virtually any imaginable surface.”

One of the appeals of UV printing is that it can build up quite a strong texture. I think some firms have referred to the process as 2.5D printing, as it can output artwork that has up to 5mm of relief - that's a deep textural quality. This kind of work can use up a lot of the base white ink, but one of the makers told me xTool's ink was about a third the cost of that sold for the EufyMake UV printing device. This could be a serious draw for makers if it stays relatively affordable. Moreover, xTool asserts that its UV inks/curing don't smell so bad. On the day, I didn't notice the presence of any bad ink smells.

There were expert artists and makers at the event, showcasing a variety of projects pre- and post-show. I received a nicely printed cup and a candle from some of the kind makers in attendance. The cup was branded with some Berlin artwork as a memento, and the candle an xTool Studio (AI) generated floral motif. Both of these were produced using a rotary tool that the 01 Omni Printer can load.

Outputting each of these projects takes around 15 minutes, with the current firmware/software. For both these jobs, a few minutes were taken up by the machine scanning the 3D shape of the item on the rotary tool ahead of the print process. Then several white coats were required to build a good foundation for the final color layers. I'm not sure if these had a varnish applied. So, as well as CMY and K inks, the 01 Omni had tanks for white and varnish. Yes, it’s a CMYKWV process. The cup should be dishwasher safe, but we will see.

The makers in the demo hall were still pretty inexperienced with the xTool 01 Omni, of course. I’d say there were still teething troubles with the fresh hardware and its software integration. For example, I noticed a few false starts getting some jobs to output, and I heard that there had been a few issues with the print head and work colliding.

Both makers and xTool seem well aware of early wrinkles, so it's likely that the early kinks will get worked out. When asked about output times, some makers said that updates were coming to the 01 Omni Printer, which are expected to give it an extra shot of speed. Such considerations are very important for folks who are buying hardware like this to propel a business. With the considerable investment needed for this hardware, we recommend reading or watching a good third-party review. Review updates can also be important to make sure any early issues in day-zero coverage are tackled.

Imec's semiconductor process technology roadmap sets the general direction of industry development and showcases the challenges the sector is set to face over the next few decades. The roadmap gives us an idea of the timelines for the next major process nodes and transistor architectures the company will research and develop in cooperation with industry giants, such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML, among many others.

Imec's latest production node roadmap shows that the international research and development organization envisions 3 angstrom-class (0.3nm) fabrication technologies by 2038, but expects contact poly pitch (CPP) to stop scaling at A10 in 2030. While things might not be looking great for Moore's Law for imec, to continue scaling the chipmaker will need to adopt new technologies, such as CFET transistors and likely Hyper-NA EUV Lithography systems.

GAA transistors have seven years left

As the production of semiconductors becomes substantially more complicated, chipmakers no longer introduce all-new process technologies every couple of years. Instead, they typically roll out a new node generation every three years, with annual incremental enhancements in between. TSMC ramped N3B production in 2023, then followed it up with N3E in 2024, and N3P in 2025. Intel planned to follow the same pattern with 20A in 2024 (which was canceled), 18A in 2025, and 18A-P in 2027.

Next-generation process technologies will continue to emerge at similar cadences, according to imec's roadmap.

Interuniversity Microelectronics Centre considers that we now live in the 2nm-class era (N2) with contact poly pitch (CPP) of around 48nm, as well as cell height of around 132nm and 6 metal tracks. The reality may be a bit different as Intel's 18A has a CPP of 50nm as well as a cell height of 160nm (high density) or 190nm (high performance), whereas TSMC's N3 can boast with a CPP of 45nm. N2 (or 18A, if you wish) will be followed by its performance and efficiency-enhanced version in the next couple of years, which is in line with how the industry has been operating in recent years.

"Of course, we are going to extend our logic roadmap to the next generation beyond N2," said Julien Ryckaert, vice president of R&D at imec. "As you know, in two nanometers we have already jumped into a new technology device paradigm in the nanosheet era, and that is going to bring us deep into the Angstrom node."

Imec expects the A14-class to emerge in 2028. TSMC expects to start high-volume manufacturing using A14 in late 2028, so the actual ramp will happen in 2029. Intel's 14A follows the same pattern. With A14, imec projects CPP to shrink to 45nm and cell height to drop to 115nm and 5.5 metal tracks. Around 2030–2031, imec expects an A10-class technology — or a 1nm-class — with a 42 nm CPP and 98 nm cell height, which will still rely on a 5.5-track architecture.

It is noteworthy that gate-all-around (GAA) transistor-based nodes can be implemented either with conventional frontside power delivery networks or with backside power delivery, which reflects both imec's and TSMC's belief that BSPDN will not immediately become mandatory across all applications, as many of them do not benefit from it.

It is also worth mentioning that imec expects High-NA EUV tools insertion at A14, which is in line with Intel's plans, but not with TSMC's plans.

CFET insertion in the early 2030s

The roadmap becomes particularly interesting at the A7 generation, which imec expects to come in 2033. While CPP remains at 42 nm, cell height drops to roughly 80nm, and the standard-cell architecture moves to 4.5 tracks. More importantly, A7 is the point where CFET emerges as a serious candidate for production insertion. Instead of placing n-type and p-type transistors side by side, CFET stacks them vertically, which adds a third dimension to transistor scaling.

Imec’s roadmap explicitly positions CFET as the leading contender for A7, which means that the organization sees conventional nanosheet architectures approaching practical scaling limits in the early 2030s. Yet, since A7's CPP does not change from A10, chipmakers may or may not adopt the all-new transistor architecture at A7. Also note that imec seems to consider BSPDN as mandatory for CFETs.

"Moving into A7, the seventh-angstrom generation, which is the fourth generation of nanosheet, we see more and more challenges in scaling the conventional nanosheet device technology," Ryckaert said. "There is a contender that we have already mentioned as well in previous presentations, where CFET could start emerging as the solution for the next era of transistors."

Beyond A7, the roadmap seems to depend on CFET evolution. The A5 generation, expected in 2035–2036, retains a 42nm CPP but reduces cell height to about 64nm using a 4-track library. By 2038, the roadmap reaches A3 with a 39nm CPP and 50nm cell height. At this point, imec envisions sequential CFET implementations and eventually bonded CFET structures that further exploit vertical integration. In fact, vertical integration seems to be the new way we should look at Moore's Law's evolution. Meanwhile, to get to a 39nm CPP and 50nm cell height, chipmakers might need to use Hyper-NA EUV lithography scanners, according to imec.

Redefining Moore's Law

The most interesting thing about imec's roadmap is that it essentially redefines what Moore's Law means. Traditionally, we consider Moore's Law as the observation that the number of transistors on a chip of a certain size doubles every 18 – 24 months, as they are getting smaller.

The fact that imec shows CPP stuck at 42 nm from A10 through A5 is almost an admission that classical transistor scaling is running out of steam, and future density gains must come from vertical integration. In the imec roadmap, transistors are still getting denser, but not exactly because individual transistors are shrinking at the same pace they used to decades ago, but because chip designers can fit more logic gates into a given area because of different transistor architectures, 3D integration, or backside power delivery.

As a result, in the coming years, we may no longer care how many nanometers a gate pitch is, or individual transistors, but rather the size of a standard cell. After all, when companies like AMD, Intel, or Nvidia design a chip, they do not place individual transistors, but actual blocks built from standard cells. Yet, calculating the size of a standard cell is complicated because while cell height is fixed, its width is not, and depends on the actual function.

Library height × CPP is not the size of a specific standard cell. It is the fundamental footprint unit of a standard-cell library and a widely used proxy for logic density. Actual standard cells have that height, but their width varies depending on function. Instead, the industry uses such metrics as logic cell area (standard-cell footprint) — Cell Height × CPP — that measures the actual footprint of the logic building blocks that designers use, not just the dimensions of individual transistors.

The transition from 6-track cells at N2 to 3-track cells at A3 illustrates how future density gains will rely as much on shrinking standard-cell height as on reducing transistor pitch. As a result, despite the fact that CPP shrinkage is expected to stall for years, logic cell area is set to decrease; designers will be able to extract transistor density gain from future nodes, proving that Moore's Law is still here.

Hetrogenous Large-Scale Integration × Cross-Technology Co-Optimization

Given all the changes that the semiconductor industry is already experiencing and what is set to come, imec believes the sector is entering a new era that it calls Heterogeneous Large-Scale Integration (HLSI). The concept reflects a shift away from traditional VLSI scaling, where progress largely depended on the evolution of transistors and increasing transistor density, toward a model that combines multiple technologies within a single compute platform.

Future systems will rely on heterogeneous integration of logic, memory, power-delivery circuitry, and optical I/O using advanced 3D and 3D + 2.5D packaging technologies, according to imec's predictions. Of course, the organization expects AI workloads to become the main driver of semiconductor demand, so expect both compute architectures and the semiconductor industry to evolve in a direction that satisfies the needs of AI applications.

"As we will move deeper into AI-driven architecture, we will need to double down on the heterogeneity that technology offers, and this will probably move the VLSI paradigm to the HLSI paradigm, the Heterogeneous Large Scale Integration," Ryckaert said.

To optimize future platforms on the system level rather than develop individual components in isolation, imec has established its Cross-Technology Co-Optimization (XTCO) framework, which could be seen as an integral part of the HLSI vision. XTCO is designed to wed development logic, memory, interconnects, power delivery, cooling, and packaging, and assesses their impact on key system metrics such as compute density, energy efficiency, thermal performance, and memory.

It remains to be seen how this is going to work out, if at all, given the fact that logic process technologies are developed at foundries, memory technologies are designed at DRAM makers, whereas cooling is developed at third parties like CoolIt or Frore Systems.

Power and cooling

As individual chips get denser and more power-hungry, power delivery is set to become a critical bottleneck, which is why all leading chipmakers — Intel, Samsung, and TSMC — are implementing or set to implement backside power delivery technologies and integrated voltage regulators.

Imec expects future AI accelerators and CPUs to rely on a combination of BSPDN, IVRs, embedded capacitors, and advanced power semiconductors to reduce losses and improve efficiency. Over time, more power-conversion stages are expected to migrate from racks and motherboards into packages themselves to deliver cleaner power directly to transistors.

Since we are talking about multi-chiplet packages consuming kilowatts of power, the importance of cooling is hard to overestimate. For sure, 3D stacking and CFETs will not make cooling any easier because thermal power density is set to increase linearly with the number of transistors, thermal resistance is set to increase, and local hotspots will become an even bigger problem than they are today. As a result, imec expects future compute platforms to rely on a combination of more advanced cooling technologies, improved heat spreading, fine-grained thermal sensors, and system-level thermal optimization techniques.

"At the end of the day, what we need to achieve is a reduced energy cost of data movement. We need to improve the TDP for better thermal management," Ryckaert said. "We need to improve the efficiency of the power delivery, and we need to obviously increase the compute density to improve the functionality."

In short, useful future scaling will depend not only on the ability to build transistors and increase their density, but on delivering power efficiently and removing heat effectively.

Paving the path forward

Imec's latest semiconductor roadmap projects logic process technologies all the way to A3 generation around 2038 and argues that Moore's Law can continue despite the slowing pace of traditional transistor scaling. While the Dennard scaling for semiconductors is over, there are plenty of interesting things incoming.

According to the roadmap, conventional gate-all-around nanosheet transistors should remain viable through A10, while CFET architectures become a candidate for production insertion at the A7 generation around 2033. Meanwhile, future transistor density gains are expected to come from vertical integration, reduced standard-cell footprints, and eventually sequential and bonded CFET structures rather than from aggressive shrinking of transistor dimensions.

Solidigm is arguably one of the most mysterious storage companies in the industry today. The company is a wholly owned subsidiary of SK hynix, yet unlike its parent company, which produces charge-trap flash memory, it uses floating-gate 3D NAND memory that it develops and manufactures internally at a dedicated fab in Dalian, China.

Solidigm originates from Intel's Non-Volatile Memory Solutions Group (NSG), the company's NAND and SSD business unit, which used to have a unique technology strategy that differed from that of other flash and drive producers. To that end, it is not surprising that Solidigm also has a unique positioning as it only offers data center drives, most of which are based on floating-gate memory and proprietary in-house designed controllers. Furthermore, Solidigm is a fully vertically integrated company.

At Computex 2026, we sat down with Avi Shetty, who is vice president of AI ecosystem, Solutions & Market Enablement at Solidigm. Before his current position at Solidigm, he spent 14.5 years at Intel's storage division, so he has deep knowledge both about technology and the market. During our conversation, we discussed how Solidigm keeps evolving, including floating-gate NAND memory, advanced packaging technologies, next-generation SSDs, liquid-cooled SSDs, and more.

Anton Shilov: Could you introduce yourself to our readers and describe what do you do at Solidigm?

Avi Shetty: My name is Avi Shetty. I work at Solidigm, where I help lead AI solutions and ecosystem initiatives. My team works with global platform providers, software ISVs, and ODMs to ensure Solidigm solutions are validated, benchmarked, and included in reference designs at both the device and cluster levels, enabling customers to fully utilize our products.

A part of SK hynix that acts independently

Anton Shilov: You were previously a part of Intel. How is the integration going? Are you now fully integrated part of SK hynix, or do you operate independently?

Avi Shetty: Let me provide some background. While Solidigm was established in December 2021, our history goes back decades. Many of us came from Intel's Non-Volatile Memory Solutions Group (NSG), which developed Intel’s NAND SSDs for both client and data center markets.

In 2021, SK hynix acquired Intel’s NAND and SSD business and established Solidigm. Since December 2021, we have operated as a wholly owned U.S. subsidiary of SK hynix, headquartered in Rancho Cordova, California.

Anton Shilov: So, you are part of SK hynix, but still maintain a degree of independence?

Avi Shetty: Absolutely. We operate as an independent subsidiary of SK hynix. Our strategy is focused entirely on enterprise SSDs. Every bit of [floating gate] NAND [at our fab in Dalian, China] we produce goes into enterprise storage solutions.

This is one of the ways we differentiate ourselves from competitors such as Samsung and Micron, which also serve mobile and client markets. We made a deliberate decision to focus exclusively on enterprise storage and AI.

We are also fully vertically integrated. We manufacture our own NAND, develop our own controllers, write our own firmware, and design our own SSDs. While we work with manufacturing partners to build products, we control the entire technology stack.

I also believe we are the only company with access to two different NAND architectures. Through SK hynix we have access to charge trap flash (CTF) technology, and we continue to develop floating gate NAND technology for our high-density QLC SSD products.

Anton Shilov: What is Solidigm's current share of the enterprise SSD market?

Avi Shetty: Approximately 24%. That is enterprise SSDs only. We do not participate in any other NAND markets. As of the first quarter of 2025, plus or minus a few percentage points, our measured enterprise SSD market share is approximately 24%. We evaluate market-share data quarterly and semiannually, and that is the latest figure we’ve publicly discussed.

Anton Shilov: How much of your business today is concentrated in high-capacity SSDs versus higher-performance products?

Avi Shetty: High-density SSDs now represent a significant portion of our business. Because Solidigm is privately held, we do not publicly disclose that breakdown. We report our financial metrics through our parent company, SK hynix.

What I can tell you is that both our 61TB-class and 122TB-class products became customer favorites almost immediately after launch. Demand for high-density storage has been extremely strong.

Anton Shilov: I assume you also work directly with hyperscalers?

Avi Shetty: We work with a broad range of customers globally. That includes U.S. cloud service providers, Chinese cloud service providers, OEMs around the world, NeoCloud providers, software ISVs, and channel partners. We maintain customer support, engineering, and sales organizations globally. Our business spans the Americas, EMEA, China, and the rest of Asia-Pacific.

Anton Shilov: Which customer segment represents the largest opportunity for growth right now? Traditional cloud providers or something else?

Avi Shetty: We intentionally maintain a diversified customer base.

What is interesting is how quickly new segments emerge. For example, the NeoCloud market has existed for some time, but AI-focused infrastructure providers such as CoreWeave, Lambda, Crusoe, and Nebius have become much more important over the last two years.

Before the AI boom, these companies represented only a small portion of demand. Today, they are becoming a meaningful part of the market.

As AI infrastructure continues to expand, Solidigm is adapting both its customer strategy and product portfolio to support these emerging deployments while continuing to serve our traditional customers.

Floating gate NAND in 2026

CTF NAND used by major memory makers has approached 276 - 286 active layers, whereas Solidigm's floating gate flash is still at 192 layers, meaning that the company is somewhat behind some of its rivals in terms of active layers as of mid-2026. It is set to catch up with its next generation that will have over 200 layers, but only in the second half of this year. However, floating gate NAND memory still has a number of advantages over CTF, particularly for applications that Solidigm targets.

Floating gate uses a conductive polysilicon island to store charge, which provides excellent cell isolation — charge stays well-contained and is less likely to spread to or interfere with neighboring cells — and this is particularly important for 3D QLC NAND with very high layer counts. In addition, Solidigm claims that floating gate gives a strong voltage threshold window and better cell isolation, which enables the company to keep scaling QLC more while maintaining good reliability.

Anton Shilov: Are you still producing floating gate NAND, and do you intend to continue?

Avi Shetty: Absolutely. We introduced our first QLC foating gate NAND product in 2018, and today we are on our fourth generation of QLC NAND.

Our flagship high-capacity product currently ships with 192-layer floating gate NAND technology and powers our 122TB SSD.

Anton Shilov: Haven't you also announced a larger drive?

Avi Shetty: We have announced a higher-capacity product and expect it to become available later this year.

Anton Shilov: The 256TB-class drive?

Avi Shetty: Correct. Approximately 245TB usable capacity.

Anton Shilov: So you are going to have a roughly 245TB SSD available this year?

Avi Shetty: Correct.

Anton Shilov: What advantages does Floating-Gate NAND provide?

Avi Shetty: Floating gate NAND gives us scalability. We have consistently been first in the industry to push storage density in standard form factors. We were the first to introduce a 30TB SSD, then a 60TB SSD, and later a 122TB SSD.

We have been shipping the 122TB drive for nearly five quarters. We launched it in the fourth quarter of 2024, and it has since become our flagship product. It is probably our most popular product of 2025.

The reason customers like the 122TB drive is efficiency. When you look at AI data centers, customers want low power consumption, scalability, and performance. While this particular product is a PCIe Gen4 solution, our roadmap continues to increase both density and bandwidth. You will see future products based on PCIe Gen5 and PCIe Gen6.

The real attraction of the 122TB SSD is scale. In a 1U server, you can install 24 of these drives and get nearly 3PB of storage in a single rack unit.

If you look at the AI data pipeline — from training to archiving — the first and last stages require massive datasets. That is where these high-capacity SSDs are being deployed today.

Now we are also seeing growing demand from inference deployments. Inference can run in core data centers or in edge and back-office environments. Those deployments require storage that can efficiently feed GPUs and support workloads such as context storage and KV cache management. High-density SSDs help provide the capacity required for those applications.

Next-generation SSDs: PCIe Gen6 drives with liquid cooling

Anton Shilov: You mentioned PCIe Gen5 and Gen6 [next-generation drives]. I assume you are referring both to next PCIe generations and future NAND generations?

Avi Shetty: Both.

We maintain separate technology and product roadmaps. Earlier, I mentioned that our current QLC NAND is our 4^th Generation technology based on 192 layers. We will continue investing in future NAND generations as well.

On the product side, we are talking about PCIe generations. We currently ship both PCIe Gen4 and PCIe Gen5 SSDs. All of our TLC products are PCIe Gen5 today, while our QLC lineup currently remains PCIe Gen4.

Future QLC products will move to PCIe Gen5, and eventually, we will introduce PCIe Gen6 SSDs as platform vendors such as AMD, Intel, and Nvidia adopt PCIe Gen6 in their systems.

Anton Shilov: You mentioned PCIe Gen6 SSDs. You have not shipped one yet, correct?

Avi Shetty: Correct. PCIe Gen6 products are part of our future roadmap.

Anton Shilov: How close are they?

Avi Shetty: We are not making product announcements at Computex, but you will hear more from us soon.

Anton Shilov: At the moment there is really only one platform that can take advantage of them anyway. Well, two, if you consider Nvidia Vera.

Avi Shetty: That is part of the equation. When we evaluate our roadmap, we consider demand, platform readiness, and overall value to customers.

For example, we have what we call a refresh philosophy. We may introduce a PCIe Gen4 refresh or a PCIe Gen5 refresh that lowers cost or improves efficiency rather than immediately moving to a new PCIe generation.

The question is whether customers gain more value from Gen6 today or from a more mature, lower-cost Gen5 product. Those are the kinds of decisions our planning teams evaluate.

What I can say is that Solidigm maintains a full roadmap covering PCIe Gen4, Gen5, and future Gen6 SSDs across all major form factors, including U.2, E1.S, E3.S, and other EDSFF variants. Our portfolio spans capacities from 2TB all the way to 122TB.

Anton Shilov: Launching an all-new product early still gives you time to validate products with platform vendors.

Avi Shetty: Absolutely. We already work closely with platform providers to validate prototypes long before products are launched. Our engineering teams participate in interoperability events and PCI-SIG workshops to ensure products are ready when platforms become available.

Anton Shilov: That is actually interesting because PCIe Gen6 interoperability workshops have been delayed multiple times. Back in 2024, people expected the ecosystem to move much faster and interoperability workshops to start in 2024, with the list of compatible products emerging in 2025.

Avi Shetty: That is true. A lot depends on platform readiness and ecosystem scaling. PCIe Gen6 by itself is not enough. This is my personal opinion, but to fully benefit from Gen6 storage performance, the industry must also address cooling. That is one reason we invested heavily in liquid-cooled storage.

Last year, we introduced what we believe was the world's first liquid-cooled storage solution for Nvidia environments. It used E1.S PCIe Gen5 SSDs with direct liquid cooling. Historically, liquid cooling was focused on CPUs and GPUs. We extended it to storage by allowing coolant to flow through a cold plate attached to the SSD. The cold plate removes heat directly from the drive. To fully exploit PCIe Gen6 performance, the ecosystem must develop those kinds of technologies as well.

Anton Shilov: So you believe PCIe Gen6 SSDs will require liquid cooling?

Avi Shetty: At least in high-performance AI environments, particularly Nvidia-based deployments, we believe liquid cooling will be necessary.

Next-generation SSDs: PLC NAND

Anton Shilov: Will future NAND generations include both TLC and QLC? And what about PLC?

Avi Shetty: Never say never. We demonstrated PLC technology using floating gate NAND at the Flash Memory Summit several years ago. However, this business requires factory optimization and maintaining a manageable number of SKUs to maximize utilization and profitability.

That said, there absolutely will be opportunities for PLC. We have not announced any specific products or timelines, but there is active PLC development underway inside Solidigm.

Anton Shilov: That is interesting. However, PLC by itself only increases capacity by about 20% compared to QLC and at the same time requires significantly more sophisticated controllers and error correction.

Avi Shetty: That is true. However, those same concerns existed during every previous transition: from SLC to MLC, MLC to TLC, and TLC to QLC.

We were the first company to commercialize QLC NAND. Initially, many competitors questioned its value. Today, the industry increasingly recognizes the total-cost-of-ownership advantages that QLC provides, and multiple vendors now offer QLC products. I think the same process will occur with PLC.

It is also important to consider the broader market. Roughly 80% of storage capacity worldwide is still deployed on hard drives. PLC does not necessarily need to replace QLC on a one-to-one basis. Instead, it can create new opportunities where the advantages of solid-state storage — lower power consumption, higher density, smaller physical footprint, and lower total cost of ownership — become compelling.

You will likely see future solution development involving software partners that help address some of the limitations you are describing.

Anton Shilov: Do you expect retention characteristics to become a major challenge with PLC NAND?

Avi Shetty: Of course. PLC is a new technology, and retention characteristics will differ from what we see with QLC today.

The same is true across all NAND types. SLC, MLC, TLC, QLC, and eventually PLC all have different retention characteristics based on the underlying technology. The existence of those challenges does not mean we stop exploring future solutions. We will continue investing in that area.

Advanced packaging for NAND

Anton Shilov: As I mentioned, PLC only increases capacity by about 20%. Advanced packaging may ultimately have a much larger impact on SSD capacity. Could you discuss where packaging technology stands today and where it is headed?

Avi Shetty: Absolutely. Let me use our current products as an example. The 122TB SSD represents a significant packaging achievement. It is a U.2 drive with 48 NAND packages. Each package contains a 22-die stack. Each die is a 1.33Tb QLC device. Those 22-die stacks are what enable us to reach 122TB in a standard form factor.

Packaging technology remains one of our core investments. We continue developing technologies that allow us to place more dies into each package and deliver higher capacities to customers.

Anton Shilov: What about increasing the number of dies per package?

Avi Shetty: That is one of the primary ways to increase density. You can either increase die capacity or increase the number of dies per package. We intend to pursue both approaches.

Anton Shilov: How many dies per package do you think remain practical?

Avi Shetty: Today we are at 22. Future products will go beyond that, although I cannot discuss specific numbers.

Anton Shilov: What did previous generations use?

Avi Shetty: Depending on capacity requirements, previous products used 4-, 8-, or 16-die stacks. Of course, we are talking about a single NAND package in each case.

Storage-Class Memory, Optane, and Nvidia's Storage Next

Anton Shilov: What about storage-class memory?

Avi Shetty: Like Optane?

Anton Shilov: Not necessarily Optane itself, but something similar — something faster than NAND flash, yet capable of offering significantly higher density than DRAM at a lower cost.

Avi Shetty: Understood. Let me frame it from the perspective of the problem we are trying to solve. If you are asking whether Solidigm is developing a storage-class memory technology similar to Optane, then the answer today is no.

What we are focused on is addressing the requirements emerging from Nvidia's Storage Next initiative. The fundamental challenge is bandwidth. HBM is extremely fast, but it is also expensive and difficult to scale economically. As AI systems continue to grow, the industry needs additional memory and storage tiers that provide greater capacity at lower cost. That creates demand for NAND-based solutions that remain non-volatile while delivering improved latency and bandwidth characteristics.

We have not made any public announcements regarding storage-class memory technologies, but we continuously evaluate future technologies and architectural approaches.

Anton Shilov: So you are exploring concepts that could potentially bridge the gap between traditional NAND and memory?

Avi Shetty: We are evaluating a wide range of technologies that could help us continue delivering leadership products to our customers. When and if we have something to announce, we will do so publicly. At this point, however, we have nothing to disclose.

Anton Shilov: So storage-class memory is not currently a product category that Solidigm is actively pursuing?

Avi Shetty: If you are specifically referring to something similar to Optane, then no.

Optane was based on a fundamentally different technology. It was not NAND. It relied on a phase-change-memory-derived architecture and represented a completely different storage medium. We are not pursuing that type of technology today. What we are investing in is future NAND technology.

Anton Shilov: You think that future NAND technologies could eventually move closer to that space?

Avi Shetty: Exactly. Future NAND innovations could help narrow the gap between HBM, DRAM, and the next storage tier. That’s certainly one of the directions the industry is evaluating as AI systems continue to demand larger memory pools and greater bandwidth.

For heavy AI users, the economics of the current boom are starting to bite. Over the past year, major labs have nudged prices upward while tightening the screws on usage — whether through stricter rate limits, smaller context windows on lower tiers, or the gradual reshuffling of features behind more expensive plans. Even where per-token costs have fallen in headline terms, the reality for users is more complicated: higher volumes, more complex workflows, and new tooling expectations mean monthly bills are creeping up, not down.

At the same time, open-weight models have improved rapidly, consumer hardware has become more capable, and tools like LM Studio, Ollama, and llama.cpp have made local deployment far more accessible than it was even a year ago. The result is a renaissance in running models on your own machines.

I’m one of the people who has taken the leap myself. In mid-March, I bought a GMKtech mini PC with an AMD Ryzen AI Max+ 395 chip and 96GB of RAM. The purchase — at the time something like £1,500 ($2,000) — was a calculated decision. The kinds of volume I wanted AI models to run through would have blown through my current subscriptions to AI models (I have a ChatGPT Plus and GLM Coding Lite plan, which combined cost me around $23 a month), and forced me onto the higher-cost monthly plans, or API-based inference.

Going local

The decision I had to make was a simple one: did I want to spend that money on a subscription that would cost me several thousand dollars over the course of a year, and end up having to pay a recurring cost for years to come to an AI lab that would likely hike prices? Or did I want to pay a one-off charge for my own hardware and a smaller ongoing cost for electricity?

I chose the latter.

When the mini PC arrived, setting it up was relatively easy — though, fully disclosure, only possible with the help of the full-fat AI models I pay for from the big labs.

The system I set up on my hardware was designed to try and help me keep track of the constantly changing news in the areas I cover for sites like Tom’s Hardware Premium and others. It takes RSS feeds and ingests the contents of stories in key beats that I cover, then grades them against a digital ‘brain’ made of how I think about the world and what I report on, generated by analyzing nearly 2,000 of my past stories over the previous four years.

When it finds candidates that are potentially interesting, those stories are ‘assigned’ to AI beat reporters, who then read around the subject on the web and produce pitches, similar to those that I send to my editors here and elsewhere. Those AI reporters then send their pitches to AI editors, who engage in a conversation with the reporters to fine-tune the idea’s framing, before presenting me with a couple of paragraphs of a broad idea that is meant to be tailored to my tastes via Telegram.

The outputs are far from perfect — I’d equate them to a newly-graduated student that I teach in terms of their taste and depth — but they’re a good starting point for me to learn about what’s important on a given day, and a provocation for how I might think about framing those events. For the kind of things I’m using AI for, even the bleeding-edge frontier models aren’t much better than the local LLM options, though I appreciate that there’s a bigger gap when thinking about coding.

Setup

The whole process uses LM Studio and runs on a mix of quantized models, generally of Qwen3.5 and 3.6. Because I’m running multiple editor and reporter processes in parallel, the parameter count on each model may seem undersized for the 96GB of RAM that my AMD GPU can access (after some BIOS tweaks): I’m using a mix of Qwen’s straightforward 3.5-9B model, as well as Jackrong’s Qwen-3.5-9B-GLM-5.1-Distilled and Qwopus-3.5-9B models. In part, that’s because thousands of calls on the models take place every day, and in order to keep on top of the backlog of stories to look through and ‘discuss,’ throughput needs to be high.

Since starting the locally-hosted project in mid-March, my local LLMs have burned through anywhere between 20 million and 50 million tokens a day alone. (Alongside troubleshooting with paid-for and hosted models, as well as parallel projects I run on my GLM Coding plan subscription, I’m using between 50-100 million tokens on an average day.)

For this kind of reading, thinking, analyzing, and re-presenting, local models work brilliantly. They have high throughput but are working in the background, meaning that the slower time to first token that many local LLM users complain about in comparison to big lab-hosted alternatives isn’t an issue for me. The model runs 24 hours a day, and if it takes two seconds or two minutes to process the prompts (between 7,000 and 18,000 tokens, depending on whether it’s a reporter or editor and how far through the discussion process it is), it doesn’t bother me. Tokens per second won’t impress those talking a big game about local LLMs on social media: the models handle the prompts at around 300 tok/s, while the output is a much slower 5-10 tok/s. Yet it works for me.

Split throughput

But for now, I’m still keeping my big lab subscriptions — though I’m using them differently. My GLM Coding plan, bought around Christmastime and which lasts for a year, is used alongside Codex through my OpenAI subscription to troubleshoot and tinker with the projects when issues arise. My coding knowledge stopped at some QuickBASIC and Delphi in my teenage years, so having the ability to call on them (and an OpenCode Go subscription I occasionally dip into) to fix problems is invaluable.

However, the proportion of my AI use has shifted significantly. Two-thirds or more of my total token use is now locally-hosted LLMs I run myself. And as local models continue to develop their abilities and the gap between them and the state of the art from big labs closes, I can envisage that it will increase. For instance, I recently vibe-coded a web interface for LM Studio that allows me to use it as a regular chatbot just this last week. And in just two months, the amount I’ve saved if I had run that project every day through API calls on GPT-5.4-mini, arguably a comparable model, is three-quarters of the cost of that first mini PC — around $1,500.

In hindsight, I wish I’d bought the 128GB version of my mini PC, which is why I decided around two weeks ago, before another memory-based price hike, to buy the bigger version. The reason was a simple one: the volume of queries I was putting through my 96GB box was starting to hit the limits, and I wanted to expand the project. I also wanted to test out locally hosted coding harnesses like Claude Code or Hermes using a local model.

The experience, trials, and tribulations from my first mini PC setup helped enormously with setting up the second PC. Token count has increased from 20-50 million tokens a day to more like 50-80 million tokens a day. I offloaded part of that massive ingest and analysis project onto the new hardware and put it onto more powerful 27B and 36B parameter models (through the Final-Bench-Darwin-36B-Opus model), freeing up space on my first mini PC and allowing me to test the idea of a locally-hosted Claude Code-style project with the spare space on my second mini PC.

That has been less successful — at least so far. Underpinning the coding harness with GLM-4.7-Flash works, but feels like too big a step back in model generations to be a useful tradeoff. Larger Qwen models have so far got stuck in their own thinking (or burned through a lot of the context window they’re assigned), but I’m considering swapping Claude Code out for a lighter-weight, less context-heavy harness and giving it a proper run.

Frontier models are getting more expensive

The bet I’ve made is a simple one: subscription and API prices from frontier labs — with the odd outlier like DeepSeek excepted — are only going to go in one direction as the companies behind them realize they need to make a financial return for investors. Even if prices don’t go into the stratosphere, labs might make tradeoffs to cut down on usage — as we’ve already seen GitHub doing. And while the race to build capacity to meet demand for those major AI labs will continue to push up prices for hardware in the short term, I still think it’s a better bet to have control over your own models and how much you pay for them than to leave it in the hands of big companies.

So I’ll keep tinkering with my local stack, which has already gone from one mini PC to two interlinked ones — and already have my eyes on a PC with an Nvidia GPU to give me the token speed that’s currently missing. But for now, I think it’s worth keeping what I have for a while and seeing how I can eke out additional benefits before making the leap financially in expanding my whole system.

This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity. In the space of 12 months, Intel has gone from canceling fabs to running short of them. In July last year, the company scrapped a planned €30 billion megafab in Magdeburg, Germany, and a $4.6 billion assembly and test plant near Wroclaw, Poland, citing a lack of committed demand. Then, in April this year, it paid Apollo $14.2 billion to repurchase the 49% stake in its Ireland fab that it had sold for $11.2 billion in 2024. Three weeks later, CFO David Zinsner described "unprecedented demand for silicon" alongside Q1 results that sent the stock up 24% in a single session, its best day since October 1987.

The next round of capacity development now hinges on two key deadlines: CEO Lip-Bu Tan told investors in January that prospective 14A customers will begin to make firm supplier decisions "starting in the second half of this year and extending into the first half of 2027." Separately, the enhanced 35% advanced manufacturing investment credit signed into law last July applies only to fab construction that begins before December 31st, 2026; projects that break ground in 2027 get nothing.

Both clocks run out within months of each other, and both bear on the same construction projects.

Arizona

Fab 52 at the Ocotillo campus in Chandler is the production foundation for everything on Intel's 2026 to 2028 product roadmap. The facility became fully operational in October last year as the first high-volume home of Intel 18A, building Panther Lake compute tiles and, later this year, Clearwater Forest. Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is "capable of more than 10,000 18A wafer starts per week," which works out to roughly 40,000 wafer starts per month at full ramp and makes it larger than TSMC's Fab 21 phase 1 and phase 2 combined.

That’s named capacity, however, not current output; Intel has indicated that 18A yields will reach industry-standard levels in early 2027, and until then, the company is capping CPU output on the node, leaving part of Fab 52's capacity idle. Tan said in May that 18A yields are improving by 7% to 8% per month.

Fab 62, the second from Intel's $20 billion 2021 Arizona expansion, is expected to be ready around 2028. Intel hasn’t officially assigned it a node, leaving it open as a stopgap for 14A if Ohio isn't ready, or as additional 18A capacity if external demand comes sooner. Brookfield Infrastructure put up to $15 billion into the two Chandler fabs in 2022 for a 49% share of the joint venture, and unlike the Apollo arrangement, Intel has made no move to buy that stake back, so every wafer out of Fab 52 and Fab 62 will have revenue share commitments attached to it.

Oregon

As the home of 14A, D1X complex at Gordon Moore Park in Hillsboro — a low-volume fab and development site — is currently the only place Intel develops leading-edge process technology, with Chandrasekaran telling CNBC the node will be developed first in Oregon, with a goal of risk production in 2028 and high-volume manufacturing in 2029.

Hillsboro houses Intel's High-NA EUV machines, including the first ASML Twinscan EXE:5200B system delivered anywhere, and 14A is the first Intel node designed around it. Oregon also carried early 18A production while Arizona ramped up. Intel began permitting work in February 2024 for a multibillion-dollar expansion of the campus following the approval of an air quality permit, though no construction start has been announced to date.

Ohio One

Ohio is Intel’s most problematic fab project on paper. It broke ground in New Albany way back in 2022 on a $28 billion first phase, originally targeting 2025 production. In February 2025, however, Chandrasekaran reset its schedule, targeting 2030 for the completion of Mod 1 with operations between 2030 and 2031, and Mod 2 in 2031 with operations in 2032. In a memo setting out this new schedule, Chandrasekaran said Intel preserves “the flexibility to accelerate work and the start of operations if customer demand warrants.”

Spanning nearly 1,000 acres, the site is designated for 14A and future nodes, and has room for up to eight fabs. Intel has spent roughly $5 billion there to date as of March 2025, including $1.4 billion in total for that year. Bechtel, the lead contractor, posted a wave of new construction job listings in January, the same month Tan declared Intel is “going big time into 14A.”

Still, customers (or a lack thereof) remain the gating factor for 14A production. Intel told investors in January that it’s got two prospective customers evaluating 14A test chips, and its SEC filings still warn that without a significant external customer, it “may pause or discontinue” 14A, successor nodes, and various manufacturing expansion projects.

Elon Musk said in April that his planned TeraFab project — the first named taker for the node — will use 14A process technology to make AI chips, though test production is expected to be years out. This also isn’t such a big win in terms of the volume commitment Intel’s filings say it needs for 14A to be viable. At the time of writing, 14A’s next and arguably most critical milestone is the 14A v0.9 PDK, which Tan says will reach external customers in October.

"The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Ireland and canceled projects

Launched in 2023, Fab 34 in Leixlip is Intel's only EUV-class site in Europe, producing Intel 4 and Intel 3 silicon for Core Ultra and Xeon 6 parts. In 2024, Apollo-managed funds paid $11.2 billion for a 49% interest in the joint venture entitled to the fab's output, a deal that gave Intel a much-needed cash injection at the time.

In April this year, Intel bought that stake back for $14.2 billion — at a premium of roughly 27% — funded from cash and about $6.5 billion in new debt issuance. Apollo walked away with around $3 billion in return for two years of exposure, and Intel paid a nine-figure annual cost of capital to reclaim needed wafer revenue.

“Flexibility and alignment are core to how we approach relationships as a long-term, solutions-oriented capital partner, and we are pleased to facilitate this transaction in support of Intel's evolving strategic and operational priorities,” said Apollo Partner Jamshid Ehsani at the time.

Magdeburg, once pitched as a €30 billion home for 14A-era production with roughly €10 billion in German subsidies attached, was postponed to 2029-2030 in November 2024. This prompted the German government to reallocate those subsidies to the federal budget and, following a $3.2 billion operating loss with Q2 2025 financial results, Intel killed the project, the subsidies dying with it.

Wroclaw's $4.6 billion assembly and test plant was canceled the same day, and Costa Rica's assembly and test operations were consolidated into Vietnam and Malaysia. Fab 38 in Kiryat Gat, Israel, the planned $25 billion expansion announced in 2023 with $3.5 billion in Israeli government backing, has been paused for the last two years, with no restart announced. Every leading-edge wafer Intel produces for the foreseeable future will come therefore come from three U.S. states and one campus in Ireland.

Packaging and test

Fab 9 in Rio Rancho, New Mexico, a $3.5 billion conversion that opened in January 2024, is the only high-volume Foveros 3D stacking site in the United States. Foveros is the packaging behind every tiled Intel design since Meteor Lake, bonding compute, graphics, and I/O dies vertically rather than laying them side by side, and it is integral to the stacked Clearwater Forest parts now ramping on 18A.

Intel runs it alongside the neighboring Fab 11x as a single co-located operation, which EVP Keyvan Esfarjani called “the only U.S. factory producing the world's most advanced packaging solutions at scale.” The buildout created hundreds of Intel jobs and more than 3,000 construction roles, and the campus later drew a further $500 million in CHIPS funding for modernization.

The $7 billion Penang complex in Malaysia, placed on indefinite hold in early 2025, has been revived: the buildout is now 99% complete, and first-phase assembly and test operations are due to begin later this year, according to Malaysian Prime Minister Anwar Ibrahim, following an earlier briefing with Tan. Intel has also outsourced EMIB production to Amkor's Songdo facility in South Korea, and its next-generation EMIB-T packaging rolls out across production fabs this year.

With Magdeburg and the Penang delay having stripped packaging options elsewhere, Rio Rancho is now the load-bearing U.S. node for the back-end work that makes Intel's entire chip roadmap possible.

Two deadlines and three things to watch

Intel’s 14A commitment window and the cutoff for tax credits both converge in the second half of this year. Tan’s stated expectation is that customers make firm supplier decisions between the second half of 2026 and the first half of 2027, with results from the upcoming October PDK potentially being the trigger for those decisions.

On June 8th, Cadence announced a multi-year agreement with Intel Foundry to co-optimize designs for 14A and deliver production-ready process design kits. This is exactly the EDA groundwork that needs to be in place before any fabless customer can commit volume, and a committed volume customer will be what unlocks acceleration at Ohio and gives Fab 62 a job. The alternative, per Intel, is to cancel 14A altogether.

Unlike the customer deadline set by Intel, the tax deadline can’t slip. The so-called One Big Beautiful Bill Act raised the Section 48D advanced manufacturing investment credit from 25% to 35% in July last year, but the law's termination clause is unchanged: the credit doesn't apply to “property the construction of which begins after December 31, 2026.”

Treasury rules let a physical-work test or a 5% spend safe harbor establish a construction start, so Intel has roughly six months to break ground on any new shells, in Ohio, Arizona, or Oregon, that it wants the U.S. government to part-fund. The government, of course, has been a shareholder since August, when $5.7 billion in unpaid CHIPS grants from Intel's $7.86 billion award and $3.2 billion in Secure Enclave funds were converted into a 9.9% equity stake.

Ultimately, we’re going to be watching for three things before January: a named 14A customer with a volume commitment; a construction-start announcement timed to beat the credit deadline; and 18A yield milestones that free up the Arizona capacity Intel’s currently sitting on.

We learned a lot about Intel’s upcoming plans for desktop CPUs at Computex 2026. In classic Intel fashion, we’ve already heard a lot about the company’s next-gen CPUs, codenamed Nova Lake, even while the recent Arrow Lake Refresh CPUs are still warm from the oven. But on the ground in Taipei, we heard not only more about Nova Lake and the Z990 platform it’s arriving on, but also how Intel intends to handle the rollout and how it will fill the gaps in its lineup with “Raptor Lake Next,” which is supposedly slated to launch next year.

Trade shows are the best opportunity to learn details about unreleased products before they show up in a press deck, and simultaneously the worst venue to do so. With jet-lagged representatives and reporters, thousands of people whizzing past, and the threat of Jensen Huang showing up to sign components and shut down a floor on a moment’s notice, it’s easy for things to get lost in the shuffle. So, we’re going to work through everything we learned about Intel’s upcoming plans in stages, starting with details that are confirmed, and working toward more speculative murmurs.

Intel has a fairly aggressive consumer roadmap, which the company itself would tell you – and the company told us as much at Computex, as a matter of fact. Both Nish Neelalojanan, senior director of client product management, and the recently joined Alex Katouzian, executive VP and GM of client, played up Intel’s roadmap to Tom’s Hardware, and for good reason.

Chronologically, Intel’s plans look something like this: We’ll see the first Nova Lake SKUs roll out at CES 2027. A few months later, we’ll see a refresh on the LGA 1700 socket with “Raptor Lake Next” CPUs, and come Computex next year, Intel will launch a 52-core flagship Nova Lake SKU. None of that is confirmed by Intel, and we have varying degrees of confidence in each step of the roadmap, so take it as speculation for now. We’ll dig more into the details we have and what’s simply rumored below.

What about AMD?

Before Intel, we should at least look at why we’re not talking about AMD’s next-gen desktop plans. Basically, we don’t have a ton of information on Zen 6 CPUs yet, and even less information about Olympic Ridge, the desktop consumer lineup of Zen 6 chips. Computex didn’t change that fact.

At Computex, AMD revealed the Ryzen 7 7700X3D, relaunched the Ryzen 7 5800X3D, and brought the RX 9070 GRE to the rest of the world. Unlike previous years, AMD didn’t hold a keynote, where we might’ve seen a more concrete tease of Olympic Ridge; AMD has already teased Zen 6 broadly several times. Bigger Zen 6 news is likely at the company’s Advancing AI event next month.

Although AMD hasn’t said when Olympic Ridge will launch, we originally expected it in late 2026. Now, 2027 is very likely. AMD has shifted the Zen 6 conversation toward its EPYC Venice chips, and confirmed production ramp on Venice in May. Although AMD traditionally leads with a consumer launch at the turn of a new microarchitecture, it’s unlikely that Olympic Ridge will launch before Venice. Demand for CPUs is spiking in the data center for agentic AI workloads, after all, and AMD is adjusting accordingly.

Olympic Ridge probably isn’t top of mind right now, from both AMD itself and its partners. AMD laid the groundwork for a unified CPU architecture generations back, and Intel’s approach has been a bit more disparate across client and data center (although that’s been changing with releases like Xeon 6 and Xeon 6+). We don’t know when Olympic Ridge news will arrive, but it almost certainly follows far greater detail about Zen 6 in the context of Venice.

What’s confirmed

Let’s start with the concrete details about Intel’s future CPU plans. These are things we have direct evidence for, be it photos, our own hands-on time, or sources we’re extremely confident in. At least two Z990 motherboards were at Computex, a third is rumored, and we saw (and held) what looked to be a near-production model in a closed-door meeting. And from that, we can already tell a lot about Nova Lake.

First, the LGA 1954 socket, which has now been pictured (we were told not to take pictures, but someone else did the dirty work, it seems). It’s the same size as the LGA 1851 socket, measuring 45 mm x 37.5 mm, and it retains compatibility with existing coolers, which we were able to confirm at Computex. It features more pins, as the name reveals, and uses the 2L-ILM, or two-lever Independent Loading Mechanism. The picture of the socket circulating matches what we saw at Computex.

The motherboard we saw featured dual 8-pin EPS connectors, along with an 8-pin PCIe connector near the bottom of the board, which is said to provide auxiliary power to the CPU. We’ve seen a leaked photo of the Z990 PCH now, which is said to draw more power due to broader PCIe 5.0 support. The Z990 board we saw, at least, had three PCIe 5.0 M.2 slots, along with three PCIe 5.0 expansion slots. Short of perhaps specialized designs with extra M.2 slots, we expect Z990 to support PCIe 5.0 across the board.

As for the chips themselves, all that is confirmed from Z990 motherboards is that Nova Lake can scale up to a high-end power design. We’ll speculate more on specific numbers later, but we’ve seen auxiliary power beyond two 8-pin EPS connectors on two Z990 motherboards now, and the motherboard we held had an extremely high-end VRM design; we can’t say more than that at this point.

An important caveat here is that we’re dealing with high-end motherboards and discussing how high the platform can scale, not how it will scale. Plenty of ink has been spilled about Nova Lake’s supposedly high power draw, but we really don’t have details about the chips themselves, rather just the tippy-top of the platform that will support them.

Outside of Z990 boards, Intel has confirmed that Nova Lake is “coming at the end of 2026.” That’s what CEO Lip-Bu Tan said at the company’s full-year 2025 earnings call back in January. What we were told by multiple vendors at Computex is Q1 2027, with a portion of those vendors specifically pointing to CES 2027. Similarly, with Z990 motherboards, some vendors said Q1 2027 while others said Q4 2026 (one even hinted at Q3). Believe it or not, these timelines actually all match up.

What’s lost in translation here is when the sale is happening. Before Nova Lake launches publicly, Intel and motherboard vendors will need to sell products into the channel, which, a few months later, will be available for sale at retailers for you to buy. What we’re likely looking at is sales into the channel in Q4, a public launch of Nova Lake at CES 2027, and retail sales in Q1. When Tan says Nova Lake is coming at the end of 2026 to a group of investors, he’s likely referring to selling into the channel, not the final retail sale.

What’s likely

Now, we’re getting into a bit more speculation. These are some of the details we heard about at Computex, or confirmations of previous rumors that we don’t have any concrete evidence for. Given the conversations we had at Computex, and a healthy dose of critical thinking, these are the details that are likely but not confirmed. There’s always a chance we’re just blind men touching an elephant on some of these points.

First, Nova Lake. For nearly a year now, it’s been rumored that the highest-end Nova Lake SKU will scale up to 52 cores. That’s the number we heard at Computex, as well, but not as a typical flagship. Rather, we heard that Intel plans to lead Nova Lake with a 28-core flagship, which will launch at CES 2027, and introduce a high-end 52-core model later in the year. The timeframe we heard was Computex 2027, but if anything is subject to change, it’s a release date that’s a year away. For now, let’s call it later in 2027.

The 52-core SKU will apparently come with 16 Coyote Cove P-cores, 32 Arctic Wolf E-cores, and a cluster of 4 LP-E cores; we didn’t hear that at Computex, nor anything to the contrary, but that’s what has been previously rumored. That model will reportedly come with two compute tiles, so the 28-core model with a single compute tile will likely look like an 8 + 16 + 4 split. That’s pure extrapolation at this point, however.

As for the 52-core model, we were told it comes with a PL1 of 175W and a PL4 of up to 700W. The PL1 number is what’s important here. Although that is a sizable increase over the 125W PL1 of both the 285K and 14900K, 52-core Nova Lake doesn’t sound like a direct replacement for those parts. Given the timing and extra power demands, it looks more like a spiritual successor to Intel Extreme Edition chips, targeting enthusiasts with deep pockets and the HEDT crowd.

Nova Lake is treaded ground at this point, however. Something new we learned about from Computex is “Raptor Lake Next.” After hearing the name, we asked Intel, which declined to comment on Raptor Lake Next at this time. Apparently, however, it will be the third refresh of Raptor Lake CPUs on the LGA 1700 socket, particularly targeting budget-conscious builders while Nova Lake satiates the enthusiast crowd.

There are some pieces of circumstantial evidence that point to a reintroduction of LGA 1700 CPUs. First, this has been previously rumored. In April, prolific leaker Jaykihn hinted at another Raptor Lake refresh coming in 2027. We’ve now heard that the range is called Raptor Lake Next from multiple sources, and it’s specifically coming in the first half of 2027, some months after the initial Nova Lake launch.

Additionally, multiple motherboard vendors told us that they’re ramping production of LGA 1700 motherboards, including DDR4 boards, though they didn’t say it was in relation to any new CPU releases. Intel itself has dropped a few hints, as well. Earlier in the year, Intel’s Robert Hallock said that Raptor Lake will be “abundantly available” in the market, and at Computex, Intel’s Nish Neelalojanan told Tom’s Hardware that Intel “will continue to make sure that there are products which can take care of older memory technologies.”

It would certainly make sense for Intel to refresh Raptor Lake a third time. Although data center demand is offsetting it, the decline in desktop sales from high memory prices hits Intel and AMD on the balance sheet as well. Just about everyone we spoke with at Computex talked about the state of memory prices, and Intel has a DDR4 platform that it’s still actively selling on the market. AMD, with a hard switch to DDR5 with Zen 4, has to reach back further to revitalize DDR4 options, but Intel already has a small ecosystem of DDR4 motherboards and CPUs available now, which it could easily bolster. We’ve heard that bolster is coming in the opening months of next year.

What that range looks like remains a mystery, however. It could be a proper refresh, or it could simply be an infusion of 14th-gen stock (and LGA 1700 motherboards) into the market along with new price points; both Raptor Lake generations have slowly crept up in price since the end of last year. The important thing here is that it seems Intel is targeting LGA 1700 for the lower end of the market, as Arrow Lake, with its underperformance and high price due to exclusively using DDR5, won’t provide the last-gen value bridge that previous generations have.

After Tom's Hardware originally broke the news about Raptor Lake Next, we followed up with Jaykihn, who provided a few specs.

*Naming unconfirmed by Intel, specifications rumored

The specs we've heard about are for the four SKUs above, which would comprise the main lineup of chips with integrated graphics enabled; apparently, Raptor Lake Next will include options with the iGPU disabled, as well as mobile chips. The final branding is unconfirmed, but we've heard that Intel intends to launch under the Core Ultra 200 name.

Out of the four SKUs, the 16-core Core 5 looks like Intel's breadwinner. Throughout 12th- to 14th-Gen, Intel topped out Core i5 models at 6 P-cores. You'd have to step up to a Core i7 for 8 P-cores. If these specs are correct, Intel is stepping down to an 8 P-core configuration a tier in branding, which will hopefully come with a cut to price.

What’s still up in the air

Some of the finer details of Nova Lake are still up in the air. That is, we don’t have any direct evidence for them, nor any corroboration from Computex. That’s not to say that the details here are false. Rather, we just need more information to say, for sure, that some of these details are a part of the Nova Lake lineup.

First and most obvious is bLLC, or big Last Level Cache. This is one of the earliest Nova Lake rumors that is still circulating, and for good reason. Intel hasn’t found an effective counter to AMD’s 3D V-Cache CPUs in more than four years. We’re closing in on half a decade where AMD has entirely owned the high-end of PC gaming, which has continually eaten away at Intel’s market share. bLCC is, apparently, Intel’s counter to 3D V-Cache, using its own Foveros 3D hybrid bonding to stack additional last-level cache.

Tom’s Hardware asked Intel CEO Lip-Bu Tan and a panel of executives at the company how it plans to address X3D CPUs, and Alex Katouzian, a 20-year Qualcomm veteran who recently joined Intel in a leadership role over the client group, said the following: “When I first came in and started reviewing road maps for the team, I was very pleasantly surprised. So, stay tuned, a very strong roadmap [is] coming, and we will be gunning for that section of the market as well. And so, please stay tuned.”

Context is important, but Katouzian is really only saying that Intel is gunning for high-end gamers with its roadmap, which, of course, it is. Otherwise, bLLC has entirely been a topic of the rumor mill. Intel has indirectly teased it with PR hits about its packaging capabilities, but that extends far beyond bLLC. Hybrid bonding, especially from a foundry perspective, has far greater legs in the data center.

Although Intel has the packaging and bonding capabilities, the scale of them for a mass-market product like Nova Lake is questionable. Intel would need to bond the SRAM to the logic tile with Forveros and package the chip with EMIB, creating the “EMIB 3.5D” combination that Intel has talked about previously. We first saw EMIB 3.5D on the Ponte Vecchio data center GPU, but most recently and relevantly on Clearwater Forest, Intel’s first foray into putting 18A in the data center. The capability is there, but if Intel can scale that up to a consumer range with more limited die space and higher per-core performance remains to be seen.

One advantage of Intel’s hybrid bonding and advanced packaging is that it can package dies from other foundries, not just those from Intel foundries. That brings us to the second finer point about Nova Lake, which is the node. Originally, the assumption was that Intel would use 18A for Nova Lake. We have 18A on mobile with Panther Lake, in the data center with Xeon 6+, but not on the desktop. Further, Intel has previously commented about reshoring its manufacturing for consumer chips after a brief stint with TSMC for logic tiles in both Lunar Lake and Arrow Lake.

Around this point last year, however, rumors started circulating that Intel is using TSMC’s N2 for Nova Lake. The source of the rumor is flimsy, however. Well-known reporter Charlie Demerjian of SemiAccurate reported in July 2025 that Intel taped out a major product. The report didn’t mention what product, what foundry, or even include “TSMC” anywhere on the page. Still, other outlets took the story, claiming that not only was Demerjian talking about Nova Lake, but also that he was talking about TSMC N2.

There are reasons Intel could use TSMC for the logic die. The company has reiterated that it’s shifting wafer capacity toward the data center, so if TSMC can fill additional capacity on the desktop, we could see TSMC on the main logic die. It’s also possible that TSMC is manufacturing other tiles on Nova Lake. Intel has consistently blended nodes in recent generations, so even if Intel were to confirm that it’s tapping TSMC for Nova Lake, that doesn’t necessarily mean the Taiwanese giant is manufacturing logic.

And, just as easily, Intel could absolutely be using TSMC for logic. That’s the point here; we really don’t know at this point, outside of vague reporting, getting swept up in the rumor mill, and taking on a life of its own. The Cinderella story for Intel would be Nova Lake on 18A, but given the struggles on 18A yields, it wouldn’t be surprising to see TSMC at the helm for Nova Lake once again.

Hurry up and wait

Intel needs a much more aggressive roadmap on the desktop than AMD, frankly, and that roadmap is starting to take shape. Although AMD and Intel compete on the finer points of performance, Team Red has almost exclusively taken market share away from Intel, quarter over quarter, for the past decade. There are only a handful of quarters in that time when AMD has lost market share, which it has always rebounded from in the quarter that follows.

Even if Intel still represents the majority of the desktop market — and it does based on the latest market research — the trend is abundantly clear. Add on top of that clear fumbles like Arrow Lake, and it’s obvious that AMD doesn’t need to move the needle much to continue swiping customers. Intel needs to make big moves to recover.

We should have more official details about those plans soon. Intel mostly sat Computex out on the consumer front, short of the Arc G3 range that, although exciting for gaming handhelds, is destined to be a niche product given the high prices of the devices those chips are going in.

For the past four years, Intel has held its Tech Tour event in the fall, taking the place of its previous Architecture Day, which took place in the late summer (most of those details have shifted to the Hot Chips conference in August). Intel has already told us that Hot Chips will have more details about Diamond Rapids, Intel’s next-gen P-core Xeons. That leaves Tech Tour for when we’ll likely get a full architectural deep dive on Nova Lake. Intel has yet to confirm Tech Tour 2026, but we have no reason to believe the company will sit out the rest of the year at this point. It also lines up with what we’re hearing about Nova Lake’s release — architectural details in the fall, a launch at CES 2027, and availability in Q1.

Regardless of when the exact dates fall, Computex made it clear that Intel is readying Nova Lake for a release soon. Multiple motherboard vendors brought Z990 motherboards to Computex and actively showed them to the press; I can’t imagine that was sanctioned by Intel.

As for Raptor Lake Next, Computex is the first quasi-confirmation we’ve heard of the range. That name apparently appears on Intel’s roadmap at some point in the first half of next year. With Nova Lake at the high-end and Raptor Lake Next in the midrange, Intel might have a one-two punch strategy to earn back some spots in the market, especially as AMD turns its Zen 6 focus toward the data center and prioritizes older architectures on desktop, given high DDR5 prices. Now, we just need to wait and see how those internal plans materialize as the rest of the year goes on.

When we referred to TSMC just several years ago, we called it 'the world's largest foundry,' implying that Intel was still the world's largest producer of advanced logic chips. However, having spent nearly $240 billion on capacity expansion over the last 10 years, TSMC now has nine sites with dozens of 300-mm fabs, many of which can process orders of magnitude more wafers using EUV-based process technologies than Intel*, which makes TSMC the world's largest maker of advanced logic chips.

Being the world's largest maker of advanced AI processors requires TSMC to stay ahead of its rivals, Intel and Samsung Foundry, both in terms of process technologies and, perhaps, even more importantly, in terms of production capacity.

Therefore, TSMC has kicked off the most aggressive manufacturing expansion in its history as the company races to meet explosive demand for AI processors, logic chips made on leading-edge nodes, and advanced packaging.

During TSMC's Tech Symposium 2026 manufacturing presentations, the company revealed that in 2025 – 2026, it effectively doubled its historical construction pace, building or converting nine fab phases annually, up from an average of four phases per year. The company is simultaneously building or ramping new fabs in Taiwan, the U.S., Japan, and Germany. In addition, it introduces new ways to improve the productivity of existing facilities.

N2 ramp: Six-figure amounts of wafers per-month by 2029

The central part of TSMC's expansion plan is its N2 process technology. At present, the company is ramping up production of chips using N2 at two sites: Fab 20 phase 1 and phase 2 in Hsinchu near TSMC's global R&D center, and Fab 22 phase 1 in Kaohsiung. Ramping a leading-edge node at three facilities simultaneously is highly uncommon for foundries. The company also plans to ramp up production at Fab 22 phase 2 shortly and Fab 22 phase 3 by the end of the year. Eventually, Fab 22 phase 4 will come online as well. As a result, TSMC aims to start mass production on its N2 process technology at five facilities in the first year, which is at an unprecedented scale.

As a result of such an aggressive ramp, TSMC expects its N2 wafer-out capacity to be 45% higher than that of N3B in the first year. Reports from 2023 – 2024 indicate that TSMC ramped its N3B production at two or three phases of Fab 18 in 2023 and reached a capacity of around 60,000 wafer starts per month by the end of that year. If the reports are accurate, then TSMC expects its N2 capacity to reach around 90,000 wafer starts per month (WSPM) by the end of the year. This exceeds the fully ramped capacity of Intel's 18A-capable Fab 52, which is believed to be at around 40,000 WSPM.

What is even more impressive is that TSMC intends to increase its N2/A16-capable capacity by 70% every year through 2028, which means hundreds of thousands of WSPM in 2029.

In addition to reaching vast capacity, ramping up five fab phases simultaneously enables TSMC to mitigate risks. If one fab phase experiences a contamination issue, tool failure, or yield issues, the entire N2 supply chain will not collapse. The same applies to ramping up production at two sites located in different parts of the country: an earthquake or utility failure can interrupt production or even cause yield loss at one of them, but it will not affect another. Such risk mitigation is critically important when customers like Apple, AMD, Nvidia, or Qualcomm, which demand a continuous supply. There is potentially another bonus with ramping up these fab phases in parallel rather than in serial, so read on.

N2 ramp: One Team and the Super Manufacturing Platform

Such an unusual ramp strategy seems to be enabled by two programs at TSMC: the "One Team" collaboration between R&D and fab operations, and the Super Manufacturing Platform (SMP) that enables multiple fabs (or rather fab phases) to work as one, which likely has similarities to Intel's "Copy Exactly." TSMC hasn't shared many details about the One Team and SMP, though we can make some educated guesses.

The One Team is a global manufacturing knowledge-transfer system that links R&D, process integration, equipment management, and high-volume manufacturing expertise during technology development and ramp-up. To speed up feedback loops, TSMC likely inserts manufacturing teams relatively early in node development so that R&D teams adjust their work to what is possible at fabs. As a result, yield learning, process optimization, and tool productivity improvements can be done quickly at one fab and then transferred to others. TSMC says that One Team enabled a 20% faster technology transfer compared to N3, without disclosing the time it typically takes to transfer technology from one fab to another.

In addition, all of TSMC's GigaFab sites now rely on its Super Manufacturing Platform (SMP), which is essentially a centralized manufacturing-control system that makes multiple fabs operate as one giant synchronized fab with standard process recipes, tool configurations, metrology, and yield management flows. This should enable TSMC to transfer production between fabs more easily, ramp new nodes faster, introduce yield fixes globally instead of locally, and reduce customer requalification work when production of chips is moved from one fab to another.

Moreover, since every fab phase generates its own tool behavior data, defect density data, process window statistics, and yield learning information, multiple simultaneous ramps may actually accelerate yield/defects learning when SMP and One Team are in place. In turn, it may speed up ramping of fab phases.

A 70% CAGR in N2/A16 capacity in the coming years is an extraordinarily aggressive ramp for leading-edge manufacturing. Without something like TSMC's' One Team structure and SMP, coordinating that scale of expansion across multiple Fab 22 phases, Fab 20, and eventually Fab 21 phase 3 in Arizona would be barely possible both from organizational (operational control) and from economic (yield learning, process window, etc.) points of view.

TSMC also noted that despite the significantly higher complexity associated with gate-all-around (GAA) nanosheet transistors, N2 is achieving a better yield learning curve than N3, which again can be attributed to the innovative approaches that the company uses.

Beyond N2: A14, A13, and A12

TSMC's N2/N2P/N2X/N2U/A16 production will largely be concentrated at Fab 20 phase 1 and 2, Fab 22 phases 1, 2, 3, 4, and, to some degree, Fab 21 phase 3. However, for nodes beyond 2nm-class (A16 is essentially N2P with a backside power delivery network), such as A14, A13, and A12, TSMC will build Fab 21 phase 3 and then the all-new Fab 25 site in central Taiwan with at least four phases.

A14 is set to start high-volume production in late 2028, so there is a good chance that TSMC will ramp it at both Fab 20 phase 3 and Fab 25 phase 1. However, given the company's aggressive approach to capacity expansion, TSMC might well surprise us once again. Also, we do not yet know how TSMC plans to upgrade N2/A16-capable fabs to subsequent nodes, if at all.

Expansion beyond N2

The expansion is not limited to the N2 production node and subsequent technologies. TSMC is continuing to grow combined N3 and N5 capacity at a 25% compound annual growth rate (CAGR) from 2022 through 2027. To address immediate demand, the company is converting some N5 capacity into N3 production, which is not particularly expensive, since N3 reuses 85% - 90% of the tools used for N5. Furthermore, as much of TSMC's N3 and N5 capacities are concentrated at Fab 18 (four phases N5, four phases N3), converting some of the N5 capacity to N3 is relatively easy from a logistical perspective.

AI is here to help (to build more AI processors)

Alongside the conversion of N5 to N3 capacity, TSMC also heavily uses AI to improve the performance of each tool, and the whole fab in particular. Essentially, TSMC uses AI to build more AI processors, which seems to be a paradox, but it is becoming popularized as AI becomes embedded within workflows.

One of the things that greatly slows down cycle times of modern fabs is batch processing of wafers in various chambers, something that is an inevitable part of some 5,000 steps. Essentially, 25 wafers ‘wait’ in a (perhaps in a CVD chamber) for a lithography tool to process them individually.

Atsuyoshi Koike of Rapidus thinks differently and believes that a single-wafer processing across all steps can significantly speed up cycle time, but at the cost of tool efficiency. TSMC does not seem to plan to use single-wafer processing (despite its purchasing power, it can likely persuade fab tool makers to produce appropriate tools), but it can certainly optimize the ways in which it uses existing tools to boost the productivity of its existing fabs.

TSMC revealed at its recent Technology Summit that it uses intelligent scheduling systems that incorporate 'state-of-the-art linear programming and heuristic algorithms' to optimize equipment efficiency, though it did not reveal what exactly is done and what is achieved. TSMC further revealed that it uses generative AI algorithms to identify optimal parameters that 'challenge the physical limits of equipment' while maintaining wafer quality. In parallel, the company analyzes tool logs using big-data analytics and text-mining systems to dynamically adjust key parameters, minimize tool idle time, and maximize output.

AI systems are also used for real-time chamber condition analysis to determine optimal chamber-cleaning timing and avoid unnecessary maintenance that could reduce machine uptime and available capacity. In addition, TSMC disclosed that AI-assisted comparison and fine-tuning of large volumes of machine verification parameters reduced the time required to validate new tools and reach high-volume manufacturing by more than 20%, which helps to ramp up new fab modules faster.

TSMC also said it achieved more flexible allocation and higher combined N3 and N5 capacity at Fab 18 in Tainan by increasing equipment commonality and integrating 'cross-technologies planning,' which essentially means that the company re-uses as many tools as possible.

Expansion beyond Taiwan

Outside of Taiwan, TSMC continues to broaden its geographic footprint. In Arizona, Fab 21 phase 1 is already producing chips using N4 technology (with capacity increasing by 1.8X this year alone), while Fab 21 phase 2 is on track to start N3 production in Q3 2027. Fab 21 phase 3 targets N2 sometime later this decade, as the company continues to construct shells both for phase 3 and phase 4. The company also reaffirmed plans for an advanced packaging facility, an R&D center, and additional land acquisitions to support future expansion.

In Japan, the company’s Kumamoto Fab 23 phase 1 is already producing 28nm and 22nm chips, while Fab 23 phase 2 underwent a major strategic shift. Originally planned for 7nm-class production, the facility will instead manufacture using technologies down to N3 3nm to address stronger-than-expected local demand and onshoring intentions of local chip designers.

Meanwhile, Fab 23 in Dresden, Germany, which is under construction, is aimed at automotive and industrial applications with legacy planar transistors and FinFET-based 28nm, 22nm, N16, and N12 production nodes.

Advanced Packaging

AI itself is now one of the main drivers behind the company's unprecedented capacity growth. TSMC disclosed that wafer shipments for AI accelerators are expected to rise 11X between 2022 and 2026. The company also highlighted the rapid growth of extremely large dies exceeding 500 mm^2, as shipments of those devices are projected to increase 6X over the same period. Such products typically require lots of wafer capacity (wafer starts) and advanced packaging technologies, since many of these designs use HBM3E memory.

Advanced packaging has therefore become just as important as wafer fabrication itself. TSMC said its CoWoS capacity will grow at an 80% CAGR between 2022 and 2027, while SoIC capacity will expand at a 90% CAGR during the same timeframe. TSMC also said it has improved development-to-HVM transition times by 30% for CoWoS and by 75% for SoIC compared to earlier generations.

TSMC currently operates 11 advanced packaging facilities in Taiwan (AP1 in Hsinchu, AP2A/AP2B/AP2C and AP8 in Tainan, AP3 in Longtan, AP5 in Taichung, AP6A/AP6B/AP6C in Zhunan, and AP7 in Chiayi). According to a recent DigiTimes report, the company is simultaneously expanding multiple advanced packaging campuses, including AP5, AP6, AP7, and AP8.

The AP7 site in Chiayi will reportedly become TSMC's largest advanced packaging campus using SoIC to support major customers like Nvidia, which plans to use 3D packaging technologies for its next-generation Feynman GPUs. AP8 — converted from a former Innolux LCD fab — is expected to exceed 40,000 wafers per month of CoWoS capacity by late 2026.

While CoWoS is the de facto standard for AI processors, SoIC is set to become much more widely used in the coming years. As a result, the company is also rapidly expanding its SoIC production capacity. DigiTimes claims that AP6 in Zhunan could approach 10,000 SoIC wafers per month, whereas AP7B may add approximately 12,000 wafers per month. Future AP7 phases are expected to support both SoIC and CoPoS technologies, though CoPoS is a part of TSMC's roadmap in the 2030s.

Advanced packaging now requires tight ecosystem integration that includes HBM suppliers, substrate vendors, OSAT partners, testing companies, materials providers, and toolmakers, with which TSMC works to standardize those tools. The very emergence of such an ecosystem emphasizes the increasing role of TSMC in the burgeoning AI industry.

An all-encompassing roadmap

After investing nearly $240 billion into capacity expansion over the last decade, TSMC has evolved from the world’s largest foundry into the world's largest producer of advanced logic chips, producing the lion's share of AI processors today.

To support the explosive AI demand and to stay ahead of Intel and Samsung Electronics, TSMC has doubled its historical fab construction pace to nine fab phases annually in 2025 – 2026 while simultaneously expanding in Taiwan, Arizona, Japan, and Germany. The company's N2 ramp is unprecedented as the company preps to ramp five fab phases within the node's first year, and N2/A16 capacity is projected to grow at a 70% CAGR through 2028.

TSMC said this aggressive expansion is enabled by its One Team organizational structure and Super Manufacturing Platform (SMP), which synchronizes manufacturing, yield learning, and process control across multiple fabs. The company is also implementing various AI-driven manufacturing optimizations, including intelligent scheduling systems, generative AI process tuning, and real-time tool analytics to improve throughput, reduce cycle times, and accelerate tool qualification.

At the same time, TSMC is rapidly expanding advanced packaging capacities. The company intends to increase CoWoS and SoIC capacities at 80% and 90% CAGR, respectively, through 2027, as demand for both technologies is expected to grow as chiplet-based designs and HBM memory are technologies of choice for AI accelerators.

*TSMC's wafer processing revenue for 2025 was $103,708.5 billion, thus representing around 84% of consolidated revenue of $122.4 billion. EUV-based N3 and N5 process technologies accounted for 60% of TSMC's wafer revenue in 2025, thus earning around $62,225 billion. Intel Foundry earned $17.826 billion in 2025, $307 million came from external customers that mainly ordered advanced packaging. It is estimated that process technologies that use EUV account for more than 10% but less than 20% of Intel's wafer revenue.

Intel does not disclose a revenue split similar to TSMC's (wafer fabrication vs. packaging/testing vs. other) in its official filings, so its wafer processing revenue is hard to estimate, especially given the fact that some of its silicon is made at TSMC and is packaged internally. Nonetheless, even 20% of Intel Foundry's 2025 revenue is $3.565 billion, which is over 17 times less than TSMC earns on its EUV-based nodes.

The AI revolution that shows no signs of stopping appears at times to have echoes of the gold rush. Whisper networks spread quickly through communities about new scarce commodities, and suddenly there’s a surge of interest as people snap up resources. For most of the ChatGPT era, you’ve struggled to get hold of a GPU for neither love nor money, with Nvidia practically able to manage its own waitlist, so great is the demand.

Much of the media’s attention – and plenty of investment – has been focused on the dash to grab as many GPUs as possible; most recently, memory has become a focal point.

But in recent weeks and months, there’s been a focus on ensuring that people have CPUs to match. For decades, the CPU has been the anonymous workhorse of the hardware stack, running operating systems, scheduling workloads, and keeping everything ticking over, rarely grabbing headlines unless there’s a supply crunch or a generational leap in performance.

Suddenly, it’s being talked about in the same breath as scarce-as-gold GPUs. What’s going on?

“AI deployment at scale has forced organizations to look at the infrastructure underneath the hype,” said Jason Beckett, chief technology officer in Europe, the Middle East and Africa at Hitachi Vantara, in comments to Tom’s Hardware Premium. As Beckett points out, while most of the attention is focused on GPUs because they run the AI models, the CPUs are vital because they handle “everything else”.

And as agentic AI becomes the norm, there’s a greater need for that CPU backbone to keep things running properly. “Always-on, multi-step reasoning systems don't create brief orchestration bursts around GPU workloads,” said Beckett. “They demand high-core-count CPUs running at sustained loads, continuously. The infrastructure requirement was always structural. It's just now unavoidable.”

Readjusting ratios

When data centers were previously being specced to deliver AI training and inference in the early days of the generative AI revolution, those building them accounted for a gargantuan bias in favor of GPUs. Chatbot conversations required between four and eight GPUs to every single CPU required, because the parallel equations required to meet user requests were GPU-inference heavy.

But as the main use case of AI changes from chatbots to agents, the requirements have also altered. A slight delay for in-depth inference while an AI model ‘thinks’ was seen as an acceptable interface choice. But as agentic AI requires rapid responses and the smooth coordination of tool calls and much more, latency can be a killer. Bolstering CPU counts can help avoid any problems that can quickly spin out into something more significant, breaking the entire agentic stack.

AMD, one of the major manufacturers of CPUs, has seen that shift first-hand. The company had previously forecast that the CPU market would grow at a rate of around 18% annually, but says that the change in requirements has materially changed the market. The rate of growth has now doubled to 35% a year, AMD claims, and will become a $120 billion market by the end of the decade.

“What AMD and Arm's results are telling us is that this is a structural, not cyclical requirement,” said Roger Cummings, CEO of PEAK:AIO, in an interview with Tom’s Hardware Premium. “In actuality, two structural shifts are driving the demand surge: the rise of agentic AI and the need for deterministic, predictable performance at rack scale.”

Much of that CPU demand is being driven by hyperscalers, who recognize the integral role that CPUs play in developing the AI clusters that are likely to power the economy in the years to come. “As GPU clusters scale, CPUs are taking on larger roles in orchestration, memory management, networking, storage coordination, and inference handling,” said Jeff Moore, vice president of strategic partnerships at Aegis Cooling, which specializes in next-gen liquid cooling solutions for AI and high-performance computing infrastructure, in an interview with Tom’s Hardware Premium.

There’s a rise in CPU-to-GPU ratios inside AI deployments, said Moore, “particularly because distributed AI workloads generate significant demand for general-purpose compute, memory bandwidth, and east-west data movement.” A recent TrendForce analysis points out that CPUs’ contribution to latency – accounting for nearly 91% of all the delay in responses – is something that AI deployments are trying desperately to counteract.

Changing designs

That shift is now visible not just in financial forecasts, but in the physical design of AI infrastructure itself. In early generative AI deployments, racks were often built around dense GPU configurations, with CPUs effectively treated as supporting components – enough to keep the system running, but not a bottleneck concern. Things are shifting now. “In the media, an AI rack is pictured as a giant box of GPUs,” said Hommer Zhao, founder of OurPCB, a PCB manufacturer with more than 15 years’ experience, in comments to Tom’s Hardware Premium. “But from a hardware design perspective, a GPU is just a very fast, very dumb engine. It cannot talk to the internet or pull data from a hard drive.”

Rather than a single host CPU loosely paired with multiple GPUs, hyperscalers are deploying configurations with higher core-count CPUs, more memory channels, and, in some cases, multiple CPUs per node to keep pace with data movement demands.

There are also thermal and power considerations shaping how racks are populated. High-core-count CPUs, especially those optimized for cloud workloads, are being selected not just for raw performance but for efficiency under sustained load. In liquid-cooled environments, CPUs are increasingly part of the same thermal design envelope as GPUs, rather than an afterthought cooled separately with air.

Financial signs of success

Recent results from AMD and Arm reinforce the idea that this is not a short-term correction but a deeper architectural shift. AMD has reported strong growth in its data center CPU segment, driven in large part by hyperscaler demand for its EPYC processors, which offer high core counts and memory bandwidth well suited to AI orchestration tasks.

Arm, meanwhile, is benefiting from hyperscalers designing their own custom silicon. “Arm accounts for close to half of all compute shipped to top hyperscalers in 2025, with over a billion Neoverse cores deployed,” said Beckett. “Those are rack-level architectural decisions made years ago.” AWS’s Graviton, Google’s Axion, and Microsoft’s Cobalt chips all reflect a move toward CPU architectures tailored for specific workloads: high-throughput, energy-efficient, and tightly integrated with networking and storage. Arm’s licensing model positions it at the center of this trend, and its recent financial results highlight how significant that hyperscaler-driven demand has become.

Both sets of results point to a change in how CPUs are being valued. In traditional enterprise contexts, the hardware was often general-purpose and interchangeable. In hyperscaler environments, it’s becoming a specialized infrastructure component, tuned for specific roles within AI systems, whether orchestration, inference at the edge, or data preprocessing.

Taken together, the changes in rack design and vendor performance suggest that CPUs aren’t a secondary consideration in AI infrastructure planning any more. Instead, they are becoming a critical factor in determining overall system efficiency and cost.

“The spotlight hasn't revealed something new,” said Beckett. “It's just finally illuminating what serious infrastructure teams never stopped building on.”

As the crowds in Taipei thin out and the crowds begin to disperse, our team on the ground at Computex 2026 ruminates on their experiences of the show itself and what it might mean for the industry at large. Day four will be our final entry into the Tom's Hardware Unfiltered series for Computex 2026, so we hope you've enjoyed peeking behind the curtain to gain an insider look at exactly what we've been up to this week.

Starting at the end is just wrong, so if you haven't yet caught up on all of the coverage coming out of Computex, be sure to check out the entire series of blogs.

• Computex 2026 Day 0
• Computex 2026 Day 1
• Computex 2026 Day 2
• Computex 2026 Day 3

Paul Alcorn: Editor-in-Chief

Day four was yet another hectic affair, with a string of meetings in the early morning continuing into the afternoon. This Computex has certainly had more attendees than I ever recall on the second day, and today was no different; there were a surprising number of people cramming all the aisles, and of course, jamming up the booths, which isn’t great if you’re trying to take pictures.

I also noticed that this Computex has far more business-to-business (B2B) focused companies in attendance. In the past, we typically saw strictly consumer products and the myriad of companies that feed into that ecosystem. This year was definitely an explosion of AI and data center technology, which is surprising. Also, the big showcases dedicated to data center hardware were absolutely packed, often just as busy as the ROG and ASRock booths of the world, if not busier. Others have noted that there really isn’t an Asia-based trade show for data center tech, and it seems that Computex has now become that destination at an incredibly fast rate.

Joe Shields: Staff Writer, Components

Day four is in the books. I managed to get about two to three hours of sleep last night, and it’s been a long day, even though I got all the meetings done early. Today’s journey began at the Grand Hyatt Hotel (Hyte), right next to the beautiful Taipei 101. Soaring over 1,600 feet in the air, the blend of traditional Asian aesthetics and modern engineering is a sight to behold.

Hyte showed off a few new items, including the Y50 case, a less expensive version of the popular Y50. We finally made it to the Gigabyte booth at the convention center and had a chance to see the X870E Infinity Next motherboard in person, and wow. It’s absolutely stunning with the 3D-printed metal heatinks and that lava-rock-like pattern. Be quiet! Showed off a few items, but I was impressed with the Light Base 803 chassis, and a new power supply (Dark Power Pro 14 IO) with software monitoring that even shows how much it costs to run your rig.

My last appointment was at Thermal Grizzly, who showed off new coatings for their waterblocks, new thermal pastes, and different versions of the WireView Pro for you RTX 5090 owners. By that point, I couldn’t tell if I was coming or going, and thankful all of my appointments were done. A little nap at the hotel and I am back to writing about Computex for the last night.

I’m incredibly thankful for the opportunity to come out to Computex. For me, it’s a completely different experience from CES in Las Vegas. Both have their positives and negatives. Tomorrow I’m excited to get a tour of Asus HQ, but really looking forward to starting the long, long trek back to the U.S. It was real, it was fun, but it wasn’t really fun. Ohio, here I come!

Jake Roach: Senior Analyst, CPUs

This was my last day in Taipei, and I tried making the most of it. The majority of my morning was spent running back and forth between the two halls of Nangang and talking with various companies, racking up some 20,000 steps in the process (the halls are literally across the street from each other). Some of the details of that tirade through the trade show I can’t talk about quite yet, but as the blisters slowly forming on my feet will tell you, I kept myself plenty busy.

My afternoon was spent at Asus HQ in the Beitou District (about an hour-long trek from Nangang on the MRT). I usually visit the Asus campus, and it is beautiful. There, I met up with several Asus reps and various other media to learn more about Asus’ announcements, as well as some products that are coming down the pike. But, as you might expect, I can’t talk about those quite yet.

Leading into Computex, the week always seems so long and grueling. And it is, make no mistake. But the irony is that right as I start to get adjusted to the 13-hour time difference and begin feeling like myself, I’m packing my bag to head home. It’s always too much time, but never enough. Oh well. I’m finishing my night with a nice plate of omurice, which I can not get at home, and trying to catch a few hours of sleep before spending 18 hours in a plane seat tomorrow.

Jeffrey Kampman: Senior Analyst, Graphics

After four intense days writing into the early hours, visiting vendor showcases, and criss-crossing the show floors at both TaiNEX halls, today was my last in Taiwan, so I once again headed over to Nangang before my departure to ferret out any last hidden hardware gems that we might have missed.

I walked through the massive Gigabyte booth with Joe, admired the company’s classy wood-trimmed Aero cases and Infinity graphics cards, and mused with Gigabyte staff about how the show and the industry have changed since I was last at Computex almost ten years ago.

DIY PC building is, for better or for worse, increasingly a guided, safe experience. The big component companies are now more than happy to serve you a full menu of coordinated parts that are practically guaranteed to come together into a coherent build. It’s getting harder and harder to find examples of earnest whimsy among booth after sprawling booth of Vera Rubin NVL72 racks and their supporting infrastructure. (Indeed, Vera Rubin NVL72 is so tightly standardized that racks from different server vendors are practically indistinguishable from one another!)

But my next stop was down the escalators to G.Skill’s booth, which maintains much of the freewheeling enthusiast spirit that I recall from my last visit to Computex so many years ago. If you want to see extreme overclockers chasing world records in real time through swirling clouds of liquid nitrogen, G.Skill’s booth is the place to be. And I got to go deep into the weeds with the company’s reps about DDR5 sub-timings, the resultant memory latencies, and their effect on modern CPU performance. After a week of parsing bold visions for the future of computing, it felt good to get back to the basics. Farewell, Computex, and I hope to be back in Taiwan soon.

Qualcomm's Snapdragon C is making a major play for the hottest laptop market in 2026: The ultra budget segment. But competition is stiff, with Apple's MacBook Neo and Intel Wildcat Lake Windows laptops offering strong performance and battery life in affordable packages - even with sky-high global memory prices.

We sat down with Qualcomm's SVP of compute and gaming, Kedar Kondap, and other Qualcomm representatives at Computex 2026 to hear how Snapdragon C fits into its existing product lineup, and how Qualcomm considers itself uniquely positioned to offer a comprehensive ecosystem of agentic AI devices and software.

This transcript has been lightly edited for clarity.

Kedar Kondap, Qualcomm SVP of Compute and Gaming: Our journey was not about solving what has happened in the past 30 years of PC innovation, but solving what's coming next in PCs. A lot of the innovation that has happened, we've obviously proved to the market that we're exceeding performance. We focused on three big metrics all along the way. One was leading with performance and making sure that we have leading performance in all of our silicon. We want to make sure we lead with power. Obviously, that used to be something super critical across the board, even as we start looking at newer generation of devices, and third, as you look at AI as a key metric.

When you think about the keynote today, and what we talked, what I shall talk about, as we enter this agentic world, it is more and more important. Each of these things play a very important role, whether it's performance, whether it's power, or whether it's AI, and the ability to run these intelligently. Right from whether it is a very small device, all the way to the data center. You saw how we're innovating, and the PC is no different. So we launched our X series processors, we extended that to the X Elite, the X Plus, and the X family. We launched the X2 Plus, we launched the X2 Elite, and the X2 Elite Extreme, and we wanted to make sure our intent was very simple: we wanted to make sure that the experiences we offer are available to all the consumers at every price point that we could address. What we introduced yesterday is a new class of platforms, the Snapdragon C. Our intent with that is to address platforms in lower price points that we can go and make sure that we can deliver the same performance pillar, the same battery life pillar, as well as provide AI functionality to all the consumers at price points that were never heard of.

So with that, we wanted to make sure that we have a full stack of products, we are addressing the needs of what consumers want. Consumers want the best performance, the best battery life, and as we enter this world of agentic beta, we want to make sure that across different devices, we're addressing all of these price points. So, we’re excited to be here, and I know there's a little bit of a longer introduction, but I want to make sure you have the perspective of where we come from.

Journalist 1: Thanks, Kadar. Nicole. You were just on stage with Advantech. Can you get us a little background on your announcements and what was said on stage?

Qualcomm Representative: Advantech has been a great partner of ours. I've done more recently the industrial business for Qualcomm, and so, you know, for us to get into this new area, and industrial is actually changing very rapidly. We are starting to see AI enter into the operation, advantage has been here in this space for a number of years, and so we announced a variety of different products to them over the last couple of years. Great to actually be at their keynote. We also announced yesterday [unintelligible] robotics reference design, which is something that is a new area for us. We've been partnered with Advantech for a number of years in this space, but the robotic session design will be a humanoid focus session.

Journalist 2: I'm wondering, Nvidia, a few hours ago, announced they were entering PC market. You guys have had it yourselves for the last two years. How are you thinking about how others come into [unintelligible].

Kedar: Welcome to the family [laughs]. We are, you know, we're excited when you think about the investments that we've made over the last several years, it's a good endorsement to the fact that there is an ecosystem that's growing outside of x86. We invested early on, we invested many years ago, with right from whether it is driving the ecosystem, driving the entire platform story. Whether it is getting the printers to work, whether it's getting the software apps to be compatible, whether it is getting the docs and peripherals to work, whether it's getting more than 2500 games to be compatible with Snapdragon, we led the way in driving that ecosystem, and I think this is positive tailwinds for the entire ecosystem. They'll tell us how we're all taking the ball forward in the trajectory that we started.

Journalist 3: This is for Nichole. She's had remarkable success in automotive and moving into robotics. Is there anything you’ve learned [unintelligible].

Qualcomm Representative: We’re learned a lot from automotive. I think AI at the edge with robotics is a really fascinating space, because you are starting to see this transition where you start to apply AI to start off with an unskilled worker, gradually start to go build up on level of skills, and ultimately start to get to something great. A lot of the underlying capability is similar to what we saw in the early days of automotive, especially the mobility part is quite similar. That will scale very quickly. We will start to see coarse dexterity, so that it's essentially transportation of goods, et cetera. That will happen over the next couple of years, and then the more complex final precision tasks will take more time.

But we are betting across the board, we are betting on models, we are betting on full embodiments. You'll hear more about this tomorrow. We're betting on a variety of different form factors with arms as well. We are also starting to look at what we can do in the end effector space, so we have a lot of technology around precision for the actual and effect of the arms, the actual digits, and what it is. What I like about robotics, which is quite different from the car, is that within the same embodiment, you have to have a lot of different technologies that cooperate, and that is something that we have a lot of capabilities. Lot more to come, but I think super interesting.

Journalist 4: When I was at the keynote from Jensen Huang, I was surprised when he mentioned the RTX Spark platform will support every Windows software ever written, and you suffered from Windows software in running on ARM. So, could you comment on that? And another question, if you could maybe share some more details about Snapdragon C platform, especially the TOPS. I saw a model from Asus, but it was behind in the glass box, and they didn’t have a lot to say of interest in that matter.

[Jensen Huang] mentioned that they will do an announcement tomorrow with Microsoft about the RTX Spark, and he mentioned that every Windows software that has ever been written will run on their platform, and this is not true for your platform, and probably for any Windows on ARM platform right now. So, I'm wondering if you want to comment on that.

Kedar Kondap: I don't want to speculate, but I'll tell you, our partnership with Microsoft has obviously gone several years in the past. We worked with them very closely. We launched the first Copilot class pieces together. We launched the first platforms where Microsoft OS supported it, and supported how these distributed computing work across a different course. So maybe once we start getting more information, we can, but I think I'm sure the engagement of Microsoft is strong enough where we work with them to build this entire ecosystem to make sure that it's compatible with Snapdragon and the architecture, so maybe once we get more information and get more, we can look at it.

The second question on Snapdragon C, so we haven't yet given out the specs for the products, but I'll tell you how I think about Snapdragon C. We wanted to, our OEMs are very anxious to bring this product to market, as is Qualcomm. There is, as we all know, there is a memory supply challenge in the market, and I've heard there's a storage supply that's also challenged, and we wanted to make sure that we have an offering where we can address a lot of price points that we've never addressed before, so think price points below what Snapdragon X has offered in the past. Snapdragon X will give you its relatable, you know, it's great platforms that get 599 today, some of them that hit 500 and above the X plus goes above and X Elite goes above that, so think it's a tier below what we can offer with Snapdragon X, and so our intent with that is to drive the same level of capabilities, obviously scaled to that tier, and what I'll tell you, it's just like the way we've exceeded expectations in launching specs of our products in the X series family of products. You should expect that the C in its class of products will lead its way, but we'll obviously give out specs for you.

Journalist 5: I've got a question regarding [Qualcomm’s] vision on how the tokens in a car, in a PC, in a smartphone and adapts and talk to each other. Cristiano said that we're going to need zillions of tokens, and they're going to be orchestrated. It means different parts going to generate the token, where it's relevant. Okay, like latency, horsepower. How do you gonna orchestrate them with your industry? Are you planning to build a software ledger, SDKs, or building a patented or open system? How do you plan in this vision to open everyone with a heterogeneous chip market, it's going to be difficult to make everyone work.

Qualcomm Representative: So I think it will vary by the ecosystem, but yeah, we will certainly build orchestrate the [unintelligible] where it does make sense. I'll give you an example of a car. We had already seen in the car a tremendous amount of content. You don't actually need, you can't even expect in many cases to be running models that all just have to go back to the cloud, just because of networking latency. So we have deployed already earlier this year 30 million parameter models in car. It depends upon what the types of use cases you're trying to run, but then if you think about this in the context of splitting search versus what it is that you're trying to run locally within the vehicle that is happening today. I think this starts to get more and more sophisticated as you start to define what is the use of the model at the edge.

So, with industrial, for example, we are starting to see already VMA is getting deployed in cameras when you have evidence at the edge, where you can annotate at the edge, send it out to cloud as an input, so it's going to depend quite a bit on which the ecosystem that you're trying to run your account. If you look at use cases like polling, if you look at use cases like search, those are probably obviously much more in consumer and enterprise nets, which should have different network orchestration, probably much more controlled by traditional ecosystems. An orchestrator is going to be a fairly standard offering as well.

Kedar Kondap: Aiden. I'm going to add a little bit more context also to what we'll just say, you know, the way you should think about how we think about overall income advantage, it's going to be the context awareness that you get across the various devices, and think of a personal knowledge graph that you build in the examples that he showed, right from whether you're wearing an XR glasses. We are able to connect. You can see what you see, you hear what you hear. You can have context awareness of what the user is doing. It's going to listen to what information you talk to when you're, say, at the doctor's office. You understand exactly when your next appointment is.

The ability for it to abstract all of this information, transfer that knowledge graph agentically into your calendar, into what your daily routine is, be able to take your personal information, whether it's talking about your healthcare routine. The goal that we see is first is to bring all of this orchestration together, and Qualcomm is uniquely positioned, as you can tell, right from whether it's a small physical personal device, whether it's a ring, or whether it's an XR glass, all the way from phones to PCs to automotive to robotics and data centers, we feel like we're in a unique position like one another.

Second, on the question about running stuff on device, now we've always said the world in the last two years. You know, I remember when we launched Snapdragon X Elite. We said with a lot of pride that, oh, we can run 30 billion parameter models. You know, today, fast forward that conversation, we showed 20 30 billion parameter models running on the C Snapdragon X platform. So, models have evolved. I can, what I could do earlier with, you know, accuracy of quantization and stuff, I can do a lot more than I couldn't do in the past. So the industry is evolving, where we're innovating, we're adding more capabilities to each of these devices on-prem, I'll say, or physically on device. At the same time, we know that the token economics, as Krishna showed, everybody in the industry see it?

So, if any of you use, if you have a poster subscription towards AI, you know you run out of tokens very quickly, and there is the fatigue is real, the fatigue on the side of a consumer, the fatigue on the side of the model. You cannot have both of those, the balance doesn't exist today, so the way we see it is one, you can connect all these orchestrations across the devices, same, you can orchestrate on what runs locally on the device, and of course we believe some of it will go in the cloud, and that hybrid orchestration is where we believe the industry is going, so build the knowledge graph across devices, run what you can locally on the device, if not, if the model is large enough, it will go to the cloud, and this whole equation will evolve over time as models start to become smaller, as they start getting quantized accuracies to be better.

What was, like I said, a 30 billion parameter running on a Snapdragon X, I can already run 30 billion parameters models quantized with very good accuracy. So that's how what we mean by this industry and ecosystem is going to change.

Journalist 6: I would like to touch on Snapdragon C again. You expect the platform to be a regional-specific solution, like for emerging markets, for example, and Qualcomm has great experiences in markets like India, for example, where do you expect it to be a global platform? And I'd like to touch on the NPU as well. Previously, every Snapdragon X platform, at least, had an NPU that OEM Certified Assistance for Copilot Plus seems to be the first solution where you sort of loosen your own set of requirements for a Snapdragon compute platform, and what led you to that decision?

Kedar Kondap: So, Nicholas, first I'll answer your first question, which is: it is a global platform. You will see this device launch globally. You know, for us it's there's a large stamp, as you know, in this particular segment. Lot of consumers that use PCs that sit in, I'll say, below the $500 price point. So, we have a large stamp that we can address there. The TAM [Total Addressable Market], as you know, is naturally biased towards emerging markets. So, from that perspective, yes, the focus, you'll see the platforms launch in many of the emerging markets, as well as developed markets. The TAM is much reduced in that, so it's just a function of the definition of where the time sits.

Your second question around NPU, no the platform does have an NPU, we just haven't talked about the sizing, but as you can tell, the silicon economics, we're sizing everything with the capabilities to be able to run use cases synchronously with the price point that we're addressing. So, think of it as you'll still be able to run, get a lot of the capabilities, you'll still be able to run a lot of use cases we talked about, while preserving the performance and battery life goodness that we bring with the Snapdragon product, so you'll see something very similar.

Journalist 7: There's been a lot of good questions on Snapdragon C, but if you're not competing with Neo, what specific product lines of products are you competing kind of in that below $500 price range?

Kedar Kondap: You know, you already heard a couple of our OEM partners talk about devices. I think Asus talked about the device. I want to make sure I don't jump the gun with the excitement that our partners want to launch it, but I think Asus has already announced. We've also addressed the fact that Lenovo, as well as HP, we announced with HP. Just want to give out somebody's information. We've announced with the OEMs, it will sit as I said, you know, Snapdragon X sits at around 599 type products, and it competes, as you know, better than what you can get with Neo and performance insights.

This gets the price points that it would be below 500, obviously. Now, the thing I always have to caveat is the memory and storage prices. I never know what it's going to do to devise price points, but that's how the platform is positioned. Think of it as small core competing products, but you know I'm nervous to say that, because it's going to be so much better than what existed in the market, so that's why I don't want to tell you that it's compete against that, because it's a different class, it's going to be a lot better than what's what you're used to seeing in market,

Journalist 8: Sorry to ambush you with another Nvidia question, as I know you already said you didn't see the announcement. They are going after a market that you guys have historically not went after, I think a few years ago you publicly said this is just not our wheelhouse, so are you guys planning to compete with what Nvidia is doing now, and if so, how?

Kedar: Like I said, I haven't seen this. I don't know what they've announced, but at the end of the day, look, we've come a long way from where we started. We go a couple years back, what we said, Rich, was we have the legacy, we have the technology in even things such as gaming. We come from, as you know, we have a very strong game studio house. We work with all the game engine guys to work with the net engine guys. We work with the studios on the mobile side and other platforms that we work with, but we bring all of the games to Snapdragon. Since we launched Snapdragon X in less than 24 months, we've done a lot of games that work with Snapdragon effectively go from 1300 to more than 2500, 2600. So I think what we've mentioned in the past is not that we couldn't support it, what we've said is we want to carefully not position this as a gaming laptop, right? The gamers who think of launching this as a AAA game-based laptop is not what we want to position.

We don't want to create confusion with what we're addressing, but from a technical perspective, nothing prevents us from addressing a lot of that, because, as you know, even when you think about creators, we've talked about our partnership, and what we've done with Adobe, what we've done with Black Magic, and others. So, we've already showcased that the entire creative industry is something that we support. We sold multiple use cases, so it's the entire ecosystem that already we've been addressing. So, like I said, I'm assuming that their introducing their platforms in market today is tailwinds for what the ecosystem will see as a strong showcase of non-x86 architecture.

Journalist 9: On the question of the Snapdragon C, somebody spoke about the emerging markets. One of the things which has happened in those emerging markets that arise on the tablet usage. So in the past three years, four years post pandemic, you can say that many of the people are buying who are stuck between a rock and a hard place, that you know, laptops are slightly expensive, they have a full use case of the productivity of a laptop, but they wanted a slightly bigger screen, so they are buying with sliders and the keyboard, especially the emerging markets. So, I just want to ask you, is your target that consumer, and do many of those cohorts is parents buying for the kids or education market, private or public, both? And the public market, you know, you know some of the PC loans, they've really done well, and they are restricted that success in the past year or so in education and some of those emerging markets, because the price points are creeping up now. So I just wanted to double click on that. Who is that target consumer in those emerging markets where we expect the volume to come from?

Kedar Kondap: So, as you know, we already play in a very strong manner with the Android tablets in all of those ecosystems, we have very strong partnerships across almost all the OEMs that you can think about. We have Samsung, OV, WOSU, Lenovo. We have all of these tablets that have launched. There are specific tablets I've launched that are focused on gaming all the way to productivity, all the way to education. So we have very strong portfolio products launched even in emerging markets with our partners.

With Snapdragon C, I can see a market out there, as you correctly pointed out, education being a very strong segment would address all of that. So, if you saw the press release that we talked about, which Snapdragon C we specifically call out that we will be in the education space. We are doing a bunch of pilot programs with our partners to go and address that. I wouldn't necessarily say that it's going to replace Android tablets, necessarily. I think hard to call whether that ecosystem is going to move away from Android to Windows, but right now they coexist pretty well. Like, there's a good TAM that's available for Android tablets with a stylus, as you correctly pointed out, as well as a TAM with Windows PC, and I think with this particular one, for now we'll be launching the Windows segment.

Journalist 10: Can I talk about we just launched, like Qualcomm with Asus A16? Will you deepen with Taiwan cooperation?

Kedar Kondap: I can't tell you how grateful I am for the partnership with the entire Taiwan ecosystem. The partnership goes obviously deep partnership with the ASUS, and we're grateful for the partnership with ASUS, brings a lot of innovation and market. If you've seen, if you haven't already played around with it, or if you haven't seen it, I encourage you to look at the A16 device with the Snapdragon X2 Elite Extreme product. It's a beautiful, thin, light laptop with significant hours of battery life, so it's a, it's a beautiful laptop, and that's because Asus brings a lot of innovation. You heard yesterday from Acer with the Snapdragon C platform that they're launching, but it goes beyond just the OEM partnership for us here in Taiwan, right?

We work very closely with all the BIOS guys, whether you know all the IBDs, we work with the inside, we work with AI devotees, we work with all the partners there, we work with all of the EC manufacturers, we work with ecosystems, so it's not just one cookware, we work with the camera sensors. So we do a standard ecosystem partnership summit here in Taiwan, the offense is just because innovation is going to happen here, and I think what you hear, even as I speak on Wednesday, is as we talk about what we try to throw the vision of moving to agenting, it's going to need a lot of innovation, that innovation is going to change the way the PCs are going to look, is going to change the edge appliance market, is going to change, because now you're going to be running these hybrid models, running and stuff, and we really believe that Taiwan is the hub for driving innovation, and, like I said, we're very grateful for the partnership that we've had with this ecosystem for the last many years.

Journalist 11: Looking towards the intelligent orchestrator for managing workloads. Do you see a primary device managing the personal AI agents? Would it be a smartphone, a transportable puck, a locally hosted cloud instance, for example?

Qualcomm Representative: I think the orchestrator is actually going to be associated with the user, so it's going to be a personal orchestrator, and the devices will evolve along that orchestrator. I think it depends upon the specific ecosystem that you refer to. So, let me pick an ecosystem that may be different from a personal device that is owned by an Apple or Google system. There are several ecosystems where the personal draft, for example, is specific to the enterprise that would like to own that specific data. It could be within an industrial environment, it could be something that requires the data to be resident within the premise owned by that specific enterprise.

In those environments, it really just comes down to what is the type of data that is being exchanged, whether it is data at the edge, data that is network specific, that is manipulated, that is interacting by the specific data. As you start to think about this in the context of the enterprise, I think, depending upon the type of data that this might be, so if it's a personal device like a camera or my glasses, then it starts to move towards the context within the data, there will be changes in the interaction, so for example, today if you think about enterprise data that is sitting on your laptop, that is part of your email, that is part of your SharePoint. How does that interact with the personal devices that you have? Those are things that, in my mind, are still going to get sorted through, but you're going to start to see the personal graph nature move more and more towards the user itself as a personal device.

We believe that the cross-device, as I said earlier, is what will play a super important role. The context awareness from the agent having access to your personal information and bringing that context to information from one device to another, and being able to drive that continuum, is what's going to differentiate more common. We feel we're in a very unique position to be able to go from pocket all the way to the cloud in driving that entire ecosystem.

Journalist 12: I have a question about the economics of the new world you mentioned already, the memory crisis, the skyrocketing memory crisis. I would like to know what impact you expect of the rising memory prices on the development of these agents in future on the consumer side, enterprise side, but also maybe on the other platform side.

Kedar Kondap: I think let's separate out two different things. One is we've all people that have been in this industry long enough to know the sequential nature of what happens with memory. Of course, this time is an anomaly in terms of what we're all seeing. I respect that, but at the same time, we know that eventually the supply chain economics balance out with that, right?

Like, over time, it may not come to the same levels as what we've seen in the past, because this is obviously a super cycle in terms of memory that we've never seen before, largely because of the needs of what AI, what the ecosystem needs. At the same time, though the token economic problem is a real problem, which is you as a consumer you want to be able to use more AI and you want to be able to be more efficient with what you're trying to do, but you're there's only so much in terms of affordability, same thing on the enterprise side, all of what you think about op-ex moving to capex, you have to be able to have that migration happen where you see your op-ex that you invested in and you're going to start moving to capex, or you're going to start getting every employee is going to get multiple models and drive that efficiency that you can get as an enterprise that you want, that migration is going to happen once you move to the other side.

With that migration, the entire equation of economics changes. Why? Because now, if I'm an enterprise, I know that running stuff on device… I'll give you an example, if I can now start running 5070 100 billion parameter models locally on prem, whether the device is a laptop, whether it's a 5 billion parameter model that runs on a phone, or whether it's an edge of line that sits in my desk running a 50-100 billion parameter model, or it's an influencing card that sits in on-prem, I know that the token economics dramatically changed, but I also know that as an enterprise to be able to run trillion parameter models, I'm going to go to the cloud, but I know I need to invest to be able to run on device.

So this balance of equation is what's important, and we feel like this is where we've always said the world is going to go hybrid, we've always said it's not once you're done with training in the cloud, it's going to start moving to the edge with your inferencing, and we feel very good about the position we're in, because that's where we've been investing for the last several years to drive this on device as well as hybrid approach.

Journalist 13: While wireless transition is a very big effort [unintelligible] has put a lot of time in those transitions and a strong focus, you almost single-handed move the industry to the next level, and that Qualcomm changed a lot, now it's more, much more diversified. So, my question is, is Qualcomm from today able to have the same focus on the safety transition in the future, or it may be more help from the industry?

Qualcomm Representative: We are wireless company first, so yes, we have a lot of focus on safety. I think wireless is in the DNA of the company, and wireless is really part and parcel of everything that we do. I mean, if you think about the complexity of building a cell phone, then there is a reason why very few companies are successful with these things. I think the 6G transition, maybe just to speak with 6G, is a very interesting transition, because we believe that the networks are going to actually become very intelligent in 6G, you'll be able to get a sense of creating a virtual digital trend of environments around you. It will bring telcos into the fore in terms of being able to get a much better sense of the physical world. It's a major area of work for us, and these G transitions take a decade, right? So you know that it took a decade for us to be develop 5G.

Journalist 14: Kedar, you answered a couple questions already on the personal graph and that comment about the agent moving closer to the user. I get the point that Qualcomm spans across multiple devices, and that they're, you know, that you're at a unique advantage because of that. But can you take us through how that would be architected? I guess inevitably, if it's spanning across devices, cloud has to be involved in this process, right?

Kedar Kondap: I think Brian, the way you should think about it is, first, we know that the entire ecosystem is fragmented, and we believe that as different hyperscalers, as different model providers, as different OS vendors, as different silicon vendors, all of these need to come together. We were not giving out much information today on what we're doing there, but as you can tell, what we are trying to indicate to the industry is today we have the ability to thread all of these things together, and we're uniquely positioned on how we want to do this over the next several months. We will come out more with respect to how we want to be able to tie these together, but the industry challenge that you highlight, and that's why we feel like we're at the center of driving innovation across this to bring this industry along to try something that's innovative.

Journalist 15: I'm going to be one of those guys who brings it back to the ARM thing. I'm just going to read you what Jensen said in his keynote, because I think I'm just going to read it deadpan. “This computer literally runs everything the world has ever created, and it runs agents.” So I don't know if that's true, but I kind of wanted to give it to you, and kind of hear, what are you guys working on in terms of like compatibility, or even emulation, because we've seen a lot of interesting ARM-based emulation coming from like open source places, so is there anything you guys are working on in terms of compatibility that is trying to push things forward?

Qualcomm Representative: I don't know how to use a broad statement like this to give you a full answer, but I'll tell you what we'll do today. There's about the last night track with my team, was we were worried about 50 claws that are available in my team, and from a snap back in perspective, X series perspective, these are run on the device, I think Krishna showed a bunch of these, a bunch of claws that he showed on stage, so you should imagine that we're, we've been leading the industry with driving agentic AI and orchestration on the PC for the last couple years.

So a lot of these models already exist, a lot of these claws run very effectively on Snapdragon, the models are running effectively on Snapdragon, so you should just assume right now that we've shown you the data that we're already dealing with industry with tight innovation.

Journalist 16: Do you see robotics requiring the two layers of intelligence like with autonomous vehicles, or will the user interaction be more integrated with its physical functionality? Essentially, will the robot-human interaction be controlled more on the user side or the robot side?

Qualcomm Representative: I think that is going to predominantly be very similar to what they can do today already. So, language in the primary interface, what the human is talking about. Where it starts to get interesting is when you start to get into responding to a command. So, for example, if the human would like the robot to go do something that kicks off a task for the robot to be able to complete, and that is usually not a question answer conversational type interaction that usually requires the robot to be able to take on a longer horizon task that brings in additional models that bring in additional tasks that are outside of what humans might typically engage in, but the primary interface will remain the same conversation.

Journalist 17: I'll bring it back to Nvidia. I just want to add that from a CPU and NPU perspective, I think, from a GPU perspective the RTX 5070 class, what I have been missing is like what is called Qualcomm’s view from the GPU premium side of the market. Let's say personal computer market, so I need a bit of clarity there, and the second part would be to just focus it towards the developers and the AI community.

Kedar Kondap: Let me tell you, let me address your first question, which is when we look at launching a particular platform in market, whether it's the Snapdragon X Elite, the X Plus or the X. We always look at what the market needs, and we have a way to size where we feel like workloads are best run on a platform. It's the composition of how you could think about silicon. We have a very powerful GPU. We have the IP that we've invested in the high-performance GPUs and CPUs in-house for the last many, many years. We have to make sure that we're addressing a certain price point from X Elite to X2 Elite and X2 Elite Extreme. We size a significant improvement in our GPU performance, largely to address a certain set at the same time. You have to know that where we're shipping products are in certain price points with that target ASP in mind. I don't know what the industry is looking at with newer platforms are getting launched in market.

I haven't seen any of that data yet, but I'll tell you, all the cores that we support are sized to do that. With respect to their second question on developers, we've come a long way today in terms of where you see developers. Like, the entire developer ecosystem is behind what we've done. I talked massive numbers in terms of apps ecosystem, we talked in terms of developers porting apps natively on platforms, natively on Snapdragon, optimized to the NPU, so we have all the tools, everything that we've provided. So I think you should just expect that as we start moving into this new era of agentic…

Brian asked the question of how we're going to bring all these together, you should assume that we're working with the entire ecosystem, because I'll repeat what I said earlier. We are in a very unique position to be able to bring all of that orchestration, so whether it's a wearable, like an earbud or a watch, all the way to whether it's a PC all the way to whether it's a tablet, auto, XR, you name it. We're going to make sure that we're sizing all our platforms and technology to what the industry needs for that particular segment, so it's very segment-based in terms of how we look at the market.

[Session Ends]

With the show floor officially open, there's plenty to see and do at the Nanggang Exhibition Center at Computex 2026. However, the reality is that for most of our team, that's not the only place that they will have to visit. At events like these, companies regularly schedule meetings outside of Computex 2026 itself, either to secure more space for their products or to show off products and concepts that aren't strictly ready for the show floor and the thousands of attendees.

In our Day 3 blog, our team of staffers has crossed Taipei, photographed exciting new hardware, and experienced the dizzying halls of TaiNEX 1 and 2. If you've not caught up on their journeys so far, be sure to read Day 0, Day 1, and Day 2 first.

Paul Alcorn: Editor-in-Chief

Another blistering day in the heat of Taiwan started with a meeting with a high-ranking Micron executive to talk about the state of the memory and storage industry. I learned a lot that I will crystallize into an article soon.

After that nice air-conditioned chat, I hit the halls, moving between multiple vendors to see the latest the industry has to offer. Asus, ROG, MSI, Patriot, Adata, and many others kept me busy throughout the day, particularly as I dug deeper into the side effects of the memory shortages. Unfortunately, not a single individual we spoke with expects any sort of recovery soon, and this will have dramatic effects on smaller module makers, the companies that make SSDs and DRAM, and a cascading effect on the other OEMs.

In fact, though Computex easily had record attendance, the halls were busier on day two than I have ever seen in my 15 years of covering this event; there were relatively few substantive announcements on the PC front. In fact, even the announcements on the data center and ODM side were exceptionally light, largely due to the impacts of supply shortages and the resulting uncertainty that has slammed the brakes on new product development.

Joe Shields: Staff Writer, Components

Three days in, and another day of 90-degree heat. It’s amazing how you can break a sweat here just by walking outside early in the morning. Today’s adventures included floating back and forth between the halls and meeting with several companies. I’ll tell you, if I see another booth with CDUs (Cooling Distribution Units), copper water blocks for AI servers, or PDUs (Power Distribution Units) supporting the AI Data Center boom, I’ll explode.

The highlight of the day has to be my second meal, Mushroom Risotto and Steak. But, because I was so entrenched in work, recovering from a spate of unexpected poor photography on my part that nearly brought my work, well, one article, to a standstill. Afterwards, I just went to bed, physically drained and mentally wiped out. Sleep… Now that’s an escapade.

There’s nothing like crashing when you’re mentally thrashed and waking up a couple of hours later practically wide awake—damn this time change. Tomorrow I’ll be all over the place, with my first meeting at a hotel, two back at the convention center, back to the same hotel for another meeting, and finally back to the convention center again. It’s certainly not the most efficient logistics, but that’s how the cookie crumbles at events like this. The most interesting man in the world says, “Stay thirsty, my friends,” but I’ll say, “Stay hydrated, friends.” One more day to go.

Jake Roach: Senior Analyst, CPUs

Well, I had to open my schedule to find out what I did today in order to write this, so if that’s not a testament to where I’m at in the Computex arc, I don’t know what is. I started my day with my final AMD roundtable of the week, this time focused on ROCm, before taking the MRT down a few stops to Intel’s demo showcase. I met with Dell and Samsung Display in the afternoon, taking a look at the XPS 13 and Samsung Display’s new QD-OLED panels, but much of my day was spent running around to various vendors, chasing down a few key stories (stay tuned on that front).

There are a lot of products at Computex, and it’s impossible to cover them all. But the most interesting conversations happen around the products, not explicitly about them. Although my gung-ho attitude earlier in the week is starting to catch up with me, I’m hitting a sleepy second wind as we close out Computex and start to peel back the curtain on what the broader industry thinks about where things are headed. Also, man, it was hot today.

Jeffrey Kampman: Senior Analyst, Graphics

I began this witheringly hot Wednesday with a surprise trip to the TICC, where Nvidia has set up its enterprise demos for this year, for some quick conversations with the leaders who are guiding the rollout of Vera Rubin and paving the way for the agentic AI future in the data center.

From there, I hopped onto the blessedly air-conditioned MRT and headed back to the Nangang Exhibition Center to criss-cross the show floor and visit some of the biggest booths at the show, including Asus, Asus ROG, MSI, and Gigabyte. And for as tough as it is out there in the consumer PC space, it’s still hard not to feel a sense of awe and wonder when you’re standing in the very center of TaiNEX 1, surrounded by countless thousands of tech enthusiasts and industry professionals, all of them hyped up by the dizzying array of new and sometimes wild stuff on display.

I closed out the day by visiting the fine folks at Noctua with Editor-in-Chief Paul, where we got a thorough deep dive into the company’s obsessively engineered solutions to problems that many PC builders wouldn’t even consider problems. Would any other company contemplate placing a tiny tuned mass damper on top of an all-in-one liquid cooler pump to smooth out its noise signature? Probably not, but Noctua did, and my ears are sensitive enough to this kind of thing for me to be seriously interested. For now, though, I am desperately in need of rest.

With the first few days firmly behind our team on the ground at Computex 2026, Day 2 is the first day that our crew got their boots on the ground on the show floor of the Nanggang Exhibition Center in Taipei, Taiwan. With a busy schedule of meetings, interviews, and presentations in tow, it's been a busy few days, and we're now deep in the throes of covering the event. This series of diaries from our team is intended to give you insights into our thoughts and feelings about covering a massive event like Computex 2026, documenting the trials and tribulations that naturally come with event coverage.

If you've not read them yet, be sure to check out our Day 0 and Day 1 Tom's Hardware Unfiltered blogs to catch up on what they've been up to so far.

Matt Safford: Managing Editor

As I hauled my increasingly complaining body through eight meetings today, I heard a familiar refrain from multiple case and cooler makers: they’re focusing on lower-cost designs (often sub-$100), because they know how cash-strapped gamers and PC builders are, thanks to the ongoing RAM, storage, and GPU pricing crisis. And to be fair, they are trying to sell PC hardware to cash-constrained consumers at perhaps the toughest time for our little hobby/obsession in decades. So, of course, the focus is on lower-cost components and hardware.

Asus, meanwhile, in celebrating the 20th anniversary of its ROG sub-brand, launched an expansive lineup of mostly rehashed Edition 20 products, at some of the highest prices I’ve seen. Take the $599 gaming keyboard, for example, or the $250 mouse. I tested them both, and they’re generally great, with high-end specs and solid performance. But they’re also wildly expensive at a time when key components (not to mention gas and groceries) remain sky-high. It’s easy to call Asus’ Edition 20 launch tone-deaf (did I mention that many of these products feature real gold-plated accents?).

But I can also see why the company (and ROG die-hards) would want to celebrate 20 years of a sub-brand that, let’s face it, has generally offered up high-priced (and generally well-regarded) hardware. But I would love to know how successful the Edition 20 lineup turns out to be, six months or more down the road. Because it’s hard to imagine throngs of people excited to buy a $1,000-plus gaming chair, or the many other high-priced Edition 20 products. But I can certainly imagine lots of people, many of our readers included, looking for a PC component bargain after shelling out for 32GB of RAM or a 2TB SSD at today’s prices. Maybe Asus should start thinking about those kinds of customers, too.

Joe Shields: Staff Writer, Components

Today, Cooler Master HQ was my first stop before heading to the Convention Center and more traditional booth visits. I have to admit, it was a bit overwhelming at first, trying to find my first meeting location and navigating through a sea of people everywhere, but mostly because I left my schedule with all the time and location information back at the hotel (thanks, Jake Roach, for the save!).

It’s very different from CES, where most companies have their own suite or ballroom at one of the Vegas hotels, and it’s a little more private. Outside of that, I had my first taste of 90-plus-degree weather with over 70% humidity. Even walking across the street to the other Hall, I broke a sweat. Oppressive when you’re not used to it. Even though I have almost twice as many meetings tomorrow as today, it doesn’t feel as intimidating after going through it all today, and all but the last meeting are in the same location.

Jake Roach: Senior Analyst, CPUs

I spent yesterday with Intel, so today was spent with the other guys: AMD. I sat in on three roundtables today with AMD’s Rahul Tikoo and David McAfee, discussing everything from the EXPO ULL to AMD’s reaction to the RTX Spark. I also spent some time in an Intel Q&A post-keynote, where I asked the company about its rumored 3D V-Cache competitor, and it gave me the exact answer I expected — “stay tuned.”

Despite being chipper — Paul (Alcorn) even said I looked “peppy” today — I am waiting for my body to crumble in on itself. I am beyond dehydrated. I haven’t been eating anything until the very end of the day, and there are other issues that I will spare you the details of. That’s a problem for future Jake, however. Current Jake is excited to look at chips.

Jeffrey Kampman: Senior Analyst, Graphics

My agenda today was once again dominated by Nvidia. We were back at the Grand HIlai early to attend a press Q&A with an undercaffeinated and punchy Jensen Huang, who was by turns happy to discuss the RTX Spark platform and unhappy with members of the press who failed to ask what he considered to be good questions. After that, we got hands-on time with RTX Spark laptops from five of the six major vendors who will lead the charge when these products come to market this fall, and we picked up some interesting details of those products that have been hard to come by from official channels.

After those briefings, I finally picked up my Computex badge proper and got a bit of floor time at the Nangang Exhibition Center, and I’ll be back tomorrow to visit more booths. The show is truly in full swing now!

Intel launched its Xeon 6+ "Clearwater Forest" processors at Computex 2026 in Taipei, and on Monday, two of the individuals responsible for the product sat down with the press to answer questions. Kira Boyko, Product Line Director for E-Core Xeon Products in Intel's Data Center Group, led the session, which was joined partway through by Tim Wilson, Vice President and General Manager of Intel's Data Center Silicon Engineering group.

Across roughly half an hour, the two addressed why Intel stripped hyper-threading out of its E-core server parts and the technical case for bringing it back, the agentic AI demand surge that has left expensive GPU fleets idling while they wait on CPUs, the deliberate decision to ship Clearwater Forest with only AVX2, and 18A supply so tight that allocating chips between customers is "daily, in some cases."

Diamond Rapids, Intel's next P-core Xeon, drew repeated questions, but Intel deferred any detail, with Evangelista pointing reporters to fuller commentary roughly two months out. That timing lines up with Hot Chips, where Intel is expected to share more on Diamond Rapids.

Clearwater Forest spec changes

Clearwater Forest tops out at 288 Darkmont E-cores per socket and 576MB of L3 cache, and is Intel's first data center CPU built on its 18A process.

Kira Boyko: It's our most performant Xeon on the market today, specifically for scale-out workloads, so it's not just a per-watt angle of fossil performance.

Jake Roach, Tom's Hardware: Was that the driving force behind the big spec changes compared to Sierra Forest? Obviously, it's double the core count, but I think there's over five times the amount of L3, and a huge increase in TDP.

Kira Boyko: The TDP is mostly that it is socket-compatible with the version of platform design that we had for Granite [Rapids]-AP before, and that is a higher-TDP product. Our initial E-core part was lower TDP, and this one has roughly the same range as the Granite version, so that's part of the platform-design alignment. But in general, we found that our customers were mostly targeting higher-TDP spaces anyway for the core density they were after, so it ended up working quite well. We already had a design that served those spaces.

Jake Roach: And the L3, was that another workload type?

Kira Boyko: You're right, a little over 5x increase, from the hundreds up to 576-ish [MB].

Jake Roach: If you have the flagship, that's quite a lot of L3.

Diamond Rapids and hyper-threading

On its recent earnings calls, Intel CEO Lip-Bu Tan has said that moving away from simultaneous multi-threading (SMT) "put us at a competitive disadvantage" and that the company will reintroduce it with the Coral Rapids generation, the P-core Xeon that follows Diamond Rapids. Intel's current shipping E-core Xeons, Sierra Forest and Clearwater Forest, run a single thread per core.

Jake Roach: I appreciate that we can't comment on future products, but there was a tease in the press deck for Diamond Rapids. It's a very anticipated product. I want to ask about hyper-threading. During the last two earnings calls, Lip-Bu Tan has referenced that hyper-threading will return with Coral Rapids. We don't currently have a Xeon P-core product without hyper-threading shipping. Does that mean Diamond Rapids does not have hyper-threading?

Andrew Evangelista: We'll comment more on Diamond Rapids [later].

Kira Boyko: I will say that E-core is single-threaded. It has the core density for the workloads it's servicing, and we are not expecting it to be replaced by Diamond Rapids. We're expecting the workloads that need more of the high-performance aspect of a P-core to go from Granite to Diamond, whereas the more scalar workloads for E-core will stick on Clearwater Forest, continue to be serviced through this next generation, and then pick up with the generation after that.

Andrew Evangelista: I think it was your question that prompted us to talk about Diamond Rapids in general. More to come.

Kira Boyko: The only thing I can really say from a Diamond perspective is AET, the new feature we're introducing on Clearwater Forest. That is expected to roll out across all of our Xeons going forward, so you can expect to see it on Diamond and future ones as well. What the roadmap looks like from a feature perspective gen to gen, I don't have any level of detail for today. But it is definitely being introduced in Clearwater. We have a number of customers deploying it on Clearwater, and others who are more classic P-core customers, with different workloads, running proof-of-concepts on Clearwater so they can hit the ground running with Diamond.

Jake Roach: I had to ask.

Kira Boyko: You're like, "That's not what I wanted, I wanted way more detail."

Jake Roach: There are a lot of articles that have been written saying it's confirmed Diamond does not have hyper-threading, and I haven't been able to find that confirmation anywhere.

Kira Boyko: There's a lot out there on Diamond that is all over the place. There are statements about [unclear] variants, and just a lot of rumors.

Andrew Evangelista: We'll have more official commentary to come, and that's what folks are anticipating. We understand there's excitement, and we'll share more [in two months].

Agentic AI and CPU demand

Journalist 2: What are customers telling you about this agentic AI wave, how they're dealing with it, and how Intel plays into that going forward?

Kira Boyko: Customers are just starting to understand their own AI deployment models, and a lot of them still aren't quite there yet. Many started by investing in GPUs and are now realizing they don't have the CPU counterparts to actually keep those GPUs going. So they made this huge investment, and they're running at something like 20% to 30%, something quite low. They're understanding that there's this space where certain workloads can be offloaded to more efficient CPUs, and that's exciting from a Xeon 6+ standpoint. Others are still going to be partnering with their providers, looking at industry white papers to understand how to best use their AI strategy.

Journalist 2: Just as an outside observer, it seemed like CPU demand was going, and then November and December happened, and everything got sold out instantly. What percent of current demand is agentic-AI-driven versus prior? I'm trying to get a sense of what it is now, and what it's going to be like six to nine months from now. It seems like a paradigm shift happened, and we're going to be riding this trend for several quarters at least.

Kira Boyko: I think we are. I think we're also going to see quite a bit of data center modernization and consolidation, looking at what workloads are already out there that can be consolidated onto CPUs. Some maybe are designed for agentic, maybe aren't, but are more storage-oriented, or workloads that can be serviced just fine on something that isn't super intense. So you can get a little more performance and energy back, and then use that to service some of their AI workloads as well.

Application Energy Telemetry

AET, or Application Energy Telemetry, is a Clearwater Forest feature that gives operators application-level visibility into energy use, which Intel says can be used both to tune workloads and to bill customers on measured rather than estimated consumption.

Jake Roach: You mentioned AET, and I know that's a really big thing with this launch. Is there any connective tissue with what we saw with Arrow Lake Refresh on the consumer front? AET is taking information from actual registers in the silicon. There's hardware on the chips doing it. Similarly, with iBot on Arrow Lake Refresh, it was hardware-enabled, where you could get these readouts running workloads and see where they could optimize. Is there any connective tissue there, or are these completely separate?

Kira Boyko: We can get back to you on whether there's some collaboration. Usually our teams are very separate, but it's very possible there is some, so we'll find out. My understanding is that this is highly customer-driven. Sometimes we leverage existing technologies.

Jake Roach: This is more to satiate my own curiosity.

Andrew Evangelista: Let me grab Tim for a second to answer that, because that's a silicon-engineering-level question. He's worked on both client and enterprise.

Jake Roach: Yeah, just because you're using Darkmont, there's at least a capability there.

Kira Boyko: Touché. Moving on to the next generation, which is not an E-core, it'll still be there as well. So even if there was some synergy, it would be moving forward to a different core base.

Andrew Evangelista: Circling back on two questions. One was similarities related to Arrow Lake.

Jake Roach: Basically, the hooks in Arrow Lake Refresh for iBot to optimize that translation. Are those hardware hooks something you're looking at? Is there any connective tissue there today?

Tim Wilson: I haven't looked at Arrow Lake in quite a while. To first order, I'd say fundamentally no, they're different use cases. Are we leveraging some of the same telemetry capability built into the hardware? It wouldn't surprise me.

SMT removal and its return

Intel split its Xeon 6 line into P-core parts with hyper-threading, such as Granite Rapids, and E-core parts without it, beginning with Sierra Forest.

Andrew Evangelista: The question on the decision for SMT and hyper-threading.

Journalist 2: Just why it was taken out, what the thinking behind that was. Was it a security thing?

Tim Wilson: I have a lot of my own personal thoughts. If you step back to the data center a couple of years ago, the thesis was that what matters is maximum core performance and then core density in the socket. So if I can deliver maximum core performance and increase the number of cores in the socket, do I really need [SMT]? One or two physical cores are always better than two virtual cores built on one physical core. I fully expect we will see use cases and workloads where that decision is incredibly useful and valuable and gives real-world value, and we've heard from some customers that, for what they're doing, single-threaded is the right answer. Having said that, there's a big portion of work that is still very much multi-threaded, especially in the virtualized space, so completely eliminating it is a problem, because we cut off some not-insignificant portion of workloads, especially when you're in a virtualized, licensed environment where licensing is based on cores and threads. So there was a technical reason for why you'd want [SMT], and that technical reason probably still holds. [...]

Journalist 2: Like a VMware thing, with a big price on cores. How are you going to market versus your main rivals, like AMD, and now Nvidia? What's the messaging going forward? From 18A to what's next, you'll be much better on the node side.

Tim Wilson: Our intention is to have leadership products with every generation, and we fully intend to do that going forward. Our go-to-market strategy is to sit down with customers and ask what they value, then go build leadership that meets those needs. With all our data center customers, we have deep discussions around the personality of the platform they want to build, beyond just cores and feeds and speeds. What is the system balance, the memory-to-compute ratio? How are they viewing multi-socket versus single-socket? What's the right number of cores for their workloads, for both private and public workloads, enterprise versus cloud? It's really sitting down in each of those and asking what the markets and customers buying our parts value, and how we optimize our products to meet their needs.

Journalist 2: Is that changing now with this agentic AI demand explosion? Are we going to see CPU racks with agentic AI as the primary use?

Tim Wilson: I'm sure you will, just like we've always built CPU racks. There are principles around CPU design that have always been true and will continue to be true. You want the highest-performance core you can build. Power efficiency is always going to matter as long as we're constrained by the amount of power you can bring inside a building's walls and the heat you can extract from them. Your memory-to-CPU harmonics, how much memory each workload takes, how much you allocate to each core, those are key. We've always designed for those parameters, and the end markets evolve over time.

Agentic AI is now exploding, but what's driving that explosion is not a new type of CPU. It's that the new AI workloads are not one call, one inference, one response. They're complex, execution-driven, multi-task queries that involve tens or hundreds of agents, and suddenly you need a control plane and an orchestrator, tasks the CPU is historically good at. How do I take a complex task and decompose it into subcomponents, figure out which can be parallelized and which depend on each other and need to be serialized, and pass those off to the GPU? I have to map memory to each of those subcomponents, and not all of them want the same memory, and I have to make calls to I/O, and in some cases to the OS or APIs.

Those are all things the control plane and orchestrator, the CPU, does really well. As you move away from a chatbot answer to "go do this analysis and give me a report on the actions I should take," that's a much different query, and the CPU plays a much bigger role. Data centers that have built on GPUs for the last three years are suddenly finding they're bottlenecked by the CPU. They have a massive GPU fleet that costs billions of dollars sitting idle, waiting for the CPU to respond. So do I see a future with agentic AI and CPU racks? Yes, but with characteristics very similar to the sorts of things we've always built into CPU racks. It's exploding because the things the CPU has always done well are the things in demand now.

Journalist 2: It seems like the whole storage infrastructure has to change, too.

Tim Wilson: That comes along with it. There's demand for storage, which drives I/O advancements and connectivity.

18A yield and wafer allocation

Clearwater Forest is a multi-process design: the compute tiles are built on Intel's 18A node, with base tiles on Intel 3 and I/O tiles on Intel 7.

Journalist 2: Questions you probably want to ask but won't answer. 18A yield volume for Xeon 6+, progressing?

Kira Boyko: We're ramping well. We have strong demand throughout the lifetime of the product, and we're working from a capacity standpoint across all of our products to hit customers at the point in time they need most. Compute is 18A, but we also have base on Intel 3 and I/O on Intel 7, so it's a multi-process product. We're mapping demand against all of our other products to figure out where we need to build.

Journalist 2: How do you choose who gets the product in this compute-supply-constrained world? Is it whoever orders first? You're sold out right now.

Tim Wilson: We give as many CPUs to as many people as we can. It tends to be more business decisions than engineering decisions, so it's a combination of long-term deals and customer relationships. The biggest problem is not demand in any way, shape, or form. The biggest problem is how we satisfy demand across every single product. If I have people demanding Xeon 6 and Xeon 6+, and still Xeon 5, how do I balance all of those and match where the supply constraints are in the industry? In some cases, customers are struggling with mismatches. They can get the GPU but not the memory to pair with it, or the memory but not the CPU. There's a lot of matching going on in the industry.

Journalist 2: On the client side, people are demanding even older products because they've already verified them.

Kira Boyko: I've seen that on the data center side, too. They've verified and tested a product, so they want that product. In such a supply-constrained environment, people will buy whatever’s on the table. And 6+ has the benefit of some backward-compatibility elements, the socket compatibility, and again, using processes that are hardened on previous products, so we can mix and match in some cases. We have customers looking for multiple products on multiple processes, and it's working with them to understand exactly what they critically need, when, and how we best service that across all their orders.

Jake Roach: If I'm remembering correctly, it was the earnings call before the most recent one, where we talked about wafer allocation split between client and data center, with a greater emphasis on wafers going toward the data center. Is that still the plan?

Tim Wilson: That's definitely the plan, and we're always having those conversations. That's more of a foundry conversation than a product conversation. [...] The whole ecosystem is sucking up all the wafers and memory, whether it's client, automotive, or any of the other industries. AI data center tends to take the supply because they're willing to pay the most, and the rest of the industries can't pay the price until supply balances out. We saw a similar effect during COVID, though that was supply-chain-driven rather than demand-driven. Those trade-offs, Gen 5 versus Gen 6 versus Gen 7, are a weekly conversation.

Kira Boyko: Daily, in some cases, on CPU allocations. [...] Given the dynamic space, our customers are modifying on a regular basis. Can we shift? What do they really need, and when? If you're asking long-term whether we'll stay in these constraints, we do see a space where things will lighten up. It's not in the immediate timeframe.

Journalist 2: Dave talked about multi-year hyperscaler contracts. What's the latest on that? Are deals getting signed, and are you getting more requests for those kinds of contracts?

Tim Wilson: I doubt either of us is the right person, by the way. They don't trust us with a lot of that information.

Journalist 2: You're not talking with data center customers on the purchase side?

Kira Boyko: We're not in the contract negotiation.

Tim Wilson: There's a principle here. If you mix commercial negotiations in with the technical discussions, it doesn't work out well, so you generally try to separate them. You let the finance people argue over pricing and contracts, and let the engineers figure out the best products to build together. When you're talking with product-side engineers, we don't have a lot of that information, and even if we did, we probably couldn't tell you.

Journalist 2: What percentage of Intel's data center revenue is hyperscaler?

Tim Wilson: You can go look at our earnings.

[Session ends]

If you take a look at Tom's Hardware this week, you might recognize that we've been posting many reports directly from the ground at Computex 2026 in Taipei, Taiwan. This year, we're offering readers a chance to take a look at how we're coping amid the sweltering Taipei heat and telling you exactly what we've been up to each day.

While new announcements (and a lot of writing) are part of the overall Computex experience, we hope you enjoy this series of blog posts from our team on the ground. If you haven't caught up on our Day 0 post, be sure to check it out first. With the busier trade show days looming, Tom's Hardware's fearsome five marches on into the depths of the Nanggang Exhibition Center and beyond.

Paul Alcorn: Editor-in-Chief

The pace of the show is quickening as we get closer to the first day of the show floor opening, which occurs tomorrow. Today found me scrambling after the Nvidia keynote to make it to the Qualcomm keynote, and then the following press question and answer session. Qualcomm really didn’t bring many new announcements to the show, so there weren’t any terribly big news gems to be found. My marathon demo run through Nvidia’s suite, which took two hours, was a lot more interesting as the company demoed a seemingly unending string of gaming and AI demos, with most of those powered by the new Microsoft Surface powered by RTX Spark. In the end, I ended up back at the hotel at 10 pm for some rest before a 7:30 am question and answer session with CEO Jensen Huang tomorrow.

Matt Safford: Managing Editor

I spent the early morning writing, before grabbing Mos Burger for breakfast and heading to the Nangang Exhibition Center (Computex HQ) to pick up my badge and take more photos for daily wrapups and our Best Of story. After showing our Computex rookie Joe Shields around a bit, we headed to Gigabyte's Computex kickoff, where the company showed off many things, including, most notably, the X870E Aorus Infinity Next, a motherboard wrapped in 3D-printed metal.

We were told that just the production and materials of this board cost thousands of dollars, so it won't be making it into your next build (unless maybe you're a billionaire), but it is interesting to see Gigabyte push the boundaries of what is possible.

Joe Shields: Staff Writer, Components

I have to talk about the night market I went to last night first. There was so much to see and even more to eat! So many different foods and vendors selling wares, carnival-style games, and there were a lot of people. I ate a pork pepper bun, fried prawns (would recommend both), and what was supposed to be a brisket burger that I think ended up being chicken sausage. Getting there (and around in general) on the subway was a lot easier than I expected, as most signs/announcements had an English translation and were color-coded.

Today was a day of unrest before the storm, with two events in the late afternoon, including one with Gigabyte, who showed off a lot of cool goodies, including the X870E Infinity Next with its metal 3D printed heatsinks — the star of the show for me so far. At this point, I’m sleepy, as the dramatic 12-hour time change has finally caught up to me. Tomorrow, the fun really begins, starting with a visit to Cooler Master HQ and then to the convention center and booth hopping for the rest of the day.

Jake Roach: Senior Analyst, CPUs

Day one of Computex is down, and it was a busy one (a sign of things to come). I started my day chatting with Intel’s Nish Neelalojanan about a broad range of consumer topics, and we’ll be rolling out some choice quotes from that interview over the coming days (the first is already live). After some time at the Qualcomm keynote, I went back over to Intel to talk Xeon 6+ and the company’s new Arc G3 Extreme.

It’s hard to overstate just how convenient Taipei is when it comes to darting around the city like this. The MRT (train) is fast, cheap, and always on time, allowing me to get around to various places while (mostly) avoiding the Taiwan heat and endless Uber bills.

Today was Intel, tomorrow is AMD. We have a series of roundtable interviews set up, so hopefully we’ll get some more interesting insights into where the x86 gang stands, especially in the face of the RTX Spark announcement from Nvidia.

Jeffrey Kampman: Senior Analyst, Graphics

Today was all about Nvidia for me, from early morning until late at night. In the morning, I joined the throngs of GTC Taipei conference-goers to hear CEO Jensen Huang talk about the company’s continuing full-court press for the data center with Vera Rubin.

We also finally learned all the juicy details of the RTX Spark platform (aka N1) and the company’s considerable efforts to spark a Windows on Arm revolution across hardware, operating system, and software. Even if you’re skeptical about Nvidia’s agentic AI vision for the future of personal computing, it’s impressive that it’s gotten everybody who needs to be on board for a seamless Windows on Arm experience on board, and the platform already feels quite mature. We’ll be spending more time with Nvidia tomorrow between a Jensen Huang Q&A and more hands-on opportunities with RTX Spark.

Intel’s Arc G3 chips are gunning for the AMD-dominated, high-tier integrated graphics market that has become such an important enabler of the modern handheld PC gaming experience. But as high-memory prices push up the costs of even entry-level discrete GPUs, there could be much more of a place for powerful onboard graphics in the PC gaming landscape in the years to come.

We sat down with Intel’s Senior Director of Product Management, Nish Neelalojanan, in Taipei, Taiwan, at Computex 2026 to talk more about the G3’s development and how it fits into Intel’s lineup. Here, we're presenting the full transcript of our conversation.

This transcript has been lightly edited for clarity.

Jake Roach, Tom's Hardware: So what was the idea behind the G3, because you guys have tried before, right? I believe it was with MSI? And now you’re putting a bigger emphasis behind it with a whole new branding.

Nish Neelalojanan, Director of Product Management, Intel: It was a combination of two things. So first of all, we started trying already with Meteor Lake, and yes, we were experimenting. This was all standard off-the-shelf parts, and we learned a lot as we came into Lunar Lake. The power management for handheld needed to be more customized, so we started tweaking further, and as we got into Panther Lake, the architecture lent itself to lower power gaming. We moved the E-Cores onto the performance cluster, so you have E-Cores both on your efficiency island and your performance cluster, that means your E-Cores have access to L3 cache, so E-Cores are now performant enough to run games.

A lot of the time, in a low-power scenario, you are more GPU-bound than CPU-bound because the GPU is power starved, so if you can reduce the power on CPU and dump it on the GPU, you'll get much better performance. So, with that architecture change with Panther Lake, now is the perfect time. All the goodness we've learned, we can capitalize on it. We have a silicon architecture, we can lend itself to low power, and we have big enough graphics now…

Jake Roach: A really impressive iGPU.

Nish Neelalojanan: So, that is what had the impetus on, hey, what if we did a CPU line, which is graphics first, or leading with a very big graphics, but small enough CPU that doesn't grab enough power, but good enough to run all your handheld games. It's great for handheld gaming or non-PC form factor, running low-power gaming. So we wanted to start a line of products, which would be integrated graphics forward, with the right CPU.

Jake Roach: And these are wholly unique entries, right? If I remember correctly, there's no 14-core Panther Lake.

Nish Neelalojanan: These are completely unique chips. So they are based off the same die, but we've optimized it with, like I said, core count, so that taking two P-Cores off, because most of the games are going to run on the E-Cores on the performance cluster, you also cut down on different I/Os, so you don't need as many ports on a handheld as you would need on a laptop, right, so you cut down, so it's cutting down all the things you don't need.

Jake Roach: Really focusing it on that form factor.

Nish Neelalojanan: Yeah, that will be on the hardware, and then software-wise, we have a lot of other software optimization. So, now in order to have them pinned onto the E-Core, we have a BIOS control optimizer, so extra ways to have your thread director direct your game threads onto your E-Cores.

It's basically making sure we are directing the game threads onto the E-Core. [We also have the] ability to do power gating, so that we have features like endurance gaming, which we had on the laptops. Now, for handheld, we've added some features, so you can go with different presets. You can say, I want 60 frames per second, and then it will optimize your profile accordingly, or I want 30 frames per second. So you have a frame cap, and then your SOC resourcing is optimized, so that you will increase your battery life 2, 3, 4, hours.

Jake Roach: Battery life is so important for a handheld, right? I was playing a little Forza Horizon 6 on the plane coming over, and one way that I'm doing that right now on Linux is with Lossless Scaling, with frame generation in any game. As you're saying, apply that 30 fps cap frame generation to the mix, and you can get really good perceived performance.

Right now, you guys have multi-frame generation through XeSS 3 through specific games, but there's no driver. Is that something you're looking into, given how important that can be for the local gaming experience?

Nish Neelalojanan: So, 100 plus games have already enabled MFG, but you could imagine, as you said, it's important. So we're exploring, but as we get closer, we'll talk more about when and where it intercepts.

Jake Roach: The other thing I did want to ask about was form factors, which is something you kind of hinted at. Right now, with component prices being so high on just a typical DIY PC, we're seeing a really big push for budget laptops for people that maybe don't need as big of graphics and handhelds for people that really care about gaming as a laptop replacement. I'm just curious, kind of broadly, what you think about the dynamics between these form factors? Is this something that is just a temporary market connection, given that prices are so expensive, and are you planning around that, or is it something more long-term? Where do you think these are going to be the preferred form factors?

Nish Neelalojanan: I think, from a budget-conscious perspective of value buyers, our core 300 series, I think probably this is the first time in a long time the mainstream is getting some of the new ideas, right? So, today if you take a value-conscious segment in the past, it was always, hey, you have the big innovation, which we launched, it gets waterfall down. But as the innovation started getting expensive more and more, that waterfall did not happen, it was basically take the old chip, do some minor updates. So we wanted to take all these new like battery life performance uplifts, and you know, having the new AI updates, all of that, but to be able to be affordable, that's what is Wildcat Lake, or Core 300 series. So that's kind of for the budget-conscious buyer, we wanted to make sure we put some new IPs out there, because I don't think anyone is putting that out.

So that's part A. Part B of your question is handheld as a form factor. I think handheld as a form factor is interesting. Different people are trying to do multipurpose use, so would it ever go from companion to main? TBD. But can it expand its use cases from, hey, can I have a handheld, can I have a docked experience? I think long-term, yes. Currently, the software interfaces and a lot of the, let's say, ecosystem around it needs to evolve for it to be meaningful, but there's a lot of experimentation around dock experiences and stuff, which we are working with partners to experiment, but as it stands, I think handheld alone as it's gaming first.

A lot of our partners are experimenting; they're having all those capabilities available. How can you dock, how can you connect keyboard and mouse directly, and then be able to do it, because, like you said, costs are going up. If someone buys this, they want to be maximizing it.

Arrow Lake refresh's positioning

Jake Roach You touched on Wildcat Lake in the mobile segment, and recently we had Arrow Lake refresh, which was a really big readjustment in pricing. In particular, I'm just kind of curious to get more color on that, because when I reviewed those chips, I the expectations, I was briefed on them, and I was like, I know what to expect, but it was a very different Intel than I was used to working with on the desktop run.

Nish Neelalojanan: Short answer would be, we wanted to make sure we are putting out things which gamers would care about and show that we care about gamers, so this was an attempt or step one in getting to that expectation, right? And then obviously same thing with handhelds, making sure we are putting something which the gamers would want, so that's the highest level.

Jake Roach: I mean, again, seeing the results, we've essentially made the original Arrow Lake line outside of a few chips, irrelevant with these two chips. The 270K Plus scales above 285k and 250K can go toe to toe with either the Core Seven or Five.

Nish Neelalojanan: That’s a good thing, right?

Jake Roach: That is a good thing, but it's a good thing for us. It is not a good thing for Intel, right? Like, internally, that undermines your own product. And so I'm curious about the decision there, because at some point you had to have had pushback on, hey, this $300 Core 7 is going to undermine our $600 Core 9 flagship.

Nish Neelalojanan: It was just a decision made with end users in mind, and we want to make sure we are providing value as we come out, and if at all we need to start somewhere, right? And in terms of desktop, that was an effort to let's go with value focus first, and that will help us then gain confidence. From an enthusiast perspective, we needed to build back our reputation. I am sure you would agree with that, and this was, we’re making sure we are providing value to the gamers, and we start with Arrow Lake Refresh, and we have a very strong roadmap to come, so we want to continue.

Jake Roach: It did seem like an appetizer, almost, given you know everything that happened with Arrow Lake, and yeah, I appreciate you wearing that a little bit, because those were again, they were very interesting parts for a number of reasons.

Nish Neelalojanan: Savior [Kim, Intel Director of Client Communications] can correct me if I said something I shouldn't, but that was kind of highest level.

Leaving Hyper-threading behind

Jake Roach: Another question I had; This is more on the mobile side of things, or SoC side of things, is around hyper threading. So I have this question for the Xeon folks that I'm meeting with later today, because there have been comments in the financial reports, comments about returning hyper threading to the data center, whole lot of stuff around that on the consumer side of things. You guys left hyper threading behind with Arrow Lake. I'm wondering now that we have a desktop generation, a mobile generation under your belt. What do you see with that move to get rid of hyper-threading? And is there any consideration for maybe going back to some form of SMT in the future?

Nish Neelalojanan: Highest level, our decisions are always are we getting the right level of performance. The best way to achieve that performance is what we want to go with. Like you said before, with Arrow Lake Refresh, you're not only getting the right game performance at the right price point, but you're also getting almost 2x multi-threaded performance compared to competition, right? So, if you can deliver that without SMT, though the end user, it doesn't matter to the end user. In fact, you're actually getting even better multi-threaded performance because they're actual physical codes versus virtual threads, right? So that's where I would leave it at. We always reevaluate, but it's the best way to give that level of performance in that given price band or that given SKU. So we continue to keep re-evaluating, and different segments may need different things.

Jake Roach: Right now it sounds like it's working out well?

Nish Neelalojanan: Yeah, and like in terms of all the different agentic AI workloads, you need CPU as an orchestrator, having nth number of threads, cleaning up data, lining up a memory, a lot of threads help. So, like I said, when there is utility, and when there is a need, we will constantly evaluate it's, it's rigid to say, oh, it's behind us, or it's rigid to say, oh, we are going to run towards it: If it makes sense, it makes sense, yes. That’s where the data center decision is. They talk more about the growing workload, there is a need.

Jake Roach: It has been interesting. We're coming up at Tom's Hardware on 30 years, and we did a retrospective on CPUs, so I went back to the very first Pentium Two review on Tom's Hardware, and seeing the hyper-threading, and how it was used over decades, it was really fascinating to look at.

Nish Neelalojanan: A lot of the low-power segments, like now, handheld, yes? Those eight E-Cores on that performance cluster are significantly helping with all the low-power gaming, right? So, a lot of these decisions are paying off as it stands. As the workload evolves, as we evolve into different architectures, we will have to evaluate based on at that time what would be the right decision. Okay.

Jake Roach: For years now, Intel Foundry has laid out a really aggressive foundry roadmap. We saw 18A first and now we finally have 18A in data center with Xeon Six Plus. Is that the kind of the cadence we should expect going forward for Intel's cutting-edge hooks to see them debut first on the consumer front?

Nish Neelalojanan: It's the same answer I said before wherever it makes sense first. So we've got especially a lot of our consumer client CPUs, we pick the right process node, which made sense for the right tile, especially now we have multi-chip solution. It gives us the flexibility to pick and choose the right process node for cost, readiness, optimizing for R&D, because sometimes you won't have that IP on a different process, so it's easier to just reuse it, based on availability. Sometimes it's costing some bigger tiles, you can put it on latest and get it to get performance. Some of the tiles where you don't need to push frequency as much, you put it on an older node. And now with all the supply in and around the industry, picking the right process nodes, which is more available, is also going to be important. So we always go through all of these considerations and pick and choose, so there is no settling on client will start data center will follow, vice versa. It's we pick the right process choice based on that architecture, for that side.

Reacting to Nvidia's RTX Spark

Jake Roach: I want to get your reaction to [Nvidia’s RTX Spark]. If you need any better reminder that Twitter is not real life, there's a lot of talk on Twitter that Nvidia entering this market completely decimates and it rules everything. I don't think that's true, but I want to see your reaction to Nvidia getting into that space.

Nish Neelalojanan: I mean, Nvidia puts out great products, and they know how to do gaming. They know how to do all these different things. So we always take everything with a healthy dose of paranoia, but we are also very, very confident with our products, in the sense that X86… Let me put it this way, when we entered this discrete graphics business, our graphics business, it took a painful few years for us to work through all the drivers, all the compatibility issues, and everything ironed out, same thing goes on when an ARM CPU enters a market that's going to be tons of compatibility DRM issues, backward compatibility As a result, we are very confident that we have the right CPU, GPU mix for clients, both for gaming and when it comes to what you call AI inference workloads.

That said, Nvidia is a great partner. We will continue to work with them. You saw some of our announcements. We have some longer-term commitments with them, so both of us have different parts of the roadmap that we will expand together, where there'll be a roadmap where we will be partnering, and where there might be places where we will be competing, but I think it's great for the industry that there is different choices.

Jake Roach: I know, it's a weird situation, especially for Intel, because you guys, you guys do work with Nvidia. Yeah, when I pose similar questions to the other guys, they, they're a little bit more fiery in their responses.

Nish Neelalojanan: Compatibility is going to be a key thing there. x86 on the CPU side is going to have a lot of advantages. We talked about some of the new instruction sets, which got announced by the x86 Consortium, a lot of those lend itself as much to gaming as much as AI, and you'll see a lot of that being talked about more.

A lot of it were agentic AI examples and stuff, because you have to say AI three times before you can talk about anything else, but they also help with gaming significantly, so yeah, it doubles the amount of registers, which you would execute one instruction, so it's based off of AVX, but there’s a few others which came out with it.

The health of the consumer PC market

Jake Roach: Finally I want your reaction more broadly to the PC market right now, because we have all the rising component prices, we have very expensive laptops. On the desktop, it's really, really hard to build a PC right now. I think motherboard sales are down some 30-40% I know you're releasing products to address that market between Wildcat Lake and Arrow Lake pretty refresh, but I kind of want to see your reaction to how that pans out over the next maybe three to five years. Is it a continual area of focus, or is it something that hopefully we're just dealing with over the next few years, where we're really focusing on the budget segment?

Nish Neelalojanan: Large memory is completely overshadowing any CPU prices, right? Memory and storage. The CPU is not anymore determining your system price point, and when you're paying that amount, people will obviously start upgrading. Now, that said, there are still Panther Lake systems you can get below $1,500 out there, right? It's going to be dependent on OEM. It's going to be dependent on markets, and even the Wildcat Lake, they'll announce a $599 starting price point. Yeah, so there are definitely designs which are coming at comparatively reasonable price points, which are available, and longer term, I think something has to give right. The over inflation, we will have to keep an eye, but if I could predict the memory market, I would be rich in stock!

Jake Roach: Let me phrase the question a little bit better, because are you making plans for a longer term, a longer term squeeze on the consumer front, because surely you're going to have to make those plans if you see the headwinds going that way.

Nish Neelalojanan: We do have products with support for DDR4 both on desktop and mobile, so Raptor Lake, you're not end of life in any of them, they're there. We'll continue to make sure that there are products which can take care of older memory technologies if they're available and cheap. Second thing is, we are making sure we are validating lower configs as well. Wildcat Lake starts at 8GB, Wildcat Lake is a single channel product, so there are products which can leverage with low memory and give reasonably good performance, so we are doing everything we can from our perspective to be able to help in any small way. But like I said, when CPU becomes the least relevant from an overall BOM (Bill of Materials) perspective, because it's so expensive. Then we also have CPUs you can buy out into that.

Jake Roach: Speaking of memory, I don't know if you had any involvement with half ranked? Is that what they call them, half ranked DIMMs from ASRock? It was with ASRock and Intel.

Nish Neelalojanan: I am not familiar with that, but we are working with a lot of indigenous memory suppliers to validate them, so we’re doing everything we can in terms of it's not just one, two, or three. If there are some local specific memory vendors, but like in PRC, and now Indonesia is even bringing up a couple of them. We're trying to validate as much as we can, so there's enough choice that people can get pockets of relief. Right? We are looking at UFS for a longer-term horizon, so that every little thing helps, right?

Jake Roach: Absolutely. I appreciate you taking the time and talking over everything. I'm very excited to see the G3 chips in action. I saw them yesterday at the Acer showcase, and I played a little bit of Forza Horizon 6, and these are pretty good.

Nish Neelalojanan: With G3 at least we're putting out some latest and greatest stuff, and in terms of a lot of these, it's not necessarily exclusive. We're broadly available, the 12 Xe on the PC side, and on the handheld, it's not like limited to one OEM. Unlike some people who hold it back, just only give it to one OEM.

Jake Roach: So all these handhelds, I believe all the ones that announced are all Windows-based handhelds. Is there consideration for Linux? How much consideration or weight do you put on that, given things like Steam OS proper?

Nish Neelalojanan: So highest level stuff we announced now is Windows based, but you can take those devices and install… and I'm sure you would imagine we would continuously want to make sure that those experiences are reasonable for end users, and we are, we would talk more about as we get closer to something, but we are exploring beyond Windows, and as we get closer, we'll talk more about.

[Session ends]

Tom's Hardware has covered hundreds of press events, and for a long time, you've always seen the finished product. You've always seen the dizzying number of articles coming from events. But what is it really like to cover Computex 2026?

Our staff on the ground are peeling back the curtain to offer you unprecedented insight into how the proverbial sausage is made. Tom's Hardware Unfiltered: From travel to urgently dashing around Taipei, and of course, quick thoughts about the things that we're seeing directly from the show. After each day, we're compiling our thoughts on what we've seen, including any trials and tribulations we've faced amid our incredibly busy schedules.

The show hasn't even kicked off, and there's still a slew of news to get through, so be sure to check out the fruits of our labor. With all that said and done, it's time to kick things off with Day 0 of our War Room dispatch.

Paul Alcorn: Editor-in-Chief

I arrived in Taipei in the blistering heat after three flights and 22 hours in transit, a grueling trip as usual, but luckily, I arrived in the evening and had no appointments. After a half-decent night’s sleep, I headed to the Acer demos to check out their new Intel G3 Extreme-powered handheld and dig up some new info on Qualcomm’s Snapdragon C platform. Acer had the laptop dutifully locked behind glass to keep curious press away from toying with the system, but I happened upon a demo unit that a Qualcomm rep was showing around. A few seconds later, and I had the Windows Task Manager open to peep the unreleased info on the eight-core CPU and its GPU. I’ll be writing up those details tonight as I wait for Nvidia’s pre-brief, which is inconveniently scheduled for 12:30 am Taipei time. That’s going to make for a long day tomorrow.

Joe Shields: Staff Writer, Components

I arrived in Taiwan around 05:40 AM on Sunday after a 17-hour flight from Ohio (five to Seattle, 12-plus to Taipei. Flying that long and being stuck inside a cigar tube, a large one at least, was better than expected, but it’s still an incredibly long flight. Traveling from the airport to the hotel by train (MRT) was easy (most signs have English writing!) and offered great views of Taipei along the way. Even though Computex hasn’t officially started, I have a meeting with Asus this afternoon, with most meetings and roundtables running Tuesday through Thursday. I’m looking forward to sleeping and heading to one of the many night markets (Shilin, one of the largest) to check out the local wares and try new foods before things get hectic later in the week.

Jake Roach: Senior Analyst, CPUs

The first day of Computex is all about getting ready for the rest of the week. My travel day was some 20 hours, leaving in the evening on Friday and arriving after 4 AM on Sunday in Taiwan (the time travel is a trip). After getting off the flight and taking a quick shower (important), I grabbed my MRT pass for the week and my badge. It’s about a 13-hour time difference for me in Taiwan, so I spent most of the day trying to get on a decent schedule so I can be ready to go when the event kicks off properly tomorrow. I was able to get my hands on the Acer Predator Atlas 8, one of the handhelds with Intel’s new G3 Extreme chip, and it’s pretty impressive. 60 fps at 1080p with High settings and no upscaling in Forza Horizon 6 is no joke.

Matt Safford: Managing Editor

After more than 20 hours of travel, my first day in Taipei started with debit card complications and was punctuated by some brief hands-on time with Acer’s Intel G3 Extreme-powered Predator Atlas 8 and Aspire Go 15. Both are interesting, but just how interesting depends on two key things we don’t know yet: performance and price. After Acer, I visited the Guanghua Digital Plaza neighborhood to grab some general photos for Computex blogs and daily announcement wrapups. Between searching for an ATM that worked with my card and walking between Taipei Metro stops, I walked nearly 13 miles, drank more iced coffees than I can count, and I am very happy to let exhaustion take me into the arms of tomorrow.

Jeffrey Kampman: Senior Analyst, Graphics

My travel to Taiwan was one of the smoothest and most comfortable international flights I’ve ever had (thanks to the quiet engines and relatively humid cabin of the Boeing 787), so I was able to get plenty of rest before arriving at 5 AM local time. I immediately set up shop in a Starbucks near my hotel to hammer away at an embargoed review for a few hours before migrating back to my hotel room as soon as it was ready so I could shower, nap, and continue that work. I was glad for the jet-lag-incurred naps, as our Nvidia pre-brief ran from 12:30 AM to 1:30 AM Monday morning prior to Jensen Huang’s keynote at 11. No rest for the weary…

In a world where nobody is launching truly new graphics cards, my Computex week will almost certainly be defined by data center products, integrated graphics processors, and AI accelerators of various shapes and sizes. Intel has already taken the wraps off its Arc G3 handheld platform, and rumors around Nvidia’s N1X and N1 platforms are as thick as the humidity here. If those launches come to pass, we’ll be looking at a very different consumer PC and mobile graphics landscape after this week.

I haven’t been back to Taiwan for over five years at this point, so I’m excited to see what’s the same and what’s changed since my last Computex.

While the show has yet to officially start, our team on the ground will be keeping you up-to-date with everything they're up to this week. Needless to say, things are very busy, so stay locked in on Tom's Hardware Unfiltered tomorrow for our next update.

The global foundry market is dominated by TSMC, which captured 69.9% of global foundry revenue in 2025, but beyond the glitz and glamor of the leading edge sit a tier of foundries that collectively manufacture the chips found in cars, power supplies for AI servers, RF front-end modules, display drivers, industrial controllers, and defense systems. GlobalFoundries, UMC, and SMIC posted a combined 2025 revenue of roughly $24 billion and hold approximately 13.5% of the global foundry market between them.

Each is pursuing a fundamentally different strategy shaped by geography, regulation, and technology choices. GlobalFoundries is becoming a U.S. and European specialty foundry, backed by $1.575 billion in CHIPS Act funding and a $3.1 billion Department of Defense contract.

Meanwhile, UMC is bridging from pure mature-node services into 12nm FinFET territory through a manufacturing partnership with Intel, and SMIC is China's de facto national champion, expanding mature-node capacity at enormous scale while pushing the limits of what DUV lithography can achieve under tightening export controls. We break down each of these trailing-edge foundries to see what might be coming up next.

GlobalFoundries

GlobalFoundries (‘GF’) exited leading-edge development in 2018 when it canceled its 7nm program and has since repositioned as a specialty foundry focused on differentiated process platforms. That strategy produced FY2025 revenue of $6.79 billion (up 1% year-over-year), with Q4 gross margin of 27.8% and full-year operating cash flow of $1.73 billion. The company's automotive segment hit a record $1.4 billion, up 17% year-over-year, according to its SEC filing.

Its current node portfolio runs from 12LP FinFET down to 180nm and spans several specialty platforms. The company's flagship is 22FDX, a 22nm fully depleted silicon-on-insulator (FD-SOI) process targeting ultra-low-power IoT, automotive radar, millimeter-wave 5G, and microcontrollers with embedded MRAM support. Meanwhile, 45RFSOI is the dominant global platform for 5G RF front-end modules. Below those sit 28nm, 40nm, and 55nm logic nodes, alongside BCD for power management, SiGe BiCMOS for high-frequency analog, and a ramping GaN-on-silicon platform at its Vermont facility.

Two recent acquisitions, however, have expanded GF beyond pure-play manufacturing. It bought Singapore-based Advanced Micro Foundry last year, making it one of the world's largest silicon photonics foundries, and acquired MIPS (for RISC-V CPU and AI inference IP) along with Synopsys' ARC and RISC-V processor IP portfolio. The company now offers customers pre-built compute IP alongside fabrication, a model no other trailing-edge foundry currently can.

GF operates five manufacturing sites. Fab 8 in Malta, New York, is its most advanced 300mm facility and holds Trusted Foundry Category 1A accreditation from the U.S. Department of Defense. A new fab at the Malta site, funded partly by a $1.587 billion CHIPS Act award, will triple the site's capacity over the next decade as part of a $16 billion, 10-year U.S. investment plan.

Fab 1 in Dresden is Europe's largest semiconductor fab, with a €1.1 billion expansion underway to push output toward 1.5 million wafers per year by the end of 2028. Fab 7 in Singapore opened in September 2023 after a $4 billion build-out, adding 450,000 wafers per year. The two remaining sites are both 200mm facilities in the U.S.: Fab 9 in Burlington, Vermont, which is targeted for the company's first high-volume GaN production line.

The company's 2026 capital expenditure guidance of 15% to 20% of revenue represents a sharp jump from 8% in 2025, driven by what management described as oversubscribed demand in silicon photonics, 22FDX, and SiGe. That investment will compress free cash flow margins in the near term, but GF has said customer prepayments and long-term agreements underpin spending.

Reports surfaced in 2025 of an internal assessment dubbed "Project Ultron" exploring a potential takeover of UMC that would create a mature-node foundry with roughly 28% combined market share. UMC denied active merger talks, and, in any case, the regulatory barriers across Taiwan, China, and the U.S. are more than likely insurmountable.

UMC

UMC reported Q1 2026 revenue of NT$61.04 billion (approximately $1.93 billion), with net income surging 107.9% year-over-year to NT$16.17 billion. Gross margin was 29.2% and capacity utilization stood at 79%, with Q2 guided to the low-80% range and wafer shipments expected to rise by high single-digit percentages.

The 22nm node is UMC's primary growth driver. Revenue from 22nm grew 93% year-over-year in 2025 and now accounts for 14% of total revenue, up from single digits the prior year. Combined, 22nm and 28nm represent 34% to 36% of quarterly wafer revenue.

UMC dominates small-panel display driver IC (DDIC) production at 28nm, holding over 90% market share in that segment, and launched an advanced 22nm embedded high-voltage (eHV) platform in 2024, targeting next-generation smartphone OLED displays. Specialty processes extend across embedded non-volatile memory (eFlash from 350nm to 28nm), RFSOI, RF CMOS, and BCD for analog and power applications down to 55nm.

UMC operates 12 fabs with combined capacity exceeding 400,000 12-inch-equivalent wafers per month. The newest, Fab 12i Phase 3 in Singapore, opened in April last year after a $5 billion investment and will start 22/28nm volume production this year, with an initial capacity of 30,000 wafer starts per month and with space reserved for a second phase.

The most significant item on UMC's roadmap is its 12nm FinFET node, co-developed with Intel and targeted for mass production in 2027 at Intel's fabs in Chandler, Arizona. The process offers 10% higher performance, 20% lower power, and roughly 10% area reduction compared with UMC's existing 14FFC, with three fewer mask layers.

UMC's CFO Chi-Tung Liu confirmed last May that the majority of UMC's R&D spending is now directed at this node. The partnership gives UMC its first U.S. manufacturing footprint and a FinFET node at scale, while Intel gains mature-node foundry volume through what are largely depreciated fabs.

SMIC

SMIC posted record full-year 2025 revenue of $9.33 billion, up 16.2% year-over-year, according to the company's annual results. Full-year utilization averaged 93.5%, a jump of eight percentage points from 2024, and wafer shipments rose 20.9% to roughly 9.7 million 8-inch-equivalent wafers.

Annual capex, meanwhile, ran at over $7 billion, reflecting an aggressive capacity build-out that is compressing margins: full-year gross margin was 21%, and the company guided Q4 2025 gross margin to 18% to 20% as depreciation from new fabs weighed on profitability even at near-full loading.

SMIC's production stack officially spans 350nm to 7nm, but the vast majority of output sits at 28nm and above. 28nm HKMG and PolySiON variants serve smartphones, networking, and DDICs. Nodes from 40nm through 180nm cover analog, power management, RF, image sensors, and microcontrollers.

At the advanced end, SMIC's N+2 process (7nm-class) is in production for Huawei's Kirin 9000S, 9020, and Ascend 910C, with an estimated 20,000 WSPM of capacity. N+3, confirmed on the Huawei Kirin 9030 in December, extends 7nm-class scaling using DUV multi-patterning, though TechInsights characterized it as firmly 7nm/6nm-equivalent in absolute terms rather than a true 5nm node.

Four major new 12-inch fabs are under construction or recently completed, in Shanghai (Lin-Gang), Shenzhen, Beijing, and Tianjin, including an $8.87 billion facility, collectively targeting approximately 340,000 wafer starts per month of new 28nm-and-above capacity.

Export controls from the U.S., the Netherlands, Japan, and Taiwan constrain SMIC's ability to scale its advanced nodes. The company has been on the U.S. Entity List since December 2020, blocking access to ASML EUV scanners and progressively tightening DUV and etch equipment supply.

Taiwan added SMIC and Huawei to its own export-control blacklist in June 2025, requiring permits for high-tech equipment shipments. Although it was reported back in August that SMIC planned to double its 7nm capacity in 2026, the company remains constrained by tooling access: analysts estimate SMIC's advanced-node capacity will remain in the low tens of thousands of wafer starts per month rather than the hundreds of thousands that an unconstrained buildout would target.

SMIC's pricing reflects the competitive pressures in the mature-node segment, with the company having reportedly cut 28nm wafer prices by roughly 40% in early 2025, dropping from approximately $2,500 to $1,500 per wafer, before reversing course with a roughly 10% increase later in the year as utilization exceeded 95%.

Pricing and demand

After two years of price declines driven by Chinese capacity additions, the mature-node segment is reaching a floor. TrendForce reported in March that UMC, VIS, Powerchip, and Nexchip were preparing price increases of up to 10% from April through June this year, with the latter confirming a 10% hike effective from June.

One big factor is tightening supply alongside the cyclical recovery: TSMC has been reallocating 40-90nm production capacity toward CoWoS advanced packaging and silicon interposer fabrication for AI accelerators, reducing the available mature-node wafer supply from the world's largest foundry.

Demand from automotive (GF's automotive revenue alone is on track for $1.5 billion in 2026), power management ICs for AI servers (typically manufactured on 28-55nm BCD processes), DDICs, and embedded flash microcontrollers continues to grow.

Whether these three foundries remain independent is an open question. The Project Ultron reports suggest that at least one party has considered consolidation, and the logic for doing so, at least in terms of economics, grows as margins compress and capex requirements grow.

While SMIC's expansion is state-backed and largely insulated from commercial return calculations, GF is tied to U.S. industrial policy and defense spending, and UMC's future hinges on whether 12nm FinFET with Intel can deliver the revenues that pure mature-node services cannot.

For decades, semiconductor design has been driven by humans coming up with bright ideas that unlock new innovations. But the benefits of better chip design have been reaped, including the rise of AI, which now means there could be another party involved in making chip designs smarter: AI itself.

‘Chip designer’ isn’t one of the roles on the chopping block as AI automation upends the job market. But in the narrow pockets of the design flow where problems are structured, and evaluators are robust, it is starting to be adopted — with benefits.

Google DeepMind's AlphaChip reinforcement-learning system has produced designs for three generations of the company's Tensor Processing Units (TPUs), with DeepMind claiming "superhuman" layouts compared with those produced by human designers. They’re not alone: Synopsys has passed 100 production tape-outs with its DSO.ai design-space-optimization tool, reporting productivity boosts of more than three times and power reductions of up to 25% for customers including STMicroelectronics and SK hynix.

"Like every new technology, AI may have multiple uses," said Borivoje Nikolić, professor of electrical engineering and computer sciences at the University of California, Berkeley, in an interview with Tom’s Hardware Premium. Nikolić drew a parallel with Moore's Law, which has historically been exploited in two ways: to reduce the cost of an existing product by porting it to cheaper processes, or to add features that were previously impossible. "I think AI will be used in both ways," he says. "At the moment, the industry seems to be focused on the first item — how to make things cheaper, how to automate things in a better way than they were in the past."

By contrast, academics are more interested in using AI to discover things humans haven't yet thought of, an approach that mirrors breakthroughs in areas such as drug discovery and protein folding with the likes of AlphaFold.

Nikolić and his colleague Sagar Karandikar have been exploring that territory in their own research on cache replacement policies, a subject deep in the weeds of processor microarchitecture. Their ArchAgent system, built on Google DeepMind's AlphaEvolve framework, generated a cache replacement policy in two days that beat the prior state-of-the-art by 5.3% in IPC speedup on Google's multi-core workload traces. On the heavily worked-over single-core SPEC06 benchmarks, it took 18 days to eke out another 0.9%. That’s a "first sign of life" for Karandikar that large language models can design genuinely new logic, rather than just tinkering with existing parameters.

"There is still a lot of human guidance, and it kind of up-levels the kind of thinking humans have to do," said Karandikar, a computer architecture researcher at Berkeley, in an interview with Tom’s Hardware Premium. "The humans involved in that project are doing more of the high-level thinking — coming up with new ideas and guiding the LLM — and the LLM does a lot of the finer policy development around that."

Where AI is making breakthroughs

For Igor Markov, a chip design researcher who has spent years at the frontline of electronic design automation, the places where AI is adding real value are specific and often mundane. Some of the biggest wins, he says, come at the low end of the flow, such as tasks that previously required engineers to interpret informal specifications written in natural language and convert them into formal descriptions that a tool can act on.

Take power and ground networks, the intricate webs of metal that feed electricity across a chip. "They’re sometimes designed just with descriptions in natural language," Markov said in an interview with Tom’s Hardware Premium. "People explain the geometry, and then it's implemented, and at some point, you need to formalize it. This is a step that was done manually, and it's pretty straightforward to automate using AI." The productivity dividend isn’t massive; “it took a couple of days, now it's a couple of hours,” he explained. But is still better than nothing, even if the output still needs to be checked.

Where Markov is most bullish is on what he calls the agentic space: the high-level orchestration of chip design flows, including deciding whether a run is doomed or whether a flow needs to be restarted entirely. “If you take a zero multiplied by something, you get a zero,” he said. “But if you already have something decent, then this high-level control can be very, very enabling.”

The most stubborn corners of the industry are starting to think about adopting AI. Analog design has long been seen as the last redoubt of human craft, but researchers have begun producing generative AI systems such as AnalogGenie, which uses a GPT-style model to discover new circuit topologies, and Princeton's AI-enabled design-space discovery for millimeter-wave and sub-terahertz power amplifiers operating between 30 and 120 GHz.

It’s in these areas that what’s often seen as AI’s failing, that it doesn’t have an inherent knowledge or muscle memory of its own, becomes a strength. Humans have a tendency when porting a design from one process node to another to assume the old topology must be close to optimal for the new one. “AI may not have those kinds of barriers,” said Nikolić.

Testing versus real life

However, some caution is needed. AI can be trained to ace demos, but can flunk the messier problems engineers face in practice. "Whether something that works in five cases works in general, and allows you to innovate, that's the key," says Markov.

There is also the problem of what it is you are asking AI to do in the first place. Ask a model to design the best chip for AI, and without a formal, unambiguous specification of what best means, the model will produce something — or anything. "You will play whack-a-mole," Markov said when it comes to making it work in practice.

He added that every previous jump in design automation has provoked similar debates about whether machines can really think. Shortest-path algorithms for wire routing, once seen as a distinctly human capability, became undergraduate coursework. Placement algorithms now routinely outperform human designers. Logic synthesis, once considered too abstract to automate, is handled by for loops and conditionals. “EDA has always been a type of AI, because it automated what people did,” Markov said. “We are just moving along the straight line, and there's no stopping.”

For now, AI is acting as a force multiplier, Markov said, squeezing more output from teams rather than shrinking them. Who’s in those teams and what they bring is also shifting: engineers who are fluent with AI coding assistants are now in demand where they weren't six months ago.

Jevons’ paradox also looms large over the potential of AI in the chip design process. As AI makes certain parts of the process dramatically cheaper and faster, Nikolić expects engineers to use that freed-up capacity to explore territory they wouldn't otherwise have dared tackle, including the design of the AI chips driving the whole cycle in the first place.

After all, if any class of silicon is ripe for the kind of optimization that hasn't yet been systematically studied, Markov argues, it is the highly structured, performance-critical accelerators powering the current boom. “There’s plenty of opportunity for humans to be improving other parts of the design flow to make it more amenable to these AI-based systems,” said Karandikar. As models become more advanced, so too might their capacities to assist in chip design and development.

Nvidia still holds approximately 70% of the AI chip market share, but that share is projected to erode as Google, Amazon, Meta, Microsoft, and OpenAI invest billions in purpose-built chips designed for their specific workloads. ASIC-based AI server shipments are projected to reach 27.8% of the market in 2026, the highest share since 2023, which also forecasts that custom ASIC shipments will grow 44.6% year-over-year in 2026, nearly triple the 16.1% growth rate projected for merchant GPUs.

This is being enabled almost entirely by TSMC, which fabricates chips for all five hyperscalers and for Broadcom, the dominant custom AI chip architect. Broadcom alone carries a $73 billion AI backlog and is targeting $100 billion in annual AI chip revenue by 2027.

Marvell, which has partnered with Amazon on Trainium and Microsoft on Maia, projects up to $11 billion in AI ASIC revenue for 2026. Together, Broadcom and Marvell control roughly 95% of the custom AI ASIC co-design market.

So, with the market projected to expand significantly across 2026 and beyond, we take a look at what companies are currently up to and where they might be headed in the future.

Broadcom

Broadcom, which has arguably emerged as the core enabler of the AI ASIC ecosystem, reported $8.4 billion in AI semiconductor revenue for Q1 FY2026 (ending February 2026), a 106% year-over-year increase, and guided to $10.7 billion in Q2. CEO Hock Tan told investors the company has "line of sight to achieve AI revenue from chips in excess of $100 billion in 2027," backed by a disclosed $73 billion AI backlog.

Broadcom has confirmed six major XPU customers, including Google, which remains the longest-standing partner, with seven generations of co-designed TPU's since 2014. OpenAI signed a multi-year collaboration in October 2025 for 10 gigawatts of custom accelerators, with first deployment targeting the second half of 2026 using both 3nm and 2nm designs. That deal came after OpenAI was widely reported to be behind a separate $10 billion order. However, Broadcom semiconductor president Charlie Kawwas joked on CNBC that OpenAI "has not given me that PO yet," leaving the identity of the mystery customer officially unconfirmed.

Meta, ByteDance, and Fujitsu round out the confirmed customer list, and analysts have identified Apple and Arm/SoftBank as potential future engagements. Arm is separately developing a custom CPU for OpenAI's Broadcom-built accelerator, a contract that could be worth billions to SoftBank.

The tech behind this growth is Broadcom's 3.5D XDSiP platform, which uses face-to-face 3D stacking via TSMC's SoIC process combined with 2.5D CoWoS integration. The platform enables packages exceeding 6,000 mm squared of silicon with up to 12 HBM stacks, far beyond the roughly 2,500 mm squared limit of conventional 2.5D designs. In February, Broadcom announced it had begun shipping the industry's first 2nm compute SoC built on this platform, integrating four N2 compute dies, one I/O die, and six HBM modules.

In terms of networking, Broadcom’s Tomahawk 6 switch chip entered volume production in March as the industry's first 102.4 Tbps Ethernet part. The companion Jericho 4 fabric chip (51.2 Tbps) began shipping last August and is designed to interconnect over one million XPUs across data centers. Nvidia's competing Spectrum-X1600, meanwhile, isn’t expected in volume until the second half of 2026.

Google TPU

Google's TPU program is the most mature custom AI silicon effort among the hyperscalers, and its latest generation represents a significant architectural leap. The TPU v7, codenamed Ironwood, was announced at Cloud Next in April 2025 and entered preview in November. Each chip delivers 4,614 FP8 TFLOPS with 192 GB of HBM3E memory at 7.37 TB/s bandwidth. It’s manufactured on TSMC's N3P process in a dual-chiplet design co-developed with Broadcom and MediaTek, and features two TensorCores with doubled 256x256 MXU arrays plus four SparseCores.

The 9,216-chip superpod configuration delivers 42.5 FP8 exaflops with 1.77 PB of aggregate HBM. Per-chip, Ironwood's 4,614 TFLOPS sits close to Blackwell's approximately 5,000 FP8 TFLOPS, but SemiAnalysis estimates that TPUs achieve higher sustained model FLOP utilization of roughly 90% for transformers versus 70% to 80% for GPUs, narrowing or erasing the real-world performance gap. Google claims that the total cost of ownership (TCO) per Ironwood chip is roughly 44% lower than a GB200 server from its own procurement perspective.

Google is now selling TPU access aggressively beyond its own services. Anthropic committed to up to one million TPUs in the largest deal in Google Cloud history back in October, while Meta entered talks for multi-billion-dollar TPU deployments in February this year. The current-generation TPU v6e Trillium remains widely available on Google Cloud at $2.70 per chip-hour on demand, delivering roughly four-times better price-performance than H100 instances for LLM workloads, according to Google's own benchmarks. Google's Axion ARM CPU, based on Neoverse V2 and reportedly manufactured on TSMC 3nm according to TrendForce, complements TPUs for general-purpose cloud workloads.

Amazon Trainium

AWS has matched Google's pace with an aggressive custom silicon roadmap developed by Annapurna Labs, the Israeli chip design house acquired by Amazon in 2015. Trainium3, which went generally available at re:Invent in December, is AWS's first 3nm chip. Each Trainium3 delivers 2.517 PFLOPS FP8 with 144GB HBM3E at 4.9 TB/s bandwidth, roughly double the compute and 1.5 times the memory of its predecessor. The new Trn3 UltraServer packs 144 chips delivering 362 FP8 petaflops with 20.7 TB of memory, a 4.4 times improvement over Trn2 UltraServers.

AWS CEO Matt Garman said at re:Invent 2025 that the company had "already deployed more than 1 million Trainium processors" and was selling them as fast as production allowed. CEO Andy Jassy called it "already a multibillion-dollar business." The Project Rainier facility in Indiana, an $11 billion, 2.2 GW campus, had roughly 500,000 Trainium2 chips running for Anthropic by October 2025, and AWS also confirmed an OpenAI deal to supply 2 GW of Trainium computing capacity.

Trainium4 was announced in December 2025 for late 2026 or early 2027 availability, promising three times FP8 performance, six times FP4 throughput, and four times memory bandwidth over Trainium3, with an estimated 288 GB of memory. One notable feature is support for Nvidia NVLink Fusion, enabling hybrid clusters that mix Trainium and Nvidia GPUs. AWS's Graviton5 ARM CPU (192 cores, TSMC 3nm, Neoverse V3) was also announced at re:Invent 2025.

Meta MTIA

Meta disclosed one of the most ambitious custom chip roadmaps in the industry in March, unveiling four new MTIA generations (300 through 500) for deployment through 2027, in addition to the already-shipping MTIA 100 and 200. The company has deployed hundreds of thousands of MTIA chips for inference across Facebook and Instagram.

The MTIA 400 delivers 6 PFLOPS FP8 and 18 PFLOPS MX4 with 288GB HBM at 9.2 Tbps bandwidth in a 1,200W envelope. The MTIA 500, scheduled for 2027 mass deployment, scales to 10 PFLOPS FP8 and 30 PFLOPS MX4 with up to 512GB HBM at 27.6 Tbps in a 2x2 chiplet configuration, consuming 1,700W. From the MTIA 300 to the 500, HBM bandwidth increases 4.5 times and compute scales 25 times, with a new chip roughly every six months.

Meta has been explicit that MTIA is not a replacement for Nvidia GPUs. The company expanded its Nvidia partnership in February for "millions of AI chips," including Grace Blackwell and future Vera Rubin platforms, in a deal reportedly worth tens of billions. Custom silicon handles optimized inference at a massive scale, while Nvidia handles frontier model training.

With $115-135 billion in 2026 capex guidance, Meta is buying everything it can from both sources. The MTIA chips are fabricated on TSMC's advanced nodes: MTIA 100 on 7nm, MTIA 200 on 5nm, and the 300-series onward reportedly moving to 3nm with CoWoS packaging.

Microsoft, Tesla, and other efforts

Microsoft's custom silicon program took a significant step forward in January with the deployment of Maia 200, manufactured on TSMC 3nm with over 140 billion transistors. The chip delivers more than 10 PFLOPS FP4 and 5 PFLOPS FP8 with 216GB HBM3E at 7 TB/s bandwidth in a 750W envelope. Microsoft claims it offers 30% better performance per dollar than the best hardware in its existing fleet and calls it "the most performant first-party silicon from any hyperscaler." Maia 200 currently serves GPT-5.2 models for OpenAI and powers Microsoft 365 Copilot workloads from its Des Moines data center.

The path to Maia 200 was far from smooth, though. The original Maia 100, built on TSMC 5nm, was reportedly designed more for image processing than generative AI and never powered production AI services at scale. Maia 200 was delayed roughly six months due to design changes requested by OpenAI that caused simulation instability, plus chip team turnover. CEO Satya Nadella has emphasized that Microsoft will continue purchasing Nvidia and AMD chips alongside Maia. Microsoft's Cobalt 200 Arm CPU (TSMC 3nm, 132 Neoverse V3 cores) was announced at Ignite 2025 and is now live in Azure data centers.

Tesla’s Dojo project, meanwhile, met a very different fate. Despite years of development and an innovative D1 chip (TSMC 7nm, 50 billion transistors, 362 TFLOPS BF16, with a unique 354-core mesh architecture), Tesla disbanded the Dojo team in August. Lead architect Peter Bannon departed, and roughly 20 engineers left to found DensityAI. Elon Musk explained that "once it became clear that all paths converged to AI6, I had to shut down Dojo." Tesla is now focusing on AI5 and AI6 inference chips, with AI6 backed by a $16.5 billion Samsung fabrication deal, while relying on Nvidia hardware for current training needs.

Among other contenders, Intel's Gaudi 3 has struggled with software maturity and missed targets. Shipment goals were cut by more than 30% in 2024, and the Habana Labs brand is being absorbed into Intel's broader accelerator efforts under CEO Lip-Bu Tan. In China, Huawei's Ascend 910C (SMIC 7nm, roughly 800 TFLOPS FP16, 128GB HBM) targets 600,000 units in 2026 but faces yield challenges at around 20%. Cambricon, meanwhile, plans to triple output to 500,000 chips.

TSMC enables it all

TSMC is the indispensable enabler across all these custom AI ASIC efforts. The foundry generated $122.4 billion in 2025 revenue, up 36% year-over-year, and forecasts a 60% compound annual growth rate for AI chip revenue through 2029.

Its CoWoS advanced packaging capacity is scaling from roughly 65,000-75,000 wafers per month in 2025 to a target of 120,000-130,000 wafers per month in 2026, and capital expenditure of up to $56 billion is planned for the year. The 2nm node entered mass production at the back-end of last year, with capacity fully booked and targeting over 60,000 WPM by the end of the year. Nvidia has secured roughly 60% of CoWoS allocation (c. 595,000 wafers), Broadcom about 15% (c. 150,000 wafers), and AMD approximately 11% (c. 105,000 wafers). Every custom ASIC in this article depends on CoWoS or its successor CoWoS-L for HBM integration, and TSMC's packaging capacity is now a more binding constraint than wafer fabrication itself.

The driving factor behind custom ASIC adoption is, of course, the rapid growth of inference workloads, which Deloitte projected to account for two-thirds of all AI compute this year.

With custom silicon’s up to 65% TCO advantage over conventional GPUs for inference at production scale, it’s easy to see why so many hyperscalers are pursuing custom ASICs. Broadcom and Marvell together control roughly 95% of the ASIC co-design market, so the question is no longer whether custom silicon will take share from Nvidia, but how quickly it erodes Nvidia's pricing power as these programs reach full production scale.

Over the past few years, we’ve seen an absolute explosion of activity in the OLED monitor space. What was once a niche panel option available on premium laptops has wonderfully spread to encompass the best gaming monitors for desktop PCs. That makes understanding the inner workings of the panels more important now than ever, especially when it comes to burn-in, the most common source of anxiety for potential customers. Below, we'll outline why this occurs, and this guide will also teach you how you can prevent it.

OLEDs differ from traditional LCDs because each pixel in the panel emits its own light when current passes through it. This design means there is no need for a separate backlight to illuminate each pixel, unlike LCDs. So, to display black, the individual pixels can be turned off, allowing true “inky” blacks, infinite contrast, and vibrant colors unmatched by LCD-based monitors. That means the necessary pixels are turned off when representing the color black.

The different types of OLED monitors

There are several types of OLED monitors, with WOLED and QD-OLED among the most popular. WOLED monitors feature red, green, blue, and white subpixels overlayed on a white OLED layer. The white light passes through the red, green, and blue filters to produce color, while the light passing through the unfiltered white subpixel can be used to enhance overall brightness (and to compensate for the inefficiency of the color filters).

QD-OLED monitors, on the other hand, use a blue-emitting layer instead of WOLED’s white layer. Furthermore, the light passes through a quantum dot layer without the need for color filters, which helps to boost color saturation compared to WOLEDs.

LG has been a big player in this space, supplying WOLED panels not only for its self-branded monitors, but also to third-party customers. The company recently announced at SID Display Week 2026 that it is launching 3rd generation Tandem OLED panel technology. LG’s development in this space has come at a rapid clip, as the company only announced its 2nd generation Tandem OLED technology back at CES 2026.

Tandem OLED is the successor to LG’s WOLED panel technology and offers some key advantages. It uses a four-layer stack (blue, green, blue, red) which passes through a filter. Whereas older WOLED panels use a separate white subpixel, the latest Tandem OLED panels use a Primary RGB layout, negating the need for the white subpixel. In practice, Tandem OLEDs tend to be brighter than their WOLED counterparts while offering improved color volume, putting them on more equal footing with QD-OLEDs.

According to LG, its 3rd-generation Tandem OLED panel technology offers peak brightness of 1200 nits and typical brightness of up to 500 nits. Despite these impressive figures (for an OLED), LG claims that it has reduced power consumption by 18 percent, while offering a panel service life of over 15,000 hours. That last figure is a 2x improvement over 2nd-generation panels.

“This advancement is enabled by a newly developed OLED element that optimizes hole and electron movement to minimize degradation while ensuring uniform picture quality, along with the application of a deep blue dopant to further improve color purity, color reproduction, brightness, low power consumption, and longevity,” LG wrote in a press release. “LG Display plans to begin mass production of the automotive panel within this year before later expanding into IT and other applications.”

Of course, these are just manufacturer claims, so we have to temper our expectations until we see the results in the real world. However, if the claims do hold up, the performance of the 3rd-generation panels should go a long way towards alleviating some of the reliability concerns some consumers have about OLED panels.

Should you be concerned about OLED burn-in?

Before we discuss OLED burn-in, we must first explain what exactly makes up an OLED. OLED stands for organic light-emitting diode. It’s the “organic” in the name that can cause issues with extended use. The use of organic compounds makes OLED panels more fragile and susceptible to power input and high sustained brightness levels.

In addition, OLEDs provide their own light source, as they are self-illuminating. Over time, these self-illuminating diodes will lose brightness and will appear dimmer to the naked eye as their luminescence degrades. When these overworked diodes sit next to diodes that haven’t seen such frequent use, what you’re witnessing is “burn-in.”

An easy example to explain how this can occur is with 24-7 TV news channels. These channels often have a mostly static banner sitting at the bottom of the screen. Because of the banner's persistence, with little movement of text and logos that can appear within it, the pixels see significantly more “power on” time than the surrounding pixels, where there is more dynamic action. If you leave that static banner in place for weeks or months at a time, you’ll eventually notice burn-in if you switch to a solid-color background.

However, there are some best practices you can implement in your daily workflow to help prevent burn-in in the first place.

OLED monitor care tips

• Set your OLED monitor to turn off or switch to a screensaver for 5 or 10 minutes if you’re not active.
• If you use a background on your computer, consider a dynamic background or a slideshow of images that rotate frequently.
• Rather than have a taskbar that is permanently docked, set it to auto-hide.
• Refrain from prolonged use of maximum brightness settings, as this can accelerate pixel decay.
• When possible, use dark mode in your operating system to limit the amount of power passing through pixels.
• When gaming, avoid using HUDs that are static in nature, as lengthy gaming sessions can accelerate image retention

Those are things you can do on your own that will go a long way towards reducing image retention. However, modern OLED monitors include automated mechanisms to help prevent and minimize image retention. For example, I personally use a Philips Evnia 8000 49-inch 240 Hz DQHD QD-OLED monitor for work and gaming. It offers a couple of tools for managing burn-in, including:

• Pixel orbiting/shifting: moves the image a couple of pixels left or right at regular intervals to prevent burn-in from static elements.
  
• Pixel refresh: this feature runs automatically after roughly 4 hours of screen on time, and it measures and adjusts voltage levels for individual pixels in the OLED screen. The feature runs for about 4 minutes.

Each OLED monitor manufacturer has their own specific tools for dealing with the same issues. For example, Asus offers Pixel Shift technology, controls for adjusting logo brightness, manual Pixel Cleaning, and automatic cleaning in standby mode.

I’ve owned my Evnia 8000 for roughly 18 months, and over that time have accumulated 1,800 hours of on-time according to the monitor’s OSD. I ran the XbitLabs Screen Burn-in Test and didn’t notice any issues, which was a relief.

Should you take the OLED plunge?

The two biggest knocks against OLED monitors are continually being addressed. There’s the issue of panel longevity, particularly with burn-in/image retention. However, sticking to common best practices when using OLEDs and enabling automatic panel refresh routines and mitigation strategies offered will go a long way toward ensuring that you get years of useful life out of your monitor. Manufacturers are also stepping up the quality of the components they’re using and reducing power consumption to help extend the life of OLED panels.

Another concern people have is cost. It’s true that OLEDs carry a premium over traditional IPS and VA panel technology. However, that premium is shrinking as production volume increases. We can’t be certain that OLED monitors will eventually reach price parity with their LCD counterparts, but the difference will likely shrink to the point where many customers will gladly fork over the extra money for a superior viewing experience (and given the popularity of OLED panels, many people are already making that jump).

With OLEDs having crossed over into nearly every facet of computing life, from smartphones to tablets, to laptops, to the best OLED gaming monitors, to productivity monitors, to portable monitors, I can say with confidence that it’s time to stop being leery of the technology and jump in with both feet.

All three leading-edge foundries — Intel Foundry, Samsung Foundry, and TSMC — have initiated mass production of chips using 2nm-class process technology. Samsung was the first one to start production using its SF2 node (though it could be argued that this is a rebadged SF3P) around mid-2025, Intel followed suit with its 18A node in November (albeit at development lines in Oregon, not production lines in Arizona), and TSMC initiated high-volume manufacturing using its N2 process at two volume fabs in Taiwan in December. We outline what's next for these three leading-edge foundries.

The current state of the market

The amount of capital, expertise, and experience required to develop leading-edge process technologies and build high-volume fabs supporting advanced nodes is so high that only three companies in the world are currently capable of producing them. Companies like Rapidus have yet to prove they are a viable leading-edge chipmaker. Meanwhile, all three leading foundries are transitioning from traditional node scaling to a more segmented, architecture- and product-driven approach, but are doing so with different priorities.

TSMC is focused on predictable scaling, combined with aggressive specialization, which is why its roadmap is split into high-performance computing-oriented technologies with backside power delivery network (BSPDN) and cost/density-optimized nodes without it.

Samsung has a wide range of node variants, though it is currently more focused on yield improvement, rather than on scaling, which is why its roadmap appears more iterative than breakthrough-focused. This is perhaps why it is behind competitors with its BSPDN implementation.

Intel seems to be pursuing the most aggressive technological roadmap with a conjoined implementation of gate-all-around (GAA) RibbonFET transistors and PowerVia BSPDN, rapid iteration, and the aggressive pursuit of High-NA EUV lithography in 2027 – 2028, years before its rivals.

Intel Foundry: The most ambitious chipmaker

Being a new player in the foundry market and a large integrated design manufacturer (IDM), Intel is pursuing a multi-faceted strategy aimed at addressing the needs of its own products, as well as attempting to land customers that do not necessarily require leading-edge process technologies.

Intel's roadmap is the most ambitious, but arguably the most volatile one, when compared to the plans of other leading foundries. On the one hand, Intel needs the best fabrication technologies to differentiate its own consumer and data center products. To that end, with its 18A and subsequent process technologies, Intel bet on the simultaneous implementation of GAA transistors and a BSPDN to maximize performance, power efficiency, and transistor density. On the other hand, since Intel has zero customers from the automotive and smartphone sectors, it does not have any technologies tailored specifically for these applications.

Intel's 18A is probably the most important technology for the company in years, as it will return production of the company's consumer CPUs back to its own fabs, something that promises to greatly improve margins. Although the company is in the process of improving yields on 18A and current 18A volumes are not significant, Intel is already preparing follow-on refinements such as 18A-P (with enhanced performance and improved power efficiency) and 18A-PT (which supports through silicon vias (TSVs) and can be used for 3D-integrated systems-in-package).

Beyond that, Intel is targeting 14A and 14A-E for 2027 ~ 2028 production readiness and an early ramp. The nodes will introduce Intel's 2^nd Generation RibbonFET GAA transistors, revamped PowerDirect backside power delivery, and Turbo Cells to improve the performance of critical data paths.

These will be the company's first nodes to use High-NA EUV lithography, at least for some 14A and 14A-E variants, which will be another attempt to introduce a technology that will differentiate Intel compared to competing nodes. Intel has said that the interest in 14A from external customers is significant. Musk's Terafab project is set to make use of Intel's 14A, as a licensee, but not as a customer.

At the same time, Intel is heavily relying on node variants to address different use cases, including performance enhancements (P), feature enhancements (E), and through-silicon via support (T). These process technologies are required to enable Intel to build custom multi-chiplet products for consumer and data center applications, which directly support its strategy to produce most of its products at in-house fabs.

Intel's roadmap also includes continued investment in mature nodes such as Intel 16 and UMC 12 as the company pursues a strategy to capture demand outside leading-edge applications, to ensure steady revenue streams.

While Intel's plans are aggressive and ambitious, the abrupt cancellation of 20A in late 2024 highlights the execution risks associated with such a roadmap.

Samsung Foundry: When yields matter more than nodes

Samsung was the first company to adopt GAA transistors with its SF3E technology in 2022, three years before Intel and TSMC. However, low and unpredictable yields have limited the adoption of this technology to niche applications like cryptocurrency mining ASICs. While SF3 was more mature, it was still adopted by select applications, mostly internally. As a result, the highest-performing chips made by Samsung are produced using FinFET-based SF4P and SF4X, which puts the company behind its rivals.

For now, reducing defect density, increasing yields, and ensuring stable yields are the top priorities for Samsung. Last year, it began making mobile system-on-chips (SoCs) using its SF2 node (which it calls the 1^st Generation 2nm GAA process), but among the major goals for the company for this year is to ramp up '2^nd Generation 2nm [SF2P] and prepare performance and power-optimized 4nm process,' which suggests limited adoption of SF2. The fact that the low-power 4nm-class node will be a major workhorse for the company. The company's roadmap also indicates SF2X (HPC-oriented) in 2026 as well as SF2A (for automotive applications) and SF2Z (SF2X with BSPDN) in 2027, though we can only wonder whether these nodes will be widely adopted.

Nonetheless, Samsung's iterative approach to the evolution of its SF2 nodes (SF2=>SF2P=>SF2X=>SF2X with backside power) is evident, which gives us hope that the company's yields will gradually improve.

Samsung's next major node will be SF1.4, a 1.4nm-class process technology optimized for consumer and smartphone applications, which won't feature backside power delivery. Samsung's slides put SF1.4 above the SF3 and SF2 families, which may suggest that this manufacturing process will feature some major enhancements, such as a new GAA transistor design or other major refinements. Samsung expects to mass-produce chips on its SF1.4 technology in 2027, so it can formally leave Intel and TSMC behind with its 1.4nm node.

A big question lingers, and that's whether Samsung plans to finally start using pellicles with its EUV lithography tools starting with SF1.4, or later. A lack of pellicles greatly increases the number of potentially yield-killing stochastic mask-borne defects, which are increasingly dominant at the 2nm and are getting much worse at thinner nodes.

TSMC: New technologies like clockwork

TSMC's roadmap remains the most structured and execution-focused among the three. The world's largest contract chipmaker initiated mass production of chips using its N2 process technology — its first node with GAA nanosheet transistors — at two fabs simultaneously late last year in a bid to meet demand from a wide range of applications, starting from Apple's smartphones and all the way to AMD's server-bound EPYC 'Venice' CPUs. Initiating volume production at two fabs simultaneously is something that rarely happens in the industry, though it looks like structural changes caused by demand from the AI segment are changing many things in the industry.

TSMC is on track to start making chips using performance-enhanced N2P with traditional frontside power delivery and A16 technology that adds backside power delivery on top, a split which highlights TSMC's increasingly segment-specific approach to leading-edge technologies.

Going forward, the company is set to continue offering advanced technologies with and without BSPDN, as this feature may be too expensive for consumer and smartphone applications, but is clearly valuable for heavy-duty data center processors. For example, A14 will emerge as a smartphone-oriented node in 2028, but then will re-emerge as a data center-oriented node once it gets BSPDN in 2029.

In addition, the company will continue to offer mainstream nodes like N4C, N3C, and eventually N2C for applications that are more sensitive to costs. Automotive-specific nodes (N7A, N5A, N3A) will lag leading-edge nodes by one to two generations, as they prioritize reliability and longevity over performance and transistor density.

TSMC's segmentation and yearly cadence for advanced manufacturing nodes enable the foundry to address the most demanding clients like Apple, AMD, Intel, Nvidia, or Qualcomm with competitive process technologies. Ultimately, such cadence and a wide range of nodes reinforce TSMC's position as the most predictable and commercially disciplined foundry.

Fractured futures

To sum things up, TSMC continues to bet on execution discipline and segmentation as it ramps its 2nm-class node at two fabs to meet overwhelming demand from a variety of applications, starting from humble cell phones all the way to heavy-duty servers.

Intel leads in architectural ambitions, as currently it is the only company that uses a process technology that features both gate-all-around transistors and backside power delivery. However, the company admits that its yields will only get to world-class level by 2027, which likely makes Intel's 18A node significantly less attractive to demanding customers.

Samsung sits somewhere in the middle, offering a wide variety of process technologies for different applications, but the company's yields with GAA-based nodes have been a challenge, which is why the firm is now focused on yield increases rather than on breakthroughs, so it does not attempt to leapfrog its competitors.

For anyone who has built their own PC, you probably know that incredible feeling of accomplishment when you finish. For an enthusiast, there’s just nothing like it. Flipping on the power switch, then pressing the power button on the case, and that sense of relief once you actually see the BIOS screen and watch it all come to life, accompanied by a swathe of RGB lighting illuminating the chassis like a warehouse rave.

There's the added benefit of hearing the machine finally take its first breaths, the fans spin up, creating a rush of air through your case. But then there’s that ever-constant hum in the background of those fans and the wind noise and other vibrations that make up the whole of the noise coming from your PC.

There are a few people out there, masochists perhaps, who don’t care about noise. The rest of us strive to have a quiet PC. Why a silent PC, some may ask? A silent PC helps with immersion if you’re a gamer, or can improve productivity by not being a loud distraction. You may be thinking, “I’ll just buy quiet fans and be OK.” And, in part, you’re not wrong.

But noise comes from a variety of sources. Be it fans on your case or on your AIO/CPU Air Cooler, a video card, or even chipsets and VRM heatsinks; fans are everywhere. There’s also noise from hard drives, pumps in an AIO or custom loop coolers, the ever-annoying coil whine, and even resonant vibrations from the chassis.

The good news is that, aside from coil whine, everything else is something you can mitigate in some fashion. Unfortunately, coil whine is something you simply have to tolerate, unless you want to apply clear nail polish to the chokes/inductors. You may be able to RMA the product due to coil whine, but you could be in the same boat after if it's a problem that plagues you later down the line.

Noise in your PC is, in fact, a byproduct of heat and airflow, and achieving the quietest PC possible requires balancing multiple competing factors. You also have to consider the tone versus loudness. Specific frequencies, like the high-pitched squeal of the chokes, can be more unappealing than lower-frequency noises. Building a quiet PC is not just about fans and buying better parts, but about working within the physical limits of your setup and figuring out how much money you’re willing to spend on silence.

Why it's challenging: the physics problem

The higher your processor or video card’s TDP/TBP (Thermal Dynamic Power/Total Board Power), the louder it gets, or the more cooling area you need to keep things quiet. The more powerful a system is, the more headwinds you face to keep it cool and prevent thermal throttling. In other words, it requires more effort to remove the heat from a fire-breathing 600W RTX 5090 and a 200W Ryzen 9 9950X3D2 than it does from a 250W RTX 5070 and a 120W Ryzen 7 9800X3D.

Thermal density on the dies themselves has also increased dramatically over the last several years. As more transistors are packed into a tiny space and stacked on top of each other, it becomes physically harder to remove the amount of heat generated within the same space. Because of this and other factors, keeping today’s high-end processors at or below their throttling points has become increasingly difficult, requiring larger coolers and more airflow to keep them running at peak performance.

Ideally, you want laminar airflow where air moves uniformly, parallel, and in the same direction at a constant velocity, but that’s nearly impossible inside a PC case. Moving air creates turbulence, which generates sound. Turbulence in fans can come from many sources, including the shape of the blades and the air passing over them, as well as being in front of or behind mesh panels, grills, heatsinks, or radiators. In short, when airflow encounters obstructions, it becomes audible as it weaves through and around them. There’s also the consideration of how multiple fans react together. If some are running at slightly different speeds, they can produce a rhythmic, off-putting resonance.

Since we know that more power and performance mean more heat, and that fans need to move more air to cool, more airflow means louder operation. And there lies the rub. If you cherish silence more than anything, something has to give. Between high-performance, cooling, and silence, you need to pick two. One will almost always be compromised for another.

Another noteworthy point is that diminishing returns of silence are also very real. While in general it’s easy to reduce noise from loud to moderate, it’s harder to go from moderate to very quiet, and even more difficult to move from very quiet to ‘near silent.’ Each small improvement requires disproportionately more effort, compromise, or cost. Massive AIOs or custom water-cooling loops aren’t cheap, and most silent fans and cases aren't either.

What can you do about it?

The first thing to be reminded of at this point is that it’s all a balancing act. You can only make a machine that outputs 750W so quiet without thermal throttling, losing performance, or spending a lot of cash. Therefore, setting your expectations is key, especially if you’re running a high-power machine. Even though it can be an uphill battle with some hardware, there are ways to get a quieter PC, at a cost or for free, even if your PC matches the output of a personal space heater. The good news is that everything below applies to any machine, be it an HTPC or a monster full-tower gaming rig.

What you can do for free

One of the first things you can do without spending any money is clean out the dust in your case, especially your dust filters, and from the components, like the CPU and GPU heatsinks and power supply intake. The more they get clogged with dust, the less air passes through to cool your system, lowers usable thermal dissipation surface area, and the more turbulent (and louder) the airflow can get, and the faster your fans need to spin to keep temperatures down.

Case placement is another factor you can easily change and matters for both dust and noise. Under the desk, or further from ear level, is ideal, so long as it’s not sitting directly on carpet (the worst place for dust!) and has access to cool air for the intakes. Proper cable management also helps, though it is often a minor detail, as most cables are tied up in the back and out of the way of fast airflow.

Another good way to reduce noise is to optimize your PC’s airflow and adjust your fan speeds. If you can run them slower, adjust it via the BIOS or through your motherboard’s software, like Armory Crate, Gigabyte Control Center, etc., and keep an eye on temperatures afterward to make sure you’re not starving any components for cool air. In the linked article, we discuss the importance of airflow, the good and bad of positive versus negative air pressure, and how to achieve those states, and it is, without a doubt, worth a full read.

At a high level, intake CFM (Cubic Feet /Minute - it’s not just fan count!!) greater than exhaust CFM is a positive-pressure environment, while more CFM exiting the case than coming in yields a negative-pressure environment. There are pros and cons to both configurations, but positive-pressure tends to be the most commonly used.

With positive airflow, the increased ‘pressure’ inside forces air out of the exhaust fans and vents, preventing dust from entering through cracks and crevices. Positive pressure is ideal for preventing dust build-up. It makes sense to use it with a high-airflow case with front mesh, a tower air cooler, and optimal for blower-style graphics cards, as it creates a balanced airflow pattern inside your chassis and keeps the temps of your core components in check.

Negative pressure is the opposite, where, at the cost of increased dust inside your chassis, it’s getting air out of the case at a greater rate. It’s good for preventing hotspots due to the vacuum effect, to use with restrictive front panels, and for small-form-factor PCs where clean airflow is hard to come by. It can even offer lower video card temperatures in specific cases, such as a restricted front panel, where heat is quickly removed from the chassis.

On the hardware side of things, starting from your CPU, you can adjust the voltage, called Vcore, through your BIOS or via overclocking software to use less power under load. Typically, you do this by using an offset that reduces voltage globally across all speeds and loads. On many AMD processors, this is even a good way to get more performance, as you can undervolt and overclock, raising the CPU multiplier for higher boost clocks. For many Zen 4 and Zen 5-based processors, you can often undervolt by 10-20mv and still boost your peak clock speed by 100-200 MHz.

On my personal Ryzen 9 9900X3D, I achieved a stable -15 mV undervolt and a +200 MHz overclock. It isn’t a night-and-day difference performance-wise, but if we can get more from less, why not? Obviously, your mileage may vary, but this reduced the maximum load temperature by several degrees and lowered the part's power consumption by up to 2%.

You can also limit your GPU's power usage by manually adjusting the voltage, the voltage curve, or by lowering the power limit. I find it easier to lower the power limit on very powerful and power-hungry cards, since it's a simple slider. You can also set an FPS limit to match your monitor’s refresh rate, so the card won’t try to produce any frames past that limit, whether it’s 120, 165, 180, or 240 Hz, thus saving power.

For example, I set a couple of my games, mainly esports titles, to a 240 FPS limit, and with my graphics card, an RTX 5090, it rarely breaks 400W. Whereas, when left to its own devices, it will try to output every frame it can, and use the full 600W+ power budget, assuming you don’t have any other bottlenecks. Graphics cards also have variable-speed fans you can adjust via software (MSI Afterburner, for example), and this is another good way to hear the sounds of silence. But be careful here, as video cards will drop ‘boost bins’ as temperature rises until it’s below a threshold. The cooler your card, the longer it stays at maximum boost clocks.

Paying for the premium of silence

You can buy a new case with sound-dampening materials like the be Quiet! Silent Base 802 ($199.99) or other silent options such as the Dark Base Pro 901 ($199.90), Fractal Design Define 7 ($204.99), or even the old Antec P101 Slient, if you can find it. The downside of these cases is that you lose the front mesh and airflow, so if you have high-power components, the internals could run warmer than in a more free-flowing design, raising your internal temperatures and, thus, fan speeds and noise. If those options won’t work, you can take a look at our Best PC Cases article to see what we picked out across a wide variety of sizes.

Often, cheap stock fans that come with cases, especially off-brand chassis, are often noisey and inferior to those you purchase from popular quiet fan brands like Noctua, be quiet!, or Arctic. Buying quiet fans based on their specifications is a good start, physically, and will allow you to go from loud to moderate with just a little effort. Our Best PC Fans article can certainly help with that endeavor. If money is no object, we liked the Noctua NF-A12x25 G2 (2x @ $64.95, or one @ $34.95). If these are too expensive, our pick for best budget silence-optimized fans is the Arctic P120 Pro. Also, the larger the fan, the more air it can move, and generally quieter while moving the same amount of air.

When picking parts for your PC, you can choose quiet parts from the beginning, such as CPU coolers, like the Noctua NH-D15 Chromax.black ($129.95), the be quiet! Dark Rock Elite or Dark Rock Pro V (both are $84.90), or the Thermalright Peerless Assassin 120SE ($39.90) for a budget-friendly air cooler option.

In the world of AIOs, one of the best for silence is the be quiet! Silent Loop 3 (360mm $129.50), or the budget Montech HyperFlow Silent (360mm $76.00 - though our review said it wasn’t the quietest on the market). If you need a high-performing AIO with silence in mind, the Corsair iCue Link Titan 360RX RGB AIO ($159.99) and its magnetic bearing dome fans had “chart-topping noise-normalized performance” and the “Lowest noise levels in common scenarios” according to our review. Custom water cooling is another way to reduce noise compared with air coolers or AIOs. While you can replace the fans on those devices, a custom loop lets you pick your own radiator, fans, and pump to optimize for performance, quiet, or a balance of both. While this cooling method costs more than the other options, you have complete control over the parts that make noise and greater control over the pump and fans. You can also expand it to add more radiators for more cooling capacity and reduced fan noise.

Major contributing parts to noise out of the way, other things matter too. When silence is golden for your build, consider moving to SATA-based SSDs to eliminate noise if you're using HDDs for anything other than cold storage, where they’re inactive/sleeping most of the time. Another potential upgrade that could save some decibels is your power supply. Most of these days run in a ‘hybrid’ mode, where the fan stays off until a certain temperature or load is reached. But the more efficient it is, think Gold/Platinum/Titanium 80 Plus or Cybenetics certifications, the better chance it remains silent at light to medium loads. The be quiet! Dark Power 13 ($111.90) is a solid choice for quiet operation and reliability. If that doesn’t work for you, please check out our Best Power Supplies guide for other options.

Takeaways

Building a quiet PC can be quite challenging, especially if you’re trying to make it ‘near-silent’, as there are many considerations that go into making something that quiet. If you have a power-hungry system, it’s going to be that much more difficult to knock off some decibels compared to a low-power system, as it has less heat to evacuate. Still, there are plenty of things you can do to improve your acoustic performance from obnoxious to tolerable without emptying your wallet or losing performance.

• Dust and clean out your case
• Adjust fan curves
• Undervolt your CPU or GPU
• Set FPS limits in your games
• Move your PC away from ear-level
• $ - Rubber isolation for fans/HDD/pumps
• $$ - Upgrade to a more efficient power supply
• $$$ - Replace fans/coolers/case with ‘silent’ models

In the end, making a quiet PC isn’t as easy as slapping “silent” fans in your case and calling it a day, though that is a start. Every watt of power your system uses becomes heat, and that heat has to go somewhere. Between fan turbulence, pumps, vibration, coil whine, and even the way air moves through the mesh on your case, countless factors are working against true silence.

The reality is that building a quiet PC is one massive tightrope walk, balancing performance, acoustics, and cooling. The closer you get to silence, the more effort, money, and compromise it tends to require. You may never eliminate noise, especially with today’s high-powered hardware. Still, with the right expectations, some tuning, and perhaps a bit of cash, you can turn an obnoxiously loud system into something more pleasing to the ear.

The Middle East has long been keen on becoming a data center hub: as early as 2017, the United Arab Emirates (UAE) launched an AI strategy that was designed to place it as a global leader in the space by the start of the next decade. It quickly showed how it wanted to do that by setting up G42 a year later to corral its cloud computing capabilities.

Qatar followed with its own national AI strategy in 2019, and Saudi Arabia did the same in 2020. All have thrown significant investment into their projects, which has in turn attracted global investment, which is also eager to take advantage of the region’s cheap energy costs and significant sovereign wealth.

Saudi Arabia and the UAE are seen as the third and fourth most attractive places to develop data centers, according to Adrian Cox, managing director and thematic strategist at Deutsche Bank Research, in an April note. They sit only behind Virginia and Texas.

The largest projects are becoming pieces of national infrastructure, requiring vast amounts of electricity, cooling capacity, fiber connectivity, and political certainty. That’s why the Gulf looked so attractive to many. In parts of Europe and the United States, data center developers are running into grid constraints, permitting delays, local opposition, and power bottlenecks. In the Gulf, by contrast, governments can work on energy policy, land allocation, planning permission, and sovereign capital with a single national strategy.

All that combined makes the region unusually well-suited to the industrial scale of AI buildout. Training and running frontier models requires dense clusters of specialized chips, which in turn require dependable power and cooling. For hyperscalers, the appeal is obvious: build where the state wants you, where capital is available, and where energy supply is less constrained than in many traditional data center hubs.

“The Middle East was a prime candidate for the expansion of data centers before the conflict given readily available supply of power, available capital for development, domestic regulatory push, and strong political ties to the US,” said Mayank Maheshwari, an equity analyst at Morgan Stanley. Big money projects were announced for the region, including the Stargate project for the Middle East, among others.

From boom to bust?

But that belief has been shaken by the disruption within the region after Israel and the United States launched their first attempt to decapitate the Iranian regime.

Iran’s Islamic Revolutionary Guard hit a number of Amazon Web Services data centers in the UAE and Bahrain with drones and missiles as part of its ongoing war against the United States and Israel. Alongside that, it has posted videos online threatening to strike the planned Stargate project on the outskirts of Abu Dhabi as payback for the United States’ involvement in the war. It all adds up to a messy, dangerous time to be operating in the space in the region. In early May, Amazon's Middle East data centers were damaged by an Iranian drone.

The whole selling point of data centers is certainty. Cloud contracts are built on promises about uptime, redundancy, and service-level agreements. AI infrastructure adds another layer of pressure because companies are building compute clusters that may be booked months in advance, paid for through long-term contracts, and integrated into the internal systems of major companies.

The question for customers is not just whether a facility can survive a strike — so far, they largely have, once restored. It’s whether customers are comfortable putting critical workloads in a region where geopolitical escalation can suddenly become an operational variable. For all the talk of sovereign AI and national compute strategies, the basic commercial promise of a data center is simple: it has to be there when you need it.

The demand for data centers in the region hasn’t gone anywhere — but those scoping out projects have. They’re eyeing up locations further eastward that are in less close proximity to an active warzone.

“We see Asia's AI data center expansion getting even stronger in the coming years, especially in Southeast Asia, Japan, and Australia as hyperscalers could divert projects from the Middle East towards Asia,” said Maheshwari.

Too much panic

Not everyone is so convinced, though. The recent instability in the Middle East hasn’t fundamentally changed the investment calculus for data centers, said Mark Whyte, global head of built environment and infrastructure at Control Risks, in an interview with Tom’s Hardware Premium.

“There has been direct impact on, I think at least one data center that has been hit by a drone, but overall, we see no slowdown in activity,” he said. “If anything, the volumes of work are only up.”

That rosy outlook isn’t echoed by everyone. “Whether or not the current ceasefire holds, it has threatened the region’s economy, supply lines and facilities, and could yet squeeze investment not only in the region but also abroad,” reckoned Cox.

Whyte doesn’t dispute the potential for foreign backers to have second thoughts — but said that wouldn’t necessarily have a massive impact on the broader direction of travel. “It may well have an impact on some of the external investment, but I wouldn't see that as being a long-term impact,” he said.

Even if projects continue, the price of building them may change, though. The biggest, most strategically important projects may still go ahead because they are backed by governments with long-term horizons and deep pockets. But marginal projects that rely on external debt, cautious institutional investors, or multinational customers that have other options could become harder to justify.

Keep calm and carry on

Part of the reason that work is continuing on projects in the Middle East is the calculus by those within the region that this is a short-term instability and that AI — and the need to power it using data centers — is so consequential that they are going full steam ahead regardless. “Countries like Saudi Arabia are looking well ahead of this, rather than reacting in a tactical way,” said Whyte.

That doesn’t mean they’re being naïve, though: drones, bombs, and missiles are flying, and that’s indubitable. As a result, protecting those data centers is all important. “From a risk and resilience perspective, I think you have to look at the threats and risks to data center networks as a military planner would,” said Whyte.

And for those who have been engaged in the idea of being central to the global data center sector for close to a decade now, there’s little reason to back off much.

Saudi Arabia is not treating the conflict as a reason to back away, Whyte argued, but as a risk to manage while it pursues a longer-term strategic goal. “The Saudis in particular, see themselves as a global powerhouse for this type of thing going forward, and how they're trying to position themselves to the future,” he said. “It may well have an impact on some of the external investment, but I wouldn't see that as being a long-term impact.”

Seagate, Toshiba, and Western Digital are the only remaining manufacturers of hard disk drives. They not only continue to produce these storage devices but are also actively advancing them as demand for HDDs rises again. While hard drives from these companies share many similarities, each relies on a different set of underlying technologies — distinct recording methods, actuator designs, platter materials, and magnetic alloys, among others — resulting in markedly different roadmaps. In this story, we examine these roadmaps and attempt to make sense of them.

The state of the HDD market

The amount of data that the world generates is higher than ever now that not only people, but also machines generate well over 400 million terabytes of data every single day, according to estimates made in 2024. Most of that data ends up in data centers, so Gartner predicts that data center storage capacity requirements will increase at a compound annual growth rate (CAGR) of 19.5% between 2024 and 2029 and will eventually reach 3.19 zettabytes (3.19 million PB, 3.19 billion TB). While a significant portion of that data will be stored on 3D NAND-based solid-state drives, the lion's share will reside on hard disk drives, as HDDs can still offer lower per-TB cost than even the cheapest NAND memory.

Hard drives have been around for nearly 70 years, and over 220 companies have produced HDDs since they were introduced in 1956. In 2026, only three hard drive manufacturers — Seagate, Toshiba, and Western Digital — remain on the market, and their supply chains are largely integrated or consolidated, meaning that the industry has largely shrunk from where it used to be a decade ago. Nonetheless, the combination of per-TB cost, storage density, and storage performance that HDDs offer makes them competitive enough, particularly in AI and traditional data centers, which need to store plenty of data that must be accessed relatively quickly and therefore placed 'near online', or nearline.

In fact, over 60% of hard drives shipped today are nearline HDDs, according to Nidec, the world's largest supplier of HDD motors. The remaining circa 40% are consumer and enterprise NAS hard drives, video surveillance HDDs, desktop HDDs (a declining category), external drives, laptop drives (an almost extinct category), and legacy high-performance enterprise HDDs (Toshiba only).

Nidec estimates that 119 million HDDs were shipped in its FY2023 (ending on March 31, 2024), and 125 million hard drives were shipped in its FY2024 (ending March 31, 2025), an indication that unit sales of mechanical storage devices are stable and are growing due to demand from AI and traditional data centers.

Unit sales of HDDs increased in calendar 2025 compared to calendar 2024, according to reports from Hoya (the only maker of glass substrates for HDD platters) and Resonac (the largest independent supplier of HDD platters), though exact numbers are unknown.

"While 2.5-inch substrates declined as forecasted, 3.5-inch substrates achieved double-digit growth, resulting in overall steady performance," said Eiichiro Ikeda, chief executive of Hoya. "Current demand is exceptionally strong and is expected to increase further. Preparations to enhance our supply capacity are also underway."

The road to 100TB and beyond

All HDD makers have adopted energy-assisted magnetic recording (EAMR) technologies, though everyone uses different methods. Seagate is ahead of the pack with its HAMR-based 44TB drive, which is shipping to two leading cloud service providers (CSPs), whereas Toshiba and WD are trailing the leader with their FC-MAMR and ePMR/ePMR2 recording technologies, as they pursue deliberately more cautious strategies.

Note: HDD makers tend to list maximum drive capacities with shingled recording. To that end, even if the table does not explicitly list SMR, presume that range-topping HDDs with leading capacity use shingled recording tech, with all of its pros and cons.

Meanwhile, both Toshiba and WD plan to transition to HAMR in the coming years, though before that, they plan to perfect their HDD platforms and push their existing recording technologies to their absolute limits. Once everyone adopts heat-assisted magnetic recording (HAMR) technology that uses platters made of glass with granular FePt magnetic alloy, the development of their roadmaps will be more or less consistent and introduce HDDs with a circa 100TB capacity by around 2030 – 2031, though some roadmap slides are more optimistic, whereas others are more cautious.

Seagate: All-in on HAMR

All HDD makers tend to experiment with various recording technologies, platters, and heads. Just like others, Seagate has experimented with all kinds of EAMR methods, including microwave-assisted magnetic recording (MAMR), but publicly it bet everything on HAMR as the most capable one.

Before Seagate finally shipped its Mozaic 3+ Exos HDDs in Q1 2024, it spent over a decade evolving HAMR from lab demonstrations (FePt + laser writing) through prototype drives and hyperscaler trials. Starting from around 2016, the company repeatedly said 'next year' for high-volume HAMR-based HDD production, only to roll out the same statement the year after.

Between 2020 and 2023, Seagate's HAMR rollout ran into a series of well-known hiccups that repeatedly pushed back commercialization despite earlier aggressive timelines. The company had originally targeted volume shipments of 20TB HAMR drives around 2020, but persistent issues, such as near-field transducer (NFT) reliability, iron platinum (FePt) media durability under repeated heating, and manufacturing yield, slowed progress. These challenges made HAMR technically viable but difficult to produce at scale, which led to multiple delays and extended customer qualification cycles.

To solve these challenges, Seagate had to develop its 2^nd Generation HAMR platform, which it eventually named Mozaic 3+, which went into high-volume production in 2024. But now that Seagate has mastered everything that accompanies HAMR, it can introduce new capacity points, qualify them, and ramp up production of new HAMR-based HDDs fairly quickly. For example, the company is now shipping its 44TB Mozaic 4-based drives to select clients and plans to expand availability in 2027. Meanwhile, Seagate intends to start qualification shipments of 50TB HDDs featuring the next-generation Mozaic 5 platform in late 2027.

Following 50TB HDDs in 2028, 60 TB HDDs by 2029 – 2030, and plans for 80+ TB drives in 2031. With ~100TB HDDs, Seagate intends to adopt high-anisotropic ordered granular FePt (FePt L1₀ phase) magnetic alloy, which will give it a further boost to set new areal density records and ultimately produce HDDs with capacities beyond 100TB.

Toshiba: Stretching MAMR (almost) to the limit

Toshiba is the smallest of all HDD makers, so it has a very calculated strategy that is designed to address parts of the market that are not served by its rivals and to derisk everything as much as possible.

To that end, Toshiba's HDD roadmap is built around a conservative, step-by-step scaling strategy focused on flux-controlled microwave-assisted magnetic recording (FC-MAMR) with some HAMR-based HDDs due in 2026 – 2027 being test vehicles, rather than high-volume products. The company's roadmap no longer lists microwave assisted switching microwave-assisted magnetic recording (MAS-MAMR) it envisioned as an intermediate step between FC-MAMR and HAMR a few years ago.

For now, Toshiba has its M12-series 28TB FC-MAMR-based 11-platter drive with conventional magnetic recording (CMR) and is sampling shingled FC-MAMR HDDs based on the same platform with 30TB – 34 TB capacities. The new M12 hard drives rely on glass platters, but with traditional cobalt platinum (CoCrPt) magnetic alloy, which once again highlights Toshiba's step-by-step approach to adopting new technologies.

Looking forward, Toshiba's roadmap scales capacity primarily through more platters (up to 12), and continued FC-MAMR improvements targeting ~40TB drives around 2027. While the company intends to launch HAMR-based HDDs too, the 40TB capacity point will likely be limited to drives for select customers rather than true workhorses. More capacious HAMR-based HDDs are due late this decade.

In essence, Toshiba is taking a lower-risk, hybrid path: maximize MAMR and mechanical scaling first, then transition to HAMR only when necessary for the next major density jump.

Western Digital: Coexisting ePMR and HAMR

After abandoning MAMR technology in 2017 and having concentrated on energy-assisted perpendicular magnetic recording (ePMR) since then, WD expects its ePMR and ePMR 2-based hard drives to co-exist with HAMR for years to come. Furthermore, as ePMR and HAMR HDDs are very different, this means that the company isn't pursuing a dual-track, like Toshiba, but a multi-track roadmap aimed at maximizing yields and derisking all the technology transitions.

This year, the company's flagship 40TB offerings will rely on ePMR with SMR technology and feature 11 aluminum platters with cobalt platinum (CoCrPt) magnetic alloy. To squeeze in 11 aluminum disks and avoid using glass platters, WD had to squeeze the internal mechanics of the drive.

At the same time, Western Digital plans to start the transition to HAMR, with the first commercial 40TB and 44TB HAMR drives entering volume production around 2027, following hyperscaler qualification. Since WD's HAMR drives use edge-emitting lasers to briefly heat the iron-platinum (FePt) layer on the platters to its Curie point — where its magnetic characteristics shift — and temporarily lower coercivity to write the data, the HDD platters must be made of glass (or glass ceramic, though this will be used sometimes next decade), not aluminum, as it may degrade or deform over time. However, based on a comment made by the chief executive of Hoya, the only glass substrate maker for HDD platters in the world, it does not look like WD plans to use glass platters in high volumes for at least a couple of years, which in turn suggests a relatively slow production ramp.

"Starting in the latter half of FY2026 [which begins on October 1, 2026], shipments [of glass substrates] to the second customer will begin in addition to our current primary customer," said Eiichiro Ikeda, chief executive of Hoya. "We expect volume to increase substantially in FY2027 [April 1, 2027]. Equipment arrangements for FY2027, specifically for the second customer, have already been decided. Regarding volume beyond FY2028 [April 1, 2028], we are currently analyzing the situation, taking into account not only the increase from the second customer but also the movements of a potential third customer. Capital expenditures will be determined based on that schedule."

Seagate seems to be the primary producer of HDD platters based on glass substrates for its HAMR HDDs, Resonac (former Showa Denko) is catching up with its glass platters for Toshiba (and Seagate), whereas WD is the world's third maker of HDD media that is about to start using glass substrates.

WD expects to use both ePMR + SMR and HAMR technologies till at least 60TB capacity sometimes in 2028 or 2029, though it looks like proven ePMR + SMR will prevail in its shipments in the coming years. Yet, looking further out, WD's roadmap becomes aggressively HAMR-driven after 60TB: capacities are expected to scale to ~100TB in 2029 – 2030, enabled by higher areal density and drive architecture that supports up to 14 platters.

In short, Western Digital's strategy is a bridge-and-accelerate model — extend ePMR as far as possible, then rapidly scale with HAMR once the transition is justified. Beyond that, the company is targeting 140TB+ drives in the 2030s, which will require a transition to even more advanced media concepts, such as ordered granular and bit-patterned media, once HAMR on granular media reaches its limits.

Beyond capacity: High-performance and energy-efficient HDDs

In addition to increasing the capacities of their hard drives, Seagate and WD intend to increase the bandwidth and I/O performance of HDDs.

Seagate has offered its Mach.2-series hard drives with two actuators that double the per-TB IOPS performance of its drives, which is important for many clients that need to maintain their quality-of-service (QoS) specification, something that is getting increasingly hard to do amid growing storage density. Going forward, Seagate intends to increase the number of actuators, though the company expects to reveal its multi-actuator HDD roadmap in late May, when the company has an event for analysts and investors.

WD plans to split its HDD lineup into High-Performance drives (High-Bandwidth and Dual Pivot) and Power-Optimized drives, each tailored for different data center workloads. High-performance HDDs aim to increase bandwidth and/or I/O performance of a single drive with a roadmap towards 8× bandwidth and 4× I/O scaling.

Among the methods used to increase performance are using more than one head to read or write data at the same time, installing another fully independent actuator on a separate pivot that has its own set of heads, and therefore acting like another HDD. Dual-Pivot HDDs are currently in the lab and are targeted to become available in 2028.

In contrast, Power-Optimized drives target 'active cold' storage tiers, where data must remain accessible but does not require high performance. These drives reduce random I/O activity and are engineered to cut power consumption by roughly 20% to lower operating costs in large-scale deployments while offering predictable performance. Such HDDs will be positioned against 3D QLC SSDs starting in 2027. WDl expects these drives to be used to store massive datasets — such as AI logs and checkpoints — at a lower total cost of ownership.

Summary

The HDD market has shrunk from over 200 drive makers in the 1980s to just three in 2026. These three companies — Seagate, Toshiba, and Western Digital — tend to compete on capacity and performance, but they tend to do so using a completely different set of technologies, even despite the fact that they use some industry-standard components (HDD platter substrates, motors, etc.).

On the technology front, Seagate is all-in on HAMR; the company is already shipping 44TB drives and targeting 100TB-class products in the early 2030s. By contrast, Toshiba is taking a cautious, step-by-step approach, stretching MAMR and mechanical scaling before introducing HAMR later this decade. Western Digital is arguably the most cautious of the HDD makers, pursuing a multi-track strategy, which includes extending ePMR to 60TB, increasing the number of platters per drive to 14, all while gradually ramping production of HAMR-based HDDs, and targeting to launch 100TB+ drives around 2030.

Beyond capacity, both Seagate and Western Digital are also rethinking HDD performance with multi-actuator and dual-pivot designs to boost bandwidth and I/O performance to make HDD-based storage systems more competitive with SSD-powered systems. In addition, WD is also developing power-optimized drives to cut energy use for 'active cold' storage.

In general, 70 years after inception, the HDD industry is alive and kicking. Three companies are competing intensely to achieve higher storage density, higher efficiency, and predictable performance while retaining competitive per-TB cost compared to solid-state drives.

When we reviewed the Steam Controller, we had the chance to sit down with Valve and talk about our experiences using it and ask questions about it.

We talked with Valve programmer Pierre-Loup Griffais and Steve Cardinali, a mechanical engineer on the Steam Controller team, to talk more about the controller's design, the fact that it works only with Steam, and to learn more about how the company is dealing with latency, among many other topics. We published excerpts from this interview in a story alongside the review. Here, we're presenting the full transcript of our conversation.

This transcript has been lightly edited for clarity.

Andrew E. Freedman, Tom's Hardware: So I've been playing around with the Steam Controller. I have questions about why you made some of the choices you did. I also have some questions about the Steam philosophy behind the controller. So I want to get into all those. I think the first thing is, why is now the time to make a controller again? The Xbox controller is widely seen as the default. The PlayStation controller has better PC support than ever. I was just plugging it in for some comparisons and had a whole bunch of PC drivers. Why is now the time for Valve and Steam to get back into the controller game?

Pierre-Loup Griffais, Valve programmer: Yeah, actually, on the PlayStation side, we've been working closely with Sony to enable that stuff and make it work as well as possible out of the box. So we expect the situation to be pretty good there.

In terms of our controller, I think that if you look at efforts like the Steam Machine and the Steam Controller, they're more or less all coming from the same spot, which is we had a bunch of Steam Deck users that were using their Steam Deck in all kinds of different ways, and some of these ways included docking on a TV, right? We got some feedback that while they really appreciated having the same exact experience with respect to like the UI and being able to get in and out of their games quickly and all that, docking a Deck meant missing some of the inputs, right? Like leaving some inputs behind, because you're leaving the Deck on the dock. And so I think the Steam Controller is a great experience for that. You have all the same inputs that you're familiar with. It's pretty much the exact same layout as the Deck, with a bunch of improvements on it, but also just for PC as a whole.

I think the Deck was a great data point on that input scheme working really well to both work for games designed with controllers and games designed without and, you know, take control of your desktop and use a bunch of PC apps and all that. So that stuff's been looking really good. And so making a controller, you know, as a standalone version of those same inputs, I think, is a logical next step there.

Freedman: One thing I was very surprised about when I first plugged the Steam Controller in, was that the setup flow really is pretty minimal, right? Update your firmware, here's how to enter Big Picture Mode, and off you go. And I think in many ways, to get the most out of the controller, it had me digging deeper in Steam Input than I think I admittedly ever have before. Did you ever consider having more sorts of teaching moments about Steam Input for newer users? Or did you just kind of kind of assume people would sort of dig in as needed?

Steve Cardinali, mechanical engineer on the Steam Controller team: You know, we wanted it to be out of the box, easy to use for people who maybe just want a controller that works like a controller and how they would expect, so that you're seeing that element there, of course. And a lot of thought went into that process. But on top of that, in developing this controller, and along with the original Steam controller in the Steam Deck. A lot of work has gone in Steam Input, like you're saying. And there's a lot, a lot there. And one of the things that the controller team is working on right now is actually a couple rounds of how-to tutorials on like how to set up your track pads in these certain ways, and the ways that we find work best; how to set up gyro; different input mappings' and layouts that we have found success with to get people started to get exposed to Steam Input and all the power it has behind it without being too overwhelming.

Griffais: It's really important to us that if you don't want to deal with any of that stuff, you don't have to, right? That the surface level experience gets you controller compatibility in games that are meant for controllers without any sort of tinkering. So the Steam Input stuff is there if you want it, but we don't want it to be a required element to just experience the baseline functionality there.

Freedman: Was there ever consideration for instance, the way Steam Deck had a game, I'm blanking on the name.

Griffais: Aperture Desk Job.

Freedman: Right. Was something like that ever a consideration for people who hadn't used the Steam Deck before or maybe might be considering this for the first time on a desktop or eventually, a Steam Machine? "Hey, here's how you get used to the input."

Griffais: Actually, I think that — and this might still be a conversation that's ongoing — but there were some conversations here about making Desk Job work well with the controller as well, because 99% of what you get through Desk Job is actually controller functionality. There is one step, I think, where it teaches you to use the touchscreen on the deck and maybe a microphone, and so I think we were thinking about making some adjustments so that it could be used just with the Steam Controller on a PC to teach you the same elements around motion controls, trackpads and all that that, you know, it walks you through. I'm not sure where those discussions are, but I think that was in the cards at some point.

Freedman: That's really interesting. So speaking of features and functionality, I happen to be playing a lot of Resident Evil 9 on my Steam Deck, and transitioning to the Controller felt very much like playing on my Steam Deck. I'm pretty sure that's the goal. When you were deciding to make a controller out of the Steam Deck, how do you decide which features from other controllers and the Steam Deck to include?

You have some from a lot of what you might consider more "basic" controllers, right? You know, your face buttons, things like rumble. Then you have things that you might consider from "elite" style controllers, for lack of a better term, right? Back buttons, gyro. So how did you decide that "OK, we're going to do back buttons, but we're not going to do replaceable thumb sticks, or we're not going to do replaceable back paddles." Where do you sort of decide?

Cardinali: Sure, yeah. For the controller, at least, it was, I wouldn't say, straightforward, but we had the guiding principle of Steam Deck users who get this controller, it should feel very similar. And it shouldn't be like a bunch of new stuff in their face that they have to then go and to the Input layout configurator and change settings, right? We wanted it to be natural. You're playing a game on your Steam Deck, and you go sit on your couch. You play it on Controller, it feels similar. So that helped us kind of keep the feature set down to what we had in Steam Deck.

The one main thing that kind of crept in that you probably have noticed or heard about is the Grip Sense. We're always trying to highlight new ways that you can play mouse and keyboard games — like competitive mouse and keyboard games — with a controller. The original Steam Controller did a great job of that, and then we carried over those trackpads and gyro over to this new controller. But as the gyro community becomes more and more prevalent, they do all sorts of things to enable and disable gyro for ratcheting. And we wanted to put something in there for them, for that community, to make sure this supports them in a competitive style as well. So that one kind of snuck in there, because we feel like that's an important feature for those kinds of games. Everything else is like. We didn't want to overburden the product with too much additional cost, or weight, or battery consumption. We wanted it to be a great controller for everybody. So we tried to really focus in on what we thought was the core, important feature set with this, you know, extra bonus in there.

Griffais: Yeah, some of these questions apply to the design of the Steam Deck too, right? Like, how did some of these inputs get in there? And what did not get in there? I think, like Steve said, every time we look at an input, we're conscious of overburdening the user. Like, having too many inputs is really not something that we want to see. And you know, the cost, the weights, everything comes into play there, But for for the back buttons in particular, I think we saw pretty early, including the first Steam Controller, that we had a bunch of players that felt limited in what they could do while manipulating the camera. And we thought it was really important to have all the functions in the game still available while you're fine-tuning the camera. We saw a bunch of users use claw grip to counteract that, right, where you're using your thumb and your index fingers to still have access to the diamond buttons, even though you're fine-tuning the stick. And we thought back buttons was a really good solution to that. So on the Steam Deck, you know, the four of them tested really well, and they weren't too invasive, right? Like, they're disabled by default. They're just part of the grip. You don't really have to think about it.

Freedman: Right.

Griffais: Grip sense is a similar thing, right? Like, it's, it's in because it doesn't really change how you have to approach the controller if you don't really use it. And so it's, it's this easy, additive thing that doesn't perturb things that way. It and is, is really, easy for us to — well, I mean, it's not that easy. There's a lot of considerations there. But it was doable, I guess, to put it in while retaining the whole feature set and not compromising the rest of the, you know, the core principles around the controller there, which are, first and foremost, have all the inputs that you would expect from regular controllers in the place that your fingers expected. Which is something that was really important for us on the Deck as well. So that the diamond buttons, the bumper trigger, the analog sticks all kind of fall into place, and then all the extra inputs are there if you need them, just like the software features for configurability.

All-new TMR sticks

Freedman: The other big addition you didn't mention is the TMR joysticks. That didn't make it into the Steam Deck or the Steam Deck OLED. So why was the controller the right place to start?

Griffais: I think the answer there is that we tried seeing if the TMR sticks would work in the Deck, right? And it was a little bit early for that. I think the technology was nascent, and the vendors there were, you know, new into the market, but we tried to see if it would have made sense for the Deck, for the Deck OLED, and, you know, we were looking at it. And so, I think, in the Steam Controller timeframe, it was just ready enough that it made sense. But I think we've seen the value around it from the get go, we tried to make it work pretty hard.

Freedman: Were there any sort of technical discussions on using TMR versus Hall effect when you're designing it?

Cardinali: You know, it primarily came down to which version of the technology we were most comfortable with using, which felt most mature and ready for us to use. But, you know, TMR, it has all the same pros as Hall effect, but the extra benefit it has is that it has lower power consumption. So that's like a huge benefit for why we went down that path, right? We don't have to eat as much battery life when using these new sticks.

Freedman: Why not put a headphone jack for passthrough audio on the controller? You're on the couch, you might want to be chatting. Why not? Why leave that one off?

Griffais: It's a hard one. I mean, it's just very, very hard to productize, like in terms of the audio bandwidth and the additional cost and complexity in the system design. I think it's something we evaluated, and then we looked at all these other features, and we focused on that instead. No, it's not to say that we don't see the value there. So it's more than it didn't make the cut this time around. Because, you know, the other things were more important when it came down to prioritization.

Connectivity

Freedman: Let's talk about the Puck. I have never seen a dock for a controller that wasn't huge before, right? It's always a big stand. So at what point did it come about that you were going to turn a 2.4 GHz wireless solution into a charger? Because it's made it hard for me to get the best battery life, because it's so easy for me to just take it and put it down and walk away and think, "Oh, I put it in the natural spot."

Cardinali: Yeah, well, we did our job then, right? [Griffais laughs] I mean, that was, that's honestly primarily one of the reasons, right? We knew we wanted a proprietary wireless connection, just to make sure that we had a robust, low-latency connection, and we can control the end-to-end conversation so that we can guarantee performance. But it's a hard thing to ask customers to have a little dongle and, like, plug it in somewhere. And then a lot of people solve that problem by having a dock, which adds extra value, but from our perspective, we wanted to minimize the burden to the desk. Right? Your desk base, some people have small desks. A big dock can take up a lot of space.

And the Puck itself — We know there's an active community of makers that use our products, and we have people internal [sic] who have designed and printed their own little mounts that hold the puck as a full dock. And we expect people to do stuff like that with this, and keeping it small allows people to do that without kind of over-prescribing how they design it and use it around it. And then it has the added benefit that it has this nice, satisfying little click when you put it over, it snaps into place. You don't have to worry about plugging it in. It kind of came about just because we knew we needed that connection. We were trying to solve problem with getting away from your PC, as well, with wireless interference. Just kind of popped up out of all those. How do we make this a good user experience.

Freedman: Speaking of connection, you recommend Bluetooth 5 or higher. How did you combat latency here? And you have a 250 Hz polling rate. We are seeing some things go up to 8,000 Hz. For me, I can't tell the difference. How do you settle on what type of connection to use to reduce latency?

Griffais: In terms of what we're working back from, it's very much the actual experience, right? So we're looking at the polling rates of the internal components and what they're actually able to report their updated data. Every component there that has analog data or digital buttons, has different performance characteristics when it comes to how quickly you can poll them from the MCU [microcontroller unit] and the trackpad, and the analog triggers. And analog sticks are all going to have different characteristics. But we wanted to make sure that we weren't leaving anything on the table where the transport, like getting the data to the PC would actually, you know, gatekeep, limit. any of the core potential of those parts. So that's kind of how we picked our core update right there, which I think, you know, is pretty high-performance. There's a lot of updates there.

But then, when we look at the transport, we think we got to a pretty good place with Bluetooth, right? Where Bluetooth, if you have one controller connected, the performance is actually pretty comparable to what you would get over our direct link using the Puck, right? But as soon as you add more controllers into the picture, that's where the limits of Bluetooth start showing up. So if you have two controllers over Bluetooth, the latency is actually doubled, and then it keeps going like that, right to the point that it becomes very noticeable, even for people that are not looking for that kind of stuff. So the custom protocol there, when you use our Puck, lets you have up to four controllers on one puck with no latency hit, which we're really excited by. But at the end of the day, the latency we're working back from is the core performance of the actual parts in the in the controller.

The Steam Ecosystem

Freedman: I want to ask more about the philosophy of the controller within the Steam ecosystem. The controller only works through Steam, right, on Windows, on macOS, if you're not in Steam, it's seen as a USB mouse. I plugged it into a PlayStation and it's seen as a USB mouse. Why not have it so that it works more widely outside of Steam even if Steam would actually still be the best place to use it?

Griffais:, I guess there's a couple dimensions to that. I guess one thing that I must point out before continuing this answer is that on Linux, we have made a built-in driver that is actually in the Linux kernel that lets you have gamepad functionality without needing Steam running. So it's kind of a baseline level of support. There's no analog to other platforms right now. So like, like you said, on Windows, macOS, or any other computer or computer-shaped object, it's going to be in default operation of, you know, being a USB mouse and keyboard composite device where you can use it to mouse around, to use arrow keys, escape, enter. You know, have basic control over your device there.

But the the main thing to keep in mind is that to be a controller, like a PlayStation controller on PlayStation or an Xbox controller on a Windows PC, you have to go through the driver framework for those controllers, and the licensing program for those controllers. Essentially, if you want to work out of the box as a PlayStation controller, you have to be a PlayStation controller, right? And so there's a bunch of stuff in a Steam controller that is kind of its own thing. And so there's not really a set precedent for having custom controllers with extra inputs that are not just aliasing buttons over standard controllers, or just doing things that don't require, you know, those extra software features to be registered using the standard driver. So then you'd end up in a spot where you have, you know, maybe a button to switch modes, where you're either in PlayStation mode, or you're in the full mode. And then, you know, the burden of trying to, like, the complexity of trying to navigate that and added cost to have those different mode of operations, and the added parts would, we think, not be worth it for the end user there.

That being said, we're pretty happy we're with where the ecosystem is. Adding games to Steam is pretty easy. We keep making it easier and easier on SteamOS, you can just right-click any installed app and say, "add to Steam." And then from that point on, you're good to go. You can assign a custom configuration to it, and it's pretty easy on other operating systems as well. So I think getting the full feature set there is possible on the whole catalog, even non-Steam games and standalone apps outside of Steam. But for sure, it comes with the kind of trade-offs when it comes to first-time setup that you enumerated.

Freedman: One of the first things I felt like I had to do once I had used the Steam Controller in Steam was that I gotta play Fortnite with it. Because that's very famously only available in one place in the PC ecosystem. And I was able to do that, but one of — I think it was one of the joysticks wasn't working as expected. Has there ever been a thought of, like, can we get this working at a baseline on other launchers, or is that just like so far down the pipe, because you can add other games to Steam?

Griffais: It's definitely something we think about, and we get feedback along those lines. I think right now, we are trying to make it as easy as possible to get it working through Steam, including adding other things through Steam. But it's possible, you know, in the future, it's something we'll look at with a different approach there. But I guess we're limited in what we can do with things like core operating system drivers and such, right?

Like Xbox controllers have built-in support within Windows itself. PlayStation controllers have a driver that they work with Microsoft on. So it's, you know, it would be quite a bit of a different method of supporting it to try and go with those ways. I think we'd rather just make it as easy as possible to get it added to Steam so you can benefit from that functionality without needing any sort of kernel driver that would potentially, down the line, cause system instability or things like that.

Like we're really, we're really happy with not having a kernel driver, because it comes with the onus of not messing it up, right? And so right now, the current method of supporting the controller is pretty safe.

Launching before the Steam Machine and Steam Frame

Freedman: The Steam Controller is launching ahead of the Steam Machine and the Steam Frame? How has that changed launch for you? It kind of feels from history that people are used to controllers launching alongside consoles. That there should be a specialized box that it controls. Obviously, it works great on other things. I've used it on a Steam Deck. I've been using it on my rig. But how has that changed the launch and how you're looking at messaging with the controller?

Cardinali: I was gonna say it really hasn't. Because from the get go, the controller wasn't just something we saw as only a Steam Machine controller, right? It is, first and foremost, a PC controller. It's going to work great with your Steam Machine. It's going to work great with your Steam Deck, but on your Windows, or wherever you have Steam, it'll work great as a Steam Controller. And essentially, you know, we had, we had thought at some point maybe they would launch together, depending on how the timing lined up. But it was never a constraint internally that it's something we had to do, because we saw them truly as two separate products that work well together, but they're their own things.

Griffais: We expect a vast majority of users will be on PC, right? There's so many people there that might be in demand for a controller. And so I think that was always our priority from the get-go.

Griffais: You can definitely draw a line between the first Steam Controller and this one in terms of development features and philosophy. Like you said, though, the first Steam Controller was more of a peripheral for PCs to play PC games, whereas this controller is more a normal controller, first and foremost, And then it adds some of the same features that let you play PC games with the first Steam controller. So a lot of it is actually working back from the feedback that we got on the first Steam Controller, where people appreciated the features that let them play their PC games, the mouse controls and all that. But they, instead of, switching between a Steam Controller when they're playing PC-only games and an Xbox controller, they wanted something that did both.

And so when we designed the controls of the Steam Deck, we very much were implementing that feedback and made sure, like we were saying before, to have a standard controller, you know, and with all of its inputs in all the spots that your hand would expect it. And so that was a that was a pretty core design principle there that followed us from the legacy of the first Steam controller. So all the extra features are there, but also, you know, the knowledge of the desire that people just want a device that does all of those things.

Ergonomics

Freedman: One thing that surprises me about this, given how many things are packed into it, how do you work to make it feel good in the hand? I mean, it's very it's ergonomic for what it is. I expected, after an extended period of time, I would find issue with, "oh, you know, you have, the touchpads down here," or, you know, where the back buttons are, anything like that. How do you sort of fit all that into something so ergonomic?

Cardinali: A lot of prototypes, a lot of prototypes. Like, we spent an entire year for this controller just thinking about ergonomics, and how do we take the Steam Deck inputs and put them in a controller in a way that's comfortable, doesn't feel too big in people's hands, especially people with small hands, and feels good in people with big hands, right? A lot of internal testing, we brought in external people to come get their hands on functional prototypes. I mean in terms of functional prototypes, before we even, like, locked the ergonomic design, we probably made 30-plus functional controllers that people could play games with.

Many of them were just different iterations on the trackpad alignment and, like, the direction orientation. The first inception. They were just square, and just like, aligned with the system, like it is in the Steam Deck, versus "clocked and canted," as we lovingly call them now. That took a lot of work to land there and a lot of testing, because with something with this many inputs, you really have to spend time and do the due diligence to make sure that it's going to be comfortable for the majority of people.

Griffais: Yeah, just like the Steam Deck, ergo was pretty much at the top of the priorities list when we're designing things. So things like making sure it's comfortable, definitely above, you know, the cosmetics around it, right? So we got the feedback a ton that Steam Deck looks bulky and uncomfortable, but then once you hold it, it feels great, right? Then, I think that's very much a result of that. Unfortunately, we didn't find a way to make it feel great and also look great. But you know, there's, there's always next one.

Component shortages & tariffs

Freedman: There's been a lot of questions about the rest of the Steam hardware lineup because of things like component shortages and tariffs. How has that affected the Steam Controller? Has that affected the $99 pricing or the timing of its release?

Griffais: Yeah, it has definitely, it's definitely affected it. I think [that] our price reflects the reality of building the product and getting it to customers at the real cost that we can make it with the reality of today's economics and, you know, dynamics. So for sure, there is things like tariffs included, depending on the region and so on.

But that being said, like for something like a controller, the current conditions, with all the memory shortages and all that, don't really affect it that much, it would have been way worse during Covid. Like during Covid, there was a microcontroller shortage, the same kind of microcontrollers that you use in a controller like that. But that's really not a problem right now. So I would say for the controller itself, it's more things like import duties and shipping costs rising because of current conditions that would affect it. So it's not as much as it would, you know, a big PC product with lots of memory in it, but it's definitely affecting it.

Freedman: And you guys definitely have experience shipping PC products during Covid.

Griffais: Unfortunately, yeah. I mean, it seems like whenever we decide to launch a product or some kind of worldwide, global condition trying to prevent us from doing so, but we've been persisting.

Freedman: Given the current situation in which you've built and priced the controller, was there anything — any features — that you had to consider taking out of the controller to make it price-efficient?

Cardinalli: I mean, those conversations happened way earlier on in development of the program, so nothing that kind of came about in the past, call it year, really affected any final feature decision, right? Those were made way earlier.

[Interview ends]

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

The Dutch company holds a 100% monopoly on EUV lithography and approximately 83% of the global lithography market overall, and its roadmap now spans four distinct generations of technology: DUV immersion systems that still handle the majority of layers on every advanced chip, low-NA EUV scanners that enabled the 5nm and 3nm era, High-NA EUV tools now entering early production at Intel and Samsung, and a Hyper-NA concept that remains in feasibility studies for the 2030s.

Each step up this ladder delivers finer resolution at exponentially higher cost and complexity, and just how aggressively the industry's largest chipmakers adopt each generation will determine the pace of transistor scaling for the next decade and beyond.

DUV immersion and low-NA EUV

ASML's DUV immersion systems are still the backbone of semiconductor manufacturing when it comes to volume production. The company sold 131 immersion DUV tools in 2025. Even a chip built on TSMC's 3nm node uses EUV on only a handful of critical layers; the majority of patterning steps still run on DUV immersion tools like the TWINSCAN NXT:2100i, which delivers 295 wafers per hour at 1.35 NA with 1.3nm overlay.

DUV single-exposure is also the standard in mature nodes powering automotive and industrial chips. While DUV multi-patterning can push down to 7nm and even 5nm, it comes at an enormous cost of up to 34 patterning steps at 7nm versus nine with EUV.

Chinese customers purchased an estimated 70% of ASML's DUV immersion systems in 2024, stockpiling ahead of tightening Dutch export restrictions that now cover the NXT:1970i and newer models. SMIC demonstrated 7nm production using DUV multi-patterning for Huawei's Kirin 9000S, according to TechInsights. But the process requires significantly longer cycle times than EUV-based production, and questions exist around whether yields are sufficient for volume commercialization.

On the EUV side, ASML's low-NA systems operate at 0.33 numerical aperture with 13.5nm wavelength light, achieving 13nm single-exposure resolution. The TWINSCAN NXE:3600D, introduced around 2021, delivers 160 wafers per hour with 1.1nm matched-machine overlay. Its successor, the NXE:3800E, began shipping in March 2024 and pushes throughput to 195 wafers per hour, upgradable to 230 — following ASML's recently updated roadmap — while tightening overlay below 1.1nm. Each NXE:3800E costs roughly $180 million. It shares its bottom module, including wafer handler and faster stage mechanics, with the High-NA EXE platform, a decision that reduces ASML's manufacturing complexity and provides fabs with a degree of serviceability continuity when they upgrade.

ASML's roadmap extends low-NA further, with the NXE:3800F expected around 2027. It targets a ≤0.9nm overlay and over 260 wafers per hour. A subsequent NXE:4200G targets a ≤0.8nm overlay and over 300 wafers per hour, with an NXE:4200H beyond that at a ≤0.7nm and 330 wafers per hour. Further out, ASML has disclosed a High Productivity platform, the NXE:4600, targeting 400 wafers per hour or more.

TSMC has confirmed that it will not use high-NA EUV for its A16 (1.6nm) or A14 (1.4nm) nodes, instead relying on low-NA with multi-patterning. Kevin Zhang, TSMC's Deputy Co-COO and Senior Vice President of Business Development, said at the company's European Technology Symposium last May that TSMC would adopt high-NA "whenever we see high-NA will provide meaningful, measurable benefit," adding that the technology team continues to extend the life of current EUV.

Computational lithography is one reason low-NA can stretch further, with ASML's Brion subsidiary developing inverse lithography technology and curvilinear mask optimization software that computationally corrects for optical distortion beyond specification, effectively squeezing better resolution from existing 0.33 NA optics without hardware changes.

TSMC has been a major user of these techniques, and their continued advancement narrows the gap between low-NA double patterning and High-NA single exposure. ASML's installed base management business, which services and upgrades the global fleet of lithography tools, reached €8.2 billion in revenue in 2025, up 26% year-over-year. That recurring revenue stream grows with every tool shipped and is increasingly important as fabs push older systems to higher utilization rates.

High-NA EUV

The jump to 0.55 numerical aperture with high-NA is the largest optical leap in EUV's history, shrinking minimum resolution from 13nm, which itself was down from 30nm with DUV, to 8nm and enabling approximately 2.9 times higher transistor density in a single exposure. ASML's first High-NA tool, the EXE:5000, shipped to Intel in December 2023 as a development platform.

Each unit of the production-capable EXE:5200B weighs in at 150,000 kilograms, requires 250 shipping crates, and takes six months and 250 engineers to assemble on-site, says Intel. Priced at approximately $380 million, the EXE:5200B delivers 175 wafers per hour at 50 mJ/cm² dose with 0.7nm overlay. ASML told Reuters in early 2024 that it had taken 10 to 20 orders by that point and planned to deliver 20 annually by 2028.

Intel announced that it had completed acceptance testing of its EXE:5200B in December 2025 at its Hillsboro D1X fab and that the tool will be used for the development of Intel's 14A fabrication process. 14A is expected to be the first production node to rely on High-NA for its most critical layers, with risk production targeted for 2027.

In September, SK hynix became the first memory manufacturer to install a commercial High-NA system at its M16 fab in Icheon, South Korea. Samsung, meanwhile, received its first EXE:5200B in October, with a second unit due in the first half of 2026 for its 1.4nm foundry node. Imec, the Belgian research institute, secured an EXE:5200 last month with a Q4 2026 qualification target for sub-2nm process development.

ASML's near-term High-NA roadmap includes the EXE:5200C, targeting 190 wafers per hour without stitching and 160 with stitching at sub-0.8nm overlay, followed by the EXE:5200D at 195/175 wafers per hour and eventually the EXE:5400E at 210/180 wafers per hour with sub-0.7nm overlay. A High Productivity variant, the EXE:5600, targets 250 wafers per hour or more.

Analysts from SemiAnalysis believe TSMC won’t adopt High-NA EUV until its 1nm-class A10 node, which would place volume deployment around 2029 to 2030, because existing low-NA EUV systems can match High-NA's 8nm resolution using double patterning, and SemiAnalysis estimates that approach may still cost less than High-NA single patterning. High-NA tools also require substantial changes to existing fab buildings to accommodate their size.

Hyper-NA and pellicles

ASML placed Hyper-NA on its official roadmap for the first time at imec's ITF World in May 2024, with former CTO Martin van den Brink commenting a few months prior that an NA above 0.7 "is certainly an opportunity that will become more visible from around 2030." The primary target is 0.75 NA, with 0.85 NA also under investigation. Zeiss has begun preliminary lens designs. Estimated tool cost: roughly $720 million per system, according to TrendForce.

At 0.75 NA, however, polarization effects begin destroying imaging contrast because one polarization orientation effectively cancels light at extreme incidence angles, thereby necessitating the use of polarizers that block photons and reduce efficiency. Depth of focus shrinks further, and resists must be made even thinner than the sub-30nm films used for high-NA, worsening etch selectivity and stochastic defects from photon shot noise. On top of all that, an electron blur of approximately 2nm may impose a solid resolution barrier regardless of optical improvements.

Pellicle development is another bottleneck. These ultra-thin membranes protect masks from particle contamination during exposure but must transmit EUV light efficiently at rising source power levels. ASML's current composite silicon-based pellicle achieves over 90% transmission at 380 W source power, but for future systems running at 600 W to 1,000 W, carbon nanotube pellicles are the next-gen technology, achieving up to 97% transmission while withstanding temperatures above 1,500 C. Mitsui Chemicals is building dedicated CNT pellicle production capacity targeting 5,000 sheets per year and commercialization aimed for this year.

Export controls and Canon NIL

EUV systems have never been sold to China, blocked since 2019 under U.S. pressure despite existing orders from Chinese customers. In addition, Dutch export controls, effective since late 2023, required licenses for advanced DUV immersion systems (NXT:2000i and newer), and by September 2024, the restrictions expanded to include the NXT:1970i and NXT:1980i.

Servicing restrictions also prohibit ASML from improving overlay accuracy or increasing throughput by more than 1% on installed Chinese systems. China represented 49% of ASML's revenue at the peak of stockpiling in Q2 2024, falling to roughly 36% for full-year 2024. ASML's management guided China to approximately 20% of revenue in 2025 and 2026, which has seen South Korea and Taiwan emerge as the primary growth markets, with SK hynix alone placing a record $7.9 billion EUV order last month covering roughly 30 systems over two years.

Canon's FPA-1200NZ2C nanoimprint lithography system, announced in October 2023, represents the only credible alternative patterning approach. At roughly $15 to $20 million per system with 90% lower power consumption than EUV, it uses direct mechanical pattern transfer rather than optical exposure. Canon delivered the first commercial unit to the Texas Institute for Electronics in September 2024, and its current specs show some significant limitations: 80 to 100 wafers per hour (versus 195+ for low-NA EUV), 14nm minimum linewidth, and 2.4 to 3.2nm overlay (versus sub-1.1nm for EUV).

Japan's Dai Nippon Printing (DNP) is targeting 2027 mass production of 1.4nm-class nanoimprint templates, but no major foundry has committed to NIL for high-volume logic manufacturing. The technology's likely niche remains repetitive memory patterns, particularly high-layer-count 3D NAND, where its cost advantage could outweigh the throughput and overlay penalties. Defect density from direct physical contact between template and resist remains the fundamental barrier to logic adoption, where a single misplaced particle can kill an entire die.

ASML revenues continue climbing

ASML's 2025 results reflect the sheer scale of its roadmap, with €32.7 billion in revenue (up 16% year-over-year), 52.8% gross margin, and €9.6 billion net income. EUV became the leading source of system revenue at 48%, or €11.6 billion, up 39% from 2024. Net bookings surged 48% to €28 billion, with Q4 2025 alone delivering a record €13.2 billion in orders. The company recognized revenue on two High-NA systems during the year.

ASML's Q1 2026 results, published April 15, show €8.8 billion in total net sales at 53% gross margin, with €2.8 billion net income. The company shipped 16 EUV and 17 immersion DUV systems in the quarter, with South Korea accounting for 45% of system sales by region and China at 19%. ASML raised its full-year 2026 revenue guidance to €36 to €40 billion, with 51% to 53% gross margins

Each NA increase delivers diminishing resolution gains at exponentially rising cost and complexity. The most likely trajectory is not a clean generational handoff but an extended coexistence: low-NA handling the bulk of EUV layers well into the 2030s, High-NA reserved for the most critical pitches at sub-2nm nodes, and Hyper-NA arriving as a targeted tool for the most extreme features, subject to workarounds for the bottlenecks we’ve discussed above.

TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology has become the de facto standard packaging method for advanced AI and HPC processors that use HBM memory, thanks to TSMC's aggressive development of the technology. Unlike lateral 2.5D CoWoS, TSMC's vertically integrated System on Integrated Chips (SoIC) technology with 3D interconnects has not been adopted as widely. However, now that the company has overcome the first generation's constraints, it will aggressively develop this technology in the coming years, as the company revealed at its recent North American Technology Symposium.

Different kinds of stacking

TSMC's 3D stacking SoIC technology has always been somewhat of a backburner project for TSMC, as it gained support for new process technologies slowly, when compared to CoWoS. From a pure interconnection pitch point of view, TSMC offered a rather fine 9 µm pitch in 2023, which was good enough to enable products like AMD's Instinct MI300-series. However, the 1^st generation SoIC had one major limitation: it only supported face-to-back (F2B) stacking, but not face-to-face (F2F) stacking, which is supported by the 2^nd generation SoIC technology. In 2025, TSMC achieved 6 µm pitches and expects the pitch size to decrease to 4.5 µm by 2029.

Face-to-back stacking imposes fundamental limits because signals cannot travel directly between dies. Instead, they must cross multiple metal layers and pass across through silicon vias (TSVs) in the bottom die, which increases latency, power consumption, and routing complexity.

In addition, this limits how densely connections can be implemented, since TSVs are relatively large structures that cannot be placed at fine pitch across active logic regions without affecting transistor density and design considerations. According to Broadcom, a real-world design using face-to-back stacking can achieve 1,500 signals/mm² with TSVs.

By contrast, face-to-face stacking removes the indirect signal path by aligning the metal layers of two dies directly and connecting them using hybrid copper bonding. This enables straight, ultra-short vertical interconnects without relying on TSVs, which increases signal density by an order of magnitude to 14,000 signals/mm², which therefore increases bandwidth, reduces latency, and cuts energy usage per bit.

As a result, communication between stacked dies resembles on-die wiring rather than chip-to-chip links, which is why companies like Broadcom view it as a crucial capability to scale compute density for next-generation AI and HPC processors.

3D packaging acceleration

Now that TSMC can do both F2F and F2B stacking, development of the technology will proceed much faster than before. The company now touts the usage of N3P dies on top of N4 dies, expects N2P on top of N3P within the next year, N2P on top of N2P by 2028, and envisions 3D stacked A14 dies by 2029.

Notably, the company hasn't demonstrated any process technologies with a backside power delivery in its SoIC roadmap. Yet, TSMC SVP Kevin Zhang reassured us that these nodes can support 3D integration as well.

"That may just be a simplification in the slide, A16 will have stacking capability," said Kevin Zhang, TSMC's Senior Vice President of Business Development and Global Sales, and Deputy COO.

"The SoIC roadmap shown does not cover all possible combinations — there are many permutations. The key takeaways are twofold. First, pitch scaling — from 9 µm to 6 µm, and eventually down to 4.5 µm. Second, the acceleration of stacking timelines. In the past, for example, you might stack N3P on N4, since the base die with TSV takes time to mature — 3nm TSV is only expected around 2027. But looking ahead to 2029, A14 TSV becomes available just one year after initial production. That shows how we are accelerating the schedule, enabling customers to stack the most advanced dies on top of each other much sooner."

The first face-to-face 3.5D designs

Being a leading developer of custom processors for hyperscalers, Broadcom is among the main users of TSMC's CoWoS and SoIC packaging technologies. Broadcom builds some of the world's largest system-in-packages, so it is not surprising that it is also among the first to use TSMC's F2F SoIC technology to build Fujitsu's Monaka supercomputer CPU.

On a high level, Fujitsu's Monaka processor is a heavy-duty general-purpose data center processor, and uses 144 Armv9 cores, spread over four compute chiplets made on TSMC's N2 technology, deploying a stacked face-to-face (F2F) atop dedicated SRAM chiplets (implemented on N5 technology) using hybrid copper bonding (HCB), equipped with a comparatively large I/O die that integrates the processor's memory controllers and PHYs for 12 DDR5 channels. Fujitsu's Monaka also features PCIe 6.0 connectivity with CXL 3.0 support for accelerators and memory expanders, as well as other interfaces expected from a modern data-center-class CPU.

Stacking N2-based CPU chiplets atop N5-made SRAM chiplets enabled Broadcom and Fujitsu to add massive amounts of cache to Armv9 cores to maximize their single-thread performance relatively cost-efficiently, but at the price of additional complexity and challenges surrounding thermals. Due to this, Broadcom and Fujitsu do not stack logic-on-logic, and it remains to be seen when TSMC's clients will actually start to use this option.

Broadcom is currently sampling Monaka with Fujitsu and aims to volume produce the CPU in 2027. Notably, while the company uses hybrid bonding, it also uses 9 µm pitches, which indicates that even innovators like Broadcom are cautious about using the latest versions of 3D integration technologies. This is in stark contrast to CoWoS, as TSMC's clients are eager to use the latest versions of the technology to build bleeding-edge processors.

Nonetheless, TSMC clearly positions its SoIC 3D stacking as a way to increase compute density, so it clearly has reasons to expect this technology to be used widely. After all, if transistor scaling is slowing down, packaging is inevitably becoming the scaling engine.

Nvidia’s RTX 30-series graphics cards made a big splash when they began arriving all the way back in 2020. Those products delivered a huge performance leap in their day, but time marches on for us all. The oldest Ampere cards are just a few months away from their sixth birthdays, and even though Nvidia has continued to support 30-series cards with its latest Game Ready driver optimizations and DLSS model upgrades, other signature GeForce features like DLSS Frame Generation are never coming to Ampere.

Even where new software features are technically supported, Ampere comes with big asterisks. DLSS 4.5 is the first upscaling model to take advantage of FP8 acceleration that’s exclusive to RTX 40- and 50-series Tensor Cores. RTX 30-series cards can still technically run DLSS 4.5 upscaling models, but the improved image quality they offer now demands a significant performance penalty from Ampere compared to past DLSS versions. And if you want to experiment with frame generation, you have to deal with the lower image quality of AMD’s cross-platform FSR 3.1 framegen tech, assuming it’s available at all in a given title.

Those software limitations aren’t insurmountable obstacles to a good gaming experience, but VRAM is a different story. Ampere cards arrived when games were less hungry for VRAM than they are today, and even the RTX 3080 has just 10GB to play with. Unless you bought into the highest end of the Ampere range, you’re likely feeling constrained by your card’s 8GB of VRAM with max settings in the latest games at resolutions higher than 1080p.

If any or all of those limitations have you itching for a more powerful, more flexible modern GPU, and you’d rather not navigate our GPU Hierarchy to figure out what constitutes a true upgrade, worry not. We’ve done the hard number-crunching work and thought through the most common gaming scenarios to arrive at the best upgrade path for each common Ampere card.

So what defines an upgrade for the purposes of this guide? First and foremost, we want to see at least a 1.5x improvement in overall raster performance from GPU to GPU as a baseline, and larger leaps are even better. The architectural advances of Nvidia’s latest Blackwell GPUs naturally mean you’ll enjoy improved RT gaming performance from our picks, as well.

Whatever your individual feelings for upscaling and framegen might be, you’ll enjoy greater freedom to play with DLSS 4.5 and MFG on the latest GeForces. Our path-traced performance results with Pragmata illustrate why you should use those features to the fullest, but it’s ultimately your choice. All told, raster gaming performance boosts still matter most, so that’s our hard line.

If you’re already in the Nvidia fold, we expect that you want to stay there, so we’ve made our picks assuming as much. But where a given Radeon card might make sense, we’ve included it as a suggestion if you’re open to switching.

Monitoring the situation

Before we talk about specific upgrade paths for your GPU, we need to take a moment and consider the monitor you’re using with it. If you only have a 1080p or 60Hz monitor, a fixed-refresh-rate panel, or all of the above, your graphics card likely shouldn’t be your first or only upgrade. It’s overwhelmingly likely that you won’t enjoy a perceptibly smoother or lower-latency gaming experience on a 60Hz monitor than you currently do with the graphics card you already own.

The continuing development of high-quality upscaling tech means that monitor resolution is no longer a hard wall for gaming smoothness and responsiveness. Instead, it’s a hard cap on the image quality you can achieve. To get the most out of DLSS (or FSR), you really want to give those upscalers the highest output resolution and highest refresh rate to work with that you can. Upscaling from lower resolution to 1080p just isn’t worth it anymore unless you absolutely must, while upscaling to 4K using DLSS 4.5 Performance requires only a small frame-rate penalty relative to native 1080p output.

Along with more and more affordable OLED options, we’re seeing plenty of dual-mode monitors that can offer high-refresh-rate 4K output alongside even faster 1080p modes for downright affordable prices. And broadly compatible variable-refresh-rate tech is now in virtually every gaming monitor, so you can likely enable G-Sync or G-Sync Compatible modes with the GPU you already have.

Best of all, displays are one of the few PC gaming products that don’t rely heavily on advanced logic chips or DRAM to work, so prices for gaming monitors have remained reasonable even as everything else has gotten eye-wateringly expensive. If your monitor is older than your Ampere GPU, it’s likely high time for an upgrade. Start there first.

RTX 3080 Ti, RTX 3090, and RTX 3090 Ti: Wait for a compelling upgrade

If you’re one of the lucky gamers with an RTX 3080 Ti, RTX 3090, or RTX 3090 Ti, you can rest easy knowing that your graphics card has plenty of life left in it. Any upgrade right now is elective rather than essential, especially if you’re already using DLSS upscaling. The RTX 3080 Ti’s 12GB of VRAM is the only conceivable pain point we can see in this upper tier of Ampere.

The only cards that are likely to feel like major upgrades for you are the RTX 4090 or RTX 5090, and unless you’re willing to compete with local LLM trailblazers for a used 4090 or put down nearly 2X MSRP for a new 5090, your best bet is to hold onto your current card unless you’re really feeling limited by its ray-tracing or path-tracing horsepower, the lack of FP8 Tensor Core acceleration for DLSS 4.5, or the lack of high-quality framegen support.

If you’re only gaming, 24GB of VRAM isn’t doing much for you, and you might ponder selling your RTX 3090 or 3090 Ti to one of those same LLM enthusiasts while the market is hot and putting the proceeds toward a new RTX 5080, which is substantially faster and more power-efficient than those cards and gives you full-speed access to DLSS 4.5 and MFG. But both of those things are nice to have rather than essentials.

RTX 3080: Upgrade if you’re feeling the VRAM pinch

The RTX 3080 isn’t constrained so much by its compute horsepower, which remains strong in pure raster gaming, as it is by its 10GB of VRAM. Especially if you’re trying to game at 1440p or 4K with max settings and minimal upscaling, you are likely finding that your 3080’s VRAM is the biggest obstacle to achieving the best combo of performance and image quality nowadays.

Unfortunately, the most tangible upgrades for the 3080 are the currently pricey RTX 5070 Ti or the chronically overpriced RTX 5080. Both of those cards will feel much faster for both raster and ray-traced games, they enable full-speed DLSS 4.5 upscaling for practically free performance boosts, and they give you access to framegen and MFG juice that the 3080 doesn’t support at all.

But you’d have to be really hurting for an upgrade to shell out for either of those cards, given their stiff premiums over MSRP right now. A faster, higher-resolution monitor paired with DLSS 4 upscaling (Preset K in Nvidia App override language) is a cheaper, easier path if you haven’t already tried it.

But if you’re a 3080 gamer looking for that “wow” moment from a new GPU, the RTX 5070 Ti and 5080 are the way, and their prices are what they are.

RTX 3070 and RTX 3070 Ti: Upgrade now

As with the RTX 3080, the biggest performance constraint for the RTX 3070 and 3070 Ti these days isn’t necessarily raw compute, but VRAM. Nvidia only ever offered these cards in 8GB flavors, and they still offer solid 1080p gaming performance with the latest titles. But if you’ve tried to max out settings at 1440p or above, you’ve likely felt the squeeze of that limited VRAM pool.

And VRAM-hungry RT gaming is inadvisable on the 3070 and 3070 Ti, as you’re going to be leaning hard on DLSS to even get to a fuzzy 1080p output. It’s just not worth it.

The RTX 5070 neatly solves all of the problems. It delivers the large baseline performance boost we want to see for a true upgrade, it has 12GB of VRAM for more demanding games at higher resolutions, and its support for DLSS 4.5 and MFG unlocks the latest tools for achieving high output image quality and smoothness. And it does all of this at a relatively reasonable price, even in today’s graphics card market.

If you don’t bleed green, you can get even more VRAM and a bit higher performance with the impressively fast and efficient Radeon RX 9070, whose prices also haven’t risen too terribly amid the current RAMpocalypse.

But that move is a bit of a leap of faith given the spotty support for FSR 4 AI upscaling and frame gen in the latest titles, and it also comes with the risk that you’ll be entirely locked out of next-gen features like path tracing, as we’ve seen in the latest Capcom games. If none of that sounds bothersome to you, though, the RX 9070 is worth a look as a possible option.

RTX 3060 Ti: Upgrade now

Like the RTX 3070 and 3070 Ti, Nvidia only ever offered the RTX 3060 Ti in an 8GB flavor, and that’s a tough enough limitation these days. But the 3060 Ti’s somewhat lower compute horsepower is a correspondingly greater liability as games march ever forward.

As with the RTX 3070 and 3070 Ti, your best upgrade bet is the RTX 5070. You’ll feel an even bigger boost in performance than you will with the 3070 duo, and you get more VRAM and better DLSS support than your existing card to go with it. Easy.

RTX 3060 12GB: Upgrade if you can make the 5070 leap

The RTX 3060 12GB keeps going and going thanks to its unusually large VRAM pool for a budget-friendly GPU. But that VRAM is paired with just so-so compute horsepower that’s really showing its age in the latest games.

The most natural upgrade for the 3060 in normal times would be the RTX 5060 Ti 16GB, which delivers the performance leap we want at a reasonable MSRP. But the ongoing RAMpocalypse has made those cards too scarce and too pricey to recommend. And the RTX 5060 Ti 8GB’s performance is all too likely to fall off a cliff due to its small VRAM pool, so we’d never suggest it as an upgrade.

Sorry to repeat ourselves, but the best step up from the 3060 12GB in today’s chaotic market is the RTX 5070, assuming you can afford it. It more than doubles the 3060 12GB’s gaming performance even at 1080p, and that gap becomes even more pronounced at 1440p and beyond.

Critically, the 5070 doesn’t leave you with less VRAM than you already have. Add in vastly better RT performance and support for DLSS Multi Frame Generation, and an RTX 5070 is a truly transformative gaming upgrade.

If you need a more budget-friendly upgrade than the RTX 5070 amid the RAMpocalypse, your only reasonable choice is the Radeon RX 9060 XT 16GB. That card delivers the 1.5x basic performance improvement that we want to see for the money, it runs FSR 4 AI upscaling and framegen where it’s available, and it slots into roughly the same power envelope as the RTX 3060 12GB. But you’ll need to be comfortable with leaving the Nvidia fold, and that might be too big a leap for some.

RTX 3050: Upgrade now

As the entry-level Ampere card, the RTX 3050 was already wimpy when it hit the market, and time hasn’t treated it well. It lands well below the 60 FPS mark in our overall standings, even at 1080p, and we’ve found that its baseline performance is so low that DLSS doesn’t improve things much.

If you’re still gaming on an RTX 3050 and have the freedom not to, it’s dead simple to find a compelling upgrade. Even the humble RTX 5060 handily doubles the 3050’s average frame rate across our tests at 1080p, and assuming you don’t run into VRAM limitations, the 5060 can even deliver a smooth 1440p gaming experience if 60 FPS is an acceptable baseline on average. That major performance boost barely comes with increased power requirements, so you won’t have to budget for a PSU upgrade, either.

But the 5060’s 8GB of VRAM means that you might still run into performance pitfalls in modern games, especially if you want to try out RT and DLSS framegen. If you’re only playing Counter-Strike 2, Fortnite, or Apex Legends, that’s less of a problem than it might be if you’re keen for the latest AAA experiences or PlayStation ports. But you’ll always be thinking about

If you’re looking for a card with greater longevity than the 8GB 5060 and aren’t married to the Nvidia ecosystem, we’d also check out the Radeon RX 9060 XT 16GB. It’s even faster than the 5060 in our tests and will allow you to start properly exploring ray tracing in titles that support it. It offers high-quality FSR 4 upscaling and framegen, and it won’t crush a small or aging PSU.

Bottom line

Nvidia graphics cards are lasting longer than ever, thanks to common architecture capabilities like RT and Tensor Cores, in addition to a continuously improving DLSS software suite that boosts both performance and image quality. But even with those benefits, games are continuously advancing, too, and today’s titles are starting to put pressure on even the top-end RTX 30-series GPUs of yore.

The AI boom and the accompanying RAMpocalypse both make this a tough time to upgrade for gamers’ wallets, but if you’re still using an RTX 30-series GPU and are starting to feel the upgrade itch, the relative stability of gaming GPU roadmaps also means that you can make the leap to a Blackwell card (or competing Radeon) with some confidence that you won’t be taken by a surprise next-generation GPU launch any time soon.

That said, if you’re still happy with your current graphics card and gaming monitor setup, don’t mind missing out on DLSS Multi-Frame Generation, and don’t feel the need to explore maxed-out ray-traced or path-traced effects in the latest titles, we wouldn’t blame you for squeezing every last bit of life out of your Ampere GPU. No matter which path you take, it’s hard to lose.

At the North American Technology Symposium 2026, TSMC revealed its updated CoWoS packaging roadmap with major enhancements. Within chipmaking, the reticle limit is the largest size that a chip can be printed within a single step of the manufacturing process. TSMC's previous CoWoS-based system-in-packages (SiPs) roadmaps topped out at a 9.5-reticle size.

Now the company expects to produce 14-reticle and over 14-reticle-sized System-in-Packages (SiPs) with up to 24 HBM5E stacks by 2029. Such high integration is designed to meet the insatiable demand that AI accelerators have for both compute and memory bandwidth, and signals that packaging, not lithography, acts as a primary driver for semiconductor technologies.

"AI compute scaling is driven by the combination of advanced logic, SoIC 3D stacking, and CoWoS technologies," a statement by TSMC reads.

Bigger, hotter and hungrier

It is common for contemporary process technologies to scale slowly in transistor density, while full-node scaling enables 15% to 20% higher transistor density every three years. Intra-node improvements yield diminishing returns in density, but continue to provide performance improvements and greater power efficiency. This may not be a big problem for consumer product-makers, but it greatly affects the developers of AI and HPC applications, who must improve their solutions every year or two to remain competitive.

For those customers, TSMC has begun mass production of 5.5-reticle-sized CoWoS SiPs, supporting up to 12 HBM3E/HBM4 stacks and has achieved yields over 98%, according to the company.

In 2027, TSMC's CoWoS roadmap outlines a 9.5-reticle-sized interposer that supports 12 HBM5 stacks, which is expected to require a 120 mm by 150 mm substrate. In 2028, the company expects to produce a 14-reticle-sized interposer capable of carrying 20 3D-stacked compute chiplets and 20 HBM5 modules. By 2029, TSMC expects to produce interposers over 14 reticle sizes, with up to 24 HBM5E stacks. One standard reticle measures 26 mm by 33 mm (858 mm²), so a 14-reticle-sized interposer measures 12,020 mm², or the size of a small plate, and slightly larger than a CD.

An SiP that uses a 14-reticle-sized interposer and measures 12,020 mm² will consume an enormous amount of power, will require an exotic cooling solution (think exotic cold plates like those developed by Frore Systems, immersion cooling, or a combination of both), and will require a massive substrate, which will occupy a significant share of a server motherboard's real estate. The dimensions of the SiP alone will redefine how AI servers are built, whereas power consumption and cooling requirements are poised to open doors to a host of new technologies.

48x more compute transistors, 34x more bandwidth by 2029

Such gargantuan multi-chiplet processors show that advanced packaging is now the de facto scaling engine for the industry. In fact, TSMC's lateral CoWoS and vertical SoIC technologies enable faster growth of transistor budgets than traditional Moore's Law scaling. In addition, such SiPs also offer more memory bandwidth.

Based on TSMC's expectations, its customers will be able to put (at least) as many as 24 3D-stacked compute chiplets on one 14 reticle-sized CoWoS interposer by 2029, when A14 will be in mass production. When combined with scaling enabled by the latest process technologies (4x from N7 to A14), an ultra-high-end SiP from 2029 with 24 3D-stacked A14-based chiplets will be able to carry 48x more compute transistors than a high-end SiP with two N7-based chiplets from 2024, according to TSMC. Granted, we've rarely seen frontier dual-chiplet N7-based SiPs in 2024, even a cautious Nvidia opted to use 4NP instead.

There is a catch regarding 3D-stacked compute transistors, though. The bottom die may overheat, whereas the top die must get enough power to reach its full potential. To that end, many designs use the bottom die for cache (e.g., AMD's Zen 5-based CPUs with 3D V-Cache), not for compute.

Nonetheless, even a 24x increase in the number of compute transistors per high-end SiP in five years is a breakthrough that could not be achieved by Moore's law alone. However, such integration comes at a price. In the 2030s, cutting-edge SiPs with 24 3D-stacked compute chiplets and 24 HBM5E modules will likely cost an order of magnitude more than a high-end SiP from the mid-2020s.

In addition to compute capability, large CoWoS interposers also enable considerably higher memory bandwidth simply because they can carry more HBM stacks. It is not that simple, though. Total memory bandwidth scales dramatically, driven by the combination of wider HBM4 and HBM5 interfaces, more advanced HBM base dies built on TSMC’s N3P process, and ongoing CoWoS improvements that enable faster interconnect speeds. As a result, a high-performance SiP integrating 24 HBM5E stacks in 2029 is expected to deliver up to 34x higher bandwidth when compared to a reference SiP with eight HBM3 stacks in 2024, according to TSMC.

"HBM bandwidth scaling comes from multiple factors," said TSMC. "First, there is the memory itself — progressing from HBM3 to HBM4, with higher I/O counts. In addition, we are leveraging more advanced logic technologies for the base die, which allows us to push data rates well beyond 10 Gb/s per pin, something that was unheard of in traditional DRAM. At the same time, our CoWoS technology enables integration of more HBM stacks within a single package. […] All of these factors together — higher data rates, more I/O, and more stacks — contribute to the overall bandwidth scaling."

Slower transistor scaling

One of the things that strikes the eye about the current and upcoming process technologies due later this decade is the slow scaling of transistor density. While A14 is set to increase per-chip transistor density by 20% compared to N2 technology in 2028, its optical-shrink successor (A13) is only poised to provide a 6% higher density a year later.

Fortunately, TSMC continues to aggressively develop its CoWoS packaging technology, which promises to enable developers of system-in-packages to put 24 3D-stacked compute chiplets and 24 HBM5E modules onto one massive 14 reticle-sized interposer before the end of the decade. This will increase compute transistor count and memory bandwidth per SiP by 48x and 34x, respectively, compared to high-end data center SiPs in 2024, according to TSMC.

However, this level of integration will likely come at a high cost. System-in-packages with up to 24 3D-stacked compute chiplets and 24 HBM5E stacks in the 2030s will probably cost an order of magnitude more than high-end SiPs from the mid-2020s.

Once every quarter, we’ll be publishing a build here at Tom’s Hardware Premium, intended to showcase the best of our building abilities. After much deliberation, we decided that for this second ‘showstopper’ build, we wanted to push Mini-ITX to its absolute limit, not as buying advice, but as a test, to see whether doing so is remotely viable.

Why are we doing this?

For the first Tom’s Hardware Premium build, I went all out and spent three months building a wooden PC that I called The Stout Owl. This was a full-ATX, 100% air-cooled machine centered around Noctua’s brown-and-beige colorway. A few months have passed, and I’ve been busy cooking up something smaller.

I’ve built many PCs in my life, but there’s one challenge I’ve never taken on: an ultra-high-end, custom-cooled ITX system. After looking around the options available, I spotted the NCase M3, and instantly saw a vision for it.

I’ve seen many NCase builds, and although I can attest to it being a fantastic case, there’s one issue I always had with many of the builds, even my own from many years ago: they hide so much of the hardware with side-mounted radiators, fans, & mesh covers.

The demands of the challenge

This led to the demands of my self-imposed challenge:

• Use an NCase M3.
• Cram in the most powerful hardware on the market.
• Retain the glass side window (and thus, no side-mounted radiator)
• Don’t use any externally-mounted hardware.

I was especially adamant about the side window, which had to be implemented. It’s easy to take a small case like this and resort to the mesh panel to keep thermals under control, but that would be a cop-out. Externally mounting hardware would be too – as tempting as it may be to use the space behind the case, so that I could add another fan or radiator, I wanted to keep the challenge confined to the borders of the 19-liter chassis.

Custom cooling this system was no longer optional, but practically mandatory in order to achieve this goal. Vertically mounting a GPU would obstruct the view of all other hardware, and you wouldn’t be able to use the glass side panel, as it would block the air intake. Keeping it mounted in the PCIe slot, you’ll see the other hardware if you use glass. However, using a glass panel when you have an RTX 5090 spitting 600 watts into the case is simply asking for problems – you’d still choke the 5090 with the size restrictions, and you’d be needlessly exposing the motherboard, memory, SSD, and power supply to a ton of heat.

With the Ncase M3 at the workshop, I started figuring out exactly how to go about tackling this challenge. With a build like this, it’s pertinent to have the case on-hand when selecting the rest of the components, because the tolerances between a part fitting, and not fitting – there were situations in which I had mere millimeters to work with, which could make-or-break the entire build.

Parts selection

For components, we decided to almost go all-out on this build. Since the goal was to push Mini-ITX to its limits, it only made sense to go with an Nvidia RTX 5090 and an AMD Ryzen 9 9950X3D.

MSI was kind enough to provide the MPG X870I EDGE Ti Evo motherboard and an RTX 5090 Suprim. We’d like to thank them for coming on board this build, as we’d been transparent with them from the beginning about the extravagant plans of custom cooling within the minute size constraints.

Powering this system was going to be a challenge. Thankfully, there are now a small handful of SFX power supplies available with a 1000-watt envelope, and I decided to go with a bit of an underdog: the Silverstone Extreme 1000Rz Platinum.

For storage, we’re using a Sabrent Rocket 4 Plus in the 1 TB flavor. Now, I’m aware that this is only a PCIe 4.SSD, and just 1 TB, a bit paltry in comparison to the rest of this system. However, the one PCIe 5.0 SSD I have on-site is currently installed in another PC. Besides, it’s not as if the Rocket 4 is a slouch in the slightest, and 1 TB is plenty for testing purposes here.

For memory, Greyscale uses a 48 GB (2x 24GB) DDR5-7200 memory kit from Team Group. I’ll detail the selection for cooling this system later when we get to building the actual cooling loop, but for now, let's build the system up ‘dry’ to make sure everything works before figuratively dunking it under water.

But first, let’s talk about NCase for a moment

NCase is quite a special brand in that it’s not a large-scale commercial organization. Rather, the founders, once known as Necere and Wahaha360 on the [H]ardForum, were dissatisfied with the offerings available, and set out on a mission to build a better ITX case than they could buy on the market.

After many design iterations, Dan and AJ finally came out with the ‘first edition’ NCase M1 back in 2012, and I can say that I’m the proud owner of number 0149.

Production was outsourced to Lian Li, largely because Lian Li excelled in the manufacturing of high-quality aluminum PC cases, but also because Lian Li was actually willing to work with the just-founded NCase. Such a partnership is always a gamble, and building the tooling for a small production-volume case, especially when it isn’t your own product, isn’t particularly profitable.

However, the partnership worked out, and now, almost 14 years later, NCase has become a thriving small business complete with support, marketing, and PR staff, and crucially, they’ve sold a lot of cases.

Before building any water-cooled PC, it’s good practice to make sure all the components actually work together. Finding out there’s a compatibility or DOA (dead-on-arrival) issue after building and filling the entire cooling loop is one of the most frustrating issues one can face that far in the build process, partly because it’s a lot of work to take the system apart, but more so because it’s entirely preventable.

To begin, I assembled a big chunk of the flat-packed NCase M3. Later, I learned from the manual that the way you’re supposed to build it is by building much of the system onto the motherboard tray first, and then installing the panels onto the case later, but I’m too stubborn to read manuals from the get-go, so here we are.

Next, it’s time to prepare the motherboard. I started by installing the AMD Ryzen 9 9950X3D into the AM5 socket. I chucked the Sabrent Rocket 4 SSD into the M.2 slot. And popped the two 24 GB DDR5-7200 modules into place. Now, I’m aware that the color theme on this motherboard and memory doesn’t totally match, but there’s a good reason for that: the economy – I’m using what I have available to me.

Let’s pretend that the reason why is that we’re going with the theme ‘Grayscale’ and thus we need to cover all parts of the gray spectrum.

Popping the motherboard into place was interesting, largely because NCase has done something I’ve never seen on any other case: screws at the back of the standoffs.

Because of the modular design where the motherboard can be mounted all the way at the top, close to the bottom, or almost anywhere in between, it doesn’t make sense to tap threading into each of the mounting holes – it wouldn’t look good, would collect dust, and cost too much to produce. So, the standoffs are held in place by a screw that affixes to the rear side.

I then mounted the Silverstone power supply. For my plan with liquid cooling, I’d have to lower it later on, but at this stage, I mounted it higher up so that it would clear the GPU area and leave room for the cables to come out.

Then, it was time to install the GPU. This was going to be a tight squeeze. The original NCase M1 was not designed to accommodate these kinds of graphics cards, and even in the larger M3, it’ll be a close shave.

I was unable to shim the GPU into place with the case assembled as it was, so I removed the front “grater” panel and popped the GPU into place. This is only a test fit after all, and the cooler will be removed in the final build. This was also a good time to install the cables for the power supply, as it’s easier to access without the front panel in the way.

I contemplated not re-installing the front panel at all, but this left the case a bit structurally unstable, and I did want to bring it back upright for pictures. The GPU still fit, but I wouldn’t need an anti-sag bracket to keep it up – the fitment was so tight that the clamping force of the front panel held the GPU up right where it belonged.

For the CPU, I reached for an old unused AMD Wraith Prism cooler, which is grossly underpowered for this CPU, but at this point, it was more about having some mass on the CPU than actually giving it adequate cooling for sustained loads.

In fact, generally for a test-run like this, it’s fine to just use the CPU waterblock, bare, without hoses attached or coolant – I wasn’t going to run the system much further beyond post, and all it would have to do is soak up the brief bit of heat generated in this brief timeframe before shutting down the PC again.

It turns out, though, that the SSD still had an old Windows installation on it from a previous test, and since there’s an actual cooler on there, I let the system boot.

Everything checked out. Time for the good part!

To cool “Grayscale,” we’d turned to Alphacool. We’ve never done a build with Alphacool watercooling gear, so were eager to try their range out.

Because we’re cramming a 9950X3D and an RTX 5090 into a system the size of a shoebox, we would be needing full-copper radiators, as these are highly effective at dissipating heat. For this purpose, Alphacool’s HPE series perfectly fit the bill.

The plan was quite straightforward. At the bottom of the NCase M3 would be a regular 30mm 280mm radiator with two of Phanteks’ new 14omm T30 fans (the company finally released them last month, five years after the 120mm version.) These fans are 30mm thick, which is 5mm more than the industry standard, and built with LCP, they are true high-performance kings.

At the rear exhaust, there would be a 120mm pump/res combo unit. This unit would be installed on its standoffs to ensure air could still escape through the vent it’s mounted on by means of positive pressure in the case. So, although there would be no fan there, I did plan on a 120mm intake fan on the side of the case, between the PSU and the motherboard.

At the top of the case, the motherboard would stop us from being able to install a 280mm radiator, so it would have to be 240mm; however, we did have vertical space, so this would be a 45mm thick radiator, again with Phanteks T30 fans installed, for a total combined thickness of 75mm. With better breathing space, this radiator would be doing most of the heavy lifting.

Lastly, the system will use soft matt-black tubing, in a thick 16/10mm (OD/ID), for nice chunky-looking tubes. Although they would be inflexible due to this thickness, which is particularly challenging in a small case such as this, they have a chunky, utilitarian look. Hopefully, this is not a choice I’d regret later.

Installing the CPU Block

To install the CPU block, we first prepare the CPU by cleaning the old paste off it, and swap the factory bracket for the mounting screws included with the block kit. Then, we give it three dots of thermal paste, and chuck the Alphacool Core 1 Aurora Silver into place.

Although it’s ‘just’ a CPU block, these copper blocks are quite weighty.

Radiator & fan install

After the CPU block, I installed the two radiators. The slim 280mm unit at the bottom of the case, and the 45mm 240mm radiator at the top. Although there’s an option for taller feet from NCase, I don’t find that lifting the chassis up any further looks particularly charming, but it also means the lower radiator wouldn’t be able to get a lot of air. This meant the top rad would be doing most of the heavy lifting.

Then, I dropped the Phanteks T30 fans into place. One immediate issue was that the CPU block’s intake port was blocked by the corner of one of the fans. This was going to be a problem later on, but we’ll get to that in a bit.

Reservoir & Pump Install

The Alphacool Core 120 pump-res combo unit is a beautiful bit of kit that slots right onto a 120mm fan mount. I debated for a few moments whether using this reservoir would be a wise choice – it did mean sacrificing the rear exhaust fan slot, but I really did not want to turn to a tubular reservoir in the middle cavity of the build – I didn’t find that it would look cohesive, and in all truth, I find that cylindrical reservoirs look a bit dated.

Unfortunately, mounting the reservoir wasn’t as straightforward as I had hoped. The NCase M3 is built from beautiful, thick, anodized aluminum, and the screws to mount the push-pin system with spacers weren’t long enough.

With the gear I had, I could have opted to mount the reservoir flush against the case, but this presented three issues:

• The side drain port would be unusable
• The chipset fan on the motherboard would get zero airflow
• It would leave the rear exhaust fully obstructed, so even positive pressure wouldn’t work so well here.

Thankfully, the vast majority of screws used in PC builds are standard M3 threading, so I ran over to my local hardware store and grabbed four M3x10 screws.

With these, I was able to mount the reservoir in place, and all was good in the world again.

A 3D game of Tetris

Now that the radiators, fans, power supply, and pump-res unit were installed, it was time to evaluate the viability of the layout.

The first revision made was flipping the top radiator to feature the ports on the rear instead of the front of the case, as in the previous configuration with the ports at the front, the fans would make the inlet port of the CPU block inaccessible.

Making this change did mean that I would be cramming a ton of fittings into a very small space, but there was no other way of making it work. I also pulled the radiator as far forward as possible. This gave me just enough clearance for both ports on the CPU block.

I also contemplated adding a third radiator. I have a few extra 120mm radiators that I use for fan testing, so I test-fit one of them, to see if it’d work.

Unfortunately, it would mean the top radiator wouldn’t fit in the intended spot anymore, and I was about 10mm short on clearance. If I were to use a 25mm thick fan, and a 25mm thick radiator, it could save 5mm on each and it would work, but I didn’t have a 25mm 120mm radiator at my disposal, so it sadly wasn’t going to happen.

I also experimented with every possible alternative for positioning the power supply. In the position I had it originally, the motherboard and GPU cable were long enough to tuck away tidily, but the 8-pin cable EPS cable to power the CPU wasn’t long enough to route out of sight. But, there was no better layout, so the CPU's power cable was going to remain visible. I should have measured this all out before and placed a CableMod order, but alas.

I placed the GPU block without the graphics card in, and pictured above is the final layout I decided to go for, but there was one crucial factor looming. As much as I wanted to use them, it did not look like I was going to have space for the Phanteks T30-140 fans on the bottom radiator.

But before going out and finding regular 25mm thick fans, I decided I had to install the GPU. Who knows, we may get some extra clearance with it installed.

For many, the most daunting part about building a custom looped system is installing a GPU block, and there are a few reasons why. Getting a stock cooler off a graphics card can be quite a convoluted process, you often need to go through a ‘warranty void if damaged’ sticker, and unlike a CPU which has a heatspreader to protect the die, GPUs don’t come with heatspreaders at all.

Now, personally, I really like that GPUs don’t come with heatspreaders – in a custom loop where the CPU is not delidded, a GPU always runs about 20 degrees cooler than the CPU. That’s a huge temperature difference that’s entirely to blame on the IHS (integrated heat-spreader.) However, it does mean you have to be careful removing the cooler, because you do not want to accidentally crack the GPU die.

To remove the cooler from MSI’s RTX 5090 Suprim, we begin by removing the backplate, which, as expected, features a warranty void if damaged sticker on one of the screws.

It’s amusing to see modern graphics cards exposed, as their PCBs are comically tiny compared to the full size of the end product with the cooler. I suppose this is why even cheaper GPUs come with backplates nowadays – to mask how small the PCBs are.

Here came the delicate part of the operation. One does not simply pull the PCB upwards from the cooler – doing so would put heavy strain on the GPU die.

In the case of this particular graphics card, this was especially so. The thermal paste was bone-dry and had all but glued the GPU to the heatsink.

To prevent any damage in cases like this, you can rotate the PCB slightly clockwise, then anticlockwise, and repeat the movement until it starts to give way. Once that happens, you can gently pull on the PCB a little while continuing the shimmying motion. After a little while, it’ll come off without using much force.

Now keep in mind, this particular graphics card is a media sample that’s been in rotation between various outlets since the beginning of the RTX 5090’s launch – it’s flown all over the world, been in many PC’s, and although it’s not been taken apart yet by anyone, even the packaging made it clear that this is a GPU that’s been passed around extensively.

You never truly know what these media samples have gone through, so perhaps it’s a good thing it ended up in my shop for servicing at this point in its life.

The same gentle approach applies to the connectors that wire the fans and RGB to the PCB. Whereas most connectors in the rest of a PC build are sized for human hands to be able to undo the clips, the connectors here are much smaller. Now, I could probably pull on them to get them to disconnect – the clips are quite small and would probably be overcome by force. But, this is a loaner card from MSI, and I absolutely did not want to call them to let them know I destroyed one of their precious 5090’s, especially in this GPU market.

With that, the GPU was disassembled successfully.

What’s interesting here is that pictured above are all the parts you need to remove to get to the 5090 Suprim’s PCB. I’ve taken apart quite a handful of GPUs in my time, and of course, there were simpler ones, but for a flagship GPU with a large, intricate cooler, this was actually really quite easy. As long as you take the proper precautions, it’s actually really quick and straightforward – I’ve had GPUs where I had significantly more steps involved in getting the PCB separated from the cooler.

Let’s take a moment to admire this GPU

Even here at Tom’s Hardware, it’s not every day that we get to witness a bare GPU die, especially not from an RTX 5090. Of course, we’re free to do what we want with our own GPUs bought with our own money, but with media samples, we’re often not allowed to tear them apart, even for some GPU reviews.

The RTX 5090 Suprim is really something to behold once undressed and cleaned up. Of course, seeing the spec of 750 mm² was the first giveaway that this was going to be a big GPU, but seeing it up close, like this… I had to grab a CPU to give a reference point you can relate to.

My father-in-law used to sell lithography machines before he retired, and I showed him this – he was in awe that a single chip could be this big. “No wonder the prices are so high – you can’t fit a whole lot of those on a single wafer.”

Generally speaking, I like to take the “X” approach to applying thermal paste to GPUs, letting the mounting pressure spread it evenly over the die. However, with the size of this GPU, I decided not to take any chances and followed Alphacool’s instructions, using the spatula to ‘plaster’ the paste over the die. I’m not sure if this is really a better approach, but the thermals in testing later were spectacular, especially on a cold loop.

Then, I placed the GPU block on a soft detailing rag so that the acrylic wouldn’t scratch, and applied the thermal pads.

I carefully placed the GPU onto the block, and placed the thicker thermal pads on the rear of the memory modules and the power connector. This is so that these can cool via the backplate.

I then placed the GPU over the edge of my desk so that the I/O bracket would fit, installed the backplate, and secured all the screws, cross-hatching them for even mounting pressure to ensure all were tightened up correctly.

With that, we have a GPU block installed on a 5090. That was surprisingly easy.

Because I wouldn’t be able to get to these later, and because I really didn’t want to forget, I installed the plugs. One of these didn’t go in as deep as the other, though. Fingers crossed that’s not a problem in the future.

With the GPU installed into the system, it confirmed my biggest fears: I did not have space for the Phanteks T30-140’s.

Leaning on the port plugs, the GPU was perfectly level. This here was maybe two mm of breathing space.

With how much the GPU was covering the fans, this was a blockage that even the almighty T30’s wouldn’t be able to overcome. I really wanted to use these fans, but this build was already pushing the limit for cooling capacity, and this here would be asking for problems.

This situation called for Noctua to come save the day, and although the 120mm variant of the NF-A12x25 G2 isn’t out yet in black, the 140mm flavor is, so I bolted over to my local PC parts store and grabbed an Sx2-pp kit.

This gave me 5mm extra breathing space around the edge of the frame, which, although still not a whole lot, would be a lot better than almost no breathing space at all.

Although the NCase M3 is small, this configuration left me with a handful of cavities for cable management. There’s one between the motherboard and the top radiator that extends over to the top of the PSU, a big one below the motherboard, in the space between the 280mm bottom radiator and the case, another behind this same radiator, and below the power supply.

I removed the heatsink from the SSD to run a few of the RGB cables out of sight through a gap between the graphics card and the motherboard. Of course, removing the GPU would be less tedious, but with how the NCase’s rear bracket is made, it would take longer, so I opted to do it this way and fish with tweezers to get them through.

I was able to tidy all up in the space between the motherboard and the top radiator, and at the bottom of the system behind the 280mm radiator, for a surprisingly tidy end-result.

I was happy with how it looked, even inside the main cavity. Yes, the CPU power cable was too short, but by angling it in a way to block the least amount of airflow, it also wasn’t all that bothersome visually. I also opted to route the GPU’s power cable over and behind, as although underneath the GPU would have looked better, it would have impacted airflow in that area.

This is what money is for right? To solve problems.

The GPU also needed an anti-sag bracket, but I had none in this size. I looked around my office, and grabbed a few coins from my coin jar that I could use as shims. Later, I cut a bit of leftover tubing to the right height and used that instead.

The system was looking sleek, and ready for tubing. However, there was one thing I wanted to do first.

Remember what I said about not running the system without coolant? Well, it turns out I’m not a man of my word. Once the cooling loop would be installed, fixing any issues would become a real pain, so I decided that it would be okay to run it for a few seconds, just to double-check that post appears on the monitor, and that all the RGB and fans were connected before proceeding.

Monitoring temperatures in the timeframe here is not something you can do – by the time you get into the right window in the BIOS, or windows, the system is likely already too hot.

Instead, you can listen to the fans – if they start spinning at full speed, you know the CPU, and by extension, likely the GPU, are too hot for comfort, and you want to shut the PC off right before this happens. This takes about 30 seconds though, which is more than enough to check whether everything is working as intended.

Loop Planning

During the planning phase, I had a pretty good idea of how to run the loop; however, things never go according to plan, especially with smaller builds like this. I had ordered a couple of extra fittings and extenders, just in case. I had four short extensions, four longer extensions, four 90-degree elbows with rotary ends on both sides, and four 45-degree elbows, also with rotary ends.

Rotary ends are particularly helpful, as although they cost a little more, they let you rotate a fitting without breaking the seal, which makes it much easier to get pieces to fit. A luxury in big builds, a necessity in small builds.

I had also ordered a drain valve, and a thermal sensor. I like running my fan curve based on the coolant temperature, because when all is said and done, the fans cool the coolant, not the CPU or GPU. Especially if both are contributing heat to the same loop, it can cause weird behavior to run the loop based on their temperatures.

However, the MSI MPG X870I Ti Edge Evo doesn’t have a connector to hook up a thermal probe, which put a damper in those plans.

It’s nice that I could lift up pieces of the case to get easy access. At first, I thought of running the reservoir’s outlet straight to the GPU’s inlet, but found that this would cause collisions with other routes.

After much puzzling, I decided to run the reservoir outlet (bottom port) straight to the CPU block’s inlet.

I installed the tubing, cutting off a few mm at a time until I was happy with the fitment.

I decided to get this pesky corner over with. In the plan, I wanted to run the GPU’s outlet straight to the upper radiator. As the 5090 would be spitting 600 watts into the loop, I wanted most of that heat to end up in the top radiator that I knew would be capable of dissipating tons of heat. I ran the outlet of this radiator back into the reservoir.

Getting these bits of tubing into place, although it may be soft tubing, was incredibly difficult. I’ll explain why in a bit, but first, let’s finish the loop.

I then ran over to the bottom radiator to the CPU’s outlet. The outlet of this radiator would go to the GPU, but the inlet of this radiator needed a more creative approach to access it.

Using a 90-degree elbow, I was able to run a stretch of tubing in a gap underneath the power supply, running through some cables, up into the main cavity.

Being a stretch that I couldn’t easily measure beforehand, I cut a longer piece so that I could cut it to size before popping the other end onto the outlet of the CPU block.

Cut to size, it fit beautifully and kink-free.

Finally, I cut a piece of tubing to run from the bottom radiator to the inlet of the GPU block.

The space I had to work with here was absolutely tiny, and the more tubes showed up, the more difficult it got to fasten the fittings. Pray for me that there are no leaks.

Leak testing

I popped the leak-tester onto the loop, pumped it up with air, and lo-and-behold – the loop was leaky. And not just a little. I was unable to pump it beyond 0.3 bar, and it would lose this pressure in a matter of 20-30 seconds.

There was good news and bad news. The good news was that I could hear the leak. The bad news was that it was the short tube run that returned the coolant from the thick radiator back to the reservoir.

Due to the magic of rotary fittings, I was able to get the top radiator surprisingly far out of position and could tighten up the problematic fitting. Because the tube run was so short, when I had done up the second fitting on this part, I had accidentally undone the first.

However, this wasn’t the only leak. The loop held pressure better, but it still wasn’t great, and although I couldn’t hear it, I suspected one of the GPU’s plugs may have been the culprit. I had tightened the fitting as hard as possible with the plastic fastener, and yet, the loop was still leaking. I pulled it out, flipped the gasket, but it was still leaking.

The point of these plastic fasteners is so that you don’t over-tighten plugs. Although not so bad here, when tightening plugs in acrylic, you have to be careful not to over-tighten, as it will crack the brittle acrylic material. These plastic tools are meant to break before the acrylic does.

But this wasn’t acrylic. So, I grabbed a screwdriver and gave it an extra shove – which worked. It seems there was something in the threading that blocked the plug from going in all the way. Once I got past that, it easily twisted into the exact same position as the other plug.

I was then able to pump the loop up to pressure, and it looked to be holding it well. I went for dinner, and two hours later when I came back, the pressure had dropped to about 0.4 bar.

Part of this was possibly due to pressure loss in the loop, likely due to microleaks, but another part was a problem these testers are known to have: if you tap them, the needle drops to the actual pressure. I had forgotten to tap it before I left to make the needle drop, so the 0.5 reading at the start may not have been entirely accurate – but with 0.4 after taps and two hours away, I had full confidence in the loop.

Even if there was a tiny leak somewhere, water is thicker than air, and thus less likely to escape, and the loop would certainly not be running at anything close to 0.5 bar anyway. I intended to run the loop hot, but not so hot to generate that kind of pressure.

Because I custom-cool PC’s fairly frequently, at some point in the past I’d made a draining hose. This is quite simply a hose that attaches to a G3/4’ port of your choice, usually one at the bottom of a loop or where you can easily get an air-bubble to appear.

I’ve found that simply opening a custom loop and letting water pour out into a sink leads to uncontrolled flow, which can lead to a big mess, and that a lack of control can lead to coolant entering the PC in places where it isn’t supposed to be.

The point of this hose is so that I can open and close the drain valve easily, and hose the coolant into a bucket lower down on the floor without making a mess of things near the PC.

First, we flush the loop

Because these are all new components, the first thing I want to do is give the loop a few flushes. Technically, you should do this to the radiators before mounting them, but I just give them a blast with compressed air in one of the ports, letting it out the other, which gets rid of most of the debris, if there even is any, without giving you drippy radiator during install. That’s also what they do in the factory, and why they install the plastic caps – to stop dirt ingress.

The flush here is mostly for peace of mind, to get rid of any oils and micro-debris that could eat away at finishes and eventually lead to clogged blocks. Though honestly, I doubt it really matters – especially in this system which will be getting dismantled in a few days.

Regardless, demineralized water doesn’t cost much, so I poured some into the loop, topping it up and cycling the pump until it was mostly full, and then used the drain hose and drain valve to clear most of it out.

If a loop is easy to fill and drain, I do this a couple of times, but this loop is more difficult. Due to the small size of the reservoir, filling it is quite tedious, as you can only add a tiny bit of fluid, and once you run the pump, it’s gone almost immediately. You don’t want to run a pump dry, and that meant starting and stopping the loop many times before the loop was full.

Consequently, what I opted to do instead was fill the loop fully, and then crack the drain valve, but only a tiny bit. Then, I kept the loop running, while it drained slowly, and squeezed the filling bottle just enough to keep the reservoir topped up, adding in water at roughly the same rate that it drained out.

This dilutes whatever dirt may be in the loop, and once I worked through about three liters of water, I drained the loop fully.

With the loop empty, I removed the drain hose, popped the plug back onto the reservoir, and filled the loop with clear coolant.

A time-consuming process, mostly

With a big PC that has a big reservoir, filling is easy: you fill the reservoir, and run the pump till the reservoir is almost empty. Then, you refill and repeat two or three times until the loop is full.

With this smaller PC, it’s a bit more complicated. The reservoir is tiny. I’m talking – less than two shots of espresso. I weighed it out, and this loop took about 850 ml of fluid. So, much of the filling I did by opening ports on the radiators to fill them up, only topping up the reservoir at a later part of the process.

Despite this, I had to top up the reservoir at least a dozen or more times, and because the filling port is right in the path of the return line, once the loop got fuller, I had to close the port while cycling the pump to stop water from sputtering everywhere. This of course, became very tedious.

Moreover, large air pockets could only be removed by picking the PC up and tilting it in all sorts of ways, even upside-down. With a big reservoir, you can just let the air move that way in due time, but because this reservoir is so tiny, if a bigger air pocket were to move to the reservoir, the chance of the pump running dry would be very high, so they all had to go.

Thankfully, because it’s a Mini-ITX PC, bleeding the loop is easy. Once full enough, close it all up, run the pump, and pick the PC up, shake it, tilt it, shake it some more, and really get all the air bubbles into the reservoir.

Top that up, repeat a couple times, and the system is bled and free of bubbles, suddenly running it much quieter. With a big PC that you can’t simply pick up and shake in all directions, it becomes a waiting game, and it can often take two to three days, or sometimes up to a week to bleed most of the air out of the loop. One of my other PCs still has a bubble near the top of the loop that I can see in the tubing, and it’s been there for years.

Before proceeding to test the PC, we must run it through its paces a few times to see how it runs currently, to see what needs to change in the configuration.

To begin, I updated the motherboard’s BIOS, and then we set the memory to the correct EXPO profile, which had it running at the intended clock speeds in a jiffy.

With that all done and Windows freshly installed, we proceeded to set the fan curves.

Because this motherboard has no thermal probe, I decided to use Fan Control to set up a custom virtual sensor – one that calculates the average temperature of the CPU and the GPU combined. From what I saw, the CPU would push itself to its 95 °C target regardless of what I did, whereas the GPU would continue to boost within its power target, and eventually settle on a maximum temperature of about 75 °C.

Now, to get a system like this quiet, it’s essential to be aware of the basic physics of cooling with radiators. Each radiator has a certain amount of heat it can dissipate, but this can be influenced by a handful of factors.

The first, and most obvious of these is which fans are installed, their RPM setpoint, and how restricted the airflow is through this setup. In the case of this PC, we’re using top-quality fans, and the radiator at the top, although 45mm thick, has tons of breathing space. The radiator at the bottom, however, is lacking breathing space, with the intake side very close to the desk, and the exhaust side largely obstructed by the graphics card.

However, there is one other factor that affects how many watts a radiator can dissipate: temperature.

A contradictory configuration

If the coolant temperature flowing through a rad is low, you can blast a ton of air through it, but you’ll really only be dissipating a few watts. On the other hand, if the coolant is nice and hot, you can run the fans at a very low speed, and yet, they’ll expel a ton of heat.

For this reason, I had chosen to route the outlet port of the GPU block straight to the upper radiator, which would be doing the heavy lifting – it’s got way more breathing space, it’s thick, and best of all – all the heat it expels goes straight out the top of the case.

To ensure the greatest temperature delta, the intake fan on the side would supply it with a healthy amount of fresh air.

What am I trying to get at with all this information: you don’t want to run a PC like this at 100% fan speed. It’s just too noisy, and although doing so does keep the coolant temperatures a lot lower, the level of diminishing returns is significant, and the user experience becomes quite unpleasant.

For context, here’s what I mean:

With the fans at 100%, total system power consumption sits at 930 watts with a combined synthetic load on the CPU and GPU.

Drop the fan speeds on a much quieter curve, and the system finds an equilibrium load at 867 watts. The RTX 5090 runs right on the mark, and the 9950X3D simply doesn’t hit its power target anymore, instead running at 150 watts as opposed to 200.

However, all of this is only when running a synthetic load. Under these conditions, the CPU will hit 95 degrees, and throttle to keep it at this target temperature of 95 degrees. The CPU will also always be the first to throttle, simply because it has an IHS that gives it a 20-degree penalty over the GPU.

Now, to fix this, we could lower the power target on the GPU, essentially manually throttling the GPU, so that the loop has the capacity to handle the CPU without throttling, but I don’t feel this is necessary at all.

Under real-world loads, there is no performance penalty. Gaming isn’t nearly as heavy on the CPU, so it can run at full boost regardless of what the GPU is doing, and productivity workloads are generally not as ‘never-ending’ as gaming, which means the cooling loop can soak up a lot of heat before any throttling would occur.

From testing, it’s clear that in a quiet fan curve configuration, the loop can dissipate about 850 watts. Go over that, and something needs to throttle. But if you look at the gaming and productivity tests above, it’s clear that even the heaviest gaming workloads don’t exceed this figure.

If you don’t want anything to throttle, you’ll have to boost the fans to full speed, but this increases the maximum noise figure from 38.6 dBA to 54.3, which is simply put, unacceptably loud, and not remotely worth the extra 50-75 watts of cooling capacity it offers. You really don’t need to be able to handle both the CPU and GPU not throttling under simultaneous synthetic loads.

When I was brainstorming build ideas for this second Showstopper at Tom’s Hardware Premium, the idea of pushing Mini-ITX to its absolute limit felt like more of a gag than something that could actually turn into a viable machine. In that respect, this build was more of a test to figure out “is it possible?” than actual buying advice. We aim to provide unique content, and hopefully this is what you came here for.

My thought was, nobody in their right mind would try to build this PC – to most, whether it would work is far too much of a gamble. However, that’s also what makes it such an interesting test.

Of course, I knew this wasn’t going to be a custom loop that runs cool and quiet; that much was obvious. What I didn’t expect, however, was that by accepting that it’d run hot, but not overheating under real-life workloads, that I’d still be able to get it to run relatively quietly, and that it’d actually turn into a perfectly pleasant PC for everyday use.

Truly: under gaming workloads with GPU and CPU temperatures hovering between 65°C and 85°C, noise levels hover between 34 and 35 dBA, with fan speeds of around 800-1300 RPM, all while not having touched power targets. If I may pat myself on the back, that’s downright impressive if you consider that in this little box we packed not only a 9950X3D, but also a beefy RTX 5090. With that in mind, the glass panel really is the cherry on the cake.

So, this is actually totally viable on any hardware, but how difficult is it?

If you’re truly interested in building a PC like this, I’d say that the biggest factor that affects the difficulty level is one’s state of mind. You have to be prepared for whatever it throws at you – whether a fan doesn’t fit, or you find a leak in the trickiest corner to get to – your mindset, the ability to accept that something isn’t going according to plan, and adapting, is the key to a successful build like this while enjoying the process.

In a way, that’s something that goes for any PC build – you have to be able to see the humor in preparing for the worst, and the worst then still happening. Laugh about it, enjoy fixing it, and carry on. Brutal acceptance is the only way, and better to laugh about it than to cry about it.

There are two more factors, though – you need small hands, that one doesn’t need a lot of explanation, and you need to be a bit creatively fearless.

If it can’t be done how it should, then it shall be done how it can

Not fearless in the careless kind of way – that will get you in trouble, but fearless in the ‘trust the process’ way. For example, let's talk about the fittings and tubing for a moment.

I had chosen to use this matt-black tubing, in the second-thickest size, because I like the chunky look and velvety finish. Let’s just say, that was a choice. It may technically be soft-tubing, but this stuff is rigid.

Consequently, when you try to get it around the tight bends needed in this build, the forces you have to put on some of the build are not for the faint of heart. In fact, you’ll often need angled adapters to make most of the bend you’re trying to make, using the soft-tubing to bridge the mostly straight distance between the compression fittings.

Getting the tubing onto the fittings isn’t that bad though. What’s tough is the force needed to twist the caps onto the fittings. I can’t stress how much force it took to get those to tighten up. Now, I am someone who’s prone to joint pain, especially when working on small detailed projects such as these, but I have to be real: the force that some of these took to tighten up was nothing short of huge.

If you have the tubing come in straight, with very little lateral pull on it, then it’s perfectly doable. But the moment you cut the end of the tubing at a slight angle, because you practically need to make part of the turn inside the fitting due to the rigidity of the tubing, they become incredibly tough to close.

It’s not recommended to work this way, you’re better off grabbing extra angled fittings, but this build had many elements of “if it can’t be done how it should, then it shall be done how it can.” Even moreso when it’s in the tight spaces of this build here. This was manageable at the start, but especially the corner pictured above, it was a real fight to get most of those fittings tightened up.

There were moments when I thought about getting out the pliers, simply because forces I needed to exert with my fingers became too painful. However, there were two problems with this – if my hands barely fit, getting pliers in there would be even more difficult, and even if possible, I didn’t want to scratch up the fitting caps.

The effort isn’t without its reward

However, what do you get in exchange? This PC is absolutely watertight, I have zero doubts about that. The fittings screwed into the blocks and radiators nicely with a clear “this is far enough, thank you” signal. And because they’re so incredibly strong, although tough to install, especially in the tight spaces, together with the rest of the components, have made the system so tough and rigid, I would almost classify this as rugged – if it wasn’t for the glass panel and the beautiful finish of the outside of the case. This is a PC you could confidently chuck in a suitcase and take on a flight, only removing most of the coolant so that it can deal with the pressure changes.

The level of confidence I have that this is a loop that won’t be developing any leaks, and can deal with a bump without it being cause for concern – this is truly wonderful.

With a 9950x3D, an RTX 5090, plenty of power and just the right amount of cooling capacity to still run quietly despite its form factor, this PC is ready to take on pretty much anything you could throw at it.

This was a tough build.

If you’ve been paying close attention over the past year and change, you’ll quickly learn that while PC gaming is clearly struggling from apocalyptic component pricing, players are slowly looking to alternative platforms and operating systems to play games on. Valve’s Steam Deck is a primary cause for this success and has spawned a breed of x86-based handheld devices over the past few years. While Sony is reportedly developing its own handheld, Valve has been hard at work developing its own hardware ecosystem, or at least trying to, no thanks to the ongoing DRAM and NAND pricing devastation.

Valve’s upcoming Steam Frame will make use of an ARM-based Snapdragon 8 Gen 3 chip, notably differing from the x86-based chips inside the now four-year-old Steam Deck and the upcoming Steam Machine. Alongside choosing an Arm-based chip for its upcoming VR headset, the company has been quietly contributing to a translation layer named FEX.

What is FEX?

FEX or FEX-Emu, translates raw x86 instructions into ARM64 instructions, with Proton handling the software and OS-level translations from Windows into something that can be understood by Linux. When FEX and Proton work in tandem, it means that Arm-based chips could very well run many “full-fat” games stored in your Steam Library.

Valve has been funding the development of FEX for years, which is, in itself, open source. As such, over the past year or so, development has started on getting FEX up and running on Android-based devices. One such example is GameNative, a slick open-source app that can tap into your Steam Library and allow you to make use of FEX (and Proton) to run games. There are additional apps that perform similar functions, such as GameSir’s Gamehub, which is a closed-source alternative that, in late 2025, came under fire for its capture of sensitive user telemetry data. So, be sure to research these options wisely if you want to try something like this out for yourself.

So, with that all in mind, let’s try to push current Android hardware to its limits and see just how well FEX is shaping up.

Setup

Of course, many Android devices might not be up to the task of running AAA, x86-based games. As it happens, I was shopping for a new Android tablet, and lucked out finding a deal on a used RedMagic Astra Gaming tablet, which is equipped with a Qualcomm Snapdragon 8 Elite Gen 4 SoC, Adreno 830 GPU, and 24 GB of LPDDR5T RAM. The device is also equipped with active cooling, which is a rarity in smaller Android tablets.

It should be noted that Snapdragon 8 Elite Gen 5 chips are rolling out in the Android ecosystem, but availability remains limited in the U.S. With a decently powerful Android device in hand, it’ll serve as a good testbed to see exactly how (and if) current hardware on portable ARM-based devices is capable of running demanding games.

GameNative’s APK is available directly from their GitHub repository, and installation was simple: Once the app was installed, all I had to do was log into my Steam account, and voila, my entire library was available to choose from. The gamepad-friendly interface allows you to select from “Compatible” titles, and with that flicked on, I was able to view exactly which titles might play nicely with the RedMagic Astra.

For this test, I wanted to test a handful of AAA gaming titles to see how well they might run and to get a good understanding of how these titles can perform on modern hardware. For a baseline, Cyberpunk 2077 (RED Engine), Clair Obscur: Expedition 33 (Unreal Engine 5), and Resident Evil 3 (RE Engine) all serve as solid showcases to see how well these games might run. Resident Evil 3’s remake is an older RE Engine title, but given my Steam Library's lack of newer Capcom titles, it’ll just have to do.

Stalled boot

With Cyberpunk 2077 installed on the device, GameNative automatically chooses the best configurations for you and then pulls all of your Steam Cloud data to sync things up. This part of the process took a while, which is (what I presume to be) the sheer number of save files on my particular Steam Cloud variant. But it dutifully whittled away at downloading all of the required files to get Cyberpunk off the ground. And then… Nothing. Cyberpunk 2077 crashed to a halt. It took some tinkering with graphics drivers and Proton versions, then running a driver test to see if everything lined up.

Afterwards, I managed to finally load Cyberpunk 2077. Given that we want to run this as more of a proof-of-concept, rather than testing the silicon to its limits from the start, I immediately went to the settings menu and put everything on low, with FSR 2 off. After loading a save in a dense urban area, the game hangs, and seemingly nothing I did managed to solve that particular problem. Onwards, I pushed to the next title, undeterred.

Playable perfomance

Resident Evil 3, by contrast, offered a much smoother experience when running the title at 720p. With settings locked in and the application allowed to access the large RAM pool of the RedMagic Astra, I was able to play the introductory segments of the title with little to no issue. That should come as little surprise to anyone who knows that Capcom’s RE Engine scales incredibly well with lower-end devices, especially if they are limited in scope, such as Resident Evil 3 – I wouldn’t chance running a heavier, open-map title like Monster Hunter: Wilds on here so soon.

With the game up and running, I then pushed the image quality with settings set to prefer performance, with no upscaling. Resident Evil 3 stayed at a steady 40- 60 FPS for most of the introductory segment, and only when dealing with more challenging scenes with multiple light sources and particle effects did our frames begin to drop to lows of around 27 FPS. That’s still playable, though not quite offering a perfect experience, and some subjectivity comes into play. Following this, testing the ‘Prefer Graphics’ preset with no upscaling, we reached a range of 25-42 FPS, which is again, more than playable enough for a single-player title. While you’re not going to get that ideal 60 FPS target, the game also doesn’t look like you’re playing it through a vaseline filter, which is a plus.

With Resident Evil 3 producing solid results, I marched on to Clair Obscur: Expedition 33. This Unreal Engine 5-based title was a tricky one to get up and running. Firstly, I had to set the lowest possible internal resolution, then select the correct drivers to get things set up. Following that, we were in the game. But there was one glaring issue: Image quality. The selected graphics driver (nor any other combination) actually yielded anything that remotely looked like Clair Obscur, with textures going haywire and environments missing some textures entirely. This one was a total, unplayable mess; even measuring its performance would have been a waste of time. So, what’s going on under the hood, and why is performance so variable between titles?

Fractured configurations

To understand why individual titles run so differently is to understand that each game runs a wholly different engine. CD Projekt Red’s RED Engine has proven to scale to systems like the Steam Deck and Switch 2, but performance in-game on the RedMagic Astra has yet to match either a Steam Deck or a Nintendo Switch 2 in image quality.

For Expedition 33’s Unreal Engine 5, this is a complicated nightmare. The CPU translation layer, in addition to DirectX12’s VKD3D translation, is what’s causing things to not load correctly, such as DX12’s mesh shaders. To put things simply, there’s a complex stack of operations required to run things smoothly, and when those graphical pipelines get as complex as a modern title, like Clair Obscur, the house of cards begins to fall down.

This isn’t a problem for Resident Evil 3’s RE Engine, which uses a lighter and cleaner implementation of DirectX12, especially when compared to Unreal Engine 5. You also have the option to launch with the DirectX 11-based DXVK, which, in itself, is much easier for a translation layer to handle than the more complicated VKD3D. The caveat here is that you’ll have to access a different legacy beta branch to enable that, as the main branch of the title forces DirectX 12.

Worsening things is the fact that so much of this support relies on community-developed graphics drivers, most notably, custom “Turnip” drivers, based on the open-source Linux Mesa project, which patches Vulkan extensions that are actively still being reverse-engineered by the developers. These optimizations get missed by the official Qualcomm system drivers, which are closed-source. Therefore, as demonstrated in Clair Obscur: Expedition 33, when Turnip drivers are met with complex shader pipelines from UE5, the GPU driver can fail to render geometry correctly, even if the title boots.

Many titles that do not require the usage of such demanding graphical pipelines can work without breaking much of a sweat: So, if you’re missing out on Slay the Spire, or Hollow Knight: Silksong, those titles are demonstrably stable using FEX and emulator apps like GameNative. For our tests, we wanted to see how FEX handled complex shaders, graphics, and modern “big-budget” experiences.

Where does this leave FEX?

In and of itself, FEX is an ongoing project, and we’re not going to see major miracles happen overnight when it comes to elements out of the project’s scope, such as Qualcomm’s development of official drivers that officially support mainstream games.

Qualcomm’s mobile chips were built strictly to run mobile apps and games, meaning that adding the wrinkle of supporting elements like desktop-level Vulkan instructions is a use case they simply never really considered supporting before. If the company wants to capitalize on the work being done by the FEX team, Qualcomm-based chips must also come with similar levels of support as desktop graphics drivers, and the likelihood of that happening is quite slim indeed. As of the time of writing, community drivers for specific titles can enhance the experience of some titles, if you're willing to go to those lengths.

While the efforts of FEX-Emu and its complex, layered translation to get things running are indeed impressive, you’re not about to be able to take your whole Steam Library with you anywhere, until there’s more maturation of these applications and the community-made drivers (potentially with the help of a company like Valve) to create workarounds, or dedicated drivers. For now, it’s still too early to start throwing FEX out as a feature in a mainstream product until all of those rougher edges, like driver support, are smoothed off for end-users. Anyway, my tablet’s back to being relegated to being a very fancy comic-book reader again until the entire software pipeline has matured.

This article is part of a series documenting quantum computing technologies and their ecosystem – the differing approaches, the key players behind them, and the key technologies that are driving us towards a quantum future. Part one looked at superconducting qubits (materialized in key industry giants such as IBM and Google) and trapped ion qubits (through IonQ and Quantinuum).

In this second part, we’ll be looking at quantum photonics – a light-based technique of defining the quantum unit of computation, the qubit. We’ll take a brief look at the what and the why of quantum photonics, and then materialize it by focusing on two particular companies, their roadmaps, and their technologies: Toronto-based Xanadu Quantum Technologies (which is making a play for public Nasdaq listing this first quarter of 2026 at an estimated 3.6B$ enterprise valuation through a SPAC deal); and the Palo Alto, California-headquartered PsiQuantum (PSIQ.PVT, with an estimated 7B$ valuation buoyed by a 1$ billion worth Series E funding round in late 2025).

Like our previous roadmap analysis, this won’t be a technical article; it’s a technology and roadmap analysis that brings understandable bites on the underlying technologies, their roadmap evolution, current state, and expected next steps. For a better understanding of what quantum computing is all about, Tom’s Hardware has a more explanatory quantum computing article you can familiarize yourself with first.

What is Quantum Photonics?

To answer what quantum photonics actually is, we have to start with the most basic: photonics is the use of light to transmit encoded information. The most widespread application of photonics that’s already a part of our infrastructure today materializes through fiber optic cables: within them, light travels at its speed (which matters for latency) and crucially, without energy losses to electrical resistance.

Because light can contain multiple wavelengths (think colors, ranging through the visible spectrum and beyond), information in fiber optic cables can be encoded in multiple paths within the same ray (a technique known as multiplexing) for increased bandwidth.

This classical approach to photonics uses billions of photons (the essential unit of light) in coherent beams, using other elements such as phase and polarization as data carriers. Classical photonics is already a well-known quantity, with multiple applications in both intercontinental information transit, data center interconnects, and more specifically, inter-chip communication.

The transition towards the quantum realm occurs when you stop looking at light as a beam and focus on the singular elements that compose it: photons. Quantum photonics, then, makes use of single-photon sources and single-photon detectors to encode and decode information through the specific strengths of quantum properties: entanglement (where two entangled photons become a coherent system) and superposition (where the universe of possible information values can be contained in a single qubit until interfered with).

This brings us to the great differentiator in current quantum photonics: the way operations are run on individual photons, and how information is encoded within them. PsiQuantum uses what’s known as a dual-rail encoding approach: informational states are derived from looking at a photon’s “choice” between path A (0) and path B (1) (these paths being known as waveguides). Xanadu approaches it through the lens of continuous-variable encoding: instead of looking at the photon itself, it looks at the photon’s light field and how it’s distributed (across properties like amplitude and phase), ‘squeezing’ them (reducing uncertainty in the amplitude variable at the cost of increased uncertainty in phase) to encode data.

These are two fundamentally different ways of obtaining the result of a photonics-based, large-scale, error-corrected quantum computer, each with its own set of engineering problems. The end-goal, however, is the same: when you can generate, manipulate, and measure individual photons, light stops being a mere transmission medium, and individual particles become the computational substrate itself.

Advantages, challenges, and the mechanics of photonic qubits

Quantum photonics is claimed to have some operational advantages over other approaches: unlike superconducting qubits, photons can be operated on at room temperature, theoretically reducing both installation, running, and maintenance costs.

The natural physical makeup of photons also means that photonic qubits are less susceptible to environmental interference, such as electromagnetic noise and thermal fluctuations. Scaling-wise, photonics-based chips can leverage semiconductor manufacturing infrastructure, and the natural speed of light means that gate times (gate operations being the result of inter-qubit operations towards a useful result) should have a higher operational limit compared to other approaches, such as trapped ions.

There’s always an opportunity cost in each quantum approach, however. In PsiQuantum’s dual-rail approach, identical photons that can be reliably entangled are very hard to generate: minute differences in wavelength, polarization, and spatial modes destroy systemic equilibrium and reliability. Photon generation (which is usually accomplished by shining a laser through a crystal) is a probabilistic operation: sometimes no photon is generated; sometimes, one is; and sometimes, more than that.

All of this leads us to the harsh truth that in quantum photonics - particularly in its dual-rail design - it’s easy to lose more than 90% of the generated photonic qubits (at generation or collection) before they ever get a chance to perform a useful computation. This means that to generate a 100-qubit photonic system, upwards of 10,000 photons must be generated. Everything else is lost.

PsiQuantum’s way of operating on individual photons means there’s no informational backup, such as what you’d get when operating on classical light beams: when the photon is lost, everything is. You can amplify billions of photons when they are a beam, but you can’t do the same for a single photon (a quirk of quantum mechanics known as the no-cloning theorem). And being incredibly small particles, a minute error in the photon’s directionality means that the emitted particle can easily fail to be detected on the other end (think of how a small angular difference at a bullet’s exit compounds on missing the bullseye).

Xanadu’s approach, on the other hand, sidesteps the requirement for photonic “perfection” at generation and is more tolerant to photon loss (the light fields don’t completely vanish on individual photon loss). But it does introduce different error correction challenges – errors are continuous (noise is present in amplitude and phase measurements), while PsiQuantum’s issues are discrete (photon present vs photon absent, resulting in discrete bit flips in calculations).

Clearly, the base technology of photonics can serve very different approaches. PsiQuantum bets that silicon photonics manufacturing can overcome the drawbacks of their dual-rail approach through scale and engineering precision to reduce errors and improve photon measurement reliability, while Xanadu’s intrinsically higher tolerance to process imperfections enables a faster timeline to quantum advantage, or so they hope.

Xanadu's approach

Founded in 2016, Xanadu’s declared mission is to build a fault-tolerant photonic quantum computing datacenter in the early 2030s. To do that, the company has been developing a particular qubit concept pioneered as early as 2001 – GKP qubits. Xanadu is seemingly keeping its cards close to its chest when materializing expectations in roadmap form.

What Xanadu does is declare its innovations through scientific publications and post-facto announcements on executed milestones, defining its fault-tolerant target architecture design as early as 2020. This happened in tandem with the company’s first quantum device demonstration, which occurred by Fall 2020 with its X8 photonic chip – a 4mm x 100mm 8-qubit device fabricated on a silicon nitride process. The blueprint for their fault-tolerant quantum future was thus laid out.

By June 2022, the company introduced Borealis – their first fully programmable photonic processor (across 1200 parameters), which leverages 216 squeezed-state photon qubits, enabling the company to claim quantum advantage through a peer-reviewed, Nature-published paper.

The problem this advantage was demonstrated in is a very specific application – namely, Gaussian Boson Sampling (GBS). Xanadu claimed that top-of-the-line supercomputers and the available state-of-the-art algorithms towards solving that problem space would take around 9,000 years to complete on classical hardware – Borealis did it in 36 microseconds. Alongside this scientific success claim, Xanadu also managed to offer the first photonic quantum computer available on cloud through Amazon Web Services’ Braket, with quantum operations being handled through Xanadu’s PennyLane open-source, quantum hardware-agnostic software stack.

In early 2025 (again through a peer-reviewed, Nature-published paper), Xanadu demonstrated its progress towards its fault-tolerant computing datacenter with Aurora – a room-temperature operated (barring the cryogenic photon detector system), modular scaling vehicle harnessing 12 physical qubits across 35 integrated photonics chips. These were integrated across 4 modular server racks with fiber optic interconnects and over 13km of optical fiber across components (which include required loops for photon timing matching).

Aurora is the company’s milestone in demonstrating all the required architectural elements of its 2020 blueprint for a fault-tolerant architecture operating together. If X8 was a proof of concept and Borealis the company’s demonstration of achievable quantum advantage through their quantum approach, Aurora is the vehicle that proved their modular integration aspirations as achievable.

Progress has fast-tracked since then: by June 2025, Xanadu was demonstrating the world’s first on-chip generation of GKP states (their error-resistant photonic qubits), with silicon manufacturing processes handling their required silicon nitride waveguides on 300mm wafers. Perhaps even more impressively, the company demonstrated its ability to integrate error-correction at the chip level, while significantly improving its photon detection efficiency.

The principal issue to still be solved, as the company identified it, relates to the quality of the GKP state photonic qubits themselves, which materializes in optical loss issues. This identified bottleneck directly relates to Xanadu’s July 2025 announcement of a strategic partnership with HyperLight and its TFLN (thin-film lithium niobate) chiplet platform technology, which replaces the silicon nitride waveguide design with HyperLight’s lithium niobate solution, significantly reducing waveguide losses and electro-optic chip losses while retaining high-volume manufacturing through semiconductor manufacturing technologies. Another angle relates to another strategic collaboration announced in August 2025 with DISCO Corporation, a developer of ultra-precision grinding and polishing machinery for photonic components, aiming to improve the quality of GKP photon generation on laser interactions.

Looking to the future, the company’s goal is to achieve up to 1,000 logical qubits by 2029; barring unexpected breakthroughs, the company expects to achieve that at a 100:1 ratio, with a requirement of around 100,000 physical qubits to do so. Besides pure qubit count, applications are the name of the game; in December 2025, Xanadu announced a breakthrough application in photodynamic cancer therapy, a medical application that joins their ongoing partnership with AstraZeneca (molecular simulations, protein folding, drug-protein binding affinity, and optimization of molecular conformations). Additionally, the company has developed quantum applications for machine learning (including classification and neuronal network implementations).

PsiQuantum

Founded in 2016 (Palo Alto, California), PsiQuantum has grown in scale in the intervening nine years, reaching its 7B$ valuation while expanding its facilities across Chicago, Australia, and the United Kingdom. The company hit the ground running with a particular vision: to skip the current era of Noisy Intermediate Scale Quantum (NISQ) computers while focusing its funding and developmental efforts on tackling the architectural, error-correction, and manufacturing problems for its choice of quantum computing architecture. The goal: to deliver a 1 million-plus qubit design as soon as feasible.

This decision flies in the face of most other quantum industry players, who have elected to develop proof-of-concept vehicles all the way through platform development and incremental, step-by-step scaling.

PsiQuantum’s ethos informed their technology choice of pursuing a photonic quantum architecture, which, as we’ve seen, can find an important common ground within semiconductor techniques, leveraging decades of already-funded and problem-solved manufacturing research and development.

PsiQuantum worked in the shadows between its 2016 founding and 2021 – the moment the company materialized a very public partnership through GlobalFoundries’ Fab 8, one of the world’s leading CMOS and – yes – photonics manufacturing players. And even as early as 2021, PsiQuantum knew exactly what it required out of GlobalFoundries’ facilities: manufacturing of its Omega quantum devices.

One year later, the company was already testing GlobalFoundries’ output through testing and validation of single photon sources, photonic switches, waveguide-integrated on-chip photon detectors, and demonstrations of quantum entanglement.

Then, silence – up until 2025, when PsiQuantum finally revealed its work through the publication of the paper “A manufacturable platform for photonic quantum computing” in Nature. It finally shed light on what Omega is all about, and the engineering systems designed around its scaling up to 1 million-plus qubits: compatibility with 300mm wafer platforms; silicon-nitride waveguides; telecom-band (1550nm) single-photon sources, guaranteeing compatibility with existing fiber infrastructure; and its arguably most important development in the world’s first Barium Titanate (BTO) manufacturing process on 300 mm wafers, the demonstrably highest-performance electro-optic material known and a breakthrough in switching performance.

The paper claimed state-of-the-art performance in key metrics, conditional (as we’ve discussed before) on photon detection: if there’s no photon to detect, there’s no fidelity to measure. It’s an interesting way to expound on a quantum system and components reaching “beyond state-of-the-art-performance", as PsiQuantum put it, even if it leaves the question open on how good the photon hit rates are that are necessary for actual computational work to occur.

The confidence and planning are there: PsiQuantum places its achievement of a large-scale, error-corrected quantum computer somewhere between the 2027-2029 timeframe, which is ahead of most other quantum players, who tend to settle expectations around 2029-and-beyond.

But first, PsiQUantum still needs to showcase actual full-system integration through its Alpha system program (whose housing facilities covering a 120,000 square foot manufacturing and testing facility in Milpitas, California, are still under construction). Only then should the company be able to execute on the next phase: execution on its 1 million-plus qubit system is dependent not only on technological development but also on a relatively more mundane requirement: finishing the actual facilities where the system is to be housed, which saw groundbreaking at the Illinois Quantum and Microelectronics Park (IQMP) in Chicago in late 2025.

What lies ahead?

The complex reality of quantum mechanics means that there are two severe bottlenecks any company must face. First, the intellectual bottleneck, as there are very few people in the world capable of working and designing such systems. The second being the economic bottleneck, due to how research, development, and manufacturing of quantum-related technologies are simply very, very capital-intensive.

Xanadu’s lack of an official, public roadmap seems to be a strategic, science-first choice (compare it to IBM’s own extremely detailed roadmap for its superconducting qubits we explored in our previous article) – especially considering the way Xanadu has announced and executed on their plans for a large-scale, fault-tolerant quantum computer.

The one-two combo of announcing key milestones as they are executed while also moving them through peer-reviewed scientific publications shows the company is confident in their planned architecture, and the strategic partnership announcements align well with their identified bottlenecks.

Across the board, quantum is still a bet: no current quantum-related revenue can sustain development costs for pure-play quantum companies (something Google, Microsoft, and IBM don’t have to contend with), which helps explain the decisiveness of funding rounds and is perhaps a measure of their behind-closed-doors progress.

The bet is that when the tomorrow of quantum advantage comes, so too will the investment be justified. Like IBM, IonQ, and the other companies on our previous roadmap article, both PsiQuantum and Xanadu are also looking beyond the 2029 timeframe towards delivering large-scale, error-corrected quantum computers. Also like IBM, Quantinuum, and IonQ, Xanadu has made it to DARPA’s Quantum Breakthrough Initiative (QBI) Stage B.

PsiQuantum specifically hasn’t been a part of DARPA’s QBI, but is still involved with DARPA in a different capacity, being one of two companies (the other being Microsoft) to qualify for the Agency’s Underexplored Systems for Utility-Scale Quantum Computing (US2QC) Stage C program in February 2025. Beyond that, the company has seen both Australian and U.S. government backing; perhaps these government-corporation programs are one of the best ways to evaluate the feasibility of any given quantum solution, considering the validation work required for inclusion.

You might recall that we put out a call for our readers to submit their PCs over on the forums recently, and many of you responded. With dozens of entries and configs to choose from, we whittled down the list to a dozen of the best-of-the-best to crown a winner in the inaugural Tom's Hardware Premium Rig Rundown. There was a bevy of entrants, spanning from dedicated wall-mounted OpenClaw setups, all the way to PC's with all the screens and RGB you could shake a stick at.

Our panel of staff has reviewed your submissions, and we're ready to show you the shortlist that had us in awe. So, thanks to the dedicated community of enthusiasts and PC modders who showed us that dedicated PC building and PC modding are still well and truly alive in 2026, despite the best efforts of AI companies and hyperscalers pricing us mere mortals out of NAND and RAM.

So, without further ado, here are the builds that impressed us the most, with our lucky winner at the end of the article.

The PC Cruiser by MissMercedes

What do you do when you're a car expert and a PC enthusiast? Take an iconic Chrysler RC Car and turn it into a real, working computer, naturally. Car journalist MissMercedes did exactly that with the PC Cruiser.

A 1:6 scale RC car turns the chassis into a case, but with the nominal amount of space inside, some deep modifications were required by removing the rear seats of the PT Cruiser model to ensure that everything could fit inside. The next challenge was to find the components to actually fit inside. With a budget build in mind, MissMercedes found an Antec H310N ITX PC, sporting an Intel Core i5-9400, and 16GB of (presumably some kind of DDR4) RAM.

MissMercedes wanted to boast that the V8 moniker would also stand true for the number of cores inside, and so the CPU was later upgraded to an Intel Core i7-9700, with the motherboard supporting Wi-Fi and Bluetooth. After tossing in an NVMe SSD, it was off to the races.

One problem remained: the 90W power supply couldn't quite handle the heft of the upgraded CPU, and so MissMercedes locked the clock speed to 3 GHz. For a budget work computer, relying on integrated graphics is more than fine enough for a journalist (ask me how I know), so this build is designed for aesthetics, not pure computing heft.

Builder MissMercedes also has designs on upgrades in the future; Cooler Master's V-series coolers have an engine-like look, but were not yet available to purchase. Other potential additions include small speakers and a healthy dose of RGB. But, the most eyebrow-raising addition is the potential to add a battery, as the RC parts of the PT Crusiser chassis are still fully functional.

Our thoughts: The PC Cruiser

Andrew Freedman: I love seeing motherboards fit in unexpected chassis without requiring modification. That's my dream. I'm so glad that this exists for the sake of it, and that lots of other people could now go and just do it after seeing this.

Matthew Safford: This build gets points for its name alone! Not sure I'd love having to pop the hatchback every time I wanted to plug something into the rear ports, though. Can't wait to see what you do whenever Cooler Master gets around to releasing its new V-Series CPU coolers!

Stewart Bendle: This is awesome. Adding a personal touch by modding your PC in line with your hobby/career.

Joe Shields: Unique build for sure! Creativity is a '10' on this one. That said, I would have picked a different car for an even better 'cool' factor, but getting everything inside that little PT Cruiser RC car without any obvious modifications is an absolute win. Well done.

Brandon Hill: That's probably the coolest PT Cruiser that has ever existed. The battery upgrade would be a great addition to this rig.

Sayem Ahmed: Now, this is the exact kind of build that I wanted to see on Rig Rundown. Not everything has to have the best, newest, top-of-the-line specs, or have a set of Lian-Li's glowing power cables. Taking a lower-powered PC and stuffing the chassis into a pretty iconic car is great fun for a build. I love it. I don't think my aunt's old PT Cruiser was this cool.

The Master Center by DronePilot

DronePilot's setup is almost dizzying to get your head around. From the sheer number of screens, to simply imagining how to set this all up in the first place. Regardless, this is less of a rig and more of a command center. Sporting a 12th Gen PC, a Lenovo Legion Go, a Haswell-based Mini-PC, a 13th Gen Intel Laptop, and a 13th Gen HP ProDesk Mini all in one place, and to have it all work exactly the way you want it to, takes an astonishing amount of work.

It's not all about the PCs, though, as the setup also features a $500 speaker setup, a bevy of ports, full Cat5, routed through switches, and, indeed, runs underneath the house itself, offering you pretty much everything within arm's reach.

The setup also functions as a real-world call center and includes a KVM to manage the sheer number of systems (and the number of TVs and displays!) this rig offers. It's an appropriately complex setup that goes beyond the scope of many of our humble desks at Tom's Hardware.

The amount of effort that's gone into the Master Center is immediately apparent, which is why it made our shortlist.

Our thoughts: The Master Center

Paul Alcorn: I am a fan of huge monitors for productivity use cases; this is an awesome setup.

Matthew Safford: Love to see a TH reader who also uses a 55-inch TV as their main monitor. And there is plenty else to be impressed with here.

Is that an Intel 4th Gen Haswell Mini PC you've got running Windows 11? If so, kudos to your abilities, and for keeping a PC that is still useful out of the trash heap! If it does what you need it to do, it's still useful.

Joe Shields: I'm on the other side of large TVs for monitors... depends on the use case. High DPI or bust when you're sitting that close.

A mid-range system feels curious, but if it works for his purpose, it works! No need to overspend! Looks like you have command of darn near everything and the ability to easily access all systems. Well done!

Stewart Bendle: Definitely a fan of the command center. The warmest room in Winter.

Sayem Ahmed: DronePilot's Setup is mighty impressive. Everything from the frankly ludicrous number of screens, to the actual layout of the room itself is super-well considered. Special shout to the speaker setup too, it's a point that often goes missed in a lot of setups, but not this one.

The Wall-mounted masterpiece by SilenceIsGolden

When a lot of people make their PCs, they want them to stand the test of time. But, as technology moves on, it becomes inevitable that one day, you'll have to replace your beloved build. But, for SilenceIsGolden, who told their wife that this would be the only PC built in the next decade, they pulled out all of the stops.

The results are nothing less than beautiful, blacked-out and wall-mounted Antec Core P3 Pro in black serves as the ultimate commitment to a computer, designed to weather the storms of time itself. Featuring 96 GB of RAM, 8 TB of total NVMe storage, including a curious Intel Optane 900p 480GB drive, a rip-roaring 9950X3D, and RTX 4090, the computer is indeed no slouch.

Even more impressively, the entire system is custom-looped and water-cooled with a suite of AlphaCool waterblocks, covering the CPU, GPU, SSDs, EK Fittings, and D5 Next pump. This was complemented with a customized Thermaltake Core Pacific DP100 distro plate, which was painted black, with some custom heatsinks thrown on for aesthetics. Alongside a handful of finishing touches, like Lian-Li's light-up Strimer RGB power cables and Alienware AW3425DW OLED display to drive it all.

SilenceIsGolden's goal of building a silent, custom-looped build certainly looks the part, but they are still looking for a way to silence the Seasonic x Noctua Prime TX-1600's PSU coil whine. When fully mounted to the wall, and with the smart-looking RGB, this build certainly looks lovely and heavy.

Our thoughts: The Wall-mounted masterpiece

Sayem Ahmed: Silence is indeed Golden for this slick wall-mounted build. The blacked-out look is very nice, but it must be pretty hard to dust a semi-open-air case like this. I appreciate the dedication to water cooling here, too. While a lot of folks buy the glowing power cables to put some awful animation over it, this actually looks really nice. I would love to do something like this, but I would also live in fear of the PC falling and cleaning it. My only real worry is for the plaster on your walls.

Stewart Bendle: These dust magnets look very cool in a clean, minimalist room. The RGB and color choices work well.

Matthew Safford: It's great to see Intel's still impressive Optane 900p drive in a modern, powerful build. And I hope you picked up all 8.5TB of solid-state storage before prices started climbing last year!

Andrew Freedman: I've never been in love with the look of a Strimer, but I quite like the RGB on this one. It looks like the electricity is flowing out of the walls and through the rig.

Joe Shields: Wall-mounted builds always get the nod in my book. This one takes it to the next level with the matching water cooling ecosystem and overall clean appearance. The high-end hardware complements the build well.

The Home Arcade by Destruk

Who hasn't dreamed of reliving the glory days of gaming with a dedicated at-home arcade setup? Modern emulation has gotten to the point where it is a reality, and with a bit of love and effort, you can get your own arcade-perfect setup at home. Destruk's home arcade gaming machine sets out to do just that.

Sporting an Intel Core i7-14700K, 32GB of DDR5 RAM, a staggering 10TB in NVMe SSD storage, alongside a total 72TB in HDD storage, this setup is an arcade archivist's dream. Powering all the graphical heft of emulating MAME and CPS3 is an RTX 4060, which should do that job without so much as breaking a sweat. But the real beauty in this arcade setup is in the peripherals, of course.

A pair of Sinden Lightguns can emulate the arcade shooters of old, in addition to dual Atari Sixer joysticks, running through a serial to USB interface, two Atari Paddle controllers, two DualShock 3's, A Kensington Orbit Trackball, a Quickshot 2 joystick powering all the 90s action, in adition to two spinners, and two eight-button traditonal Noir Arcade layouts, complimented by a pair of eight-way joysticks and buttons, Skylanders Portal, and a Commodore 1541 disk drive. The arcade unit by GameRoomSolutions is wrapped in Gatchaman artwork, a nod to the classic anime, and whose cast features in the 2008 arcade fighter Tatsunoko vs Capcom.

This is all seemingly organized chaos, and it looks excellent. With the setup powered by a staggering 65-inch Roku TV, Destruk explains that the total cost of this setup came to less than $4,000, built before the RAMpocalypse. Somehow, Destruk still has three USB ports left and is planning to add a racing wheel and pedals.

Our thoughts: Home Arcade

Joe Shields: Yes, please. I always wanted a stand-up arcade game in my basement. The standup console with the buttons and the accessories on the wall is impressive.

Andrew Freedman: Do you have 'The Simpsons'? Can I come over and play 'The Simpsons'?

This system is prepared for everything. Lightguns? Atari joysticks? PS3 controllers (my least favorite PlayStation controller, but hey, not my rig!)? The Skylanders Portal of Power? That's dedication to playing games the way the developers intended.

Stewart Bendle: Everyone should have a home arcade. It should be mandatory. This is a sweet little construction that would certainly keep me entertained for days.

Sayem Ahmed: I have a real soft spot for emulation machines, and this feels like the natural conclusion of what I would want to achieve. It's great to see that the arcade spirit is alive and kicking, with a pair of Sinden Lightguns at the ready if you ever want to run through Point Blank or any other number of arcade classics at home. The mention of attaching a racing setup to this is interesting. I could use a bit of Outrun in my life. I'm also not sure how it's possible to work on 900 Pinball games, but if you can run Black Knight 2000 on there, I'll be at your door in a flash.

Manual Metal by Edman565 (Winner)

Manual Metal by Edman565 might be one of the wildest PC builds that we've ever seen at Tom's Hardware. Edman545's dedication to building the ultimate hard-lined, custom-looped build has collectively floored us.

From the images alone, we can see a total of 11 displays, and multiple devices powering Manual Metal, which has been named appropriately, as the build seeks to evoke the same feeling as tuning a manual car, with appropriate styling for the hard-lined steel pipes, and controlled via a custom built panel, with all of the switches and knobs you could want. Furthermore, the system has two radiators placed outdoors, for that extra cooling boon.

To get to the meat and potatoes of the build itself, we're looking at a Ryzen 9 9950X3D, alongside an AMD Radeon RX 9070 XT, 128 GB of DDR5 RAM, and a total of 3.5 TB of NVMe storage. But, the more impressive part of all this is the cooling setup, which is powered by a total of ten Noctua Industrial F12 fans, two PrimoChill radiators, a Thermaltake Pacific W8 on the CPU, an AlphaCool Core Swift on the GPU, dual-looped Bykski PWM pumps and reservoirs, and custom stainless steel tubing and valves.

Aside from the dizzying number of displays, there's enterprise-grade networking involved here too, with an Intel X550-T2 Dual 10GB/s PCIe adapter, a dedicated Creative Sound Blaster, and a Game Capture card too.

The cooling setup here is by far one of the most impressive things about this build: "I commissioned a custom mount for the reservoirs. I used two so that it can be configured as two loops, depending on which valves are open. Being the only clear part of this system, I can tell the water is flowing by the vortex created when the pumps are cranking," said Edman565.

They also noted that one pump could easily power the system, but installing two allowed for manual adjustment of the flow rate for the outdoor loop. Even more impressive, the custom control panel evokes a classic fighter-jet feeling, which was entirely custom-made just for Manual Metal. It's pretty astonishing and resulted in a near-unanimous win for our panel.

Our thoughts: Manual Metal

Matthew Safford: Love seeing those old Dell 4:3 monitors (which I remember using in my college's library) put to good use! There's so much impressive customization going on here, I don't even know where to begin.

Andrew Freedman: Sometimes, you just have to drop your hands in admiration that someone has done something that you will never have the skills, space, or insurance coverage to do. The PC is incredible, but I'm wowed by the home improvement work.

Joe Shields: Wow. This is. Wow. If I wasn't married with two kids, it's how I would do it. Custom controller, outside cooling, 3D printed parts. Absolutely amazing setup, even if some of the screens are 4:3.

Sayem Ahmed: I think we have our winner, folks. This is really one of the most impressive systems that I've seen to date. The control panel not only looks cool, but serves as an excellent way to measure things in an analog-like way without resorting to a screen, which is frankly, more boring, and way less cool than this.

I cannot imagine the number of man-hours that it took to build Manual Metal. Everything from the fluid paths to the cable management and sheer amount of effort and love radiating from this system is everything an enthusiast should aspire to.

DIY forever.

Well done to Edman565 for winning Rig Rundown with the astonishing Manual Metal build. We'll be in contact with you shortly.

CPU reviews aren’t made equally. They should, and do, follow the same process. I double-check everything on the test bed is the same, run a gauntlet of benchmarks using the same software stack and OS configuration, and spit the results out into various spreadsheets to eventually turn that raw data into hundreds of graphs for you to peruse. But the ups and downs during that process can vary wildly, and I was caught on the extreme end of that variation with Intel’s new Core Ultra 7 270K Plus and Core Ultra 5 250K Plus.

Blindly running benchmarks and throwing the data into a chart is a quick way to come to bunk conclusions. PCs and benchmarks aren’t perfect, and when you run as many benchmarks as we do here at Tom’s Hardware, it’s inevitable that you’ll encounter some strange results. The challenge with Intel's 270K Plus and 250K Plus was that those strange, unbelievable results were actually representative of the real performance of the chips. I spent no less than 50 hours (and probably more) simply rerunning benchmarks on various CPUs because I didn’t believe the results I was seeing.

That’s the best compliment I can give Intel’s small but potent range of Arrow Lake Refresh CPUs. There are still problems with them, and I want to make that clear lest this devolves into some marketing slop about unbelievable benchmark results. But the fact remains that I spent a lot of extra time sanity checking, because the performance was so impressive, and that’s worth closer examination.

The launch dust has settled on the 270K Plus and 250K Plus. The comparisons are in and the conclusion is clear: Intel made some compelling, value-oriented CPUs. Here, I’m going to take you behind the scenes of the testing process, as well as break down why these two CPUs are so important for Intel.

Arrow Lake is difficult to benchmark

There’s no other way to put it: Arrow Lake is annoying to benchmark. To avoid massive retests hours before a review embargo lifts, I’m constantly checking results against other data I’ve gathered to make sure my testing is on track. It’s much easier to quickly rerun a test with an odd result than it is to realize your data is off after you’ve already gone through a dozen CPUs. These checkpoints are even more important when working under an NDA. You’re working in a vacuum, bound contractually not to compare your results with other reviewers.

In generations past, it was pretty easy to know if you could trust the data you were seeing, but not with Arrow Lake. Even when the first CPUs rolled out, Intel made it clear that there would be performance regressions in some workloads. Further, there are still some workloads that do not play nicely with Intel’s Arrow Lake’s SoC-like CPU architecture.

Overall, the 270K Plus is about as fast as the Core i9-14900K and 2.4% faster than the Ryzen 7 9700X in games at 1080p. But in Minecraft, the Ryzen 7 9700X is nearly 50% faster. There are reasons why Arrow Lake chips perform poorly in this particular game: namely, how the maximum render chunk distance stresses the memory chain throughout your system, but the reasons aren’t important. When working in a vacuum, it’s hard to take these extreme outliers at face value.

That’s true at the other end of the spectrum, as well. Even looking at the multithreaded performance geomean, there’s reason to doubt the results. Am I supposed to believe that the 270K Plus is nearly 8% faster than the Core Ultra 9 285K, despite costing half the price and coming with a reduction in peak clock speed? Again, there are reasons for this discrepancy — in this case, a massive boost in die-to-die frequency — but these kinds of results pop up everywhere with Arrow Lake CPUs. You can come up with a technical explanation for a few odd results, but expand that over dozens of (what would otherwise be) outliers, and it gets difficult to trust you actually gathered the right data.

In fairness, this isn’t a problem specific to Arrow Lake, but it is a problem specific to any radical architecture shift. We just don’t see radical architecture shifts often. AMD has been building on the foundation of Zen for nearly a decade, and although Intel shook things up with Alder Lake and its hybrid architecture, it took a similar approach to what we saw in the 14nm days by pushing clocks and power as far as they could go. Arrow Lake completely threw a wrench in the system by not only featuring a hybrid core architecture, but also a disaggregated design and the elimination of Hyperthreading.

The difficulty comes up not in evaluating discrepancies, but rather in how big those discrepancies should be. It’s one thing to say that the Core Ultra 5 245K isn’t a very good gaming CPU. It’s another to say that it’s 7.5% slower, and not 10% or even 15% slower, than AMD’s Ryzen 5 9600X in games at 1080p. That is the challenge when reviewing Arrow Lake, and it’s a challenge I ran up against when evaluating the 270K Plus and 250K Plus.

Rerunning the test benches

After it was all said and done, I ended up retesting the entire Arrow Lake stack, short of the Core Ultra 5 225, which wasn’t included as part of my test pool. I rerun benchmarks all the time; that isn’t unique. But with the 250K Plus and 270K Plus, I reran the full suite of tests for each chip. That’s somewhere between 10 and 12 hours of testing per CPU for applications, an additional two to three hours for power testing, and another few hours for game testing. In other words, a full retest isn’t something I resort to lightly.

I had tested the main Arrow Lake stack prior to the 270K Plus and 250K Plus showing up on my doorstep. I use a frozen test image, so gathering that data early gave me some time when the CPUs showed up to deal with any anomalies. After they arrived and I ran my tests, that’s when the reality of retesting started to set in. Seeing multithreaded performance with the 270K Plus that outdid the 285K set off alarm bells. Especially in applications, both CPUs were handily beating chips that cost twice as much without batting an eye.

First, I started with the raw comparison points, retesting the 265K and 245K, and looking at the uplifts with their Arrow Lake Refresh counterparts using Intel’s data as a reference point. The results were the same. I then expanded up to the 285K and threw games into the mix. The results were the same. By the end of the gauntlet, I realized that the performance was so impressive that it made me doubt the reliability of a benchmark suite that’s been refined over the course of decades of CPU testing here at Tom’s Hardware.

A lot of that doubt comes down to how Intel positioned the 270K Plus and 250K Plus. We’re talking about a $300 and $200 CPU, respectively, and although prices have trended upward since release, they’re still value-focused, midrange chips, based on pricing. Based on performance, they’re a tier above what their prices would suggest and probably $100 cheaper than what the market demands.

It’s a radical departure for Intel. Since the dying days of 14nm, we’ve seen Intel slowly cede ground to AMD. But prices have slipped. Last-gen CPUs have become more viable from a value perspective, and Intel hasn’t been able to adequately address the gaming crowd with an X3D competitor. That all came to a head with the original launch of Arrow Lake. Intel was still postulating that it could counter AMD’s offerings point-for-point, but the data just didn’t back that up. We were left in a situation where Intel’s chips were so undesirable that CPUs that were two generations old were selling for more than the shiny new Arrow Lake options.

Intel needed a reset, both on pricing and messaging, to signal to buyers that although AMD dominates at the high-end, Team Blue can still deliver a lot of value around midrange price points. And the 270K Plus and 250K Plus are an aggressive reset. They deliver in an area that’s largely been ignored by AMD as it pushes out endless X3D variations, and the slightly elevated prices of Arrow Lake Refresh chips are a signal that Intel’s new position is paying off.

The question, and my concern, is how long this will last. It’s one thing to sell off silicon on a fire sale to make up for a lacking generation of chips. It’s another to commit to a new position in the consumer CPU market, especially after decades of being the top dog.

The Arrow Lake reset — and looking toward Nova Lake

Arrow Lake Refresh alone isn’t enough for Intel to turn things around on the consumer front. Let’s not be shortsighted. They’re great chips, and easy to recommend in a value-oriented build, but there’s a reason not a single Intel chip appears in the top 10 of Amazon’s CPU best sellers, and why its chips only occupy five of the top 25 slots. We can look at best-seller lists, region or retailer-specific data, or even the Steam hardware survey. But anyone who builds PCs and is around those who are building PCs doesn’t need to look far to see that you go with an AMD chip more often than not.

Intel can’t overcome that level of mind share with two CPUs, especially not two CPUs that still only manage to match AMD’s non-X3D offerings in gaming performance. What it can do is set the tone for Nova Lake.

One consistent thread throughout reviews of the 270K Plus and 250K Plus — and one I particularly harped on in my reviews — is the LGA 1851 socket. It’s a dead end. Intel hasn’t outright confirmed we won’t see another chip using this socket, but I’d be shocked if we did. And unlike sending out a long-lived platform on a high note, as we saw with AM4 and the Ryzen 7 5800X3D, LGA 1851 barely saw the light of day with the disappointing reception of the original Arrow Lake chips.

Regardless if you upgrade your CPU every generation or wait for a new memory standard to finally make a platform swap, socket longevity is important. It’s not just about if you’ll upgrade to a new CPU; it’s about having the option to upgrade. It’s why you buy a motherboard with four M.2 slots even if you’ll never fill them. It’s why an ATX board comes with four DIMM slots despite the fact that most builders will only occupy two. The option to upgrade your CPU is powerful, even if you’ll never do it. Buy into an AM5 platform, and you can go further in the future. Buy into an LGA 1851 platform, and you’re already restricting yourself to a full motherboard and CPU swap down the line. This shouldn’t be your only consideration when choosing a CPU, but these types of differences can sway a buying decision when other differentiators are exhausted.

Intel, I suspect, is aware of this. We don’t know if the LGA 1954 socket that Nova Lake chips will use will continue forward for multiple generations, but it’s a lot easier to buy into a platform that’s just rolling out than one that already has a foot out the door. The stance Intel is taking with the 270K Plus and 250K Plus, situating itself as a value-oriented alternative that punches above its price tag, has to extend beyond these two CPUs, onto a platform that future-looking buyers are willing to invest in.

That’s what I’m looking for with Nova Lake. We have big rumors about Intel’s X3D competitor, supposedly called bLLC, and speculation about a 44-core flagship. That’s great, and I’m sure there will be fireworks between AMD and Intel at the high-end. It’s these chips like the 270K Plus and 250K Plus, however, where Intel needs to take ground. Arrow Lake Refresh is resounding proof that it can occupy that space. Let’s just hope Intel doesn’t change its mind again.

Intel’s Arrow Lake platform was a huge disappointment at launch. It barely managed to compete with its predecessor, Raptor Lake Refresh, in gaming performance, all while AMD’s X3D CPUs continued to dominate the rankings among the best CPUs for gaming. Intel responded with heavy price cuts, but the situation was too far gone by then.

Now, we have a new challenger. The Core Ultra 7 270K Plus has launched at a remarkable $300 price point, $100 cheaper than what the Core Ultra 7 265K launched at, all while showing big increases in gaming and productivity performance. Intel is trying (maybe desperately) to regain the ground it lost with the original Arrow Lake and succeeding.

Its competitor for today’s faceoff is the Ryzen 7 9700X. Although on paper it has a lot fewer cores than the Core Ultra 7 270K Plus, it is in the same price bracket as the Intel chip. This is a purchase decision potential buyers may face when they have $300-$350 to spend on a new CPU.

Let’s run these two CPUs through our rigorous six-round gauntlet to determine which CPU is truly the best, and if Intel has made a successful attempt at redemption.

Features and Specifications: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

Under the hood, Arrow Lake Refresh is exactly what it sounds like. The Core Ultra 7 270K Plus is based on the same microarchitecture as the 265K, built using TSMC’s 3nm process. Intel has provided 24 total cores in the 270K Plus, split into 8 Lion Core P-cores and 16 Skymont E-cores. There is only one thread per core across all Arrow Lake CPUs, bringing the total thread count to 24.

Intel claims that the 270K Plus is not just a better binned Arrow Lake CPU, but rather a new wafer and product code. Nevertheless, the main difference between the 270K Plus and the 265K is the clock speed. The Core Ultra 7 270K can climb up to 5.4 GHz on the P-cores, while the E-cores can boost up to 4.7 GHz. Being a K-series SKU, the multiplier is unlocked, giving you full access to overclocking.

Core clocks aren’t too different, but uncore clocks have shifted a lot. Intel increased the die-to-die frequency by 900 MHz compared to stock Arrow Lake chips, as well as bumped the fabric frequency by 400 MHz.

The chip also supports DDR5 memory at 7200 MT/s and 20 lanes of PCIe Gen 5. There is a total of 76MB of cache on the chip, with 36MB of that being L3 cache. Intel has kept the same power limits for the 270K Plus as the previous Ultra 7 CPUs, with a TDP of 125W and MTP boosting to 250W. The CPU uses the same Intel LGA 1851 socket and is compatible with existing 800-series Intel motherboards.

Its competitor, the Ryzen 7 9700X, is also no slouch on the spec sheet. Based on the Zen 5 architecture and built on TSMC’s 4nm production process, the Ryzen 7 9700X is compatible with the AM5 socket and existing 800-series AMD motherboards. It uses AMD’s chiplet-based design with core complexes, which has been very successful in previous Ryzen CPUs.

The 9700X has 8 cores and 16 threads, with no P-core and E-core split. The CPU supports DDR5 memory at 5600 MT/s and provides 24 PCIe Gen 5 lanes. Although it does not have the ridiculous amount of L3 cache as its X3D siblings, it still has a respectable total of 36MB. AMD markets the 9700X with a TDP of 65W and an extended TDP of 105W.

The boost clock of the Ryzen 7 9700X is 5.5 GHz, which is exactly the same as the maximum turbo boost of the 270K Plus. All AMD Ryzen CPUs are unlocked, so you can overclock the Ryzen 7 9700X as well.

Comparing the two CPUs on paper is a bit complicated since their architectures and core layouts are so different. Intel clearly has the superior core/thread count and a slightly more modern underlying architecture. The clock speeds are very similar, but Intel supports higher-speed memory as standard. On the flip side, Intel has much higher power draw ratings.

⭐ Winner: Intel Core Ultra 7 270K Plus

While it is not possible to say which CPU is better just by looking at specs on paper, Intel clearly puts up a better showing in this round. The 9700X does provide more PCIe lanes and a lower TDP, but Intel wins out in almost all other categories.

Gaming Benchmarks and Performance: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

We ran both CPUs through a gauntlet of games across a wide variety of genres to get a good idea of average performance. The 1080p resolution was chosen since it maximizes the CPU usage and allows us to see the difference between the two chips. We also used the GeForce RTX 5090 graphics card to minimize GPU bottlenecks. You can read our individual reviews of both the Core Ultra 7 270K Plus and the Ryzen 7 9700X to get a more in-depth analysis.

Kicking things off with our 17-game 1080p performance geomean, the Core Ultra 7 270K Plus puts out an average FPS score of 162.2, leading the Ryzen 7 9700X’s average score by 2.4%. The gap between the two CPUs is slightly larger when looking at 1% lows. In our geomean, the Core Ultra 7 270K Plus scores 6.1% better 1% lows than the Ryzen 7 9700X. So far, so good for Intel.

Looking at individual benchmarks tells an interesting story. In A Plague Tale: Requiem at 1080p, the Core Ultra 7 270K Plus actually trails the Ryzen 7 9700X by 3.2% on average. However, the 1% low numbers are flipped, as the Core Ultra 7 270K actually has a 14% better result in this particular title. The trend returns to normalcy in Cyberpunk 2077, where the Core Ultra 7 270K is 8% faster in both average FPS and 1% low results.

Elsewhere, we saw wins for the Ryzen 7 9700X, including in F1 2024, where it leads by a noticeable 13% on average. The 9700X also crushed it in Minecraft, leading by 33% in average FPS. However, both CPUs were tied in 1% low results at exactly 57 FPS, which is a peculiar result. Arrow Lake CPUs broadly don’t play nicely with Minecraft with a maximum render chunk distance of 96.

The Core Ultra 7 270K Plus also saw some big wins. In Hitman 3, the new Intel chip scored a 13% lead over the Ryzen 7 9700X, while also being 7% faster in 1% lows. Hogwarts Legacy also favored Intel heavily, leading to a 12.4% better average FPS result for the 270K Plus in this game. Both of these games support Intel’s new iBOT feature, which improves gaming performance in select titles.

It is safe to say that the two CPUs trade blows when it comes purely to gaming performance. We also saw some results that were essentially tied, such as Monster Hunter Wilds, Final Fantasy XIV, TES Oblivion Remastered, and Baldur’s Gate 3. However, the Core Ultra 7 270K Plus slightly edges the Ryzen 7 9700X, delivering 2-3% better average gaming performance.

While gaming, the Core Ultra 7 270K Plus drew 107.7W, which is a big bump over the Core Ultra 7 265K. It is also 18% higher than the Ryzen 7 9700X, which drew an average of 87.8W while gaming. However, when we look at efficiency numbers calculated in FPS/W, the new Core Ultra 7 270K Plus is still 2.6% more efficient while gaming than the Ryzen 7 9700X. The temperatures of the two CPUs were not significantly different in our testing.

Intel has launched the Core Ultra 7 270K Plus at a very competitive $300 price point, and that favors it quite well in the value conversation. Calculating the value using FPS-per-dollar, the Intel CPU edges out the Ryzen chip by 5.5%. The $10 price premium of the Ryzen 7 9700X, combined with its marginally lower gaming performance, makes it a slightly worse value compared with the Intel Core Ultra 7 270K Plus.

⭐ Winner: Intel Core Ultra 7 270K Plus

Intel’s new CPU puts up an impressive showing in the gaming round of this faceoff. While the advantages are marginal, it provides slightly better gaming performance than the Ryzen 7 9700X at a lower price, though it consumes a bit more power.

Productivity Performance: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

We also put the Core Ultra 7 270K Plus through its paces against the Ryzen 7 9700X in a series of productivity tasks. These tests cover both single-threaded and multi-threaded applications to give us a good idea of the general performance level of the two CPUs. While the Core Ultra 7 270K Plus clearly has way more cores, the comparison makes sense since both CPUs are very similar in price at the time of writing.

We have a huge result for the new Core Ultra 7 270K Plus right off the bat when we look at our multithreaded performance ranking geomean. The Ultra 7 270K Plus delivers chart-topping multi-core performance in our testing, and leaves the Ryzen 7 9700X in the dust. Comparing the geomeans, the Core Ultra 7 270K Plus is a whopping 77% better than the Ryzen 7 9700X in our multi-core tests on average. That is almost double the productivity performance.

Looking at individual benchmark results, we see the Core Ultra 7 270K Plus take a gigantic 90% lead over the Ryzen 7 9700X in the Cinebench 2024 multi-core test. The POV-Ray test isn’t much better for the Red Team, as the Core Ultra 7 270K Plus has a staggering 127% higher score in this test. The lead is 74% in Blender Junkshop, 92% in V-Ray 6, and 73% in HandBrake x265 10-bit encoding test. You get the idea.

The driving force behind Intel’s dominance in this round is the superior core/thread count of the Core Ultra 7 270K Plus. While the Ryzen 7 9700X is quite a competent 8-core, 16-thread CPU, its core layout pales in comparison to the 24-core, 24-thread 270K Plus. You can argue that the 16 E-cores don’t really contribute a lot in performance, but you can’t really bet against raw core count when it comes to multithreaded productivity performance.

Single-threaded performance also follows the same trend, though the differences are much less dramatic this time around. Our single-threaded performance ranking geomean still has the Core Ultra 7 270K Plus at the top of the pile, with an average 10% higher score than the Ryzen 7 9700X. It also improves upon the Core Ultra 7 265K by about 3.3%, which is a welcome bump in single-threaded performance.

Cinebench 2024’s single-core test puts the Core Ultra 7 270K Plus ahead of the Ryzen 7 9700X by 5.4%, while Cinebench 2026 sees the lead grow to about 7.8%. In the Lame Extended single-thread audio encoder, the Core Ultra 7 270K Plus was about 3% faster than the Ryzen 7 9700X to deliver the finished file. The POV-Ray chart shows the Intel CPU pulling ahead by a much larger margin of 36.2%, but that result seems to be more of an outlier.

With a standout lead in both multi-core and single-core performance, the Core Ultra 7 270K Plus should be the clear choice for consumers who are looking to use their PCs for both gaming and productivity. Frankly, the Core Ultra 7 270K Plus gives much more expensive CPUs in this category a tough time, making it an excellent value for productivity.

⭐ Winner: Intel Core Ultra 7 270K Plus

Thanks to its superior core count, the Intel Core Ultra 7 270K Plus absolutely dominates the Ryzen 7 9700X in our productivity benchmarks, taking home this round by a landslide.

Overclocking: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

The Core Ultra 7 270K Plus ships with a 900 MHz bump in die-to-die clock speed compared to the Core Ultra 7 265K. This suggests that Intel has pretty much cranked all the knobs to the maximum straight from the factory. However, a unique new feature is that the bump in die-to-die frequency is now standard, and you don’t need a Z-series board to unlock it.

With a Z-series motherboard, you can get more granular in your overclocking. Intel has controls for core overclocking, of course, but also levers for uncore frequencies and official support for far higher memory speeds. Although the disappointment of Arrow Lake has stained its reputation, this generation introduced some of the deepest overclocking features we’ve ever seen, and they shine on the Core Ultra 7 270K Plus.

AMD’s Zen 5 chips still feature the same tried-and-tested overclocking suite, with the main focus on Precision Boost Overdrive 2 (PBO2) and Curve Optimizer. PBO2 allows users to let the CPU govern itself and adjust its frequencies based on available power and thermal headroom.

Curve Optimizer is another key feature that enables finer control. You can achieve even greater gains by fine-tuning the voltage offsets per core. This can often lead to sustained higher boost clocks without manually setting fixed high voltages or frequencies. While manual overclocking is still possible on Zen 5 CPUs, the best and most consistent results often come from Curve Optimizer and Precision Boost Overdrive 2.

While both CPUs offer unlocked multipliers, they take different approaches to overclocking. Intel’s approach offers slightly greater flexibility, and its CPUs traditionally have more overclocking headroom, though this is subject to the silicon lottery. AMD has better automated features, such as PBO, but overclocking gains are often minimal.

⭐ Winner: Intel Core Ultra 7 270K Plus

Both CPUs have compelling overclocking features, but Intel just edges it out in this round thanks to greater flexibility with its overclocking tools.

Power Consumption, Efficiency, and Cooling: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

With the launch of Arrow Lake, Intel shifted its focus to efficiency, sacrificing some performance in the process. The Core Ultra 7 270K Plus takes things back slightly in the power consumption department, pushing the power limits for more performance. We’re using the default 65W TDP for the Ryzen 7 9700X here, though note its power consumption will increase significantly with its optional 105W TDP mode.

Starting with idle power consumption, the Core Ultra 7 270K Plus consumes an average of 29 watts in this test, while the Ryzen 7 9700X is around 31% lower at 22 watts. The Core Ultra 7 270K Plus also consumes 4 more watts at idle than the Ultra 7 265K. When in an active idle state, such as YouTube playback, the Core Ultra 7 270K Plus spikes to 38 watts, a clear and noticeable 52% increase over the Ryzen 7 9700X.

Moving on to all-core workloads to gauge peak power consumption, the Core Ultra 7 270K Plus consumes a whopping 198% more power than the Ryzen 7 9700X in the y-cruncher multi-threaded AVX test. That largely comes down to Zen 5’s implementation of AVX-512, which allows the Ryzen 7 9700X to run these SMID-style instructions far more efficiently.

In Cinebench 2024’s multi-core render, the Core Ultra 7 270K Plus consumes around 160% more power than the Ryzen 7 9700X. Of course, as we saw earlier, the 270K Plus also delivers around 90% better performance than the Ryzen 7 9700X in this test, but the raw efficiency numbers still favor AMD.

Looking at a few more benchmarks, the same trend can be seen in Blender - Monster, where the Core Ultra 7 270K Plus consumes 151% more power than the 9700X. Interestingly, the new Arrow Lake Refresh CPU also demands 45% more power on average than the Core Ultra 7 265K, a significant difference. Between the 270K Plus and the Ryzen 7 9700X, the power demand gap is around 145% in HandBrake x265 encoding, 161% in HandBrake SVT_AV1, and 179% in Blender Classroom.

We can also look at the performance-per-watt numbers from various benchmarks to gauge the efficiency of the two CPUs. First, in HandBrake x265 encoding, the Core Ultra 7 270K Plus is around 29% worse in watts-per-fps than the Ryzen 7 9700X. In Linpack, the efficiency gap narrows to around 10%, still in favor of the Ryzen 7 9700X. Cinebench 2024 also shows the points-per-watt calculation favoring the AMD chip by about 20%.

Another neat way to visualize the power consumption difference is by a scatter plot, which shows the relationship between power and performance a bit more clearly. In the Linpack efficiency graph, the Core Ultra 7 270K Plus is plotted to the far bottom right, while the 9700X is a bit to the middle. This means that the 270K Plus delivers much better performance with only a slight increase in power draw.

The Blender Classroom scatter plot is much more interesting. While the 270K Plus is still plotted to the far right, it is much higher on the task energy axis this time around. The 9700X is almost at the bottom-left of the graph, making it much more efficient than the 270K Plus at this task, even though its performance is quite a bit lower.

The entire conversation about power consumption is quite interesting. On the one hand, the Ryzen 7 9700X is much more efficient and consumes much, much less power than the 270K Plus, but its overall performance level is also quite a bit lower. It almost seems like the two CPUs are not in the same class, but their price tags suggest otherwise.

⭐ Winner: AMD Ryzen 7 9700X

The AMD Ryzen 7 9700X consumes less than half the power on average than the Core Ultra 7 270K Plus, and is also more efficient in several tests, making it the clear winner in this round.

Pricing: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

Intel has launched the Arrow Lake refresh CPUs at a very competitive price point. The $300 Core Ultra 7 270K Plus is almost $100 cheaper than the Core Ultra 7 265K when it launched. This puts it in the same ballpark as the Ryzen 7 9700X, which can be found at around $310 at the time of writing. However, comparing the prices of the two CPUs is not as straightforward as just comparing the numbers on the box.

To get a clearer idea of how much each CPU costs, we need to evaluate the total cost of the platform. While the Core Ultra 7 270K Plus is slightly cheaper up front, it may not be more affordable once we factor in the cost of other components such as RAM, a compatible motherboard, and a CPU cooler. Due to how recent the Core Ultra 7 270K Plus is, prices have shifted up toward $350, as well.

DRAM prices are absolutely ridiculous at the time of writing due to the global memory shortage, so the numbers here may change. Both CPUs are compatible with DDR5 memory, which is why this particular cost is shared. A decent 32GB (16x2) DDR5 memory kit running at 6000 MT/s at CL36 can run you about $350-$400 at current rates.

The pricing conversation becomes more interesting once we get to the motherboards. Intel’s LGA1851 platform offers multiple chipsets at different price points, but we would go with Z890 motherboards to take advantage of the unlocked multiplier. A basic Z890 motherboard is currently in the $200-300 range, but you can go with more feature-rich variants that can cost as much as $600 for the really fancy ones.

On the AMD side, the AM5 platform has matured a bit and is not quite as expensive as Intel. Our chipset of choice for the 9700X is the X670E, the top-of-the-line AM5 chipset for this generation. A basic X670E motherboard can be found in the $150-200 range, while a more competent offering can be in the $300-400 range, slightly less than Intel’s offerings. You can even go with a more affordable B-series motherboard and still take advantage of the 9700X’s overclocking capabilities.

For cooling, both CPUs need competent aftermarket solutions. For the 270K Plus, a high-end dual-tower air cooler ($100-120) or a 360mm AiO liquid cooler ($150-250) is recommended, given its higher power draw. You can get away with a 240mm AiO liquid cooler on the Ryzen 7 9700X ($80-150), but just to be on the safe side, investing in a 360mm AiO is not a bad idea.

Currently, AMD makes a much stronger case for total platform cost. It can be paired with more affordable motherboards without losing functionality, and it is also easier and cheaper to cool. Plus, it draws much less power, which can affect other purchasing decisions, such as the power supply.

Moreover, Intel’s LGA1851 is basically a dead-end platform. We do not expect another CPU release on this platform, which is a big factor in determining the overall value of this investment. On the flip side, AMD has committed to supporting the AM5 socket until at least 2027, which makes it much better from a longevity standpoint.

⭐ Winner: AMD Ryzen 7 9700X

While the Core Ultra 7 270K Plus is slightly cheaper up front, its total platform cost is higher, which makes it a difficult bargain. Socket LGA1851 is also on its last legs, which does not do the value proposition any favors.

Bottom Line: Intel Core Ultra 7 270K Plus vs Ryzen 7 9700X

With a dominant 4-2 lead in our six-round gauntlet, the new Intel Core Ultra 7 270K Plus decimates the Ryzen 7 9700X. Intel is seeking redemption with Arrow Lake Refresh, and they seem to have taken a step in the right direction with the 270K Plus.

The Ryzen 7 9700X put up a respectable showing in our gaming and productivity tests, but it was beaten in both rounds by the Core Ultra 7 270K Plus. The productivity numbers are particularly astonishing, as the gap is so big that you are almost forced to double-check the numbers.

The obvious caveat is power draw. Intel has increased the power draw of the 270K Plus quite significantly over the 265K. This also means that it consumes around 150-200% more power than the Ryzen 7 9700X in certain all-core workloads, though that gap shrinks if you plan on running the 9700X in its 105W mode. It is also a bit more costly once you factor in the price of the entire platform. Not to mention, the LGA1851 platform is on its way out with Nova Lake, which Intel says is on-track to launch this year.

Nevertheless, the Core Ultra 7 270K Plus has its place. It is a very competent $300 CPU that decimates most of our lineup in productivity, though it is still a bit behind the Ryzen X3D CPUs in gaming. As for the Ryzen 7 9700X, it seems overdue for a price cut, as it doesn't justify its $310 price tag when more compelling options are available at a similar price.

⭐ Winner: Intel Core Ultra 7 270K Plus

More CPU Faceoffs

• AMD Ryzen 9 9950X vs Intel Core i9-14900K
• Intel Core i5-14400 vs AMD Ryzen 5 7600X
• AMD Ryzen 7 9850X3D vs Intel Core i9-14900K
• AMD Ryzen 7 9850X3D vs Ryzen 7 9800X3D

PCI Express (PCIe) is a foundational technology that's been around for decades, and that's not going to change anytime soon. The standard is set to change and evolve over the coming years, and the technology has a rich history behind it, too. PCIe inherited elements from the original PCI standard (such as configuration space, PnP, BARs, and command/status registers), so the history of this technology stretches into the annals of computing history.

Ever since its introduction in 2004, PCIe has been evolving in accordance with a simple rule: each new major revision roughly doubles link bandwidth while maintaining backward compatibility. The pace of formally introducing a new PCIe version every three or four years remained mostly stable, barring a major slip between PCIe 3.0 and PCIe 4.0. But what changed in recent years is not the pace, but the difficulty of each new iteration. Early generations increased throughput almost effortlessly by doubling transfer rates (clocks) and improving encoding efficiency. Today, the roadmap pushes PCIe directly into the territory where manufacturing tolerances, materials, and retimers define what is possible and how much it costs.

Nonetheless, PCI-SIG, the standard that oversees the development of PCIe and adjacent standards, continues to steadily introduce new PCIe generations every three to four years, ensuring its relevancy for years to come. Before diving into the future of the standard, let's first take a look back at history.

A quick look back

PCIe began as a replacement for shared buses in the early 2000s and introduced point-to-point connections and scalable lane counts. PCIe 1.0 operated at a 2.5 GT/s data transfer rate per lane, followed by PCIe 2.0 at 5 GT/s. PCIe 3.0 increased the data rate to 8 GT/s, which was far from doubling the prior generation, but introduced a more efficient 128b/130b NRZ encoding scheme, which significantly reduced protocol overhead.

PCIe 4.0 doubled the transfer rate to 16 GT/s in 2017, and marked the first time where a new PCIe revision was adopted by enthusiast-grade desktop PCs only two years after the formal publication of the standard.

PCIe 5.0 followed in 2019 at 32 GT/s per lane, and brought the electrical designs of data centers to client systems, requiring higher-grade PCB materials and stricter signal-integrity controls. Now, the bus provides up to 128 GB/s bidirectional bandwidth through an x16 slot, which is an overkill for consumer graphics cards, but increasingly useful for AI accelerators and high-end storage.

While PCIe 5.0 connectivity is must have for data centers, not every mainstream and entry-level consumer PC supports PCIe 5.0 for SSDs and graphics cards, which highlights that the cost of the technology introduced in 2019 is still fairly high for inexpensive computers.

PCIe 6.0: An inflection point

Introduced in 2022, PCIe 6.0 represented a major inflection point for the technology: instead of driving conventional two-level signaling to ever higher frequencies, the specification transitioned to PAM4, a four-level modulation method that carries two bits per symbol, and introduced 242B/256B FLIT encoding. This change allows throughput to double to 64 GT/s per lane without doubling the clock rate, but it comes with severe tradeoffs.

Multi-level signaling methods like PAM4 compress voltage margins dramatically, making them far more sensitive to electrical noise, jitter, crosstalk between lanes, and even tiny imperfections in PCB manufacturing, something that historically reserved this transmission method in enterprise-grade networking like 400Gb Ethernet or InfiniBand.

To ensure that everything works, PCI-SIG mandated forward error correction (FEC) and significantly more complex equalization, which is costly in terms of silicon complexity (more compute power required), added latency, and power.

To a large degree, PCIe 6.0 controllers with Physical Interfaces (PHYs) now resemble mixed-signal processors, rather than simple interfaces, as they now have to pack DSP blocks for high-resolution analog processing, adaptive equalization, and FEC engines, which all consume power. Furthermore, validation requirements across the platform are much tighter with PCIe 6.0 compared to previous generations.

Meanwhile, from a platform perspective, the greatest limitation is no longer bandwidth or latency; it is distance. At PCIe 4.0's 16 GT/s and PCIe 5.0's 32 GT/s, system designers can still route signals across motherboard traces up to 11 inches under favorable conditions using quality materials. This is no longer the case with PCIe 6.0. According to channel-loss figures published by Astera Labs, a direct copper trace operating at 64 GT/s can span as little as 3.4 inches under a 32 dB loss budget, depending on materials and conditions.

To a large degree, such constraints redefine motherboard engineering: lengths once considered trivial now require architectural decisions, since factors like dielectric loss, copper surface roughness, via impedance, and connector discontinuities all affect signal integrity. Consumer-grade laminates have also become inadequate, mandating manufacturers to use high-cost, low-loss materials typically reserved for networking equipment.

Furthermore, since raw copper can no longer maintain usable eye graph margins across practical distances, retimers are no longer optional for meaningful distances between the root complex and the slot: modern servers with PCIe 5.0 use between 17 and 24 of them, and PCIe 6.0 is set to raise that dependency dramatically. For example, two retimers per link can extend a PCIe Gen6 trace reach to roughly 10 inches, but the PCIe specification does not allow more than two retimers between a host and an endpoint, so server motherboard designers must be creative.

Retimers are not a panacea, though: each retimer adds unavoidable latency, cost, validation burden, and power draw, easily adding over 200W per server. Connector design faces similar pressure. Interfaces originally designed for signaling in the low single-digit GHz range are now expected to operate cleanly at tens of GHz, which is why companies like Molex are introducing new connector and cable families explicitly for PCIe 6.0 and 7.0. Obviously, such connectors and cables are expensive, complex, and physically larger than they used to be in PCIe 4.0 times.

Given all the complexities surrounding PCIe 6.0, Wallace C. Kuo, chief executive of Silicon Motion, says that he does not expect consumer-grade SSDs with a PCIe 6.0 interface to become a widely-adopted product before 2030.

PCI 7.0, 8.0 and beyond

Beyond PCIe Gen 6, the roadmap remains consistent in terms of cadence and performance increase, but hardly in terms of implementation and adoption cadence by the industry. PCIe 7.0 targets another performance doubling to 128 GT/s per lane, but this time actually increasing clocks and further refining the PAM4 modulation scheme and tightening electrical tolerances.

PCIe 8.0, which is still under development, aims to double that again to 256 GT/s with the specification available sometime in 2028. If achieved, an x16 connection would approach an almost 1 TB/s of aggregated bandwidth in both directions. Whether such speeds remain viable on copper is an open question. Connector vendors are already developing specialized hardware, including extended-reach cables and high-density sockets, to accommodate future data rates. Optical interconnects and co-packaged PHY designs are no longer academic exercises and could become requirements at some point, although Al Yanes, the head of PCI-SIG, implies that the organization is looking forward to enabling a 256 GT/s speed over copper. Only time will be able to tell if that'll become a reality.

The future of PCIe: Predictable performance, demanding silicon

One notable question about the evolution of PCI and PCIe technologies is what defines them at different parts of their history. Intel originally began developing PCI for desktop PCs in 1990, only envisioning its entrance in the server space in the mid-1990s. Yet, by the time PCIe entered the scene, Intel was dominating the server market early in the new millennium.

Both PCI and PCIe were originally designed with PCs in mind as PC sales grew at a high pace in the 1990s and early 2010s, driving sales of bandwidth-hungry graphics cards that were (and still are) mandatory for video games. Over the following years, the growth of cloud infrastructure flourished, demanding its own set of capabilities and costs. Today, AI infrastructure dominates, setting new targets for performance and capabilities.

In general, the PCIe roadmap still promises predictable performance growth. But given what application is now driving the IT world, maintaining that pattern now demands exponential increases in engineering effort. Higher data rates shorten trace distances, raise board costs, and require more active silicon to preserve signal integrity. But at the same time, make more work done at any given second, thus maximizing performance efficiency.

However, whether future generations remain electrical or transition toward optics, PCI Express is no longer optional; it is the structural backbone of modern compute systems, starting from a humble PC all the way to Elon Musk's Colossus with hundreds of thousands of Nvidia GPUs.

Back in February, we had the opportunity to attend WD's (formerly Western Digital) Innovation Day 2026, where the company outlined its plans for the future. Notably, the company discusses its split from SanDisk, and it's expectations for the future, including discussion around its HAMR roadmap, in addition to its ePMR discussions, and fielding questions from analysts.

Like many of our previous event transcripts, this is almost exactly what we heard at the press-only event. As such, some elements have been lightly edited for flow and clarity. If you have not had the chance to check out other Tom's Hardware Premium transcripts, be sure to check out our coverage from CES and GTC 2026.

Ambrish Srivastava: I guess we have to go first with Amit in that case, so just a quick — we have mic runners, there's four of us, we'll start off with Amit, and then we'll queue up Aaron Rakers, right next to Amit. Ah, name and firm, please.

Amit Daryanani: Thanks a lot; Amit Daryanani, Evercore. Thanks for the presentation. The two things that stood out, and I'd love to get your perspectives on this; one is the cost-per-bit decline—if you could just talk about how you are thinking about cost-per-bit declines over the next three to five years of the roadmap. Is that different in ePMR versus HAMR? Just, if you can walk through that math a little bit.

And then, Irving, for you, it seems like you want to commit towards an ePMR and a HAMR roadmap at least through 2028; if all customers care about is 'the highest capacity', 'the most reliable at scale', why have a dual technology roadmap when it seems like HAMR is going to work out? Just walk through the dynamic given what customers are asking for. Thank you.

Irving Tan: That sounded like more than one question, in one question. [laughing] So, let me try to address the cost-down question for a second. Obviously, you know, the cost down that was delivered, dollar per teraybte, has been about ten percent over the last few quarters. Obviously we're not guiding to anything beyond that, but more importantly, what you've heard Ahmed, even as we deliver a roadmap that has both HAMR and ePMR, the common platforming that we've done to ensure that it's common mechanicals, the fact that we've internalized our own laser capability, gives us the confidence that we'll be able to maintain a very competitive cost-down trajectory going forward.

In relation to the roadmap — and I think Ahmed, it's cool for you to join in — obviously what we want is to give our customers very smooth transitions, and you've heard how risk-adverse they are to transitions given the size and scale and the importance of storage to their business. So we'll continuously work with our customers to make sure that the economics work for them, the economics work for us. The reality is, as we go beyond, say 60, 70, we will have to transition to HAMR. As we get to 80, 90, 100 terabytes, there is — at some point, the laws of physics will require us to transition to HAMR, but we want to do it in a way that makes economic sense, that manages risk, gives our customers smooth transitions, AND equally important, makes economic sense for us, as well. The benefit we have is that we're able to do both whilst delivering the strong financial performance that Kris read off.

Ambrish Srivastava: I'm going to go to Aaron and after that we'll come to Erik over here.

Aaron Rakers: Thank you, Ambrish. Aaron Rakers, with Wells Fargo. First question on the laser, the integration of the laser technology, I'm curious — and I apologize if I missed this — can you help us appreciate when that inserts itself in the roadmap? Is that a point of gross margin leverage, are there any kind of further details on how we should think about that technology path as we go to the HAMR?

And then Kris, for you, I just want to ask, I mean — first of all, congrats on the Sandisk ownership, it's $5.075 billion [laughing] I'm curious if, as we pivot now to this significant free cash flow generation that appears to be supported by this model, how do you actually structurally think about your capital structure? You know? Are you wanting to build cash in a balance sheet, what's the appropriate level of cash to run the organization; I'm just trying to get a frame for how you think about excess cash generation because you clearly are going to have a lot of capacity for capital return; I'm curious about how you, longer-term, think about that. Thank you.

Irving Tan: You can go ahead and take the laser question.

Ahmed Shihab: Yeah, well — I was hoping that Kris would answer the laser question too. [laughing]

Kris Sennesael: I can, but please go ahead. [laughing]

Ahmed Shihab: Oh, thank you. The laser technology, it's — it is smaller, it is cheaper for us to produce, so that is going to be useful and accretive to the business, and we are starting a slow ramp in introducing it. So it's not going to be a lightswitch transition because we want to be careful about when we transition that. So we'll start that transition right around the 48-, 40-terabyte range, and even a little bit before that.

Kris Sennesael: In terms of capital structure; so, assuming a successful monetization of the Sandisk shares, we're going to end up with $1.6 billion dollars of debt on the balance sheet, which is the convert. At the appropriate time, I want to get rid of the convert, but still keep about $1.6 billion dollars of debt on the balance sheet. So yes, we have strong free cash flow; the intent is to return all of that free cash flow back to the shareholders.

Ambrish Srivastava: We're going to go to Erik and then we'll tee up Asiya over here, and then Wamsi after that.

Erik Woodring: Awesome. Good morning guys. I'll rebut Aaron and say, remember you guys once had 23 million shares of Sandisk, and— [laughing]

Irving Tan: Hindsight is 20/20, Erik. [group laughing]

Erik Woodring: Very true. No, thank you guys for all the content here. I just want to break it down, which is — we've gone through a lot of different configurations and platforms that you're introducing; they all have 11 platters on them. Your competitor is coming out with HAMR with 10 platters. How do you remain price-per-terabyte, price-per-exabyte competitive; how do you continue to push down cost per terabyte when we have that kind of differential. What are you doing differently that allows you to remain competitive despite that one extra platter per drive.

Irving Tan: So maybe I'll just make one big comment and then I'll leave it to Ahmed. You saw his presentation, he had two very important points. One is we're going to continue to focus on increasing areal density. Right? So, if you look at it, we're going to deliver a 40 terabyte ePMR, as example, that's only 11 platters; that's close to 4 terabytes a platter. When we get to 60, we'll introduce another platter. So that's 5 terabytes per platter. So we're increasing areal density. Right? So then on HAMR, we said we would get up to 10. By 2029?

Ahmed Shihab: 28.

Irving Tan: 28, sorry. He's even ahead of me.

Ahmed Shihab: He's sandbagging. [crowd laughing]

Irving Tan: So, if you talk about what the rest of the industry has been saying, they're saying we're going to get up to 10 terabytes per platter. So we're equal or potentially, timeline-wise, going to be ahead of them in areal density. Now, what we are doing is to increase the capacity of the drives beyond areal density. So we're going to be at parity or even ahead on areal density per platter, but we have that ability because of the innovative work that the teams have been doing, the laser technology, to — within the same drive — to increase the number of platters. Alright? So that's how you get to a potential 140. So we feel actually, from a drive economics standpoint, actually, our dollar-per-terabyte is going to be even more competitive going forward.

Erik Woodring: Okay. And maybe just a quick followup, going back whatever it is, just 12 months ago to the last Analyst Day, I think we were setting a floor for op margins and gross margins at 24% and 38%; I know we're kind of dreaming the dream now, which is exactly what we were all asking for, but if we do think about the other side of that, where do we think about the potential floor and margins, is it any different than a year ago or has that changed as well? Thank you so much guys.

Kris Sennesael: No — so the financial model that I put out there, as I said, it's a target model, so we still have some time to go and some work to do to get to the targets, but I have confidence that once we hit those targets over the next three to five years, we will be able to continue to operate the business at or above those values.

Ambrish Srivastava: We'll come to Asiya and then after that Wamsi.

Asiya Merchant: Thank you, Asiya Merchant, Citigroup, and thank you for all the content; that was great. Just one for Kris, and if I can, one for Irving as well. Kris, you know, when you talk about stable pricing, I know right now it's a great environment, just walk us through why stable pricing makes sense beyond maybe the next few quarters where you have great visibility; if there's a down cycle, why do you still think stable pricing could probably prevail?

And then one for Irving; Irving, on the earnings call you also talked about quantum computing. I didn't get to hear anything about it, maybe it's just the timeframe here that we're talking about. Just walk us through that innovation that you've talked about and how does that fit into the broader roadmap? Thank you.

Kris Sennesael: So, as it relates to pricing, for me, pricing is fully tied to how much value do we deliver to our customers, right? It has nothing to do with tightness in the supply chain or strength in the cycle or weakness in the cycle. It's "how much value do we provide to our customers," and moving to higher-capacity drives with better areal density, with better performance, is what our customers want, it's what our customer needs, and delivers a tremendous amount of value. That's why we are going to remain disciplined in terms of pricing, no matter where we are in the cycle. And that's why I have high confidence in this stable pricing environment.

Irving Tan: Yeah. Maybe I'll just add onto that. I've been in regular communication with our customers, with one of the big ones, just two weeks ago — I mean, what they really want from us is predictability in pricing. It's very hard for them to be designing their datacenter architectures two, three years, five years out when you have the volatility that we're seeing in some of the storage tiers. So what we're really focusing is on continuing to deliver value to them, and as Kris said, to be able to share that value, so that we can deliver that stable pricing. Obviously in the near term we're seeing mid-to-high single digits, but in the long term model, a stable pricing environment.

In relation to your second question on Quantum and — we didn't want to distract from all the exciting things. We had to stay on the the drive itself, and obviously as I mentioned, we look to have regular Innovation Days to keep you posted on what we're doing. But the reason I mentioned it — because we're not building the business just for today. We are also incubating new growth vectors for the company for tomorrow, and that's why I took a moment to highlight the rich core capabilities and IP that we have. If you look up what the next, probably, tech growth driver beyond AI; quantum represents a huge opportunity going forward. And our magnetics capability, our magnetics junction technology capability, our nano-fabrication technology, by which we build our drives, positions us very well to deliver cost-economical qubits to support quantum computing going forward. And that's kind of why we made the strategic investment into Qolabs — not because it's a financial investment, but we're also a key technology partner to them, to be able to bring quantum computing economically at scale, just like we have done for the hard drive industry.

Ambrish Srivastava: Great. And while you get ready for a question, I want to widen our horizon and see who's in the back as I've been sticking with the front-benchers but we'll go with Wamsi and—

Wamsi Mohan: Thank you, Wamsi Mohan, Bank of America, I appreciate you guys doing this, and Kris, love your comment on 'no ceiling to numbers,' that's definitely encouraging here. I guess the two questions I have are one, you noted smooth transition across recording technologies and looks like relative to last year your EPMR road map is significantly different. I think last year you said ePMR might end at 36, now we're saying 60 plus, so very different. How do you think that impacts the adoption of HAMR at your customers just given the fact that so far you've seen tremendous success with EPMR, and that might be an easier transition at higher capacities. So do you think it impacts the transition to HAMR from a WD perspective?

So that's my first question, and second question is, there was a lot of innovation you shared here in terms of performance, improving performance, in terms of power, in terms of IOPS. Just curious how you think about this could expand the TAM for Western Digital, and does that — when this comes around does it accelerate your growth rate even further? Thank you.

Ahmed Shihab: So the — when we talk to our customers, one of the things they're really very clear about is they really don't like those step up transitions, and they want to have that smoother ramp in terms of equivalent capacity so they can choose when to ramp the capacity points for themselves. And that's really the genesis of why we pushed the ePMR technology further. We don't think it's going to decelerate HAMR adoption because customers understand, to get to the beyond-60-terabytes, to the 80 to the 100s, they really need to adopt HAMR. But they want to be sure of the quality and the reliability of this new technology, new recording technology that hasn't been in the data centers for two, three, five years, so they get comfortable with it.

So they appreciate us creating that road map for them. And since it's manufactured on the same lines, we're not — we've created — it's fungible capacity from that perspective. So we feel that it's the right approach for the customers; that's certainly the feedback we've heard from all the customers is, they appreciate the thoughtful approach that we've taken to the transition. They will transition in their own time. There's a deadline, but there is a transition.

Irving Tan: I guess in terms of the performance features, Wamsi, that you're referring to, obviously we anticipate the take-up rate within the existing fleet of drives that we have shipping to customers, on the high bandwidth drives — Ahmed, would I say, 20, 15%?

Ahmed Shihab: About 20%.

Irving Tan: Okay, 20% of customers would want that in their fleets, right? And then obviously the energy efficient drives, that actually opens up a new TAM for us because that actually is an unfilled need between the hard drives and the archival storage tiers. Obviously all these new capabilities will be reflected in pricing that's above and beyond what we deliver for pure capacity today.

Ambrish Srivastava: Great. We'll go with Steve Fox over there? And then [points].

Steven Fox: Hi, thanks for all the great information; really an eye opener for someone who's followed this industry for many years. Um, one question; it seems like maybe it's an older question, but thinking about your areal density curve, it looks like it's going to be a lot faster over the next three years than you're talking about for bit growth, and you just mentioned new TAMs, etc. So, can you sort of talk — and I recognize you're not going to be 100% at 10 terabytes per platter in three years, but can you sort of talk about how you manage that sort of additional supply through this areal density and where else it could go?

Ahmed Shihab: So increasing the areal density, the acceleration of the areal density that we're seeing, it's really the focus of our engineers on the media recipes, how we design the media recipes and how we increase the — change the head design. So we're taking further advantage of technology we've had in our drives for some time; we're just being a lot more bullish about what they can do and we that's how we get the higher densities that we're looking for right now.

Steven Fox: But I guess I'm wondering, it compares to like a 25% bit growth CAGR and you're increasing areal density by two and a half [times] over like three years, so how does how do we equate those two numbers together?

Kris Sennesael: So, we will continue to innovate as fast as we can, and Ahmed has lined out the timing of that. Of course, on top of that, you have to lay an adoption curve at the customers, and the combination of all of that, for us, we believe we will be able to supply in line with the nearline growth of mid20s that we expect over the next three to five years.

Ambrish Srivastava: Great. We're going to go to Tom O'Malley?

Tom O'Malley: Tom O'Malley, Barclays. Thank you guys for doing this; appreciate it. Not not much to pick at here, just two questions on the technology side. You spent a little time talking about the bottleneck of SATA for flash. Can you talk about industry improvements in memory bandwidth and if you see that getting better over the next couple of years, and if that may help flash providers? And then second, you talked about a common API for flash and hard disk drives. A big gating factor for more flash use in the past has been the difficulty with moving the software over. As you guys integrate that, is that going to hurt you in customers being more readily able to move back and forth between flash and HDDs? Thank you.

Ahmed Shihab: Improvements in — so improvements in memory interfaces is just going to accelerate the pace with which data moves around. So that's just going to require more and more data to be transferred in and out of storage. So that's why we feel our bandwidth drives help us really meet some of that demand. So we see that trend is going in parallel with each other, and I think that's an important thing for us to have delivered to our customers.

On your second question, which I kind of — will the API hurt us versus help us? We feel that in those customers that have already started on flash, we want to meet them where they are. So we don't want to make an abrupt transition for them; we want to make a smooth transition for them as well. So by offering the same API and making the transition on the same media, they get the same performance capabilities, and then when they're ready they can take advantage of the hard drive economics without disrupting their business. And I think that's an important transition.

I don't think it'll hurt us going the other way, because starting with hard drives, you're going to like the economics, you're going to like the performance. There will be a small amount of workloads that may benefit from flash, but being customer-centric, it's the right thing to do for the customer.

Irving Tan: Yeah, if I may add, I think it's ultimately down to the workloads and specifically what we're looking at in the platforms with those open APIs is to really focus on the neoclouds where they're starting from a flash-first perspective to really open up the HDD TAM that we don't really actively participate today. As they start to grow and amount of their storage requirements increase, the economics will require them to move into that direction.

Ambrish Srivastava: We'll go, right next to Tom, right there. [points] Thank you.

Ananda Baruah: Hey, yeah, thanks guys. Ananda Baruah, Loop Capital. With the roadmap for areal density that you provided, which is super impressive — is there a useful way to think about mitigation of the supply-demand gap that's in place today? Is there a time frame that you think supply-demand can start to normalize? It sounds like regardless you guys have your paradigm on economics and value-add, that you have, so sounds like that won't change based on supply-demand equilibrium, but any context there given that your areal density roadmap seems like it's going to move pretty quickly over the next couple years? Thanks.

Irving Tan: Yeah, I mean — as we know that the supply environment is very strong, and the demand side of the house is trying to catch up. Obviously from a roadmap standpoint and from a production standpoint there's limited opportunity in what we can do for calendar year 26, but as we get — as you see the road map, as we're able to ramp up, as customers — again, as Kris mentioned, depending on the adoption cycle as we move to the latter part of '27, '28, we anticipate that gap to narrow. But again, you know, something that we've seen is that the demand for storage continues to grow at a rapid rate, so — even the mid-20s, who knows what it's going to be going forward.

Ambrish Srivastava: Can we come to the front here please?

Yang Pu: This is Yang Pu for Karl Ackerman at BNP Paribas. Thank you for this great presentation. I have two questions, first to Ahmed about the high bandwidth drives. The idea of dual-actuator drives has existed for years, but never really took off; why is that? And why do you believe they can be successful today? And I have a follow-up.

Ahmed Shihab: Okay. I think as I said earlier, these ideas have been around for a while, but typically the way they were implemented required customers to change the interfaces, the software, the hardware, and they typically cost more money and more power. That's been the history of trying to introduce these technologies. What we've done in our designs is really paid attention to keeping the customer experience the same. So we took all the complexity away from the customer and kept it inside the drive. That's a testament to our engineering capabilities and the way that we're able to work through the drive in the small form factor we have, but keep the customer experience the same. That's what's different about these. I've seen many of these ideas, as a customer, come to me over the years, and typically it suffered from poor experience, poor power, or it's more expensive, and in this case we solved for those problems very quickly based on the history of technologies we've been incubating for quite some time.

Irving Tan: Yeah, I hope you see the big change in in our focus as a company. We talked about, a year ago, being really focused on our customer in everything. You've probably heard the word customer close to 100 times over the last two hours and everything we are doing starts with the customer at the center. Having Ahmed and more and more of our talent that comes from the hyperscale environment really gives us good insight into what we need to be doing from our customers. It's not a technology-first view. It's a customer-first view that technology enables the outcome that they want.

Ambrish Srivastava: You go to —

Yang Pu: Sorry, I have a followup. It's just a overarching question, just a long-term look at where we are in the cycle right now. Demand is through the roof, and supply is constrained; the industry is very consolidated. I feel like it's hard to apply any of our previous experience of the historical cycles onto this one. How do you think this cycle would unwind? What would make you — anything make you worry about, like, in three to five years, anything would change? Or do you all sleep very well in night? I know no one has a crystal ball but any of your longtime perspective would be very helpful.

Irving Tan: Well, we let you guys predict the cycle, right? We don't do that; you guys are experts at it. I think our focus is on staying close to our customers. The fact that three of our top five customers have entered into long-term agreements with us that extend one and two, all the way up to calendar '28, through to '27. As Kris mentioned, we're having active discussions with the rest for '28, '29, and some of them for even '30. That visibility gives us the confidence of where things need to go and the fact that you know we're not driving this business with high CapEx unit capacity focus, we can toggle technology if we need to to meet exabyte supply and demand balance.

Ambrish Srivastava: [points]

Mehdi Hosseini: Thank you. Mehdi Hosseini, Susquehanna. Two follow-ups; one for Ahmed. Should I assume that most of the drives installed today, and over the next couple of years, are going to be on a SAS bus interconnect infrastructure?

Ahmed Shihab: No, most of the drives that exist today are on SATA interfaces. So all the hyperscalers use SATA interfaces. They're sufficient for their capabilities, and they have done for the last 10 years.

Mehdi Hosseini: Sure. Is that going to be sufficient, especially as for inferencing, and assuming that inferencing; some is done in the cloud and some on the edge. How is how would that change the SAS or SATA requirement?

Ahmed Shihab: We don't see the — customers have been really good at building the software layer, the object store layers and the file system layers such that they can aggregate the performance for many thousands of drives into serving those workloads. But as those workloads get hotter, they're looking for that more performance from us so that they can serve even more capacity and more performance to their end users. So the interfaces and the design of the boxes will evolve to meet the performance needs that we have in the future.

Mehdi Hosseini: Sure. Okay. And just one quick free cash flow question. Should I assume that the capital intensity will remain in the same range?

Kris Sennesael: Yeah, absolutely. So the CapEx intensity is four to six percent to revenue, and all the innovation that — Ahmed has talked about it, right? Especially because it's even recording technology agnostic, right? Will not require a step-up, will NOT require a step-up in CapEx.

Mehdi Hosseini: Thank you. Oh by the way I guess if we were all trying to figure out the downside is we have to figure out when is the next flood hitting Malaysia. God forbid. [chuckles]

Ambrish Srivastava: So, you used up four or five questions for the next several earnings calls. [group laughing] As did Amit! But we're going to go over there to Matt.

Matthew Scheffler: Hi, Matthew Scheffler, Investment Strategies Fund. You know, the amount of innovation sort of belies this question, but how do we know we're spending enough on R&D?

Ahmed Shihab: [chuckling] I think the results show that we are being very frugal about how we get ideas to market. We test the ideas the way that makes sense to us. We incubate them. We test them and only develop the ideas that are really resonating for our customers' experience; take them forward. So there's a lot more ideas than what we are looking at behind the scenes, it's just we do it in a very responsible and very frugal way.

Irving Tan: Yeah. Maybe I'll just add on to that, and Kris wants to as well. Look, we have definitely not stifled R&D at all. And even a year ago at the investor day, we said very clearly: we would return 100% of excess free cash flow to our shareholders. That's after the investments that we make into R&D. So again, we we're building a business not only for delivering our core drive business for today, we're also making investments into incubations for the future. These new growth vectors are something we are and will continue to make investments in, going forward — both R&D investments, and also financial investments into whether it's startups or M&A that we think is necessary, because our innovation framework has three pillars to it. We build internally, we partner, right? We co-innovate with our partners. And we also have a buy model of it. So that will not change going forward. Kris?

Kris Sennesael: Yeah, and so again, we're not starving the company. We are focused on accelerating the pace of innovation. I will allow him to spend more R&D dollars provided he does it in the most effective, most efficient way, and there is a strong return on investment. I'll stop it there. [group laughs]

Ambrish Srivastava: We have time for one more question; we're going to go to CJ over there. [points]

CJ Muse: Thank you. CJ Muse with Cantor Fitzgerald. Two questions: the first one I want to push you a little bit on gross margins. You're just a couple quarters away, I think, from 50% if you keep pricing stable and you maintain that 10% cost down. So, curious: is there something that's occurring going forward in the transitions that's reducing either your cost down, or yields not going to impact things as well? We'd love to learn a little bit more on that. And then second question would be probably a question you haven't received in, ever, which would be cannibalization going the other way. With NAND pricing moving the way it is, are you talking with customers and starting to see demand perhaps pick up that had traded away over to SSDs? Thanks so much.

Kris Sennesael: Yeah. So I'll take the gross margin question. So you think about it the right way. We are making good progress at improving gross margins. We are getting closer to the 50 and 50-plus gross margins. Obviously, we have a technology transition in front of us, but we've always stated, and I'll be happy to repeat it today, that if and when we transition to HAMR, this will be neutral to accretive to the gross margins.

Irving Tan: Yeah. And CJ to your question, look — I think what you see from the innovation that we shared today, from a capability standpoint, from a performance standpoint, we are reinventing the hard drive to make it much more competitive, much more suited for the AI workloads for today. At a minimum it's definitely going to preserve that 80% of bytes that's stored in hard drives. Do we think there's opportunity for us to expand on that given pricing? Again, it's a highly volatile environment and we'll see. But at a minimum I think it really gives us that confidence that we will continue to maintain that 80% share with some upside opportunity to grow it over time.

Ambrish Srivastava: Great. Thank you. So we come to the conclusion of our session.

For a policy designed to decide concretely who gets access to the world’s most powerful AI chips, Washington has produced a hell of a lot of uncertainty.

The Biden administration’s Framework for Artificial Intelligence Diffusion was published in January 2025 and was meant to come into force on May 15 that year. But just before that deadline, the Trump administration said it would rescind the rule, ordered officials not to enforce it, promised a replacement, then spent months gesturing at a new framework without actually delivering one. In March this year, yet another planned replacement rule was pulled back.

Chris McGuire, senior fellow for China and emerging technologies at the Council on Foreign Relations — and a former deputy senior director for technology and national security at the US National Security Council between 2022 and 2024 — put it succinctly in an interview with Tom’s Hardware Premium: “The administration has a contradictory policy on this.” So what’s going on?

AI diffusion rules sit at the heart of the 21st-century power struggle over who gets access to advanced computing, who gets to build frontier AI systems, and how much leverage the U.S. can exert over allies, partners, and rivals. The existence of the rules is meant to improve national security by stopping advanced chips and model capabilities from flowing to adversaries while keeping the U.S. and its closest partners ahead. But in practice, businesses, foreign governments, and analysts have had to develop a sense of strategic improvisation.

Kevin J Wolf, a veteran export controls lawyer at Akin Gump, who previously served as assistant secretary of commerce for export administration in the U.S. government, told Tom’s Hardware Premium that “the Trump administration is just simply not enforcing, as a practical matter, the AI diffusion rule.”

But Wolf drew a distinction between practical and legal enforcement. Export controls usually derive a lot of their force from what is written into the Federal Register, as well as the predictability of the process surrounding those rules.

Companies make billion-dollar investment decisions because they believe Washington, however slow or frustratingly it moves, is coherent. Wolf believes this coherence has broken down. That’s down to the departure of subject matter experts from the White House with the change of administration. “The AI experts, the chip experts, and the tool experts, they were all fired or quit early last year.”

Uncertainty in continuity

Yet there is some element of continuity … sort of. In the absence of a decision by the Trump administration, the Biden-era diffusion framework still exists. But practically, Wolf said, the administration is behaving as though it doesn’t. That leaves exporters, cloud providers, and governments in the position of trying to infer American industrial strategy from Trump’s Truth Social posts and snatched pronouncements from the White House.

“I have no idea what their objective is,” Wolf said. Worse, he added, “there is no 'there' there.” Implying that Trump is not really saying anything of substance on the matter at all.

In theory, the idea underpinning the U.S. AI diffusion policy is simple. “The principal goal was, we want to make sure that as much AI compute around the world as possible is in data centers that we trust,” said McGuire. Chips are the physical bottleneck for building frontier systems and military capabilities — which gives them political leverage.

But if that’s still the goal, the current US policy is doing a strange job of achieving it. Washington seems to want the benefits of control without the administrative state required to exercise it.

Alexander Capri, senior lecturer in the business school at the National University of Singapore believes the U.S. is aiming for containment as well as platform capture. The logic, he said, is that restricting sales too tightly risks “kneecapping American companies” just as Chinese firms are catching up.

That means that rather than trying to deny everyone access, the US is trying to make itself indispensable. “It’s now about building dependence and reliance on America, on the American tech stack,” Capri said in an interview with Tom’s Hardware Premium. The result is more overseas partnerships, more Gulf investment, and more American cloud and chip infrastructure abroad, with the corollary that more countries are tied into a U.S.-led AI ecosystem by commercial necessity.

At the moment, that’s true. American AI chip suppliers retain enormous leverage. “The alternative to US AI chips is not Chinese AI chips,” said McGuire. “It’s no AI chips.” Nvidia, for instance, has an 81% market share by revenue for chips destined for data centers, according to IDC. That power means the US can shape the market, decide which partners get access, and compel companies and countries to build their AI stacks inside an American-designed architecture.

Chaos and confusion

The problem is that leverage only works if it is used coherently. Right now, there’s confusion over what the U.S. is aiming for. Wolf said existing flows appear broadly normal, and for companies already shipping or already operating data centers, business is largely continuing. “The uncertainty is making plans in the future,” said Wolf. “Do we build this data in country X?” he explained. Companies might decide to do so, then find in a month, a week or a year that it’s suddenly embargoed under a Trump administration decision. “No one knows,” he said.

Because of that, some businesses are holding back investment altogether, reluctant to pour billions into overseas capacity that might be trapped by a future rule. But others are doing the opposite, racing ahead to try to make money before Washington changes its mind again. In Southeast Asia, this has produced a mixture of hesitation and acceleration, while also allowing the area to gain more than $55 billion of investment in 2025.

But countries that thought they might become neutral hosts for AI infrastructure have found themselves caught in a geopolitical storm they can’t control. Malaysia and Thailand are attractive because they welcome investment while sitting outside the U.S.’s China embargo. However, it becomes trickier because they can be attractive for the same reason to bad actors looking to route chips somewhere less visible.

McGuire pointed to recent smuggling cases — including the one involving former Super Micro executives (the company itself denies any wrongdoing, and is cooperating with the investigation) — as evidence that is more than a theoretical risk. “This third country diversion problem is real and it’s big,” he said. “The industry is not policing itself right now.”

A status quo… but for how long?

For now, Washington can still rely on the brute fact that the rest of the world still needs American chips. But that window won’t stay open indefinitely, and several of the people watching this closest think the sheer strategic importance of AI will eventually force the White House to stop improvising.

“I think they’re going to have to, because the tech is going to force their hand,” McGuire said. The idea that advanced AI chips can “flow to most countries in the world without the US government having any visibility or insight,” he argued, will soon “seem preposterous.”

Until then, though, the vacuum is itself becoming policy. Wolf said what’s most striking is the absence of the normal Washington machinery around rulemaking. “There are no speeches, there’s no government outreach, there’s no conferences,” he said.

That means there’s no settled doctrine to decode, or no obvious coalition pushing one approach over another, which means there’s no real confidence that anyone inside the administration has fully decided what comes next. For allies, investors, and countries trying to build AI capacity without becoming collateral damage, that’s the real lesson of Trump’s chip policy: It appears no one's steering the most important supply chain in tech.

Last week, the United States Federal Communications Commission (FCC) took the drastic step of banning the future import of consumer-grade Wi-Fi routers manufactured overseas. The announcement rang alarm bells, as nearly all consumer routers available are produced outside the U.S., leaving a potentially vast vacuum for anyone who needs to replace their router in the coming months. We reached out to TP-Link, Asus, Netgear, and Linksys for comment to get the deeper story on the ins-and-outs of the new measures.

What’s the purpose of the FCC’s actions?

So, why is the FCC taking this step? There's no secret that President Donald Trump and his administration have made national security a top priority, and the president's 2025 National Security Strategy determined, “the United States must never be dependent on any outside power for core components—from raw materials to parts to finished products—necessary to the nation’s defense or economy. We must re-secure our own independent and reliable access to the goods we need to defend ourselves and preserve our way of life.”

Now, it's debatable whether a Netgear Orbi 970 mesh router sitting on your bookshelf at home poses a direct threat to national security or the economy at large, but it's clearly on this administration's mind. In last week's announcement, the FCC added that foreign-made routers “pose unacceptable risks to the national security of the United States or the safety and security of United States persons.”

“I welcome this Executive Branch national security determination, and I am pleased that the FCC has now added foreign-produced routers, which were found to pose an unacceptable national security risk, to the FCC’s Covered List,” added FCC Chairman Brendan Carr. “Following President Trump’s leadership, the FCC will continue to do our part in making sure that U.S. cyberspace, critical infrastructure, and supply chains are safe and secure.”

What are the immediate effects on consumer routers?

There are a few things to consider with this new directive, however. For starters, it doesn't affect routers that have already been imported into the U.S. and are currently available for sale (or those that have been sold and are currently in the hands of end-users). So, at least for the near-term, your average John or Jane Doe shouldn't notice any changes in availability when shopping for a wireless router from your favorite brick-and-mortar or online retailer.

However, things could change once the existing stock of routers depletes at various retailers, and even then, only if manufacturers haven’t secured a spot on the Conditional Approval list. If manufacturers aren’t able to secure Conditional Approval and consumer routers are banned from sale, we could see a shortage, which in turn would lead to price increases affecting all consumers. We've already seen what the AI craze has done to the supply of memory, which, in turn, has ushered in significant price hikes over the past year. There’s the potential for this type of scenario to play out in the router market if the U.S. becomes overly stringent with approvals.

These actions would also likely affect ISPs, which provide routers to customers when they sign up for new service. All in all, it’s a tricky situation for all involved.

What do Router manufacturers think of this move?

We reached out to several popular router manufacturers, including TP-Link, Asus, Netgear, and Linksys. Netgear and TP-Link provided statements to Tom’s Hardware on their respective positions. Asus posted a statement on its U.S. website. Not surprisingly, TP-Link, which has already been on shaky ground with the U.S. government in recent years for its ties to China, seemed almost upbeat about the announcement.

"This action from the FCC appears to affect virtually all new consumer-grade routers seeking authorization to be sold in the United States," wrote TP-Link in a statement to Tom's Hardware. "Because nearly every manufacturer in this sector produces hardware abroad or relies on a global supply chain, this new requirement will set a bar for the entire industry. Placing all manufacturers and their supply chains under the same scrutiny is a positive step in the direction of making the router industry more secure."

TP-Link has been singled out in the past by both the Biden and Trump administrations, and it has even established its headquarters in Irvine, California, where it employs several hundred people. However, with this new action from the FCC, TP-Link likely feels that it is no longer solely under the microscope, and all of its competitors will have to play by the same rules to curry favor with the U.S. government.

For its part, TP-Link adds that the majority of the routers sold in the U.S. are not produced in China, but instead in Vietnam. That still doesn't help TP-Link remove the U.S. government’s crosshairs, but the company adds that it "has already been planning to establish U.S.-based manufacturing to complement our existing company-owned facilities in Vietnam. TP-Link is well-positioned — in fact, possibly better positioned than any of its competitors — to succeed under the new guidelines and maintain its position as the leading U.S. vendor of secure network devices."

Netgear also issued a brief, optimistic statement: “We commend the Administration and the FCC for their action toward a safer digital future for Americans. Home routers and mesh systems are critical to national security and consumer protection, and today’s decision is a step forward. As a U.S.-founded and headquartered company with a legacy of American innovation, Netgear has long invested in security‑first design, transparent practices, and adherence to government regulations, and we will continue to do so.”

In addition, Asus struck an upbeat tone, writing, “Asus has proudly served U.S. customers since 1991, with a long-standing commitment to trusted innovation and strong product security. We are confident in the integrity of our supply chain and the security of our networking products. This FCC action has no impact on existing Asus router users, software updates, and customer support.”

FCC action may lead to security headaches for router users

I mentioned earlier that the ban doesn't affect routers already imported into the U.S. and that no masked individuals will show up at your door to take away your routers. However, the FCC has added another poison pill to the situation.

The FCC's Office of Engineering and Technology notes, “All routers authorized for use in the United States may continue to receive software and firmware updates that mitigate harm to U.S. consumers at least until March 1, 2027. These include all software and firmware updates to ensure the continued functionality of the devices, such as those that patch vulnerabilities and facilitate compatibility with different operating systems.”

In other words, if you currently own a router manufactured outside the United States and the company hasn't been added to the FCC "Conditional Approval" list, it would no longer be eligible for firmware updates within a year. It doesn't take a rocket scientist to realize that discontinuing firmware updates would render a huge swath of routers unprotected, leaving them even more vulnerable to DDoS attacks and other serious security vulnerabilities. The very thing that the FCC wants to prevent could become even more problematic with the March 1, 2027, deadline.

What can router manufacturers do?

The administration is offering somewhat of a lifeline to router manufacturers in the form of a Conditional Approval from the FCC. Companies can submit an application, which will be subject to review by the Department of Defense or the Department of Homeland Security.

Companies are asked to submit a wealth of information, including corporate structure, beneficial owners, foreign government interests, the country of origin for all components used in a router's design, and the location of final assembly (among other requirements).

However, one of the biggest and most costly requirements is for companies to provide an "onshoring plan" to "establish or expand" manufacturing capacity in the U.S. for their routers. Companies must also provide "a description of existing U.S.-based manufacturing and assembly for the router including: percentage of components assembled in the United States and current U.S. headcount and facilities (locations, functions, etc.).”

If granted, Conditional Approvals are in place for a team of up to 18 months.

What does this mean for consumers going forward?

In the short term, we don’t expect that the router market will be affected too harshly if you’re looking to purchase from one of the major players (which have significant resources) in this arena. Given the statements from Asus, Netgear, and TP-Link, they all seem pretty confident that it is a welcome development and that they should continue to provide hardware to customers, likely through Conditional Approvals from the U.S. government. This would likely also extend to other big names like Linksys. All of these companies should also be able to grease the wheels to avoid a ban on software updates for their routers.

Where things could get more problematic is for smaller, foreign-based companies that offer budget networking devices and have little to no existing corporate or manufacturing operations in the U.S. We’re talking companies like Cudy, Reyee, and OKN (among others). It remains to be seen how these companies will be able to appease the FCC not only to secure permission to sell within the U.S., but also to provide firmware updates beyond March 1, 2027.

Noctua is known for building some of the world’s quietest and most reliable cooling fans. The brand is a partnership between the Austrian RASCOM and Taiwanese Kolink; RASCOM handles marketing, sales, and product management, whereas Kolink handles manufacturing, and together they handle product development. We delved into the interesting history of the brand late last year.

You most likely know Noctua for their signature brown and beige fans, but not everyone digs these colors – many of us prefer our fans in plain black, and although Noctua is happy to make these nowadays, their development isn’t something that happens overnight.

To manage expectations, Noctua keeps a published roadmap with the brand’s upcoming products, which is updated a few times per year. The most recent is from January 2026, and it details the products we can expect in Q1, Q2, and Q3 of this year.

Reliable Fans, Unreliable Roadmap

Now, before we dig into the details of Noctua’s roadmap, a disclaimer: The company is notoriously unreliable when it comes to sticking to its published roadmap. This is not without reason, however.

You see, there’s something you should know about Noctua: The brand prides itself on building quality products. Inevitably, this comes with unforeseen issues, and Noctua consequently finds itself delaying the launch of products to meet its own quality standards. There's more to it than just that, of course. Noctua didn't publish a roadmap until a few years ago, after facing much criticism from the public.

Q2 2026: Noctua is getting into water cooling

Noctua just released the Flux Pro Noctua Edition in partnership with Antec in March, which we’ve already built a system into. The Flux Pro case is made by Antec, and the Noctua Edition is the first case ever built to feature Noctua branding and a host of Noctua fans. But it's in Q2 where things start to get even more interesting.

Just like the brand was firmly against producing black fans for a long time, Noctua has also been firmly against liquid cooling. The reason is simple: pump noise.

Noctua has nothing against the power of liquid cooling. But when you pair the excellent NF-A12x25 G2 with a liquid cooler, under load the pump speed has to ramp up significantly, meaning its noise will stand out above the rest of the system. This is not an issue for PCs with cheaper fans (or not one most people care much about, anyway), but certainly an issue in a system designed for silence. But the market wants what the market wants. Noctua has been all about partnerships lately, and for building its very own liquid cooler, it teamed up with Asetek.

Asetek's history isn’t all too popular with the enthusiast community, but no one can deny that the company does have formidable experience making all-in-one liquid coolers. They’ll be pulling the EMMA (Gen 8) V2 platform out for optimal thermal and acoustic performance, and Noctua has made a handful of significant design choices that should make the pump significantly less obtrusive than other AIOs, among which is a tuned mass damper – similar to what the Taipei 101 skyscraper uses to keep the building upright in earthquakes, but much, much smaller.

Noctua has been talking about making its own liquid cooler for quite some time, and unlike many partnerships it has engaged in, the AIO will be a fully Noctua-branded product. With the Noctua brand always comes an industry-leading 6-year warranty. Reliability is often an issue with cheap AIOs, but with Noctua backing the product, I reckon we can be confident that Asetek’s new platform is due to stand the test of time.

The Noctua AIO will come in 240mm, 360mm, and 420mm sizes, all in the industry-standard 30mm radiator thickness. There's no specific price or release date quite yet, so keep your eyes peeled for any announcements.

Q2 2026: Finally, a Black NF-A12x25 G2

If you’ve been craving an NF-A12x25 G2, but don’t like the beige-and-brown colorway, your prayers will be answered: Noctua is unleashing the black variant of the NF-A12x25 G2 to the world in Q2 2026. Or at least, so says the roadmap.

The NF-A12x25 G2 is a fan that pushes the limits of what is physically possible in the 120mm x 120mm x 25mm form factor, and it does so by using Sterrox Liquid Crystal Polymer (LCP) for the impeller. This gives it extra tensile strength so that the blades don’t bow outwards at high duty, which is critical because the impeller is spaced at just 0.5mm from the frame.

But, the reason why it’s taken a while to come to market is that changing the color pigment in LCP has some funny ways of interacting with the molding process; you’d think, simply change the pigment, inject the substance into the same mold. Bob’s your uncle. But the reality isn’t that simple. With most fans, this wouldn’t be an issue, but due to the 0.5mm spacing, there is zero room for error.

Q2 2026: Pulsar Feinmann Noctua Edition

As a wrap for Q2, Noctua is teaming up with Pulsar for a Feinmann Noctua Edition gaming mouse. The Feinmann is a rather unique mouse — it’s built with a magnesium alloy shell that’s filled with holes to deal with sweaty hands. If you’re someone who suffers from Trypophobia, this mouse isn’t for you. But Noctua saw it and thought, “Hey, we can put a fan in there,” and so they did.

Due to the magnesium alloy shell, the Pulsar Feinmann is ultra light, weighing in at just 46 grams. The Noctua edition is probably a few grams heavier – the fan that’s due to be mounted inside weighs just under 9 grams without a cable. Even with that, less than 60 grams would still be extremely light. For context, anything under 100 grams is considered light. For comparison's sake, the Logitech MX Master 4 weighs in at 150 grams.

The sensor inside the mouse is the PixArt PAW3950, which offers a 39k DPI resolution, can cope with up to 50G acceleration, and tracks at up to 75 inches per second. With polling at 8,000 Hz, the Pulsar Feinmann is already an incredibly attractive gaming mouse as is.

Add some Noctua colorway touches, and this will be one of the most unique pointing devices to exist. Considering the original, non-Noctua edition costs $180, and adding some Noctua tax, it wouldn’t be surprising if this mouse costs north of $250.

As with other Noctua collaboration products, expect limited production of the mouse. The chances are that over time, this will gain collector value among diehard Noctua enthusiasts.

Q3 2026: A desk fans & co-branded PSUs

With all the releases slated for Q2, Q3 is set to be a little less exciting. We can expect a 140mm desk fan, a USB fan controller to pair it with, and last but not least, a Seasonic Prime PX Noctua Edition power supply.

The advent of the Seasonic Prime PX Noctua Edition is particularly interesting, as it brings a Noctua Edition power supply to a more mainstream power envelope.

Currently, Noctua is already selling a PSU in partnership with Seasonic – the Prime TX-1600 Noctua Edition, which, as its name implies, is a very beefy unit capable of delivering 1,600 watts nominal. That is a huge amount of power, and not everyone needs this.

The Prime PX HPD series will come in envelopes of 850 W, 1,000 W, and 1,200 W, which is much more appropriate for the masses.

To give some context to this statement, Even The Stout Owl, a fully handmade wooden PC with 100% Noctua G2 fans, which packs a Core Ultra 9 285K, 96 GB of DDR5 CUDIMM memory, 4 TB of SSD space, and a Noctua RTX 5080, only typically pulls around 500 watts under real-world loads. With synthetic loads, this figure gets pushed to 800-810 watts, meaning even that PC could make do with the smallest PSU of the lot.

But keep in mind that PSUs operate at peak efficiency around 50% load (generally speaking, this is a good rule of thumb to go by), which gives a good argument for slightly oversizing a PSU. Oversize too far, and you’ll end up with unnecessarily higher idle draw and never reach peak efficiency. For more on PSU bottlenecks and sweetspots, we've done our own testing last year with the RTX 5090.

The Prime PX series is also a short power supply, barely fitting a 120mm fan. This makes them fit in pretty much all but the smallest cases. Of course, the Noctua-Edition Prime PX’s will also come with an NF-A12x25 G2 fan installed, a brown shroud with Noctua’s signature intake-noise-reducing shape, and Noctua-themed cabling.

The Thermosiphon is still MIA, for now

One of Noctua's most anticipated products is the elusive thermosiphon cooler.

With Noctua’s take on pump noise, a thermosiphon cooler would be the perfect outcome, as it would need a pump. Instead of being filled with water, a thermosiphon cooler is filled with a phase-changing coolant, which boils when subjected to heat from the CPU, and condenses when cooled in the radiator.

Except unlike a heatpump or air-conditioner, this doesn’t happen under the mighty force of a compressor – rather, the coolant is one that’s engineered to evaporate and condense at temperatures typically seen in PCs, rising from the boil, and falling back down by gravity as a liquid – a passive, gravity-driven cycle. This is similar to the process that happens in heatpipes.

For something as complex as this, it’s no surprise we can’t find the thermosiphon cooler on the roadmap. It was first demoed at Computex in 2024, but has been in the works long before then, according to our own sources. The thermosiphon cooler is something Noctua is developing in partnership with Calyos, which has experience building computer cases that act as passive heatsinks, driven by phase-change cooling.

With the complexities of developing a product such as a phase-change cooler, Noctua has said that the thermosiphon cooler will not be listed on the roadmap until it is near completion, nor will it give a rough ETA.

The curious case of the disappearing NH-D12

Also demonstrated at Computex in 2024 was Noctua’s first full-size, dual-tower 120mm CPU cooler. Noctua has been around for 20 years, and in all that time, it has never built a dual-tower, dual-120mm-fan CPU cooler that uses standard square-frame fans.

Yes, the legendary NH-D15 and the new NH-D15 G2 are phenomenal coolers – but they’re huge, and with the round-frame fans, they look a bit incohesive, lacking clearly-defined boundaries. Of course, one of the reasons it may have disappeared off the roadmap is the limited situations in which a D12 may be needed – for space-restricted applications, Noctua already builds the D12L, a low-profile variant, and where there is enough space, the D15 will offer superior performance.

All that said, Noctua had stated that the prototype D12 offered D15-level performance in a 120mm form factor. However, being a smaller cooler, it’d have to cost less than the D15, and we don’t imagine Noctua is in the market to cannibalize its own product portfolio.

The NH-D12 was revealed in June 2024, and at the time, it had a release window of Q2 2025. It’s now a year later, and it’s nowhere to be seen on Noctua’s roadmap.

As Noctua's roadmap evolves, and we get a better understanding of what's on offer, be sure to check back on this page for updates. Who knows, we might even have the NH-D12 back on the roadmap.

Microsoft first announced DirectStorage for PC back in 2020, with Forspoken being the first game to officially support it in early 2023. However, it wasn’t until Ratchet & Clank: Rift Apart was released later that year that we saw the full DirectStorage suite in action. Ratchet & Clank: Rift Apart was the first title to ship with GDeflate compression and support for GPU decompression of assets – a task that had previously been the responsibility of the CPU.

In theory, this should have facilitated more seamless streaming of assets with smoother performance, as the feature aimed to reduce the CPU bottleneck associated with the decompression of assets during gameplay. In practice, the opposite happened, in particular on Nvidia GPUs.

What is DirectStorage?

DirectStorage on PC aims to bring many of the benefits of the fast storage technology used in the PS5 and Xbox Series X|S. Its purpose is to allow games to make full use of NVMe SSDs with minimal CPU overhead, allowing for reduced load times, faster asset streaming, and larger, more dense worlds in games. DirectStorage 1.1 also added support for GPU decompression, which would shift the burden of decompression of game assets from the CPU to the GPU. This amplifies the amount of data that can be transferred through the SSD -> RAM -> VRAM pipeline.

Unlike CPUs, GPUs have thousands of cores, and they are also very efficient at performing repeatable tasks in parallel. GDeflate is a data-parallel compression scheme that is specifically optimized for GPU decompression.

GDeflate has two levels of parallelism. First, the original data stream is split into 64 KB tiles, and each time is compressed separately. If the CPU does the decompression, then each tile can be decompressed by a different thread. If the GPU does the decompression, then each tile can be decompressed by a single thread group. Second, the data is arranged within a tile so that many lanes within a thread group can decompress that tile in parallel. GPU decompression not only saves CPU cycles, but also saves system interconnect bandwidth and on-disk footprint since the data remains compressed until it reaches VRAM.

One benefit of data moving at a faster rate through this pipeline is that, theoretically, you would need to hold less data in system memory at any point in time, which could be extremely helpful given the skyrocketing prices of DDR. This will be especially true if game developers start to lean even more into the high bandwidth of NVMe storage. Another benefit, which is especially evident in Ratchet & Clank, is that textures load in faster with DirectStorage enabled. As you can see above, with it disabled, you get blurry textures until the higher resolution textures load in.

What is the problem?

When Ratchet & Clank: Rift Apart launched, many users reported that disabling DirectStorage by removing the dstorage.dll files from the game folder (and therefore falling back to CPU decompression) resulted in better performance – particularly in terms of more stable frametime. The issue affected mainly Nvidia GPUs, including the 4090 and 3090.

In early 2025, Marvel’s Spider-Man 2 was released on PC with DirectStorage and GPU decompression support. Once again, there were reports of improved performance when disabling DirectStorage and falling back to CPU decompression on NVIDIA GPUs. When testing on a 4090, I saw increases of 18-25% in 1% lows in Spider-Man 2 when disabling DirectStorage, depending on resolution. These GPUs struggled to handle both rendering and decompression tasks simultaneously.

Do Blackwell GPUs suffer from this issue?

My initial tests were performed on a 5090, but I was pleasantly surprised to see that leaving DirectStorage enabled no longer tanked performance. However, the 5090 is an absolute beast, so this was not necessarily a sign that the Blackwell architecture is better suited to handle GPU decompression. For that, we need to test more Blackwell GPUs across the stack. Note that AMD Radeon GPUs never experienced this issue, so we will only be testing Nvidia cards in this article.

Test system

• AMD Ryzen 7 9800X3D
• 64GB (2x32GB) G.SKILL Flare X5 DDR5 @6200 MHz CL30
• Crucial T700 Gen5 SSD
• Asus ROG STRIX B850-F Gaming WiFi
• Corsair Nautilus 360 RS AIO Cooler

As you can see in both Spider-Man 2 and Ratchet & Clank, the RTX 5090 does not skip a beat with DirectStorage/GPU decompression enabled at any resolution. In fact, we now see some gains in average framerate and 1% low in some cases.

Below, we test the RTX 5070 in the same games at the same settings at 1080p and 1440p.

Similarly, the RTX 5070 sees some nice gains in 1% lows with DirectStorage enabled. At 1440p, the GPU load throughout the Spider-Man 2 benchmark is over 98%, so we are GPU-bound, and yet the 5070 has no issues rendering and decompressing assets simultaneously during gameplay.

Now for an even bigger test. Can the RTX 5060 maintain the same level of performance when it has to render and decompress assets on-the-fly?

Indeed, it can. At 1080p, the GPU load throughout the Spider-Man 2 benchmark run is over 98%, which means that even when GPU-bound, the RTX 5060 does not lose any performance when it is tasked with decompressing assets during gameplay.

By contrast, you can see below how the RTX 4060 handles GPU decompression.

The performance degradation can be quite significant in terms of the 1% lows, which is indicative of how smooth and stable the game feels when traversing the game world. In contrast with the RTX 5060, the 4060 struggles when it is tasked to decompress assets.

However, GPU decompression is working as intended on the 40-series from a texture streaming perspective. Textures load in on time, just as they do on the 50-series.

Possibly the most interesting result, however, is what we see on a 4060 laptop.

Laptop specs

• RTX 4060 Laptop
• Intel Core i7-13620H
• Gen4 SSD
• 16GB DDR5

As you can see, even on a system with a lower-end CPU, we still experience a drop in performance when shifting the decompression task from the CPU to the GPU on a previous-generation RTX card. This is true even at 720p when we are CPU-bound (the GPU load in Spider-Man 2 throughout the benchmark is 76%.)

From the tests, it is clear that Blackwell GPUs across the stack experience no performance degradation – from the 5090 all the way down to the 5060. Meanwhile, previous-generation GPUs still struggle with GPU decompression, at least the ones tested here.

Why do Blackwell GPUs handle GPU decompression better?

We only tested a limited selection of hardware and scenarios, but our results do show a few clear tendencies. It’s not entirely clear why the RTX 50-series handles GPU decompression better than their predecessors. The Blackwell data center GPUs have a dedicated decompression block, but there is nothing in the consumer Blackwell whitepaper that indicates the consumer GPUs have such a block.

One possible explanation is the addition of an improved scheduler in the Blackwell architecture. Despite its name – AI Management Processor (AMP) – the scheduler can be used to improve any asynchronous workloads running simultaneously with other graphics workloads, not just AI-related tasks. The AMP is implemented using a dedicated RISC-V processor, which isn’t anything new for NVIDIA GPUs, as RTX cards since Turing have featured RISC-V-based GPU System Processors. What does appear to be new is the fact that it was built specifically for Windows Hardware-Accelerated GPU Scheduling (HAGS), which allows the GPU to handle its own memory more efficiently without having to rely on the CPU.

According to the whitepaper, AMP matches the Microsoft architectural model that describes a configurable scheduling core on the GPU through HAGS. The AMP appears to be smarter and more efficient than previous generation schedulers, and the faster and more efficient scheduling of asynchronous workloads that it facilitates could be what we are seeing with GPU decompression on Blackwell GPUs.

AMD's position in the data center market has changed drastically in recent years: The company transformed from being an underdog, supplying less than 1% of server CPUs in 2017, to commanding nearly 29% of the server CPU market as of late 2025.

After increasing shipments of processors for data centers by several orders of magnitude in less than 10 years, AMD is changing the way it approaches the market in a bid to continue expansion. On the AI front, AMD is switching to an annual cadence of new product releases, and the company is doing the same for traditional data center CPUs.

Over the next 24 months, AMD is set to introduce the Zen 6-based EPYC Venice CPU with up to 256 cores in 2026, EPYC Verano processor in 2027, the Instinct MI400-series AI and HPC accelerators in 2026, which will power the Helios rack-scale solution for AI. It will also release the Instinct MI500-series AI and HPC GPUs in 2027, which will serve as the base for the company's next-generation rack-scale AI system.

Launching around half a dozen major product designs, including several specialized CPUs and two rack-scale solutions, is a big deal. So let's go over AMD's data center roadmap for 2026 and 2027.

2026 CPUs: Venice and Venice-X — featuring up to 256 Zen 6 cores

AMD's upcoming sixth-gen EPYC Venice processor will rely on the company's next-generation Zen 6 microarchitecture and will also be the firm's first data center design to be made on TSMC's N2 (2nm-class) process technology. The chip will scale up to 256 high-performance Zen 6 cores, a 33% increase over the current EPYC Turin processors that feature up to 192 Zen 5c (compact cores).

AMD's next-gen EPYC CPUs are expected to adopt the all-new SP7 form factor, which can accommodate more compute complex dies (CCDs) on the package, increase the number of memory channels, enhance I/O capabilities, and boost peak power delivery to feed extra cores.

In addition to the increased core count, another key improvement will be a major boost in memory bandwidth; EPYC Venice will provide up to 1.6 TB/s of per-socket memory throughput, more than doubling the 614 GB/s available on current EPYC CPUs. While AMD has not detailed the mechanism behind this increase, it is likely to involve support for advanced memory modules such as MR-DIMM or MCR-DIMM, which are becoming the default choice for CPUs with large core counts that are starved for sufficient memory bandwidth.

The processor will also significantly enhance connectivity with accelerators, since AMD plans to double CPU-to-GPU bandwidth, likely by adopting PCIe 6.0, which can deliver roughly 128 GB/s of bidirectional bandwidth per link before encoding overhead. With as many as 128 PCIe lanes, Venice should be capable of moving substantially larger volumes of data between CPUs and accelerators such as AMD's upcoming Instinct MI400-series GPUs, which will be particularly handy for AMD's rack-scale AI solutions.

AMD claims the EPYC Venice processor will deliver up to 70% higher performance compared with the existing EPYC 9005-series, although the company did not specify the workloads used for this comparison, so take the claim with a pinch of salt.

Although AMD has so far not released fifth-gen EPYC Turin processors with 3D V-Cache aimed at AI and HPC workloads that demand massive single-thread performance, the company clearly teased EPYC Venice-X with extra L3 cache as being a part of its sovereign AI and HPC platforms featuring the Instinct MI430X and MI440 accelerators.

Whether AMD plans to offer specialized versions of its EPYC Venice processors based on the Zen 6 microarchitecture for space and power-constrained deployments, such as edge and network solutions, remains to be seen. It's certainly a possibility given that there are no Zen 5-based offerings for these segments.

2027 CPUs: Verano — A brand-new design, or Zen 6 with BSPDN?

While we can only wonder about AMD's plans for specialized versions of sixth-gen EPYC processors, we do not know that AMD intends to release its EPYC Verano high-performance processors in 2027 to power its next-generation rack-scale AI system.

AMD does not officially name its codenamed Verano CPUs as the seventh-gen EPYC offering, so we have no idea whether these are based on the Zen 7 microarchitecture or Zen 6 (it may be a Zen 6+ version), featuring tangible enhancements. What those enhancements might be is anyone's guess, as AMD has not disclosed any official details.

The planned introduction of Verano processors in 2027 coincides with the ramp of TSMC's A16 fabrication process, which is expected to enter high-volume production in late 2026. A16 will be the foundry's first manufacturing node to incorporate backside power delivery, a feature designed to improve power distribution and efficiency, which will be particularly beneficial for large datacenter CPUs and AI accelerators.

AMD has not confirmed which process technology will underpin its 2027 server processors and GPUs. But given the timing of the roadmap and the advantages of backside power delivery for high-current compute silicon, it would not be surprising if AMD's 2027 data center products are built on A16. In the end, by re-architecting the power delivery of Zen 6 CPUs for servers, AMD would get a 'free' performance upgrade and gain valuable experience building processors with a backside power delivery network (BSPDN) — all without moving to an all-new microarchitecture, which would greatly simplify debugging.

2026 AI Accelerators: Instinct MI400 series — different subsets of CDNA 5

Starting with the Instinct MI400-series data center GPUs, AMD will offer three distinct products based on different subsets of the CDNA 5 architecture, each aimed at different types of workloads and deployments. By tailoring each accelerator to a specific workload, AMD can simplify execution units in AI GPUs, improve power efficiency, maximize performance, and even lower manufacturing costs, albeit by investing in an additional tapeout on TSMC's 2nm tapeout, which is costly.

The Instinct MI440X and MI455X models are designed primarily for low-precision AI computation, including such data formats as FP4, FP8, and BF16. AMD plans to use the MI440X as the foundation of its Enterprise AI platform, which uses AI servers based on one EPYC Venice CPUs (using the Zen 6 architecture) and eight Instinct MI440X accelerators. These machines are designed for on-premises AI deployments for training and inference, and feature power consumption and cooling requirements that are compatible with existing data center infrastructure.

The Instinct MI455X will be AMD's flagship AI offering that is meant to deliver the absolute maximum performance when installed into AMD's Helios rack-scale systems, which will be liquid-cooled. AMD once projected its Instinct MI455X to offer 2X performance (without disclosing the data format), increase memory capacity by 50%, and grow bandwidth by more than 100% compared to the Instinct MI355X. Meanwhile, the MI455X is set to hit 40 dense FP4 PFLOPS, which is slightly lower than Nvidia's Rubin GPU, which is expected to offer 50 dense FP4 PFLOPS.

By contrast, the Instinct MI430X targets sovereign AI and HPC environments and therefore supports both FP32 and FP64 precision, required for traditional technical computing and supercomputing workloads. AMD envisions that customers deploying MI430X accelerators will also use EPYC Venice-X processors that add extra cache and offer enhanced single-thread performance.

AMD plans to use Infinity Fabric for intra-package connectivity on its MI430X, MI440X, and MI455X accelerators, which is not surprising. For scale up connectivity, AMD expects to deploy UALink, the industry's first standard interconnection for AI accelerators. Broad deployment of UALink will depend on ecosystem support from companies such as Astera Labs, Auradine, Enfabrica, and Xconn, however. Based on recent rumors, AMD is looking at UALink-over-Ethernet connectivity.

2026 / 2027 rack scale platform: Helios — AMD's first rack-scale AI system

AMD's Instinct MI455X and UALink are two key ingredients of Helios, the company's first rack-scale AI system. This machine will use EPYC Venice CPUs, pack 72 Instinct MI455X accelerators (interconnected using UALink or UALink-over-Ethernet), offer 31 TB of HBM4 memory with 1400 TB/s of bandwidth, and drive 2900 FP4 dense PFLOPS. The unit will be behind Nvidia's VR200 NVL72 system in terms of compute performance, but as it will feature more HBM4 memory capacity, it may have an edge over its rival in memory-dependent workloads. In addition, Helios will use Pensando Vulcano network interface cards (NICs), which are expected to be one of the industry's first 800 GbE network cards that comply with the Ultra Ethernet specification.

Recent rumors indicated that AMD may delay widespread availability of its Instinct MI455X accelerators and Helios rack-scale systems from the second half of 2026 to Q2 2027 — reports AMD was quick to deny. But uncertainties surrounding the broad availability of UALink switches in calendar 2026 clearly impact the sentiment about AMD's Helios and rack-scale solutions relying on the industry-standard interconnection in general. Then again, considering that AMD has signed multi-billion-dollar deals with AI companies to supply them with its future AI systems, it is possible that the first batches of rack-scale MI455X UALoE72 systems will be exclusively available to companies like Meta and OpenAI, whereas other clients will get them sometime in 2027.

2027 AI Accelerators: Instinct MI500 series — CDNA 6 and 256-way MegaPod

Although all eyes are on AMD's Instinct MI400-series and Helios, right now the company has an even more impressive AI solution in the pipeline: Instinct MI500-series accelerators based on the CDNA 6 architecture. The next-generation AI rack is rumored to pack 64 EPYC Verano CPUs and 256 Instinct MI500-series GPU packages.

The system architecture — tentatively called Instinct MI500 UAL256 — spans three interconnected racks. The two outer racks each contain 32 compute trays that integrate one EPYC Verano processor and four Instinct MI500 accelerators. The central rack hosts 18 trays dedicated to UALink switches that link the cluster together. In total, the deployment includes 64 compute trays and 256 GPU modules. Given the power density of modern AI accelerators, the MI500 MegaPod will rely on liquid cooling for both compute trays and networking hardware.

Compared to Nvidia's Kyber VR300 NVL576 pod, which integrates 144 quad-chiplet GPUs, AMD's MI500 UAL256 configuration provides about 78% more GPU packages per system. However, it remains unclear whether the platform can match the expected performance of NVL576, which is projected to deliver 147 TB of HBM4 memory and roughly 14,400 FP4 PFLOPS of compute.

AMD is expected to introduce the system in late 2027, roughly when Nvidia’s VR300 NVL576 Kyber platforms are anticipated to arrive. If this timeline holds, both companies will likely ramp production of their respective MI500-series and Rubin Ultra-based rack-scale systems in 2028.

With an increasing amount of AMD's revenues stemming from data center workloads, the company must remain competitive beyond 2027 if it is to compete with future architectures, such as Nvidia's Feynman architecture. As the AI race continues, AMD's position in the near-term appears to be a solid foundation in ensuring its products are competitive.

Following Nvidia's GTC 2026 keynote, where CEO Jensen Huang laid out the company's Vera Rubin architecture and the Groq 3 LPU acquisition, Nvidia VP of Hyperscale and HPC Ian Buck sat down with press for a Q&A session in San Jose.

Buck addressed CPX's delay, the LPU-GPU decode architecture, the Vera CPU’s role in the AI data center, and took questions on the Intel NVLink Fusion partnership. This is a full transcript of a session attended by Tom's Hardware at GTC 2026, and as such, the transcript can occasionally be unclear; we have denoted any moments as such within the copy. Before diving into the transcript, it's worth refamiliarizing yourself with Jensen Huang's keynote from last week, which we've linked below.

CPX delay and LPU decode architecture

Ian Buck: As part of bringing the LPU to market this year with Vera Rubin... we've pulled CPX. It's still a good idea, but in order to dedicate our focus on... optimizing the decode with LPU this year. So we'll be thinking about CPX more in the next generation [and] we're going to execute on decode with LPU now, this year.

A couple other things I wanted to touch on. I also get a lot of questions about how we're doing this. How does the LPU work? How does it work with the GPU? Jensen went over it briefly. This might be more technical, but it's an important point.

The way we do the decode is with a Groq 3 LPU LPX rack. Here we have 256 LPU chips combined with a Vera Rubin NVL72. We're going to do the decode using Dynamo. We've combined the two teams, so Groq's software team has joined our Dynamo team.

We now do not only disaggregation of separate GPUs that you pre-fill and decode, but also the decode itself is actually split between the LPU and GPU. That's what makes the extremely fast token generation economical. We can focus and run the computations that benefit from the fast SRAM of the LPU over here in one layer, and literally the next layer, we can send the intermediate activation state over to the GPUs to do all the attention math, all the softmax, all the routing, all the KV calculations, so that only the LPUs need to have copies of the weights. All the per-query state, all the KV[cache] state, which can get quite large, can operate and stay in the HBMs.

Of course, both processors can do both things. The LPUs can do the attention math. Obviously the GPUs can do the [...] as well. So you can optimize for resiliency.

Dynamo was launched a year ago. It was nicknamed the operating system of [the] AI factory. I will say it's been a roaring success. If any of you got to go to the Dynamo meetups, it was where all of the different users of Dynamo, developers, and customers were all talking. I think we get about 100 GitHub submissions a day now, and about a third of them are coming from external [sources].

Vera CPU positioning

Ian Buck: Definitely happy to talk about Vera. I've actually brought with me the Vera board. This is the Vera module. It's a reference module that we give to system partners, which they can build. It has two Vera CPUs and LPDDR5 memory. So this is a dual-socket server that will operate and run all of the tooling: PyTorch, compiling, SQL queries, as well as for HPC partners.

It is the world's best agentic CPU. It has 88 cores designed so that you can put everything on. Turn on everything. Run them all at full speed. Compile on every core. Browse or render on every core. Python on every core. SQL on every core.

The agentic world needs a CPU that has the world's best single-threaded performance under load, has the world's best memory bandwidth under load, and has the best energy efficiency under load. And it turns out, while it started with a CPU that was an excellent CPU to be married with our GPUs, it makes perfect sense that all the things we needed to do to operate and run AI with our GPUs also makes a great CPU as well.

Journalist 1: Is it safe to say [Rubin] CPX is not going to come out in 2026?

Ian Buck: I'm never going to say no to how fast we can innovate. But I think we can do a lot better [with LPU decode first].

Journalist 2: Jensen was asked about the target market, target use case. And he said he was very careful about how he answered that. He didn't want to position it as a direct drop-in replacement for x86.

Ian Buck: We only are going to build one Vera SKU [...] other people are going to build x86 SKUs [...] the world is not going to be served by one SKU of CPU. And that's not our intention. The intention is that we'd like to solve a workload problem. It's not designed to be a dollar-per-vCPU chip. The amount of technology and, frankly, just the cost to build something that solves that critical workload makes it not for that market; it's a bad gaming chip.

But it is inspired by single-threaded performance. You may not need 88 cores, but it's actually a unique workload because in agentic AI, it's in the critical path for both training and running these models. When you're training a model to code, for example, you start from a model that needs to learn how to code better. And as you're training on Vera Rubin, you're halfway through training, and you say: go write a program that computes the Fibonacci series, or solves a New York Times crossword puzzle.

The AI model will then try to write that program. It then needs to score how well it did. We're not going to run that Python on the GPU. It's a CPU job. The GPU tells the CPU to go run it. So it opens up a sandbox, boots a Linux instance, starts the Python interpreter, executes, compiles, and runs that code. And it's got to score it — how well did it do? Lines of code, accuracy, did it crash? — very quickly. So that all those results from the training run can get back to the GPU in order to do the next iteration of training.

It is in the critical path. There are ways of overlapping. You'll hear about off-policy, where maybe you're training on the N-minus-one data, doing pipelining. But you can't do too much of that because you get model drift.

So what the world is asking for, what it needs, is a really fast CPU that can generate a lot of training data while you're training in order to make the model faster, and never let [the] GPU go idle. This might be a $30 billion, gigawatt data center of GPUs. I'm not going to skimp on the CPU side and have it sit idle, or have the potential of that model come up short because I couldn't run the compilation for too long and had to cut it off.

And then finally, when you actually deploy AI after you're done training, it's not just the AI model. The GPUs are telling the CPUs what to do. They run a SQL query, or they render an image, or they go to a website — all that’s happening on the CPUs. The more tool calling that can happen in fixed power, the more efficient it can be and still maintain these interactive use cases, the more valuable those tokens are.

And lastly, as we get to the agent world, where it's not just us doing chatbot with humans in the loop, we're going to have agents talking to agents at machine speed. You just took humans out of the loop again. That can happen as fast as the computers can compute.

Journalist 2: So, just to be clear, your customers — your ODMs, your Dell, HPs — if they want to build a system, that’s what they’ll get?

Ian Buck: They can build it like this [referring to the reference board brought to the Q&A] or, we will ship the chip itself.

Journalist 2: So, in theory then, your partners could go off the reservation and build a gaming PC, or whatever they wanted to do with it?

Ian Buck: They could. I think they’re all highly motivated to build what Nvidia recommends [and take advantage of] the opportunities with agentic use cases.

Intel NVLink Fusion partnership

Journalist 3: Ian, what's become of the partnership with Intel? Last year, you guys announced a partnership.

Ian Buck: We didn't talk about it in this keynote, but it's progressing. Fusion is a key part of that strategy. It's an IP block plus a chiplet that allows CPUs like x86 to talk across NVLink to our GPUs, or even other accelerators. We've announced multiple partnerships including Intel, and that is definitely progressing. It takes a little while to integrate at the silicon level. Obviously, it's pretty intimate integration. But I think we'll see some more announcements about that shortly.

Journalist 4: Is that partnership going to involve implementing Nvidia IP on Intel process technology? And if so, who's going to be doing the lifting there?

Ian Buck: There's a separation between the manufacturing of who builds the chip or chiplets from the IP integration. The integration I talk about is the IP hooking into the fabric of the processor. This [the Vera module] is actually multiple chiplets. You've got multiple I/O dies, memory interface tiles, as well as the core. If you look at the right angle, you can see one, two, three, four, five, six pieces of silicon come together. So who builds which piece, in which factory, and who does the integration, that's up to the partners. It'll be different for each integration.

Journalist 2: We asked Jensen about that, and he said, look, our bits will be coming from TSMC, the Intel stuff will be coming from wherever they choose to get it.

Journalist 4: I think we're trying to determine, is this a toe in the water to develop Nvidia IP on Intel process technology? I asked Jensen yesterday, and he said he's not excited.

Ian Buck: Obviously those questions are his [Jensen’s] domain. He's a good person to be asking about those questions.

CPX is still a good idea, says Buck

Journalist 4: Looking at the disaggregated architecture that you've implemented with LPX, it does strike me as a situation where it almost makes more sense to pair CPX with LPX racks rather than relying on an HBM-based product like Rubin.

Ian Buck: CPX is still a good idea. It is the opportunity to improve token throughput, to get to that next tier of agents talking to agents that need to run a 1 trillion, 2 trillion parameter model with 400,000 to 500,000 KV input context at token rates of about 1,000 tokens per second, because there's no human in the loop. Input tokens do impact decode speed [...] so 400,000 tokens of context significantly changes the token rate.

When we talk about pivoting from CPX to LPU, that's where the focus was. Right now there's a limit to how many chips [...] we want to do this this year. We want to do this with Vera Rubin. Just because of that effort, this will help those agentic AI frontier labs be able to take that level of intelligence to market.

The volume AI market is offline inference, non-reasoning chatbots, recommendation systems, reasoning chatbots, multimodal, deep research. This [LPX] will not add value to all of those. Everything can be served on [Vera Rubin NVL72]. But that next tier is super important as we turn the corner, and it was important to make sure we had that brought to market this year.

CPX is an optimization, it’s still a good idea [and] it would help break down the cost of the pre-fill stage, but sing these GPUs for the pre-fill portion of the workload is sufficient right now.

LPX paired with Vera Rubin

Journalist 4: If CPX is not coming until 2027, but Vera as a standalone is available sooner than that, is the Vera CPU going to be available sooner [unintelligible] will there be something that doesn’t use AI to compare it with before 2027?

Ian Buck: The LPU racks, Groq, they would run the whole model on the LPU racks alone. That capability exists. But the challenge with doing that is you had to feed not only the entire model, but all of the KV cache and all of the multiple queries on an SRAM chip that only has 500 megabytes. This [Vera Rubin GPU] has 280 gigabytes.

So as models got bigger and contexts got larger, and you just had to keep all of that state around, as well as do all that attention math, it gets costly to have that many LPUs run a trillion-parameter model with the weights plus KV cache. It didn't need to be paired with anything. But it was very expensive. And Jensen showed that in the chart as well. You could get to 1,000 tokens per second, but the economics of doing that with that many chips just don't work.

It has nothing to do with prefill. Pre-fill is just step one, how quickly can you get to your first token. After you've done that, there's pre-fill, GPUs, or whatever you're using in pre-fill. It doesn't matter. Your token rate is all about the number of processors you're using to generate every token after that. So it's not as simple as that. If you just did [Groq 3] LPX, you would need a lot of chips because of all that context.

By combining the LPX with Vera Rubin, we don't need all that. We just do on the LPU what it's good at, which is basically the memory bandwidth, seven times faster than HBM. That lets the mixture-of-experts layers that are inside each expert group run here. The whole rest of the model, all the attention math, can run on the GPUs.

So instead of dozens of racks of LPX, we can deliver that level of performance with just two racks of LPX and one rack of Vera Rubin. And as a result, the token rate gets to 1,000 tokens per second, but the economics go back to the sweet spot. Tokens will be higher value for sure, tens or hundreds of tokens per second rather than thousands. And you can also deploy at data center scale to serve a market. Building it once, serving a few customers in a highly constrained environment is nice, but that doesn't create a market. You have to build an architecture that, by combining LPX with Vera Rubin at one-to-one, or one-to-two, or maybe one-to-four rack ratios, can activate a market to deploy a 100-megawatt data center, a 500-megawatt, a gigawatt data center and serve those models economically.

Journalist 4: And just to be clear, all those benefits you're talking about are on the decode side, after we're over the pre-fill hump?

Ian Buck: Pre-fill [...] it’s just the first token. How long does it take to get the first token? That's all CPX was trying to optimize. It's an important problem, but you can solve it with existing hardware. You can solve it with NVL72, with the older architectures. We can reduce the time to first token, and we can also solve it today by just adding a few more [...] it parallelizes very easily. But it's just the first token. [LPU decode] will increase the speed of every token after that.

LPX chip-to-chip

Journalist 3: I was wondering if you could talk a little bit more about how the LPX is going to connect to other chips, both in the Nvidia ecosystem and outside the Nvidia ecosystem? What about working with CPUs that other companies might make or that customers might procure from elsewhere?

Ian Buck: When we licensed the IP, obviously there was limited stuff that we could change. But there were some last-minute changes that we were able to make to bring it to market. So this is the version [Groq 3/LP30], which is almost largely what it was. We're still using the chip-to-chip signaling that was already there.

Journalist 4: So there's no Nvidia NVLink chip-to-chip on it yet.

Ian Buck: Not yet. As the roadmap shows, it's coming with LP40 in the next generation. That's when we'll add the NVLink interconnect. On the next version, we'll also rev the compute side, and we'll add FP4 capabilities and all the Tensor Core math stuff that we have in our GPUs.

Scale-up rack-to-rack

Journalist 1: Can you walk us through how scale-up rack-to-rack works?

Ian Buck: [Pointing to the Vera Rubin module] This is a Vera Rubin. I have two Rubin GPUs here, one Vera CPU. These are the NVLink connections. This is purposely that close. This stuff is flying. The bandwidth in this direction [NVLink] is between 10x to 20x more, in terabytes per second, than in this direction [PCIe]. Here, we just use the same connector, but we have multiple lanes of PCIe connected to networking, multiple NICs, storage planes, or other systems.

The significance between the amount of bandwidth [intelligible] this way... you need that much bandwidth to have all GPUs within one rack really operating as one. The main use of scale-up is parallelism, taking the most compute-intensive part of the computation and doing tensor parallelism across all the GPUs.

When the world went to mixture of experts, where every layer has many experts [intelligible], Kimi K2 has over 200 experts per layer but only activates eight of them. Imagine using your entire brain to do two plus two. All those experts have to talk to all those experts extremely fast. That's why NVLink is so fast and why we have a dedicated NVSwitch, a lot of them in the rack, purposely in the middle of the racks so the signal is super fast.

We do it all in copper. You'll see the copper cables in the back. There's over 5,000 of them, because short-run copper is both fast and cheap. There's no retimers. It's also the lowest power. I don't have to drive a retimer or a transceiver or an optical fiber. One of the real reasons we went to liquid cooling was not just to get GPU performance, but to connect as many GPUs together in copper so that we could provide scale-up without exploding the cost. You could build 72 GPUs all with fiber and that many transceivers, but it's expensive and would consume a lot of power. A transceiver can consume significant power just slamming the laser on and off.

This generation, we're all in copper. Jensen did talk about going beyond 72 GPUs per rack. In the overall design of the NVSwitches, we're actually building an NVSwitch that has ports in the front. We can do a level two of NVLink and actually scale up the number of GPUs to 576. We have a prototype of that working with Grace Blackwell right now.

The models today don't benefit from that, but the models tomorrow will. It's a chicken-and-egg relationship between what capability we have versus what the models can do. And it's important that we show we're doing that, so that next-generation models can take advantage of it and design for that future where we have two layers of NVLink scale-up.

With the Kyber rack, we can densify further. We can put 144 GPUs in a single rack, again all in copper. And then we can even go a step further: with 144, we can scale to 576, and then double to 1,152. I really look forward to showing you that when we get there.

Journalist 4: Could you clarify how optical connections intersect with the roadmap? If there's an optical-capable rack with Grace Blackwell in it, does that mean you're going to put co-packaged optics with that generation?

Ian Buck: Rubin gets optical. And Ambulink is CPO [co-packaged optics].

Journalist 1: With LP30 only supporting FP8, are you looking at on-the-fly dequantization, or do you need to run everything in FP8?

Ian Buck: You don't need to run everything in FP8. Today's FP4, NVFP4, is done layer by layer, or actually block by block. When you go and look at Nvidia-optimized versions of all these models, you'll see that some of the math is FP16, FP8, and FP4. We can mix and match.

The way the engineers do it is they explore the space and then they run both hand-coded and AI-generated kernels to try all the different combinations. We then run that on a fleet of GPUs that we've rented back from the clouds to explore the space to make sure it's performant and accurate. We also test to make sure the accuracy didn't fall off or drop to a point where it's no longer valuable.

One big data point that's kind of fun: in October to January, the team was optimizing specifically focused on DeepSeek and DeepSeek-like models. They got that 4x uplift in just four months. Same GPUs, all the ones that everyone's already bought, the whole install base 4x faster.

To do that, they actually ran about 250 simulations and then about 1.2 million GPU hours. We had all sorts of ideas exploring the entire space across a massive fleet of GPUs for four months to get those results.

There is still more to come. Software is an untold story here. People like to say who's got the faster chip, and I'm like, who's got the better software ecosystem? That's why it's so hard to benchmark these things, because the whole stack end-to-end matters. How efficiently all of your different chips work together. We need six chips today, seven chips tomorrow to make all this stuff actually get performance. And the combinatorial optimization space is massive. We've got 400 engineers that work on that, and it came to 1.2 million GPU hours.

[Session ends]

Earlier this month, Apple released the MacBook Neo, a $599 laptop that impressed reviewers (myself included) with surprisingly good quality for the price.

"Yes, the MacBook Neo is $599. But it rarely feels like it," I wrote in my review. "Apple invested in a premium aluminium chassis, a bright, good-quality screen, and a decent keyboard and mouse. Putting performance aside, those are the parts of a computer that most people care the most about."

I stand by those words, but there are, of course, people who put performance above all else, even at $599. And to those people, I have good news: You can get a Windows PC!

Some table stakes here: We haven't been able to review a ton of budget Windows PCs. In fact, the companies that make them don't usually like to make them available for loans. But we've done a bit of internet window shopping, and using some comparisons from our own data and online, we can more closely evaluate the performance gains that some Windows laptops offer at this price point.

The competition

I browsed multiple big box stores and shops from laptop manufacturers. One quick theme came up: Many laptop deals in this price range are sold by third-party sellers, some of which don't seem so reputable.

I stuck with laptops that are being sold directly from the vendor's store. The MacBook Neo, sold at many stores, will come with a 1-year warranty and support. So these systems had to, also. That weeded out a surprising number of candidates.

To get good pricing, though, some of this had to rely on sales. For example, HP sells a 14-inch laptop on its website with a $499.99 MSRP with a last-gen Intel N150, a 1366 x 768 display topping at 250 nits, 4GB of RAM, 64GB of eMMC storage, and Windows 11 Home in S Mode. At least it has a Copilot key? Shoppers should be aware that they can do better if they shop around.

I chose three major competitors:

• Lenovo IdeaPad Slim 3x, a Snapdragon laptop with the latest standards, but a two-year old CPU. Sound familiar?
• Asus Vivobook Go 15, a $499 notebook, matching the MacBook Neo's education price.
• Dell 14 Plus, on sale exclusively for $649 at Dell.com, shows what an extra $50 can get you on Windows if you catch the right sale.

Here they are in a table to compare the major specs:

Something for everyone

If you want a premium experience, the MacBook Neo will win. Of these systems, the Neo is the only one with a completely aluminum body. Others, like the IdeaPad and the Dell 16 Plus, have aluminum top covers but are otherwise made of plastic. Apple’s is also the lightest machine of the bunch, at 2.7 pounds, while the IdeaPad and Asus are both more than 3.5 pounds.

The big question most people will want to know is about system memory. The Qualcomm-based IdeaPad and the Dell 16 Plus both come with 16GB, while the Asus sticks with 8GB, like the Neo. All of those are soldered (in Dell's case, it's also on-package because it uses Intel's Lunar Lake architecture).

Apple's A18 Pro, a six-core processor with 2 performance cores and 4 efficiency cores, debuted in the iPhone 16 Pro in 2024. The Intel Core Ultra 5 226V in the Dell, an 8-core processor, was released the same year. Months later, in January 2025, the 8-core Qualcomm Snapdragon X (X1-26-100), the least-powerful chip in this laptop lineup, dropped. The Vivobook Go boasts the oldest processor; the AMD Ryzen 5 7520U launched in 2022 with 4 cores on a 6nm process (that platform launched in 2023).

I can tell you from experience that the MacBook Neo's display is significantly better than what you typically see in big box stores at the $599 price point. If you get this Dell 16 Plus while on sale, you can get a 2560 x 1600 screen, which is slightly higher in resolution. But Dell is only promising 300 nits of brightness; we measured the Neo at 452.6 nits. Asus promises just 250 nits of brightness. On paper, the Neo sure sounds better – and it looks quite good in person. The other laptops offer bog-standard 1080p displays, which I would've called good enough for the price until now.

Both Apple and Dell have 1080p webcams. Those vary a ton in quality. I know Apple's is great, I can't speak for Dell's. When I showed Apple's to managing editor Matt Safford, he said, "I'm pretty sure that's the best-looking 1080p [laptop] webcam I've ever seen." The other two have 720p webcams, but hey, at least they have privacy shutters.

All of Apple's competition has larger batteries, though that isn't everything in battery life. In our MacBook Neo review, the Surface Laptop with Snapdragon X Plus and a 50 WHr battery outperformed the Neo, so it's possible that the IdeaPad, with a lower-power chip and a 60 Whr battery, and a lower-resolution, likely dimmer, lower screen would go even longer.

Apple's laptop also comes with a 20W USB-C charger. You could use a faster one, but if we're going based on what you get in the box, that's measly. The IdeaPad and Dell come with 65W chargers, while the Vivobook comes with a 45W charger.

One of the biggest issues I had with the MacBook Neo was the lack of backlit keys. Lenovo has backlit keys on the IdeaPad, as does Dell on the 14 Plus. But Asus' Vivobook also has darkened keys.

There’s no doubt that Apple's competitors offer more ports, including mixes of USB-A and USB-C, SD card readers, and even a Thunderbolt 4 port on that Dell. Many of the USB ports are 5GBps, making them slower than the fastest port on the Mac. But if variety trumps speed, then the PC is your friend here.

Single and multi-core performance

The main reason these systems weren't compared in our Neo review was that we didn't have scores in our benchmark database. Just to get a sense of performance, though, we're comparing our Geekbench 6 scores for the MacBook Neo to what we're seeing in the Geekbench database for others. It's not ideal, but it's what we've got to work with.

In this comparison, we see that Apple's Neo with A18 Pro still maintains a strong lead in single-core performance, where most Neo owners are likely to spend most of their time browsing the web, writing documents, working on spreadsheets, watching videos or movies, or doing other basic tasks. That being said, if you do switch into multi-core performance, both the Qualcomm Snapdragon X1-26-100 and Intel Core Ultra 5 226V outdid the Neo. Given the IdeaPad and Dell Plus housing those laptops also have 16GB of RAM as configured, they're more able to run multi-core tasks well in the first place.

Geekbench is great for emulating short, bursty workloads — the kind you're likely to run on a budget laptop. But this may not be illustrative of how these systems perform over a longer duration of time. And of course, a lot depends on what you actually do on your laptop.

What about education pricing?

Apple shaves $100 off the MacBook Neo for education pricing, bringing it down to $499, the same price as the Asus Vivobook. When you compare this head-to-head with the Vivobook on paper, the Neo wins every time, with the Vivobook’s bigger battery. (A larger battery doesn't inherently mean better battery life, though).

That being said, there is one important note to think about: software. While many students will likely be able to get along just fine with macOS, if you're in a specialized high school program or college major that uses software that only runs on Windows, you'll need a PC. If that's the case, leaning towards x86, like that Intel Lunar Lake chip in the Dell, is probably a smart choice; Qualcomm still has some work to do on app compatibility.

But if you're doing most work in the browser, Microsoft Office, or other software available on both platforms, the Mac's price will be extremely enticing here. The best Windows competitors are a bit more expensive.

A new breed of competition?

In general, when I review systems, I review everything about the system, as a full package. And for people doing basic tasks, I maintain that the MacBook Neo is a great value.

That being said, it does have limits. Those who need multi-core performance, more RAM, and more ports (and more properly-labeled ports, at that) do have options in this price range. You just have to give up something else, like build quality and/or a bright screen. That's how cheap laptops tend to work. But on single-core workloads, build quality, and when it comes to the displays, you really do have to hand it to Apple.

In Asus' most recent earnings call, co-CEO S.Y. Hsu said that the MacBook Neo was "certainly a shock to the entire market,” before turning around and saying it was mostly a content consumption device with just 8GB of RAM that you can't upgrade. I would tell him to also look at the Vivobook his company sells.

But that shock will hopefully lay the foundation for better competition from Windows OEMs at lower prices. It will be difficult during this RAM crisis, but raising the bar for budget notebooks across the ecosystem would really be great for everyone, no matter what operating system they prefer. And frankly, Apple's competitors better be ready to answer the MacBook Neo with something that feels as complete as the Neo does, or they'll risk looking out of touch. There are plenty of people who prefer a Windows PC to a Mac, but it's not like Microsoft has been earning fans with its OS lately. There's work to do.

Intel's 2026 roadmap is unlike any the company has published in recent years, because its manufacturing ambitions and its product launches have to succeed simultaneously.

Panther Lake, the Core Ultra Series 3 laptop processor unveiled at CES in January, is the first consumer chip built on Intel 18A — the company's new process node combining RibbonFET GAA transistors with PowerVia backside power delivery. Clearwater Forest, the next-generation Xeon E-core server CPU formally introduced March 3 at MWC 2026, is the server counterpart to it, and both are proof points for a foundry business that Intel has publicly stated could not justify proceeding to its next node, 14A, without first securing a major external customer.

Meanwhile, Intel is currently shipping the AI data center chip Gaudi 3, which has been available through cloud partners since late 2024. The chip was supposed to be followed by Falcon Shores, but Intel cancelled it for commercial release and confirmed it would deploy the chip internally instead, redirecting its GPU roadmap toward inference workloads. That produced Crescent Island, an inference-focused data center GPU which is expected to enter customer testing in the second half of 2026, with a potential successor in ‘Jaguar Shores’, due 2027.

Meteor Lake to Nova Lake

Since 2023, Intel's consumer CPU roadmap has focused on architectural consolidation, including the abandonment of the monolithic die. Meteor Lake, which launched in December 2023 as the first Core Ultra series processor, moved Intel's consumer laptop chips onto Intel 4 with Foveros 3D packaging, splitting compute, graphics, SoC, and I/O functions across separate tiles connected via hybrid bonding. That was an inflection point, with every subsequent generation iterating on that foundation rather than departing from it.

Then came Lunar Lake, the Core Ultra 200V series that launched in September 2024, which Intel hailed as its most power-efficient x86 platform, targeting the Copilot+ PC category with a fourth-generation NPU and the debut of the Xe2 graphics architecture. Arrow Lake followed in October 2024 as the desktop counterpart under the Core Ultra 200S branding.

While both share the multi-tile approach, they diverge at the process level. Arrow Lake consumer parts don’t use Intel 20A; Intel publicly confirmed the decision to use external nodes instead — almost certainly from TSMC — for the consumer desktop line. Intel originally said that 20A would be the node that would introduce RibbonFET and PowerVia, but the company moved those technologies to 18A instead and treated 20A as a stepping stone it bypassed for production.

Panther Lake, announced at CES in January 2026 as Core Ultra Series 3, is the first client platform built on Intel 18A. Intel cited over 200 system designs in development across laptop partners, alongside a claimed 60% better multi-threaded performance versus Lunar Lake at similar power, and up to 180 total platform TOPS — 120 of which come from the Xe3 integrated GPU and 50 from the NPU 5 architecture. Those figures are Intel estimates tied to specific workloads and comparison generations; the NPU alone meets Microsoft's 40 TOPS threshold for Copilot+ PC certification, but the 180 TOPS figure reflects all three compute engines combined.

Nova Lake is next, with Intel's Q4 2025 earnings guidance initially targeting an end-of-2026 launch. This, as we understand, is likely to be delayed to 2027; process node and die configuration details remain unconfirmed, and it’s far too early to speculate given that the upcoming Arrow Lake refresh (Core Ultra 200K Plus) is still to come.

Xeon and data center CPUs

Xeon 6 formalized a split Intel had been building toward for several years: P-core variants targeted at compute-intensive and AI inference workloads, and E-core variants aimed at density, throughput-per-watt, and scale-out workloads like containerized cloud infrastructure.

Sierra Forest launched in June 2024 as the first Intel 3 server product. Its E-core design packs a high thread count into a constrained thermal envelope, making it well-suited for high-density rack deployments. Granite Rapids, the P-core counterpart, followed in September 2024, targeting scientific computing, high-performance databases, and AI inference on large models. Both families share a common platform foundation — a unified I/O die connected via EMIB packaging — which reduces platform churn for OEMs and provides a validation reuse advantage across derivative SKUs.

Meanwhile, Clearwater Forest, introduced March 3 at MWC 2026, is Intel's first 18A server CPU. Expected to be released later this year, the chip packs 288 Darkmont E-cores across 12 compute chiplets in its maximum configuration, each with 24 cores all built on 18A. Those compute tiles are stacked on three active base dies fabricated on Intel 3 using Foveros Direct 3D, while two I/O tiles on Intel 7 handle connectivity, and lateral integration across the package is handled by EMIB.

EMIB 3.5D then extends this further by combining those Foveros-stacked modules with Intel's second-generation EMIB bridges — scaled from 55-micron to 45-micron bump pitch — to link heterogeneous tiles laterally across the package, whether those are identical compute modules or disparate I/O and memory dies. The result is a package whose total silicon area far exceeds what a conventional silicon interposer could accommodate. A clean Clearwater Forest launch would therefore validate both Intel 18A and its advanced packaging simultaneously.

Finally, Diamond Rapids will arrive as an exclusively 16-channel platform after Intel cancelled the 8-channel SKUs that were originally planned for the Xeon 7 lineup. The remaining parts are expected to pack up to 192 P-cores across four compute tiles in an LGA9324 package, with 2nd-generation MRDIMM support pushing memory bandwidth to roughly 1.6 TB/s — nearly double Granite Rapids' ~844 GB/s. Intel has indicated a 2H 2026 launch window, but has said nothing more solid at this stage.

AI accelerators

Intel’s AI accelerator portfolio hasn’t followed as clean a generational progression as its CPUs have. Gaudi 3, as previously mentioned, is the current shipping product and has been available through cloud partners and direct customers since late 2024, with Intel expanding availability throughout 2025.

Intel has marketed Gaudi 3 around openness and software portability, with the argument being that customers locked into Nvidia’s CUDA ecosystem face procurement and pricing constraints that a chip running on open frameworks like PyTorch and oneAPI can avoid. While this has let the chip find some traction, Gaudi 3 hasn’t achieved a meaningful share in large-scale training clusters where Nvidia’s accelerators still dominate by a huge margin.

The most concrete successor to Gaudi 3 in the near-term is Crescent Island, which Intel announced as an inference-focused data center GPU in October 2025 at the OCP Global Summit, with customer sampling due to begin in the second half of 2026. The card is built on the Xe3P architecture, a performance-enhanced version of the Xe3 GPU used in Panther Lake, and carries 160 GB of LPDDR5X memory.

That memory choice is a deliberate departure from the HBM stacks used by Nvidia and AMD in their high-end accelerators: Intel is positioning Crescent Island as a power- and cost-optimized part for air-cooled enterprise servers, with Intel CTO Sachin Katti citing "tokens-as-a-service" providers as the primary target. No performance figures have been disclosed.

When and if it does sample later this year, it will be going up against AMD's Instinct MI450 and Nvidia's Vera Rubin architecture, both of which use HBM4 and target a broader range of workloads. Crescent Island's narrower inference focus could make it competitive on cost-per-token, but the 160GB LPDDR5X configuration offers substantially less memory bandwidth than HBM-based competitors, which remains the main bottleneck for large model inference.

Jaguar Shores, meanwhile, has been confirmed by Intel as a product, though technical details about it remain sparse. Intel products chief Michelle Johnston Holthaus stated during the company's Q1 2025 earnings call that Jaguar Shores remains on the AI roadmap despite the cancellation of its predecessor, Falcon Shores, and described it as a rack-scale design incorporating silicon photonics interconnects. Intel has also confirmed, via a slide shown at its AI Summit, that Jaguar Shores will carry the Gaudi brand and use HBM4 memory from SK hynix.

Should it launch, Jaguar Shores would be Intel’s first return to HBM-based AI acceleration since Ponte Vecchio, but specifications remain unconfirmed, and we’re very unlikely to see a release until 2027 at the earliest. That would put it up against Nvidia’s Vera Rubin successors and AMD’s Instinct MI500 series — and whether it can be competitive by then depends heavily on software maturity, an area where Intel’s track record in AI acceleration has been consistently weak.

Process nodes and packaging

Intel 4, which debuted with Meteor Lake, was Intel's first EUV-enabled manufacturing node, claiming 21.5% higher frequencies at the same power as Intel 7, or 40% lower power consumption at the same frequency, alongside a 2x transistor density improvement for high-performance libraries. Intel 4 also introduced second-generation Contact-over-Active-Gate, enhanced copper interconnects with cobalt cladding for better performance and electromigration resistance, and doubled MIM capacitance density to reduce voltage droop.

Production ran at Intel's D1 facility in Hillsboro, Oregon, with Fab 34 in Ireland coming online for Intel 4 volume production in late 2023. Notably, only Meteor Lake's compute tile used Intel 4; the graphics, SoC, and I/O tiles were sourced from TSMC and older Intel nodes, reflecting the limited scope of Intel 4 as a chiplet-specific node.

Intel 3 followed as an 18% performance-per-watt improvement over Intel 4, with broader EUV usage, improved transistor cells, and both I/O and high-density cell libraries suited for server workloads. Sierra Forest, which launched in June 2024 as the first E-core Xeon 6, was its first flagship product, followed by Granite Rapids with P-cores in September 2024. Unlike Intel 4, Intel 3 was designed as a more general-purpose node from the start, underpinning Intel's server ramp and serving as the base die for Clearwater Forest's heterogeneous packaging.

Intel 20A, meanwhile, was the planned introduction point for RibbonFET and PowerVia in production, and Intel confirmed it entered production readiness in 2024. But Intel also confirmed the decision to shift Arrow Lake consumer parts away from Intel 20A to external nodes. The only logical explanation for this is that Intel concentrated its 20A engineering on proving the key technologies it needed for 18A rather than committing a high-volume product line to an intermediate node.

Every product on Intel's 2026-2028 roadmap runs on Intel 18A, the company's first node to combine RibbonFET gate-all-around transistors with PowerVia backside power delivery. RibbonFET wraps the gate entirely around the channel on all four sides, improving electrostatic control and reducing leakage compared to the FinFET structures Intel used through its 10th Gen era. PowerVia routes power through the back of the silicon wafer, freeing front-side routing resources for signal interconnects. 18A entered high-volume manufacturing in October, but yields remain below profitable levels and, per CFO David Zinsner, will not reach desired cost thresholds until the end of 2026 at the earliest.

Intel 14A, which uses High-NA EUV — which Intel is the first to deploy — remains contingent on securing a major external foundry customer. The good news is that Intel has said it has two prospective customers in the works following early PDK access, and CEO Lip-Bu Tan reckons that firm supplier decisions will be made in the “second half of this year… extending into the first half of 2027.” A lot is riding on these prospective customers, with Intel having publicly discussed the possibility of slowing or cancelling 14A and subsequent nodes if external foundry revenue does not materialize at scale. Without it, the capital expenditure required to develop and ramp leading-edge nodes past 18A will become extremely difficult to justify.

The future of Intel

Whether Clearwater Forest's 2026 launch materializes will be a solid indication of whether 18A performs at the scale Intel has projected, while Panther Lake's rollout through laptop OEMs will test whether 18A volume manufacturing is genuinely ramping up or still constrained to early production quantities.

Meanwhile, any announcement from Intel Foundry on an external customer committing to 18A or beginning 14A engagement could substantially change the economics of Intel’s roadmap.

During the 10nm era, Intel's manufacturing problems were visible and protracted over several years. Today's timeline is more compressed, and Intel’s public milestones — Panther Lake and Clearwater Forest shipping on 18A in close succession — are specific enough to hold the company to account.

The voracious hardware demands on AI hyperscalers have been driving up prices (and driving down availability) of all kinds of PC hardware for half a year now. If you’re after a new external SSD, prices have so far nearly doubled from their all-time lows. But compared to the price of RAM, an RTX 5090, or an internal SSD, spending 70-80% more for external storage than you would have paid this time last year is a relative bargain.

And if you do need a new external drive, you might want to buy one soon. Because new drive launches in 2026 seem to be few and far between, as we should expect given the current demands on the supply of flash storage. And it seems likely that the few companies that are launching new external drives may be having to make do with some… less-than-ideal NAND. Exhibit A: Take a look at the sustained writes from this Orico drive I recently reviewed.

In our real-world file transfer test, it was at least in the range of other drives of its class.

But when it comes to sustained write speeds, the results were the worst I’ve seen for any SSD since I started testing external storage for Tom’s Hardware. We use Iometer to hammer the SSD with sequential writes for 15 minutes to measure the size of the write cache and performance after the cache is saturated.

Keep in mind that we tested a 512GB review sample, so the faster SLC cache will be larger on higher-capacity models. But if and when you do enough fast writing to hit the native NAND speed, you are looking at writes in the 60-80 MB/s range – with occasional dips below 50 MB/s.

This performance was so low that I reached out to Orico to make sure this was the expected speed and we weren’t dealing with a faulty drive. A representative told me that, while higher-capacity models would have more SLC cache and perform slightly better overall, “the product is functioning normally and there are no quality issues.”

In short, the drive was working as expected, while delivering sustained write speeds that are worse than hard drive write speeds, and even worse than many of the best flash drives we’ve tested. I had to get a closer look.

Opening the BookDrive

Prying the BookDrive open, the controller for the internal M.2 drive is a DRAMless Maxiotek map1202C, which Google tells me has been used in various drives going back as far as 2019. I couldn’t identify the maker of the flash, though. Neither the two alphanumeric strings silkscreened on the NAND packages showed up in search results, and there doesn’t seem to be another label underneath what’s on the surface of the chips.

But regardless of who made them, the flash in this “new” external SSD has the slowest write performance of any solid-state drive I’ve tested in at least a decade – and possibly ever. Even Intel’s 2008-era X25-M internal SSD managed to hit 72.2 MB/s writes in our testing — I didn’t start testing SSDs until sometime in 2009.

External storage in 2026

Granted, the surprisingly bad performance of one recent drive may not definitively tell us a whole lot about all the external storage drives launching in 2026. But we’re already in mid-March, and Sandisk is the only major SSD company I’m aware of that has announced new portable drives this year. We’re awaiting those SSDs for testing, and I fully expect them to perform much better than the Orico drive above.

But Sandisk’s new mid-range (20 Gbps) Extreme V3 drive sells for $459.99 direct from SanDisk (supposedly marked down from $574.99). And given the 20 Gbps interface bandwidth cap, how much better could that new drive be than Crucial’s X10 Pro drive that I tested (and was generally impressed by) back in 2023? Parent company Micron may have publicly ditched its consumer-focused Crucial brand in favor of the lucrative AI market late last year, but the X10 Pro is still readily available, and at a current $259 for the 2TB model, it’s priced $200 (just shy of 44%) less than Sandisk’s brand-new drive at the same capacity.

It seems pretty safe to assume that any new external SSDs from big-name brands will be priced similarly to Sandisk’s recently announced drives. Because, from a business standpoint, any stock that flash companies are holding back from their eager AI customers to put into consumer products is probably a financial risk. And any new product from smaller drive makers (generally those who aren’t making their own flash), if there are many new products at all, will have to make do with whatever scrap flash is available that both AI companies and the flash makers themselves don’t want. Chances are, both the performance and the endurance of the flash in those drives will be questionable at best.

Buy soon, and consider an older SSD

In short, if you need a new solid-state external drive, I would advise looking at something that came out more than six months ago (before the rise of AI hyperscaler demand), that has been thoroughly tested (by Tom’s Hardware or some other site you trust), and that is still available at a reasonable price. Our Best External SSD page has six great solid-state options that we’ve tested.

Because who knows how long the stock of those older drives is going to last? While some new drives this year may be a little faster, they’re almost certainly going to be significantly more expensive than what’s available now. Any new drives from smaller companies may fail to meet even basic SSD performance expectations from several years ago. If you wait long enough and the market doesn’t improve, you may be stuck buying a drive that both costs much more and performs much worse than what’s available now.

The AI revolution has exposed our overreliance on a handful of companies that keep the tech world humming and society running smoothly. Nvidia’s dominant role in the supply of GPUs has propelled it to record valuations and boosted the stock market — and caused consternation over its control of the chips vital to AI advancement. And TSMC’s role as a dominant, leading-edge foundry has sparked geopolitical spats as the company's importance to the AI revolution becomes clear.

But beyond the headlines, there’s another overreliance issue to AI’s future hovering on the horizon — and it’s in a technology and component most people haven’t even heard of.

A Japanese company called Nittobo controls roughly 90% of the global supply of specialist glass-fiber cloth (T-glass), which sits inside every advanced AI chip package — and demand is now so high and supply so squeezed that it’s causing issues.

What is T-glass?

T-glass is a low-CTE (coefficient of thermal expansion) glass cloth used in the organic core of IC substrates — the interconnect layer that sits between a chip and its printed circuit board. It helps keep large, high-heat chip packages dimensionally stable as packaging gets denser and more complex, something that is becoming more important as AI processors grow bigger and run hotter. The physics of keeping AI processors flat and functional depends on T-glass.

Nittobo dominates that market, and neither it nor any other company can spin up a new T-glass production line overnight. The material requires specialized electric melting furnaces operating at temperatures between 1,600 and 1,700°C, and the manufacturing process takes years of investment and expertise to scale. That’s because it involves melting raw silica-rich glass, then spinning it into yarn and weaving it into an ultrathin cloth.

Another type of glass fiber used in semiconductor packaging is named E-glass, whichs is used much in the same manner. While E-glass is low-cost, it is mainly used in lower-end chips like microcontrollers and older mobile processors. Where T-glass slips in is in its thermal strength. For higher-powered chips, specifically for massive 2.5D and 3D packaging, and therefore advanced AI accelerators, T-glass is the preferred option.

Nittobo is tripling capacity at its Fukushima plant in Japan, but the new supply from the plant won’t arrive on the market until mid-2027. That squeezed supply means prices have risen between 20 and 30%, while lead times for downstream materials like copper-clad laminates have stretched from their normal 8 to 10 weeks to beyond 20.

“With T-glass supply even more constrained now, suppliers are no longer providing lead times,” said Bill Ho, analyst at Yuanta.

An irreplaceable option?

“It is not easy to replace the T-glass,” explained Bilal Hachemi, an analyst at Yole Group who tracks the IC substrate supply chain, in an interview with Tom’s Hardware Premium. The reason, he says, is that T-glass “has specific dielectric and CTE values that work better for the AI chips, especially for the organic core.” Hachemi points out that the IC substrate industry has historically operated on thin margins, which means even modest demand surges can trigger shortages. “Any increase in demand for build-up materials, ABF material, or T-glass can cause potential shortage, because it’s against the basics of this industry,” he said.

What makes the current crunch particularly acute is who is driving it. Hyperscalers are building or ordering ever-larger chip packages that require more T-glass per unit. Each subsequent generation of a given AI accelerator uses a bigger interposer and more complex substrate, which translates directly into greater material consumption. According to data from Nvidia, interposer sizes have grown from 814mm² for the Hopper architecture to 1,700mm² for Blackwell — a 109% increase — with the forthcoming Rubin and Feynman generations scaling further still.

Bank of America estimates that Nittobo’s electronic materials segment will see sales nearly double from ¥40.9 billion ($266 million) in 2025 to ¥87.7 billion by March 2028, with operating margins approaching 48%. “Demand for T-glass cloth seems likely to grow more than originally expected,” said Takashi Enomoto, research analyst at Bank of America. “The focus has been on growth in demand for thick T-glass for use in GPU and CPU semi packages, but now ultra-thin T-glass demand is likely to rise on a shift from E-glass to ultra-thin T-glass in leading-edge devices.”

With that in mind, the scramble for allocation has begun in earnest. Hachemi says that Nvidia reaching out directly to an upstream material supplier like Nittobo is unprecedented. “For the first time, we are seeing Nvidia, the end customer, reaching out to the upstream material suppliers to secure the capacity and make sure they will get it,” he explained, saying it was the first time he’d seen this happen in that particular area of the supply chain. The worry is that once Nvidia locks down its share, rival chip buyers will be left fighting over whatever remains.

Unlocking the blocks

Nittobo is investing heavily to try and ensure there’s plenty of demand for those who need it. Beyond the capacity increase at its Fukushima plant, Nittobo is doubling capacity of the raw yarn at its Taiwan plant and importing yarn back to Japan for cloth manufacturing. It has also struck a collaboration deal with Nanya Plastics to outsource some weaving.

That deal is an indication of how tight the market is: Nittobo is partnering with one of its biggest competitors to ease the bottleneck. By 2027, roughly 20% of Nittobo’s glass cloth is expected to be woven by Nanya, the company disclosed in a recent letter to shareholders.

Despite those efforts, relief from the tight market doesn’t look likely any time soon. Hachemi estimates the supply-demand imbalance won’t be resolved until the second half of 2027 at the earliest. And he warns that the same pattern could repeat with other critical materials in the IC substrate stack, pinpointing copper foil layers, solder mask, and copper-clad laminates as potential chokepoints.

“If you want to secure all the supply chain capacity regarding IC substrate, you need to look also for other important materials,” he said.

Just as with other physical elements of AI infrastructure, the T-glass shortage isn’t just affecting GPU packages. JPMorgan noted in a recent research note that demand for ultra-thin T-glass — which is used in smartphone memory and system-in-package applications — is also rising sharply, driven by a shift away from conventional E-glass in leading-edge devices. In recent years, Nittobo has prioritized thick T-glass expansion for the AI market, but now faces growing demand for ultra-thin variants as well.

Given the dominance of Nittobo, other companies have been reticent to try and move into the space. But new entrants are starting to try and spin up their own T-glass supplies, given such high demand. Taiwan Glass, Grace Fabric, and several Chinese manufacturers have been trying to produce comparable materials, but yields remain low enough to deter meaningful market entry. Nittobo’s advantage remains key because it has both proprietary glass composition and its direct-melting production method, a more cost-effective but technically demanding process that competitors have struggled to replicate.

Whether that changes by 2027 and the market begins to unlock, alongside Nittobo’s new capacity, is difficult to forecast. But even if it can, Hachemi has a warning for those thinking T-glass is the end of the problem. “A similar phenomena can happen to other materials, too,” he said.

As for Nittobo's customers, Nvidia's Jensen Huang has spoken on-record about enjoying the ongoing constraints: "I've got all the packaging, I've got all the systems, I've got all the connectors, I got all the cables. Everything from copper to multilayer ceramic capacitors, everything is secured." Huang said at a recent press conference, and T-Glass is just one crucial component in the ongoing AI build out.

Since late 2025, thanks to the AI boom, we’ve seen prices skyrocket for RAM, video cards, and now storage, making building or buying a PC today much more expensive than it was. Where you might, in the past, spend more on mid-range or even a premium-class motherboard, now that build budget is probably going to some other piece of high-priced hardware.

So, where can you save money without losing performance? One of those areas is the motherboard. For the latest-generation Intel and AMD boards, prices range from wallet-emptying $900 to $1,200 for Asus, Gigabyte, and MSI flagships, down to around $90 across the three primary chipsets (Intel Z890/B860/H810 and AMD X870E/B850/B840). There are lesser desktop chipsets from both camps – H810 for Intel and B840 for AMD. And although these motherboards are entry-level and cost less, they’re mainly meant for office use, everyday computing, or budget-oriented PCs. They’re essentially for those who really don’t need a ton of connectivity but still want the benefits of the latest platform, whereas others are more feature-rich and capable.

As you can see, there’s a huge price and feature gap between the cheapest and most expensive motherboards. The priciest boards offer the best hardware available for the platform, including 10 GbE, Wi-Fi 7, flagship-class audio, robust power delivery, fast memory support, fast (and more) storage, and more. The cheap boards use slower networking, a lower-quality audio codec, fewer power-delivery phases, and slower memory support, with fewer storage ports. But some boards punch above their weight class, while others may be overpriced relative to their features. So you should understand your wants and needs before making a purchase.

But the real question you should ask yourself when buying a motherboard today is, do you need most of these high-end features, or can you work with a much less expensive options with fewer, or perhaps, slower features? How bad, really, are the cheapest (or at least cheaper) motherboards?

What do you give up, how much can you save, and of course, how cheap is too cheap? The answers will vary depending on your needs, but we’ll dig into all of these questions below. Hopefully, you walk away with more knowledge to make a better-informed decision about saving money where you can, and perhaps spend the savings on RAM, video cards, or storage, where prices have really gone up.

AMD and Intel Chipsets: What you get on paper

Let’s start with what each chipset includes, so you can get a high-level view of what each offers. Note that what you see listed in our table is a minimum. Sometimes boards will add controllers for additional USB or SATA ports, a second Ethernet port, or additional functionality, such as bifurcating the PCIe slots. But here’s a table showing what each of the chipsets offers as a base:

As you can glean from the chart, AMD’s dual PROM21 chips that make up the X870E chipset offer the most native connectivity. The single-PROM21 chip X870 drops some things, and B850 and B840, which also use the same single PROM21 chip, drops more. When you get down to B850, and especially B840, you can lose PCIe 5.0 on the slot (B840 only supports PCIe 4.0), and some M.2 storage, and you generally won’t see USB4 ports either. In short, the further down you go in chipset families, the fewer of everything will be available.

Similar to AMD, Intel’s current-gen flagship chipset, Z890, offers all the bells and whistles (from a single chip, note), whereas B860 and especially H810 offer less of almost everything. Fewer USB ports, PCIe 5.0 slots, and M.2 storage. The further down you go, the less there is to start, and more becomes optional.

The key is knowing what you need today and what you’re likely to want in the future, so you can decide whether a cheap motherboard without some high-end features will be sufficient for your needs.

The main features you’re likely to lose by going cheap, and what matters most

One thing that definitely declines when going from flagship to more mainstream boards is the quality of Voltage Regulation Modules (VRMs). Budget-class motherboards list support for all compatible CPUs, but the MOSFETs and Chokes used on extreme-budget boards (in particular, the business-class chipsets from Intel and AMD) may not allow a high-power CPU to maintain its performance, as they can get too hot and throttle, lowering the voltage and clock speed. So one thing you definitely don’t want to do is pair a cheap H810 or B840 motherboard with a flagship-class processor and expect 100% performance all the time. Unless you plan to use an APU or low-power desktop CPU, I’d avoid any board without heatsinks on the VRMs.

Memory support is another specification that looks great on paper but doesn’t matter in the grand scheme of things, at least when talking about performance. The sweet spot for AMD machines today is around 6000-6400 MT/s, with the lowest CL rating. Intel supports higher memory speeds than AMD, thanks to CU DIMMs (with a built in clock driver to support the higher speeds). But the price and benefits of going that high (9000 MT/s or more) are rarely worth the cost of admission unless you're trying to break records. So Intel’s price-to-performance sweetspot, regardless of the higher supported speeds, is still a lot lower than the ceiling for most motherboards, and similar to AMD in the 6400 MT/s range, or even a bit higher.

In short, most motherboards will happily run faster RAM, but the performance difference between a DDR5-6000 CL36 kit and a DDR5-7200 CL34 kit (as we run in our testing) isn’t much. And the price for the same 32GB capacity at the higher speed is almost 25% more ($379.99 versus $474.99 for the same Patriot kit). The performance difference between the two memory speeds is only a couple of percent at best across real-world applications (in part due to the memory fabric dropping from 1:1 to 1:2). Unless you’re trying to break records or need extreme memory bandwidth for your work, you don’t need to worry about memory support on cheap motherboards, as most will run past what the platform is rated for and outside of the lowest Intel chipset (H810), capable of reaching these sweet spot speeds.

PCI-Express excess?

Another consideration is PCIe support. The fastest available on current platforms is PCIe 5.0, and you can use that bandwidth in both the PCIe slot(s) and the M.2 socket(s). PCI scaling, even on the best video card today, the RTX 5090, doesn’t matter much when you’re talking PCIe 5.0 x16/x8, or 4.0 x16. The difference is a margin of error for gaming, but can be more for other activities (like video rendering and game development - according to Puget Sound), with lower bandwidth. Even on the extreme budget side of things, it shouldn’t matter, as there’s at least one full bandwidth PCIe slot. Keep it above PCIe 4.0 x8, and you’d only notice any difference in benchmarks. Just be careful: On some boards, there is lane sharing between the PCIe slots and M.2 sockets, so installing a drive will cut the PCIe slot bandwidth in half; check the specs closely before buying.

Storage speeds and quantity

Storage is another important element. Unless you’re only ever going to install one drive, M.2 socket count, speed, and SATA port count are all important considerations when choosing a motherboard. On the most expensive motherboards, you get up to seven M.2 sockets (using included add-in-cards), with four PCIe 5.0 (128 Gbps) capable. And at the bottom end, it’s PCIe 4.0 x4 (64 Gbps) or half that with PCIe 3.0. That sounds like a big difference, and on paper it is, but you won’t notice a difference between PCIe 5.0 and 4.0-based M.2 storage unless you’re often transferring huge files between the fastest storage devices. And given the current price of SSDs, many more people will likely be living with PCIe 3.0 speeds, which is still generally fine for mainstream computing and gaming.

Rear expansion options

USB count on the rear IO (and front panel) is also a critical are of consideration. Too few, and you don’t have enough ports for your peripherals without adding a hub. Too many, or paying for speed you won’t use, can also be a waste, but more is generally better in this case. Most boards come with at least one Type-C and several Type-A with varying speeds. The higher up the chipset, the more speed and ports you’ll see, but the lower you go, the fewer. Case in point: Many of the really inexpensive motherboards don’t include a front-panel Type-C port of any kind, rendering that useful port on your case useless (at least without spending more money on adapters or an add-in card).

Wired and wireless networking

Networking on the cheapest of boards will still be fast enough for most users. Even if the board comes with a single 1 GbE and integrated Wi-fi 6/6E, that’s still plenty fast for most users. And many don’t have a 6E or above router to take advantage of the increased Wi-Fi speeds/specs. Obviously, as you climb the product stack, you see faster speeds (2.5/5/10 GbE) and the same with Wi-Fi (up to Wi-Fi 7). But most of us are using Gigabit internet and Ethernet, or less in the case of internet, so the only way to take advantage of the extra bandwidth is through a LAN (say, a NAS) with the same speed or faster ports. That said, some boards don’t ship with Wi-Fi at all, which is fine if you’re using Ethernet. Adding even the fastest M.2-based Wi-Fi 7 card is relatively cheap ($33.99) if you end up needing it.

Audio is another item that tends to fall by the wayside for most users. Right now, there are five prevalent codecs on the market. The older, basic Realtek ALC897, the last-generation Realtek ALC1200/1220, and the latest, ALC4080/4082. Even the ALC897 is sufficient for most people, but if you’re a gamer or a discerning listener with a decent set of speakers or cans, you’ll want to see the 1200 or 4000 series codecs in use. Or, if you have a pair of AudioEngine A2+ speakers (see our best PC speakers page) or another set of speakers with a built-in DAC, it’s irrelevant. As you move towards the top of the stack, Boards often include third-party DACs and amplifiers, which further improves things with the right equipment.

Build quality and good looks

Last but not least is build quality and aesthetics. Build quality is one of those things that sounds more important than it usually is. I’m not discounting the importance so much as saying it’s not often we see a spate of failures plague motherboards (though ASRock and Asus’ woes recently with AMD processors could constitute such a situation). More often, it's random, one-off issues. So, the build quality from the factory is generally good (or at least good enough), regardless of board class.

While the properties of motherboard components do differ through the product stack (like layers of the PCB or amount of copper used in the traces), for the most part, it doesn’t matter. More is generally still better, especially for those using high-end processors and planning to overclock (PBO or manual), but it also adds complexity and potential failure points. In other words, any board can be faulty or fail in several ways, regardless of price. So keep your receipts for at least a while after your system is up and running without issues.

Aesthetics is a polarizing subject. If you go cheap, budget-class boards tend to have fewer heatsinks, exposing more of the PCB, and they lack RGB (though you can add lighting through any onboard ARGB/RGB headers); budget boards generally do not look as good as the more expensive offerings. As you step up in price, you’ll see larger heatsinks, RGB lighting, and more ornate designs and features such as LCD screens on a few high-end/flagship models, or even faux-wood accents like on the Gigabyte X870E Aero Wood (pictured above). But if your board is going into a case without a window, or it's a function-over-form machine, looks don’t really matter. Still, the further down the stack you go, the ‘worse’ a motherboard generally looks.

Which Features Matter Most