China's LineShine is the world's fastest supercomputer – though having said that, it does depend on who exactly is counting. The machine, based in the National Supercomputing Center in Shenzhen, debuted at number one in the June 2026 TOP500 list published in mid-July because of its eye-popping results, with nearly 2.2 exaflops, or more than two quintillion floating-point calculations per second. The system also topped the competing HPCG ranking. But the picture was more mixed taken in the round: LineShine finished fourth on the mixed-precision HPL-MxP test and was well off the pace on the Green500 energy-efficiency table.

The gap for the supercomputer sits depending on who's ranking it, showing how what used to be a simple race for supremacy has actually become several overlapping competitions. It also highlights how "fastest" has different definitions depending on what is measured, how it is measured, and which operators publish their results.

We previously reported how LineShine uses 13.79 million cores built around China's domestic LingKun platform, 304-core LX2 processors, the proprietary LingQi interconnect, and Kylin operating system. It's also the first CPU-only machine on the TOP500 to sustain more than two exaflops, reaching around 80% of its theoretical peak while drawing 42.2 megawatts. That makes it impressive enough – but it’s also a big win on a geopolitical stage.

China rising

LineShine is the first Chinese system to lead the TOP500 since 2017, ending a period in which China stopped submitting its most advanced machines to the public ranking. Jack Dongarra, emeritus professor of computer science at the University of Tennessee and one of the TOP500's founders, has previously said that two unreported Chinese systems may already have been faster than the then-leading US machine, Frontier.

The TOP500 has used the High Performance Linpack benchmark, or HPL, since the ranking began in 1993. In the test, computers have to solve a dense web system of linear equations using double-precision arithmetic. Like many tests, the regularity of it can be heavily tuned, producing a clean output that invites long-run comparisons across architectures and decades.

It’s tempting to look at rankings like this as the be-all and end-all, but even TOP500 says its result doesn’t reflect a machine's overall performance, because no single number can. But HPL remains valuable because it tests whether millions of processor cores and the links between them can be corralled into one tightly coordinated calculation. "It shows you can go 400 kilometres per hour with your Porsche," said Julian Kunkel, professor of high-performance computing at the University of Göttingen and deputy head of high-performance computing at GWDG, in an interview with Tom’s Hardware Premium. "This is the maximum speed. TOP500 does not tell us anything other than we have an instrument that could go that far."

That speed matters because supercomputers are as much scientific instruments as anything else, used to simulate climate systems, aircraft engines, nuclear accidents and prospective fusion reactors. Scientists want answers relatively quickly. "Imagine I do the weather prediction for tomorrow, and you need 25 hours to calculate it," says Kunkel. By the time the answer arrives, so has tomorrow, rendering it useless.

A mixed picture

The HPCG test and its sparse calculations make less efficient use of processors while putting greater strain on memory bandwidth, latency, and communication between nodes – the sorts of things that scientific applications really need. LineShine's first-place score of 22 petaflops on this measure suggests that its memory and interconnect systems are as powerful as its CPUs. "Those results describe different capabilities, not a contradiction," said Dongarra, responding to Tom’s Hardware Premium’s questions by email.

But another ranking looks at performance in a different way. The way HPL-MxP is designed favors GPUs and dedicated tensor or matrix engines. On this one, LineShine nabbed fourth place globally with 7.92 exaflops, a 3.6-fold increase over its HPL result. But the published HPL and HPL-MxP lists show the accelerator-heavy El Capitan achieved a 9.2-fold improvement, Aurora 11.5-fold and Frontier 8.4-fold.

Dongarra said the different results on different checks show a trade-off in specialization, rather than a universal weakness. LineShine's CPU-centered design has less dedicated low-precision throughput, so other machines do better on mixed-precision workloads – but he said it would be churlish to say LineShine is less capable overall. And the IO500 – which Kunkel co-founded — tests storage bandwidth and metadata performance, while Green500 divides HPL performance by power consumption.

The different metrics by which supercomputers can be measured mean that those procuring them often overlook the rankings in favor of things like time-to-solution and reliability or energy use.

What about AI?

The race for public supercomputing has been disrupted by the rise of private AI infrastructure. Although Microsoft's Eagle system appears at number seven in the latest TOP500, most frontier AI clusters publish only GPU counts, theoretical FP8 performance, or tokens-per-second claims – and some don’t really disclose much at all publicly, worried that their competitors might pick up on it.

There are some AI-based testing regimes out there, including MLPerf, which offers standardized AI training and inference tests, including new DeepSeek-V3 and GPT-OSS 20B workloads in its 2026 training suite. However, submissions to the scoring system remain voluntary, and AI labs might not want to submit them in case they score badly, torpedoing their public perception — meaning we know very little about some of the world's most consequential computing systems.

It’s also a distraction, said the experts. "There is no sense for any private AI system to run HPL," said Kunkel. Doing so would take thousands of expensive accelerators away from commercial work and require days of tuning a result their customers don’t use, and probably don’t care about.

Dongarra reckons LineShine probably isn’t best at everything, even though among those systems that are submitting public results, it showed the strongest measured double-precision and HPCG performance. That, he believes, makes it good enough to say this is a very good supercomputer. Any credible assessment, he said, "requires a portfolio of measurements" — covering time-to-solution, sustained performance under mixed workloads, reliability, ease of programming, cost and power alongside the headline benchmarks.

So while LineShine's HPL victory is significant and technically impressive, it also highlights how there is no longer one supercomputer race. Systems whose results are never disclosed may be faster for particular AI workloads, "but without comparable public evidence,” said Dongarra, “that remains a claim rather than a ranking".

Divided across two countries and four campuses, Samsung's foundry roadmap runs from the Korean bases at Pyeongtaek, Hwaseong, and Giheung to the new U.S. site at Taylor. Samsung began mass-producing its first-gen 2nm process in 2025, moved equipment into its long-delayed Taylor, Texas fab in April this year, and lined up Tesla's AI6 processor under a $16.5 billion contract signed in July 2025, yet none of it has closed the gap with TSMC.

Samsung confirmed the 2nm milestone in its fourth-quarter 2025 results, the same release in which it returned its foundry unit toward profitability on the back of HBM4 logic-die orders. The unit still trails TSMC roughly 11:1 by revenue, and 2nm yields are reported to be sitting near 55%, below the threshold the business needs to run advanced nodes at a profit.

What separates Samsung from TSMC isn't fabs or customers but yield, and Samsung has been able to absorb the cost of that gap because its foundry unit sits inside the Device Solutions division alongside a memory business posting record profits. The company reports no standalone foundry P&L, which has given the operation years of runway that a pure-play foundry wouldn't have the benefit of.

Taylor, Texas

Samsung's Taylor project is both the centerpiece of its roadmap and the company's longest-running headache. The full campus, covering two fabs, an advanced packaging facility, and an R&D center, has been reported at around $44 billion, with the portion tied to U.S. funding set at over $37 billion. Samsung's CHIPS Act award was revised down from up to $6.4 billion to up to $4.745 billion as the project's scope narrowed, with Texas adding roughly $250 million in state incentives in September last year.

Construction stalled through 2024 and into 2025, with reporting at the time attributing the halt to an absence of committed customers and yield problems on the node the fab was meant to run. Samsung held an equipment move-in ceremony in April, and the site is now set to install a third-gen SF2P+ variant of its 2nm process, with trial production targeted by the end of 2026, full mass production in 2027, and a capacity goal of around 50,000 wafer starts per month. The facility's anchor tenant is Tesla, whose AI6 chip Samsung will build at Taylor under the eight-year deal running through 2033. Tesla's AI6 has reportedly slipped by around six months, tied to a delayed engineering run on Samsung's 2nm line, pushing volume toward late 2027.

Pyeongtaek

Pyeongtaek remains Samsung's largest production base, built out across a series of lines designated P1 through P5. In the near term, activity at Pyeongtaek centers on P4, where Samsung has pulled forward equipment move-in and is reported to be installing an HBM4 base-die line on its 1c-class DRAM, and on P5, the final planned fab at the site, where construction had been halted and is now reviving on the strength of AI memory demand. The P5 buildout carries a reported total investment of nearly 90 trillion won and a 2029 production target, according to Korean trade press.

The Korean expansion runs against a backdrop of capex restraint. Through 2024 and 2025, Samsung was reported to have cut foundry investment sharply and to have reviewed pausing both Pyeongtaek and Taylor work as losses mounted, with foundry utilization sitting around 50% in the second half of 2024 before recovering as clients returned.

Hwaseong and Giheung R&D

Process development runs out of Hwaseong's EUV line. The newer Giheung NRD-K research complex, a roughly 20 trillion won investment running to 2030 and dedicated to advanced-node R&D. Samsung deployed an ASML High-NA EUV research tool, the Twinscan EXE:5000, at Hwaseong for process development, and was understood to be buying two mass-production-class EXE:5200 systems — with the second originally being due to arrive in the first half of this year — aimed at the SF1.4 node and next-generation DRAM.

On the logic side, that plan has since shifted: Samsung's updated roadmap keeps SF1.4 on Low-NA tooling and reserves High-NA for the 1nm generation. Given that this research base feeds the production fabs, its output will now set the pace for how quickly Samsung can stabilize 2nm and move to 1.4nm.

The processes

Samsung's 2nm family runs from the first-generation SF2, now in mass production, through SF2P this year, the SF2P+ variant headed to Taylor, and SF2Z, which adds backside power delivery and is planned for mass production in 2027. The 1.4nm node, SF1.4, was originally targeted for 2027 mass production when Samsung announced it at the 2022 Foundry Forum. That date is now officially 2029, per an updated roadmap Samsung presented at the 2026 Next-Generation Lithography + Patterning Conference in August, which commits the company to three more years of refining the SF2 family before moving down a node.

The same presentation gave Samsung's first confirmation of where High-NA EUV enters production: not at 2nm or 1.4nm, but with the 1nm-class SF1A node around 2030. "We believe High-NA EUV will become necessary from A10 and below," Chang Min Park, Master VP of Technology at Samsung Electronics, told the conference, saying the tooling needs further improvement before it can carry mass production at larger nodes. SF1A is slated to run alongside SF1.4+, an enhanced 1.4nm variant that stays on proven Low-NA flows, so customers wary of High-NA's smaller exposure field and higher cost will have a fallback on familiar tooling.

As always, roadmaps live and die by their yields, and Samsung's is no exception. The company's first-gen 2nm yields were reported as climbing through 2025, but as of April, they still sat near 55%, below the level the business needs for profitable high-volume output, with reporting suggesting Qualcomm could route work back to TSMC as a result. These figures are obviously estimates rather than Samsung disclosures, and they've varied across sources, but they're consistent enough to say that yield — not capacity or customers — is Samsung's biggest constraint with 2nm.

To compensate, Samsung has been pulling back aggressively on price to stay competitive. The company is reported to have cut its 2nm wafer price to around $20,000, undercutting TSMC by roughly 33%, a discount that'll no doubt win price-sensitive work but compress the margin on a node already running below break-even yields. Undercutting on price while trailing on yield is a difficult combination to fund, which is why the unit's losses have set the pace of its recovery.

Exynos and external customers

Samsung's anchor customer on 2nm is its own mobile chip unit. The Exynos 2600, built on SF2, is the node's first commercial product and powers the standard Galaxy S26 and S26+. However, the Galaxy S26 Ultra runs Qualcomm's Snapdragon SoCs worldwide, and the Exynos reportedly covers only around a quarter to a third of S26 builds because yields cap how many it can supply.

A successor, the Exynos 2700 on SF2P, is in development for the Galaxy S27, with mass production targeted for the second half of this year. Samsung using its own processor to prove a node before committing to external customers is the same play we saw the company run at 3nm.

Externally, 2nm customers remain thin. The clearest to date is Japanese AI firm Preferred Networks, which Samsung confirmed as a turnkey customer for SF2 plus 2.5D packaging on AI accelerators. Tesla's AI6 is obviously the biggest name, and there are reports of a 2nm CPU order from a North American fabless customer identified as AMD and of advanced-stage talks with Qualcomm over Snapdragon work, though neither is confirmed.

HBM4

The strongest case for Samsung's integrated model sits in memory rather than logic. The company said it shipped the industry's first commercial HBM4 in February this year, running at 11.7 Gbps per pin against the 8 Gbps JEDEC baseline and extendable to 13 Gbps, with per-stack bandwidth up to 3.3 TB/s. The logic base die under that stack is built on Samsung's own 4nm foundry process, which lets the company source the base die in-house rather than buying it from TSMC as some rivals must, and it's reported to be moving the base die for custom HBM to its 2nm process for samples in 2027.

That capability has translated into qualification, with Nvidia CEO Jensen Huang confirming in June that Samsung, SK hynix, and Micron had all passed certification to supply HBM4 for the Vera Rubin platform. Samsung is still the smaller supplier, with analysts putting SK hynix at roughly two-thirds of Nvidia's HBM4 allocation and Samsung in the mid-20% range. Still, qualification of all three vendors ends the period when Samsung was locked out of Nvidia's top memory tier.

Samsung has also moved early on the next step, having begun shipping HBM4E samples around May, claiming roughly 3.6 TB/s of bandwidth, and is positioning custom HBM with logic-based dies tailored to individual accelerator customers, including Nvidia, AMD, Broadcom, and hyperscalers, with samples due in 2027. SK hynix followed with its own HBM4E samples weeks later, so although the lead is measured in weeks rather than generations, memory is the part of Samsung's business where it competes at the front rather than from behind.

Firmly in second place

Samsung has reshuffled its foundry leadership twice in a year, naming Han Jin-man to head the business in November 2024 and restoring a dual-CEO structure over the Device Solutions division in November 2025, with Jun Young-hyun over the DS division and Roh Tae-moon added as co-CEO.

The reshuffles followed a stretch in which foundry and System LSI losses were put by analysts at 3.18 trillion won for 2024, before reportedly narrowing below 1 trillion won by the third quarter of 2025 as utilization recovered from around 50% in late 2024 toward roughly 80% in early 2026. Chairman Jay Y. Lee has publicly ruled out spinning the foundry off to address the conflict that running it alongside the Exynos design unit creates for fabless customers, saying the company intends to grow the business rather than separate it.

The spending behind that recovery is massive, with Samsung having guided to more than 110 trillion won in combined facilities and R&D investment for 2026. The Device Solutions division is taking the bulk of a 10.2 trillion won first-quarter capital outlay, and Taylor ramp investments are set to rise from the second quarter onward. Ultimately, the company is funding an advanced-node buildout on both sides of the Pacific while the unit that runs those fabs is only now climbing back toward break-even.

In Q4 2025, TrendForce put TSMC's foundry revenue at $33.7 billion against roughly $3.4 billion for Samsung's foundry unit, leaving Samsung second with around 7% of the market. By Q1 2026, the same source had TSMC at $35.86 billion and Samsung near $3.2 billion, a gap of roughly 11 to one. Samsung is reported to be targeting foundry profitability by 2027, and a 20% market share, and its own 2026 guidance promises double-digit revenue growth and improved profitability driven by advanced nodes. The company is also reported to be reviewing a second Taylor fab and moving foundry leadership closer to its U.S. customers, a sign it's planning for the demand it hasn't yet converted.

Whether that holds depends on the same metric that has dogged the Taylor launch and the Tesla schedule. SF2 mass production and a marquee customer are both in place; what closes the distance to TSMC, or fails to, is yield reaching the level that makes a $44 billion fab and a $16.5 billion contract pay for themselves.

Buying a motherboard today can be a daunting task. There are more options than ever, with more features than ever, making it harder to know what you really need. Prices have also climbed consistently over the last several generations, with flagship motherboards now routinely costing as much as a high-end CPU or graphics card.

Modern motherboards range in price from under $100 for the most basic, to well over $1,000 for flagship/Halo-type boards from the ‘Big 4’ (Asus, ASRock, Gigabyte and MSI). But more expensive doesn’t always mean a better experience, especially if you’re likely not to use the hardware and features you’re paying for.

Several factors drive motherboard pricing. From the PCB layer count and copper content at your most basic level, chipset (some, like X870E, have two chips), power delivery, to controllers and premium components, they all increase the Bill of Materials (BOM). So what do you actually gain by spending more? It depends on the board, but outside of more robust power delivery, you tend to get additional, improved, or faster everything. Be it storage with M.2 sockets and SATA ports, USB ports, wired or wireless networking, the audio solution, or PCIe slots and bifurcation. And you can’t forget about the aesthetics. In general, the more you spend, the better the specs and the better they look. Some even include integrated screens. But it goes beyond just the hard specifications.

In addition to the hardware, motherboard partners attempt to inject value with DIY-friendly innovations such as toolless M.2 sockets and heatsinks, larger BIOSes with integrated drivers, or even quick-connect Wi-Fi antennas. All things that make building or swapping parts out easier on your PC. They’re even including “AI” features designed to help with overclocking and other functions like networking, or even local AI work, to make getting the most out of your system easier. And while some of those features can be valuable, their true worth is measured by the individual and whether they can get any use out of it.

The real question you need to ask yourself is what you need (and want) for how you use your PC today and in the near future, as every PC user is different. Whether you use your PC primarily for gaming, work purposes, or breaking overclocking records, needs will vary. The point of this article is to help users navigate through a dizzying array of options, determine what’s actually too much versus what you need, and perhaps save money by focusing on the right parts for your usage.

The cost of a motherboard

What, outside of marketing forces, drives motherboard pricing? First, there’s the BOM. Everything you see on the board has a cost. Starting with the PCB itself, it comes in layers like a sandwich, allowing all of the connectivity to reach where it needs to go without electrical interference. Budget boards tend to use fewer PCB layers and less copper, think 6-layer and 1 Oz, while mid-range and higher use 8/10 layers and 2 Oz of copper as selling points. Of course there’s validation and engineering costs that go into it, too.

On top of the PCB, you have various bits like the VRMs, which can range from downright anemic and a hindrance to performance, to overkill for anyone except extreme overclockers. Cheap boards tend only to give you the basics: fewer VRM phases and lower-rated MOSFETs (think 50A/60A), chokes, and capacitors. More expensive boards use a higher phase count and higher-rated MOSFETs, around 80A-110A.

For example, the popular 80A Intersil ISL99380 MOSFET can be found for around $2.72 apiece (@ 100 qty), while the less capable Vishay SIC623 50/60A is $1.69 per (@ 3,000 qty). Now, these prices are just what we can find online in lower quantities. If you need 100,000 units, prices will drop, and we don’t know what price the board partners contracted at. But the point is the difference in cost. The idea that the power bits on a 12-phase board with 50A MOSFETs will cost less than a 24-phase board with high-end 110A SPS MOSFETs should be clear, and we haven’t even touched on the chokes and capacitors that make up the VRMs.

Other onboard items such as network chips, USB controllers/hubs, SATA controllers, audio solutions with DACs and/or amplifiers, PCIe switches, BIOS chips, and more all add up (and that’s just the hardware/ICs). For example, a Marvell Aquantia AQC113 is around $27 apiece for 1,000 units, while the 2.5 GbE Realtek RTL8125BG can be found as low as $2 apiece for 30 units. Pricing isn’t publicly disclosed for many items to compare; for instance, we can’t find pricing for the ASmedia ASM4242 USB4 chip, but you can expect it to fetch a premium over most other supplemental, slower USB controllers. On the other side of the tracks, Intel’s JHL8540 Thunderbolt 4 chip costs a bit over $13 apiece for 2,000 units.

DIY-friendly features such as toolless M.2 sockets and PCIe latches likely also cost more than the basic M.2 socket with screws and PCIe slots without those features, but that’s something more tangible, even if it’s only used for installation and upgrade purposes, and likely not a significant part of the BOM cost.

You also can’t forget the appearance. From basic boards with minimal heatsinks and no RGBs to massive decorative heatsinks and shrouds, RGB lighting, and integrated screens, it all adds up. And of course, you have to factor in R&D to get these boards and all of their features created and to market in the first place. Just remember that not every additional dollar translates into something you’ll notice in everyday use.

Where does the value end?

Unfortunately, we don’t have a black-and-white answer to this question, as it depends on the person making the purchase and their needs, or how they plan to use the PC. Speaking generically, very few people need incredibly robust, 20-plus-phase, 110A MOSFET VRMs, even with a high-power flagship-class processor. Most users with any processor will be fine with a 12-18 phase board with 60-80A MOSFETs. There’s almost no point in paying the premium for a more-capable design so long as what it has can handle your processor without throttling it. And as you can see from our motherboard benchmarks below, performance is generally price-agnostic among these tightly grouped results.

Unless you plan to overclock and use extreme cooling methods, those monster 20-plus-phase 110A MOSFET power systems are overkill. Items like onboard buttons to adjust BCLK, voltage, or the multiplier are useless for all but the most extreme overclocking, used at the brink of stability. 99.9% of users who overclock can do so in the BIOS or use Windows tools without these extra features, which add cost. For example, the ASRock Z890 Taichi OCF with all of the overclocking bells and whistles for ~$400 isn’t the right choice unless you’re overclocking competitively.

Popular processors like the AMD Ryzen 7 9800X3D and other X3D derivatives won’t need anything close to that and work just fine with 10-12 phase 50-60A MOSFETs. The same goes with Intel. You’ll need a better motherboard for a Core Ultra 285K than for a 250K Plus, especially if you plan to overclock.

10 GbE, or even 5 GbE, networking is another item that, chances are, you don’t need for most PC activities. With average download speeds in the US hovering just over 300 Mbps, you don’t need to worry about faster wired connectivity unless you need the bandwidth for your internal network, like a NAS or transferring among devices on your internal network. For example, I have 1 Gbps (sequential) fiber, which is the fastest my area offers currently. In this case, 1 GbE is enough, but leaves no room for upgrades. A good sweet spot for wired networking is 2.5 GbE, so anything over that is overkill for anyone who doesn’t need a fast LAN connection.

Wireless networking is another story. 2025 and 2026 brought Wi-Fi 7 to the masses, supplanting Wi-Fi 6/6E. The problem here is that few have Wi-Fi 7 wireless devices in the first place. Your motherboard, and perhaps your new phone or laptop, may have it, but that’s about it. This also means you need a Wi-Fi 7-capable router, and if you don’t have a capable adapter, buy one, which increases the total cost of ownership. Chances are you’ll be fine on Wi-Fi 6E or even the ‘slower’ Wi-Fi 7 (160 MHz instead of 320 MHz), depending on your device count and bandwidth needs. The more you have of both, the more 320 MHz Wi-Fi 7 can be beneficial.

PCIe lane switches (read: bifurcation) are also something that not many users need unless you have PCIe add-in cards. This is something you’ll need to dig into the specifications to find, as it’s not typically listed as a feature. It generally happens automatically due to lane sharing anyway, but that ability can add cost to the bottom line. You also need to watch out for lane sharing so you get what you pay for with your chosen hardware. Be it M.2 sockets and PCIe, or USB and M.2 sockets, chances are you’ll experience lane sharing in some form or another on Intel and AMD chipsets, more so on the mainstream and high-end boards. And while money doesn’t prevent this occurrence, there are only so many lanes to go around; the more features you try to add to a limited number of lanes, the more it has to share.

Take, for example, the flagship MSI MEG X870E Godlike and Godlike X we reviewed. Even though this is a $1,000 motherboard, it’s still limited to the lanes and bandwidth the chipset offers. In this case, the rear USB4 ports share bandwidth with the second PCIe 5.0 x4 M.2 socket (M2_2). Here, because the board supports bifurcation, there are a few ways that setup plays out. If you want all of the bandwidth for the M.2, the USB4 port(s) are disabled. You can split them and share bandwidth, or you can get all the bandwidth for the USB4 ports, disabling the M.2 socket. On the same board, the third PCIe slot and fourth M.2 socket share the chipset's PCIe 4.0 lanes.

If we drop down to the X870 chipset, which uses only one Prom 21 chip and has fewer available lanes for sharing, we see a lot of the same thing. On the X870 Tomahawk Wifi (a $229 board), the rear USB4 port doesn’t share with anything but also only uses one PCIe 5.0 M.2 socket. Lane sharing on it is the same as the $1,000 Godlike between a PCIe slot and an M.2 device. In this case, the M.2 device doesn’t even receive the full x4 bandwidth, no matter what hardware is connected. The moral of the story here is to make sure you check the specifications and see what, if any, lane sharing occurs with your specific hardware configuration.

Who should buy what?

When selecting a motherboard, there are a few basic tenets I look at before purchasing, regardless of how I use the PC:

• CPU compatibility - You can’t fit square pegs into round holes. Intel doesn’t work with AMD, AM4 boards don’t work with AM5 processors, and so on. Make sure the board you want supports the processor you plan to purchase.
• Form Factor - Pick a size that fits your chassis: Mini-ITX, MicroATX, ATX, E-ATX.
• RAM Support - DDR4 or DDR5; again, you can’t fit square pegs into round holes. You can even save some money using DDR4 and not lose much performance.
• Storage - How many M.2 sockets do you need, and at what speeds? How many SATA ports?
• Expansion slots - How many do you need, and at what speeds? PCIe 5.0 or PCIe 4.0?
• Rear I/O and connectivity - Make sure you have enough USB ports and the speeds you need for the usage.
• Networking - How fast for the wired solution? Do I need two? Is Wi-Fi 7 an absolute need or a want?

At a high level, we can say motherboards that cost:

• Under $150: have basic functionality, fewer high-speed connections, weaker VRM designs
• $150-250: additional connectivity, the sweet spot for most users
• $250-400: even more connectivity, storage, and premium features, a sweet spot for enthusiasts
• $400+: enthusiast-class features, extreme VRMs, aesthetics, and diminishing returns
• $1,000+: Halo products where you pay for everything, not necessarily for better performance

Basics aside, how many and what speed you need for each feature varies depending on the person and how they plan to use the PC. Currently, I have seven USB devices, three M.2 drives, and one SATA-based HDD, along with a 9900X3D. By day, my workflows are generally light, with a dozen or two Chrome tabs up at one time along with Google Docs and a messaging application. By night, when my work is done, the kids are taken care of, and my wife goes to sleep, it’s a gaming PC.

A gamer’s needs are different than someone who uses the PC for content creation, for example, or a workstation user (powerful multi-core processors and a lot of RAM), or even a competitive overclocker. You don’t need a ton of or the fastest of anything to get the most out of your CPU, graphics card, and RAM. In other words, each type of user/functionality moves different features up and down on the priority list.

For example, as a budget-conscious gamer planning to use an X3D chip, I’d look at AMD and the B650E or B850 chipset-based motherboards, as they offer the best balance of price and features for a high-end gaming CPU without the tax of unnecessary enthusiast features. If you need advanced connectivity like USB and multiple PCIe 5.0 connections, that’s fine. The same goes for Intel; the B860 boards will do most users just fine.

Content creators often need a well-balanced system with high-speed connectivity such as Thunderbolt 4/5 or USB4, multiple M.2 storage slots, and fast networking to handle large media files and heavy workflows. You tend to see those features in X870/Z890 motherboards, specifically those with “Creator” in the title.

Extreme overclockers should look for boards with robust power delivery and overclocking features, such as integrated buttons on the motherboard or 2-DIMM slots that benefit memory overclocking. Boards like the ASRock X870E Taichi OCF ($499.99) or the Asus ROG Crosshair X870E Apex ($726.50) are good examples with features dedicated to overclocking and getting every last MHz out of your system. They are also overkill for just about everyone who doesn’t have a Dewar full of liquid nitrogen.

Final thoughts

So how much is actually too much? The takeaway is that it depends on the situation. Most of us don’t require overkill power delivery and massive VRM heatsinks. Nor do we need 4-5 M.2 sockets or a dozen USB ports, and we can easily get away with less. Most motherboards in the $250-$400 range in the mainstream and enthusiast segment offer enough of everything to be a ‘good enough’ solution for most users. That said, they can also be overkill. It’s when you get into the budget chipsets (think A620 for AMD and Q870/H810 for Intel) that you may run into problems with VRM capability when using high-end processors, as well as connectivity shortcomings.

It seems counterintuitive, and you do get more features on higher-tier motherboards, but buying a more expensive motherboard doesn’t let you bypass the platform's hard limits. It often adds more lane/bandwidth sharing. For the most part, this isn’t a bad thing. You just have to know what hardware you plan to use and what you need from it. Drawing on the examples above, do you need the USB4 port(s) and that bandwidth for external devices (like storage), or the second PCIe 5.0 M.2 socket and its 128 Gbps of bandwidth? Or do you need the last PCIe expansion slot for an add-in card?

If you can answer these questions, you’re most of the way to avoiding overbuying on your motherboard and can then put that extra cash toward something you can actually benefit from. The best motherboard isn’t the one with the most features: it’s the one with the features you actually need. If you still need some assistance buying a new motherboard, check out our best motherboard list, which covers a wide variety of platforms, form factors, and price points. You can also check out our curated best motherboard deals to stretch your dollar even further.

This week, we managed to sit down with Robert Hallock, Intel VP and General Manager of Enthusiast Channel Business, in a rare interview that catches the company during a curious time, between product cycles and several months after the launch of the Core Ultra 200S Plus lineup of CPUs. With the company’s data center business booming, have consumer products been left behind, or will Intel continue to step in the right direction in regaining trust with a core audience that it’s appealed to for decades: the humble enthusiast?

The following is a transcript of our interview with Hallock, which has been lightly edited for flow and clarity. We hope you enjoy this unredacted look, exclusively available to Tom’s Hardware Premium subscribers. You can also catch session transcripts from earlier in the year, featuring Intel, AMD, Nvidia, Valve, and more.

Jake Roach (Senior CPU Analyst, Tom’s Hardware): I appreciate you doing this outside of a typical product cycle.

Robert Hallock (VP & GM Enthusiast Channel Business, Intel): Of course.

Roach: I really just wanted to get your read on a lot of things because things are crazy in the enthusiast desktop space right now.

Hallock: They are.

Roach: So, how are things going in enthusiast desktop land given memory shortages, NAND shortages, everything going on right now?

Hallock: I think the market's experiencing a tale of two kingdoms. Yeah. For the folks who have a significant amount of discretionary budget, they can absorb the cost impacts of what's going on in the industry, and most other people cannot. Right? And that's having a very different impact, as you can imagine, on different parts of the market. Low-end mainstreams really taking a beating. Enthusiast and premium, not so bad. You could, depending on the device class, maybe even be growing positive. So it's a very starkly divided market at the moment.

Roach: I guess I hadn't heard that kind of take on it before. I guess it makes sense that you have more discretionary spending, or if you already were kind of invested in a certain ecosystem. I haven't heard that before.

Intel’s flexibility in the consumer market

Roach: I'm curious about the position of Intel right now. There's AMD, Intel, and Nvidia, right? And you've seen a kind of big shift for AMD and NVIDIA. Nvidia doesn't even break out gaming as a business category anymore; it's embedded now, and I think AMD is now coming up on close to double the data center revenue that they have from their client business. But for Intel, the majority of your revenue still comes from the client business. Does that put you in kind of a unique position right now with so much focus on the data center?

Hallock: I think that it does. I like to believe that it does, and I'm hoping, selfishly for myself, that it does. One of the things that I believe that Intel, that people truly sleep on about Intel when talking about the big fight of this company versus that company, just how big Intel is, how many resources Intel has. As I look at, for example, you know our desktop enthusiast roadmap, I don't have to trade supply with a data center part; I don't have to worry about it. I don't have to think about it.

I can build a roadmap and a plan for the market that is sized against purely what is going on in the client market. And that kind of freedom is very empowering when you're trying to run an enthusiast desktop business for enthusiasts, and it doesn't mean that we're immune to what's going on in the market. It doesn't mean we're immune to supply fluctuations upstream of us. That happens too, right? But at a fundamental level, I can sit down with my team and my partners and build a plan for a product for the year, and not have to worry about what's going on with Xeon, as an example, and vice versa, right? That's their luxury too, right? I can do my thing in client land, and they can do theirs in data center land, and it's okay. And so the size of Intel is what allows that to happen. And at it is at its best, it allows us to maximize the investment and the return on multiple product categories. It's a nice one that works out that way.

Roach: I think it's been maybe a few earnings calls back. There were some mentions in a couple of earnings calls about wafer allocation moving toward the data center to meet demand for Xeon. But you're saying that's not really a concern when it comes to future launches.

Hallock: No, and so, just to give a little inside baseball. It depends on what era you're talking about. If we're just coming into the sudden AI boom, where prices are multiplying very, very rapidly. That was a surprising moment for everyone in the industry. Like we kind of felt it coming.

We heard the rumors, but the size and scale were very abrupt. It was immediate. That is still surprising. It was immediate, and in those cases, yeah, you’re probably going to have to trade some supply around. But once you’re in, like once you’re in it, now you know the plan for it.

Roach: Okay, so that was a temporary measure, gotcha.

On Intel’s enthusiast roadamps

Roach: So, shifting back to the desktop, I know you've mentioned several times about this ambitious enthusiast roadmap, presumably that centers around 18A and Nova Lake. So far, what we've seen out of 18A has been more premium offerings. Obviously, we have Panther Lake; we have Wildcat Lake. Wildcat Lake [is] not a premium offering, but it makes some pretty big concessions to reach that budget price point of single-channel memory and all of that. So I'm curious, given that there is such a large divide between this enthusiast premium category, this budget category, do you think that the DIY PC market can be served by a single product stack, especially on this kind of cutting-edge node?

Hallock: I truly believe that what the market is going to see going forward, and this is just an industry-level comment, is, and I want to stress this is not just Intel...You're probably going to see a split. You'll have a premium socket and a mainstream socket from everybody. If you're playing in desktop space, that is probably what you'll do because the supply chain costs, the upstream costs, have the same costs that are currently harming the entry-level and mainstream market; I don't see those abating anytime soon, right? And so it means that in order to continue providing affordable computer hardware, you're going to have to make some design concessions.

You're going to have to make some concessions in your product stack, and that's purely to control costs and give people an option that they can actually afford. Otherwise, if you don't do it, the other alternative is it just disappears because it's unaffordable. So, seeing a split is likely the outcome for everybody.

Roach: I was telling Thomas yesterday when Gamer Days first came out, I think there was a day when the Core Ultra 250K Plus was $150. I’m like, ‘Man, at that price, that is one hell of a deal.’

Hallock: Hell of a CPU? Yes, it is.

Roach: So obviously we have Arrow Lake Refresh. Arrow Lake Refresh is great, very positive reception. But we've also seen this… One of the stories we really heard a lot from the motherboard guys at Computex was spinning up older DDR4 boards with LGA 1700. I think Gigabyte just reintroduced one a few days ago, and that's great to see because there weren't a ton of those boards even when Alder Lake launched.

But, one of the things that has been concerning for me – covering CPUs – is a lot of volatility in pricing on 13th- and 14th-gen processors, oftentimes selling for much more than comparables from AMD or even for certainly from from Arrow Lake. I'm wondering: are there any plans to maybe improve supply, or some sort of effort to stabilize the pricing of those so it's a bit more consistent?

Hallock: Well, I think what you're seeing is the fact that those 10nm parts are still phenomenally good. We don't spend a lot of time talking about them in the media or at Intel. It's old stuff, and we've all moved on. But they're still phenomenally good CPUs. And if you look at the sort of bucket of options that you can buy for these older DDR4 platforms, it is very likely that Alder Lake or Raptor Lake are the fastest of the bunch in that mix.

Roach: They are. I just recently did a whole DDR4 vs DDR5 article.

Hallock: And so what you're seeing is just like if people are going to go to more affordable hardware, they still want the fastest available for their money, and that happened to be Alder Lake and Raptor Lake. So there was a sudden inrush of demand into these parts that was certainly not anticipated when you start your wafers and your builds long before that moment ever happens. So it's very hard to predict. But going forward, 10-nanometer products like Raptor Lake – that is a core part of the portfolio that I want to offer to people for years to come. LGA 1700 is still a good socket. Lots of people are still interested in DDR4, so keep offering. And you'll see it smooth out over time. It'll come back to normal. That's the plan.

Roach: Yeah, it was really interesting going back because obviously with Alder Lake’s launch, there was a bunch of discussion about DDR4 versus DDR5, but seeing how it scaled all the way up to 14th-gen. You have the 14700K with DDR4 at parity with a 5800X3D in gaming, and obviously much faster in applications. So yeah, I’ve been hoping for a $300 14700K that I can recommend to people.

On Intel's approach to AI in the enthusiast segment

Roach: I wanted to shift a little bit away from desktop. I know that is your, well. I guess maybe not desktop, but the kind of traditional view of just a single-socketed processor. Intel has this kind of breadth of IP, great graphics IP, lots of experience with memory and advanced packaging. And honestly, it's been surprising to me that we haven't seen what I like to call the 'big chip’ out of Intel yet, a consumer 'big chip' out of Intel. Between Strix Halo, I guess Gorgon Halo now, the M-series from Apple, and of course RTX Spark. I appreciate that that's not directly under your purview, but do you think that's an important area of the market, or is this a way to kind of capitalize on this sudden rush in demand for kind of these AI developer workstations?

Hallock: Tricky to say. I'm not sure about that part of the roadmap, but it's an interesting place because in a before time, a big integrated graphics device would have been pitched for gaming, right? It would have been pitched for gaming.

And the market has not always responded positively to that sort of setup, like whether or not the performance is right or the power is right, and oftentimes it's better than the CPU plus discrete option you can get for the same price and the same power. It's better.

Just, there's something about it people just don't take it, and then this whole AI thing came along in a real way – the agentic AI component of it – and certainly renewed demand for that kind of hardware. Now, does that sustain? I don't know. Do people come out of this seeing the value for gaming again – that I also don't know. But you know, we are looking at it, we are exploring it. It's certainly an interesting part of the market. A lot of excitement. People love to talk about it. But interestingly, I don’t think the actual run rate is all that high. So, it’s something we’re cautious about.

Roach: I will tell you every single event I have been to where they've had one of these agentic 'buy your box and run an agent forever’ demos, I don't think I've ever seen a single person actually sitting and watching one of those demos. I don't know what that says, but interesting to note.

Hallock: Just on AI software in general… It's an evolutionary process. Businesses can absolutely benefit now, like Intel has. I personally have agents running for me at work to do processes that honestly took a lot of my time. Sure. And now they're completely automated, and I just have to fact-check them, and that's great. I've saved a lot of time doing this, but you know, the transition to an average consumer – I don't know if we're there yet, right? We're not there yet, and I suspect that's probably informing the demo interest. But it is also a bit of a chicken-and-egg thing.

If you are not AI-aware or AI-ingrained, if you haven't just been dunked in the AI bucket because of your job or your profession or whatever, it is difficult to imagine what you could use it for, right? So now you're caught in this trap, 'well, I've heard about it, I don't know what I could use it for, but then I can get my hands on it, and now I don't know what to do with it.' It's like learning a search engine when we all had to do that, right? But on steroids.

Roach: It’s funny having conversations with friends and people who aren’t in this world because… recording and transcription, right? Like, that’s a super great use case of just, I mean, it’s not even an agentic or an advanced thing. I’ll explain that to them. They’re like, ‘Oh, that’s a great use case.’ I mean, for most people, AI is the sloppy AI images and things like that. That’s AI. They see no other use case for it.

Hallock: That's the great injustice in this industry, right? There are so many things that we all call AI. They all have the same name. And some of them are just like a sticker on a toaster, and some of them are legitimately useful, and they run on your computer, and you have custody over your information and your privacy. That's not bad, but that's quite a spectrum. Yeah, one word, and it's such a shame.

Roach: It is a shame too. With the hardware advancements, it's a bummer being at Tom's Hardware, being mostly a consumer-facing brand, and talking about things like Vera, things like Venice. I'm sure later this month, things like Diamond Rapids. You know, and all that stuff is very interesting from a hardware perspective.

Challenging AMD with new consumer hardware

Roach: I was interested to hear your perspective on this. I was at Advancing AI last month for the Venice launch, and I don't know how long it's been, but it's certainly been since Ryzen, since the original Zen, that AMD's leading with Zen 6 in the data center instead of on client. I just wanted to get your reaction to that.

Hallock: I think it's a natural reaction for them. Makes a lot of sense. What I would say is, as we think about our own roadmap, I have a new core. *chuckles* It's coming to desktop first. I hope enthusiasts do the math about that one, and… That's all I'm going to say.

Roach: Okay, perfect. I would expect no less of a diplomatic response, but I appreciate the response nonetheless. That is, it is exciting to hear that there's still a focus on consumers, because I know for GPUs especially, but even some questions with CPUs about, are we even going to get new hardware? Like, is that a thing?

And I think this goes to a bit of an extreme that all of our local compute's going to wither away, and then it's all going to be cloud instances or whatever that we rent from some data center somewhere. I don't think that's the case, but it is encouraging to hear that there is at least some focus on launching new enthusiast products. I'm wonderi–

Hallock: Not just some focus; I have new CPUs all the way out to 2030. I have a back-to-back-to-back-to-back cadence for gamers, for desktop built for that purpose. Obviously I can’t go into what any of that is, but I’m accelerating for the gaming market. We are moving faster than we ever have in product and release cadence. We’re very serious about this.

Yeah, I understand people are skeptical after the last couple of years. I truly get that. But the signal Intel is trying to send is like… We’re gearing up for one of the most significant desktop CPU launches we have ever had.

We took a team that was time-shared with other businesses. And now this slice of the market has a full org structure inside Intel, and if you're not in corporate America, what that means is the company is so serious about it. They're putting real people, with a lot of budget behind it, right? And having an owner, a sponsor, people that care about it, looking after it – custodians of that work – it makes a real difference.

Just... The difference between Arrow Lake and Arrow Lake Refresh. That’s the difference.

Roach: Oh man, that was a big difference. Oh. Different teams on those? Okay, I hadn’t realized because when we talked about Arrow Lake Refresh, it was… You had made mention of like ‘Hey, we’ve updated our roadmap, and this is our first, maybe peace offering after Arrow Lake.’

But I didn’t realize it was a completely different, or not completely different, but a different team.

Hallock: Yeah, well. Pretty much completely different. Marketing people, different product managers, different business people, and simply, we have a different philosophy on how this market should run, and what people should get for their dollar. And I’m glad that people appreciate it.

A post-Arrow Lake shakeup

Roach: Okay, so there was a big shakeup after. That was one of the questions I had. What were the key takeaways from Arrow Lake? But it sounds like those takeaways were addressed immediately.

Hallock: A couple takeaways that you saw manifest in the [Arrow Lake] refresh launch: The software experience for DIYers, which nobody likes to admit that we all need software for our CPUs because they all have a lot more cores than any game typically expects these days. And so the resilience of that software experience. How do people obtain it? How do they install it? How can they validate your performance? How can they verify that they're getting what you are promising? All of that was kind of open-loop in the Arrow Lake original timeframe.

We had some aspects coming from motherboard vendor websites, some from Windows updates, some from Intel.com. It's too complicated for people, so that directly led into the Intel platform performance package- like, kind of crazy- but put all your useful bits in one spot and tell people to download it.

Well, when you lose sight of this enthusiast DIY space and how people consume software and hardware in this part of the market, it's easy to get turned around. OEMs have a very different strategy. They go through these massive validation efforts and have huge QA labs and can set up a system image with point releases, and… Normal people don't have those resources.

You have to make it very easy for them. So, software resilience was a big one. And then when you look at a pile of IP, some engineer says, ‘Hey, your CPU can do this to this.’ That's your range of capability, and inside you open the box. You've got some stuff you can smudge around, like frequencies or voltage or core counts or specs on and off. You can decide to remix those very differently too. You decide to price it differently.

So what you're seeing is Intel got healthy on its software foundations for DIYers. Intel got healthy on its respect for performance per dollar for customers. We set up some really healthy internal processes for future platforms. Arrow Lake was a tough, tough lesson to learn, but a good one, because it drove some really, really useful changes inside Intel.

The importance of CPU software optimization

Roach: You've really beaten the drum on the importance of software; software is just as important as hardware. Just this past week I was testing out the BC-250. If you're familiar.

Hallock: Yeah.

Roach: The PS5 APU that was repurposed. And if you need a crash course in the importance of software to a gaming experience, just boot up one of those things. But can you explain, from your view, what the importance of software is, especially given Intel's… This is pretty ancient history at this point, but you know, use of specific compilers and things like that. What is your view about the importance of software to an overall performance package?

Hallock: I am scared to open this box, lest I get misinterpreted. So, here’s the deal. From the perspective of a software developer, it's actually really tough to be a professional software developer, especially if you are not self-publishing, especially if you have a publisher breathing down your neck. Because it means that your publisher is picking the release time, not you.

That's time crunch number one. Time crunch number two is… What hardware are we targeting? What CPU do I have at my desk as a developer? What does our QA lab have? What has the publisher allowed us to buy with our budget for QA? What does my historical install base look like for other games? And every time you open the box on any of those, you find more subdivision of compatibility that you need to worry about. That's time crunch number two.

Time crunch number three is, did you start on a console, or did you start on PC? Which were you targeting first? Probably console. So now you have to do a port, which is a time crunch. Some publishers outsource this. There are companies that all they do is console ports to PC.

Roach: A lot of Sony games.

Hallock: You know, I’m thinking of Nixxes. What a great developer! They've been amazing over the years at doing these kinds of ports. So all you're really doing is budgeting a decreasing amount of time as a dev, and then you're like, okay, well, my game has to run on a CPU anywhere from four cores to, gosh, like 32 threads, 24 threads, depending on the vendor. It's a lot.

And so what ends up happening is they just draw a line in the sand. This is the hardware we have in QA. This is what's on my desk. This is what's in the console, and that's what we have time to look at. And maybe we'll look at other stuff later. And a lot of the time, one thing that many gamers still don't quite understand is, like, it's not even really the Windows scheduler or the OS scheduler that's determining how these CPUs get used when you're running a game-they have their own layer.

It's called an affinity mask, and they tell the OS how to use the CPU. So the game is in control of how to do the scheduling, sending all these hints to the operating system. What if those hints are wrong? What if those aren't the right hints for the CPU you have in the socket? What if the game is newer than your hardware, or substantially older than your hardware? Or the developer never looked at your combination?

These are all moments where the game can easily give up huge chunks of performance, or just not run. And everybody has to deal with this, right? Every CPU vendor has to address these challenges somehow. We call it the Intel Platform Performance package; AMD calls it the chipset driver.

Right, we've all got this, and it's so important because it can reach into the operating system, or reach into the application, or reach into the firmware of the CPU itself, and make those real-time adjustments to get the performance back. Gamers would not like how this industry looks without this software from the CPU vendors. It would be a much, much less performant, much slower, higher frame time, more stuttering, sort of environment.

Roach: Yeah, it’s already quite surprising to deal with.

Hallock: Yeah, software cannot replace the CPU, and that is not what we're proposing, right? We're not saying, 'hey, I'm going to give up 10% on the hardware and give you 10% back on the software because it's cheaper.' No, I want 10% of both.

That it’s not trade; it’s both. And that is why we’re interested in pursuing it, and why I think it’s so important, because I’ve now spent serious time at two processor companies and have seen the performance gains that come from this kind of software, and what they contribute to the experience, including my own gaming system that I’m talking to you on right now.

And so, that’s why I’m big on software, because the performance would be much, much worse without it – not insurmountably, but it would functionally limit the kind of hardware that you can produce if everything has to fit in this lowest common denominator of software. That’s the other outcome, and that would be even worse. We cannot have the hardware be stagnant because of the software.

Roach: Gotcha. Yeah. That’s certainly giving up. It’s not the 10% hardware for 10% software. Leaving stagnant software gives up a lot more.

Hallock: That’s right.

Roach: Yeah. You know, we did a story probably a couple of days ago. This guy who, we call him a hardware researcher, but he really just does memes. He made a C compiler that would compile completely with Move and Assembly, and then he made a leaderboard of… it was the x86 Hall of Shame, where he tried to find a single assembly instruction, how to make it run as slow as possible, and he got one up to 189 billion cycles.

Yeah, it was ridiculous. He basically found the two slowest areas in the fabric, the two highest-latency areas in the fabric. Ran the instruction on one of them, and then had the other one make a bunch of frivolous four-byte reads, and like lock it up. Yeah. Anyway, just a great example of how you can make hardware–

Hallock: What people don't understand, every CPU architecture is like the fine art of intelligent compromise, and it's like, okay, well, just as like a random example, could you make the read and write link the same size? Sure.

But what if the reads are like 10 times more common than the writes? Do you really need them to be bidirectionally the same size? Like it's going to show up on a micro benchmark. Someone's going to complain about it, but in real performance, day-to-day, do you actually need it? Yeah, probably not. And there's stuff like that all over a modern CPU based on decades of just, like, learning how people are likely to use this thing; it actually does shape the microarchitecture itself somewhat, like a reflexive principle, right? We speak it into existence by using our processors in a certain way. It's fun.

Checking in on IBOT

Roach: On software, I think I'm probably much higher on IBOT personally than you know. We've seen some interest in it. We did some testing for it. I think it's this thing that probably becomes more important as time goes on. I'm just wondering how it's going. We've had one update, I believe, one game update. I just wanted to check in on how IBOT’s coming along.

Hallock: Going well. You know, we continue to work on multiplayer support, which was kind of in the initial scope. It's taking, I think, longer than the public may have expected, because we certainly do not want people to get in trouble using this technology. And that means you have to talk to a lot of people to do it. We're actively working on non-gaming workloads.

We are working on another upcoming release. I don't have the exact date for this, but we're working on the bits for the next update. And then we're also thinking about, for Nova Lake, you know, what is version 2.0, for lack of a better phrase? What do we want to build into that release based on the new hardware capabilities? Which I know is both some details and not a lot of details, but it's very important to us; it is a long-term, permanent aspect of our roadmap.

Roach: Yeah, I think the game selection has been interesting to see. Obviously, when we spoke around Arrow Lake refresh, you had mentioned, ‘Hey, there's going to be a lot of games where there's no benefit whatsoever, or a lot of workloads in general where there's no benefit whatsoever. We just want to improve where we can.’

I'm curious how you go about finding those improvements, because surely it can't be just throwing everything at the wall and seeing what sticks.

Hallock: No, well, sometimes it is. Okay. Sometimes it is. It’s a multi-part process. We do have a team that proactively goes out and evaluates things that are very popular, high profile in the community. Just because it's so obvious to go grab those and take a look. We also have automated systems that go through workloads and try to find opportunities. That does a lot of heavy lifting. Dirty word, but we have AI tools that can also help us analyze and find opportunities. So it's one part manual and a lot of automation to find these, and we go from there.

Adressing Nova Lake rumors

Roach: I wanted to ask something a little bit more direct about Nova Lake because speculation around Nova Lake has been going on for a while. I wanted to focus on the high-end, there's been kind of these endless rumors about a 52-core part. You have teased previously scaling up Thread Director to deal with these higher core-count CPUs. I'm wondering right now: What does something like this ultra-high core count, or like a high-end desktop processor, what is that offering right now to the market, in your view?

Hallock: My view has always been that the market will initially go. ‘Ah, what am I going to do with this kind of hardware?’ And then they figure it out. And my most recent example of this comes from my time at AMD. I was sitting at Computex, and at the time we were unveiling our first 12-core CPU. So that would have been the 5900X, I think, maybe the 3900x. It's been a while, and I was sitting in the room with a bunch of journalists who – 18 months ago – had been like, "Why eight-core in consumer? What are you even talking about? Why? Why does this exist?” Same people sitting in front of me. I'm talking about a 12-core CPU, and they're like, "Where's your 16-core?" Like a poorly, poorly kept secret at that point, right? Like it was only like a week away from getting announced, and everybody knew it existed.

How quickly perspectives change. Suddenly, we went from four-core to eight-core, to 12, to 16 in three years. And man, how quickly people’s opinions changed about the value of [higher] core counts. I don’t think, in the history of the PC industry, [that] bigger bar better, more performance better. Never a bad answer. And that does inform my thinking about the roadmap, and Intel’s thinking about the roadmap going forward. It’s never a bad idea to offer more hardware to people.

Roach: The irony. About that, I think it was Zen...It must have been Zen 2. The irony about that is that the 12-core SKUs are always significantly worse than the eight-core and the 16-core. I guess there are some workloads where it makes sense, but yeah, it's interesting to hear.

I think, you know, one of the big hopes for Nova is a competitor to V-Cache. I know this is something you're well aware of, and you know has been brought up numerous times. I watched some previous interviews that you did, I believe, with a recent one with PC Games Hardware, and you had mentioned ways to improve cache locality as something like, ‘Hey, we don't just need to stack a bunch more cache on the chip. We have other levers we can pull to find this performance or to offer something that the X3D chips offer.’

I'm curious what those levers are, because you've made reference to them before, and I just wanted to get a little bit more of a technical explanation.

Hallock: We will have to wait for the fullness of time, won’t we?

Roach: Yes, we will. Hey. You can’t knock me for trying.

Hallock: No, you have to try, and I appreciate and respect that. You know, my bottom line is this is going to be both an answer and a non-answer. Sorry. But I want to try to answer the question for the public more generally. We understand and appreciate there is a like a lot of hope, a lot of expectation, and a lot of desire surrounding Nova Lake. We get it.

And in some ways... selfishly. We’ve lived through it. Every negative comment, every bad tweet, every crappy article. It wears on you. It really does. And we want to deliver a product with Nova Lake that meaningfully addresses these criticisms.

Yeah, just pick one [CPU from Intel or AMD]. I’m not going to confirm anything else, but pick one. I think the Nova Lake product will do the job.

Roach: Okay. Well, that's good to hear. I have to imagine, especially with Nova Lake in particular, given how much they're, you know… There's probably a story on Videocardz or WCCFTech, probably a lot on Tom's Hardware every two or three days. So, yeah, it's a lot.

Hallock: Well, I think it’s reflective of how excited people are, how much anticipation, how much demand is pent up for this moment.

Roach: I know we're almost out of time, but I did want to share with you real quick. It was a big thing that we talked about this year at CES. Actually, I was talking to AMD PR, and they were getting reactions [to AMD’s new announcements]. And I told them, I was like, man, there is a Dark Knight sentiment. You live long enough to see yourself become the villain…happening right now in the industry. I think there's certainly a lot of that reaction that we've seen at least. So, for what that's worth…

Hallock: I have read those comments. Yeah. You know, a product like Nova Lake cannot address every single slice of the market. It just can't, given the current market that we're in. But I, I do hope and do believe that people will look back and go, ‘damn, you know, that was pretty, pretty freaking good.’ Yeah, that's what we were hoping for. And if Intel just keeps going, we're gonna be okay. And that's the trajectory we're on. That's who I want to be, as a business for gamers.

Roach: Yeah, I've heard you say that numerous times, which is encouraging to hear. So I appreciate it, and yeah, thank you so much for taking the time to do this. You know, I always enjoy talking with you, and I'm excited to see what comes next.

[Session ends]

The AMD BC-250 has taken on a new life. It’s a PS5 APU that was repurposed for mining during the crypto boom, and now it’s being repurposed once again as a Linux gaming board. The BC-250 has seen some coverage in years past. It was originally a board you could pick up for less than $100, but now you’ll likely spend over $200 on one. We’re taking a closer look at the board and the performance it offers now for a few key reasons.

First, we have the Steam Machine. Valve’s long-awaited console-like PC is here and much more expensive than anyone expected at over $1,000. You can easily put together a BC-250 build for around $400 or $500, and even less if you have a power supply and SSD lying around. If you can get in the realm of Steam Machine performance for half the price (and the BC-250 can, based on our testing), that’s pretty compelling.

There have also been some significant developments among the BC-250 community. The board only works in the first place due to a community-developed BIOS and GPU driver, and developers have continued to experiment with what’s possible with the hardware. Now, there are tools that enable all 40 Compute Units (CUs) on the board (it defaults to 24 CUs), as well as tools to enable the two disabled Zen 2 cores, taking the six-core CPU to an eight-core CPU.

Now, the BC-250 isn’t a cut-down PS5 APU, at least from a hardware perspective. It actually patches two more graphics CUs compared to the PS5. Though, as should become clear throughout this story, relating the BC-250 to the PS5 on anything but the silicon on the board isn’t the best idea.

All in, we spent about $350 on the BC-250, with around $200 of that going toward the board (it’s currently listed for around $175 on eBay) and the additional budget going toward a 3D-printed case, fans, and a power supply. You could spend as little as the cost of the board if you can 3D print a case, bring your own fans, and repurpose an old PSU and NVMe SSD. If you’re starting from scratch, you’ll spend between $400 and $500.

Even for “full” price, the BC-250 is significantly cheaper than what you can get elsewhere. The PS5 digital edition is now $600, while the Pro will run you $900. The newly-released Steam Machine starts at $1,050, and that’s with just 512 GB of storage. The BC-250 is significantly cheaper and offers performance that can rival these platforms. What you save in money, however, you spend in time.

The BC-250 is a great project if you like tinkering, but it’s not a set-it-and-forget-it gaming device, even after the initial setup. After a few weeks of using the board, that much became clear.

A PS5 APU, not a PS5: BC-250 specifications

The BC-250 is described as a cut-down PS5 APU, and that’s exactly what it is, but the “cut-down” portion of the description carries a lot of weight. It comes with eight Zen 2 cores, but two of them are disabled, and a 40-CU RDNA 2 GPU, though only 24 of those CUs work out of the box.

The community has been able to unlock all 40 CUs with good success. Ultimately, your mileage with unlocking all 40 CUs will vary; some boards will work just fine with all 40, others with 32 or 36, and some with the base 24. As I’ll dig into more later, I was able to unlock all 40 CUs and run them stably up to 1,850 MHz, much higher than the recommended 1,500 MHz max frequency.

Out of the box, both the CPU and GPU run at locked frequencies of around 3.5 GHz and 1,500 MHz, respectively. You’ll need to separately install a GPU and CPU governor for dynamic frequency scaling (a necessity in the case of the GPU, though optional for the CPU). Achievable frequency on the CPU and GPU is entirely determined by your thermals. Both governors allow for overclocking, but the BC-250 is thermally constrained, even with active airflow, so don’t expect to push far beyond the stock frequency, particularly on the CPU.

Unfortunately, storage is a big bottleneck for the BC-250, and one of the biggest points of divergence compared to a PS5. The M.2 runs at just PCIe 2.0 x2 speeds, delivering about 1 GB/s of maximum performance with an NVMe SSD. The good news is that, due to how slow the interface is, you can save some money and get a less-performant but larger drive for storage.

As of a few days ago, at the time of writing, some initial fixes to unlock the extra two CPU cores have rolled out, which I was able to get working after a bit of trial and error. Outside of the GPU and CPU, the BC-250 has a bit less L3 cache. The APU, from a hardware perspective, is very similar to the PS5. Though that ignores the complex I/O system present in the PS5, not to mention the various layers of software that Sony runs on the APU.

Given that the BC-250 wasn’t designed for gaming, it’s important to keep that context in mind. You could just as easily describe it as a crypto mining board that’s been repurposed for gaming as you could a PS5 APU that’s been repurposed for mining. The BC-250 is a mining board, and the only reason it works is due to a large number of enthusiasts trying to get the damn thing to work and sharing their advancements along the way.

Although Linux gaming broadly has made a ton of advancements over the past few years, the BC-250 has unique hurdles you need to overcome. It needs fixes to scale the frequency on both the CPU and GPU; otherwise, it’s locked at a fixed frequency. It needs a custom BIOS image to even boot, and a specific configuration in the BIOS to avoid immediately crashing. Those are all steps you need to take to get the BC-250 to work in the first place, let alone start optimizing it to squeeze out the best performance.

There is extensive community documentation for the BC-250, which I referenced ad nauseam throughout this process. It’s an excellent resource, but even still, I had to search out solutions outside of the documentation. This is cobbled together from community fixes, and the documentation seeks to cover as many distros as possible. But it’s nigh impossible to have complete documentation on the BC-250, as valiant as the effort linked above is.

Expect a bumpy (but rewarding) road. It’s better to think of the BC-250 as a project, rather than a commodity like the PS5. Yes, you can play games on it and get surprisingly good performance, but you’ll spend a good amount of time simply tinkering with the machine, at first to get it to work, and later to optimize it. And you will inevitably run up against games that either don’t work or have poor performance, prompting another investigation and optimization cycle. I find the process rewarding; others will find it frustrating.

Setting up and configuring the BC-250

Getting the BC-250 is only one part of the process here. At the least, you need a power supply that can deliver at least 20A on the 12V rail. A standard PSU will work, but FlexATX power supplies are a better fit. I ended up purchasing a 3D-printed case, along with a power supply, from eBay. The BC-250 documentation includes several PSU recommendations, along with case designs, if you want to go about choosing your parts piecemeal.

Here’s what I’d recommend at minimum:

• BC-250
• 300W+ PSU (at least 20A on 12V rail)
• 2x Arctic P12 high-pressure fans (if using CU unlock)

Regardless of the route you choose, double-check fan mounting points (there aren’t any mounts on the BC-250 itself) and case/PSU compatibility. Many small form factor BC-250 designs you can 3D print are designed around a FlexATX PSU. Before booting, verify your 8-pin pinout against the community documentation. If the 12V pins are in the wrong position, you can fry your board.

With the board ready, the first step is to flash a new BIOS from the shell. It’s straightforward enough, though without the modern conveniences of firmware flashback in the event of a failure. If you lose power, you’ll brick your board and need a hardware controller to reset it, so I recommend connecting to a UPS during the flashing process. You can grab the correct files from the documentation.

From there, you need to clear your CMOS by removing the battery and configure a few BIOS options to force the integrated graphics, set the UMA frame buffer size, and disable IOMMU. From there, you need to choose which Linux distro you’re going to use, which is very important. I’d recommend experimenting with a few different distros, especially if you’re new to Linux.

For gaming, the go-to options are Bazzite and CachyOS, the former of which I originally went with. There are some “optimized” images floating around for the BC-250 that supposedly rope in all of the configuration and fixes you need into a fresh OS image. I wouldn’t recommend using those. Setting up the BC-250 is getting easier by the day (I have found new fixes and scripts that automate installing several fixes just in the time I’ve been testing the board), so these optimized images are, at best, out of date, and at worst, not actually optimized at all. Tread carefully.

You don’t need an optimized image because, at least for Bazzite and CachyOS, scripts exist that can automate the entire setup process. Strictly speaking, the only thing you need is the GPU governor. Previously, you would need a kernel patch, but a GPU governor via an SMU now exists and is what I used. The governor is what allows dynamic frequency scaling on the GPU, as well as overclocking.

You’ll also need a compatible kernel, which is easier to manage on rolling distros like CachyOS. 6.18.18 LTS is the recommended kernel at the time of writing, but 6.17.11+ works, along with 6.12.x to 6.14.x LTS. Other kernels may work, though some (such as 6.15.0) are broken and will trigger a kernel panic.

With your distro chosen and a correct kernel working, here are the optimization steps I took:

• Install GPU and CPU governor
• Unlock 40 CUs
• Setup Zswap with 32GB swap page
• Install ACPI fix
• Configure PWM sensors

Again, scripts exist for these patches, the most critical of which don’t even require kernel patching any longer. The exact fixes you need and the method to install them will depend on the distro you choose, however, so make sure to keep the setup documentation handy.

The list above is in order of importance. Once you have the GPU governor, the next step is to try to enable the full GPU. Previously, you would need a kernel patch, but the bc250-cu-live-manager utility can enable the CUs via a User Mode Register (UMR) without the need for a kernel patch. Not only is this easier to do, but it also persists across updates, unlike a kernel patch, where new kernels will force you to go through the unlock process again. The end result is identical regardless of the path you choose.

I spent a good deal of time testing the 40 CUs before doing any other optimizations, and I’d recommend you do the same. Just because the board has 40 CUs doesn’t mean you can use all of them. I was able to unlock all 40, though not at the frequencies some others have reported. And some users aren’t able to use all 40, rooting out bad clusters for a 32-CU or 36-CU configuration. Overclocking-like trial and error is necessary here, though, as we’ll get to in the performance section later, experimenting is worth the hassle. Using all 40 CUs, even at suboptimal clock speeds, offers much better performance.

Although setting everything up on Bazzite should be easy, I ran into issues numerous times. It’s an immutable OS image, which can cause problems depending on the fixes you’re trying to apply. It’s a great choice if you want to quickly set up the BC-250, but it became clear that an immutable image isn’t optimal if you want to get the best performance. Further, some newer fixes simply wouldn’t work, such as unlocking the extra two CPU cores.

The CachyOS pivot

After a few days of optimizing, testing, and troubleshooting Bazzite, I made the hard decision to wipe the machine and start fresh with CachyOS. In hindsight, I should have started with CachyOS from the beginning for numerous reasons, but mainly because it’s a rolling Arch-based distro. Bazzite is a Fedora Atomic-based distro. It’s immutable, adding guardrails to make it difficult to break anything, but in the process, making it much more difficult to apply low-level changes like kernel patches.

If you’re not familiar with Linux and don’t care to become familiar, Bazzite is your best bet. It’s convenient, and it includes a ton of small community fixes right in the startup menu, such as the LSFG-VK project for Lossless Scaling. It became clear, however, that you’re trading performance for convenience with Bazzite. CachyOS is more hands-on, but it’s much easier to actually accomplish what you need to with the BC-250.

Most notably, CachyOS (and other rolling release distros) allow you to easily manage your kernel. There are alternative methods for critical setup items like the GPU governor and CU unlock that don’t require a kernel patch. However, having the ability to easily patch your kernel helps when you run up against compatibility or performance issues, allowing you to try alternative installation methods or community fixes.

Further, CachyOS has access to yay, or Yet Another Yogurt, the simple command-line call to search and install packages from the Arch User Repository (AUR). It takes some time getting used to living in the command line as often as you do on any Arch-based distro. But even knowing just a few basic commands allows you to accomplish what you want much faster than fumbling around with flatpaks, at least in my experience.

Getting set back up was simple thanks to a community script that automates nearly all of the configuration and optimization for the BC-250. The BC250-Toolkit script brings together all of the various community patches, including optional optimizations, and it just worked. Coming off of Bazzite, it was a treat not to run up against the immutable walls of the distro. I was able to accomplish in a few hours what took me more than a day with Bazzite.

CachyOS specifically has a few optimizations for gaming, as well. First, there’s the BORE, or Burst-Oriented Response Enhancer, scheduler that, as the name implies, is optimized for bursty workloads (Michael Larabel over at Phoronix has a great writeup on that). CachyOS also includes packages for x86-64 v3 and v4, the former of which is relevant to the BC-250.

These optimizations represent a substantial performance improvement. In Forza Horizon 6, for example, I went from 61 FPS at 4K with the Low preset to 72 FPS on CachyOS after it was configured properly (with 40 CUs in both cases). In Cyberpunk 2077, I went from 74.7 FPS on Bazzite to 82.2 FPS at 1080p with the Steam Deck preset, and perhaps more impressively, from 47.8 FPS to 56.5 FPS at 1440p.

I saw higher peak performance on Bazzite in Unigine Superposition, though that’s likely due to more thermal headroom for the GPU, as I wasn’t able to enable the extra CPU cores on Bazzite. I mainly wanted to show this chart to bring the “optimized” Bazzite image into the fold, which was supposedly an image that was already configured for the BC-250. Using a script to automate the installation of several tools (like the one available for CachyOS) is one thing. Using an entirely custom image is another. I’d suggest starting with a clean, official image regardless of the distro you choose.

Testing performance on the BC-250

The best touchstone for comparisons with the BC-250 is the Steam Machine. The Steam Machine is more powerful simply based on the spec sheet. I ran a truncated list of benchmarks to see how the BC-250 stacks up, as well as several additional benchmarks on the BC-250 alone. Performance here is tough to compare fairly. Even just with CachyOS and Bazzite above, we see large performance differences. And, as will become clear in this section, there were numerous tests that either showed performance issues inconsistently or simply failed to run at all.

Our best point of comparison between the Steam Machine and BC-250 comes in Cyberpunk 2077. Neither machine is capable of achieving a playable frame rate at 4K, but the fully-optimized BC-250 is just 6.7% behind at 1440p. At 1080p, however, the performance drop is 16.1%, exposing perhaps the biggest performance issue with the BC-250.

Forza Horizon 6 also highlights this issue; the CPU in the BC-250 is very weak. It’s not only weak because it’s using the aging Zen 2 architecture, but it also has only six cores (or eight, if you can enable them). It’s such a hurdle because the clock speed is severely limited to just 3.5 GHz, the same as the PS5. We are completely CPU-bound at 1080p and even 1440p in Forza Horizon 6, and then miraculously, at 4K, the larger GPU of the BC-250 is able to take over and actually beat the Steam Machine.

A system so hamstrung by the CPU makes sense in the context of a console. Sony has a performance target, and it makes sense to opt for a weaker CPU and a more powerful GPU. The CPU can reach that performance target. But in the context of a PC where you’re given more options, resolutions, and performance-enhancing features, the limitation of the CPU becomes clear. There’s an obvious performance wall you’ll run into with the BC-250 that no amount of tweaking can solve.

For a clear view of the CPU limitation here, look at the Forza Horizon 6 benchmark above. Running at 1080p with Low graphics is going to induce a CPU bottleneck in most systems, but the gap between GPU render performance and CPU render performance here is massive. According to the game’s benchmark, we were bottlenecked by the CPU entirely throughout the run.

Even at 4K, you can see that the CPU is still a significant influence on performance in this game, showcasing just how unbalanced this system is. Again, that imbalance makes sense for the PS5, but it’s a critical caveat with the BC-250.

In the gallery above, you can browse our other comparative results to get an idea where the BC-250 lands. I’m going to move past comparisons and look at the BC-250 in isolation. An apples-to-apples comparison really isn’t possible (nor fair) with the BC-250. That’s not only due to the wide performance window depending on your specific board and software stack, but also the clear performance limitations of the BC-250 that require certain workloads that wouldn’t make sense with other machines.

Chief among those limitations is VRAM, and memory in general. You have just 16 GB of GDDR6 for the whole system, which is much less of an issue on the PS5 where there’s careful memory management. As you can see in the chart above, I don’t have 4K results for Spider-Man 2 or Doom: The Dark Ages, and that’s due to a lack of VRAM.

In both cases, the games crashed at 4K, but worse, they wouldn’t start back up. I made the mistake of flipping to 4K before turning FSR on, which locked me out of starting the game until I manually edited the settings file prior to launch. 4K is possible on the BC-250, though it has a very narrow performance window considering the VRAM limitations and CPU performance.

Although FSR Performance mode is ideal for 4K (50% scaling, 1080p input resolution), I opted for Balanced to avoid the CPU bottleneck we can see present in other games (you can even see it here in some games, such as Spider-Man 2). However, turning up the input resolution also puts a greater strain on VRAM. You’ll need time and patience to experiment with these more demanding titles to find the ideal balance of settings on the BC-250; of course, if you’re just playing Silksong, none of this matters much.

The VRAM limitation is also relevant for frame generation. With such a narrow memory footprint, you’ll struggle to use frame generation at 4K if you’re already pushing the VRAM to its limits (those buffered frames need to live somewhere). Thankfully, Lossless Scaling is an option on Linux with LSFG-VK, which doesn’t strain your VRAM like in-engine tools.

An important aspect of performance with the BC-250 is cooling. Most governor profiles cap temperature at 80 degrees for multiple reasons. First, the heatsink of the BC-250 is closed on top. You can sit and rip apart the top of the heatsink for direct airflow with a pair of tweezers, but I left the heatsink on my board intact for now, using two Arctic P12 fans to assist with cooling.

Cooling is all the more important with the 40CU unlock and enabling the extra two Zen 2 cores. Stress-testing in Furmark over a 20-minute run, you can see how quickly the GPU throttles from 1,850 MHz back down to 1,500 MHz as it reaches the temperature cap of 80 degrees.

Remember, however, that Furmark is a stress test. I wasn’t thermal throttling in games, with the CPU and GPU settling around 70 degrees in Doom: The Dark Ages. I’ve included CPU and GPU power in the chart above, as well, and you can see that, combined, they rarely poked over 100W. Keep in mind that we’re exclusively looking at GPU and CPU power here, not whole system power. Whole system power can peak above 225W.

The stock heatsink and dual Arctic P12S do a good job keeping the BC-250 chugging along, even with all of the silicon unlocked and a moderate overclock on the GPU. However, Furmark makes it clear that this current iteration of the system can’t sustain its performance over long periods of time. It would take longer for that drop to show up in the most demanding games, unlike in Furmark, where we can see the drop in just 20 minutes. But I plan on revisiting the cooling solution in this BC-250 build. Maybe I can even raise the temperature limit closer to the 100-degree TJmax.

The bad and the ugly of BC-250 gaming

Although the BC-250 offers compelling performance for the price, I’d be remiss if I didn’t highlight the numerous quirks I ran into while testing. There are performance issues and limitations with the board that you can explain with hardware, and further compatibility issues that you can explain away with Linux. Then, there’s everything else: the weird bugs, quirks, and oddities that pop up when running a largely community-developed software stack on unofficial hardware that wasn’t built for this purpose.

The above image of Resident Evil 9 is a microcosm of what I’m talking about. The RE Engine is remarkably scalable, and that was on full display with my BC-250 testing. Requiem offered excellent performance, even all the way up to 4K. It didn’t feel like I was compromising much of anything with the BC-250. But then I turned on the “hair strands” setting, and the result is what you can see above.

No, it’s not due to the CU unlock, any overclock, or even the overlay you can see. It’s just something with this set of hardware, this software stack, and the hair strands setting in Resident Evil Requiem.

Similarly, in Doom: The Dark Ages, any resolution change I would apply necessitated a restart of the game. Otherwise, I’d get the ghostly streaking you can see in the image above. On one of these reboots, the game suddenly stopped rendering reflective surfaces, resulting in the strange black voids you can see below.

This isn’t a criticism of the BC-250, and certainly not of the remarkable work of the passionate developers and enthusiasts who’ve created fixes and workarounds for the hardware. The fact that this board boots at all and runs games is a minor miracle. The context of what the board is, however, is important.

You will, inevitably, run into strange issues that aren’t documented anywhere. These are two examples, but I also ran into strange problems elsewhere. The widely used MangoHUD overlay, for example, didn’t pull in my GPU’s clock speed correctly after an update, even after ensuring I applied the community fix through the GPU governor to map the reporting correctly. And once you add external devices, compatibility gets even more complex. The board doesn’t have Bluetooth or Wi-Fi, for example, and an external adapter should work (this UGreen Wi-Fi 6 adapter I purchased does), but it’s just as likely that a driver for another adapter doesn’t work or isn’t available.

I don’t have an issue with these quirks, but the BC-250 also isn’t my primary gaming machine. You should just be aware of them. And, if you’re going to invest in a BC-250 build of your own, be ready to encounter some strange issues that you might not be able to easily troubleshoot.

What’s next?

The BC-250 is a project, and like any good project, it isn’t done here. Now that I’ve messed around with the configuration, tried out different distros, got the critical mods working, and measured performance, I want to actually use the BC-250 long-term. Maybe I can find some additional optimization steps I can take, or workarounds for some of the strange issues that I noticed during testing. Regardless of what it is, I’m confident that I’ll mess around with the BC-250 more outside of just playing games on it.

My clear next step is to work on cooling. I kept things conservative here in order to get valid data in a timely manner, but I want to dig deeper into what I can do on the thermal front, not only to raise the temperature limit, but also to push the GPU overclock further. That may involve some CU tinkering, as well; if I can get similar performance at 36 CUs and better thermal headroom, I may be able to push higher overall performance.

China has started low-volume production of domestically developed immersion DUV lithography machines, with around five systems planned for this year and roughly 20 in 2027, according to a report from July 27, which wiped roughly $44 billion off ASML's market value.

The manufacturer was named as Shanghai Aishengna Electronic Technology Group by Reuters the following day, a state-owned company established in August 2023 with 7 billion yuan (around $1 billion) in registered capital that absorbed engineering teams from Huawei-affiliated startup Yuliangsheng and state scanner maker SMEE. The first units are due at SMIC, Hua Hong, and CXMT this year for production-line validation rather than volume output, but the machines are far from matching ASML's models and still require further testing.

Five machines represent about 3.8% of the roughly 130 immersion systems ASML deploys in a typical year (a class of lithography machines that put a super thin layer of liquid over the wafer during processing), with the European giant holding an estimated 98.7% of the total immersion market. The Chinese tool reportedly prints 28nm-class features in a single exposure and reaches 7nm, and theoretically 5nm, through multipatterning, the same route SMIC already runs on its installed ASML fleet. Neither company has confirmed the report, no machine has been shown publicly, and no throughput or overlay figures have been disclosed, against the 330 wafers per hour and 2.5nm overlay of ASML's current flagship immersion tools.

SMIC’s scanner

SMIC has been running a domestic immersion scanner, developed under the codename Mount Everest, since September last year, when the Financial Times reported that China's largest foundry had begun testing the Yuliangsheng tool with production-line integration targeted from 2027 after qualification.

FT compared the machine against ASML's Twinscan NXT:1950i, a system that entered the market in 2008, which puts the design roughly a decade and a half behind the tools ASML sells today. Yuliangsheng, founded in Shanghai in 2022 with 1 billion yuan (around $149 million) in registered capital, is understood to have delivered three lithography machines to fabs for testing by late last year, but this hasn’t been officially confirmed.

Many of the critical components needed for the machines are still imported from Japan, and delays at those local suppliers are what have capped 2026 output at around five units. The 2027 target of 20 machines is therefore an ambitious target that assumes a domestic component base that hasn't been established yet, and the imported parts remain within reach of any future export-control round.

18% litho localization

SMEE's most advanced shipping product remains the SSA600 series, a 90nm-class dry ArF scanner that was in mass production as of May last year. The 28nm-capable SSA/800 immersion tool the company announced in 2023 has never been deployed, and a state-media claim of its successful development was deleted shortly after publication. In December last year, SMEE won a roughly RMB 110 million ($16 million) single-source government contract for a KrF scanner specified at 110nm resolution and 15nm overlay, a useful indicator of where its production-grade capability is at the moment.

Domestic equipment took 35% of Chinese fab purchases in 2025, beating Beijing's 30% target and up from about 10% three years earlier, according to figures from China's semiconductor industry association. Etch and thin-film deposition passed 40% localization, and metrology reached 25%, while lithography managed just 18%, most of it in trailing-edge and packaging tools. From the end of 2025, new fab capacity additions are required to source at least half their equipment domestically, a mandate that guarantees the new scanners a customer base, whatever their specs turn out to be.

Etch, deposition, and everything else

Naura Technology became the world's fifth-largest chip equipment maker by 2025 sales, trailing only ASML, Applied Materials, Lam Research, and Tokyo Electron, and moving ahead of KLA. The company booked RMB 27.14 billion ($4 billion USD) in revenue in the first three quarters of 2025 against RMB 6.05 billion ($589 million USD) for all of 2020, holds an order backlog stretching into 2027, and has started developing lithography tools for the first time. AMEC grew revenue and net profit by more than 30% in 2025, while cleaning specialist ACM Research posted $901.3 million for fiscal 2025 and guided to as much as $1.18 billion for 2026.

SiCarrier, the Shenzhen firm widely linked to Huawei, debuted around 30 tools at SEMICON China in March 2025, spanning etch, deposition, metrology, and test, and was reportedly valued at RMB 65 billion ($9.63 billion USD) by September 2025 with more than RMB 10 billion ($1.48 billion USD) in orders. The U.S. added it to the Entity List in December 2024.

The sector's own leadership is less triumphant than the numbers suggest. In March, SMIC co-founder Wang Yangyuan and the heads of YMTC, Naura, and EDA firm Empyrean jointly described China's tool industry as "small, fragmented, and weak" and called for national consolidation, with Big Fund III's $47.5 billion being redirected toward lithography and EDA. The Aishengna venture, which merged the Yuliangsheng and SMEE teams into one state-owned vehicle, looks like the first product of that pressure to consolidate. China spent a record $49.5 billion on wafer fab equipment in 2024, per SEMI, and remains the world's largest buyer through 2027, even after a pullback in 2025.

EUV lithography

A Reuters investigation in December 2025, dubbed China’s “Manhattan Project,” described an operational prototype EUV light-source machine in a high-security Shenzhen lab, completed in early 2025, that generates EUV photons but hasn't yet exposed a wafer. More than 3,000 researchers are said to work across the program, with Huawei playing the coordinating role and SMEE handling system integration.

Two teams are chasing the light source: one led by Lin Nan, a Beihang University professor who worked at ASML from 2015 to 2021, has a solid-state laser-produced-plasma design running at 3.42% conversion efficiency against the roughly 5.5% commercial viability required, while Zhao Yongpeng's laser-assisted discharge plasma group at Harbin Institute of Technology has reached around 100W of EUV output against the roughly 600W that ASML's production sources deliver.

Beijing's target is chip output from the machine by 2028, with Reuters' sources calling 2030 more realistic. A separate strand of reporting described a reverse-engineered prototype built around an intercepted Cymer light source that has likewise produced nothing. Earlier claims of a Huawei EUV trial production in 2025 and mass production in 2026, which circulated via Chinese media in March 2025, were never confirmed by any primary source. Tsinghua University's accelerator-based SSMB concept, which would need a synchrotron of a staggering 100 to 150 meters in circumference, remains an academic project.

Export controls

The MATCH Act, introduced in the House and Senate in early April, would ban not only sales of immersion DUV tools to SMIC, Huawei, Hua Hong, CXMT, and YMTC but also the servicing of machines already installed, and would give the Netherlands and Japan 150 days to align.

At this stage, it remains a bill, not a law, but servicing restrictions would strike directly at the installed ASML base that produces every advanced chip China currently makes, including SMIC's N+3 node in Huawei's Kirin 9030. Chinese fabs have been preparing for exactly that scenario by using third-party engineers and gray-market parts to Frankenstein older ASML machines.

ASML's China exposure is already shrinking on schedule, with the country representing 20% of system sales compared to 41% in 2024 and 33% last year, even as the company raised full-year guidance to €43 to €45 billion in July. Likewise, Applied Materials expects to lose $600 to $710 million in China revenue this fiscal year.

Ultimately, three markers will indicate whether China’s domestic DUV program is a legitimate rival or yet more state-sanctioned hot air. The main one would be validated production wafers from an Aishengna tool at SMIC, Hua Hong, or CXMT with published throughput and yield, followed by delivery of anything close to the 20 machines planned for 2027, and a first exposed wafer from the Shenzhen EUV prototype before the 2028 target set by Beijing.

The requirements of AI clusters have made optical interconnections practical for scale-out connectivity, but as bandwidth needs increase, optical connectivity is becoming viable for scale-up connections as well. As a result, the industry is moving optical interfaces closer to CPUs and GPUs, from the front-panel transceiver to the package itself through co-packaged optics (CPO) — and eventually directly into the processor package.

Optical connectivity has been used for decades, since electrical links cannot efficiently and reliably transmit data over long distances at high data transfer rates. But the cost and complexity of optical components limited their use to long-reach connections.

Today, the importance of CPO is rising: Electrical interconnects are no longer scaling as quickly as AI processors, and feeding thousands of accelerators within a data center requires an exponential increase in communication bandwidth. In a traditional optical networking architecture, the processor or switch ASIC communicates electrically with a pluggable optical transceiver located at the front panel of a server or switch. As signaling speeds climb to 200 – 400 Gb/s per lane and beyond, however, transmitting electrical signals over long copper PCB traces on a motherboard becomes increasingly inefficient, causing higher insertion loss, greater power consumption, and tighter signal integrity requirements.

While technically possible, it demands the use of better materials, re-timers, complex compensation processing, and equalization circuitry, which increases the cost of server infrastructure and its power consumption. CPO moves optical engines next to the processor or switch ASIC to shorten the electrical path before signals are converted into light, which means lower power consumption per transmitted bit, increased bandwidth density, and predictable scalability. As a result, CPO is increasingly viewed as a necessary technology for next-generation AI infrastructure.

Because AI is viewed as a major megatrend, CPO is set to become ubiquitous; there are dozens of companies working in the CPO ecosystem, including foundries, OSATs, optical I/O startups, laser manufacturers, fiber suppliers, packaging houses, and networking vendors.

As there are so many vendors pursuing different goals with different strategies, for this story, we are going to limit ourselves only to companies that actually produce things and whose roadmaps reflect their technological capabilities. So far, only four foundries have publicly articulated meaningful CPO manufacturing strategies: Intel Foundry, GlobalFoundries, Samsung Foundry, and TSMC.

The four companies each represent four different CPO strategies and have very distinct plans for the future, so their visions and capabilities may not be directly comparable. Nonetheless, reviewing their offerings gives us an idea about where the industry is going from the perspective of actual foundries.

TSMC: COUPE for everything

TSMC has historically been absent from the optical connectivity market as a product supplier. But having worked on silicon photonics for many years, it now has the broadest ecosystem and manufacturing roadmap with its Compact Universal Photonic Engine (COUPE).

TSMC's silicon photonics technology roadmap currently has three stages that span from a 1.6 Tbps optical engine with conventional pluggable optics to a 12.8 Tbps optical engine located within a processor package. The COUPE roadmap is tightly coupled with the company's advanced packaging technologies and the evolution of the company's micro-ring modulators (MRMs) that adjust light and directly impact performance. As a result, several TSMC customers (e.g., Nvidia) plot their silicon photonics strategies around the evolution of COUPE.

The first phase of the roadmap — called COUPE on PCB — relies on a COUPE that bonds a 65nm electronic integrated circuit (EIC) with a photonic integrated circuit (PIC) using the company's SoIC-X bonding technology. The initial implementation targets OSFP (Octal Small Form-factor Pluggable) optical modules and delivers 1.6 Tbps of bandwidth (2x the throughput of copper Ethernet solutions, along with 2x the power efficiency). Therefore, the first-gen COUPE is out of the scope of this article. TSMC says the SoIC-X interface features very low impedance and enables lower power consumption at high signaling speeds.

The second generation — dubbed COUPE on substrate — marks TSMC's transition from conventional pluggable optics to co-packaged optics (CPO). In this stage, COUPE is integrated with the company's chip-on-wafer-on-substrate (CoWoS) advanced packaging technology and co-packaged with a network switch ASIC. This architecture enables motherboard-level optical interconnects with aggregate bandwidth up to 6.4 Tbps, 2x power efficiency, and 10x lower latency than existing pluggable solutions, which is fantastic for a variety of applications, such as NVLink, Ethernet, and InfiniBand switches.

The third phase — called COUPE on interposer — pushes silicon photonics even closer to compute dies: A 12.8 Tbps optical engine is integrated directly into the processor package to enable ultimate bandwidth and scalability. Beyond doubling bandwidth again, the company expects the architecture to offer 5x power efficiency and 20x lower latency than today's pluggable solutions. That will make it particularly attractive for hyperscalers that build clusters with thousands of accelerators. Unfortunately, TSMC characterizes this phase as exploratory and has not disclosed its commercialization timeline.

The main agenda of COUPE is to move the optical engine as close to compute as possible. There is another dimension in TSMC's silicon photonics strategy, however: the evolution of the photonic devices themselves, the MRMs integrated into PICs. The company plans to bring the world's first 200 Gbps/lane (wavelength) micro-ring modulator into production in 2026 and then continue scaling the technology with 400 Gb/s MRMs, additional optical wavelengths, and denser fiber-array integration. This evolution is expected to increase COUPE’s bandwidth density from 0.5 Tb/s/mm in 2026 to 4 Tb/s/mm by 2030, providing an 8x improvement over four years.

It is noteworthy that TSMC presents the MRM roadmap separately from the evolution of COUPE packaging, which suggests that advances in micro-ring modulators represent an independent technology roadmap for the photonic integrated circuit (PIC), rather than being tied to a specific packaging generation. This potentially means that future COUPE products could adopt newer generations of MRMs regardless of whether the optical engine is mounted on a PCB, package substrate, or silicon interposer — although the latter will probably deliver the greatest system-level benefits by minimizing the electrical distance between compute dies and optical interfaces.

Intel: Optics for CPUs, GPUs, DPUs, and accelerators

Intel has been shipping various products with optical interconnections for decades and even attached its silicon photonics solutions to Xeon and Xeon Phi processors in the mid-2010s. Today, Intel's public CPO roadmap is less explicit than TSMC's, but its direction is fairly clear: move optical I/O directly next to CPUs, GPUs, accelerators, and eventually other compute chiplets. Meanwhile, so far, Intel has not unveiled plans to use its CPO technology for switches.

Intel's CPO strategy is largely focused on its Optical Compute Interconnect (OCI) chiplet, which is a self-contained optical I/O subsystem packing both EIC and PIC that can be co-packaged with any compute device using a PCIe interface to enable high-performance optical connectivity. Intel demonstrated the first OCI in 2024. That prototype implementation used 64 PCIe 5.0 lanes at 32 GT/s in each direction to connect to the host and provided 4 Tbps of bidirectional optical bandwidth over eight fiber pairs over a distance of up to 100 meters. Each fiber carried eight DWDM wavelengths spaced at 200 GHz, and every wavelength (lane) transported about 32 Gbps (8 FPs × 8 WLs × 32 Gbps = 2,048 Gbps in each direction).

The 2024 OCI implementation is good for testing the technology, but with rather slow 32 Gbps lanes, it has not been adopted commercially. Meanwhile, this technology has already been proven and demonstrated. Intel is currently working on its next-generation OCI with 200G/lane PICs to support 800 Gbps and 1.6 Tbps applications, though it is unclear when it is set to be available, as Intel has not yet disclosed an equivalent to TSMC's MRM roadmap.

It should be noted that future OCI implementations supporting bandwidth of 10s of terabits per second could interface with compute dies using next-generation PCIe 6.0 interfaces or even native die-to-die UCIe links when integrated into commercial products. Furthermore, Intel can naturally integrate OCI chiplets using its advanced packaging technologies to ensure high performance and low power.

As noted above, Intel's focus with OCI has always been its integration with CPUs, GPUs, DPUs, accelerators, or other compute devices, but not necessarily switches. It remains to be seen whether Intel's next-generation AI hardware roadmap will include switching silicon, but for now, it does not seem that the company is targeting optical switches with its OCI chiplets. Since OCI is protocol-agnostic, limiting it to compute devices seems like an artificial limitation, though we have little indication about Intel's reasoning behind the decision.

Samsung Foundry: Addressing everything

Samsung Foundry's silicon photonics strategy is arguably the most comprehensive among leading foundries. Unlike Intel, whose CPO roadmap is focused on its OCI chiplet for integration with compute devices, or TSMC, whose COUPE optical engine is another major ingredient of its foundry platform, Samsung intends to offer all types of optical connectivity devices, starting from pluggable transceivers in 2026, to switch CPO later on, and all the way to optical engines on the interposer of a processor package in 2030. Unfortunately, Samsung does not publicly provide a lot of information about its plans, so our main source of information will be SF's slide from a conference published by SemiVision.

This year, Samsung Foundry intends to offer a merchant PIC platform that relies on an EIC and a PIC mounted side by side on a PCB for conventional pluggable optics. The PIC will support 100 Gbps-class optical interfaces using CWDM technology, which is good enough for traditional pluggable optical transceivers (though Samsung does not specify the exact implementation), so there's no indication of CPO here.

In 2027, Samsung Foundry intends to catch up with TSMC's first-gen COUPE and offer an optical engine that stacks an EIC on top of a PIC using thermo-compression bonding (TCB). Samsung expects energy efficiency of this generation to improve from approximately 10 pJ/bit for its initial PIC platform to 5 pJ/bit, though Samsung has said nothing about bandwidth or latency. Samsung's TCB-based OE seems to be an intermediate product between merchant PICs and true CPO, so it will generally address onboard optics and pluggable transceivers.

By 2028, SF intends to move optical engines to the substrate of Ethernet or InfiniBand switch ASICs, which will be its first true CPO. The company intends to adopt hybrid copper bonding (HCB) with 10 µm pitches for its OEs to improve bandwidth density. Based on the slide from the roadmap, to address next-generation switches, Samsung is poised to increase optical lane speeds from 100 Gbps to 200 Gbps and ultimately 400 Gbps, although the company does not disclose when exactly each speed bin will be introduced (though it looks like 400 Gbps will come in 2029 – 2030) as well as the underlying modulator technology or other device-level details behind this scaling.

In 2029, Samsung Foundry will finally integrate its optical engine on an interposer next to CPU/GPU/XPU or other compute device, which will reduce energy consumption to 2 pJ/bit while providing extremely high bandwidth. Samsung calls this 'CPO Turnkey,' which implies that such integration will require its own packaging technologies. The next step in Samsung's roadmap is called 'next-generation CPO Turnkey,' and it integrates virtually the entire optical subsystem — including lasers — alongside compute and memory, which will be its ultimate CPO offering expected by 2030 and onwards.

While Samsung Foundry's ultimate goal to offer highly integrated turnkey CPO solutions is clear, the company also intends to offer two merchant platforms for pluggable optical transceivers, perhaps to de-risk development of its future products and to capitalize on the high demand for optical connectivity that exists today and will continue going forward.

GlobalFoundries: A bespoke vendor-agnostic OCI-MSA CPO platform

Unlike Intel Foundry, Samsung Foundry, and TSMC, GlobalFoundries does not produce or intend to produce AI processors, switch ASICs, or advanced packages. Instead, it aims to become a merchant co-packaged optics provider that will produce and sell bespoke CPO solutions that enable optical connectivity (including OCI MSA connectivity) for processors made by other chipmakers.

GF's silicon photonics effort dates back to the IBM Microelectronics acquisition in 2015, which brought IBM's silicon photonics technology and engineering teams into the company. Over the years, GlobalFoundries has expanded its silicon photonics capabilities into what eventually became the GF Fotonix platform and, more recently, the company acquired AMF and InfiniLink to further strengthen its production and design capabilities.

The key element of GlobalFoundries' CPO strategy is its Silicon photonics Co-packaged Advanced Light Engine (SCALE) platform that combines photonic IP, advanced packaging technologies, and a reference optical engine architecture that includes EIC and PIC. Unlike Intel's OCI chiplet, SCALE allows GF's clients to customize optical engines in accordance with their needs and have them manufactured by GF.

Under the program, GlobalFoundries manufactures the PIC and EIC using its own process technologies and then packages them into an OCI MSA-compliant optical engine using its methods. If the EIC requires a leading-edge node that GF does not have, it could instead be fabricated by another foundry and then integrated by GF. Customers then co-package the optical engine alongside their own switch ASICs or AI accelerators.

For now, SCALE supports both CWDM and DWDM transmission using qualified 50 Gbps and 100 Gbps MRMs, integrated photodiodes, and coupled-ring resonators. The platform has demonstrated bidirectional operation with up to 16 DWDM lanes per fiber, which theoretically opens doors to optical links with up to 1.6 Tb/s of bandwidth per direction. On the integration side of things, it supports advanced 2.5D and 3D integration using TSVs and copper bonding with pitches ranging from 110 µm to below 45 µm, which is good enough for integration using CoWoS-S and CoWoS-L technologies.

Just like Intel with its OCI, GlobalFoundries does not necessarily tie its SCALE CPO customers to its silicon or packaging technologies. Furthermore, the company allows its clients to customize their optical engines while retaining compatibility with the OCI-MSA requirements.

The future of CPO

Co-packaged optics (CPO) is set to become a key technology for next-generation AI infrastructure as conventional electrical interconnects struggle to keep pace with the bandwidth demands of rapidly developing AI processors.

Among foundries, TSMC, Intel, Samsung Foundry, and GlobalFoundries have each developed distinct CPO strategies that range from merchant optical engines to optical I/O chiplets and vertically integrated CPO platforms.

Given the different capabilities of the contract chipmakers, their roadmaps differ significantly in both scope and implementation, with some companies trying to lock in customers with a proprietary platform and others offering different degrees of freedom.

However, they all share the same objective: move optical interfaces progressively closer to compute dies to reduce power consumption, increase bandwidth density, and lower latency for the next generation of AI systems that will require considerably more bandwidth than today's clusters.

In the 3D printing community, there’s a common saying: buying a 3D printer is easy—learning modeling, mesh repair, and slicer settings is the real challenge.

While AI-powered 3D generation has made it possible to create detailed models in minutes, turning those models into successful prints still requires significant technical work. From mesh repair and model splitting to print optimization and multi-color workflow management, many AI-generated models never make it beyond the screen.

Hi3D was built to close that gap between AI creation and physical manufacturing. Over the past year, the company has expanded beyond AI model generation, developing an end-to-end workflow designed specifically for 3D printing.

Today, Hi3D has established partnerships across the digital fabrication ecosystem, including Creality, MakerWorld within the Bambu Lab ecosystem, and xTool. These collaborations enable deeper integrations for printable model generation, AMS multi-color workflows, enhanced 3MF output, and broader digital manufacturing applications.

With its anniversary release, Hi3D takes another step forward. Automated part separation, multi-color optimization, color cleanup, material-saving algorithms, intelligent model orientation, and print parameter generation are now unified into a single AI-driven workflow.

The result is simple: tasks that once required multiple software tools and hours of manual work can now be completed automatically—helping creators move from image to printable object faster than ever before.

Hours to 2 Minutes: Auto Character Split with Built-In Print-Ready Tolerances

For makers printing large models—or working with smaller build volumes such as the A1 mini—model splitting is often one of the most time-consuming steps. Traditional workflows require manually cutting meshes, creating connection structures, and adjusting tolerances, often resulting in assembly issues after printing.

Hi3D’s Auto Character Split automates the entire process:

1. Intelligent Topology Recognition – Automatically identifies heads, torsos, limbs, and other structural components, generating optimized printable segments.
2. Watertight Mesh Generation – Every separated part is exported as a closed, watertight mesh ready for slicing and printing.
3. One-Click Joint Creation – Users can instantly add snap-fit connectors, mortise-and-tenon structures, or articulated ball joints for movable figures.
4. AI-Optimized Assembly Tolerances – Mechanical clearances are automatically calibrated for FDM printing, enabling reliable assembly directly off the build plate with minimal post-processing.

Tasks that previously required hours of manual modeling and adjustment can now be completed in just a few minutes.

Deep Integration with the Bambu/AMS Ecosystem: From AI Model to Print-Ready 3MF

Multi-color printing often requires extensive manual color painting and parameter adjustments, especially for complex AI-generated models. Color data can be lost during export, and preparing a print-ready file typically involves multiple software steps.

Hi3D streamlines this process through deep integration with the Bambu Lab ecosystem, featuring an official filament library, automatic color mapping, and enhanced 3MF generation.

Once a model is created, Hi3D automatically maps on-screen colors to official Bambu Lab filament profiles and exports an optimized 3MF file containing print settings such as temperatures, layer heights, infill density, wall parameters, and support configurations.

Instead of manually preparing files in a slicer, users can send the generated 3MF directly to Bambu Studio or OrcaSlicer and start printing immediately.

Reduce Multi-Color Waste by Up to 50% with AI Color Cleanup

For users of Bambu AMS and other multi-material systems, excessive filament purging remains one of the biggest challenges in multi-color printing. AI-generated textures often contain tiny color fragments and gradient noise, triggering unnecessary filament swaps that increase print time and material waste.

Hi3D addresses this with its Color Cleanup algorithm:

• Noise-Aware Color Merging – Automatically detects and removes insignificant color fragments generated by AI textures.
• Reduced Filament Swaps – Minimizes unnecessary color changes during slicing.
• Lower Cost, Faster Prints – Reduces purge waste by up to 50% while improving print efficiency by 30–50%.

Smart Build Plate Layout for Higher Print Success Rates

Model orientation is often the deciding factor in print quality and reliability. Hi3D’s Smart Build Plate Layout system automatically analyzes geometry, center of gravity, and support requirements to optimize model placement.

• Surface-First Mode – Prioritizes visible surfaces to reduce support marks and post-processing.
• Eco-Support Mode – Minimizes support usage while maximizing bed adhesion and print stability.

By automating decisions that traditionally rely on maker experience, Hi3D helps users achieve better print quality with less trial and error.

Bridging the Gap: From Beginner-Friendly Creation to Advanced Manufacturing

Beyond advanced tools for model splitting, multi-color optimization, and print preparation, Hi3D also lowers the barrier to entry through its Maker Templates. Users can upload a photo to generate printable figurines, pet models, or custom keycaps that are automatically optimized for 3D printing.

With its anniversary release, Hi3D is expanding beyond AI model generation into a complete AI-powered workflow built specifically for physical manufacturing. By combining AI creation, print optimization, and hardware-aware automation in a single platform, Hi3D helps creators move from idea to finished object with significantly less manual work.

As AI 3D technology continues to mature, the industry is shifting from simply generating models to generating manufacturing-ready models. Hi3D’s latest update represents another step toward that future, making 3D printing more accessible for beginners while providing greater efficiency for experienced makers.

Ready to experience a smoother workflow from AI-generated models to successful 3D prints? Visit Hi3D.ai and see how AI-powered creation, optimization, and printing come together in a single platform.

New users can receive 300 free Hi3D credits through the link below and experience the complete AI-to-3D-print workflow for themselves—from concept generation to printable 3MF files.

Get started here：Hi3D.ai

AI hardware has been a pretty simple game for years: Whose GPU has the most FLOPS, the most memory, or the fastest clock? But as hyperscalers want more performance from the same size of facilities, who controls the fabric between the chips is becoming another question frequently asked – in large part because it can dictate whether AI hardware follows the principles of Moore’s law that have held for decades, or breaks out into a new paradigm.

“Moore's Law is deader than a doornail, absolutely just toast,” said Nick Harris, chief executive of photonics firm Lightmatter, in an interview with Tom's Hardware Premium. The way to make a processor faster used to be to pack in more silicon, but there is a physical limit to how big a single chip can be – so performance now depends on networking dozens, then hundreds, of chips together. “Ultimately, networking is the future of computing,” Harris said. “The performance of these AI systems is completely hamstrung and bottlenecked by your ability to achieve low latency and very, very high bandwidth.”

It all comes down to scale-up and scale-out. Scale-up is the ultra-low-latency interconnect inside a single server, rack, or pod that makes many accelerators behave like one giant machine. Scale-out is the wider network, combining those machines into clusters. There is a third factor, called scale-across, that links whole data centers together. As Polina Bayvel, professor of optical communications and networks at University College London, told us, the hyperscalers are "on a drug which says that the more you put in, the better is the answer" – and between 72 and 144 GPUs now go into a single scale-up rack before it needs to reach outward.

Copper was sufficient within racks for years, but it has hit a wall, and a supply shortage. “Your arm reach, my arm reach, is about two metres – the copper cable is a little shorter than that,” Harris explained, “and we’ve already hit the limit.” Thus, optical interconnects are becoming more important, and moving from rack-to-rack cabling toward the accelerator package itself. Earlier this month, Elon Musk made moves to purchase Mesh Optical, as part of TeraFab and SpaceX's ongoing AI ambitions.

Moving light towards the chip

Today, optical signals usually arrive through pluggable transceivers, the standard modules that sit around 18 inches from the switch. The next step is near-package optics, which brings that down to roughly six inches. After that comes co-packaged optics, or CPO, where optical chiplets sit around the GPU or switch. The most ambitious version puts the optics on an interposer beneath the chip itself. “As you progress, you increase the speed and you reduce the energy consumption with each one of those leaps,” said Harris.

For now, the industry’s attention is on the step before the really radical one. “I think 2027 and 2028 are going to be very, very big years for near-package optics,” Harris said. He describes it as the test bed: the last stop before the optical transceiver effectively ships as part of the accelerator or switch, rather than as a separate component bolted on nearby.

Lightmatter is already building CPO parts at TSMC and GlobalFoundries, which it expects to ship in 2028. At the same time, it is working with customers on the more integrated interposer approach – the one for companies that, in Harris’s words, “realise they’d like to have an advantage in the market.”

The reason is power. Bayvel says about 20 percent of a data center’s energy goes into networking: The business of connecting GPUs and CPUs across racks, rooms and data centres. The other 80 per cent is consumed by the GPUs themselves. But she is clear-eyed about what happens to any savings. “Whatever energy you save through optics isn’t going to be there for saving the world,” she said. “It’s to stick another 1,000 GPUs in.”

Warring standards

Nvidia has a vertically integrated answer spanning both domains, from NVLink and NVSwitch for scale-up to Spectrum-X Ethernet and InfiniBand for scale-out. The rest of the industry, including AMD, Broadcom, Cisco, Arista, Marvell, Meta, Microsoft and OpenAI, is trying to prise that open through UALink, Ultra Ethernet and a new optical specification.

The sense that a standards war is building is becoming obvious. At Computex, AMD showed its Helios MI455X platform, a 72-GPU rack meant to rival Nvidia's Vera Rubin NVL72. But its scale-up fabric runs UALink-over-Ethernet rather than native UALink – a stopgap forced by the fact that dedicated UALink switching silicon from partners such as Astera Labs and Marvell was not ready in time. Engineering samples are due in the second half of 2026, with mass production slipping to Q2 2027, while AMD's next-generation MI500-series rack is expected to follow quickly.

Bayvel says the wider contest is one between CPO and linear-drive pluggable optics (LPO). CPO integrates lasers and optics alongside the processing and is probably more power-efficient, “but probably less reliable –so if your laser fails, you need to replace the whole board.” LPO keeps things in conventional pluggable slots and is more serviceable. “There’ll be a brave person who will bet their house on which will win,” she said. She guesses that they coexist, split by application, with a rough 60/40 lean towards CPO.

The laser bottleneck

The problem is that silicon can do almost everything except the one thing this industry increasingly needs it to do: shine.

Silicon is cheap, abundant, and brilliant for electronics. It is why the modern chip industry exists. But it is terrible at emitting light. “Silicon doesn’t emit light at all — that’s a big problem,” said Frederic Gardes, professor of silicon photonics at the University of Southampton, in an interview with Tom’s Hardware Premium.

For decades, the industry has worked around that by using so-called III-V materials such as indium phosphide and gallium arsenide, which are much better at producing light. But that fix brings its own problem. Those materials sit in a much tighter, more geopolitically exposed supply chain, with China controlling around 80 percent of supply. Getting lasers onto silicon is, Gardes said, “one of the key problems” the field now has to solve.

But it’s also where the money is. “Half of the revenue opportunity for this industry is lasers,” Harris said. “It’s a freaking power supply, but it turns out that it’s half of the revenue opportunity.” The irony is that the bit everyone needs most is also the bit that may prove most fragile. Gardes calls lasers “the weakest link.”

That weakness is already showing up in the supply chain. Laser makers Lumentum and Coherent are booked out for years. And the industry is starting to standardise. In March, AMD, Broadcom, Meta, Microsoft, Nvidia and OpenAI founded the Optical Compute Interconnect (OCI) Multi-Source Agreement, a hyperscaler-led effort to define a common optical physical layer for scale-up — one that can carry both NVLink and UALink, starting at 200Gbps per direction and scaling towards 3.2Tbps per fibre.

Whichever route wins, Bayvel worries the industry is fixating on the data center while neglecting the networks that must carry all this AI-generated traffic across land, sea and space. “Really, nobody’s looking at that,” she said, “and I think that's going to be a big problem down the line.”

The USB ecosystem is in the midst of another transition that will affect how laptops, desktops, storage devices, displays, and peripherals connect in the second half of the decade.

USB4 Version 2.0, Thunderbolt 5, and a refreshed certification program converge around higher throughput, expanded power delivery, and an attempt to simplify a standard that has accumulated layers of optionality over nearly three decades, which we've explained in our USB decoded explainer.

So, what's next? In 2026, USB4 Version 2.0 and Thunderbolt 5 are now actively being implemented in the premium laptop and desktop segments, shifting from the long-running 20 Gbps and 40 Gbps era toward links that can deliver 80 Gbps bidirectional bandwidth and 120 Gbps asymmetric modes for display-heavy workloads.

From 12 Mbps to 80 Gbps

USB began in the mid-1990s to replace a sprawl of legacy connectors — serial, parallel, PS/2 — with a single, self-configuring interface. USB 1.0 launched in 1996 at just 12 Mbps, fast enough for keyboards, mice, and early webcams.

The 2000 release of USB 2.0 raised that to 480 Mbps, enabling external optical drives and the first wave of consumer flash storage. But it was USB 3.0 in 2008 that marked the transition to high-bandwidth, general-purpose peripheral buses, pushing 5 Gbps over a new SuperSpeed signaling layer. USB 3.1 and 3.2 followed, expanding bandwidth to 10 Gbps and then 20 Gbps with dual-lane signaling, but also introducing a tangle of naming conventions that made it difficult for users to identify what a port or cable could actually do.

Throughout this evolution, USB retained backward compatibility by design. A USB 2.0 flash drive could still work when plugged into a USB 3.2 Gen 2x2 port, and a modern USB-C charger could power an old USB 3.0 hard drive. This interoperability helped USB become the default connector for consumer computing. That said, it also left the standard fragmented beneath the surface. Features such as power delivery, alternate modes for video output, and PCIe tunneling were added incrementally, and not all devices implemented them uniformly.

The introduction of USB-C in 2014 began to consolidate physical connectors, and the debut of USB4 in 2019 marked the start of a new architecture focused on integrated high-speed transport. But many of USB4’s promises, such as 40 Gbps throughput and universal power, depended on how thoroughly a given device implemented the spec. That complexity is still being worked through, even as USB4 v2 and Thunderbolt 5 push bandwidth and capability well beyond what USB 3.x ever attempted.

The state of USB4

USB4 has been positioned as the unifying successor to the fragmented USB 3.x family, but the reality of this is more nuanced. USB4 is a modular architecture built atop the Thunderbolt 3 transport specification that Intel contributed to the USB Promoter Group. The standard defines a tunnel capable of carrying DisplayPort, PCI Express, and USB packets simultaneously, distributing bandwidth dynamically across workloads. All USB4 ports use USB-C as the physical connector and require USB Power Delivery for negotiation, but beyond that baseline, implementations vary widely.

Most more budget-conscious laptops and PCs ship with USB4 20 Gbps rather than the full 40 Gbps mode. Many omit PCIe tunneling, which restricts the use of external NVMe enclosures, capture cards that require direct PCIe links, and eGPU housings. Others support only single-lane DisplayPort tunneling, capping multi-monitor configurations even when total bandwidth appears sufficient.

Thunderbolt 4 remains the most complete expression of USB4 Version 1.0, because it mandates 40 Gbps operation, PCIe tunneling with at least 32 Gbps of sustained throughput, dual 4K displays, DMA protection, and 15W of minimum port power. Intel platforms consistently meet this bar. Meanwhile, AMD systems vary by OEM and chipset, with only a subset of designs offering full USB4 40 Gbps with PCIe tunneling.

This implementation variability reflects the flexibility of USB4’s architecture. The specification allows device makers to scale features based on cost and power constraints, especially in thin-and-light systems. For users, however, the USB4 label alone does not guarantee any particular performance characteristic without checking controller documentation or certification badges.

USB-C’s role has grown alongside this transition. The connector now consolidates power, data, and display signaling, and it is the required physical interface for USB4, Thunderbolt 3, Thunderbolt 4, and Thunderbolt 5. With Power Delivery 3.1, USB-C can negotiate up to 240W via 48V Extended Power Range modes across fixed 28V, 36V, and 48V power profiles. A single cable can power a high-end notebook, drive a high-resolution display, and host multiple data devices simultaneously because power negotiation occurs on the separate Configuration Channel, rather than the high-speed lanes.

Enter USB4 Version 2.0 and the shift to 80 Gbps

USB4 Version 2.0 marks the largest technical jump in USB signaling since the transition from USB 2.0 to USB 3.0. Instead of adding more lanes, the new specification doubles throughput by replacing NRZ signaling with PAM3 modulation. PAM3 encodes three amplitude levels per symbol, enabling 40 Gbps per lane across the same physical wires that carried 20 Gbps in previous generations. With two bonded lanes in each direction, USB4 v2 reaches 80 Gbps symmetrical bandwidth. An asymmetric mode increases this to 120 Gbps in one direction for display-oriented workloads, while the reverse direction can be reduced.

The transport layer receives several upgrades. PCIe tunneling now supports PCIe Gen4, which doubles per-lane throughput for external SSDs and eGPU boxes, relative to Gen3 tunneling in USB4 v1. DisplayPort tunneling advances to DisplayPort 2.1 with UHBR20 signaling, enabling dual 8K or a single 12K display with full chroma and high refresh rates. Backward compatibility with USB4 v1, Thunderbolt 3, and Thunderbolt 4 devices is retained, although those devices fall back to older signaling modes when connected.

Many certified passive USB-C cables up to one meter will support 80 Gbps, but anything longer typically requires active retimers. These active cables include embedded signal processing and sometimes operate directionally, which introduces design considerations for things like hubs and monitors. The USB-IF’s new labeling scheme identifies cables explicitly as USB 40 Gbps, USB 80 Gbps, or USB 240W to mitigate the long-standing ambiguity that accompanied earlier USB 3.x naming.

Thunderbolt 5 rides alongside USB4 v2 as its highest-fidelity implementation, with Intel’s specification guaranteeing features that USB4 v2 only defines as optional. These include mandatory 80 Gbps symmetrical operation, 120 Gbps asymmetric display mode, PCIe Gen4 tunneling with at least 32 Gbps of sustained throughput, and support for 240W charging. Thunderbolt 5 also mandates lane symmetry and strict latency targets to support high-bandwidth, low-jitter peripherals such as external GPUs, docked workstations, and multi-display gaming setups. We can see that in higher-end systems in mid-2026, the full-fat Thunderbolt 5 spec is rolling out, with our recently reviewed Razer Blade 16 (2026) coming fully equipped with the port.

Because Thunderbolt 5 builds directly atop the USB4 v2 physical layer, its cables and controllers are interoperable across the USB4 family, but with stricter certification criteria. In practice, Thunderbolt 5 functions as the version of USB4 v2 that guarantees complete feature exposure, similar to how Thunderbolt 4 served as the reference point for the USB4 v1 era.

The next decade of universal connectivity

There has been some discussion among users and industry analysts about what the future of USB might look like. A likely future USB5 standard might see schemes beyond PAM3, if USB-C’s electrical characteristics prove capable of sustaining higher speeds. PAM4 could be a candidate here. Meanwhile, copper links are approaching practical limits at these data rates, prompting the active commercialization of optical USB-C cables that embed fiber transceivers inside standard connectors. While expensive today, optical links could carry future USB4 v3 or USB5 signaling across tens of meters, without electromagnetic interference or the attenuation challenges of copper.

Power delivery beyond 240W is another open question. The 48V EPR ceiling aligns well with current mobile workstations and most gaming laptops, but heavier categories such as portable displays, desk-dock hybrids, and workstation replacements may increase pressure for higher wattage tiers. Whether USB-C remains the long-term vehicle for that expansion or yields to a successor connector will depend on thermal constraints and cable reliability at elevated voltages.

The USB-IF’s renewed emphasis on clear labeling may ultimately define how smoothly the transition unfolds. The shift from version-based branding to explicit “USB 40 Gbps,” “USB 80 Gbps,” and “240W Certified Cable” identifiers is intended to eliminate the ambiguity that has characterized the standard for nearly a decade. Adoption will, of course, depend on consistent enforcement by manufacturers and retailers.

USB has moved far beyond its origins as a peripheral interconnect. The convergence of USB4 v2, Thunderbolt 5, and expanded Power Delivery turns the USB-C port into a high-bandwidth, multi-protocol backplane for modern systems.

A single connector can now supply workstation-class PCIe bandwidth, high-resolution video, and sustained charging for devices that previously required dedicated power bricks. The next steps in the roadmap take USB into signaling regimes that challenge copper’s limits while retaining full backward compatibility with the ecosystem that grew around USB 2.0 and USB 3.x.

As the 80Gbps era proliferates, users will encounter hardware that behaves less like a simple peripheral port and more like an external extension of a system’s internal fabric. As we move through the second half of the decade, OEMs are now starting to standardize full-feature implementations rather than the partial configurations that marked the early years of USB4.

If that consolidation takes place, the connector that started as a replacement for serial and parallel ports will continue its evolution into one of the most capable physical interfaces in computing.

In this installment of our ongoing quantum computing roadmaps, we turn to the area that has arguably made the most significant technical strides in 2025 and early 2026: neutral atom quantum computing. Be sure to familiarize yourself with part one, which covered superconducting qubits – through IBM and Google – and trapped-ion qubits, through IonQ and Quantinuum. Part two examined quantum photonics through Xanadu's continuous-variable approach and PsiQuantum's silicon-photonic architecture.

Like its predecessors, this is a technology and roadmap analysis rather than a technical deep-dive. We'll give you enough context to understand why neutral atoms have recently captured the attention of both the scientific community and major industry players, then look at what three of its key companies – QuEra, Atom Computing, and Pasqal – are building and planning.

What is Neutral Atom Quantum Computing?

Where superconducting qubits build their quantum systems from engineered Josephson junctions on chips, and trapped ions use electromagnetic fields to suspend individual atoms in vacuum, neutral atom quantum computing uses tightly focused laser beams – called optical tweezers – to trap individual neutral atoms in precisely controlled spatial arrangements.

Each trapped atom acts as a qubit: information is encoded in the atom's internal electronic states, and operations between qubits are performed by briefly exciting atoms into what are known as Rydberg states (the neutral atom mechanism for two-qubit logic gates). These are high-energy orbitals where electrons sit far from the nucleus, enabling long-range interactions between neighboring atoms when triggered. Switching a Rydberg excitation on and off is, in functional terms, the quantum analog of a logic gate – laser on, interaction happens; laser off, atoms return to isolated, quiet stability.

The atoms are laser-cooled to microkelvin temperatures during operation, but unlike superconducting systems – which require the entire chip and most surrounding hardware to be cooled to around 10-20 millikelvin – the surrounding hardware operates near room temperature. The cooling infrastructure is limited to a vacuum chamber and optical components, rather than a laboratory-filling dilution refrigerator.

The core quantum hardware is a vacuum cell that, in isolation, is about the size of a science experiment: a small glass chamber housing the atom array, surrounded by the optical tweezers. Pasqal has specifically cited total system power consumption of 4 kilowatts – a figure that would fit comfortably inside a standard server rack allocation.

Neutral atom systems require extremely stable laser sources across multiple wavelengths, precise spatial light modulators or acousto-optic deflectors to steer individual tweezer beams, high-resolution cameras for atom readout, and classical control electronics fast enough to execute real-time feedback loops during computation. The laser stack for a modern neutral atom system is substantial – a different beast from cryogenic engineering, but no less demanding of specialist expertise.

The majority of neutral atom companies – QuEra, Pasqal, and Infleqtion (a fourth player not covered here) - use rubidium-87 as their qubit atom. Rubidium is the well-trodden path: Its laser-cooling requirements are well understood; the required laser wavelengths fall in mature commercial product ranges, and decades of atomic physics research have produced a deep ecosystem of techniques and tooling around it.

Qubits are encoded in rubidium's hyperfine states – two specific energy levels in the ground state separated by a 6.8 GHz microwave transition – which are the same transitions used in atomic clocks, hence their extraordinary stability and coherence in the second-scale range.

Atom Computing elected a harder path: strontium atoms. Strontium's qubit transitions are more weakly coupled to environmental magnetic field fluctuations than rubidium's electron-based hyperfine states – which is technically significant because magnetic field noise is one of the dominant coherence killers in the rubidium qubit. This advantage comes at a cost: Alkaline earth atoms require more complex multi-wavelength laser systems, including ultraviolet laser sources, and the control techniques needed to isolate specific qubit transitions are more technically demanding. Coherence times up to tens of seconds have been demonstrated on strontium-based platforms, compared to the seconds-scale coherence of rubidium – a tangible advantage for deep circuits.

Why only Atom Computing? Part of the answer is expertise: CEO and founder Dr. Ben Bloom came from the NIST and JILA optical atomic clock community, where strontium is a well-developed tool. The research foundations were already in place. For most teams building neutral atom computers, rubidium is the faster, lower-overhead choice; the marginal coherence improvement from strontium doesn't justify the additional laser complexity unless you already have that expertise. It's a choice that illustrates a broader pattern in quantum computing: The optimal qubit technology isn't universal; it's relative to what your team knows how to build and maintain.

Advantages, challenges, and the mechanics of neutral atom quantum computing

Neutral atom systems carry two structural advantages that are difficult to replicate in other modalities.

The first is atomic identity: Every rubidium-87 atom is, by the laws of physics, identical to every other rubidium-87 atom. Superconducting qubits are manufactured devices with individual fabrication imperfections, requiring per-qubit calibration to achieve consistent performance. Neutral atoms need no such process – uniformity is a physics guarantee rather than an engineering achievement.

The second is reconfigurability. Unlike superconducting chips, where qubit connectivity is determined by physical wiring at fabrication time and cannot be changed, neutral atom arrays can be dynamically reprogrammed mid-computation. Atoms can be physically shuttled from one region of the array to another, placing them in proximity for gate operations and returning them to isolated storage afterwards. The processor's connectivity is software-defined rather than hardware-fixed: Any qubit can interact with any other. Readers of part one of this Quantum Roadmaps series will recognize the framing – this is the structural answer to the interconnectivity constraints we noted in superconducting architectures, where routing a gate between non-adjacent qubits requires threading through intermediate qubits (each step adding potential for error). Here, the qubit comes to the operation.

The reconfigurability described above is a result of modern, gate-based neutral atom processors implementing what is known as a zoned architecture, which partitions the atom array into three distinctly functional regions.

Storage zones hold atoms that are not currently being operated on. Because neutral atoms don't interact with each other unless deliberately brought close together, atoms sitting in storage zones remain isolated.

Entangling zones are regions where selected atoms are moved into close proximity, the Rydberg excitation is activated, and two-qubit gates are performed. Multiple entangling operations can proceed simultaneously in different parts of the array, as long as they don't spatially interfere – an equivalent to parallel gate execution in different lanes.

Readout zones are isolated areas where ancilla qubits – the backbone of error correction – are measured using optical fluorescence, without disturbing atoms in the storage and entangling zones.

This spatial separation is what makes mid-circuit measurement practical: You illuminate one region of the array while the rest of the computation continues undisturbed. This measurement occurs repeatedly throughout a computation to offset errors in real time, helping preserve the stability of the quantum state you're trying to compute – an architecturally non-trivial achievement.

One of the main challenges in neutral atom quantum computing relates to atom loss - neutral atoms are held in their tweezer traps by the focused laser beam. If a stray gas molecule drifts into the vacuum and collides with the trapped atom (or if thermal energy fluctuations become large enough), the atom can absorb enough kinetic energy to drift away into the vacuum chamber. Gone, simply – along with whatever quantum state was encoded in it.

This is called an erasure error, and while a whole-atom loss may sound dramatically impactful for any quantum computation you are trying to perform, it is actually easier to handle than most other types of quantum errors: You know exactly where it happened. A detection system continuously images the array, so a missing atom at a specific position is immediately flagged. Knowing the error location is roughly equivalent to knowing which memory address failed in a chip, rather than discovering that a subtly wrong value in the middle of your calculation chain threw the entire result out the proverbial window.

When this happens, a fresh atom is loaded in from a reservoir - a magneto-optical trap that continuously captures and cools background atoms adjacent to the main array. When it replaces the lost atom, it naturally has no memory of its predecessor's quantum state and is essentially a blank slate (called its electronic ground state). What preserves the logical computation is the error-correcting code: By distributing a single logical qubit's information across many physical qubits simultaneously, the code can tolerate the known loss of one physical qubit and reconstruct the logical state from the remaining ones.

The classical computing analogy is perhaps an ASIC versus an FPGA: a superconducting chip's fixed wiring is like an application-specific integrated circuit – high performance in the tasks it was designed for, but its capabilities are determined at manufacture. A neutral atom array's software-defined connectivity is more like a field-programmable gate array – somewhat slower per individual operation, but reconfigurable to whatever a task demands, including tasks the ASIC's architecture simply wasn't built to handle efficiently.

Where classical processors are measured partly by clock speed, quantum’s analogue to processing capability lives and dies by two metrics: coherence times (the window where calculations can be performed, which run to seconds in neutral atom quantum computing), and gate speed (how quickly individual operations execute). This places neutral atom solutions between trapped ions (seconds to minutes) and superconducting qubits (hundreds of microseconds).

Two open engineering questions balance the advantages described above. Rydberg gate operations run at approximately one to ten microseconds – slower than superconducting gates (tens of nanoseconds) and comparable to trapped ions. For very deep circuits requiring millions of gate operations, this matters. And while atom loss is now manageable via replenishment, maintaining the fidelity of the replenished qubit's reintegration into an ongoing error-correcting computation remains an active area of refinement.

QuEra

QuEra was spun out of Harvard and MIT in 2021, built on foundational research from Professor Mikhail Lukin's group and the MIT-Harvard Center for Ultracold Atoms. The company has raised over $507 million in total funding – including a $230 million Series B in December 2025, backed by Google Quantum AI, SoftBank Vision Fund, and NVIDIA NVentures – and operates from Boston, Tokyo, and the United Kingdom.

Its first commercial system, Aquila – a 256-qubit analog processor – launched on Amazon Braket in 2022 and remains the most-accessed neutral atom system by external user hours. From there, QuEra has consistently executed on its commitments. A 2023 Harvard-MIT-QuEra-NIST collaboration published a demonstration of 48 logical qubits in Nature, a result that remains the field's most-cited paper, and it established neutral atoms as the quantum error correction leader. A January 2026 follow-up pushed that to 96 logical qubits from just 448 physical atoms – the current verified world record, doubling the prior best - and the clearest demonstration yet of the gate-based, zoned architecture described above.

In June 2026, QuEra and AWS announced an expanded partnership to bring Libra – QuEra's first named fault-tolerant system – to Amazon Braket in 2028. Libra targets 256 error-corrected logical qubits at "megaquop scale," or one million reliable logical quantum operations at a 10⁻⁶ logical error rate. A follow-on generation – loosely termed "gigaquop-scale" (one billion reliable logical operations) – is described as the threshold for first commercial applications, suggesting a post-2028 system already in architectural planning.

It's worth noting Google's decision to both invest in QuEra’s $230M Series B and simultaneously launch its own neutral atom program in Boulder, Colorado, in early 2026 – while its superconducting Willow chip remains its production system – constitutes one of the strongest external validation signals that the modality has received. Google placing a parallel bet on its superconducting qubits doesn’t necessarily mean higher faith in one over the other, but it does mean something.

Atom Computing

Atom Computing was founded in 2018 in Berkeley, California by Dr. Ben Bloom, and has raised over $300 million in total funding, including $100 million in Series C and a $100-million Letter of Intent from the U.S. Department of Commerce, contingent on development milestones – both announced in June 2026.

The company's commercial strategy is tightly coupled to a strategic partnership with Microsoft, whose Azure Quantum platform provides the error-correction software stack that sits between the Atom's physical hardware and the application layer. The significance of this co-design arrangement is visible in the results: In October 2023, the company set a world record with a 1,225-site, 1,180-qubit array – the first gate-based quantum platform of any modality to exceed 1,000 qubits. A November 2024 joint demonstration with Microsoft produced 24 entangled logical qubits at 99.6% two-qubit gate fidelity, and 28 logical qubits running a benchmark algorithm with real-time error correction.

The company's most commercially significant development is Magne – currently being installed at QuNorth, a Nordic quantum initiative funded by Denmark's EIFO and the Novo Nordisk Foundation, expected to be operational in early 2027. Magne targets approximately 50 logical qubits from 1,225 physical qubits. It is, per Atom Computing's description, the world's first commercial quantum computer delivered with logical qubits as its primary specification – not a physical qubit headline count, but error-corrected logical qubits as the unit of sale. That shift in the commercial framing – from physical to logical – matters as a signal of where the industry is moving.

Atom Computing has not published a formal public roadmap. From available statements and a 2025 whitepaper, the company plans roughly a 10x qubit count increase per generation (a seemingly Moore’s Law-coded roadmap), placing next-generation systems in 2028 at approximately 10,000 physical and 100+ logical qubits. A June 2026 collaboration with UK company Nu Quantum will explore photonic networking between separate atom array modules – the interconnect approach that would allow scaling beyond single-array limits. Microsoft's own benchmarking framework anchors the targets: 50 logical qubits represents "general simulation advantage"; 100, "scientific advantage for classically intractable problems"; 1,000, "industrial advantage in catalysis and chemistry."

Pasqal

Pasqal was founded in 2019 in Paris, emerging from the Institut d'Optique Graduate School and co-founded by Professor Alain Aspect – awarded the 2022 Nobel Prize in Physics for foundational work on quantum entanglement. The company has raised over $300 million in funding, employs 275+ people, and serves more than 25 clients. A SPAC business combination with Bleichroeder Acquisition Corp. II signed in March 2026 at approximately $2 billion pre-money equity value, would bring Pasqal to public markets with roughly $649 million in cash, post-merger.

If QuEra is the scientific pace-setter and Atom Computing's distinguishing move is its Microsoft co-development model, Pasqal's differentiator is commercial and infrastructural: The company has deployed neutral atom processors directly inside high-performance computing centers as co-processors. Systems are installed at GENCI in France, Forschungszentrum Jülich in Germany, and CINECA in Italy. Revenue in 2025 reached 16.5M€ in commercial bookings, with clients that include Crédit Agricole CIB (portfolio optimization and derivatives pricing), Thales (satellite constellation planning), EDF (energy systems optimization), and CMA-CGM (maritime logistics routing). In early 2026, the company announced a demonstrated quantum advantage over classical methods in a materials science simulation of magnetic materials – a result being watched for peer-reviewed publication.

Pasqal maintains one of the most transparent public roadmaps in the space. Named hardware generations progress from Vela (2026, 256+ qubits) through Centaurus (2028, ~10,000 physical qubits, early fault-tolerant operation) to Lyra (2029, 100 high-fidelity logical qubits), with a 2030 target of 200+ logical qubits. The company also recently acquired Aeponyx – a Canadian photonic integrated circuit developer – to replace bulk laser optics with chip-scale photonic components, addressing both control precision and the manufacturing scalability of its control systems.

The difference in Pasqal's approach compared to that of Atom Computing and QuEra is that the company isn't yet deploying a digital, gate-based quantum architecture, but an analog one. Rather than executing discrete sequences of qubit operations, Pasqal's deployed systems evolve the entire atom array as a continuous quantum system — programming the physics directly, rather than translating a problem into circuit instructions.

If the earlier ASIC-versus-FPGA analogy held for the configurability question, this is the deeper version of it: Pasqal is currently selling the quantum equivalent of a dedicated hardware accelerator, purpose-matched to specific problem classes like materials simulation and combinatorial optimization, rather than a general-purpose quantum processor. That distinction helps explain both the commercial traction — analog quantum systems excel at exactly the optimization and simulation problems enterprises are already paying to solve — and the roadmap logic: Vela, the 256-qubit system launching in 2026, is where Pasqal begins the transition toward full gate-based digital operation.

Beyond Qubit counts

Raw physical qubit counts have dominated quantum computing headlines for years. But as we've touched on in parts one and two of this series, the metric that increasingly defines the fault-tolerance race is the ratio of physical qubits required to produce one logical qubit – the reliably error-corrected unit of computation that can actually be chained together to solve real problems.

The ratio depends on two things: the physical error rate of individual gates, and the connectivity of the hardware (which determines which error-correcting codes can be efficiently implemented). The ratios between the technologies we’ve already explored in part one (superconducting qubits and trapped ions) stand at around 1,000:1 physical to logical qubits and approximately 2:1 in terms of Quantinuum’s ion trap. Photonics quantum approaches, as explored in part two, are a different beast: Photon loss rates push physical-to-logical toward the 100:1 range or beyond – depending on where in the photon-to-qubit hierarchy you start counting.

For neutral atom quantum computing, QuEra’s approach currently sits at around 5:1. The numbers are more akin to apples-to-oranges than we’d like, but that’s the name of the game across these approaches. Improvements in error correction algorithms can and will change these ratios, but it’s a good approximation of where the technologies currently stand.

The neutral atom field has moved with unusual speed. The modality went from a 256-physical-qubit research system on AWS in 2022 to a 96-verified-logical-qubit world record in early 2026, a first commercial logical-qubit sale being installed in Denmark, and a named 256-logical-qubit fault-tolerant cloud system announced for 2028. That pace was not widely anticipated even two years ago.

As with the previous articles in this series, the convergence point is the same: fault-tolerant, error-corrected systems around the late 2020s to early 2030s, as the horizon for computers that genuinely outperform classical ones on commercially meaningful problems. What distinguishes the neutral atom path is the combination of software-defined connectivity enabling efficient error-correcting codes, coherence times in the seconds, and hardware that – for the first time across the three modalities we've examined – begins to look like something deployable in a conventional data center environment rather than requiring a specialized facility built around it.

DARPA's Quantum Benchmarking Initiative – our recurring external validation metric across this series – has selected QuEra for both Stage A and Stage B, and Atom Computing for its Stage B. That puts the neutral atom field in the same validated bracket as IBM, IonQ, and Quantinuum from part one, and Xanadu from part two. Whether neutral atom eventually takes the lead or the actual answer lies in a multi-modal quantum computing system is a question that the next few years will answer.

When German Gref, chief executive of Sberbank, told Russian state broadcaster Channel One in May that he hoped to run the country's flagship GigaChat AI model on Chinese-made processors, it highlighted how difficult getting access to the global supply chain was for countries like Russia.

Sberbank, Russia’s largest lender and the driving force behind Russia's push into AI, is seeking to secure Chinese chips because Western sanctions continue to block its access to advanced hardware from abroad. Tom’s Hardware’s own reporting suggests the most likely candidate to power Sberbank’s systems is Huawei's Ascend 950 family, the most advanced silicon China currently produces.

Sberbank may well want chips, but getting hold of them from Huawei will be easier said than done. The Chinese chipmaker already has enormous orders to fulfill from ByteDance, Alibaba, and Tencent, with ByteDance alone committing $5.6 billion to the Ascend 950PR earlier this year. Huawei is targeting 750,000 units of that chip in 2026 and expects to earn $12 billion in AI chip revenue throughout this year.

But it highlights how U.S. sanctions are pushing China to develop its own chips, which in turn attract other controversial states. That potentially allows China to extend its reach across an entire parallel supply chain.

A sanctions-busting Sino-Russian alliance

“Economic restrictions are pushing Russia toward Chinese compute solutions,” said Allen Maggard, a senior analyst at C4ADS, the Washington, DC-based global security nonprofit, in comments to Tom’s Hardware Premium. But Russia doesn’t need much pushing, Maggard argued. “I don't see a scenario in which Russia can economically scale its domestic compute capacity using Western solutions alone,” he explained. In part, that’s down to the country’s constrained economy. “Its defence industry can afford Western chips for individual weapon systems – for now – but its civilian tech sector cannot. That leaves China's electronics and computing sectors as Russia's most economical option going forward."

Sberbank is not an isolated case in this way. Tramplin Electronics, a Russian sovereign IT company set up just over a year ago, is already marketing a processor called Irtysh based on a design from China's Loongson Technology. At the same time, Element, Russia's biggest chipmaker, in which Sberbank acquired a 41.9% stake in January, has reportedly begun producing microchips inside China for the Chinese automobile market. “A shift is clearly underway,” Maggard said, “but toward greater mutual access between the Chinese and Russian electronics sectors, probably skewed in China's favour.”

All that adds up to less of a meeting of equals than Russia becoming a dependent customer of a still-developing semiconductor ecosystem – though Maggard points out that under Vladimir Putin, the Kremlin will likely resist a total surrender of sovereignty. “Moscow would certainly prefer, and likely intends, to build a parallel technology bloc with Beijing,” he said.

Are actions backfiring?

The irony is that Western policy, which was designed to try and slow or stymie the development of China and Russia’s high-tech economy, may well have helped manufacture exactly the kind of trading bloc it set out to prevent.

The issue is compounded by uncertainty in Washington DC, where the inhabitant of the White House seemingly can’t decide what he wants from the situation. In the space of 12 months, the Trump administration banned Nvidia's H200, unbanned it, slapped a 25% tariff on it, and created a licensing framework that experts immediately called contradictory. On 13 January, the Commerce Department published a regulation permitting the sale of advanced AI chips to China – a move described by the Council on Foreign Relations as "strategically incoherent" – that, if implemented strictly, would block most exports, but if implemented loosely, would fail to address any of the concerns that motivated the controls in the first place.

Then, a day after the rule cleared Nvidia to sell, Chinese customs officers were reportedly told not to let the chips into the country at all.

China is capitalizing on the chaos. Beijing's drive toward self-sufficiency long predates anything Washington has done, said Mishel Kondi, a senior analyst with C4ADS's Human Security and Conflict Prevention team in comments to Tom’s Hardware Premium. "The PRC announced Made in China 2025 in 2015,” she points out. “That precedes export controls.”

Her analysis of Chinese government documentation over that period shows China has maintained a state-directed strategic priority of breaking from U.S. and friend-shored technologies. “In other words,” she said, “China's goal of building a more self-contained AI chip ecosystem predates U.S. export controls.”

Kondi said that it’s too early to judge whether the export controls are a triumph or a failure. "U.S. export controls have created real challenges for China's compute and limited its ability to scale and innovate," she explained, even as Chinese actors exploit loopholes through university procurement, transshipment via Southeast Asian jurisdictions, and corporate diversion through shell companies in secrecy jurisdictions such as the Cayman Islands. But there is a risk in feeding the beast. “The risks of accelerated domestication grow if China has greater access to advanced chips,” she warned, “and it would be a mistake to interpret that strategy as a response to export controls.” (It’s worth noting that China has reportedly gained access to an EUV machine that it was never meant to get its hands on.)

China’s growing chip dominance

China has been keen to bolster its chip sector for years, and it’s starting to reap dividends. Lisuan Tech – a Shanghai start-up founded in 2021 that nearly went bankrupt in 2024 – has begun shipping the LX 7G100, China's first fully homegrown gaming GPU, built on a 6nm process using an in-house architecture the company calls TrueGPU. It sells for roughly $480. Despite pre-launch claims that it rivaled Nvidia's RTX 4060, it’s still a stage behind Western designs. Independent benchmarks on Bilibili placed it closer to an RTX 3060. But it exists, it is wholly Chinese… and is being sold into a captive domestic market.

Beyond China’s border, the captive market increasingly includes Russia. The Russian market for GPU-based AI accelerators reached 62.7 billion rubles in 2025, according to Russia-based analysts TAdviser, up roughly 20% on the year before. Nvidia-based cards still account for around 84% of sales in volume terms, with the RTX 4060 the single most popular model. Russian customers are increasingly forced to look at Chinese cards as an alternative. Nvidia chips arrive through grey channels routed through China, Turkey, the UAE, and India at a premium.

In late May, the European Commission proposed a nine-month derogation on dealings with Yangzhou Yangjie Electronic, a Chinese chipmaker it had added to its 20th Russia sanctions package barely a month earlier, after EU automakers warned that chip stocks could run dry within weeks. That was because European carmakers needed access to the chips after the Nexperia crisis disrupted supply across the continent. Both Russia and China will have noticed the expediency with which Europe is willing to drop sanctions when needed.

By that point, China may be competing on the global stage. In late May, Huawei said its high-end chips would reach transistor density equivalent to 1.4nm processes within five years, unveiling a "Tau Scaling Law" focused on shortening interconnects and improving data movement rather than shrinking transistors. TSMC plans to begin 1.4nm mass production in 2028, meaning Huawei would still be three years behind, but the gap is closing.

That has experts like Kondi watching on carefully. “The risks of accelerated domestication grow if China has greater access to advanced chips,” she said, “and wider PRC access to these chips also empowers China's defence capabilities and enables it to expand its pervasive and repressive surveillance apparatus.”

Rapidus is bidding Japan's entire return to leading-edge logic on one fab in Chitose, Hokkaido, and the schedule now turns on a 2027 mass-production target for a 2nm process that no high-volume customer has yet committed to.

Since opening the IIM-1 pilot line in April last year, the company has run wafers through Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached its expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike said the same month that more than 60 companies are in talks over 2nm capacity, but not one has yet signed a volume agreement. Given that its entire production base is the single IIM-1 facility, this leaves Rapidus with no diversification and no fallback site if the node doesn’t go ahead as planned.

However, the fab has the hopes of an entire nation pinned on it, and its plans are promising. Here's the breakdown.

A ticking clock on IIM-1

IIM-1, short for Innovative Integration for Manufacturing, broke ground in September 2023 at Bibi in Chitose, with the cleanroom completed in 2024. ASML delivered a TWINSCAN NXE:3800E in December 2024, the first mass-production-grade EUV system installed in Japan, and the tool completed its first exposure on April 1st last year. The pilot line also began operating that month.

Rapidus is currently targeting 2027 for mass production, but the company has given that date without any further qualification, with its business plan simply pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The same plan sets out a capacity ramp from roughly 6,000 wafer starts per month at the outset to around 25,000 within the first year, a fourfold increase that Rapidus is counting on to bring per-wafer costs down.

IIM-1’s siting in Chitose offers the abundant water that wafer cleaning demands, a cool climate that eases cooling loads, and some of Japan's strongest renewable-energy potential across wind, solar, and hydro. Local and prefectural authorities have organized around the project under a “Hokkaido Valley” initiative that aims to build a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.

The 2nm process

Rapidus’s 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to learn the node, with roughly 80 later returning to Chitose to transfer and tune the process for production, according to IBM.

The differentiator the company is leaning on is manufacturing flow, with IIM-1 running single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. It’s understood that the 2nm Process Design Kit (PDK) reached early customers in Q1 this year. Still, Rapidus hasn’t yet published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.

The program extends beyond the wafer, with Japan’s New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus providing funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also floated panel-level glass-substrate packaging as part of its longer-term roadmap. Building that back-end capability in Chitose rather than outsourcing it would mirror the integrated approach Intel and Samsung take.

Japan’s government as a shareholder

Rapidus’s February funding round closed at ¥267.6 billion, or about $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment, the first made possible by a 2025 revision to Japan's subsidy law permitting government equity in Rapidus, made Tokyo the largest single shareholder, with a golden share giving it veto power over major decisions, including share transfers and technology partnerships.

That round sits on top of a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, taking Rapidus’s combined capital and capital reserves to around ¥425 billion. The shares the state holds are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates, a clause that pairs with the golden share to give Tokyo both upside alignment and a downside lever.

Rapidus’s buildings and equipment are also currently owned by Japan's New Energy and Industrial Technology Development Organization (NEDO) and leased back, with the company previously obligated to buy them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.

The customer conundrum

Koike said in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10 of them. The names attached to those talks in reporting by TrendForce are IBM and the Canadian RISC-V accelerator startup Tenstorrent, with Fujitsu, a founding investor, separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, the firm led by chip architect Jim Keller and currently being considered for takeover by Qualcomm, agreed back in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center (LSTC) project, with Tenstorrent handling the CPU and Rapidus' AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.

Neither of these amounts to the committed high-volume order that Rapidus needs, and fast. Koike has described interest as growing “like a runaway steam engine,” but interest is not the same as allocation. Rapidus’s cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan’s current mainstream parts, a premium that’ll only narrow with volume.

Japan's two-track strategy

Rapidus is the leading half of a national plan that’s running on two tracks. The other is TSMC's JASM venture in Kumamoto, on the southern island of Kyushu, where a first fab backed by Sony, Denso, and Toyota began mass production in December 2024 on mature 12nm, 16nm, 22nm, and 28nm nodes aimed at automotive and industrial chips.

A second Kumamoto fab broke ground in 2025, and its planned node was upgraded twice, first to 4nm and then to 3nm, with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north. The Kumamoto plants carry far less technical risk and are already shipping; Rapidus carries nearly all of the program's execution risk and none of its proven output.

Even as the 2nm line ramps, Rapidus plans to begin 1.4nm process development in 2026, start construction on a 1.4nm fab in 2027, and reach mass production around 2029. The node leans on the company's research ties: Rapidus joined imec's core partner program in April 2023, giving it access to the Belgian institute's pilot line, and imec's position is that 1.4nm single-patterned layers require High-NA EUV, the 0.55 numerical-aperture tool that resolves the most critical metal layers in one exposure rather than several. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production, according to figures cited by both TrendForce and Nikkei.

Rapidus’ financials highlight how far all this is from being self-sustainable, having posted a ¥375 million loss for fiscal 2025 with total assets of ¥749.5 billion, while still aiming to raise around ¥1 trillion from private investors. The ASEAN+3 Macroeconomic Research Office has been cited as estimating that committed funding still falls short of the roughly ¥5 trillion needed for stable production, dependent on a private investor base that has yet to materialize at scale.

Meanwhile, TSMC moved its N2 node to volume production in late 2025, and Samsung began first-generation SF2 mass production the same year, which puts Rapidus roughly two years behind both on a node that customers can already buy elsewhere with proven yields. There’s also something of an adversarial backdrop developing: TSMC employees were reportedly accused last year of taking 2nm trade secrets said to be destined for Rapidus, an allegation a Japanese government official later characterized as non-critical. The episode has no confirmed bearing on Rapidus’s process, which is built on IBM IP.

Rapidus is targeting operating profitability around fiscal 2030 and an IPO in fiscal 2031, a timeline that assumes the 2027 ramp lands on schedule and that the customers now in talks convert into committed volume. Three milestones will indicate whether those targets are possible: a named customer with a committed volume order, evidence that 2nm yields are tracking toward the levels TSMC and Samsung already run at, and confirmation that the capacity ramp is hitting its 25,000-wafer target.

Ahead of our review of the Steam Machine, we sat down with Valve engineers Pierre-Loup Griffais and Yazan Aldehayyat to talk about the compact SteamOS PC. We discussed the pricing, the design process at Valve, component shortages (how could you not?), and even Windows support. We published excerpts from this interview in a story alongside the review. Here, we're presenting the full transcript of our conversation.

This transcript has been lightly edited for clarity.

Andrew E. Freedman, Tom's Hardware: I think I'd be remiss if I didn't talk about the elephant in the room, which of course is pricing. The Steam Machine starts at $1,049 in the U.S. for the 512GB option. How do you think that price is going to hit, and how do you think it reflects the vision of the Steam machine when you were building it?

Pierre-Loup Griffais, engineer, Valve: I think we'd be hard-pressed to make predictions on how exactly the market's going to respond to it. I think it's very different than what it looked like last year. And so in terms of what appetite people have to buy a gaming PC at a certain price, everyone's going to have a different opinion on whether it's a good value or whether the product makes sense for them. So I don't know if we're hazarding any predictions there.

But it's definitely the case that our original design, of course, was based on memory and storage prices from two years ago or so, and so we were in a different segment than we were hoping to be, but I think it's more of a reflection of where the market as a whole is than Steam Machine itself, right? So, I think if you're looking at building a PC from parts, either comparable horsepower or more horsepower, you know, you're probably looking at a similar price point here. At least that would be our expectation, right? That if you're, if you're looking at a trade-off of, "I want something that's about as powerful," you're still looking at a price that's roughly what we're offering there. And then you have all the things that you can't really build, like the form factor, the quietness, the CEC integration, the dedicated Bluetooth antenna for controller support. All that stuff is not really something that you can put in your own gaming PC and are still strong reasons that people might want to get the Steam Machine.

Freedman: Some of that definitely tracks. I've been going through our database, and things that were around the price point of the Steam Machine now are not the price of the current Steam machine anymore.

Yazan Aldehayyat, engineer, Valve: Yes, yes.

Valve speaks on Steam Machine compared to traditional consoles

Freedman: You're very much calling the Steam machine a PC. You haven't been calling it a console. Do you see that as a totally different audience, because the PlayStation 5 Pro is $899 right now, which is higher than it used to be? Do you see that as a competitor inside Valve, or are you looking at this like this is specifically a PC for a PC audience for people who already have Steam libraries?

Griffais: Yeah, I think it's a pretty different offering, right? I feel like if you're playing on PC, you're not looking at something like a console system and comparing just the price and the specs, because you have a bunch of games on PC, and you would have to buy those games on the other platform, or you would have to factor in whatever subscription cost there is to play online. There's a lot of factors there where it's not really apples to apples, right? And so I think it's an offering for folks that want to play on PC by definition or have some use for a PC that's around that powerful, it's probably quite a different decision than figuring out if something like a console is for you. There's a lot of trade-offs there.

Aldehayyat: I think the value of the Steam Machine is inherently tied to the value of your Steam library in a lot of ways. The more games you have on Steam, the more valuable the Steam machine is to you, and the Steam Machine makes your existing library even more valuable. So, those two kinds of decisions are very much intertwined, and I think at least early on, for sure, we suspect that it's for people who already have a big Steam library. The Steam Machine is just going to make a lot of sense to them.

Griffais: Yeah, and folks also have a lot of stuff on PC that's not necessarily on Steam, right? Like, there's a lot of different libraries on different stores, there's downloaded games, there's MMOs, all this stuff is also there, right, including productivity apps. There's some desktop use you can do with it. So, I guess the value of it is a little bit harder to express than just, like, you have that price and you have that library.

Freedman: Do you see Steam Machine as a possible entry point for someone who's just getting into Steam, or would you sort of advise those people to be starting elsewhere?

Griffais: For sure. Yeah, I think it could be. Usually, I guess it's hard for us to reason around what someone that's not on PC might or might not do, just because we're not really used to talking to those users. But I think we've seen some people use something like Steam Deck as an entry point for PC, and it seems to have worked for a bunch of people. I would think that Steam Machine is the same between the verification program and the SteamOS experience, that, you know, whose sole aim is to basically get out of the way, so that you can get to your games as easily as possible. I think that it's a good kind of niche for that.

Aldehayyat: I think it's like just to emphasize that point, it's we think it's a good entryway in big part because of how easy it is to set up and play games, right, like if somebody who's curious about PC gaming, and you're interested in getting into it, but you're a little intimidated by all the information that you need to know to build your own PC, or tinker with drivers, or whatever. The Steam Machine could be a really compelling offering for you, because then you can play those games with a lot less work, and maybe after you really get into it, you decide to build your own PC, and that's cool, that's great, that's awesome. But if you're a little bit intimidated, or maybe you're a PC gamer. Your life got a lot busier, you don't have as much time, that could be another way for you to get back into it. So the ease of use is something that we really cared a lot about was really important to us.

Griffais: We've heard that a lot for Steam Deck. People that are like, "I used to play on PC, I might have games on Steam, I might not, but I used to be a PC gamer, and you know, I have a family now, I have kids or something. I've been wanting to get back into it, but it seems complicated, or a time sink, or something." A bunch of people seemed to have found Steam Deck as a good way to address that, and I expect it might be the same.

Freedman: I mean, I can tell you, I have a toddler. I just finished Resident Evil Requiem, and I played the majority of it on a Steam Deck, because I was able to do it after her bedtime in a place in our apartment, far away from her room.

Aldehayyat: Great.

Griffais: First-person or third-person with Grace?

Freedman: For Grace, first-person. So I've got one more price question, and we'll get on to some engineering stuff.

Subsidizing hardware & the VRAM conundrum

Freedman: So you're not subsidizing the Steam Machine, which Valve said would make the PC a more closed platform, I guess maybe more similar to some consoles. but it's been said a lot that Valve subsidized the Steam Deck. I'm not sure I've actually found any definitive sources that say that. Did Valve subsidize the Steam Deck?

Griffais: Not really. If you look at certain SKUs at certain points of time, you know, it might be below or above cost by a small margin. I think there's some comments that we made around it, you know, being painful and all that early on, that was more about being as close as possible to cost than anything. Same thing here, right? If you look at where we thought Steam Machine was going to be in terms of pricing, and where we are now, and where Steam Deck used to be, and what it is now, you know, as we've had to announce some price changes recently, we're actually quite a bit more aggressive now, because we understand that the higher price is less accessible to people.

I guess we're able to be very aggressive with margin, right? And so we're even more aggressive now, trying to be as close as possible to the actual cost of the parts that we're shipping up.

Aldehayyat: But it's important that the Valve hardware is a self-sustained program; it's not subsidized by software sales, so that's kind of the piece to get across.

Freedman: So, on the hardware, one big worry back from the announcement was some of the hardware choices, which aren't, for lack of a better term, current gen, either in terms of AMD's technologies or in some cases compared to other modern graphics cards. The GPU specifically has 8GB of VRAM. How is Valve handling this internally, both your feedback and what you're doing with SteamOS?

Griffais: So there's a few aspects to that. One comes down to the system design when we picked the parts for it, and the GPU, and the amount of memory that was going to be available for the GPU specifically. I think we are very aware that, you know, eight gigs is kind of aggressive and could be kind of in the middle of what you would need there. But we made a lot of calculations on "what are you able to play with things like that?" and our conclusion was that for the stuff that you would want to play, and the level of details, and everything that you would want for that level of performance, you won't be in the spots where you're running out of VRAM.

The cases where you're running out of VRAM are actually cases that you would not want to be playing on a system like that. It'd be too slow. It's possible that there's some games in the future where that calculus is going to be a little bit different, right? Like, they take more VRAM at the same performance or something. But right now I think we're doing pretty good there. The cases where you're exercising the VRAM limits are actually cases that you wouldn't want to play as a real user, in my opinion. But that being said, between the Steam Deck release and now, we have done a ton of work on SteamOS to teach it about discrete VRAM.

We only used to support APUs, where we didn't have that problem — we had a whole other set of different memory management problems instead — and then improve the handling of VRAM under stress, under load conditions, and trying to get to the best outcome. So we're still rolling out updates there, but I think in practice the experiences improved rapidly around those cases. And we're continuing to do a bunch of work there.

Aldehayyat: I also want to just say that everybody sees that upgrade cycle for PCs have been slowing down dramatically. And more importantly, the new games coming out are able to scale generations of CPUs and GPUs a lot more gracefully than they used to. So, again, for us, the metric that we care about is, can you play the games on Steam? Can you play every game on Steam? And we think the Steam Machine absolutely can, right now, and we think the longevity for it is actually quite good, given the current reality of the upgrade cycles. I mean, maybe 10 years ago, a device like this wouldn't last as long, wouldn't have the legs to be competitive for as long. But given where we at now, even as of today, it can play your Steam library pretty well, and given what the market is doing right now, and the upgrade cycles, it still has the longevity to be a good device for people for many years to come.I think that one of the great things about the PC ecosystem is that games are not designed with a fixed performance target, they're able to come up and down, and you can tune them to be a great experience on a variety of hardware,

Griffais: And in a way, things like Steam Deck, and the new-ish, you know, segment of growing PC handhelds has been helping with that too, because people have scalability more in mind, I think. And there's been, there's been games, you know, that have made adjustments to have you know different level details or different presets for lower-end configs that I think you know that same effect will happen in the future and will pay dividends for all of PC as well. You have people that you know are probably playing on old laptops and things like that that maybe don't have to upgrade as much now because the developers, you know, have more scalability in mind, which is, I think, a good development for everyone.

4K capable, 1080p optimized

Freedman: I found that you know you can largely get playable frame rates on this thing. I mean, I'm someone willing to turn down settings.

But there was the 4K with FSR comment that had turned some heads initially in my testing. I found that's largely true, that you know, if you're willing to turn some settings down, you can get somewhere around 4K 60 with FSR. But why call it 4K capable, as opposed to really marketing it as a really solid 1080p or 1440p machine, rather than using FSR in the measurements, which kind of depends on which version of FSR the game is using?

Aldehayyat: A big part of that messaging actually came because we found a lot of people who are not as familiar with tuning their gaming settings want to just make sure that it's compatible with their 4K TV. So, basically, it's just our way of telling people that yes, if you have a 4K TV, you'll be able to use your Steam Machine with it. Not everybody understands the difference between render resolution and your TV resolution, so yes, for a lot of games, rendering a 1080p or 1440p is definitely the sweet spot, but we kind of wanted to make sure people understand that it still can work with your 4K TV, and you have the ability to upscale your content to that resolution, basically.

Griffais: And I think generally it's broadly true for the catalog as a whole, right? For sure, if you're looking at the current segment of games and what's coming out, then that's going to be what's stressing it out the most in terms of performance. Steam has a lot of games that extend decades into the past, as well. There's a ton of games that are playing that are coming out right now that are going to play just fine at 4K native on the Machine. There's there's a wide variety of different performance targets that games have, but in general, I think there's a ton of good experiences that you can have at 4K natively on the Machine. But for sure, for things that are coming out, or more recent games, I would personally probably pick, you know, 1080p render resolution, or 1440p, depending on how scalable it is.

Freedman: Speaking of 1080p, I noticed early on in the testing that 1080p seems to be the default resolution set across SteamOS on the Steam Machine. I was actually kind of surprised by it. I was going through, first on a per-game basis, boosting it up, so I could, you know, test multiple resolutions on my monitor. And I think very much like the sort of like the Steam Controller, there's not a huge on-ramp, not a lot of hand-holding on how to work this type of thing, so is there going to be any sort of messaging or sort of tutorials from Valve elsewhere that explain how to adjust these settings so you can get exactly what you're looking for?

Griffais: Yeah, I think we want to make that more visible and make it pretty obvious to folks that know what it is that this is happening. There's also different work that I think we want to do around that system. Another one is that when we're testing the games, we can also flag them for different default resolutions. So for an indie game or a game that's a little bit lower spec, or an old game, we should have the ability to say that game is actually just fine at 4K, or you know, other resolutions, so that you don't have to go change that setting. A

The thing we're trying to avoid is that some games, the way that they detect settings, you know, is all different. Games do that very differently, right? And it's possible for some games to start at 4K very high ray tracing. And the experience with that is not great. You don't want to start a game and have that sort of experience as a user, especially when you're trying to get to a point where most people can run a game and expect, you know, to be able to play it and not tinker with it. So we're trying to make sure the baseline is on the safe side, where you're going to have a fine experience. But for the folks that want more detail, more definition, they can access those settings, and they know what they're doing, right?

So I think that it could definitely use a little bit more visibility, so that you are very aware of what the OS is doing behind the scenes, and very aware of how you can go change that setting in a way that right now maybe is not as visible as it could be.

The verified program deepens

Freedman: Speaking of all this, there's the verified program. I mean, obviously, the verified program made it very clear if you could play something on Deck. On Steam Machine, assuming you turn off that 1080p flag, you get into more resolutions, more potential settings that are supported, really, just more options and games all around, because you have more powerful hardware. So, when something is verified on the Steam machine, is that specifically verified at 1080p, or is it going to be more like a modular thing where you explain where it's verified?

Griffais: The only thing that we want to make sure that a verified game gets at is that by default it's above 1080p 30, right? So that's really what we're shooting for, and again, it's all about the default experience, because I think all those things that you said are broadly true for the Deck as well. Like you can actually load up a game on deck, uncheck the resolution settings, set it to 4K, and set very high ray tracing. Look into all that stuff, and we're not trying to have the verified system tell you, like, hey, if you do that, then you need to change the settings to X and Y to get to a certain frame rate. We're just saying, oh, you're changing settings — at that point, you're outside of the realm of what the verified system is designed to do, because it's for those users that are not really doing that., and we expect the same to be true for the Machine Similarly as the deck, I think we'll see an effect where more and more games also pick settings that were intended for the Machine as time goes, as developers are putting those presets in, which will further make the default experience match the expectations of those users that are working from the verified system.

Freedman: I very clearly remember, I think one of those was Cyberpunk 2077. That was the first game where I saw that they had a Steam Deck setting. I was like, "Well, I know which one to pick."

Griffais: And, of course, most users never had to pick that, because it was selected by default, right? And if someone can have played the game and never seen that settings menu, that's a win in our book, right? But we also want to make sure that people that want to tinker with that can also do that, and every step of the way, we're messaging to developers, like, hey, even if you know you're running on a Steam Deck, even if you know you're running on a Steam Machine, do not disable settings, do not hide settings, that's not what people want to see. There's a lot of users that you might not be aware of that are all going to have very different opinions on what settings make sense on the device that you're playing, and we're really trying to make sure that you know the SteamOS experience upholds that core principle of PC gaming.

Freedman: I know that quite a handful of places have resources online — all they do is go through Steam Deck settings, tinker, and try to make it the best they can.

Hardware design, repairability and limitations

Freedman: So, I want to move this a bit more towards the hardware design. So every major component is cooled by one big heat sink with the 120 millimeter fan. I'm curious, how did you choose that kind of design? What are the benefits of that?

Aldehayyat: There's actually a couple of reasons. I mean, obviously, the first thing is that it's the most compact design you could come up with, right? Like, if you have one thermal module, then you know you could make the device as small as possible. So that was the number one sort of factor that made us go into that path. But the other thing that is interesting about this is that if you have two separate thermal modules, then each one has to be designed for the absolute worst case for each one, so you end up with a combined volume that is larger than the device is ever going to be. But if you have one, then it can share, basically, right? So, if the CPU is not eating up its entire thermal budget, the GPU can use that, or if the GPU is not eating its entire thermal budget, the CPU can share that. So that's one of the advantages, is that your ability to kind of allocate thermal headroom back and forth between the CPU and the GPU, and all that kind of stuff, independently.

To be clear, it was very, very challenging to make that design work, because when you're trying to touch off of different things, tolerances really eat you up, so you have to come up with, because you know, good thermal module design requires you to have the absolute minimum gap between whatever you're trying to cool and the thermal module itself, and the GPU die to the thermal module, the CPU die to the thermal module, they both have to basically have the smallest gap possible. Nut then in reality, like things vary and the CPU is tall and the GPU is taller and the motherboard bows and the thermal module has tolerances, so actually getting the design to have enough compliance in the right places to accommodate all those tolerances was by far the hardest challenge we had to overcome. But by overcoming it, I think we ended up at the most compact design, cost-effective design.

Griffais: It's also the quietest. Having one big module lets us have a big fan, which then can spin lower and, or, you know, lower RPMs. So we're pretty happy to have been able to make that work, because it turned out really good in terms of the ratio between how quiet it is and its normal performance.

Freedman: I opened it up to take a look, and I was able to take the whole thing out of the case with a single Torx T9 screwdriver. I don't think this was built with the idea that a ton of people were going to open it, but was repairability like a serious consideration of the design?

Aldehayyat: I mean, yeah, absolutely. We care about repairability a lot, and we tried our best to make the device as repairable as possible while still making it compact. I mean, those two things, generally speaking, fight each other. The more compact something is, the harder it is to take apart. So, we think we found a good balance. It's just kind of part of our philosophy, right? We think it's your device, so you get to do whatever you want with it. We definitely did not put any artificial barriers for people to do this, but we actually go a step further and try our best to make it as easy as possible. There's limitations to that, but things like the fact that the SSD is on the FPC that loops around to make the SSD accessible, that was not by accident, nor was it the easiest way to do this. We could have buried it under the thermal module, and that would be actually way easier, but we chose not to do that. It's just kind of a part of our philosophy, even though it's not necessarily the easiest or cheapest way to do things, we still think it's the right way to do things.

Griffais: Yeah, there's a few things that we generally try to have. You know, we can't hit them all the time, but I think we've, we've done, you know, a pretty good job of it ever since Steam Deck OLED, especially, making sure that, all screws use the same type, that they're machine screws, so you can take them apart and put them back without damaging some plastic or some wood receiver there. Also labeling stuff, right? Like, there's a lot of labels on the little connectors on the boards that we could easily have removed in production, but it's actually really useful; We're also taking them apart, right? It's useful for us, but I think you know, we definitely are not intending that most people will open this, like you say, but we want to make sure the people who do are not going to run into barriers.

Freedman: Yeah, I mean, there's an awful lot of Steam Deck mods. I'm sure a lot of those same types of people will be very interested in this. So a lot of the ports — this is probably by the design of making it so compact — they're attached via daughter boards and ribbon cables. Will those components be made available either for tinkerers or repair shops?

Aldehayyat: Yeah, so similar to how we did it with the Steam Deck, we're going to work with iFixit to make the parts available. We're going to basically try and make as many parts available as possible. I don't know for sure the full list of components that will be available, but I believe all the FPCs, daughter boards, and ports will be available through iFixit. I'm not sure which ones they decide to sell, or whatever. But yeah, our goal is to make those parts available as widely as possible.

Freedman: Is it any more difficult to make those parts available because of just the general component shortage, or are you stacked up on those ones?

Griffais: It's actually easier because they're on daughter boards, right? If that stuff wasn't the main board, then you'd be in trouble because there's some soldered-down memory, the VRAM, right, is the only soldered-down; the system RAM isn't, it's SO-DIMMs. If anything, it's a little easier for things like ports, and yes,

Aldehayyat: Believe it or not, right now, even things like the FR4, like the raw PCB material, it has shortages. But it just so happens that the memory shortage is way worse, so yeah, it's not really a major challenge to make those parts available at this point.

Freedman: And I'm assuming if you work with iFixit, that also means I'll be publishing maintenance manuals of some sort, right?

Aldehayyat: Yes, we're going to partner with them too, and they're going to create a lot of the repair manuals, replacement parts instructions, and things like that.

Freedman: Because opening it is super simple, but getting to the RAM, to the SO-DIMMs, that's got a lot of ribbon cables.

Aldehayyat: Yeah, we're aware of that, and I'll be honest, it is something that we really wanted to improve, and we tried to make the RAM more accessible, but there was just no real way to. I don't say it was impossible; it was just given the time and engineering resources we have, we just could not come up with a solution that worked. With the SSD, we were able to put on the flex and just read it around. With memory, you just can't do that because of signal integrity reasons. And trying to make an access hatch through the power supply just wasn't possible for safety reasons. So there's really no way. We couldn't come up with a solution, but maybe in the future we can come up with something,

Reckoning with hardware shortages and pricing

Freedman: I know in the blog post it says that there were some components you were barely able to source at all. Outside of memory, which components have been the most difficult to get for the Steam Machine?

Aldehayyat: Storage, obviously,

Freedman: You mentioned PCB, PCB materials.

Aldehayyat: Yeah. I mean, honestly, it's a little shocking right now. There are some shortages in plastics. There are some shortages in FR4, some capacitors. But all of those kind of pale in comparison to the memory and storage shortage. If this was a normal time, people would be concerned about these things, but given the memory and the supply shortage, this just doesn't really crack the top ten of problems. It's just kind of to show that really everything is constrained, but the memory and shortage overtake all of them. So that's really the primary focus.

Freedman: And the other interesting thing I found in sort of sourcing and building a design is that the blog post suggests you started sourcing parts somewhere in 2022, which suggests you've been at the Steam Machine for a few years. Are you able to talk about the general timeline of product development for the Steam Machine?

Griffais: The process starts very early. I mean, in terms of specific time frames, it's a little hard, you know, just because our memory is fried from working hard on trying to ship this thing. But you know, the design process, I think, probably started like three years ago, or so, when we were building machines from parts, trying to get at the right performance target. And then we started progressively moving to the next step, building it up as, like, a whole all-in-one thing, and then refining the form factor and all that. But from that point on, you're already starting to test the waters and getting in touch with suppliers, making sure that you're going to have multiple suppliers for the things that you're sure you're going to have, so it's definitely a long pipeline. But I would say plans for full-scale production of the object that you're looking at now is probably like a year or so.

Aldehayyat: I also think that the research and development, I guess we take more seriously here at Valve, and potentially some other places. Things don't go from "here's a presentation for a device," and then we start planning to make it. We first start by making some prototypes to convince ourselves that this actually makes sense, and there's an actual research phase that it's like, "OK, here are the technologies that we need to prove out, here are some prototypes we need, we think we need to make to make us believe that this device makes sense." There was never, during that phase, there was never really a plan to make a product. It was just kind of like gathering information, doing prototyping of critical technologies, proving them out, stuff like that, so that takes a while. And then after you do all that, you decide, OK, we want to make this thing happen. Let's start actually doing the development part of that, then that takes a year and a half, or something like that. So, depending on which, how you want to count things, it could have been three, four, five years, it could have been a year and a half, you know. But I would say it's just that we're constantly investigating different things, so it's kind of hard to put a timeline on it.

Griffais: For us, working on these things is very incremental and very gradual. So, in a sense, this all started 15 years ago when we got into hardware, because Steam Machine is actually one of the first things we worked on. The work on SteamOS that we started back then, you can draw a straight line through from that to where we are now: the work on inputs, even you know, the work on Steam Machine with OEMs, they taught us a bunch of stuff that we're leveraging right now. We're always trying to make sure that when we build something, we can reuse it in the future, and we don't have to start from scratch. And so, even back then, everything we were doing with SteamOS is fully represented in the current experience, and we're just building from here.

Windows support incoming

Freedman: Is Windows support still the same on Steam Deck? Will you be issuing new drivers?

Griffais: That's our goal. Right now, we're still working on certain drivers, you know, around Bluetooth and stuff, but that's definitely our goal. And we've been talking to AMD about the best way for users to get the graphics drivers as well, because I think it's pretty important that they can get at the latest fixes.

Aldehayyat: Yeah, but the model will be very similar to the way the Steam Deck Windows drivers work. It's going to take us a little bit of time after launch to get all the drivers lined up, but the general process of us publishing the drivers on our website will probably be the same.

Freedman: Is Valve still working on dual boot with Windows 11? I mean, the Windows resources page I just mentioned, it says the Steam Deck is capable, the OS installer wasn't ready yet.

Griffais: So it's something we're working towards. We don't have dual boot, an easy dual boot wizard plumbed right now. There's a few ways that you go about it, but right now, most of them include some manual steps where you repartition your disks and resize stuff by hand. We want to make that process easier in the future. But the thing that we're doing right now with SteamOS is we want to make sure that if someone builds a PC like a Steam machine, so something that has an AMD discrete GPU, and then whatever other parts they pick, they can choose whatever segment of GPU they want.

We're going to have a SteamOS USB install drive that they can just install SteamOS onto, so that they can have basically the same experience as the Steam Machine. It's pretty similar to how you would re-image a Steam Deck. But we want to make sure that if you're building from parts, that you have that option. So, we'll also be making that available at the same time.

Freedman: Will that mean at the same time as the Windows drivers, or—

Griffais: Just the product launch.

There's already SteamOS images out there that will work there, but we just want to make sure that we have one that has all the latest OS components that we're shipping at launch with Steam Machine, so that everything is ready from the get-go for that sort of experience.

Valve's new reservation system

Freedman: The reservation system you're using, I think it's the most radical one I've ever seen from Valve. I totally get why you're doing it. How'd you come up with that internally?

Griffais: Just lots of discussion. The reservation system that we originally came up with for the Steam Deck was also born of the same sort of discussion. We're talking about, "OK, here's the situation: how many units we have, what the user experience is going to be on purchase. Working back from that, how can we improve the user experience?" We see a lot of users stressed out about trying to secure supply for other products. We just see what's happening in the wild, and how people are frustrated with, like, not knowing where to get something, or having to periodically just recheck online retailers, trying to figure out.

I mean, my experience trying to buy PS5 kind of painted a lot of that stuff, in a sense. But the current iteration on the reservation system here, was just similar. We worked from, OK, we think the broad strokes of the system are good, but there's still an effect where people are rushing at the door, trying to refresh. Our websites might have problems, and then that seems unfair to people that run into that, right? We want to make sure that there's an even playing field initially, and then work from there. So, yeah, it's all I think based on discussions and user feedback.

Freedman: The blog post says that the people who get on the reservation queue, separate from the waitlist, could last through the end of the year. Is that all the first production run?

Griffais: We're constantly producing and trying to secure additional parts and stuff. There's not really discrete, you know, different runs and different segments, so it's a very linear thing. But for sure, depending on how many people sign up, it might extend into time frames that we're not really even sure of, because supply is so interesting.

Aldehayyat: It was just six months, as far as we were willing to make a prediction. As Pierre-Loup said, if there's more demand, we obviously are planning to make more, and so maybe there'll be another waitlist or something. But six months, we felt, is the appropriate amount of time to kind of put a cap on the waitlist, essentially,

Griffais: The interesting and I guess hard thing is that getting supply right now also means getting a wide variety of different prices, right? So it's possible that you would be able to make more, but in a way that the pricing ends up being different. And so we're still trying to figure that out, because if there's ever a bunch of people that want the machine, but the supply is not there on the back end, we'll have to make hard decisions about what are we doing to secure more supply, and does it still result with the product at this price, or would we have to rethink that.

Because we don't really know how the situation is going to continue to evolve. You know, maybe things are going to go back down, and then it's all good, and it can continue to go like that. But maybe not, and so I guess what we're trying to convey with this blog post is that it seems like all bets are off, and we're going to work through it just with the users as well.

[Interview ends]

With no new GPUs or major mobile CPU platform launches surrounding the show, the laptop announcements at Computex this year fell into two disparate categories, appealing to users with very different budgets. There were devices trying to compete with the MacBook Neo, like Dell’s attractive XPS 13 ($599 to start, with a limited-time student discount) and Qualcomm’s Snapdragon C platform, which promises laptops as low as $300 (we saw it in person in the as-yet-unpriced Acer Aspire Go 15). Both of those, like Apple’s competing Neo, will start with just 8GB of RAM (actually, Acer says “up to 8GB”), thanks to the ongoing AI-driven memory crisis.

On the opposite end of the Computex laptop spectrum, there was, of course, Nvidia’s long-anticipated Windows-on-Arm announcement: RTX Spark Superchip for laptops (formerly N1X), which pairs a 20-core Arm CPU with 6,144 CUDA cores. And since Nvidia and its partners (both laptop makers and Microsoft) are pitching RTX Spark as the agentic computing platform of the future, Spark laptops get all the RAM that portable, local AI PCs could ask for – up to 128GB of LPDDR5X.

The specs sound impressive, but let’s just say I am curious to see how Microsoft and Nvidia’s partnership will implement local agents into Windows 11 in the coming months, and how much useful and intuitive functionality will exist specifically for RTX Spark laptops by the time they actually launch. It’s not like Microsoft has the best track record when it comes to Copilot features, both in Windows and elsewhere. At Build, Microsoft focused on running OpenClaw in Windows with execution containers that create boundaries, such as certain files or programs.

And while we don’t yet know pricing for the RTX Spark laptops, with similarly configured DGX Spark desktops selling for close to $5,000, it’s a safe bet that high-end RTX Spark laptops are going to be well out of the price range of most consumers – although lesser versions based on N1 silicon (and with far less RAM) may slip below the $2,000 mark. While gaming performance on top-end Spark laptops is expected to be roughly similar to an RTX 5070, I suspect pricing will make the platform a tough sell for those primarily interested in gaming, just as it is for AMD’s Strix Halo – and AMD’s x86 silicon doesn’t have the gaming complications that Spark’s Arm CPU will have to navigate.

So it feels like AI developers (and I suppose well-heeled AI tinkerers) will be the primary early adopters of RTX Spark laptops when they begin shipping (this fall, according to Nvidia). By then, we’ll also likely know more about both Qualcomm’s Snapdragon C SoC and Dell’s Intel Wildcat Lake-powered XPS 13 (including how much it will cost to configure it above the baseline 8GB of RAM or with a Panther Lake processor). But as limiting and backward-looking as an 8GB laptop may be in 2026, so far I find these more traditional, more affordable laptops more interesting than RTX Spark – in part because while I don’t know exactly how they will perform, I do know generally what I will and won’t be able to do with them when they arrive.

And given how expensive seemingly everything is these days, it’s nice to see a few companies focused on making things look and feel nice while remaining relatively affordable. It may have taken a big push from Apple and its MacBook Neo. But if Windows wants to remain relevant as a platform, it needs both forward-looking options like RTX Spark and affordable options that still look and feel great, like Dell’s XPS 13. I just wish the latter could happen with more RAM than the laptop I bought in early 2019.

Imec's semiconductor process technology roadmap sets the general direction of industry development and showcases the challenges the sector is set to face over the next few decades. The roadmap gives us an idea of the timelines for the next major process nodes and transistor architectures the company will research and develop in cooperation with industry giants, such as TSMC, Intel, Nvidia, AMD, Samsung, and ASML, among many others.

Imec's latest production node roadmap shows that the international research and development organization envisions 3 angstrom-class (0.3nm) fabrication technologies by 2038, but expects contact poly pitch (CPP) to stop scaling at A10 in 2030. While things might not be looking great for Moore's Law for imec, to continue scaling the chipmaker will need to adopt new technologies, such as CFET transistors and likely Hyper-NA EUV Lithography systems.

GAA transistors have seven years left

As the production of semiconductors becomes substantially more complicated, chipmakers no longer introduce all-new process technologies every couple of years. Instead, they typically roll out a new node generation every three years, with annual incremental enhancements in between. TSMC ramped N3B production in 2023, then followed it up with N3E in 2024, and N3P in 2025. Intel planned to follow the same pattern with 20A in 2024 (which was canceled), 18A in 2025, and 18A-P in 2027.

Next-generation process technologies will continue to emerge at similar cadences, according to imec's roadmap.

Interuniversity Microelectronics Centre considers that we now live in the 2nm-class era (N2) with contact poly pitch (CPP) of around 48nm, as well as cell height of around 132nm and 6 metal tracks. The reality may be a bit different as Intel's 18A has a CPP of 50nm as well as a cell height of 160nm (high density) or 190nm (high performance), whereas TSMC's N3 can boast with a CPP of 45nm. N2 (or 18A, if you wish) will be followed by its performance and efficiency-enhanced version in the next couple of years, which is in line with how the industry has been operating in recent years.

"Of course, we are going to extend our logic roadmap to the next generation beyond N2," said Julien Ryckaert, vice president of R&D at imec. "As you know, in two nanometers we have already jumped into a new technology device paradigm in the nanosheet era, and that is going to bring us deep into the Angstrom node."

Imec expects the A14-class to emerge in 2028. TSMC expects to start high-volume manufacturing using A14 in late 2028, so the actual ramp will happen in 2029. Intel's 14A follows the same pattern. With A14, imec projects CPP to shrink to 45nm and cell height to drop to 115nm and 5.5 metal tracks. Around 2030–2031, imec expects an A10-class technology — or a 1nm-class — with a 42 nm CPP and 98 nm cell height, which will still rely on a 5.5-track architecture.

It is noteworthy that gate-all-around (GAA) transistor-based nodes can be implemented either with conventional frontside power delivery networks or with backside power delivery, which reflects both imec's and TSMC's belief that BSPDN will not immediately become mandatory across all applications, as many of them do not benefit from it.

It is also worth mentioning that imec expects High-NA EUV tools insertion at A14, which is in line with Intel's plans, but not with TSMC's plans.

CFET insertion in the early 2030s

The roadmap becomes particularly interesting at the A7 generation, which imec expects to come in 2033. While CPP remains at 42 nm, cell height drops to roughly 80nm, and the standard-cell architecture moves to 4.5 tracks. More importantly, A7 is the point where CFET emerges as a serious candidate for production insertion. Instead of placing n-type and p-type transistors side by side, CFET stacks them vertically, which adds a third dimension to transistor scaling.

Imec’s roadmap explicitly positions CFET as the leading contender for A7, which means that the organization sees conventional nanosheet architectures approaching practical scaling limits in the early 2030s. Yet, since A7's CPP does not change from A10, chipmakers may or may not adopt the all-new transistor architecture at A7. Also note that imec seems to consider BSPDN as mandatory for CFETs.

"Moving into A7, the seventh-angstrom generation, which is the fourth generation of nanosheet, we see more and more challenges in scaling the conventional nanosheet device technology," Ryckaert said. "There is a contender that we have already mentioned as well in previous presentations, where CFET could start emerging as the solution for the next era of transistors."

Beyond A7, the roadmap seems to depend on CFET evolution. The A5 generation, expected in 2035–2036, retains a 42nm CPP but reduces cell height to about 64nm using a 4-track library. By 2038, the roadmap reaches A3 with a 39nm CPP and 50nm cell height. At this point, imec envisions sequential CFET implementations and eventually bonded CFET structures that further exploit vertical integration. In fact, vertical integration seems to be the new way we should look at Moore's Law's evolution. Meanwhile, to get to a 39nm CPP and 50nm cell height, chipmakers might need to use Hyper-NA EUV lithography scanners, according to imec.

Redefining Moore's Law

The most interesting thing about imec's roadmap is that it essentially redefines what Moore's Law means. Traditionally, we consider Moore's Law as the observation that the number of transistors on a chip of a certain size doubles every 18 – 24 months, as they are getting smaller.

The fact that imec shows CPP stuck at 42 nm from A10 through A5 is almost an admission that classical transistor scaling is running out of steam, and future density gains must come from vertical integration. In the imec roadmap, transistors are still getting denser, but not exactly because individual transistors are shrinking at the same pace they used to decades ago, but because chip designers can fit more logic gates into a given area because of different transistor architectures, 3D integration, or backside power delivery.

As a result, in the coming years, we may no longer care how many nanometers a gate pitch is, or individual transistors, but rather the size of a standard cell. After all, when companies like AMD, Intel, or Nvidia design a chip, they do not place individual transistors, but actual blocks built from standard cells. Yet, calculating the size of a standard cell is complicated because while cell height is fixed, its width is not, and depends on the actual function.

Library height × CPP is not the size of a specific standard cell. It is the fundamental footprint unit of a standard-cell library and a widely used proxy for logic density. Actual standard cells have that height, but their width varies depending on function. Instead, the industry uses such metrics as logic cell area (standard-cell footprint) — Cell Height × CPP — that measures the actual footprint of the logic building blocks that designers use, not just the dimensions of individual transistors.

The transition from 6-track cells at N2 to 3-track cells at A3 illustrates how future density gains will rely as much on shrinking standard-cell height as on reducing transistor pitch. As a result, despite the fact that CPP shrinkage is expected to stall for years, logic cell area is set to decrease; designers will be able to extract transistor density gain from future nodes, proving that Moore's Law is still here.

Hetrogenous Large-Scale Integration × Cross-Technology Co-Optimization

Given all the changes that the semiconductor industry is already experiencing and what is set to come, imec believes the sector is entering a new era that it calls Heterogeneous Large-Scale Integration (HLSI). The concept reflects a shift away from traditional VLSI scaling, where progress largely depended on the evolution of transistors and increasing transistor density, toward a model that combines multiple technologies within a single compute platform.

Future systems will rely on heterogeneous integration of logic, memory, power-delivery circuitry, and optical I/O using advanced 3D and 3D + 2.5D packaging technologies, according to imec's predictions. Of course, the organization expects AI workloads to become the main driver of semiconductor demand, so expect both compute architectures and the semiconductor industry to evolve in a direction that satisfies the needs of AI applications.

"As we will move deeper into AI-driven architecture, we will need to double down on the heterogeneity that technology offers, and this will probably move the VLSI paradigm to the HLSI paradigm, the Heterogeneous Large Scale Integration," Ryckaert said.

To optimize future platforms on the system level rather than develop individual components in isolation, imec has established its Cross-Technology Co-Optimization (XTCO) framework, which could be seen as an integral part of the HLSI vision. XTCO is designed to wed development logic, memory, interconnects, power delivery, cooling, and packaging, and assesses their impact on key system metrics such as compute density, energy efficiency, thermal performance, and memory.

It remains to be seen how this is going to work out, if at all, given the fact that logic process technologies are developed at foundries, memory technologies are designed at DRAM makers, whereas cooling is developed at third parties like CoolIt or Frore Systems.

Power and cooling

As individual chips get denser and more power-hungry, power delivery is set to become a critical bottleneck, which is why all leading chipmakers — Intel, Samsung, and TSMC — are implementing or set to implement backside power delivery technologies and integrated voltage regulators.

Imec expects future AI accelerators and CPUs to rely on a combination of BSPDN, IVRs, embedded capacitors, and advanced power semiconductors to reduce losses and improve efficiency. Over time, more power-conversion stages are expected to migrate from racks and motherboards into packages themselves to deliver cleaner power directly to transistors.

Since we are talking about multi-chiplet packages consuming kilowatts of power, the importance of cooling is hard to overestimate. For sure, 3D stacking and CFETs will not make cooling any easier because thermal power density is set to increase linearly with the number of transistors, thermal resistance is set to increase, and local hotspots will become an even bigger problem than they are today. As a result, imec expects future compute platforms to rely on a combination of more advanced cooling technologies, improved heat spreading, fine-grained thermal sensors, and system-level thermal optimization techniques.

"At the end of the day, what we need to achieve is a reduced energy cost of data movement. We need to improve the TDP for better thermal management," Ryckaert said. "We need to improve the efficiency of the power delivery, and we need to obviously increase the compute density to improve the functionality."

In short, useful future scaling will depend not only on the ability to build transistors and increase their density, but on delivering power efficiently and removing heat effectively.

Paving the path forward

Imec's latest semiconductor roadmap projects logic process technologies all the way to A3 generation around 2038 and argues that Moore's Law can continue despite the slowing pace of traditional transistor scaling. While the Dennard scaling for semiconductors is over, there are plenty of interesting things incoming.

According to the roadmap, conventional gate-all-around nanosheet transistors should remain viable through A10, while CFET architectures become a candidate for production insertion at the A7 generation around 2033. Meanwhile, future transistor density gains are expected to come from vertical integration, reduced standard-cell footprints, and eventually sequential and bonded CFET structures rather than from aggressive shrinking of transistor dimensions.

Solidigm is arguably one of the most mysterious storage companies in the industry today. The company is a wholly owned subsidiary of SK hynix, yet unlike its parent company, which produces charge-trap flash memory, it uses floating-gate 3D NAND memory that it develops and manufactures internally at a dedicated fab in Dalian, China.

Solidigm originates from Intel's Non-Volatile Memory Solutions Group (NSG), the company's NAND and SSD business unit, which used to have a unique technology strategy that differed from that of other flash and drive producers. To that end, it is not surprising that Solidigm also has a unique positioning as it only offers data center drives, most of which are based on floating-gate memory and proprietary in-house designed controllers. Furthermore, Solidigm is a fully vertically integrated company.

At Computex 2026, we sat down with Avi Shetty, who is vice president of AI ecosystem, Solutions & Market Enablement at Solidigm. Before his current position at Solidigm, he spent 14.5 years at Intel's storage division, so he has deep knowledge both about technology and the market. During our conversation, we discussed how Solidigm keeps evolving, including floating-gate NAND memory, advanced packaging technologies, next-generation SSDs, liquid-cooled SSDs, and more.

Anton Shilov: Could you introduce yourself to our readers and describe what do you do at Solidigm?

Avi Shetty: My name is Avi Shetty. I work at Solidigm, where I help lead AI solutions and ecosystem initiatives. My team works with global platform providers, software ISVs, and ODMs to ensure Solidigm solutions are validated, benchmarked, and included in reference designs at both the device and cluster levels, enabling customers to fully utilize our products.

A part of SK hynix that acts independently

Anton Shilov: You were previously a part of Intel. How is the integration going? Are you now fully integrated part of SK hynix, or do you operate independently?

Avi Shetty: Let me provide some background. While Solidigm was established in December 2021, our history goes back decades. Many of us came from Intel's Non-Volatile Memory Solutions Group (NSG), which developed Intel’s NAND SSDs for both client and data center markets.

In 2021, SK hynix acquired Intel’s NAND and SSD business and established Solidigm. Since December 2021, we have operated as a wholly owned U.S. subsidiary of SK hynix, headquartered in Rancho Cordova, California.

Anton Shilov: So, you are part of SK hynix, but still maintain a degree of independence?

Avi Shetty: Absolutely. We operate as an independent subsidiary of SK hynix. Our strategy is focused entirely on enterprise SSDs. Every bit of [floating gate] NAND [at our fab in Dalian, China] we produce goes into enterprise storage solutions.

This is one of the ways we differentiate ourselves from competitors such as Samsung and Micron, which also serve mobile and client markets. We made a deliberate decision to focus exclusively on enterprise storage and AI.

We are also fully vertically integrated. We manufacture our own NAND, develop our own controllers, write our own firmware, and design our own SSDs. While we work with manufacturing partners to build products, we control the entire technology stack.

I also believe we are the only company with access to two different NAND architectures. Through SK hynix we have access to charge trap flash (CTF) technology, and we continue to develop floating gate NAND technology for our high-density QLC SSD products.

Anton Shilov: What is Solidigm's current share of the enterprise SSD market?

Avi Shetty: Approximately 24%. That is enterprise SSDs only. We do not participate in any other NAND markets. As of the first quarter of 2025, plus or minus a few percentage points, our measured enterprise SSD market share is approximately 24%. We evaluate market-share data quarterly and semiannually, and that is the latest figure we’ve publicly discussed.

Anton Shilov: How much of your business today is concentrated in high-capacity SSDs versus higher-performance products?

Avi Shetty: High-density SSDs now represent a significant portion of our business. Because Solidigm is privately held, we do not publicly disclose that breakdown. We report our financial metrics through our parent company, SK hynix.

What I can tell you is that both our 61TB-class and 122TB-class products became customer favorites almost immediately after launch. Demand for high-density storage has been extremely strong.

Anton Shilov: I assume you also work directly with hyperscalers?

Avi Shetty: We work with a broad range of customers globally. That includes U.S. cloud service providers, Chinese cloud service providers, OEMs around the world, NeoCloud providers, software ISVs, and channel partners. We maintain customer support, engineering, and sales organizations globally. Our business spans the Americas, EMEA, China, and the rest of Asia-Pacific.

Anton Shilov: Which customer segment represents the largest opportunity for growth right now? Traditional cloud providers or something else?

Avi Shetty: We intentionally maintain a diversified customer base.

What is interesting is how quickly new segments emerge. For example, the NeoCloud market has existed for some time, but AI-focused infrastructure providers such as CoreWeave, Lambda, Crusoe, and Nebius have become much more important over the last two years.

Before the AI boom, these companies represented only a small portion of demand. Today, they are becoming a meaningful part of the market.

As AI infrastructure continues to expand, Solidigm is adapting both its customer strategy and product portfolio to support these emerging deployments while continuing to serve our traditional customers.

Floating gate NAND in 2026

CTF NAND used by major memory makers has approached 276 - 286 active layers, whereas Solidigm's floating gate flash is still at 192 layers, meaning that the company is somewhat behind some of its rivals in terms of active layers as of mid-2026. It is set to catch up with its next generation that will have over 200 layers, but only in the second half of this year. However, floating gate NAND memory still has a number of advantages over CTF, particularly for applications that Solidigm targets.

Floating gate uses a conductive polysilicon island to store charge, which provides excellent cell isolation — charge stays well-contained and is less likely to spread to or interfere with neighboring cells — and this is particularly important for 3D QLC NAND with very high layer counts. In addition, Solidigm claims that floating gate gives a strong voltage threshold window and better cell isolation, which enables the company to keep scaling QLC more while maintaining good reliability.

Anton Shilov: Are you still producing floating gate NAND, and do you intend to continue?

Avi Shetty: Absolutely. We introduced our first QLC foating gate NAND product in 2018, and today we are on our fourth generation of QLC NAND.

Our flagship high-capacity product currently ships with 192-layer floating gate NAND technology and powers our 122TB SSD.

Anton Shilov: Haven't you also announced a larger drive?

Avi Shetty: We have announced a higher-capacity product and expect it to become available later this year.

Anton Shilov: The 256TB-class drive?

Avi Shetty: Correct. Approximately 245TB usable capacity.

Anton Shilov: So you are going to have a roughly 245TB SSD available this year?

Avi Shetty: Correct.

Anton Shilov: What advantages does Floating-Gate NAND provide?

Avi Shetty: Floating gate NAND gives us scalability. We have consistently been first in the industry to push storage density in standard form factors. We were the first to introduce a 30TB SSD, then a 60TB SSD, and later a 122TB SSD.

We have been shipping the 122TB drive for nearly five quarters. We launched it in the fourth quarter of 2024, and it has since become our flagship product. It is probably our most popular product of 2025.

The reason customers like the 122TB drive is efficiency. When you look at AI data centers, customers want low power consumption, scalability, and performance. While this particular product is a PCIe Gen4 solution, our roadmap continues to increase both density and bandwidth. You will see future products based on PCIe Gen5 and PCIe Gen6.

The real attraction of the 122TB SSD is scale. In a 1U server, you can install 24 of these drives and get nearly 3PB of storage in a single rack unit.

If you look at the AI data pipeline — from training to archiving — the first and last stages require massive datasets. That is where these high-capacity SSDs are being deployed today.

Now we are also seeing growing demand from inference deployments. Inference can run in core data centers or in edge and back-office environments. Those deployments require storage that can efficiently feed GPUs and support workloads such as context storage and KV cache management. High-density SSDs help provide the capacity required for those applications.

Next-generation SSDs: PCIe Gen6 drives with liquid cooling

Anton Shilov: You mentioned PCIe Gen5 and Gen6 [next-generation drives]. I assume you are referring both to next PCIe generations and future NAND generations?

Avi Shetty: Both.

We maintain separate technology and product roadmaps. Earlier, I mentioned that our current QLC NAND is our 4^th Generation technology based on 192 layers. We will continue investing in future NAND generations as well.

On the product side, we are talking about PCIe generations. We currently ship both PCIe Gen4 and PCIe Gen5 SSDs. All of our TLC products are PCIe Gen5 today, while our QLC lineup currently remains PCIe Gen4.

Future QLC products will move to PCIe Gen5, and eventually, we will introduce PCIe Gen6 SSDs as platform vendors such as AMD, Intel, and Nvidia adopt PCIe Gen6 in their systems.

Anton Shilov: You mentioned PCIe Gen6 SSDs. You have not shipped one yet, correct?

Avi Shetty: Correct. PCIe Gen6 products are part of our future roadmap.

Anton Shilov: How close are they?

Avi Shetty: We are not making product announcements at Computex, but you will hear more from us soon.

Anton Shilov: At the moment there is really only one platform that can take advantage of them anyway. Well, two, if you consider Nvidia Vera.

Avi Shetty: That is part of the equation. When we evaluate our roadmap, we consider demand, platform readiness, and overall value to customers.

For example, we have what we call a refresh philosophy. We may introduce a PCIe Gen4 refresh or a PCIe Gen5 refresh that lowers cost or improves efficiency rather than immediately moving to a new PCIe generation.

The question is whether customers gain more value from Gen6 today or from a more mature, lower-cost Gen5 product. Those are the kinds of decisions our planning teams evaluate.

What I can say is that Solidigm maintains a full roadmap covering PCIe Gen4, Gen5, and future Gen6 SSDs across all major form factors, including U.2, E1.S, E3.S, and other EDSFF variants. Our portfolio spans capacities from 2TB all the way to 122TB.

Anton Shilov: Launching an all-new product early still gives you time to validate products with platform vendors.

Avi Shetty: Absolutely. We already work closely with platform providers to validate prototypes long before products are launched. Our engineering teams participate in interoperability events and PCI-SIG workshops to ensure products are ready when platforms become available.

Anton Shilov: That is actually interesting because PCIe Gen6 interoperability workshops have been delayed multiple times. Back in 2024, people expected the ecosystem to move much faster and interoperability workshops to start in 2024, with the list of compatible products emerging in 2025.

Avi Shetty: That is true. A lot depends on platform readiness and ecosystem scaling. PCIe Gen6 by itself is not enough. This is my personal opinion, but to fully benefit from Gen6 storage performance, the industry must also address cooling. That is one reason we invested heavily in liquid-cooled storage.

Last year, we introduced what we believe was the world's first liquid-cooled storage solution for Nvidia environments. It used E1.S PCIe Gen5 SSDs with direct liquid cooling. Historically, liquid cooling was focused on CPUs and GPUs. We extended it to storage by allowing coolant to flow through a cold plate attached to the SSD. The cold plate removes heat directly from the drive. To fully exploit PCIe Gen6 performance, the ecosystem must develop those kinds of technologies as well.

Anton Shilov: So you believe PCIe Gen6 SSDs will require liquid cooling?

Avi Shetty: At least in high-performance AI environments, particularly Nvidia-based deployments, we believe liquid cooling will be necessary.

Next-generation SSDs: PLC NAND

Anton Shilov: Will future NAND generations include both TLC and QLC? And what about PLC?

Avi Shetty: Never say never. We demonstrated PLC technology using floating gate NAND at the Flash Memory Summit several years ago. However, this business requires factory optimization and maintaining a manageable number of SKUs to maximize utilization and profitability.

That said, there absolutely will be opportunities for PLC. We have not announced any specific products or timelines, but there is active PLC development underway inside Solidigm.

Anton Shilov: That is interesting. However, PLC by itself only increases capacity by about 20% compared to QLC and at the same time requires significantly more sophisticated controllers and error correction.

Avi Shetty: That is true. However, those same concerns existed during every previous transition: from SLC to MLC, MLC to TLC, and TLC to QLC.

We were the first company to commercialize QLC NAND. Initially, many competitors questioned its value. Today, the industry increasingly recognizes the total-cost-of-ownership advantages that QLC provides, and multiple vendors now offer QLC products. I think the same process will occur with PLC.

It is also important to consider the broader market. Roughly 80% of storage capacity worldwide is still deployed on hard drives. PLC does not necessarily need to replace QLC on a one-to-one basis. Instead, it can create new opportunities where the advantages of solid-state storage — lower power consumption, higher density, smaller physical footprint, and lower total cost of ownership — become compelling.

You will likely see future solution development involving software partners that help address some of the limitations you are describing.

Anton Shilov: Do you expect retention characteristics to become a major challenge with PLC NAND?

Avi Shetty: Of course. PLC is a new technology, and retention characteristics will differ from what we see with QLC today.

The same is true across all NAND types. SLC, MLC, TLC, QLC, and eventually PLC all have different retention characteristics based on the underlying technology. The existence of those challenges does not mean we stop exploring future solutions. We will continue investing in that area.

Advanced packaging for NAND

Anton Shilov: As I mentioned, PLC only increases capacity by about 20%. Advanced packaging may ultimately have a much larger impact on SSD capacity. Could you discuss where packaging technology stands today and where it is headed?

Avi Shetty: Absolutely. Let me use our current products as an example. The 122TB SSD represents a significant packaging achievement. It is a U.2 drive with 48 NAND packages. Each package contains a 22-die stack. Each die is a 1.33Tb QLC device. Those 22-die stacks are what enable us to reach 122TB in a standard form factor.

Packaging technology remains one of our core investments. We continue developing technologies that allow us to place more dies into each package and deliver higher capacities to customers.

Anton Shilov: What about increasing the number of dies per package?

Avi Shetty: That is one of the primary ways to increase density. You can either increase die capacity or increase the number of dies per package. We intend to pursue both approaches.

Anton Shilov: How many dies per package do you think remain practical?

Avi Shetty: Today we are at 22. Future products will go beyond that, although I cannot discuss specific numbers.

Anton Shilov: What did previous generations use?

Avi Shetty: Depending on capacity requirements, previous products used 4-, 8-, or 16-die stacks. Of course, we are talking about a single NAND package in each case.

Storage-Class Memory, Optane, and Nvidia's Storage Next

Anton Shilov: What about storage-class memory?

Avi Shetty: Like Optane?

Anton Shilov: Not necessarily Optane itself, but something similar — something faster than NAND flash, yet capable of offering significantly higher density than DRAM at a lower cost.

Avi Shetty: Understood. Let me frame it from the perspective of the problem we are trying to solve. If you are asking whether Solidigm is developing a storage-class memory technology similar to Optane, then the answer today is no.

What we are focused on is addressing the requirements emerging from Nvidia's Storage Next initiative. The fundamental challenge is bandwidth. HBM is extremely fast, but it is also expensive and difficult to scale economically. As AI systems continue to grow, the industry needs additional memory and storage tiers that provide greater capacity at lower cost. That creates demand for NAND-based solutions that remain non-volatile while delivering improved latency and bandwidth characteristics.

We have not made any public announcements regarding storage-class memory technologies, but we continuously evaluate future technologies and architectural approaches.

Anton Shilov: So you are exploring concepts that could potentially bridge the gap between traditional NAND and memory?

Avi Shetty: We are evaluating a wide range of technologies that could help us continue delivering leadership products to our customers. When and if we have something to announce, we will do so publicly. At this point, however, we have nothing to disclose.

Anton Shilov: So storage-class memory is not currently a product category that Solidigm is actively pursuing?

Avi Shetty: If you are specifically referring to something similar to Optane, then no.

Optane was based on a fundamentally different technology. It was not NAND. It relied on a phase-change-memory-derived architecture and represented a completely different storage medium. We are not pursuing that type of technology today. What we are investing in is future NAND technology.

Anton Shilov: You think that future NAND technologies could eventually move closer to that space?

Avi Shetty: Exactly. Future NAND innovations could help narrow the gap between HBM, DRAM, and the next storage tier. That’s certainly one of the directions the industry is evaluating as AI systems continue to demand larger memory pools and greater bandwidth.

For heavy AI users, the economics of the current boom are starting to bite. Over the past year, major labs have nudged prices upward while tightening the screws on usage — whether through stricter rate limits, smaller context windows on lower tiers, or the gradual reshuffling of features behind more expensive plans. Even where per-token costs have fallen in headline terms, the reality for users is more complicated: higher volumes, more complex workflows, and new tooling expectations mean monthly bills are creeping up, not down.

At the same time, open-weight models have improved rapidly, consumer hardware has become more capable, and tools like LM Studio, Ollama, and llama.cpp have made local deployment far more accessible than it was even a year ago. The result is a renaissance in running models on your own machines.

I’m one of the people who has taken the leap myself. In mid-March, I bought a GMKtech mini PC with an AMD Ryzen AI Max+ 395 chip and 96GB of RAM. The purchase — at the time something like £1,500 ($2,000) — was a calculated decision. The kinds of volume I wanted AI models to run through would have blown through my current subscriptions to AI models (I have a ChatGPT Plus and GLM Coding Lite plan, which combined cost me around $23 a month), and forced me onto the higher-cost monthly plans, or API-based inference.

Going local

The decision I had to make was a simple one: did I want to spend that money on a subscription that would cost me several thousand dollars over the course of a year, and end up having to pay a recurring cost for years to come to an AI lab that would likely hike prices? Or did I want to pay a one-off charge for my own hardware and a smaller ongoing cost for electricity?

I chose the latter.

When the mini PC arrived, setting it up was relatively easy — though, fully disclosure, only possible with the help of the full-fat AI models I pay for from the big labs.

The system I set up on my hardware was designed to try and help me keep track of the constantly changing news in the areas I cover for sites like Tom’s Hardware Premium and others. It takes RSS feeds and ingests the contents of stories in key beats that I cover, then grades them against a digital ‘brain’ made of how I think about the world and what I report on, generated by analyzing nearly 2,000 of my past stories over the previous four years.

When it finds candidates that are potentially interesting, those stories are ‘assigned’ to AI beat reporters, who then read around the subject on the web and produce pitches, similar to those that I send to my editors here and elsewhere. Those AI reporters then send their pitches to AI editors, who engage in a conversation with the reporters to fine-tune the idea’s framing, before presenting me with a couple of paragraphs of a broad idea that is meant to be tailored to my tastes via Telegram.

The outputs are far from perfect — I’d equate them to a newly-graduated student that I teach in terms of their taste and depth — but they’re a good starting point for me to learn about what’s important on a given day, and a provocation for how I might think about framing those events. For the kind of things I’m using AI for, even the bleeding-edge frontier models aren’t much better than the local LLM options, though I appreciate that there’s a bigger gap when thinking about coding.

Setup

The whole process uses LM Studio and runs on a mix of quantized models, generally of Qwen3.5 and 3.6. Because I’m running multiple editor and reporter processes in parallel, the parameter count on each model may seem undersized for the 96GB of RAM that my AMD GPU can access (after some BIOS tweaks): I’m using a mix of Qwen’s straightforward 3.5-9B model, as well as Jackrong’s Qwen-3.5-9B-GLM-5.1-Distilled and Qwopus-3.5-9B models. In part, that’s because thousands of calls on the models take place every day, and in order to keep on top of the backlog of stories to look through and ‘discuss,’ throughput needs to be high.

Since starting the locally-hosted project in mid-March, my local LLMs have burned through anywhere between 20 million and 50 million tokens a day alone. (Alongside troubleshooting with paid-for and hosted models, as well as parallel projects I run on my GLM Coding plan subscription, I’m using between 50-100 million tokens on an average day.)

For this kind of reading, thinking, analyzing, and re-presenting, local models work brilliantly. They have high throughput but are working in the background, meaning that the slower time to first token that many local LLM users complain about in comparison to big lab-hosted alternatives isn’t an issue for me. The model runs 24 hours a day, and if it takes two seconds or two minutes to process the prompts (between 7,000 and 18,000 tokens, depending on whether it’s a reporter or editor and how far through the discussion process it is), it doesn’t bother me. Tokens per second won’t impress those talking a big game about local LLMs on social media: the models handle the prompts at around 300 tok/s, while the output is a much slower 5-10 tok/s. Yet it works for me.

Split throughput

But for now, I’m still keeping my big lab subscriptions — though I’m using them differently. My GLM Coding plan, bought around Christmastime and which lasts for a year, is used alongside Codex through my OpenAI subscription to troubleshoot and tinker with the projects when issues arise. My coding knowledge stopped at some QuickBASIC and Delphi in my teenage years, so having the ability to call on them (and an OpenCode Go subscription I occasionally dip into) to fix problems is invaluable.

However, the proportion of my AI use has shifted significantly. Two-thirds or more of my total token use is now locally-hosted LLMs I run myself. And as local models continue to develop their abilities and the gap between them and the state of the art from big labs closes, I can envisage that it will increase. For instance, I recently vibe-coded a web interface for LM Studio that allows me to use it as a regular chatbot just this last week. And in just two months, the amount I’ve saved if I had run that project every day through API calls on GPT-5.4-mini, arguably a comparable model, is three-quarters of the cost of that first mini PC — around $1,500.

In hindsight, I wish I’d bought the 128GB version of my mini PC, which is why I decided around two weeks ago, before another memory-based price hike, to buy the bigger version. The reason was a simple one: the volume of queries I was putting through my 96GB box was starting to hit the limits, and I wanted to expand the project. I also wanted to test out locally hosted coding harnesses like Claude Code or Hermes using a local model.

The experience, trials, and tribulations from my first mini PC setup helped enormously with setting up the second PC. Token count has increased from 20-50 million tokens a day to more like 50-80 million tokens a day. I offloaded part of that massive ingest and analysis project onto the new hardware and put it onto more powerful 27B and 36B parameter models (through the Final-Bench-Darwin-36B-Opus model), freeing up space on my first mini PC and allowing me to test the idea of a locally-hosted Claude Code-style project with the spare space on my second mini PC.

That has been less successful — at least so far. Underpinning the coding harness with GLM-4.7-Flash works, but feels like too big a step back in model generations to be a useful tradeoff. Larger Qwen models have so far got stuck in their own thinking (or burned through a lot of the context window they’re assigned), but I’m considering swapping Claude Code out for a lighter-weight, less context-heavy harness and giving it a proper run.

Frontier models are getting more expensive

The bet I’ve made is a simple one: subscription and API prices from frontier labs — with the odd outlier like DeepSeek excepted — are only going to go in one direction as the companies behind them realize they need to make a financial return for investors. Even if prices don’t go into the stratosphere, labs might make tradeoffs to cut down on usage — as we’ve already seen GitHub doing. And while the race to build capacity to meet demand for those major AI labs will continue to push up prices for hardware in the short term, I still think it’s a better bet to have control over your own models and how much you pay for them than to leave it in the hands of big companies.

So I’ll keep tinkering with my local stack, which has already gone from one mini PC to two interlinked ones — and already have my eyes on a PC with an Nvidia GPU to give me the token speed that’s currently missing. But for now, I think it’s worth keeping what I have for a while and seeing how I can eke out additional benefits before making the leap financially in expanding my whole system.

This roadmap provides an in-depth analysis of Intel's current plans for its chip production capacity. In the space of 12 months, Intel has gone from canceling fabs to running short of them. In July last year, the company scrapped a planned €30 billion megafab in Magdeburg, Germany, and a $4.6 billion assembly and test plant near Wroclaw, Poland, citing a lack of committed demand. Then, in April this year, it paid Apollo $14.2 billion to repurchase the 49% stake in its Ireland fab that it had sold for $11.2 billion in 2024. Three weeks later, CFO David Zinsner described "unprecedented demand for silicon" alongside Q1 results that sent the stock up 24% in a single session, its best day since October 1987.

The next round of capacity development now hinges on two key deadlines: CEO Lip-Bu Tan told investors in January that prospective 14A customers will begin to make firm supplier decisions "starting in the second half of this year and extending into the first half of 2027." Separately, the enhanced 35% advanced manufacturing investment credit signed into law last July applies only to fab construction that begins before December 31st, 2026; projects that break ground in 2027 get nothing.

Both clocks run out within months of each other, and both bear on the same construction projects.

Arizona

Fab 52 at the Ocotillo campus in Chandler is the production foundation for everything on Intel's 2026 to 2028 product roadmap. The facility became fully operational in October last year as the first high-volume home of Intel 18A, building Panther Lake compute tiles and, later this year, Clearwater Forest. Naga Chandrasekaran, Intel's chief technology and operations officer, told CNBC in December that the fab is "capable of more than 10,000 18A wafer starts per week," which works out to roughly 40,000 wafer starts per month at full ramp and makes it larger than TSMC's Fab 21 phase 1 and phase 2 combined.

That’s named capacity, however, not current output; Intel has indicated that 18A yields will reach industry-standard levels in early 2027, and until then, the company is capping CPU output on the node, leaving part of Fab 52's capacity idle. Tan said in May that 18A yields are improving by 7% to 8% per month.

Fab 62, the second from Intel's $20 billion 2021 Arizona expansion, is expected to be ready around 2028. Intel hasn’t officially assigned it a node, leaving it open as a stopgap for 14A if Ohio isn't ready, or as additional 18A capacity if external demand comes sooner. Brookfield Infrastructure put up to $15 billion into the two Chandler fabs in 2022 for a 49% share of the joint venture, and unlike the Apollo arrangement, Intel has made no move to buy that stake back, so every wafer out of Fab 52 and Fab 62 will have revenue share commitments attached to it.

Oregon

As the home of 14A, D1X complex at Gordon Moore Park in Hillsboro — a low-volume fab and development site — is currently the only place Intel develops leading-edge process technology, with Chandrasekaran telling CNBC the node will be developed first in Oregon, with a goal of risk production in 2028 and high-volume manufacturing in 2029.

Hillsboro houses Intel's High-NA EUV machines, including the first ASML Twinscan EXE:5200B system delivered anywhere, and 14A is the first Intel node designed around it. Oregon also carried early 18A production while Arizona ramped up. Intel began permitting work in February 2024 for a multibillion-dollar expansion of the campus following the approval of an air quality permit, though no construction start has been announced to date.

Ohio One

Ohio is Intel’s most problematic fab project on paper. It broke ground in New Albany way back in 2022 on a $28 billion first phase, originally targeting 2025 production. In February 2025, however, Chandrasekaran reset its schedule, targeting 2030 for the completion of Mod 1 with operations between 2030 and 2031, and Mod 2 in 2031 with operations in 2032. In a memo setting out this new schedule, Chandrasekaran said Intel preserves “the flexibility to accelerate work and the start of operations if customer demand warrants.”

Spanning nearly 1,000 acres, the site is designated for 14A and future nodes, and has room for up to eight fabs. Intel has spent roughly $5 billion there to date as of March 2025, including $1.4 billion in total for that year. Bechtel, the lead contractor, posted a wave of new construction job listings in January, the same month Tan declared Intel is “going big time into 14A.”

Still, customers (or a lack thereof) remain the gating factor for 14A production. Intel told investors in January that it’s got two prospective customers evaluating 14A test chips, and its SEC filings still warn that without a significant external customer, it “may pause or discontinue” 14A, successor nodes, and various manufacturing expansion projects.

Elon Musk said in April that his planned TeraFab project — the first named taker for the node — will use 14A process technology to make AI chips, though test production is expected to be years out. This also isn’t such a big win in terms of the volume commitment Intel’s filings say it needs for 14A to be viable. At the time of writing, 14A’s next and arguably most critical milestone is the 14A v0.9 PDK, which Tan says will reach external customers in October.

"The Holy Grail is v0.9 PDK. Right now, we are looking at October to [hand it to] the outside customer. Internal customer will be earlier, so that we make sure that we really clean the pipe, make sure that we are doing right, make sure that we can sell with good quality."

Ireland and canceled projects

Launched in 2023, Fab 34 in Leixlip is Intel's only EUV-class site in Europe, producing Intel 4 and Intel 3 silicon for Core Ultra and Xeon 6 parts. In 2024, Apollo-managed funds paid $11.2 billion for a 49% interest in the joint venture entitled to the fab's output, a deal that gave Intel a much-needed cash injection at the time.

In April this year, Intel bought that stake back for $14.2 billion — at a premium of roughly 27% — funded from cash and about $6.5 billion in new debt issuance. Apollo walked away with around $3 billion in return for two years of exposure, and Intel paid a nine-figure annual cost of capital to reclaim needed wafer revenue.

“Flexibility and alignment are core to how we approach relationships as a long-term, solutions-oriented capital partner, and we are pleased to facilitate this transaction in support of Intel's evolving strategic and operational priorities,” said Apollo Partner Jamshid Ehsani at the time.

Magdeburg, once pitched as a €30 billion home for 14A-era production with roughly €10 billion in German subsidies attached, was postponed to 2029-2030 in November 2024. This prompted the German government to reallocate those subsidies to the federal budget and, following a $3.2 billion operating loss with Q2 2025 financial results, Intel killed the project, the subsidies dying with it.

Wroclaw's $4.6 billion assembly and test plant was canceled the same day, and Costa Rica's assembly and test operations were consolidated into Vietnam and Malaysia. Fab 38 in Kiryat Gat, Israel, the planned $25 billion expansion announced in 2023 with $3.5 billion in Israeli government backing, has been paused for the last two years, with no restart announced. Every leading-edge wafer Intel produces for the foreseeable future will come therefore come from three U.S. states and one campus in Ireland.

Packaging and test

Fab 9 in Rio Rancho, New Mexico, a $3.5 billion conversion that opened in January 2024, is the only high-volume Foveros 3D stacking site in the United States. Foveros is the packaging behind every tiled Intel design since Meteor Lake, bonding compute, graphics, and I/O dies vertically rather than laying them side by side, and it is integral to the stacked Clearwater Forest parts now ramping on 18A.

Intel runs it alongside the neighboring Fab 11x as a single co-located operation, which EVP Keyvan Esfarjani called “the only U.S. factory producing the world's most advanced packaging solutions at scale.” The buildout created hundreds of Intel jobs and more than 3,000 construction roles, and the campus later drew a further $500 million in CHIPS funding for modernization.

The $7 billion Penang complex in Malaysia, placed on indefinite hold in early 2025, has been revived: the buildout is now 99% complete, and first-phase assembly and test operations are due to begin later this year, according to Malaysian Prime Minister Anwar Ibrahim, following an earlier briefing with Tan. Intel has also outsourced EMIB production to Amkor's Songdo facility in South Korea, and its next-generation EMIB-T packaging rolls out across production fabs this year.

With Magdeburg and the Penang delay having stripped packaging options elsewhere, Rio Rancho is now the load-bearing U.S. node for the back-end work that makes Intel's entire chip roadmap possible.

Two deadlines and three things to watch

Intel’s 14A commitment window and the cutoff for tax credits both converge in the second half of this year. Tan’s stated expectation is that customers make firm supplier decisions between the second half of 2026 and the first half of 2027, with results from the upcoming October PDK potentially being the trigger for those decisions.

On June 8th, Cadence announced a multi-year agreement with Intel Foundry to co-optimize designs for 14A and deliver production-ready process design kits. This is exactly the EDA groundwork that needs to be in place before any fabless customer can commit volume, and a committed volume customer will be what unlocks acceleration at Ohio and gives Fab 62 a job. The alternative, per Intel, is to cancel 14A altogether.

Unlike the customer deadline set by Intel, the tax deadline can’t slip. The so-called One Big Beautiful Bill Act raised the Section 48D advanced manufacturing investment credit from 25% to 35% in July last year, but the law's termination clause is unchanged: the credit doesn't apply to “property the construction of which begins after December 31, 2026.”

Treasury rules let a physical-work test or a 5% spend safe harbor establish a construction start, so Intel has roughly six months to break ground on any new shells, in Ohio, Arizona, or Oregon, that it wants the U.S. government to part-fund. The government, of course, has been a shareholder since August, when $5.7 billion in unpaid CHIPS grants from Intel's $7.86 billion award and $3.2 billion in Secure Enclave funds were converted into a 9.9% equity stake.

Ultimately, we’re going to be watching for three things before January: a named 14A customer with a volume commitment; a construction-start announcement timed to beat the credit deadline; and 18A yield milestones that free up the Arizona capacity Intel’s currently sitting on.

We learned a lot about Intel’s upcoming plans for desktop CPUs at Computex 2026. In classic Intel fashion, we’ve already heard a lot about the company’s next-gen CPUs, codenamed Nova Lake, even while the recent Arrow Lake Refresh CPUs are still warm from the oven. But on the ground in Taipei, we heard not only more about Nova Lake and the Z990 platform it’s arriving on, but also how Intel intends to handle the rollout and how it will fill the gaps in its lineup with “Raptor Lake Next,” which is supposedly slated to launch next year.

Trade shows are the best opportunity to learn details about unreleased products before they show up in a press deck, and simultaneously the worst venue to do so. With jet-lagged representatives and reporters, thousands of people whizzing past, and the threat of Jensen Huang showing up to sign components and shut down a floor on a moment’s notice, it’s easy for things to get lost in the shuffle. So, we’re going to work through everything we learned about Intel’s upcoming plans in stages, starting with details that are confirmed, and working toward more speculative murmurs.

Intel has a fairly aggressive consumer roadmap, which the company itself would tell you – and the company told us as much at Computex, as a matter of fact. Both Nish Neelalojanan, senior director of client product management, and the recently joined Alex Katouzian, executive VP and GM of client, played up Intel’s roadmap to Tom’s Hardware, and for good reason.

Chronologically, Intel’s plans look something like this: We’ll see the first Nova Lake SKUs roll out at CES 2027. A few months later, we’ll see a refresh on the LGA 1700 socket with “Raptor Lake Next” CPUs, and come Computex next year, Intel will launch a 52-core flagship Nova Lake SKU. None of that is confirmed by Intel, and we have varying degrees of confidence in each step of the roadmap, so take it as speculation for now. We’ll dig more into the details we have and what’s simply rumored below.

What about AMD?

Before Intel, we should at least look at why we’re not talking about AMD’s next-gen desktop plans. Basically, we don’t have a ton of information on Zen 6 CPUs yet, and even less information about Olympic Ridge, the desktop consumer lineup of Zen 6 chips. Computex didn’t change that fact.

At Computex, AMD revealed the Ryzen 7 7700X3D, relaunched the Ryzen 7 5800X3D, and brought the RX 9070 GRE to the rest of the world. Unlike previous years, AMD didn’t hold a keynote, where we might’ve seen a more concrete tease of Olympic Ridge; AMD has already teased Zen 6 broadly several times. Bigger Zen 6 news is likely at the company’s Advancing AI event next month.

Although AMD hasn’t said when Olympic Ridge will launch, we originally expected it in late 2026. Now, 2027 is very likely. AMD has shifted the Zen 6 conversation toward its EPYC Venice chips, and confirmed production ramp on Venice in May. Although AMD traditionally leads with a consumer launch at the turn of a new microarchitecture, it’s unlikely that Olympic Ridge will launch before Venice. Demand for CPUs is spiking in the data center for agentic AI workloads, after all, and AMD is adjusting accordingly.

Olympic Ridge probably isn’t top of mind right now, from both AMD itself and its partners. AMD laid the groundwork for a unified CPU architecture generations back, and Intel’s approach has been a bit more disparate across client and data center (although that’s been changing with releases like Xeon 6 and Xeon 6+). We don’t know when Olympic Ridge news will arrive, but it almost certainly follows far greater detail about Zen 6 in the context of Venice.

What’s confirmed

Let’s start with the concrete details about Intel’s future CPU plans. These are things we have direct evidence for, be it photos, our own hands-on time, or sources we’re extremely confident in. At least two Z990 motherboards were at Computex, a third is rumored, and we saw (and held) what looked to be a near-production model in a closed-door meeting. And from that, we can already tell a lot about Nova Lake.

First, the LGA 1954 socket, which has now been pictured (we were told not to take pictures, but someone else did the dirty work, it seems). It’s the same size as the LGA 1851 socket, measuring 45 mm x 37.5 mm, and it retains compatibility with existing coolers, which we were able to confirm at Computex. It features more pins, as the name reveals, and uses the 2L-ILM, or two-lever Independent Loading Mechanism. The picture of the socket circulating matches what we saw at Computex.

The motherboard we saw featured dual 8-pin EPS connectors, along with an 8-pin PCIe connector near the bottom of the board, which is said to provide auxiliary power to the CPU. We’ve seen a leaked photo of the Z990 PCH now, which is said to draw more power due to broader PCIe 5.0 support. The Z990 board we saw, at least, had three PCIe 5.0 M.2 slots, along with three PCIe 5.0 expansion slots. Short of perhaps specialized designs with extra M.2 slots, we expect Z990 to support PCIe 5.0 across the board.

As for the chips themselves, all that is confirmed from Z990 motherboards is that Nova Lake can scale up to a high-end power design. We’ll speculate more on specific numbers later, but we’ve seen auxiliary power beyond two 8-pin EPS connectors on two Z990 motherboards now, and the motherboard we held had an extremely high-end VRM design; we can’t say more than that at this point.

An important caveat here is that we’re dealing with high-end motherboards and discussing how high the platform can scale, not how it will scale. Plenty of ink has been spilled about Nova Lake’s supposedly high power draw, but we really don’t have details about the chips themselves, rather just the tippy-top of the platform that will support them.

Outside of Z990 boards, Intel has confirmed that Nova Lake is “coming at the end of 2026.” That’s what CEO Lip-Bu Tan said at the company’s full-year 2025 earnings call back in January. What we were told by multiple vendors at Computex is Q1 2027, with a portion of those vendors specifically pointing to CES 2027. Similarly, with Z990 motherboards, some vendors said Q1 2027 while others said Q4 2026 (one even hinted at Q3). Believe it or not, these timelines actually all match up.

What’s lost in translation here is when the sale is happening. Before Nova Lake launches publicly, Intel and motherboard vendors will need to sell products into the channel, which, a few months later, will be available for sale at retailers for you to buy. What we’re likely looking at is sales into the channel in Q4, a public launch of Nova Lake at CES 2027, and retail sales in Q1. When Tan says Nova Lake is coming at the end of 2026 to a group of investors, he’s likely referring to selling into the channel, not the final retail sale.

What’s likely

Now, we’re getting into a bit more speculation. These are some of the details we heard about at Computex, or confirmations of previous rumors that we don’t have any concrete evidence for. Given the conversations we had at Computex, and a healthy dose of critical thinking, these are the details that are likely but not confirmed. There’s always a chance we’re just blind men touching an elephant on some of these points.

First, Nova Lake. For nearly a year now, it’s been rumored that the highest-end Nova Lake SKU will scale up to 52 cores. That’s the number we heard at Computex, as well, but not as a typical flagship. Rather, we heard that Intel plans to lead Nova Lake with a 28-core flagship, which will launch at CES 2027, and introduce a high-end 52-core model later in the year. The timeframe we heard was Computex 2027, but if anything is subject to change, it’s a release date that’s a year away. For now, let’s call it later in 2027.

The 52-core SKU will apparently come with 16 Coyote Cove P-cores, 32 Arctic Wolf E-cores, and a cluster of 4 LP-E cores; we didn’t hear that at Computex, nor anything to the contrary, but that’s what has been previously rumored. That model will reportedly come with two compute tiles, so the 28-core model with a single compute tile will likely look like an 8 + 16 + 4 split. That’s pure extrapolation at this point, however.

As for the 52-core model, we were told it comes with a PL1 of 175W and a PL4 of up to 700W. The PL1 number is what’s important here. Although that is a sizable increase over the 125W PL1 of both the 285K and 14900K, 52-core Nova Lake doesn’t sound like a direct replacement for those parts. Given the timing and extra power demands, it looks more like a spiritual successor to Intel Extreme Edition chips, targeting enthusiasts with deep pockets and the HEDT crowd.

Nova Lake is treaded ground at this point, however. Something new we learned about from Computex is “Raptor Lake Next.” After hearing the name, we asked Intel, which declined to comment on Raptor Lake Next at this time. Apparently, however, it will be the third refresh of Raptor Lake CPUs on the LGA 1700 socket, particularly targeting budget-conscious builders while Nova Lake satiates the enthusiast crowd.

There are some pieces of circumstantial evidence that point to a reintroduction of LGA 1700 CPUs. First, this has been previously rumored. In April, prolific leaker Jaykihn hinted at another Raptor Lake refresh coming in 2027. We’ve now heard that the range is called Raptor Lake Next from multiple sources, and it’s specifically coming in the first half of 2027, some months after the initial Nova Lake launch.

Additionally, multiple motherboard vendors told us that they’re ramping production of LGA 1700 motherboards, including DDR4 boards, though they didn’t say it was in relation to any new CPU releases. Intel itself has dropped a few hints, as well. Earlier in the year, Intel’s Robert Hallock said that Raptor Lake will be “abundantly available” in the market, and at Computex, Intel’s Nish Neelalojanan told Tom’s Hardware that Intel “will continue to make sure that there are products which can take care of older memory technologies.”

It would certainly make sense for Intel to refresh Raptor Lake a third time. Although data center demand is offsetting it, the decline in desktop sales from high memory prices hits Intel and AMD on the balance sheet as well. Just about everyone we spoke with at Computex talked about the state of memory prices, and Intel has a DDR4 platform that it’s still actively selling on the market. AMD, with a hard switch to DDR5 with Zen 4, has to reach back further to revitalize DDR4 options, but Intel already has a small ecosystem of DDR4 motherboards and CPUs available now, which it could easily bolster. We’ve heard that bolster is coming in the opening months of next year.

What that range looks like remains a mystery, however. It could be a proper refresh, or it could simply be an infusion of 14th-gen stock (and LGA 1700 motherboards) into the market along with new price points; both Raptor Lake generations have slowly crept up in price since the end of last year. The important thing here is that it seems Intel is targeting LGA 1700 for the lower end of the market, as Arrow Lake, with its underperformance and high price due to exclusively using DDR5, won’t provide the last-gen value bridge that previous generations have.

After Tom's Hardware originally broke the news about Raptor Lake Next, we followed up with Jaykihn, who provided a few specs.

*Naming unconfirmed by Intel, specifications rumored

The specs we've heard about are for the four SKUs above, which would comprise the main lineup of chips with integrated graphics enabled; apparently, Raptor Lake Next will include options with the iGPU disabled, as well as mobile chips. The final branding is unconfirmed, but we've heard that Intel intends to launch under the Core Ultra 200 name.

Out of the four SKUs, the 16-core Core 5 looks like Intel's breadwinner. Throughout 12th- to 14th-Gen, Intel topped out Core i5 models at 6 P-cores. You'd have to step up to a Core i7 for 8 P-cores. If these specs are correct, Intel is stepping down to an 8 P-core configuration a tier in branding, which will hopefully come with a cut to price.

What’s still up in the air

Some of the finer details of Nova Lake are still up in the air. That is, we don’t have any direct evidence for them, nor any corroboration from Computex. That’s not to say that the details here are false. Rather, we just need more information to say, for sure, that some of these details are a part of the Nova Lake lineup.

First and most obvious is bLLC, or big Last Level Cache. This is one of the earliest Nova Lake rumors that is still circulating, and for good reason. Intel hasn’t found an effective counter to AMD’s 3D V-Cache CPUs in more than four years. We’re closing in on half a decade where AMD has entirely owned the high-end of PC gaming, which has continually eaten away at Intel’s market share. bLCC is, apparently, Intel’s counter to 3D V-Cache, using its own Foveros 3D hybrid bonding to stack additional last-level cache.

Tom’s Hardware asked Intel CEO Lip-Bu Tan and a panel of executives at the company how it plans to address X3D CPUs, and Alex Katouzian, a 20-year Qualcomm veteran who recently joined Intel in a leadership role over the client group, said the following: “When I first came in and started reviewing road maps for the team, I was very pleasantly surprised. So, stay tuned, a very strong roadmap [is] coming, and we will be gunning for that section of the market as well. And so, please stay tuned.”

Context is important, but Katouzian is really only saying that Intel is gunning for high-end gamers with its roadmap, which, of course, it is. Otherwise, bLLC has entirely been a topic of the rumor mill. Intel has indirectly teased it with PR hits about its packaging capabilities, but that extends far beyond bLLC. Hybrid bonding, especially from a foundry perspective, has far greater legs in the data center.

Although Intel has the packaging and bonding capabilities, the scale of them for a mass-market product like Nova Lake is questionable. Intel would need to bond the SRAM to the logic tile with Forveros and package the chip with EMIB, creating the “EMIB 3.5D” combination that Intel has talked about previously. We first saw EMIB 3.5D on the Ponte Vecchio data center GPU, but most recently and relevantly on Clearwater Forest, Intel’s first foray into putting 18A in the data center. The capability is there, but if Intel can scale that up to a consumer range with more limited die space and higher per-core performance remains to be seen.

One advantage of Intel’s hybrid bonding and advanced packaging is that it can package dies from other foundries, not just those from Intel foundries. That brings us to the second finer point about Nova Lake, which is the node. Originally, the assumption was that Intel would use 18A for Nova Lake. We have 18A on mobile with Panther Lake, in the data center with Xeon 6+, but not on the desktop. Further, Intel has previously commented about reshoring its manufacturing for consumer chips after a brief stint with TSMC for logic tiles in both Lunar Lake and Arrow Lake.

Around this point last year, however, rumors started circulating that Intel is using TSMC’s N2 for Nova Lake. The source of the rumor is flimsy, however. Well-known reporter Charlie Demerjian of SemiAccurate reported in July 2025 that Intel taped out a major product. The report didn’t mention what product, what foundry, or even include “TSMC” anywhere on the page. Still, other outlets took the story, claiming that not only was Demerjian talking about Nova Lake, but also that he was talking about TSMC N2.

There are reasons Intel could use TSMC for the logic die. The company has reiterated that it’s shifting wafer capacity toward the data center, so if TSMC can fill additional capacity on the desktop, we could see TSMC on the main logic die. It’s also possible that TSMC is manufacturing other tiles on Nova Lake. Intel has consistently blended nodes in recent generations, so even if Intel were to confirm that it’s tapping TSMC for Nova Lake, that doesn’t necessarily mean the Taiwanese giant is manufacturing logic.

And, just as easily, Intel could absolutely be using TSMC for logic. That’s the point here; we really don’t know at this point, outside of vague reporting, getting swept up in the rumor mill, and taking on a life of its own. The Cinderella story for Intel would be Nova Lake on 18A, but given the struggles on 18A yields, it wouldn’t be surprising to see TSMC at the helm for Nova Lake once again.

Hurry up and wait

Intel needs a much more aggressive roadmap on the desktop than AMD, frankly, and that roadmap is starting to take shape. Although AMD and Intel compete on the finer points of performance, Team Red has almost exclusively taken market share away from Intel, quarter over quarter, for the past decade. There are only a handful of quarters in that time when AMD has lost market share, which it has always rebounded from in the quarter that follows.

Even if Intel still represents the majority of the desktop market — and it does based on the latest market research — the trend is abundantly clear. Add on top of that clear fumbles like Arrow Lake, and it’s obvious that AMD doesn’t need to move the needle much to continue swiping customers. Intel needs to make big moves to recover.

We should have more official details about those plans soon. Intel mostly sat Computex out on the consumer front, short of the Arc G3 range that, although exciting for gaming handhelds, is destined to be a niche product given the high prices of the devices those chips are going in.

For the past four years, Intel has held its Tech Tour event in the fall, taking the place of its previous Architecture Day, which took place in the late summer (most of those details have shifted to the Hot Chips conference in August). Intel has already told us that Hot Chips will have more details about Diamond Rapids, Intel’s next-gen P-core Xeons. That leaves Tech Tour for when we’ll likely get a full architectural deep dive on Nova Lake. Intel has yet to confirm Tech Tour 2026, but we have no reason to believe the company will sit out the rest of the year at this point. It also lines up with what we’re hearing about Nova Lake’s release — architectural details in the fall, a launch at CES 2027, and availability in Q1.

Regardless of when the exact dates fall, Computex made it clear that Intel is readying Nova Lake for a release soon. Multiple motherboard vendors brought Z990 motherboards to Computex and actively showed them to the press; I can’t imagine that was sanctioned by Intel.

As for Raptor Lake Next, Computex is the first quasi-confirmation we’ve heard of the range. That name apparently appears on Intel’s roadmap at some point in the first half of next year. With Nova Lake at the high-end and Raptor Lake Next in the midrange, Intel might have a one-two punch strategy to earn back some spots in the market, especially as AMD turns its Zen 6 focus toward the data center and prioritizes older architectures on desktop, given high DDR5 prices. Now, we just need to wait and see how those internal plans materialize as the rest of the year goes on.

When we referred to TSMC just several years ago, we called it 'the world's largest foundry,' implying that Intel was still the world's largest producer of advanced logic chips. However, having spent nearly $240 billion on capacity expansion over the last 10 years, TSMC now has nine sites with dozens of 300-mm fabs, many of which can process orders of magnitude more wafers using EUV-based process technologies than Intel*, which makes TSMC the world's largest maker of advanced logic chips.

Being the world's largest maker of advanced AI processors requires TSMC to stay ahead of its rivals, Intel and Samsung Foundry, both in terms of process technologies and, perhaps, even more importantly, in terms of production capacity.

Therefore, TSMC has kicked off the most aggressive manufacturing expansion in its history as the company races to meet explosive demand for AI processors, logic chips made on leading-edge nodes, and advanced packaging.

During TSMC's Tech Symposium 2026 manufacturing presentations, the company revealed that in 2025 – 2026, it effectively doubled its historical construction pace, building or converting nine fab phases annually, up from an average of four phases per year. The company is simultaneously building or ramping new fabs in Taiwan, the U.S., Japan, and Germany. In addition, it introduces new ways to improve the productivity of existing facilities.

N2 ramp: Six-figure amounts of wafers per-month by 2029

The central part of TSMC's expansion plan is its N2 process technology. At present, the company is ramping up production of chips using N2 at two sites: Fab 20 phase 1 and phase 2 in Hsinchu near TSMC's global R&D center, and Fab 22 phase 1 in Kaohsiung. Ramping a leading-edge node at three facilities simultaneously is highly uncommon for foundries. The company also plans to ramp up production at Fab 22 phase 2 shortly and Fab 22 phase 3 by the end of the year. Eventually, Fab 22 phase 4 will come online as well. As a result, TSMC aims to start mass production on its N2 process technology at five facilities in the first year, which is at an unprecedented scale.

As a result of such an aggressive ramp, TSMC expects its N2 wafer-out capacity to be 45% higher than that of N3B in the first year. Reports from 2023 – 2024 indicate that TSMC ramped its N3B production at two or three phases of Fab 18 in 2023 and reached a capacity of around 60,000 wafer starts per month by the end of that year. If the reports are accurate, then TSMC expects its N2 capacity to reach around 90,000 wafer starts per month (WSPM) by the end of the year. This exceeds the fully ramped capacity of Intel's 18A-capable Fab 52, which is believed to be at around 40,000 WSPM.

What is even more impressive is that TSMC intends to increase its N2/A16-capable capacity by 70% every year through 2028, which means hundreds of thousands of WSPM in 2029.

In addition to reaching vast capacity, ramping up five fab phases simultaneously enables TSMC to mitigate risks. If one fab phase experiences a contamination issue, tool failure, or yield issues, the entire N2 supply chain will not collapse. The same applies to ramping up production at two sites located in different parts of the country: an earthquake or utility failure can interrupt production or even cause yield loss at one of them, but it will not affect another. Such risk mitigation is critically important when customers like Apple, AMD, Nvidia, or Qualcomm, which demand a continuous supply. There is potentially another bonus with ramping up these fab phases in parallel rather than in serial, so read on.

N2 ramp: One Team and the Super Manufacturing Platform

Such an unusual ramp strategy seems to be enabled by two programs at TSMC: the "One Team" collaboration between R&D and fab operations, and the Super Manufacturing Platform (SMP) that enables multiple fabs (or rather fab phases) to work as one, which likely has similarities to Intel's "Copy Exactly." TSMC hasn't shared many details about the One Team and SMP, though we can make some educated guesses.

The One Team is a global manufacturing knowledge-transfer system that links R&D, process integration, equipment management, and high-volume manufacturing expertise during technology development and ramp-up. To speed up feedback loops, TSMC likely inserts manufacturing teams relatively early in node development so that R&D teams adjust their work to what is possible at fabs. As a result, yield learning, process optimization, and tool productivity improvements can be done quickly at one fab and then transferred to others. TSMC says that One Team enabled a 20% faster technology transfer compared to N3, without disclosing the time it typically takes to transfer technology from one fab to another.

In addition, all of TSMC's GigaFab sites now rely on its Super Manufacturing Platform (SMP), which is essentially a centralized manufacturing-control system that makes multiple fabs operate as one giant synchronized fab with standard process recipes, tool configurations, metrology, and yield management flows. This should enable TSMC to transfer production between fabs more easily, ramp new nodes faster, introduce yield fixes globally instead of locally, and reduce customer requalification work when production of chips is moved from one fab to another.

Moreover, since every fab phase generates its own tool behavior data, defect density data, process window statistics, and yield learning information, multiple simultaneous ramps may actually accelerate yield/defects learning when SMP and One Team are in place. In turn, it may speed up ramping of fab phases.

A 70% CAGR in N2/A16 capacity in the coming years is an extraordinarily aggressive ramp for leading-edge manufacturing. Without something like TSMC's' One Team structure and SMP, coordinating that scale of expansion across multiple Fab 22 phases, Fab 20, and eventually Fab 21 phase 3 in Arizona would be barely possible both from organizational (operational control) and from economic (yield learning, process window, etc.) points of view.

TSMC also noted that despite the significantly higher complexity associated with gate-all-around (GAA) nanosheet transistors, N2 is achieving a better yield learning curve than N3, which again can be attributed to the innovative approaches that the company uses.

Beyond N2: A14, A13, and A12

TSMC's N2/N2P/N2X/N2U/A16 production will largely be concentrated at Fab 20 phase 1 and 2, Fab 22 phases 1, 2, 3, 4, and, to some degree, Fab 21 phase 3. However, for nodes beyond 2nm-class (A16 is essentially N2P with a backside power delivery network), such as A14, A13, and A12, TSMC will build Fab 21 phase 3 and then the all-new Fab 25 site in central Taiwan with at least four phases.

A14 is set to start high-volume production in late 2028, so there is a good chance that TSMC will ramp it at both Fab 20 phase 3 and Fab 25 phase 1. However, given the company's aggressive approach to capacity expansion, TSMC might well surprise us once again. Also, we do not yet know how TSMC plans to upgrade N2/A16-capable fabs to subsequent nodes, if at all.

Expansion beyond N2

The expansion is not limited to the N2 production node and subsequent technologies. TSMC is continuing to grow combined N3 and N5 capacity at a 25% compound annual growth rate (CAGR) from 2022 through 2027. To address immediate demand, the company is converting some N5 capacity into N3 production, which is not particularly expensive, since N3 reuses 85% - 90% of the tools used for N5. Furthermore, as much of TSMC's N3 and N5 capacities are concentrated at Fab 18 (four phases N5, four phases N3), converting some of the N5 capacity to N3 is relatively easy from a logistical perspective.

AI is here to help (to build more AI processors)

Alongside the conversion of N5 to N3 capacity, TSMC also heavily uses AI to improve the performance of each tool, and the whole fab in particular. Essentially, TSMC uses AI to build more AI processors, which seems to be a paradox, but it is becoming popularized as AI becomes embedded within workflows.

One of the things that greatly slows down cycle times of modern fabs is batch processing of wafers in various chambers, something that is an inevitable part of some 5,000 steps. Essentially, 25 wafers ‘wait’ in a (perhaps in a CVD chamber) for a lithography tool to process them individually.

Atsuyoshi Koike of Rapidus thinks differently and believes that a single-wafer processing across all steps can significantly speed up cycle time, but at the cost of tool efficiency. TSMC does not seem to plan to use single-wafer processing (despite its purchasing power, it can likely persuade fab tool makers to produce appropriate tools), but it can certainly optimize the ways in which it uses existing tools to boost the productivity of its existing fabs.

TSMC revealed at its recent Technology Summit that it uses intelligent scheduling systems that incorporate 'state-of-the-art linear programming and heuristic algorithms' to optimize equipment efficiency, though it did not reveal what exactly is done and what is achieved. TSMC further revealed that it uses generative AI algorithms to identify optimal parameters that 'challenge the physical limits of equipment' while maintaining wafer quality. In parallel, the company analyzes tool logs using big-data analytics and text-mining systems to dynamically adjust key parameters, minimize tool idle time, and maximize output.

AI systems are also used for real-time chamber condition analysis to determine optimal chamber-cleaning timing and avoid unnecessary maintenance that could reduce machine uptime and available capacity. In addition, TSMC disclosed that AI-assisted comparison and fine-tuning of large volumes of machine verification parameters reduced the time required to validate new tools and reach high-volume manufacturing by more than 20%, which helps to ramp up new fab modules faster.

TSMC also said it achieved more flexible allocation and higher combined N3 and N5 capacity at Fab 18 in Tainan by increasing equipment commonality and integrating 'cross-technologies planning,' which essentially means that the company re-uses as many tools as possible.

Expansion beyond Taiwan

Outside of Taiwan, TSMC continues to broaden its geographic footprint. In Arizona, Fab 21 phase 1 is already producing chips using N4 technology (with capacity increasing by 1.8X this year alone), while Fab 21 phase 2 is on track to start N3 production in Q3 2027. Fab 21 phase 3 targets N2 sometime later this decade, as the company continues to construct shells both for phase 3 and phase 4. The company also reaffirmed plans for an advanced packaging facility, an R&D center, and additional land acquisitions to support future expansion.

In Japan, the company’s Kumamoto Fab 23 phase 1 is already producing 28nm and 22nm chips, while Fab 23 phase 2 underwent a major strategic shift. Originally planned for 7nm-class production, the facility will instead manufacture using technologies down to N3 3nm to address stronger-than-expected local demand and onshoring intentions of local chip designers.

Meanwhile, Fab 23 in Dresden, Germany, which is under construction, is aimed at automotive and industrial applications with legacy planar transistors and FinFET-based 28nm, 22nm, N16, and N12 production nodes.

Advanced Packaging

AI itself is now one of the main drivers behind the company's unprecedented capacity growth. TSMC disclosed that wafer shipments for AI accelerators are expected to rise 11X between 2022 and 2026. The company also highlighted the rapid growth of extremely large dies exceeding 500 mm^2, as shipments of those devices are projected to increase 6X over the same period. Such products typically require lots of wafer capacity (wafer starts) and advanced packaging technologies, since many of these designs use HBM3E memory.

Advanced packaging has therefore become just as important as wafer fabrication itself. TSMC said its CoWoS capacity will grow at an 80% CAGR between 2022 and 2027, while SoIC capacity will expand at a 90% CAGR during the same timeframe. TSMC also said it has improved development-to-HVM transition times by 30% for CoWoS and by 75% for SoIC compared to earlier generations.

TSMC currently operates 11 advanced packaging facilities in Taiwan (AP1 in Hsinchu, AP2A/AP2B/AP2C and AP8 in Tainan, AP3 in Longtan, AP5 in Taichung, AP6A/AP6B/AP6C in Zhunan, and AP7 in Chiayi). According to a recent DigiTimes report, the company is simultaneously expanding multiple advanced packaging campuses, including AP5, AP6, AP7, and AP8.

The AP7 site in Chiayi will reportedly become TSMC's largest advanced packaging campus using SoIC to support major customers like Nvidia, which plans to use 3D packaging technologies for its next-generation Feynman GPUs. AP8 — converted from a former Innolux LCD fab — is expected to exceed 40,000 wafers per month of CoWoS capacity by late 2026.

While CoWoS is the de facto standard for AI processors, SoIC is set to become much more widely used in the coming years. As a result, the company is also rapidly expanding its SoIC production capacity. DigiTimes claims that AP6 in Zhunan could approach 10,000 SoIC wafers per month, whereas AP7B may add approximately 12,000 wafers per month. Future AP7 phases are expected to support both SoIC and CoPoS technologies, though CoPoS is a part of TSMC's roadmap in the 2030s.

Advanced packaging now requires tight ecosystem integration that includes HBM suppliers, substrate vendors, OSAT partners, testing companies, materials providers, and toolmakers, with which TSMC works to standardize those tools. The very emergence of such an ecosystem emphasizes the increasing role of TSMC in the burgeoning AI industry.

An all-encompassing roadmap

After investing nearly $240 billion into capacity expansion over the last decade, TSMC has evolved from the world’s largest foundry into the world's largest producer of advanced logic chips, producing the lion's share of AI processors today.

To support the explosive AI demand and to stay ahead of Intel and Samsung Electronics, TSMC has doubled its historical fab construction pace to nine fab phases annually in 2025 – 2026 while simultaneously expanding in Taiwan, Arizona, Japan, and Germany. The company's N2 ramp is unprecedented as the company preps to ramp five fab phases within the node's first year, and N2/A16 capacity is projected to grow at a 70% CAGR through 2028.

TSMC said this aggressive expansion is enabled by its One Team organizational structure and Super Manufacturing Platform (SMP), which synchronizes manufacturing, yield learning, and process control across multiple fabs. The company is also implementing various AI-driven manufacturing optimizations, including intelligent scheduling systems, generative AI process tuning, and real-time tool analytics to improve throughput, reduce cycle times, and accelerate tool qualification.

At the same time, TSMC is rapidly expanding advanced packaging capacities. The company intends to increase CoWoS and SoIC capacities at 80% and 90% CAGR, respectively, through 2027, as demand for both technologies is expected to grow as chiplet-based designs and HBM memory are technologies of choice for AI accelerators.

*TSMC's wafer processing revenue for 2025 was $103,708.5 billion, thus representing around 84% of consolidated revenue of $122.4 billion. EUV-based N3 and N5 process technologies accounted for 60% of TSMC's wafer revenue in 2025, thus earning around $62,225 billion. Intel Foundry earned $17.826 billion in 2025, $307 million came from external customers that mainly ordered advanced packaging. It is estimated that process technologies that use EUV account for more than 10% but less than 20% of Intel's wafer revenue.

Intel does not disclose a revenue split similar to TSMC's (wafer fabrication vs. packaging/testing vs. other) in its official filings, so its wafer processing revenue is hard to estimate, especially given the fact that some of its silicon is made at TSMC and is packaged internally. Nonetheless, even 20% of Intel Foundry's 2025 revenue is $3.565 billion, which is over 17 times less than TSMC earns on its EUV-based nodes.

The AI revolution that shows no signs of stopping appears at times to have echoes of the gold rush. Whisper networks spread quickly through communities about new scarce commodities, and suddenly there’s a surge of interest as people snap up resources. For most of the ChatGPT era, you’ve struggled to get hold of a GPU for neither love nor money, with Nvidia practically able to manage its own waitlist, so great is the demand.

Much of the media’s attention – and plenty of investment – has been focused on the dash to grab as many GPUs as possible; most recently, memory has become a focal point.

But in recent weeks and months, there’s been a focus on ensuring that people have CPUs to match. For decades, the CPU has been the anonymous workhorse of the hardware stack, running operating systems, scheduling workloads, and keeping everything ticking over, rarely grabbing headlines unless there’s a supply crunch or a generational leap in performance.

Suddenly, it’s being talked about in the same breath as scarce-as-gold GPUs. What’s going on?

“AI deployment at scale has forced organizations to look at the infrastructure underneath the hype,” said Jason Beckett, chief technology officer in Europe, the Middle East and Africa at Hitachi Vantara, in comments to Tom’s Hardware Premium. As Beckett points out, while most of the attention is focused on GPUs because they run the AI models, the CPUs are vital because they handle “everything else”.

And as agentic AI becomes the norm, there’s a greater need for that CPU backbone to keep things running properly. “Always-on, multi-step reasoning systems don't create brief orchestration bursts around GPU workloads,” said Beckett. “They demand high-core-count CPUs running at sustained loads, continuously. The infrastructure requirement was always structural. It's just now unavoidable.”

Readjusting ratios

When data centers were previously being specced to deliver AI training and inference in the early days of the generative AI revolution, those building them accounted for a gargantuan bias in favor of GPUs. Chatbot conversations required between four and eight GPUs to every single CPU required, because the parallel equations required to meet user requests were GPU-inference heavy.

But as the main use case of AI changes from chatbots to agents, the requirements have also altered. A slight delay for in-depth inference while an AI model ‘thinks’ was seen as an acceptable interface choice. But as agentic AI requires rapid responses and the smooth coordination of tool calls and much more, latency can be a killer. Bolstering CPU counts can help avoid any problems that can quickly spin out into something more significant, breaking the entire agentic stack.

AMD, one of the major manufacturers of CPUs, has seen that shift first-hand. The company had previously forecast that the CPU market would grow at a rate of around 18% annually, but says that the change in requirements has materially changed the market. The rate of growth has now doubled to 35% a year, AMD claims, and will become a $120 billion market by the end of the decade.

“What AMD and Arm's results are telling us is that this is a structural, not cyclical requirement,” said Roger Cummings, CEO of PEAK:AIO, in an interview with Tom’s Hardware Premium. “In actuality, two structural shifts are driving the demand surge: the rise of agentic AI and the need for deterministic, predictable performance at rack scale.”

Much of that CPU demand is being driven by hyperscalers, who recognize the integral role that CPUs play in developing the AI clusters that are likely to power the economy in the years to come. “As GPU clusters scale, CPUs are taking on larger roles in orchestration, memory management, networking, storage coordination, and inference handling,” said Jeff Moore, vice president of strategic partnerships at Aegis Cooling, which specializes in next-gen liquid cooling solutions for AI and high-performance computing infrastructure, in an interview with Tom’s Hardware Premium.

There’s a rise in CPU-to-GPU ratios inside AI deployments, said Moore, “particularly because distributed AI workloads generate significant demand for general-purpose compute, memory bandwidth, and east-west data movement.” A recent TrendForce analysis points out that CPUs’ contribution to latency – accounting for nearly 91% of all the delay in responses – is something that AI deployments are trying desperately to counteract.

Changing designs

That shift is now visible not just in financial forecasts, but in the physical design of AI infrastructure itself. In early generative AI deployments, racks were often built around dense GPU configurations, with CPUs effectively treated as supporting components – enough to keep the system running, but not a bottleneck concern. Things are shifting now. “In the media, an AI rack is pictured as a giant box of GPUs,” said Hommer Zhao, founder of OurPCB, a PCB manufacturer with more than 15 years’ experience, in comments to Tom’s Hardware Premium. “But from a hardware design perspective, a GPU is just a very fast, very dumb engine. It cannot talk to the internet or pull data from a hard drive.”

Rather than a single host CPU loosely paired with multiple GPUs, hyperscalers are deploying configurations with higher core-count CPUs, more memory channels, and, in some cases, multiple CPUs per node to keep pace with data movement demands.

There are also thermal and power considerations shaping how racks are populated. High-core-count CPUs, especially those optimized for cloud workloads, are being selected not just for raw performance but for efficiency under sustained load. In liquid-cooled environments, CPUs are increasingly part of the same thermal design envelope as GPUs, rather than an afterthought cooled separately with air.

Financial signs of success

Recent results from AMD and Arm reinforce the idea that this is not a short-term correction but a deeper architectural shift. AMD has reported strong growth in its data center CPU segment, driven in large part by hyperscaler demand for its EPYC processors, which offer high core counts and memory bandwidth well suited to AI orchestration tasks.

Arm, meanwhile, is benefiting from hyperscalers designing their own custom silicon. “Arm accounts for close to half of all compute shipped to top hyperscalers in 2025, with over a billion Neoverse cores deployed,” said Beckett. “Those are rack-level architectural decisions made years ago.” AWS’s Graviton, Google’s Axion, and Microsoft’s Cobalt chips all reflect a move toward CPU architectures tailored for specific workloads: high-throughput, energy-efficient, and tightly integrated with networking and storage. Arm’s licensing model positions it at the center of this trend, and its recent financial results highlight how significant that hyperscaler-driven demand has become.

Both sets of results point to a change in how CPUs are being valued. In traditional enterprise contexts, the hardware was often general-purpose and interchangeable. In hyperscaler environments, it’s becoming a specialized infrastructure component, tuned for specific roles within AI systems, whether orchestration, inference at the edge, or data preprocessing.

Taken together, the changes in rack design and vendor performance suggest that CPUs aren’t a secondary consideration in AI infrastructure planning any more. Instead, they are becoming a critical factor in determining overall system efficiency and cost.

“The spotlight hasn't revealed something new,” said Beckett. “It's just finally illuminating what serious infrastructure teams never stopped building on.”

As the crowds in Taipei thin out and the crowds begin to disperse, our team on the ground at Computex 2026 ruminates on their experiences of the show itself and what it might mean for the industry at large. Day four will be our final entry into the Tom's Hardware Unfiltered series for Computex 2026, so we hope you've enjoyed peeking behind the curtain to gain an insider look at exactly what we've been up to this week.

Starting at the end is just wrong, so if you haven't yet caught up on all of the coverage coming out of Computex, be sure to check out the entire series of blogs.

• Computex 2026 Day 0
• Computex 2026 Day 1
• Computex 2026 Day 2
• Computex 2026 Day 3

Paul Alcorn: Editor-in-Chief

Day four was yet another hectic affair, with a string of meetings in the early morning continuing into the afternoon. This Computex has certainly had more attendees than I ever recall on the second day, and today was no different; there were a surprising number of people cramming all the aisles, and of course, jamming up the booths, which isn’t great if you’re trying to take pictures.

I also noticed that this Computex has far more business-to-business (B2B) focused companies in attendance. In the past, we typically saw strictly consumer products and the myriad of companies that feed into that ecosystem. This year was definitely an explosion of AI and data center technology, which is surprising. Also, the big showcases dedicated to data center hardware were absolutely packed, often just as busy as the ROG and ASRock booths of the world, if not busier. Others have noted that there really isn’t an Asia-based trade show for data center tech, and it seems that Computex has now become that destination at an incredibly fast rate.

Joe Shields: Staff Writer, Components

Day four is in the books. I managed to get about two to three hours of sleep last night, and it’s been a long day, even though I got all the meetings done early. Today’s journey began at the Grand Hyatt Hotel (Hyte), right next to the beautiful Taipei 101. Soaring over 1,600 feet in the air, the blend of traditional Asian aesthetics and modern engineering is a sight to behold.

Hyte showed off a few new items, including the Y50 case, a less expensive version of the popular Y50. We finally made it to the Gigabyte booth at the convention center and had a chance to see the X870E Infinity Next motherboard in person, and wow. It’s absolutely stunning with the 3D-printed metal heatinks and that lava-rock-like pattern. Be quiet! Showed off a few items, but I was impressed with the Light Base 803 chassis, and a new power supply (Dark Power Pro 14 IO) with software monitoring that even shows how much it costs to run your rig.

My last appointment was at Thermal Grizzly, who showed off new coatings for their waterblocks, new thermal pastes, and different versions of the WireView Pro for you RTX 5090 owners. By that point, I couldn’t tell if I was coming or going, and thankful all of my appointments were done. A little nap at the hotel and I am back to writing about Computex for the last night.

I’m incredibly thankful for the opportunity to come out to Computex. For me, it’s a completely different experience from CES in Las Vegas. Both have their positives and negatives. Tomorrow I’m excited to get a tour of Asus HQ, but really looking forward to starting the long, long trek back to the U.S. It was real, it was fun, but it wasn’t really fun. Ohio, here I come!

Jake Roach: Senior Analyst, CPUs

This was my last day in Taipei, and I tried making the most of it. The majority of my morning was spent running back and forth between the two halls of Nangang and talking with various companies, racking up some 20,000 steps in the process (the halls are literally across the street from each other). Some of the details of that tirade through the trade show I can’t talk about quite yet, but as the blisters slowly forming on my feet will tell you, I kept myself plenty busy.

My afternoon was spent at Asus HQ in the Beitou District (about an hour-long trek from Nangang on the MRT). I usually visit the Asus campus, and it is beautiful. There, I met up with several Asus reps and various other media to learn more about Asus’ announcements, as well as some products that are coming down the pike. But, as you might expect, I can’t talk about those quite yet.

Leading into Computex, the week always seems so long and grueling. And it is, make no mistake. But the irony is that right as I start to get adjusted to the 13-hour time difference and begin feeling like myself, I’m packing my bag to head home. It’s always too much time, but never enough. Oh well. I’m finishing my night with a nice plate of omurice, which I can not get at home, and trying to catch a few hours of sleep before spending 18 hours in a plane seat tomorrow.

Jeffrey Kampman: Senior Analyst, Graphics

After four intense days writing into the early hours, visiting vendor showcases, and criss-crossing the show floors at both TaiNEX halls, today was my last in Taiwan, so I once again headed over to Nangang before my departure to ferret out any last hidden hardware gems that we might have missed.

I walked through the massive Gigabyte booth with Joe, admired the company’s classy wood-trimmed Aero cases and Infinity graphics cards, and mused with Gigabyte staff about how the show and the industry have changed since I was last at Computex almost ten years ago.

DIY PC building is, for better or for worse, increasingly a guided, safe experience. The big component companies are now more than happy to serve you a full menu of coordinated parts that are practically guaranteed to come together into a coherent build. It’s getting harder and harder to find examples of earnest whimsy among booth after sprawling booth of Vera Rubin NVL72 racks and their supporting infrastructure. (Indeed, Vera Rubin NVL72 is so tightly standardized that racks from different server vendors are practically indistinguishable from one another!)

But my next stop was down the escalators to G.Skill’s booth, which maintains much of the freewheeling enthusiast spirit that I recall from my last visit to Computex so many years ago. If you want to see extreme overclockers chasing world records in real time through swirling clouds of liquid nitrogen, G.Skill’s booth is the place to be. And I got to go deep into the weeds with the company’s reps about DDR5 sub-timings, the resultant memory latencies, and their effect on modern CPU performance. After a week of parsing bold visions for the future of computing, it felt good to get back to the basics. Farewell, Computex, and I hope to be back in Taiwan soon.

Qualcomm's Snapdragon C is making a major play for the hottest laptop market in 2026: The ultra budget segment. But competition is stiff, with Apple's MacBook Neo and Intel Wildcat Lake Windows laptops offering strong performance and battery life in affordable packages - even with sky-high global memory prices.

We sat down with Qualcomm's SVP of compute and gaming, Kedar Kondap, and other Qualcomm representatives at Computex 2026 to hear how Snapdragon C fits into its existing product lineup, and how Qualcomm considers itself uniquely positioned to offer a comprehensive ecosystem of agentic AI devices and software.

This transcript has been lightly edited for clarity.

Kedar Kondap, Qualcomm SVP of Compute and Gaming: Our journey was not about solving what has happened in the past 30 years of PC innovation, but solving what's coming next in PCs. A lot of the innovation that has happened, we've obviously proved to the market that we're exceeding performance. We focused on three big metrics all along the way. One was leading with performance and making sure that we have leading performance in all of our silicon. We want to make sure we lead with power. Obviously, that used to be something super critical across the board, even as we start looking at newer generation of devices, and third, as you look at AI as a key metric.

When you think about the keynote today, and what we talked, what I shall talk about, as we enter this agentic world, it is more and more important. Each of these things play a very important role, whether it's performance, whether it's power, or whether it's AI, and the ability to run these intelligently. Right from whether it is a very small device, all the way to the data center. You saw how we're innovating, and the PC is no different. So we launched our X series processors, we extended that to the X Elite, the X Plus, and the X family. We launched the X2 Plus, we launched the X2 Elite, and the X2 Elite Extreme, and we wanted to make sure our intent was very simple: we wanted to make sure that the experiences we offer are available to all the consumers at every price point that we could address. What we introduced yesterday is a new class of platforms, the Snapdragon C. Our intent with that is to address platforms in lower price points that we can go and make sure that we can deliver the same performance pillar, the same battery life pillar, as well as provide AI functionality to all the consumers at price points that were never heard of.

So with that, we wanted to make sure that we have a full stack of products, we are addressing the needs of what consumers want. Consumers want the best performance, the best battery life, and as we enter this world of agentic beta, we want to make sure that across different devices, we're addressing all of these price points. So, we’re excited to be here, and I know there's a little bit of a longer introduction, but I want to make sure you have the perspective of where we come from.

Journalist 1: Thanks, Kadar. Nicole. You were just on stage with Advantech. Can you get us a little background on your announcements and what was said on stage?

Qualcomm Representative: Advantech has been a great partner of ours. I've done more recently the industrial business for Qualcomm, and so, you know, for us to get into this new area, and industrial is actually changing very rapidly. We are starting to see AI enter into the operation, advantage has been here in this space for a number of years, and so we announced a variety of different products to them over the last couple of years. Great to actually be at their keynote. We also announced yesterday [unintelligible] robotics reference design, which is something that is a new area for us. We've been partnered with Advantech for a number of years in this space, but the robotic session design will be a humanoid focus session.

Journalist 2: I'm wondering, Nvidia, a few hours ago, announced they were entering PC market. You guys have had it yourselves for the last two years. How are you thinking about how others come into [unintelligible].

Kedar: Welcome to the family [laughs]. We are, you know, we're excited when you think about the investments that we've made over the last several years, it's a good endorsement to the fact that there is an ecosystem that's growing outside of x86. We invested early on, we invested many years ago, with right from whether it is driving the ecosystem, driving the entire platform story. Whether it is getting the printers to work, whether it's getting the software apps to be compatible, whether it is getting the docs and peripherals to work, whether it's getting more than 2500 games to be compatible with Snapdragon, we led the way in driving that ecosystem, and I think this is positive tailwinds for the entire ecosystem. They'll tell us how we're all taking the ball forward in the trajectory that we started.

Journalist 3: This is for Nichole. She's had remarkable success in automotive and moving into robotics. Is there anything you’ve learned [unintelligible].

Qualcomm Representative: We’re learned a lot from automotive. I think AI at the edge with robotics is a really fascinating space, because you are starting to see this transition where you start to apply AI to start off with an unskilled worker, gradually start to go build up on level of skills, and ultimately start to get to something great. A lot of the underlying capability is similar to what we saw in the early days of automotive, especially the mobility part is quite similar. That will scale very quickly. We will start to see coarse dexterity, so that it's essentially transportation of goods, et cetera. That will happen over the next couple of years, and then the more complex final precision tasks will take more time.

But we are betting across the board, we are betting on models, we are betting on full embodiments. You'll hear more about this tomorrow. We're betting on a variety of different form factors with arms as well. We are also starting to look at what we can do in the end effector space, so we have a lot of technology around precision for the actual and effect of the arms, the actual digits, and what it is. What I like about robotics, which is quite different from the car, is that within the same embodiment, you have to have a lot of different technologies that cooperate, and that is something that we have a lot of capabilities. Lot more to come, but I think super interesting.

Journalist 4: When I was at the keynote from Jensen Huang, I was surprised when he mentioned the RTX Spark platform will support every Windows software ever written, and you suffered from Windows software in running on ARM. So, could you comment on that? And another question, if you could maybe share some more details about Snapdragon C platform, especially the TOPS. I saw a model from Asus, but it was behind in the glass box, and they didn’t have a lot to say of interest in that matter.

[Jensen Huang] mentioned that they will do an announcement tomorrow with Microsoft about the RTX Spark, and he mentioned that every Windows software that has ever been written will run on their platform, and this is not true for your platform, and probably for any Windows on ARM platform right now. So, I'm wondering if you want to comment on that.

Kedar Kondap: I don't want to speculate, but I'll tell you, our partnership with Microsoft has obviously gone several years in the past. We worked with them very closely. We launched the first Copilot class pieces together. We launched the first platforms where Microsoft OS supported it, and supported how these distributed computing work across a different course. So maybe once we start getting more information, we can, but I think I'm sure the engagement of Microsoft is strong enough where we work with them to build this entire ecosystem to make sure that it's compatible with Snapdragon and the architecture, so maybe once we get more information and get more, we can look at it.

The second question on Snapdragon C, so we haven't yet given out the specs for the products, but I'll tell you how I think about Snapdragon C. We wanted to, our OEMs are very anxious to bring this product to market, as is Qualcomm. There is, as we all know, there is a memory supply challenge in the market, and I've heard there's a storage supply that's also challenged, and we wanted to make sure that we have an offering where we can address a lot of price points that we've never addressed before, so think price points below what Snapdragon X has offered in the past. Snapdragon X will give you its relatable, you know, it's great platforms that get 599 today, some of them that hit 500 and above the X plus goes above and X Elite goes above that, so think it's a tier below what we can offer with Snapdragon X, and so our intent with that is to drive the same level of capabilities, obviously scaled to that tier, and what I'll tell you, it's just like the way we've exceeded expectations in launching specs of our products in the X series family of products. You should expect that the C in its class of products will lead its way, but we'll obviously give out specs for you.

Journalist 5: I've got a question regarding [Qualcomm’s] vision on how the tokens in a car, in a PC, in a smartphone and adapts and talk to each other. Cristiano said that we're going to need zillions of tokens, and they're going to be orchestrated. It means different parts going to generate the token, where it's relevant. Okay, like latency, horsepower. How do you gonna orchestrate them with your industry? Are you planning to build a software ledger, SDKs, or building a patented or open system? How do you plan in this vision to open everyone with a heterogeneous chip market, it's going to be difficult to make everyone work.

Qualcomm Representative: So I think it will vary by the ecosystem, but yeah, we will certainly build orchestrate the [unintelligible] where it does make sense. I'll give you an example of a car. We had already seen in the car a tremendous amount of content. You don't actually need, you can't even expect in many cases to be running models that all just have to go back to the cloud, just because of networking latency. So we have deployed already earlier this year 30 million parameter models in car. It depends upon what the types of use cases you're trying to run, but then if you think about this in the context of splitting search versus what it is that you're trying to run locally within the vehicle that is happening today. I think this starts to get more and more sophisticated as you start to define what is the use of the model at the edge.

So, with industrial, for example, we are starting to see already VMA is getting deployed in cameras when you have evidence at the edge, where you can annotate at the edge, send it out to cloud as an input, so it's going to depend quite a bit on which the ecosystem that you're trying to run your account. If you look at use cases like polling, if you look at use cases like search, those are probably obviously much more in consumer and enterprise nets, which should have different network orchestration, probably much more controlled by traditional ecosystems. An orchestrator is going to be a fairly standard offering as well.

Kedar Kondap: Aiden. I'm going to add a little bit more context also to what we'll just say, you know, the way you should think about how we think about overall income advantage, it's going to be the context awareness that you get across the various devices, and think of a personal knowledge graph that you build in the examples that he showed, right from whether you're wearing an XR glasses. We are able to connect. You can see what you see, you hear what you hear. You can have context awareness of what the user is doing. It's going to listen to what information you talk to when you're, say, at the doctor's office. You understand exactly when your next appointment is.

The ability for it to abstract all of this information, transfer that knowledge graph agentically into your calendar, into what your daily routine is, be able to take your personal information, whether it's talking about your healthcare routine. The goal that we see is first is to bring all of this orchestration together, and Qualcomm is uniquely positioned, as you can tell, right from whether it's a small physical personal device, whether it's a ring, or whether it's an XR glass, all the way from phones to PCs to automotive to robotics and data centers, we feel like we're in a unique position like one another.

Second, on the question about running stuff on device, now we've always said the world in the last two years. You know, I remember when we launched Snapdragon X Elite. We said with a lot of pride that, oh, we can run 30 billion parameter models. You know, today, fast forward that conversation, we showed 20 30 billion parameter models running on the C Snapdragon X platform. So, models have evolved. I can, what I could do earlier with, you know, accuracy of quantization and stuff, I can do a lot more than I couldn't do in the past. So the industry is evolving, where we're innovating, we're adding more capabilities to each of these devices on-prem, I'll say, or physically on device. At the same time, we know that the token economics, as Krishna showed, everybody in the industry see it?

So, if any of you use, if you have a poster subscription towards AI, you know you run out of tokens very quickly, and there is the fatigue is real, the fatigue on the side of a consumer, the fatigue on the side of the model. You cannot have both of those, the balance doesn't exist today, so the way we see it is one, you can connect all these orchestrations across the devices, same, you can orchestrate on what runs locally on the device, and of course we believe some of it will go in the cloud, and that hybrid orchestration is where we believe the industry is going, so build the knowledge graph across devices, run what you can locally on the device, if not, if the model is large enough, it will go to the cloud, and this whole equation will evolve over time as models start to become smaller, as they start getting quantized accuracies to be better.

What was, like I said, a 30 billion parameter running on a Snapdragon X, I can already run 30 billion parameters models quantized with very good accuracy. So that's how what we mean by this industry and ecosystem is going to change.

Journalist 6: I would like to touch on Snapdragon C again. You expect the platform to be a regional-specific solution, like for emerging markets, for example, and Qualcomm has great experiences in markets like India, for example, where do you expect it to be a global platform? And I'd like to touch on the NPU as well. Previously, every Snapdragon X platform, at least, had an NPU that OEM Certified Assistance for Copilot Plus seems to be the first solution where you sort of loosen your own set of requirements for a Snapdragon compute platform, and what led you to that decision?

Kedar Kondap: So, Nicholas, first I'll answer your first question, which is: it is a global platform. You will see this device launch globally. You know, for us it's there's a large stamp, as you know, in this particular segment. Lot of consumers that use PCs that sit in, I'll say, below the $500 price point. So, we have a large stamp that we can address there. The TAM [Total Addressable Market], as you know, is naturally biased towards emerging markets. So, from that perspective, yes, the focus, you'll see the platforms launch in many of the emerging markets, as well as developed markets. The TAM is much reduced in that, so it's just a function of the definition of where the time sits.

Your second question around NPU, no the platform does have an NPU, we just haven't talked about the sizing, but as you can tell, the silicon economics, we're sizing everything with the capabilities to be able to run use cases synchronously with the price point that we're addressing. So, think of it as you'll still be able to run, get a lot of the capabilities, you'll still be able to run a lot of use cases we talked about, while preserving the performance and battery life goodness that we bring with the Snapdragon product, so you'll see something very similar.

Journalist 7: There's been a lot of good questions on Snapdragon C, but if you're not competing with Neo, what specific product lines of products are you competing kind of in that below $500 price range?

Kedar Kondap: You know, you already heard a couple of our OEM partners talk about devices. I think Asus talked about the device. I want to make sure I don't jump the gun with the excitement that our partners want to launch it, but I think Asus has already announced. We've also addressed the fact that Lenovo, as well as HP, we announced with HP. Just want to give out somebody's information. We've announced with the OEMs, it will sit as I said, you know, Snapdragon X sits at around 599 type products, and it competes, as you know, better than what you can get with Neo and performance insights.

This gets the price points that it would be below 500, obviously. Now, the thing I always have to caveat is the memory and storage prices. I never know what it's going to do to devise price points, but that's how the platform is positioned. Think of it as small core competing products, but you know I'm nervous to say that, because it's going to be so much better than what existed in the market, so that's why I don't want to tell you that it's compete against that, because it's a different class, it's going to be a lot better than what's what you're used to seeing in market,

Journalist 8: Sorry to ambush you with another Nvidia question, as I know you already said you didn't see the announcement. They are going after a market that you guys have historically not went after, I think a few years ago you publicly said this is just not our wheelhouse, so are you guys planning to compete with what Nvidia is doing now, and if so, how?

Kedar: Like I said, I haven't seen this. I don't know what they've announced, but at the end of the day, look, we've come a long way from where we started. We go a couple years back, what we said, Rich, was we have the legacy, we have the technology in even things such as gaming. We come from, as you know, we have a very strong game studio house. We work with all the game engine guys to work with the net engine guys. We work with the studios on the mobile side and other platforms that we work with, but we bring all of the games to Snapdragon. Since we launched Snapdragon X in less than 24 months, we've done a lot of games that work with Snapdragon effectively go from 1300 to more than 2500, 2600. So I think what we've mentioned in the past is not that we couldn't support it, what we've said is we want to carefully not position this as a gaming laptop, right? The gamers who think of launching this as a AAA game-based laptop is not what we want to position.

We don't want to create confusion with what we're addressing, but from a technical perspective, nothing prevents us from addressing a lot of that, because, as you know, even when you think about creators, we've talked about our partnership, and what we've done with Adobe, what we've done with Black Magic, and others. So, we've already showcased that the entire creative industry is something that we support. We sold multiple use cases, so it's the entire ecosystem that already we've been addressing. So, like I said, I'm assuming that their introducing their platforms in market today is tailwinds for what the ecosystem will see as a strong showcase of non-x86 architecture.

Journalist 9: On the question of the Snapdragon C, somebody spoke about the emerging markets. One of the things which has happened in those emerging markets that arise on the tablet usage. So in the past three years, four years post pandemic, you can say that many of the people are buying who are stuck between a rock and a hard place, that you know, laptops are slightly expensive, they have a full use case of the productivity of a laptop, but they wanted a slightly bigger screen, so they are buying with sliders and the keyboard, especially the emerging markets. So, I just want to ask you, is your target that consumer, and do many of those cohorts is parents buying for the kids or education market, private or public, both? And the public market, you know, you know some of the PC loans, they've really done well, and they are restricted that success in the past year or so in education and some of those emerging markets, because the price points are creeping up now. So I just wanted to double click on that. Who is that target consumer in those emerging markets where we expect the volume to come from?

Kedar Kondap: So, as you know, we already play in a very strong manner with the Android tablets in all of those ecosystems, we have very strong partnerships across almost all the OEMs that you can think about. We have Samsung, OV, WOSU, Lenovo. We have all of these tablets that have launched. There are specific tablets I've launched that are focused on gaming all the way to productivity, all the way to education. So we have very strong portfolio products launched even in emerging markets with our partners.

With Snapdragon C, I can see a market out there, as you correctly pointed out, education being a very strong segment would address all of that. So, if you saw the press release that we talked about, which Snapdragon C we specifically call out that we will be in the education space. We are doing a bunch of pilot programs with our partners to go and address that. I wouldn't necessarily say that it's going to replace Android tablets, necessarily. I think hard to call whether that ecosystem is going to move away from Android to Windows, but right now they coexist pretty well. Like, there's a good TAM that's available for Android tablets with a stylus, as you correctly pointed out, as well as a TAM with Windows PC, and I think with this particular one, for now we'll be launching the Windows segment.

Journalist 10: Can I talk about we just launched, like Qualcomm with Asus A16? Will you deepen with Taiwan cooperation?

Kedar Kondap: I can't tell you how grateful I am for the partnership with the entire Taiwan ecosystem. The partnership goes obviously deep partnership with the ASUS, and we're grateful for the partnership with ASUS, brings a lot of innovation and market. If you've seen, if you haven't already played around with it, or if you haven't seen it, I encourage you to look at the A16 device with the Snapdragon X2 Elite Extreme product. It's a beautiful, thin, light laptop with significant hours of battery life, so it's a, it's a beautiful laptop, and that's because Asus brings a lot of innovation. You heard yesterday from Acer with the Snapdragon C platform that they're launching, but it goes beyond just the OEM partnership for us here in Taiwan, right?

We work very closely with all the BIOS guys, whether you know all the IBDs, we work with the inside, we work with AI devotees, we work with all the partners there, we work with all of the EC manufacturers, we work with ecosystems, so it's not just one cookware, we work with the camera sensors. So we do a standard ecosystem partnership summit here in Taiwan, the offense is just because innovation is going to happen here, and I think what you hear, even as I speak on Wednesday, is as we talk about what we try to throw the vision of moving to agenting, it's going to need a lot of innovation, that innovation is going to change the way the PCs are going to look, is going to change the edge appliance market, is going to change, because now you're going to be running these hybrid models, running and stuff, and we really believe that Taiwan is the hub for driving innovation, and, like I said, we're very grateful for the partnership that we've had with this ecosystem for the last many years.

Journalist 11: Looking towards the intelligent orchestrator for managing workloads. Do you see a primary device managing the personal AI agents? Would it be a smartphone, a transportable puck, a locally hosted cloud instance, for example?

Qualcomm Representative: I think the orchestrator is actually going to be associated with the user, so it's going to be a personal orchestrator, and the devices will evolve along that orchestrator. I think it depends upon the specific ecosystem that you refer to. So, let me pick an ecosystem that may be different from a personal device that is owned by an Apple or Google system. There are several ecosystems where the personal draft, for example, is specific to the enterprise that would like to own that specific data. It could be within an industrial environment, it could be something that requires the data to be resident within the premise owned by that specific enterprise.

In those environments, it really just comes down to what is the type of data that is being exchanged, whether it is data at the edge, data that is network specific, that is manipulated, that is interacting by the specific data. As you start to think about this in the context of the enterprise, I think, depending upon the type of data that this might be, so if it's a personal device like a camera or my glasses, then it starts to move towards the context within the data, there will be changes in the interaction, so for example, today if you think about enterprise data that is sitting on your laptop, that is part of your email, that is part of your SharePoint. How does that interact with the personal devices that you have? Those are things that, in my mind, are still going to get sorted through, but you're going to start to see the personal graph nature move more and more towards the user itself as a personal device.

We believe that the cross-device, as I said earlier, is what will play a super important role. The context awareness from the agent having access to your personal information and bringing that context to information from one device to another, and being able to drive that continuum, is what's going to differentiate more common. We feel we're in a very unique position to be able to go from pocket all the way to the cloud in driving that entire ecosystem.

Journalist 12: I have a question about the economics of the new world you mentioned already, the memory crisis, the skyrocketing memory crisis. I would like to know what impact you expect of the rising memory prices on the development of these agents in future on the consumer side, enterprise side, but also maybe on the other platform side.

Kedar Kondap: I think let's separate out two different things. One is we've all people that have been in this industry long enough to know the sequential nature of what happens with memory. Of course, this time is an anomaly in terms of what we're all seeing. I respect that, but at the same time, we know that eventually the supply chain economics balance out with that, right?

Like, over time, it may not come to the same levels as what we've seen in the past, because this is obviously a super cycle in terms of memory that we've never seen before, largely because of the needs of what AI, what the ecosystem needs. At the same time, though the token economic problem is a real problem, which is you as a consumer you want to be able to use more AI and you want to be able to be more efficient with what you're trying to do, but you're there's only so much in terms of affordability, same thing on the enterprise side, all of what you think about op-ex moving to capex, you have to be able to have that migration happen where you see your op-ex that you invested in and you're going to start moving to capex, or you're going to start getting every employee is going to get multiple models and drive that efficiency that you can get as an enterprise that you want, that migration is going to happen once you move to the other side.

With that migration, the entire equation of economics changes. Why? Because now, if I'm an enterprise, I know that running stuff on device… I'll give you an example, if I can now start running 5070 100 billion parameter models locally on prem, whether the device is a laptop, whether it's a 5 billion parameter model that runs on a phone, or whether it's an edge of line that sits in my desk running a 50-100 billion parameter model, or it's an influencing card that sits in on-prem, I know that the token economics dramatically changed, but I also know that as an enterprise to be able to run trillion parameter models, I'm going to go to the cloud, but I know I need to invest to be able to run on device.

So this balance of equation is what's important, and we feel like this is where we've always said the world is going to go hybrid, we've always said it's not once you're done with training in the cloud, it's going to start moving to the edge with your inferencing, and we feel very good about the position we're in, because that's where we've been investing for the last several years to drive this on device as well as hybrid approach.

Journalist 13: While wireless transition is a very big effort [unintelligible] has put a lot of time in those transitions and a strong focus, you almost single-handed move the industry to the next level, and that Qualcomm changed a lot, now it's more, much more diversified. So, my question is, is Qualcomm from today able to have the same focus on the safety transition in the future, or it may be more help from the industry?

Qualcomm Representative: We are wireless company first, so yes, we have a lot of focus on safety. I think wireless is in the DNA of the company, and wireless is really part and parcel of everything that we do. I mean, if you think about the complexity of building a cell phone, then there is a reason why very few companies are successful with these things. I think the 6G transition, maybe just to speak with 6G, is a very interesting transition, because we believe that the networks are going to actually become very intelligent in 6G, you'll be able to get a sense of creating a virtual digital trend of environments around you. It will bring telcos into the fore in terms of being able to get a much better sense of the physical world. It's a major area of work for us, and these G transitions take a decade, right? So you know that it took a decade for us to be develop 5G.

Journalist 14: Kedar, you answered a couple questions already on the personal graph and that comment about the agent moving closer to the user. I get the point that Qualcomm spans across multiple devices, and that they're, you know, that you're at a unique advantage because of that. But can you take us through how that would be architected? I guess inevitably, if it's spanning across devices, cloud has to be involved in this process, right?

Kedar Kondap: I think Brian, the way you should think about it is, first, we know that the entire ecosystem is fragmented, and we believe that as different hyperscalers, as different model providers, as different OS vendors, as different silicon vendors, all of these need to come together. We were not giving out much information today on what we're doing there, but as you can tell, what we are trying to indicate to the industry is today we have the ability to thread all of these things together, and we're uniquely positioned on how we want to do this over the next several months. We will come out more with respect to how we want to be able to tie these together, but the industry challenge that you highlight, and that's why we feel like we're at the center of driving innovation across this to bring this industry along to try something that's innovative.

Journalist 15: I'm going to be one of those guys who brings it back to the ARM thing. I'm just going to read you what Jensen said in his keynote, because I think I'm just going to read it deadpan. “This computer literally runs everything the world has ever created, and it runs agents.” So I don't know if that's true, but I kind of wanted to give it to you, and kind of hear, what are you guys working on in terms of like compatibility, or even emulation, because we've seen a lot of interesting ARM-based emulation coming from like open source places, so is there anything you guys are working on in terms of compatibility that is trying to push things forward?

Qualcomm Representative: I don't know how to use a broad statement like this to give you a full answer, but I'll tell you what we'll do today. There's about the last night track with my team, was we were worried about 50 claws that are available in my team, and from a snap back in perspective, X series perspective, these are run on the device, I think Krishna showed a bunch of these, a bunch of claws that he showed on stage, so you should imagine that we're, we've been leading the industry with driving agentic AI and orchestration on the PC for the last couple years.

So a lot of these models already exist, a lot of these claws run very effectively on Snapdragon, the models are running effectively on Snapdragon, so you should just assume right now that we've shown you the data that we're already dealing with industry with tight innovation.

Journalist 16: Do you see robotics requiring the two layers of intelligence like with autonomous vehicles, or will the user interaction be more integrated with its physical functionality? Essentially, will the robot-human interaction be controlled more on the user side or the robot side?

Qualcomm Representative: I think that is going to predominantly be very similar to what they can do today already. So, language in the primary interface, what the human is talking about. Where it starts to get interesting is when you start to get into responding to a command. So, for example, if the human would like the robot to go do something that kicks off a task for the robot to be able to complete, and that is usually not a question answer conversational type interaction that usually requires the robot to be able to take on a longer horizon task that brings in additional models that bring in additional tasks that are outside of what humans might typically engage in, but the primary interface will remain the same conversation.

Journalist 17: I'll bring it back to Nvidia. I just want to add that from a CPU and NPU perspective, I think, from a GPU perspective the RTX 5070 class, what I have been missing is like what is called Qualcomm’s view from the GPU premium side of the market. Let's say personal computer market, so I need a bit of clarity there, and the second part would be to just focus it towards the developers and the AI community.

Kedar Kondap: Let me tell you, let me address your first question, which is when we look at launching a particular platform in market, whether it's the Snapdragon X Elite, the X Plus or the X. We always look at what the market needs, and we have a way to size where we feel like workloads are best run on a platform. It's the composition of how you could think about silicon. We have a very powerful GPU. We have the IP that we've invested in the high-performance GPUs and CPUs in-house for the last many, many years. We have to make sure that we're addressing a certain price point from X Elite to X2 Elite and X2 Elite Extreme. We size a significant improvement in our GPU performance, largely to address a certain set at the same time. You have to know that where we're shipping products are in certain price points with that target ASP in mind. I don't know what the industry is looking at with newer platforms are getting launched in market.

I haven't seen any of that data yet, but I'll tell you, all the cores that we support are sized to do that. With respect to their second question on developers, we've come a long way today in terms of where you see developers. Like, the entire developer ecosystem is behind what we've done. I talked massive numbers in terms of apps ecosystem, we talked in terms of developers porting apps natively on platforms, natively on Snapdragon, optimized to the NPU, so we have all the tools, everything that we've provided. So I think you should just expect that as we start moving into this new era of agentic…

Brian asked the question of how we're going to bring all these together, you should assume that we're working with the entire ecosystem, because I'll repeat what I said earlier. We are in a very unique position to be able to bring all of that orchestration, so whether it's a wearable, like an earbud or a watch, all the way to whether it's a PC all the way to whether it's a tablet, auto, XR, you name it. We're going to make sure that we're sizing all our platforms and technology to what the industry needs for that particular segment, so it's very segment-based in terms of how we look at the market.

[Session Ends]

With the show floor officially open, there's plenty to see and do at the Nanggang Exhibition Center at Computex 2026. However, the reality is that for most of our team, that's not the only place that they will have to visit. At events like these, companies regularly schedule meetings outside of Computex 2026 itself, either to secure more space for their products or to show off products and concepts that aren't strictly ready for the show floor and the thousands of attendees.

In our Day 3 blog, our team of staffers has crossed Taipei, photographed exciting new hardware, and experienced the dizzying halls of TaiNEX 1 and 2. If you've not caught up on their journeys so far, be sure to read Day 0, Day 1, and Day 2 first.

Paul Alcorn: Editor-in-Chief

Another blistering day in the heat of Taiwan started with a meeting with a high-ranking Micron executive to talk about the state of the memory and storage industry. I learned a lot that I will crystallize into an article soon.

After that nice air-conditioned chat, I hit the halls, moving between multiple vendors to see the latest the industry has to offer. Asus, ROG, MSI, Patriot, Adata, and many others kept me busy throughout the day, particularly as I dug deeper into the side effects of the memory shortages. Unfortunately, not a single individual we spoke with expects any sort of recovery soon, and this will have dramatic effects on smaller module makers, the companies that make SSDs and DRAM, and a cascading effect on the other OEMs.

In fact, though Computex easily had record attendance, the halls were busier on day two than I have ever seen in my 15 years of covering this event; there were relatively few substantive announcements on the PC front. In fact, even the announcements on the data center and ODM side were exceptionally light, largely due to the impacts of supply shortages and the resulting uncertainty that has slammed the brakes on new product development.

Joe Shields: Staff Writer, Components

Three days in, and another day of 90-degree heat. It’s amazing how you can break a sweat here just by walking outside early in the morning. Today’s adventures included floating back and forth between the halls and meeting with several companies. I’ll tell you, if I see another booth with CDUs (Cooling Distribution Units), copper water blocks for AI servers, or PDUs (Power Distribution Units) supporting the AI Data Center boom, I’ll explode.

The highlight of the day has to be my second meal, Mushroom Risotto and Steak. But, because I was so entrenched in work, recovering from a spate of unexpected poor photography on my part that nearly brought my work, well, one article, to a standstill. Afterwards, I just went to bed, physically drained and mentally wiped out. Sleep… Now that’s an escapade.

There’s nothing like crashing when you’re mentally thrashed and waking up a couple of hours later practically wide awake—damn this time change. Tomorrow I’ll be all over the place, with my first meeting at a hotel, two back at the convention center, back to the same hotel for another meeting, and finally back to the convention center again. It’s certainly not the most efficient logistics, but that’s how the cookie crumbles at events like this. The most interesting man in the world says, “Stay thirsty, my friends,” but I’ll say, “Stay hydrated, friends.” One more day to go.

Jake Roach: Senior Analyst, CPUs

Well, I had to open my schedule to find out what I did today in order to write this, so if that’s not a testament to where I’m at in the Computex arc, I don’t know what is. I started my day with my final AMD roundtable of the week, this time focused on ROCm, before taking the MRT down a few stops to Intel’s demo showcase. I met with Dell and Samsung Display in the afternoon, taking a look at the XPS 13 and Samsung Display’s new QD-OLED panels, but much of my day was spent running around to various vendors, chasing down a few key stories (stay tuned on that front).

There are a lot of products at Computex, and it’s impossible to cover them all. But the most interesting conversations happen around the products, not explicitly about them. Although my gung-ho attitude earlier in the week is starting to catch up with me, I’m hitting a sleepy second wind as we close out Computex and start to peel back the curtain on what the broader industry thinks about where things are headed. Also, man, it was hot today.

Jeffrey Kampman: Senior Analyst, Graphics

I began this witheringly hot Wednesday with a surprise trip to the TICC, where Nvidia has set up its enterprise demos for this year, for some quick conversations with the leaders who are guiding the rollout of Vera Rubin and paving the way for the agentic AI future in the data center.

From there, I hopped onto the blessedly air-conditioned MRT and headed back to the Nangang Exhibition Center to criss-cross the show floor and visit some of the biggest booths at the show, including Asus, Asus ROG, MSI, and Gigabyte. And for as tough as it is out there in the consumer PC space, it’s still hard not to feel a sense of awe and wonder when you’re standing in the very center of TaiNEX 1, surrounded by countless thousands of tech enthusiasts and industry professionals, all of them hyped up by the dizzying array of new and sometimes wild stuff on display.

I closed out the day by visiting the fine folks at Noctua with Editor-in-Chief Paul, where we got a thorough deep dive into the company’s obsessively engineered solutions to problems that many PC builders wouldn’t even consider problems. Would any other company contemplate placing a tiny tuned mass damper on top of an all-in-one liquid cooler pump to smooth out its noise signature? Probably not, but Noctua did, and my ears are sensitive enough to this kind of thing for me to be seriously interested. For now, though, I am desperately in need of rest.

With the first few days firmly behind our team on the ground at Computex 2026, Day 2 is the first day that our crew got their boots on the ground on the show floor of the Nanggang Exhibition Center in Taipei, Taiwan. With a busy schedule of meetings, interviews, and presentations in tow, it's been a busy few days, and we're now deep in the throes of covering the event. This series of diaries from our team is intended to give you insights into our thoughts and feelings about covering a massive event like Computex 2026, documenting the trials and tribulations that naturally come with event coverage.

If you've not read them yet, be sure to check out our Day 0 and Day 1 Tom's Hardware Unfiltered blogs to catch up on what they've been up to so far.

Matt Safford: Managing Editor

As I hauled my increasingly complaining body through eight meetings today, I heard a familiar refrain from multiple case and cooler makers: they’re focusing on lower-cost designs (often sub-$100), because they know how cash-strapped gamers and PC builders are, thanks to the ongoing RAM, storage, and GPU pricing crisis. And to be fair, they are trying to sell PC hardware to cash-constrained consumers at perhaps the toughest time for our little hobby/obsession in decades. So, of course, the focus is on lower-cost components and hardware.

Asus, meanwhile, in celebrating the 20th anniversary of its ROG sub-brand, launched an expansive lineup of mostly rehashed Edition 20 products, at some of the highest prices I’ve seen. Take the $599 gaming keyboard, for example, or the $250 mouse. I tested them both, and they’re generally great, with high-end specs and solid performance. But they’re also wildly expensive at a time when key components (not to mention gas and groceries) remain sky-high. It’s easy to call Asus’ Edition 20 launch tone-deaf (did I mention that many of these products feature real gold-plated accents?).

But I can also see why the company (and ROG die-hards) would want to celebrate 20 years of a sub-brand that, let’s face it, has generally offered up high-priced (and generally well-regarded) hardware. But I would love to know how successful the Edition 20 lineup turns out to be, six months or more down the road. Because it’s hard to imagine throngs of people excited to buy a $1,000-plus gaming chair, or the many other high-priced Edition 20 products. But I can certainly imagine lots of people, many of our readers included, looking for a PC component bargain after shelling out for 32GB of RAM or a 2TB SSD at today’s prices. Maybe Asus should start thinking about those kinds of customers, too.

Joe Shields: Staff Writer, Components

Today, Cooler Master HQ was my first stop before heading to the Convention Center and more traditional booth visits. I have to admit, it was a bit overwhelming at first, trying to find my first meeting location and navigating through a sea of people everywhere, but mostly because I left my schedule with all the time and location information back at the hotel (thanks, Jake Roach, for the save!).

It’s very different from CES, where most companies have their own suite or ballroom at one of the Vegas hotels, and it’s a little more private. Outside of that, I had my first taste of 90-plus-degree weather with over 70% humidity. Even walking across the street to the other Hall, I broke a sweat. Oppressive when you’re not used to it. Even though I have almost twice as many meetings tomorrow as today, it doesn’t feel as intimidating after going through it all today, and all but the last meeting are in the same location.

Jake Roach: Senior Analyst, CPUs

I spent yesterday with Intel, so today was spent with the other guys: AMD. I sat in on three roundtables today with AMD’s Rahul Tikoo and David McAfee, discussing everything from the EXPO ULL to AMD’s reaction to the RTX Spark. I also spent some time in an Intel Q&A post-keynote, where I asked the company about its rumored 3D V-Cache competitor, and it gave me the exact answer I expected — “stay tuned.”

Despite being chipper — Paul (Alcorn) even said I looked “peppy” today — I am waiting for my body to crumble in on itself. I am beyond dehydrated. I haven’t been eating anything until the very end of the day, and there are other issues that I will spare you the details of. That’s a problem for future Jake, however. Current Jake is excited to look at chips.

Jeffrey Kampman: Senior Analyst, Graphics

My agenda today was once again dominated by Nvidia. We were back at the Grand HIlai early to attend a press Q&A with an undercaffeinated and punchy Jensen Huang, who was by turns happy to discuss the RTX Spark platform and unhappy with members of the press who failed to ask what he considered to be good questions. After that, we got hands-on time with RTX Spark laptops from five of the six major vendors who will lead the charge when these products come to market this fall, and we picked up some interesting details of those products that have been hard to come by from official channels.

After those briefings, I finally picked up my Computex badge proper and got a bit of floor time at the Nangang Exhibition Center, and I’ll be back tomorrow to visit more booths. The show is truly in full swing now!

Intel launched its Xeon 6+ "Clearwater Forest" processors at Computex 2026 in Taipei, and on Monday, two of the individuals responsible for the product sat down with the press to answer questions. Kira Boyko, Product Line Director for E-Core Xeon Products in Intel's Data Center Group, led the session, which was joined partway through by Tim Wilson, Vice President and General Manager of Intel's Data Center Silicon Engineering group.

Across roughly half an hour, the two addressed why Intel stripped hyper-threading out of its E-core server parts and the technical case for bringing it back, the agentic AI demand surge that has left expensive GPU fleets idling while they wait on CPUs, the deliberate decision to ship Clearwater Forest with only AVX2, and 18A supply so tight that allocating chips between customers is "daily, in some cases."

Diamond Rapids, Intel's next P-core Xeon, drew repeated questions, but Intel deferred any detail, with Evangelista pointing reporters to fuller commentary roughly two months out. That timing lines up with Hot Chips, where Intel is expected to share more on Diamond Rapids.

Clearwater Forest spec changes

Clearwater Forest tops out at 288 Darkmont E-cores per socket and 576MB of L3 cache, and is Intel's first data center CPU built on its 18A process.

Kira Boyko: It's our most performant Xeon on the market today, specifically for scale-out workloads, so it's not just a per-watt angle of fossil performance.

Jake Roach, Tom's Hardware: Was that the driving force behind the big spec changes compared to Sierra Forest? Obviously, it's double the core count, but I think there's over five times the amount of L3, and a huge increase in TDP.

Kira Boyko: The TDP is mostly that it is socket-compatible with the version of platform design that we had for Granite [Rapids]-AP before, and that is a higher-TDP product. Our initial E-core part was lower TDP, and this one has roughly the same range as the Granite version, so that's part of the platform-design alignment. But in general, we found that our customers were mostly targeting higher-TDP spaces anyway for the core density they were after, so it ended up working quite well. We already had a design that served those spaces.

Jake Roach: And the L3, was that another workload type?

Kira Boyko: You're right, a little over 5x increase, from the hundreds up to 576-ish [MB].

Jake Roach: If you have the flagship, that's quite a lot of L3.

Diamond Rapids and hyper-threading

On its recent earnings calls, Intel CEO Lip-Bu Tan has said that moving away from simultaneous multi-threading (SMT) "put us at a competitive disadvantage" and that the company will reintroduce it with the Coral Rapids generation, the P-core Xeon that follows Diamond Rapids. Intel's current shipping E-core Xeons, Sierra Forest and Clearwater Forest, run a single thread per core.

Jake Roach: I appreciate that we can't comment on future products, but there was a tease in the press deck for Diamond Rapids. It's a very anticipated product. I want to ask about hyper-threading. During the last two earnings calls, Lip-Bu Tan has referenced that hyper-threading will return with Coral Rapids. We don't currently have a Xeon P-core product without hyper-threading shipping. Does that mean Diamond Rapids does not have hyper-threading?

Andrew Evangelista: We'll comment more on Diamond Rapids [later].

Kira Boyko: I will say that E-core is single-threaded. It has the core density for the workloads it's servicing, and we are not expecting it to be replaced by Diamond Rapids. We're expecting the workloads that need more of the high-performance aspect of a P-core to go from Granite to Diamond, whereas the more scalar workloads for E-core will stick on Clearwater Forest, continue to be serviced through this next generation, and then pick up with the generation after that.

Andrew Evangelista: I think it was your question that prompted us to talk about Diamond Rapids in general. More to come.

Kira Boyko: The only thing I can really say from a Diamond perspective is AET, the new feature we're introducing on Clearwater Forest. That is expected to roll out across all of our Xeons going forward, so you can expect to see it on Diamond and future ones as well. What the roadmap looks like from a feature perspective gen to gen, I don't have any level of detail for today. But it is definitely being introduced in Clearwater. We have a number of customers deploying it on Clearwater, and others who are more classic P-core customers, with different workloads, running proof-of-concepts on Clearwater so they can hit the ground running with Diamond.

Jake Roach: I had to ask.

Kira Boyko: You're like, "That's not what I wanted, I wanted way more detail."

Jake Roach: There are a lot of articles that have been written saying it's confirmed Diamond does not have hyper-threading, and I haven't been able to find that confirmation anywhere.

Kira Boyko: There's a lot out there on Diamond that is all over the place. There are statements about [unclear] variants, and just a lot of rumors.

Andrew Evangelista: We'll have more official commentary to come, and that's what folks are anticipating. We understand there's excitement, and we'll share more [in two months].

Agentic AI and CPU demand

Journalist 2: What are customers telling you about this agentic AI wave, how they're dealing with it, and how Intel plays into that going forward?

Kira Boyko: Customers are just starting to understand their own AI deployment models, and a lot of them still aren't quite there yet. Many started by investing in GPUs and are now realizing they don't have the CPU counterparts to actually keep those GPUs going. So they made this huge investment, and they're running at something like 20% to 30%, something quite low. They're understanding that there's this space where certain workloads can be offloaded to more efficient CPUs, and that's exciting from a Xeon 6+ standpoint. Others are still going to be partnering with their providers, looking at industry white papers to understand how to best use their AI strategy.

Journalist 2: Just as an outside observer, it seemed like CPU demand was going, and then November and December happened, and everything got sold out instantly. What percent of current demand is agentic-AI-driven versus prior? I'm trying to get a sense of what it is now, and what it's going to be like six to nine months from now. It seems like a paradigm shift happened, and we're going to be riding this trend for several quarters at least.

Kira Boyko: I think we are. I think we're also going to see quite a bit of data center modernization and consolidation, looking at what workloads are already out there that can be consolidated onto CPUs. Some maybe are designed for agentic, maybe aren't, but are more storage-oriented, or workloads that can be serviced just fine on something that isn't super intense. So you can get a little more performance and energy back, and then use that to service some of their AI workloads as well.

Application Energy Telemetry

AET, or Application Energy Telemetry, is a Clearwater Forest feature that gives operators application-level visibility into energy use, which Intel says can be used both to tune workloads and to bill customers on measured rather than estimated consumption.

Jake Roach: You mentioned AET, and I know that's a really big thing with this launch. Is there any connective tissue with what we saw with Arrow Lake Refresh on the consumer front? AET is taking information from actual registers in the silicon. There's hardware on the chips doing it. Similarly, with iBot on Arrow Lake Refresh, it was hardware-enabled, where you could get these readouts running workloads and see where they could optimize. Is there any connective tissue there, or are these completely separate?

Kira Boyko: We can get back to you on whether there's some collaboration. Usually our teams are very separate, but it's very possible there is some, so we'll find out. My understanding is that this is highly customer-driven. Sometimes we leverage existing technologies.

Jake Roach: This is more to satiate my own curiosity.

Andrew Evangelista: Let me grab Tim for a second to answer that, because that's a silicon-engineering-level question. He's worked on both client and enterprise.

Jake Roach: Yeah, just because you're using Darkmont, there's at least a capability there.

Kira Boyko: Touché. Moving on to the next generation, which is not an E-core, it'll still be there as well. So even if there was some synergy, it would be moving forward to a different core base.

Andrew Evangelista: Circling back on two questions. One was similarities related to Arrow Lake.

Jake Roach: Basically, the hooks in Arrow Lake Refresh for iBot to optimize that translation. Are those hardware hooks something you're looking at? Is there any connective tissue there today?

Tim Wilson: I haven't looked at Arrow Lake in quite a while. To first order, I'd say fundamentally no, they're different use cases. Are we leveraging some of the same telemetry capability built into the hardware? It wouldn't surprise me.

SMT removal and its return

Intel split its Xeon 6 line into P-core parts with hyper-threading, such as Granite Rapids, and E-core parts without it, beginning with Sierra Forest.

Andrew Evangelista: The question on the decision for SMT and hyper-threading.

Journalist 2: Just why it was taken out, what the thinking behind that was. Was it a security thing?

Tim Wilson: I have a lot of my own personal thoughts. If you step back to the data center a couple of years ago, the thesis was that what matters is maximum core performance and then core density in the socket. So if I can deliver maximum core performance and increase the number of cores in the socket, do I really need [SMT]? One or two physical cores are always better than two virtual cores built on one physical core. I fully expect we will see use cases and workloads where that decision is incredibly useful and valuable and gives real-world value, and we've heard from some customers that, for what they're doing, single-threaded is the right answer. Having said that, there's a big portion of work that is still very much multi-threaded, especially in the virtualized space, so completely eliminating it is a problem, because we cut off some not-insignificant portion of workloads, especially when you're in a virtualized, licensed environment where licensing is based on cores and threads. So there was a technical reason for why you'd want [SMT], and that technical reason probably still holds. [...]

Journalist 2: Like a VMware thing, with a big price on cores. How are you going to market versus your main rivals, like AMD, and now Nvidia? What's the messaging going forward? From 18A to what's next, you'll be much better on the node side.

Tim Wilson: Our intention is to have leadership products with every generation, and we fully intend to do that going forward. Our go-to-market strategy is to sit down with customers and ask what they value, then go build leadership that meets those needs. With all our data center customers, we have deep discussions around the personality of the platform they want to build, beyond just cores and feeds and speeds. What is the system balance, the memory-to-compute ratio? How are they viewing multi-socket versus single-socket? What's the right number of cores for their workloads, for both private and public workloads, enterprise versus cloud? It's really sitting down in each of those and asking what the markets and customers buying our parts value, and how we optimize our products to meet their needs.

Journalist 2: Is that changing now with this agentic AI demand explosion? Are we going to see CPU racks with agentic AI as the primary use?

Tim Wilson: I'm sure you will, just like we've always built CPU racks. There are principles around CPU design that have always been true and will continue to be true. You want the highest-performance core you can build. Power efficiency is always going to matter as long as we're constrained by the amount of power you can bring inside a building's walls and the heat you can extract from them. Your memory-to-CPU harmonics, how much memory each workload takes, how much you allocate to each core, those are key. We've always designed for those parameters, and the end markets evolve over time.

Agentic AI is now exploding, but what's driving that explosion is not a new type of CPU. It's that the new AI workloads are not one call, one inference, one response. They're complex, execution-driven, multi-task queries that involve tens or hundreds of agents, and suddenly you need a control plane and an orchestrator, tasks the CPU is historically good at. How do I take a complex task and decompose it into subcomponents, figure out which can be parallelized and which depend on each other and need to be serialized, and pass those off to the GPU? I have to map memory to each of those subcomponents, and not all of them want the same memory, and I have to make calls to I/O, and in some cases to the OS or APIs.

Those are all things the control plane and orchestrator, the CPU, does really well. As you move away from a chatbot answer to "go do this analysis and give me a report on the actions I should take," that's a much different query, and the CPU plays a much bigger role. Data centers that have built on GPUs for the last three years are suddenly finding they're bottlenecked by the CPU. They have a massive GPU fleet that costs billions of dollars sitting idle, waiting for the CPU to respond. So do I see a future with agentic AI and CPU racks? Yes, but with characteristics very similar to the sorts of things we've always built into CPU racks. It's exploding because the things the CPU has always done well are the things in demand now.

Journalist 2: It seems like the whole storage infrastructure has to change, too.

Tim Wilson: That comes along with it. There's demand for storage, which drives I/O advancements and connectivity.

18A yield and wafer allocation

Clearwater Forest is a multi-process design: the compute tiles are built on Intel's 18A node, with base tiles on Intel 3 and I/O tiles on Intel 7.

Journalist 2: Questions you probably want to ask but won't answer. 18A yield volume for Xeon 6+, progressing?

Kira Boyko: We're ramping well. We have strong demand throughout the lifetime of the product, and we're working from a capacity standpoint across all of our products to hit customers at the point in time they need most. Compute is 18A, but we also have base on Intel 3 and I/O on Intel 7, so it's a multi-process product. We're mapping demand against all of our other products to figure out where we need to build.

Journalist 2: How do you choose who gets the product in this compute-supply-constrained world? Is it whoever orders first? You're sold out right now.

Tim Wilson: We give as many CPUs to as many people as we can. It tends to be more business decisions than engineering decisions, so it's a combination of long-term deals and customer relationships. The biggest problem is not demand in any way, shape, or form. The biggest problem is how we satisfy demand across every single product. If I have people demanding Xeon 6 and Xeon 6+, and still Xeon 5, how do I balance all of those and match where the supply constraints are in the industry? In some cases, customers are struggling with mismatches. They can get the GPU but not the memory to pair with it, or the memory but not the CPU. There's a lot of matching going on in the industry.

Journalist 2: On the client side, people are demanding even older products because they've already verified them.

Kira Boyko: I've seen that on the data center side, too. They've verified and tested a product, so they want that product. In such a supply-constrained environment, people will buy whatever’s on the table. And 6+ has the benefit of some backward-compatibility elements, the socket compatibility, and again, using processes that are hardened on previous products, so we can mix and match in some cases. We have customers looking for multiple products on multiple processes, and it's working with them to understand exactly what they critically need, when, and how we best service that across all their orders.

Jake Roach: If I'm remembering correctly, it was the earnings call before the most recent one, where we talked about wafer allocation split between client and data center, with a greater emphasis on wafers going toward the data center. Is that still the plan?

Tim Wilson: That's definitely the plan, and we're always having those conversations. That's more of a foundry conversation than a product conversation. [...] The whole ecosystem is sucking up all the wafers and memory, whether it's client, automotive, or any of the other industries. AI data center tends to take the supply because they're willing to pay the most, and the rest of the industries can't pay the price until supply balances out. We saw a similar effect during COVID, though that was supply-chain-driven rather than demand-driven. Those trade-offs, Gen 5 versus Gen 6 versus Gen 7, are a weekly conversation.

Kira Boyko: Daily, in some cases, on CPU allocations. [...] Given the dynamic space, our customers are modifying on a regular basis. Can we shift? What do they really need, and when? If you're asking long-term whether we'll stay in these constraints, we do see a space where things will lighten up. It's not in the immediate timeframe.

Journalist 2: Dave talked about multi-year hyperscaler contracts. What's the latest on that? Are deals getting signed, and are you getting more requests for those kinds of contracts?

Tim Wilson: I doubt either of us is the right person, by the way. They don't trust us with a lot of that information.

Journalist 2: You're not talking with data center customers on the purchase side?

Kira Boyko: We're not in the contract negotiation.

Tim Wilson: There's a principle here. If you mix commercial negotiations in with the technical discussions, it doesn't work out well, so you generally try to separate them. You let the finance people argue over pricing and contracts, and let the engineers figure out the best products to build together. When you're talking with product-side engineers, we don't have a lot of that information, and even if we did, we probably couldn't tell you.

Journalist 2: What percentage of Intel's data center revenue is hyperscaler?

Tim Wilson: You can go look at our earnings.

[Session ends]

If you take a look at Tom's Hardware this week, you might recognize that we've been posting many reports directly from the ground at Computex 2026 in Taipei, Taiwan. This year, we're offering readers a chance to take a look at how we're coping amid the sweltering Taipei heat and telling you exactly what we've been up to each day.

While new announcements (and a lot of writing) are part of the overall Computex experience, we hope you enjoy this series of blog posts from our team on the ground. If you haven't caught up on our Day 0 post, be sure to check it out first. With the busier trade show days looming, Tom's Hardware's fearsome five marches on into the depths of the Nanggang Exhibition Center and beyond.

Paul Alcorn: Editor-in-Chief

The pace of the show is quickening as we get closer to the first day of the show floor opening, which occurs tomorrow. Today found me scrambling after the Nvidia keynote to make it to the Qualcomm keynote, and then the following press question and answer session. Qualcomm really didn’t bring many new announcements to the show, so there weren’t any terribly big news gems to be found. My marathon demo run through Nvidia’s suite, which took two hours, was a lot more interesting as the company demoed a seemingly unending string of gaming and AI demos, with most of those powered by the new Microsoft Surface powered by RTX Spark. In the end, I ended up back at the hotel at 10 pm for some rest before a 7:30 am question and answer session with CEO Jensen Huang tomorrow.

Matt Safford: Managing Editor

I spent the early morning writing, before grabbing Mos Burger for breakfast and heading to the Nangang Exhibition Center (Computex HQ) to pick up my badge and take more photos for daily wrapups and our Best Of story. After showing our Computex rookie Joe Shields around a bit, we headed to Gigabyte's Computex kickoff, where the company showed off many things, including, most notably, the X870E Aorus Infinity Next, a motherboard wrapped in 3D-printed metal.

We were told that just the production and materials of this board cost thousands of dollars, so it won't be making it into your next build (unless maybe you're a billionaire), but it is interesting to see Gigabyte push the boundaries of what is possible.

Joe Shields: Staff Writer, Components

I have to talk about the night market I went to last night first. There was so much to see and even more to eat! So many different foods and vendors selling wares, carnival-style games, and there were a lot of people. I ate a pork pepper bun, fried prawns (would recommend both), and what was supposed to be a brisket burger that I think ended up being chicken sausage. Getting there (and around in general) on the subway was a lot easier than I expected, as most signs/announcements had an English translation and were color-coded.

Today was a day of unrest before the storm, with two events in the late afternoon, including one with Gigabyte, who showed off a lot of cool goodies, including the X870E Infinity Next with its metal 3D printed heatsinks — the star of the show for me so far. At this point, I’m sleepy, as the dramatic 12-hour time change has finally caught up to me. Tomorrow, the fun really begins, starting with a visit to Cooler Master HQ and then to the convention center and booth hopping for the rest of the day.

Jake Roach: Senior Analyst, CPUs

Day one of Computex is down, and it was a busy one (a sign of things to come). I started my day chatting with Intel’s Nish Neelalojanan about a broad range of consumer topics, and we’ll be rolling out some choice quotes from that interview over the coming days (the first is already live). After some time at the Qualcomm keynote, I went back over to Intel to talk Xeon 6+ and the company’s new Arc G3 Extreme.

It’s hard to overstate just how convenient Taipei is when it comes to darting around the city like this. The MRT (train) is fast, cheap, and always on time, allowing me to get around to various places while (mostly) avoiding the Taiwan heat and endless Uber bills.

Today was Intel, tomorrow is AMD. We have a series of roundtable interviews set up, so hopefully we’ll get some more interesting insights into where the x86 gang stands, especially in the face of the RTX Spark announcement from Nvidia.

Jeffrey Kampman: Senior Analyst, Graphics

Today was all about Nvidia for me, from early morning until late at night. In the morning, I joined the throngs of GTC Taipei conference-goers to hear CEO Jensen Huang talk about the company’s continuing full-court press for the data center with Vera Rubin.

We also finally learned all the juicy details of the RTX Spark platform (aka N1) and the company’s considerable efforts to spark a Windows on Arm revolution across hardware, operating system, and software. Even if you’re skeptical about Nvidia’s agentic AI vision for the future of personal computing, it’s impressive that it’s gotten everybody who needs to be on board for a seamless Windows on Arm experience on board, and the platform already feels quite mature. We’ll be spending more time with Nvidia tomorrow between a Jensen Huang Q&A and more hands-on opportunities with RTX Spark.

Intel’s Arc G3 chips are gunning for the AMD-dominated, high-tier integrated graphics market that has become such an important enabler of the modern handheld PC gaming experience. But as high-memory prices push up the costs of even entry-level discrete GPUs, there could be much more of a place for powerful onboard graphics in the PC gaming landscape in the years to come.

We sat down with Intel’s Senior Director of Product Management, Nish Neelalojanan, in Taipei, Taiwan, at Computex 2026 to talk more about the G3’s development and how it fits into Intel’s lineup. Here, we're presenting the full transcript of our conversation.

This transcript has been lightly edited for clarity.

Jake Roach, Tom's Hardware: So what was the idea behind the G3, because you guys have tried before, right? I believe it was with MSI? And now you’re putting a bigger emphasis behind it with a whole new branding.

Nish Neelalojanan, Director of Product Management, Intel: It was a combination of two things. So first of all, we started trying already with Meteor Lake, and yes, we were experimenting. This was all standard off-the-shelf parts, and we learned a lot as we came into Lunar Lake. The power management for handheld needed to be more customized, so we started tweaking further, and as we got into Panther Lake, the architecture lent itself to lower power gaming. We moved the E-Cores onto the performance cluster, so you have E-Cores both on your efficiency island and your performance cluster, that means your E-Cores have access to L3 cache, so E-Cores are now performant enough to run games.

A lot of the time, in a low-power scenario, you are more GPU-bound than CPU-bound because the GPU is power starved, so if you can reduce the power on CPU and dump it on the GPU, you'll get much better performance. So, with that architecture change with Panther Lake, now is the perfect time. All the goodness we've learned, we can capitalize on it. We have a silicon architecture, we can lend itself to low power, and we have big enough graphics now…

Jake Roach: A really impressive iGPU.

Nish Neelalojanan: So, that is what had the impetus on, hey, what if we did a CPU line, which is graphics first, or leading with a very big graphics, but small enough CPU that doesn't grab enough power, but good enough to run all your handheld games. It's great for handheld gaming or non-PC form factor, running low-power gaming. So we wanted to start a line of products, which would be integrated graphics forward, with the right CPU.

Jake Roach: And these are wholly unique entries, right? If I remember correctly, there's no 14-core Panther Lake.

Nish Neelalojanan: These are completely unique chips. So they are based off the same die, but we've optimized it with, like I said, core count, so that taking two P-Cores off, because most of the games are going to run on the E-Cores on the performance cluster, you also cut down on different I/Os, so you don't need as many ports on a handheld as you would need on a laptop, right, so you cut down, so it's cutting down all the things you don't need.

Jake Roach: Really focusing it on that form factor.

Nish Neelalojanan: Yeah, that will be on the hardware, and then software-wise, we have a lot of other software optimization. So, now in order to have them pinned onto the E-Core, we have a BIOS control optimizer, so extra ways to have your thread director direct your game threads onto your E-Cores.

It's basically making sure we are directing the game threads onto the E-Core. [We also have the] ability to do power gating, so that we have features like endurance gaming, which we had on the laptops. Now, for handheld, we've added some features, so you can go with different presets. You can say, I want 60 frames per second, and then it will optimize your profile accordingly, or I want 30 frames per second. So you have a frame cap, and then your SOC resourcing is optimized, so that you will increase your battery life 2, 3, 4, hours.

Jake Roach: Battery life is so important for a handheld, right? I was playing a little Forza Horizon 6 on the plane coming over, and one way that I'm doing that right now on Linux is with Lossless Scaling, with frame generation in any game. As you're saying, apply that 30 fps cap frame generation to the mix, and you can get really good perceived performance.

Right now, you guys have multi-frame generation through XeSS 3 through specific games, but there's no driver. Is that something you're looking into, given how important that can be for the local gaming experience?

Nish Neelalojanan: So, 100 plus games have already enabled MFG, but you could imagine, as you said, it's important. So we're exploring, but as we get closer, we'll talk more about when and where it intercepts.

Jake Roach: The other thing I did want to ask about was form factors, which is something you kind of hinted at. Right now, with component prices being so high on just a typical DIY PC, we're seeing a really big push for budget laptops for people that maybe don't need as big of graphics and handhelds for people that really care about gaming as a laptop replacement. I'm just curious, kind of broadly, what you think about the dynamics between these form factors? Is this something that is just a temporary market connection, given that prices are so expensive, and are you planning around that, or is it something more long-term? Where do you think these are going to be the preferred form factors?

Nish Neelalojanan: I think, from a budget-conscious perspective of value buyers, our core 300 series, I think probably this is the first time in a long time the mainstream is getting some of the new ideas, right? So, today if you take a value-conscious segment in the past, it was always, hey, you have the big innovation, which we launched, it gets waterfall down. But as the innovation started getting expensive more and more, that waterfall did not happen, it was basically take the old chip, do some minor updates. So we wanted to take all these new like battery life performance uplifts, and you know, having the new AI updates, all of that, but to be able to be affordable, that's what is Wildcat Lake, or Core 300 series. So that's kind of for the budget-conscious buyer, we wanted to make sure we put some new IPs out there, because I don't think anyone is putting that out.

So that's part A. Part B of your question is handheld as a form factor. I think handheld as a form factor is interesting. Different people are trying to do multipurpose use, so would it ever go from companion to main? TBD. But can it expand its use cases from, hey, can I have a handheld, can I have a docked experience? I think long-term, yes. Currently, the software interfaces and a lot of the, let's say, ecosystem around it needs to evolve for it to be meaningful, but there's a lot of experimentation around dock experiences and stuff, which we are working with partners to experiment, but as it stands, I think handheld alone as it's gaming first.

A lot of our partners are experimenting; they're having all those capabilities available. How can you dock, how can you connect keyboard and mouse directly, and then be able to do it, because, like you said, costs are going up. If someone buys this, they want to be maximizing it.

Arrow Lake refresh's positioning

Jake Roach You touched on Wildcat Lake in the mobile segment, and recently we had Arrow Lake refresh, which was a really big readjustment in pricing. In particular, I'm just kind of curious to get more color on that, because when I reviewed those chips, I the expectations, I was briefed on them, and I was like, I know what to expect, but it was a very different Intel than I was used to working with on the desktop run.

Nish Neelalojanan: Short answer would be, we wanted to make sure we are putting out things which gamers would care about and show that we care about gamers, so this was an attempt or step one in getting to that expectation, right? And then obviously same thing with handhelds, making sure we are putting something which the gamers would want, so that's the highest level.

Jake Roach: I mean, again, seeing the results, we've essentially made the original Arrow Lake line outside of a few chips, irrelevant with these two chips. The 270K Plus scales above 285k and 250K can go toe to toe with either the Core Seven or Five.

Nish Neelalojanan: That’s a good thing, right?

Jake Roach: That is a good thing, but it's a good thing for us. It is not a good thing for Intel, right? Like, internally, that undermines your own product. And so I'm curious about the decision there, because at some point you had to have had pushback on, hey, this $300 Core 7 is going to undermine our $600 Core 9 flagship.

Nish Neelalojanan: It was just a decision made with end users in mind, and we want to make sure we are providing value as we come out, and if at all we need to start somewhere, right? And in terms of desktop, that was an effort to let's go with value focus first, and that will help us then gain confidence. From an enthusiast perspective, we needed to build back our reputation. I am sure you would agree with that, and this was, we’re making sure we are providing value to the gamers, and we start with Arrow Lake Refresh, and we have a very strong roadmap to come, so we want to continue.

Jake Roach: It did seem like an appetizer, almost, given you know everything that happened with Arrow Lake, and yeah, I appreciate you wearing that a little bit, because those were again, they were very interesting parts for a number of reasons.

Nish Neelalojanan: Savior [Kim, Intel Director of Client Communications] can correct me if I said something I shouldn't, but that was kind of highest level.

Leaving Hyper-threading behind

Jake Roach: Another question I had; This is more on the mobile side of things, or SoC side of things, is around hyper threading. So I have this question for the Xeon folks that I'm meeting with later today, because there have been comments in the financial reports, comments about returning hyper threading to the data center, whole lot of stuff around that on the consumer side of things. You guys left hyper threading behind with Arrow Lake. I'm wondering now that we have a desktop generation, a mobile generation under your belt. What do you see with that move to get rid of hyper-threading? And is there any consideration for maybe going back to some form of SMT in the future?

Nish Neelalojanan: Highest level, our decisions are always are we getting the right level of performance. The best way to achieve that performance is what we want to go with. Like you said before, with Arrow Lake Refresh, you're not only getting the right game performance at the right price point, but you're also getting almost 2x multi-threaded performance compared to competition, right? So, if you can deliver that without SMT, though the end user, it doesn't matter to the end user. In fact, you're actually getting even better multi-threaded performance because they're actual physical codes versus virtual threads, right? So that's where I would leave it at. We always reevaluate, but it's the best way to give that level of performance in that given price band or that given SKU. So we continue to keep re-evaluating, and different segments may need different things.

Jake Roach: Right now it sounds like it's working out well?

Nish Neelalojanan: Yeah, and like in terms of all the different agentic AI workloads, you need CPU as an orchestrator, having nth number of threads, cleaning up data, lining up a memory, a lot of threads help. So, like I said, when there is utility, and when there is a need, we will constantly evaluate it's, it's rigid to say, oh, it's behind us, or it's rigid to say, oh, we are going to run towards it: If it makes sense, it makes sense, yes. That’s where the data center decision is. They talk more about the growing workload, there is a need.

Jake Roach: It has been interesting. We're coming up at Tom's Hardware on 30 years, and we did a retrospective on CPUs, so I went back to the very first Pentium Two review on Tom's Hardware, and seeing the hyper-threading, and how it was used over decades, it was really fascinating to look at.

Nish Neelalojanan: A lot of the low-power segments, like now, handheld, yes? Those eight E-Cores on that performance cluster are significantly helping with all the low-power gaming, right? So, a lot of these decisions are paying off as it stands. As the workload evolves, as we evolve into different architectures, we will have to evaluate based on at that time what would be the right decision. Okay.

Jake Roach: For years now, Intel Foundry has laid out a really aggressive foundry roadmap. We saw 18A first and now we finally have 18A in data center with Xeon Six Plus. Is that the kind of the cadence we should expect going forward for Intel's cutting-edge hooks to see them debut first on the consumer front?

Nish Neelalojanan: It's the same answer I said before wherever it makes sense first. So we've got especially a lot of our consumer client CPUs, we pick the right process node, which made sense for the right tile, especially now we have multi-chip solution. It gives us the flexibility to pick and choose the right process node for cost, readiness, optimizing for R&D, because sometimes you won't have that IP on a different process, so it's easier to just reuse it, based on availability. Sometimes it's costing some bigger tiles, you can put it on latest and get it to get performance. Some of the tiles where you don't need to push frequency as much, you put it on an older node. And now with all the supply in and around the industry, picking the right process nodes, which is more available, is also going to be important. So we always go through all of these considerations and pick and choose, so there is no settling on client will start data center will follow, vice versa. It's we pick the right process choice based on that architecture, for that side.

Reacting to Nvidia's RTX Spark

Jake Roach: I want to get your reaction to [Nvidia’s RTX Spark]. If you need any better reminder that Twitter is not real life, there's a lot of talk on Twitter that Nvidia entering this market completely decimates and it rules everything. I don't think that's true, but I want to see your reaction to Nvidia getting into that space.

Nish Neelalojanan: I mean, Nvidia puts out great products, and they know how to do gaming. They know how to do all these different things. So we always take everything with a healthy dose of paranoia, but we are also very, very confident with our products, in the sense that X86… Let me put it this way, when we entered this discrete graphics business, our graphics business, it took a painful few years for us to work through all the drivers, all the compatibility issues, and everything ironed out, same thing goes on when an ARM CPU enters a market that's going to be tons of compatibility DRM issues, backward compatibility As a result, we are very confident that we have the right CPU, GPU mix for clients, both for gaming and when it comes to what you call AI inference workloads.

That said, Nvidia is a great partner. We will continue to work with them. You saw some of our announcements. We have some longer-term commitments with them, so both of us have different parts of the roadmap that we will expand together, where there'll be a roadmap where we will be partnering, and where there might be places where we will be competing, but I think it's great for the industry that there is different choices.

Jake Roach: I know, it's a weird situation, especially for Intel, because you guys, you guys do work with Nvidia. Yeah, when I pose similar questions to the other guys, they, they're a little bit more fiery in their responses.

Nish Neelalojanan: Compatibility is going to be a key thing there. x86 on the CPU side is going to have a lot of advantages. We talked about some of the new instruction sets, which got announced by the x86 Consortium, a lot of those lend itself as much to gaming as much as AI, and you'll see a lot of that being talked about more.

A lot of it were agentic AI examples and stuff, because you have to say AI three times before you can talk about anything else, but they also help with gaming significantly, so yeah, it doubles the amount of registers, which you would execute one instruction, so it's based off of AVX, but there’s a few others which came out with it.

The health of the consumer PC market

Jake Roach: Finally I want your reaction more broadly to the PC market right now, because we have all the rising component prices, we have very expensive laptops. On the desktop, it's really, really hard to build a PC right now. I think motherboard sales are down some 30-40% I know you're releasing products to address that market between Wildcat Lake and Arrow Lake pretty refresh, but I kind of want to see your reaction to how that pans out over the next maybe three to five years. Is it a continual area of focus, or is it something that hopefully we're just dealing with over the next few years, where we're really focusing on the budget segment?

Nish Neelalojanan: Large memory is completely overshadowing any CPU prices, right? Memory and storage. The CPU is not anymore determining your system price point, and when you're paying that amount, people will obviously start upgrading. Now, that said, there are still Panther Lake systems you can get below $1,500 out there, right? It's going to be dependent on OEM. It's going to be dependent on markets, and even the Wildcat Lake, they'll announce a $599 starting price point. Yeah, so there are definitely designs which are coming at comparatively reasonable price points, which are available, and longer term, I think something has to give right. The over inflation, we will have to keep an eye, but if I could predict the memory market, I would be rich in stock!

Jake Roach: Let me phrase the question a little bit better, because are you making plans for a longer term, a longer term squeeze on the consumer front, because surely you're going to have to make those plans if you see the headwinds going that way.

Nish Neelalojanan: We do have products with support for DDR4 both on desktop and mobile, so Raptor Lake, you're not end of life in any of them, they're there. We'll continue to make sure that there are products which can take care of older memory technologies if they're available and cheap. Second thing is, we are making sure we are validating lower configs as well. Wildcat Lake starts at 8GB, Wildcat Lake is a single channel product, so there are products which can leverage with low memory and give reasonably good performance, so we are doing everything we can from our perspective to be able to help in any small way. But like I said, when CPU becomes the least relevant from an overall BOM (Bill of Materials) perspective, because it's so expensive. Then we also have CPUs you can buy out into that.

Jake Roach: Speaking of memory, I don't know if you had any involvement with half ranked? Is that what they call them, half ranked DIMMs from ASRock? It was with ASRock and Intel.

Nish Neelalojanan: I am not familiar with that, but we are working with a lot of indigenous memory suppliers to validate them, so we’re doing everything we can in terms of it's not just one, two, or three. If there are some local specific memory vendors, but like in PRC, and now Indonesia is even bringing up a couple of them. We're trying to validate as much as we can, so there's enough choice that people can get pockets of relief. Right? We are looking at UFS for a longer-term horizon, so that every little thing helps, right?

Jake Roach: Absolutely. I appreciate you taking the time and talking over everything. I'm very excited to see the G3 chips in action. I saw them yesterday at the Acer showcase, and I played a little bit of Forza Horizon 6, and these are pretty good.

Nish Neelalojanan: With G3 at least we're putting out some latest and greatest stuff, and in terms of a lot of these, it's not necessarily exclusive. We're broadly available, the 12 Xe on the PC side, and on the handheld, it's not like limited to one OEM. Unlike some people who hold it back, just only give it to one OEM.

Jake Roach: So all these handhelds, I believe all the ones that announced are all Windows-based handhelds. Is there consideration for Linux? How much consideration or weight do you put on that, given things like Steam OS proper?

Nish Neelalojanan: So highest level stuff we announced now is Windows based, but you can take those devices and install… and I'm sure you would imagine we would continuously want to make sure that those experiences are reasonable for end users, and we are, we would talk more about as we get closer to something, but we are exploring beyond Windows, and as we get closer, we'll talk more about.

[Session ends]

Tom's Hardware has covered hundreds of press events, and for a long time, you've always seen the finished product. You've always seen the dizzying number of articles coming from events. But what is it really like to cover Computex 2026?

Our staff on the ground are peeling back the curtain to offer you unprecedented insight into how the proverbial sausage is made. Tom's Hardware Unfiltered: From travel to urgently dashing around Taipei, and of course, quick thoughts about the things that we're seeing directly from the show. After each day, we're compiling our thoughts on what we've seen, including any trials and tribulations we've faced amid our incredibly busy schedules.

The show hasn't even kicked off, and there's still a slew of news to get through, so be sure to check out the fruits of our labor. With all that said and done, it's time to kick things off with Day 0 of our War Room dispatch.

Paul Alcorn: Editor-in-Chief

I arrived in Taipei in the blistering heat after three flights and 22 hours in transit, a grueling trip as usual, but luckily, I arrived in the evening and had no appointments. After a half-decent night’s sleep, I headed to the Acer demos to check out their new Intel G3 Extreme-powered handheld and dig up some new info on Qualcomm’s Snapdragon C platform. Acer had the laptop dutifully locked behind glass to keep curious press away from toying with the system, but I happened upon a demo unit that a Qualcomm rep was showing around. A few seconds later, and I had the Windows Task Manager open to peep the unreleased info on the eight-core CPU and its GPU. I’ll be writing up those details tonight as I wait for Nvidia’s pre-brief, which is inconveniently scheduled for 12:30 am Taipei time. That’s going to make for a long day tomorrow.

Joe Shields: Staff Writer, Components

I arrived in Taiwan around 05:40 AM on Sunday after a 17-hour flight from Ohio (five to Seattle, 12-plus to Taipei. Flying that long and being stuck inside a cigar tube, a large one at least, was better than expected, but it’s still an incredibly long flight. Traveling from the airport to the hotel by train (MRT) was easy (most signs have English writing!) and offered great views of Taipei along the way. Even though Computex hasn’t officially started, I have a meeting with Asus this afternoon, with most meetings and roundtables running Tuesday through Thursday. I’m looking forward to sleeping and heading to one of the many night markets (Shilin, one of the largest) to check out the local wares and try new foods before things get hectic later in the week.

Jake Roach: Senior Analyst, CPUs

The first day of Computex is all about getting ready for the rest of the week. My travel day was some 20 hours, leaving in the evening on Friday and arriving after 4 AM on Sunday in Taiwan (the time travel is a trip). After getting off the flight and taking a quick shower (important), I grabbed my MRT pass for the week and my badge. It’s about a 13-hour time difference for me in Taiwan, so I spent most of the day trying to get on a decent schedule so I can be ready to go when the event kicks off properly tomorrow. I was able to get my hands on the Acer Predator Atlas 8, one of the handhelds with Intel’s new G3 Extreme chip, and it’s pretty impressive. 60 fps at 1080p with High settings and no upscaling in Forza Horizon 6 is no joke.

Matt Safford: Managing Editor

After more than 20 hours of travel, my first day in Taipei started with debit card complications and was punctuated by some brief hands-on time with Acer’s Intel G3 Extreme-powered Predator Atlas 8 and Aspire Go 15. Both are interesting, but just how interesting depends on two key things we don’t know yet: performance and price. After Acer, I visited the Guanghua Digital Plaza neighborhood to grab some general photos for Computex blogs and daily announcement wrapups. Between searching for an ATM that worked with my card and walking between Taipei Metro stops, I walked nearly 13 miles, drank more iced coffees than I can count, and I am very happy to let exhaustion take me into the arms of tomorrow.

Jeffrey Kampman: Senior Analyst, Graphics

My travel to Taiwan was one of the smoothest and most comfortable international flights I’ve ever had (thanks to the quiet engines and relatively humid cabin of the Boeing 787), so I was able to get plenty of rest before arriving at 5 AM local time. I immediately set up shop in a Starbucks near my hotel to hammer away at an embargoed review for a few hours before migrating back to my hotel room as soon as it was ready so I could shower, nap, and continue that work. I was glad for the jet-lag-incurred naps, as our Nvidia pre-brief ran from 12:30 AM to 1:30 AM Monday morning prior to Jensen Huang’s keynote at 11. No rest for the weary…

In a world where nobody is launching truly new graphics cards, my Computex week will almost certainly be defined by data center products, integrated graphics processors, and AI accelerators of various shapes and sizes. Intel has already taken the wraps off its Arc G3 handheld platform, and rumors around Nvidia’s N1X and N1 platforms are as thick as the humidity here. If those launches come to pass, we’ll be looking at a very different consumer PC and mobile graphics landscape after this week.

I haven’t been back to Taiwan for over five years at this point, so I’m excited to see what’s the same and what’s changed since my last Computex.

While the show has yet to officially start, our team on the ground will be keeping you up-to-date with everything they're up to this week. Needless to say, things are very busy, so stay locked in on Tom's Hardware Unfiltered tomorrow for our next update.

The global foundry market is dominated by TSMC, which captured 69.9% of global foundry revenue in 2025, but beyond the glitz and glamor of the leading edge sit a tier of foundries that collectively manufacture the chips found in cars, power supplies for AI servers, RF front-end modules, display drivers, industrial controllers, and defense systems. GlobalFoundries, UMC, and SMIC posted a combined 2025 revenue of roughly $24 billion and hold approximately 13.5% of the global foundry market between them.

Each is pursuing a fundamentally different strategy shaped by geography, regulation, and technology choices. GlobalFoundries is becoming a U.S. and European specialty foundry, backed by $1.575 billion in CHIPS Act funding and a $3.1 billion Department of Defense contract.

Meanwhile, UMC is bridging from pure mature-node services into 12nm FinFET territory through a manufacturing partnership with Intel, and SMIC is China's de facto national champion, expanding mature-node capacity at enormous scale while pushing the limits of what DUV lithography can achieve under tightening export controls. We break down each of these trailing-edge foundries to see what might be coming up next.

GlobalFoundries

GlobalFoundries (‘GF’) exited leading-edge development in 2018 when it canceled its 7nm program and has since repositioned as a specialty foundry focused on differentiated process platforms. That strategy produced FY2025 revenue of $6.79 billion (up 1% year-over-year), with Q4 gross margin of 27.8% and full-year operating cash flow of $1.73 billion. The company's automotive segment hit a record $1.4 billion, up 17% year-over-year, according to its SEC filing.

Its current node portfolio runs from 12LP FinFET down to 180nm and spans several specialty platforms. The company's flagship is 22FDX, a 22nm fully depleted silicon-on-insulator (FD-SOI) process targeting ultra-low-power IoT, automotive radar, millimeter-wave 5G, and microcontrollers with embedded MRAM support. Meanwhile, 45RFSOI is the dominant global platform for 5G RF front-end modules. Below those sit 28nm, 40nm, and 55nm logic nodes, alongside BCD for power management, SiGe BiCMOS for high-frequency analog, and a ramping GaN-on-silicon platform at its Vermont facility.

Two recent acquisitions, however, have expanded GF beyond pure-play manufacturing. It bought Singapore-based Advanced Micro Foundry last year, making it one of the world's largest silicon photonics foundries, and acquired MIPS (for RISC-V CPU and AI inference IP) along with Synopsys' ARC and RISC-V processor IP portfolio. The company now offers customers pre-built compute IP alongside fabrication, a model no other trailing-edge foundry currently can.

GF operates five manufacturing sites. Fab 8 in Malta, New York, is its most advanced 300mm facility and holds Trusted Foundry Category 1A accreditation from the U.S. Department of Defense. A new fab at the Malta site, funded partly by a $1.587 billion CHIPS Act award, will triple the site's capacity over the next decade as part of a $16 billion, 10-year U.S. investment plan.

Fab 1 in Dresden is Europe's largest semiconductor fab, with a €1.1 billion expansion underway to push output toward 1.5 million wafers per year by the end of 2028. Fab 7 in Singapore opened in September 2023 after a $4 billion build-out, adding 450,000 wafers per year. The two remaining sites are both 200mm facilities in the U.S.: Fab 9 in Burlington, Vermont, which is targeted for the company's first high-volume GaN production line.

The company's 2026 capital expenditure guidance of 15% to 20% of revenue represents a sharp jump from 8% in 2025, driven by what management described as oversubscribed demand in silicon photonics, 22FDX, and SiGe. That investment will compress free cash flow margins in the near term, but GF has said customer prepayments and long-term agreements underpin spending.

Reports surfaced in 2025 of an internal assessment dubbed "Project Ultron" exploring a potential takeover of UMC that would create a mature-node foundry with roughly 28% combined market share. UMC denied active merger talks, and, in any case, the regulatory barriers across Taiwan, China, and the U.S. are more than likely insurmountable.

UMC

UMC reported Q1 2026 revenue of NT$61.04 billion (approximately $1.93 billion), with net income surging 107.9% year-over-year to NT$16.17 billion. Gross margin was 29.2% and capacity utilization stood at 79%, with Q2 guided to the low-80% range and wafer shipments expected to rise by high single-digit percentages.

The 22nm node is UMC's primary growth driver. Revenue from 22nm grew 93% year-over-year in 2025 and now accounts for 14% of total revenue, up from single digits the prior year. Combined, 22nm and 28nm represent 34% to 36% of quarterly wafer revenue.

UMC dominates small-panel display driver IC (DDIC) production at 28nm, holding over 90% market share in that segment, and launched an advanced 22nm embedded high-voltage (eHV) platform in 2024, targeting next-generation smartphone OLED displays. Specialty processes extend across embedded non-volatile memory (eFlash from 350nm to 28nm), RFSOI, RF CMOS, and BCD for analog and power applications down to 55nm.

UMC operates 12 fabs with combined capacity exceeding 400,000 12-inch-equivalent wafers per month. The newest, Fab 12i Phase 3 in Singapore, opened in April last year after a $5 billion investment and will start 22/28nm volume production this year, with an initial capacity of 30,000 wafer starts per month and with space reserved for a second phase.

The most significant item on UMC's roadmap is its 12nm FinFET node, co-developed with Intel and targeted for mass production in 2027 at Intel's fabs in Chandler, Arizona. The process offers 10% higher performance, 20% lower power, and roughly 10% area reduction compared with UMC's existing 14FFC, with three fewer mask layers.

UMC's CFO Chi-Tung Liu confirmed last May that the majority of UMC's R&D spending is now directed at this node. The partnership gives UMC its first U.S. manufacturing footprint and a FinFET node at scale, while Intel gains mature-node foundry volume through what are largely depreciated fabs.

SMIC

SMIC posted record full-year 2025 revenue of $9.33 billion, up 16.2% year-over-year, according to the company's annual results. Full-year utilization averaged 93.5%, a jump of eight percentage points from 2024, and wafer shipments rose 20.9% to roughly 9.7 million 8-inch-equivalent wafers.

Annual capex, meanwhile, ran at over $7 billion, reflecting an aggressive capacity build-out that is compressing margins: full-year gross margin was 21%, and the company guided Q4 2025 gross margin to 18% to 20% as depreciation from new fabs weighed on profitability even at near-full loading.

SMIC's production stack officially spans 350nm to 7nm, but the vast majority of output sits at 28nm and above. 28nm HKMG and PolySiON variants serve smartphones, networking, and DDICs. Nodes from 40nm through 180nm cover analog, power management, RF, image sensors, and microcontrollers.

At the advanced end, SMIC's N+2 process (7nm-class) is in production for Huawei's Kirin 9000S, 9020, and Ascend 910C, with an estimated 20,000 WSPM of capacity. N+3, confirmed on the Huawei Kirin 9030 in December, extends 7nm-class scaling using DUV multi-patterning, though TechInsights characterized it as firmly 7nm/6nm-equivalent in absolute terms rather than a true 5nm node.

Four major new 12-inch fabs are under construction or recently completed, in Shanghai (Lin-Gang), Shenzhen, Beijing, and Tianjin, including an $8.87 billion facility, collectively targeting approximately 340,000 wafer starts per month of new 28nm-and-above capacity.

Export controls from the U.S., the Netherlands, Japan, and Taiwan constrain SMIC's ability to scale its advanced nodes. The company has been on the U.S. Entity List since December 2020, blocking access to ASML EUV scanners and progressively tightening DUV and etch equipment supply.

Taiwan added SMIC and Huawei to its own export-control blacklist in June 2025, requiring permits for high-tech equipment shipments. Although it was reported back in August that SMIC planned to double its 7nm capacity in 2026, the company remains constrained by tooling access: analysts estimate SMIC's advanced-node capacity will remain in the low tens of thousands of wafer starts per month rather than the hundreds of thousands that an unconstrained buildout would target.

SMIC's pricing reflects the competitive pressures in the mature-node segment, with the company having reportedly cut 28nm wafer prices by roughly 40% in early 2025, dropping from approximately $2,500 to $1,500 per wafer, before reversing course with a roughly 10% increase later in the year as utilization exceeded 95%.

Pricing and demand

After two years of price declines driven by Chinese capacity additions, the mature-node segment is reaching a floor. TrendForce reported in March that UMC, VIS, Powerchip, and Nexchip were preparing price increases of up to 10% from April through June this year, with the latter confirming a 10% hike effective from June.

One big factor is tightening supply alongside the cyclical recovery: TSMC has been reallocating 40-90nm production capacity toward CoWoS advanced packaging and silicon interposer fabrication for AI accelerators, reducing the available mature-node wafer supply from the world's largest foundry.

Demand from automotive (GF's automotive revenue alone is on track for $1.5 billion in 2026), power management ICs for AI servers (typically manufactured on 28-55nm BCD processes), DDICs, and embedded flash microcontrollers continues to grow.

Whether these three foundries remain independent is an open question. The Project Ultron reports suggest that at least one party has considered consolidation, and the logic for doing so, at least in terms of economics, grows as margins compress and capex requirements grow.

While SMIC's expansion is state-backed and largely insulated from commercial return calculations, GF is tied to U.S. industrial policy and defense spending, and UMC's future hinges on whether 12nm FinFET with Intel can deliver the revenues that pure mature-node services cannot.

For decades, semiconductor design has been driven by humans coming up with bright ideas that unlock new innovations. But the benefits of better chip design have been reaped, including the rise of AI, which now means there could be another party involved in making chip designs smarter: AI itself.

‘Chip designer’ isn’t one of the roles on the chopping block as AI automation upends the job market. But in the narrow pockets of the design flow where problems are structured, and evaluators are robust, it is starting to be adopted — with benefits.

Google DeepMind's AlphaChip reinforcement-learning system has produced designs for three generations of the company's Tensor Processing Units (TPUs), with DeepMind claiming "superhuman" layouts compared with those produced by human designers. They’re not alone: Synopsys has passed 100 production tape-outs with its DSO.ai design-space-optimization tool, reporting productivity boosts of more than three times and power reductions of up to 25% for customers including STMicroelectronics and SK hynix.

"Like every new technology, AI may have multiple uses," said Borivoje Nikolić, professor of electrical engineering and computer sciences at the University of California, Berkeley, in an interview with Tom’s Hardware Premium. Nikolić drew a parallel with Moore's Law, which has historically been exploited in two ways: to reduce the cost of an existing product by porting it to cheaper processes, or to add features that were previously impossible. "I think AI will be used in both ways," he says. "At the moment, the industry seems to be focused on the first item — how to make things cheaper, how to automate things in a better way than they were in the past."

By contrast, academics are more interested in using AI to discover things humans haven't yet thought of, an approach that mirrors breakthroughs in areas such as drug discovery and protein folding with the likes of AlphaFold.

Nikolić and his colleague Sagar Karandikar have been exploring that territory in their own research on cache replacement policies, a subject deep in the weeds of processor microarchitecture. Their ArchAgent system, built on Google DeepMind's AlphaEvolve framework, generated a cache replacement policy in two days that beat the prior state-of-the-art by 5.3% in IPC speedup on Google's multi-core workload traces. On the heavily worked-over single-core SPEC06 benchmarks, it took 18 days to eke out another 0.9%. That’s a "first sign of life" for Karandikar that large language models can design genuinely new logic, rather than just tinkering with existing parameters.

"There is still a lot of human guidance, and it kind of up-levels the kind of thinking humans have to do," said Karandikar, a computer architecture researcher at Berkeley, in an interview with Tom’s Hardware Premium. "The humans involved in that project are doing more of the high-level thinking — coming up with new ideas and guiding the LLM — and the LLM does a lot of the finer policy development around that."

Where AI is making breakthroughs

For Igor Markov, a chip design researcher who has spent years at the frontline of electronic design automation, the places where AI is adding real value are specific and often mundane. Some of the biggest wins, he says, come at the low end of the flow, such as tasks that previously required engineers to interpret informal specifications written in natural language and convert them into formal descriptions that a tool can act on.

Take power and ground networks, the intricate webs of metal that feed electricity across a chip. "They’re sometimes designed just with descriptions in natural language," Markov said in an interview with Tom’s Hardware Premium. "People explain the geometry, and then it's implemented, and at some point, you need to formalize it. This is a step that was done manually, and it's pretty straightforward to automate using AI." The productivity dividend isn’t massive; “it took a couple of days, now it's a couple of hours,” he explained. But is still better than nothing, even if the output still needs to be checked.

Where Markov is most bullish is on what he calls the agentic space: the high-level orchestration of chip design flows, including deciding whether a run is doomed or whether a flow needs to be restarted entirely. “If you take a zero multiplied by something, you get a zero,” he said. “But if you already have something decent, then this high-level control can be very, very enabling.”

The most stubborn corners of the industry are starting to think about adopting AI. Analog design has long been seen as the last redoubt of human craft, but researchers have begun producing generative AI systems such as AnalogGenie, which uses a GPT-style model to discover new circuit topologies, and Princeton's AI-enabled design-space discovery for millimeter-wave and sub-terahertz power amplifiers operating between 30 and 120 GHz.

It’s in these areas that what’s often seen as AI’s failing, that it doesn’t have an inherent knowledge or muscle memory of its own, becomes a strength. Humans have a tendency when porting a design from one process node to another to assume the old topology must be close to optimal for the new one. “AI may not have those kinds of barriers,” said Nikolić.

Testing versus real life

However, some caution is needed. AI can be trained to ace demos, but can flunk the messier problems engineers face in practice. "Whether something that works in five cases works in general, and allows you to innovate, that's the key," says Markov.

There is also the problem of what it is you are asking AI to do in the first place. Ask a model to design the best chip for AI, and without a formal, unambiguous specification of what best means, the model will produce something — or anything. "You will play whack-a-mole," Markov said when it comes to making it work in practice.

He added that every previous jump in design automation has provoked similar debates about whether machines can really think. Shortest-path algorithms for wire routing, once seen as a distinctly human capability, became undergraduate coursework. Placement algorithms now routinely outperform human designers. Logic synthesis, once considered too abstract to automate, is handled by for loops and conditionals. “EDA has always been a type of AI, because it automated what people did,” Markov said. “We are just moving along the straight line, and there's no stopping.”

For now, AI is acting as a force multiplier, Markov said, squeezing more output from teams rather than shrinking them. Who’s in those teams and what they bring is also shifting: engineers who are fluent with AI coding assistants are now in demand where they weren't six months ago.

Jevons’ paradox also looms large over the potential of AI in the chip design process. As AI makes certain parts of the process dramatically cheaper and faster, Nikolić expects engineers to use that freed-up capacity to explore territory they wouldn't otherwise have dared tackle, including the design of the AI chips driving the whole cycle in the first place.

After all, if any class of silicon is ripe for the kind of optimization that hasn't yet been systematically studied, Markov argues, it is the highly structured, performance-critical accelerators powering the current boom. “There’s plenty of opportunity for humans to be improving other parts of the design flow to make it more amenable to these AI-based systems,” said Karandikar. As models become more advanced, so too might their capacities to assist in chip design and development.

Nvidia still holds approximately 70% of the AI chip market share, but that share is projected to erode as Google, Amazon, Meta, Microsoft, and OpenAI invest billions in purpose-built chips designed for their specific workloads. ASIC-based AI server shipments are projected to reach 27.8% of the market in 2026, the highest share since 2023, which also forecasts that custom ASIC shipments will grow 44.6% year-over-year in 2026, nearly triple the 16.1% growth rate projected for merchant GPUs.

This is being enabled almost entirely by TSMC, which fabricates chips for all five hyperscalers and for Broadcom, the dominant custom AI chip architect. Broadcom alone carries a $73 billion AI backlog and is targeting $100 billion in annual AI chip revenue by 2027.

Marvell, which has partnered with Amazon on Trainium and Microsoft on Maia, projects up to $11 billion in AI ASIC revenue for 2026. Together, Broadcom and Marvell control roughly 95% of the custom AI ASIC co-design market.

So, with the market projected to expand significantly across 2026 and beyond, we take a look at what companies are currently up to and where they might be headed in the future.

Broadcom

Broadcom, which has arguably emerged as the core enabler of the AI ASIC ecosystem, reported $8.4 billion in AI semiconductor revenue for Q1 FY2026 (ending February 2026), a 106% year-over-year increase, and guided to $10.7 billion in Q2. CEO Hock Tan told investors the company has "line of sight to achieve AI revenue from chips in excess of $100 billion in 2027," backed by a disclosed $73 billion AI backlog.

Broadcom has confirmed six major XPU customers, including Google, which remains the longest-standing partner, with seven generations of co-designed TPU's since 2014. OpenAI signed a multi-year collaboration in October 2025 for 10 gigawatts of custom accelerators, with first deployment targeting the second half of 2026 using both 3nm and 2nm designs. That deal came after OpenAI was widely reported to be behind a separate $10 billion order. However, Broadcom semiconductor president Charlie Kawwas joked on CNBC that OpenAI "has not given me that PO yet," leaving the identity of the mystery customer officially unconfirmed.

Meta, ByteDance, and Fujitsu round out the confirmed customer list, and analysts have identified Apple and Arm/SoftBank as potential future engagements. Arm is separately developing a custom CPU for OpenAI's Broadcom-built accelerator, a contract that could be worth billions to SoftBank.

The tech behind this growth is Broadcom's 3.5D XDSiP platform, which uses face-to-face 3D stacking via TSMC's SoIC process combined with 2.5D CoWoS integration. The platform enables packages exceeding 6,000 mm squared of silicon with up to 12 HBM stacks, far beyond the roughly 2,500 mm squared limit of conventional 2.5D designs. In February, Broadcom announced it had begun shipping the industry's first 2nm compute SoC built on this platform, integrating four N2 compute dies, one I/O die, and six HBM modules.

In terms of networking, Broadcom’s Tomahawk 6 switch chip entered volume production in March as the industry's first 102.4 Tbps Ethernet part. The companion Jericho 4 fabric chip (51.2 Tbps) began shipping last August and is designed to interconnect over one million XPUs across data centers. Nvidia's competing Spectrum-X1600, meanwhile, isn’t expected in volume until the second half of 2026.

Google TPU

Google's TPU program is the most mature custom AI silicon effort among the hyperscalers, and its latest generation represents a significant architectural leap. The TPU v7, codenamed Ironwood, was announced at Cloud Next in April 2025 and entered preview in November. Each chip delivers 4,614 FP8 TFLOPS with 192 GB of HBM3E memory at 7.37 TB/s bandwidth. It’s manufactured on TSMC's N3P process in a dual-chiplet design co-developed with Broadcom and MediaTek, and features two TensorCores with doubled 256x256 MXU arrays plus four SparseCores.

The 9,216-chip superpod configuration delivers 42.5 FP8 exaflops with 1.77 PB of aggregate HBM. Per-chip, Ironwood's 4,614 TFLOPS sits close to Blackwell's approximately 5,000 FP8 TFLOPS, but SemiAnalysis estimates that TPUs achieve higher sustained model FLOP utilization of roughly 90% for transformers versus 70% to 80% for GPUs, narrowing or erasing the real-world performance gap. Google claims that the total cost of ownership (TCO) per Ironwood chip is roughly 44% lower than a GB200 server from its own procurement perspective.

Google is now selling TPU access aggressively beyond its own services. Anthropic committed to up to one million TPUs in the largest deal in Google Cloud history back in October, while Meta entered talks for multi-billion-dollar TPU deployments in February this year. The current-generation TPU v6e Trillium remains widely available on Google Cloud at $2.70 per chip-hour on demand, delivering roughly four-times better price-performance than H100 instances for LLM workloads, according to Google's own benchmarks. Google's Axion ARM CPU, based on Neoverse V2 and reportedly manufactured on TSMC 3nm according to TrendForce, complements TPUs for general-purpose cloud workloads.

Amazon Trainium

AWS has matched Google's pace with an aggressive custom silicon roadmap developed by Annapurna Labs, the Israeli chip design house acquired by Amazon in 2015. Trainium3, which went generally available at re:Invent in December, is AWS's first 3nm chip. Each Trainium3 delivers 2.517 PFLOPS FP8 with 144GB HBM3E at 4.9 TB/s bandwidth, roughly double the compute and 1.5 times the memory of its predecessor. The new Trn3 UltraServer packs 144 chips delivering 362 FP8 petaflops with 20.7 TB of memory, a 4.4 times improvement over Trn2 UltraServers.

AWS CEO Matt Garman said at re:Invent 2025 that the company had "already deployed more than 1 million Trainium processors" and was selling them as fast as production allowed. CEO Andy Jassy called it "already a multibillion-dollar business." The Project Rainier facility in Indiana, an $11 billion, 2.2 GW campus, had roughly 500,000 Trainium2 chips running for Anthropic by October 2025, and AWS also confirmed an OpenAI deal to supply 2 GW of Trainium computing capacity.

Trainium4 was announced in December 2025 for late 2026 or early 2027 availability, promising three times FP8 performance, six times FP4 throughput, and four times memory bandwidth over Trainium3, with an estimated 288 GB of memory. One notable feature is support for Nvidia NVLink Fusion, enabling hybrid clusters that mix Trainium and Nvidia GPUs. AWS's Graviton5 ARM CPU (192 cores, TSMC 3nm, Neoverse V3) was also announced at re:Invent 2025.

Meta MTIA

Meta disclosed one of the most ambitious custom chip roadmaps in the industry in March, unveiling four new MTIA generations (300 through 500) for deployment through 2027, in addition to the already-shipping MTIA 100 and 200. The company has deployed hundreds of thousands of MTIA chips for inference across Facebook and Instagram.

The MTIA 400 delivers 6 PFLOPS FP8 and 18 PFLOPS MX4 with 288GB HBM at 9.2 Tbps bandwidth in a 1,200W envelope. The MTIA 500, scheduled for 2027 mass deployment, scales to 10 PFLOPS FP8 and 30 PFLOPS MX4 with up to 512GB HBM at 27.6 Tbps in a 2x2 chiplet configuration, consuming 1,700W. From the MTIA 300 to the 500, HBM bandwidth increases 4.5 times and compute scales 25 times, with a new chip roughly every six months.

Meta has been explicit that MTIA is not a replacement for Nvidia GPUs. The company expanded its Nvidia partnership in February for "millions of AI chips," including Grace Blackwell and future Vera Rubin platforms, in a deal reportedly worth tens of billions. Custom silicon handles optimized inference at a massive scale, while Nvidia handles frontier model training.

With $115-135 billion in 2026 capex guidance, Meta is buying everything it can from both sources. The MTIA chips are fabricated on TSMC's advanced nodes: MTIA 100 on 7nm, MTIA 200 on 5nm, and the 300-series onward reportedly moving to 3nm with CoWoS packaging.

Microsoft, Tesla, and other efforts

Microsoft's custom silicon program took a significant step forward in January with the deployment of Maia 200, manufactured on TSMC 3nm with over 140 billion transistors. The chip delivers more than 10 PFLOPS FP4 and 5 PFLOPS FP8 with 216GB HBM3E at 7 TB/s bandwidth in a 750W envelope. Microsoft claims it offers 30% better performance per dollar than the best hardware in its existing fleet and calls it "the most performant first-party silicon from any hyperscaler." Maia 200 currently serves GPT-5.2 models for OpenAI and powers Microsoft 365 Copilot workloads from its Des Moines data center.

The path to Maia 200 was far from smooth, though. The original Maia 100, built on TSMC 5nm, was reportedly designed more for image processing than generative AI and never powered production AI services at scale. Maia 200 was delayed roughly six months due to design changes requested by OpenAI that caused simulation instability, plus chip team turnover. CEO Satya Nadella has emphasized that Microsoft will continue purchasing Nvidia and AMD chips alongside Maia. Microsoft's Cobalt 200 Arm CPU (TSMC 3nm, 132 Neoverse V3 cores) was announced at Ignite 2025 and is now live in Azure data centers.

Tesla’s Dojo project, meanwhile, met a very different fate. Despite years of development and an innovative D1 chip (TSMC 7nm, 50 billion transistors, 362 TFLOPS BF16, with a unique 354-core mesh architecture), Tesla disbanded the Dojo team in August. Lead architect Peter Bannon departed, and roughly 20 engineers left to found DensityAI. Elon Musk explained that "once it became clear that all paths converged to AI6, I had to shut down Dojo." Tesla is now focusing on AI5 and AI6 inference chips, with AI6 backed by a $16.5 billion Samsung fabrication deal, while relying on Nvidia hardware for current training needs.

Among other contenders, Intel's Gaudi 3 has struggled with software maturity and missed targets. Shipment goals were cut by more than 30% in 2024, and the Habana Labs brand is being absorbed into Intel's broader accelerator efforts under CEO Lip-Bu Tan. In China, Huawei's Ascend 910C (SMIC 7nm, roughly 800 TFLOPS FP16, 128GB HBM) targets 600,000 units in 2026 but faces yield challenges at around 20%. Cambricon, meanwhile, plans to triple output to 500,000 chips.

TSMC enables it all

TSMC is the indispensable enabler across all these custom AI ASIC efforts. The foundry generated $122.4 billion in 2025 revenue, up 36% year-over-year, and forecasts a 60% compound annual growth rate for AI chip revenue through 2029.

Its CoWoS advanced packaging capacity is scaling from roughly 65,000-75,000 wafers per month in 2025 to a target of 120,000-130,000 wafers per month in 2026, and capital expenditure of up to $56 billion is planned for the year. The 2nm node entered mass production at the back-end of last year, with capacity fully booked and targeting over 60,000 WPM by the end of the year. Nvidia has secured roughly 60% of CoWoS allocation (c. 595,000 wafers), Broadcom about 15% (c. 150,000 wafers), and AMD approximately 11% (c. 105,000 wafers). Every custom ASIC in this article depends on CoWoS or its successor CoWoS-L for HBM integration, and TSMC's packaging capacity is now a more binding constraint than wafer fabrication itself.

The driving factor behind custom ASIC adoption is, of course, the rapid growth of inference workloads, which Deloitte projected to account for two-thirds of all AI compute this year.

With custom silicon’s up to 65% TCO advantage over conventional GPUs for inference at production scale, it’s easy to see why so many hyperscalers are pursuing custom ASICs. Broadcom and Marvell together control roughly 95% of the ASIC co-design market, so the question is no longer whether custom silicon will take share from Nvidia, but how quickly it erodes Nvidia's pricing power as these programs reach full production scale.