Kioxia and Sandisk last week said they had started sampling of their latest 3D NAND memory with 332 active layers that features a combination of the industry's leading areal density and performance. The new 10th Generation BiCS 3D TLC NAND is set to address density and performance-sensitive data center applications, as well as promises to surpass Samsung’s latest V10-class 3D NAND in terms of storage density.

Unlike the previous generations, 10th Generation BiCS (BiCS10) is explicitly aimed at data center-grade storage, where bit density and performance are more important than cost. Indeed, the new type of memory features a 332-layer active layer architecture, greater than 29 Gb/mm² density, and a 4,800 MT/s data transfer rate to enable extreme performance for data center solid-state drives featuring PCIe 5.0 and 6.0 interfaces. Kioxia and Sandisk plan to offer BiCS9 NAND specifically for client applications.

When we normally describe 3D NAND memory, we usually mention all possible applications, which include high-end consumer SSDs (after all, we are Tom's Hardware, we are hardware enthusiasts!) and data center drives. We did not mention consumer applications for BiCS10 for a very specific reason: Kioxia does not position this generation for client devices and only targets data center-grade drives. Whether or not to expect BiCS10 on a high-performance SSD near you probably depends on supply and demand, given the current market circumstances.

While the BiCS10 332-layer 3D NAND boosts bit density by 59% all the way to over 29 Gb/mm², it also promises to deliver meaningful performance and efficiency gains specifically for enterprise applications. Kioxia claims read latency drops by around 4 microseconds (about 10%), while read energy consumption is reduced by 25%, from roughly 100 mJ/GB to approximately 75 mJ/GB.

According to Kioxia, these improvements stem from a redesigned read scheme that changes how unselected word lines behave during consecutive read operations. In a 332-layer NAND stack, a significant portion of read latency and power consumption is associated with repeatedly charging long word lines from ground (VSS) to the read voltage (VREAD).

Normally, NAND memory discharges its wordlines to ground (VSS) after every read, which is a general-purpose approach that works regardless of what the next operation is. However, there is no need to discharge at all times. Therefore, during continuous read operations, the word lines are not fully discharged in the case of BiCS10. Instead, they are lowered to an intermediate voltage and then raised back to VREAD for the next read, which makes a lot of sense for read-heavy applications (most cloud applications are).

After the initial read, the circuitry reduces the word-line voltage only to an intermediate level instead of completely discharging it to VSS. Before the next access, the voltage is restored to VREAD from that intermediate level rather than from ground. Since the voltage excursion is considerably smaller, the word lines recharge more quickly and require less current, which improves both read latency and energy efficiency. The approach is particularly beneficial for very tall 3D NAND stacks, where long word lines amplify charging delays and power losses during sustained sequential read workloads.

It is interesting to note that Kioxia and Sandisk plan to manufacture their BiCS9 and BiCS10 3D NAND products at different production sites. The newest Fab 2 facility in Kitakami, Iwate Prefecture, will handle production of the flagship 332-layer BiCS10 memory, while the long-established Yokkaichi complex in Mie Prefecture will continue manufacturing the 218-layer BiCS9 generation.

This manufacturing split makes a lot of sense. Fab 2 is equipped with Kioxia’s most advanced production tools, so it is better suited to manufacture the highest-density NAND from Kioxia and Sandisk. Meanwhile, the mature Yokkaichi fabs are well-suited for client-oriented BiCS9 production. The manufacturing facility has largely been depreciated, which enables the company to manufacture mainstream NAND at lower cost and reserve its newest capacity in Kitakami for leading-edge products.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

In a world where memory is no longer a commodity but a strategically valuable asset, customers are eager to sign long-term supply agreements (LTAs) with their suppliers to ensure a steady supply of 3D NAND and/or DRAM. Micron this week announced that it had signed 16 strategic customer agreements (SCAs), 14 of which are worth around $100 billion. Furthermore, the company expects to receive cash deposits and other commitments worth $22 billion, but has warned there is no foreseeable end in sight to the RAM crisis driving up PC component prices.

“14 of the 16 SCAs that we have signed have a cumulative revenue at minimum price per our contracts of approximately $100 billion over the remaining agreement term,” a statement by Micron reads. “Under the SCAs we have signed so far, we project to receive cash deposits and related financial commitments of $22 billion.”

Based on Micron’s claims, the company has about $100 billion of guaranteed baseline revenue already locked in under 14 of those 16 strategic customer agreements, assuming customers only buy the minimum committed volumes and only pay the minimum contract price. In reality, Micron can earn more if customers buy higher volumes or pay higher prices. Furthermore, Micron expects customers who signed these long-term SCAs to put up real money up front — or make equivalent binding financial commitments — as part of reserving future memory supply.

Micron claims it has signed strategic customer agreements with four 'very large customers' and three 'medium-sized customers,' which means that the contracts were inked with clients that previously did not commit to LTAs. The contracts are signed with a five-year term (except the automotive LTAs, which have a term of three years), from calendar 2026 to calendar 2030.

Micron claims that memory supply will be insufficient in 2027 and may improve gradually only in 2028. To that end, it is not surprising that its clients are willing to sign LTAs for 3D NAND and DRAM to ensure that they have enough memory for their products.

"With respect to supply, our customers are recognizing that supply shortages in memory and storage will take considerable time to improve," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks. "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand."

Normally, Micron and other memory producers inked LTAs with select clients only (read: with Apple, Nvidia). 16 LTAs is a lot for this kind of arrangement, and this looks like a business model shift for the company. It is noteworthy that the 16 signed contracts represent roughly 20% of Micron's DRAM volume and 33% of the company's NAND volume over the period through 2030. That said, Micron may sign more LTAs with more companies.

In the spirit of the times, Biwin, a well-known producer of solid-state drives and memory modules, announced that it had signed a two-year 3D NAND memory agreement worth $1.86 billion, the company told us at Computex 2026. We then dug up the announcement in a filing with the Shanghai Stock Exchange. The amount of money the company plans to spend on flash memory exceeds 50% of Biwin's annual revenue, demonstrating how committed SSD makers are to securing NAND supply amid shortages. Biwin's disclosure comes after several other companies assumed massive amounts of debt to secure supply, and crushing shortages have forced customers into ever-longer long-term supply agreements (LTAs).

Under the terms of the agreement, Biwin will purchase $1.86 billion worth of 3D NAND memory from an unknown supplier over a period of 24 months that starts on June 30, 2026. Both bit volume and pricing are fixed, so Biwin will get its memory at the fixed price no matter how high spot or contract prices are at the time. Of course, this represents risks if NAND prices drop in the next two years, though industry observers believe that NAND supply to SSD module makers will worsen in 2027, so Biwin's risks seem to be manageable.

"The total committed purchase amount under the Contract is US$1.8608 billion, and the commitment period is 24 months," Biwin's filing with the Shanghai Stock Exchange reads. "In accordance with the Contract, both quantity and price are fixed. The Company will complete purchases in batches from the third quarter of 2026 through the second quarter of 2028."

Biwin is among the world's biggest branded suppliers of SSDs, though with a 10% market share in 2024, it cannot rival Kingston or NAND makers themselves. The company's willing to spend $1.86 billion could enable it to grow its market share, or just supply SSDs to large customers, such as hyperscalers that demand a stable supply. At the same time, the purchase commitment that represents over 50% of Biwin's annual revenue shows how difficult it is becoming for the company to get its NAND, with some even commenting that the spot market could dry up in the future as companies are forced to sign LTAs instead. The big question is whether other SSD makers without their own NAND memory will follow through.

What strikes the eye in the announcement is that the procurement volume for 2026 accounts for 4.45% of Biwin's total NAND flash purchases in 2025, which indicates that the company is paying a fortune for a relatively low volume of NAND. Meanwhile, the procurement volume for 2027 accounts for 14.88% of the company’s total NAND flash purchases in 2025, which further underlines the increased pricing of NAND.

It should be noted that for $1.86 billion, the company is 'locking in a portion of its baseline demand for the next 24 months,' which means that the amount of NAND memory it gets does not cover all of its needs. Yet, there is good news too: give the large scale of the company and its roadmap, the overall risk of the supply agreement is 'considered manageable.'

China’s Yangtze Memory Technologies is expected to start operations at its Phase 3 Wuhan fab late this year as the first leading-edge memory plant built to comply with Beijing's unwritten requirement that new Chinese fabs source at least half their equipment from domestic suppliers.

Three sources familiar with the plans told Reuters that more than 50% of Phase 3's tooling has been sourced inside China, that the company aims to add two more fabs of equivalent scale on top of the Phase 3 plant, and that the latter two are not yet committed to specific dates or locations. Phase 3 alone will reach 50,000 wafers per month by 2027 and 100,000 wafers per month at full capacity, doubling YMTC's current 200,000 wafers per month of combined capacity at its first two Wuhan fabs.

50% Chinese tooling

It was reported in late December that Chinese authorities have begun rejecting state approval for new fab construction unless applicants can prove through procurement tenders that at least half their equipment will be Chinese-made. While this rule isn’t published in any formal regulation, officials have told applicants that 50% is a baseline, not a target, with the long-term objective being exclusively domestic wafer fab rules.

Applications below the threshold are typically rejected, with waivers granted only for advanced production lines where domestic alternatives don’t yet exist, and YMTC’s Phase 3 is now understood to be the first leading-edge memory project that’ll clear that bar. The two follow-on fabs YMTC has now told Reuters it wants to build will need to clear it again, twice, before they can break ground.

3D NAND fits this mandate

It’s obvious why YMTC will be the first to launch a fab with a majority of Chinese tooling: 3D NAND. This scales vertically rather than horizontally, which shifts the manufacturing bottleneck away from lithography (the area where China's domestic toolchain is weakest) and toward high-aspect-ratio etch, deposition, and wafer bonding (where it’s strongest).

Each new generation of 3D NAND adds layers rather than shrinking features so that the same lithography node can support 128, 232, or 300+ layer stacks, provided the etch tools can cleanly cut channel holes through 7-to-10-micron dielectric stacks.

In China, it’s Advanced Micro-Fabrication Equipment (AMEC) that provides these tools. Its Primo HD-RIE dielectric etch platform, launched in 2015, was designed for high-aspect-ratio contact applications and was qualified for 6nm flash production a decade ago. AMEC has been working on 3D NAND etch ever since.

Meanwhile, Naura Technology Group, China's largest chip equipment maker by revenue, is supplying etching tools for chips with more than 300 layers, and is testing its etch tools on SMIC's 7nm logic line after deploying them at 14nm. Naura filed 779 patents in 2025, more than double what it filed in 2020, while AMEC filed 259.

All that aside, YMTC still depends on imported tools for lithography — that’s not ideal, given that U.S. lawmakers are now looking at extending the ban on EUV lithography tools to the older DUV machines that YMTC relies on heavily. In terms of Chinese alternatives, Shanghai Micro Electronics Equipment's SSA800-10W is nominally 28nm-capable, but it’s barely deployed in any production fab, and the Yuliangsheng immersion DUV scanner that SMIC began testing in late 2025 is years from supporting volume manufacturing.

For Phase 3 to clear 50% domestic tooling without leading-edge domestic litho, YMTC has to be substituting deeply elsewhere: in etch, deposition, CMP, photoresist removal, cleaning, and metrology. Analysts estimate that Chinese suppliers have reached roughly 50% self-sufficiency in cleaning and photoresist-removal tools alone.

DRAM and HBM allocation

It’s also understood that part of each new fab's capacity will be dedicated to DRAM rather than NAND, with the proportion contingent on YMTC's progress in qualifying its low-power DRAM samples currently with customers. YMTC has decided to allocate 50% of its Phase 3 capacity specifically to DRAM, with one YMTC supplier telling Nikkei Asia in February that the company "started to develop their own DRAM more than two years ago" and now has "the technological foundation and the market" to scale.

That foundation includes a back-end stack that no other Chinese DRAM contender has matched. Wuhan Xinxin Semiconductor Manufacturing, the foundry subsidiary YMTC controls, began developing HBM packaging capacity using hybrid bonding and other IP from YMTC roughly two years ago, and bought equipment for a monthly capacity of around 3,000 wafers. XMC is also working on its own through-silicon via process technology, though the development stages are not public

When YMTC moves from LPDDR samples to volume DRAM and eventually to HBM stacking, it’ll benefit from having the assembly side already (partly) in-house; CXMT, China’s other HBM contender, still needs to build that infrastructure or buy it from XMC.

Convenient timing

The remarks made to Reuters come less than two weeks after a bipartisan group of U.S. lawmakers introduced the Multilateral Alignment of Technology Controls on Hardware Act.

Introduced in the House of Representatives on April 2nd by Michael Baumgartner with Senate companion legislation expected later in the month, the MATCH Act would impose a country-wide export ban on immersion DUV lithography tools and cryogenic etch systems to China and require allies, including the Netherlands and Japan, to align with U.S. controls within 150 days.

The bill explicitly names YMTC, alongside CXMT, Hua Hong, and Huawei, for additional restrictions beyond the country-wide ban. Bernstein analysts called the proposal "far stricter" than previous restrictions and warned it could effectively cap China's advanced chipmaking capacity at current levels.

If the MATCH Act passes in something close to its current form, the stockpiled foreign tools currently keeping YMTC's first two fabs running become harder to maintain over time, and the case for accelerating Phase 4 and Phase 5 on a domestic foundation will grow stronger, not weaker. The two unannounced fabs are conditional on Phase 3 yields clearing acceptable margins, but the regulatory environment around them is moving in one direction.

The high price of commodity memory will inevitably affect the prices — and, eventually, shipments — of inexpensive consumer electronics (CE), as makers of entry-level products are less likely to absorb increased costs. As a result, fabless developers of chips are revising their orders to foundries in order to adjust their inventory, in accordance with what they believe the market needs, said co-chief executive of SMIC, China's top foundry. Interestingly, he also mentioned memory overbooking as a factor affecting memory prices, according to a report from the Wall Street Journal.

 "The combined effect of these factors [related to increased memory prices] has resulted in a decline in mid to low-end [smartphone processor] orders received by foundries," said Zhao Haijun, co-CEO of SMIC, during an earnings call with financial analysts and investors. "End user companies in these segments are facing pressure from both tight supply and rising prices for memory chips. Even if end user companies can pass on these cost increase to consumers via end-product price rises. Such moves will lead to a decline in demand for end products."

Zhao mentioned overbooking as one of the factors that contributed to the sharp rise of 3D NAND and DRAM prices, as many makers of PCs and smartphone tried to order more memory than they needed — which caused prices to skyrocket, and forced many of them adjust their business outlook.

SMIC's executive already discussed this situation back in November, claiming that, as makers of inexpensive CE and smartphones struggle to obtain memory and face excessive prices, they adjust their inventory of entry-level and mid-tier application processors so they don't sit on stocks full of system-on-chips (SoC) while being unable to produce handsets. As a result, SMIC's clients among developers of mobile SoCs also altered their orders accordingly.

More recently, executives of TSMC confirmed that they expected minimal smartphone processor unit growth, primarily due to volume declines of entry-level and mainstream SoCs. TSMC is somewhat immune to such demand drops, however, as the majority of application processors it produces are aimed at high-end, mainstream smartphones, which are less sensitive to fluctuations of DRAM and 3D NAND prices.

"As for PC or the smartphone, to tell the truth, we expect a higher memory price, so we expect the unit growth will be very minimal," C.C. Wei, chief executive of TSMC, told analysts and investors. "But for TSMC, we did not feel our customers changed their behavior. […] We supply most of the high-end smartphones. The high-end smartphone is less sensitive to the memory price. So, the demand is still strong."

It's worth noting that despite declining sales of SoCs for inexpensive handsets, SMIC does not expect its revenues to decline sharply — as, for now, SMIC has some 'protection' against such drops. The company believes that as China adopts more and more chips that are developed and made domestically, it will have enough orders to maintain its growth.

" In 2026, the effects of industrial chain reshoring from overseas and domestic customers, new products, replacing legacy overseas products will persist, creating sustained incremental growth opportunities for the domestic industrial chain," Zhao said.

SanDisk’s stock price hit an all-time high of $650 per share at market open today, but has since dropped to $587.96. Despite that, it’s still an increase of over 1,500% from last year, when its stock was priced at $36 per share. This massive surge is driven by record-breaking profits for the company, which rose 7.7x year over year to $803 million, as reported by Digitimes. The company also noted in its January 29 earnings release that it will extend its joint venture with Japanese flash memory and SSD manufacturer Kioxia, as the two companies prepare to launch their next-generation 3D NAND in 2026.

This growth is primarily driven by the ongoing AI buildout, with revenue from AI data centers, hyperscalers, and semi-custom customers growing by 76%. Aside from that, revenue from industrial and automotive customers increased by 63%, while revenue from the consumer market grew by 52%. “This quarter’s performance underscores our agility in capitalizing on better product mix,” SanDisk CEO David Goeckeler said. “All at a time when the critical role that our products play in powering AI and the world’s technology is being recognized.”

Memory chips have made headlines as their prices have skyrocketed globally, but NAND is expected to follow close behind as AI tech companies pour money into infrastructure and siphon the world’s supply of memory and storage. In fact, a Kingston rep warned late last year that you shouldn’t wait if you need to upgrade your RAM or SSD, as “prices will continue to go up.”

SanDisk is one good example of this, as the company is set to double the price of its 3D NAND enterprise SSDs in the first quarter of this year. It’s unclear whether this move will also affect the 3D NAND used in consumer products, but they’re typically manufactured in the same fabs that produce these enterprise-grade chips. But as AI companies continue to build more advanced models, the ever-increasing training and inference workload will only increase demand for NAND chips, helping SanDisk increase its revenue even further.

Micron this week announced that it had begun construction of a new advanced wafer fabrication facility in Singapore, which will take over 10 years to completely build and will cost about $24 billion. The new fab will produce 3D NAND memory with initial wafer output sometimes in the second half of 2028.

The new Fab 10B is being built at Micron's existing 3D NAND manufacturing campus in North Coast Wafer Fab Park in Singapore and is designed to deliver up to 700,000 square feet of cleanroom space once it's fully built out. To put the number into context, Micron's Fab 10A and Fab 10X have a cleanroom space of around 500,000 square feet, so the new Fab 10B will more than double Micron's 3D NAND capacity in Singapore.

"This investment underscores Micron’s long-term commitment to Singapore as an important hub in our global manufacturing network, enhancing supply chain resiliency and fostering a vibrant ecosystem for innovation," said Manish Bhatia, executive vice president of global operations at Micron Technology.

The new facility will be Singapore's first double-story wafer fab, which will enable Micron to build it out in iterations and without increasing actual footprint of the fab, which greatly simplifies building out the facility, albeit at the cost of more complex architecture.

The new Fab 10B will be configured in a way to support multiple next-generation 3D NAND manufacturing technologies, including nodes with over 500 active layers, so expect it to be equipped with the latest fabrication tools. In addition to volume production of 3D NAND, the new facility will also be used for R&D purposes, which will greatly simplify process integration and product ramps up. As an added bonus, the new facility will enable Micron to deepen its collaboration with academic and industrial research partners in the region.

Micron says that the new fab will focus on production of high-capacity 3D NAND devices for AI and data center applications, as the company considers these applications its major growth engines going forward. Still, it is necessary to note that the fab will be capable of making all types of 3D NAND devices if Micron needs to in response to future market changes. The current AI boom may or may not last beyond the 10-year timeframe it'll take for Fab 10B to become fully operational, so that versatility is welcome in the face of the typically cyclical nature of silicon demand.

In addition to producing 3D NAND in Singapore, Micron is also constructing an HBM assembly plant in the country. That HBM packaging operation remains on track to contribute materially to Micron's HBM output in calendar 2027.

From an employment standpoint, the new 3D NAND wafer fab is expected to create around 1,600 jobs, largely focused on fab engineering and manufacturing operations. Combined with the approximately 1,400 roles associated with the HBM packaging facility, Micron's current expansion plans in Singapore amount to about 3,000 new positions.

Chinese researchers have developed a capacitor-less DRAM-like memory cell that uses two transistors (2T0C) with dual-gate control, built at a 4F² minimum area, reports TrendForce, citing ResearchGate. The new memory cell architecture uses a self-aligned process. It promises to achieve reliable multi-bit storage, fast DRAM-like write times, and extended retention without a discrete storage capacitor, according to its developers. While it's not a DRAM replacement for now, it could become a viable solution for various eDRAM and stacked 3D memory applications.

Sanctions imposed by the U.S. and its allies on China's semiconductor sector greatly limit the capabilities of the People's Republic to produce chips on advanced production nodes, as companies like CXMT, SMIC, and YMTC do not have access to the latest tools. However, curbing pathfinding, research, and development (R&D) in academia is considerably harder (if possible at all), which is why Chinese scientists can conduct world-class research and develop innovative technologies that are on par with the West.

Before we proceed, let's establish some terminology to avoid confusion. In semiconductor memory discussions, 4F², dual-gate 4F², and 4F² 2T0C are often used interchangeably, even though they describe different layers of the design stack. While all three can appear in the same sentence, each answers a fundamentally different question: how dense the cell is, how the transistor is built, and how the bit is stored.

• 4F² is a layout and density metric that defines the minimum possible area of a memory cell — four times the square of the process feature size — and says nothing about the internal structure of the cell. A 4F² footprint can host a classic 1T1C DRAM cell, an SRAM bitcell, or even a resistive memory element.
• The term 'dual-gate' describes a device-level detail: a dual-gate transistor uses two independently controlled gates to improve electrical control over the channel, reduce leakage, and stabilize threshold voltage. Dual-gate transistors are widely used in the semiconductor industry in logic (FinFET is a dual-gate transistor), SRAM, or DRAM-like cells.
• Finally, 4F² 2T0C describes the actual memory architecture featuring two transistors that store data without a dedicated capacitor by relying instead on charge retained in a transistor channel or floating node. This design gives the cell DRAM-like behavior: it still needs refresh, but avoids the scaling challenges associated with deep capacitors.

When combined, the phrase 'dual-gate 4F² 2T0C memory' means a capacitor-less DRAM cell, based on dual-gate transistors, with DRAM-class density at a minimum. In short, we are dealing with three separate concepts combined in a unique design, rather than a singular invention.

4F² dual-gate 2T0C memory

Being unconstrained by curbs set by the U.S. and allies, National Key Laboratory of Integrated Circuit Manufacturing Technology at the Institute of Microelectronics of Chinese Academy of Sciences (IME CAS) teamed up with the Beijing Superstring Academy of Memory Technology (SAMT), and Shandong University to develop a 4F² 2T0C memory cell architecture that can store two bits of data per-cell (4 levels of charge), offering a write latency of around 50ns, and data retention for up to 470 seconds, making it a viable memory technology. However, while this isn't a DRAM killer, it may be a potent candidate for embedded DRAM and stacked 3D memory built on top of logic.

The breakthrough

The 4F² dual-gate 2T0C memory cell architecture developed by researchers at IME CAS uses two vertical IGZO transistors—one for write (TW) and one for read (TR)—that share a common storage node (SN). Dual-gate operation improves electrostatic control and read stability, enabling capacitor-less, multi-bit storage (2 bits demonstrated) within a compact 4F² footprint. The scientists used a self-aligned single-step (SASS) process to build the cell.

Tests conducted by IME CAS scientists prove that the vertical dual-gate transistor combines high drive current with a sharp turn-on, which makes it easier to clearly distinguish stored charge levels during reads. The cell can hold data for about 470–500 seconds for '1' and '0,' respectively, which is inherently higher than that of DDR5 (which counts in milliseconds), but it is certainly not enough for a storage device.

In addition, the cell can complete a write operation in roughly 50ns, according to its developers. While a 50ns latency is comparable to that of DDR5 (which is about 20 – 40ns), read latency is much more important for real-world performance, but since it depends on sense amplifier architecture (keep in mind that we are dealing with multi-bit storage here) and the actual system, scientists from IME CAS do not publish it.

Reliability testing at 85°C confirms that the device remains stable under prolonged thermal and electrical stress, and threshold voltage shifts are limited to −22.6 mV under negative bias temperature stress (NBTS) and 87.7 mV under positive bias temperature stress (PBTS). A threshold-voltage shift below about 100 mV is considered functionally benign because it does not materially change the transistor’s on/off behavior, timing, or noise margins, so seeing <100 mV shifts at 85°C under accelerated stress can be considered as strong stability (especially for IGZO transistors that are vulnerable to bias stress).

The magic behind the reliable operation of the 2-bit 4F² dual-gate 2T0C memory cell, as well as its solid retention time, is the usage of both gates of the read and write transistors as capacitive contributors to the same storage node, which doubles storage node capacitance (C_SN) compared to single-gate cells, without increasing overall area. As a result, the 2-bit 4F² dual-gate 2T0C memory cell architecture can enable both high density and high reliability at a small area.

SASS production flow

Scientists at IME CAS used its proprietary self-aligned single-step (SASS) production flow to build their 4F² dual-gate 2T0C memory cell. The SASS flow enables the entire vertical dual-gate 2T0C sidewall stack to be built in just one lithography and etch step that simultaneously patterns all pre-deposited layers. This means that write (TW) and read (TR) transistors are formed simultaneously rather than stacked in separate passes, which excludes misalignment and repeated thermal/contamination exposure, which potentially improves yields.

In the demonstrated 4F² vertical cell, the channel height is 120nm, the IGZO channel thickness is ~6nm (it is deposited using atomic layer deposition), and the effective gate length is ~40 nm, as seen in the cross-sectional TEM image. The TEM image also confirms a ~90° vertical sidewall with no top/bottom-device misalignment.

As noted above, the SASS process produces the full stack in one lithography/etch step that patterns pre-deposited layers, which is a fairly simplistic manufacturing method.

First, the researchers deposit a full multilayer stack on the wafer. This stack already includes everything the cell will need later: 30nm of indium tin oxide for ground (GND), the bit line (BL), and the storage node (SN); 40nm of tantalum for the read and write word lines (RWL/WWL); and 40 nm layers of silicon oxide to electrically isolate them. Altogether, the structure consists of five electrode layers separated by four SiOx layers, all deposited before any patterning takes place.

Next comes the main SASS step. Using one lithography mask and one vertical etch, the process cuts through the entire pre-deposited stack at once. This single etch step patterns all five electrode layers and four insulating layers at the same time into a clean vertical sidewall. Since everything is defined in one cut, the write and read transistors are perfectly aligned by design: there are no overlay errors from multiple patterning steps, which is why it is called 'self-aligned.'

Once the sidewall is in place, it is turned into an active device. The exposed tantalum is heated in oxygen at 400 °C, where it self-oxidizes to form a ~9 nm tantalum-oxide high-k gate dielectric directly on the metal. The vertical surface is then coated layer by layer: a ~6 nm IGZO channel is deposited using ALD, followed by the second gate stack, made up of a ~15 nm hafnium-oxide dielectric and a ~25 nm indium-zinc-oxide conductive gate layer.

But is it viable?

Despite detailed knowledge of device-level and vertical nanometer-scale dimensions, the absence of disclosed lateral half-pitch information prevents mapping the IME CAS process to a specific DRAM node. Keeping in mind that we are dealing with a research-grade materials stack and have no idea about yields, any general assessment of the cost efficiency of the process would be inaccurate.

That said, while the production flow looks simple and the lack of capacitors opens doors for eDRAM applications (as logic nodes are not exactly great for producing DRAM-class capacitors), there are questions about the practicality of 4F² dual-gate 2T0C memory. First up, a multi-level cell architecture requires advanced sense amplifiers that are both complex and power hungry, something not appreciated by embedded applications. Secondly, while IGZO TFTs are mature in displays as feature sizes are fairly large and yields are high (and forgiving), memory arrays demand dramatically smaller sizes, and defects are not forgiving.

Given all the uncertainties, it is impossible to assess whether IME CAS's 4F² dual-gate 2T0C memory architecture makes sense for commercial applications.

Despite similarieis, it's not a replacement for DRAM

Chinese researchers from IME CAS have demonstrated a 4F² dual-gate 2T0C, capacitor-less DRAM-like memory cell that reaches the minimum DRAM-class cell area without using a storage capacitor.

The cell is fabricated using a self-aligned single-step (SASS) process and is based on two vertical IGZO transistors sharing a common storage node. Tests conducted by IME CAS show 2-bit storage per cell, write times of around 50ns, and data retention of roughly 470–500 seconds, while the devices remain stable at 85°C. Meanwhile, the dual-gate design enhances retention by increasing the effective storage-node capacitance without increasing the cell area.

For now, 4F² dual-gate 2T0C DRAM-like memory is not a replacement for commodity DRAM. Yet, the work points to a route for embedded and 3D-stacked memory. However, the absence of disclosed lateral pitch, information about manufacturability, the multi-level cell architecture, and uncertainties about the feasibility of IGZO TFTs for mass production of memory cast doubt about the future of this memory architecture. But although we can question the practical applicability of 4F² dual-gate 2T0C DRAM-like memory architecture for existing applications and products, this does not belittle the achievement of Chinese scientists, who managed to make this technology work.

Sandisk is on track to double the price of its high-capacity 3D NAND memory devices for enterprise-grade solid-state drives this quarter in anticipation of strong demand for server-class storage in the coming quarters, reports Nomura Securities (via @jukan05). It is unclear to what degree the price increase of high-capacity 3D NAND will affect quotes on mainstream flash memory used in client devices, but normally, 3D NAND for smartphones and PCs follows enterprise-grade chips as they are made at the same fabs.

"Channel checks indicate that several memory suppliers continued to push prices higher, with enterprise-grade NAND facing especially aggressive increases," a note to clients by Nomura Securities reads. "SanDisk’s NAND used in enterprise SSDs is cited as potentially rising by more than 100% quarter over quarter in the March period."

Nomura Securities, which is among the prominent financial analyst firms with good contacts in the high-tech industry, attributes plans of memory suppliers to increase prices of enterprise-grade 3D NAND both to short-term shortages and to mid-term growth of demand driven by AI in general and changes to AI storage in particular.

Nomura names Nvidia's Inference Context Memory Storage Platform (ICMSP) — which is based on the BlueField-4 DPU equipped with a 512 GB SSD that carries KV cache — among the demand drivers for enterprise storage this year. Every compute tray in the VR NVL144 rack is equipped with a BlueField-4 data processing unit with a 512 GB drive, making it 18 DPUs with 9.216 TB of 3D NAND per rack. Assuming that Nvidia ships 50,000 VR NVL144 racks per annum, the company will have to get roughly 0.439 EB of 3D NAND somewhere. Its partners supplying their versions of VR NVL144 racks with BlueField-4 DPUs will also increase their consumption of 3D NAND memory this year with the Vera Rubin platform.

While Nvidia's ICMSP can consume around an exabyte of 3D NAND per annum in 2026 ~ 2027 in the best case scenario, it cannot really be a reason for 3D NAND price doubling overnight, as the industry produces over 800 EB of NAND every year. Meanwhile, we still do not know how much 3D NAND a typical VR NVL144 machine carries, so we cannot estimate storage demands for Rubin-based platforms in general.

Nonetheless, as demand for AI systems for storage is skyrocketing in general, they will inevitably drive up demand, and once it outpaces supply, prices will get higher, which is exactly what we are seeing today.

Kioxia will produce its next-generation BICS9 and BICS10 3D NAND memory next year, but will use different fab sites for different types of flash, according to Nikkei. BiCS10 transitions to an all-new 332-layer 3D NAND array to address high-capacity solutions for AI and hyperscalers.

Perhaps the biggest surprise about 332-layer BiCS10 is that Kioxia (and Sandisk) is pulling in production of this type of memory to 2026, if the Nikkei report is correct. The publication states that both companies initially planned to produce BiCS10 memory in the second half of 2027. However, demand from the AI, cloud, and enterprise sectors likely prompted Kioxia to begin production ahead of schedule for its most advanced memory announced to date.

While both BICS9 and BICS10 use the CBA (CMOS directly Bonded to Array) architecture and boast a 4.8 GT/s Toggle DDR 6.0 interface, BICS9 uses a smaller 218-layer 3D NAND array to target performance-hungry low-power applications.

Different fabs for different memory

As noted above, Kioxia (and therefore Sandisk) will use different fab sites to make BiCS9 and BiCS10 3D NAND. Specifically, the newest Fab 2 near Kitakami, Iwate prefecture, will become the base for making high-capacity 332-layer BiCS10 NAND, whereas the established complex near Yokkaichi in Japan's Mie prefecture will remain the center for 218-layer BiCS9 3D NAND.

The decision to produce flagship BiCS10 devices at Fab 2 in Iwate Prefecture makes a lot of sense, as the site has the latest equipment, even though Kioxia's R&D center is in Yokkaichi. However, the fabs in Yokkaichi are still good enough (and largely depreciated) for BiCS9, will address mainstream devices, and must be cost-effective to manufacture.

Keep in mind that the information is largely unofficial and unconfirmed by Kioxia and Sandisk; many details are subject to change ahead of an official announcement.

CBA: The key to next-generation 3D NAND

Developing high-speed memory interfaces for 3D NAND is challenging, so leading flash memory suppliers have taken a page from Yangtze Memory's playbook. Companies have begun producing memory arrays and peripheral CMOS logic responsible for memory operations on separate layers. These are then attached together using hybrid-bonding techniques. Kioxia and Samsung call their architecture CMOS Directly Bonded to Array (CBA) and have been deploying the technique since BiCS8 3D NAND, which started production in the second half of 2024.

The companies plan to continue using CBA with BiCS9 and BiCS10, but this time around, adopting an 8-bit Toggle DDR 6.0 interface with a 4.8 GT/s data transfer rate (600 MB/s). This is done to increase performance to unprecedented levels for both generations of 3D NAND, which are set to coexist in the market, targeting different applications.

Kioxia’s Toggle DDR 6.0 interface combines three elements: an unmatched DQS timing scheme, per-pin VREF training (PPVT), and a compact 2-way decision-feedback equalizer (2TI-DFE). Each data pin (DQ [7:0]) has its own calibrated reference voltage, enabling the receiver to detect bits at 4.8 Gbps correctly.

Instead of using the heavier 4-way interleaved DFE used in DRAM interfaces, Kioxia implemented a 2-way version with a Data-Driven Self-Reset (DDSR) circuit. This holds the previous decision values (OP and OM) until it detects a polarity change via a small 3-input NAND gate, preventing incorrect feedback and reducing both area and power.

On the timing side, the Toggle DDR 6.0 interface uses an unmatched DQS structure with PPVT and a simplified 2TI-DFE to simplify timing alignment while still enabling deterministic data read windowing. This cooperation extends the safe sampling window for incoming data without requiring additional analog hardware, which is costly in terms of power and transistor budget. Shmoo plots for all eight data lines confirm that the interface should stay reliable at 4.8 GT/s with this design.

BiCS9: 218L 3D NAND meets Toggle DDR 6.0 at 4.8 GT/s

Implementing both a very high-speed interface and an all-new 3D NAND array with 332 active layers is a costly project that yields high-performance, high-capacity 3D NAND that not all applications actually require. To that end, BiCS9 combines the proven 218-layer 3D NAND array with the NAND interface at 4.8 GT/s.

As Sandisk calls it, BiCS9 will power 'capital-efficient, high-performance, low-power products,' which primarily includes cost-sensitive client storage solutions such as those used in PCs and smartphones, as well as products that require pure performance, and do not need the highest capacity or storage density available.

Perhaps, once yields of 332-layer 3D NAND match those of 218-layer 3D NAND, Kioxia and Sandisk will transition to the new process technology and lower their costs. For now, it makes more sense for both companies to reserve the 332-layer 3D NAND array for applications requiring maximum storage density and capacity.

BiCS10: 332L 3D NAND with lower latency and lower power meets Toggle DDR 6.0 at 4.8 GT/s

While 332-layer BiCS10 3D NAND increases bit density by a whopping 59% to 29 Gb/mm^2, this isn't the only improvement the new type of memory offers, as it also shrinks read latency by around 4 microseconds, and reduces read power consumption by 29%, from around 100 mj per GB to near 75 mj per GB.

Based on Kioxia's description, the company has boosted read performance in BiCS10 3D NAND by changing how the unselected word lines (WLs) behave during continuous reads. In a very tall 332-layer stack, most of the delay and energy cost comes from repeatedly charging long WL strings from VSS up to VREAD.

Normally, after each read, the internal read voltage fully drops to ground and then climbs back to VREAD for the next cycle, which takes time and draws significant current. Kioxia's new method avoids that full swing: after the first read, the circuit lowers VREAD only to an intermediate level (still above VSS), and then, before the next read, raises it back to the full read voltage. Because the WLs move over a smaller voltage range, the array charges faster and consumes less current. Such an architecture makes the read path more efficient and better suited for continuous-access workloads, which is crucial for high-layer NAND dies.

The ongoing structural change of the DRAM market caused by the shift of manufacturing capacities to production of high bandwidth memory (HBM) for AI accelerators has already caused a massive price hike of commodity DDR and LPDDR memory — but the worst is yet to come.

According to the general manager of Chinese memory giant TeamGroup, contract prices of DRAM and NAND products have almost doubled recently. Supply of commodity memory is set to worsen in early 2026, and normalization is unlikely before 2027 – 2028 when more production capacity emerges, reports DigiTimes.

December contract prices of some categories of DRAM and 3D NAND increased 80% to 100% month-on-month, according to Gerry Chen, general manager of TeamGroup, a prominent maker of memory modules, solid-state drives, and products based on 3D NAND. Spot prices tell a similar story. A 16Gb DDR5 chip was priced at $6.84 on average at DRAMeXchange on September 20. On November 19 average spot price was $24.83, but on December 1 average spot price of a 16 Gb DDR5 IC increased to $27.2 (session low was $19, session high was $37).

Essentially, memory alone for a 16 GB memory module costs around $217.6. A PCB, assembly, and testing, additional parts like PMIC will add $8 – $10, so a 16 GB memory module now costs $225 – $228 without manufacturer premiums, logistics, and taxes.

Chen expects availability of DRAM and NAND to worsen in the first and second quarters of 2026 once distribution stockpiles are exhausted. At that point, he cautions, obtaining allocation could become difficult regardless of willingness to pay. In his view, relief would not come quickly: he projects the current shortages to extend into late 2027 and potentially beyond.

The reason for shortages of commodity memory is well known: DRAM makers reallocate their production capacities to HBM (which uses larger DRAM dies than commodity types of memory) that is consumed by AI accelerators, like Nvidia's B300 or custom accelerators by large cloud service providers, such as AWS, Google, and Microsoft. These companies tend to book supply years in advance, so at some point, DRAM makers will not have enough capacity to meet demand for commodity DRAMs.

Building a new greenfield fab takes at least three years, so even if companies like Micron, Samsung, or SK hynix made a decision to build a memory fab today, it would come online in late 2028 at the earliest and would be fully ramped only sometime in 2029.

When it comes to NAND, NAND suppliers also prioritize large customers, which happen to be makers of AI servers. Chen does not expect capacity to swing back to PCs, smartphones, and other consumer devices in 2026, which will affect the prices of these devices.

The effects are clear to see. Enthusiasts are seeing RAM prices for custom-built PCs increase by orders of magnitude week on week, with 64GB of DDR5 RAM now costing more than a PS5 in some cases. This week's Black Friday and Cyber Monday RAM deals might be the last chance to buy RAM before prices skyrocket even further.

SK hynix last week used the 2025 Global Summit to reveal its AI NAND strategy and AIN storage products aimed at artificial intelligence applications. While AI systems have historically used storage devices designed for enterprise servers, SK hynix believes that purpose-built NAND-based storage solutions — AIB P, AIN B, and AIN D — will better serve the needs of AI servers and clusters and will enable higher performance efficiency.

Going forward, SK hynix will offer three distinct product lineups tailored for the specific needs of AI clusters and servers: AIN D for high-density storage, AIN P for high-performance storage, and AIN B — based on High Bandwidth Flash (HBF) technology — for emerging ultra-high-performance storage devices that can be installed along HBM memory. Each product family is designed to address its own set of workloads with their own set of technologies while balancing capabilities and costs to improve every stage of AI, from ingestion and archiving to training and inference.

SK hynix's AIN D (Density) solution will use 3D QLC NAND to store massive AI datasets at the lowest cost per bit when it comes to NAND flash memory. The company expects AIN D to be designed to reach petabyte-level density, far beyond today's terabyte-scale SSDs, which retain key benefits of solid-state drives, such as fast access time and high throughput. SK hynix plans to replace nearline HDDs with these products.

By contrast, AIN P (Performance) will address performance needs of AI inference applications with redesigned SSD controllers and 3D NAND flash memory to maximize input-output operations (IOPS) with a 512B granularity for AI workloads, such as vector database searches and fine-grained random reads. Indeed, SK hynix expects samples of its AIN P SSDs to deliver around 50 million 512B IOPS with a PCIe 6.0 interface and up to 100 million IOPS with a PCIe 6.0* interface by 2027.

"The architecture can deliver up to 50 million IOPS with the 512-byte access for PCIe 6.0, which is seven times higher than conventional PCIe Gen6 enterprise SSD," said Chunsung Kim, vice president of SK hynix. "It is not just built for AI workloads, AIM P can also deliver high IOPS and throughputs for conventional storage applications as well. The proof of concept sample will be available in the E3 form-factor by the end of next year and 100 million IOPS over Gen6, the mass production capable product will be available by the end of 2027.

*A single PCIe 6.0 x4 SSD cannot physically sustain 100 million 512-byte IOPS. The link bandwidth caps out around 31 GB/s vs. around 48 GB/s such performance would require. Reaching that figure would need PCIe 6.0 x8 or x16, PCIe 7.0 x4, or a custom interconnect.

The most advanced element of SK hynix's AI NAND family will be AIN B (Bandwidth) — solid-state storage devices based on the HBF technology developed by SanDisk and co-standardized now by SanDisk and SK hynix. The architecture promises to combine HBM-like bandwidth with NAND density, enabling AI systems to handle more inference batches or longer token sequences without adding AI accelerators or HBM. Given that there is no HBF standard, SK hynix does not talk about actual performance numbers or when it expects AIN B to become available. At the summit, both companies hosted the 'HBF Night' event, where they called for collaborative effort to accelerate NAND innovation.

Both firms co-hosted an 'HBF Night' during the summit, gathering engineers and architects from major global tech players to coordinate ecosystem development.

"Through OCP Global Summit and HBF Night, we were able to showcase SK hynix's present and future as a global AI memory solution provider, thriving in a rapidly evolving AI market," Ahn Hyun, President and Chief Development Officer, said. "In the next generation NAND storage market, SK hynix will collaborate closely with customers and partners to become a key player."

Kioxia is working with Nvidia to build a solid-state drive that would deliver 100 million random IOPS already in 2027, the company said at a news conference earlier this month, Nikkei reports. Nvidia reportedly plans to use a couple of such SSDs — totalling a whopping 200 million IOPS — attached directly to its GPUs to boost AI performance.

"We will proceed with development in accordance with the proposals and requests from Nvidia," said Koichi Fukuda, chief technology officer of Kioxia's SSD division.

100 million IOPS SSD

Kioxia's drives with 100 million random read speeds are projected to use a PCIe 7.0 interface to connect to GPUs in a peer-to-peer mode and will be exclusively designed for use in AI servers that need to access and process vast amounts of data quickly.

Today's high-end solid-state drives can deliver around 3 million 4K random IOPS, but to meet the performance needs of modern and upcoming GPUs — which are optimized for burst memory access — they need to get substantially faster and change the way they interact with NAND media.

Earlier this year, Silicon Motion's CEO Wallace Kou told Tom's Hardware that Nvidia was interested in building SSDs that offer as many as 100 million random IOPS, 33 times more than existing drives can deliver. Around the same time, Kioxia disclosed plans to build XL-Flash-based 'AI SSDs' with over 10 million 512K random read IOPS in the second half of 2026.

AI workloads rely on frequent, small, random reads to retrieve embeddings, model parameters, or database entries. In such cases, 512-byte blocks better represent actual usage patterns than 4KB blocks and provide lower latency. While drives that operate 512B blocks may not deliver the same raw bandwidth as typical SSDs with 4K blocks, it is easier to scale out sequential read/write speeds with multiple drives than to lower the latencies of conventional SSDs.

It remains to be seen whether Kioxia's AI SSD with a 10 million 512K IOPS random performance will materialize in 2026 if Kioxia plans to build drives with a 100 million IOPS random performance in 2027.

Using XL-Flash?

What is interesting is how exactly Kioxia plans to build its 100 million IOPS drive. Its proposed AI SSD is based on XL-Flash, which is SLC NAND memory with high endurance, very low latency, and fairly high performance. Kioxia's XL-Flash devices feature 16 planes (up significantly from 3 to 6 planes on modern 3D NAND devices for client PCs), which points to higher sequential and random performance. As Kioxia does not publish specifications of XL-Flash, it is impossible to judge the per-device performance of this memory type.

Meanwhile, considering that an Innogrit Tacoma-based 400GB XL-Flash SSD with 32 NAND dies (with seven allocated for overprovisioning) and a PCIe 5.0 x4 interface delivers 3.5 million random read IOPS and 0.5 million random write IOPS, we can estimate that each die contributes up to 109,375 random read IOPS and 15,625 random write IOPS—though this calculation comes with some caveats.

Assuming perfect linear scaling across loads of NAND devices, a 100 million 512B IOPS SSD would require 915 of such dies (presuming the same levels of over provisioning). Now that Kioxia knows how to pack 32 NAND ICs into a single package, it can certainly build a drive based on 915 XL-Flash ICs (in 28 packages). Such a drive would require a special controller with at least a PCIe 5.0 x16 host interface (though PCIe 7.0 x4 would be more preferable). The problem is, there is no perfect linear scaling. Real-world performance of NAND devices in SSDs is limited by channel bandwidth, multi‑plane constraints, command pipelining/overheads, queue depth, firmware, and loads of other factors. Hence, the best case scenario for a 100 million 512B IOPS SSD featuring XL-Flash devices is a multi-controller module with dozens of controllers and a switch. Such a solution may well make sense in all-flash arrays, but Kioxia is explicitly talking about an SSD.

Welcome, HBF?

Decades of evolution have made NAND flash memory both cheap and incredibly sophisticated. No matter what modern device you pick up, the likelihood is that it will use some kind of NAND, which has become ubiquitous in both consumer products and data centers. If you cast your mind back several decades, NAND was expensive, despite its capability to be faster than spinning disks. As the technology has matured, its use has grown exponentially. But what's next?

In the coming years, we're going to see cheaper, more advanced non-volatile flash memory inside our devices. Those 3D NAND devices will be built from over 500 layers and boast interface speeds of up to 4800 MT/s. This blistering speed may pave the way to all-new kinds of devices with significantly increased performance compared to today's best SSDs.

The next step

Like other technologies, 3D NAND develops in multiple directions. End users demand higher capacity, higher performance, lower power, compact dimensions, and lower cost. Manufacturers themselves want to earn money, so while meeting demand, they try to cut costs by making smaller memory devices. Given the current state of industry development, the best way to keep the size of 3D NAND dies in check is to increase the number of layers and decrease the size of the actual data storage location — the memory cell itself. This practice is commonplace among memory makers today.

Leading makers of 3D NAND memory, including Kioxia, Micron, Samsung, SK Hynix, and YMTC, have all developed multiple 3D NAND generations, consistently increasing layer counts while reducing cell sizes. For now, the majority of 3D NAND-based devices, including SSDs and smartphones, rely on memory with 2xx layers, with each layer holding an incredible number of memory cells for data storage.

This might be 218-layer 3D NAND from Kioxia, 232-layer 3D NAND from Micron, or 286-layer 3D NAND from Samsung.

The pace at which manufacturers adopt new layer counts and boost transfer rates varies across the industry, making things difficult to track. So let's examine where we were in 2023, how it's going, and where we might be in 2027. Just as a reminder: Kioxia also has a close production partnership with Western Digital's flash division, which also owns SanDisk as a subsidiary. Within this article, we'll refer to the duo as Kioxia / Western Digital.

In recent years, the industry faced significant challenges in building an SSD with a PCIe 5.0 x4 interface that would fully saturate that interface. ICs with a high-performance interface that could fully saturate the lane using an eight-channel controller (e.g., 2400 MT/s) are rare. Instead, ICs that supported lower speeds are much more common.

By early 2023, all three major NAND vendors — Kioxia / Western Digital, Micron, and Samsung — had established 2400 MT/s as the baseline interface speed across TLC products. Kioxia's BiCS 6T and 6Q nodes, Micron’s B58, and Samsung’s V8T are representative of these tiers as a mainstream standard, and perhaps this reflects a consistent performance scaling for both consumer and enterprise storage segments.

In 2024, Samsung took the next incremental step by introducing its V9T TLC at 3000 MT/s. This intermediate speed tier, not shared by other vendors in the roadmap, highlights Samsung’s focus on being a vertically integrated company that focuses mainly on its own-brand products, like smartphones and SSDs.

Kioxia / Western Digital reached 3200 MT/s in the second half of 2024, with its 8th Gen BiCS 3D TLC, followed by QLC (BiCS 8Q) products in 2025 H2. However, Kioxia / Western Digital has not mentioned using 7th Gen products at all, skipping it entirely.

This reflects a general push to align both TLC and QLC offerings on higher-performance platforms. Notably, Kioxia / Western Digital is the only vendor explicitly listed in the roadmap as deploying 3200 MT/s in both cell types, showing a strong commitment to QLC performance uplift.

In 2024, Micron came to leadership with its B68S IC, sporting a 3600 MT/s data transfer rate. By the second half of 2025, the company’s QLC roadmap plans to catch up with Samsung via the N69 generation. This highlights Micron’s early adoption of faster interfaces for high-end products, but since it's yet to be released, its impact and uptake remain to be seen. Kioxia/Western Digital also lists its BiCS 8Q QLC reaching 3600 MT/s in 2025 H2, indicating a broader QLC performance push across the industry.

All vendors eventually converge at 4800 MT/s by 2027, which becomes the high-performance standard. Kioxia/WD reaches this milestone with BiCS 9T TLC in 2027 H1, Micron with B78 TLC and N79 QLC in 2027 H1–H2, and Samsung with its 11th generation of V-NAND.

Performance headwinds

Manufacturing high-speed NAND flash (3600 MT/s and higher) requires a more expensive logic process technology, which drives up production costs and inflates flash memory prices.

An increase in 3D NAND data transfer rates will have a very practical implication on how devices like SSDs or smartphones are built.

To fully saturate a PCIe 5.0 x4 interface — which provides up to 15.75 GB/s of effective bandwidth — a modern NAND flash setup requires an SSD controller with eight channels at 2400 MT/s, six channels at 3600 MT/s, or just four channels at 4800 MT/s. In a year or two, PCIe 5.0 SSD controllers won't require eight channels to fully saturate the hungry interface.

For PCIe 6.0 x4, which doubles throughput to around 31.5 GB/s effective (after protocol overhead), the number of required channels increases 16 at 2400 MT/s, 12 at 3600 MT/s, and eight at 4800 MT/s. As NAND I/O performance approaches these thresholds, high-end SSDs can exploit PCIe 6.0 capabilities with eight high-speed NAND devices. However, it remains to be seen whether PCIe 6.0 x4 SSDs will be a reality for consumer storage devices within the next few years.

Die capacities

Based on the roadmap data that we have collated, leading 3D NAND makers will converge, landing with 1 Tb and 2 Tb die capacities by around 2026 - 2027, particularly for 3D QLC products. While there are some 2Tb QLC NAND devices announced as of May 2025, none of them are actually on the market yet.

Micron, Kioxia/Western Digital, Samsung, SK Hynix, and YMTC all plan to offer 3D QLC devices reaching 2 Tb capacities, typically paired with interface speeds of 3200MT/s – 4800 MT/s over the next few years. Despite the significantly increased layer count, 3D NAND manufacturers are not jumping to capacities higher than 2Tbs per device for the time being, perhaps due to cost concerns.

Rising layer counts: How does each company stack up?

Kicking off with Kioxia and Western Digital, this duo's 3D NAND roadmap featured BiCS 6 with 162 layers across both TLC and QLC variants in the first half of 2023. BiCS 6 represents a mature and commercially proven node, used in mainstream SSDs and enterprise storage. This generation aligns with the industry’s transition toward high-density vertical stacking, while supporting a 2400 MT/s interface speed.

Kioxia and Western Digital didn't stop there, and in the second half of 2024, these companies introduced BiCS 8 in both TLC (BiCS 8T) and QLC (BiCS 8Q) forms, now featuring between 218 and 232 layers. This generation continues to rely on 2400 MT/s – 3600 MT/s interfaces, marking both vertical and performance scaling. Also, it demonstrates Kioxia’s intent to advance QLC’s competitiveness in both storage density and performance.

BiCS 8 will be a fairly long-standing node for Kioxia and Western Digital, as it will be replaced in the first half of 2027. BiCS 9T is set to replace it, boasting a layer count of greater than 300, representing quite an aggressive step forward. This milestone puts Kioxia in alignment with other vendors’ 3D NAND scaling targets, while also introducing 4800 MT/s interface speeds.

Micron’s lineup includes the now legendary B58 IC with 232 layers and a 2400 MT/s data transfer rate. But its 1st Gen ICs featured a lower rate; its full speed was only achieved sometime in the first half of 2023. Nevertheless, the B58 gave Micron an early lead in vertical scaling versus competitors still shipping 162–192 layer products.

In the second half of 2024, Micron advanced to the B68S IC, increasing the layer count to 276. This generation pairs higher density with elevated performance (3600 MT/s), making it a major step in Micron’s 3D NAND roadmap, and making the company one of the leading makers of enthusiast-grade SSDs with the model 4600.

In the first half of 2027, Micron is expected to introduce its B78 3D TLC NAND ICs, with a 4800 MT/s interface. However, the exact layer count is not known. Given the trend from B58 (232L) to B68S (276L), it is reasonable to expect B78 to reach well beyond 300 layers, likely on par with Kioxia’s and Samsung’s leading nodes. However, there are no official materials on exact layer counts, so this remains speculation.

When it comes to 3D NAND makers, Samsung is a rare animal. All producers of flash memory prefer to sell their chips as parts of their own devices, such as SSDs, and to that end, Micron works closely with Silicon Motion and Phison to optimize controllers for its memory and drives. In a similar vein, Kioxia works with Phison. Unlike its rivals, Samsung has its own 3D NAND and controllers to build its SSDs and other products using NAND flash memory. The company also sells its 3D NAND ICs on the open market as an additional boon.

Samsung offered its V8T IC in 2023 H2 with 236 layers, placing it alongside Micron’s B58 and slightly ahead of Kioxia’s BiCS 6. This node continues to be Samsung’s workhorse today.

By the second half of 2025, Samsung is set to mass produce V9T, scaling to 286 layers — a 50-layer jump over V8T. This milestone indicates V9T’s interface speed remains at 3600 MT/s, indicating a controlled ramp before moving to more aggressive performance targets.

Looking ahead to 2026 H1, Samsung’s roadmap lists V10T IC with an expected layer count of over 400, representing the most ambitious vertical target. While this node’s interface speed is also pegged at 4800 MT/s, its standout feature is the sheer layer height, suggesting multi-tier stacking and next-gen integration techniques, such as string stacking and hybrid bonding. However, Samsung has not officially announced that it is using any of those specific techniques quite yet.

SK hynix’s current product lineup includes the V8T IC with 238 layers, a 2400 MT/s interface, and has been available since the second half of 2023, marking their entry into late-Gen 3D NAND scaling. The next major leap occurs with V9T, reaching 321 layers in the first half of 2025, and then increasing interface performance to 3600 MT/s by the second half of 2025.

This shows a rapid vertical scaling effort while improving I/O bandwidth. The company's most ambitious node, V10T, is set to debut in 2027 H1, with 500 layers and a 4800 MT/s interface — matching top-tier bandwidth targets from other vendors, and surpassing them in vertical stack height. The roadmap extends further to V11T (4800 MT/s), though its layer count is not explicitly known.

On the QLC side, SK hynix’s roadmap begins with V7Q in the first half of 2024 at 176 layers, then it extends to V9Q, which delivers 3200 MT/s performance and a 2 Tb die capacity — implying a 300L+ stack. By the first half of 2027, QLC products are also expected to adopt the 500-layer structure (V10Q) at 4800 MT/s, mirroring TLC’s configuration.

When it comes to layer counts, China-based YMTC is not a leader, but its 3D NAND development shows a clear trajectory from mid-tier to high-tier stacking. YMTC’s 3D TLC product (X4-9060) features 128 layers and a 3600 MT/s interface, and was followed quickly by X3-9070 in the second half of 2024. X3-9070 jumped to 232 layers while maintaining the same data transfer rate. This indicates a rapid scaling of vertical density — despite sanctions by the U.S. government. This is likely enabled by the company’s proprietary Xtacking architecture, which separates logic and memory layers to simplify integration. However, no QLC-specific layer counts are known for now.

By 2026 – 2027, YMTC’s roadmap aims to enter the high-performance class of its competitors. The X5-9080 and X5-9070 3D TLC NAND products operate at 4800 MT/s, and the latter is explicitly listed as a 1 Tb die, suggesting a likely move to 300+ layers, although exact counts are not known. Meanwhile, the company’s 3D QLC line (e.g., X4-6080, X5-6080) appears on the roadmap in parallel, also reaching 4800 MT/s by the second half of 2026, hinting at comparable architectural advances.

YMTC’s roadmap outlines a fast-paced rise from 128L to 232L and potentially 300L+ stacking within three years—driven by a balance of aggressive layer scaling and interface speed improvements across both TLC and QLC products.

What's next for 3D NAND?

The future of 3D NAND is defined by fairly aggressive vertical scaling, faster interfaces, and a push toward higher per-die capacities, which will enable products that will enable faster, denser, and more cost-efficient storage across consumer and enterprise segments. To make that happen, all major vendors are set to converge at a 4800 MT/s interface speed and 300–500-layer stacks by 2027.

However, this progress is not without complexity. Vertical scaling introduces new challenges in terms of yield, while higher speeds now also require logic process nodes, which raises manufacturing costs. Eventually, when everyone in 3D NAND manufacturing converges at hybrid bonding (which YMTC already uses, while sporting one of the industry’s widest patent portfolios). These techniques will add another layer of complexity, and companies will require some time to get used to these new processes.

In any case, the future of 3D NAND is bright, as the industry races towards faster speeds, higher stacks, and more complex manufacturing technology.

Kioxia and SanDisk have begun sample shipments of their ninth-generation BiCS FLASH, a NAND flash technology that blends legacy architectures with modern enhancements to create a bridge between the current BiCS8 generation and the forthcoming BiCS10. While BiCS10 is expected to deliver higher capacities through a cutting-edge 332-layer design, BiCS9 takes a more cost-optimized approach, targeting enterprise SSDs built for AI workloads and mid-tier storage solutions where efficiency and performance balance are key.

What sets BiCS9 apart is its hybrid construction, achieved through CMOS directly Bonded to Array (CBA) technology. In this process, the logic and memory cell wafers are fabricated separately under optimized conditions before being bonded into a single, high-performance package. This innovation allows Kioxia to mix and match mature cell structures—such as a 112-layer BiCS5 or a 218-layer BiCS8—with a modern I/O interface. The result is a chip capable of delivering Toggle DDR 6.0 speeds of up to 3.6 Gb/s, with peak speeds reaching 4.8 Gb/s under controlled testing conditions.

Despite employing fewer layers than BiCS8 or the next-gen BiCS10, BiCS9 still brings meaningful upgrades. Write performance is up by 61%, read speeds improve by 12%, and power efficiency rises by 36% during writes and 27% during reads compared to previous 512 GB TLC designs. An 8% increase in bit density further underscores the careful engineering that allows BiCS9 to deliver strong performance without inflating costs.

Yangtze Memory Technologies Co. (YMTC), China's leading producer of NAND memory, has been on the Entity List of the U.S. Commerce Department since late 2022, which essentially bars its access to advanced fab tools. Despite sanctions and restrictions, YMTC plans to expand its production capacity this year, aiming to capture a 15% share of NAND memory production by the end of 2026, reports DigiTimes. The company also plans to build a trial production line that exclusively uses Chinese fab tools.

YMTC to expand capacity to 150,000 wafer starts per month

YMTC was expected to reach a monthly capacity of 130,000 wafer starts per month (WSPM) by the end of 2024, which equates to roughly 8% of the worldwide NAND supply, according to DigiTimes. While YMTC's abilities to procure fab tools from leading producers, such as ASML, Applied Materials, KLA, and LAM Research are extremely limited, the company still plans to increase its production capacity to around 150,000 WSPM. Earlier this year, the company began mass production of its X4-9070 3D TLC NAND memory, featuring 232 active layers and a total of 294 active layers. The company's 5th Generation NAND memory bonds two structures containing 150 and 144 layers together to achieve a total of 294 layers.

The increased output, combined with the increased number of layers (or gates per vertical NAND string), effectively increases NAND memory bit output for YMTC. However, it remains to be seen whether such a strategy can enable the company to double its market share and achieve 15% of the global NAND output by late 2026.

Unlike other global NAND suppliers, who are cutting production and investment due to soft demand and pricing pressure, YMTC continues to expand. Bit growth across the industry is forecast to rise by about 10% to 15% in 2025, but YMTC is expected to ramp up its bit growth aggressively.

In addition to its flagship 1TB 3D TLC X4-9070 device with a 3600 MT/s interface, the company intends to release its 3D QLC X4-6080 device later this year. We do not know how many active layers this device will use, though it is more than likely that it will retain the 294-layer production technology.

Next year, the company will introduce its 2TB 3D TLC X5-9080 device, as well as a 3D QLC X5-6080 device with a 4800 MT/s interface. The 2TB NAND device will enable YMTC to build high-capacity SSDs with very high performance. Though it remains to be seen whether the company can produce enough of these particular chips.

YMTC's next-generation node will likely use more than 300 layers and will likely require the company to bond three 3D NAND structures together. This means that wafers will spend more time in the fab, therefore reducing the number of wafer starts per month, but increasing bit output.

A new hope?

Under the export rules imposed in late 2022, American companies cannot ship tools that can be used to make 3D NAND memory with over 128 layers to Chinese entities. Of course, the U.S. government cannot ban the usage of string stacking (the technology used by YMTC to build its 232L 3D NAND), so YMTC can continue scaling its 3D NAND using American tools. However, the U.S. Department of Commerce put YMTC into its Entity List in December 2022, which means that American companies should get an export license from the Department of Commerce to sell tools to the Chinese company.

We do not know whether or not YMTC managed to acquire any new American tools after 2022, but the NAND flash producer plans to begin trial production on a new manufacturing line built entirely with domestically developed equipment in the second half of 2025, according to DigiTimes.

This marks a major step forward in China's goal to reduce reliance on foreign semiconductor production tools. However, a 100% localization of fab tools is well beyond what analysts may think is possible for Chinese chipmakers today.

Looking ahead, YMTC is expected to account for approximately 30% of China’s NAND consumption in 2025, but its output still falls short of national demand. The upcoming trial line is expected to help YMTC ease output constraints, even though yield levels are a major concern, due to Chinese tools being known for lower yields when compared to their American, Japanese, or European counterparts.

Analysts believe YMTC's new production line, which exclusively uses Chinese fab tools, could lead to a doubling of YMTC's bit output by the end of 2026, potentially pushing its share of the global NAND market beyond 15%.

However, these predictions may be too optimistic, as the new production line will be a trial intended to test the capabilities of tools made in China, not to produce 3D NAND devices in high volume.

If YMTC's trial production line results end up being promising, it could scale it to build flash memory chips at volume. However, scaling up will require a lot of time, so YMTC's aspirations of capturing 15% of the NAND market by late 2026 remain optimistic. It is believed that if YMTC's production capacity exceeds 200,000 WSPM, this could also influence global pricing trends.

YMTC already leads transition to domestic tools

Samsung has introduced its upcoming 10th-generation V-NAND flash memory with over 400 active layers and a 5.6 GT/s interface speed at the International Solid-State Circuit Conference 2025. The new type of memory not only boasts a record number of active layers and groundbreaking performance (which will enable some of the best SSDs), but it also uses Samsung's cell-on-peripheral (CoP) architecture with hybrid bonding, a first for Samsung. 

The 10th Gen V-NAND device that Samsung presented at ISSCC is a 3D TLC NAND device with over 400 active layers, a 1 Tb capacity per die, and a 5.6 GT/s interface speed. As the new memory IC continues to use a triple-level cell design, it offers a 28 Gb/mm^2 density, which is slightly lower compared to Samsung's 1Tb 3D QLC V-NAND, which reaches 28.5 Gb/mm^2. However, density may not be Samsung's main goal with this particular product as the key innovations that it introduces are the record number of active layers (over 400) and hybrid bonded periphery circuitry. 

While Samsung, just like other makers of NAND, has placed peripheral circuitry below the memory array for some time now, with its 10th Generation V-NAND, the company produces peripheral circuits (featuring row decoders, sense amplifiers, buffers, voltage generators, I/O) on a separate wafer using its logic technology. Then, it bonds it to the wafer with a 3D NAND memory array. Other leading makers of 3D NAND memory — including Kioxia/Sandisk and YMTC — also produce 3D NAND array and periphery on different wafers and then bond them together. 

Such an architecture enabled Samsung to dramatically increase the interface speed of its 10th Gen V-NAND memory to 5.6 GT/s. At this rate, a single NAND device can offer a peak transfer rate of 700 MB/s. In larger configurations, ten of these could fully utilize a PCIe 4.0 x4 interface, while twenty would max out a PCIe 5.0 x4 connection. A setup with 32 dies across two NAND packages would push performance close to the limits of PCIe 6.0 x4. 

Most NAND packages on SSDs are built with either eight or 16 dies. A package containing sixteen dies can store up to 2TB, meaning that four in a single-sided SSD would provide 8TB of capacity. A dual-sided M.2 2280 drive could double that to 16 terabytes. However, Samsung has not released a new dual-sided SSD in recent years as they are not compatible with the vast majority of notebooks.

Without any doubt, Samsung's 10th Generation V-NAND's increased bandwidth and capacity could play a crucial role in next-generation storage devices as these devices enable Samsung to build ultra-high-performance SSDs and UFS modules with competitive capacity points. However, market availability of such products will depend on how quickly Samsung ramps up its latest 3D TLC V-NAND. Yet, Samsung has not yet disclosed when its 10th Gen V-NAND will be incorporated into its own SSD lineup.

Officially, the development of mainstream storage class memory (SCM) like Intel Optane has been suspended at big companies like Intel and Micron, but it looks like China-based Numemory, also known as Xincun Technology, has quietly introduced a new Optane-like memory. The company's first SCM memory devices wed the performance of dynamic random access memory (DRAM) and the non-volatile capabilities of NAND flash memory. But it looks like at a high price.

Good performance, not enough capacity (yet?)

As for general performance, South China Morning Post claimed last fall, citing the company, that Numemory's NM101 chips can be used for SSDs that can load a 10GB high-definition video in just one second. This is in line with what modern performance-mainstream SSDs with a PCIe 5.0 x4 interface can do. However, there is no word about the new memory's data retention rates or possible endurance limitations regarding the number of writes. 

Because Numemory's NM101 seems to use an industry-standard NAND interface with a standard 1.2 volts I/O (typical for internal voltages of low-power M.2 SSDs), it is possible to use these devices for SSDs, provided that there is a controller (and firmware) that supports this memory, it is possible to build SSDs that will be drop-in compatible with existing PCs. 

However, 64Gb (8GB) and 128Gb (16GB) memory devices are not exactly economically viable for SSDs these days. One needs 128/64 ICs to build a 1TB SSD. This may not be a problem for an enterprise-grade U.2, ruler, or add-in card SSD that can accommodate loads of NAND packages. But M.2-2280 modules can only house up to four memory packages on one side and four on another side, so it is probably impossible to build 1TB M.2-2280 drives based on Numemory's NM101 and NM102. However, judging how rapidly Numemory has managed to double the capacity of its devices, the company can indeed become a contender for high-performance SSDs. 

Also, if some clients in China would like to use SCM for some performance and relatively capacity-hungry applications that do not necessarily need an M.2-2280 form factor, they can certainly do so, unlike their peers elsewhere now that Intel's Optane (3D XPoint) is gone. Then again, Intel's 2nd Generation Optane memory also had two decks and offered 128 Gb per device, so building truly high-capacity storage devices using such memory was hard, too. Yet, Intel sold boatloads of Optane-branded products.

64Gb and 128Gb devices with a 3200 MT/s interface

Xincun Technology's 1st Generation Numemory device emerged back in September last year. The NM101 is a 64Gb (8 GB) single-level cell (SLC) 3D-stacked memory IC with an industry-standard 3200 MT/s NAND interface. The operating voltage of the memory array is 5.3/4.5 volts (which points to a mature process technology used to make the IC), whereas the I/O voltage is 1.2 volts, an industry standard. 

Since 64Gb (8 GB) capacity is hardly enough for more or less high-capacity storage devices, the company quickly followed up with its 2nd Generation product earlier this year. The NM102 memory chip features a 128Gb (16 GB) capacity yet retains an SLC architecture and a 1.2V I/O voltage. Numemory does not disclose the operating voltages for its NM102, so we can only make guesses. 128Gb is the capacity of Intel's 2nd Generation Optane (3D XPoint) memory devices. 

Xincun does not disclose further specifications of its devices, only briefly mentioning 'ultra-fast microsecond-level response times,' which is a very vague description of latency, to put it mildly. To put the number into context, Intel's Optane promised 10 ~ 15 microseconds read latency and over 200-microsecond write latencies, whereas modern 3D TLC NAND can boast 80 microseconds read latency and write latencies that are in the ballpark of hundreds of microseconds. By contrast, the latency of DDR5 SDRAM is 10 to 20 nanoseconds, depending on the exact memory subsystems.

No details about architecture

Unlike the vast majority of SCM producers, Xincum does not reveal the underlying architecture of its devices (impedance memory, phase-change memory, MRAM, FeRAM), so we do not know how close this SCM is to DRAM and how far away it is from SLC 3D NAND. Yet, the manufacturer states that its memory is a 'a promising next-generation non-volatile storage technology for large-scale mass production.' Speaking of mass production, it is also unclear whether Xincun has its own production capacity or has outsourced manufacturing to a foundry. As the company has 220 employees and 80% of them are R&D personnel, we doubt the firm has its own fab. 

Xincun Technology was established in Wuhan in July 2022 with the aim of developing storage class memory, which was then missing from the portfolio of commercially available memory technologies developed in China, which strives to become self-sufficient in terms of critical chip supply. Production of Xincun's chips can be considered a notable achievement in China's ongoing efforts to strengthen its semiconductor capabilities in general and develop unique technologies in particular.

Yangtze Memory Technologies Co. (YMTC) has quietly started to ship its 5th-Gen 3D NAND memory with 294 layers in total as well as 232 active layers, and analysts from TechInsights have managed to obtain these ICs for analysis, reports @Jukanlosreve. As it turns out, YMTC has successfully increased bit density to the levels of its industry peers, while it also achieved the highest vertical gate density — despite sanctions against the company imposed by the U.S.

There are a couple of catches, however. 

The chip achieves a remarkable total number of layers (or gates per vertical NAND string) — 294 — which TechInsights says is the highest for current commercial products. The number of active layers of YMTC's 5th Generation 3D NAND is expected to be 232, the same as in the case of the company's 4th-Gen 3D NAND, which has 253 layers in total. The increase in the total number of layers could be a way to improve yield by increasing redundancy or enabling certain features.

Like its predecessors, the 3D NAND device uses string stacking. However, it is unclear whether Yangtze Memory uses two ~147-layer arrays or multiple arrays with fewer layers. In any case, the 294 layers (including active and dummy layers) are an important milestone for YMTC and the whole flash memory industry.

232 active layers is not a record layer count for 3D NAND, but it is in line with the rivals. Only SK hynix's 321-layer 9th Generation 3D NAND has more than 300 active layers these days, though its shipments will start in the first half of this year. The achievement of 294 total layers (or gates per vertical NAND string) not only positions YMTC as a strong contender in the global NAND flash memory market but also signals significant progress in China's semiconductor industry amid major U.S. sanctions. 

In terms of bit density, YMTC's 5th Gen 3D TLC device surpasses 20 Gb/mm², which seems to be in line with what SK hynix's G9 3D TLC NAND IC offers and is just slightly below the 22.9 Gb/mm² featured by Kioxia's/Western Digital BiCS8 3D QLC NAND device, according to TechInsights. YMTC's competitors have yet to introduce 3D TLC NAND chips with density levels similar to those of the market.

With its 5th Generation 232-layer 3D TLC NAND devices, Yangtze Memory continues to use hybrid bonding technology to connect the flash array with CMOS logic and interface, which enables the company to maximize storage density and I/O performance for the best SSDs that usually surpasses what is offered by rivals. YMTC's 3D TLC NAND ICs use Xtacking 4.0 architecture. 

YMTC's 232-layer 3D NAND with 294 gates per NAND string marks a significant milestone for the company specifically and the Chinese memory industry more broadly. It is noteworthy that Yangtze Memory has not formally announced its 5th Generation 3D TLC NAND devices but has instead quietly begun their volume shipments. This move was possibly made to avoid drawing the attention of the U.S. government and risking further sanctions.

Phison was the first company to offer an SSD controller with a PCIe 5.0 x4 host interface and was the indisputable leader in the market of enthusiast-grade SSDs for a couple of years. This week, the company cemented its lead by introducing its next-generation PCIe 5.0 SSD controller for the best high-end SSDs, the PS5028-E28. The new chip promises even higher performance and compatibility with next-gen 3D NAND.

The Phison PS5028-E28 is a brand-new, eight-channel controller that can work with upcoming types of 3D NAND featuring a 4200 MT/s interface and supports SSDs with a 32TB capacity. Regarding performance, the unit promises a maximum sequential read and write performance of 14.5 GB/s (the absolute maximum that a PCIe 5.0 x4 interface can offer) as well as a maximum random read and write performance of 3 million IOPS.

Due to its compatibility with next-generation 3D NAND memory, the Phison E28 controller will enable SSDs with capacities of up to 32TB, which is good enough for client PCs, workstations, and even entry-level datacenter applications.

Phison did not disclose many specifications for its new E28 controller. However, it is reasonable to expect it to have improved compute capabilities compared to the E26 to ensure compatibility with upcoming generations of 3D NAND memory and to provide enhanced functionality.

Phison uses TSMC's N6 process technology (6nm-class) to make its PS5028-E28 chip, which is a significant upgrade compared to TSMC's 12FFC (12nm-class) production node used to make the PS5026-E26 controller. The average power consumption of an E28-based SSD will be around 8.5W, which is slightly higher than the 7W advertised for E26-based drives. However, this is expected since NAND memory gets more complex and requires more processing to read reliably.

At its CES 2025 booth, Phison demonstrated E28-based SSDs with 3D TLC NAND memory from Kioxia (T2BIGB5A2V), which is unsurprising as the two companies work closely together. Over time, the controller will be qualified with 3D NAND memory from other makers, including Micron.

It is hard to say when exactly the actual SSDs based on Phison's PS5028-E28 controller will hit the market. Still, knowing how long it takes to qualify a new controller with advanced memory, we would speculate that the next-generation PCIe 5.0 x4 drives will be available a year from now.

YMTC, a Chinese 3D NAND maker, is not only ramping up production of flash memory at a rapid pace, but does so using silicon wafers produced in China, according to chief executive and chairman of Sumco, a major raw wafer manufacturer. This, among other tactics, allows the Yangtze Memory Technology Co. (YMTC) to increase the output of 3D NAND despite major sanctions imposed by the U.S. government against the company. It also indicates that China is strengthening its chip supply chain to boost the production of its own homegrown blank wafers, which are then used to create various types of semiconductors. 

"Although the majority of wafers produced in China are test wafers, based on our investigations, we understand that wafer production is at around one million," said Mayuki Hashimoto, CEO and chairman of Sumco, at the company's earnings call earlier this month (via SeekingAlpha), according to a quote published by Sravan Kundojjala, an analyst with SemiAnalysis. "The key memory player, where the state is the majority stakeholder, is thought to be consuming 400,000 to 500,000 in domestically produced wafers." 

Chinese 3D NAND and DRAM makers have been procuring new equipment and expanding their manufacturing capacity for several years now. For example, Changxin Memory (CXMT), a DRAM maker, increased its monthly output from 70,000 300-mm wafers per month in 2022 to 200,000 wafers per month in 2024, according to a media report.

The exact capacity of YMTC's fabs is unknown, but if the quote is accurate and the company consumes some 500,000 domestically produced wafers (and probably some produced abroad, too), we can presume that the manufacturer can now build several hundreds of thousands of 3D NAND wafers per month (at least around 250,000), keeping in mind that the company produces NAND memory array and NAND logic using different process technologies on two different wafers, which are then joined together.  

Based on data from TrendForce, Yangtze Memory controlled around 5% of the global 3D NAND market, though given how hard it is to analyze Chinese companies, it is possible that the scope of YMTC capabilities could be even more vast. The very fact that even major American companies adopt 3D NAND memory from YMTC for their performance-mainstream solid-state drives proves that Yangtze Memory produces enough flash memory not only for the Chinese market, but for overseas markets, too. 

Another thing to note about the claims made by the head of Sumco is that Chinese companies are ramping up the production of silicon wafers required to make chips. For now, the country can produce around a million wafers, and these wafers may not be suitable for the most advanced process technologies, according to Sumco. However, this localization is a part of the People's Republic's broader plan to build a more self-sufficient semiconductor industry. 

"China appears to have developed their own capability to fabricate wafers," said Hashimoto. "Quality does not necessarily appear to be very good, but there is strong pressure to comply with the 'Buy China' policy. Local Chinese chipmakers, particularly those with a high degree of state involvement have little choice but to use made in China wafers. This policy directly competes with the inflow of wafers from the free world up to this point, but we do not have a lot of clarity on what exactly is going on."

Kioxia expects flash demand for NAND memory to increase 2.7 times by 2028, spurred by advances in artificial intelligence, Reuters reports. Kioxia will expand its manufacturing capacity and introduce new process technologies in the coming years to meet this upcoming demand.

The chipmaker is expanding its manufacturing capacity in Japan to support this anticipated growth. In particular, Kioxia is advancing construction at its Kitakami facility in Iwate prefecture, aiming for production by fall 2025 after a year-long delay. Production was initially planned for last year, but the timeline shifted due to the industry-wide drop in memory demand. This new capacity, combined with additional cleanroom space at its Yokkaichi plant, is expected to provide enough production bandwidth to address future market needs.

In October, Bain halted plans to list Kioxia on the stock market after potential investors urged a valuation cut. The company's new commentary aims to enhance investors' trust in long-term demand for 3D NAND memory in general and Kioxia's products in particular, as well as re-emphasize plans to kick off production at the company's second production facility in Kitakami.

Earlier this year, Kioxia resumed full-capacity production at its Yokkaichi and Kitakami fabs. The company had previously reduced production by over 30% starting in October 2022 due to weak demand for its 3D NAND memory used in smartphones. Demand for 3D NAND began to recover in the latter half of 2023 as memory inventories declined and the smartphone and PC markets slowly rebounded. Demand for memory chips used in these devices has now stabilized, with additional growth from datacenter orders.

As the demand for AI servers and datacenter-class storage devices grows, Kioxia can address both with 3D NAND flash memory and with enterprise-grade SSDs based on unique controllers and firmware. Other drivers that could lift demand for 3D NAND include on-device AI experiences, which require high-capacity high-performance local storage.

To bolster domestic production, the Japanese government has assigned up to $1.64 billion in subsidies for Kioxia and its partner, Western Digital, to expand their facilities in Yokkaichi and Kitakami. This move aligns with Japan's strategic objective to revitalize its semiconductor industry and position Kioxia as a key player in the global 3D NAND market.

As 3D NAND memory prices are falling due to weaker-than-expected demand in the IT sector, major flash makers are mulling adjusting their output and reducing investments in non-volatile memory, reports DigiTimes, citing South Korean media. Instead, they could invest more in DRAM production as demand for HBM memory from the AI industry is setting records.

Right now, all major makers of 3D NAND—Kioxia, Micron, Samsung, and SK Hynix—are considering reducing the output of non-volatile memory and reducing investments in building out additional flash capacities. If they do it, this will stabilize the pricing of 3D NAND and may somewhat reduce the pricing of DRAM, at least in the short and mid-terms.

Given the current market conditions, companies like Samsung and SK Hynix focus on DRAM, where demand is stronger, particularly in AI. According to the report, they are exploring the possibility of converting parts of their NAND production lines to focus on DRAM in general and HBM in particular, including Samsung's potential conversion of its P4 line and SK Hynix's plans for its Cheongju M14, M15X, and M16 facilities.

Demand for PCs declined in 2H 2022 and 1H 2023, as did demand for 3D NAND memory. As a result, both PC makers and suppliers of SSDs got their hands full of NAND flash and ceased buying more memory. As a result, 3D NAND makers cut their production rates, and utilization rates of their flash production lines dropped from 20% to 30% in 2023. As demand for PCs grew and so did demand for non-volatile memory, 3D NAND manufacturers increased production, and their utilization rates rebounded to 80% - 90% in early 2024.

However, demand has remained subdued, especially for standard 3D NAND products, causing companies to adjust production gradually in line with market trends. High-capacity NAND devices are among the exceptions, but they still see consistent demand as AI and other data centers need high-capacity SSDs.

The IT industry had anticipated a boost in sales of PCs and mobile devices in the latter half of 2024, expecting a replacement cycle to drive up orders. Unfortunately, an economic downturn has dampened consumer confidence, delaying the expected surge in sales to the second half of 2025. This delay has forced manufacturers to reevaluate their production strategies, extend the timeline for inventory management, and consider more aggressive production cuts.

When the U.S. banned the sale of advanced chipmaking tools to Chinese entities in October 2022, China's 3D NAND champ YMTC suffered significantly as it could not get tools it had already paid for. But almost two years later, YMTC is making steady progress in replacing foreign chipmaking tools with domestically developed alternatives, according to Bloomberg which cites TechInsights. 

YMTC has turned to domestic suppliers like Advanced Micro-Fabrication Equipment (AMEC), which specializes in etching equipment; Naura Technology, which focuses on deposition and etching tools; and Piotech, another deposition specialist, for chipmaking equipment. While the company continues to rely on foreign suppliers like ASML and Lam Research for key tools, these Chinese companies are increasingly shouldering a larger part of the production flow, according to TechInsights. 

In recent years YMTC introduced its Xtacking 3.0 and Xtacking 4.0 architectures with up to 232 active layers and high-speed interfaces, which enabled the 3D NAND maker to stay competitive with global leaders like Micron, Samsung, and SK Hynix. Competitive enough to power some of the world's best SSDs. 

Despite this progress, YMTC faces technical hurdles. Its latest NAND chip, produced using Chinese tools, has 70 fewer layers than an earlier version, largely due to lower production yields, according to Bloomberg and TechInsights. The reduced number of layers is attributed to the use of domestic equipment, which resulted in more defects during manufacturing. However, YMTC stated in an email sent to Bloomberg that it was continuously enhancing its product performance, and the variation in the number of layers in its latest devices was unrelated to the production yield of any specific equipment. Still, as soon as the number of defects decreases and yield increases, expect YMTC to increase the number of active layers. 

As the U.S. continues to tighten export controls on advanced chips and equipment, China is pushing for self-reliance in this crucial sector. SMIC's and YMTC's progress is the best indicator that these efforts work. SMIC makes competitive Kirin application processors for Huawei's smartphones and is said to be making Ascend 910B processors for AI servers using its 2nd Generation 7nm process technology, whereas YMTC supplies memory to Huawei and a bunch of other customers in China. The company recently even inked a deal to supply 3D NAND memory for an SSD by U.S.-based Patriot, which promises to offer high performance at a low price. 

While AMEC, Naura, and Piotech are making steady progress with more sophisticated fab tools, slowly closing the gap with leading U.S. companies like Applied Materials and Lam Research, their advancements are less seen by the general public, largely because neither they nor their clients are interested in showing their progress to the outside world in general and the U.S. in particular. 

But while YMTC is adopting more domestic equipment — particularly because Chinese companies are very keen on producing competitive etching and deposition tools — the country's semiconductor industry, in general, continues to rely on foreign tools, such as those from ASML, Applied Materials, KLA, Lam Research, and Tokyo Electron. 

In the first half of 2024, China became the top spender on semiconductor-making equipment as Tianxia-based chip producers invested $25 billion in new tools. This surpassed the combined investments of South Korea, Taiwan, and the U.S., highlighting China’s push to localize chip production amid fears of Western trade restrictions. By the end of 2024, China's total spending on semiconductor equipment is projected to reach $50 billion, reflecting confidence in future market demand and the industry's growth.

Kioxia has filed for an initial public offering (IPO) on the Tokyo Stock Exchange, aiming for an October debut, reports Nikkei. The NAND flash maker aims to raise at least $500 million and could be valued at over $10 billion, according to Financial Times. Even after the IPO, the company will be controlled by Bain Capital, SK hynix, and Toshiba. 

Kioxia, the world's third largest supplier of NAND flash memory based on its performance in Q1 2024, as reported by TrendForce, has been seeking an IPO for a while and now that there is interest in stocks associated with the AI boom, it is time for its owners to capitalize on this. The company is currently 56% owned by a special-purpose entity created by Bain Capital and SK hynix (which can control up to 15% of Kioxia), while Toshiba retains a 41% stake. Both Bain and Toshiba intend to gradually reduce their stakes following Kioxia's public listing. 

This IPO marks Kioxia's second attempt to go public. The company had initially planned to list in 2020, but uncertainties caused by the COVID-19 outbreak and escalating trade tensions between the U.S. and China led to a postponement. The decision to proceed now reflects an improved business climate and strong financial performance from Kioxia, which reported a record net profit of ¥69.8 billion ($477 million) in Q2 2024 and then ended production cutting. 

Last year Kioxia attempted to merge with Western Digital's NAND and SSD business. The goal was to create a strong contender against the current market leader Samsung, but the plan was halted due to objections of SK hynix.  

Despite its strong financials, Kioxia's $10.3 billion valuation is expected to be at a discount compared to Samsung and Western Digital. This discount reflects the company's position in the market (largely caused by its production-cutting tactics), its debt levels, and the need to offer attractive pricing to entice both global and domestic investors. 

Kioxia's IPO will occur amid Western Digital's split into two companies: a NAND and SSD maker and a hard drive maker. After the split, Western Digital's NAND company will control around 12% of the global NAND memory supply, leaving Kioxia with another 12%. The two companies will be considerably behind Samsung and SK hynix, and even if they had merged, they would only be comparable to SK hynix in terms of NAND market share.

Chinese 3D NAND champion YMTC has filed a lawsuit against Micron in the Northern District of California (via Blocks & Files) accusing the American company of infringing 11 of its patents covering various aspects of 3D NAND operation. Yangtze Memory asks the court to order Micron to stop the stop the sale of Micron's memory in the U.S. while awarding it with royalty fees. 

YMTC says that Micron's 3D NAND memory with 96 layers (B27A), 128 layers (B37R), 176 layers (B47R), and 232 layers (B58R) as well as some of Micron's DDR5 SDRAM products (Y2BM-series) infringe 11 of its patents or patents applications filed in the U.S. The list of patent applications gathered by @lithos_graphein indicates that they cover general aspects of 3D NAND and DRAM functionality, which may essentially mean that YMTC is trying to make Micron's life harder in a get to gain a leverage against the U.S. government. 

The U.S. Department of Commerce blacklisted YMTC in late 2022, which made it considerably harder for the company to obtain advanced fab equipment from American companies to build its market-leading 3D NAND devices. Last year the company faced even larger problems when the DoC barred sales of fab tools and technologies that could be used to build 3D NAND with more than 128 active layers, which was another blow for the company. 

But Yangtze Memory has managed to persuade Chinese Cybersecurity Review Office to ban the use of Micron's memory in PCs used by government agencies as well as local governments. 

Despite severe restrictions set by the U.S. government, YMTC continued to evolve its 3D NAND memory. The company's Xtacking 3.0 flash memory is in mass production (and some of such devices even do not infringe U.S. sanctions) and now the company is working on 3D NAND featuring its Xtacking 4.0 architecture. Also, earlier this year the company said that it had managed to dramatically improve endurance of 3D QLC NAND to a level of 3D TLC NAND (to 4,000 program/erase cycles), which significantly improves characteristics of inexpensive SSDs. 

Interestingly, U.S.-based Patriot Memory is prepping a high-end PCIe Gen5 x4 SSD with an up to 14 GB/s read speed based on a controller from Maxiotek (a China-based company that evolved from JMicron) and 3D NAND memory from YMTC.

Quinas Technology, a startup working to bring the UltraRAM technology to mass production one day and which demonstrated the first chips last year, this week received £1.1 million ($1.43 million) funding from Innovate UK to accelerate the technology's transition from the lab to the fab, reports ElectronicsWeekly.com.

UltraRAM, developed by Lancaster physics professor Manus Hayne some four or five years ago, is a non-volatile type of memory that features DRAM's performance, durability, and energy efficiency. UltraRAM retains data even after power is removed, and the company claims it has at least 4,000X more endurance than NAND and can store data for 1,000+ years.

To offer its unique properties, UltraRAM relies on quantum resonant tunneling used in photonic devices such as LEDs, laser diodes, and infrared detectors but not mass-produced electronic devices. From a semiconductor device perspective, UltraRAM is a compound device featuring GaSb, InAs, and AlSb layers deposited on top of each other using the molecular beam epitaxy (MBE) method, which has never been used for memory production (at least not outside of academia). 

"We are delighted that Innovate UK is supporting this ambitious project, and that IQE has committed to developing the first part of UltraRAM mass production," said professor Hayne. "This latest award takes the total of our grant funding up to £4 million." 

The main objective of this one-year project is to increase the UltraRAM wafer sizes from 75 mm, produced at Lancaster, to 150 mm at IQE, a British semiconductor company that owns Quinas. This will be achieved using metal-organic chemical vapor deposition (MOCVD) rather than the molecular beam epitaxy (MBE) commonly used in academic settings. The report says IQE will use most of the project funding to transition the compound semiconductor layers developed at Lancaster University to a scalable industrial process at its Cardiff-based facility. 

A significant part of this development involves IQE enhancing its ability to grow the compound semiconductors GaSb and AlSb. Lancaster University will do an initial MBE epitaxy to establish a benchmark for industrial growth, and then IQE will manufacture these semiconductors on a larger scale. Lancaster will assess the quality and characteristics of the produced material. 

Concurrently, Lancaster University will work on reducing the size of individual UltraRAM devices and creating larger arrays. This process aims to eventually demonstrate the feasibility of fabricating UltraRAM on an entire 200-mm wafer, which is not enough to compete against 3D NAND and DRAM commercially, but it could be used as a proof of concept. 

"It is estimated that the global memory chip market will be worth about $320 billion by 2030, but the UK currently has no stake in it," said James Ashforth-Pook, CEO and co-founder of Quinas. "Future compute will place ever-increasing demands on memory capability, driven by emerging applications like novel AI and quantum compute, as well as evolution in more traditional markets like defence and aerospace. UltraRAM's unique combination of non-volatile storage and rapid access memory addresses many of those needs, offering the potential for huge energy savings and carbon emission reduction."

TrendForce's latest report indicates that spot prices for both DRAM and NAND flash memory are unlikely to increase soon due to two reasons. First, there's plenty of inventory on the market. Second, the Chinese government's recent actions against smuggling of refurbished DRAMs has had a further effect on DRAM prices. 

In the DRAM market, spot prices continue decline, in a stark contrast to contract prices. This happens because of excessive inventory levels at module houses, which tend to buy DRAMs on the spot market. Also, weak consumer product markets contribute to the declining prices as makers of hardware do not need more memory than they already have and do not by on the spot market. 

Another major factor that contributes to the decline is the crackdown on smuggling in the Chinese market, which has caused reballed DRAM chip prices to drop further. Reballing is a technique used to repair DRAM chips by replacing the solder balls on the chip's underside, which are used to connect the chip to a circuit board. In many cases, this makes them work again, but such chips are not as reliable as new DRAM. 

Back to pricing. Since the end of May an average spot price of DDR4 1Gx8 2666MT/s chip decreased by 2.54%, falling from $1.881 to $1.835 in the past week alone. While the decreases may not seem significant, they are consistent. 

Similarly, the spot NAND flash market is experiencing weak transactions due to sufficient inventory levels at SSD makers (some of which produce the world's best SSDs), preventing a revival of demand despite price reductions by spot suppliers. This has already led to a continued divergence between spot and contract prices. Also, there is uncertainty regarding potential demand for inventory replenishment in Q3 2024. Notably, the spot price of a 512Gb 3D TLC NAND wafer dropped by 0.57% this week, reaching $3.309. 

In general, both DRAM and NAND flash sport memory markets face significant challenges in terms of pricing due to soft demand. TrendForce does not expect price recoveries in the short term due to market dynamics and external pressure, such as government crackdowns. 

Just earlier this week we reported that Kioxia ceased cutting production of its 3D NAND memory and is set to increase output, potentially to boost market share. This move alone could have major implications on 3D NAND supply and price.

Kioxia has resumed full production after 20 months of cuts. Improved market conditions are behind the changes, reports Nikkei. This potentially means that the world's fourth-largest maker of 3D NAND is back to competing for market share, which could mean price drops for flash memory. The company has also secured refinancing of ¥540 billion ($3.424 billion) and a new line of credit worth ¥210 billion ($1.332 billion) from its lenders. 

In June, Kioxia increased production to full capacity at its Yokkaichi and Kitakami plants, which produce NAND flash memory, the report says. The production cuts, which began in October 2022, were a response to declining demand for Kioxia's 3D NAND memory designed for smartphones, with reductions exceeding 30% at their peak. Additionally, the launch of a new fab at the Kitakami site has been delayed from 2023 to at least 2025. 

However, demand for 3D NAND began to pick up due to the depletion of memory inventory and the slow recovery of smartphone and PC markets, that began in the second half of 2023. By now, demand for chips used in smartphones and PCs has stabilized, while orders from data centers have increased. As a result, NAND prices are expected to rise by 13% to 18% in the April-June quarter. However, as 3D NAND makers begin to increase production, prices may stabilize and then decrease. 

Kioxia reported a net profit of ¥10.3 billion ($65.284 million) for the January-March quarter, marking its first profitable quarter in six quarters. A profitable quarter and a more favorable business environment prompted creditor banks to refinance significant loans and establish new credit facilities. 

The lending syndicate, including Sumitomo Mitsui Banking, MUFG Bank, and Mizuho Bank, has shown confidence in Kioxia's recovery by refinancing existing loans and providing new credit. They will also support the company in upgrading equipment that will enable migration to next-generation 3D NAND nodes. 

Kioxia and Western Digital plan a combined investment of ¥729 billion ($4.620 billion) to install more advanced production tools into its fabs, with the Japanese government subsidizing approximately one-third of the cost.  

Although Kioxia's plans to list on the Tokyo Stock Exchange were delayed due to trade tensions and market conditions, the company is now focusing on this listing to raise necessary funds, which is a good sign for lenders. 

In a rather unexpected turn of events, Western Digital (WD) has teased the industry's first 2Tb 3D QLC NAND device at an investor conference ahead of its official announcement. The new flash memory could potentially reshape the high-capacity solid-state drives market, enabling much faster and larger SSDs that consume less power. The device uses the proven 218-layer BiCS8 production node and is so tiny it can fit on a fingertip. WD also shared plenty of comparative performance data, touting power, density, and I/O performance gains over competing flash.

"I am really excited to share with you a preview of the BiCS8 2Tb 3D QLC die," said Robert Soderbery, Executive Vice President and General Manager of Western Digital's Flash Business. "We have designed this die to meet the data center and AI storage needs. We are going to shortly announce this product, but I want to share it with you today. This happens to be the world's highest-capacity memory die."

A 2Tb (256GB) 3D QLC NAND die is indeed a huge achievement, as the 'base' product that Western Digital introduced on its 218-layer BiCS8 production technology is a 1Tb 3D TLC device. At this point, we have no idea about the exact architecture of the 2Tb IC, such as the speed of its interface (it is probably fast), or the number of planes, or its latency. However, the company did share detailed comparative performance and power metrics (below), and given the fact that the company positions the device for data centers in general and AI storage needs in particular, one can make some assumptions about its performance targets. 

Now, a 256GB 3D QLC NAND device would allow manufacturers to build a 1TB SSD using just four memory ICs and a 2TB drive using eight devices, which greatly lowers their costs. Creating a 16-die package would enable a stunning 4TB in a single chip package.

Thus, assuming that Western Digital (and its manufacturing partner Kioxia) can produce these 2Tb 3D QLC NAND ICs in high volume and with decent yields, the new device can redefine the cost of high-capacity solid-state drives.

As you can see in the album above, WD says its QLC die density is 15 to 19% denser than the competition. It also claims to be 50% faster than competing NAND (I/O speed) while requiring 13% less power to program per gigabyte of data than competitors. You can also see the method the company uses to create the die — WD creates a die with only the CMOS control circuitry and another with the stacked memory cells, then flips the latter over and bonds the two devices together using hybrid bonding technology (much like Chinese fab YMTC's Xtacking tech).

"We typically show you a wafer, but I felt like the view of a wafer does not quite convey what we have achieved," said Sodebery. "So, if you allow me for a quick second, I want to show you the die. I have one here. Please zoom in [on] what I am holding on my finger here. This is the size of the die, much smaller than my fingertip." 

Western Digital plans to formally announce its 2Tb 3D QLC NAND device soon, so we'll likely learn more detailed specifications soon.

SK hynix is evaluating Tokyo Electron's (TEL) latest cryogenic etching tools, which operate at -70C temperatures, to enable new flavors of 3D NAND with more than 400 layers. Cryogenic etching tools 'drill holes' three times faster than conventional tools, a capability that will be instrumental for 3D NAND with over 400 active layers, reports The Elec.

Instead of importing the actual equipment to South Korea, SK hynix is sending test wafers to Tokyo Electron labs in Japan. This method enables the 3D NAND maker to effectively assess the technology's potential without shipping actual tools to SK Hynix and installing them into fabs. The new etching system operates at a chilling temperature of -70°C, which is a stark contrast to the 0°C to 30°C range of current etching processes.

The report says TEL's next-generation etching machine can make a 10-µm-deep etch with a high aspect ratio in just 33 minutes, over three times faster than existing tools. This achievement is not only a major technical improvement but also greatly increases 3D NAND production efficiency, which could reshape the production timelines and output quality of 3D NAND devices.

When it comes to producing 3D NAND, some may say that 'etching vertical holes' is simple — but it is not. In fact, etching deep memory channel holes with good uniformity is a challenge, which is why the industry has adopted double stacking and even triple stacking (building two or three separate stacks instead of one with a 'deep' channel hole) for 3D NAND. 

SK hynix's 321-layer 3D NAND products are said to use a triple-stack structure. With the adoption of TEL's new etching equipment, it will be possible to build a 400-layer 3D NAND device in a single or double stack, which means higher production efficiency. The decision on whether future products with more than 400 layers will transition to a single or double stack will depend on how reliably the tool performs and whether it can reproduce its results consistently.

A significant environmental advantage of TEL’s equipment is its use of hydrogen fluoride (HF) gas, which has a global warming potential (GWP) of less than 1. This is a drastic reduction compared to the traditionally used perfluorocarbons like carbon tetrafluoride (CF4) and octafluoropropane (C4F8), which have GWPs of 6030 and 9540, respectively. As a result, the potential adoption of TEL's new tool reflects a growing industry trend towards greener manufacturing practices.

While SK hynix is testing the etching tool by sending wafers to Tokyo Electron, Samsung Electronics is concurrently evaluating the same technology by importing a demo version of the tool. The results of these tests will determine the future adoption and potential standardization of cryogenic etching technologies in semiconductor manufacturing in general.

Micron is set to receive $6.1 billion in grants from the U.S. Commerce Department under the CHIPS and Science Act, according to Bloomberg. The money will be used to build a massive DRAM fab that will make memory chips on a EUV-based process technology and is set to come online by the end of the decade. There are also plans for a brand-new fab complex in the state of New York over the next 20 years. 

Micron has rather massive expansion plans both worldwide and the United States. In the U.S., Micron broke ground on its $15 billion EUV DRAM fab near its headquarters in Boise, Idaho, back in late 2022. The semiconductor production facilities will be one of the largest DRAM plants in the world. In 2022, the company also announced plans to build a $100 billion fab complex consisting of four modules in New York state over the next 20 years. The fab complex is expected to produce DRAM, 3D NAND, and novel types of memory that may not even exist just yet. 

"New federal funding from President Biden’s CHIPS and Science Act will help lock in 50,000 jobs, a $100 billion investment and millions of dollars in community benefits," said Kathy Hochul, New York Governor, in a statement published by Bloomberg. 

Micron's receipt of the grants is contingent upon securing additional financial incentives, including investment tax credits and local subsidies, which are necessary to offset the higher costs of domestic production compared to overseas operations. The funding arrangement also includes unspecified loans, adding a layer of financial complexity to the package. 

President Joe Biden is expected to formally announce these plans during an upcoming visit to Syracuse, New York, underscoring the national importance of the semiconductor industry, the report says.  

Micron's global strategy extends beyond the U.S. as the company is maintaining and expanding facilities in Japan, Singapore, and Taiwan, where the company produces memory, as well as in China and India, where the company tests and packages its chips. Meanwhile, the U.S. government's focus remains on strengthening the domestic supply chain and reducing dependency on foreign semiconductor production.

Samsung Electronics is set to begin mass production of its 9th generation V-NAND later this month, according to a Hankyung media report. The new generation of Samsung's 3D NAND memory will feature 290 active layers, which is hardly a significant increase from 236 layers, but this brings with it a substantial change in how these flash devices are made. 

The report about 290-layer 9th Generation V-NAND contradicts Samsung's official plans to introduce 3D NAND memory with over 300 layers in 2024, so take the new information with a grain of salt. Meanwhile, it is possible that Samsung decided to reduce the number of active layers in its V-NAND memory to boost yields. Increasing yields at the cost of areal density may be a good way for Samsung to lower the costs of some of the best SSDs that it makes, particularly the drives for mainstream and low-cost systems. 

A key feature of Samsung's 9th Generation V-NAND with 290 active layers is a string stacking production technique, according to the report. Manufacturing processes using string stacking involves building a CMOS layer with logic, then a 145-layer 3D NAND memory array on top, and then another 145-layer of 3D NAND flash above that. While this manufacturing technique is a complex one, it is poised to increase yields for 3D NAND memory products with hundreds of layers, as it is easier to build two 145-layer 3D NAND arrays than one 290-layer 3D NAND array. 

Ultimately, the increased number of layers should enable Samsung to increase areal recording density of its 3D NAND devices. Increasing the density of 3D-NAND is a major goal for all NAND memory makers, as demand for flash in the industry is increasing. Increasing the number of layers in 3D NAND devices also increases production efficiency. Normally, makers of 3D NAND memory tend to increase the number of layers with every new node quite substantially. This may not be the case with Samsung's 9th Generation V-NAND with 290 layers, as it looks like this node will be primarily used to learn how to use string stacking in mass production. Also, it is possible that with 9th Generation V-NAND Samsung will also put more focus on 3D QLC NAND memory devices.

Looking ahead, Samsung has aggressive plans for maintaining its position in the 3D NAND flash market by introducing 3D NAND devices with an even higher number of layers, according to the report. Following the launch of the 290-layer V9, the company intends to release a 430-layer 10th generation V-NAND in the second half of 2025, the report says. This information is corroborated with last year's Blocks and Files report. 

Meanwhile, other industry players are not far behind. SK hynix is gearing up to produce 321-layer NAND by early next year, while YMTC in China plans to manufacture 300-layer products by the second half of 2024, the report says.

Kioxia plans to mass produce 3D NAND memory with over 1,000 layers by 2031, according to the company's chief technology officer (CTO), Hidefumi Miyajima, reports Xtech Nikkei. During his lecture at the 71st Applied Physics Society Spring Meeting at Tokyo City University, Miyajima discussed the technical challenges and solutions for achieving over 1000 layers in a 3D NAND device.

Increasing the number of active layers in a 3D NAND device is the best way to boost the recording density of flash memory nowadays, so all 3D NAND makers strive to do this with new process nodes every 1.5 to 2 years. Each new node brings several challenges, as 3D NAND makers have to increase the number of layers and shrink NAND cells both laterally and vertically. This process requires manufacturers to adopt new materials with every new node, which is a major research and development challenge.

Today, Kioxia's best 3D NAND device is 8th Generation BiCS 3D NAND memory with 218 active layers and a 3.2 GT/s interface (first introduced in March 2023). This generation introduces a novel CBA (CMOS directly Bonded to Array) architecture, which involves separate manufacturing of the 3D NAND cell array wafers and I/O CMOS wafers using the most suitable process technology and bonding them together. The result is a product with enhanced bit density and improved NAND I/O speed, which ensures that the memory can be used to build the best SSDs. 

Meanwhile, specifics about the CBA architecture, such as whether the I/O CMOS wafers include additional NAND peripheral circuitry like page buffers, sense amplifiers, and charge pumps, have not been disclosed by Kioxia and its manufacturing partner Western Digital. By producing memory cells and peripheral circuits separately, manufacturers can leverage the most efficient process technologies for each component, leading to further advantages as the industry progresses towards methods like string stacking, which will certainly be used for 1,000-layer 3D NAND. 

It should be noted that Samsung also expects to achieve production-level 1,000-layer 3D NAND.

Typically, the more charges a NAND flash cell can hold, the less durable it is in terms of program/erase cycles. But 3D NAND material innovations, advancements of NAND controllers, and error correction algorithms can significantly increase the number of P/E cycle a NAND flash cell can sustain. This is what happened with Yangtze Memory Technologies Co.'s X3-6070 3D QLC device that boasts the endurance of 3D TLC ICs, ITHome reports. 

YMTC's X3-6070 3D QLC NAND device belongs to the company's fourth Generation products and features 128 active layers as well as Xtacking 3.0 architecture with a 2400 MT/s interface. While 128 active layers do not seem like a record by today's standards, one of the key part about this 3D QLC NAND device is that the manufacturer claims rather significant endurance of 4,000 program/erase cycles for this IC. The fast interface supported by these devices makes them suitable for the best SSDs featuring a PCIe 4.0 or PCIe 5.0 interface. 

Back in the day, it was believed that 3D TLC NAND could sustain 1,000 to 3,000 P/E cycles, but advancements of materials, controllers, and ECC methods increased that number to 4,000 P/E cycles and beyond. 3D QLC NAND was originally thought to be capable of 100 to 1,000 P/E cycles, but all makers of memory increased that number, as well. YMTC is perhaps the only company to advertise that its 3D QLC NAND is as durable as 3D TLC NAND, other makers of flash memory are surely also making progress in this direction.

Without any doubt, 4,000 P/E cycles is a great achievement for YMTC's X3-6070 3D QLC NAND memory devices. It remains to be seen how competitive these flash memory ICs are considering the fact that they have 128 active layers, whereas YMTC's competitors offer QLC 3D NAND devices with 176 or more active layers. 

YMTC currently uses its X3-6070 3D QLC NAND memory for its PC41Q consumer-grade solid-state drive. This SSD boasts a sequential read/write speed of 5500 MB/s and a data retention period of one year at 30 degrees Celsius, which is on par with TLC solid-state drives. With endurance of 4,000 P/E cycles, Yangtze Memory is looking forward to use 3D QLC NAND flash for enterprise-grade storage devices.

Reports about Samsung prepping a high-capacity SSD subscription storage service made quite a splash earlier this week. Samsung showcased its PBSSD as a Service solution at Nvidia-hosted GPU Technology Conference (GTC 2024) and we were able to check it out and learn more about the service. indeed we are talking about a solution potentially enabling petabytes of all-flash storage. But at the same time, this is not quite what we expected based on the report. 

Despite the name, PBSSD is not a petabyte-scale solid-state drive (Samsung's highest-capacity drive can store circa 240 TB), but rather a 'petascale' storage system that can scale-out all-flash storage capacity to petabytes. Samsung demonstrated Supermicro's all-flash storage system at GTC as an example of a 'petascale' machine. Supermicro's server is based on AMD's EPYC 9004-series processor and can accommodate 16 E3.S NVMe drives with a PCIe 5.0 x4 interface for added performance.  

Samsung has a Petascale server with 16 15.36 TB SSDs, so for now the whole 1U unit can only pack up to 245.76 TB of 3D NAND storage (which is pretty far from a petabyte), so four of such units will be needed to store a petabyte of data. In addition, Samsung also demonstrated Supermicro's H13 all-flash petascale system with CXL support that can house eight E3.S SSDs and has four front-loading E3.S CXL bays for memory expansion.

Supermicro claims its machine does not use PCIe Gen5 retimers, which are typically required for these connections. Possibly, Supermicro uses an ultra-low-loss printed circuit board for H13, which allows it to fit into PCIe specifications concerning signal loss. 

Secondly, while Samsung's PBSSD as a Service solution is meant to be a service, it is not exactly meant to compete against established storage service providers, such as AWS, Google, or Microsoft Azure. Samsung positions its PBSSD product as a solution for managed service providers (MSPs), cloud service providers, and end-users with their own datacenters or with their racks in colocated datacenters. The company will deliver hardware at a monthly fee, enabling Samsung's clients to offer affordable high-performance storage services to various companies. 

What will differentiate Samsung's PBSSD as a Service solution from other 1U all-flash-array servers is that the South Korean company promises to provide maintenance and security to end users and some colocations, though this will probably depend on where the particular hardware is installed. MSPs would probably like to manage and maintain everything themselves.  

PBSSD does not leverage Samsung's Flexible Data Placement (FDP) method designed to enhance data placement to ensure greater predictability and performance in hyperscale workloads. Without FDP, PBSSD may not be the most intresting solution for hyperscale CSPs, who might prefer to build their own servers using Samsung's drives. 

Samsung expects to deliver the first PBSSD as a Service machines in the first half of 2024. Over time, these servers will gain NVMeoF support, but the company does not disclose when it is set to be ready to ship them.

Samsung is set to announce its high-capacity SSD subscription storage service at Nvidia's GPU Technology Conference (GTC 2024), which is focused mostly on advancing artificial intelligence. Samsung will position its pay-as-you-go storage service as a solution for AI developers with growing storage needs. In addition, Samsung is also expected to announce its new 12Hi HBM3E memory that will be used by various next-generation AI and HPC GPUs at GTC, according to a report in Business Korea.

Modern business storage requirements are ever increasing and not all of these businesses can afford the upfront costs for high-capacity storage. To address such companies, Samsung is reportedly rolling out its high-capacity SSD subscription service that will enable companies to increase their storage capability when they need it without buying expensive solid-state storage systems. 

The central part of Samsung's high-capacity SSD subscription storage service will be the company's petabyte (PB)-level SSD solution, known as PBSSD. As the name implies, PBSSD can store at least one petabyte of data, or 1000TB. Samsung's highest-capacity drives to date can store 256 TB of data, so PB SSD quadruples that. Because far not every customer needs a petabyte of storage, the storage device is designed to be multi-user friendly. 

PBSSD leverage Samsung's technology known as Flexible Data Placement (FDP), which has been approved in NVMe standards. FDP is a method designed to enhance data placement, leading to greater predictability and performance in real-world hyperscale workloads.

The Samsung subscription service is designed to alleviate the financial burden on customers by eliminating the need for a large initial investment in storage infrastructure, according to Business Korea. Samsung will not only provide storage, but will naturally offer storage management, maintenance, security, and seamless upgrades. This vast storage capacity, combined with the subscription model, offers an economically viable solution for managing and expanding storage needs. 

With this new service, Samsung will be competing against established players in the cloud storage business, such as Amazon Web Services, Google, and Microsoft Azure. It remains to be seen whether the company can indeed be competitive against these companies and what benefits its service will offer. 

Japanese 3D NAND maker Kioxia has proposed a deal to its investor SK Hynix (which also happens to be its rival 3D NAND maker from South Korea), offering it to produce non-volatile memory at Kioxia's fabs in Japan, Reuters reports citing Jiji news agency. This move aims to make SK Hynix change its mind regarding Kioxia's merger plan with Western Digital. Meanwhile, it remains to be seen whether SK Hynix gets interested.

The negotiations between Kioxia and Western Digital had come to a halt last year when SK Hynix, a South Korean company, expressed opposition to forming a large 3D NAND memory chip conglomerate between the American and Japanese companies. SK Hynix had reasons to stop the merger because Kioxia and Western Digital would create a player massively larger than SK Hynix.

To overcome this obstacle and secure SK Hynix's support, Kioxia has suggested allowing SK Hynix to use its Japanese 3D NAND fabs operated jointly by Kioxia and Western Digital for chip production. This strategic offer is intended to pave the way for the merger's approval, ultimately creating a large player in the global 3D NAND memory chip market.

With some extra capacity from Kioxia, SK Hynix could significantly boost its 3D NAND memory output without investing in expanding its fabs or building new ones, which seems like an attractive deal in general. Meanwhile, the financial terms of such a deal are entirely unknown.

The combined company between Kioxia and Western Digital would control roughly one-third (31.4%) of the global 3D NAND market by revenue, according to Q3 2023 market shares tracked by TrendForce. This is significantly higher than SK Hynix's share of 20.2% and is comparable to Samsung's share of 31.4%. Meanwhile, even if part of Kioxia's (or instead the merged entity's) production capacity goes to SK Hynix, the new company will likely be larger than the South Korean memory giant, which is why the latter may still consider it a significant threat.

It should be noted that neither Kioxia nor SK Hynix have confirmed talks about capacity, so the information should be taken with a grain of salt.

Japan's industry ministry announced that it will be adding more subsidies for Kioxia and Western Digital, promising 242.9 billion yen (US$ 1.64 billion) to build two state-of-the-art facilities to mass produce NAND memory chips and fulfil the needs for AI and data center applications. This includes 92.9 billion in subsidies previously approved in 2022, so there's an additional 150 billion yen overall.

Once construction is completed in the Mie and Iwate prefecture, the facilities will make 218-layer 3D NAND chips for the respective markets. The ministry believes that with this investment, it would reclaim its reputation as a major chip manufacturing hub.

This will also enable the country to secure chip supply as trade relations between China and the United States remain tense. Industry Minister Ken Saito told Reuters, "The more data is used, the more memory consumption will increase so in that sense global demand will surely grow in accordance with NAND's characteristics." He also stated, "Japan and the US will work together to fulfil the responsibility of supplying memory products needed by the world."

Western Digital and Kioxia were planning to merge a few months ago, but SK Hynix objected a few days after the announcement as the proposal would undervalue its investment, leading to the merger plans being cancelled the next day. Regardless, Japan has had its own goals in place with these companies since 2022, so it increased the subsidies to help overcome the downturn in the NAND market that occurred last year.

A gold rush in the NAND market?

The need for higher-performing and higher-capacity memory has always created a certain demand from the worldwide market, but with the ever-growing use of generative AI and data centers around the world, the demands must be met. Japan also believes that it will generate 9,000 jobs in the region as a result of this investment.

It's common for countries to subsidize and invest in manufacturing facilities for leading companies. Through these plants, shipments are expected to begin in September 2025, though experts believe it could take longer.

The United States has also been doing the same with Intel, Samsung, and SK Hynix. Under the CHIPS Act, Samsung and SK Hynix can only operate their existing facilities in China, while newer facilities will be made in the United States. Intel and TSMC are also getting subsidies from the United States for near-future plants. The U.S will also be a major hub for GPU packaging, as Nvidia will also be using Intel's foundry for GPU packaging production.

Japan, the U.S., and other countries are all aiming to boost chip manufacturing facilities in their respective regions, aiming to dramatically decrease dependency on plants located in China. But even with sanctions, China is making its plans to secure its future in generative AI applications for multiple fields, though Intel CEO Gelsinger claims China will remain ten years behind for the foreseeable future.

China's champion 3D NAND producer Yangtze Memory was recently accused by the Pentagon of being a 'military company', potentially posing risks to U.S. national security. In a strongly worded statement passed to Reuters, YMTC said that it does not supply its memory for military use.

"We have not supplied, or been directed by any entity, to supply our technology for military use," a statement by YMTC published by Reuters reads.  

YMTC is among the global 3D NAND technology leaders with its unique Xtacking technology that enables it to offer 3D NAND with range-topping speed data transfer speeds (potentially to enable the best SSDs with a PCIe 5.0 x4 interface). Therefore it is certainly not in YMTC's interests to upset the U.S. government by supplying memory to the People's Republic's Liberation Army. 

Meanwhile, being blacklisted by the U.S. Department of Commerce, and not exactly welcome by customers in Europe or the U.S., YMTC must be prepared to sell its 3D NAND memory exclusively to buyers in China. Some of those buyers are makers of SSDs, PCs, and smartphones and this is where Yangtze Memory can at least partly control the destiny of its 3D NAND devices.  

But YMTC produces loads of memory, so it has to sell an 'unused' volume to distributors back in China, which is where the company loses control over the final use of its memory chips. That said, calling YMTC directly responsible for where its memory devices end up may be a little bit of an over-reach. Meanwhile, YMTC owner Tsinghua Unigroup is a partially state-owned company, which is certainly a concern for the U.S. Ministry of Defence.

Recently, the Pentagon added YMTC to its list of concerns due to its possible links to the Chinese military. This list seeks to pinpoint companies that could jeopardize U.S. national security by aiding Beijing's military-industrial efforts.

While being on this list does not stop YMTC from operating in the U.S., it does block the company from getting contracts with the Defense Department. Moreover, this designation might prompt tougher actions such as being blacklisted by the U.S. Treasury Department, which would negatively impact their business activities in America. Yet again, YMTC hardly has any significant business activities in the U.S.  

Nonetheless, the inclusion into the list makes the life of the company harder, which is why it decided to make a statement claiming that it is not linked to the People's Republic's military activities.

The Pentagon recently designated over a dozen Chinese technology firms, including 3D NAND maker Yangtze Memory Technologies Corp. (YMTC), as 'military companies' that pose national security risks to the United States. The inclusion into the list does not cause any immediate effect, but it bans the U.S. military from buying devices featuring YTMC's chips, and it bars the companies from buying advanced chipmaking equipment based on U.S. intellectual property. Meanwhile, the Pentagon also excluded SMIC Hong Kong International Co Ltd from the list.

YMTC is among dozens of China-based companies included in the so-called 1260H list that highlights companies with alleged ties to the Chinese military and potentially supporting Beijing's military-industrial complex. YMTC is named to be a 'military company along with artificial intelligence (AI) firms Yitu Technology and Beijing Megvii, drone manufacturers Chengdu JOUAV and DJI Technology, lidar producer Hesai Technology, and tech company NetPosa. All of them have operations in the U.S.

Pentagon's 1260H list, established under the National Defense Authorization Act for 2021 and updated annually, serves as a mechanism for the Defense Department to flag companies that could threaten U.S. national security by allegedly supporting Beijing's military activities. The inclusion on the list does not entail a ban on operations within the U.S. but renders participants ineligible for Defense Department contracts. Moreover, being named can lead to further actions like blacklisting by the U.S. Treasury Department, which would significantly curtail their business prospects in the United States. 

An interesting thing about the current edition of the list is that the Pentagon excluded SMIC Hong Kong International Co. Ltd. from the list, citing that this unit does not belong to Semiconductor Manufacturing International Corp., China's largest foundry. Now, SMIC itself calls its Hong Kong unit a 'representative office.' That office naturally does not produce chips or is involved in any activities in mainland China. However, it is unclear whether the exclusion from the 1260H list opens SMIC doors to win contracts with the Pentagon.

SMIC and YMTC are on the U.S. Department of Commerce Bureau of Industry and Security's Entity List, and they cannot access advanced technologies developed in the USA, including wafer fab equipment. This is obviously a bigger concern for both companies than their ability to bid for U.S. government contracts.

Plextor is one of the legendary names in client PC storage and has been associated with high quality and performance for nearly three decades. But it looks like Kioxia thinks differently, as it has decided to shut down the Plextor brand for SSDs and use the Solid State Storage Technology (SSSTC) trademark instead, according to a report by HKEPC. SSSTC will focus solely on drives for enterprise, datacenter, and industrial applications.

The GoPlextor.com website has already been shutdown, and Plextor.com leads to SSSTC.com — which only lists products for enterprise, datacenter, and industrial applications and no longer lists consumer SSDs. 

SSSTC is a wholly owned subsidiary of Kioxia, which makes 3D NAND memory and various NAND flash-based products, including SSDs and memory cards. Kioxia obtained SSSTC from Lite-On, which decided to get rid of its solid-state storage business in 2019. It sold this unit for $165 million to Toshiba Memory, which was renamed Kioxia later that year. Plextor used to make some of the best SSDs. 

The main values of Lite-On's SSD unit were its capable R&D team, the brand's reputation for reliability and high performance among PC enthusiasts, and its well-established business relations with channel and OEM clients. 

Meanwhile, success of Plextor's SSDs was largely driven by the success of Marvell's SSD controllers and Plextor's ability to design competitive firmware. But Marvell was late to market with PCIe Gen4 and PCIe Gen5 controllers as its developers fled to InnoGrit. Unlike its rivals, Plextor never adopted Phison's platforms, but started relying on controllers from InnoGrit, Marvell, and Silicon Motion, which meant that the company had to disperse its resources and design three different branches of firmware — not a particularly good way of using limited resources. As a consequence, the value of the Plextor brand dropped among enthusiasts, and Kioxia has decided to kill it off instead of reviving it. 

In fact, from now on, Kioxia's SSSTC will no longer offer client SSDs at all, and will instead focus on enterprise, datacenter, and industrial drives. Kioxia itself will, of course, continue to provide SSDs for client applications, but the company is somewhat behind its rivals: it still does not have a single drive with a PCIe 5.0 interface, while many of its rivals have already launched two generations. 

SSSTC will continue to offer RMA services to current owners of Plextor drives, but don't expect new Plextor-branded products to emerge in the future. Something similar happened to the OCZ brand, which was also abandoned by Toshiba (the ancestor of Kioxia) in favor of its own brand SSDs. 

Plextor will be missed since the brand has been known for its excellent optical disk drivers and SSDs for over 30 years.

Guangdong province in China has set up a new ¥11 billion ($1.5 billion) fund to boost its semiconductor industry, continuing China's regional chip fund trend. Shanghai started its chip fund back in 2016, and now has ¥28.5 billion ($4.02 billion) in it. These local efforts across China show how serious the country is about building a self-reliant chip industry — and they are all in line with the goals set by the federal government, according to a report by the South Central Morning Post. 

The new fund is called the Guangdong Semiconductor and Integrated Circuit Industry Equity Investment Fund Phase II. It follows the first phase, which launched in December 2020 and put ¥10 billion ($1.41 billion) into various chip projects in Guangdong. Both funds are designed to fund local semiconductor initiatives, although authorities of the region do not list projects that the funds have financed.

Money for the Guangdong fund comes mainly from the Guangdong government's Guangdong Yuecai Holdings, which owns over 90% of the fund. There's also cash coming in from Dongguan and Zhongshan, two cities that each have a 4.5% share. 

Guangdong's chip fund is a local version of something bigger: the China National Integrated Circuit Industry Investment Fund (the "Big Fund"). The Big Fund has been around since 2014 and has pumped loads of money into China's chip industry — despite some issues with corruption. It started with more than ¥138 billion ($19.462 billion), and grew even bigger in 2019 with over ¥200 billion ($28.2 billion) in its second phase. 

One of the peculiarities of Chinese funding of semiconductor projects is that the cash comes from multiple sources, including the Big Fund, local governments, and banks — some of which are government controlled. SMIC, China's foundry champion, for example, does not own many of the fabs that it operates. 

On one hand, such an approach greatly simplifies establishing new semiconductor fabrication facilities and ensures that companies such as SMIC are producing chips needed by local companies. On the other hand, this does alter SMIC's business model, which differs substantially from other foundries as the company does not have to follow typical CapEx depreciation schedules.

Kingston, the world's No. 1 supplier of retail memory modules and storage devices, has formed a joint venture with Longsys Electronics to operate in China. The move will combine the strengths of Kingston and Longsys, and lower risks for the former. In addition, the partnership will better address the Chinese retail memory market and avoid any potential problems caused by the U.S.-China tensions. 

Under the terms of the deal, Kingston will hold a 49% stake in the joint venture, whereas Longsys will own the majority with a 51% stake. The joint venture will function as an independent entity with full corporate governance and management capabilities. Its focus will be on offering 'diverse and high-end embedded storage solutions' to customers in mainland China. The joint venture will handle its own product planning, R&D management, supply chain management, and sales. Meanwhile, Longsys will conduct R&D and technical support, whereas Kingston will be responsible for core resource procurement and branding.

By forming a joint venture with a Chinese company, Kingston opens its doors to work with virtually any entity in China that needs embedded storage. Given how keen the U.S. government is to place China-based companies in its Entity List, Kingston saves time and effort by not directly working with certain China-based customers and partnering with a local company to handle these clients. 

Kingston is the world's No. 1 supplier of branded memory modules and solid-state drives. Its lineup also has plenty of embedded storage and memory products, though it is hard to say how successful the company is in this territory.

This joint venture is a response to the ongoing political and business tensions between the U.S. and China. DigiTimes says this represents a bigger trend where American tech companies are teaming up with local firms to stay strong in China. This partnership could also be great news for the supply chain, with companies like Phison Electronic, which works with Longsys, likely to benefit from the deal.

Changxin Memory Technologies (CXMT), a major DRAM manufacturer in China, has decided to hold off on its planned IPO due to volatile market conditions — to some degree the same uncertainties surrounding Chinese chip manufacturing in general. Instead, the company is looking to raise money from investors aiming for a valuation of about ¥140 billion ($19.5 billion), reports Bloomberg.

The company had its eyes set on launching its IPO on the Shanghai STAR board in 2023 and even rearranged its shareholder structure to get ready. But after talking it over with regulators and potential investors, Changxin is choosing to play it safe and wait for a better time. The company is now exploring other ways to fund its growth, as it's adopting new memory technologies and needs to deploy new fabrication tools.

Changxin isn't just any chip manufacturer, it's China's largest domestic DRAM manufacturer and can be considered a key part of China's ambition to achieve technology self-sufficiency. For now, CXMT is significantly behind industry heavyweights like Micron, Samsung, and SK Hynix in terms of process technologies (down to 17nm) and manufacturing capacity. But CXMT certainly wants to catch up and sees this funding round as a stepping stone to more advanced tech in the future.

Changxin's decision to delay its IPO is influenced by both internal and external factors. While investor interest in the company is still being assessed, there's a general increase in Chinese investor confidence in local technology firms, particularly those aligned with the Chinese government's ambitions to develop a self-reliant tech industry. However, challenges persist, such as U.S. sanctions on Yangtze Memory Technologies Co. (YMTC), which affects the broader semiconductor industry in China.

This hold-up with the IPO is not just a Changxin decision, as many other companies are thinking twice about going public right now, reports Bloomberg. Another example is the Swiss company Syngenta, which pushed back its massive $9 billion IPO in Shanghai to the end of 2024.