TSMC this week posted financial results for the first quarter of 2026 and lifted its 2026 revenue guidance and capital expenditures to the high end of its original expectations. Accelerating sales of AI accelerators and accompanying hardware increases demand for TSMC's wafers, which is why the company said it would build another 3nm-capable fab in addition to those already planned. But while the company is confident in its long-term prosperity driven by the AI megatrend, it warned about profitability due to the war in the Middle East.

AI megatrend earns TSMC tens of billions in one quarter

"Our conviction in the multiyear AI megatrend remains high, and we believe the demand for semiconductors will continue to be very fundamental," said C.C. Wei, chief executive of TSMC, during the company's earnings conference. He admitted that capacity during the quarter was 'tight,' whereas Jen-Chau Huang, TSMC's chief financial officer, confirmed 'higher-than-expected' overall capacity utilization.

Indeed, the HPC segment (an ambiguous term that TSMC uses to describe everything from client PCs to high-end AI accelerators) accounted for 61% of TSMC's revenue in Q1 2026 (or approximately $21.9 billion), up from 46% in Q1 2024 (approximately $8.68 billion), which represents colossal growth in just two years. The smartphone segment accounted for 26% of TSMC's earnings in Q1 2026, whereas IoT and automotive commanded 6% and 4% of the company's revenue in the same quarter.

Based on TSMC's annual report released this week, it looks like Nvidia, with its aggressive capacity booking strategy, has become TSMC's top customer, accounting for 19% of the foundry's revenue for 2025, dethroning Apple, which was responsible for 17% of TSMC's earnings for 2025.

On the fabrication technologies side of matters, TSMC's 5nm-class nodes accounted for 36% of the company's wafer revenue in Q1 2026 (driven by the success of Nvidia's Blackwell AI accelerators), 3nm-class processes were responsible for 25% of the foundry's earnings, while 7nm-class technologies represented 7% of TSMC's revenue. In general, advanced nodes (7nm and below) accounted for 74% of the company's earnings. Yet, keep in mind that while TSMC is mass producing 2nm-class (N2) chips for its customers, it has not formally shipped them to clients and therefore does not recognize 2nm-related revenue.

Capacity additions

As Nvidia's leading AI platforms, as well as offerings from other vendors, are set to shift from TSMC's 5nm-class family of nodes (N5, N4) to 3nm-class lineup of process technologies (N3), demand for the latter is going to skyrocket this year and remain strong for years to come. To meet this demand, TSMC will add three N3-capable fabs to its lineup over the next couple of years.

"Historically, we do not add additional capacity to a node once it has reached its target capacity," Wei said. "However, as a foundry, our first responsibility is to provide our customers with the most advanced technologies and necessary capacity to unleash their innovations. Based on our assessment, to meet the strong demand for AI applications, we are stepping up our CapEx investment to increase our N3 capacity."

First up, the company will add a new N3-capable fab module to its Gigafab cluster at Tainan Science Park, aiming to start volume production in the first half of 2027. While TSMC has been building the fab module for some time, this is the first time it has disclosed its capabilities.

Secondly, TSMC's N3-capable Fab 21 phase 2 in Arizona is on track to come online in the second half of 2027. This is the first time the foundry has clarified when Fab 21 phase 2 is set to begin making chips. TSMC's CEO also confirmed that the company had acquired the second plot of land near Fab 21 to build additional fab modules, though he never confirmed how many fab modules would be built.

Thirdly, the company plans to upgrade the capabilities of its Fab 23 phase 2 (aka JASM phase 2) to 3nm by installing more advanced equipment. Originally, Fab 23 phase 2 was projected to make chips on N6 (6nm-class) and N7 (7nm-class) fabrication technologies, then TSMC pondered upgrading it to N4 (4nm-class). Now, the plan is to make it N3-capable when it comes online in 2028.

The decision to add 3nm capacity was not made overnight, though it looks like TSMC expects demand for FinFET-based N3 — its final FinFET node — to remain strong well into the second half of the decade (it takes a year to ramp up a fab, so these three fabs will contribute meaningfully to TSMC's capacity in 2028 - 2029). Separately, the company will continue converting N5-capable facilities into N3-capable fabs in Taiwan and make some of its fabs capable of building chips on N7, N5, and N3 nodes.

"In addition to all the new fabs, we continue to convert 5nm tools to support 3nm capacity in Taiwan," Wei added. "We are also leveraging our manufacturing excellence to drive greater productivity across our fab in all locations to generate more wafer output. We are also focusing on capacity optimization across nodes, including flexible capacity support among N7, N5, and N3 nodes."

One of the main challenges for TSMC's expansion is to get fab tools to support new capacity as fast as possible, but this is not easy, as leading suppliers of semiconductor production equipment are also constrained in terms of capacity.

"We try very hard to speed it up and pull in all the equipment as we can, [but] our supply is very tight," Wei said. "Demand is continuing to increase, so we continue to work with our suppliers to speed it up."

As far as TSMC's N2 and A16-capable capacity is concerned, the company is currently ramping Fab 20 in Hsinchu Science Park and Fab 22 in Kaohsiung Science Park. While the capacity of the former will remain largely intact in the coming years, Fab 22 will gain capacity aggressively over time, according to Global Semi Research, though TSMC did not touch upon N2 capacity expansion during the earnings call.

Another record quarter, but there may be hiccups

TSMC's first quarter revenue reached $35.9 billion, an increase of 40.6% year-over-year, and a 6.4% rise over the previous quarter. The company's net income totaled $18.2 billion, which is the company's highest net profit for a quarter, while its gross margin was 66.2%. TSMC expects its Q2 2026 revenue to be between $39 billion and $40.2 billion, which is a 32% year-over-year growth.

"Our business in the first quarter was supported by strong demand for our leading-edge process technologies," said Wendell Huang, Senior VP and Chief Financial Officer of TSMC. "Moving into second quarter 2026, we expect our business to be supported by continued strong demand for our leading-edge process technologies."

In addition, the company indicated that for the full year 2026, it expects revenue to increase to over 30% (up from its original expectations of around 30%) over the previous year to approximately $158 billion, which gives it an opportunity to increase its CapEx budget towards the high-end of its guidance between $52 billion and $56 billion.

Meanwhile, TSMC warned that its costs may increase due to the ongoing war in the Middle East.

"In addition, given the recent situation in the Middle East, prices for certain chemicals and gases are likely to increase," said Huang. "Based on our current assessment, there may be impact to our profitability, but it is too early to quantify the impact."

This month, Amazon Web Services introduced the Graviton5, its fifth-generation custom general-purpose server processor, designed to compete against industry-standard CPUs from AMD and Intel in AWS's data centers. The new processor extends AWS's in-house Arm-based CPU program with a CPU that packs up to 192 cores and 180 MB of L3 cache, and is designed to compete with higher-end AMD EPYC and Intel Xeon processors, potentially replacing some of them in AWS data centers.

At a glance

The AWS Graviton5 processor is fabricated using a 3nm-class process, likely by TSMC. The processor integrates 192 Neoverse V3 cores alongside an assumed 180 MB L3 cache. AWS says that the new CPU will deliver 25% higher performance compared to its predecessor, which appears to be conservative, as the Graviton5 offers a twofold increase in the number of cores. The chip uses the Armv9.2 ISA that brings several microarchitecture enhancements and a fivefold increase in L3 cache size.

The new processor is now available in Amazon EC2 M9g instances in preview, while compute-optimized C9g and memory-focused R9g variants are scheduled for launch in 2026. The current EC2 M9g instances are up to 30% faster for databases, up to 35% faster for web applications, and up to 35% faster for machine learning workloads compared to M8g, according to AWS.

Diving deeper: 192 Neoverse V3 cores

Amazon Web Services is intentionally opaque about the exact specifications and internal design of its Graviton5 CPU. Nonetheless, it offers comparisons with the previous-generation Graviton4 chip, which allows us to decode some details and delve into them with a little more depth.

AWS and Arm officially confirm that Graviton5 integrates 192 Neoverse V3 cores per package, fabricated using a 3nm-class process, making it the densest CPU in the Graviton lineup and the densest Armv9.2 processor available to date. The internal layout of the processor has been redesigned to reduce communication overhead, and AWS claims up to 33% lower inter-core latency, which is particularly noteworthy given the twofold increase in core count.

When we discuss Neoverse V3, we cannot help but think about the Arm-developed compute subsystems (CSS). While Arm confirmed that we are dealing with Neoverse V3, neither Amazon nor Arm has confirmed that Graviton5 uses Arm-developed CSS. That means we're likely dealing with a unique design in Graviton 5.

In performance comparisons between the Neoverse V3 core and its predecessor, Arm claims a 9%-16% uplift over Neoverse V2 across general cloud workloads and up to 84% in AI data analytics. This is one of the reasons why AWS is so conservative about performance upticks, both for Graviton5 as well as compute-intensive M9g instances in general. Another reason for AWS's conservative performance estimate is that it does not sell leading-edge performance like AMD or Nvidia, but rather predictable performance per dollar and scalability in the cloud. Nonetheless, with a 192-core processor, AWS puts itself into the highest league among CPU developers.

L3 cache replaces system-level cache

One interesting thing to note about Graviton5 is that it comes with L3 cache, not system-level cache like Graviton4. While L3 and SLC in data center CPUs have a lot in common, they are not the same thing. Traditionally, L3 cache is a last-level cache located inside each compute tile or core cluster in a data center CPU. L3 primarily serves CPU workloads by reducing DRAM access; it is optimized for low latency and directly participates in the core's coherence protocol. Therefore, L3 is tightly coupled to the cores and is physically close to them.

By contrast, SLC sits outside the core clusters on the SoC fabric and is shared by all CPU cores, various other accelerators, I/O devices, NICs, and DMA engines. It tends to be much larger (often 100–300+ MB) and optimized for throughput rather than latency, as it acts as a global buffer that reduces pressure on DRAM and provides coherent access for heterogeneous compute blocks. SLC can improve scaling for very high core counts and enables unified memory semantics across CPUs, GPUs, and on-die accelerators, a role traditional L3 caches cannot fulfill on their own.

Amazon has not publicly explained the design decision, but based on Graviton4’s architecture and what we know about Graviton5, the reason is almost certainly architectural scalability. The move from SLC in Graviton4 to a large 180 MB L3 in Graviton5 is not cosmetic; it reflects fundamental changes in how a 192-core processor moves data, manages latency, and maintains coherence.

Graviton4's architecture — 96 Neoverse V2 cores, a CMN-700 mesh, 12 DDR5-5600 channels — operates efficiently with a centralized or semi-centralized SLC. But doubling the core count to 192 dramatically increases mesh traffic, hop distances, and contention on any unified cache structure. At this scale, a monolithic SLC could almost certainly become a latency bottleneck and would not support AWS’s claim of up to 33% lower inter-core communication latency. A distributed L3 sliced across the die allows hot data to remain physically close to compute clusters, reducing average access latency and improving overall coherence behavior.

The fivefold cache expansion AWS advertises reinforces this architectural necessity. Scaling Graviton4's 36 MB SLC by that factor yields 180 MB, and AWS's additional statement —2.6X more cache per core, at double the core count — implies ~187 MB total, which aligns with a large, multi-slice L3 rather than a single SLC block, which would create routing complexity.

Finally, L3-based designs offer stronger multi-tenant performance predictability, which is crucial for AWS. Under cloud workloads, shared caches experience heavy cross-tenant interference and variable latency, so when designing cache subsystems, developers must take into account AWS's use case. To sum things up, the shift to a distributed L3 was a necessary architectural evolution for Graviton5.

New memory subsystem, I/O, and security features

Just as AWS didn't disclose many details about other design aspects of Graviton5, it also didn't disclose much about the memory subsystem of the CPU. It goes without saying that Graviton5's memory subsystem is more powerful than that of Graviton4, as it supports higher memory speeds, which likely means that it at least retains a 12-channel memory subsystem of the Graviton4, but with higher data transfer rates (i.e., higher than DDR5-5600).

A 12-channel DDR5 design operating at 6400 MT/s would provide around 614 GB/s of aggregate bandwidth, which translates to approximately 3.2 GB/s per core, which is actually lower than 5.6 GB/s per core in the case of Graviton4. However, the larger L3 cache could compensate for this decrease in memory bandwidth. Then again, we do not know the exact number of memory channels supported by Graviton5.

Input/output throughput is similarly increased, according to AWS: network bandwidth is up by 15% on average across instance sizes, with as much as double the throughput for the largest configurations. Storage bandwidth through Amazon EBS rises by around 20% on average, according to AWS. These gains are designed to improve performance not only for compute-heavy applications, but also for distributed systems that depend on fast storage and networking.

On the security side, Graviton5 is built on the AWS Nitro System, with sixth-generation Nitro Cards that handle virtualization, networking, and storage. AWS has also introduced a new component called the Nitro Isolation Engine, which the company describes as a formally verified isolation layer. Instead of relying solely on conventional security validation, the Isolation Engine uses mathematical proofs to demonstrate that workloads are separated from each other and from AWS operators. The architecture enforces a zero-operator-access model, and AWS plans to allow customers to review the implementation and the formal proofs behind it to ensure maximum security. Such security measures could be a part of the company's effort to attract clients who have traditionally used on-prem servers.

Wrapping it up

AWS's new Graviton5 processor offers a 192-core, 3nm Arm-based CPU with around 180 MB of L3 cache. This positions the cloud giant as a competitor to the high-end AMD EPYC and Intel Xeon solutions for data centers. The CPU integrates Neoverse V3 cores and delivers an advertised 25% performance uplift, which is conservative given the twofold increase in core count, large microarchitectural improvements in the Armv9.2 ISA, and a fivefold increase in cache capacity. Also, AWS confirms 33% lower inter-core latency due to a redesigned internal layout but has not disclosed whether it uses Arm's CSS, suggesting that Graviton5 may be a unique Annapurna Labs design built around Neoverse V3 cores.

A key architectural shift is replacing Graviton4's SLC with a large distributed L3 to enable better coherence scaling across 192 cores and predictable latency. The processor also gains a faster memory subsystem (likely retaining 12 channels at higher DDR5 speeds), improved network and storage bandwidth, and the new Nitro Isolation Engine, which uses formal verification to guarantee tenant isolation and enforce zero-operator access.

At present, Graviton5 powers new EC2 M9g instances — up to 30% – 35% faster for databases, web services, and machine learning — and compute-optimized C9g and memory-optimized R9g variants will follow in 2026.

TSMC intends to raise prices on wafers produced using its advanced process technologies by 5% to 10% starting in 2026, according toa report by DigiTimes. The new pricing strategy reportedly is said to reflect the company's increased capital expenditures (CapEx) — driven by expansion of advanced manufacturing capacities in the U.S. and Taiwan — amid the intention to keep its margin targets on track. We performed the basic math and found that a price increase would significantly improve the company's CapEx position; however, we await further clarification from TSMC regarding the reported price hikes.

An up to 10% price hike next year

The new pricing model will purportedly apply to the N5, N4, and N3-series (5nm, 4nm, and 3nm-class) process technologies, but adjustments will differ depending on the application segment and the customer's purchasing behavior. Smartphone processors are expected to see a 5% increase, production quotes on CPUs are projected to rise by 7%, whereas large processors for AI and HPC applications will see a 10% increase.

Customers who order both legacy and cutting-edge nodes may be eligible for special pricing benefits in a bid to encourage the use of TSMC's technology portfolio, deepen client engagement across multiple product categories, and ensure that the foundry's outdated fabs remain fully utilized. However, customers focusing only on the latest nodes would bear the full extent of the increase.

It is noteworthy that, at present, chip production at TSMC's Fab 21 in Arizona already comes at a roughly 15% premium compared to the company's fabs in Taiwan. Despite this, the upcoming 2026 price adjustments are said to be implemented uniformly across all geographical sites, with no location-specific exceptions, so a hypothetical N5/N4-based chip made in Taiwan this year will be 25% more expensive once produced in the U.S. next year. Hence, it will still be cheaper to make silicon in Taiwan.

Lisa Su, the chief executive of AMD, recently confirmed that the cost of producing chips in the U.S. is between 5% and 20% higher compared to Taiwan. However, AMD has accepted these higher costs, which indicates that TSMC has successfully passed on extra expenses from U.S. fabs to its customers, softening some of the company's own margin pressures.

$9 billion extra revenue?

TSMC's official numbers reveal that N5/N4 and N3 process technologies accounted for around 50% of the company's wafer processing revenue in the second quarter of 2025. TSMC's HPC segment — which includes everything from game consoles to client PCs, and from graphics processors for gaming to GPUs for AI and HPC applications — accounted for 60% of its earnings, whereas SoCs for smartphones accounted for 27% of the company's $30.07 billion revenue in Q2 2025.

Given that the vast majority of smartphones and AI/HPC processors tend to transit to more advanced nodes from TSMC's N7/N6 fabrication technologies, it appears that TSMC plans to increase quotes on the vast majority (circa 87%) of products that it produces by 5% to 10% next year. Assuming that the average increase will be around 7.5% for N3 and N4/N5, the company will get an 'extra' $9 billion provided that TSMC's N3 and N4/N5 absolute revenues will remain at current levels. Since Apple will be ramping up production of chips on TSMC's N2 (which is more expensive than N3), TSMC's revenue is expected to increase; however, it remains to be seen whether the company's N3 revenue will remain at current levels.

Keep in mind that N2/N2P/A16-capable fabs are more expensive than N3-capable fabs, so TSMC is spending more on its next-generation fabs than it did on its current-generation production facilities. In addition, the foundry must spend more on its N2-capable capacity as the technology is more popular among chip designers than N3 and N5 were at the same stage of development.

Also, given the company's commitment to build additional fabs in Arizona, an advanced packaging facility nearby, and an R&D center in the U.S. on top of leading-edge fabs in Taiwan in the coming years, the company might need to increase its CapEx for 2026, 2027, and 2028 beyond $42 billion, which is why a portfolio-wide price increase makes sense for the company.

$9 billion in extra earnings driven by increased prices will not buy TSMC a new N2-capable fab, but it represents 21% - 23% of the company's CapEx for 2025, which is expected to be between $38 billion and $42 billion. Therefore, $9 billion would be very instrumental to TSMC in terms of maintaining its margin and/or increasing its CapEx.

Are customers ready to pay more?

TSMC's customers seem to be ready for such price hikes, at least judging by comments from AMD and Nvidia's CEOs. TSMC's 3nm and 4nm/5nm-class technologies do not have any competition from Intel Foundry and have limited competition from Samsung Foundry.

With 2nm-class nodes, TSMC will feel even more comfortable for at least a couple of years. TSMC's 2nm-class technology provides significant performance, power, and area improvements compared to N3E and N3P, so the company's customers are expected to be willing to pay extra for it. This is why the foundry is rumored to be planning to charge $30,000 per N2 wafer and $45,000 per A16 wafer. Since there are multiple companies taping out N2/N2P chips now and planning to mass produce them in 2026 – 2027, they will have no choice but to purchase those wafers at TSMC.

Last but not least, keep in mind that TSMC will not have any rivals with its 2nm-class fabrication technologies for quite a while. Intel's 18A — even though it features gate-all-around transistors and backside power delivery, unlike N2/N2P that only rely on GAA transistors — is still not even qualified for mass production by third parties at Arizona fabs. Furthermore, it does not appear that there is significant interest in 18A outside of Intel.

Hence, at least before 18A-P or even 14A becomes available to Intel Foundry customers, TSMC's N2/N2P/A16 will be unrivalled, at least in terms of high-volume production. To that end, TSMC will reportedly rapidly expand N2/N2P/A16-capable capacity from less than 20,000 wafer starts per month in Taiwan in late 2025 all the way to 200,000 WSPM at multiple fabs in Taiwan and one in the U.S. by 2028.

TSMC needs tens of billions of dollars to fuel such massive leading-edge production capacity, and price hikes are among the ways to get them. We've reached out to TSMC for further clarification and await a response.

We had the opportunity to interview TSMC's Kevin Zhang, the deputy co-COO and SVP at TSMC, to discuss the latest trends in the semiconductor industry and how they impact TSMC's strategy moving forward.

Since its founding in the 1980s, TSMC's business strategy has been to meticulously fulfill the needs of its customers, transforming itself in accordance with the ever-evolving semiconductor landscape. In the coming years, the needs of the company's clients will become so diverse that it will offer different leading-edge production capabilities for segment-specific needs, marking a major milestone in its 'Everyone's Foundry' ideology.

Everyone's Foundry

Historically, processors for PCs were the driving force behind the industry's transition to next-generation chip manufacturing technologies. Then the smartphone revolution changed the rules of the game, and mobile SoCs became the alpha users of TSMC's (and the industry's) leading-edge fabrication processes.

The rise of AI once again changes everything, as data center-grade processors are about to become key adopters of TSMC's leading-edge nodes. However, as consumer devices still demand more performance and functionality every year, they also require a new process technology every year. As a result, TSMC has reached a point where it must offer different leading-edge technologies to meet highly distinctive needs. This is in addition to offering advanced packaging technologies for client and AI/HPC applications.

These are some of the things we have learned from our interview with Kevin Zhang, Senior Vice President and co-COO, who is responsible for TSMC's technology roadmap, business strategy, and key customer engagement.

The road ahead

As users' needs change, semiconductor technologies follow. In the coming years, the industry will require three distinct offerings from contract chipmakers in general, and TSMC in particular.

The trend is moving in three directions:

• Maximum transistor density and performance efficiency.
• Maximum performance efficiency with the best possible power supply at reasonable costs.
• Multi-chiplet packaging solutions for data centers.

To address these distinct demands, TSMC is aligning its technology roadmap around three complementary directions: advanced transistor scaling, optimized power delivery, and leadership in multi-die system integration.

For products that require maximum performance efficiency, such as smartphones and PCs, TSMC will offer its N3P, N2, N2P, and A14 process technologies. These nodes are optimized for strong performance-per-watt without the complexity and cost of backside power delivery, enabling efficient scaling for mobile and consumer SoCs where area efficiency and battery life are critical.

For data center processors that consume a kilowatt or more of power, TSMC intends to offer A16 with Super Power Rail Backside Power Delivery Network (BSPDN) in late 2026, followed by A14 with SPR in 2029.

Also, to meet the growing need for multi-chiplet packaging solutions for data center-grade AI infrastructure, TSMC has expanded its advanced packaging portfolio, which includes silicon photonics, and embedded power components, into cohesive, high-bandwidth, energy-efficient systems.

Moore's law is (not) dead

Anton Shilov:  Let's start with a rehashing of a traditional question that you hear quite often these days, and this concerns Moore's Law and whether it is alive or dead. With the transition from N5 to N3, we saw mixed chip density increased by around 30%. With the transition from N3 to N2, we can expect a 15% increase in transistor density. For A16, the expected increase is between 7% and 10% (the key feature of A16 is backside power delivery, rather than reworked transistors). Will we continue to witness diminishing returns when it comes to scaling (of transistor density) with every new node going forward, or will there be breakthroughs?

Kevin Zhang: If you look at the 5nm to 3nm to 2nm, and now to A14. The trend right now, we see power efficiency [improvements] of about 30% per generation. This is a kind of trend. We are seeing we are able to continue to drive transistor density aggressively in a ballpark with 20% per generation. So, performance [gains], we are talking about 15%. So those are the numbers I think are consistent with past generations. Going forward, beyond A14, I can say based on what we see, we have loads of innovations [incoming], so we can leverage that trend to continue beyond A14.

Anton Shilov: Now that you mentioned A14, you mentioned that it provides full node scaling benefits due to some technological breakthroughs, and you also mentioned the 2nd-Generation GAA nanosheet transistors. Does this mean that the breakthrough involves things like new materials, or something like this?

Kevin Zhang: I do not want to get into a specific innovation scheme at this point. Our technology team may publish a paper down the road at IEDM, I will let them to talk about. I have to tell you [changes from N2/A16] are quite substantial. From what we see today, we have full confidence to deliver A14 into high volume production in 2028 with substantial geometry scaling. So, I think it will really allow customers to harvest the intrinsic technology scaling benefits.

Every application needs its own node

Anton Shilov: When you announced A16, you said that backside power delivery was especially beneficial for AI HPC designs. In one of your interviews, you noted that smartphone SoCs can continue using process technologies without backside power delivery. Will your customers continue to be able to use next-gen nodes like A14 and A12 without a backside power delivery network (BSPDN)?

Kevin Zhang: I think we see some bifurcation for mobile applications, for example, where the power consumption is not that significant, compared to high-performance computing (HPC) [processors that] consume like a thousand or multiple thousand watts per die, per chip, or per package. We think mobile application customers continue to want to have a front side power delivery that is sufficient to achieve power, performance, and cost benefits. So, that's why you see we have N2 technology, we have A14, which does not have backside power delivery or Super Power Rail (SPR).

But as I mentioned earlier, a year after A14, we will have a version of [this] technology with the Super Power Rail [for] HPC applications. Your observation is correct, we are going to provide both technology tracks to allow different product segments to achieve their own optimization point.

Anton Shilov: Does it mean that going forward, your process technologies will get more tailored for a particular application?

Kevin Zhang: I think you can put in that way: our technology platform [will be] tailored for different applications. This is already happening today. You see mobile, we have a different optimization point. This is happening at the whole level as a design class level.

You see the transistor library, for example. We have different transistor libraries optimized for different product configurations, different product applications. At the transistor technology level, you talk about the Super Power Rail, and then you look at a package, we also have a different optimization point. You see, CoWoS is largely leveraged by HPC or AI applications. Then you look at the InFO [packaging technology], which is heavily leveraged by mobile customers. So yes, we already optimized our technology explicitly for different product segments.

Anton Shilov: Back in the day, you developed those HPC-oriented X process technologies like N4X, N3X, and now N2X. But starting with A16, they are already optimized for HPC from the start, is that correct?

Kevin Zhang: That is correct. A16 with Super Power Rail is really tailored for HPC applications. However, with the X-lineup — N4X, N3X, and N2X — we really try to enable customers to achieve maximum speed for single-thread applications.

Note: TSMC tends to offer multiple iterations of process technologies within one PDK (for example, N5, N5P, N4, N4P, or N3B, N3E, N3P). This enables the foundry to use expensive equipment for as long as possible, and also enables TSMC's customers to reuse their IP for as long as possible.

Anton Shilov: Now that it gets more expensive to transit from one node to another, do you expect the number of iterations within one generation to increase, or stay at around three or four? Will there be any specific questions of A16 or A14?

Kevin Zhang: If you look at the roadmap, you can count how many derivative versions of each major node we introduced, right? I mean, you use the 3nm example; you already see that there is N3E, N3X, N3P, and now we have N3C. So, we already have four different major flavors. But I do want to point out one thing: they are different derivative versions of [one] technology, they are compatible. For example, N3E to N3P to N3C, customers can reuse much of the design. You might need to characterize [chip design] a little bit differently because of certain things we optimize. But largely, the physical design can be reused directly. This allows our customer to basically leverage their previous product design or previous IP to achieve further optimization based on the process enhancement or process optimization.

Anton Shilov: So, going forward, starting from A14 and A16, are they going to offer those specialized versions as well?

Kevin Zhang: The Super Power Rail introduced quite new features because the power connection is totally moved from the front to the back. So, it does require a quite significant new design. That is a uniqueness of A16. When you move the power to the backside of the wafer, on the front side, much of the cell library [can be re-used] by applying some of the minimum changes. The changes largely happen on how you hook up the power.

Anton Shilov: But starting from A14, which is a brand-new node, do you plan to offer further iterations of this technology like you do today?

Kevin Zhang: I can tell you we continue to follow what we have done in the prior generations, like the 2nm, with A14. I would not be surprised [if] next year we are talking about the A14P or A14X. There will be A14C at some point. All of these are going to follow a similar philosophy [of current offerings]: to make it compatible, to make it incremental, and allow our customers to harvest the benefit of the investment that they have put in 14A when they make that transition.

Anton Shilov: Now that you have mentioned the C variants of process technology, can you estimate the cost benefits of N3C?

Kevin Zhang:  The product level cost benefit depends on specific product design, product configuration, but from pure intrinsic technology capability point of view, I am talking about an order of 10% cost benefit.

As requirements grow, chip designers adopt more advanced process technologies

Anton Shilov: TSMC management has mentioned several times that the number of N2 tape-outs in the first two years is expected to be higher than the number of N3 and N5 tape-outs in their first two years, despite the fact that customers had to adopt all-new IPs for GAA process nodes. What are the reasons for that?

Kevin Zhang: Well, I think the main reason, it is driven by application. We talk a lot about AI these days. [But the] fundamental AI requirement is really energy-efficient compute, right? Whether it is a data center, whether it is edge devices. But you think about a data center, right? Today, data center's biggest single cost component is electricity, the consumed power. So, by adopting more advanced silicon technology, you bring power down substantially.

So, the customer sees a significant cost of ownership benefit by adopting more advanced silicon technology. So, this is really the underlying force for customers to be more aggressive in adopting advanced silicon technology nodes. Same things as they continue to incorporate more compute capability.

Think about the AI capability, for example, for a video. You know, the [video] you have taken [and uploaded to YouTube] needs extensive compute capability [from a Google datacenter]. So, all of these essentially drive the customer to go to a more advanced silicon, more advanced transistor technology.

So, we see that the trend is actually accelerating. That's why I showed that chart earlier. You see over the last three generations, the NTO number continue to increase, right? 2X for first year and the 4X for second year. So, this is really the reason behind those numbers.

Anton Shilov: Data center applications increasingly use a multi-chiplet design approach. However, when it comes to multi-chiplet solutions, we know that power consumption increases when a chip design gets disaggregated, so chip designers have to deal with this. But do you think you can help them cut the power consumption of their disaggregated designs on the foundry level?

Kevin Zhang: That is already happening today. Each specific function, elements, CPU, GPU AI neural engine, for example. They actually require a different optimization point. Today, we already offer many different flavors of transistors. For example, we allow a designer to use a different transistor for different function design optimization points today on the same die. They are already doing that. This is very important for us, to work with [a] customer to provide that specific optimization. So that's a monolithic design.

For multi-chiplet design, they actually can use drastically different silicon technology. Some, for example, use [the] most advanced technology, let's say 2nm for compute, but for low power, low speed elements, they can stay with a 3nm or even 5nm, or 4nm for that matter, and then leveraging our advanced integration scheme to bring them together. So, this is actually happening already today, at the system level we are working very closely with our different customers for different product applications.

Note: Using different transistor libraries and process technologies can optimize power consumption. However, a multi-chiplet solution will still likely consume more power than an integrated solution. When it comes to 3D integration, TSMC's customers have to wait for the foundry to develop TSV versions of a process technology (e.g, N4 TSV, N3 TSV, N2 TSV, etc.) before this node can be used as a base die.

Anton Shilov: Last year, you talked about system-on-wafer integration for extremely powerful solutions. But how many customers are actually interested in such huge system-on-wafer level processors? Cerebras and Tesla, obviously. Are there many more?

Kevin Zhang: We see that trend, people continue to drive a larger interposer size to bring more compute units, more HBM. So that trend will continue. We see customer want to leverage wafer-level integration to address their future needs. But you know, this is probably a few years out because right now I talk about production CoWoS, it is 3.5X reticle size, in the future there will be 5X reticle size and 9X reticle size, and beyond 9X, wafer-level integration will become an important integration scheme. But they are still a few years out. But there are customers. You mentioned Cerebras and also Tesla's Dojo. They are more aggressive to leverage the wafer level integration.

TSMC will continue to evolve

With over 500 clients from different market segments, TSMC is evolving its strategy to address increasingly divergent customer needs by offering multiple, segment-optimized leading-edge manufacturing technologies for AI, HPC, and consumer applications and enabling its clients to reuse their IPs as its fabrication processes evolve. This once again emphasizes the company's long-standing 'Everyone's Fab' philosophy, shifting from a one-size-fits-all approach to a portfolio of purpose-built nodes and packaging solutions.

Going forward, TSMC will offer leading-edge process technologies with its Super Power Rail backside power delivery network (e.g., A16 and A14P) for AI and HPC applications; leading-edge nodes without BSPDN (e.g., N3P, N2, N2P, A14) for client and smartphone processors; and cost-optimized advanced nodes (e.g., N4C, N3C, N2C) for designs aimed at cost-sensitive applications.

Previously, the company offered its cost-optimized nodes only for mature nodes (e.g., N16FFC, N12FFC). For multi-chiplet and disaggregated designs, TSMC continues to expand its 3DFabric portfolio with diverse offerings for client/mobile (InFO), for AI and HPC 2.5D integration (CoWoS), for client and data center 3D integration (SoIC), and even system-on-wafer (SoW) integration for the most demanding solutions.

TSMC started to produce chips on its performance-enhanced N3P (3rd Generation 3nm-class) process technology in the fourth quarter of 2024, as planned, the company revealed at its North American Technology Symposium 2025. N3P succeeds N3E and targets client and data center applications that require enhanced performance while retaining 3nm-class IP. The technology will be succeeded by N3X in the second half of this year.

TSMC's N3P is an optical shrink of N3E that retains design rules and IP compatibility while offering 5% higher performance at the same leakage or 5% – 10% lower power at identical frequencies, along with a 4% transistor density boost for designs with a typical mix of logic, SRAM, and analog blocks. As N3P's density gain comes from improved optics, it enables better scaling across all chip structures, particularly benefiting SRAM-heavy high-performance designs. N3P is now in production — so the company is currently building up products on this technology for its lead customers.

Advertised PPA Improvements of TSMC's New Process Technologies

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.

But the era of 3nm-class process technologies for high-performance applications does not stop at N3P. The node will be followed by N3X, which promises to increase maximum performance by 5% at the same power or reduce power consumption at the same frequency by 7% when compared to N3P. However, the key benefit of N3X compared to N3P is its support for up to 1.2V voltage (which is extreme for a 3nm-class technology) which will enable the absolute maximum frequency possible (Fmax) for applications that need it (i.e., client CPUs). That Fmax comes with a tradeoff: up to 250% higher leakage power — so chip developers must be careful when building N3X-based designs that feature a 1.2V voltage. Mass production of N3X chips is on track for the second half of this year.

" N3P started production late last year, in 2024," said Kevin Zhang, senior vice president of business development and global sales and deputy COO at TSMC. "We continue to enhance our 3nm technology. […] Our strategy has been after our introduction of the new nodes, we continue to do enhancement in order to allow our customer to harvest the technology scaling benefit. […] We recognize it is a significant investment for our customers to get [to a new] node, for example, developing IP on the ecosystem. So, we want our customer continue to harvest more benefits from their investment at each new node, but at the same times we are providing them enhancement at a product level."

TSMC tends to offer multiple iterations of process technologies within one process development kit (e.g., N5, N5P, N4, N4P, N4C). On one hand, this allows the company to use expensive equipment for as long as possible — on the other hand, this also allows its customers to reuse their IP for as long as possible. Therefore, N3P are N3X are natural additions to the N3 family of production nodes.

While the eyes of technology enthusiasts are on TSMC's 2nm-class fabrication processes that rely on gate-all-around (GAA) nanosheet transistors, the vast majority of advanced processors for client applications that will hit the market in the coming quarters (including the next-generation of iPhones, iPads, and Macs) will be made on TSMC's N3 family of process technologies.

Apple has started large-scale production of its next-generation M5 processor for desktops, laptops, and high-performance tablets, reports ETNews citing its own sources. The new system-on-chip (SoC) is expected to use a performance-enhanced N3P fabrication process, which was set to enter mass production in the second half of 2024, so the information has some merit. Still, as the information comes from an unofficial source, it should be taken with a grain of salt. 

Apple's M5 is the next-generation CPU for entry-level Macs as well as high-end iPad Pro tablets. The M5 family is projected to include M5, M5 Pro, M5 Max, and M5 Ultra processors, though Apple has not formally disclosed its plans concerning the lineup. Also, the company did not disclose any specifications of these units, though we expect them to feature new general-purpose cores, revamped GPUs, improved NPUs, and possibly enhanced memory subsystems. 

The report claims that Apple's new M5 processors will use organic substrates featuring 'Ajinomoto's upgraded ABF films,' which can increase the density of interconnections as well as decrease the thickness of SoC packages. In addition, the high-end M5 Pro, Max, and Ultra versions will use hybrid bonding and a 2.5D packaging technology — TSMC's SoIC-mH (molding horizontal) — to disaggregate the CPU and GPU (taking a page from Intel's book) and reduce thermal density, according to Ming-Chi Kuo, a reputable analyst from TF International Securities. Transition to multi-chiplet designs with high-performance CPUs makes sense for Apple, as it will let the brand increase yields at the cost of a longer production cycle. 

This year's SoCs are all expected to use TSMC's N3P manufacturing technology, a performance-enhanced optical shrink of the company's N3E fabrication process. As an optical shrink, the N3P node allows processors developers to either boost performance by 4% at the same power level or cut power use by 9% at identical clock speeds. Additionally, it increases transistor density by 4% for mixed designs, defined by TSMC as 50% logic, 30% SRAM, and 20% analog circuits. 

Considering microarchitectural enhancements, process technology improvements, and the multi-chiplet design of Apple's premium M5 SoCs, it's logical to assume they'll offer substantial performance advantages over M4 CPUs (though actual numbers remain to be seen). 

TSMC said multiple times that its N3P would enter mass production in the second half of 2024, so it would make sense, time-wise, for the company to have started mass producing chips on this manufacturing node late last year. It is likely that Apple's M5 will be among the first processors to use N3P (though this is speculation), so the chance that TSMC is currently mass producing the SoC is fairly high. As for higher-end M5 Pro, M5 Max, and M5 Ultra variants that presumably rely on a multi-chiplet design and use advanced packaging, we expect their mass production will start a little later. 

This doesn't mean the first Apple products with the M5 are around the corner — Apple finished updating its lineup of products with its M4 series processors in October, so it's likely not going to rush the successors just yet. We expect we'll see M5 products later this year.

As competition between contract chipmakers heats up, foundries tend to increase their capital expenditures to satisfy the demands of their clients for the latest production nodes. TSMC last week said it would dramatically increase CapEx spending this year as it preps to ramp up manufacturing of 2nm-class chips next year. Intel is expected to follow, though its CapEx increase will likely be moderate. But unlike its industry peers Samsung intends to slash spending on its foundry unit, reports TrendForce citing SEDaily.

Samsung has been spending billions of dollars every year on its foundry and memory production capacities for about 10 years now. However, the Samsung Foundry unit is cutting its CapEx by more than half in 2024, allocating ₩5 trillion ($3.5 billion) compared to ₩10 trillion ($7 billion) last year, according to the report. The decision allegedly reflects reduced client demand and efforts to improve efficiency. Samsung has reportedly faced difficulties in attracting large customers due to delays in advanced manufacturing processes and lower-than-expected yield rates. Utilization rates for its 4–7nm-class production lines at Pyeongtaek have reportedly fallen by over 30%, though SEDaily does not specify the period over which the utilization rate dropped by a third.

The report claims that Samsung Foundry's 2025 investment will prioritize the Hwaseong S3 and Pyeongtaek P2 production facilities. At S3, part of the 3nm production line will be upgraded to 2nm, which is considered a minor modification rather than a major new investment, as Samsung's SF3P process technology was renamed to SF2, so the latter hardly requires a lot of all-new tools for mass production. Meanwhile, P2 will see the installation of a 1.4nm test line with a monthly capacity of 2,000–3,000 wafer starts by the end of 2025. Smaller investments are also planned, such as upgrading existing equipment and supporting infrastructure development at the Taylor plant in the U.S. Essentially, the plan is to upgrade existing fabs rather than expand capacity.

Samsung's rivals have different plans

By contrast, TSMC last week stated it would increase its CapEx spending from $29.76 billion in 2024 to $38 billion – $42 billion in 2025. Approximately 70% of this budget will be spent on advanced process technologies, while 10% to 20% will be allocated to specialty technologies. The remaining 10% to 20% will be dedicated to advanced packaging, testing, mask-making, and other related areas.

TSMC intends to start mass production of chips on its N2 (2nm-class) fabrication process in the second half of 2025 and ramp it up in 2026. TSMC reports that the number of planned 2nm tapeouts is higher than the number of N4 and N3 tapeouts at the same stages of their development. As a result, the company will need more N2-capable production capacity and is equipping its fabs with appropriate tools.

Intel is also about to start ramping up production of chips on its 18A manufacturing process later this year while preparing for next-gen nodes and making chips for its Intel Foundry clients. To that end, TrendForce expects the company to increase its CapEx from $11 billion – $13 billion in 2024 to $12 billion – $14 billion in 2025. While this will still be significantly less than TSMC plans to invest in its production capacity, it will still be substantially higher than Samsung's alleged CapEx, if the report is to be believed.

The recent 6.4-magnitude earthquake in Taiwan did not cause significant damage to TSMC and its fabs, but it still required the company to halt production and will probably mandate that it recalibrate its tools. ComputerBase reports that up to 20,000 wafers in mid processing could be affected.

A 6.4-magnitude earthquake struck southern Taiwan at 12:17 AM on Tuesday, centered in Dapu Township, Chiayi, and 9.4 km deep. TSMC evacuated staff from its central and south production sites and halted production. Tremors were strongest at level 5 in the Southern Taiwan Science Park and level 4 in the Central Taiwan Science Park, while Hsinchu facilities recorded milder level 3 tremors.

Key sites affected include TSMC's Fab 18 in the Southern Taiwan Science Park, a major hub for 3nm production; Fab 8, a 200mm fab; and Fab 14, which produces chips on 4nm and 5nm-class fabrication technologies, reports TrendForce. Apparently, the production disruption could affect up to 20,000 wafers that were being processed at these fabs. Some of these may be completed but most will likely be scrapped, which will disrupt shipments of chips to at least some companies, meaning lower than-expected availability of some products.

The affected 10,000 to 20,000 wafers represent a small fraction of TSMC's production. The company processed 3.418 million 300-mm equivalent wafers in the last quarter, and its average daily output is around 37,000. Hence, the earthquake will not significantly affect TSMC's financial situation. However, if a fabless company loses a batch of its processors, that might hurt its sales.

Regarding TSMC's fabs, inspections revealed no structural issues or disruptions to utilities like electricity and water. The buildings are designed to withstand earthquakes up to magnitude 7, so this most recent quake was hardly a big problem for TSMC. However, high-precision chipmaking tools installed in the factories are considerably vulnerable. Even though machines are designed to absorb vibrations, they are calibrated to make chips, and right now, they might need a recalibration, which will take time. The good news is that some costs will likely be offset by insurance. Despite the disruptions, TSMC is expected to resume full production swiftly.

A similar event in April 2024 caused TSMC losses of $92 million. At that time, equipment in areas with magnitude 5+ tremors required three days to return to normal, and some wafers being processed were lost.

Apple's A-series smartphone processors have evolved significantly from the A7 (28nm) to the A18 Pro (3nm), gaining more cores, transistors, and features. With each new node, TSMC charged Apple more per wafer, so the price increased from $5,000 for a 28nm wafer with A7 processors to $18,000 for a 3nm-class wafer for A17 and A18-series processors, reports Ben Bajarin, the chief executive and principal analyst at Creative Strategies.

Bajarin notes that as Apple's A-series chips have evolved, their transistor count has consistently increased, starting at 1 billion in the A7 and reaching 20 billion in the A18 Pro. That makes sense because the number of cores and features has also increased: in 2013, the A7 featured two high-performance cores and a four-cluster GPU, whereas, in 2024, the A18 Pro features two high-performance cores, four energy-efficient cores, a 16-core NPU, and a six-cluster GPU. 

A-series processors are aimed at smartphones, and Bajarin says their die sizes have remained relatively consistent, ranging between 80 and 125 square millimeters across generations. This was enabled by a steady increase in transistor densities facilitated by TSMC's latest process technologies. 

The most substantial transistor density increases occurred in the earlier nodes, such as transitions from 28nm to 20nm and then to 16nm/14nm. However, recent process technologies (N5, N4P, N3B, N3E) exhibit slower density improvements. The peak period for transistor density improvements occurred around the A11 (N10, 10nm-class) and A12 (N7, 7nm-class), with gains of 86% and 69%, respectively. Recent chips, including the A16 to A18 Pro, show a noticeable slowdown in density advancements, primarily due to slower SRAM scaling. 

However, despite diminishing returns, Bajarin notes that production costs have risen sharply. Wafer prices climbed from $5,000 for the A7 to $18,000 for the A17 and A18 Pro, while the cost per square millimeter increased from $0.07 to $0.25. 

Bajarin says his information comes from a third-party supply chain report, and the company that produced it has sources at TSMC. Bajarin has also triangulated certain factors through his own sources. In general, the listed TSMC pricing looks more or less consistent with previous reports, though we should always take non-official information with a grain of salt. 

To make things even harder for Apple, performance increases have also slowed down with the latest generations of its processors (with A18 and M4-series being exceptions) as it got harder to extract higher instruction per cycle (IPC) throughput with the latest architectures. Nonetheless, Apple has managed to maintain performance-per-watt gains with each generation. 

"Given it is harder to pull out IPC gains, but getting efficiencies where they can even if its costs related to area increase, [is a viable] performance-per-watt [gain] strategy," Bajarin told Tom's Hardware. 

According to well-cited industry reports, TSMC always sells its customers wafers with sellable and non-sellable dies, not just sellable dies. Therefore, the number of chips derived from a wafer depends on the manufacturing yield. Higher yields produce more chips per wafer, while lower yields result in fewer. This yield-based variability impacts the cost-effectiveness of the wafers for customers. However, there is one important part here: TSMC guarantees that it will try to achieve a certain yield target before production starts.

If the actual yield falls short by a substantial margin, such as 10% to 15%, TSMC may provide financial compensation or discounts to affected customers. These terms aim to reassure clients about TSMC's reliability and the value of their high-cost wafers. 

Being an alpha customer for the latest process technologies, Apple has a chance to adjust manufacturing processes to lower defect density and increase its yields, so the company is in a better position from a cost perspective than other TSMC clients. Also, it's rumored that Apple is TSMC's only customer that pays TSMC on a per-chip, not per-wafer, basis. If true, this sets Apple further apart from other TSMC customers.

According to reports from leakers on the Chinese social media site Weibo, Mediatek and Nvidia are collaborating on a 3nm AI CPU. IT Home shared a report from user "Mobile Chip Expert" today, claiming that the CPU is entering the tape-out phase of production this month, with mass production on track for late 2025. 

We've reported on rumors of potential MediaTek and Nvidia collaborations for a few months now, so as usual, take this new report with a serving of salt. Previous rumors of a PC chip collaboration were the companies working on an AI card processor. However, today's reports are connected to rumors of an Nvidia/MediaTek AI processor that started in May.

The MediaTek AI processor is expected to be paired with an Nvidia GPU. The post also names Lenovo, Dell, HP, and Asus as prospective customers looking to adopt the processor in OEM hardware. The chip has also been linked to a rumored $300 price tag. 

Today's report curiously only refers to the rumored chip as an "AI PC" CPU, surprising as both previous leaks about the collaboration and MediaTek's stable of products would point to a mobile chip or SoC being more likely. MediaTek specializes in mobile products and typically employs AMD as a hardware partner. AMD uses MediaTek’s Wi-Fi 6E solutions in its mobile platforms, and MediaTek and AMD have also been connected through rumors of a 5G notebook for some time. 

It would not be surprising if the MediaTek/Nvidia chip transitioned to only an AI PC solution and moved away from being a mobile phone offering. After the big waves and lessons learned from the Qualcomm Snapdragon X Elite launch this year, there is room for another Windows-on-Arm competitor from a primarily mobile company like MediaTek. One of the most prominent problems reviewers had with the performance of Snapdragon X-powered computers was their lack of graphical strength, which Nvidia can quickly solve. Nvidia's name recognition alone will do much to boost the MediaTek chip, whether it is Nvidia's return to mobile graphics or a different venture into laptop-form-factor AI PCs.

MediaTek and Nvidia's only officially announced collaboration is the Dimensity Auto Cockpit platform, an SoC for cars that license Nvidia's graphics IP and Nvidia Drive OS. The chip seeks to be a front-runner in automotive chips by offering full support for infotainment platforms, including AAA gaming with RTX graphics and safety features such as HDR multi-camera support. So far, no US-based cars seem to have adopted the platform.

Alphawave Semi, an IP and contract chip designer, has developed the industry's first 3nm UCIe chiplet that enables die-to-die connectivity for system-in-packages made on TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology. The chiplet targets high-demand sectors such as hyperscalers, HPC, and AI, and allows users to build a wide range of system-in-packages (SiPs). 

"Achieving successful silicon bring-up of 3nm 24 Gbps UCIe subsystem with TSMC's advanced packaging is a significant milestone for Alphawave Semi and underscores the company's expertise in utilizing the TSMC 3DFabric ecosystem to deliver top-tier connectivity solutions," said Mohit Gupta, Alphawave Semi’s SVP and GM of Custom Silicon and IP. 

Although the 3nm chiplet can be used separately to connect UCIe 1.1-compliant chiplets, the main purpose of the IP is to be integrated into other chiplets to enable die-to-die connectivity by either Alphawave Semi (for its customers) or companies licensing the IP. The silicon-proven 3nm die-to-die interface IP is a big deal for the market as it allows for the building of multi-chiplet SiPs, implemented using TSMC's most advanced fabrication process to date. 

Since TSMC's N3 production nodes are expensive to use, disaggregation of large monolithic designs is a good way to improve yields — and this is where Alphawave's silicon-proven 3nm die-to-die interface IP comes into play. Compatibility with TMSC's CoWoS is an important capability for the IP. 

The 3nm chiplet supports a bandwidth density of 8 Tbps/mm and targets TSMC's CoWoS 2.5D silicon-interposer-based packaging — the same packaging that Nvidia uses for its Hopper H100 and next-generation Blackwell B100 and B200 GPUs for AI and HPC applications. Alphawave Semi's UCIe chiplet subsystem packs both PHY and controller IP, and supports a wide range of protocols — including streaming, PCIe, CXL, AXI-4, AXI-S, CXS, and CHI. The chiplet can connect a variety of 3nm components in a SiP. 

Alphawave Semi's UCIe subsystem IP adheres to the most recent UCIe Specification Rev 1.1 and is equipped with extensive testing and debugging features, including JTAG, BIST, DFT, and Known Good Die (KGD) functionalities. Another standout feature of this IP is its ability to monitor lane health in real-time — which greatly enhances SiP's robustness.

We interviewed Mike Clark, AMD's Corporate Fellow Silicon Design Engineer, during the company's recent Tech Day, where it unveiled the Zen 5 microarchitecture that powers the company's Ryzen 9000 and Ryzen AI 300 processors. 

Clark, known as the 'Father of Zen' or, depending on which AMD employee you ask, the 'Zen Daddy,' has worked on AMD's CPU architectures for 31 years. He was the lead architect of the first generation of Zen, which he unveiled at Hot Chips while the company was teetering on the edge of bankruptcy back in 2016. 

Over the last seven years, AMD has unveiled five generations of Zen, each delivering double-digit increases in instructions per clock (IPC) improvement. Clark has led Zen's development through all five generations, with a sixth in the hopper, transforming AMD from a struggling chipmaker to a stock market darling that has now clawed back a significant amount of market share from Intel. Now AMD has nearly twice the market cap of its long-time foe Intel, and the architectures driven by Clark served as the fuel for the incredible turnaround.

AMD's Zen 5 architecture will span both the 4nm and 3nm process nodes, powering the next generation of AMD's entire CPU product stack that spans from desktop and mobile PCs to its EPYC processors for the data center. Designing one cohesive underlying architecture to address all those markets is an incredible engineering feat. AMD is launching the 4nm Zen 5 chips at the end of this month, but it hasn't yet announced the timeline for the 3nm variants. Clark expanded on the challenges of designing Zen 5 for both the 4nm and 3nm processes concurrently, saying the two versions are basically arriving "on top of each other."

AMD has used its compact Zen 'c' cores, smaller cores designed for background tasks much like Intel's E-cores, to reduce cost and boost performance in its laptop processors. However, unlike its competitor, AMD hasn't brought those cores to its mainstream and high-end desktop lineup yet. Zen 5c marks the second iteration of AMD's compact cores, but they are currently not planned for the mainstream Ryzen 9000 family. However, Clark said he thinks compact cores will come to future Ryzen desktop chips and also expanded on the techniques the company uses for its unique implementation.

Intel has famously abandoned injecting hardware acceleration support for high-performance AVX-512 instructions, but AMD's Zen 5 marks the debut of full AVX-512 acceleration for the Ryzen family. Unlike Intel, which has to reduce clock speeds when its processors run AVX-512 workloads, AMD says these powerful instructions will run at the same clock speeds as standard integer operations. Clark also expanded on how the company achieved that feat and said that its Zen 5c cores can also run full AVX-512.

Below is a lightly edited transcript of the key points of our conversation with Clark.

Will Zen 5c 'compact cores' come to high-end desktop PC chips?

AMD's approach to its compact Zen 5c cores is inherently different than Intel's approach with its e-cores. As with Intel's E-cores, AMD's Zen 5c cores are designed to consume less space on a processor die than the 'standard' performance cores while delivering enough performance for less demanding tasks, thus saving power and delivering more compute horsepower per square millimeter than was previously possible (deep dive here). But the similarities end there. Unlike Intel, AMD employs the same microarchitecture and supports the same features with its smaller cores. 

With Zen 5, AMD has also designed the smaller compact cores to deliver nearly the same performance as the larger cores, thus preventing the faster Zen 5 cores from waiting on the compact cores during threaded workloads. Clark said that he expects AMD's compact cores to eventually come to the company's desktop processors, explained that AMD uses a thread placement technique to target certain workloads to the smaller cores, and expanded on how AMD has shrunk its standard cores to create Zen 5c.  

Tom's Hardware (TH): When you view Zen 5c compact cores, do you think they only have a place in power-constrained environments [mobile]? Could you see this coming over to desktop PCs, where power isn't a consideration?

Mike Clark (MC): [...] If we keep building the compact cores in the way that we talked about—which I think we will; I don't know why I said it a little more theoretically—the hard part is really making sure we hit the right frequency point so that it's balanced with however many [cores] you're going to put down. But let's say you're really good at that, then there's no reason not to put a compact core on a desktop.

Whether it's the same performance at a given core count to the customer and cheaper because there's less area used, or we can squeeze in even more cores on a desktop because of the compact cores. And we couldn’t leverage them [performance cores] anyway because they were TDP-constrained when you got out to that many cores, so you may as well have used a compact core. I think as we get more experienced with Windows and see that the scheduling does work, well, I think you'll see us, in desktop, using the compact cores to both get more cores and be more cost-effective. Because it's wasted area [for performance cores] because we can't run everything at that 5.7 GHz frequency.

TH: When using compact cores in a heterogeneous design, do you schedule workloads into those cores using some sort of thread placement?

MC: We don't have any hardware that can magically move cores or make it transparent to software, so we leverage software. We can build a table of capabilities of the different cores and dynamically update that table to give them feedback as things are going on so that they can manage where to place the core for a lightly threaded workload. [...] We expect both the classic cores and the throughput [Zen 5c] cores to keep up at the same level and not be burdened by the throughput core not really having enough compute. The algorithm runs at the order of the slowest cores, so those throughput cores can run at a pretty high frequency so that we can handle true multi-threaded workloads. But then when you have multi-processing, you need to be smart about where you place things.

You should test it. I haven't seen it, but you can run Teams, and you'll see it on the compact cores. You can open up your browser, and it'll go over to the performance cores because you need that burstiness. And then, when you're done, it'll go away; Teams will still stay on those compact cores, and you'll get the best of both worlds.

TH: When you are looking at the standard core and shrinking it down while closely matching the performance capabilities so you don’t have thread dependency problems, how do you achieve that? Denser libraries, closer spacing?

MC: It's more of the latter — the library’s the same. [..] There are sort of logical blocks, and there are even subblocks, but to hit the high frequency in certain critical speed pads, we have to break the design down into small pieces, which we then do custom work on. But at the end of the day, it's a rectangle; things are further apart than they need to be, there's whitespace, and that's all to drive that high frequency. But then we say, ‘Okay, well, lower the max frequency.’ Then, we can combine blocks together; we don't need to do as much custom work, and it can pull the design in. It's now just naturally smaller because we utilize the space more. When it was bigger there's extra logic for repeaters and stuff like that, there’s buffering, and that all gets removed.

It's amazing how much you can shrink the core at whatever target you picked to then find a bunch of area and power to get the squeeze out of it. It was really just because of what we had to do to get that high frequency. Now, you could say, ‘Well, why aren't you better at picking those small bundles? ' But we've been doing that for years, and we can't perfect the smaller blocks. It's just kind of in the nature of the design.

How Zen 5 runs at normal frequencies while running AVX-512 workloads

TH: You mentioned that Zen 5 runs AVX-512 instructions at the same clocks as standard instructions. Intel has struggled with this for a long time, and then they've done all kinds of things, like bifurcating AVX instructions into different classes denoted by power usage. Has Zen 5 employed any notable tweaks to keep the AVX-512 clocks high? What's your secret to success?

MC: Fundamental to what I would call our secret to our success is trying to introduce it at a point where it's more balanced with the rest of the machine. That’s so it doesn't look like such a one-off and so you don't have to treat it as such a one-off, which leads to all those problems. Now, it can obviously burn more power, but so could AVX-256. But it's better that things grow together. If you imagined us trying to put AVX-512 on Zen 2, we had just grown from AVX-128 to AVX-256 at that time. I just have this balance thing; that's what Zen is, and it's just so in balance.

Now, we've learned as well. Even on the integer side, our schedulers burn a lot of power. And so, on both sides, I think a lot of the trick is, and I’m sure Intel's learned this too, is laying out the floor plan in a way that you're cognizant of where hotspots are going to be, knowing also that you never get everything right, so putting in sensors everywhere — but especially where you're worried. We've been good at getting those to work and using our firmware to manage that dynamically so that we can better respond. There are times when we do have to throttle it down because multiple cores are using it, and it’s more TDP-constrained. But that happens on the integer side, too.

TH: So frequencies would be pretty much in lockstep with integer?

MC: It’s just trying to sense it and react to it enough so that it's not, ‘Oh, this one guy [core] did it, and we took everyone down [frequency],’ and it’s not really that serious of a situation. So, it’s a management problem that we’ve grown to understand and deploy across the design, not just for AVX-512.

TH: When we look at the compact cores running AVX-512, do they run that at standard full data path, full 512-bit width, or do they run double-pumped AVX-256?

MC: We can do either. For what we’re launching today in Strix Point, both the performance core and the compact core both have the AVX cut-down [AVX-256] because they're in a heterogeneous situation, and they're in a mobile platform where area is at a premium. 

And while you could argue we could try to have it, we don't want software to have to try to deal with something like that. Even though we cut it down on the performance core, which helps the area, we can have more throughput cores at some level. But we could build a compact core for other markets, and I think you'll see that where we do have the full 512-bit data path as well because it's great for AI and vector workloads, even if it's a more dense design, that doesn't mean it doesn't want great vector performance when it needs it.

The biggest challenge of Zen 5 design

TH: What was the biggest challenge you encountered with Zen 5 development?

MC: It was actually dealing with two technologies [designing Zen 5 for both the 4nm and 3nm process technologies], especially a technology that the previous generation was in. And trying to do so much change, and therefore the unavoidable reality that in 4nm it's going to be [consume] more power than it's going to be in 3nm, no matter how smart we are. 

But we need that flexibility in our roadmap, and it makes sense. But still that was really hard to try to control having the two technologies and the features, and a feature that looks great in 3nm not looking so great in 4nm because of the power impact of the not-as-efficient transistor and how it affects the floorplan. Normally, we do the architecture in one, and then we port on the next one, and then you have a lot of time to deal in the floor plan with the two technologies. [..] It was just really challenging. But that gives Zen 6 a lot of room to improve.

And we're going to deliver 3nm here in short order with 4nm; basically, they're on top of each other. So the design teams are separate in building those, but we're trying to communicate and work together — it is still the same. We've tried to keep it simple for our own sanity. We have all these designs we have to validate and we have to build, and the more they're different, the more things just get out of control. It drives complexity.

That was a challenge, and one we love because, like I said, now that we've done it, we've learned a lot from it. We're going to be able to do it better the next time. That's what makes this job so fun: constantly learning, constantly new challenges, and new innovation.

Due to the high demand for advanced processors in consumer electronics and high performance computing, TSMC is looking to hike its wafer pricing for all types of customers in 2025, according to a Morgan Stanley note to clients cited by Eric Jhonsa , an investor. Apparently, the world's largest contract maker of chips plans to hike its prices by up to around 10% next year. Keep in mind that the information comes from an unofficial source though so apply the required amount of skepticism.

Negotiations with AI and HPC customers, such as Nvidia, suggest these clients can tolerate approximately 10% price hikes for 4nm-class wafers from around $18,000 per wafer to around $20,000 per wafer. As a result, the 4nm and 5nm nodes, primarily used by companies like AMD and Nvidia, are expected to see an 11% blended average selling price (ASP) hike. This means that prices of N4/N5 wafers may increase by approximately 25% since Q1 2021, at least for some customers. 

Although discussions with smartphone and consumer electronics clients, such as Apple, have been challenging, there are signs of acceptance for modest price increases, the report claims. Morgan Stanley expects a 4% ASP increase for 3nm wafers in 2025. While wafer prices depend on actual agreement and volumes, some believe that a wafer produced on TSMC's N3 node costs around $20,000 or higher, but will increase next year. Morgan Stanley believes that companies should be room for companies to 'pass through the additional costs to end users.' 

Contrarywise, mature nodes like 16nm are unlikely to experience price increases due to sufficient capacity. 

To possibly make its customers a bit more willing to pay extra, Morgan Stanley's recent supply chain investigations indicate that TSMC is signalling a potential shortage of leading-edge capacity unless its customers 'appreciate TSMC's value' to secure their capacity allocation. 

Additionally, prices for advanced chip-on-wafer-on-substrate (CoWoS) packaging may surge by 20% over the next two years, Morgan Stanley analysts believe.  

In 2022, TSMC raised wafer prices by 10%, followed by an additional 5% in 2023. Looking ahead, another 5% blended increase is anticipated for 2025 in a bid to help TSMC's gross margin rebound to 53% - 54% by 2025.

Intel on Wednesday said that its 3nm-class process technology called Intel 3 has entered high volume production at two sites as well as provided some additional details about the new production node. The new process brings in both higher performance and higher transistor density as well as supports voltages of 1.2V for ultra-high-performance applications. The node is aimed at Intel's own products as well as at foundry customers. It will also evolve over the coming years.

"Our Intel 3 is in high volume manufacturing in our Oregon and Ireland factories, including the recently launched Xeon 6 'Sierra Forest' and 'Granite Rapids' processors," said Walid Hafez, Foundry Technology Development Vice President at Intel.

Intel has always positioned its Intel 3 fabrication process to be aimed at datacenter applications that require leading-edge performance enabled by revamped transistors (compared to Intel 4), their power delivery circuitry with reduced transistor via resistance, and design co-optimization. The production node supports both <0.6V low voltage as well as >1.3V high voltage for maximum loads. When it comes to performance, Intel promises that the new node will enable 18% higher performance at the same power and transistor density compared to Intel 3. 

To get the best combination of benefits for performance and density, chip designers will have to use a combination of 240nm high performance and 210nm high density libraries. Furthermore, Intel clients can choose between three metal stacks: 14 layers for costs, 18 layers for an optimal balance between performance and cost as well as 21 metal layers for higher performance.

For now, Intel will use its 3nm-class process technology to make its Xeon 6 processors datacenters. Eventually Intel Foundry will use the production node to manufacture datacenter-grade processors for its customers. 

In addition to base Intel 3, the company will also offer Intel 3T that supports through silicon vias and can be used as a base die. In the future, Intel will offer feature-enhanced Intel 3-E for chipsets and storage applications, and performance-enhanced Intel 3-PT that can be used for a wide range of workloads, such as AI/HPC and general purpose PCs.

AMD's hotly anticipated 5th-Gen EPYC Turin processors will launch in the second half of 2024, Lisa Su announced during her Computex 2024 keynote. The 3nm chips mark the debut of AMD's Zen 5 architecture for data center chips, and AMD claims they are up to 5.4x faster than Intel's competing current-gen Xeon chips in key AI workloads.

Turin comes in two variants: one with up to 128 standard Zen 5 cores and another using density-optimized CPU cores called Zen 5c — that model stretches up to 192 cores. Su also announced that AMD now has 33% of the data-center market.

The new Zen 5c-powered chips will feature up to 192 cores and 384 threads fabbed on the 3nm process node, then paired with a 6nm I/O Die (IOD) crammed into a single socket. The chip is comprised of 17 chiplets. The highest core count models utilize AMD's Zen 5c architecture, which uses density-optimized cores that are conceptually similar to Intel's e-cores. However, AMD pioneered this core type for x86 chips in the data center. 

The models with standard full-performance Zen 5 cores come with 12 compute dies with the N4P process node and one central 6nm IOD die, for a total of 13 chiplets.

AMD displayed a spate of benchmarks against Intel's competing Xeon chips, but as with all vendor-provided benchmarks, take them with some salt. AMD claims an up to 5.4X advantage in an LLM AI model (chatbots) over Xeon, along with a 2.5X advantage in translation models and a 3.9X advantage in summarization work. AMD also showed a 3.1x advantage in the scientific NAMD workload with its 128-core Turin model and a live demo of Turin delivering 4X more tokens per second than Xeon.

The 192-core Zen 5c chips are the follow-on series to AMD's EPYC Bergamo, the industry's first x86 data center processor with density-optimized cores (Zen 4c). Bergamo tops out at 128 cores. 

The 'standard' Turin models with the Zen 5 architecture stretch to 128 cores, marking a strong generational gain over the current-gen EPYC Genoa, which peaks at 96 cores.

AMD's 192-core EPYC Turin chips are designed for the highest core density. They have an optimized Zen 5c core that halves the area needed for each core yet supports the same features as the full-fat Zen 5 cores, making them exceedingly attractive to hyperscalers (AMD says it owns 50% of this market segment).

The Zen 5c Turin chips will compete with Intel's 144-core Sierra Forest chips, which mark the debut of Intel's Efficiency cores (E-cores) in its Xeon data center lineup, and Ampre's 192-core AmpereOne processors, not to mention the custom silicon being developed or employed by Google and Microsoft.

Meanwhile, the standard Zen 5 EPYC processors will take on Intel's coming Xeon 6 lineup. Turin will drop into motherboards with the same SP5 socket used for 4th-Gen EPYC Genoa and Bergamo, allowing the existing kit to be simply upgraded to a drastically faster chip. This tactic also speeds quals on newer motherboards and servers, thus enabling a quicker time to market.

AMD also shared some benchmarks highlighting its claimed advantages in AI workloads with its existing 4th-Gen EPYC chips over competing Intel models. We expect more details to emerge as the Turin chips move closer to the market.

Samsung Foundry is about to land an order from AMD to make the latter's processors using 3nm-class process technology with gate-all-around field effect transistors (GAAFETs), reports Korea Economic Daily. The information is strictly unofficial and should be taken with a grain of salt. Yet, if the report is accurate, this will mark the first time in recent years that AMD will dual-source its products. 

AMD's chief executive, Lisa Su, reportedly said at ITF World 2024 that the company will mass-produce chips on a 3-nm-class GAA process, and the only company to offer such a production technology is Samsung Foundry. Unfortunately, it is unclear which products — CPUs (CCDs and/or IODs), GPUs, DPUs, chipsets, or maybe adaptive SoCs — AMD aims to produce at Samsung Foundry, though we would bet on some small chips initially to maximize yields. 

"Lisa Su's comments are viewed as effectively formalizing AMD's 3nm foundry collaboration with Samsung," an industry source told Korea Economic Daily. 

The move to use Samsung Foundry in addition to TSMC can be considered a strategic move for AMD as the company will expand its manufacturing capacity, sell more products, establish an important relationship, and gain leverage for price negotiations with TSMC. 

For Samsung, securing AMD as a client is critical in closing the market share gap with TSMC. However, Samsung is so significantly behind the world's No. 1 contract maker of chips that it would take years to challenge the Taiwanese foundry. Nonetheless, this partnership could significantly boost Samsung's foundry business and enhance its competitive position in the semiconductor market. 

GAAFETs offer several benefits over the currently used FinFETs. GAA transistors feature horizontal channels completely surrounded by gates. These channels are created through epitaxy and selective material removal, allowing designers to fine-tune them by adjusting the channel width: wider channels enhance performance, while narrower channels reduce power consumption. The architecture of GAAFETs can significantly decrease transistor leakage current (lowering power usage) and reduce variability in transistor performance, which is good for mobile processors and datacenter-grade products. 

Arm on Wednesday introduced its first compute subsystems for client PCs, greatly simplifying the development of processors for desktops, laptops, and tablets running Android, Linux, and Windows. The new CSS packs high-performance CPU and GPU IPs and will enable Arm's partners to build high-end system-on-chips for mobile devices and therefore potentially greatly expand the Arm ecosystem.

"We are now delivering physical implementations across Arm, CPU and GPU, making it easier to build and deploy Arm-based solutions and leaving nothing to chance, enabling new performance points, compute capabilities, and helping speed time to market," said Chris Bergey, SVP & GM of Arm's Client Line of Business. 

Arm's CSS for client PCs relies on two ultra-high-performance Arm Cortex-X925 general purpose cores (up to 3MB L2 cache per core and over 3.60 GHz clocks, SVE, SVE2 support), four high-performance Cortex-A725 cores, two energy-efficient Cortex-A520 cores, and an Immortalis-G925 graphics processor. Arm's latest CSS can support up to 14 CPU cores. The CSS is a production-ready physical implementation that can be made on a 3nm process technology (presumably TSMC's N3E — though this is speculation). 

Actual specifications of Arm's CSS implementation could be altered by the processor vendor to meet its performance and power goals, but the FPGA that Arm used for performance evaluation included a Cortex-X925 core (2 MB L2, 3.80 GHz), 16MB L3, 32MB system level cache, DSU at 2 GHz, and LPDDR5X-8533 memory. 

"Arm is providing more value, optimizing the whole stack for new 3nm process nodes, working with our leading foundry partners," Bergey said. "This allows us to provide IP in physical form. CSS for client brings together the physical implementation with the goodness of the Armv9 architecture for AI." 

Arm says that its 2024 CSS for client PCs provides significantly higher performance than its TCS23 (total compute solution 2023) platform from last year, both in synthetic and real-world applications — at least based on FPGA performance runs.

The Cortex-X925 CPU achieves a 36% increase in peak performance, as shown by Geekbench 6 single core scores compared to TCS23, according to Arm. It also reduces application launch times by 33% on average across five of the top 10 apps, enhancing productivity and providing a smoother user experience on mobile devices. Additionally, it offers a 60% improvement in web browsing speed, according to the Speedometer 2.1 benchmark, and boosts peak graphics performance by 30% on average across seven graphics benchmarks, including ray tracing and variable rate shading (VRS).  

The new Cortex-X925 platform also offers up to 42% higher performance in LLaMA 3 (eight billion parameters) and up to 46% higher performance in Phi 3 (3.8 billion parameters) AI models compared to Cortex-X4, when using KleidiAI libraries designed to speed up AI applications on modern Arm CPUs. 

Processors based on Arm's CSS will compete both against x86 processors from vendors like AMD and Intel and against SoCs from Qualcomm, which is about to roll out its Snapdragon Elite processors.

When Huawei and Semiconductor Manufacturing International Co. (SMIC) patented self-aligned quadruple patterning (SAQP) lithography methods to produce advanced microchips earlier this year, most assumed the companies were working on building chips using their 5nm-class fabrication process. Apparently, that's not the limit of their plans, as Huawei is now looking forward to using quadruple patterning for 3nm-class manufacturing technology as well.

SiCarrier, a state-backed chip manufacturing equipment developer that's working with Huawei, also patented a multi-patterning technique, confirming SMIC's plans to use this technology for future nodes. Experts like Dan Hutcheson from TechInsights suggest that while SAQP may allow China to manufacture 5nm-class chips, EUV machines will be essential for long-term competitiveness beyond these nodes. Industry experts never envisioned the use of quadruple patterning for 3nm-class nodes.

7nm-class process technology features 36nm–38nm metal pitches, while 5nm-class nodes shrink the metal pitches to 30nm–32nm. At 3nm, metal pitches will get to approximately 21nm–24nm. That could achieve critical dimensions of approximately 12nm for high-volume manufacturing, something that even Low-NA EUV tools cannot achieve without using of double patterning. Yet it looks like Huawei and SMIC plan to get there with SAQP using DUV tools.

SAQP is crucial for Huawei and SMIC as they lack access to leading-edge lithography tools like ASML's Twinscan NXT:2100i and Twinscan NXE:3400C/3600D/3800E. That's due to export rules imposed by the Nerherlands, with the U.S. being the primary instigator of the restrictions. SAQP involves repeatedly etching lines on silicon wafers to increase transistor density, reduce power consumption, and enhance performance. This approach mirrors Intel's previous attempts to avoid relying on extreme ultraviolet (EUV) lithography machines in 2019–2021 with its 10nm-class (later renamed "Intel 7") node.

Despite the potential benefits, SAQP's use presents difficult challenges. Intel's first-generation 10nm-class process technology failed at least in part due to this method. Yields were rumored to be so bad that the only 10nm Canon Lake CPU only had two CPU cores and the integrated graphics was disabled. However, for SMIC, SAQP is necessary to progress in semiconductor technology, enabling the production of more sophisticated chips — including next-generation HiSilicon Kirin processors for consumer devices and Ascend processors for AI servers.

Although the cost per 5nm or 3nm chip using SAQP will almost certainly be higher, making it less feasible (if at all) for commercial devices, the method remains vital for China's advancements in semiconductor technology. These advancements are essential not only for consumer electronics but also for applications like supercomputers and potentially for developing military capability.

Ampere Computing today introduced its roadmap for the coming years, including new CPUs and collaborations with third parties. In particular, the company said it would launch its all-new 256-core AmpereOne processor next year, made on TSMC's N3 process technology. Also, Ampere is teaming up with Qualcomm to build AI inference servers with the company's accelerators. Apparently, Huawei is also looking at integrating third-party UCIe-compatible chiplets into its own platforms.

256-core CPUs incoming

Ampere has begun shipping 192-core AmpereOne processors with an eight-channel DDR5 memory subsystem it introduced a year ago. Later this year, the company plans to introduce 192-core AmpereOne CPUs with a 12-channel DDR5 memory subsystem, requiring a brand-new platform. 

Next year, the company will use this platform for its 256-core AmpereOne CPU, which will be made using one of TSMC's N3 fabrication processes. The company does not disclose whether the new processor will also feature a new microarchitecture, though it looks like it will continue to feature 2 MB of L2 cache per core. 

"We are extending our product family to include a new 256-core product that delivers 40% more performance than any other CPU in the market," said Renee James, chief executive of Ampere. "It is not just about cores. It is about what you can do with the platform. We have several new features that enable efficient performance, memory, caching, and AI compute." 

The company says that its 256-core CPU will use the same cooling system as its existing offerings, which implies that its thermal design power will remain in the 350-watt ballpark. 

Teaming up with Qualcomm for AI servers

While Ampere can certainly address many general-purpose cloud instances, its capabilities for AI are fairly limited. The company itself says that its 128-core AmpereOne CPU with its two 128-bit vector units per core (and supporting INT8, INT16, FP16, and BFloat16 formats) can offer performance comparable to Nvidia's A10 GPU, albeit at lower power. Ampere certainly needs something better to compete against Nvidia's A100, H100, or B100/B200. 

So, it teamed up with Qualcomm, and the two companies plan to build platforms for LLM inferencing based on Ampere's CPUs and Qualcomm's Cloud AI 100 Ultra accelerators. There is no word when the platform will be ready, but it demonstrates that Ampere's ambitions do not end with general-purpose computing.

Chiplet plans

Last but not least, Ampere announced the formation of a UCIe working group within the AI Platform Alliance. The company intends to leverage the flexibility of its CPUs with the UCIe open interface technology and incorporate customer-developed IPs into future CPUs, which essentially enable it to build custom silicon for its clients.

TSMC successfully started production of chips on its second generation 3nm-class process technology in the fourth quarter of 2023, meeting its planned milestones. The company is now preparing for mass production of chips on the performance-enhanced version of this node, N3P. This should occur in the second half of 2024, TSMC announced at the European Technology Symposium.

The N3E process entered volume production as scheduled, achieving defect densities comparable to N5 technology when it entered mass production in 2020. That's a good result as TSMC managed to meet the demand from Apple and Huawei back them. TSMC describes its N3E yields as 'great,' which is perhaps evident as the only processor to use N3E for now — Apple's M4 — increased both the number of transistors and operational clockspeed compared to N3-based M3.

"N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at the event. "We have seen great yield performance on customers' products, so they did go to market as planned."

A key detail of the N3E process is its simplification relative to TSMC's original N3 process (aka N3B). By removing some layers that required EUV lithography and completely avoiding usage of EUV double patterning, N3E reduces production costs as well as widens the process window and improves yields. These changes, however, sometimes reduce transistor density and power efficiency, a tradeoff that can been mitigated by design optimizations.

Looking ahead, the N3P process provides an optical shrink of the N3E, and it's showing promising progress as well. It has passed essential qualifications and shows yield performance nearing that of N3E. This next evolution in TSMC's technology portfolio aims to boost performance by up to 4% or cut power usage by about 9% at the same clock speeds, while also enhancing transistor density by 4% for chips with mixed design configurations.

N3P maintains compatibility with the N3E's IP blocks, design tools, and methodologies, making it an attractive option for developers. This continuity ensures that most new chip designs (tape outs) are expected to transition from using N3E to N3P, leveraging the latter's improved performance and cost-efficiency.

The final readiness of N3P for production is scheduled for the latter half of this year, when it enters the HVM (high volume manufacturing) stage. TSMC anticipates immediate adoption by chip designers. Given its advantages in performance and cost, N3P is poised to become popular among TSMC's customers, including Apple and AMD.

While the precise timing for the market debut of N3P-based chips remains uncertain, it's anticipated that major players like Apple will use this technology for its 2025 processor lineup. That includes SoCs for smartphones, PCs, and tablets.

"We have also successfully delivered N3P technology," the TSMC executive said. "It has passed qualification and yield performance is close to N3E. [The process technology] has also received product customer tape outs and will start on production in the second half of this year. Because of [PPA advantages] of N3P, we expect the majority of tape outs on N3 to go to N3P."

Nvidia's post-Blackwell next generation Vera Rubin GPUs for AI and HPC applications will enter mass production in late 2025, according to renowned analyst Ming-Chi Kuo on Medium.com. Nvidia will focus on the power consumption of its data center GPUs with the R100 processors based on the Rubin architecture, as the extreme amounts of power devoured by Blackwell-based processors present a concern for data centers.

Nvidia's Vera Rubin GPUs will be made on one of TSMC's 3nm-class process technology — most likely using a custom version of the performance-enhanced N3P, though that's merely our speculation. They will reportedly adopt CoWoS-L packaging of about 4x reticle size, though the company has not finalized the interposer design at this point, the analyst says. The package will enable Nvidia to equip its R100 GPU with eight HBM4 stacks.

Although Ming-Chi Kuo has excellent track record with predicting Apple's products and plans, he's still an unofficial source. That means, as usual, you should apply the standard application of salt.

One of the design goals for Nvidia's Rubin GPUs is to keep power consumption in check. Nvidia's B200 GPU can be configured to consume up to 1000W of power, with the GB200 solution that consists of two B200 GPUs and one Grace CPU consuming up to 2700W. Such power consumption makes it challenging for data centers to feed and cool down large clusters of these compute GPUs, so Nvidia will have to do something about it. It remains to be seen whether it will actually manage to lower power consumption while tangibly increasing performance compared to Blackwell-based products, or if it will instead focus on performance efficiency.

Nvidia is projected to start mass production of R100 processors in the fourth quarter of 2025, so actual system and rack solutions based on the company's Rubin GPUs will enter production in the first half of 2026, the analyst believes. As a result, we can expect that R100-based machines will hit actual data centers starting in mid-2026 at earliest. However, given the massive interest in AI and recent history, Nvidia could start talking about Vera Rubin at next  year's GTC.

Assuming the information about R100's timing and process technology is correct, it means that Nvidia will stick to its strategy of adopting proven process technologies for its GPUs. By Q4 2025, TSMC will start production of chips on its N2 family of fabrication nodes (2nm-class). These will provide better power, performance, and transistor density characteristics than N3P. By the time N2 is ready, N3P will probably feature lower defect density and reduced pricing (relative to N2), enabling higher yields for Nvidia's near-reticle-size chiplets.

Samsung Foundry is set to detail its third generation process technology featuring gate-all-around (GAA) transistors at the VLSI Symposium 2024 in June. The technology is called SF2, and it will be the company's initial 2nm-class fabrication process. The node is projected to offer significant improvements when it comes to performance and efficiency.

Samsung will outline key details about its SF2 fabrication technology at a session on June 19, 2024. Based on the company's own description, the upcoming node will further refine Samsung's multi-bridge channel field-effect transistor architecture with a unique epitaxial and integration process. This will enable it to increase transistor performance by 11–46 percent and reduce variability compared to an unspecified FinFET-based process technology by 26%, while decreasing leakage by about 50%.

"A product performance aware 3rd generation MBCFET (SF2) is revealed to maximize gate-all-around benefit fully by introducing unique epitaxial and integration process, which overcomes the scaling and GAA structure conflict with a product gain," the description by Samsung reads. "The product major narrow NS transistor was boosted by N/PFET +29/+46%, as well as a wide NS transistor +11/+23%. In addition, through transistor global variation reduction by 26% from FinFET, a product leakage distribution was significantly scaled by ~50%."

Business Korea reports that Samsung is not only pushing technological boundaries but is also strengthening its ecosystem for its 2nm-class fabrication process. The company is working with over 50 intellectual property (IP) partners and holds more than 4,000 IP titles, though for obvious reasons only a handful of them are aimed at GAA nodes in general and SF2 in particular. Meanwhile, earlier this year Samsung and Arm inked a deal to co-optimize Cortex-X and Cortex-A cores for Samsung's gate-all-around transistor-based manufacturing technologies.

Development of Samsung's SF2 process technology's design infrastructure is said to be completed in Q2 2024, which is when the company's chip development partners will be able to start designing products for the production node.

On a related note, Samsung is on track to start making chips using its second generation 3nm-class fabrication process, called SF3, this year. Samsung's first generation 3nm-class node called SF3E was not a particular success, as the company mostly produced cryptocurrency mining chips on this technology. But Samsung hopes its SF3 node will see more widespread usage, with more sophisticated designs including products for datacenters.

The race is on to begin shipping 2nm-class process technology. With Samsung detailing the design specifications this summer, we expect we'll see the first products build on Samsung SF2 in 2025. It will compete with TSMC's 2nm family of nodes, including N2P. Intel Foundry is also working on its 2nm-class Intel 18A node, which could see the first designs ship by the end of 2024. Intel 20A solutions are also in the works and should ship this year. How the various process technologies will ultimately stack up remains to be seen.

TSMC's 3nm fabrication process accounted for 15% of the company's revenue in Q4'23. Only one of TSMC's customers used it at the time: Apple. But as more customers adopt the manufacturing process, 3nm process nodes will account for a considerably larger share of TSMC's revenue, reports ICSmart.cn.

This year TSMC's N3-series nodes — including N3B and N3E — will account for over 20% of the foundry's revenue in 2024, the report claims. Apple currently exclusively uses TSMC's N3B to make its A17 Pro system-on-chip (SoC) for smartphones, as well as the M3-series processors for iMac desktops and MacBook laptops. Later this year, AMD and Intel are expected to adopt TSMC's N3E and, possibly, N3B for their upcoming processors, and 3nm will thus understandably account for a higher portion of TSMC's revenue.

AMD is preparing to launch its new Zen 5-based processors made on 3nm- and 4nm-class process technologies later this year. Apparently, the platform codenamed Nirvana will also use TSMC's 3nm technology and is anticipated to be released in the second half of the year.

Apple's new iPhone 16 series will be equipped with the A18-series processor, and the upcoming M4-series processors for Mac PCs will also be produced using TSMC's 3nm technology, the report says. Production for both major chips is set to commence in the second quarter of this year, according to ICSmart.cn, which shows Apple's continued reliance on TSMC's N3-series node.

Intel is also expected to leverage TSMC's 3nm technology for its Lunar Lake MX SoCs, with mass production scheduled for the second quarter. This marks the first time Intel has entrusted TSMC with the full range of chips for its mainstream consumer platform, the report notes. This collaboration highlights TSMC's expanding role in serving Intel, which also happens to be the company's rival on the foundry market.

With three major customers using TSMC's 3nm family of process technologies, the node will account for even larger portion of TSMC's revenue this year. More companies are expected to adopt TSMC's N3 nodes in 2025, including performance-enhanced N3P, and the report suggests 3nm will account for over 30% of TSMC earnings in 2025.

Nvidia will host its GPU Technology Conference (GTC) next week, where the company is expected to give developers a sneak peek at its next-generation codenamed B100 GPU for AI and HPC applications, reports Reuters. Nvidia is not expected to start shipments of new products for datacenter and client PCs based on the upcoming Blackwell architecture for some time. But Nvidia is to unlikely miss an opportunity to talk about it at its own GTC conference. Nvidia has not confirmed any plans for Blackwell. 

"Don't miss this keynote from Nvidia founder and CEO Jensen Huang," a statement by Nvidia reads. "He will share how Nvidia's accelerated computing platform is driving the next wave in AI, digital twins, cloud technologies, and sustainable computing." 

Nvidia itself calls the upcoming keynote by its chief executive and founder Jensen Huang at GTC 2024 a "transformative moment in AI," which might be a hint that he will indeed demonstrate capabilities of the Blackwell-based B100 compute GPU at the trade show. Indeed, Nvidia's A100 GPU, which is based on the Ampere architecture, was announced during the keynote of Nvidia's GTC in May 2020. The conference was held virtually due to the COVID-19 pandemic. Nvidia's H100 GPU, which is based on the Hopper architecture, was announced during the keynote address at the GTC in March 2022.

Earlier this year Nvidia gave a sneak peak of B100 performance in a document covering its H200 GPU for AI and HPC. Based on the simplistic performance graph demonstrated by the company showed, we could expect a massive performance uplift compared to existing A100 and H100 GPUs. Performance in AI applications depend on many factors, including the number of parameters, performance of a memory subsystem (which depends on its bandwidth and capacity), code optimization and many others, so for now take performance estimates from Nvidia with a grain of salt. 

Nvidia's B100 in particular and Blackwell-based products in general clearly have potential. The new processors are expected to be produced on one of TSMC's N3 (3nm-class) process technologies so Nvidia will be able to increase transistor count (i.e., the number of execution units) and this alone will boost performance of the company's B100 processor. Furthermore, if rumors about Nvidia's B100 are correct and Nvidia opted for a multi-chiplet design, expect a dramatic increase in transistor count and the number of execution units, albeit at the cost of a massive power increase (which is expected to exceed 1,000W). 

The next-generation microarchitecture will inevitably increase performance as well. Finally, B100 will use faster memory than H100 and H200, so expect improvements on this front too. In short, with B100 we could see the biggest generation-to-generation performance gain in the recent years of Nvidia's GPUs.

Nvidia is readying the company's GeForce RTX 50-series (Blackwell) products to rival the best graphics cards. While the launch date is still uncertain, renowned hardware leaker @kopite7kimi claims that based on his information, the memory interface configurations of the Blackwell family will not be too much different from the Ada Lovelace series. Since this is a leak, take it with a grain of salt. We gather from some previously released leaks that the company plans to retain a 384-bit memory bus with its next-generation range-topping GB202 GPU based on the Blackwell architecture.

Nvidia's Blackwell will likely be the company's first family to support GDDR7 memory, whose higher data transfer rates and architectural peculiarities promise to significantly increase performance compared to existing GDDR6 and GDDR6X-base memory solutions. Given that the 1st Generation GDDR7 SGRAM ICs will feature a data transfer rate of 32 GT/s, a 384-bit memory subsystem featuring these chips would offer around 1,536 GB/s of bandwidth, so a 512-bit memory interface will hardly be missed.

Micron says that 16 Gb and 24 Gb GDDR7 chips will be available in 2025, though its roadmap does not indicate whether these devices will be launched simultaneously or 16 Gb will come out earlier. That said, what remains to be seen is whether Nvidia will use 16 Gb or 24 Gb GDDR7 memory ICs with its initial GeForce RTX 50-series graphics boards.

GeForce RTX 50-series Blackwell GPU Memory Configurations*

*Specifications are unconfirmed.

With Nvidia's Blackwell family being at least two or three-quarters away, it is hardly a good business to make predictions by now. Yet, we have outlined possible memory configurations of the GB200-series powered offerings in the table.

For several generations now, Nvidia's top-of-the-range consumer graphics cards have used a 384-bit memory interface (AD102, GA102), which has proven to be optimal from a performance and cost point of view. Cut-down versions of Nvidia's range-topping consumer graphics products featured a 320-bit memory interface, whereas high-end GPUs featured a 256-bit bus (e.g., AD103, GA103, and GA104). Meanwhile, there are also GPUs in performance mainstream segments with a 192-bit memory bus (e.g., AD104, GA106) and a mainstream segment with a 128-bit memory interface (e.g., AD106, AD107, GA107).

While the comment by the leaker indicates the Blackwell family will largely retain memory interface configurations of the current Ada Lovelace family, it should be kept in mind that based on the same leaker, the Blackwell series will lack the GB204 GPU. In contrast, the rumored GB205 will likely not directly succeed AD104.

TSMC is poised to receive a federal incentive exceeding $5 billion for its site in Arizona, according to a Bloomberg report that cites sources familiar with the matter. The U.S. government is not yet ready to announce the incentive because it has to be finalized with the world's largest contract maker of chips, but the sum looks very significant.

It is unclear whether TSMC—which produces chips for AMD, Apple, Intel, Nvidia, and Qualcomm—will receive $5 billion in grants or whether the sum includes grants, loans, and/or loan guarantees. Also, it is unclear whether it will use loans and loan guarantees to build and expand its site near Phoenix, Arizona, or will rather invest its own money.

If the information about $5 billion incentives for TSMC is accurate, then it is highly likely that the report about Intel's award package of around $10 billion is probably also accurate. Also consider the fact that Intel's projects in the U.S. are far more ambitious and costly than TSMC's. For example, Intel is building a brand-new site in Ohio, which is set to cost over $100 billion. 

TSMC's project in Arizona involves an investment of $40 billion to construct two semiconductor fabrication facilities. For the world's No. 1 foundry, this is a way to diversify its geographical footprint and remain adaptable to the trend of onshoring semiconductor manufacturing. However, TSMC's Arizona project has faced multiple setbacks.

TSMC commenced construction of its first new U.S. fab in early 2021, with the aim to start production at the facility in 2024. However, due to a reported shortage of skilled workers in the state, TSMC had to delay the installation of some fab tools and, therefore, push back the production start of the fab to 2025. The production facility — called Fab 21 phase 1 — will use TSMC's 5nm-class process technologies, including N5, N5P, N4, N4P, and N4X. 

In addition to Fab 21 phase 1, TSMC also announced its Fab 21 phase 2 in late 2022. That fab was meant to produce chips on its 3nm-class production process, which includes N3, N3E, N3P, and N3X. While the fab shell is still under construction, installation of equipment for Fab 21 phase 2 was postponed earlier this year because of a lack of U.S. subsidies and demand uncertainties. Consequently, Fab 21 phase 2, which was expected to come online in 2025, is now anticipated to begin operations sometime in 2027 or 2028, a considerable deviation from the original schedule. 

It remains to be seen whether the incentive package will affect TSMC's plans for Fab 21 phase 2.

Samsung Foundry has reportedly decided to rebrand its 2nd generation 3nm-class fabrication technology, known as SF3, to a 2nm-class manufacturing process called SF2, thus requiring a contract to be rewritten. ZDNet notes that the renaming move could be a way for Samsung to simplify process nomenclature and attempt to better compete against Intel Foundry, at least visually. Intel is set to roll out its Intel 20A production node, which is also a 2nm-class technology, later this year.

In response to the story, Samsung issued a statement stating that since the information about the reported renaming of the SF3 manufacturing technology to the SF2 fabrication process did not come from Samsung, it cannot comment on the matter. Meanwhile, Samsung said that it is going to make some foundry-related announcements in due course.

Samsung's process technology roadmap up through 2027 was unveiled in the fall of 2022 and listed a number of nodes, including SF3E, SF4P, SF3, SF4X, SF2, SF3P, SF2P, and SF1.4. Apparently, since early 2024, Samsung has notified its customers about changes in its roadmap and the renaming of SF3 to SF2. The company reportedly went as far as re-sign contracts with customers who intended to use the SF3 production node.

"We were informed by Samsung Electronics that the 2nd generation 3nm [name] is being changed to 2nm," a source told ZDNet. "We had contracted Samsung Foundry for the 2nd generation 3nm production last year, but we recently revised the contract to change the name to 2nm."

Samsung intends to start making chips based on what is now called SF2 in the second half of 2024. Given that a customer reportedly had to rewrite a contract that reportedly only renamed process technology, it would appear that Samsung's SF3 has indeed been renamed to SF2 without any changes — it would be impossible to use a different process technology to make a chip designed for SF3 without reworking the design.

While this information is currently unofficial and doesn't come directly from Samsung, it corroborates a rumor that emerged earlier this year that Samsung was set to make an AI processor for a Japanese startup using its 2nm-class process technology in 2025.

Samsung's SF3 technology uses gate-all-around (GAA) transistors that Samsung brands as Multi-Bridge-Channel Field Effect Transistors (MBCFET). SF3 (now SF2) does not feature a backside power delivery network (BSPDN), a major disadvantage compared to Intel's 20A process technology that introduces both GAA transistors and a backside power delivery network for higher performance and energy efficiency.

Samsung Foundry has reportedly communicated this change to its customers and partners since the start of 2023, following discussions that began in late 2022. If the process formerly known as SF3 is now being renamed to SF2, we suspect further name changes will cascade down Samsung's roadmap and that the former SF2 node will get a new name as well.

Update 3/6/2024: Added Samsung statement.

Although Samsung Foundry was the first chipmaker to adopt gate-all-around (GAA) transistors for its SF3E (3nm-class, early) fabrication technology, it will only adopt a backside power delivery network (BSPDN) starting from its SF2 (2nm-class) manufacturing process, according to a report from Chosun.com. 

The report claims that promising results obtained with backside power delivery led to Samsung's rethinking of implementing BSPDN into a commercial process technology. The company allegedly planned to introduce a backside power delivery network with its 1.7nm-class fabrication node but will pull it in and introduce it with the SF2 process due in 2025, based on the company's roadmap. There is a major catch with the report, though: Samsung's current public roadmap does not include any 1.7nm-class nodes and only contains SF2, SF2P, and SF1.4 technologies. 

Samsung has implemented backside power delivery for two Arm-based test chips and achieved a 10% and 19% die area reduction without disclosing the process node, according to the company's paper presented at the VLSI Symposium in mid-2023. Typically, backside power delivery enables thicker, lower-resistance wires, which can deliver more power to enable higher performance and save power. Samsung's paper noted a 9.2% reduction in wiring length, enhancing performance. Additionally, the paper indicates that backside power delivery offers such benefits as a 3.6% Fmax improvement, a 2.4% standard block area reduction, and a 1.6% standard block performance improvement.

The work was not a part of Samsung's and Arm's ongoing collaboration to co-optimize Cortex-A and Cortex-C cores for Samsung's SF2 (2nm-class) process technology, but given the results achieved by Samsung, it could end up being a major part of the project. 

If the report is accurate, pulling in the introduction of a backside power delivery network to SF2 will make the process technology significantly more competitive against Intel's 20A and 18A fabrication technologies in 2025, as well as TSMC's N2P process in 2026 – 2027.

Meanwhile, the lack of BSDPN in SF3 and SF3P will certainly limit performance, power, and transistor density of these nodes compared to competing offerings. While lower peak performance, power, and transistor density may not be a huge disadvantage for some designs, it will inevitably be a drawback for things like smartphones and data center chips.

TSMC founder and industry icon Morris Chang says that customers have approached him to build up to ten new fabs for AI processors, an incredible request that speaks to an insatiable demand. The request isn't entirely surprising, as the demand for processors used for AI applications is booming, and it is well known that market leader Nvidia cannot satisfy it. Meanwhile, the amount of AI compute performance available to companies like OpenAI appears insufficient, which is why companies are demanding more processors from existing suppliers, and some are even planning to build their own silicon.

"They are not talking about tens of thousands of wafers," said Morris Chang, the founder of TSMC, at a conference in Japan, reports Nikkei. "They are talking about fabs, [saying] 'We need so many fabs. We need three fabs, five fabs, 10 fabs.' Well, I can hardly believe that one." The report says Chang predicts demand for AI processors to be in the middle, "between tens of thousands of wafers and tens of fabs."

TSMC is one of a few companies on the planet that builds semiconductor manufacturing facilities that have a production capacity of around 100 thousand wafer starts per month. These 'Gigafabs' tend to produce processors using a variety of advanced process technologies. Running such large plants allows TSMC to reuse expensive wafer fab equipment for different process nodes, which greatly optimizes utilization rates and costs.

But a Gigafab costs a lot of money: a large 3nm-capable fab may cost well over $20 billion when fully built and equipped, and it requires years of construction. Meanwhile, TSMC's 2024 capital expenditure (CapEx) budget is between $28 billion and $32 billion, so the company isn't building multiple Gigafabs every year. Building ten leading-edge fabs would have cost well over $200 billion, and that does not include the cost of supporting the supply chain and infrastructure. Such a huge sum is significantly beyond TSMC's investing capabilities. 

This is perhaps why we are hearing rumors that Sam Altman, chief executive of OpenAI, is trying to raise trillions to build a network of fabs to be run by leading chipmakers that would produce a sufficient amount of AI processors. While the plan looks rather fantastic itself, it would hardly be economically viable. 

Developers of advanced processors for AI and HPC tend to use leading-edge process technologies for their parts, and typically, these processors are produced for two or three years. After that, they move to new nodes. If companies like TSMC build an excess of leading-edge capacity just to meet immediate demand from the AI sector, they might end up with an excess of advanced capacity that has not been fully depreciated (and it is impossible to depreciate a fab in just a few years) several years later, which will lead to losses in the foundry sector.

Contract makers of chips certainly know that, so it isn't likely we'll see 10 new leading-edge fabs built just for AI chips any time soon. However, we can expect that production will increase within rational limits. 

Morris Chang, the founder of TSMC, has forecasted a resurgence in Japan's semiconductor industry with the inauguration of TSMC's first chip manufacturing facility in the country. He believes that this new fab will be a catalyst for revitalizing Japan's once-dominant chipmaking sector and enhancing global chip supply resilience, reports Nikkei. Meanwhile, Japan is stepping up its support for TSMC by offering an additional ¥732 billion ($4.86 billion) in subsidies to build a second semiconductor factory, reports Reuters. 

In the late 1980s, Japan was at the forefront of the global semiconductor market, boasting six of the top 10 chipmakers worldwide. However, a series of challenges, including trade disputes with the U.S., missed opportunities during the PC revolution, and insufficient investment, led to a decline in its industry leadership. Despite this, Japanese firms like Sony, Renesas, and Kioxia continue to hold significant market shares in specific segments such as image sensors and 3D NAND flash memory chips.

Chang's optimism for the new TSMC plant in Japan is rooted in his positive experiences with chip production in the country dating back to 1968 when he established a joint venture with Sony for Texas Instruments. He praised Japan's historical production quality and expressed hope for achieving high yields at TSMC's new fab, despite acknowledging the challenge posed by TSMC's already high yields in Taiwan.

The demand for chip production capacity is surging, particularly driven by the artificial intelligence (AI) boom. According to Chang, AI chipmakers are seeking not just tens of thousands of wafers, but multiple new fabs with formidable semiconductor manufacturing capacity. 

The Japanese government, represented by Minister Ken Saito, has shown strong support for TSMC's investment, viewing it as a model for semiconductor industry growth. The new plant is already having a positive impact on the local economy in Kyushu, offering higher-than-average wages and promising to contribute to the region's economic development.

The extra funds to be provided by the Japanese government are intended to help TSMC establish its second fab in Japan, adding to the subsidies already provided for TSMC's first fab in Japan. The new fab will focus on producing chips using more advanced production nodes and these chips could be used for AI applications and autonomous vehicles, which is crucial for Japan's goal of maintaining a reliable semiconductor supply chain, producing chips for automotive and other industries domestically, and become a global leader in chip production. Meanwhile, the Japanese government's latest financial commitment could push the total subsidies for TSMC beyond the 1 trillion yen mark.

Design collaboration between the IP developers and foundries is crucial for maximizing performance and minimizing power consumption of circuits. On Tuesday, Arm and Samsung announced that they would jointly optimize the design of Arm's next-generation high-performance Cortex-X and Cortex-A cores for Samsung's upcoming process technologies that rely on gate-all-around (GAA) multi-bridge-channel FET (MBCFET) transistors.

The collaboration is focused on optimization of Arm's Cortex-A and Cortex-X general-purpose CPU cores for Samsung's next-generation 2nm-class process technology, though the companies does not disclose whether they intend to tailor Arm's IP for Samsung's SF2 production node expected in 2025 or the SF2P fabrication process projected to arrive in 2026.

Arm and Samsung said that they would tailor Arm's Cortex-A and Cortex-X cores for a wide range of applications, including "next-generation datacenter and infrastructure custom silicon," smartphones, and various chiplet-based solutions that need high-performance general-purpose CPU cores.

"Optimizing Cortex-X and Cortex-A processors on the latest Samsung process node underscores our shared vision to redefine what's possible in mobile computing, and we look forward to continuing to push boundaries to meet the relentless performance and efficiency demands of the AI era," said Chris Bergey, SVP and GM of the Client Business of Arm.

As a result of the joint work between Arm and Samsung, customers of the two companies will be able to license Samsung 2nm-optimized versions of Cortex-A or Cortex-X cores, depending what they need, for their custom designs. This will simplify the development process and speed up time-to-market, which potentially means that we might see Samsung-made 2nm designs for datacenter and adjacent applications rather sooner than later. For now, however, Arm and Samsung are tightlipped about when they expect the first fruits of their collaboration to be available for their joint customers.

Unlike FinFET transistors, which are widespread today, GAA nanosheet-based transistors can be tuned in various ways to maximize performance, optimize power consumption, and/or maximize transistor density. Therefore, we expect quite promising results from this collaboration between the two technology giants.

While Arm's Cortex-A and Cortex-X cores are similar in terms of architecture, Cortex-X tend to have performance optimizations that allow them to run faster. These cores should realize significant benefits from the design-technology co-optimization (DTCO) by Arm and Samsung when they arrive, some time in the next couple of years.

Intel's plan to move 'oversized equipment' for its new fab in New Albany, Ohio, is being delayed, reports NBC4i. The move, which was supposed to start this past weekend, has been pushed back to no earlier than February 17 because of bad weather and the huge size of the 'overweight and oversized loads' of the equipment. The project to move the equipment is expected to last over nine months, meaning this phase of Intel's construction could be done near the end of 2024. There isn't a firm indication of how much work remains to be done at the site after the equipment is delivered. Still, it clearly will take much longer for the plant to become operational: Intel recently confirmed that its initial plans to begin producing chips in Ohio in 2025 were too optimistic. 

Intel needs to transport and install plenty of fab tools at the site in the coming months. The current project involves transporting 18 oversized loads on trailers over 200 feet long, which could take up to nine months to finish. It is unclear which tools Intel will transport, but since the site in Ohio is brand new, it could be anything from advanced lithography machines to turbine generators. 

The equipment is vital for constructing Intel's fab and was initially set to be transported through Franklin County starting Saturday. However, the Franklin County Engineer’s Office has now delayed the start date. Groveport police mentioned that the move might even get pushed to late February or early March, showing there's still some uncertainty on when the move will happen. 

Weather issues, especially a flooded dock in Manchester, Adams County, are partly to blame for the delay. This dock, where the equipment will be taken off barges, is currently underwater, complicating the start of the transport. 

Because the trailers carrying the loads are so large, they cannot go under overpasses, which is why the move requires using back roads, and the exact route they will take has not been announced yet. With a project this big expected to last nine months, the delay in getting started is a notable setback. 

While the setback of a few weeks is rather minor given the long three- to five-year timelines associated with building a modern fab, as Intel recently told us, the company is already facing more significant setbacks on the project.

"While we will not meet the aggressive 2025 production goal that we anticipated when we first announced the selection of Ohio in January 2022, construction has been underway since breaking ground in late 2022, and we have not made any recent changes to our pace of construction or anticipated timelines," an Intel representative told Tom's Hardware. "Typical construction timelines for semiconductor manufacturing facilities are 3-5 years from groundbreaking, depending on a range of factors."

TSMC has been the world's number one contract maker of chips for years, but its earnings have long been significantly below those of Intel and other leading memory makers. However, a lot has changed in recent years, and in 2023, TSMC's revenue exceeded that of Intel and Samsung, as observed by Dan Nystedt, a Taiwan-based analyst. TSMC also leads in operating profit, showing that the company continues to rake in cash as the world's foundry. 

Nystedt compiled the numbers from calendar-year revenue figures, not fiscal-year performance. Also, it's important to note that these figures also include revenue from other sources within each company and aren't comprised solely of income from manufacturing silicon.

As Nystedt notes, TSMC is now the largest chip semiconductor company in the world of any kind. Despite a challenging year, TSMC earned $69.3 billion in 2023, significantly more than Intel, whose revenue dropped to $54.23 billion, and Samsung, which earned $50.99 billion. Based on fourth-quarter guidance, Nvidia could end 2023 with revenue of over $58 billion, the analyst estimates, so it will outperform both Intel and Samsung, but not TSMC. 

TSMC is a newcomer to this top spot, as historically, it has lagged Intel and Samsung despite being the world's largest foundry. TSMC's revenue began to increase rapidly in 2020, largely because of the coronavirus pandemic and increased demand for everything digital, including PCs and game consoles. And since modern production nodes are generally expensive to use, TSMC's revenues are indeed increasing. Since TSMC has pulled ahead of Intel and Samsung in terms of process technologies, it can enjoy selling its services at a hefty premium, which definitely helps with revenue.

Intel led the semiconductor industry for decades, from 1992, when it dethroned NEC, to 2017, when Samsung outperformed it by a significant margin. But Samsung's semiconductor revenue depends on 3D NAND and DRAM memory prices, whereas Intel's revenue largely consists of logic products, such as CPUs for client and data center applications. Additionally, at this point, many of Intel's products are made by TSMC. 

It is noteworthy that TSMC does not develop its own processors but instead makes some of the world's most advanced chips for fabless developers, such as AMD, Apple, Nvidia, Qualcomm, and many others. Apparently, this formula is working very well, at least for now. What remains to be seen is whether Intel will manage to reclaim the crown years down the road when its Intel Foundry Services division starts taking a piece of TSMC's market by getting orders to make chips using its leading-edge process technology.

We reached out to Intel to confirm a report that the company is pushing back the timeline for its $20 billion fabs in Ohio to late 2026 due to market issues and delays in U.S. government funding, a story that was originally reported by the Wall Street Journal. The Intel representative neither confirmed nor denied the delay and also didn't provide a firm date for the fab opening. However, the representative did indicate that it is normal for big fab projects to require three to five years. 

"While we will not meet the aggressive 2025 production goal that we anticipated when we first announced the selection of Ohio in January 2022, construction has been underway since breaking ground in late 2022, and we have not made any recent changes to our pace of construction or anticipated timelines," an Intel representative told Tom's Hardware. "Typical construction timelines for semiconductor manufacturing facilities are 3-5 years from groundbreaking, depending on a range of factors." 

Relying heavily on government funds, Intel's first two fabs at its Ohio site, nicknamed the 'Silicon Heartland' by Intel CEO Pat Gelsinger, were originally set to start producing chips next year. But now the project is expected to wrap up construction by late 2026 or even later, the report claims, citing two sources familiar with the matter. WSJ's sources cite two reasons for the postponement: challenges with demand and the slow rollout of the U.S. government funding under the CHIPS Act. 

Intel started to build the first two fabs at its Ohio site in September 2022. Normally, it takes about a year and a half to construct a semiconductor production facility shell and between a year or two (depending on the size of the facility) to install wafer fab tools into that shell. That said, Intel's original plans to start making chips at its Ohio fabs in 2025 were more than reasonable.  

"We remain fully committed to the project and are continuing to make progress on the construction of the factory and supporting facilities this year," the representative explained to Tom's Hardware. "As we said in our January 2022 site-selection announcement, the scope and pace of Intel's expansion in Ohio may depend on funding from the CHIPS Act and other business conditions." 

Currently, 800 people are working on the project, and it is expected that this number will grow significantly by the end of the year, WSJ claims. Yet, it is unclear when the construction is set to be complete and when Intel plans to initiate equipment move-in. 

Intel intends to make its Ohio site a $100 billion semiconductor production hub. The site is projected to host multiple fabs built on Intel's own money, subsidies of the Ohio state, and grants from the government under the CHIPS Act. Ohio has already shown its support with $600 million in grants (on the condition that the fabs will be completed by December 31, 2028) that are available to Intel and which can be used to fund construction costs. 

The delay in the project, while a setback, is part of dealing with the realities of strategic financial planning for large-scale manufacturing. In essence, Intel's Ohio project delay appears to be a strategic response to external funding delays and market dynamics. Intel remains committed to the project, seeing it as a key piece in strengthening its manufacturing prowess in particular and the U.S. semiconductor industry in general.

It is noteworthy that Intel is not the only company that's been said to delay its large-scale fab projects in the U.S. Both Samsung Foundry and TSMC had to delay deployment of their fabs in Texas and Arizona for various reasons.

Samsung Foundry has begun trial production of chips on its 2nd Generation 3nm-class process technology known as SF3, reports Chosun, citing unnamed industry sources. The company reportedly aims to achieve a yield of over 60% within the next six months. The information should be taken with a pinch of salt since it comes from an unofficial source. Meanwhile, the SF3 production start is a big deal for Samsung and the industry.

Samsung is reportedly testing the performance and reliability of chips made on its SF3 node. Meanwhile, the first product that Samsung reportedly plans to use its SF3 for is its application processor for wearables, which will be used for the company's upcoming Galaxy Watch 7. Also, the company is expected to use the production node for its Exynos 2500 system-on-chip for Galaxy S25-series smartphones due next year.

Samsung believes that its SF3 fabrication will offer greater design flexibility by enabling different gate-all-around (GAA) transistor nanosheet channel widths within the same cell type. This allows it to achieve lower power and greater performance for circuits that need it and increase transistor density by optimizing designs. Meanwhile, Samsung's 1st Generation SF3 is reportedly only used for tiny cryptomining chips. 

Samsung's official position, published in November 2023, was that the company was set to start high-volume manufacturing (HVM) of chips on its SF3 (2nd Generation 3nm-class) production node in the second half of 2024. By now, Samsung Foundry should have started trial production on SF3, which corroborates the report.

Meanwhile, the report mentions a 60% yield target for an alleged hypothetical test chip without disclosing other targets such as transistor count, die size, performance (i.e., clocks), power consumption (i.e., leakage) as well as its peculiarities like cell libraries (e.g., high-performance, high-density, etc.), and SRAM to logic ratio, to name a few.  

Typically, companies fight for defect density (defects kill circuits and make chips unsellable) and performance variability (chips that do not hit performance or power targets are also unsellable).  

Meanwhile, die size, performance, and power targets for a tiny application processor for smartwatches, a decent SoC for smartphones, and a datacenter-oriented processor are entirely different. If a small chip's yield is 60%, it means the defect density of a process technology is too high and, in the case of modern process technologies, commercially unacceptable. Meanwhile, if a chip of a reticle size (858mm^2) yields at 60%, this might be considered reasonable, yet might call for design or process technology adjustments. Typically, foundries and chip designers tweak both to increase yields. 

With all the uncertainty concerning Samsung Foundry's SF3 yield targets, take the whole report with a grain of salt. Meanwhile, the fact that SF has started risk production using SF3 was essentially confirmed by Samsung itself.

TSMC, the world's top foundry, is set to delay the deployment of its second fab in Arizona by at least a year compared to the initial schedule, the company said this week. Furthermore, the company is also backtracking on its prior commitments of which nodes the factory would produce, so now it isn't clear whether the Fab 21 phase 2 will make chips on its 3nm process technology or a different node. The delays and ambiguities about the project stem from uncertainties with demand as well as U.S. government decisions concerning subsidies.

"The second fab shell is under construction, but what technology [to use] in that shell is still under discussion," said outgoing chairman Mark Liu at the company's conference call with analysts and investors (via SeekingAlpha). "I think that also has to do with how much incentives that fab, the U.S. Government can provide. […] The current planning [for the fab] is '27 or '28, that will be timeframe."

When TSMC announced plans to increase investment in its Arizona site to $40 billion in total (up from $12 billion for 5nm/4nm-capable Fab 21 phase 1) in late 2022, it said that its Fab 21 phase 2 would be capable of making chips using its N3 family of process technologies (3nm-class) and would come online in 2026. It also indicated that the two Arizona fabs would feature a capacity of over 600,000 wafer starts per year (50,000 wafer starts per month).

Uncertainties with subsidies from the U.S. government under the CHIPS Act, as well as demand from its clients, apparently made the company delay the fab's deployment by at least a year. As a result, now that the fab is coming online in 2027 or even 2029, and the company now questions whether it needs to build a 3nm-capable fab at the time, or rather equip it to make chips on its N2 (2nm-class) production technology or more advanced. Or perhaps, TSMC could opt for a more mature fabrication process.

"To be honest, most of the fab in overseas, what technology is being set up, really, it is a decision of customers' demand in that area at that timing," Liu said. "So, nothing is definitive, but we are trying to optimize value for the overseas fab for TSMC."

There is good news, though. After facing multiple setbacks with Fab 21, its first advanced fab in the U.S., TSMC now firmly states that the facility is coming online in the first half of 2025. 

"We are well on track for volume production of N4, or 4nm process technology, in the first half of 2025 [in Arizona] and are confident that once we begin operations, we will be able to deliver the same level of manufacturing quality and reliability in Arizona as from our fabs in Taiwan," Liu stressed. 

Along with introducing its IDM 2.0 paradigm in 2021, which involves using both internal and external production capacities, Intel also outlined its impressive plan for 'five nodes in four years,' now dubbed '5N4Y.' The culmination of that impressive project is supposed to be the company's 18A (1.8nm-class) technology, which is scheduled to become production-ready in "early 2025." Little is known about the company's plans beyond 18A, but now it says it will reveal its new roadmap in February. 

Intel plans to host its IFS Direct Connect event on February 21, where Intel Foundry Services will discuss its roadmap beyond 5N4Y. Featured speakers at the event are Pat Gelsinger, Chief Executive of Intel; Stu Pann, General Manager of IFS; Keyvan Esfarjani, General Manager of Intel's Supply Chain and Operations, as well as Ann Kelleher, Executive Vice President responsible for Process Technology Development at Intel.

If you're interested in the process technologies that are set to come after 18A, Ann Kelleher's presentation is the one to watch. What to expect from Intel beyond 18A is up in the air, but we expect the company to continue building on its latest innovations. Intel's 20A introduces RibbonFET gate-all-around (GAA) transistors and PowerVia backside power delivery network (BSPDN), and 18A refines both technologies. At the recent IEDM event, the company outlined a further evolution of BSPDN, so expect one of Intel's process technologies after 18A to use this feature. GAA will obviously evolve as well, so we expect Intel to innovate in this realm, too.

Meanwhile, the disparity in the requirements of chips for different applications necessitates Intel to specialize in various process technologies, something that Intel does already. For example, Intel 3 offered a denser high-performance library and increased drive current, which is just what the doctor ordered for data center-class processors. Whether this approach will be extended and Intel will offer other specialized nodes remains open to question.

Intel describes the IFS Direct event as follows:

"Hear from Intel leaders, technologists, and partners as they share details of our strategy, process technology, advanced packaging, and ecosystem. Learn how Intel Foundry Services can help you build your silicon designs leveraging Intel’s resilient, security, and sustainably oriented, source of supply." 

The career profiles of the event speakers indicate that Intel plans to disclose both the technical and executive directions of Intel and IFS. However, the nature of the event implies that its focus will be squarely on Intel Foundry Services operations.

Intel has quite literally bet the company on the rapid development of its production nodes as it looks to deliver five new nodes in a mere four years. Intel is now poised to bring its 20A (2nm-class) and 18A (1.8nm-class) fabrication technologies to market ahead of competing processes from TSMC and Samsung Foundry. The company's chief executive, Pat Gelsinger, believes that Intel 18A's tech — which will be used for mass products in the second half of 2024 — is 'a little bit ahead' of TSMC's N2 (2nm-class), which is coming in the second half of 2025. Intel will also make this tech available to its foundry (IFS) customers, providing the company with a strategic advantage in both its own products and its foundry operations.

"I have a good transistor; I have great power delivery," Gelsinger said in an interview with Barron's. "I think I am a little bit ahead of N2, TSMC's next process technology in time."

Intel's 20A and 18A process technologies bring two major innovations: gate-all-around (GAA) RibbonFET transistors and PowerVia backside power delivery network (BSPDN). 20A is projected to be a relatively short-lived node, allowing Intel to learn all the peculiarities of GAA and BSPDN; Intel expects to re-establish unquestioned leadership in the semiconductor industry with 18A. Clearly, the company's hopes are pinned on this node.

Intel now says that 18A silicon goes to the fab in Q1 2024, which is in line with expectations that the first products based on the process technology will be available in the second half of 2024. In contrast, TSMC is set to start making chips on its N2 process technology sometime in the second half of 2025. Additionally, while TSMC's N2 features nanosheet GAA transistors, it still uses less-performant traditional power delivery.

TSMC still believes that its performance-enhanced N3P technology, due in 2024, will offer comparable power, performance, and transistor density to Intel 18A, and it claims that N2 will be better across the board than N3P and 18A.

But Gelsinger believes that 18A will offer considerable benefits compared to N2, particularly when it comes to performance — enabled by both enhanced RibbonFET and backside power.

"I think everybody is looking at the transistor of TSMC’s N2 versus our 18A," said Gelsinger. "It is not clear that one is dramatically better than the other. We will see who is best. But the backside power delivery, everybody says Intel, score. You are years ahead of the competition. That is powerful. That is meaningful. It gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance."

Gelsinger also implied that TSMC's N2 could end up being a very expensive production node, which will give Intel's 20A and 18A a chance to land foundry orders from customers seeking higher cost-efficiency without hurting corporate margins.

Increasingly sophisticated wafer fab tools are needed to produce chips on leading-edge process technologies, thus intensifying costs with each new node. Analysts from International Business Strategies believe that the situation will worsen at 2nm, with chip costs growing by around 50% compared to 3nm processors, reports Nikkei, ultimately resulting in a $30,000 price tag for each wafer of 2nm chips.

IBS estimates that a 2nm-capable fab with a capacity of roughly 50,000 wafer starts per month (WSPM) costs around $28 billion, up from around $20 billion for a 3nm fab with a similar production capacity. The cost increase will be driven by the increased number of EUV litho tools required to maintain a 50,000 WSPM capacity for a 2nm-class technology. This will significantly increase production costs per wafer and per chip, which will inevitably affect companies that use leading-edge fabrication technologies, such as Apple, which is currently the only company that mass produces processors for smartphones and PCs using TSMC's latest N3B (3nm-class fabrication process). 

Expand the tweet above to see the relevant predictions. IBS further estimates that it will cost Apple around $30,000 to process a single 300mm wafer using TSMC's N2 fabrication process when it is introduced in the 2025 – 2026 timeframe, which is up from around $20,000 for an N3-based wafer, as estimated by IBS and some other analysts. Such a tangible cost-per-wafer increase will inevitably increase the per-chip cost by a similar margin.

However, IBS seems to be a little dramatic with its per-chip cost estimate. The company believes that Apple's current 3nm per-chip cost is around $50, but it does not define the chip's die size. Arete Research estimates that Apple's latest A17 Pro system-on-chip for smartphones has a die size between 100mm^2 and 110mm^2, which is in line with die sizes of the company's previous-generation A15 (107.7mm^2) and A16 (around 5% larger than A15, so, approximately 113mm^2) SoCs. If Apple's A17 Pro has a die size of 105mm^2, then one 300-mm wafer can fit 586 of these, which brings their cost to approximately $34 at an unrealistic 100% yield and $40 at a more realistic 85% yield.

International Business Strategies further estimates that a 2nm 'Apple chip' will cost around $85, up from $50, which implies rather low yields. At $30,000 per wafer and 85% yield, a single 105mm^2 chip would cost $60, but this is a very rough estimate.

In contrast, a projection from earlier this year indicated a cost of $25,000 per 2nm wafer at TSMC's fabs, reminding us that estimates can vary significantly. 

Even with very rough estimates about 2nm fab costs and wafer costs, it is clear that chips made using a 2nm node will be more expensive than processors produced on a 3nm-class process technology. That said, expect companies like AMD and Intel to accelerate the adoption of multi-chipset designs comprised of chiplets made on different nodes in the coming years, thus defraying the costs associated with leading-edge nodes. Meanwhile, it is likely that smartphone processors will retain monolithic designs for a while as advanced packaging costs are still quite high.

Despite the lack of access to advanced chip production equipment due to U.S. sanctions, China-based SMIC remains committed to developing post-7nm fabrication processes, such as 5nm and 3nm, according to a report from Nikkei. 

Having developed its 2nd-gen 7nm-class process technology, which is good enough for smartphone processors, the report claims that SMIC has now dedicated a research and development team to working on 5nm- and 3nm-class process technologies, citing two sources with knowledge of the matter. The team is led by co-CEO Liang Mong-Song, who used to work at TSMC and Samsung and is considered one of the best semiconductor scientists and executives in the industry.

"There is not any smarter scientist or engineer than that guy," Dick Thurston, former chief legal counsel at TSMC, told EE Times earlier this year. "He is really one of the more brilliant minds I have seen in semiconductors."

SMIC has come a long way from being a small foundry in China; today it is the industry's No. 5 contract maker of chips. Amid growing tensions between the U.S. and China, the company was listed on the U.S. Department of Commerce's Entity List and lost access to leading-edge wafer fab tools, severely slowing its progress and adoption of new process technologies.

As a result, SMIC couldn't get extreme ultraviolet (EUV) lithography tools from ASML, so the company's second-gen 7nm-class node relies solely on deep ultraviolet (DUV) lithography. This isn't an incredible feat, given that TSMC's N7P process node also doesn't use EUV. For now, ASML's Twinscan NXT:2000i lithography machines are the best tools SMIC has, and they can etch production resolutions as fine as 38nm. This level of precision is adequate for printing 38nm metal pitches using double patterning, which is suitable for 7nm-class nodes. At 5nm, metal pitches shrink to 30 – 32nm, and at 3nm, they drop to 21 – 24nm, according to ASML and IMEC. Therefore, EUV becomes crucial for these nodes.

But using lithography tools with ultra-fine resolution (13nm for Low-NA EUV) is not the only path to achieving ultra-small feature sizes — multi-patterning is an option, but this is a complicated process that lengthens cycle times, can affect yields, wears fab equipment, and certainly increases costs. However, without EUV tools, SMIC simply has no choice but to use triple, quadruple, or even quintuple patterning to achieve lower resolutions. 

Thurston believes that under co-CEO Liang Mong-Song, SMIC can produce (if it is not already producing) 5nm chips in large quantities without using EUV tools. We have heard mentions of 5nm-class process technology from SMIC several times already, so we would consider information about this potential node as 'there is no smoke without fire.' However, this is the first time we have heard about SMIC's possible ability to design a DUV-only 3nm-class fabrication process from a largely reliable source. 

A German budget crisis threatened the federal funding of Intel's, TSMC's, and Wolfspeed's fabs as well as multiple other high-tech projects in the country. But as the year comes to an end, the coalition came to an agreement to fund building up these important facilities and this week the government formally announced that investments have been secured.

"The agreement of the 'traffic light coalition' is good for East Germany," said Michael Kellner, Parliamentary State Secretary at the Federal Ministry of Economics, reports Zeit Online (via ComputerBase). "The investments for the transformation projects are secured. With these funds, we secure our future economic power. This benefits our entire country, people like the middle class." 

Previously, Chancellor Olaf Scholz (SPD), Economics Minister Robert Habeck (Greens), and Finance Minister Christian Lindner (FDP) had announced an agreement in the budget dispute, according to Zeit.

"It is an important signal that the investments for the semiconductor industry in East Germany are secured," said Carsten Schneider, the Federal Government's Commissioner for the New Federal States. "Both Intel in Magdeburg and TSMC in Dresden can rely on the Chancellor's commitments."

Germany has pledged $22 billion in incentives to chipmakers, including Intel, TSMC, and Wolfspeed, who agreed to build new fabrication plants in the country. However, the approval of Germany's 2024 Federal Budget has experienced delays due to a ruling by the Federal Constitutional Court, which ruled that the reallocation of unused funds from the Coronavirus crisis to the Climate and Transformation Fund in 2022 was unconstitutional. The German government had planned to use this fund to subsidize chip production, leading to a postponement in the finalization and approval of the budget.

This judicial decision has cast some uncertainty over the funding. Yet, both federal and regional governments remain committed to supporting the establishment of the new fabs, which is why they agreed to fund the projects.

The codename of Nvidia's post-Blackwell GPU architecture could be Vera Rubin, if a new statement by hardware leaker @kopite7kimi is correct. Given Nvidia's new and more aggressive introduction cadence, Nvidia's Rubin GPUs for artificial intelligence (AI) and high-performance computing (HPC) are expected to be released in 2025. However, it is unclear whether Nvidia's client GPUs are set to adopt the same architecture.

@kopite7kimi says two GPUs belong to the Rubin family, the R100 and the GR200. The R100 is likely the first product based on the 'big' Rubin GPU for AI and HPC workloads, whereas the GR200 is likely a refined Rubin GPU akin to the GH200 GPU launched earlier this month. It is close to impossible to guess the characteristics of these GPUs, given that they are two years away and their target specifications are only being finalized now.

In fact, we would not even try to guess whether Nvidia plans to make Rubin GPUs at its traditional foundry partner TSMC (using its N3P or N3X fabrication process), Intel (using its 18A manufacturing technology), or Samsung (using its SF3 or SF3P production node).

Nvidia's newly unveiled roadmap indicates that from now on, the company will update its data center-grade GPUs aimed at AI and HPC workloads once a year, not once in two years as previously. As a result, the company aims to release codenamed Blackwell products in 2024, and codenamed Rubin products in 2025. It is unclear whether the company also plans to update its client GPUs once a year, like in the good old days of the 2000s and 2010s. To that end, while we expect Blackwell to power some of the best graphics cards in 2024 and 2025, we suspect the Vera Rubin architecture may not make it to the consumer market — it would be more like the Volta architecture.

It is noteworthy that Vera Rubin will be the first of Nvidia's architectures named after an astronomer. Through her observations of the rotation rates of galaxies in the 1960s and 1970s, Rubin provided strong evidence for the existence of dark matter, which was a major contribution to the field of physics. Previously Nvidia named its GPU architectures only after physicists, including Fahrenheit, Celsius, Kelvin, Rankine, Curie, Tesla, Fermi, Kepler, Maxwell, Pascal, Volta, Turing, Ampere, Ada Lovelace, Hopper, and Blackwell.

The German government is committed to supporting the construction of chip fabs by Intel, TSMC, and Wolfspeed, despite facing financial challenges due to a budget crisis, reports HardwareLuxx. In fact, Intel and Wolfspeed have already received firm funding commitments from the government.

"The decisive sentence is, all projects that we have conceived must be made possible," said Robert Habeck, Minister of Economy, emphasizing strong support for the fab projects.

Germany has committed $22 billion in incentives to semiconductor companies such as Intel, TSMC, and Wolfspeed, leading to commitments to build new fabs in Germany. However, the 2024 Federal Budget in Germany is facing delays due to a decision by the Federal Constitutional Court, which found reallocation of unspent Corona crisis funds to the Climate and Transformation Fund in 2022 unconstitutional. The German government had intended to use this fund to subsidize chip manufacturing, which is why they had to postpone the final discussions and approval of the budget.

This court ruling has introduced uncertainties into the funding, but it looks like both federal and local authorities are dedicated to support the construction of new fabs. There is a strong consensus among political parties and state governments about the importance of these semiconductor projects for the future of German industry.

The government is now looking for ways to fund these projects. They are considering using the current federal budget and possibly suspending the debt brake for this and next year. They are also mulling cutting budgets in other departments. In addition, Saarland, which promised subsidies to Wolfspeed, is facing constitutional legal challenges with its credit-financed fund that demand revisions to its financial planning.

To address these financial challenges, the Bundestag approved a supplementary budget for 2023, allowing for the raising of an additional €45 billion. However, this amount is still not enough to cover the total cost needed for these semiconductor projects and other spending, indicating that the German government still has financial hurdles to overcome.

With the multi-tile designs of its client CPUs, Intel can improve its built-in graphics cores and bring their capabilities and performance closer to those of standalone GPUs. Starting from Arrow Lake processors due next year, its new built-in Xe-LPG Plus GPUs will gain eXtended Matrix Extensions (XMX) support, a technology for advanced XeSS upscaling features as well as for acceleration of artificial intelligence workloads, reports Coelacanth Dream.

Intel is set to start rolling out its Xe-LPG GPU microarchitecture, starting with Meteor Lake processors. Xe-LPG represents the company's 2nd Generation low-power Xe architecture that is further enhanced for gaming and is therefore closer to the Xe-HPG microarchitecture used for discrete GPUs. But as it turns out, even the Xe-LPG does not support XeSS. This is not going to substantially hurt the product as XeSS can work without XMX, and Meteor Lake has a built-in AI accelerator, which Intel aggressively promotes among independent software vendors (IHVs) anyway.

But Intel will still add XMX to its Arrow Lake processors and Xe-LPG Plus GPUs. XMX extensions are designed for matrix multiplication operations in FP64, FP32, FP16, and bfloat16 formats, which are crucial in many AI algorithms, including neural networks. Neural networks are used both for AI workloads as well as graphics enhancements, so the addition of XMX to Arrow Lake will play a positive role in graphics processing.

Perhaps an even more important thing about the addition of XMX to a mass-market client CPU is that XMX will be supported on hundreds of millions of PCs within a year, which will greatly popularize the technology and will offer significant incentives for software developers to take advantage of it. 

Although Intel's Xe-branded built-in GPU cores are quite capable, the company still made some efforts to reduce its silicon footprint to cut costs. As a result, Intel's Xe-LP and Xe-LPG GPUs lack XMX, which is important for advanced XeSS upscaling and AI capabilities. As it turns out, with a multi-tile Arrow Lake processor design, the company can finally add XMX to its built-in GPUs. The only question that remains is whether XMX will also be supported by the Lunar Lake MX platform, which again places GPU into the same piece of silicon with CPU.

Subsidies that multinational chipmakers are set to receive to build their fabs in Europe will come from two sources: the European Union itself, as part of the European Chips Act approved in July, and individual states. So far, Germany has promised $22 billion in incentives to chipmakers like Intel and TSMC, which is why the companies announced plans to build fabs there. But it looks like a stalled German budget approval has slowed down billions for the chipmakers, according to a report from ComputerBase.de.

Both Intel and TSMC vowed to invest billions in their projects in Germany, so without timely government money, the companies may need to invest additional money themselves (i.e., increase their CapEx or reallocate funds from other projects), scale down their projects, slow buildout, or find additional investors.

The German Federal Budget for 2024 has been delayed in response to a ruling by the Federal Constitutional Court, which deemed reallocation of unused Corona funds to the Climate and Transformation Fund in 2022 as unconstitutional. The German government planned to use the Climate and Transformation Fund to subsidize chipmaking as these are sustainable economic projects — but now that it cannot be done, the ruling coalition (consisting of the SPD, Greens, and FDP) has postponed the final discussions and approval of the budget.

This means that the budget will not go to the Bundestag for a vote next week (as planned) and will most likely no longer be signed by the Federal President in time before the end of the year. While the coalition aims to finalize the budget within the year, the exact timeline for the approval of the 2024 budget remains uncertain due to these complications.

Given the delay and revisions in the budget thanks to the constitutional court ruling, all areas of government spending, including potential subsidies for chipmakers, might be under review. This could lead to adjustments in the allocation of funds or even the cutting of subsidies altogether. This means that Intel and TSMC may not get subsidies on time — or at all — next year, which will have implications on how the companies conduct business. But at this point it is hard to tell how exactly the German budget crisis will affect Intel, TSMC, and others.

Renowned hardware leaker @kopite7kimi corrected their own prediction that Nvidia's next-generation flagship graphics processing unit based on the Blackwell architecture would feature a 512-bit memory interface. It will not. Nvidia's GPU, currently known as GB202, will apparently continue to use a 384-bit memory bus, but will adopt GDDR7 type of memory.

Nvidia's GB202 GPU is projected to feature up to 24,576 CUDA cores, a 33% increase over the number of CUDA cores packed in the AD102 GPU (18,432 CUDA cores). Rumors suggest the company will use one of TSMC's 3nm-class fabrication processes to make its GPUs based on the Blackwell architecture — though it remains to be seen whether Nvidia and TSMC will customize TSMC's 3nm-class nodes for GPUs, or if they'll stick to the default.

"Damn, we must adjust our evaluation of [GeForce] RTX 5090/5080," wrote kopite7kimi in an X (formerly Twitter) post.

"I think I probably made an empirical mistake," said kopite7kimi in another post. "I mistakenly applied the ratio of Ada Lovelace's L2 [cache] and [memory controller] to Blackwell, [which led to an incorrect assumption regarding GB202's 512-bit memory interface]." 

When asked whether they meant a 384-bit memory interface for GB202 graphics processing unit, they replied positively, clarifying that the part will also use GDDR7. While a 512-bit bus would enable Nvidia to massively increase bandwidth available to its next-generation flagship graphics cards (presumably named the Nvidia GeForce RTX 5090), using GDDR7 over a 384-bit interface will also provide tangible benefits. 

If Nvidia uses Micron's 32 GT/s 16 Gb ICs, then its RTX 5090 will get 1.536 TB/s of memory bandwidth — that's up from the the 1.008 TB/s the RTX 4090, the best graphics card available today, gets. Yet, with 16 Gb ICs, Nvidia will still have to stick to 24 GB of memory on its premium consumer board.

Samsung said that its upcoming SF1.4 (1.4nm-class) process technology will increase the number of nanosheets from three to four, Jeong Gi-Tae, vice president of Samsung Foundry, told The Elec, reports DigiTimes. The move promises to bring significant benefits for performance and power consumption.

Samsung was the first company to introduce a process technology that relies on gate-all-around (GAA) nanosheet transistors with its SF3E (also known as 3nm-class gate-all-around ear, 3GAE) in mid-2022. The company uses the technology to make various chips, but it is believed that usage of the node is limited to tiny chips, such as those used for cryptocurrency mining. Next year Samsung plans to introduce its SF3 technology, which is poised to be used by a wider range of applications. In 2025, Samsung plans to roll out its performance-enhanced SF3P technology that is designed with data center CPUs and GPUs in mind. 

Also in 2025, Samsung expects to introduce its SF2 (2nm-class) fabrication process, which will not only rely on GAA transistors, but will also feature backside power delivery, which brings substantial benefits when it comes to transistor density and power delivery, 

Perhaps the biggest overhaul of Samsung production nodes after the introduction of GAA-based SF3E will happen in 2027, when Samsung's SF1.4 technology will gain an additional nanosheet by increasing the number of nanosheets from three to four.

Increasing the number of nanosheets per transistor can enhance the driving current, improving performance. More nanosheets allow for more current to flow through the transistor, enhancing its switching capabilities and operational speed. Also, more nanosheets can lead to better control of the current flow, which can help in reducing leakage current, thus reducing power consumption. Furthermore, improved control over current flow also means that the transistors generate less heat, which increases power efficiency. 

Both Intel and TSMC intend to start using GAA transistors with their 20A and N2 (2nm-class) process technologies due in 2024 and 2025, respectively. By the time these companies introduce their nanosheet-based nodes, Samsung will have significant experience with gate-all-around transistors, which might be beneficial for the foundry.

It is not uncommon for server processors to support instructions that are not supported by client CPUs. But it looks like Arrow Lake S processors for desktops will support instructions that will not be supported by Arrow Lake CPUs for laptops, as noticed by @InstLatX64.

As it turns out, Arrow Lake processors in LGA1851 packaging will support such instructions as AVX-VNNI-INT16, SHA512, SM3, and SM4. In addition, the CPU will support an LBR Event Logging feature. The exact reasons why Intel decided not to implement these features into mobile parts is unclear, but it is possible that the company could not add support because ultra-low-power x86 cores in the SoC die do not support these instructions and therefore they will not be enabled on the compute die as well. 

Meanwhile, the new instructions may actually be missed on the mobile parts. Intel's AVX-VNNI-INT16 are Vector Neural Network Instructions with 16-bit integer data types designed specifically to accelerate convolutional neural network (CNN) and deep learning workloads, which should be quite handy for generative AI applications.

As for other instructions, SHA512, SM3, and SM4 are cryptographic technologies meant to accelerate appropriate algorithms, and given that there are always security concerns, these additions will also be welcome. It should be noted, though, that SM3 and SM4 are primarily used in China.

As far as Intel's Last Branch Record (LBR) feature is concerned, this is a debugging and performance tuning feature supported by some of its processors. LBR keeps a record of the processor's recently executed branches, including addresses of the branch and target instructions. This information helps developers understand program execution flow, identify performance bottlenecks, and analyze speculative execution side-channel attacks like Spectre and Meltdown.

Although mobile Arrow Lake CPUs may not support these instructions supported by desktop versions of these processors, it is likely that eventually, Intel's mobile processors will gain support for things like AVX-VNNI-INT16, SHA512, SM3, and SM4, after more software makers start using them.

TSMC had to cancel plans to build its 1.4nm-capable fab in Longtan Science Park in Taoyuan City's Longtan District due to opposition of locals and the company has yet to decide where to build it. One of the options is to build it in Kaohsiung Science Park (also known as Luzhu Science Park) near the Kaohsiung city, where the company's second 2nm-capable fab is set to be located, according to a report by money.UDN.com.

TSMC's first N2-capable fab will be located at the company's site near Baoshan, Hsinchu County, near its R1 R&D facility that is focused on N2 development. The company's second fab that is set to make chips on one of TSMC's N2 production node is expected to be located near the Kaohsiung Science Park (which is a part of Southern Taiwan Science Park) near the Kaohsiung city. Meanwhile, for its 1.4nm-capable facility that is set to come online in 2027, TSMC was considering expanding its site in Longtan Science Park in Taoyuan City's Longtan District and building the shell by 2026. But the world's largest foundry had to abandon the project due to protests of the locals.

From supply chain, talent, and land availability, Kaohsiung Science Park seems to be a good candidate for TSMC's 1.4nm-capable fab. At the end of the day, the company's Kaohsiung site already employs 1500 people directly and 500 indirectly. Therefore, it makes sense to build there. Alternatively, it could build its new facility near Baoshan, Hsinchu County, as the company already has extensive operations there — though it is unclear whether TSMC has enough land there.

TSMC's 1.4nm-class fabrication technology seems to be an important milestone for TSMC. The world's No. 1 is not going to use extreme ultraviolet (EUV) lithography tools with a 0.55 numerical aperture (High-NA) optics with its 2nm-class process technologies (unlike its rival, Intel). But the company will have to start using ASML's Twinscan EXE machines at some point and it is highly likely that it is going to need them for its 1.4nm-class manufacturing node. 

ASML's Twinscan EXE scanners are considerably bigger than regular Twinscan NXE tools with a 0.33 NA, which is why it will be either impossible or complicated to install them into existing fabs. As a result, the company will need redesigned fab buildings for 1.4nm-class-capable facilities, which is why it is important for TSMC to start constructing one of them sooner rather than later.

TSMC would not comment on its 1.4nm-capable fabs or discuss peculiarities of its 1.4nm process technology — so this is all speculation, for now.

There is some good news for TSMC, too. The company's fab in Kumamoto, Japan, is on-track to start mass production on TSMC's N16-class nodes in 2024. Furthermore, the company is mulling to expand the site and make chips on N7 and N6 process technologies, according to Nikkei. Japan is ready to provide TSMC as much as $6 billion in subsidies for its second fab in the country.