Intel has reached an agreement to transfer a majority stake in its Altera division to Silver Lake for $4.46 billion, which values the business at $8.75 billion. The deal is part of Intel's effort to streamline its operations and improve its financial position, while making Altera the world's largest pure-play FPGA provider.

Under the terms of the agreement, Silver Lake will acquire 51% of Altera, while Intel retains 49%, ensuring it continues to benefit from the unit's future performance. The transaction enables Altera to function as an independent company focused on programmable logic technologies. Specifically, Altera aims to double down on established fields such as automotive, aerospace, and communications, while also targeting growth in areas like artificial intelligence, cloud platforms, edge systems, and next-generation wireless networks.

Intel, on the other hand, will reduce operational complexity and focus on its primary business areas: CPUs, GPUs, supporting platforms, and chip production.

"Today's announcement reflects our commitment to sharpening our focus, lowering our expense structure and strengthening our balance sheet," said Lip-Bu Tan, chief executive officer of Intel. "Altera continues to make progress repositioning its product portfolio to participate in the fastest growing and most profitable segments of the FPGA market."

Altera will be led by Raghib Hussain starting May 5, 2025. He replaces Sandra Rivera, who is stepping down after a 25-year tenure at Intel. Hussain previously served as president of Products and Technologies at Marvell and co-founded Cavium. His earlier roles included engineering positions at Cisco and Cadence, as well as founding a security firm called VPNet.

"We are grateful for Sandra’s strong leadership and lasting impact throughout her 25-year Intel career and wish her continued success as she begins a new chapter," said Tan. "Raghib is a superb executive we selected to lead the business forward based on his vast industry experience and proven track record of success. We look forward to partnering with Silver Lake upon closing of the transaction, as their industry expertise will help to accelerate Altera's efforts and unlock additional economic value for Intel."

Intel bought Altera in 2015 for $16.7 billion — its biggest deal ever at the time — viewing the acquisition as a strategic move to broaden its revenue sources and strengthen its role in the data center market. Today, Intel sells a controlling stake in Altera for some $4.46 billion as the company is now valued at $8.75 billion, a significant decrease from the sum that Intel paid for Altera 10 years ago.

The deal is expected to be finalized in the second half of 2025, subject to regulatory approval and other conditions. Once closed, Intel will remove Altera’s financial results from its consolidated statements. In the previous fiscal year, Altera generated $1.54 billion in revenue, posted a $615 million loss under standard accounting rules, but showed a $35 million profit on a non-GAAP basis.

This week, Altera officially raised a flag with its own name near its headquarters in San Jose, California, marking its spinoff from Intel and becoming an independent company. The newly formed company, which remains owned by Intel, will focus on expanding its FPGA offerings with greater flexibility while maintaining a strategic partnership with Intel.

"Today marks a proud milestone as we officially raise the Altera flag as an independent FPGA company," a statement by Altera published in an X post reads. "We are excited to drive the future of innovation with agility and focus, shaping the next era of FPGA technology on http://altera.com."

FPGAs, Altera's specialty, are particularly suited for adapting to rapidly changing technological needs without the high costs associated with ASIC development. Altera aims to strengthen its presence in established sectors like automotive, communications, and aerospace, as well as in emerging areas such as AI, cloud computing, edge technologies, and 6G.

Regarding AI, FPGAs are well-suited due to their flexibility and lower costs for adding new instructions and data formats. In addition to custom AI applications, FPGAs can be used to simulate upcoming AI processors before implementing them in silicon. Furthermore, Altera's FPGA AI Suite integrates with frameworks like TensorFlow and PyTorch, allowing developers to build optimized solutions that are compatible with industry standards.

Although now independent, Altera intends to maintain a close relationship with Intel Foundry, which will manufacture its chips using competitive production nodes. This collaboration ensures reliable supply chains while also granting Altera the freedom to work with other foundries, enabling it to broaden its manufacturing options and remain competitive. If the company's strategy succeeds, an initial public offering (IPO) could follow.

When Intel acquired Altera for $16.7 billion in its largest acquisition in 2015, the company pinned a lot of hopes on the FPGA developer as a way to diversify its revenue streams and possibly enhance its position in the datacenter. Now, Intel hopes that Altera will be successful as an independent entity, which could enable it to gain some additional cash during the IPO.

Altera will be led by CEO Sandra Rivera.

According to Reuters reports, Intel's CEO Pat Gelsinger and other key executives are to present their plan to trim Intel's fat and course-correct the company. The meeting will focus on removing assets and reducing costs, with items of discussion apparently including Intel's upcoming Magdeburg, Germany fab and its ownership of Altera.

Intel announced a $1.6 billion loss in its now-infamous August 1 earnings call, which also carried the news that Intel had laid off 15% of its workforce and aims to reduce spending by $10 billion by 2025. The loss came thanks to Intel's falling behind in the AI arms race and its 13th/14th-generation widespread CPU failures. Intel stock had its worst day in 50 years immediately following the call, and the company has continued to suffer in the month since. Chip industry legend Lip-Bu Tan resigned from the board of executives, resulting in a 6% drop in Intel stock and a significant lack of industry experience.

Significant changes to Intel were always likely to reverse this major downturn, but recent reports reveal that Gelsinger's plans may include seriously drastic measures. Construction on Intel's upcoming Magdeburg chip fab is expected to be paused or canceled, leaving the $32 billion project unfinished. Magdeburg's local government has already begun drafting plans in case Intel withdraws its commitment to the project.

Intel is also likely to sell off its ownership of Altera, its programmable chip business, which is currently a fully spun-off company owned solely by Intel. Altera has been an industry fixture for decades, with Intel investing heavily in reviving Altera after acquiring the company in 2015. Altera has been a part of Intel's broad market strategy for ten years but is likely to be entirely sold off to another interested chip manufacturer in the coming months.

Unsurprisingly, Intel is not expected to entertain discussion about spinning off or selling its Intel Foundry wing. Intel's contract foundry business, one of Intel's most significant expenses, has been kept distinct from the rest of Intel's business since Q1 2024 and is considered a tentpole part of Intel's future. Two separate sources have confirmed that Intel will not propose any plans to sell its foundry wing to TSMC or another similar buyer, keeping it around for the day it is hopefully as profitable as Gelsinger believes it can be.

Intel's sharp decline can be attributed to several factors. Lip-Bu Tan reportedly blamed his exit from Intel on a bloated workforce, and Gelsinger blamed expenditures across the board as a major problem. Intel is still mired in issues related to the instability and failure rate of 13th and 14th Generation CPUs, which could lead to permanent chip damage. Tech media heavily reported Intel's lethargic response to a disastrous product failure, leading to increased public distrust of Intel's brand. While selling off companies will help quell Intel's bleeding out; the company has a long road ahead to stability.

Just like it announced in October, Intel has spun off its programmable solutions group into a standalone FPGA company that regains its historical name, Altera. Intel took over Altera for $16.7 billion in late 2015, which was among the largest acquisitions in the high-tech industry back then. The new Intel-owned company will operate independently, much as it used to, while it focuses on expanding its product lineup.

Altera will continue offering field-programmable gate array (FPGA) solutions across a wide range of applications, including traditional sectors like automotive, communications, data centers, embedded systems, industrial, and military-aerospace, as well as emerging and developing sectors like AI, cloud, network, and edge computing. The company will be led by chief executive Sandra Rivera and chief operating officer Shannon Poulin.

Altera's FPGAs can be used to evolve rapidly developing standards and technologies without investing tens of millions into expensive application-specific integrated circuits (ASICs). Intel mentions trends like CXL, Ethernet, and 6G wireless, as areas of focus. 

FPGAs could also be used for AI as it is easy and cheap to add new data formats and commands to FPGAs (compared to the development of new ASICs). In particular, Altera pins a lot of hope on its FPGA AI Suite (powered by the OpenVINO platform) that can generate optimized intellectual property based on popular frameworks like TensorFlow and PyTorch.

"As customers deal with increasingly complex technological challenges and work to differentiate themselves from their competitors and accelerate time to value, we have an opportunity to reinvigorate the FPGA market," said Rivera. "We are leading with a bold, agile, and customer-obsessed approach to deliver programmable solutions and accessible AI across a broad range of applications in the comms, cloud, data center, embedded, industrial, automotive, and mil-aero market segments." 

The split with Intel is expected to grant Altera more independence, which is predicted to fuel its expansion in the competitive FPGA market. Meanwhile, Intel and Altera will continue their strategic collaboration, especially through Intel Foundry, which will produce chips for the FPGA company on a contract basis. This relationship will allow Altera to offer its customers FPGAs produced on competitive nodes as well as supply predictability. Naturally, the separation enables Altera to go to other foundries more often than it used to as a part of Intel. 

While the original merger was seen as a highly promising move for Intel, as FPGAs significantly broadened the company's reach, especially in the data center, it appears that Intel now believes its programmable solutions business will fare better as an independent entity. It remains to be seen how much valuation Altera will get in the coming years when and if it pursues an initial public offering (IPO).

Intel has unveiled plans to spin off its Programmable Solutions Group (PSG) into an independent entity by January 1, 2024. Intel says that this strategic move is part of an effort to increase equity investments, enhance value, and further harness the FPGA market's potential. Sandra Rivera will head PSG as CEO, with Shannon Poulin serving as COO. 

The separation is expected to offer PSG greater autonomy, which is anticipated to drive its growth within the competitive FPGA sector, which spans from automotive to aerospace and from defense to datacenters. Intel says that with the spin-off, PSG will be better positioned to capitalize on these diverse sectors. Meanwhile, Intel and PSG are set to maintain a strategic partnership, particularly with Intel Foundry Services. This affiliation will enable PSG to provide customers with reliable supply predictability, vital for a resilient supply chain.

With the intended separation, Intel aims to enable PSG the liberty to grow its share in the FPGA market. Over the subsequent two to three years, Intel aspires to introduce an IPO for PSG. Intel says it is also open to collaborations with private stakeholders to invigorate business expansion, while still holding onto the majority of its shares. 

Intel acquired Altera, its Programmable Solution Group, on December 28, 2015, for approximately $16.7 billion. This was Intel's largest acquisition in history and one of the largest mergers in the high-tech business. Back then it was considered as a very promising move for Intel as FPGAs greatly expanded the company's scope, particularly in the datacenter field. But it looks like Intel thinks that its programmable solutions business will perform better on its own.

FPGA's growth trajectory shown by Intel looks promising, with projections indicating a compound annual growth rate of over 9% for the total available market, potentially reaching a worth of $11.5 billion by 2027. 

PSG is anticipated to commence its independent operations on January 1, 2024, while still receiving continued backing from Intel. Starting from the first quarter of 2024 Intel plans to present PSG as an individual business segment. Sandra Rivera's appointment as CEO of PSG is a logical move given her acquaintance with the business unit. She will continue her leadership role in DCAI until a suitable successor emerges. 

Intel's decision echoes its broader corporate strategy, as evidenced by its previous actions like the Mobileye IPO in 2022 and partnerships in 2023. Such endeavors highlight Intel's commitment to its IDM 2.0 strategy, aimed at propelling growth in its central operations and maximizing shareholder value across its diversified assets.

Oracle this week said that it had ported its Oracle Database 19c Enterprise Edition, the current long-term support release of Oracle Database, to Ampere's Altra processors that use the Arm instruction set architecture (ISA). The move marks a milestone both for Ampere and Arm ISA as Oracle is one of the most widely used enterprise software suites.

Separately, the company said that eventually it might ditch x86-based instances running Database on processors from AMD and Intel from its data centers in favor of instances enabled by Ampere CPUs. Oracle hopes that by tailoring its Database software for Ampere's single-thread CPUs, it will tangibly increase performance efficiency of its data centers. Furthermore, Ampere, in which Oracle is a lead investor, could also implement tweaks into CPUs to better run Oracle's Database.

"It is a major commitment to move to a new supplier. We've moved to a new architecture and we've moved to new supplier," Larry Ellison, Oracle's founder, said at an event hosted by Ampere, reports Reuters. "We think that this is the future. The old Intel x86 architecture, after many decades in the market, is reaching its limit."

Oracle Database 19c Enterprise Edition is now certified for work on Ampere Altra-based servers for both on-premises deployments and in the cloud by subscribing to Oracle Database Service using OCI Ampere A1 compute instances enabled by Ampere Altra on Oracle Cloud Infrastructure (OCI). It will continue to be offered on AMD and Intel-powered instances probably for years to come. But with Arm-based Ampere servers, Oracle hopes to offer "highly economical price points."

Oracle's OCI Ampere A1 can be used in a flexible VM format ranging from 1 to 57 CPU cores, each with 8GB of memory (maxing out at 456GB), 1 Gbps of network bandwidth for each CPU core (up to a total of 40 Gbps per VM).

Oracle's Database enterprise database management software is used by large businesses, banks, government agencies, retailers, and manufacturers for running online transaction processing (OLTP), data warehousing (DW) and mixed (OLTP & DW) workloads. The software has been in development since 1979 and supports a wide variety of hardware and software platforms, including IBM's Mainframe and Power-bases systems, x86 CPUs from AMD and Intel, Sun's SPARC processors, Intel's IA64 (Itanium) chips, and now Arm-based Ampere Altra SoCs.

"Today's announcement highlights the broad architectural shift across the market to Ampere processors that meet the demands of both modern cloud and on-premises environments," said Jeff Wittich, Chief Product Officer of Ampere. "With the Ampere Altra family of processors, customers of the world's most popular database — Oracle Database — now have a high-performance, energy efficient architecture built with sustainability in mind for organizations of all sizes."

While running Database on energy-efficient cloud-native Ampere's Altra CPUs promises to make a lot of economic sense for Oracle, OCI still needs to offer high-performance computing (HPC), and Dense-IO instances for those who need maximum performance and ultra-fast local storage. So, this week the company announced OCI Compute E5 HPC and OCI Compute E5 Dense-IO instanced based on AMD's 4th Generation EPYC processors with their vast core counts and rich I/O capabilities.

ASRock Rack has showcased its first motherboard for Ampere's Altra and Altra Max processors marking its entrance into the Arm-based servers business. The company's ALTRAD8UD-1L2T demonstrated at Computex can be used to build miniature servers or workstations featuring up to 128 Armv8 cores and datacenter-grade expandability and manageability. 

ASRock Rack's ALTRAD8UD-1L2T fully supports Ampere's Altra and Altra Max CPUs with 32 – 128 cores that can be paired with up to 2TB of memory using eight DDR4-3200 modules. In addition, the motherboard takes advantage of rather abundant I/O capabilities that Ampere's 1st Generation Altra Max datacenter SoCs have, including 128 PCIe Gen4 lanes with down to x2 and x4 bifurcation.  

Regarding physical slots, the motherboard has four PCIe x16 slots, two M.2-2280 slots, four SlimSAS connectors, and two OCuLink connectors for SSDs. The platform also has two 10GbE ports controlled by the Intel X550, one GbE connector enabled by the Intel I210, and one GbE driven by the Realtek RTL8211F for remote management supported by the Aspeed AST2500 BMC. The motherboard also has an SPI connector for TPM modules, USB 3.2 Gen1 ports, and a D-Sub VGA display connector.

One of the peculiarities of the ASRock ALTRAD8UD-1L2T platform is that it comes in the company's proprietary Deep microATX form factor, which will prevent it from installing into regular microATX chassis. In fact, we don't even know if it can be mounted into standard ATX or Full ATX towers. Yet, ASRock Rack will probably offer a chassis to install such motherboards into racks or desktop environments.

One of the questions about the ALTRAD8UD-1L2T is its target market. Ampere's Altra and Altra Max processors are tailored for cloud workloads, so using them as client machines hardly makes any sense for anything other than cloud software development. Yet, ASRock certainly sees that the market of microATX-ish platforms for Ampere CPUs is promising enough to address it.

ASRock Rack is the sixth company to offer a platform based on Ampere Altra processors after Foxconn, Gigabyte, HPE, Supermicro, and Wiwynn. 

Ampere this week introduced its AmpereOne processors for cloud datacenters that happen to be the industry's first general-purpose CPUs with up to 132 that can be used for AI inference.

The new chips consume more power than their predecessors — Ampere Altra (which will remain in Ampere's stable for at least a while) — but the company claims that despite of higher power consumption, its processors with up to 192 cores provide higher computational density than CPUs from AMD and Intel. Some of those performance claims can be controversial.

192 Custom Cloud Native Cores

Ampere's AmpereOne processors features 136 ­– 192 cores (as opposed to 32 to 128 cores for Ampere Altra) running at up to 3.0 GHz that are based on the company's proprietary implementation of the Armv8.6+ instruction set architecture (featuring two 128-bit vector units that support FP16, BF16, INT16, and INT8 formats) that are equipped with a 2MB of 8-way set associativity L2 cache per core (up from 1MB) and are interconnected using a mech network with 64 home nodes and directory-based snoop filter. In addition to L1 and L2 caches, the SoC also has a 64MB system level cache. The new CPUs are rated for 200W – 350W depending on exact SKU, up from 40W – 180W for the Ampere Altra. 

The company claims that its new cores are further optimized for cloud and AI workloads and feature 'power and are efficient' instructions per clock (IPC) gains, which probably means higher IPC (compared to Arm's Neoverse N1 used for Altra) without a tangible increase in power consumption and die area. Speaking of die area, Ampere does not disclose it, but says that the AmpereOne is made on one of TSMC's 5nm-class process technology. 

Although Ampere does not reveal all the details about its AmpereOne core, it says that they feature a highly accurate L1 data prefetcher (reduces latency, ensures that the CPU spends less time waiting for data, and reduces system power consumption by minimizing memory accesses), refined branch misprediction recovery (the sooner the CPU can detect a branch misprediction and recover, it will reduce latency, and will waste less power), and sophisticated memory disambiguation (increases IPC, minimizes pipeline stalls, maximizes out-of-order execution, lowers latency, and improves handling of multiple read/write requests in virtualized environments). 

While the list of AmpereOne core architecture improvements does not seem too long on paper, these things can indeed improve performance significantly and they required a lot of research to be made (i.e., which things slowdown performance of a cloud datacenter CPU the most?) and a lot of work to implement them efficiently.

Advanced Security and I/O

Since the AmpereOne SoC is aimed at cloud datacenters, it is equipped with appropriate I/O, which includes eight DDR5 channels for up to 16 modules supporting up to 8TB of memory per socket, 128 lanes of PCIe Gen5 with 32 controllers and x4 bifurcation.

Datacenters also require certain reliability, availability, serviceability (RAS), and security features. To that end, the SoC fully supports ECC memory, single key memory encryption, memory tagging, secure virtualization, and nested virtualization, just to name a few of them. In addition, AmpereOne has numerous security capabilities like crypto and entropy accelerators, speculative side channel attack mitigation, ROP/JOP attack mitigation, and so on.

Curious Benchmark Results

Without any doubts, Ampere's AmpereOne SoC is an impressive piece of silicon designed to handle cloud workloads and featuring 192 general-purpose cores, the industry's first. Yet, to prove its points, Ampere uses rather curious benchmark results.

Ampere sees compute density of its AmpereOne as its main advantage. The company claims that one 42U 16.5kW rack filled with 192-core AmpereOne SoC-based 1S machines can support up to 7926 virtual machines, whereas a rack based on AMD's 96-core EPYC 9654 'Genoa' can handle 2496 VMs and a rack powered by Intel's 56-core Xeon Scalable 8480+ 'Sapphire Rapids' CPUs can handle 1680 VMs. This comparison makes a lot of sense in the 16.5kW power budget. 

But 42U rack power density is rising and exascalers like AWS, Google, and Microsoft are ready for this particularly for their performance-demanding workloads. Based on a survey from UpTimeInstitute in 2020, we can say that 16% of companies deployed typical 42U rakcs with rack power density from 20kW to over 50kW. By now, the number of typical deployments with 20kW racks has increased, not decreased, as the latest and previous-generation CPUs from AMD increased their TDPs compared to their predecessors.

When it comes to performance, Ampere demonstrates the advantages of its 160-core AmpereOne-based system with 512GB of memory running Generative AI (stable diffusion) and AI Recommenders (DLRM) against systems based on AMD's 96-core EPYC 9654 CPU with 256GB of memory (meaning that it worked in an eight-channel mode, not 12-channel mode that is supported by Genoa). Ampere-based machines produced 2.3X more frame/s for generative AI and over 2X more queries/s for AI recommendations. 

In this case Ampere compared performance of its systems crunching data with an FP16 precision, whereas AMD-based machines computed with an FP32 precision, which is not an apples-to-apples comparison. Furthermore, many FP16 workloads are now run on GPUs rather than on CPUs and massively-parallel GPUs tend to offer spectacular results with generative AI and AI recommendations workloads.

Summary

Ampere's AmpereOne are the industry-first general-purpose CPUs with up to 192 cores, which certainly deserves a lot of respect. These CPUs also feature robust I/O capabilities, advanced security features, and promise improved instructions per clock (IPC) gains. Also they can run AI workloads with FP16, BF16, FP8, and INT8 precision. 

But the company chose to use rather controversial methods to prove its points when it comes to benchmark results, which casts some shadow on its achievements. That said, it will be particularly interesting to see independent test results of AmpereOne-based servers.

Intel revealed more new details about the 3D Foveros chip design it will use for its Meteor Lake, Arrow Lake, and Lunar Lake chips today as a teaser to the company's presentation at Hot Chips 34, a semiconductor industry conference that sees the titans of tech sharing the architectural details of their new processors. Intel CEO Pat Gelsinger will keynote the event, and the company also has four technical presentations, including the consumer 'Lake' processors we'll discuss here and Ponte Vecchio GPUs, FPGAs, and the Xeon D processors. 

First and foremost, there have been recent rumors that Intel's Meteor Lake will be late to market due to Intel switching from the TSMC 3nm node to the 5nm node for its GPU tile/chiplet. While Intel still isn't sharing information about which specific node it will use for the GPU, company representatives say the planned node for the GPU tile has not changed, and the processor is on track for an on-time release in 2023. Notably, Intel will only manufacture one of the four tiles used to construct its Meteor Lake chips — TSMC will produce the other three. Industry sources indicate the GPU tile is TSMC N5 (5nm).

The first image in the above album is a new diagram that Intel shared of its Meteor Lake processors. We also added the following slides from our Intel 4 process node coverage. The new image has a few new details — Intel says this diagram is of a mobile processor that will ship to the market with six performance cores and two clusters of efficiency cores. Intel hasn't confirmed, but these are thought to feature the Redwood Cove and Crestmont architectures, respectively. Meteor Lake and Arrow Lake chips will scale to meet the needs of the mobile and desktop PC market, whereas Lunar Lake will serve the mobile 15W and under market. 

Packaging and interconnect advancements are rapidly changing the face of modern processors. Both are now just as important as the underlying process node technology — and arguably more important in some facets.

Many of Intel's disclosures today center around its 3D Foveros packaging tech that it will use as a bedrock for its Meteor Lake, Arrow Lake, and Lunar Lake processors for the consumer market. This technology allows Intel to stack chiplets vertically atop one unifying base die with a Foveros interconnect. Intel also uses Foveros for its Ponte Vecchio and Rialto Bridge GPUs and the Agilex FPGAs, so this is a foundational technology for several of the company's next-gen products.

Intel first brought 3D Foveros to market in its low-volume Lakefield processors, but the four-tile Meteor Lake and nearly 50-tile Ponte Vecchio are the company's first high-volume chip production with the technology. After Arrow Lake, Intel will transition to the new UCIe interconnect, thus tapping into the forming ecosystem of chiplets that use a standardized interface.

Intel revealed that it will place the four Meteor Lake chiplets (called 'tiles' in Intel parlance) on top of a passive Foveros interposer/base tile. The chiplets and interposer are wired together with TSV connections, and the interposer doesn't have any logic. The Meteor Lake base tile is different than the one found in Lakefield, which served as an SoC of sorts. The 3D Foveros packaging tech also supports active interposers. Intel says it manufactures the Foveros interposer with its low-cost and low-power-optimized 22FFL process (the same as Lakefield). Intel also has a newer 'Intel 16' variant of this node for its foundry services, but it isn't clear which version Intel will use for the Meteor Lake base tile.

Intel will mount the compute tile, which uses the Intel 4 process (more here), the I/O tile, the SoC tile, and the graphics tile (tGPU) atop this interposer. All of these units are Intel-designed and feature Intel architectures, but external foundry TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles.

Industry sources tell us that the I/O die and SoC are fabbed on TSMC N6, while the tGPU uses TSMC N5. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Foveros uses a 36-micron bump pitch (a critical measurement of interconnect density), an improvement over the 55-micron bump pitch it used with Lakefield. The Foveros roadmap includes 25- and 18-micron pitches with future designs. In the future, Intel says it could theoretically even use hybrid bonding interconnects (HBI) to reach 1-micron bump pitches. 

Cost has been one of the overriding concerns with exotic 3D packaging, and Foveros will be Intel's first foray into high-volume manufacturing with its leading-edge packaging tech. However, Intel says that chips produced with 3D Foveros packaging will be extremely price-competitive with standard monolithic (single-die) chip designs — and perhaps even less expensive in some cases. 

Intel designed the Foveros die to be as low-cost as possible and still deliver on the company's electrical and performance goals — it's the cheapest die on the Meteor Lake package by orders of magnitude. Intel isn't sharing speeds and feeds for the Foveros interconnect/base tile yet, but says the interfaces can run at 'multiple GHz' in the passive configuration (this statement also heavily implies that Intel has active versions of the interposer already in development). As such, Foveros doesn't incur any bandwidth or latency constraints that require design tradeoffs. Intel also expects the design to scale well in both performance and cost, meaning it can make either value-optimized designs or performance-oriented variants for other segments.

We see the real savings when we zoom out to the bigger picture. Leading-edge nodes are becoming exponentially more expensive per transistor as the industry progresses to smaller nodes, especially with monolithic designs, due to yield concerns. Additionally, designing new IP blocks, like I/O interfaces, for smaller nodes doesn't provide as much of a payoff for the investment. Therefore, re-using non-critical tiles/chiplets on 'good enough' legacy nodes saves time, cost, and developmental resources, not to mention simplifying the testing process.

For a monolithic die, Intel has to serially test the different chip elements, like the memory or PCIe interfaces, which can be a time-consuming process. In contrast, Intel can test chiplets concurrently to save time. Foveros also affords advantages in designing chips for certain TDP ranges, as the different chiplets can be tailored for the needs of the design.

If you think most of these points sound very familiar, you're right — these are the same factors that propelled AMD down the chiplet path back in 2017. AMD wasn't the first to use a chiplet-based design, but it was the first to design a modern mass-produced chip using the design philosophy, so Intel is a bit late to the tech. However, Intel's initial foray with 3D packaging tech is far more complex than AMD's organic interposer-based designs, which will have both advantages and disadvantages. The proof will be in the final silicon, which Intel says is on track for a 2023 launch. Arrow Lake and Lunar Lake will follow in 2024. 

Here's the overview of the topics that Intel will cover this week at Hot Chips 34. We'll have more in-depth coverage as the actual presentations occur, so you can expect an update to this article soon. Stay tuned. 

When Alibaba's T-Head subsidiary introduced its 128-core Yitian 710 processor consisting of 60 billion transistors and produced on TSMC's N5 node, it made quite a splash in the world of CPUs. This week the company published official performance results of the chip at SPEC.org, an industrial benchmark, and revealed that the chip is actually the world's fastest processor in SPEC CPU2017 integer workloads, as noticed by ServeTheHome. 

Alibaba's T-Head Yitian 710 datacenter system-on-chip integrates 128 Arm v9 cores operating at up to 3.20 GHz with 1MB of L2 cache per core and 128MB L3 cache per chip. The SoC packs eight DDR5-4800 memory channels that can provide up to 307.2 GBps of bandwidth, as well as 96 PCIe 5.0 lanes to attach high-performance solid-state storage, network cards, and other devices. The chip is exclusively used by Alibaba Cloud, which developed its proprietary Panjiu servers specifically for the Yitian 710 SoC. Panjiu can be used both for general-purpose and accelerated AI workloads, but to test the CPU in the SPEC CPU2017 benchmark Panjiu was used purely as a number crunching machine.  

The tested Alibaba Cloud Panjiu server was based on a 128-core Yitian 710 operating at 2.75 GHz and mated with 512GB of DDR5-4800 (using eight 64MB modules). The machine run Anolis OS release 8.6 installed on a 240GB SATA SSD. 

The machine's baseline SPEC CPU2017 integer rate reached 510 (3.984 per core), but there is no benchmark for the peak score. Meanwhile, even 510 is 15% higher when compared to AMD's 64-core EPYC 7773X processor, which scored 440 baseline result (6.875 per core). The highest baseline result achieved by Intel's 36-core Xeon Platinum 8351N processor is 266 (7.38 per core), whereas the best rate hit by Ampere's Altra 80-core machine is 301 (3.7625).  

While Yitian's and Ampere's per core results look less impressive than their baseline results, the massive number of cores and the overall integer capability speak for themselves. If one needs an extreme integer rate, then the 128-core monster from Alibaba's T-Head looks to be the processor of choice. 

Now, while integer rate of Yitian 710 in SPEC CPU2017 is nothing but spectacular, for some reason Alibaba Cloud did not submit any floating point results of its platform. Perhaps, the floating point unit of the processor is not as impressive as its integer unit, or maybe software and/or CPU microcode still have to be polished off. In any case, at present CPU2017 floating point rates are dominated by AMD's EPYC 7773X-based machines. 

Alibaba Cloud will start to offer instances powered by its Panjiu servers equipped with its Yitian 710 processors this September. At present the cloud service company offers select customers to test drive Yitian 710-based machines.

Ampere's Altra processors were developed primarily for cloud service providers, which is why the company pushed systems on their base to customers like Alibaba and Oracle. But as the company is gaining traction, it wants its platforms to be available to a broader audience. To do so, it needs to partner with large server makers, and starting from the third quarter, HPE will offer ProLiant machines powered by Ampere's Altra CPUs with up to 128 cores.

Hewlett Packard Enterprise's ProLiant RL Gen11 powered by Ampere's Altra (up to 80 cores) and Altra Max (up to 128 cores) processors is a single-socket 1U machine. They can house up to 4TB of memory using 16 DDR4 memory modules, up to 10 2.5-inch NVMe SSDs, and two M.2 SSDs. In addition, the machine can accommodate three PCIe Gen4 expansion cards and two OCP 3.0 add-in-boards.

Unlike companies like Foxconn or Wiwynn, which aim their Ampere Altra-based machines primarily at cloud services providers, HPE positions its ProLiant RL Gen11 servers for enterprises with cloud native developments. Meanwhile, since the ProLiant RL Gen11 is a server machine designed for enterprises, it comes with HPE's iLO with the company's silicon root of trust capabilities for traditional HPE server management and OpenBMC enabled for open-source deployments. So, the ProLiant RL300 Gen11 is naturally fully supported by HPE.

Still, given the nature of Ampere's Altra CPUs, HPE's ProLiant RL Gen11 is not exactly a competitor for x86 servers from the company (at least not for classic enterprise applications), and the manufacturer expects owners of these machines to run cloud applications tailored for these Arm processors. Ampere claims that its Altra CPUs can offer 2.5 – 3 times the performance of competing systems at half the power; however, this claim is quite general. It depends on actual workloads and has to be verified by independent testing.

HPE will start selling its ProLiant RL300 Gen11 servers based on Ampere's Altra and Altra Max processors beginning Q3 2022. The machines will be available worldwide for purchase or as-a-service through HPE GreenLake. The pricing of the machine is unclear, but it will undoubtedly depend on the exact configuration.

HPE will only offer a single-socket Ampere Altra machine in its ProLiant lineup for scale-out environments. Still, the company implied that eventually, it would also offer machines with a more significant number of CPUs.

One of the first customers to adopt the new machine will be CloudSigma, a cloud IaaS and PaaS provider with advanced hybrid hosting solutions in Europe, The US, APAC, and the Middle East in over 20 locations.

Law Street Media reported that Japanese professor Masahiro Iida had sued Intel for infringing U.S. Patent No. 6,812,737. The complaint accuses Intel of manufacturing, using, and selling Field Programmable Gate Array (FPGA) and System-on-Chip (SoC) chips that employ Adaptive Logic Modules (ALM), a patent that Iida has held from 2004 to 2014.

When Iida was a doctoral student back in 2001, he had discovered a method to configure large look up tables (LUTs) so that a single M-input N-output LUT can operate as a single “whole” LUT or as a group of “fractured” LUTs. His discovery reportedly helped substantially reduce the implementation area and power consumption for chips that leveraged the innovation.

Iida filed for a patent application on June 29, 2001, and consequently did so in the United States on June 28, 2002. As a result, the United States Patent and Trademark Office (USPTO) issued the '737 patent entitled “programmable logic circuit device having to look up table enabling to reduce implementation area” to Iida on November 2, 2004, which he has been the sole owner since then until October 1, 2014.

Altera and Xilinx are two the big players in the FPGA market. Intel bought Altera for $16.7 billion in 2015, and AMD consequently acquired Xilinx for $54 billion this year. Iida’s complaint pertains to Altera’s Stratix II line of FPGA chips launched in 2004 using ALMs. The company continued to utilize ALMs in its subsequent Stratix chips, including the Stratix III, Stratix IV, Stratix V, and Stratix 10, and in some of its other Arria and Cyclone product lines. After the Altera acquisition, Intel continued to manufacture and commercialize the Stratix, Arria, and Cyclone lineups. In addition, the chipmaker’s Agilex chips also utilize ALMs.

According to the filing, Intel may have benefited significantly from the products, with up to 80% of its annual revenues coming from selling FPGA and SoC that used ALMs. The filing estimated at least $11.5 billion from sales of the accused products over six years (Q3 2016 to 2022).

Professor Iida’s counsel sent a certified letter to Intel’s General Counsel concerning the ’737 patent infringement. Intel has infringed at least claim 1 of the ’737 patent. Despite the plaintiff’s notice, Intel continued to make, offer to sell and sell the accused FPGA chips without a license from Iida.

Iida is looking for monetary compensation equal to or greater than a reasonable royalty that he should have received if Intel had licensed his patent. He also requested that the Court grant him up to three times that amount found by the jury for Intel’s infringement pursuant and his attorney’s fees.

Ampere officially positions its Altra processors primarily for cloud workloads, but Gigabyte decided that these parts with up to 128 cores are good enough for compute GPU-based servers for artificial intelligence (AI) and high-performance computing (HPC) applications. This week the company formally rolled-out its G492-PD0 server that combines an Arm-based CPU and a heavy-duty compute GPU. 

Gigabyte's G492-PD0 server comes with one Ampere Altra Max (128 Arm v8.2 cores) or Altra (80 Arm v8.2 cores) processor as well as up to eight Nvidia A100 80GB SXM4 compute GPUs interconnected between themselves using Nvidia's NVLink bus at 600GB/s. The system can be equipped with up to 4TB of DDR4-3200 memory using 16 modules, four M.2 solid-state drives, six U.2 SSDs, and ten low-profile PCIe expansion cards. The whole machine is powered by three 3000W 80+ Platinum power supplies (+ one additional PSU for redundancy).

Gigabyte's 4U machine fully leverages Nvidia's HGX platform, so it fully leverages not only NVLink with NVSwitches for GPUs, but also the green company's GPUDirect RDMA for direct data exchange between GPUs and third-party devices like SSDs and network cards.

Previously, Gigabyte offered Nvidia A100 GPU-based servers with up to two 64-core AMD EPYC 7003 or 40-core Intel Xeon Scalable 'Ice Lake' processors. Those machines tend to be expensive given that both AMD and Intel charge a lot for their flagship offerings for servers that are in high demand. With a system based on Ampere's Altra/Altra Max, Gigabyte can offer somewhat lower pricing. Meanwhile, Gigabyte's G492-PD0 server has fewer PCIe lanes and potentially lower performance in some workloads, but organizations that buy GPU servers tend to do research before buying new machines to ensure they meet their needs.

There is another reason why Gigabyte needs this server: Gigabyte and users of its AI and HPC servers need is to gain experience with Arm-based CPUs in context of GPU-powered HPC applications before Nvidia launches its platforms powered by its Grace CPU and H100 compute GPU next year. Usage of Ampere Altra and Altra Max CPUs with up to 128 cores makes a lot of sense for Gigabyte as the machines are Arm-based and have a lot of cores.  

It is noteworthy that Ampere's Altra/Altra Max-based platforms in general and Gigabyte's G492-PD0 machine in particular have been certified by Arm for its SystemReady program for easy deployment of Arm-based servers. The Arm SystemReady program offers an official set of platform definitions that cover machines that range from IoT and edge servers all the way to cloud machines.

AMD announced during its earnings call that it will infuse its CPU portfolio with Xilinx's FPGA-powered AI inference engine, with the first products slated to arrive in 2023. The news indicates that AMD is moving swiftly to incorporate the fruits of its $54 billion Xilinx acquisition into its lineup, but it isn't entirely surprising — the company's recent patents indicate it is already well underway in enabling multiple methods of connecting AI accelerators to its processors, including using sophisticated 3D chip stacking tech.

AMD's decision to pair its CPUs with in-built FPGAs in the same package isn't entirely new — Intel tried the same approach with the FPGA portfolio it gained through its $16.7 billion Altera purchase in late 2015. However, after Intel announced the combined CPU+FPGA chip back in 2014 and even demoed a test chip, the silicon didn't arrive until 2018, and then only in a limited experimental fashion that apparently came to a dead-end. We haven't heard more about Intel's project, or any other derivatives of it, for years. 

AMD hasn't revealed any specifics of its FPGA-infused products yet, but the company's approach to connecting the Xilinx FPGA silicon to its chip will likely be quite a bit more sophisticated. While Intel leveraged standard PCIe lanes and its QPI interconnect to connect its FPGA chip to the CPU, AMD's recent patents indicate that it is working on an accelerator port that would accommodate multiple packaging options.

Those options include 3D stacking chip tech, similar to what it currently uses in its Milan-X processors to connect SRAM chiplets, to fuse an FPGA chiplet on top of the processors' I/O die (IOD). This chip stacking technique would provide performance, power, and memory throughput advantages, but as we see with AMD's existing chips that use 3D stacking, it can also present thermal challenges that hinder performance if the chiplet is placed close to the compute dies. AMD's option to place an accelerator atop the I/O die makes plenty of sense because it would help address thermal challenges, thus allowing AMD to extract more performance from the neighboring CPU chiplets (CCDs).

AMD also has other options. By defining an accelerator port, the company can accommodate stacked chiplets on top of other dies or simply arrange them in standard 2.5D implementations that use a discrete accelerator chiplet instead of a CPU chiplet (see above diagrams). Additionally, AMD has the flexibility to bring other types of accelerators, like GPUs, ASICs, or DSPs, into play. This affords a plethora of options for AMD's own proprietary future products and could also allow customers to mix and match these various chiplets into custom processors that AMD designs for its semi-custom business.

This type of foundational tech will surely come in handy as the wave of customization continues in the data center, as evidenced by AMD's own recently-announced 128-core EPYC Bergamo CPUs that come with a new type of 'Zen 4c' core that's optimized for cloud native applications.

AMD already uses its data center GPUs and CPUs to address AI workloads, with the former typically handling the compute-intensive task of training an AI model. AMD will use the Xilinx FPGA AI engines primarily for inference, which uses the pre-trained AI model to execute a certain function.

Victor Peng, AMD's president of its Adaptive and Embedded Computing group, said during the company's earnings call that Xilinx already uses the AI engine in image recognition and "all kinds" of inference applications in embedded applications and edge devices, like cars. Peng noted that the architecture is scalable, making it a good fit for the company's CPUs.

Inference workloads don't require as much computational horsepower and are far more prevalent than training in data center deployments. As such, inference workloads are deployed en masse across vast server farms, with Nvidia creating lower-power inference GPUs, like the T4, and Intel relying upon hardware-assisted AI acceleration in its Xeon chips to address these workloads.

AMD's decision to target these workloads with differentiated silicon could give the company a leg up against both Nvidia and Intel in certain data center deployments. Still, as always, the software will be the key. Both AMD CEO Lisa Su and Peng reiterated that the company would leverage Xilinx's software expertise to optimize the software stack, with Peng commenting, "We are absolutely working on the unified overall software enabled the broad portfolio, but also especially in AI. So you will hear more about that at the Financial Analyst Day, but we are definitely going to be leaning in AI both inference and training."

AMD's Financial Analyst Day is June 9, 2022, and we're sure to learn more about the new AI-infused CPUs then. 

Intel announced its new Agilex M-Series of FPGA (Field-Programmable Gate Array) products, and at the same time gave some very interesting positioning toward cryptocurrency mining. Intel is claiming several "world-firsts" with the Agilex M-series, including usage of the Intel 7 (previously Intel 10 nm) manufacturing process, support for up to 32 GB HBM2e DRAM (via twin memory stacks), and a 60% performance increase compared to previous-generation Stratix FPGAs. No claims on cryptocurrency mining performance were made by Intel, however.

Designed by Intel's Programmable Solutions Group (PSG), which incorporated the talent and design IP from Intel's $16.7 billion Altera acquisition back in 2015, the new Agilex M-Series promise to offer the highest memory bandwidth in the industry. This is thanks to a pair of HBM2e stacks configurable up to 32 GB, which provide up to 820 GBps in memory bandwidth (410 GBps per stack). That could prove particularly useful for Dagger Hashimoto / Directed Acyclic Graph (DAG) workloads frequently associated with cryptocurrency mining, e.g. Ethereum.

Additionally, intel says its new Agilex M-Series are the first FPGAs supporting cache and memory coherency with Intel's Xeon CPUs via the Compute Express Link interconnect standard. Agilex-M FPGAs are also the world's only solutions capable of operating with three types of memory: HBM2e, DDR5, and Intel Optane — though to be fair, Intel has locked other vendors out of Optane implementations in the past.

The new Agilex M-Series FPGAs offer the industry's highest memory bandwidth for an FPGA, thanks to the inclusion of HBM2e memory and an external DDR5/LPDDR5 memory bank, all controlled via Agilex M's hardened memory controllers. Intel also claims the industry's highest Digital Signal Processing (DSP) compute capabilities in an HBM-enabled FPGA, though note that Intel doesn't claim the highest compute density in non-HBM-enabled FPGAs.

The same is true regarding Intel's efficiency claims. The company says its Agilex M products offer over twice the fabric performance per watt vs competitive 7nm FPGAs (read, Xilinx's Versal). The devil, as always, is in the details: Intel isn't claiming twice the performance per watt of its competitor's offerings, only fabric efficiency, likely boosted by the company's usage of its EMIB technology.

This is the first time an Intel FPGA product is being marketed toward cryptocurrency-related workloads, and it's the second Intel product in a single month looking to enter the blockchain space, after Intel's Bonanza Mine ASIC (Application-Specific Integrated Circuit) was made public. Intel seems to be adopting a broader strategy when it comes to blockchain workloads, and the company will be offering at least three distinct product segments that serve this space. While the Bonanza Mine ASIC and its subsequent iterations are a given, the new Agilex M-Series FPGAs are also joined by Intel's upcoming Arc Alchemist, which, as the company pointed out, will offer full performance in cryptocurrency mining workloads.

That Intel is marketing FPGAs for mining workloads doesn't detract from the more conventional use-cases for these chips, which include compute, cloud-to-edge infrastructure, pervasive connectivity, and AI. FPGAs are particularly desired due to their high flexibility, which allows for businesses to quickly iterate on semiconductor designs on the same piece of silicon, instead of spending the resources in multiple tape-outs of different approaches, solutions, and stages of a given chip's design.

It is interesting that Intel is broadening the appeal of its FGPAs toward markets they previously weren't in. This is happening against the backdrop of the apparently diminishing competitiveness of its Altera-based products compared to those made by Xilinx, which was recently acquired by AMD, turning it into a bigger company (by market capitalization) than even Intel.

By itself, Xilinx showcased an extremely impressive 2021, raking in $3.15 billion in revenue for a cool 20% increase YoY. Intel's PSG group, in contrast, brought in $1.9 billion in revenue, with only a 4% revenue increase YoY, signaling that the market found Xilinx's offerings to be preferable over Intel's solutions. However, Intel claimed that its PSG group could have brought in an additional $500 million in revenue were it not for the supply constraints felt throughout the semiconductor market at large — supply constraints that interestingly weren't mentioned in Xilinx's own earnings report.

It remains to be seen if Intel's "new" FPGA market, blockchain, will account for anything more than a product release marketing move, or if the company's solutions can indeed bring added value to a market dominated by ASICs.

Ampere Computing and Rigetti Computing today announced a strategic partnership to create hybrid quantum-classical computers. Aiming to unlock a new generation of quantum-based machine learning applications, the partnership will see the pairing of Ampere's Altra Max Arm CPUs with Rigetti Computing's Quantum Processing Units (QPUs) in cloud-based High-Performance Computing (HPC) environments. The companies hope to take the biggest bite possible from the estimated $26 billion Quantum Computing as a Service (QCaaS) market by 2030.

The partnership aims to develop hybrid computing solutions that can be easily deployed in data centers to accelerate critical areas such as climate change, fusion energy, quantitative finance, drug development, and materials science. The integrated solutions are further meant to accelerate the discovery and deployment of high-performance machine learning algorithms. Ampere Altra Max-powered cloud servers are expected to process the vast amounts of data resulting from quantum workloads performed on Rigetti's QPUs.

"Our collaboration with Rigetti is a natural extension of our strategy to create cloud native processors optimized for a wide range of workloads and customer needs," said Renee James, Ampere's founder and CEO. "Quantum machine learning is emerging as a significant opportunity for scientific computing users and their providers of public and private clouds. We believe that Ampere and Rigetti will enable quantum computations of increased complexity, with the potential for higher performance at lower costs."

How Ampere's CPUs and Rigetti's QPUs will be integrated is still a mystery. At least part of the companies' efforts seems to be focused on accelerating quantum computing simulations run on classical systems. These would include Ampere's Altra Max Arm CPUs, which pack 128 Arm v8.2+ cores per chip running at up to 3.0 GHz. The company's claim of performance density of "up to 3,500 cores per rack" is likely one of the reasons Ampere Computing has already snagged several design wins with customers, including Microsoft and Tencent.

Rigetti's QPUs are based on superconducting qubits, which require cryogenically-secure environments to enable qubit coherence, entanglement, and workload processing. The company's QPUs are designed with several lessons taken from classical semiconductors and are described as a "lithographically defined chip-based technology." This means that deployment occurs within a self-contained chip-like structure, which includes the qubit array, a linear superconducting resonator (for qubit readout) and associated wiring.

The chip-like approach allowed Rigetti to design its QPUs with through-silicon vias and superconducting flip-chip cap bonding technologies. Both these solutions help insulate the qubit array from electromagnetic interference, which would lead to calculation errors and qubit decoherence, while also allowing qubit-to-qubit communication via the associated signal delivery wiring. Rigetti says it can achieve scalability simply by multiplying the number of chips within delivered systems, which the company has already done with the announcement of its 80-qubit Aspen-M, which is a multi-chip quantum computing system based on a pair of the chip's 40-qubit Aspen-11 QPUs.

Interestingly, Rigetti also published benchmark results for its Aspen-11 and Aspen-M systems under the Circuit Layer Operations per Second (CLOPS) metric proposed by IBM in October last year. The chips achieved a CLOPS score of 844 and 892, respectively. However, since the CLOPS metric still hasn't been finalized as a standard, it's impossible to know if results from Rigetti's QPUs are comparable to IBM's (which is the only other company to have ever announced benchmark scores under the metric). 

Even so, IBM's published CLOPS scores for systems with 5, 27, and 65 qubits were 1419, 951, and 753, respectively, as of the October 2021 standard proposal date. Rigetti's Aspen systems seem to offer positive scaling even while increasing qubit counts. However, linear scaling isn't expected, as the CLOPS standard allows for different workload complexities to be gauged (and scaled) against qubit counts.

Both Rigetti Computing and Ampere Computing have been at the forefront of their respective markets, and the partnership announcement seems to provide them with ample opportunity to build upon each other's strengths in the new, brave world of distributed quantum computing.

Intel updated its lineup of the famous Nios soft processors with the latest Nios V softcore, designed around the open-source RISC-V instruction set architecture.

The Nios family of processors is Intel's implementation of simple low-power processors designed to fit inside Field Programmable Gate Array (FPGA) designs and occupy just a tiny portion of it, supplying basic CPU functionality. According to Gartner, the Nios CPU family is the most widely-used softcore tech in the FPGA industry. These soft cores allow FPGA designs to have the basic functionality that the design would require from a CPU. This way, the company provides hardware designers with basic CPU needs with their Intel FPGAs, enabling faster hardware development.

The industry is becoming more interested in the open RISC-V ISA, and according to recent reports, Intel has also expressed interest in purchasing RISC-V startup SiFive for $2 billion. That makes plenty of sense given the wide range of applications that RISC-V can satisfy, just as we see with the Nios V soft cores. 

The importance of using RISC-V as an ISA template for these types of cores lies with the open-source hardware initiative that aims to open the whole ecosystem, making it accessible to anyone.

The Nios II, a predecessor of Nios V, is Intel's 32-bit digital signal processing (DSP) and system control based on reduced instruction set computer (RISC) design principles. The Nios II iteration is a 32-bit RISC CPU with 32 general-purpose 32-bit registers, a complete 32-bit instruction set, data path, address space, and single-instruction 32 × 32 multiply and divide, producing a 32-bit result. While we don't know the details of Nios V, we assume it is very similar.

For now, the Nios V is a microcontroller in the V/m form. This design uses the RV32IA part of the RISC-V specification with atomic extensions, a 5-stage pipeline, and AXI4 interfaces, creating a capable microcontroller design. However, Intel plans to continue engineering Nios V design IPs and develop a Linux-capable V/g general-purpose Nios V form of processor capable of running Linux kernel.

The introduction of Nios V means that Intel is finally jumping on the RISC-V open-source bandwagon. The company already offers some of the first designs based on the open ISA, and in the future, we could see more powerful designs emerge from Intel's design centers. 

Ampere's flagship 128-core Altra Max M128-30 may not be the world's highest-performing processor, yet it packs an unprecedented number of general-purpose 64-bit cores, has a reasonable power consumption and  is priced at a fraction of what AMD and Intel charge for their flagship EPYC and Xeon Scalable offerings. 

Ampere charges $5,800 for its top-of-the-range Altra Max M128-30 processor that features 128 Arm Neoverse N1 cores operating at up to 3.0 GHz, 128 PCIe Gen4 lances, and eight memory channels, according to Phoronix. By contrast, AMD's top-of-the-line EPYC 7763 CPU with 64 cores that can work at 2.45 GHz – 3.50 GHz is priced at $7,890 whereas Intel's Xeon Platinum 8380 processor with 40 cores functioning at 2.30 GHz – 3.40 GHz costs $8,099. 

In fact, even the cheapest 32-core Ampere Altra Q32-17 with 32 cores at 1.70 GHz and 128 PCIe Gen4 lanes is priced at $800, which is below AMD's 16-core EPYC 7302 that costs $978. Meanwhile, Intel has Xeon Silver 'Ice Lake-SP' processors that cost around $500, but these chips only feature eight cores. 

Arm's Neoverse N1 cores are not as advanced as AMD's Zen 4 or Intel's Ice Lake-SP cores, but they are small enough to pack 128  cores into a chip that consumes no more than 250 watts and still get viable yields.  

Ampere positions its Altra and Altra Max processors with up to 128 core largely for hyperscale providers of cloud services. Those providers can develop software that scales well with the number of cores (and is less dependent on per core performance) and is optimized for AArch64 in general as well as Neoverse N1 in particular. That leaves the company with a fairly limited number of potential customers. Therefore, Ampere has to offer an indisputable advantage over offerings from AMD and Nvidia, which seems to be its price per core.  

For high-volume white box servers used by hyperscale cloud giants that that run relatively limited number of applications, such an advantage may be quite tangible. For example, with Ampere's Altra-based servers Oracle can offer an Arm general-purpose core at one cent per hour, which translates to $30.72 for a 128-core processor per day. 

Meanwhile, for high-performance machines used in the enterprise a lower CPU price will not matter much since the cost of processors in many types of enterprise servers does not play a huge role as these machines are equipped with plenty of memory as well as a high-performance storage subsystem.  

n addition to Ampere and Oracle, there are other companies that are pushing Arm-based enterprise-grade processors to servers. Fujitsu, which A64FX processors power Fugaku supercomputer (which is soon to be replaced from the No. 1 sport in the Top 500 list by the upcoming AMD EPYC/Instinct-powered Frontier machine) is offering similar chips to various enterprises. Huawei is deploying its Arm-based SoCs primarily in its own data centers. 

AMD's recent server efforts have been tremendous. The company not only released CPUs with 64 cores and worked hard to win designs with server makers and cloud giants like Google, but it also prioritized producing EPYC processors over client CPUs and GPUs. These efforts paid off in the second quarter as, according to a report from analyst firm Omdia, AMD has reached its highest server CPU market share in years.

AMD Is Gaining Share

According to the report, around 3.4 million data center servers were sold in the second quarter of 2021 (flat year over year). Additionally, server makers earned $21.5 billion due to growing demand from hyperscale cloud service providers.

AMD controlled 16% of data center servers, Intel lost some revenue share to AMD, and Arm-based servers continued to progress, albeit in a limited number of cases. Omdia says that Ampere's Altra (deployed by Oracle) and chips from Fujitsu and Huawei are the most successful server-grade Arm SoCs.

An avid reader will certainly notice that data from Omdia appears to differ from data shared by Mercury Research last month, which shows that AMD commanded around 11.6% of server unit share in Q2 2021. This happens because Omdia includes all types of general-purpose servers in the report, like mainstream/datacenter machines (blades, rack servers, whitebox servers used by hyperscalers, tower servers, hyperconverged infrastructure servers), edge servers (a small emerging category), and four-socket and beyond servers.

Other firms do not include certain niche types of servers (e.g., machines with four or more CPUs) that sometimes happen to be categories in which AMD does not participate, which is why server-related reports from IDC, Mercury Research, and Omdia can have different perspectives. In the case of Omdia, it only covers data center machines. 

Omdia says that AMD's 16% share in data center servers is the highest share that the company has ever reached in this market segment, but it didn't elaborate. AMD controlled over 25% of the server market in Q3 2006, based on data from Mercury Research. It's important to remember that the server market is not only larger than it was in 2006 in terms of units, but the machines themselves are becoming more expensive, so there's more revenue to be gained. 

Hyperscalers Accelerating Purchases

Omdia says accelerated adoption of AMD's EPYC processors by hyperscalers in general, and Google in particular, helped AMD increase its share in Q2 2021. Cloud providers were Intel's stronghold for years, but it appears AMD is beginning to gain traction here, just like it gained traction with enterprises. 

Speaking of hyperscalers, it is necessary to note that they use whitebox servers produced by companies like Wiwynn, QCT (Quanta), Tyan (MiTAC), and Ingrasys (Foxconn). These companies controlled 26% of the market and produced $5.566 billion worth of servers in Q2 2021, up 17% quarter-over-quarter and 9% year-over-year. In fact, hyperscale cloud service providers like AWS, Azure, Facebook, and Google consumed more servers in the second quarter than any server vendor shipped during this timeframe. 

Speaking of big server vendors. Dell EMC maintained its lead and sold $3.655 billion worth of servers in Q2 2021. The company was followed by HPE with $2.727 billion (nearly a billion of USDs behind), whereas Inspur was No. 3 with $2.285 billion. Inspur's sales grew 45% quarter-over-quarter, so the company probably delivered several large orders to its clients in China. Meanwhile, the company's server sales dropped by 5% year-over-year. By contrast, Lenovo increased its server revenue to $1.652 billion, up 15% QoQ and 13% YoY.

Shipments of Servers at Risk

Since demand for servers is growing, everyone in the supply chain benefits. Omdia expects server revenue to hit $92 million for 2021 and increase by 11% compared to 2020. For obvious reasons, companies like AMD benefit more than makers of smaller components like power management ICs (PMICs) or network controllers. But as ironic as it is, makers of small components may put further growth of the server market in the second half of the year (and therefore server revenue) at risk. 

Lead times for some server components extended to 52 – 70 weeks by early July, forcing some manufacturers to procure loads of cheap but critical components, putting additional pressure on the supply chain. PMICs are made on 200-mm fabs that are relatively cheap, but building additional capacity takes a long time, so shortages will persist for quite a while. 

Summary

According to multiple researchers, AMD is gaining server market share as the server market grows due to demand from hyperscale cloud service providers. AMD has successfully won designs with enterprise server makers and is now gaining traction with hyperscalers, which almost guarantees steady shipment growth.

For now, AMD's EPYC CPUs have an indisputable trump over Intel's Xeon processors: their core count. However, component shortages could slow down server shipments and thus AMD's expansion.

If you want to cram up to 80 Arm Neoverse cores into a surprisingly compact workstation, Adlink has you covered with a novel design that packs an incredible amount of compute and memory onto a small carrier board. The board can then slot into a larger motherboard that fits inside standard E-ATX computer cases. 

The company has introduced one of the industry's first COM-HPC Server Type Size E Modules, using Ampere's Altra chip to build miniature systems with up to 80 Arm v8.2 64-bit cores. The platform is compliant with the COM-HPC standard and is intended for workstation, server and edge applications that require significant compute capabilities and low power consumption.  

Adlink's COM-HPC Ampere Altra Server Type Size E Module houses between 32 and 80 Arm Neoverse N1 cores, six memory channels supporting up to 768 GB of DDR4-3200 memory (using six DIMMs), and 64 PCIe 4.0 lanes.

The Ampere Altra Q80-28 SoC with 80 cores runs at 2.80 GHz and consumes around 175 Watts. Despite all that, the carrier board measures a diminutive 200×160 mm (7.87 x 6.3 inches), exhibiting spectacular compute density. You can then slot that carrier board into a larger motherboard that can fit inside E-ATX cases to create the Ava development system, as you can see in the picture and video below.

Adlink positions its Altra-based Server Module for workstations and 'inexpensive' edge applications that require low maintenance costs. The board has rather decent connectivity features (which can be further expanded using PCIe devices), such as four 10GbE ports, one GbE connector for remote management, and four USB 3.0 ports. The motherboard is also ready to install standard AArch64 Ubuntu 20.04 as well as Yocto Linux operating systems.

“By teaming up with Ampere and Arm and using their Arm Neoverse N1-based Ampere Altra SoC, our high performance-per-watt COM-HPC Ampere Altra architecture allows our strategic partners and customers to process data intensive workloads at the edge without worrying about big upfront investments, hardware overheating, or ongoing maintenance costs,” says Alex Wang, Adlink’s product manager of embedded boards and modules.

In addition to the COM-HPC Ampere Altra module, Adlink has also released its COM-HPC Ampere Altra prototype system that is designed primarily for software developers interested in building products for Arm-based servers. The company hasn't shared pricing or availability information yet, but we'll update as more information becomes available. 

As the semiconductor industry heads towards another inflection point, Intel, with its deep pockets, is letting other companies know that it is a willing buyer. Only time will tell what the company will buy, though.

As the semiconductor industry becomes more capital intensive it should enter another round of consolidation, according to Pat Gelsinger, chief executive of Intel. Chip design and production are becoming more expensive, which opens merger & acquisition doors for large companies like Intel. Speaking to the Wall Street Journal this week, Pat Gelsinger said that the semiconductor giant is willing to buy other players as the industry faces major transformations. The head of Intel made the comments after its alleged acquisition target GlobalFoundries reportedly started procedures to go public, scuttling any potential deal.  

Intel's CEO did not mention GlobalFoundries specifically in the interview, but he did say that the company was willing to buy smaller players in the semiconductor field when asked about the U.S.-based foundry.  

"There will be consolidation in the industry," Gelsinger said. "That trend will continue, and I expect that we are going to be a consolidator. […] M&A takes willing buyers and willing sellers. I am a willing buyer."  

The number of companies that can produce chips using leading-edge fabrication technologies is declining. Just 15 years ago there were a number of integrated design manufacturers (IDMs) and foundries that could roll out leading-edge nodes around the same time with Intel and challenge the blue giant. Now the number of IDMs and foundries have shrunk either as a result of M&A or because some companies ceased making chips. Today, only three companies in the world can produce chips using leading-edge processes and some cannot move beyond 14nm/12nm nodes, whereas others have not even entered the FinFET era. 

Like other big companies, Intel is always in an M&A mode as the company is permanently trying to acquire new IP and talent, expand its product lineup, and/or enter new markets. Intel has made dozens of acquisitions over the course of the most recent 25 years.  

Strategic acquisitions like the purchase of Altera in 2014 enabled Intel to enter the FPGA market; takeovers of Mobileye, Movidius, and Nervana made Intel a serious competitor in the fields of AI and autonomous vehicles; Chips and Technologies transaction was Intel's entrance into the graphics field; other deals strengthened Intel's existing product lines with new technologies and/or IP. What Intel has not done (at least not in recent history) was buying other makers of semiconductors as the company has always had enough production capacity.  

While Pat Gelsinger says that M&As are not at the top of his agenda as Intel's CEO, industry consolidation is something inevitable and Intel will have to participate in it. A takeover of GlobalFoundries makes great sense for Intel as a part of its IDM 2.0 strategy (even despite the fact that it will be hard to complete due to antimonopoly regulators). Furthermore, the ongoing economic processes might make some other companies a low-hanging fruit, or a strategic target that is not to be missed. 

In a press release today, Samsung has announced memory modules based on the CXL standard, bringing together PCIe 5.0 and DDR5 for AI and high-performance computing work in data centers.

CXL is an open standard first mooted in 2019, with a view to bringing high-speed, low latency communication between a CPU and its RAM, accelerator cards, and other devices, while expanding memory capacity and bandwidth greatly. CXL is based upon the industry supported PCIe 5.0 interface. With the new standard, which removes the limitations of limited memory channels, Samsung foresees RAM capacity scaling to multiple terabytes.

The Compute Express Link Consortium includes Samsung, AMD, ARM, IBM, Intel, Broadcom, Micron, and Nvidia among many others. It has previously been seen in Agilex FPGAs (Field Programmable Gate Arrays) made by Intel via its purchase of Altera Corporation.

It’s not just the new standard that marks these new memory modules out. Samsung has added new controller technologies such as memory mapping, interface converting and error management to the mix, and the new module has been successfully validated on next-generation server platforms from Intel.

Dr Debendra Das Sharma, an Intel Fellow and Director of I/O Technology and Standards at Intel, said, “Data center architecture is rapidly evolving to support the growing demand and workloads for AI and ML, and CXL memory is expected to expand the use of memory to a new level. We continue to work with industry companies such as Samsung to develop a robust memory ecosystem around CXL.”

The UK Secretary of State for Digital, Culture, Media and Sport on Monday began to probe AMD's proposal to acquire Xilinx for $35 billion. The CMA launched an inquiry inviting interested parties to notify it if the potential transaction can negatively impact UK's consumers or businesses. The deadline for the first phase of the investigation is July 6, 2021. 

"The Competition and Markets Authority (CMA) is considering whether it is or may be the case that this transaction, if carried into effect, will result in the creation of a relevant merger situation under the merger provisions of the Enterprise Act 2002 and, if so, whether the creation of that situation may be expected to result, in a substantial lessening of competition within any market or markets in the United Kingdom for goods or services," the statement by the CMA reads.  

Last October AMD and Xilinx announced that they reached a preliminary agreement for AMD to acquire Xilinx for $35 billion in an all-stock transaction. Shareholders of both companies approved the deal this April. 

AMD needs Xilinx, a leading developer of FPGAs, to better compete with Intel, which owns Altera. Both AMD and Xilinx could survive and prosper independently, but the management of these companies believes that the combined company will be stronger than the two separate businesses. 

With the takeover of Xilinx, AMD will be able to offer three types of compute devices used in datacenters: CPUs, GPUs, and FPGAs. Furthermore, it will be able to develop hybrid products combining general-purpose processor cores, compute GPU capabilities and field-programmable transistors.

Update 2/4/2020 6:00pm PT: Added additional pictures of delidded processor. We've added additional analysis below.  

Intel's CEO recently confirmed that the company had started to sample its next-generation Xeon Scalable 'Sapphire Rapids' processors to partners, so it isn't particularly surprising that the first images of the CPU have emerged, proving that the chip is in the hands of Intel's partners. 

Being a sample rather than a commercial product, the processor is marked as Intel Confidential and features the QVV5 sSpec, along with a 1.30 GHz frequency. The image was published by YuuKi_AnS, a known hardware leaker who sometimes has access to unreleased chips. 

We confirmed the CPU's validity with an independent source with knowledge of the matter, who identified the device as a 28-core Sapphire Rapids A2 sample that Intel sent to partners several weeks ago.

The backside of the chip looks exactly like it should, according to the blueprints of Intel's 4677-pin socket (made by TE Connectivity) that have floated around since at least October 2019. This might be considered more proof that the CPU is indeed a Sapphire Rapids sample in LGA4677 packaging. 

We understand that the A2 sample features 28 cores, but it is unclear whether the processor — which is made using Intel's 10nm Enhanced SuperFin process technology — uses a multi-chip-module (MCM) design or one monolithic die. The heat spreader on the CPU has one big bulge that can cover more than one chiplet. 

Update: YuuKi_AnS has published a photo of the delidded Sapphire Rapids processor revealing what is under the hood of the CPU. The Sapphire Rapids sample apparently carries four dies and an Altera Max 10 FPGA (which is probably used for startup/initialization purposes).

Using TE’s blueprint of Intel’s 4677-pin socket, we can estimate that an LGA4677 processor package measures slightly less than 72.4x54 mm, therefore occupying ~3,910 mm2. Using some very rough napkin math, we can estimate that the four dies occupy a significant portion of that area, which makes these chiplets fairly large.

Since we're allegedly looking at a 28-core CPU, each die should only have seven active cores. Unless Intel decided to pack enormously large caches and loads of special-purpose accelerators into its Sapphire Rapids chiplets, we can gather that each chiplet integrates a significantly higher number of cores (14, according to YuuKi_AnS), but at this point many of them are disabled. In any case, the image shows that Intel’s Xeon Scalable ‘Sapphire Rapids’ CPU uses four dies presumably interconnected using EMIB technology. Since it is inherently easier to make smaller chiplets than one large die, it should be easier for Intel to ramp up the production of its next-gen CPU for data centers and supercomputers.

It's noteworthy that the new alleged Intel Sapphire Rapids A2 sample doesn't look like another assumed sample of a Sapphire Rapids CPU, of which a picture emerged last year. The backside of the processor from December actually looks like the backside of an LGA4189 CPU, which means that it might not be a Sapphire Rapids in an LGA4677 package. Meanwhile, since the front side of the device has two bulges and does not look like the front side of Intel's Cooper Lake or Ice Lake-SP CPU, it is indeed an unannounced processor that allegedly uses an MCM design. 

One thing to note about the current leak is that YuuKi_AnS added two stickers to his pictures. The stickers carry the G14056-002 part number, which matches the part number of Intel's Xeon Phi 7120P. Obviously, the addition does not add any credibility to the leak, but since the CPU packaging corresponds to the LGA4677 blueprints and we have another confirmation from an independent source, it is highly probable that we are dealing with a Sapphire Rapids sample.    

As reported by Reuters, activist hedge fund Third Point, which reportedly owns a $1 billion stake in Intel, has penned a letter to Intel Chairman Omar Ishrak asking the company to explore "strategic alternatives," like spinning off its fabs and/or divesting itself of unsuccessful acquisitions, to address the company's recent market share losses. The hedge fund also cites an ongoing exodus of Intel's top chip designers, saying the company has a "human capital management issue" and that chip architects have been "demoralized by the status quo." 

The letter cites several of Intel's recent missteps, including losing the chip manufacturing lead to Taiwan-based TSMC and Korean chipmaker Samsung, which comes as a result of the company's delayed 10nm and 7nm process nodes. The hedge fund also notes that several of Intel's long-term customers, such as Apple, Microsoft, and Amazon, are now designing their own chips due to Intel's stagnation, eroding its customer base (particularly in the high-margin server market). The letter also cites Intel's share losses to AMD on the CPU side of the business and Nvidia's dominating position in AI workloads as signs that Intel needs to take drastic measures. 

The letter calls for Intel to retain an investment advisor to explore strategic alternatives, such as spinning off certain unsuccessful acquisitions or separating its fabs from its chip design operations. The latter would require spinning off the company's fabs into a separate business, possibly a joint venture, much like AMD did when it separated from GlobalFoundries.  

Intel posted a response to its investor relations site, stating: 

"Intel Corporation welcomes input from all investors regarding enhanced shareholder value. In that spirit, we look forward to engaging with Third Point LLC on their ideas towards that goal."

The prospect of Intel spinning off its fabs entirely seems unlikely. The company's native chip production capacity has helped it to largely avoid the shortages we've seen with other chipmakers, like AMD and Nvidia, in the wake of the global pandemic. Intel's tightly-controlled supply chains are also a strength that has helped it combat the waves of shortages that have impacted all facets of semiconductor production, such as secondary componentry like substrates and power ICs. 

In the past, Intel tried to operate as a contract chip manufacturer through its Intel Custom Foundry (ICF) initiative, which was largely a failure (in part due to 10nm delays, and also because Intel purchased Altera, it's largest ICF customer). That means Intel's most likely path to separating its chip design and fabrication efforts would come as some type of joint venture. Still, it's unclear if Third Point has made any significant suggestions to establish a framework for such a separation.  

Intel has already signaled an increased willingness to embrace third-party foundries to access their leading-edge nodes, thus expanding its existing use of third-party silicon to its core logic components (a first). However, that isn't a long-term solution to the company's woes: Intel has more than twice the semiconductor output of TSMC, which is largely thought to be Intel's presumptive partner for third-party chips. Given that TSMC is already capacity constrained, it obviously wouldn't have enough output to satisfy Intel's incredible volume without making massive long-term investments of its own. 

Those types of investments seem unlikely, given that Intel's business would likely be short-lived. Intel CEO Bob Swan recently said that even though Intel will now engage third-party foundries as strategic partners, it will continue to develop its own leading-edge nodes and has deployed a "fix" for its own 7nm node (though that fix has led to an untenable delay). 

Swan says that Intel will decide if it will turn to outside foundries as a stop-gap or invest in its own 7nm equipment, and also where and what to outsource, by "really early next year." However, Intel has taken crushing losses this year: Its stock is down 23% this year and is one of the worst-performing on the Dow. Investors are obviously losing patience – Intel's stock is up 7% on the news of the letter from the activist hedge fund. 

Taiwan Semiconductor Manufacturing Co.'s board of directors has approved spending $3.5 billion on the company's upcoming fab in Arizona. The project will be co-financed by TSMC, the state of Arizona, and the U.S. federal government. The first commercial wafers are expected to be produced at the fab in 2024.

A $12 Billion Plan

"Approved an investment to establish a wholly-owned subsidiary in Arizona, United States of America, with a paid-in capital of US$3.5 billion (approximately NT$99.75 billion)," the statement by TSMC reads.

Construction of the fab is scheduled to start in 2021 and the fab is projected to start high-volume production in 2024. The initial production capacity target of the facility is about 20,000 wafer starts per month (WSPM) and one of the nodes to be used there is TSMC's 5 nm, which probably means N5 as well as N5P fabrication technologies. TSMC’s evolutionary N4 process might land there as well, but the company has not formally announced this. 

In total, TSMC plans to spend $12 billion on its fab in Arizona from 2021 to 2029. The factory will employ about 1,600 people directly and thousands more indirectly. Keeping in mind that Intel Corp. already has multiple fabs in Arizona and Oregon, TSMC will not have to build a semiconductor industry supply chain from scratch, but rely on local suppliers.

TSMC’s Most Advanced Non-Taiwan Fab

In recent years, all of TSMC's advanced chips were produced solely in Taiwan. The company also owns a 200-mm Fab 10 in Shanghai, 300-mm Fab 16 in Nanjing, 200-mm WaferTech in Camas, Washington, and co-owns 200-mm SSMC in Singapore. These facilities are not quite in the same league as the company's domestic fabs that produce chips using leading-edge process technologies, such as 7 nm and 5 nm nodes.

TSMC's fab in Arizona will be the foundry's most advanced production facility outside of Taiwan, but it is not going to use the company's most sophisticated N3 node in 2024. TSMC's 3 nm technology is expected to enter volume production in the second half of 2022 in Taiwan and so far, the company has announced no plans to bring it to its U.S. subsidiary. 

TSMC's key customers — Apple, Altera/Intel, AMD/Xilinx, Nvidia, Qualcomm and many others — are from the U.S. Clients like Apple and Qualcomm tend to use the company's most advanced fabrication technologies, but also place the largest orders as they have very significant volume requirements. This is why TSMC tends to build so-called GigaFabs in Taiwan, facilities with a production capacity north of 100,000 WSPM. So, while bringing N5/N5P/N4 to the U.S. in 2024 seems like a good idea overall, the 20,000 WSPM fab may not serve TSMC's high-volume customers from North America until several years down the road.

Improving Competitive Positions in the USA

But the fab in Arizona clearly improves ties between TSMC and the U.S. government, which is good for TSMC’s military chip business and might be good if the federal government decides that it needs to produce chips for other sensitive applications solely in the USA.

Owning an advanced fab in the USA also makes TSMC more competitive with GlobalFoundries, which has been working hard for years to land orders for military and non-military U.S.-developed chips that need to be produced in America, as well as Samsung Foundry, which does not produce any sub-10 nm chips in the U.S. 

Last but not least, by running a fab in Arizona, TSMC will inevitably have to attract more American talent, which again makes it more competitive in general since these people will not work for other makers of semiconductors.

Taiwan Set to Remain TSMC’s Manufacturing Stronghold

With a plan to spend $12 billion on its Arizona fab in the U.S., TSMC clearly expands its presence in the country and while initial production volumes are not going to be high (20,000 WSPM is not a large fab by TSMC’s standards), the company scores a number of other goals with its new production facility. Eventually production capacities in the U.S. may be expanded, but for the foreseeable future Taiwan will remain the company’s manufacturing base.

The same board meeting that approved the $3.5 billion investment in the Arizona fab also approved capital appropriations of approximately $15.1 billion (approximately NT$430.6 billion) to build new manufacturing capabilities in Taiwan.  

The giant investments will be used to build a new fab (presumably we are talking about TSMC’s fab near Hsinchu, Taiwan, that will be used to make 2-nm chips towards the middle of the decade), expand leading-edge production capacities, install new tools to offer specialty process technologies, install or upgrade advanced packaging fabs, and on research and development in Q1 2021. 

Typically, TSMC tends to spend tens of billions of U.S. dollars every year on CapEx in Taiwan and such investments can hardly be compared to $3.5 billion the company intends to spend in Arizona.

In what could be a move to broaden its attack on rival chipmakers Intel and Nvidia, the Wall Street Journal reports that AMD is in advanced talks to buy FPGA-maker Xilinx in a deal that could top $30 billion. The talks are said to have resumed after a recent pause, so it's unclear if they will result in a successful acquisition, but a decision could come as early as next week. We've reached out to AMD for comment and will update accordingly.

Xilinx is primarily known for its FPGA products. The two companies have a history of working in close collaboration on deep learning projects, such as the Xilinx deep learning solution on AMD EPYC processors (among many other pursuits).

FPGAs (Field Programmable Gate Arrays) are semiconductor devices that can be rapidly reconfigured on the fly. They offer certain advantages over other types of devices, like CPUs and GPUs, in a wide variety of workloads. 

Xilinx has a full spate of cutting-edge tech under its roof. Its latest 7nm Versal Premium ACAPs feature the PCIe 5.0 interface and support the CXL interconnect, 112G transceivers, 600G ethernet cores, and 123 TBps of bandwidth across its network-on-chip (NOC). You can read the full details of the company's APAC platform here.

Bringing Xilinx's technology portfolio into AMD's war chest could enable tightly-integrated CPU+FPGA solutions that would fit well within AMD's current chiplet-inspired design methodologies. It's easy to envision future EPYC data center processors with integrated FPGA chiplets to boost AI workload performance.

Xilinx's broad technology pallet includes leading-edge connectivity options that could also serve as a backbone for more expansive data center architectures. AMD would certainly have plenty of options with Xilinx under its roof; the FPGA maker currently engages in the automotive, aerospace and defense, data center, HPC, industrial, IoT, and communications markets. The firm also has deep experience in software development/enablement. 

Notably, Intel purchased Xilinx's main rival, FPGA-maker Altera, for $16.7 billion in 2015, and has integrated the company into its Programmable Solutions Group (PSG). If the reported AMD purchase of Xilinx goes through, it will certainly open up another front in its attack on Intel's broad TAM. You can see the full roster of Intel's AgileX FPGAs that come as a result of the Xilinx acquisition here.

The AMD news comes in the wake of Nvidia's ongoing efforts to purchase ARM for $40 billion and could mark yet another big deal during an ongoing wave of industry consolidation. Xilinx also has a solid portfolio of SmartNic/DPUs that would serve as a nice AMD parry to Nvidia's DPU thrust that comes as the fruits of its Mellanox acquisition. 

The WSJ reports that AMD will likely leverage its high stock valuation, it now has a $100 billion market cap, as currency to purchase Xilinx.

This is breaking news..updates to come. 

Today, Ampere announced plans to expand its Altra family of server processors with the Altra Max chip, which arriving by the end of the year with a whopping 128 CPU cores.

Similar to the Amazon Graviton2, the Ampere Altra is based on Arm's Neoverse N1 (codename Ares) microarchitecture. TSMC carves the Altra for Ampere with its 7nm FinFET manufacturing process. The Altra family currently features 11 different models, however, the list and specifications are subject to change. 

Each core inside the Ampere Altra corresponds to a single thread and comes with its own cache. We're looking at 65KB of L1I cache, 64KB of L1D cache and 1MB of L2 cache per core. 

As for the Altra line's other attributes, the 7nm processors each support up to eight channels of DDR4-3200 ECC memory and a maximum capacity up to 4TB . For expansion, the Altra provides 128 lanes of high-speed PCIe 4.0 lanes per socket, but also support up to 192 PCIe 4.0 lanes in a 2P setup.

Ampere Altra Specifications

Ampere has one of the simplest CPU nomenclatures known to mankind. The Q, which stands for Quicksilver, is followed by the chip's number of cores and then the clock speed. 

The Q80-33 is the current flagship of the Altra family. The processor delivers 80 cores up to 3.3 GHz within a 250W package. 

The Q80-33 will eventually pass the torch to the Altra Max, which will flaunt up to 128 cores. Ampere has confirmed that the Altra Max (codename Mystique) will be socket-compatible with current Altra offerings. We suspect that the the Altra Max will have an M prefix in its model names.

Ampere will sample the Altra Max in the fourth quarter of this year, and the processor should be available next year. 

The company is also firm on its commitment to roll out the 2nd Generation Altra processors (codename Siryn) in 2022. If the nomenclature remains the same, the Siryn should sport the S prefix. The next-generation processors will leverage TSMC's 5nm process node.

Ampere expects to sample Siryn in the latter part of 2021 with a scheduled launch in 2022.

AMD has hired top Intel executive Daniel “Dan” McNamara to grow the chipmaker’s Epyc business after last year’s launch of Rome. The hire comes amid several other promotions.

Dan McNamara led Intel’s FPGA group after joining the company from Intel’s acquisition of Altera in 2015. Most recently, he served as the general manager and senior vice president of Intel’s Network and Custom Logic Group, which consists of the company’s network infrastructure and Intel FPGA groups. That group was formed last year, but he left in October already, according to CRN.

McNamara will now take on a similar role at AMD, leading the company’s Server Business Unit, which falls under Forrest Norrod’s Datacenter and Embedded Solutions Business Group. According to AMD, he will be responsible for building on the successful launch of the second-generation Epyc Rome processors in 2019 and accelerate adoption among cloud and enterprise customers, AMD says.

AMD has also promoted four others to senior vice president (SVP):

• Nazar Zaidi to SVP of Cores, Server SoC and Systems IP Engineering with continued responsibility for leading the development of leadership CPU cores, server SoCs and system IP.
• Andrej Zdravkovic to SVP of Software Development, which spans graphics, client and data center products.
• Spencer Pan to SVP of Greater China Sales and president of AMD Greater China.
• Jane Roney to SVP of Business Operations.

AMD CEO Lisa Su commented: “Strengthening and expanding our leadership team are key to building on the significant momentum we have generated over the past several years. I am delighted to announce these additions to our senior leadership team. Each of these leaders will play key roles in helping us achieve our long-term growth objectives in the coming years.”

SoC stands for system on a chip. This is a chip/integrated circuit that holds many components of a computer—usually the CPU (via a microprocessor or microcontroller), memory, input/output (I/O) ports and secondary storage—on a single substrate, such as silicon. Having all of these components on one substrate means SoCs use less power and take up less space than their multi-chip counterparts. SoCs are becoming increasingly popular with the growth of Internet of Things and edge and mobile computing. Take, for example, Intel’s September 2018 acquisition of SoC firm Silicon Engineering Group and older acquisitions of Altera and others.

One common example of tech that uses an SoC is video game consoles, such as the Nvidia Tegra X1 used in the Nintendo Switch or the AMD Flute and AMD Gonzalo SoCs expected to power the next Xbox and PlayStation, respectively. Raspberry Pi computers, Arduino boards and STEM kits also use SoCs. SoCs are often used in STEM kits because they are easy to use, and, therefore, helpful in teaching STEM. You also find SoCs in smartphones and tablets. 

Broadly speaking, there are three different types of SoCs:

• SoCs that use a microcontroller (a chip with the CPU, RAM, ROM and potentially other components). Example: Arduino boards
• SoCs that use a microprocessor (a chip with a CPU only). Examples: SoCs for smartphones, like Qualcomm’s Snapdragon 845 (also used for virtual reality headsets) and the Apple A12 Bionic SoC used in the iPhone XS, iPhone XS Max and iPhone XR. Rasperry Pi and Intel's line of SoC FPGAs.
• SoCs for specific applications, which may or may not use a microprocessor or microcontroller. This is known as an ASIC (application-specific integrated circuit).

This article is part of the Tom's Hardware Glossary.

Further reading:

• Raspberry Pi: Projects, Models, Prices, How to Get Started
• Best Kids' Robots: STEM Kits That Teach You to Code
• I Turned My Six Year Old Into a Code-Wielding, Robot-Building STEM Fan. Here's How.

Intel announced on Thursday that it had begun shipments of the first of its 10nm Agilex FPGAs to early access customers, including Microsoft. Intel says they will use it to create solutions for networking, 5G and accelerated data analytics.

With the announcement, Intel follows in the footsteps of its competitor Xilinx, who started shipping its next-gen Versal ACAPs roughly two months ago. We provided a comparison of the products at the time. Despite being later than the once-promised second half of 2018, Intel is surely going to like the fact that it has practically erased the gap of roughly a year it had at the 16/14nm generation.

When Intel acquired Altera in 2016, the story it liked to tell was that the FPGA company that moved earlier to a new process node tended to have the most market share that generation, and hence that one of the benefits of Intel was that it could leverage its process technology lead to gain share on Xilinx. With the two companies now neck and neck, other merits will likely decide in whose favor the market share will swing.

Intel says that the participants of the early access program include Colorado Engineering Inc., Mantaro Networks, Microsoft and Silicom. Microsoft said it plans to use Agilex in a number of its upcoming projects. Dan McNamara, SVP of the recently formed Networking and Custom Logic Group (formerly the Programmable Solutions Group) at Intel, pitched Agilex as follows:

“The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology. These unmatched assets enable new levels of heterogeneous computing, system integration, and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link.”

Intel introduced Agilex in April as we detailed, but its changes can be summarized as follows:

• 10nm process and EMIB 3D SiP packaging to support a custom logic continuum: integrate analog, memory, custom computing, custom I/O and Intel eASIC (structured ASIC) device tiles
• The first FPGA to support Compute Express Link (CXL) for a low latency, memory coherent interconnect to future Xeon Scalable processors
• 2^nd generation HyperFlex architecture for 40% higher performance or 40% lower power
• ~2x DSP floating-point performance, or 4x (up to 40TFLOPS) using the newly supported FP16 and BFLOAT16 data formats
• Support for (up to) DDR5, PCIe 5.0, HBM3 and 112G transceiver speeds

Intel subsidiary Altera, now Intel’s Programmable Solutions Group, on Friday lost a court case about a tax regulation that was also closely watched by other technology companies, like EA, eBay, Microsoft and Google, with billions of dollars of tax revenue at stake. As reported by The Wall Street Journal, the federal appeals court however sided with the Internal Revenue Service (IRS).

The Altera-IRS case revolved around share-based compensation, a popular way for companies to reward employees. The IRS had written a regulation that required companies to deduct more of it as an business expense abroad instead of deducting it in the U.S, which was favorable. This was especially relevant before the late 2017 tax law that reduced the tax rate (and hence narrowed the gap compared to foreign tax rates), since companies benefited from deducting the share-based compensation expenses against the higher U.S. tax rate.

On Friday, the Ninth Circuit Court of Appeals ruled 2-1 for the IRS over Altera. Chief Judge Sidney Thomas wrote: "We disagree with the Tax Court that the 2003 regulations are arbitrary and capricious. While the rulemaking process was less than ideal, the [law] does not require perfection." 

The result of the case is the same as last year. "We conclude that the regulations withstand scrutiny under general administrative law principles, and we therefore reverse the decision of the Tax Court," Sidney Thomas wrote at the time. The court heard the case again because one of the judges had died before the ruling was issued.

Intel did not want to comment, but last year Intel had expressed disappointment in the ruling.

The Altera case involved taxes on a relatively small $80 million of revenue, but a positive outcome of the case could have had a much larger impact for other companies, who were hence watching the case closely. Tech giants such as Google's parent Alphabet, EA, eBay, Microsoft and Google have cited the outcome of the case as a risk factor in their financial statements. For instance, Alphabet said it in 2016 that it could gain at least $3.5 billion if Altera prevailed.

FPGAs are often used for video and vision processing applications. To improve its position in this key market, Intel today announced the acquisition of the UK based Omnitek, a provider of IP and customized solutions for FPGAs. The deal contributes to Intel’s strategy to bring full solutions to the market that extend beyond just the silicon.

Omnitek specializes in vision, video, and image processing solutions for workloads like video over IP, projector video processing, video conferencing and AI inferencing. The company has developed a wide breadth of IP, often replacing ASICs and ASSPs with FPGAs.

Omnitek last year introduced its DPU (deep learning processing unit) for AI inferencing, achieving 16.8 TOPS of INT8 performance on a Xilinx UltraScale+ FPGA. The DPU is programmable in C, C++ or Python and supports various common topologies such as CNNs (convolutional neural networks). This programmability is one of the key features that make FPGAs attractive for deep learning inferencing. 

For Intel, this acquisition fits in their strategy for providing end-to-end solutions to customers, like its Select Solutions for the data center, the upcoming Project Athena for the PC, or full self-driving car solutions with Mobileye. Dan McNamara, SVP of Intel's Programmable Solutions Group, said: “Omnitek’s technology is a great complement to our FPGA business. Their deep, system-level FPGA expertise and high-performance video and vision-related technology have made them a trusted partner for many of our most important customers. Together, we will deliver leading FPGA solutions for video, vision, and AI inferencing applications on Intel FPGAs and speed time-to-market for our existing customers while winning new ones.”

As the second part of Intel's strategy in artificial intelligence and IoT, the company has put a lot of focus on improving its vision portfolio. About a year ago, Intel introduced the OpenVINO toolkit for vision AI inferencing at the edge, also supporting FPGAs.

And lastly, IP such as Omnitek’s lowers the bar to deploy FPGAs, attracting more developers to use them, as Omnitek's own DPU demonstrates. This was one of the important points that Intel made with Agilex and OneAPI, which we recently covered with their Data-Centric Innovation Day. For more information about FPGAs, be sure to read this explainer. 

This is the second major acquisition to support Intel's Programmable Solutions Group after they acquired eASIC last year. Intel didn't provide financial details.

In-Depth on AgileX: Intel Making FPGAs Accessible

Intel announced its next-generation 10nm AgileX FPGA, which it had formerly announced under the Falcon Mesa codename, at its Data-Centric Innovation Day. Intel's AgileX comes brimming with next-gen tech, like support for PCIe 5.0, DDR5, HBM3, Optane Memory DIMMs, and memory coherency with Xeons.

Altera was one of the first and only high profile customers that Intel announced for its Custom Foundry. Over time there was also talk that Altera would be the first to use Intel’s 2.5D EMIB (Embedded Multi-Die Interconnect Bridge) packaging technology, which Intel touts as a cheaper and superior alternative to the interposer for chiplet mix-and-match strategies.

Intel liked Altera so much that it acquired the company in early 2016 for $16.7 billion. As a backgrounder, Altera designed and manufactured its previous-gen Stratix 10 FPGAs on Intel’s 14nm node, succeeding the 20nm Arria generation. Those eventually launched in the second half of 2017.

After the acquisition, the Altera design team was still working on Stratix 10, so Intel set up a second, parallel development team that began work on the 10nm generation. And while we will cover the whole breadth of technology that makes up this product, it is interesting that this is the first FPGA conceived and designed with Altera as an integrated part of Intel. Intel is eager to emphasize this point, as it allowed it to design this new family from the ground up, from architecture development and process/packaging co-optimization to I/O and software.

Intel has a very broad portfolio of data-centric IP, and FPGAs have followed a trend of integrating increasingly more of that IP. Deeper IP integration was also one Xilinx’s (Intel's primary FPGA competitor) messages behind its 7nm Versal (formerly Project Everest) FPGA. Xilinx intends to launch its competing FPGA in 2019. 

AgileX: FPGA for the Data-Centric World

As a broad overview, Intel focuses on three main goals for AgileX: high-performance compute capabilities, any-to-any integration, and software. In short, AgileX is based on the Hyperflex 2 architecture built on the 10nm process and delivers 20 TFLOPS of single-precision performance. Intel is also using EMIB to connect any chiplet tile and any process node to the FPGA. That allows the company to tune and highly personalize the FPGA to the needs of each customer. Finally, Intel wants to make FPGAs accessible to all software developers with its OneAPI programming interface.

Compute: Hyperflex 2

The 10nm AgileX FPGA also incorporates memory coherency with Xeon processors and includes several high bandwidth and memory capabilities.

First and foremost, AgileX will provide a welcome boost in performance. Altera introduced the Hyperflex architecture (PDF) in Stratix 10. The idea behind Hyperflex is to weave in bypassable hyper-registers throughout the core fabric, in every routing segment, on all block inputs, and throughout the FPGA's interconnect. Hyperflex has more than 10x the number of hyper-registers than ALM registers, which allows any path between logic cells to be registered.

This enables a new approach for improved timing, pipelining, and optimization to eliminate critical paths that cause routing delays, along with unlocking additional software optimization opportunities. This architecture combined with the 14nm process helped Stratix 10 achieve a 4x higher logic density and 2x increase in clock speed (or 70% lower power).

Intel isn't releasing Hyperflex 2 architecture specifics but says that AgileX will be up to 40% faster than Stratix 10 or consume 40% less power. Intel has also doubled its DSP capabilities, providing 20 TFLOPS of single-precision or 40 TFLOPS of half-precision performance. Intel says AgileX is the only FPGA with hardened FP16 and Bfloat16 capabilities.

On the memory side, which Intel says is becoming more and more important, AgileX adds support for DDR5, HBM3, and Optane DC Persistent Memory DIMMs. This covers the entire memory spectrum from low latency devices to SSDs, too.

To expand the interconnect beyond the confines of the chip, AgileX is compatible with both PCIe 4.0 and PCIe 5.0, though PCIe 5.0 support will come at a later date. These faster interfaces double or quadruple the data rate compared to PCIe 3.0. Intel also looks to extend its transceiver leadership with 112G transceivers. Intel tells us that they are currently the only FPGA vendor shipping with 58G PAM-4 transceivers, while Xilinx is still on 28G.

FPGA for AI

For AI, Intel touts its "AI Plus" as a key value proposition. This technology means an FPGA can also do data ingest and preprocessing before it uses the actual neural network. Intel also tweaked the DSP blocks to enhance AgileX's suitability for AI workloads. Seeking to retain its leading floating-point performance, Intel added additional DSP hardware to achieve 40 TFLOPS of FP16 performance and added hardened Bfloat16 support like the Cooper Lake, Ice Lake, and Nervana Spring Crest processors that are also coming to market this year. Intel says AgileX is the only FPGA with hardened FP16 and Bfloat 16 support.

On the integer side of things, Intel added support for lower precision INT8 through INT2 and said AgileX will deliver up to 92 TOPS INT8 performance. All this is supported on the software side by Intel's OpenVINO toolkit and OneAPI.

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Any-to-Any Integration and Memory Coherency

Xeon Memory Coherency

Intel says that AgileX will be the first memory-coherent accelerator for Xeon Scalable processors.

Over the last year, Intel has introduced Programmable Accelerator Cards (PACs) containing an FPGA connected to the CPU via PCIe, basically the analogue of graphics cards for FPGAs. That is where the accelerator-for-Xeon part comes from. The new part here is memory- or cache-coherency. This enables the CPU and FPGA to share a common memory space to reduce overhead, latency and data movement, basically allowing the FPGA and Xeon to work on the same data in parallel.

Intel says coherency is very important and will drive a number of new applications in both the network and the cloud, like database acceleration, infrastructure offload applications, and functions-as-a-service.

Memory coherency is made possible by the Compute Express Link (CXL) interconnect (announced last month). To recap briefly, this is a new protocol, similar in nature to NVLink, OpenCAPI, Gen-Z, and CCIX, that works over the PCIe electrical interface (PCIe 5.0 for CXL) and serves as a high-bandwidth, low latency interconnect between the CPU and accelerators like GPUs and FPGAs. It also supports any other accelerator, and even memory.

To sum up, the advantages of memory coherency and CXL are resource sharing for higher performance, reduced overhead and latency, reduced software stack complexity and, lastly, lower overall system cost because the technology is plug-and-play. As a side note, today Intel uses its ultra-path interconnect (UPI) for connecting multiple Xeons.

Any-to-Any Integration

True to Intel's design goals with chiplets, the AgileX FPGA consists of a central monolithic die connected to smaller packages (chiplets) that provide several essential functions. Any-to-any integration means Intel can integrate any chiplet from any foundry.

The Intel AgileX block diagram gives a few interesting examples of the versatility of this approach. The FPGA fabric itself is still monolithic (although that might change when 3D Foveros chip stacking comes into the picture), but Intel outlines several examples of chiplets. As an aside, Stratix 10 supports six chiplets, so this diagram with five chiplets probably does not disclose how many chiplets Intel can attach to the central AgileX die.

Obviously, support for transceivers and HBM remains, but Intel bumped support up to 112G and HBM3, respectively. There is also a chiplet for PCIe 5.0 connectivity, and this example really demonstrates the agility (pun intended) of AgileX. PCIe 4.0 products arrive this year, but AgileX supports PCIe 5.0 via an Intel-produced chiplet. This option will not be available at launch, but Intel can add the capability later. That will significantly enhance the platform capabilities over time, as PCIe 5.0 is also required for memory coherency. This is possible because PCIe 5.0 is backwards compatible with PCIe 4.0 and because EMIB uses its own protocol (called AIB) for communication between the two chiplets.

Chiplets can also consist of custom compute tiles, custom I/O, and the CPU coherent interface (I/F). Higher core count dies, with CPUs from the Cortex A7x series, analog and digital converters, and “optical chiplets” are also planned. All those chiplets reside next to the FPGA in the same chip package. Xilinx has chosen Versal for its 7nm branding, but Intel's FPGA is arguably far more versatile.

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OneAPI and the AgileX Family

Enabling Any Developer Through OneAPI

To make FPGAs broadly accessible to traditional software developers, AgileX will support the OneAPI programming environment. While there is a lot of hardware in AgileX, Intel argues that its (OneAPI) software is more important than the hardware for AgileX. Intel says the hardware really doesn't matter if they can't make it easier to program FPGAs, which in turn expands the user base. For their core RTL developers, Intel claims a 30% reduction in compile times and a 15% improvement in memory utilization with the latest version of Quartus Prime. This version is coming this month and will also add support for AgileX.

The Product Family

Intel announced three series as part of the AgileX product family.

The F-series is the most basic, and we think it is probably the only one that will be available initially. It supports up to 58G transceivers, PCIe Gen4 and DDR4. The base die also contains a quadcore A53 CPU, although Intel has strongly hinted that there will a chiplet with an A7x series octa-core SoC.

The point of the A53 is not to burden the base FPGA with too many CPU transistors, with the general message being that higher performance CPUs and higher core counts chiplets can be provided in extra tiles via EMIB, so only those customers who need it have to pay for it.

The I-series is meant for bandwidth-intensive applications, so it includes 112G transceivers and PCIe Gen5 support. This allows the coherent memory attachment to Xeon Scalable to be added, as the CXL interconnect requires PCIe 5.0. Lastly, the M-series adds high-bandwidth memory (HBM).

The first device becomes available in Q3, which Intel said is “right on schedule with what we expected.” We're sure this is a statement about product sampling because Intel gave a presentation in late 2017 that mentioned the second half of 2018 for sampling. General availability typically begins about a year after sampling.

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The Logic Continuum and Closing Thoughts

Innovation Race at the Edge, Comms, and Cloud

Ever since Intel's Bob Swan (now CEO) took over as CFO in late 2016, Intel has consistently shifted its messaging towards becoming a data-centric company. FPGAs fall coherently into that picture by being workhorses for processing, storing and moving data. In fact, with 5G, AI and IoT and all the ways data is being created, Intel believes that it is in the largest FPGA adoption cycle in history.

This massive amount of data is causing what Intel calls an innovation race. From the edge to the network to the cloud, companies are racing to innovate and get solutions to market as fast as possible. FPGAs are ideal for these workloads and afford a faster time to market, while still allowing companies to provide customized solutions.

Custom Logic Continuum

Intel’s goal, however, is to support customers throughout the whole lifecycle of a solution. As the pace of innovation slows down, customers will start focusing more on power, performance, and cost. This is where Intel positions eASIC, a company it acquired last year that designs structured ASICs. Those chips combine some characteristics of FPGAs and ASICs. For instance, eASIC's design time is closer to an FPGA, and the chips capture some of the power and performance benefits of an ASIC. But on the downside, they lose programmability.

The eASIC eventually paves the way for a fully-custom ASIC design. Intel also has design teams working to fulfill its goal to be part of the whole lifecycle of a product from programmable to custom. This is what Intel calls the "custom logic continuum" that it claims no other vendor can provide.

The key is the reusable IP. You begin with the FPGA, move to an eASIC, and lastly port it to an ASIC. Intel plans to evolve all three of these families. eASIC is currently fabbed on the 28nm process, but they can be built on various nodes. Intel tells us to expect to hear more about its plans for eASICs in the second half of the year.

While Intel does not forget its core embedded markets of old, it sees the edge, networking, and cloud as the three main catalysts for further FPGA adoption. Each of those categories leverages both the core value proposition of an FPGA, like time to market, programmability, and some additional aspects.

At the edge, it’s all about delivering real-time, low latency intelligence and data processing, such as frame-by-frame video processing. In the communications infrastructure market, FPGAs accelerate diverse packet-processing applications that require copious amounts of bandwidth. Obviously, cloud use-cases are even more diverse. But for the cloud service providers themselves, they want to rent clock cycles to their customers, so every clock cycle used for something else is wasted. For them, FPGAs can be used for infrastructure offload applications.

To sum up, Intel’s goal is to drive ultimate capabilities in agility, flexibility, and scalability to move, store and process data, for which FPGAs are the first step in the custom logic continuum.

Closing Thoughts

Intel has brought a long laundry list of new features and capabilities to AgileX. As the first FPGA conceived from the ground up as part of Intel, Intel’s Programmable Solution Group has done a surprisingly good job at aligning their development with Intel's broader, data-centric strategy. This is evident from support for Optane Persistent Memory, Bfloat16, memory-coherency with Xeons via the CXL interconnect, and support for OneAPI.

Altera was already an Intel foundry customer and used its EMIB interconnects for the previous-gen Stratix 10, but it looks like Intel can really take heterogeneous integration to the next level with AgileX. It’s early days, but Intel envisions a whole ecosystem of both standard and custom chiplets from eASIC that it can connect via EMIB to personalize the FPGA.

Intel's acquisition of eASIC together with its existing ASIC teams also gives it the opportunity to be part of the complete custom logic continuum lifecycle, which is a unique capability. It will probably take time for Intel to build this ecosystem out, but we can already see one big benefit with the new memory coherency with Xeon. This functionality is built upon the PCIe 5.0 CXL interconnect, but Intel expects CXL to come to market in 2021, well after the initial AgileX launch. The mix-and-match design allows Intel to add the memory coherency capability later without respinning the entire FPGA. It should be clear this goes far beyond simply adjusting the number of chiplets connected to an I/O die as some of Intel's competitors do.

The base FPGA should provide a hefty performance and power improvement through the benefits of the 10nm process, second-gen Hyperflex architecture, and increased DSP capabilities for both floating-point and integer operations (which go as low as INT2). Intel also ticked the boxes for DDR5, HBM3, and 112G transceivers. The base die also contains a quad-core A53 CPU.

Intel hopes this combination of capabilities will provide the most flexible, scalable, and agile FPGA for the data-centric world as AI, 5G and IoT fuel an explosion of data that Intel says will spur the largest adoption cycle of FPGAs in its history. From what we’ve seen, the amount of technology packed into AgileX is impressive. The design touches virtually every asset of Intel’s portfolio, with OneAPI serving as the cornerstone that ties Intel’s portfolio together for all software developers.

Lastly, at the Architecture Day in December, Intel showed a concept of an FPGA as a “sea of reconfigurable sectors.” This design stacks several layers of FPGA via Intel’s new 3D packaging technology Foveros on a 7nm process. As one last tidbit that we got from our briefing, Intel described Foveros as “Phase 2” of AgileX. As Dan McNamara, SVP of the Programmable Solutions Group, confirmed: “We’re looking at that for future derivatives of AgileX.” To what extent Intel will use Foveros in Phase 2 is unclear, but it’s clear there is more to come.

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Cascade Lake and Friends

Intel announced its Cascade Lake line of Xeon Scalable data center processors at its Data-Centric Innovation Day here in San Francisco. The second-generation lineup of Xeon Scalable processors comes in 53 flavors that span up to 56 cores and 12 memory channels per chip, but as a reminder that Intel company is briskly expanding beyond “just” processors, the company also announced the final arrival of its Optane DC Persistent Memory DIMMs along with a range of new data center SSDs, Ethernet controllers, 10nm Agilex FPGAs, and Xeon D processors.

This broad spectrum of products leverages Intel’s overwhelming presence in the data center (it currently occupies ~95% of the worlds server sockets), as a springboard to chew into other markets, including its new assault on the memory space with the Optane DC Persistent Memory DIMMs. The long-awaited DIMMs open a new market for Intel and have the potential to disrupt the entire memory hierarchy, but also serve as a potentially key component that can help the company fend off AMD’s coming 7nm EPYC Rome processors.

Intel designed the new suite of products to address data storage, movement, and processing from the edge to the data center, hence its new Move, Store, Process mantra that encapsulates its end-to-end strategy. We're working on our full review of the Xeon Scalable processors, but in the meantime, let's take a closer look at a few of Intel's announcements. 

56 Cores, 112 Threads, and a Whole Lotta TDP

AMD has already made some headway with its existing EPYC data center processors, but the company’s forthcoming 7m Rome processors pose an even bigger threat with up to 64 cores and 128 threads packed into a single chip, wielding a massive 128 cores and 256 threads in a single dual-socket server. The increased performance, and reduced power consumption, purportedly outweighs Intel’s existing lineup of Xeon processors, so Intel turned to a new line of Cascade Lake-AP processors to shore up its defenses in the high core-count space. These new processors slot in as a new upper tier of Intel's Xeon Platinum lineup.

These new 9000-series chips come packing up to 56 cores and 112 threads in a dual-die MCM (Multi-Chip Module) design, meaning that two die come together to form a single chip. Intel claims the processors offer the highest-performance available for HPC, AI, and IAAS workloads. The processors also offer the most memory channels, and thus access to the highest memory bandwidth, of any data center processor. Performance density, high memory capacity, and blistering memory throughput are the goal here, which plays well to the HPC crowd. This approach signifies Intel's embrace of a multi-chip design, much like AMD's EPYC processors, for its highest core-count models.

The 9200-series comes in three flavors with 56-, 48-, and 32-core models on offer. Clock speeds top out with the 56-core Xeon Platinum 9282 model with a 3.8 GHz boost, and base speeds weigh in at an impressive 2.6 GHz. The flagship Xeon Platinum 9282 also comes equipped with 77MB of L3 cache.

Each processor has two internal die that consists of modified 28-core XCC (extreme core count) die, and each die wields a six-channel memory controller. Together, this gives the processor access to 12 channels of DDR4-2933 memory, providing up to 24 memory channels and 3TB of DDR4 memory in a two-socket server. That facilitates up to 407 GB/s of memory throughput for a two-socket server equipped with the 56-core models.

Intel still uses garden-variety thermal interface grease between the die and heatspreader, but the 9282 weighs in with a monstrous 400W TDP, while the 48-core models have a 350W TDP and the 32-core models slot in with a 250W rating. Intel says the 400W models require water cooling, while the 350W and 250W models can use traditional air cooling. Unlike the remainder of the Cascade Lake processors, these chips are not compatible with previous-generation sockets. Instead of being socketed processors, the 9200-series processors come in a BGA (Ball Grid Array) package that is soldered directly to the host motherboard via a 5903-ball interface.

The 9200-series chips also expose up to 40 PCIe 3.0 lanes per chip, for a total of 80 lanes in a dual socket server. Each die has 64 PCIe lanes at its disposal, but Intel carves off some of the lanes for UPI (Ultra-Path Interconnect) connection that tie together the two die inside the processor, while others are dedicated to communication between two chips in a two socket server. Overall, that provides four UPI pathways per socket with a total of 10.4 GT/s of throughput. 

A dual-socket server presents itself as a quad-socket server to the host, meaning the four NUMA nodes appear as four distinct CPUs, but the dual-die topology poses latency challenges for access to 'far' memory banks. Intel says it has largely mitigated the problem with a single-hop routing scheme that provides 79ns of latency for near memory and 130ns for far memory access.

Intel has provided its partners with a reference platform design that crams up to four nodes, each containing two of the 9200-series processors, into a single 2U rack enclosure. Intel hasn't announced pricing for the chips, largely because they will only be available inside OEM systems, but says they are shipping to customers now.

Let's shift gears to the standard socketed Xeon processors.

Cascade Lake Xeon Platinum, Gold and Silver

Intel's new mainstream Xeon processors come as an iterative update to its Purley lineup and leverages the same Skylake microarchitecture as its predecessor, but Intel claims the new chips offer, on average, a 30% gen-on-gen performance boost in real-world workloads. Comparing Intel's Cascade Lake to the previous-gen models, the company offers up to 25% more cores at the same price points.

Cascade Lake also represents Intel's first data center processors with in-silicon mitigations for the notorious Meltdown and Spectre vulnerabilities. The existing patches result in reduced performance that varies based on workload, but newer mitigations baked directly into the processors should help reduce the impact.

Cascade Lake features many of the same fundamental design elements of the Xeon Scalable lineup, like a 28-core ceiling, up to 38.5 MB of L3 cache, the new UPI (Ultra Path Interface), up to six memory channels, AVX-512 support, and up to 48 PCIe lanes. These processors drop into the same socket as the existing generation of Purley chips. 

Intel's most notable advancements come on both the process and memory support front. Intel boosted memory support from DDR4-2666 to DDR4-2933 and doubled capacity up to 1.5TB of memory per chip. The company has moved forward to the 14nm++ process. Intel says the updated process allowed it to improve frequencies, power consumption, and institute targeted improvements to critical speed paths on the die.

Intel's new DL Boost suite adds support for multiple new AI features, which the company claims makes it the only CPU specifically optimized for AI workloads. Overall, Intel claims these technologies provide a 14X performance increase in AI inference workloads. Intel also added support for new VNNI (Vector Neural Network Instructions) that optimize instructions for smaller data types commonly used in machine learning and inference. VNNI instructions fuse three instructions together to boost int8 (VPDPBUSD) performance and fuse two instructions to boost int16 (VPDPWSSD) performance. These AVX-512 instructions will still operate within the normal AVX-512 voltage/frequency curve during the operations.

Intel's Cascade Lake lineup has grown tremendously with the addition of several new types of processors designed for specific use-cases, and the company continues to segment its stack into Platinum, Gold, Silver, and Bronze categories. However, now the Cascade Lake-AP processors that span up to 56 cores slot in as the ultimate tier of performance for the Platinum category, while the standard 8200-series Platinum models, which top out at 28 cores, are drop-in compatible with existing Xeon Scalable servers with the LGA 3647 socket.

Intel also introduced new workload-specialized processors that have Intel's Speed Select technology. These processors allow for finer-grained control of the processors' frequency, such as assigning certain cores to work at a set frequency so that workloads targeted at certain cores (through affinity manipulations) experience a better overall quality of service, which boosts performance. Networking-optimized SKUs also forgo Turbo Boost entirely to eliminate sporadic bursts that introduce performance inconsistency. 

Intel segments its product stack through several variables, including core count, base frequencies, PCIe connectivity, memory capacity/data rates, AVX-512 functionality, Hyper-Threading, UPI connections, and FMA units per core. Intel also doesn't offer Optane Persistent DIMM support with some Bronze models. In other words, you pay every penny for every single feature you get.

You'll notice that Intel hasn't released pricing for the exotic 56-core models, but that's because they only come in OEM systems. The flagship 8000-series processor, the Xeon Platinum 8280, weighs in at $10,009 per chip. The Platinum lineup dips down to $3,115 for the 8253 model, while the Gold family spans from $1,221 to $3,984 for the networking-optimized variant. Meanwhile, the Silver lineup spans from $417 to $1,002. As per usual, the 1K-unit tray pricing doesn't represent what the largest companies will pay after volume discounts.

Optane DIMMs Have Bright Prospects

Intel also announced the long-awaited arrival of its new Optane DC Persistent Memory DIMMs. The new DIMMs slot into the DDR4 interface, just like a normal stick of RAM, but come in three capacities of 128, 256, and 512GB. That's a massive capacity increase compared to the industry-leading 128GB DDR4 memory sticks and enables a total of up to 6.5TB of Optane storage in a dual-socket server. Intel designed the DIMMs to bridge both the performance and pricing gap between storage and memory, and although Intel hasn't released pricing yet, the new DIMMs should land at much lower price points than typical DRAM.

The new modules use Intel's 3D XPoint memory and can be addressed as either memory or storage. Unlike DRAM, 3D XPoint retains data after power is removed, thus enabling radical new use cases. 3D XPoint is also fast enough to serve as a slower tier of DRAM, but it does require tuning the application and driver stacks to accommodate its unique characteristics.

Much like NAND, 3D XPoint has a finite lifespan, but Intel says that it warranties the modules for an unlimited amount of use over the five-year warranty period. Intel says that it bases this endurance rating on the maximum possible throughput possible to the DIMMs for the duration of the five-years, putting to rest any endurance concerns. Intel also encrypts all data stored on the DIMMs to protect user data.

The DIMMs feature a controller, much like an SSD, that manages an abstraction layer. The DIMMs do consume more power than standard DRAM, so thermal throttling can become a concern in dense servers. To circumvent the issue, Intel offers a range of settings that span from 12W to 18W, at a quarter-watt granularity, to tune performance and thermal generation to the environment. Overall, the DIMMs consume about 3X the power of a standard 8/16GB DDR4 DIMM. Power consumption is a huge consideration in the data center, and gaining 32x the memory capacity in exchange for a 3x increase in power consumption is a dramatic improvement. 

Intel designed a new memory controller to support the DIMMs. The DIMMs are physically and electrically compatible with the JEDEC standard DIMM slot but use an Intel-proprietary protocol to deal with the uneven latency that stems from writing data to persistent memory. Intel confirmed that the Optane DIMMs could share a memory channel with normal DIMM slots, but the host system requires at least a single stick of DRAM to operate.

The new class of memory requires new programming models to unleash the full performance benefit, and application performance varies based upon workload. Intel has worked diligently to promote the ecosystem, and we're working of a full review of the Optane DC Persistent Memory DIMMs. Stay tuned for deep-dive details.

Xeon D-1600, New SSDs, and 100Gb Ethernet

Xeon D-1600

Intel's Xeon D-1600 series slots in as the SoC (System On Chip) solution for power and space-constrained environments, which is critical for Intel's 5G ambitions. These chips find their way into a range of devices, but edge processing for 5G networks is a specific target with this new generation of SoCs.

Xeon D-1600 pricing spans from $106 to $748, highlighting that this broad stack of Xeon D-1600 processors, which slot in under the throughput-optimized D-2100 series, addresses a plethora of different use-cases.

The Broadwell-based D-1600 lineup spans up to eight cores and supports up to 128GB of dual-channel DDR4 clocked at (up to) 2400 MT/s, while the D-2100 series spans from four cores to 16 and supports up to 512GB of memory.

Critically, the D-1600 SoCs also come equipped with (up to) an integrated quad-10GBe interface. The Xeon D-1600 processors span from a 27W TDP up to 65W, making them well-suited for a diverse number of power-constrained applications. Core counts span from two to eight cores, with clock speeds ranging from a 2.5GHz base frequency to a 3.2 GHz boost.

Intel Columbiaville 800 Series Ethernet Adapters

Intel's Ethernet adapters don't draw as many flashbulbs, but they serve as a key strategic asset for the company. Intel's new 800 Series adapters offer up to 100Gbps port speeds and support the new ADQ (Application Device Queue) feature that partitions network traffic into dedicated swim-lanes to boost performance significantly. The adapters also support Dynamic Device Personalization (DPP) profiles that enable smart packet sorting to route data intelligently. These adapters also support RDMA via iWARP and RoCE v2.

Intel hasn't released pricing information for the cards yet, which are sampling to customers, but expects them to launch in Q3 2019.

Intel Optane SSD DC D4800X and D5-P4326

Intel announced its new DC D4800X Optane SSDs, which provide dual port functionality that provides multiple pathways into the storage device. This feature provides redundancy, failover, and multi-pathing capabilities for mission-critical applications.

Intel also announced the D5-P4326 SSD. This new SSD adheres to the new standardized ESDF "ruler" form factor and boosts capacity by switching to QLC (Quad-Level Cell) flash. Even though we've seen Intel's MLC variants of these drives demoed for years, these new models are the first for the general market.

The denser flash enables up to 30.72TB per ruler, and up to 1PB of storage per 1U server. Random read/write speeds weigh in at 580,000/11,000 IOPS, while sequential read/write performance lands at 3,200/1,600 MB/s. As expected, QLC flash results in reduced endurance of 0.9 DWPD (Drive Writes Per Day), but this should be sufficient for warm and cold data storage.

Intel hasn't released performance or pricing specifics of its new dual port Optane SSDs, but we'll update as more information becomes available.

Also, stay tuned for our deep-dive analysis of Intel's new 10nm Agilex FPGAs.

According to a report by DigiTimes, president and CEO of Compal Electronics Martin Wong believes Intel will continue to face 14nm CPU supply shortages well into the second half of 2019. Compal is an original design manufacturer (ODM) from Taiwan that has had customers such as Apple, Acer, Lenovo, Dell, Toshiba, Hewlett-Packard and Fujitsu.

Intel’s CPU Shortage

There have been multiple additional reports about Intel’s short supply recently. Intel itself has acknowledged the issue and recently we learned of its expansion of testing capabilities for 14nm processors.

Still, according to Wong, Intel hasn’t given its downstream partners a clear schedule for when the shortage might be solved, leading Wong to conclude that the shortages could last for at least another year.

Acer recently said that Intel’s CPU shortages have started impacting the whole notebook market, DigiTimes said in its report. Inventec, another Taiwanese ODM, has also had to cut its growth expectations for the third and fourth quarter this year to single-digit growth, according to the report.

Intel 10nm Woes Continue

Although Intel has made it seem like its CPU shortages are due to higher demand, the truth is the company’s plans included having its 10nm fabs ready so it can manufacture its latest chips on 10nm, while keeping the older chips on 14nm. Intel was also planning on taking orders from other customers (including for FPGA production for Altera, which Intel recently purchased).

Since the 10nm design failed to work properly and provide good yields, Intel was forced to manufacture its latest chips on the 14nm fabs, which, as you can expect, overcrowded those fabs.

Potential AMD Opportunity

AMD’s Ryzen chips have been rising in popularity, but notebook vendors have been the slowest to adopt the company’s chips so far. Intel’s CPU shortages into the next year could be a good opportunity for AMD to convince some laptop makers to use more Ryzen chips in their product line-ups.

As Intel faces supply shortage, the company has also started increasing the prices of its 14nm processors, which could also be risky if more consumers start to see AMD’s offerings as a better value.

Intel announced this week its acquisition of NetSpeed Systems. The moves comes as Intel looks to grow its Silicon Engineering Group and expand its portfolio of interconnect-related intellectual property. Terms of the deal weren't disclosed, but Intel did say it plans to honor NetSpeed's existing contracts prior to bringing all of its work in-house.

NetSpeed is a system-on-chip (SoC) company with six products: four interconnects called Orion, Gemini, Orion AI and Crux and two add-ons called Pegasus and SoC Builder. Besides Intel, its customers include several Fortune 100 companies in the telecommunications, semiconductor and mobile industries, as well as Arm. Altera, which Intel acquired in late 2015, was also a NetSpeed customer (talk about internal synergy).

Those products are supposed to help NetSpeed offer the "easiest and most cost effective way to assemble an SoC." Promises like that are going to become increasingly important to companies like Intel as more and more devices are expected to offer "smart" features. NetSpeed said its products have applications from connected homes and cars to cloud computing and mobile--all of which have become areas of focus for Intel.

"NetSpeed’s highly configurable and synthesizable offerings will help Intel more quickly and cost-effectively design, develop and test new SoCs with an ever-increasing set of IP,." Intel said in its announcement.

NetSpeed co-founder and CEO Sundari Mitra will become an Intel vice president reporting to Jim Keller, the lead architect of AMD's Zen microarchitecture who joined Intel after a stint at the Tesla electric car maker.

The company also explained how it plans to use NetSpeed's technologies and expertise:

"As SoCs grow more complex and as new fabrication processes explode the number of design rules, architects are increasingly utilizing front-end tools like NetSpeed’s to automate the design and validation process – saving time and money. NetSpeed’s technology helps architects estimate and optimize SoC performance in advance of manufacturing through a system-level approach, user-driven automation and state-of-the-art algorithms."

Mitra told the Silicon Valley Business Journal that this deal is also something of a homecoming for her. She worked at Intel right out of college before heading to Sun, founding Prism and selling that company to Mosys, Inc. Combine that familiarity with Intel and NetSpeed's age--four years is an eternity for a startup--and it's not hard to imagine why Mitra and Co. would decide it was time to become part of something bigger.

At its first AI Developer Conference, Intel announced the Nervana NNP-L1000, which is the first neural network processor (NNP) to come out of the Nervana acquisition. The chip will prioritize memory bandwidth and compute utilization over theoretical peak performance.

Intel’s New Attempt To Succeed In The ML Market

Initially, Intel started competing with Nvidia in the machine learning (ML) chip market with its Xeon Phi architecture, which used tens of Atom cores to “accelerate” ML tasks. However, Intel must have realized that Phi alone wasn’t going to allow it to catch up to Nvidia, which seems to make significant leaps in performance every year.

As such, the company began looking for other options, which led it to buy Altera for its field programmable gate arrays (FPGAs), Movidius for its embedded vision processor, MobilEye for its self-driving chip, and Nervana for its specialized neural network processor. Also, Intel has started working on its own dedicated GPU. The company is also working on neuromorphic and quantum computing chips.

Intel calls all of these options a “holistic approach” to artificial intelligence. However, the company may also want to avoid betting everything on a single architecture again, as it did with Phi, and then fall even farther behind Nvidia in the ML chip market. On the other hand, this scattered strategy for ML may also confuse developers, because they won’t know which technology Intel will back the most in the long-term (and Intel may not know yet, either).

Intel’s Nervana NNP-L1000

For now, Intel seems to focus more on pushing its Nervana chips to ML researchers, possibly because it may be the one that is going to compete most directly with Nvidia (at least until Intel’s dedicated GPUs arrive).

The Nervana NNP-L1000, code-named Spring Crest, seems to put great emphasis not so much on peak trillion operations per second (TOPS) as on high memory bandwidth and low latency.

Intel showed the following performance numbers for its Lake Crest prototype, which is currently being demoed to some partners:

General Matrix to Matrix Multiplication (GEMM) operations using A(1536, 2048) and B(2048, 1536) matrix sizes have achieved more than 96.4 percent compute utilization on a single chip. This represents around 38 TOP/s of actual (not theoretical) performance on a single chip.Multichip distributed GEMM operations that support model parallel training are realizing nearly linear scaling and 96.2 percent scaling efficiency for A(6144, 2048) and B(2048, 1536) matrix sizes – enabling multiple NNPs to be connected together and freeing us from memory constraints of other architectures.We are measuring 89.4 percent of unidirectional chip-to-chip efficiency of theoretical bandwidth at less than 790ns (nanoseconds) of latency and are excited to apply this to the 2.4Tb/s (terabits per second) of high bandwidth, low-latency interconnects.All of this is happening within a single chip total power envelope of under 210 watts. And this is just the prototype of our Intel Nervana NNP-L1000 (Lake Crest) from which we are gathering feedback from our early partners.

The Nervana NNP-L1000, which will be the first Nervana product to ship to customers, promises 3-4x the neural network training performance compared to Lake Crest, according to Intel.

Intel said that the NNP-L1000 would also support bfloat16, a numerical format that’s being adopted by all the ML industry players for neural networks. The company will also support bfloat16 in its FPGAs, Xeons, and other ML products. The Nervana NNP-L1000 is scheduled for release in 2019.

A new patch that’s now live on the Overwatch PTR means big changes for both Ana and Mercy. Ana's alterations are pretty simplistic, with what amounts to a damage buff, whereas Mercy has been nerfed again significantly.

As Blizzard's Jeff Kaplan previously announced, Ana's Biotic Rifle will now do 70 damage per shot instead of 60. Though this may be a small augment in terms of damage, it should be enough to make her a viable option again for support players. That's what Blizzard is hoping for, anyway, as Kaplan explained in a post on the official Overwatch forums.

Mercy is becoming a little less powerful in contrast to Ana, with her popular Resurrect ability on the receiving end of a nerf. Previously, there was no cast time for Resurrect, but now it will take 1.75 seconds to complete Resurrect on a target.

To make matters worse for Mercy mains, her movement speed has been reduced by a whopping 75% while casting Resurrect. Casting can now be interrupted by enemies if Mercy is knocked back or damaged, as well.

It's all in a bid to rebalance the popular healer, whose Resurrect ability Blizzard has deemed "too strong and frustrating to play against."

"Now that it has a cast time, there is more room for enemies to counter the ability," Blizzard's latest patch notes read. "However, casting Resurrect happens instantly when Valkyrie is active. This should make her feel powerful when she transforms on the battlefield."

If you're itching to see how these alterations may affect your own play style, you can try them out right now. Both Ana's damage buff and Mercy's Resurrect nerf are currently available for testing via Overwatch's PTR.

The high-volume IoT market encompasses many diverse applications and multiple solutions vie to power the next generation of products. Intel expanded its field programmable array (FPGA) family with the new Cyclone 10, which comes as yet another advantage of its Altera acquisition in late 2015.

Brain drain and R&D stagnation typically impact newly acquired companies, but the (former) Altera team continues to execute well on its roadmap--the new product family comes on the heels of the Stratix 10 FPGA release in October. Low-power FPGAs serve as a key strategic piece for Intel as it restructures and dives deeper into new market segments.

Intel split the Cyclone 10 into the performance-oriented GX and low-power optimized LP series. The GX series uses TSMC's 20nm process and is geared for a number of uses in the industrial, automotive, and broadcast markets. These include machine vision, robotics, infotainment, Advanced Driver Assistance Systems, and audiovisual applications.

The automotive segment is rapidly growing due to autonomous technologies, which many view as a "future" technology. Autonomous capabilities are actually separated into several levels. Level 5 offers full autonomous driving capabilities, while levels 1 and 2 provide features that are already on the market, such as adaptive lane cruise control, collision avoidance, and automatic parking. Vehicle infotainment applications are also growing rapidly.

Several players are angling for a piece of this sizable market. At Micron's analyst day, it predicted that Level 1 and 2 autonomous features would see a tremendous uptake in 2018 as the technology spreads to lower-priced vehicles. Micron currently has 40% market share of autonomous vehicle memory/storage solutions, but Intel's Cyclone 10 series aims to grab share on the compute side as the company fans out to capture more of the IoT market.

FPGAs offer power to performance advantages compared to some solutions, but they also require more specialized programming for each application. Specialized programming can be a downside, but it fits well into the target markets because the ability to rapidly reprogram an FPGA offers an additional level of flexibility.

The GX series offers twice the core performance of its predecessor and scores an "industry first" for low-cost FPGAs with 10.3 Gbps transceiver I/O support and IEEE 745-compliant hard floating-point DSP blocks. The single-precision floating-point DSP processes at up to 134 GFLOPs. Other highlights include DDR3/L EMIF support and OpenCL support.

The Cyclone LP slots in for low-cost and low static power applications, such as industrial motor control, interfacing, sensor fusion, and I/O expansion, among many others. It's available in several different temperature grades to support differing commercial, automotive, and industrial applications. Intel claims it consumes up to 50% less static power than its predecessor. The low-power design employs a high-density fabric, memory, and I/O architecture.

Intel's releasing the latest version of Quartus, its FPGA programming software, along with the Cyclone 10 FPGA products in the second half of 2017.

Intel's $16.7 billion Altera purchase in late 2015 signaled a shift in the company's strategy to increase its capabilities in several core areas. The acquisition has now borne fruit in the form of the new Stratix 10 FPGA, which surprisingly wields a quad-core ARM Cortex-A53 processor and a dollop of HBM2 memory that offers up to 1TBps of memory bandwidth. 

CPUs and FPGAs have slugged it out in several categories as the go-to solutions for high-performance applications, and each has its own advantages. CPUs can perform a wide range of operations and fit into just about any mold, whereas FPGAs have evolved into highly specialized chips that offer power versus performance advantages in targeted applications. CPUs hold the simplicity advantage, as FPGAs require specialized programming to unlock their true potential.

For Intel, bringing Altera into the fold will allow it to grab a slice of the broader FPGA pie while simultaneously infusing FPGAs on-package with its own Xeon products, such as the forthcoming Purley platform. Of course, the broader initiative is to bring FPGAs on-die with the CPU, but the road map for that achievement is cloudy. Intel also has its Xeon Phi line, which provides the company with a diverse stable of products.

The Stratix 10 steps into the ranks with up to 10TFLOPS of single-precision floating DSP performance. Four on-package HBM2 components feed the beast with up to 1TBps of memory bandwidth. Intel claims the Stratix 10 offers up to 70% lower power consumption than Altera's previous-generation Stratix V when normalized for performance. At the end of the day, the goal of all compute solutions is to provide the most performance in as dense a package as possible, and Intel claims to have that wrapped up with 5x the density and 2x the core performance of the previous-generation products.

Much of the performance enhancement is borne on the back of the increase to 5.5 million logic elements, which is a significant advantage over the competing Xilinx XCVU13P, which features 3.78 million logic elements. Intel and Altera also noted that the Stratix 10 could be reprogrammed in milliseconds, which is a key requirement for on-the-fly repurposing.

Surprisingly, the Stratix 10 SoC also features an embedded quad-core 64-bit ARM Cortex-A53 processor (up to 1.5 GHz); one would have imagined that Intel would bring its own Atom processors into the mix. Much ink has been spilled on the ARM and Intel wars, so the Cortex-A53's presence on the Stratix 10 SoC  is an interesting development. Business makes for strange bedfellows; it's likely that the Stratix 10 was already well under development when Intel purchased Altera, which means we might see the switch to x86 processors in future Altera FPGAs.

Most acquisitions (well, at least the good ones) provide both companies with tangible assets that promote their existing technologies. Altera made its quasi-debut as an Intel company when it presented at IDF 2016 in August. During the session, company representatives hailed the access to Intel's semiconductor prowess and processes as a key win that will allow Altera to accelerate its own developmental process. The new Stratix 10 serves as a good example of that collaboration, as Intel built it on its own second-generation 14nm 3D tri-gate process (this likely denotes the 14nm+ process). Intel also brings a wealth of engineering talent to the table. The new Stratix 10 features a "revolutionary" new HyperFlex architecture, which provides additional performance and power efficiency by streamlining the registers (Hyper-Register), enhanced core clocking (localized clock trees that reduce skewing), and Hyper-Aware design flow (a "Fast Forward Compile tool").

Microsoft recently announced that it's using FPGAs as the bedrock of several facets of its cloud and Bing infrastructure. The move is largely due to FPGA reprogrammability, which allows data centers to alter their use case on the fly, and there are several large data center operators that will serve as tasty targets for Intel's latest FPGAs. The fusion of on-die FPGAs with Xeon CPUs will bring forth perhaps the greatest advantages in terms of flexibility, which means that Intel could also use the Altera FPGA architecture as a stepping stone into new segments, like the burgeoning machine learning market.

Specifications And Software

We’re getting our hands dirty with the Corsair Gaming K70 RGB Red, a model that comes with a 104-key U.S. layout and media keys, but no dedicated macros. It has Cherry MX RGB Red switches on board.

Although Corsair was by no means the first to release a keyboard with multi-color backlighting, it has the distinction of bringing adjustable per-key backlighting to the gaming keyboard world. It did so with the RGB series, which included the K65 RGB, K70 RGB and K95 RGB. For one year, Corsair had an exclusive partnership with Cherry to use the all-new Cherry MX RGB switch, so it took other manufacturers a while to develop their own with partners, or wait for the exclusive partnership to end.

Specifications

Corsair Utility Engine Software

Corsair’s RGB keyboards got much flack in their early days for having terrible software, and although some elements may have improved with version 1.14.43, the “CUE” or “Corsair Utility Engine” software is still something close to abysmal. 

To begin, the opening screen presents us with four main tabs: Profiles, Actions, Lighting and Settings.

Profiles

The Profiles tab contains the basic profile settings. There is one sub-tab labelled ”Assignments” where you can set each individual key to act as a macro. To make a macro, you right-click the key you want to configure (left click does nothing) and assign an action. Then, a large window shows up with a handful of elements you can configure, name and save. The options are precise, including down-to-the-millisecond timing between keystrokes and whether it should start on press or after the release of the switch.

In the next sub-tab in profiles (Lighting), you can choose from a few preset lighting effects using the standard settings. With advanced settings, you can pick from the custom lighting effects, which you have to create elsewhere in the CUE software.

The “Performance” sub-tab in profiles customizes what the “lock” button does. Standard, it disables only the Windows key, but you can also configure it to disable Alt-Tab, Alt-F4 and Shift-Tab.

The “Actions” section is where the macros are stored. This is convenient, because it means that the macros you create are saved without being assigned to certain keys, even if it seemed so when you first created it. Therefore, when you delete a macro from a specific key, you’re actually just unassigning it. Assuming you name your macros sensibly, they are quite easy to manage in this way.

The real nightmare is in creating lighting effects. The main Lighting tab isn’t where you adjust the lighting. That’s just where unassigned effects are stored, similar to the Macros. This is confusing, because when I made a solid green effect, it didn’t appear on the keyboard. Eventually, I realized that I had to go back to Profiles-->Lighting, select the keys I wanted to light up in green, and then apply that effect to them. (As frustrating as that may be, Razer’s Synapse and G.Skill’s software also have the lighting split up in two different menu areas.)

Creating a simple effect is already a challenge, but if you have the patience to learn the software, you can make practically anything you want – people have made Pacman effects, Snake, Thunder, and more (although I do not want to imagine how much time it would have taken to make those). Fortunately, under the “standard settings,” there are a few pre-made lighting effects.

One thing we did note when playing around with the lighting is that the Cherry MX RGB switch appears to be unable to display the color white effectively. To make white, it combines all three of its colors, which results in a rainbow of colors cast on the switch north of the one being lit up.

The lighting also isn’t particularly bright. In a dark environment it lights up beautifully, but if you’re sitting next to a window in broad daylight, you’ll have trouble telling whether the keyboard is lit at all. This is something at which Razer’s keyboards with the white backplate and Logitech’s keyboards with the Romer-G switches do a notably better job.

If you want to know exactly how to make the lighting effects, Corsair has a manual that is 140 pages long.

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Product Tour

Keys and Switches

The Cherry MX RGB Red switches on the Corsair Gaming K70 are specially crafted by Cherry to be RGB-lit, and therefore they have a few alterations from the original non-lit versions.

The 16.8-million color LED are enclosed inside the clear upper casing, as opposed to on the surface as seen on older Cherry MX switches. The result is that the entire casing lights up in whichever color the LED produces, and extra light is beamed directly up to shine brightly through the lettering of the keycaps.  

This lighting technique itself has an impressive design, but the lights aren't very bright. On top of that, a rainbow of colors appears on the opposing keycap when using white light, which is quite the design oversight for a switch specifically designed for RGB-lighting.

The keypress feedback from the switches remains the same as the older variants. The Red switch is still linear, has an actuation force of 45 g and a 2 mm travel to reach the actuation point, and it bottoms out after 4 mm of travel. Unlike the original Corsair Vengeance mechanical keyboards, all of the switches on the Corsair Gaming K70 are mechanical. The standard K70 and K90 boards had cheaper rubber dome switches placed under the less commonly-used keys such as Esc, the F-Keys and the macro keys.

The media keys are placed at the top right of the keyboard, immediately above the numpad. The first line has a stop button, previous, play/pause, and next button. Above the media switches is a volume roller, which is made of metal and has a pleasing mesh finish on it. The roller sensitivity is not adjustable, but I found that it offers a predictable level of volume adjustment – it’s not too sensitive, nor do you have to roll it endlessly to get to the desired volume.

There is also a brightness adjustment button that allows you to pick from three levels of brightness (or you can turn off the lighting entirely), and there is a Windows-key disable button for when you’re gaming.

Keyboard Housing

On many keyboards, the backplate is mounted down inside a chassis, but Corsair opted to design the Gaming K70 differently, with the backplate set as one smooth piece of 2 mm-thick aluminum across the whole top of the keyboard and the keycaps mounted right on top.

One side effect of this design is that you can see the switch casings below the keycaps. This makes an otherwise extremely clean-looking keyboard look a little messy, and we might consider that a design flaw--if switches didn't light up.

The top panel/backplate is a single 2 mm slab of brushed aluminum that has been anodized in black. The bottom portion of the keyboard case is made of strong ABS plastic, which, together with the strong aluminum slab, means that there is practically zero flexion.

Wrist Rest, Cable, BIOS Mode, Feet

Corsair ships this keyboard with a wrist rest, and a good one at that. Its made of the same strong ABS plastic as the keyboard casing, but the majority of the surface is covered in a rubberized soft-touch material. It is certainly one of the most comfortable wrist rests I’ve used.

The wrist rest no longer screws into the side of the board like on the older K90, and although I thought I was going to miss that feature, I actually didn’t. It never felt like it was about to fall off or break, and the clip-in connectors are strong enough to hold it in place.

The cable is thick, has a braided sleeve from start to end, and feels solidly made. However, in practice, I found that I didn’t like the cable's unwieldy, and it has a tendency to retain its shape. In the box, it came folded (naturally), and the places that are bent were difficult to soften and straighten. As a result, the cable zig-zags across your desk rather than neatly laying itself out. I’d like a slightly more flexible cable.

The K70 RGB has the usual stands to lift the rear of the keyboard, but it also has stands at the front of the board to lift the entire unit.

There is also a BIOS mode slider labeled 1, 2, 4 and 8. Each sets a different polling rate. For example, “1” stands for “1 ms,” meaning a polling rate of 1000 Hz, whereas “8” stands for “8 ms,” resulting in a polling rate of 125 Hz. Not all motherboards support 1000 Hz polling, so you may need to dial down that setting to be able to access and work in the system BIOS.

Teardown, Performance And Conclusion

Teardown

Opening the Corsair K70 RGB wasn’t difficult, but I did end up having to destroy parts of it.

Corsair employed Cherry stabilizers, which don't have the metal bars and small plastic parts you get with Costar stabs. This makes removing or replacing the larger keys just as easy as the smaller keys.

Once you’ve removed all of the keycaps, 22 screws are accessible from the top. Once you remove those, though, there are a couple more screws still hidden. One is hiding under the Corsair logo sticker, and another is obscured beneath one of the plastic covers next to the volume rocker. Prying the Corsair logo off without damaging it isn’t possible, and the volume rocker cover can also cracked when removing it.

After the above, the plastic backing comes off without any difficulty, exposing the top.

The USB cable is sturdily affixed to the keyboard. It fits well in the structure of the board, which means that you can tug on the cable without putting any stress on the electric connections.

All the solder points in the board look neat, and there is no visible flux residue on the board – nothing negative stood out to us.

Putting the keyboard back together is the same process in reverse, though sadly, the Corsair logo and volume rocker cover have suffered slight, permanent damage. (In hindsight, if we had used a heat gun and a razor blade, we may have removed the logo without damage.)

Key Rollover

Corsair claimed that the K70 RGB boards have N-Key rollover (NKRO), which means that you can press any combination of keys you want and all strokes will register correctly. We fired up the Aqua Key Test (link hosted here), and we can confirm Corsair’s claims.

Audio

The sound that the K70 RGB makes with the Cherry MX RGB Red switches is quite clean, likely due to the sturdy body.

Conclusion

Even as the first keyboard to market with individual per-key RGB lighting, Corsair has done a fine job with the K70 RGB. The design shows that Corsair put serious thought into it (albeit with oversights), and the build quality shows excellent craftsmanship.

The biggest gripe we had with the keyboard was the accompanying software. To make a signature lighting effect is nothing short of a headache, and the macro creation isn’t as streamlined as it could be.

It's also unfortunate that the Cherry MX RGB switches cannot display the color white effectively, and that the lighting isn’t particularly bright. For a switch that is engineered for RGB lighting (albeit retro-engineered), we expected better.

The $189 price tag is steep, but it reflects the build quality and features.

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Intel's forthcoming 14nm Skylake Xeons are still in development, but a motherboard vendor here at Computex 2016 already had several Purley platforms (which will house the new chips) on display in its suite. Intel has not publicly shared any information on the new platform, but the boards indicate that the company has working silicon and is on the downward side of development.

Intel purchased Altera for $16.7 billion in December 2015 to gain access to FPGA (Field-Programmable Gate Array) technology. FPGAs (as the name implies) can be reprogrammed in the field to boost performance for specific tasks. Intel has publicly stated that it will incorporate FPGAs on-die with the current generation of Xeons, and there is no doubt that this practice will continue with the Purley platform. The next-generation Xeons will apparently be larger affair, which indicates that Intel engineered in plenty of room for FPGAs and GPU accelerators.

We did not have a ruler handy to measure the socket, but the JEDEC-compliant DDR4 slots that flank the socket are of the normal size, thus illuminating the mammoth nature of the next generation Xeons. The socket cover indicates that it is an LGA 3647 socket, meaning it packs in an additional 1,636 pins in comparison to the LGA 2011 socket (likely needed for additional paths into the aforementioned FPGAs).

A dual-socketed sled was also on display, and we note that the narrow ILM socket arrangement is present on both boards. The large rectangular socket would likely consume a considerable amount of motherboard real estate with a normal square ILM configuration.  

There are precious few Intel-provided details on the new architecture, but a widely circulated document was discovered on a website owned by Konferencji Uzytkownikow KDM (the HPC User Conference). Marcin Kaczmarski, the Senior Sales Manager for central and Eastern Europe (at the time), purportedly presented the PDF at an HPC conference. A picture with Kaczmarki at a conference in front of one of the slides appears to lend some credence to the documents. However, as we were not there physically to confirm the details, we caution readers that the following technical details traipse into unconfirmed territory.

The incredible size of the processors begs the TDP question, as dense designs are particularly TDP-sensitive. The slides indicate that the Purley platform features a configurable TDP that ranges from 45 to 165W, and as the 2U system on display confirms, this can be dissipated in a dense configuration. The documents indicate that the 28-core/56-thread Purley platform will feature an on-die Intel Omni-Path architecture (a 100 Gbps fabric for HPC applications), along with the requisite 1 and 10 GbE connectivity options.

The slides also tout a persistent "all new memory architecture" that offers up to 4x the capacity of RAM and 500x the performance of NAND. These specifications do not align exactly with Intel's much-ballyhooed 3D XPoint claims of "1000x the performance and endurance of NAND with 10x the density of DRAM." The Purley presentation reportedly occurred on May 11, 2015, which is before the official 3D XPoint announcement on July 28, 2015. This suggests that Intel may have tweaked the final performance specifications between the presentation and the formal announcement.

The 2U server we observed at Computex features a total of 12 memory slots per socket, which is indicative of a new hexa-channel memory controller. This tracks well with other industry reports at Computex that Intel is laying the 3D XPoint foundation by enabling more slots for system memory on emerging platforms, such as Kaby Lake. We expect 3D XPoint-based NVDIMMs will play a large role in the Purley platform, as well.

The platform will support both E5 and E7 processors and scale to 2, 4 and 8-socket implementations. The slides indicate the new platform will offer up to 1.5x the memory bandwidth and utilize new AVX-512 instructions, along with optional QuickAssist and Cannonlake graphics and media transcode accelerators. There is also the notable mention of a new 2- and 3-channel UPI interconnect that supports 9.6 and 10.4 GT/s data transfers. The UPI acronym is undefined at this point, but many speculate that it will serve as a faster and more scalable replacement for the QPI interconnect.

All conjecture aside, the presence of Purley systems at Computex 2016 indicates that we are rapidly approaching a new platform launch. The new platform will be faster than the previous generation, but that is to be expected. The real news is that Intel is embracing FPGAs to counter the death of Moore's law.

Intel will likely deploy FPGAs, and other accelerators, on an as-needed basis for large custom orders, so it may be a modular architecture. There might be standard SKUs with FPGAs, as well. We are likely more than a year away from an enthusiast-targeted Purley implementation, and frankly, it would be hard to imagine it including FPGAs. In either case, it will certainly be interesting to see what Intel has in store.

Paul Alcorn is a Contributing Editor for Tom's Hardware, covering Storage. Follow him on Twitter and Google+.

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Internet video traffic is expected to increase 80 percent by 2020, and much of the new content requires intense graphical processing. The development of new and enhanced video services, such as 360 degree rotational streaming, VOD (Video On Demand), augmented reality and virtual reality, are leading to a veritable explosion in graphical processing workloads. Simultaneously, the video content delivery ecosystem is expanding to support higher resolution video, such as 4K and 8k UHD, and cable providers and content delivery networks are struggling to meet the increasing needs of end users. 

Intel's new Xeon E3-1500 v5 steps in to satisfy the needs of these complex environments through the use of Intel Iris Pro P580 integrated graphical processors (IGP). The P580 IGP employs 72 Execution Units (EU) to expand upon the performance of the previous-generation Xeon E3 v4 family, which utilized Iris Pro P5700 and P3600 IGPs with 48 EU. Intel indicated that the new Iris Pro offers up to 26 percent more performance than the E3 v4 series.

Intel offers numerous solutions for various intensity levels, and the E3 v5 series slots in behind the Xeon E5 and E7 series, which offer the most performance through software transcoding. Intel also offers its Visual Compute Accelerator (VCA), which is a PCIe card that boasts three Intel E3 v4 processors, and it is natural to assume that the company will offer a new VCA version with its new E3 v5 progeny on board. Intel also offers the Altera Arria 10 FPGA for customized applications. The industry largely employs customized architectures that leverage ASICs, FPGAs or fixed-function DSPs for video processing, while Intel positions the E3 v5 series as a more general purpose platform.

The Intel E3 v5 adds a new hardware acceleration tool with its Quick Sync Video, which powers demanding real-time HEVC encoding tasks to speed HD and UHD video transcoding. Intel cites impressive numbers from the Quick Sync addition, such as the ability to process up to two real-time 4K 30 FPS video streams and up to 15 1080p 30 FPS steams. Intel also claims that it provides superior power efficiency metrics in comparison to PCIe-based graphics accelerators. HEVC provides up to double the compression with increased video quality at the same bitrate. Intel also notes an increase of up to 26 percent for 3D Mark 11 performance in remote environments.

Performance Optimized

The E3 v5 family moves from the Broadwell microarchitecture, which it utilized in the E3 v4 product stack, to the Skylake architecture with the same 14nm process. This brings the whole host of Skylake advantages, such as an IPC increase, to the E3 v5 series.

The company divided the new family into two categories, with the E3-1585 v5, E3-1585L v5 and the E3-1565L v5 falling into the performance category. The company also developed two reliability-optimized SKUs, which we cover later.

The goal for any workload is to do more work in less space, but the challenge is to accomplish the feat within a friendlier power budget. All of the E3 v5 processors offer the same core/thread count as their predecessors, not to mention the increase in graphical processing power, but the E3-1585 v5 and E3-1585L v5 reduce TDP by 30W and 20W, respectively. The bookend E3 v5 products offer either the same, or higher, base and turbo frequencies, but the E3-1585L v5 takes a slight step back in comparison to its previous-generation counterpart. All of the E3 v5 SKUs offer a higher IGP base frequency.

Intel increased memory support for the new platform up to 64 GB DDR4 2133 MHz from the previous limit of 32 GB of 1600 MHz DDR3. This offers more speed and capacity but has the added effect of reducing power consumption and increasing efficiency. Intel also doubled the amount of RAM that can be used for graphics processing up to 32 GB.

Intel employs 128 MB of eDRAM (DRAM embedded on-die) to serve as a last level cache (L4 in this case) for the CPU. This allows the company to utilize a speedier bus (50GB/s), and include more cache on-die in comparison to SRAM (DRAM has a notable ~3x density advantage). The previous-generation E3 v4 Series also featured 128MB of eDRAM, but the Skylake architecture no longer employs the eDRAM as a victim cache, which optimizes performance.

Reliability Optimized

Intel designed the "reliability optimized" SKUs for communications providers, which typically employ hardware for much longer duty cycles than normal data center products. These Xeons are designed for 10 years of use, and Intel will sell the processors for seven years, which enables telecommunications vendors to use a validated platform for an extended period of time.

The entire E3 v5 family utilizes the Intel C236 chipset in lieu of the C226 chipset used with the previous generation, and, as shown above, the processors are BGA-mounted to the motherboard to increase density. The C236 chipset is fairly standard fare, but it expands support to DDR4 and features a third-generation PCH. The chipset also supports up to six 6 Gbps SATA ports, six USB 3.0 ports and eight USB 2.0 ports. 

Intel Graphics Virtualization Technology

Intel's Graphics Virtualization Technology (GVT) comes in several flavors. The E3 v5 supports GVT-d (direct) and GVT-g. The former assigns a single GPU to a virtual machine for high-end use-cases, such as CAD, while the latter virtualizes the Intel graphics driver into between two to seven instances, which allows multiple users to run separate applications on a single GPU. Intel also added GVT-s (shared) for the v5 family, which supports a large number of simultaneous users to leverage common applications, such as Microsoft Office and the Chrome browser. Hypervisor support is listed in the graphic above.

Intel announced several additional features in its Intel Media Server Studio 2016 software. The company added HEVC hardware decode and encode functionality along with support for CentOS 7.2 and Windows Server 2016. Media Server Studio 2016 pre-release packages are available to OEM and ISV pre-release today, and public availability is slated for Q3 2016.

Intel will face competition from a range of solutions in this segment, such as the aforementioned ASIC and DSP-based solutions, and Nvidia GRID, which is enjoying significant industry uptake.

The addressable market is more than enough to lure the industry heavyweights; HEVC encoders have a projected 129 percent CAGR, and with 4K devices predicted to triple by 2020, it might continue to skyrocket. Intel Xeons populate an overwhelming 99 percent of data center sockets, and the company hopes the E3 v5 will solidify its position and dominate the fast-growing video processing segment as well.

Paul Alcorn is a Contributing Editor for Tom's Hardware, covering Storage. Follow him on Twitter and Google+.

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As chips become smaller and more powerful, and as new ways to accelerate deep learning are discovered, it’s not just large data centers that can run the “artificial intelligence” in your devices, but also small embedded chips can be put into anything from IoT devices to self-driving cars.

Deep Learning Training

There are two stages when working with deep neural networks. In the first stage, the neural network is “trained.” That’s when the parameters of the network are determined using examples of labeled inputs and a desired output. For instance, the network could be trained to “learn” how a human face looks by feeding it millions of pictures with human faces.

In the past, machine learning engineers used to code these parameters manually, which was a highly complex task and produced less than stellar results. It was just too hard for humans to think of all the needed parameters and algorithms to create an “artificial intelligence” that could “see” and recognize objects and humans. Thanks to deep neural networks, these parameters can now be generated automatically by training them to recognize certain items.

Deep Learning Inference

In the second stage, the network is deployed to run “inference,” which is the part of the process that classifies new unknown inputs using the previously trained parameters. For example, if a few new pictures are introduced to the neural network, it can determine which of them has a human face in it. This inference stage requires far fewer resources to run than the training stage, which is why it can now also be done locally on embedded chips and small devices.

It is widely accepted that the best way to train deep neural networks right now is to use GPUs because of their speed and efficiency compared to CPUs. Some companies, including Microsoft and Intel (through Altera), believe that field programmable gate arrays (FPGAs) could provide a sufficient alternative to GPUs for high-performance and efficient training of deep neural networks in the future.

However, the next big fight for efficiency will also be for the inference stage of the process, which can now be done on hardware that requires only a few Watts of power.

Nvidia Bets On GPUs For Inference

Nvidia believes that GPUs are not only ideal for deep neural network (DNN) training because of the inherent efficiency of graphics processors for such tasks, but also for DNN inference. In order to train deep neural networks to become moderately good for an intended purpose, you need large clusters of high-end GPUs.

Therefore, for the foreseeable future, training DNNs on embedded chips won’t be practical, but running inference on them is quite doable because of the much lower performance requirements to achieve a desired result.

In a recent test performed by Nvidia that compared its Tegra X1 with Intel’s Core i7 6700K, Nvidia’s embedded chip demonstrated performance that compared favorably with the Intel CPU, but with an order of magnitude lower power consumption. The Jetson TX1 (which has a performance of 1TFLOPs vs 1.2 TFLOPS for Tegra X1) achieved a top processing speed of 258 images/second with an efficiency of 45 img/sec/W, whereas the Core i7 achieved a peak performance of 242 img/sec with an efficiency of 3.9 img/sec/W.

Although Nvidia’s previous CUDA Deep Neural Network (cuDNN) software library was focused on DNN training, the current cuDNN 4 also introduced optimizations for inference in both small and large GPUs, which should further improve the performance of deep neural networks running on both the Tegra X1 and the company’s larger GPUs.

Nvidia is also working on a GPU Inference Engine (GIE) that optimizes trained neural networks and delivers GPU-accelerated inference at runtime for web, embedded and automotive applications. This software engine will be part of Nvidia's Deep Learning SDK soon. Deep learning software seems to be an area where Nvidia has a leadership position right now, with its GPUs supporting a wide range of deep learning applications.

Nvidia’s Jetson TX1 embedded module is targeted mainly at autonomous vehicles that need to recognize objects and process a large number of pictures or frames in a short amount of time so the cars can react quickly when needed. However, the Jetson TX1 could also be used in robots or drones, or other devices that need teraFLOPS+ performance on a relatively low power budget (under 10W for the Tegra X1 SoC).

Movidius Bets On ‘Vision Processing Units’ (VPUs)

Movidius’ goal is to create an embedded chip that beats even conventional smartphone SoCs in power consumption but can still deliver enough performance to run deep neural networks. This is why the company went with a more custom and highly-parallel “vision-focused” architecture that combines programmable SIMD-VLIW processors with hardware accelerators for video decoding and other tasks.

The Myriad 2 vision processing unit (VPU) can perform 8-, 16-, and 32-bit integer and 16- and 32-bit floating point arithmetic. It also has unique features such as hardware support for sparse data structures and higher local thread memory than what is typically found in a GPU.

Movidius’ VPU, which has a TDP of 1.2W and achieves a performance of 150 GOPS (giga operations per second) inside the recently announced Fathom neural compute stick, can be put into anything from wearables to tablets such as Google’s Project Tango, but also in surveillance cameras and drones, robots, and AR/VR headsets for gesture and eye tracking.

Movidius provides multiple solutions for 3D depth, natural user interfaces, object-tracking with its software development kit that are optimizing for its vision processing unit. Developers can also customize those solutions or run their own proprietary solutions on the platform.

More Efficient Client-Side Deep Learning

In the context of total power consumption for a given outcome, sending data that is first processed in the cloud to a client device through long-distance networks can be significantly less efficient than processing it locally on the device. The only issue concerns how much performance you can squeeze into a small device and whether that level of performance is enough for the results you’re trying to achieve with deep learning inference. However, client-side inference also has an advantage in low latency, which can enable all sorts of deep learning applications that wouldn’t be possible through the cloud.

Processing information such as personal pictures and videos in the cloud through deep learning can also be a big privacy risk, not just from the company doing the processing of that data, but also from attackers looking to obtain that processed information. A surveillance camera, for instance, would be less at risk of getting hacked remotely if it performed its analytics locally instead of in the cloud.

Both Nvidia and Movidius see that deep learning is the “next big thing” in computation, which is why Nvidia is optimizing its GPUs for it with each new generation, and why Movidius created a specialized platform dedicated to deep learning and other vision-oriented tasks.

Just as cloud-based deep learning is poised to grow at a fast clip over the next few years, we’re going to see more embedded chips take a shot at deep learning as well, as more of our devices try to become more aware of our surroundings through computer vision and need to process that information quickly, intelligently, and in a power-efficient way.

Lucian Armasu is a Contributing Writer for Tom's Hardware. You can follow him at @lucian_armasu. 

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Bev Crair, the Vice President and General Manager of the Storage Group at Intel, turned the information faucet on a little more at Storage Visions today. Information about 3D XPoint has been slow to emerge since Intel and Micron first announced it in 2015, which has fueled wild speculation. In the tech world, it's the equivalent to the predictions about the new Star Wars series, and a similar number of rumors abound.

To our knowledge, this is the first known close-up image of a working 3D XPoint device. We used a Storage Visions badge to prop the drive up for lighting purposes, and the metal clip extending from the middle of the DIMM is not part of the Intel NVDIMM.

The DIMM package is nearly identical to older FBDIMMs and even features a similar raised FPGA section in the middle of the heatsink. The FPGA is employed to orchestrate the internal NVDIMM functions, much like an SSD controller. 

The 3D XPoint NVDIMM utilizes the DDR4 interface to communicate directly with the CPU. Intel stated today that the current maximum capacity per 3D XPoint NVDIMM is 512 GB, and dual-socket servers can address up to 6 TB total with two CPUs. The largest DDR4 modules weigh in at a mere 128 GB apiece. To put the 6 TB per-server density server into perspective: Windows Server 2012 R2 supports only 4 TB of memory.

The implications of the enhanced memory density for in-memory compute is nothing short of revolutionary. Intel also indicated that it continues to work on the NVMe Over Fabrics initiative, which will help servers blast data across the network at near-local performance.

From previous pictures of Intel/Micron's 3D XPoint, we know that the die size is likely very large, but we aren't sure of its density, which is a key consideration when calculating cost efficiency.

Intel has historically skirted defining the 3D XPoint performance specifications as well, choosing instead to leave us with generic answers such as "similar to 100x the performance of current generation NAND." That equates to roughly the performance of current DDR4 DRAM, and Intel reiterated again today that we should expect DRAM-like speeds.

The FBDIMM-like package, with its FPGA in the middle, is very interesting and allows us to gain a little further insight. Intel used FBDIMMs on one mainstream Intel chipset generation, and it also employed the use of an FPGA in tandem with memory packages. The chipset spanned enterprise systems with two, four and even eight processors, but the most famous version also reached the market via Intel's Skulltrail enthusiast-class dual-socket system.

FBDIMMs ran very hot, and the FGPA controller could reach as high as 95 degrees Celsius for double refresh products. Unfortunately, that was the maximum "within spec" rating, which hampered adoption and eventually limited the use of FBDIMMs. Any serious enthusiast with a Skulltrail system knows this all too well, and may even still have the scars as a reminder.

Intel recently acquired Altera (for $16.7 billion), a semiconductor design-house that also recently announced an FPGA-based SSD controller.

Microsoft also detailed its role for enabling NVDIMM functionality, and thus 3D XPoint, in a panel today. Microsoft has an in-house build of Server 2016 with a new file system designed specifically to address new ultra-low latency NVDIMM devices. NVDIMMs are a range of Storage Class Memory (SCM) products that utilize the memory bus and DRAM, NAND, and now 3D XPoint to provide ultra-fast storage performance.

There are three classes of NVDIMM products, as outlined here. Microsoft is focusing on providing NVDIMM-N support at first, which is also the logical form factor for 3D XPoint NVDIMMs. Microsoft is designing ReFS and NTFS to be SCM-aware and feature latency optimizations that exploit the inherent advantages of storage-class memory. A Microsoft representative stated that the new system would first release to end users as an upcoming Technical Preview build.

Intel is still holding the details of its latest technology close, but some information is beginning to trickle out as the ecosystem develops and expands. There are reports that leading-edge samples are already in the hands of some Intel/Micron partners, but Intel is incredibly vague about general availability (as usual for anything 3D XPoint related), though it is predicted to be sometime this year.

For its final move in 2015, Intel bought out Altera in an all-cash purchase of approximately $16.7 billion. Obviously, Altera will no longer keep its original name; instead, it will be part of Intel's business group under the new brand called the Programmable Solutions Group (PSG), with Dan McNamara, Altera's former vice president and general manager for its embedded and systems division, at the helm.

Altera's main focus of production was field-programmable gate arrays (FPGA), and Intel wants the PSG to continue working in that field. However, it will also collaborate with Intel's Data Center and Internet of Things groups to create new products. As for those who still utilize Altera's products, Intel assured customers that it will support current and future devices created by the PSG, such as its lineup of FPGAs and ARM-based SoCs.

Prior to the purchase of Altera, the two companies collaborated in the past. In 2013, Intel announced that its 14nm tri-gate transistor technology (which was used for military devices, wireline communications and cloud networking) would include Altera's FPGAs. Later that same year, Altera's Stratix 10 SoC devices would incorporate a quad-core, 64-bit ARM Cortex A53 processor. The SoC itself was manufactured on Intel's 14nm tri-gate technology.

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During the ARM TechCon 2013 conference last week, Altera revealed that its ARM-based 64-bit chips will be manufactured using Intel's 14 nm Tri-Gate process starting in late 2014. The chip will incorporate a high-performance, quad-core 64-bit ARM Cortex-A53 processor system, floating-point digital signal processing (DSP) blocks and high-performance FPGA fabric.

"The ARM Cortex-A53 processor, the first 64-bit processor used on a SoC FPGA, is an ideal fit for use in Stratix 10 SoCs due to its performance, power efficiency, data throughput and advanced features," reads the company's press release. "Leveraging Intel's 14 nm Tri-Gate process and an enhanced high-performance architecture, Altera Stratix 10 SoCs will have a programmable-logic performance level of more than 1GHz; two times the core performance of current high-end 28 nm FPGAs."

This will be a three-pronged move for Intel: it's a new stream of revenue in a declining PC market; a way to compete with other foundries like TSMC, GlobalFoundries, Samsung and others; and to somehow break ARM's "supremacy" in the mobile market. "It's huge. Imagine ARM's most powerful and technologically advanced 64-bit processor built on Intel's leading-edge fabs. A duo that will be hard to beat," said Nathan Brookwood, principal analyst at Insight 64, while speaking with Forbes.

Building Altera's 64-bit chip will also open the door for Intel to fab SoCs for competing ARM-based chip suppliers like Nvidia and Qualcomm. "Intel will build Apple's A7, Qualcomm's Snapdragon or the Nvidia Tegra for the right price. Now, the question is, are they ready to pay that premium [to ARM] and feed their direct competitor? But that would actually make business sense for everyone," Brookwood added.

CNET points out that Altera won't be the first; Netronome claimed to be one of Intel's first ARM-based customers back in April. Netronome's next-generation flow processors will be manufactured on Intel's 22 nm Tri-Gate process, and used in a broad range of demanding network, security and content processing applications found in high end networks with speeds up to 100 Gbps. NFPs are the industry's only processor specifically designed for tight coupling with Intel Architecture (IA) processors.

CNET reports that Altera and Netronome went to Intel because the chip giant is making steady progress in building up its foundry business. Microsemi, Achronix and Tabula are also signed on to use Intel to produce their chips. Microsemi, which will only use Intel for its digital products, will have its first 22 nm-based parts made by the end of 2014 or in early 2015.

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Affordable Z87 Express Motherboards: Not Quite "Back To Basics"

PC enthusiasts like myself expect a lot more from our systems than the industry's standard for basic computing. We want performance and an attractive price. Often, our expectations include overclocking as well, since dropping $1000 on Intel's fastest desktop processors simply isn't an option for most of us.

To that point, this passion of ours got a little more complicated when Intel decided to lock the ratio multipliers on its CPUs, and fundamentally remove BCLK frequency as a variable, and charge a premium for the handful of processors that can still be overclocked at all. The starting price on those is $220, by the way.

Fans of AMD's hardware have plenty of reasons to feel as though they've taken the high ground. It's only a shame that the company's best efforts fall so short of where Intel has been sitting for two years. Sadder still is when you take a look at AMD's roadmap and see a distinct lack of FX-series parts beyond Vishera.

Along the way, enthusiast-oriented motherboards crept up in price as we learned to push performance beyond what even those thousand-dollar CPUs can do, at the same time sucking down power and generating more taxing thermal loads. We tend to make up for that fact by expecting the other components to cost less. Graphics cards, SSDs, and memory all just get cheaper over time, right? It's no longer necessary to spend big bucks on a feature-complete motherboard to get the most out of CPUs. Nowadays, it's pretty normal to spend more on your processor than the platform that supports it.

And so we have five motherboards under $160 that support Intel's LGA 1150-based chips built on the Haswell architecture.

Intel might charge a premium for the privilege of owning an overclockable processor, but the company at least deserves credit for exposing enthusiast-class features on mainstream motherboards. With the introduction of its Z87 Express Platform Controller Hub, you get SATA 6Gb/s transfer rates on all six ports, a full battery of six USB 3.0 ports without a bunch of motherboard-down controllers, and an integrated PCI Express controller that supports three links without the need for expensive switches.

All of that saves you, oh, somewhere around $20 in cost, we're estimating. So, this round-up's $160 price cap should be comparable to the $180 boards from the previous generation. So, let's see if mainstream Haswell offers us anything more attractive than the higher-end segment.

ASRock Z87 Extreme4

ASRock hopes to demolish its competition in the enthusiast-value segment by providing a full set of features for less than $160 (sometimes even less than $150, depending on the deal of the day; ASRock's prices tend to move a lot more than we're used to). That full set includes three-way CrossFire using PCI Express 3.0 slots, four front-panel USB 3.0 ports, an extra eSATA 6Gb/s controller, HDMI monitor pass-through for external devices like game consoles, Intel's own network controller hardware, and DTS Connect-enabled ALC1150 audio.

The combination of five analog outputs and DTS Connect over optical S/PDIF gives users a wide range of options to connect multi-channel speaker systems, though the four nearby USB 3.0 ports seem sparse on a board that hosts an extra four-port hub.

Those missing USB 3.0 ports are instead found on a second front-panel header, yielding a total of four USB 3.0 and six USB 2.0 front-panel connections. The USB 3.0 hub consumes one of the Z87 Express PCH's native ports, so ASRock exposes the left-over interface as an external connector mounted internally, where it can be used to attach USB-based Wi-Fi, flash, or Bluetooth.

Three PCIe x16 slots connect the CPU’s 16 PCIe 3.0 lanes in x16/x0/x0, x8/x8/x0, or x8/x4/x4 modes. We’re typically not fans of four-lane connections for graphics, but the use of PCI Express 3.0 should alleviate any bottleneck that would have earned our ire in the past. Unfortunately, three-way SLI is officially unsupported, though Nvidia fans can still use the three slots for two-way SLI plus a third card.

ASRock moves the front-panel audio connector three slots up from the traditional bottom-rear corner to shorten the distance to its audio solution, which itself is moved closer to the I/O panel. This design, along with a TI NE5532 600 Ω-compatible headphone amplifier and enhanced EMI shielding, make up its Purity Sound solution.

The relocated front-panel connector benefits builders using cases with audio cables that can't quite reach the bottom-rear corner. On the other hand, if you prefer wrapping that cable around the bottom of your motherboard tray, you might now have to go over the board's top, which looks a little messier. These board vendors can't please everyone, it seems.

Less controversial are the power, reset, and CLR_CMOS buttons next to a two-digit diagnostics display. While most mainstream folks rarely need those features, they often come in handy when we're testing hardware outside the confines of a case. ASRock even sockets its two firmware ICs in case you somehow manage to corrupt them both.

The Z87 Extreme4 supports up to eight SATA drives, but includes only four cables (that’s a total of eight drives, since the eSATA connector is shared with one of the added internal ports).

Z87 Extreme4 Firmware

ASRock changed little in the firmware transition from Z87 Extreme6 to Z87 Extreme4, keeping all of its pre-defined overclocks in place. That made it easy for us to start with its Turbo 4.4 GHz setting and manipulate other settings from there.

A top clock rate of 4.7 GHz at our old 1.3 V setting was impressive, though we’ve since found that AVX-heavy tests push our CPU to its thermal limits at that voltage. Retesting at 1.25 V was successful at 4.6 GHz.

Our DDR3-3000 kit from G.Skill failed to operate at its specified values on this board, though we increased the BCLK setting enough to push a 2666 MT/s data rate to 2746 MT/s.

ASRock compensates high memory ratios with beyond-spec voltage, which we'd prefer not to see. Dropping to the DDR3-2666 memory setting allowed us to reach an actual 1.65 V at a fairly reasonable 1.635 V setting.

Primary, secondary, and tertiary memory timings can be individually changed from automatic to manual mode, allowing users to configure familiar values.

Z87 Extreme4 Software

ASRock applications include XFast Lan (by CFOS), Xfast USB (by FNet), XFast RAM (a RAM drive utility), and App Charger. The DTS-enabled version of Realtek Audio Manager is par for the purchase, and the Z87 Extreme4 even includes the same trial software previously discussed in our ASRock’s Z87 Extreme6 review.

ASRock A-Tuning still works, but this production version now has an actual image of the motherboard to show where devices are connected. Nice improvement there.

After several unsuccessful attempts to enter the firmware during a super-fast Windows 8 reboot, I resorted to ASRock’s “Reboot to UEFI” utility, rather than the operating system's Advanced startup procedure.

Asus Z87-Plus

Equipped with the same high-end Intel network controller, the same ASMedia add-in SATA 6Gb/s controller, the same USB 3.0 hub, and a slightly cheaper audio codec, Asus’ Z87-Plus needs to do something extremely well in order to overcome its price premium compared to ASRock’s competing Z87 Extreme4. Asus has a long list of features that it says add more value than any other vendor, and the USB BIOS Flashback feature is one strong example.

The BIOS Flashback IC resembles an SoC (system on a chip) for its specific function, allowing users to update the firmware with nothing more than a USB flash drive and power supply. Incompatible parts play no role here, since you don't even need to have a processor installed. This is particularly brilliant when a customer purchases an older motherboard that was sitting on a store shelf for months and an unsupported CPU at the same time. Of course, Haswell just came out, so you wouldn't actually need this value-add until later, when Intel refreshes its platform.

Asus skips the I/O panel-based eSATA connector that ASRock shares with an internal port, and instead routes that interface to a connection accessible internally. The Z87-Plus also skips over the Z87 Extreme4's second internal USB 3.0 connector in favor of exposing six ports on the rear I/O panel. Your own preferences should dictate the configuration that works best.

Your needs will also determine the best slot arrangement. Asus splits the CPU’s 16 PCI Express 3.0-capable lanes across two slots, wiring its third slot to slower second-gen pathways from the PCH. While that means the third slot has far less bandwidth, it also won’t steal lanes away from the two graphics cards you might also install. Frankly, Asus' implementation makes more sense for most enthusiasts. But it incurs another drawback: the bottom slot is only wired up to two of those slower PCI Express 2.0 lanes. That means the third physical x16 is almost as ill-suited to a high-end RAID card as it is to three-way CrossFire. Being better for most users is an admission that most folks (particularly in the mainstream space) aren't using intricate storage arrays or three-card graphics setups.

The Z87-Plus doesn't have a POST code display or a bunch of motherboard-based buttons. But it does come equipped with switches. Among them are EPU and TPU mode selectors for automatic under- and overclocking, depending on your power or performance needs. The buttons you do see on-board correspond to power, BIOS Flashback, DirectKey for direct-to-UEFI booting (particularly useful in Windows 8), and MemOK for DRAM-underclocking to assist diagnostics.

We didn’t find any serious layout concerns on the Z87-Plus. Asus moves its front-panel audio connector around an inch forward from its typical location to help builders using cases with slightly short cables, and instead puts a special header for its ThunderboltEX card in the bottom-rear corner.

The Z87-Plus installation kit includes only four SATA cables, though a single SLI bridge and cable-bunching front-panel header extenders are also useful.

Z87-Plus Firmware

While Asus spent a lot of time on its user-configurable UEFI start page, the most interesting settings are still found in the firmware’s Advanced menus. The company prepared a video walk-through that outlines its efforts.

The Asus Ai Tweaker menu offers separate manual and XMP modes, which are virtually identical, except that XMP overclocking mode starts with an XMP-based memory overclock. You can still change memory multiplier and timings, even after enabling an XMP profile.

The Z87-Plus eagerly pushed our CPU to 4.7 GHz at 1.3 V, though we recently discovered that tests heavily optimized for AVX cause thermal throttling at that voltage. Dropping to 1.25 V, the processor was stable at 4.6 GHz.

Because Intel's fourth-gen Core processors don't support 30 x 100 MHz memory ratios, the Z87-Plus configures our XMP-3000 profile using an increased base clock rate paired with a DDR3-2933 ratio (22 x 133 MHz). We eventually topped the memory’s maximum data rate at 1.65 V by reaching DDR3-3021. In the words of Jim Carrey in The Mask, smokin'!

The Z87-Plus adds slightly more than 25 mV to whatever memory voltage setting you specify, so we dropped to 1.625 V. Our meter showed between 1.651 to 1.654 volts after making that change.

Primary, secondary, and tertiary timings can be individually switched between automatic and manual configuration. We lock in our memory’s primary timings during overclocking tests.

The Haswell architecture's fully integrated voltage regulator makes it impossible to apply traditional CPU load-line calibration. Asus compensates somewhat by adjusting VCCIN. We achieved stability there by choosing the board’s "Level 2" Load-line Calibration setting.

Other overclocking options include Auto OC By Ratio and Auto OC By BCLK. The first method raised our CPU multipliers to 41-42-43-43x (4.1 to 4.3 GHz, depending on utilization) at stock voltage, and picked a data rate of DDR3-2400 at 1.65 V. The second method used a fixed CPU multiplier of 34x and a DRAM multiplier of 20x, with a 125 MHz base clock pushing the CPU core to 4.25 MHz at stock-voltage and DRAM to DDR3-2500 at 1.65 V.

Z87-Plus Software

Rather than copy whole sections from our Z87-Pro review or re-create those previous descriptions using identical screen shots, I spent a couple hours with the Z87-Plus software suite looking for differences and verifying that its bundled software works properly.

Application menus remain, but some are reduced to reflect the Z87-Plus’ lower-cost feature set. For example, references to the Z87-Pro’s Wi-Fi controller are missing from the Z87-Plus, which doesn't include wireless networking.

The TPU menu remains fully capable of altering CPU and DRAM clocks and voltage levels. I took the above screen shot after dropping the multiplier from 46x to 45x, increasing the core voltage from 1.25 to 1.277 V, and increasing the base clock to 101 MHz.

Also present (but not detailed in the previous software overview), Asus Boot Setting offers a DirectBIOS toggle for rebooting to UEFI mode, in addition to Fast Boot settings. Similar in function to the DirectKey on-board button, the software applet is particularly handy in a closed-up build running Windows 8.

Asus also gets its own skin for Realtek HD Audio Manager.

Other programs include Asus WebStorage Agent, Asus Disk Unlocker for large-capacity drives on older operating systems, a customized version of CPU-Z that doesn’t read core voltage correctly, Daemon Tools virtual optical drive, Intel’s network and RAID utilities, and various other freeware/shareware/trial-ware.

Biostar Hi-Fi Z87X 3D

The name of Biostar’s latest $150 motherboard is much more than a bunch of SEO (search-engine optimized) terms smashed together. The firm promises technology to back its Hi-Fi Z87X 3D’s title. For instance, a group of transistors for its high-current "3D" headphone amplifier (we know, we know...) are plainly visible between the audio codec’s EMI shield and analog audio jacks. The company promises over 100 dB through a pair of high-impedance 600 Ω headphones and a signal-to-noise ratio exceeding 110 dB.

Biostar continues pushing this "Hi-Fi" theme into power circuitry and even the board’s ground layers, claiming less signal interference. I might not have the audio gear to test the company's claims on that subsystem, but I can at least test the value of its low-noise power claims through overclocking.

The "3D" part of the title also refers to simulated 3D through headphones, a technology that’s been around for at least 15 years. Noticing that most of today’s users entered the scene after Aureal disappeared, Biostar states that “It's fantastically, especially if you've never experienced this kind of acoustic phenomenon before," typos and all.

Typically, Biostar leans heavily on a chipset’s integrated features to save cost, so we were a little surprised to only find two of the chipset’s six USB 3.0 ports on the I/O panel. We’d prefer four USB 3.0 ports and a pair of USB 2.0, rather than what the company ended up implementing.

A pair of USB 3.0 ports also connect to a forward-facing front-panel header, leaving two ports wasted in a market where many competitors add hubs just to push beyond Intel's Z87 Express specs.

A single PCIe lane feeds Realtek’s 8111F network controller, and the Hi-Fi Z87X 3D doesn’t even have a PCIe to PCI bridge. That leaves Biostar with seven PCH-based lanes to feed slots, including a x16 interface at the bottom electrically wired to four second-gen lanes. Although three-way CrossFire might be more appealing if Biostar had borrowed PCI Express 3.0 connectivity from the CPU, anyone not running a three-way array will be glad that the bottom slot doesn't tap into the middle-slot's lanes. Besides, consider the market we're addressing with these boards. Is it probable that anyone shopping for a $150 motherboard is going to have three quick Radeon cards or a CPU fast enough to feed them? Not likely. Instead, links originating from the CPU switch from x16-x0 to x8-x8 when that middle slot is populated. The bottom slot can still serve less bandwidth-hungry RAID controllers or video capture cards.

Sticking with Biostar’s previous high-value overclocking theme, we find a substantial 12-phase CPU voltage regulator at the top of the board and an integrated Port 80 display at the bottom. Catering to showmanship, power and reset switches simplify those functions when the board is on an open test bench.

The easiest way to reduce front-panel audio noise is to place its header near the controller. Biostar places its corresponding header directly in front of the I/O panel header so that both connectors can be easily fed by the same amplifier circuit. Cases with short front-panel cables are also easier to wire, but builders who insist upon hiding this cable behind the motherboard tray will probably be disappointed.

Like most of today’s competitors, Biostar includes four SATA cables in its Hi-Fi Z87X 3D installation kit. Unlike those competitors, Biostar also adds a nice microphone.

Hi-Fi Z87X 3D Firmware

Biostar’s O.N.E. menu is now nothing more than a launching point for menus that host actual settings, with one exception: the “Start” page for consecutive UEFI entry can now be set here.

A trend emerges as we continue to migrate our CPU overclock testing from 1.3 V to 1.25 V. Like the two previously-detailed competitors, we reached 4.7 GHz at 1.3 V and 4.6 GHz at 1.25 V.

The Hi-Fi Z87X 3D automatically configures our DDR3-3000 to 30 x 100 MHz, even though Biostar knows that the Haswell-based processor’s integrated memory controller doesn’t support this ratio. When we changed to a 133 MHz base clock, the board automatically switched to a 22x multiplier for a data rate of DDR3-2933. Our XMP-based timings remained.

We were even able to push the memory to 3021 MT/s by increasing the base clock, and without altering the automatically-chosen values for primary, secondary, or tertiary timings.

We’ve been hearing companies bragging about their memory overclocking triumphs at extra-high voltage levels. But we don’t accept marketing as a reason to prematurely kill our hardware. Each board in today’s comparison is manually configured to 1.65 V, and that's a voltage we verify using a volt meter. The Hi-Fi Z87X 3D reached that real voltage at a voltage setting of 1.611 V.

Hi-Fi Z87X 3D Software

Biostar’s TOverclocker utility changes slightly from our previous description in response to the Z87 platform’s alterations.

We were able to verify CPU core voltage, multiplier, and base clock functions. Other settings appeared to work, but were difficult to verify.

Besides showing system status, the H/W Monitor menu also contains a CPU fan speed override from firmware-based control.

Biostar Smart Ear 3D controls the motherboard’s 3D audio virtualization.

Bio-Remote 2 allows users to control their PC from a smart phone, and use that same device as a mouse or PowerPoint presenter.

Other Biostar programs such as its BIOS Update and Green Power utilities remain unchanged from our previous round-up.

Gigabyte Z87X-UD3H

Packed with four extra USB 3.0 ports and two eSATA connectors, Gigabyte put great effort into locking the Z87X-UD3H at its current $160 price point. The board's I/O panel is similarly packed with four full-sized video connectors, though the CPU’s integrated controller only supports three simultaneous outputs.

The six I/O panel-based USB 3.0 ports are easily accessed, but the same convenience doesn’t always apply to the Z87X-UD3H’s four front-panel connectors. That’s because one of the dual-port headers is located beneath the bottom PCIe x16 slot, where it can be blocked by a graphics card.

Not that most of us would put a graphics card in the third slot. The top two x16 slots share the processor’s sixteen PCIe 3.0 pathways, switching from x16/x0 to x8/x8 whenever the second slot is filled. Meanwhile, the bottom slot gets its four lanes from the Platform Controller Hub. Furthermore, placing a x4 (or longer) card in the bottom slot causes the Z87X-UD3H to disable two of its x1 slots.

The x1 slots that get disabled are located between the first and second x16 slots. This makes sense, since the first slot under a graphics card is often blocked by a graphics cooler anyway. At least Gigabyte was thoughtful enough to make the top x1 slot always active.

The Z87X-UD3H encourages overclocking exhibitions with its placement of power, reset, and CLR_CMOS buttons in the board’s upper-front corner. A pair of CMOS selector switches next to those buttons lets you jump from one IC to the other, and disable dual-BIOS technology to prevent improper error recovery. The exhibition theme continues, bolstered by a row of voltage detection points along the front edge. Gigabyte even adds a Port 80 code display next to the main power connector to tell overly-aggressive overclockers what they did wrong.

Traditionally, front-panel audio connectors show up in the bottom-rear corner, and Gigabyte lets history repeat itself on its Z87X-UD3H. Unfortunately, the front-panel cables on some cases are just a little too short to reach. Builders who like to wrap their auxiliary +12 V power cable over the top of the motherboard tray will also find the eight-pin connector's upward-facing latch difficult to disengage once the cable is wrapped tightly over it.

Apart from those minor differences, the Z87X-UD3H layout resembles the first three motherboards that we've already outlined in this round-up. Three slots worth of spacing between x16 interfaces improves airflow in systems with multiple graphics cards, and forward-facing SATA connectors work with all but the most outdated case designs.

The Z87X-UD3H includes only four SATA cables to connect its eight internal ports. Of course, you could instead pretend that the board only has six internal ports, since two must remain unpopulated in order to enable eSATA.

Z87X-UD3H Firmware

Gigabyte began teasing its user-configurable UEFI even before the Z87 launch, but hasn't yet produced a firmware-specific video walk-through like Asus' to show off the changes. Z87X-UD3H does allow screenshots though, so I grabbed this one to show its default start page:

All of the basic overclocking controls are accessible from the default home page, and a button at the bottom of that page allows users to add items from other menus and subtract items from the default menu. Users who prefer large fonts can also use the Resolution Toggle key (F7) to expand the center settings menu to full screen.

Unwilling to settle for basic controls, we jumped straight to the Performance menu and toggled in for a tighter screen shot. The Frequency menu provides base clock and multiplier controls for the CPU core, integrated graphics, and DRAM. XMP mode is supported here, as well as from the DRAM menu. We reached 4.7 GHz at 1.3 V and 4.6 GHz at 1.25 V.

Gigabyte still uses the term “Uncore Ratio” for portions of the CPU that ASRock/Asus now call “Cache Ratio” and Biostar calls “Ring Bus Frequency”. Because this ratio affects many of the same items formerly referred to as the uncore, I’m satisfied with Gigabyte’s response.

Because memory clock and XMP mode can both be set from the frequency menu, the DRAM menu is really only needed to access timings. Switching from Auto to Quick timing mode allows both channels to be set simultaneously.

Primary, secondary, and tertiary timings are individually switchable between automatic and manual configuration. After selecting XMP Profile 1, the Z87X-UD3H set our DDR3-3000 to its rated timings at DDR3-2933. We weren’t able to bump it any higher at its rated voltage.

Gigabyte still spreads voltage settings across an unwieldy number of menus, with a main Voltage menu that serves no other function than to link submenus.

Remember that we just said we couldn’t overclock past DDR3-2933 at the memory’s rated voltage? The Z87X-UD3H covertly adds 20 mV, so its 1.630 V setting provided an actual 1.65 V.

Z87X-UD3H Software

As with competing products, the Z87X-UD3H also includes a pile of freeware, shareware, and trial applications (nag-ware). Unlike competitors, the cFosSpeed packet-prioritization suite hasn’t been re-branded.

Gigabyte App Center links to the same applications as our previous review, including the @BIOS firmware update utility for Windows, USB Locker to control port access for USB drives, the EasyTune utility, On/Off Charge 2 for fast and/or silent (system off) charging of USB-connected devices, and EZ Setup for Intel’s new integrated applications.

Colin Brix explains the idea behind EZ-Setup in the following video:

Gigabyte EasyTune hasn’t changed noticeably from our previous description, though that description didn’t include a screenshot of its advanced menu. Here we find controls for base clock, integrated GPU ratio, CPU multiplier, and various voltage levels. I was able to confirm CPU settings functional through CPU-Z.

There’s a lot more to EasyTune, including overclocking profiles and fan maps, and anyone unfamiliar with these features might want to check them out.

MSI Z87-G45 Gaming

Even the $155 version of MSI’s Gaming series includes an E2205 network controller from Killer Gaming. So, we weren’t surprised to see little else added on top of the Z87 chipset's integrated capabilities. We found, for example, four of the chipset’s six USB 3.0 ports on the I/O panel, supplementing the two accessible from a front-panel header. There’s no eSATA, and internal SATA is limited to six drives.

We did find Realtek’s upgraded ALC1150 eight-channel audio codec, tied to both coaxial and optical digital outputs, but no DTS Connect license to convert live multi-channel audio (such as game sound) into a 5.1 stream. The Z87-G45 Gaming does include Creative Sound Blaster Cinema software for those who would like to modify output, and an increased-capacity amplifier for those who prefer high-impedance headphones.

MSI’s efforts to maximize the platform's ability to accommodate gaming hardware includes a trio of PCIe x16 slots that switch from x16-x0-x0 to x8-x8-x0 and x8-x4-x4 as cards are added. Intel's integrated PCIe 3.0 controller helps address our concern about four-lane slots for multi-card arrays, though Nvidia deliberately disables three-way SLI support on all of the boards in today's round-up. In x4 mode, you're only able to turn on CrossFire. 

The lack of third-party controller hardware means that the remaining four PCIe x1 slots are always on, saving MSI from the stinging commentary we reserve for platforms that trade on-board functionality for connectivity when you add an upgrade. That same scarcity of controllers also means that the mSATA slot steals one of the six forward-facing SATA ports if you populate it. We're alright with this. A nice big 256 GB mSATA-based SSD would definitely cut back on cable clutter. 

Other features include an I/O panel CLR_CMOS button and a row of voltage detection points along the motherboard’s front edge. Many competing products carry the overclocking theme outside of a case with on-board power and reset buttons, but we recognize that those features aren't very useful once your system is buttoned up. The only capability we really longed for during our overclocking tests was a Port 80 diagnostics display. Only three of the five submissions in today's piece include that luxury.

A well-developed layout leaves us with no major concerns or complaints. MSI moves the front-panel audio cable forward from the bottom-rear corner by about an inch, which is particularly helpful to builders who might otherwise find their cables half an inch too short. I’ve always wondered why so many case manufactures make the same mistake....

Cutting back in one place to pay for added features in another can be a good strategy, but we find it difficult to justify the inclusion of only two SATA cables. That’s the minimum needed in almost every build, and we always prefer room to upgrade. Users can buy more cables or re-use old ones, of course, but they probably won't looks like MSI's. Windowed case users beware!

Z87-G45 Gaming Firmware

MSI keeps the large-font clock and small-font settings theme for its Z87-G45 Gaming motherboard, and users can still jump quickly to its OC menu for clock and voltage configuration.

Accustomed to hitting 4.7 GHz at 1.3 V and 4.6 GHz at 1.25 V using four competing boards, were we very disappointed to see both of those limits drop by 100 MHz on the Z87-G45 Gaming. DRAM overclocking was similarly disappointing, with a maximum data rate of 2800 MT/s using G.Skill’s DDR3-3000 kit.

Everyone cheats a little with DRAM voltage these days, which is why I now adjust this setting using a voltage meter. The Z87-G45 Gaming gets to 1.65 V after picking the 1.635 V setting, and that’s far less egregious than some competing products. Thank you, MSI.

Primary, secondary, and tertiary timings are individually selectable between automatic and manual modes. The Z87-G45 Gaming maintains our memory’s XMP settings throughout overclock testing.

Our volt meter didn’t show any voltage issues using the Z87-G45 Gaming’s automatic settings, so we left those as-configured.

Z87-G45 Gaming Software

MSI still uses a customized version of Intel XTU for tuning, and its Live Update 5 hasn’t needed an overhaul in a couple motherboard generations. The Killer NIC optimization software and Creative Sound Blaster Cinema are also consistent from our previous review. With no major changes to discuss, we began looking for things that weren’t covered in previous round-ups.

MSI loads its installation disk up with freeware, shareware, and trial software in addition to its own applications and motherboard-specific software. Unfortunately, some of that nag-ware is automatically selected when you go to install the platform's drivers. 

Remember Gigabyte’s EZ Setup? MSI has been doing the same thing for a while, but calls its application “Super RAID”.

Reboots are super fast, even without added optimizations. After missing a couple of attempts to enter the UEFI, we were happy to find a “Go To BIOS” button in MSI’s Fast Boot applet.

Test Settings And Benchmarks

We were almost surprised to find Thermalright’s classic MUX-120 competitive with our recent review of high-end heat sinks, even when using its original clip-on mounting system. It’s the ease of that mounting system that wins this tester over in motherboard round-ups, and the good performance points to a good design.

Alternatively, we can point to problems with the Core i7's heat spreader interface as a reason why much larger coolers couldn’t provide much better temperatures in that review.

G.Skill’s F3-17600CL9D-8GBXLD is the only memory in this lab that defaults to our DDR3-1600 CAS 9 test standard. Faster RAM always uses slower defaults, and slower RAM requires XMP to get there. The problem is that some boards automatically enable other overclocking features when XMP is enabled. Consistency rules these tests.

We replaced the slower memory with G.Skill’s DDR3-3000 kit for our overclocking stability tests.

Corsair sent its 80 PLUS Plantinum-rated AX860i for our benchmark needs, citing enhanced support of C7 suspend mode.

Results: 3DMark And PCMark

Intel’s steady shift favoring integration leaves fewer and fewer motherboard-down components able to affect performance. We do still find board vendors trying to sneak in multiplier enhancements (via Turbo Boost), but we're determined to root out those issues and make every review a fair fight. After all, it’s not like you can count on a vendor's sneaky multiplier adjustment to help improve your maxed-out overclocking results.

3DMark looks pretty close to even, with ASRock’s half-percent default overclock giving it a slight lead in the Physics test.

PCMark favors ASRock slightly, again likely due to a tiny BCLK overclock. We’re most interested in the storage score from this test however, and it’s very consistent across all boards.

Results: SiSoftware Sandra

Sandra's Arithmetic and Cryptography modules are fairly consistent across all boards, despite tiny base clock differences.

Gigabyte drops slightly behind in Sandra's Memory Bandwidth test, though only by a few percent.

Results: Audio And Video Encoding

Lower is better for our audio and video tests. Biostar takes first place by a tiny margin in only one benchmark. Asus' Z87-Plus falls one second behind in two tests.

Results: Adobe Creative Suite

The Z87-G45 Gaming falls slightly behind in both After Effects and our OpenCL-accelerated Photoshop test. Retesting proved those deficits repeatable, but did not expose any flaw in the board that could cause them. MSI did have a major BIOS update right after we started testing, and we’re beginning to wonder if it might have changed these results. Unfortunately, we deliberately set a cut-off date for BIOS submissions to maintain fairness.

Though it’s packaged with Adobe’s Creative Suite, Acrobat is an office application. It gets bundled with productivity benchmarks in our overall performance charts.

Results: Productivity

Biostar and Gigabyte both fall a couple seconds behind the pack in 3ds Max, but the benchmark takes so long that two seconds isn’t significant.

Results: File Compression

The Z87-G45 Gaming takes a couple more small losses in WinRAR and WinZip, though results this close appear almost identical when we average them into overall performance.

Power, Heat, And Efficiency

We manually enable power-saving settings on each board before starting the benchmarks. Although the performance numbers came in very close, we tend to look for the power results to match.

In fact, the power consumption differences appear much larger than the benchmark result deltas.

We expect the most miserly motherboards to also have the lowest temperatures, but this isn't true either. ASRock’s Z87 Extreme4 demonstrates the lowest power consumption and the highest temperatures.

Again, performance differences are minor. MSI’s barely-noticeable losses in a handful of benchmarks nudge its benchmark score to just 1% under average. ASRock’s miniscule overclock likely helps it go 1% over average. Meanwhile, Biostar’s similar 1%-over-average result takes us by surprise.

The reason we show performance on an efficiency page is that it’s an easy way to compare work to energy. In this case, the comparison is work over time, so factoring out the time gives the best-performing boards a slightly larger lead. With a difference in computing time of less than 1% over average for each board, the easiest calculations are probably sufficient.

This chart shows that ASRock’s actual performance lead is roughly equal to its overclock. Still, an average power consumption nearly 11% below the average of all five boards allows its Z87 Extreme4 to take top efficiency honors.

Overclocking

Due largely to the fully integrated voltage regulator inherent to Intel’s Haswell architecture, four out of five motherboards tested today achieved the same overclocking results. We find no winner here…

Once used as a way to overclock multiplier-locked processors, base clock adjustments lost their significance when Intel adopted an integrated clock generator. The company could have given enthusiasts some flexibility back through the same multiplier straps you see on Sandy Bridge-E platforms, but only its Haswell-based K-series parts get this functionality. If you buy a locked four-gen Core processor, expect that word to mean locked out of clock multiplier and strap selection.

DRAM data rates over 2133 MT/s have an insignificant impact on most of our performance benchmarks. More bandwidth is mostly useful for gaming through the on-die HD Graphics 4600 engine. Asus and Biostar take top honors here.

When Picking A Winner Is Almost Impossible

Four out of five motherboards in today’s review were top CPU overclockers. Though it means less to overall system performance, two of those boards were also top DRAM overclockers. That tie goes to Asus' Z87-Plus and Biostar's Hi-Fi Z87X 3D.

In this day in age, performance differences directly attributable to the motherboard are tiny. Often, we see vendors juicing their BCLK frequencies by a touch here in there for the slightest advantage. We've called this cheating in the past. However, when we compared relative performance to relative price on August 5th, the above chart is what we end up with.

Biostar's Hi-Fi Z87X 3D is at the top. On the 5th, it was also the cheapest board in our round-up. And yet it hung in there with the rest of the pack in terms of overclocking. This platform is light on value-added extras; however, it handles the basics well. As such, it rose to the surface as the original pick for our Smart Buy award. This is a Tom's Hardware recognition that explicitly calls out bang for your buck, and it's well-deserved.

Comparison shoppers might point out that for $5 more, MSI’s Z87-G45 Gaming offers an improved audio codec, a high-end network controller, and an mSATA slot. We did see a few very tiny performance deficits, though. More important, the board came up a little short in overclocking, where we expected it to stretch 100 MHz higher. In a story where several platforms win something, coming up short in overclocking is what stopped us short from adding the Z87-G45 to our list. Instead, we had to consider what another $5 might buy.

Back on the 5th, three motherboards were in the $160 range, all equipped with high-end features, adding a third-party controller for additional SATA connectivity and hubs for USB 3.0 ports. Of the trio, ASRock's Z87 Extreme4 has the best audio implementation, while Asus' Z87-Plus achieves top honors in DRAM overclocking. ASRock also has the ability to split three PCI Express x16 slots into x8-x4-x4 if you really want to run a trio of Radeon cards in CrossFire. Just be aware that any other card you drop into the third slot will take bandwidth away from the graphics subsystem.

The Asus and Gigabyte boards also have third x16 slots, but they take their lanes from Intel's Z87 Express Platform Controller Hub. The Z87-Plus only wires up two second-gen lanes to its third slot, while Gigabyte connects four. To get there, Gigabyte disables two of its x1 slots. Both sacrifices are a little tough for me to accept, but we can only look to Intel for designing yet another PCH with eight PCI Express 2.0-capable lanes for expansion. Asus adds USB BIOS Flashback, a feature that proves most valuable on long-life platforms like Socket AM3. Gigabyte adds a Port 80 diagnostics display that comes in useful when you're setting up an overclock (though it might also help diagnose a failed component). The two companies have exceptional reputations in the industry, and they've spent many years developing compelling supporting software.

Those considerations opened us up to a three-way tie at the top of this round-up's price range. However, as it tends to do, ASRock cut a $20 discount with Newegg, dropping the price of its Z87 Extreme4 to $140. Whereas we were hesitant to recognize all three boards selling at $160, the Z87 Extreme4's discount was the tie breaker. Here's how our value chart appears today:

We don't like giving out awards based on temporary discounts since our logo shows up on packaging long after prices go back up, and moving forward, we're taking steps that should prevent any vendor from playing pricing games. Until the next round-up, though, it'd be impossible for us to deny that ASRock's Z87 Extreme4 is an impressive buy for the amount of hardware you get at $140. In this case, you, the reader, win. ASRock earns recognition parallel to Biostar as a result.

This isn't to take away anything from the two boards still selling around $160: Asus' Z87-Plus and Gigabyte's Z87X-UD3H. We suspect both are truly worth more than the price at which they're selling, and wouldn't hesitate to recommend either to an enthusiast able to put their feature sets to good use. So, in an unprecedented move for us, we're acknowledging both platforms with Tom's Hardware Approved recognition.

One thing we will add: ASRock's Z87 Extreme4 is worth its more prestigious award as long as it's notably cheaper than the Z87-Plus and Z87X-UD3H. We're holding ASRock responsible for maintaining the lower price it just set into place, and we're asking you to help. The free market is dynamic, and prices do fluctuate. But if you can't find the Z87 Extreme4 in stock within 10% of $140, let us know before our next round-up. We're here to be your advocates, after all.