The saga involving Chinese DRAM maker CXMT's alleged theft of Samsung's trade secrets is going strong. The South Korean court case already includes multiple convictions, two of which carry prison sentences for ex-Samsung engineers. The latest chapter is a doozy, though. Korean publication NoCut News spilled the chips on Project Hefei, a purported CXMT roadmap outlining long-term planning about said technology "acquisitions," personnel poaching, and production tape-out — all key pieces that may have directly led to CXMT's ascension to 10% of the global DRAM market.

According to leaked court documents, the prosecution says that Project Hefei was CXMT's entire DRAM development plan and was spearheaded by the firm's head of development (formerly Samsung's DRAM development lead), around August 2016 — not much longer after CXMT itself was created in June 2016.

In brief, the purported plan was to nab Samsung's Process Recipe Plan (PRP) by September 2016, poach key Samsung engineers by October 2016, have R&D complete in July 2017, and start making DRAM wafers by August 2018 at a rate of 10,000 a month. NoCut says the PRP dataset comprises 620 steps in DRAM manufacturing and includes data on equipment, consumables, and production methods.

The report states that in August 2016, CXMT first attempted to make wafers of 18nm chips by relying on the collective memories of the Samsung engineers it had hired away. Those recollections apparently proved insufficient, so after allegedly gaining illicit access to Samsung's PRP, CXMT prepared its own document in September 2016. The leaked data even included specific equipment suppliers and model numbers.

CXMT's "new" PRP was then handed out to key specialists, many of them ex-Samsung engineers, whom the prosecution says ought to have immediately recognized the data as originating from the Korean firm. The document apparently included notation and notes on process developments that were all unique to Samsung. A convicted ex-Samsung researcher with the surname Jeon, previously sentenced to 7 years in prison for manually copying parts of the PRP before leaving for CXMT, testified in this case as a witness.

The whole CXMT debacle has been playing out in South Korean courtrooms since January 2024 and is arguably far bigger than just "a company stole some tech from another." A decade ago, most of the DRAM market was taken by the Big Three: Samsung, Micron, and SK hynix. CXMT was created in June 2016 in Hefei (hence the project name), with a modest government investment of around $1.9 billion USD, allegedly with no R&D facilities whatsoever or any plan for research.

Going from zero facilities and institutional expertise to DRAM wafer production in little over two years would be an unprecedented feat, and presumably nigh impossible without the alleged IP theft; getting just the memory fab up and running usually takes two to four years, let alone any time for research. The firm claimed in 2019 that it designed its then-new 8 Gb DDR4 chips entirely in-house as a "leapfrog, independent" technology and began selling DRAM chips locally.

Then the AI locusts charged in and ate every chip on the planet. This demand resulted in explosive growth for CXMT, from an estimated 4% of the global DRAM market in Q2 2025 to around 10% in Q2 2016, marking the first time in over a decade that the Big Three held less than 90% of the pie.

Production capacity expanded to three 12" wafer fabrication facilities, expected to churn out a collective 350,000 wafers until the year is done — close to the same figure that Micron produces, of 375,000 to 385,000. CXMT is also planning to open a second fab in Beijing, aiming to produce over 600,000 wafers per month once it's online.

Furthermore, CXMT's gains aren't coming just from its DRAM market share. Revenue grew 716% in Q2 2026 alone, and its IPO on the Shanghai STAR Market in July 2026 saw its stock climb 466%, netting the firm a cool $8.6 billion USD and making it the most valuable chipmaker in the Chinese stock market.

About 70% of that money is reportedly going towards further expansion of DRAM production, rather than pricier, more complicated HBM. However, the firm has supplied HBM3E samples to Alibaba's T-Head and Cambricon, even as Samsung and SK hynix enter HBM4 production.

As of the South Korean prosecution's last tally in December 2025, Samsung's damages due to CXMT's alleged machinations ascended to "at least tens of trillions of won." A back-of-the-envelope extrapolation, considering quite a while has passed, might suggest a figure in the range of ₩40 trillion, or $29.5 billion, and rising exponentially.

The lasting impact on the memory market and technology in general is going well beyond plain number descriptors, though. All things considered, if the allegations are true, then CXMT's machinations resulted in a geopolitical-scale economic event. Dr. Evil would be proud.

The goal of next-generation HBM5 memory specification is to double performance and increase power efficiency compared to HBM4E, Samsung announced at the 'Memory Executive Summit,' an event that precedes 'Semicon Taiwan 2026.' Considering that it is barely realistic to double the data transfer rate of HBM4E in just one generation, the comment made by Samsung may imply that HBM5 will double the number of interface pins to boost bandwidth.

The goal of HBM5, which is currently under development, is to double the performance and improve the performance per watt by 20% compared to the HBM4E generation, according to Choi Jang-seok, the head of the product planning team of the memory business department of Samsung Electronics DS division. Previously, Samsung announced that its HBM5 memory stacks will feature a heat path block (HPB), which will reduce thermal resistance by 20% and simplify cooling of HBM5 modules.

Doubling HBM5’s per-stack memory bandwidth would result in peak bandwidth of around 4 TB/s per stack already in 2028 – 2029. TSMC expects AI accelerators to get to 20 – 24 HBM5/HBM5E per package configurations by the end of the decade, which means that these systems-in-packages will get a whopping 80 TB/s – 96 TB of memory bandwidth just several years down the road.

Although both DRAM makers like Micron, Samsung, or SK hynix as well as developers of HBM controllers and PHYs like Cadence, Rambus, or Synopsys already offer HBM4/HBM4E controllers and interfaces rated for 16 GT/s data transfer rates, the official JEDEC transfer rate for HBM4E will be around 12 GT/s.

If Samsung expects HBM5 to deliver twice the bandwidth of HBM4E, the HBM5 specification must either double the per-pin data transfer rate from 12 GT/s to 24 GT/s, double the interface width from 2,048 to 4,096 bits, or combine a wider interface with a higher data transfer rate. Increasing HBM5 memory stack interface width to 4,096 bits has so far been envisioned by KAIST and Marvell; however, this is certainly not an even semi-official confirmation of the specification's target.

From a performance-per-watt perspective*, widening the interface is generally easier than doubling the per-pin signaling rate. Higher per-pin speeds require faster drivers, receivers, clocks, equalization, tighter timing margins, and a more sophisticated PHY since maintaining signaling integrity at speeds well beyond 20 GT/s is not easy. But while a wider HBM interface moves more bits in parallel at a lower speed per wire, going from 2,048 to 4,096 pins means twice as many TSV/I/O paths, drivers, receivers, bumps, more complicated routing, and extremely complicated base die. So while a 4,096 I/O at moderate speed is probably best for pJ/bit, the interface/package complexity gets so extreme that it may offset the gains. Furthermore, such a wide interface Perhaps a 3,072-bit interface combined with a moderate increase in data transfer rate would be a reasonable engineering compromise, though engineers involved in JEDEC’s decision-making process may think otherwise. In any case, for now, any discussion of HBM5 specifications remains speculative.

Nonetheless, the target to double the bandwidth of HBM4E (2 TB/s per stack) within one generation is clearly a very aggressive one.

*It should be noted that achieving a 20% higher energy efficiency can be achieved not only by increasing performance, but by improving DRAM process technology, optimizing base die, lowering TSV I/O voltages, architectural changes, or power management.

Samsung has unveiled a three-phase roadmap to progressively transform high-bandwidth memory (HBM) into an integrated memory-and-compute system, culminating in the company's zHBM architecture, which places the processor directly beneath the DRAM stack and eliminates the conventional 2.5D interposer link between the two. Detailing the roadmap at Hot Chips 2026, Samsung's Sangwook Han, of the company's DRAM design team, identified the base die as the key enabler of the evolution, which began with the company’s decision to manufacture the HBM base die on an advanced logic process.

In conventional HBM, the base die (B-die) was fabricated on the same DRAM process node as the core dies (C-dies) in the stack above. Starting with HBM4, Samsung moved the base die to a 4nm logic process, primarily to reduce power draw and minimize die area. Additionally, it gave Samsung a much more capable piece of silicon.

The company contends that a die built on the same class of logic process as XPUs could do much more than serve as a data interface. Samsung now plans to progressively offload more functions into the base die, eventually removing the physical gap between memory and the XPU entirely.

The current state of HBM and its growing constraints

The current HBM architecture comprises multiple DRAM core dies stacked vertically on a base die and connected through thousands of TSVs. The stack sits beside an XPU on an interposer, with the base die bridging the memory and compute silicon.

Bandwidth has been the main driver of HBM’s evolution. The current HBM4 stack has roughly 1 to 5 TB/s of bandwidth obtained through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each. These figures are expected to rise with upcoming HBM generations. The problem is that conventional ways of scaling bandwidth present significant challenges.

TSV signaling speed is difficult to increase, so HBM generations have added more TSVs instead. However, this consumes area and forces tighter TSV pitches. The PHY has also grown more demanding. HBM4 doubled the data I/O count from 1,024 to 2,048 DQs, and signaling speed keeps rising. Power is an even bigger issue. While energy per bit is improving, total HBM power continues to rise as bandwidth is scaling faster. Samsung says this is why HBM4 moves the base die to an advanced logic process, as the denser, more efficient logic reduces power draw.

This move underpins and enables the three-phase plan. An advanced logic node shrinks the interface circuitry while enabling the HBM base die to perform functions previously handled by the processor. Samsung calls this direction custom HBM, or cHBM, which keeps the conventional DRAM stack but customizes the logic underneath it for a specific accelerator.

Phase 1: Reclaim XPU area

The first phase is about handing processor area back to compute in what Samsung calls “XPU area reclamation.” AI accelerators are hitting familiar scaling walls, such as slowing process scaling and dies pressing against reticle and interposer limits. To expand compute, Samsung plans to evict non-compute blocks, moving their functions to the base die’s underutilized silicon.

The first target is the HBM Physical Interface (PHY), one of the largest blocks on the base die. Samsung proposes replacing the traditional interface with a much smaller die-to-die (D2D) link. On an 11 × 12.8mm HBM4 base die, the conventional PHY occupies more than 8 × 4mm, while the custom HBM D2D block is about 8.5 × 1.5mm, with channel depth cut from 5.5mm to 2mm. Because the matching interface on the XPU shrinks too, Samsung also reclaims processor silicon.

Conversely, shrinking the same power into less silicon increases power density and creates hotspots. Samsung’s answer is a Heat Path Block (HPB) that provides an alternative route for heat to exit the concentrated interface region. The company says an HPB covering more than half of the PHY can slash peak temperature by more than 35%.

The bigger Phase 1 change is moving the memory controller from the XPU to the custom HBM base die. Han estimated controllers account for 5 to 10% of an XPU's area — space that, refilled with compute, could yield a 10–20% performance gain. Moving the controller next to memory also enables a new SRAM-based repair scheme in which failed C-die addresses can be redirected to SRAM on the base die, avoiding the need to sacrifice an entire spare row or column for a single defective cell.

Phase 2: Making the die a more useful smart memory subsystem

Even with the controller moved in, Samsung says a substantial portion of the base-die area remains unused. Phase 2 fills that space with more functions, first with some relatively straightforward additions. The company proposes SoC-like telemetry and reliability features, including thermal, voltage, process, and aging sensors, as well as more advanced self-test hardware.

It also wants to use the edge of the base die for direct memory expansion, arguing that capacity is becoming as important as bandwidth. Dedicated controllers and PHYs could connect a secondary tier of external memory directly to custom HBM, rather than going through conventional PCIe expansion. Han said that extra memory could be LPDDR or even HBM, offering higher bandwidth and lower latency than PCIe-based memory extension.

Last in Phase 2 is compute — right on the base die. Samsung wants to place selected processing elements (PEs) under the DRAM, offloading memory-bound work while compute-heavy operations remain on the GPU. It calls this broader 2.5D architecture advanced HBM (aHBM), citing benefits such as less traffic across the interposer and reduced latency and I/O power draw.

Phase 3: zHBM goes fully 3D, placing the processor underneath the memory

Phase 3 appears to be Samsung's most radical step, with the company halting HBM architecture optimization and rebuilding it instead. Introducing zHBM, Samsung's “ultimate solution” for maximizing bandwidth under future AI's brutal power limits.

The zHBM concept eliminates the conventional side-by-side arrangement of XPU and HBM across an interposer. Instead, the processor sits directly beneath the DRAM stack in a true 3D structure. This architecture allows Samsung to replace the large edge PHY with distributed I/Os spread across the die. Data no longer has to travel laterally across an interposer, thereby shortening the physical path and eliminating the need for conventional HBM PHY and D2D link interfaces.

Samsung says the biggest payoff is power. Its projections show zHBM cutting I/O power by around 70% compared with HBM5. In another example, Samsung models roughly 2.3X more DRAM bandwidth while reducing memory power by about 100W compared to a four-stack HBM4E system.

On the flip side, thermals are the obvious complication. Han said Samsung is targeting roughly four-high zHBM stacks, compared with the much taller 12-high or 16-high configurations possible with conventional HBM, specifically because of heat. Distributed I/O helps by spreading the circuitry rather than concentrating it into hotspots, but zHBM is a balancing act involving capacity, bandwidth, heat, and physical integration.

Manufacturing zHBM will also require advanced wafer-on-wafer bonding and hybrid copper bonding to meet the required I/O density, with a much tighter co-design process between the DRAM and SoC teams. Samsung did not provide a firm launch date or timeline for the phases. However, HBM4’s 4nm logic base die is the concrete starting point, while cHBM and aHBM are nearer-term extensions, with zHBM as the long-term endpoint.

China's DRAM champion ChangXin Memory Technologies (CXMT) has started risk production of HBM3E memory, The Information reports. Although CXMT remains a generation behind the big three memory manufacturers, which are mass producing HBM4, it goes without saying that reaching the HBM3E milestone highlights the company's rapid technological progress.

Specifications of CXMT's HBM3E products are unknown, though keeping in mind that we are dealing with risk production, specifications of actual HBM3E products from CXMT may differ from risk production samples. Meanwhile, general JEDEC specifications are well known: HBM3E modules feature a 1,024-bit-wide memory interface, supports data transfer rates up to 9.6 GT/s per pin, and can stack 8 or 12 memory devices. Depending on the exact speed bins, HBM3E can provide up to 1.228 TB/s of memory bandwidth.

Capacity of actual memory stacks depends on the number of DRAM dies used in that stack: HBM3E products can offer 24GB of capacity using an eight-die stack or 36GB using a 12-die stack when built with 24Gb DRAM devices.

Several Chinese developers of advanced processors are already evaluating CXMT's HBM3E with their processors, including Alibaba Group's T-Head and Cambricon Technologies, according to the report. If testing and qualification proceed as planned, these companies could begin using CXMT's HBM3E in commercial products as early as next year.

Since every HBM package requires multiple large DRAM dies, growing HBM output could consume considerable DRAM manufacturing capacity, which is when CXMT's aggressive capacity expansion will be useful.

CXMT's manufacturing of HBM3E is important for multiple reasons and arguably the HBM3E generation itself matters less than CXMT's ability to manufacture usable HBM at all.

Firstly, HBM is one of the critical components of modern AI accelerators, so if CXMT's HBM3E qualifies with processors from Cambricon, T-Head, and other Chinese designers, China becomes less dependent on Micron, Samsung, and SK hynix for building high-performance AI hardware.

Secondly, despite being a generation behind HBM4, HBM3E is still very capable memory and can provide several TB/s of bandwidth, sufficient for powerful AI accelerators. In fact, many Chinese developers of AI accelerators do not necessarily need HBM4/HBM4E to build useful AI systems.

Thirdly, HBM is substantially harder than making ordinary DRAM. CXMT needs not only competitive DRAM dies, but also high-yield stacking, through silicon vias (TSVs), very fine interconnects, thermal management, packaging, and testing. Reaching HBM3E risk production proves that China's memory ecosystem is advancing beyond simply manufacturing commodity DRAM.

Finally, there is also an important geopolitical angle. Export restrictions constrain China's access to advanced AI processors and HBM, so a combination of Chinese-designed accelerators, CXMT HBM3E, and advanced domestic packaging indicates that China becomes one step closer to semiconductor self-sufficiency.

ChangXin Memory Technologies (CXMT) has announced in a social media post that it has started mass production of LPDDR6 memory for a Xiaomi smartphone, Reuters reports. This is not entirely unexpected given the general LPDDR6 mass-production timeline, but the announcement is still surprising because two China-based companies are ahead of industry announcements. Yet, there are caveats.

LPDDR6 is perhaps the most substantial upgrade to the GDDR-class memory ever. Firstly, it uses PAM3 signaling, which encodes 3 bits of information across two symbols, compared with the NRZ signaling used by LPDDR5/LPDDR5X. Second, the data transfer rate increases to 43.2 GT/s. Third, the reduced I/O width from 32 bits to 24 bits requires rework at both the hardware and software levels.

Given the differences between LPDDR5 and LPDDR6, the most important factor here is not exactly LPDDR6 manufacturing, but a broader view.

On the one hand, CXMT reached mass production of LPDDR6 roughly at the same time as the established DRAM leaders, meaning it is on par with them, if not ahead. This marks a substantial change from earlier generations, when Chinese DRAM technology generally lagged considerably behind Samsung, SK hynix, and Micron.

On the other hand, reaching mass production does not necessarily mean that CXMT has achieved full technological or manufacturing parity with its larger rivals. The official announcement covers only one smartphone maker and one model, meaning CXMT's LPDD6 still has to pass validation for other handsets and other makers.

Still, the significance of CXMT's announcement is hard to understate. CXMT is no longer merely catching up by introducing a new memory generation years after its international competitors. With LPDDR6, CXMT is entering the market during the standard's initial commercialization, which means the technology gap between China's leading DRAM producer and the industry's established players has narrowed considerably.

Which brings us to the question of whether CXMT can maintain this pace. Developing a competitive LPDDR6 device is one thing, producing it at high yields and in sufficient volumes to supply major customers is another. For now, we are talking about a niche smartphone with memory operating at undisclosed performance.

If CXMT can mass-produce LPDDR6 for the whole market and manufacturers, we may well have seen the change of the industry leader. Yet, given one niche device, we certainly cannot say so for now.

China's leading DRAM producer ChangXin Memory Technologies (CXMT) has filed a lawsuit against the U.S. Department of Defense in an attempt to overturn its classification as a company linked to China's military, Reuters reports. CXMT claims that it has no connection to the Chinese People's Liberation Army, and argues that the Pentagon's decision lacks supporting evidence, violated due-process requirements, and has damaged both its business and reputation.

The Pentagon initially classified CXMT as a Chinese military company in January 2025, when Joe Biden was the president. The Trump administration subsequently maintained the designation when the Defense Department updated the list in June. CXMT says it spent more than a year supplying information to the Defense Department in an attempt to overturn the classification and remove itself from the list.

The company claims the DoD published a notice in February indicating that CXMT would be taken off the list but withdrew that notice later the same day without any explanation. In June, the Pentagon classified CXMT as 'directly affiliated with MIIT and indirectly affiliated with SASAC and MIIT.' MIIT is China's Ministry of Industry and Information Technology, whereas SASAC is the State-owned Assets Supervision and Administration Commission of the State Council, an organization that formally owns the government's stakes in non-financial state-owned enterprises.

While CXMT memory can certainly be found in systems used by the PLA or China's secret services, this does not automatically make CXMT a direct supplier to these entities and therefore does not prove that CXMT is a Chinese military company.

CXMT points out the Pentagon's original motivation to include the DRAM maker in its list was a remarkably weak-looking 'military grade' argument. According to the complaint, DoD's 2024 report said CXMT contributed to China's defense industrial base partly because its DRAM is dual-use and cited an advertisement describing CXMT products as 'military grade.' CXMT says that advertisement came from an unauthorized distributor, which later admitted the characterization was erroneous.

In addition, CXMT claims that its DRAM products conform to JEDEC commercial standards and lack the requirements imposed on Chinese military-grade semiconductor components involving areas such as temperature, packaging, testing, and military oversight. Also, it says that should its products be made in the U.S., they would be classified as for 'purely civilian uses' and that it 'does not hold any licenses to manufacture products for military use.'

Inclusion on the Pentagon's list of companies linked to the Chinese military can result in restrictions involving U.S. government contracts, something that CXMT barely seeks. But more importantly, it can affect a company's commercial relationships (as many companies do not want to be affiliated with companies linked to the Chinese military) and reputation. Indeed, CXMT claims that since January 2025 the designation has continuously hurt it commercially and reputationally, and that the lawsuit is intended to protect its business interests.

The ongoing DRAM crisis has led to a sharp increase in laptop prices, with manufacturers facing exponentially high component costs, particularly memory and SSDs. The situation has created a growing gap in the affordable gaming laptop segment, with most entry-level models becoming increasingly expensive. In its response, MSI has introduced the new Katana 15 HX C14 that features Intel’s 14th-gen Raptor Lake Refresh processors along with support for both DDR5 and DDR4-3200 memory.

Depending on the region, MSI will be offering the value-focused gaming laptop in two variants, featuring dual SO-DIMM slots with either DDR4 or DDR5 compatibility. For context, a 32GB (2x16GB) DDR4-3200 SO-DIMM memory kit can be purchased for around $200, while a DDR5-6000 kit goes for over $400. MSI did not specify the DDR4 capacity as standard, only that the laptop supports up to 96GB, which seems unlikely given no 48GB DDR4 SO-DIMMs exist.

Configurable with up to a 24-core Intel Core i9-14900HX processor, the laptop should offer plenty of CPU performance for demanding tasks besides gaming. It will be available with up to an Nvidia RTX 5070 laptop GPU offering support for the latest AI features, GDDR7 memory, DLSS 4.5, and real-time ray tracing. MSI claims that the Katana 15 HX C14 is tuned for up to 170W of combined CPU and GPU power, while the cooling system with dual fans, three heat pipes, and four exhaust outlets helps in sustained performance. There are also dual-PCIe Gen 4x4 M.2 slots, allowing gamers to add a separate SSD dedicated to their gaming library.

Display options include a 15.6-inch IPS panel available with either QHD (2560x1440) resolution that supports up to a 165 Hz refresh rate or FHD (1920x1080) resolution with up to a 144 Hz refresh rate. In terms of design, the laptop comes in a stealthy black finish with textured slash patterns inspired by traditional Japanese blades along with bright red logos. The chassis measures 22.9mm in terms of thickness and weighs 4.62 pounds, making it fairly compact for a 15-inch gaming notebook.

Other notable features include support for Wi-Fi 6E and Bluetooth 5.4, a 4-Zone RGB gaming keyboard with 1.7mm key travel, a 240W power adapter, USB Type-C with Power Delivery 3.0, a 60Whr battery, and DTS-enhanced dual 2W speakers. According to MSI, the new Katana 15 HX C14 will be available globally, although there's no pricing information at the moment.

High-bandwidth memory (HBM) is one of the key components of AI systems that is not currently assembled in the U.S., but this is going to change in 2029, when SK hynix initiates packaging of HBM memory modules at its facility in Indiana. This week, the company held a groundbreaking ceremony for its HBM production base in America and intends to start construction of the plant shortly.

SK hynix's HBM production site in West Lafayette, Indiana, will specialize in advanced packaging, testing, and R&D of HBM. The facility is set to cost the company around $4 billion, which highlights its advanced technology capabilities as well as vast capacity. The DRAM maker expects to open the cleanroom by October 2028 and begin volume production of next-generation HBM in the second half of 2029, which is about a year later than originally envisioned. Once commercial operations kick off, SK hynix expects the Indiana site to employ around 1,000 people.

Despite being described as an HBM production base, the Indiana site will not manufacture the DRAM wafers, but will package HBM stacks using DRAM wafers produced in South Korea and base dies produced in South Korea, Taiwan, or the U.S. Nonetheless, SK hynix intends to market the resulting devices as its first U.S.-made next-generation HBM products. Meanwhile, as custom HBM-class memory gains traction in the second half of the decade, assembling such stacks close to American customers may be particularly important both for SK hynix and its clients, as it enables SK hynix to shrink the feedback loop significantly.

In addition to building the advanced packaging and testing plant, SK hynix will also establish an Advanced Packaging R&D Testbed next to the manufacturing lines. The facility will enable SK hynix to work with customers, universities, and commercial partners on future packaging technologies, build prototypes, and quickly validate their performance and manufacturability in an actual production environment. In the era of customized HBM, such a facility could become a significant competitive advantage for SK hynix.

SK hynix also signed a memorandum of understanding with Purdue University to jointly research system integration and advanced packaging technologies, including HBM.

"The United States is the epicenter of AI innovation, bringing together premier customers, top-tier R&D capabilities, and partners and Indiana fab will become a gateway to deliver first Made in USA HBM products," said Kwak Noh-Jung, CEO of SK hynix. "We will expand our investments and collaboration in the U.S., grow together, and become the most trusted partner in shaping the future of AI in America."

Nvidia's NVLink Fusion program gives the company's partners the building blocks necessary to connect custom chips with the NVLink scale-up domain used to join many separate processors into a single coherent system like the Vera Rubin NVL72 rack-scale accelerator. Today, Nvidia is adding a new building block to that toolkit: NVHBM, a custom implementation of the high-bandwidth memory that underpins practically every AI accelerator in use today.

As Nvidia describes it, NVHBM is a custom HBM base die that promises higher bandwidth, lower power usage, and a smaller on-die footprint than traditional HBM4e. Nvidia says it's designed and validated with "leading memory vendors," so it promises custom silicon developers faster time-to-market than implementing commodity HBM from the ground up. But it's worth re-emphasizing that this isn't an HBM replacement. Instead, it's a new building block that Nvidia is only offering to its custom silicon partners.

Memory bandwidth is everything for AI accelerators, and NVHBM promises up to 30% higher bandwidth per stack than standard HBM4e. For memory-bandwidth-bound AI workloads, that higher bandwidth translates into higher throughput, such as a higher tokens-per-second rate for AI inference.

The custom NVHBM base die also reduces the footprint of memory-related circuitry on the main custom accelerator die. Traditionally, the HBM memory controller has been incorporated into the primary silicon die on the package. NVHBM instead moves the memory controller into the base die of the HBM stack and provides a smaller custom PHY that NVLink Fusion customers can then integrate into their designs.

Nvidia says this approach frees up precious package real estate that can then be used for additional compute die area — up to 30% more compute on the primary silicon die. NVHBM further promises to simplify the interposer routing used to join multiple chips together for designs using advanced packaging techniques.

NVHBM also provides power savings versus off-the-shelf HBM4e stacks. As Nvidia has continuously hammered home in the Vera Rubin roll-out, every watt that isn't going into token production is a watt wasted. Nvidia says NVHBM uses 15% less power than commodity HBM4e, and that power savings can be banked for performance-per-watt improvements, reallocated into more functional units for a custom accelerator design, or translated into higher sustained performance within the same power budget.

Higher bandwidth at lower power is a huge win for AI accelerators that are moving massive data structures like model weights and KV caches around, especially when those savings are multiplied across many thousands of chips. The energy saved on data movement can be plowed back into higher performance from the accelerator itself or reallocated to support larger numbers of accelerators within the same fixed power envelope.

But these are, as of now, reasons for Nvidia's prospective partners to consider incorporating NVLink Fusion and NVHBM into their custom designs, not benefits that will materialize in the Rubin rack-scale systems already in production.

Along with NVHBM itself, Nvidia announced that Amazon's Annapurna Labs will be its first partner on NVHBM. , and Annapurna VP Nafea Bshara says: “We look forward to this technology collaboration to benefit future AWS infrastructure designs.” Annapurna's next-generation Trainium 4 AI chips will already support the NVLink Fusion scale-up interface, so it seems likely that follow-on chips will support NVHBM, too.

d-Matrix presented Raptor, which it calls the first 3D DRAM accelerator for generative inference, at Hot Chips 2026 this week, showing a TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed DRAM die that delivers 100 TB/s of bandwidth from 32GB per card.

Co-founder and CTO Sudeep Bhoja put the vertical interface's energy cost at 0.37 pJ/bit against roughly 2.4 pJ/bit for moving data into an HBM4 base die, calling it "a measured number" from working silicon, and the accompanying ISCA 2026 paper, written with the University of British Columbia, projects around 4.7 times higher throughput per card than HBM-based designs. Bhoja, however, didn't disclose who manufactures the DRAM die.

CEO Sid Sheth told CNBC in June that Raptor is slated to launch in 2027, but at Hot Chips the company gave no firm date or information on volume and pricing, and every performance figure shown, including 988 tokens per second per user on the 2.8-trillion-parameter Kimi K3 model at 1M-token context, is a d-Matrix projection built on early silicon.

The custom DRAM die

Raptor inverts the usual 3D stacking arrangement by putting the logic die on top and the DRAM underneath, so a cold plate sits directly on the compute silicon and the DRAM die doubles as the interposer, carrying PCIe and die-to-die signals down through its TSVs. "For the same amount of power, you can drive the bandwidth up," Bhoja said during the session, "and so we were able to drive the bandwidth up here to 100 terabytes per second."

The one-high stack achieves a power density of roughly 0.5W per square millimeter, which liquid cooling can handle, but the DRAM is designed for a junction temperature of 105°C, where retention collapses from a standard 32ms to 4ms, and the memory must refresh eight times more often. d-Matrix absorbed that penalty by shrinking each microbank to 1,366 rows and about 5.33MB, so a full refresh sweep costs only 1.37% of overall bandwidth.

The die carries 840 banks per chiplet, of which 72 (around 9%) are spares wired into a two-level mux chain the company calls bank chaining, letting any two failed banks anywhere on the die be switched out while channels stay symmetric. A [132,128] Reed-Solomon code on the logic die corrects two symbol errors per 128 bytes, with a CRC behind it. The interface has no PHY, no burst structure, and no sideband pins, so conventional data-bus inversion was impossible; d-Matrix instead compares each 128-byte flit to the previous one and stores a 1-bit inversion tag alongside the ECC metadata, recovering roughly 20% of the I/O power DBI would have saved. At full tilt, the vertical interface still burns 296W of the 422W per-package budget the ISCA paper discloses.

The bank geometry, spare-bank mux tree, refresh behavior, and interleaved ECC columns were all co-designed with the compute die. The 0.37 pJ/bit figure exists only because of that pairing, and no memory maker has anything like this die in its catalog.

Who's supplying it?

d-Matrix has named TSMC for the N4P logic die and Alchip as its ASIC design and 2.5D/3D packaging partner, but neither company operates a DRAM fab, and across the Hot Chips talk, the ISCA paper, and every public announcement since the Pavehawk 3DIMC test silicon came online last September, the firm has never identified who fabricates its custom DRAM. Only three companies make leading-edge DRAM at volume, and all three are allocating capacity to HBM4 lines that are effectively sold out through 2026.

J.P. Morgan estimates DRAM prices will have risen more than 400% between the start of 2024 and the end of 2026. In addition, analysts have recorded contract price increases of 90% to 95% in Q1 2026 alone, and SK hynix CEO Kwak Noh-jung told Reuters in July that "customer demand will remain higher than our supply capacity even beyond 2030."

Nvidia, the memory makers' largest and most leveraged customer, is reportedly testing Rubin Ultra configurations with as little as 192GB because it may not be able to source enough HBM4E. A startup with roughly $450 million raised, asking a memory maker to run a bespoke die with non-standard bank geometry on capacity that could otherwise print HBM, is negotiating from a far weaker position than that, and until the supplier is named, Raptor's 2027 volume plan rests entirely on an unknown, undisclosed dependency.

The die's 11.4 MB/mm² density is roughly half of HBM4's 21.9 to 26.3 MB/mm², Bhoja acknowledged during the Q&A: "A lot of the drop for us was also because we used a not-so-advanced DRAM. And so if we used a more mainline DRAM, just like the HBM4 guys are doing, we would be able to push that up almost all the way to the HBM4 numbers." The density penalty therefore tracks back to whatever foundry arrangement d-Matrix currently has.

32GB per card

Raptor's 32GB per card stands against 192GB to 288GB for HBM4-equipped accelerators, so d-Matrix sizes deployments at rack scale instead: 72 cards carry 2.3TB, enough to hold Kimi K3's weights at 4-bit precision with headroom for around 54 concurrent users at 1M context, by its own calculations. "Even with 32 gigabytes of memory capacity, we are able to solve SOTA models in a scale-up network, so no bits are wasted," Bhoja said.

KV cache growth works against that arithmetic over time, and co-presenter Aayush Ankit, who led Raptor's SoC architecture at d-Matrix before joining Meta's MTIA team, explained the failure mode while dismissing SRAM alternatives: "We are making this unit of compute blazingly fast. Communication becomes a bottleneck soon enough." Once models and context no longer fit a single rack, inference spills into the inter-card synchronization overhead that the vertical bandwidth was meant to eliminate, which the ISCA paper concedes.

Cerebras claimed 969 tokens per second on Llama 3.1 405B in November 2024, with third-party firm Artificial Analysis verifying the figure on live hardware, and that remains the closest published reference point for Raptor's numbers. d-Matrix's 988 tokens per second per user on a model seven times larger would be a step change if it holds water, but no third party has measured Raptor, and the comparison points in the ISCA paper are simulations anchored to early silicon characterization.

Asked by an Nvidia employee about multi-layer stacking plans, Bhoja said: "Our roadmap is still a work in progress, and we have a hard enough time trying to get one-high to work and work around all of the thermal issues of that." Samsung brought its own version of the idea to Hot Chips with zHBM, a concept that stacks HBM directly on the processor and carries a claimed 70% power-efficiency gain over an HBM4E setup, with no production timeline before HBM5. The problem for d-Matrix is that Samsung runs its own DRAM fabs; d-Matrix doesn't. Whether it can get wafers at volume remains to be seen.

Full d-Matrix Hot Chips 2026 presentation

Earlier this month, Samsung introduced the industry's first LPDDR5X-PIM memory, adding in-memory logic to the low-power memory standard, and at Hot Chips 2026, it dove into the memory technology that we've previously seen at play through HBM stacks.

PIM, or Processing-in-Memory, is a technology Samsung demoed as early as 2021, piloted through HBM stacks in AMD accelerators. It's a small bit of logic that sits alongside DRAM cells, allowing basic calculations to happen directly in-memory. By handling those basic calculations locally, Samsung is able to eliminate the processor as a bottleneck and speed up, in particular, AI inference. In inference tasks, Samsung says its LPDDR5X-PIM is 2.28x faster than standard LPDDR5X, in fact.

The reason for adding in-memory processing to LPDDR5X is pretty clear: HBM is too damn expensive. Micron warned just a day earning at Hot Chips that the HBM wafer demand is only getting worse, and Samsung opened its presentation with something we're all well aware of. Memory makes up the bulk of AI chip costs, and its share of the pie continues to grow. Add on top of that the power demands of DDR5, much less HBM, and LPDDR5X seems like an ideal target for PIM.

Samsung introduced HBM-PIM in 2023, and at the time, introduced the concept of LPDDR5X-PIM. What it shared at Hot Chips is a real product, taking the concept of LPDDR5X-PIM and putting it through validation. Samsung is also looking ahead for LPDDR6X-PIM, and the company says it hopes to have an initial specification from JEDEC this year.

Bringing in-memory processing to Samsung LPDDR5X

Above, you can see a basic layout of how Samsung integrated PIM into LPDDR5X. Each memory bank has its own PIM, which is an advancement over HBM-PIM, where Samsung had to cut banks to fit the logic. The memory bank, scale register file, and source register file feed parallel MAC trees. Once calculated, the output (either integer or floating point output) is written to a vector register file.

Samsung says its LPDDR5X can operate in two modes: single-bank (traditional DRAM) or multi-bank (PIM). Traditional DRAM controllers work, with commands switching between standard read/write or a PIM read/write depending on the mode. The challenge, according to Samsung, was reordering with conventional DRAM.

Samsung uses what it calls Address Align Mode (AAM) to get around the reordering issue. It maps DRAM addresses to MAC instructions, assigning the VRF/SRF address based on the RA/CA address, respectively, and not the Instruction Register File.

To demonstrate how data moves through the memory cells and calculations are performed, Samsung provided an example of a MAC operation, assuming weight parameters for the data are already written into the cell, and the memory is operating in multi-bank (PIM) mode.

Storing 512 bytes of FP8 activation data, it's first broken down into 16, 256-bit packets, which are written into each of the banks in and noted in the Source Register File.

A PIMX_RD reads the weight data from the DRAM bank, feeding into the MAC trees alongside the data from the SRF. Once the calculation is done, the output vector from each operation is written into the Vector Register File.

Once the calculation is done, a PIMX_WR command transfers the output data back to the DRAM bank. Samsung noted there doesn't need to be a 1:1 relationship between reads and writes, but it's useful for this example. With a VRF size of 1 kbit, a maximum of four calculations can be written to the VRF.

With the output written back to memory banks, the host just needs to read the data from memory. The host switches to single-bank (conventional DRAM) mode and executes 16 reads to gather the output from all of the memory banks.

Samsung LPDDR5X specs and preliminary performance

Samsung's LPDDR5X-PIM looks a lot like LPDDR5X. It uses a standard 561-ball array for packaging, just like LPDDR5X, and Samsung uses two 64-bit ranks with 16 GB modules. The critical number here is bandwidth. With LPDDR5X-9600, peak bandwidth is 76.8 GB/s, but that's increased by eightfold with PIM to 614 GB/s by reducing data movement and keeping basic logic local.

Samsung uses four dies per rank, for a total of eight dies. Not the various registers above, as well, as they're important for the illustration of data flow through Samsung's LPDDR5X-PIM memory.

In Samsung's preliminary benchmarks, LPDDR5X-PIM is impressive. In model run time, Samsung say a 2.28x improvement with PIM, and in tokens per second (TPS), PIM offered a 3.01x increase in performance.

The slide above shows what happened behind the scenes to gather these numbers, with Samsung using an edge AI accelerator — we're not sure which, but perhaps an early Gaia SoC — and testing Llama 3.1 with 8 billion parameters. Notably, the output is different, which one attendee pressed Samsung about. The company says optimizations are ongoing to improve accuracy, but it expects the performance benefit to remain the same.

One of the main advantages of LPDDR5X is right there in the name: low power. With PIM, power consumption becomes more of a concern, but Samsung says it doesn't expect higher power consumption overall compared to conventional DRAM. The presenter noted that peak power consumption will be "much higher" due to the bursty power draw of the PIM, but Samsung still expects overall power draw to be lower than conventional DRAM.

That comes down to extra reads/writes. Although PIM represents a power increase, decreasing the number of times data needs to move between DRAM and the host will lead to overall lower power consumption. "We're not having significant power increase," as Samsung's Karam Hwang put it.

LPDDR5X has, until recently, only had applications in consumer products. However, SOCAMM2 serviceable modules allowed Nvidia to use LPDDR5X as the memory of choice with its Vera CPU. And Intel uses LPDDR5X with its new Crescent Island AI accelerator.

Even with PIM, LPDDR5X doesn't come remotely close to the bandwidth with available with HBM, but it has a lot of applications elsewhere. Samsung's targets of server, client, and mobile are telling, with LPDDR5X-PIM accelerating edge AI on mobile and client devices, as well as arriving in lower-scope accelerators like Crescent Island.

Full Samsung Hot Chips 2026 presentation

When it comes to building a gaming PC, DDR5 RAM clocked at speeds of 6,000 MT/s is often touted as the sweet spot for specs. While slower and faster speeds are available, it's very much the benchmark for both price and performance, which is why it's noteworthy that this particular configuration now costs $400, a more than 400% increase from the low prices we've seen in the past.

• $401 for Corsair Vengeance 32GB DDR5 600 ($215 off)

In addition to our ongoing RAM price tracking, we perform daily spot checks on pricing for discounts or deals for 32GB (2x16GB) of DDR5 RAM, given its aforementioned significance as the "benchmark" when it comes to capacity. In recent weeks, the price of 32GB DDR5 6000 RAM has been creeping ever closer to that unfortunate $400 milestone, and in the last few hours we've just crossed the threshold. That's not to say that prices might fluctuate back down in a day or two, but generally the traffic is only moving in one direction.

You can buy 32GB of DDR5 RAM at slower speeds for less — this Corsair Vengeance DDR5 4800 is "just" $359 — but good RAM is now harder (and more expensive) to come by than ever before.

According to data from PCPartPicker, this particular 32GB DDR5 6000 kit from Corsair has been as little as $80 in years gone by at Newegg, marking a full 400% price increase on the lowest we've ever seen on this model.

RAM prices elsewhere have climbed by as much as 500%, with 128GB of DDR5 now costing $3,399 in stores. The causes of the PC component crisis are numerous and well-documented. AI buildouts are consuming much of the world's NAND and flash manufacturing capacity, which is having a knock-on effect for consumer production. Famously, Micron even wound up its consumer brand Crucial in favor of serving more enterprise customers.

All signs point to the memory shortage, and thereby pricing, getting worse in the coming months. As such, bundles and pre-built PCs remain one of the only ways to insulate yourself from cost increases if you're in the market for new hardware. As mentioned, slower memory speeds are available at lower prices, but compromising for 4,800 MT/s RAM to save $40 when building a PC is an extremely tough state of affairs.

Memory will account for roughly 30% of hyperscaler capex this year, up from about 8% in 2023 and 2024. Conventional DRAM contract prices rose 90% to 95% in a single quarter, and Meta is already running recycled DDR4 behind CXL across millions of servers, cutting server counts by up to 25% for some inference workloads. Into that market, Marvell has brought a three-tier "AI memory infrastructure" portfolio, announced at FMS 2026 in Santa Clara on August 4 and pitched to EE Times last week, where product marketing VP Khurram Malik put DDR4 reuse at the top of the CXL use-case list.

Only one piece of it is new: the Bravera SC6 PCIe 6.0 SSD controller, which samples in Q4. Structera X has been shipping since 2024, the Structera S switch was announced at OFC in March, and the Photonic Fabric optical memory tier came with the Celestial AI acquisition in February. Meta, the reference customer for the use case Marvell is selling, did it with an ASIC of its own design rather than anything from Marvell.

What's new (and what isn't)

The Bravera SC6 is a PCIe 6.0 x4 controller with 16 NAND channels, eight chip enables per channel, a 3,600 MT/s ONFI and Toggle interface, and 12 Arm Cortex-R82 cores plus three Cortex-M7s, according to Marvell's product blog.

Marvell says it doubles the Bravera SC5, supports NAND from multiple suppliers, and uses a host-managed flash translation layer, meaning cloud operators control write placement, garbage collection, and wear leveling themselves, with KV cache spillover from HBM to SSD as the primary workload. Sampling starts in Q4 2026, which puts drives in 2027 at the earliest on the timeline Tom's Hardware Premium laid out for the PCIe 6.0 controller field, where Phison and Silicon Motion are chasing the same Gen6 drive launches.

Structera X 2404 and X 2504, the DDR4 and DDR5 expansion controllers, were announced in July 2024, and Marvell's FMS blog says both are in hyperscaler deployments, with inline LZ4 compression that Malik told EE Times yields roughly 2 to 2.5 times the effective capacity.

The Structera S 30260 switch, announced at OFC in March, carries 260 PCIe 6.0 and CXL 3.x lanes, connects 16 or 32 CPUs or GPUs to up to 48TB of shared memory at 4 TB/s aggregate bandwidth and under 460ns round trip, and begins sampling this quarter. Photonic Fabric came in with the $3.25 billion Celestial AI acquisition that closed in February, with Marvell now describing it as a shared-memory tier reaching up to 50 meters with up to 32 TB of warm KV cache and a claimed 2 to 3 times token throughput inside existing footprints. Marvell also took a $2 billion investment from Nvidia in March, tied to NVLink Fusion, the proprietary scale-up fabric CXL pooling has to sit alongside.

DRAM contract prices have tripled since Structera launched

Conventional DRAM contract prices rose 90% to 95% quarter-on-quarter in Q1 2026, the steepest increase on record for every DRAM category. Q2 added another 58% to 63%, and server DRAM is set to climb a further 13% to 18% in Q3, held in check mainly by the long-term agreements U.S. hyperscalers signed to cap pricing through 2027 and 2028. Server DRAM buyers in the U.S. and China were receiving about 70% of their orders late last year as suppliers diverted wafers to HBM.

Samsung, SK hynix, and Micron have all been winding down DDR4 output since last year, and TrendForce put the legacy memory rally at up to 50% for DDR4 in Q1 alone. A module pulled from a decommissioned 2021 server is now worth a multiple of what it was when Structera X was announced, and the DDR5 that would replace it has roughly doubled in price twice. When Marvell first pitched DDR4 reuse in 2024, it was a sustainability line item, but two years later, the memory crunch has turned it into a capex line item.

Meta's recycling numbers

Meta's Vistara ASIC, presented at ISCA 2026 in late June, is a CXL 2.0 Type-3 expander on a PCIe 5.0 x16 link that bridges two DDR4 channels to a host and runs at 128GB per chip using 32GB modules recovered from retired machines. Each MemServer pairs a 158-core AMD EPYC Turin with 768GB of local DDR5-6400 and 256GB of CXL-attached DDR4-2400, and Meta claims idle round-trip latency of around 50ns on the controller path.

The paper states that around 40% of Meta's fleet is memory-capacity bound, that its servers last three to five years while the DRAM inside them is good for seven to 10, and that the deployment cuts server counts by up to 25% for disaggregated ML inference, average latency by 29% for distributed caching, and job failures by 33%, The Register from the paper ahead of the talk.

Malik told EE Times, "The first and foremost important use case within CXL is the recycling of DDR4," and Marvell's FMS release says Structera X was "developed in close collaboration with leading hyperscalers" without naming one. Meta's paper describes an in-house ASIC, an in-house MemServer chassis, and an in-house Linux page-placement stack, the full path one would take when volume justifies its own silicon, while Astera Labs' Leo controllers reached Microsoft Azure's M-series preview in November last year.

CXL's deployment gap

SemiAnalysis declared CXL dead for AI in March 2024 because Ethernet-style SerDes such as NVLink carry roughly three times the bandwidth per millimeter of die edge as PCIe 5.0 or 6.0, so every CXL lane on an accelerator costs scale-up bandwidth that could have gone to the GPU-to-GPU fabric instead.

Marvell's CXL pitch accordingly targets CPU-side capacity and KV cache staging rather than the GPU-to-GPU path where you’ll find NVLink Fusion. Yole estimated two-thirds of servers sold in Q1 2025 were CXL-capable and expects more than 90% to be by the end of this year, yet it puts the share of servers actually using CXL at close to zero today and only 13% by 2030.

Marvell's benchmarks for the Structera S show a 16TB pooled DRAM tier delivering 4.8 times the inference throughput and an 82.7% cut in time to first token in GPU configurations, attributed to keeping KV cache in DRAM instead of recomputing or reloading it. Those are vendor numbers with no disclosed model or baseline, and the switch only starts sampling this quarter. Nvidia, AMD, and the SSD makers all offer their own routes for the same cache spillover.

Nvidia has told some of its largest customers that the prices of servers containing its AI chips will rise by more than 15% in many cases, Bloomberg reported on Saturday. The increases will take effect on Grace Blackwell and Vera Rubin systems shipping early next year, according to people familiar with the matter, who commented on communications that have not yet been made public. The size of each increase will depend on the chip generation and the memory configuration involved. Companies that build servers under contract for large data center operators, including Microsoft, Google, and Oracle, have recently notified their customers of the forthcoming increases, the people told Bloomberg.

This is another example of the so-called "RAMageddon" that's gripping the DRAM market, with contract prices having risen at record rates this year. Analysts projected that conventional DRAM contract prices would climb 58% to 63% quarter-over-quarter in Q2 2026, following a Q1 surge of 90% to 95%, as suppliers reallocated capacity toward HBM and server products. SK hynix said in October last year that it had already sold out its entire 2026 memory production capacity, and Samsung and SK hynix raised 2026 HBM3E supply prices by close to 20% before the year began.

AI systems carry enormous memory loadouts, with Nvidia's Rubin GPU shipping with up to 288GB of HBM4 per package, and the NVL72 rack-scale system combines 72 of those GPUs, putting more than 20TB of HBM in a single rack before accounting for the LPDDR attached to its Vera CPUs. With HBM production consuming roughly four times the wafer area of equivalent conventional DRAM, memory has become one of the largest line items in an AI server's bill of materials, and it's continuing to rise at a stratospheric pace.

Ironically, the supply crunch that's now inflating Nvidia's systems is the same one its demand helped to create. The three major memory makers spent this and last year shifting advanced nodes and new capacity toward HBM and high-capacity server DRAM, starving commodity markets in the process. Consumer DDR5 pricing has more than doubled since late 2025 as a result, with a mainstream 32GB DDR5-6000 kit selling for around $392 in August against $110 to $140 a year earlier, according to our RAM price tracker.

Nvidia has already passed rising costs through to consumers, raising prices on GeForce graphics cards earlier this month. The Bloomberg report indicates the same unrelenting pressure has now reached the top of the Nvidia stack, where hyperscalers as well as PC builders will be absorbing the increase. A 15% rise on rack-scale systems that sell for several million dollars each adds hundreds of thousands of dollars per rack across deployments that run to thousands of racks.

Nvidia runs a gross margin of roughly 75% non-GAAP, among the highest in the semiconductor industry, and the reported hikes indicate the company intends to pass memory cost inflation on to customers rather than absorb it, which it can more than afford to do. Meanwhile, supply of its accelerators from TSMC still can't meet demand, which limits buyers' immediate leverage.

Whether the increases push hyperscalers further toward AMD's accelerators or their own custom silicon will depend on how quickly those alternatives can absorb displaced demand, and all of them draw HBM from the same three constrained suppliers.

Bad bots account for 91% of the traffic reaching one retailer's DDR5 memory product pages, roughly 10 automated requests for every legitimate visit, according to a LinkedIn post this week from Jérôme Segura, VP of threat research at bot-mitigation firm DataDome. The figure updates research DataDome published in March, which measured the ratio at about 6:1 across several e-commerce sites.

Over the same period, the cheapest 128GB DDR5-6400 kit tracked by Tom's Hardware has reached $3,399, ten times its record low pricing. The Thales 2026 Bad Bot Report puts bad bots at 40% of all web traffic, less than half the share Segura reports on DDR5 listings.

DataDome's March report documented a single operation that generated more than 10 million blocked requests, with a one-hour sample showing 91 DDR5 listings each polled around 551 times, or once every 6.5 seconds. The requests carried cache-busting parameters to defeat cached stock data and targeted industrial module makers such as Micron and Apacer, as well as DIMM socket suppliers Amphenol and TE Connectivity, alongside consumer brands.

Segura wrote on LinkedIn that retailers carrying memory should assume their "traffic analytics are probably understating the problem significantly."

Keep in mind that the 91% figure comes from one unnamed retailer, and DataDome hasn't published a sample window or its methodology. DataDome also sells the product that blocks this traffic, and page requests ultimately aren't purchases, so the ratio measures monitoring pressure on listings rather than how much stock bots actually end up securing, which can’t easily be quantified.

Apacer CEO C.K. Chang said in July that DRAM supply to independent module makers could fall to 30% of 2026 levels next year, and TrendForce expects conventional DRAM contract prices to rise another 13% to 18% in Q3 after roughly 60% in Q2. Hyperscale buyers have reportedly placed deposits against most of 2027's DRAM output.

A 32GB DDR5-6000 kit that averaged $72 this time last year now averages $392 on PCPartPicker. While graphics card and console scalping in 2020 and 2021 ran against scheduled restocks that eventually outpaced resale demand, no equivalent restock date exists for consumer DDR5 before 2027 at the earliest.

Framework stopped selling standalone RAM in November last year, citing scalpers, and Micro Center sells its CPU, motherboard, and 32GB DDR5 bundles in-store only with a one-per-household limit. Newegg and Amazon have run repeated CPU-plus-memory bundles that price a 32GB kit well below its standalone cost, which ties each kit to a processor a reseller then has to move as well. On eBay, we found G.Skill's Trident Z5 Neo 32GB kit listed at $836.54 in December against a $429.99 retail price, roughly double, and about seven times the $117.99 it sold for before the shortage.

ChangXin Memory Technologies (CXMT), China's largest maker of dynamic random access memory (DRAM), planned to obtain Samsung's IP related to its memory process technologies in a bid to develop its own production nodes, according to testimony given in a South Korean criminal case involving leaked Samsung technology, reports Maeil Business. The company's managers allegedly had no intention to develop an in-house process technology from scratch, so obtaining IP from Samsung was a strategic decision.

The intention was a key part of CXMT's business plan rather than an opportunistic attempt to acquire Samsung's technology after the start of its own DRAM process development, according to the testimony of a former Samsung engineer identified as Jeon, who worked at Samsung for 28 years before jumping ship to CXMT sometimes around 2016. This April, Jeon was sentenced to seven years in prison for illegally obtaining a 600-step Process Recipe Plan (PRP) information concerning Samsung's DRAM fabrication processes in general and the 18nm-class node in particular.

"From the beginning, CXMT CEO and CTO tried to develop DRAM by stealing Samsung Electronics' Process Recipe Plan (PRP) information," Jeon told the court this week, according to Maeil Business. "CXMT had no research institutes or facilities at the time of its establishment, and had no intention of developing technology through its own research."

Copying the recipe does not automatically give you a working process. Nonetheless, a detailed process recipe can dramatically shorten development of any production node because it reveals things like the sequence of steps, deposition or etch conditions, anneals, cleans, implant parameters, temperatures, pressures, tool types, and so on. For a memory process, a ready process recipe can remove a huge amount of trial-and-error and reveal how the process integration is supposed to work. Meanwhile, even to ensure that the recipe works as intended, one needs to obtain the same or compatible tools as well as adjust their characteristics accordingly.

However, while a process recipe can potentially help to ramp any fabrication technology, a process recipe itself does not necessarily reveal the complete transistor architecture or physical design. For that, perpetrators also want things like cross-sectional structures, masks/layout information, design rules, device dimensions, capacitor geometry, process window, and so on. Such details are not easy to get for a brand-new fabrication technology, but they can be obtained by reverse engineering of shipping products. By combining process recipe with reverse engineering, experienced DRAM engineers can reconstruct much of the technology. Meanwhile, process integration engineers can save years of trial-and-error with actual fab tools.

Normally, it takes DRAM companies around 3 – 5 years to design a process node from device development to yield ramp. For a new player, development time from scratch will probably be around five years rather than three unless pre-competitive IP is licensed or certain heavy-lifting is done elsewhere. In fact, the Maeil Business report claims it took Samsung five years to develop its 18nm-class node.

Meanwhile, CXMT began mass production of DDR4 SDRAM in 2019 using a 22nm-class node. Mass production of memory using a 18nm-class process technology began in 2023. Such a timeline raises a question of whether CXMT's 22nm-class G1 was derived/adapted from the knowledge of Samsung's process technologies and/or their process recipes, the more advanced 18nm-class node, or did the allegedly obtained Samsung IP primarily help CXMT develop the later 18nm generation? In any case, there is a court ruling that CXMT stole IP from Samsung to boost its own memory production capability.

After posting record profits amid high memory prices, SK hynix ran into a dispute with employees over profit sharing and wage increases, which threatened to escalate into collective action by the company's union. This week, SK hynix management and the labor union reached a preliminary 2026 wage and collective bargaining agreement that significantly changes how the company's profit-sharing bonuses will be distributed, reports Maeil Business citing Yonhap. The good news is that no strikes are planned at the memory maker.

The tentative labor package reportedly calls for a 6.3% wage increase and an increase in welfare points provided by the company. In addition, under the proposed arrangement, employees will receive 40% of their performance-based profit distribution in cash, while the remaining 60% will come in the form of SK hynix shares. The proposal changes SK hynix's 2025 profit-sharing scheme, which allocated 10% of the previous year's operating profit to employee profit-sharing program, but the bonus was to be paid complete in cash: employees received 80% in cash immediately and remaining 20% over the next two years.

The union argued that stock-based bonuses expose employees to potential losses if SK hynix shares decline and could create tax complications, as income tax may be calculated using the share price when the stock is awarded. Specifically, the workers argued that performance bonuses normally paid in cash should not be converted into assets that carry investment risk. Yet, the SK hynix management and union have agreed to remove the 10% ceiling, potentially providing more money to employees, maintain the mechanism for 10 years, and pay the bonuses in cash and stock.

If SK hynix meets current market expectations and earns 25 trillion won ($17.897 billion) in operating profit this year, the profit-sharing pool would amount to 2.5 trillion won ($1.79 billion) based on the 10% formula. SK hynix reportedly has approximately 35,000 employees, so on average every employee will get 70 million won, or $50,120 ($20,048 in cash and $30,072 in stock). Yet, actual compensation will differ depending on an employee's position and individual performance assessment.

On August 4, before the fifth round of negotiations, an SK hynix union told members that if management did not present a revised proposal, it would be difficult to settle the dispute through negotiations alone and the union would have to take necessary action, which was obviously a way to threaten the management with a strike. Yet, the parties have come to terms.

The dispute comes as Samsung Electronics has faced similar labor action over compensations.

Pine64 has stopped producing Linux devices entirely, announcing this week on its official Telegram news channel that "there isn't [sic] any plans to continue producing more Linux devices in the near future" because of the ongoing DRAM and eMMC shortage. The stoppage covers the company's full lineup of Arm and RISC-V single-board computers, the PinePhone family, the PineTab2 tablet, and the PineNote e-reader, with remaining PineNote and PineTab2 stock estimated to last around three months.

Microcontroller-based products, such as the PineTime smartwatch, PineVoice smart speaker, and Pinecil soldering iron, won't be affected, and production will continue as usual. Development on the upcoming PineTime Pro will also continue: Pine64 said its demo firmware now has basic drivers for the display, touch, motion sensing, GPS, and audio, though some issues need fixing before a pilot batch enters production. The company also hasn't ended software support for existing Linux hardware.

The AI-driven memory crunch has raised prices on everything from DDR5 kits — which have sold on eBay for more than $2,000 — to prebuilt PCs from Dell, CyberPowerPC, and Maingear. Unfortunately, Pine64 buys the single worst-supplied part in the entire NAND market. TrendForce reported in April that the eMMC/UFS segment faces the tightest supply gap of any NAND category, because its production capacity overlaps with far higher-margin enterprise SSDs, making it the last in line for supplier allocation.

Phison CEO Khein-Seng Pua said in February that 8GB eMMC modules had risen from $1.50 to $20 in a year, a 13-fold increase, and warned the shortage could shut down entire consumer electronics companies in 2026. Pine64 hasn't shut down, but a whole product category has, and it's the first named vendor to kill a lineup outright instead of repricing it.

Other small-board makers have taken the opposite route. Raspberry Pi has raised prices repeatedly, pushing the Pi 5 16GB to $205 and the 500+ to $410, while launching a 3GB Pi 4 and leaning on a stockpile of older LPDDR2 to hold prices on legacy boards. Framework followed in January, raising its desktop pricing to cover LPDDR5x costs, which, since Strix Halo boards use soldered RAM, it couldn't pass to users any other way.

Pine64 sells its hardware near cost as a community service, so it has no margin to absorb higher component prices and, evidently, believes its buyers won't, either. Its mid-2027 checkpoint aligns with supply forecasts that don't expect new memory fab capacity to arrive in volume before late 2027 or 2028.

Pine64 said any decision on resuming production depends on component pricing after mid-2027, meaning its Linux hardware could be off the market for two years — or more.

What could possibly go wrong when you try to steal trade secrets from a restricted facility using a 360-degree action camera hidden in snacks? Forgetting to turn off the device’s Bluetooth and Wi-Fi transmitters, as it turns out.

A senior engineer at Nanya Technology has been indicted in Taiwan for allegedly copying 32 files containing information about the company's DRAM manufacturing process, reports Freedom Times. The engineer was reportedly in talks with Chinese recruitment agencies and allegedly planned to pass Nanya's trade secrets to its next employer in the People's Republic in exchange for higher compensation.

Yeh Yen-wei, a senior engineer in the Advanced Process Development Division at Nanya, joined the company in 2022 and began to communicate with Chinese recruiters in 2025 to explore employment opportunities in the People's Republic. Sometime in mid-February 2026, he submitted his resignation. However, before leaving the company in mid-April, on March 28, April 4, and April 5 — during weekends and either late at night or early in the morning — he visited the company's restricted office areas with his Insta360 X4 Air action camera hidden among snacks to get it past security checks.

Once inside, Yeh used his legitimate account credentials to access Nanya's virtual machines and opened various internal research and development documents. He then used the camera to capture photographs and video of information associated with Nanya's DRAM process technologies and production methods. It goes without saying that he retained the information when he officially resigned from Nanya in mid-April.

However, his actions did not go unnoticed. Nanya's IT security team detected 'abnormal' wireless signals inside the company's restricted facilities (i.e., identified the device using its Bluetooth and/or Wi-Fi signals) and tied them to the employee's access records and activity logs. Eventually, Nanya reported the suspected theft to Taiwanese authorities, which led to an indictment.

The New Taipei District Prosecutors Office charged Yeh under Taiwan's Trade Secrets Act with unauthorized reproduction of trade secrets intended for use in China, an offense for which he faces up to 10 years in prison, as well as with breach of trust under the Criminal Code. Meanwhile, forensic examination of the seized equipment uncovered no evidence that Yeh had successfully transmitted Nanya's confidential information to a Chinese company or anyone outside the company, so he could potentially get off easy.

Since late 2025, RAM, storage, and graphics card prices have shot through the roof, making items that were once affordable out of reach for many people. Anyone still in the market for those parts has to rely on combo deals for any reasonable pricing. Newegg has an excellent 3-item combo running where you essentially get the 16GB of DDR5 RAM for FREE with a huge $274 discount. For only $658.99, you get the powerful Ryzen 9 9900X processor, a quality Asus X870E-Plus Wi-Fi 7 motherboard, and 2x8GB Team Group DDR5-5200 RAM, along with a free Cooler Master 240mm AIO.

● Check out this deal at Newegg

The star of the combo has to be the ‘free’ RAM. The combo offers 16GB (2x8GB) of TeamGroup’s T-Force Vulkan DDR5-5200. And while the RAM speed is outside of AMD’s sweet spot, you’d be hard-pressed to notice a performance difference without looking at a frame counter. These black, non-RGB sticks will also look great with the included motherboard. If you apply the ~$274 discount to the RAM, you’re getting it for free. And if 16GB isn’t enough, buy the same kit again net 32GB for only $240.

Although we didn’t review AMD’s Ryzen 9 9900X, we know the non-X3D chips, like its big brother, the Ryzen 9 9950X, were generally well received by our reviewer and the public alike. Its strong multicore and single-threaded performance, native AVX-512 support, and backward compatibility with AM5 motherboards make this CPU an excellent choice for someone who uses their PC for more than just gaming and can make use of the additional cores and threads, as you can see from our benchmark data:

The Ryzen 9 9900X is a 12-core, 24-thread processor built on TSMC’s 4nm FinFET process (6nm for the I/O die) with a base clock of 4.4 GHz and boost up to 5.6 GHz. It has a TDP of 120W and is relatively easy to manage the thermals, even when overclocking the fully unlocked processor. While overclocking isn’t what it used to be, you can still squeeze out a couple of hundred more GHz, and sometimes you can get there, even when lowering the voltage. In short, there’s a lot of performance out of the box, and even a bit more headroom left if you want to overclock.

Last, the Asus TUF Gaming X870E-Plus Wifi 7 is a solid all-around motherboard for the AM5 platform. It delivers sufficient power to support flagship-class processors and easily handles the 9850X3D in the combo, even with some overclocking. It comes with four M.2 sockets (one PCIe 5.0) and two SATA ports for storage, fast networking with integrated Wi-Fi 7 and 2,5 GbE, ample USB ports on the rear IO (13, including two USB4 40 Gbps Type-C), and a quality audio solution based on the last-gen Realtek flagship (ALC1220P). Asus’ AI solutions (AI Cache Boost, Overclocking, Cooling II, and Networking II) and the DIY-friendly design make it easy to build and get the most out of your system.

If you’re in the market for an AM5-based system that isn’t based on an X3D chip, this $658.99 combo (an incredible $274 savings) is one of the better deals available at Newegg right now. And you even get a free 240mm Cooler Master AIO. Getting RAM for what essentially amounts to ‘free’ is not something we see frequently. You can even upgrade to 32GB and still find yourself well ahead versus buying alone. Get this deal while it lasts.

Yangtze Memory Technologies (YMTC) shipped 14% of the world's NAND flash in the second quarter of 2026, entering the global top three for the first time and narrowly displacing Kioxia, according to Counterpoint Research's Memory & Storage Tracker published today. Samsung led with 25%, SK hynix followed at 22%, and Micron rounded out the top five. The Chinese vendor's climb comes during a quarter when enterprise SSDs absorbed 48% of every NAND bit shipped worldwide, up from 26% a year earlier, and industry revenue grew fivefold year over year by Counterpoint's count.

In terms of revenue, however, YMTC sits fifth behind both Kioxia and Micron, with nearly all of its output going into consumer products. Consumer bits now sell for a fraction of what hyperscaler buyers pay for enterprise eSSDs holding KV caches and inference datasets. The company has been included on the U.S. Entity List since December 2022, which bars it from achieving Western server qualification, where the big bucks are earned, limiting its addressable market to the Chinese domestic channel plus whatever consumer demand the incumbents leave behind.

They're leaving behind plenty — Samsung's shipment share has dropped from 32% in Q2 2024 to 25% as it caps NAND output in favor of higher-margin DRAM, SK hynix subsidiary Solidigm grew bit shipments 40% quarter over quarter on server demand, and Kioxia's entire 2026 production is already sold out, largely to enterprise customers. Kioxia itself sends over 30% of its bits into servers, per Counterpoint, but its customers pulled back as prices climbed, and slower growth cost it the number three spot it held a quarter earlier.

With NAND contract prices up roughly 75% in Q2 alone, the vacuum in the consumer channel is a segment that YMTC is perfectly set up to serve. The company grew shipments 22% year over year and 5% sequentially while mass-producing 267-layer 3D NAND on its Xtacking architecture, with development underway on devices exceeding 300 layers. Meanwhile, its third Wuhan fab has cleared Beijing's 50% domestic-tooling threshold and is due to begin production late this year, with two follow-on fabs planned.

Counterpoint says that it expects eSSDs to pass half of all NAND bits by year-end, meaning the consumer pool YMTC dominates is shrinking as a share of the total market even as YMTC's slice of it grows. According to the firm, YMTC plans to shift its mix toward eSSDs in the second half, backed by what it called growing avenues for capital support. That shift depends on winning server customers it currently can't reach outside China, and holding a number-three spot earned on cheap bits will get harder if it can't.

Intel CEO Lip-Bu Tan has revealed that new memory architectures — once thought a commodity business — are now strategically interesting and one of his pet projects, while speaking about the comeback of the American chip industry. He further noted that the memory industry is ripe for innovation, and also hinted at exploring ways to stack memory on top of a CPU.

After years of being a commodity, memory became a strategic asset in recent quarters and will likely remain one for a while, so suddenly, leading makers of 3D NAND and DRAM became highly profitable companies, something the Intel CEO is keenly aware of:  "I used to be, 'do not invest in memory because it is a kind of commodity business,' but now it has become different," Tan said. […] "There is a lot of new technology coming out. So, we are kind of looking at one of my pet projects, some of the new memory architecture. I think you just saw the news: I hired my good friend, Seok-Hee Lee, who used to run SK Hynix. So, you kind of know something that I am thinking about. We are not ready to unfold it."

Tan did not reveal anything about the pet project and did not even specify whether the project is one of his personally favored strategic initiatives at Intel, or an initiative in one of the companies that he has invested in. He did mention that stacking memory on top of a CPU could make a lot of sense, though did not elaborate. Tan's remarks also follow the revelation of an Intel XBM patent that does away with the silicon interposer of HBM.

" I think CPU and memory, I think there are a lot of ways we can really do stacking together," Tan said. "And also try to find some new architecture for memory. I think in some way the memory, a lot of innovation are not there. So, there is some really good area."

Not everyone in the industry remembers, but Intel started as a memory company in 1968 and was quite a successful memory maker until the eighties, when Japanese companies took the lead, and Intel had to exit the market completely after suffering severe losses. Since then, the company has attempted either to return to the memory market with NAND and Optane, or at least to capitalize on a new type of memory with RDRAM. In all three cases, the company abandoned its memory initiatives without incurring significant losses.

Given the current profitability of 3D NAND and DRAM makers, producing memory is certainly a good business again and will remain profitable for some time. However, to re-enter it, companies like Intel would need capital to build at least one fab, R&D to develop competitive process technologies, and time. While licensing a technology — assuming that a company has capital — is an option, we strongly doubt that at this point Intel may be inclined to invest capital in memory and not in its core products and foundry businesses. Furthermore, it is unclear how investors react to such investments given the fact that the company struggles to become a strong competitor in the foundry market and has exited 3D NAND and 3DXPoint/Optane businesses after failing to achieve strategic targets.

Apple reportedly has around $1 billion in "processor wafers on the shelves awaiting packaging" amid ongoing memory shortages, putting pressure on the firm as it nears the launch of the iPhone 18. Tim Culpan of Culpium says Apple is "scrambling" for memory supply ahead of release, working with suppliers to get memory ready so it can finish packaging the A20 Pro and C2 chips that are reportedly inside the iPhone 18 lineup.

It's an interesting peek behind the curtain of the current supply chain limitations, which reach beyond simply DRAM chips. With fully-integrated SoCs across both desktop and mobile, Apple is uniquely vulnerable to supply chain limitations, not only in DRAM supply, but also in packaging capacity to bring together DRAM chips with processor wafers.

According to Culpan, Apple primarily sources DRAM from Micron, with smaller engagements from SK Hynix and Samsung. Micron (along with the other major memory players) has reportedly sold capacity for DRAM and HBM through 2027. A flurry of long-term agreements (LTAs) have cropped up over the past several months, guaranteeing supply to certain companies for several years.

The A20 Pro is the first chip to use TSMC's N2 process, and it has been progressing well, with TSMC reportedly sitting on around $1 billion worth of Apple wafers awaiting packaging with DRAM. Packaging happens with TSMC's new Wafer-Level Multi-Chip Module (WMCM) process, according to Culpan, which is similar to the CoWoS packaging but for mobile parts.

Culpan reports that "Apple and its assemblers remain confident that they can meet initial demand," but DRAM shortages could put pressure on shipments past the initial launch. Apple reportedly plans to ship around 200 million iPhone 18 units across the lineup throughout the device's lifespan. The iPhone 17 range saw record shipments last year, surpassing 245 million devices shipped in 2025.

Apple is one of several companies reportedly looking to alternative suppliers for DRAM, namely China's CXMT. The Chinese memory supplier has become a hot topic in the halls of the U.S. government over the past several weeks, with Apple reportedly lobbying for clearance as the government weighs the option to ban CXMT.

This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.

Here's a breakdown of each type of technology that the company announced.

• zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
• zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
• BV-NAND (aka Samsung’s 10^th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).

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zHBM: Placing HBM stack on top of logic

Around the time we first heard about HBM4's 2,048-bit interface, we read a 'semi-official' report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung's zHBM appears to be a continuation of that effort.

Samsung's zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the 'performance of HBM5', while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.

While Samsung's claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a 'next-generation interface system incorporating zHBM' will deliver 'approximately eight times the performance of HBM5,' it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as '8x higher bandwidth.'

Instead, the general term 'performance' may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn't reveal which die stacking/bonding technology it will use for zHBM.

In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.

For now, Samsung hasn't disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.

zNAND-O(on-device): Put storage close to compute

Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company's V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.

Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.

Since the technology is in development, Samsung hasn't shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions 'improved I/O performance and low-latency,' it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.

BV-NAND: Good old V-NAND gets a new treatment

With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.

Samsung formally announced its 400-layer-class V-NAND (aka 10^th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm² with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung's 10^th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk's BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.

Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.

Samsung's new brand strategy

As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.

Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company's new tech, like zHBM and zNAND-O, is years away.

Following its massive $8.6 billion initial public offering (IPO) in July, ChangXin Memory Technologies (CXMT) began considering building its sixth DRAM fab in China to boost memory output in the coming years, Reuters reports. If all announced projects proceed as planned, the company's production capacity could more than double in the mid-term future, the report claims. Meanwhile, investment banker Dan Niles believes China could capture 30% of the DRAM market by 2030, according to P Equity Research.

Growing at a rapid pace

CXMT currently operates three 300-mm DRAM fabs: two near Hefei and one in Beijing's Yizhuang district. Unofficial reports claim that each fab is capable of processing around 100,000 wafers per month, so the company's output may be around 300,000 wafer starts per month (WSPM).

The company is pursuing an aggressive expansion strategy and is currently building additional fabs near Shanghai and Hefei, according to Reuters. The company's sixth fab will reportedly be located in Beijing's Yizhuang area, adjacent to its existing facility. Once these projects are fully operational, the company’s total manufacturing capacity could exceed 600,000 WSPM, which will double its current output, according to Reuters. Meanwhile, researchers from Citrini believe that CXMT could exit 2026 with a capacity of 350,000 WSPM, which is just 25,000 WSPM shy of what Micron targets by the end of the year. Citrini Research models that by 2030, CXMT will have production capacity of around 950,000 WSPM.

Building three big DRAM fabs is a big deal, from both financial and execution points of view. However, it is not a secret that virtually all fabs owned by Chinese companies are built using money from local and federal governments under the 'Hefei model,' which aims to transform cities into economic juggernauts by leveraging high-risk projects. So it is not surprising that both Shanghai and Beijing have provided financial assistance and other forms of support to attract CXMT to their regions, according to Reuters.

CXMT's existing Beijing fab, operated by Changxin Jidian, received backing from E-Town Capital and Beijing E-Town Technology, both affiliated with the Yizhuang development zone, according to a person familiar with the matter cited by Reuters. In fact, the district has evolved into a relatively major semiconductor manufacturing hub that already hosts CXMT, SMIC, Naura Technology, and Xiaomi, the report claims.

The right timing

The proposed fab would be located in Beijing's Yizhuang district, roughly 20 kilometers southeast of the city center, where CXMT already operates a 300-mm DRAM manufacturing facility. The planned production capacity and total capital investment for the project have not yet been disclosed, although Reuters points out that a leading-edge DRAM fab typically costs well over $10 billion.

Sources cited within the report said the company is seeking at least 60 million yuan ($8.9 million) in financial support from the Beijing Economic-Technological Development Area, and additional state-owned technology companies have also expressed interest in participating. Discussions remain preliminary, and neither the overall size nor the structure of the financing package has been finalized.

From CXMT's point of view, this is the right time for financial influxes as the company can sell all of its DRAM output at good prices to a variety of customers. Those being domestic PC and server makers (including Lenovo), and global brands such as Micron, Samsung, and SK hynix, which prioritize shipments of their DRAM output to the AI sector.

Apple, Dell, and HP have all reportedly qualified CXMT's memory and are ready to deploy it in their devices sold in China, while Acer and Asus have already begun to use DRAM from the Chinese maker. If CXMT signs long-term supply contracts with the world's leading PC makers, it is nearly guaranteed to sell out its output to these vendors in the coming years, which justifies investments in its expansion.

30% of DRAM market by 2030?

Dan Niles, founder of Niles Investment Management, believes that many investors underestimate how much share CXMT could capture over the coming years and how much share China may seize in the coming years.

His argument stems from historical DRAM market leadership shifts. In 1975, U.S. companies controlled 95% of the DRAM market, with Intel alone holding 75%. Japan then turned DRAM into a commodity business, increased its share to 80% by 1985, while the U.S. fell to 10% and then just 2% by 1990. Then South Korea repeated that playbook in the mid-1980s and eventually displaced Japanese suppliers, and today it accounts for roughly 62% of the global DRAM production.

With Micron's investments of hundreds of billions of dollars in U.S. DRAM capacity, the country is set to regain its massive presence on the global DRAM scene; China could capture 30% of the market by 2030, according to Niles.

China already consumes around 30% of global memory output, as it produces hundreds of millions of PCs and smartphones both for domestic and global consumption; it is reasonable to expect the country to produce as much commodity memory locally as possible. Keeping in mind China's push for semiconductor self-sufficiency and willingness to invest huge amounts of money in domestic fabs, it is possible to expect the country to rapidly gain DRAM output and share. China is already pushing its chipmakers hard to start DRAM production, and the government reportedly asked CXMT to share its process technologies with others.

Not that easy

There are multiple factors — both technological and political — that may, if not stop, but greatly slow down CXMT's and China's DRAM expansions in the coming years.

First up, there are export controls in place that prevent Chinese entities from getting sophisticated wafer fab equipment required to make DRAM using 18nm-class process technology or more advanced. If the proposed MATCH Act passes, then limitations on Chinese companies will get more severe, which will reduce their expansion ability.

Secondly, even if CXMT (or another Chinese DRAM maker) finds a way to produce more advanced DRAM using relatively outdated tools (i.e., use old tools for sub-16nm nodes), they will need to acquire those tools in quantity to increase their output. Meanwhile, companies like ASML have relatively limited production capacities, and CXMT is certainly not the only memory maker seeking to expand its production capacity in the coming years. While SMEE and SiCarrier are developing lithography tools in China, they will be unlikely to ramp up production of immersion DUV scanners to higher levels any time soon.

Thirdly, building fabs is one thing; operating leading-edge DRAM production at high yields is another. China has recruited engineers from Micron, Samsung, SK hynix, and TSMC for years, but scaling from three to six or more fabs requires thousands of experienced process, yield, device, lithography, and integration engineers. Building fabs adjacent to existing sites enables CXMT and other chipmakers to share experience and knowledge internally, which helps to develop experienced talent. But will it be enough for the long term?

Next, expanding wafer capacity alone is insufficient. DRAM producers must continuously migrate to finer process technologies (e.g., 16nm-class, 14nm-class, 12nm-class) to remain cost-competitive. If export controls delay access to equipment or materials needed for these nodes, Chinese fabs could end up producing more wafers at a higher cost per bit than competitors.

Finally, some American lawmakers want to prohibit U.S.-based companies from acquiring memory from CXMT and other Chinese vendors. They have every reason to believe that China wants to take control of a sizeable DRAM market share in a bid to use it in its strategic interest and have leverage over the market, something the country already has with rare earth metals. If the lawmakers manage to turn the proposal into law, demand for CXMT's and other China-made DRAM will drop. It will probably be sufficient inside China, but whether it will be enough to justify 10 or more big DRAM fabs is a different question.

Pushback against Micron's planned manufacturing complex in Clay, New York, which comprises four separate fabs, is once again at the center of an environmental lawsuit. Filed by Neighbors for a Better Micron and Jobs to Move America — the same groups that filed a separate lawsuit against Micron in January — filed a new complaint Friday, claiming that approved wastewater and air permits aren't valid and will allow Micron to leak "forever chemicals" into the Oneida River.

"The Permits were issued against eh backdrop of the significant environmental consequences already acknowledged through the course of the Micro Project's State Environmental Quality Review Act (SEQRA) review. including the release of PFAS and other highly persistent and hazardous chemicals," the complaint reads. "Rather than fully and meaningfully evaluate and address those consequences and impose the necessary protections before granting final authorization, [the Department of Environmental Conservation] issued permits that defer essential analyses, controls and limitations, and mitigation decisions until after issuance or until future regulations and studies have been conducted."

The lawsuit names the New York State Department of Environmental Conservation (DEC), Onondaga County (where Clay is located), and Micron. Its claim is that, despite Micron receiving wastewater and air permits from the DEC, those permits aren't adequate to regulate the plant's emissions. In one part of the lawsuit, the petitioners claim the permits are "not routine operating approvals," and in another, claim the loose permit guidelines "are not collateral or technical omissions."

Per- and polyfluoroalkyl substances, otherwise known as PFAS or "forever chemicals," are synthetic chemicals that are essential to semiconductor manufacturing. The chemicals are present throughout nearly the entirety of the manufacturing chain, necessitating strict water and air containment management to align with environmental regulations. "The SPDES permit authorizes the acceptance and discharge of Micron's industrial wastewater containing identified emerging contaminants, including PFAS compounds, but it imposes no substantive controls on those harmful contaminants beyond monitoring their presence and concentration."

In January, the two petitioners named in this complaint filed another lawsuit against Micron, claiming that the project failed to comply with the state's environmental review process. Last month, Micron asked a judge to dismiss the lawsuit. It's still set for oral arguments on August 25, however.

This lawsuit currently doesn't have a date set for oral arguments, if it ever reaches that point. The petitioners are seeking the nullification of both wastewater and air permits, which would force Micron back under the environmental review process, and costs associated with the suit.

Storage and memory manufacturer Lexar has listed a new 32GB (2x16GB) DDR5-7200 CL38 memory kit in China with a price tag of 3,999 yuan (roughly $592). Part of the second-generation Thor RGB series, the kit features a sandblasted aluminum heat spreader, thermal pads, and eight LEDs that support a variety of RGB lighting effects. It is rated for 38-48-48-86 timings at 1.40V and supports both Intel XMP 3.0 and AMD EXPO profiles.

Lexar says the modules use carefully selected domestically produced DRAM, although it does not specify the actual manufacturer. While there is no confirmation, the company may be using DRAM chips made by CXMT (ChangXin Memory Technologies). Lexar has also published a compatibility list covering 43 motherboards, including 30 Asus models and 13 MSI models across Intel Z890, Intel B860, and AMD B850 platforms. The compatibility list also includes supported boards for a faster 32GB (2x16GB) DDR5-7600 CL38 memory kit.

Interestingly, none of AMD's X870 or previous-generation motherboards appear on the list. That said, the kit should work on most DDR5 boards that Lexar hasn't tested, but the absence of AMD's flagship consumer chipset from the compatibility list is a bit odd. Notably, major motherboard manufacturers, including MSI and Gigabyte, have already started optimizing their motherboards to support CXMT memory ICs.

A few months ago, Corsair began adopting CXMT DDR5 chips in select memory kits, including its popular Vengeance lineup. Likewise, major PC manufacturers such as HP and Dell have started qualifying CXMT DRAM, while Acer and Asus have reportedly asked their Chinese manufacturing partners to source locally made memory chips.

The arrival of CXMT-made DDR5 chips earlier this year raised hopes that a new DRAM supplier could ease supply constraints and eventually lower memory prices. So far, there seems to be little evidence of that happening. At around $592, Lexar's new DDR5-7200 kit is priced in line or only slightly below many comparable 32GB DDR5-7200 kits currently available in the U.S. Similar kits from brands such as G.Skill, Corsair, and Kingston are currently selling anywhere from $585 to $700.

There’s been a shift toward using a single DIMM of DDR5 to skirt the worst of the RAM pricing crisis. AMD has suggested to us previously, at least, that it’s an option PC builders are exploring, and it’s a wrinkle that’s shown up in dozens of prebuilts; one that we’ve been careful to avoid when recommending products, particularly during peak shopping events. But just how much gaming performance are you giving up with a single DIMM when using one of the best CPUs for gaming?

The conventional wisdom is that you’re giving up quite a bit of performance, resting on the ideas of previous DDR generations, where going down a single stick will cut your bandwidth in half. The same is true with DDR5, but things are a bit messier, which we’ll dig into later.

At a high level, using a single DDR5 DIMM doesn’t compromise gaming performance by nearly as much as you might expect. We saw drops of around 8% to 10% across Intel and AMD CPUs, and less than a 5% difference with AMD’s Ryzen 7 9800X3D.

A proper dual-channel configuration is still the way to go for optimal performance. However, our testing shows that even a single DDR5 DIMM offers superior performance to dual-channel DDR4 on CPUs that support both memory generations.

Using a single DIMM isn’t ideal, and it brings up compatibility issues if you plan on adding another DIMM down the line (another area we’ll touch more on in-depth later). But as a stopgap measure amid surging DRAM prices, a single DIMM of DDR5 holds up surprisingly well in gaming scenarios, and it represents a nice on-ramp into a DDR5 platform while prices are out of control.

Testing single-DIMM DDR5 in games

The geomean below speaks for itself. Moving down to a single DIMM drops some performance, but it’s not nearly as stark as I expected. There are some important notes about how we tested before dissecting the results, however.

As usual, we tested at 1080p with a mixture of High and Ultra settings, using Nvidia’s RTX 5090 Founder’s Edition to minimize the influence of the GPU. That’s even more important here, as we’re not evaluating CPUs but the memory that feeds the CPU. We're looking at a separate GPU and CPU here, as well; dual-channel memory is vital if you're using an iGPU.

We also wanted to create a realistic testing scenario. Assuming you’re going for a 2x16GB configuration, that means starting with a single 16GB DIMM, not a 32GB one. That’s what we did here. Our single-DIMM configurations run with just 16GB of memory, while dual-DIMM configurations run with 32GB. Capacity isn’t a major limitation for our testing here, though it will pose performance issues if you’re running several applications alongside your game.

The Ryzen 5 7600X was our biggest loser, dropping 10.9% of its average performance across our 13-game geomean with a single 16GB DIMM. The Core Ultra 7 270K Plus, meanwhile, dropped 8.7% of its average performance, while the Core i5-14600K similarly dropped 8.3% of its performance. The 1% lows are especially notable here, scaling with average performance rather than falling off a cliff.

Unsurprisingly, the Ryzen 7 9800X3D fared the best, dropping just 2.8% of its performance on average. As you’ll see through our individual game tests, the Ryzen 7 9800X3D shows identical performance with two DIMMs and a single DIMM in multiple games. The large and speedy L3 minimizes the impact of using a single DIMM, giving AMD’s 3D V-Cache CPUs another notch in their belt (as if they needed another).

Our other geomeans don’t say much. A single-DIMM configuration consumes a few watts less, leading to slightly lower efficiency when balanced against the lowered performance.

007 First Light, the newest game in our test suite, shows good scaling across our test pool, so it’s a good place to start. The Core Ultra 7 270K Plus dropped 8.9% of its performance with a single DIMM, while the 9800X3D dropped 6.5%. The 14600K is worth highlighting here. A single DIMM lost us 7.9%, but that’s still better than dual-channel DDR4, and by a decent 6.8% margin.

This trend is fairly consistent, too. Starfield is punishing for single-DIMM configurations, with the 14600K losing 10.6% of its average performance. Even then, a single DDR5 DIMM is 6.9% faster than dual-channel DDR4. Intel platforms can scale up to high data rates, and we use 7,200 MT/s for Intel chips. With slower speeds, the performance will equalize. Still, I’d strongly consider a single DDR5 DIMM if you’ve been eyeing an LGA 1700 platform with DDR4, assuming you’re primarily focused on gaming.

Starfield shows the benefits of 3D V-Cache in this single-DIMM configuration clearly. While the performance losses with other CPUs are brutal in this title, the 9800X3D dropped just a few frames, a 1.6% decrease in average performance.

Doom: The Dark Ages is similarly harsh on single-DIMM configurations. The Ryzen 5 7600X dropped 17.3% of its average performance, and the 270K Plus fell by 14%. The 9800X3D holds up well, however, with just a 4.2% average performance loss. Marvel’s Spider-Man 2 (in the gallery below) shows a similar dynamic.

However, the addition of 3D V-Cache mainly helps in these games where we see bigger losses with other CPUs. There are several games in our suite where the performance loss between a single DIMM and dual-channel configuration was minor, particularly in GPU-heavy titles. The Last of Us Part One shows that in action.

Similarly, the performance loss is minor in Counter-Strike 2, just a handful of frames even north of 600 FPS. Even the Core i5-14600K, which was hit the hardest by far, dropped just 5.9% of its average performance (and it’s still faster than a dual-channel DDR4 configuration).

You can browse the results of the other games we tested in the gallery above, though they tell much the same story as the titles we highlighted. The two biggest learnings from this testing are that a single, fast DDR5 DIMM often outpaces dual-channel DDR4, and that AMD’s 3D V-Cache can smooth over the rough edges of using a single DIMM, particularly in those memory-sensitive titles.

How we tested

We tested on our normal test bed that we use for CPU reviews, with the only difference being dropping one of our DIMMs. As usual, we enabled XMP/EXPO for testing, both on single- and dual-DIMM configurations, opting for higher speeds on Intel platforms. AMD’s sweet spot is around 6,000 MT/s.

The data rate is noteworthy for the DDR4 comparison, in particular. With slower DDR5, we expect the delta between dual-channel DDR4 and single-DIMM DDR5 to decrease.

In addition to enabling XMP/EXPO, we disable Virtualization-Based Security (VBS), enable Resizeable BAR, and disable any automatic overclocking features that aren’t covered by warranty, including AMD’s Precision Boost Overdrive and Intel’s Extreme performance profile.

Complexities of DDR5

DDR5 has much higher data rates compared to DDR4 (2x or more), and that’s the result of significantly more complexity on DDR5 DIMMs compared to DDR4. Notably for this testing are the two 32-bit subchannels of DDR5, as well as enlarged prefetch and bank groups. You are getting half the total bandwidth with a single DDR5 DIMM, absolutely, but it’s a little more nuanced than simply running your memory in a single-channel configuration.

DDR4 uses a single 72-bit channel, and 64 of those bits transfer data (the additional 8 are for ECC). With DDR5, you get two 40-bit subchannels, 32 of which are used for data transfer. Critically, these subchannels have their own Command/Address (CA) interface, allowing them to operate independently of each other.

In addition, DDR5 doubles the prefetch size to 16N, doubles the number of banks and bank groups, and increases burst length from 8 bytes to 16 bytes. The math here is straightforward enough. With DDR4, you can transfer 64 bits of data over the interface at a burst of 8 bytes, giving you 64 bytes of data and aligning with cache line sizes. Each of the subchannels in DDR5 can transfer 64 bytes of data, as well, with a 32-bit width and burst length of 16 bytes.

It’s pseudo-dual-channel memory on a single DIMM. There are two independent memory operations that can happen each cycle, both of which transfer 64 bytes of data. That is a big reason why even a single DDR5 DIMM (particularly one with a higher data rate) can outpace even a proper dual-channel DDR4 configuration.

The common wisdom about using a single DIMM comes mainly from previous DDR generations, where you can only get that single 64-byte transfer each cycle, necessitating a second DIMM to have two independent operations.

Let me be clear: two DDR5 DIMMs are still better. Instead of two operations per cycle, you can perform four. The main difference is that, for modern CPUs and games, just those two operations give you the vast majority of your performance, and you don’t run into a massive performance bottleneck as you do with just a single operation via DDR4. After all, there are still a lot of DDR4 systems out there.

On the issue of compatibility

The elephant in the room with upgrading to a DDR5 platform with a single DIMM is compatibility. If you get a single DDR5 DIMM now, you should plan to add another in the future. Unfortunately, there aren’t a lot of easy answers when it comes to combining two DIMMs that aren’t in a kit together. It should work, but mixing and matching can lead to stability issues and/or lowered performance.

Generally, combining two DIMMs of the same spec should work. For instance, if you bought this Patriot Viper Venom DDR5-6000 CL30 DIMM to start your new build, and then bought a second one later, it should work. “Should” carries a lot of weight on its shoulders, however. Maybe Patriot sources DRAM from multiple places, or your second DIMM’s timings don’t completely align with your first. That could cause stability or performance issues.

There have been some attempts to get past this hurdle, such as the ROG Certified program with select Asus motherboards, but it’s impossible to know for sure if two separate DIMMs will work together or not without testing. The best you can do is to make sure you buy the same brand of memory, with the same spec, if you add a second DIMM. Make sure to keep your receipt handy in the event you need to return it, as well.

Once you have your second DIMM, make sure to test it first at stock JEDEC speeds/timings (no XMP/EXPO). Run games or applications you normally run, and then use a utility like MemTest64 to check for stability. I’d recommend keeping your PC running in this state for a few days to see if any BSODs, application crashes, or poor performance issues pop up. After that’s done, repeat the process with XMP/EXPO enabled, assuming you’re using matching DIMMs (incompatible XMP/EXPO profiles won’t work together).

Assuming DRAM prices continue at an elevated rate before you upgrade, you may want to consider investing in a dual-channel kit down the line and selling your single DIMM. Even kits can run into compatibility issues, though the likelihood is far, far lower.

Memory supply from major DRAM manufacturers to independent module makers could drop to just 30% of the amount supplied in 2026 next year, according to C.K. Chang, CEO of Taiwanese memory vendor Apacer, further tightening an already squeezed supply chain.

Chang made the comments during the company's 1H 2026 investor conference on July 24, and in subsequent media interviews after the conference. Although memory price increases are expected to slow during the second half of 2026 — reportedly due to consumers deciding that RAM is too expensive — he believes severe shortages will persist into at least the middle of 2027, and that DRAM will remain the most constrained segment.

According to Chang, the greatest risk facing Apacer, which buys memory wafers from manufacturers such as SK Hynix and Samsung and turns them into finished memory products, is no longer overpaying for the chips, but failing to obtain any supply at all.

In preparation for growing shortages and to prevent a wider shortfall next year, the company says it grew its inventory to NT$12.4 billion ($383.2 million USD) at the end of June, up from NT$8.38 billion ($259 million USD) one quarter earlier, representing an increase of approximately 48%. The company is also arranging a five-year syndicated loan of up to NT$4 billion ($123.6 million USD) to purchase additional chips whenever manufacturers make them available, among other needs.

Chang’s projection does not mean worldwide DRAM production will fall by more than 70%. His statement specifically refers to the volume major chip manufacturers may allocate to downstream module companies such as Apacer, which purchases memory chips and packages them into DIMMs, SSDs and embedded storage products. DRAM manufacturers are increasingly reserving their output for high-bandwidth memory (HBM), server memory, and other products purchased directly by large AI and cloud customers.

Samsung, SK Hynix and Micron — the world's biggest memory chip makers — are prioritizing higher-margin HBM and advanced server memory as AI infrastructure spending consumes an increasing share of available manufacturing capacity. Chang estimates that approximately 60% of DRAM capacity is now directed toward server-related applications, leaving conventional DDR4 and DDR5 products competing for a shrinking portion of the market.

DDR5 RDIMM server modules have received some of the most aggressive price increases and retain the greatest potential for future mark-ups, according to Chang. Demand from AI servers, enterprise storage, industrial computers and edge AI systems remains strong, while consumer PC and smartphone demand is considerably weaker and more sensitive to rising component costs. That weaker demand is, of course, mostly in comparison to the AI industry. Consumer demand remains strong enough to mop up the shrinking supply. The RAM shortage is now reportedly affecting the price of cars, far beyond consumer electronics.

NAND flash is also being pulled into the AI boom. High-capacity enterprise SSDs are increasingly being used for model storage, data staging and key-value cache offloading, allowing colder portions of AI workloads to spill out of expensive DRAM. Flash cannot replace DRAM outright because it offers considerably lower bandwidth, but it can still serve as a tier within AI memory systems, increasing demand for enterprise SSDs and NAND alongside server memory.

Chang expects DRAM contract prices to rise by approximately 30% during the third quarter of 2026 and NAND flash to increase by more than 20%. He expects price growth to moderate again during the fourth quarter.

Elsewhere, analysts project a 40% increase in DRAM prices in Q3 2026, even as demand extends to the oldest standards still in production. Samsung and SK Hynix, both South Korean companies — who together with US-based Micron Technologies control over 90% of the global DRAM market — had earlier warned that shortages could last beyond 2027. And the CEO of Adata projects that the global DRAM shortage will run for another 10 years.

Chinese manufacturers are not expected to provide immediate relief. Chang said Chinese memory maker CXMT’s DDR5 products had become competitive and that both CXMT and Chinese NAND producer YMTC had narrowed their pricing gaps with established international suppliers. However, domestic demand in China already exceeds available supply, while capacity expansion, manufacturing yields, product validation and platform compatibility continue to limit their ability to change the global balance. Furthermore, the prices of new DRAM modules from CXMT are reportedly similar to those of the big three.

Stockpiling memory inventory at historically high prices carries the risk of substantial losses if the market suddenly reverses. Apacer, however, says it has seen no evidence of an approaching collapse. For now, the company is betting that possessing expensive memory in 2027 will be considerably better than having no memory to sell at all.

Unless you already have a kit of DDR5, or deep pockets for PC hardware, you’re stuck right now. Despite seeing some of the best CPUs for gaming released just in the past year, the DDR5 tax represents a major hurdle to building or upgrading your PC. Intel’s LGA 1700 CPUs hold an unintended solution, offering support for both DDR4 and DDR5. We wanted to see if this on-ramp to a next-gen platform was really as smooth as it looks at first glance.

The idea is simple. If you already have a DDR4 kit, you can upgrade to a relatively new CPU while keeping the door open for a transition to DDR5 without buying a new chip. It’s inexpensive, and a bit more of a practical solution than upgrading to DDR5 with a single DIMM and worrying about pairing it with another later.

Our testing shows how much of a performance difference there is with DDR4 in games. We’re focused on games here for a few reasons. First, in non-gaming applications, memory speed is highly dependent on the specific workload you’re running. Games, despite using different engines, are largely similar workloads that stress the hardware in similar ways. Further, those workloads are continually evolving as new games, new technologies, and new hardware targets are released.

We kept our testing focused on Intel’s LGA 1700 CPUs because they’re the only options that give us a true apples-to-apples comparison between DDR4 and DDR5. We don’t have any AMD CPUs in our test pool because there aren’t any chips that support both DDR4 and DDR5. This isn’t intended to be a competitive analysis between AMD and Intel. That conversation opens up a much broader conversation about total platform cost.

Testing DDR4 vs. DDR5 on Intel’s LGA 1700 CPUs

To test DDR4 and DDR5’s gaming performance, we ran Intel’s main LGA 1700 stack through a 15-game gauntlet of benchmarks. Notably, we don’t have results for the Core i9-12900K, as our sample has a janky memory controller that won’t boot on DDR5 systems. You can read a full breakdown of how (and why) we tested in the way we did in the section below.

We ran all of the games through our 16-game benchmark suite, though we cut Doom: The Dark Ages from the results here. An update for the game rolled out mid-way through testing and skewed our results, so we’re omitting it. The 15 remaining games still paint a clear picture of the performance difference between DDR4 and DDR5.

As usual, we tested with the RTX 5090 Founder’s Edition at 1080p with a mixture of High and Ultra settings. We test at 1080p to maximize the differences between CPUs, and it remains the most widely-used resolution for gaming. Deltas between CPUs will decrease as the resolution climbs and the GPU becomes a larger influence in performance.

Below is our geomean from testing across the suite. Given that we’re looking to compare a single CPU’s performance with DDR4 and DDR5, we’ve highlighted some CPUs with the same color (13700K is always dark red, for instance, while 14700K is always dark blue).

The chart above is a bit difficult to parse, mainly because we’re often jumping several entries to get to a comparison point. For the stack of chips we tested, here’s a clearer overview of the performance difference with DDR4:

As we’ll get into with the individual game tests below, the drop in performance between DDR4 and DDR5 can be much larger than the comparison in our geomean (and, in turn, smaller in other games). What’s important for the overall performance drop is the trend as we move to newer chips. You can see a 9% drop grow to 14%, as DDR4 becomes a more significant bottleneck when the processor it’s feeding becomes more powerful.

That trend is one of the main driving forces behind our look at DDR4 and DDR5 gaming performance today. We looked at DDR4 and DDR5 performance extensively near the Alder Lake launch, and even more recently last year, evaluating performance across a wide range of applications. The testing here is focused solely on gaming to answer a critical question of building a PC today: Are you really giving up that much gaming performance with DDR4?

The answer is, yes, you’re giving up around 11% to 14% of your gaming performance overall when the memory is the only variable that changes. That’s a consistent drop, as well. Older titles care see less of a benefit from DDR5 generally, but we saw a steady decrease of around 11-14% across the games we tested, with some titles pushing above a 20% drop.

007 First Light is the newest game we tested, and it outpaces our averages. The 14900K sees a 16.5% drop with DDR4, while the 13600K drops 12.7% of its performance. Especially among the most powerful CPUs here, you can see DDR4 level off performance in a way that’s undesirable. The 14900K, for instance, is just 1.7% faster than the 13900K with DDR4, but it’s 4.6% faster with DDR5.

Similarly, in Crimson Desert, you can see the 13700K lose 13.7% of its performance with DDR4, and the 14600K drop 13.2% of its performance. It’s worth noting that neither of these games are particularly sensitive to memory speed. You can see in our recent Ryzen 7 5800X3D re-review that even a boost from 3D V-Cache doesn’t give CPUs with a robust memory chain an automatic advantage.

Perhaps the most consequential of the newer games we tested is Marvel Rivals, not only because it shows a much larger gap between DDR4 and DDR5, but also because it’s the most-played game in our test suite by a long shot (short of Counter-Strike 2). For weaker chips like the 12600K, the gap is 13.9%, just slightly above our geomean. For the more powerful 14700K, however, it shows a gap of 25.3%. Even the 14600K drops 17.4% of its performance with DDR4.

Counter-Strike 2 is less extreme, perhaps as a consequence of having such a high floor for average frame rates. You can see that the Alder Lake chips don’t care much about DDR4, with the Core i7-12700K performing identically across both memory standards. That gap grows with more powerful CPUs, however, with the 14700K creeping up toward a 10% delta.

In Spider-Man 2, we can see more consistent drops across the stack of chips we tested, with most CPUs dropping around 18% of their average performance with DDR4. That’s true even on the weaker 12700K, which lost 15% of its performance. The 14900K, meanwhile, was 18.7% slower with DDR4.

Even in an older, GPU-heavy title like Cyberpunk 2077, we can see a consistent drop. You can see in this game that we become completely bound by the GPU at the top of the rankings, but that’s a level these chips can’t hit when paired with DDR4. The 14700K drops about 14% of its performance, and the 13600K, about 13% of its performance.

You can browse through our remaining benchmarks using the gallery above, but most games tell a similar story. The gap between DDR4 and DDR5 persists, of course, but there’s another angle to look at the data. DDR4 flattens off performance, creating a bottleneck with faster CPUs. That could be justification for buying a weaker chip if you can only afford DDR4 memory right now.

Outside of performance, one important aspect of using a DDR4 system compared to DDR5 is power consumption. With DDR4, power consumption of the CPU increases, as you can see in the chart above. The jump is generally only a few watts, but it’s worth noting nonetheless. In games, we’re well below the operating temperature of all the chips in our test pool, but when pushing toward maximum power draw, DDR4 will post yet another limitation.

How (and why) we tested DDR4 vs. DDR5 now

DDR5 is way too expensive, and Intel’s LGA 1700 CPUs represent a unique value proposition given the unprecedented increases in memory prices over the past several months. The idea is that you can upgrade to a newer platform while sticking with DDR4, giving you a stopgap for an eventual DDR5 upgrade. It seems Intel recognizes this value proposition, as well, as it’s reportedly slated to launch Raptor Lake Next CPUs on the LGA 1700 socket.

We tested the main stack of chips, short of the Core i9-12900K, as described above. We didn’t test variants like KS releases to keep our testing focused, as well as lower-end SKUs like the 12100F or 14400. The memory controllers in these lower-end chips are weaker, sustaining lower DDR5 speeds, so expect less of a difference in performance with them.

Below, you can see the test benches we used. In addition to keeping hardware consistent, we use a frozen OS image with an identical software stack. We’re running the same version of the same apps on the same OS update, with identical drivers.

In the BIOS, we enabled XMP for both kits of memory. We also tested with Resizeable BAR turned on, and Virtualization-Based Security (VBS) turned off. Most motherboard vendors off a profile with the power limits removed on Intel CPUs, which can push the processor outside of warrantied specifications. We stuck with the default “Performance” profile for our testing here.

Is DDR4 still worth it?

It makes sense that we’ve seen a shift back toward DDR4. Although DDR4 prices have risen in lockstep with DDR5 prices, they started from a much lower base. A kit of DDR4 today is not much more expensive than a DDR5 kit of similar capacity a year ago. And, with estimates that the memory shortage could persist through 2030, there’s a strong argument for going with a DDR4 system if you’re in need of an upgrade.

The performance trade-off alone isn’t as big of a problem as it appears at first glance. You’re going to lose about 15% of your average gaming performance with Intel’s LGA 1700 CPUs (particularly Raptor Lake chips). You’ll spend more than twice as much on a 32GB kit of DDR5-6000 as you will on a 32GB kit of DDR4-3200, as you can see in our RAM price tracker. And, you might already have a DDR4 kit, cutting that cost completely out of an upgrade. Dollars spent for performance gained, DDR4 makes complete sense.

However, performance isn’t the only factor at play, and that’s the unfortunate reality of using a DDR4 platform right now. It’s a dead end, both for performance and upgrade potential. As we saw in our recent testing of the Ryzen 7 5800X3D, there’s a performance wall in games with DDR4, one which the 5800X3D often runs up against. The memory is a bottleneck, and it doesn’t seem like there’s a way around that problem without upgrading to DDR5.

We also aren’t seeing any new DDR4 CPUs, at least right now. AMD re-released the Ryzen 7 5800X3D, and there are murmurs of Raptor Lake Next. But given the current landscape, we don’t expect a CPU that will radically change the performance you can get out of a DDR4 platform.

Instead of sticking with DDR4 for a better CPU, the best course of action right now is to bite the bullet on DDR5 and buy a weaker CPU, particularly if gaming performance is your main concern. Given that memory prices are out of control, there are excellent deals on DDR5 CPUs right now, allowing you to offset the cost of an upgrade and giving you a kit of DDR5 to carry forward in future builds.

As an example, AMD’s recently-released Ryzen 7 7700X3D is $80 cheaper than the re-released Ryzen 7 5800X3D, despite coming in nearly 20% faster in average gaming performance. The $230 Ryzen 5 7600X3D shows similar gains, and it’s even more affordable.

In Intel’s camp, the Core Ultra 7 270K Plus and Core Ultra 5 250K Plus represent some of the best all-around value in the CPU world right now, with compelling gaming performance and chart-topping application performance, all for around $300.

You will spend more on a cheaper CPU and a kit of DDR5. There’s no indication that the memory shortage is ending soon, however. We’ve actually seen prices continue to increase despite the surge leveling off. Opting for DDR5 today buys you better gaming performance, but more importantly, it gives you a kit of memory that you can continue to use as new CPUs and platforms are released.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

You're probably already well aware of the three largest memory vendors: South Korea's SK hynix and Samsung, and the United States' Micron. There's a fourth player up and coming in the market, though, and that's China's ChangXin Memory Technologies, more commonly known as CXMT. CXMT is pumping out RAM as fast as it can to soften the effects of the RAMpocalypse on domestic (to China) consumers, and it's also expanding capacity quickly. Given these factors and the size of the Chinese market, it should come as no surprise that motherboard vendors, including Gigabyte, are advertising fresh support for the chip.

MSI appears to have been the first major motherboard vendor to publicly promote BIOS optimizations specifically for CXMT DDR5 memory, initially through China-market BIOS releases and later with global announcements. What Gigabyte is saying is a little different: not only is CXMT RAM supported on Gigabyte motherboards for both AMD's Socket AM5 and Intel's LGA 1851, but it's supported at impressive speeds of up to 8200 MT/s on select boards.

As proof, Gigabyte offers up a CPU-Z screenshot showing a pair of 16GB Lexar modules equipped with CXMT chips achieving a speed of 8200 MT/s with a CAS latency of just 40 cycles on one of its B850M FORCE motherboards. We have to remark that Gigabyte doesn't show the voltage required to hit these speeds, likely for good reason, but the firm did it without disabling the chip's integrated graphics. That doesn't prevent the chips from posting an excellent AIDA64 latency of just 65.4 nanoseconds on the monolithic Ryzen 5 8600G used for the test. For context, typical EXPO kits usually run around 80ns, JEDEC timings are more like 100ns, and LPDDR-based systems rarely come below 110-120ns.

As Gigabyte says, "CXSH (CXMT) chip-based memory offers a welcome additional source of supply for consumers." (CXSH is the JEDEC manufacturer ID code for CXMT) Gigabyte specifically notes that it is modules with 16-gigabit and 24-gigabit ICs that are supported; that means 16GB and 24GB single-rank modules, or 32GB and 48GB dual-rank modules.

While CXMT memory is certainly a welcome additional source of supply, it's also not really clear how much of that memory is actually making its way outside of China, particularly to the US and Europe. CXMT isn't on the US Commerce Department's "Entity List" yet, so the firm's parts aren't actually banned, but the company is once again considered a Chinese military company by the Department of Defense after being briefly removed from the 1260H list in February. Lawmakers here in the states, likely laden with donations from the big three memory firms, want to see CXMT banned, while US tech companies like Corsair, HP, and Dell are already integrating ChangXin RAM into their products, and Apple wants in, too.

The reality is that, as a DIY builder, you are fairly unlikely to know or care if your memory is manufactured by CXMT. You don't usually buy RAM directly from SK hynix, Samsung, or Micron (certainly not since Micron unceremoniously executed Crucial); you buy your RAM from Silicon Power, G.SKILL, Patriot, Corsair, or one of the many other vendors who assemble DIMMs. If the RAM runs at its rated specifications, there's not a lot of reason for the individual consumer to care where it came from. It's nice to hear that the new chips are officially supported by familiar mainboards, though.

As Apple and other American companies seek to use memory chips from China-based CXMT and YMTC amid massive supply constraints, U.S. lawmakers want to ban exports of Chinese memory chips to the U.S., citing concerns of weakening domestic and allied suppliers and indirectly supporting the development of 3D NAND and DRAM by Chinese companies, reports the Financial Times.

John Moolenaar, Republican chair of the U.S. House China Committee, and Democratic Congressman George Whitesides asked Commerce Secretary Howard Lutnick to prevent U.S. companies from purchasing semiconductors from businesses included either on the Pentagon's Chinese Military Companies blacklist or the Commerce Department's Entity List. They also called on the administration to add CXMT to the Entity List and impose additional restrictions on YMTC.

"Dependence on Chinese memory manufacturers creates an unacceptable risk for U.S. national security, economic security, and supply chain security," the letter by Moolenaar and Whitesides reads.

Apple has been seeking approval from the Trump administration to source memory from CXMT amid a severe global DRAM supply crisis caused by the rapid expansion of AI infrastructure. Corsair, and some other suppliers of branded memory modules and SSDs have been using DRAM from CXMT and 3D NAND from Yangtze Memory for some time now.

"We are alarmed that Apple and other U.S. tech companies seek to purchase memory from Chinese semiconductor manufacturers, including those with ties to the Chinese military," the U.S. lawmakers wrote.

DRAM maker CXMT is already on the Pentagon's Chinese Military Companies list, whereas 3D NAND producer YMTC is already in the DoC's Entity List. Their presence in the lists does not outright prevent American companies like Apple from buying their products, but at a significant political risk.

Technically, American companies could buy chips from CXMT and YMTC to use inside products bound for China or other countries and continue to use memory from traditional suppliers in products aimed at the U.S. market. To prevent this, Moolenaar and Whitesides also urge the American government to coordinate with Japan, South Korea, and the EU to prevent CXMT and YMTC from taking advantage of the current supply shortage to establish themselves in allied supply chains, which they believe could ultimately leave the West strategically dependent on Chinese memory.

Moolenaar and Whitesides argue that purchases from Chinese memory manufacturers could indirectly support technologies applicable to China's military.

"Leading Chinese memory manufacturers are all closely intertwined with the Chinese military; thus, every memory purchase by a U.S. company will directly subsidize the People’s Liberation Army's development of this critical dual-use technology," the letter stresses.

The lawmakers argue that CXMT and YMTC could repeat China’s playbook in solar, steel, telecom, and EV markets: use state subsidies to undercut foreign rivals, weaken their investments, and ultimately exploit the resulting dependence for strategic leverage. That said, using Chinese memory now could permanently weaken Western production capacity and leave the West strategically dependent on China for a critical component of AI infrastructure, Moolenaar and Whitesides believe.

Homegrown DDR5 memory from China, manufactured by ChangXing Memory Technologies, has been making the rounds lately as more and more vendors start legitimizing it. However, new testing from overclocker Safedisk, shared by Uniko's Hardware, purportedly shows that it actually carries inferior performance compared to similar options from SK Hynix, alongside significant variance in the silicon between different batches.

CXMT began producing DDR5 in late 2025 despite lacking any cutting-edge EUV lithography tools. Fast forward to today, and reports of the company matching Micron's memory capacity by this year are now floating around. If true, China would become the second-largest memory maker in the world. At such scale, it's no wonder that many companies in China have already started sourcing CXMT-made RAM to fill the gap in the consumer market.

Throughout 2026, we've seen motherboard manufacturers verify CXMT's DDR5 with official BIOS optimizations that allow it to run beyond 8,000 MT/s at this point. OEMs such as Dell and HP are using CXMT RAM in their region-bound systems, and even proper PC hardware companies like Corsair are using CXMT modules. Lexar, Kingbank, Netac, Asgard, Gloaway and more are also producing retail DDR5 kits with CXMT chips.

As such, the testing features a Kingbank 48GB (2x24) DDR5-6000 kit running at CL36 and found several weaknesses despite successfully achieving an 8,600 MT/s overclock at CL44. The first revelation is that CXMT modules don't scale with voltage, meaning you can't just increase voltage in hopes of achieving higher clocks. CXMT's DDR5 apparently doesn't respond well to tuning sub-timings either, forcing you to remain stuck with baseline CAS latency (or higher, like in this case).

Different batches of CXMT-equipped memory perform differently, too, so silicon lottery plays a much bigger role than it would with other vendors. Speaking of which, SK Hynix-made DDR5 modules allegedly performed better at identical clock speeds, while CXMT's modules were less susceptible to overclocking in general. We didn't get any comparative benchmarks for any metric, so take these claims with a grain of salt.

Overall, if the testing is to be believed, it serves as counterprogramming against the popular narrative forming around China as the savior of consumer interests. CXMT's strength lies in the fact that it doesn't have to cater to opulent AI clients as much as the Big Three, which reduces opportunity cost, allowing CXMT to produce more DDR5 memory. That doesn't mean it would be cheaper, though, or at least no evidence has suggested that so far.

CXMT has remained limited to the Chinese region for now, and breaking through to the Western market would mean impressing a lot of skeptics. Not only would pricing play a big factor, but the reliability of a new DRAM manufacturer would raise serious concerns. Stories like these certainly don't help, but with CXMT's IPO on the way, it's only a matter of time before it becomes a serious mainstream contender.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

SK Hynix CEO Kwak Noh-jung says that 2027 will be the "worst year" for the ongoing memory shortage in comments shared with Reuters. The remark comes on the heels of SK Hynix successfully marking the largest-ever IPO for a foreign company on the U.S. stock market, raising $26.5 billion. Although Kwak points to next year being the worst for RAM shortages, the executive expects the memory crunch to last until 2030.

"We forecast that next year will be the worst year in the industry's history from the supply perspective," Kwan told Reuters. "We still forecast that customer demand will remain higher than our ​supply capacity even beyond 2030. But we are doing our best to solve the problem."

In March, SK Group chairman Chey Tae-won also suggested shortages would last until 2030, and the company has previously pointed to 2027 as a key shortage point, alongside Samsung. DRAM demand is largely driven by the HBM used in AI accelerators, which require far more sophisticated manufacturing and packaging processes compared to consumer DDR5. On top of advanced manufacturing, HBM also consumes more wafer capacity than DDR5, forcing major memory brands to reallocate supply and double down on an already sticky supply situation.

Forecasts like this are tricky. It's in SK Hynix's financial interest for memory shortages to continue, even well beyond 2030. SK Hynix has set a record for quarter-over-quarter revenue, and rival Micron has seen its stock value increase 213% this year, pushing its share price to around $990.

However, Kwan's remarks aren't just a bid to rally behind SK Hynix stock. Over the past few months, we've seen Micron and SK Hynix ink long-term supply agreements (LTAs). These agreements commit supply over multiple years to particular companies and define a price floor and ceiling during the agreement term. Although LTAs don't directly influence market prices, they secure demand, and we've seen a lot of LTAs over the past several months to bind DRAM supply.

Although memory (and NAND) prices will remain elevated for at least the next several months, we've seen some signs of the market cooling. Earlier this month, a TrendForce report showed DRAM contract prices up 15% to 18% quarter over quarter for Q3 2026. That's a large increase, but far lower than the QoQ increases we've seen previously.

We're nearing some semblance of stability in the memory market, just stability at vastly elevated prices. How long that lasts is anyone's guess. Although memory brands like SK Hynix have visibility into market trends, those can rapidly change. Just this year, we've seen a massive pivot toward AI spending going toward CPUs, pushing Intel's stock to record highs while shedding around $1 trillion in Nvidia's market cap; a year ago, that would've been almost impossible to predict.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

ChangXin Memory Technologies, or CXMT, has just received official validation from MSI for its high-speed DDR5 memory modules. The manufacturer has released new beta BIOSes across its AM5 lineup, unlocking stable frequencies up to 8,200 MT/s for 3GB CXMT chips on dual-DIMM motherboards. Previously, RAM using these modules was limited to around 6,800 MT/s despite the hardware itself being capable of much more.

The test BIOS comes from MSI China — there's no announcement on global channels for some reason, and it's only available for select motherboards at the moment. MSI tested region-bound retail kits from Lexar and KingBank on boards with both two slots and four slots, but we only have screenshots for the former, courtesy of Videocardz.

One test was conducted using 24GB sticks (2x24) on the MEG X870E Unify model and a Ryzen 7 9700X CPU. This was mostly a standard kit since it came with a 6,000 MT/s EXPO profile. The other config consisted of 16GB sticks (2x16) with an EXPO profile already running at 7,200 MT/s, so it was somewhat cherry-picked silicon, paired with a Ryzen 5 9600X on a MAG B850 MPower motherboard.

The results showed that on dual-DIMM motherboards, 24Gbit (3GB) modules from CXMT were able to clock up to 8,200 MT/s, passing MemTest with 101% coverage. Conversely, 16Gbit (2GB) chips were also stable at 8,000 MT/s on the same test bench with 101% coverage. Moving over to quad-DIMM, the patch notes for the BIOS say they've "also been raised to DDR5-7200," where the limit was stuck at 6,800 MT/s prior.

This is not the first time MSI has optimized Chinese RAM for some of its motherboards. Earlier this year, the company did the same thing for Intel's 800-series models in China. Anyway, these specific BIOSes are meant for the AM5 socket and they're based on existing stable releases — just patched with unlocked memory overclocking features. More motherboards should be supported soon, but for now you can check out the MSI China's community release channel if you want to try one yourself.

Memory prices will keep climbing through the third quarter of 2026, but the blistering increases of the past few quarters are set to cool as consumer buyers reach the ceiling of what they can afford, according to a detailed TrendForce report. The research firm's latest memory pricing survey projects conventional DRAM contract prices to rise 13% to 18% quarter-over-quarter (QoQ) in Q3 2026, with NAND Flash contract prices increasing 10% to 15%; substantial gains, but a marked slowdown from the roughly 60% jumps recorded in the second quarter.

According to the report, the cooldown is driven by consumer electronics manufacturers' unwillingness and inability to absorb higher memory costs after months of relentless price increases, rather than by improved supply. In other words, memory remains in short supply, but consumers are no longer willing to keep paying ever-higher prices.

AI continues to be the market's driving force. Demand for AI inference systems and hyperscale data centers remains strong enough to keep both DRAM and NAND supply constrained, while memory manufacturers continue shifting production capacity toward higher-margin server products. This leaves less capacity available for consumer memory, preventing prices from falling even as demand from PCs and smartphones weakens.

As a result, the memory market is increasingly split between enterprise and consumer customers. On the server side, TrendForce expects demand to remain healthy through 2027 as improving CPU availability supports continued deployments of AI servers built around x86 processors and registered DIMMs (RDIMMs). Although server DRAM is expected to remain undersupplied during the third quarter, price increases should moderate because a portion of purchases is covered by long-term supply agreements.

Consumer markets appear to paint a very different picture. Notebook manufacturers are expected to keep replenishing inventories, but higher memory costs are gradually feeding through into retail pricing, a trend TrendForce believes could weigh on PC shipments for the rest of the year. Smartphone vendors face similar pressure, with many expected to raise handset prices to offset persistently high LPDRAM (low-power DRAM) costs while simultaneously becoming more cautious with production plans as consumer demand softens.

The same pattern is beginning to emerge across storage products. PC manufacturers accumulated substantial client SSD inventories during the first half of 2026, reducing their willingness to accept another round of price increases. Suppliers have responded by taking a more flexible approach during contract negotiations, helping to moderate SSD pricing even as enterprise storage continues to benefit from AI infrastructure spending.

Not every segment is seeing the same level of demand. TrendForce notes that NVIDIA's RTX PRO 6000 Blackwell has yet to generate the expected wave of GDDR7 demand, while weaker notebook shipments have also softened demand for graphics memory. At the opposite end of the market, retail products such as USB flash drives and memory cards remain sluggish as higher upstream costs become increasingly difficult to pass on to consumers.

For PC builders, the report suggests that meaningful price relief is still some way off. Memory prices are continuing to rise because AI infrastructure remains the industry's top priority. However, the pace of those increases is slowing as consumer demand reaches its breaking point.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

The price of DDR5 memory is setting new highs these days as demand badly outstrips supply. In a bid to save money, Meta is recovering legacy DDR4 memory from used servers and is installing it into new machines using its in-house developed Vistara ASIC that enables it to connect old memory modules to its latest servers running AMD EPYC 'Turin' processors that only support DDR5 memory.

Interestingly, Meta is not the only company developing such a solution. Panmnesia, a startup from South Korea, has developed an off-the-shelf CXL controller and switch that enables servers to attach considerably larger memory pools without extending latency, which differentiates Panmnesia’s solution from competing CXL offerings.

Custom ASIC enables DDR4 memory to work with new servers

Vistara is Meta’s first-gen custom CXL memory expander ASIC designed to attach outdated DDR4 memory to modern servers. The chip implements a CXL 2.0 Type-3 memory expander over a PCIe 5.0 x16 interface and bridges standard DDR4 RDIMMs to host processors. Each ASIC supports two independent 72-bit DDR4 memory channels and can provide up to 256 GB of capacity using 64 GB DIMMs. At present, Meta deploys 128 GB per ASIC using 32 GB DDR4 modules recovered from decommissioned servers.

Meta deploys Vistara in its MemServer platform, where two ASICs connect to a single 158-core AMD Turin processor over PCIe 5.0 x8 links. Each server combines 768 GB of DDR5-6400 local memory with 256 GB of CXL-attached DDR4-2400, which expands memory capacity to 1 TB. The software stack transparently exposes CXL memory as a separate NUMA node and enables Linux to migrate cold pages to the slower DDR4 tier (with 76 GB/s of bandwidth) and retain frequently accessed data in local DDR5 (with 614 GB/s of bandwidth).

The ASIC is based on three RISC-V processor cores for secure boot, device initialization, firmware management, and health monitoring. Meta claims it has optimized its CXL controller and memory pipeline to reduce protocol overhead, minimize queuing delays, and lower idle round-trip latency to around 50ns. The chip also incorporates advanced reliability features, including Reed-Solomon two-symbol error correction and x4 chip-kill support.

Not only Meta's Vistara

Meta is not the only company that wants to attach legacy DDR4 memory to newer servers that rely on DDR5 memory and save some money. While Vistara is available exclusively to Meta, there is a new CXL expander solution from Panmnesia that will be available to other companies.

"There has been a perception that putting a switch between the CPU and devices makes it hard to meet the memory-access latency these systems expect, so directly attached multi-headed devices (MHDs) stayed the norm even though they were harder to scale," said Myoungsoo Jung, chief executive of Panmnesia. "Our work shows this is not an inherent limit of CXL or CXL switches — it is a trait of early-stage CXL, and one that fades as the standard and the products around it mature. With a fabric switch that carries our next-stage CXL controller, scalability, low latency, and stable performance can come together."

CXL is a protocol that sits on top of the PCIe physical interface. As a result of this, many early CXL implementations were built by modifying existing PCIe IP, which is why such implementations inherited architectural characteristics optimized for PCIe rather than for memory-semantic communications, which added substantial latency, according to Panmnesia. By contrast, its new CXL controller IP features a redesigned data path that replaces separate per-layer buffers with shared buffers to eliminate much of the synchronization overhead. In addition, it features additional latency optimizations throughout the protocol stack that offset the additional hop introduced by the switch.

The accompanying CXL fabric switch introduces Port-Based Routing (PBR), which removes the tree-topology limitations of conventional Hierarchy-Based Routing (HBR) used by PCIe and early CXL implementations. The fabric switch still supports both PBR and HBR to enable flexible system topologies, optimized traffic routing, and stable performance. In practice, it enables companies like Meta to install more DDR4 memory into their modern servers without major performance degradation because of high latency.

Panmnesia claims that while early CXL deployments could connect only a handful of compute nodes to shared memory pools, its fabric scales to up to 64 nodes, which means greater flexibility for hyperscalers that tend to run thousands of servers, but which now have to rationalize usage of expensive DRAM.

Panmnesia says its next-generation CXL technologies are progressing toward commercialization. The company has pre-release silicon for its PCIe 6.4/CXL 3.2 Fusion Switch and has completed development of its PCIe 7.0/CXL 4.0 Combo IP, which supports the latest features introduced by the CXL 4.0 specification.

In a world where memory is no longer a commodity but a strategically valuable asset, customers are eager to sign long-term supply agreements (LTAs) with their suppliers to ensure a steady supply of 3D NAND and/or DRAM. Micron this week announced that it had signed 16 strategic customer agreements (SCAs), 14 of which are worth around $100 billion. Furthermore, the company expects to receive cash deposits and other commitments worth $22 billion, but has warned there is no foreseeable end in sight to the RAM crisis driving up PC component prices.

“14 of the 16 SCAs that we have signed have a cumulative revenue at minimum price per our contracts of approximately $100 billion over the remaining agreement term,” a statement by Micron reads. “Under the SCAs we have signed so far, we project to receive cash deposits and related financial commitments of $22 billion.”

Based on Micron’s claims, the company has about $100 billion of guaranteed baseline revenue already locked in under 14 of those 16 strategic customer agreements, assuming customers only buy the minimum committed volumes and only pay the minimum contract price. In reality, Micron can earn more if customers buy higher volumes or pay higher prices. Furthermore, Micron expects customers who signed these long-term SCAs to put up real money up front — or make equivalent binding financial commitments — as part of reserving future memory supply.

Micron claims it has signed strategic customer agreements with four 'very large customers' and three 'medium-sized customers,' which means that the contracts were inked with clients that previously did not commit to LTAs. The contracts are signed with a five-year term (except the automotive LTAs, which have a term of three years), from calendar 2026 to calendar 2030.

Micron claims that memory supply will be insufficient in 2027 and may improve gradually only in 2028. To that end, it is not surprising that its clients are willing to sign LTAs for 3D NAND and DRAM to ensure that they have enough memory for their products.

"With respect to supply, our customers are recognizing that supply shortages in memory and storage will take considerable time to improve," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks. "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand."

Normally, Micron and other memory producers inked LTAs with select clients only (read: with Apple, Nvidia). 16 LTAs is a lot for this kind of arrangement, and this looks like a business model shift for the company. It is noteworthy that the 16 signed contracts represent roughly 20% of Micron's DRAM volume and 33% of the company's NAND volume over the period through 2030. That said, Micron may sign more LTAs with more companies.

DDR2 contract prices rose 55% to 60% in the second quarter of the year and are projected to climb another 35% to 40% in the third, according to research published this week by TrendForce, pushing the AI-driven memory shortage onto a standard that first shipped in 2003 and that the three largest DRAM makers stopped prioritizing years ago. The increases come from buyers redesigning products around older memory to secure supply, and from a split among the handful of remaining DDR2 suppliers, with Winbond reducing output as ESMT expands it.

The shortage hasn’t hit DDR2 directly, but Samsung, SK hynix, and Micron have steered wafer capacity toward HBM and server DRAM to feed AI infrastructure spending, thinning the supply of mature-node parts, including DDR4. As DDR4 tightened, OEMs and ODMs began specifying DDR3 in its place, and some DDR3 designs were reworked to use DDR2, with each tier of buyers chasing whatever generation it could still source. The result of this is shortages moving down through successive generations, something we saw unfolding back in March, when earlier data showed DDR3 and DDR2 prices rising 20% to 40% in a single month.

This continues the market inversion we’ve watched unfold throughout the year, as DDR4 climbed past DDR5 on price despite being slower and older, and in which module makers and motherboard vendors restarted DDR4 production after the big three had moved to wind it down.

Winbond and ESMT are the two main remaining sources of DDR2 components, and they’re responding to the squeeze in different ways. Winbond is gradually cutting DDR2 production to shift capacity toward higher-margin DDR3, DDR4, and LPDDR4, while ESMT is doing the reverse, concentrating its wafer allocation at foundry partner PSMC on DDR2 to capture the demand Winbond is tossing aside. Taiwanese suppliers, including Nanya, are already struggling to match the volume of orders migrating down from DDR4, and because new capacity depends on slow process migration, Winbond's withdrawal removes supply faster than ESMT can replace it.

Of course, today’s PCs don’t use DDR2, so we’re likely to see the impact of these price increases landing in areas like embedded systems, networking equipment, industrial controllers, automotive electronics, and other long-lived devices that were designed around it and are too costly to requalify on newer memory generations like DDR4 and five.

The spread of rising contract prices to DDR2 suggests that we’re staring down the barrel of a very long-term DRAM shortage. Contract prices across the wider market are still rising with no sign of levelling off, and meaningful new capacity isn’t expected until late 2027 at the earliest as a best-case scenario.

Apple CEO Tim Cook has warned in an interview with the Wall Street Journal that price hikes on Apple products are unavoidable because the price of memory has increased to a degree that the company must now pass on increases to customers. The outgoing chief executive of Apple did not disclose the scope of the increases or when to expect them to happen, though the warning itself is noteworthy.

Cook said in the interview that price increases had become necessary due to skyrocketing prices of LPDDR and 3D NAND memory, which the company uses in its PCs, smartphones, tablets, and other products. He noted that Apple had attempted to offset rising component costs and protect customers from higher prices, but indicated in the interview that the company could no longer absorb the increases indefinitely. While Cook declined to discuss timing or the magnitude of the planned price hikes, some Apple products may see higher prices sooner rather than later. The company already raised the base price of its Mac Mini last month and eliminated its highest-end model.

TechInsights estimates that Apple will need to hike the price of a flagship iPhone Pro model by about $270 to maintain its current gross margins, which could push flagship iPhone pricing into a substantially higher price band. To make matters worse, Apple faces rising DRAM requirements as it expands memory-hungry on-device AI capabilities.

Apple is a unique company in the sense that it is both one of the world's largest suppliers of smartphones and one of the industry's biggest PC OEMs. Still, its Mac business is negligible compared to the iPhone business.

Memory makers are more inclined to ship non-volatile NAND memory to smartphone makers as they can ship LPDDR with it, according to Nelson Duann, a senior vice president of Silicon Motion, speaking in an interview with Tom's Hardware. If Duann is correct that NAND makers prefer smartphones because they can bundle NAND and LPDDR sales, then Apple should be among the most favored customers in the industry, not among the disadvantaged ones.

Also, keep in mind that historically Apple has used long-term supply agreements, prepayments, equipment financing, and advance capacity reservations to secure key components, including DRAM, NAND flash, displays, advanced packaging, and even semiconductor foundry capacity. As one of the world’s largest electronics manufacturers and semiconductor buyers, Apple is among the few companies capable of negotiating with memory suppliers from a position of considerable strength.

As a result, Apple is not in a situation where it cannot get enough memory; it can probably get more than other suppliers of smartphones and PCs, but it surely has to buy both DRAM and NAND at a premium. That said, it is not surprising that Apple will have to increase prices; what remains to be seen is the magnitude of the increase.

AMD on Monday announced that it had acquired MEXT, a startup that developed a memory tiering technology that makes NAND flash memory appear as DRAM to the operating system, which enables operators of data centers to save money on DRAM. AMD expects the acquisition to help customers improve system efficiency, lower operating costs, and deploy large-scale workloads more quickly.

As AI models continue to expand and datasets grow larger, memory availability has become an increasingly important factor affecting overall system performance. In many cases, memory resources, not CPUs or GPUs, are becoming a performance bottleneck. Meanwhile, in many cases DRAM is used inefficiently.

MEXT addresses memory efficiency challenges with an AI-based memory tiering technology that moves infrequently accessed data from expensive DRAM to NAND storage, which costs orders of magnitude less per unit of capacity, and in a way that's transparent to applications. MEXT's Predictive Memory Engine continuously analyzes memory access patterns and uses AI models to anticipate which data stored in flash will be needed next. Those memory pages are proactively transferred back into DRAM before applications request them and enable software to access data as though it were in main memory, thus preserving performance levels.

By increasing the amount of usable memory available to applications, MEXT's technology aims to improve utilization of existing infrastructure and at the same time reduce needs for expensive DRAM. This approach can potentially lower total cost of ownership for cloud providers and enterprise customers and enable larger workloads to run on existing hardware. AMD believes that these capabilities can benefit both traditional data center applications and modern AI deployments, where access to large memory pools is often critical for efficiency and scalability.

AMD plans to incorporate MEXT's technology into its data center product portfolio and expand its capabilities to address memory-hungry AI workloads. The company already offers integrated solutions that combine processors, accelerators, networking technologies, and software, so MEXT's Predictive Memory Engine will complement the already broad portfolio.

As an added bonus to the technology itself, AMD gains a team with expertise in memory architectures, infrastructure software, and large-scale computing systems. Terms of the deal are unknown.

Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

A coalition of nine US trade associations has urged the Trump administration to take immediate action on what it describes as an emerging memory chip shortage driven by the explosive growth of AI data centers. In a June 3 letter sent to US Commerce Secretary Howard Lutnick and Treasury Secretary Scott Bessent shared with Tom's Hardware, the organizations — representing telecommunications providers, automakers, medical device manufacturers, and major retailers — warned that AI infrastructure deployments are consuming an outsized share of global memory production, creating supply constraints and price increases that could ripple across large segments of the US economy.

The coalition warned that the AI data center expansion, which has consumed an unprecedented share of global memory capacity, has led to a memory chip shortage that could lead to higher prices for consumer electronics, increased costs for broadband and telecommunications infrastructure, disruptions to automobile and medical device production, and delays affecting federal contractors attempting to fulfill government procurement obligations. The letter argues that these risks are emerging despite billions of dollars of US investment intended to strengthen domestic semiconductor supply chains.

The signatories acknowledged AI's importance but argue it shouldn't come at the expense of the rest of the economy. "While recent developments in AI offer the promise of generational technological advances and are important for US tech leadership, we must also ensure other key industries are not negatively impacted by this disruption in the marketplace," the coalition said.

The organizations are asking the administration to work directly with memory suppliers and major chip buyers to address the imbalance. Their recommendations include accelerating expansion of memory manufacturing capacity in the United States and allied nations, using trade agreements to strengthen supply-chain resilience, ensuring adequate memory supply for non-AI industries, leveraging CHIPS Act programs where possible, and reducing regulatory barriers that may slow capacity growth.

"We urge the Administration to work with memory chipmakers and chip buyers to assess steps that can be taken to address this imbalance in the memory market and protect against harm to consumers, workers, and businesses of all sizes," the letter states.

The warning arrives as memory manufacturers increasingly prioritize high-bandwidth memory (HBM), the specialized memory used in AI accelerators from companies such as Nvidia and AMD. Demand for HBM has surged over the past two years as hyperscalers race to deploy larger AI clusters, prompting memory suppliers to devote an increasing share of their production capacity to AI-oriented products.

Samsung and SK Hynix — which together with Micron control over 95% of global DRAM production — have been diverting wafer capacity toward high-margin HBM for AI accelerators, starving the commodity DRAM and NAND markets in the process. Both companies warned in April that significant shortages will continue through at least 2027. IDC, meanwhile, has already revised its 2026 PC market forecast downward by up to 9% as a direct consequence of memory scarcity and rising prices.

Industry analysts have repeatedly warned for months that AI demand is reshaping the economics of the memory market. While memory shortages have historically been cyclical, the coalition argues that AI infrastructure spending is creating a structural shift large enough to affect industries far removed from data centers. The letter marks the first coordinated, multi-industry push for federal intervention. Whether the administration will respond — and how — remains to be seen.

Representatives told Tom's Hardware at Computex 2026 that counterfeit memory modules with G.Skill and V-Color badges have hit various marketplaces in China, and the problem is widespread enough that V-Color has observed lower sales to certain clients. Fake memory modules are nothing new, but in this case, forged DIMMs reportedly use printed circuit boards (PCBs) that are identical to those used by G.Skill and V-Color, which makes early detection of counterfeit products difficult.

“We have customers telling us that some Chinese manufacturers are making copies of our products, as well as products from other brands, and selling them at lower prices than we do,” a spokesperson for V-Color told Tom’s Hardware. “We do not really know how they are doing it. The PCB looks the same, even the heat spreader looks identical.”

Given the current situation with memory prices, counterfeit memory modules have become a growing problem in Asian online marketplaces, particularly in gray-market and second-hand channels. Recent reports described fake DDR5 modules containing dummy ‘chips’ made of plastic or fiberglass with fake markings, as well as mislabeled modules marked as products from well-known brands. However, the new case is different because forged memory modules use PCBs that are identical to those used by G.Skill and V-Color and use the same heat spreaders and perhaps complex RGB lighting, making distinguishing between real and counterfeit products particularly difficult.

While developing a PCB for an enthusiast-class memory module takes time and money, producing that PCB is fairly easy, as makers of DIMMs use neither complex PCBs nor too complex equipment. Also, developing enthusiast-grade memory modules (ensuring that they run at the right specifications with popular CPUs) also takes time and money. In addition, sourcing chips from DRAM makers or distributors to make fake memory modules is hard, if even possible at all today. Finally, quality control at the chip level and at the module level is relatively costly, and these two are the main value adders when it comes to enthusiast-grade memory. That said, forging high-end memory modules is easy and might be a profitable business, especially if perpetrators have access to second-hand memory chips. Speaking of chips, the V-Color representative could not say which ICs the fake modules used.

“We do not know because we have not had any of those modules in our hands,” the spokesman said. “We only use SK hynix memory, so we cannot say what chips they are using. We have not received any RMAs related to them. Other brands may have received returns and been able to inspect the products, perhaps because the memory chips were different.”

While a representative for G.Skill confirmed that there are counterfeit G.Skill memory modules sold on Chinese marketplaces, he said that the issue has existed forever, so users should buy their high-end DIMMs from official partners and resellers in a bid to avoid the problem.