The two biggest NAND flash memory manufacturers on the planet, Samsung Electronics and SK Hynix, are reportedly working to upgrade their Chinese factories to produce more advanced chips for use in AI data centers, Reuters reports. The move comes as the two companies continue to fight off competition from the fast-growing Chinese memory makers like CXMT. Fierce competition in the lucrative AI RAM market has already seen manufacturers slash consumer-focused production to allow them to increase production capacity for the more advanced — and money-spinning — components.

Citing four people familiar with the companies' plans, the report claims that Samsung Electronics aims to switch its Xian plant to the production of 286-layer flash chips by the end of the year. SK Hynix has its sights set a little lower, targeting chips with 240 or more layers at its Dalian facility. That factory was taken over back in 2021, but a timescale for the new upgrades isn't clear.

However, while Samsung Electronics and SK Hynix are well placed to deal with the growing threat from Chinese chipmakers, both are faced with additional complications in the form of U.S. regulations. Export controls on chipmaking equipment were applied in 2022, with the aim of slowing China's technological progress. Both companies, based in South Korea, must now get licenses in order to install U.S.-built hardware in Chinese factories. The report points to this as a reason for the recent growth of Chinese firms like Yangtze Memory Technologies Co. (YMTC). The company told investors at a recent IPO preparation meeting that it aims to become the world's largest NAND flash producer by the end of 2027.

While both Samsung Electronics and SK Hynix say that they are working in consultation with the U.S. authorities, there's little doubt that this extra step has hampered the companies' ability to upgrade their factories to better meet the new AI memory demand.

It's impossible to overstate just how key Samsung and SK Hynix are to NAND supply. Samsung's Xian factory produces around 40% of the company's global output. It currently produces chips that have around 200 layers, but Samsung's plans aim to boost that to 286 layers for V9 NAND chips. For its part, SK Hynix's Dalian plant currently produces chips with 192 layers, with the company's aim for 240-layer chips reportedly confirmed by three people familiar with the plans.

Meanwhile, CXMT, China's premier chipmaker, is looking to move beyond DRAM production. A report from September 2026 noted that it was eyeing production of 3D NAND memory for use in solid-state storage (SSD) products. The country's largest DRAM producer, CXMT, posted $22.41 billion in revenue and $11.57 billion in net profit in the first half of 2026 after years of losing money. But despite this purple patch, the company is still much smaller than the likes of Samsung, SK Hynix, and Micron.

Micron faces a one-day labor stoppage at its Taoyuan operations in Taiwan on October 22, Reuters reports. Micron's employees are striking for concrete terms for this year's bonus and a clearer mechanism for sharing the company's future profits. The strike's teeth come from the resultant financial impact on Micron's operations, as semiconductor fabs are supposed to operate around the clock. The scheduled protest comes amid strong demand for memory chips and will have a minor impact on Micron's memory output.

The Taoyuan union wants Micron to present a specific proposal for this year's additional employee bonus and establish a transparent formula for distributing a portion of future profits. Previous negotiations between the company and the union ended unsuccessfully in September, which prompted employees to approve industrial action in early October. Nonetheless, the union stresses that the October 22 strike is intended to pressure Micron into reaching an agreement rather than terminate negotiations. The union is prepared to conclude a deal if the company presents terms acceptable to employees across its Taiwanese operations.

The situation could become more serious if employees at Micron's Taichung operations, its largest manufacturing site in Taiwan, decide to join the action. A separate labor organization that represents workers at that facility is scheduled to meet with Micron for mediation on October 22, the same day as the Taoyuan protest. However, the Taichung union has not yet authorized a strike.

Micron's fabs in Taiwan produce commodity DDR5 and LPDDR as well as expensive high-bandwidth memory (HBM) for AI accelerators. Amid record demand for memory of all types, even a one-day suspension of operations would have a material impact on Micron's output and earnings.

Modern semiconductor fabs are supposed to work 24/7/365, as many processes cannot be halted. However, if management has sufficient time and personnel to prepare, a one-day warning strike does not necessarily mean a complete shutdown of Micron's Taoyuan manufacturing operations, not to mention permanent damage to wafers or equipment. The actual consequences of the strike will depend on employee participation, which manufacturing operations are affected, and Micron's contingency plans. While it is likely that the output will drop, the decline will likely be negligible.

Micron employs approximately 15,000 people in Taiwan. The workers point to compensation arrangements at Samsung Electronics and SK hynix as examples of how semiconductor manufacturers can distribute profits among employees as AI-driven demand generates unprecedented cash flows for memory firms.

What if you could buy a cheap used DDR5 SODIMM (laptop memory) kit and transform it into a super-fast DDR5 desktop kit? That’s what electronics hobbyist Blighted Agent recently did when they succeeded in converting a SK hynix 2x 16GB DDR5-5600 SODIMM kit they got from Facebook Marketplace for $120 into a 2x 16GB DDR5-7800 desktop kit, claimed to be worth around $1,000. They also had to buy some blank DDR5 desktop memory PCBs from AliExpress for around $16 each, and a set of heatsinks for around $18.

In the above video, our hero says they bought the donor laptop 2x 16GB DDR5-5600 sticks for just $120, which is a bargain. With extra bits and pieces from AliExpress (desktop DDR5 PCBs, etc.), the total bill of materials came to $175. Blighted Agent comments that the SODIMMs used what he believed to be SK hynix A-die modules, which are the same as the ICs used in expensive desktop DDR5 modules like the G.Skill Trident Royal line.

The process began with taking the memory ICs from the donor modules using a hot air station. Then they were cleaned and had 0.45mm leaded solder balls added, using a DDR5 stencil, reballing jig, and hot air. Next, the blank desktop DDR5 PCBs were prepared. A little solder was added to the plethora of BGA connectors to be ready for the memory chips to connect to.

The old DDR5 ICs and the new desktop modules could now be mated, using flux, the preheater, hot air, and watching and prodding carefully with a dental pick. Blighted Agent’s experience lets him know when the BGA chips have successfully mated with the PCB. You can eyeball when they pop precisely into place due to surface tension, and offer up a modicum of resistance to pick prodding.

Finally, the enthusiast added the SPD chip and BIOS chip from the SODIMMs to the new desktop DIMMs. These new desktop DIMMs were quickly tested in a PC before they were finished off with carefully applied thermal pads and the fancy-looking heatsinks.

Blighted Agent felt lucky that there were no issues with the newly created desktop modules. There’s a lot of intricate things that can go wrong during such a process. The initial boot verification showed them recognized in his Asus ROG Maximus Z790 Apex Encore motherboard as two “SK hynix 16,384MB 5600MHz” modules, which was correct. Some tuning resulted in rock-steady performance at DDR5-7800 CL38 and 1.40V. This was verified by stress testing for 90 minutes, which the enthusiast reckons was ample for a gaming PC. It is very likely a better result than using those mechanical SODIMM-to-DIMM converters you can buy, which can be problematic.

Blighted Agent seems to specialize in BGA soldering work, and has also successfully upgraded several graphics cards with double the VRAM. Though videos like this are edited to be brief, and they make the process look easy, the TechTuber admits there is a lot that can go wrong during this kind of rework. Moreover, with RAM modules, they lack the testing equipment to locate an issue with any particular IC on the PCB. So, if this module didn’t work, they might have ended up in a world of pain, not knowing which memory chip had an issue due to either an internal fault or a BGA soldering glitch.

Looking around at used DDR5 SODIMMs, it looks like Blighted Agent was very lucky to get a used working 32GB kit for $120. I just checked eBay U.S., and the best deal there was $320. Meanwhile, the best price for a new 32GB DDR5-6000 kit seems to be $449 at the time of writing.

We reported on Russian enthusiast VIK-on succeeding in a similar project earlier this year, but all their costing was in Rubles, and they went the extra mile in flashing custom firmware so the remade modules would be auto-detected with 6400 MT/s XMP support on most motherboards. In late 2026, DDR5 RAM continues to be too expensive.

Elon Musk has criticized memory makers for what he calls 'extortionate' pricing amid an unprecedented shortage of both conventional DRAM and high-bandwidth memory (HBM). Although Musk did not identify the companies he criticized, his remarks seem to be directed at Samsung Electronics and SK hynix, as he praised Micron for its more 'reasonable' approach at the same time. Interestingly, Micron also enjoys exceptionally high profitability: its latest quarterly gross margin reached 81%.

"Micron has been reasonable regarding future memory prices, while others have been extortionate, which is something today's customers will not forget," Musk wrote in a post on X. "Micron is making the smart move for long-term customer loyalty."

Musk did not provide specific details of said extortionate pricing or disclose terms offered by different memory suppliers (which tend to be confidential). Consequently, it is impossible to determine whether Samsung and SK hynix charge substantially more than does Micron for comparable products. Nevertheless, Musk's remarks suggest considerable frustration with the pricing policies of South Korean memory manufacturers.

Over the past several quarters, memory has transformed from an easy-to-obtain commodity to a strategic asset, and makers of 3D NAND and DRAM have certainly benefitted massively from this shift. Historically, memory makers have responded to strong demand and rising prices with aggressive capacity expansions, which eventually led to oversupply and falling prices. This time around, however, manufacturers have raised memory prices severalfold without comparable increases in production capacity. As a result, supply still lags behind demand and will continue to do so for years to come, which puts further upward pressure on memory prices.

What makes Musk's praise of Micron particularly interesting is the company's financial performance, which clearly suggests that the company is taking advantage of the situation in the market. In its fourth quarter of fiscal 2026, Micron reported revenue of $54.23 billion and a GAAP gross margin of 81%, up from 40% a year earlier. The company's cloud memory unit earned $16.283 billion, and its non-GAAP gross margin totaled 83%; its core data center storage business sold goods worth $18.002 billion with a 90% gross margin; while sales of the automotive and embedded units totaled $6.824 billion with gross margins reaching 84%.

Perhaps the most surprising part of Micron's last quarter report was its mobile and client revenue of $13.114 billion and non-GAAP gross margin of 90%, which means that Micron earned higher profit selling memory and storage for client devices than it did for selling memory solutions for data centers. Such results clearly indicate that even supposedly reasonable memory prices can generate extraordinary profits in the current market.

Memory manufacturers are increasingly shifting toward long-term supply agreements (LTAs) that guarantee future supply and provide customers with predictable prices of DRAM, HBM, and NAND. So far, Micron has signed 26 strategic customer agreements that cover more than 35% of its expected revenue through 2030. These contracts include $32 billion in customer financial commitments, most of which consist of cash deposits. The company acknowledges that its new agreements reflect higher prevailing memory prices, and it by no means is trying to sell memory at a discount.

Samsung has reportedly secured long-term contracts covering 75% – 80% of its planned memory output in 2027, according to South Korea's ⁠Korea Economic Daily (via @Jukan05). SK hynix is reportedly pursuing similar arrangements as AI infrastructure investments continue to absorb available memory capacity.

Market insiders and analysts expect memory supply shortages to persist through at least 2028, and that gives manufacturers considerable leverage in contract negotiations. Memory suppliers have little incentive to reduce prices and are eager to enjoy their position, but Musk's warning suggests that today’s pricing policies could influence customer relationships once supply and demand eventually return to balance.

CXMT expects to launch its first 4F² product, a server DDR5 RDIMM, by the end of the year, company president Cao Kanyu said in remarks reported by Yicai. The memory will be built on a denser cell layout, not yet commercialized, using vertical transistors to reduce the cell’s footprint by about one-third on paper. No speeds or capacities have been announced yet for the new product.

Cao spoke about the new RDIMM at the Integrated Chips and Chiplets Conference on Saturday. A 4F² cell is 2F by 2F at about two-thirds the area of current 6F² cells at the same feature size, and designs so far all stand the transistor up. The company has produced research and patent filings on the technology with papers in 2021, 2023, and 2025, and an 8Gb full-array research example was demonstrated at IEDM 2023.

Cao said CXMT’s version, the Vertical Surrounded Gate (VSG) transistor, has a channel that stands vertically with the gate wrapped around it, allowing stronger gate control with less leakage. Most importantly, standing the transistor up shrinks the cell. CXMT now has more than 300 published patent families tied to 4F², he added. The report says the industry as a whole is moving toward 4F² with 3D solutions that decouple DRAM and CMOS processes, combining them with wafer-level hybrid bonding, which allows logic and cell density to be optimized independently. Cao also covered CXMT’s own hybrid-bonding work, which began in 2019, with published patents.

Aside from this announcement, China’s primary DRAM maker has been in the news lately for its manufacturing and market-share gains. Its fifth-generation G5 DRAM technology platform, announced Sept. 20, is in mass production. TrendForce puts CXMT’s share of global DRAM revenue at 9.5% in the second quarter, up from 7.6% in the first, good for fourth place. Last November, CXMT showed off DDR5-8000 and LPDDR5X-10667. It has revealed itself as a manufacturer to be taken seriously by the biggest existing players.

Samsung showed off a 16Gb, 10nm-class 4F² DRAM design in its ISSCC 2026 paper in February. That one also used vertical-channel transistors (VCT), with the array bonded on top of the periphery using wafer-to-wafer hybrid copper bonding. The company claims the bonding raises dies per wafer by more than 20% with the same design rules. In April, The Elec reported that Samsung had a working 4F² VCT die on its sub-10nm “10a” process, with mass production targeted for 2028. Later South Korean reports clouded that date: the VCT version has since been split off as “D0a-V” with no timeline, and there is no firm timeline for adopting 4F².

SK hynix laid out plans at VLSI 2025 for a 4F² vertical-gate platform and 3D DRAM at nodes of 10nm and below, with circuitry bonded under the cell array. The April report also puts SK hynix’s 4F² debut at the 10b node, one step after Samsung’s 10a. Micron’s plans remain less clear, with no widely reported 2026 statement.

The announcement is perhaps more interesting for what wasn’t mentioned: capacity, speed, die density, process node, named customers, or intended volume. All we have is a date and a purported cell design, admittedly well-supported by the literature, but no product that has been tested by anyone outside of CXMT. Beyond Cao’s talk, CXMT hasn’t posted a release about the product in its Chinese or English newsrooms.

South Korean reports have said that CXMT’s initial products may only partly use 4F² and that producing stable units at volume is a separate challenge. With about 11 weeks left in the year, it will be interesting to see what CXMT actually delivers.

PC shipments globally have dropped by 20.1% year-over-year in the third quarter of 2026, a decline of 15.8 million units. According to research firm IDC Global, this marks a steeper decline compared to the 3.8% year-over-year decrease that the market experienced last quarter. It’s also down 9.1% from the second quarter of this year. Many research firms have been warning about this since late last year, with IDC warning that the PC market could shrink up to 9%, with the budget sector being hit the hardest. Some experts estimate that the situation isn’t expected to improve until 2029, with Tom’s Hardware readers saying that they won’t upgrade their systems in the next two years.

These price increases have been directly caused by the boom in AI data centers, with hyperscalers pouring massive amounts of money into the crucial HBM needed to support AI GPUs. This has led to memory manufacturers pivoting toward this technology, leaving less production capacity for consumer memory. One good example of this is Micron, which killed the Crucial RAM and SSD brand in late 2025 so that it can focus on data center production. As PC makers fight for a shrinking supply of memory chips, we saw memory prices climb by as much as 500%, with 128GB of DDR5 now costing as much as $3,399.

Manufacturers didn’t sit idly by and let the market take its course, though. Many of them stocked up on inventory in the second quarter of 2026 to try and head off the projected higher prices caused by the shortage, which directly led to the reduced shipments being reported. “What we’re seeing is the result of the strong first half pull-in. Vendors and channels loaded up on inventory early in the year to get ahead of price hikes, and that has thrown off the usual seasonality, where Q3 is typically larger than Q2,” said IDC consumer devices research director Jitesh Ubrani. “Channels are now worried about carrying too much inventory into a market where high prices are suppressing demand. That could translate into promotions and some short-term relief for consumers, but we don’t expect pricing anywhere near what it was a year ago. Prices will remain elevated. With macro conditions worsening, the risk is that the outlook for the next few quarters gets worse before it gets better.”

The top three PC vendors suffered the most, with Lenovo shedding 22.6%, HP shipping 30.9% fewer units, and Dell shipments contracting by 25%. On the other hand, Apple’s shipments shrank by 11.3%, while Asus’s numbers fell by 8.6%, with the rest of the market shipping 14% less year-over-year. Despite being hit the hardest, Lenovo, HP, and Dell still maintained their lead at 23.8%, 16.5%, and 12.1% market share, respectively.

Even though other industry leaders, including Micron, say that the situation will not improve for the next few years, Acer CEO Jason Chen went against the grain and said that these fears are just being hyped to protect the margins of memory chip makers. He estimated that PC prices will decline by the latter half of 2027 as Chinese memory chip capacity comes online, with only high-end parts like LPDDR5X-9600 and niche CPUs such as the Nvidia N1 and N1X remaining in short supply.

A YouTube channel best known for its skillful graphics card fixes has published its first RAM module repair video. Tony from NorthWestRepair’s latest video shows his attempts to mend a pair of high-capacity DDR5 sticks worth a purported $16,000. It isn’t the repair skills that are newsworthy here. Rather, it’s the shift in economics that makes the chuck-it-and-replace-it attitude to bad RAM a philosophy that simply doesn’t apply in 2026. The impact of the AI-pocalypse means that spending a couple of hundred dollars on repair labor to save a several-thousand-dollar DDR5 DIMM is now sensible. If you can repair RAM, you can now start a business.

Two DDR5 sticks were sent in to Tony, described as having physical damage. They are both ECC sticks, meant for servers, one with 128GB and the other with 256GB of DRAM ICs onboard. Tony sounded happy at the start of the video, as this is an excuse to use his Unified DDR Flasher Main Board, for which he had just acquired an RDIMM extension that works with these server sticks.

Initial close physical inspection didn’t reveal any conclusive evidence of the source of the problems. So, it was hoped electrical tests would provide more clues. A data line tester didn’t highlight any issues, though. Tony used flux and hot air to reflow the solder on the first DIMM, which is a far simpler process than a reball (where all the memory ICs are taken off, cleaned, and given new solder balls). Initial signs were that the module was now working OK. So, he moved to the next DDR5 DIMM.

The second DIMM “may have a faulty PMIC chip,” which is why it seemed more severely broken than the first module, Tony indicated. Powering on a system with this DIMM inserted showed no signs of life, and the DIMM didn’t even warm up (thermal camera checks). That contrasts with the first fix.

Because this DIMM is completely dead, Tony did some work on the non-DRAM chips like the PMIC and SPD EEPROM first. Then he decided to reflow some other chips, including memory ICs, like before, while the board was warm. Some ICs were also reballed after inspection, making Tony suspicious of them.

The repairer found a short circuit via voltage injection and thermal camera monitoring. This was fixed with a new capacitor and by fixing the short on the damaged edge of the PCB. Finally, a new PMIC chip ended the quest, and this second DDR5 DIMM powered on and trained successfully.

The repair is good to see, saving these valuable components from e-waste. However, the bigger picture is that repairing memory modules could now be a viable business. Previously, it didn’t make sense to spend a hundred or two on labor to fix a DIMM that would cost about the same or even less to replace with a new one. Now the repair fee might be just a fraction of a replacement price.

Micron released its fiscal Q4 2026 financial results on Wednesday, expectedly setting another record for revenue with $54.23 billion for the quarter, up nearly five times since the same period last year. Micron also hit a record 87% gross margin, the largest contributor to which was Micron's Mobile and Client (consumer) business unit. Further, Micron's client business was the only one that shipped less memory last quarter, despite bringing in the highest operating margin at 88%.

Micron's margins overall are up significantly year-over-year; Core Data Center surged from 25% to 85%, and Automotive and Embedded have climbed from 20% to 79%. The Mobile and Client unit also saw significant growth, with a 29% operating margin in fiscal Q4 2025, and now a margin of 88%. Cloud Memory margins grew, though not to the same extent as other units, moving from 48% to 76%.

The gross margins are interesting to look at, too. In a financial statement, the gross margin equals revenue minus cost of goods. Operating margin, on the other hand, equals revenue minus cost of goods and all other operational expenses. The operating margin simply excludes taxes and interest.

The gap between gross and operating margin is what's interesting in the breakdown above. The Mobile and Client unit has the smallest gap, with only a 2% difference. The Core Data Center unit matches the Mobile and Client unit with a 90% gross margin, but it has a lower operating margin at 85%. In other words, the cost of running Micron's consumer business is extremely low relative to the amount of revenue it currently generates.

It also saw the lowest amount of growth for the quarter, with revenue up 14% quarter-over-quarter. Micron says this was "driven by higher pricing, partially offset by lower bit shipments." Out of Micron's four business units, the Mobile and Client unit was the only one that shipped less memory in the past quarter.

For clarity's sake, a bit shipment is just a shipment. Micron measures shipments in bits rather than units. It's the capacity Micron has shipped in a quarter, not the actual number of DRAM or NAND chips.

Outside of Mobile and Client, Micron attributes higher revenue to higher pricing and bit shipments. The situation in the Mobile and Client unit echoes a sentiment we've heard elsewhere: growth in the consumer market is still happening, but it's driven by higher pricing, not growth in shipments.

Earlier this year, Intel's David Zinsner, chief financial officer, attributed a 13% YoY growth in Intel's consumer business to higher average selling price (ASP), not increased unit sales. Zinsner clarified that Intel "thought we had seen some inflation on our cost and needed to pass that on to the end customer."

Micron's outlook for fiscal Q1 2027 has revenue set at another record of $61.5 billion ± $1.5 billion, with gross margin rounding from 87% in fiscal Q4 2026 to 86.25%.

Another record quarter signals more squeeze on the DRAM and NAND markets. Echoing rival SK hynix, Micron says it expects memory and storage to be "much tighter" in 2027 and 2028, claiming that the company expects the industry to be supply-constrained in both years. That's despite a growth in supply that Micron anticipates.

The company says it expects industry NAND bit shipments to grow in the mid-20% range, and DRAM bit shipments to grow in the low-20% range. The industry broadly will produce more memory over the next two years, says Micron, but that still won't keep pace with demand.

Worrying still is this line in Micron's earnings slides: "we do not have line of sight to when supply and demand will return to balance." However, the company says it plans to increase its capital expenditure (capex) in fiscal 2027 compared to its prior estimates.

A "majority" of that increase is set aside for construction of additional clean room space, which Micron has set for 2028 through the end of the decade. Hopefully, that additional clean room space coming online will ease supply constraints, but we're still a long way from that point.

Micron said during its FY 2026 earnings call that RAM and storage chip shortages will worsen in 2027 and 2028, even as it announced a record gross margin of 86.25%. CEO and chairperson Sanjay Mehrotra said that the company has already sold most of its capacity for next year and that customers will have to pay more compared to 2026.

“In calendar 2027 as well as 2028, we see demand exceeding supply. In fact, we see greater tightness in the industry in 2027 and in 2028 versus 2026. Overall, supply-demand environment is only getting tighter,” Mehrotra said. “We do not have line of sight to when supply and demand will return to balance.”

The memory and storage industry is not holding back on increasing production, though, with Micron saying that NAND and DRAM shipments are expected to grow in the low-to-mid 20s percentage range for the next two years. However, it seems that this is not enough to match growing demand, as it expects “the industry to remain supply constrained in both years.” Still, it seems that manufacturers are prioritizing HBM demand for AI data centers, with the company expecting shipments of these chips to grow faster than conventional DRAM.

Micron and other chip manufacturers are bringing new factories online to increase output, but it’s going to take years before they can start producing chips. But even as we’re amid an unprecedented multi-year memory chip shortage, Micron also announced record financial guidance. It forecasted a record $61.5 billion FQ1 revenue and a gross margin of 86.25%, implying a gross profit of more than $53 billion. After accounting for an estimated $2.06 billion in operating expenses and a tax rate of around 15.5%, the company said its earnings per share sit at $38.15, plus or minus $1.00, for approximately 1.15 billion shares.

These are record numbers, but it’s not surprising given the amount of money being poured into AI data centers. It has gotten to the point where the memory workers from Samsung and SK hynix have demanded and received bonuses worth hundreds of thousands of dollars, with Micron’s workers in Taiwan threatening to strike if they do not receive a bigger slice of the AI pie. While this is good news for the average employee from these big companies, it’s unfortunately bad news for the average person who must pay for RAM and storage at higher prices.

Micron’s prediction goes directly against the Acer CEO’s prediction that PC prices will decline by late 2027, especially as Chinese RAM chips enter the market and consumers simply refuse to pay more for expensive memory chips. We can only wait and see which of these CEOs will be correct when it comes to DRAM and NAND pricing.

A PC RAM maker has honored its guarantee promises despite the memory kit in question’s price rising eightfold since it was bought. This is news in 2026, as we’ve heard of so many companies dealing with AI-inflated component pricing refusing to replace items, instead refunding the original purchasing price despite the products now being worth many multiples of the original price. These glad tidings come via Redditor Double-South8863, who says their $150 G.Skill Trident Z5 Neo RGB 64GB DDR5-6000 RAM kit, now priced at $1,200 on Amazon, was back at full capacity after the company replaced the stick. They received the replacement within two weeks.

“I will never buy any RAM other than G.Skill for as long as I live,” pledged Double-South8863 on Reddit. They informed their fellow social media posters that one of the 64GB RAM kit’s sticks died at the beginning of September. After some A/B testing, they were sure one of the 32GB sticks was dead.

On September 8, about a week after the issue first reared its head, Double-South8863 decided to start an RMA process and get the dud G.Skill Trident Z5 Neo RGB 32GB DDR5-6000 stick replaced. They remember buying this highly desirable RAM kit online in May 2025 for the princely sum of $150. Now it is worth a king’s ransom at $1,200 on Amazon, and price tracker sites show it's even been as high as $1,300.

Perhaps the Redditor was aware of the reports of companies and their dastardly deeds regarding RMAs, as they are active on the PCMR subreddit. However, they optimistically went ahead and completed the RMA paperwork, then received instructions, including a shipping address to initiate the warranty exchange. Double-South8863 says they mailed the misbehaving memory module back to G.Skill on September 15. The Redditor’s post celebrating G.Skill’s customer service, proclaiming that they were now a “customer for life,” was published on September 26.

If you check the G.Skill site, you will note that this RAM-first firm still offers a limited lifetime warranty on all its popular RAM kits. Please note that, according to the official terms, this lifetime warranty “automatically terminates upon discontinuation or end-of-life ("EOL") designation of that specific model by G.Skill.” That means you shouldn't expect to swap out a faulty DDR5 module for a replacement for the whole of your natural life.

PC enthusiasts and DIYers are having a hard time right now as several key components required for performance builds are at all-time-high pricing. Meanwhile, those with a working setup pray that nothing will go wrong with the precious equipment they already have. Sadly, things do break, some components more than others. However, warranty obligations seem to have come under increased strain in recent months as consumer product scarcity means component makers can’t or won’t follow RMA norms that had been established for decades. Some of the worst cases we’ve seen involve PCs and component makers trying to refund the original (low) prices paid, substituting failed parts with non-equivalent parts, or even worse.

The maker of XMG gaming laptops and Schenker workstations said the prices for DDR5 SO-DIMMs have increased sixfold since July 2025, and it believes RAM will be in short supply through 2027 and beyond. The company said this in the r/XMG_gg subreddit, where the company also announced a price increase of $113 (€100) and $228 (€200) for most of its gaming laptop models, plus a massive $342 (€300) hike for one professional laptop.

This dramatic DDR5 SO-DIMM price jump tracks closely with desktop RAM, which experienced a similar 500% climb in the past 12 months. But what’s also concerning is that other components have increased in cost, too. Aside from RAM and SSDs, XMG noted that PCBs, electronic components, CPUs, graphics cards, and video memory are also facing similar cost pressures, resulting in higher costs. The war in the Middle East has compounded the situation, especially as increased oil and fuel prices are making air freight costs higher, while also increasing insurance premiums for sea cargo traveling from Asia to Europe via the Red Sea and the Suez Canal.

Because of this, the company says it was forced to increase the prices of several of its models. It also reminded customers that its margins are fixed and that the resulting hikes are solely driven by higher upstream costs. A company representative also said, “If relevant input prices fall again, we will reflect this in our retail prices as well — just as we have done in the past.” This is similar to Framework’s pricing strategy, where it recently cut the memory prices for the Laptop 13 Pro after it was able to find another source for cheaper LPCAMM2

The post also gave a bearish outlook on the memory situation, echoing Micron CEO Sanjay Mehrotra’s words that the DRAM shortages will go well into 2027. This contrasts with Asus CEO Jason Chen’s prediction that component prices will start reversing in the latter half of 2027, and that the long-term predictions of high memory costs are just chip makers wanting to retain high gross margins for as long as possible. Chen said that Chinese memory makers increasing their production would help ease the shortage and that price increases are reportedly cooling as consumers refuse to pay more. Unfortunately, we have no way of knowing which of these two perspectives is correct, and we can only wait and see what happens with memory prices over the next 12 months.

Memory prices are at record highs due to demand from the AI sector and are not going to drop any time soon. In fact, the cost of manufacturing memory chips on a per-area basis can be higher than the price of silicon processed using TSMC's N2 and N3 fabrication technologies, which are used to make compute chips, according to an observation made by Kurnal Insights. While the comparison has merit, it has an important caveat.

Based on media leaks, Kurnal from Kurnal Insights considers that a 300-mm wafer processed using TSMC's N3 technology costs $20,000, which translates to approximately $0.283 per mm² when the wafer price is divided by its area. For TSMC's N2, the analyst assumes a considerably higher wafer price of $30,000, or around $0.424/mm². These calculations are based on unofficial information and do not account for unusable wafer edges, dicing, test structures, defects, or yield, so they should be viewed as nominal wafer-area prices rather than the actual price of usable silicon.

The calculation for DRAM works differently. Kurnal assumes a DRAM price of $1.50 per Gb and then multiplies it by the bit density of different generations. At 0.219 Gb/mm², 1y DRAM works out to $0.329/mm², whereas 1z DRAM with its 0.273 Gb/mm² density reaches $0.410/mm². Finally, 1b DRAM at 0.436 Gb/mm² produces a figure of $0.654/mm², considerably higher than the nominal $0.424/mm² calculated for an N2 wafer.

There is an important distinction here. The N2 and N3 numbers represent assumed prices charged by TSMC for processing a wafer, whereas the DRAM figures represent the potential selling value of the memory contained within a square millimeter of silicon, thus illustrating how much revenue a DRAM maker can theoretically get from a given die area at the assumed memory price.

Interestingly, Kurnal Insights' $1.50/Gb assumption is almost exactly in line with the current spot price of DDR5 eTT memory. According to DRAMeXchange, 16Gb DDR5 eTT chips carried a session-average price of $24.80 on September 21, equivalent to $1.55/Gb. At that price, 1b DRAM with a density of 0.436 Gb/mm² would be valued at approximately $0.676/mm², just 3% above Kurnal's $0.654/mm² estimate.

It goes without saying that producing DDR5 memory is considerably cheaper than making logic chips using TSMC's N3 process technology. However, with DRAM in short supply, memory makers are getting considerably more money for their silicon than they did historically.

There are a few important caveats that make the comparison somewhat less straightforward. The calculations do not account for packaging costs, with logic requiring more expensive techniques. Additionally, TSMC manufactures chips on a contract basis, and the actual price of a processed wafer depends on the volumes, customer, and other commercial terms. Thus, comparing estimated TSMC wafer prices with DRAM spot prices is not exactly an apples-to-apples comparison. Even TrendForce notes that DDR5 spot procurement remains limited and transactions are sporadic, which means spot prices do not necessarily reflect the prices at which Micron, Samsung, and SK hynix sell the bulk of their DRAM.

Therefore, contract DRAM prices would provide a considerably better basis for an economically meaningful comparison. However, we do not know contract prices, and while they are clearly higher than historical memory prices, they may not be as high as spot prices. To that end, we cannot state for sure that DRAM makers get more money for their wafers than TSMC does for its logic wafers.

China's DRAM champion CXMT has begun mass production using its 5th-generation DRAM process technology.

CXMT says its new process technology — G5, as the company calls it — reduces DRAM’s active-area half-pitch to 11.95nm using quadruple-patterning lithography. The 11.95nm half-pitch corresponds to an active-area pitch of 23.9nm, something that puts this particular dimension roughly in the range of other advanced 10nm-class DRAM technologies. However, it cannot be directly translated into a conventional DRAM node designation. Separately, CXMT says its DRAM-optimized high-K metal gate (HKMG) process reduced the height of the core cell array to 6,762nm.

The company also says it modified its process flow and introduced unspecified new materials to enable storage capacitors with a depth-to-width aspect ratio of about 45:1.The figure is certainly difficult to compare directly with competing DRAM process technologies, but SK hynix says that capacitor aspect ratios will need to exceed 100:1 as DRAM critical dimensions eventually fall below 10nm.

A 45:1 aspect ratio means CXMT’s storage capacitors are 45 times deeper than they are wide, which is what enables the company to reduce DRAM cell area and fit more memory arrays onto a wafer and retail predictable capacity. However, increasingly high aspect ratios make etching, deposition, mechanical stability, and ultimately high-yield manufacturing considerably more challenging.

The first disclosed mass-produced devices using G5 are said to be 24Gb LPDDR5X devices, which have already entered mass production. The chips offer 50% more capacity than CXMT's previous comparable products and are available in two package formats for different mobile-device designs. According to the Chinese report, the 24Gb LPDDR5X products are already entering mainstream Chinese flagship smartphones.

A nanometer caveat?

Meanwhile, there are some important caveats.

First up, CXMT's 11.95nm figure represents the active-area half-pitch rather than a conventional process-node designation, so calling G5 a 12nm process is a large degree of simplification at best.

Secondly, the two revealed physical dimensions do not mean technological parity with the latest DRAM processes from Micron, Samsung, and SK hynix, as density, capacitor scaling, transistor characteristics, power consumption, and, arguably most importantly when it comes to commodities, yields matter.

Thirdly, CXMT says G5 provides at least 50% more gross dies per wafer than G4, but without actual numbers, this is obsolete. CXMT also did not disclose yields, which makes it impossible to determine the increase in productivity, not to mention known-good dies or the actual manufacturing cost per bit. Yet again, even a claimed 11.95-class DRAM node is an achievement.

Acer chairperson and CEO Jason Chen is expecting that prices for components will start reversing in the latter half of next year. According to DigiTimes, Chen told reporters that only high-end DDR5 parts like LPDDR5X-9600 and niche CPUs like Nvidia’s N1 and N1X chips are in short supply. Since supplier pricing lags consumer pricing by about a few months, he also added that PC prices will still rise between 5% and 20% towards the end of this year, plateau by the first half of 2027, before finally declining after years of AI-drive hikes.

The AI boom has driven shortages for various PC components, beginning with GPUs in late 2022, before expanding to memory chips by late 2025. This made memory prices climb 500% in 12 months, although the increases have seemingly cooled as consumers refuse to absorb further hikes. Some memory companies like SK hynix are saying that the shortage will be worse next year and that it won’t be until 2030 before pricing will start to normalize. The Adata chief even said that the DRAM shortage would last another 10 years. This is plausibly true, especially as HBM demand from AI hyperscalers remains strong, and the various memory chip fabs under construction aren’t expected to come online until the 2030s.

However, Chen disagreed with this take. He said that the major memory suppliers naturally want to keep their margins as high as possible for longer, “so they keep putting out the message: let me tell you, prices won’t come down until the year 20-whatever.” The Acer chairperson argued that there’s already ample memory and SSD supplies, while the purported CPU shortage is now limited to specific models. He also added that Chinese memory makers churning out cheaper alternatives would disrupt the market — something that SK Group Chairman Chey Tae-won feared. In fact, Acer, alongside HP and Asus, has started using CXMT chips in some of its products, while some Lenovo models sold in Germany were found to have YMTC SSDs.

Nevertheless, he says that price increases are becoming their own trend, saying that SSDs, PCBs, and fiberglass cloth used in motherboards are seeing their own hikes. “A lot of people come and tell us they want to raise prices, and we find it a bit baffling — this needs to go up, too?” Chen said to the reporters.

The overall tenor from Chen is good news, though, if computer manufacturers could finally lower prices after years of shortages and expensive parts.

A new report claims Chinese DRAM champion CXMT is eyeing production of 3D NAND memory. Reuters reports, citing three people familiar with the company's plans, that CXMT intends to build a 3D NAND R&D production line at its second manufacturing facility near Beijing. There is no information on when the experimental production line will become operational, though, given that CXMT's second Beijing fab has not even broken ground yet, the line is at least two or three years away. In addition, the memory maker has established a research institute in Beijing that has NAND flash development among its projects, according to one source. CXMT has not formally confirmed any 3D NAND initiatives, so the information should be taken with a grain of salt.

For now, there are no details on CXMT's 3D NAND architecture, number of active layers, process technology, expected performance, or production capacity. Nevertheless, the report claims that CXMT has already discussed its NAND ambitions with prospective customers. One of them is said to be a recently established company that plans to use CXMT-made NAND devices in storage products aimed at AI and supercomputing applications.

It remains to be seen whether CXMT's 3D NAND project will eventually progress to high-volume manufacturing, but if it does, the initiative will take CXMT beyond its traditional DRAM specialization and directly into YMTC's territory. Until recently, China's two major memory producers had focused exclusively on their 3D NAND and DRAM realms where they have achieved quite a success. Yet, it looks like both companies want to become one-stop shops for DRAM and NAND — just like their bigger rivals Micron, Samsung, and SK hynix — as YMTC is reportedly exploring DRAM production.

While CXMT's alleged plan to build 3D NAND may look somewhat logical from business diversification point of view, it does not make a lot of commercial sense for now.

Or China's industrial policy?

CXMT is China's dominant DRAM producer and posted $22.41 billion in revenue and $11.57 billion in net profit in the first half of the year after years of bleeding money. Despite obvious success, the company is still considerably smaller than the Big Three memory suppliers, which means it has plenty of room to expand in the industry where it already has experience, process technology, fabs, and customers. Furthermore, AI gives CXMT an obvious reason to focus resources on advanced DRAM as well as HBM3E, which are arguably much more strategically valuable products than commodity 3D NAND.

That said, for CXMT, allocating resources to 3D NAND, which requires completely different process technologies, manufacturing expertise, and equipment, does not make much economic sense. However, from the Chinese government's perspective, turning CXMT into the country's second major 3D NAND producer fits almost perfectly within its semiconductor self-sufficiency plans.

CXMT was created with Hefei government money (which held a 37% stake in the company during its IPO) and received support from China's Big Fund, which means that federal and local governments retain control over the company and may shape its strategic decisions, which is exactly what they do. Whether or not CXMT can indeed become a decent 3D NAND maker is an entirely different question.

The memory chip that makes a router remember how to be a router is a world away from the sleek GPUs that are attracting eye-popping investments and alarming valuations, as well as sending stock markets shooting upwards. They’re small, historically have been cheap, and are based on technology that has been around for years.

But despite being a world away from GPUs, the price of these often overlooked chips is skyrocketing, thanks to the all-encompassing memory price crisis caused by the AI boom.

While public and press attention has focused on the expensive chips, there’s an equally large impact beginning to be felt on older, less attractive memory chips. HBM is vital for AI accelerators, while DRAM and high-capacity NAND are being swallowed up by rapidly expanding data centres. A June report from Morgan Stanley reckons memory prices have risen more than sixfold over the last year, breaking with decades in which memory became steadily cheaper as production increased.

It’s not just HBM and DRAM that’s being affected. The crunch is also spreading down into much older forms of memory, including NOR flash and single-level cell, or SLC, NAND. Morgan Stanley expects NOR flash to remain undersupplied through 2026, while JPMorgan has warned its forecasts don’t fully capture a potential supply crunch in SLC NAND. The effects are already showing up in prices. TrendForce says contract prices for both NOR flash and SLC NAND rose by more than 100% during the first half of 2026, while it expects SLC NAND prices to rise another 120% to 170% in the second half of the year compared with the first half.

Picking winners

An increase in prices will have an impact on the tech we use day in, day out. NOR flash is commonly used to store boot and program code, and is a core part of automotive, industrial, and networking equipment. SLC NAND is deployed across a number of uses because of its reliability and endurance when placed in embedded hardware with long lifespans.

Both are vital. And both are being overlooked in favour of higher-margin chips — pushing the supply crunch to tech that previously never faced any issues. “The SLC NAND market is probably under a billion dollars a year,” said Jim Handy, a semiconductor and SSD analyst at Objective Analysis, in an interview with Tom’s Hardware Premium. That tiny scale adds up to a big problem, because it disincentivises any new investment.

“What you've got going on is a purely economic phenomenon,” said Handy. Hyperscalers and cloud providers are “all trying to outspend each other”, pouring unprecedented sums into semiconductors to build AI infrastructure. That willingness to spend big means the most profitable customers naturally move to the front of the queue.

Companies including Nvidia, Broadcom and Marvell need huge amounts of semiconductor manufacturing capacity for chips destined for AI systems. “They’re sucking up all of the wafers,” says Handy. “And then the companies who make NOR flash and SLC are having a hard time getting wafers to build their product, and so they have to raise prices.”

The problem is even starker in the NAND market. Bryan Ao, research manager at TrendForce, told Tom’s Hardware Premium in an interview that major NAND manufacturers, including Micron, Kioxia and SK Hynix, have been cutting the wafer capacity devoted to SLC because they can make considerably more money using it for newer NAND technologies. Ao estimates that a 12-inch wafer devoted to mainstream NAND can ultimately generate close to $20,000 in revenue. Use the same space to produce SLC and the figure is closer to $6,000 to $8,000.

Even if they wanted to, smaller SLC suppliers in China and Taiwan can’t just spin up new production. Lead times for some semiconductor manufacturing equipment have stretched to between 12 and 15 months, said Ao. The result is what he calls “severe undersupply”.

Big prices, big returns

BNP Paribas forecasts the average NAND price will hit $279.50 per terabyte during 2026, up from $73.10 in 2025. JPMorgan expects the memory shortage to persist for at least another two years, with customers getting just 70% to 80% of their orders fulfilled. TrendForce says manufacturers are shifting capacity towards advanced, higher-value memory products, with mature processes increasingly squeezed as a result.

There are some alternatives available. Kioxia says its serial SLC NAND is an alternative to NOR flash. But moving an existing industrial or networking product onto a different chip can itself require engineering work and qualification. Nor is there much incentive for memory manufacturers to fix the problem by building new SLC capacity – which means manufacturers are unlikely to invest billions in capacity whose useful market may disappear. That creates an unusual trap: there may not be enough demand to justify new factories, but there is still more demand than the shrinking supply can satisfy.

Hardware manufacturers can eat the higher component bill and accept lower margins, or pass it on. “We'll just have to either have lower margins, or we'll have to raise the prices to the consumer,” Handy said.

An ongoing issue

The problem is one that seems to have no solution – at least in the short term. Ao expects memory prices to remain high over the next five years and does not expect them to return to 2023 or 2024 levels. That broadly fits with the structural nature of the shortage identified by TrendForce, which says there are no significant capacity expansion plans for NOR flash or SLC NAND.

Handy sees one possible way out, but it is hardly reassuring. “As long as the race between the hyperscalers keeps up to spend, then it will continue to be an issue,” he said.

Handy compares the AI buildout to the internet infrastructure boom of the late 1990s. Rather than enough capacity eventually arriving to restore balance, he thinks spending may simply overshoot what the market can economically support.

“I'm expecting the same kind of a thing to happen here that we've got too many people spending too much money on AI, and not really making any return on it yet,” he said.

Until then, the least exciting memory chips in a computer may become some of the hardest to replace. Or, as Ao put it: “Pretty much we have to get used to this high price, no matter which segment of memory.”

PieceMakers, a Nanya-backed DRAM designer, began trading on Taiwan’s Emerging Stock Board on September 16 at a NT$740 reference price, Cnyes reported ahead of the debut. PieceMakers is not an HBM company. Instead, it bets that inference memory diverges from training memory, President Lee Hsiao-wen told Cnyes, and that DRAM stacked directly on the processor with hybrid bonding can sit between Nvidia’s SRAM-only Groq LPU and HBM. As it stands, design fees, not chips, carry the company's profit, with AI custom-design work accounting for around 40% of the company's revenue in the first half of 2026. Piecemakers Chairman Joseph Ting told TechNews that its first volume customer program will not contribute to the company's financials until 2027 at the earliest.

At roughly 60.4 million shares outstanding, that price values the company at around NT$44.7 billion (around $1.4 billion). Taiwan's Emerging Board is the Taipei Exchange's pre-listing market, not a main-board IPO, so shares trade through market makers ahead of any formal listing application. The stock ended its first session at NT$915, 23.6% above the NT$740 reference price, after opening at NT$1,035 and trading as high as NT$1,205.

Nanya Technology is the largest holder of Piecemakers, at 33.96%, after selling 715,000 shares at NT$740 to seed the float, a disposal it disclosed in a Sept. 9 exchange filing reported by Knews.

What PieceMakers sells

PieceMakers was founded in January 2006 in Hsinchu, Taiwan, led by chairman Joseph Ting and president Lee Hsiao-wen. Historically, the company has designed standard SDR/DDR DRAM and known-good-die (KGD) parts through representatives in China, Japan, France, Turkey, and Israel. Now, the company seeks to shift from direct product sales to custom design services, paid as non-recurring engineering (NRE) fees, and then to IP licensing, royalties, and turnkey production from 2027, the company said at its Sept. 7 briefing, UDN reported.

Revenue from the AI custom design unit has risen from around 4% in 2024 to almost 40% in the first half of 2026. The products behind that increase are HBLL (High Bandwidth, Low Latency RAM), a 2D die rated at 144 GB/s that was taped out in 2016 for Intel’s HPC line and published at ISSCC in 2017, and HiBaLL, the 3D-stacked version rated at more than 1 TB/s, the company claims.

The company described its customers to Cnyes as developers of cloud AI inference accelerators, international semiconductor players, and North American customers, with some programs in design and verification, and none named. Qualcomm CEO Cristiano Amon’s Computex keynote backdrop in June listed PieceMakers among Taiwan ecosystem partners, although neither company has defined the relationship. The takeaway is that the profit is in design fees and not chips. The margin curve matches a pre-royalty Non-Recurring Engineering (NRE) business, rather than a traditional memory vendor.

Why Nanya is chasing this instead of HBM

Nanya’s AI-memory strategy is custom and edge rather than HBM3E. PieceMakers is the first half of a strategy laid out in 2024. On Aug. 7, 2025, Nanya announced a joint venture with Etron Technology, a Hsinchu-based chip designer, capitalized at NT$500 million, with 80/20 ownership. The venture was envisioned to design custom high-bandwidth memory for edge AI devices rather than for data center accelerators. Nanya president Pei-Ing Lee said earlier in 2025 that the company would not compete in HBM3 or HBM3E, TrendForce reported.

Both halves of the strategy rely on Formosa Advanced Technologies, the Formosa Plastics Group’s test and assembly affiliate, for packaging. It is building the through-silicon-via (TSV) and die-stacking processes that both need. The surge in DRAM pricing has made commodity memory Nanya’s real business, which leaves PieceMakers a cheap side bet that has become a windfall. Nanya took advantage of this by selling around 3% of its stake in a move that suggests it is acting more as an investor than a parent building a memory stack.

The inference gap

Groq is an AI inference startup that Nvidia struck a $20 billion licensing-and-talent deal for on Dec. 24, 2025. Nvidia announced its first chip built from that, the Groq 3 LPU (language processing unit), Nvidia’s SRAM-based inference chip, at GTC, its annual developer conference, in San Jose earlier this year.

There is no HBM or DRAM on the Groq 3 LPU. Instead, it uses 512MB of SRAM on the die to deliver 150 TB/s of bandwidth against 22 TB/s from the 288GB of HBM4 on each Rubin GPU. It’s a decode-only co-processor with Rubin handling the prompt prefill, displacing Nvidia’s Rubin CPX from the roadmap.

At Hot Chips 2026, Nvidia’s Igor Arsovski, Groq’s former chief architect, said the rack is in production and published the first third-party benchmark: 3,431 tokens per second on a 100K-context, 31B-parameter model, at about four times the next-fastest public endpoint, in a single-request test that we noted isn’t directly comparable to the shared endpoints it was measured against. The cost is capacity: at 512MB per chip, a 256-LPU rack holds 128GB, with the model needing 62 chips at FP8 just to hold the benchmark weights. Nvidia accepted that trade for decode speed, which supports Lee’s point that the market leader’s newest inference product contains no HBM.

At Hot Chips, Samsung’s Sangwook Han laid out a three-phase HBM roadmap that ends in zHBM, which is DRAM stacked directly on top of the processor rather than beside it on an interposer. Samsung projects about 70% less I/O power usage than HBM5 with roughly 2.3x the bandwidth of a four-stack HBM4E system, with zHBM’s stacks limited to about four-high due to heat, at around 100W less. This would require wafer-on-wafer hybrid copper bonding and tight co-design between DRAM and SoC teams. SK hynix’s Jaesik Lee, VP of package engineering, said on Aug. 23 that hybrid bonding won’t be ready for HBM4E, leaving HBM5 as the earliest point. Counterpoint Research expects full-scale HBM production with the technique around 2029–2030.

PieceMakers offers a different version. Instead of the GPU-plus-HBM 2.5D layout, it bonds the DRAM stack directly onto the processor, wafer-on-wafer, with hybrid bonding instead of microbumps. This fits far more connections with the finer pitch, improving bandwidth, and the shorter path reduces both latency and power consumption. The company puts its wafer-on-wafer product at more than 2 TB/s per layer with latency under 20ns, the company figures, but the target is more capacity than SRAM at a lower cost and power than HBM. PieceMakers is not doing the TSV or hybrid bonding itself, as this is handled by the customer’s logic wafer foundry, Ting added. This custom service promises a 2027 date against Samsung's undated roadmap end and SK hynix's HBM5-at-the-earliest timing. Nvidia and Samsung have each, in their own way, settled the architecture question, with the open question being the customer.

Yield is the product

Lee also said that yield is the biggest hurdle to wafer-on-wafer mass production. The repair architecture has to be designed in, with testing before bonding, after bonding, and then after logic integration. Lee’s own example was 80% yield per layer, at which four layers come out at about 41% and eight at 17%. Our recently-published hybrid bonding state of play covers the process side in more detail.

This better puts into perspective why the company sells repair and known-good-die IP as much as it does bandwidth. It’s also why an IP-and-royalty model fits the strategy — yield IP is portable across customers while a bandwidth number is not.

What to watch

For PieceMakers, AI revenue remains primarily NRE until there is a first named customer, with the first volume program expected in 2027 at the earliest. Ting said that Nanya’s Q3 2026 results, which come in late October, will gauge the PieceMakers gain and reveal further financial information. SK hynix’s hybrid-bonding timing, which targets HBM5 at the earliest, is the current benchmark, although its 16- and 20-layer memory stacks are a separate problem from a few DRAM layers on a logic wafer. Qualcomm may also describe its relationship with PieceMakers more formally.

PieceMakers is likely to end up as an IP licensor with a small number of accelerator customers and turnkey volume through Nanya and Formosa Advanced Technologies. The technology risk is the foundry’s and the customer’s, which is why PieceMakers’ design-fee model works. PieceMakers is expected to benefit from a 2027–2028 ramp, later than Ting’s 2027. If the largest HBM maker won’t bond its own memory this way before HBM5, PieceMakers’ own 2027 date is the one it must meet.

Micron this week introduced its first 512GB DDR5-9200 memory module that is designed for servers used for applications that demand a lot of memory. The new modules — which are currently being validated by AMD and Intel with their next-generation server platforms — will enable server makers to build machines with up to 12TB of fast memory. What remains to be seen is the price of such modules and servers.

To build its 512GB DDR5 RDIMM, Micron uses advanced packaging that stacks multiple DRAM dies vertically and connects them using through-silicon vias (TSVs). The company does not disclose which memory devices and how many of them it uses, but claims that a single 512GB RDIMM consumes over 60% less operating power than four 128GB modules — based on 16.0W for one 512GB module compared with the 44.2W total for four 128GB modules — which suggests that we are dealing with fairly advanced ICs.

Micron's 512GB module is not the industry's first 512GB DDR5 RDIMM — that achievement belongs to Samsung — but it is certainly the industry's first 512GB module certified to operate with a 9200 MT/s data transfer rate with standard 1.1V voltage (which implies on usage of Micron's 16Gb DDR5-9200 devices made on its 1γ (1-gamma) fabrication process that uses EUV lithography and consumes 20% less power than predecessors, though we are speculating).

Truth to be told, 512GB DDR5 memory modules are rather niche products, which is perhaps why Samsung's 512GB RDIMMs formally introduced in 2021 have not become widespread even after AMD and Intel introduced processors with over 100 cores. Micron positions its 512GB DDR5 RDIMM primarily for servers running analytics, in-memory databases, simulations, virtualization, agentic AI, and other workloads demanding high-core-count processors and plenty of memory. As processors with 200 or more cores emerge, 512GB modules may become more relevant as 12TB of memory in a server running two 256-core CPUs means 24GB per core, which no longer looks particularly excessive for applications like in-memory databases, analytics, or caching.

Micron claims that in memory-constrained Spark Support Vector Machine (SVM) analytics workloads, systems featuring 512GB memory modules can provide up to 1.4 times the performance of configurations equipped with 256GB DDR5 modules, though the company does not disclose how much memory in total these systems use. Micron also says the higher-capacity memory can increase throughput and concurrency for memory-intensive database and caching applications such as RocksDB and Redis.

AMD and Intel are working with Micron to qualify the new modules for their upcoming server platforms. Micron plans to begin volume production of its 512GB DDR5 RDIMMs sometime in the second half of 2027 and intends to align the schedule with customer requirements.

One of the more pressing questions about Micron's 512GB DDR5-9200 memory modules is their price. A 256GB DDR5-6400 RDIMM currently retails for around $19,000. Given the unique proposition that 512GB modules have for memory-constrained applications, such modules can cost significantly more than 256GB memory sticks, which will not help their broad adoption.

A computing enthusiast has shared images of a fat stack of DDR4 RAM sticks that they found at home. VastOption8705 told other tech fans on Reddit that they “found 10k worth of RAM sitting in my garage.” We count 30 sticks of DDR4-2666, and three sticks shown separately are all 64GB modules. If they are all 64GB modules, that number of sticks would add up to 1,920GB of RAM…

How did this huge amount of RAM end up in VastOption8705’s garage? The story goes that the Redditor was allowed to keep an old server from their workplace. Such 'generosity' isn’t unheard of, and it might have actually saved the company some recycling fees.

Is server DDR4 useful?

Numerous comments on the Reddit post jokingly pitch for RAM stick donations. But they might be barking up the wrong tree. Looking more closely at the sticks, where the labels are clearly readable, reveals that they are Samsung 64GB DDR4 ECC registered DIMMs (RDIMMs).

These kinds of RAM sticks are commonly used in servers built around Intel Xeon, AMD Epyc, or AMD Threadripper platforms. Sadly for their market value and the folks on Reddit hoping for some spare RAM, they aren’t consumer PC friendly. Even if you have a DDR4-supporting motherboard, these ECC RDIMMs will be both physically and electrically incompatible with your home creator/gaming PC.

Pricing and the Australia question

A quick poke around eBay U.S. listings shows that a single 64GB DDR4-2666 stick like those shown can be bought for between $350 and $425. So, we could roughly value the 30 sticks at $12,000 if a price of $400 per stick were achieved. The OP’s touted $10K valuation wasn’t far off. But if VastOption8705 lives in Australia, as they seem to, and guesstimated the value in Australian dollars, AU$10,000 currently equates to ~US$7,200 – quite low.

If you have spare RAM in your garage, don't share your address on public forums. The best I could find is a pair of 8GB DDR4 SO-DIMMs in my drawer. I also had some 30-pin SIMMs, SDRAM, PowerMac ROMs, and DDR3 modules probably worth just pennies, despite the RAMpocalypse.

The saga involving Chinese DRAM maker CXMT's alleged theft of Samsung's trade secrets is going strong. The South Korean court case already includes multiple convictions, two of which carry prison sentences for ex-Samsung engineers. The latest chapter is a doozy, though. Korean publication NoCut News spilled the chips on Project Hefei, a purported CXMT roadmap outlining long-term planning about said technology "acquisitions," personnel poaching, and production tape-out — all key pieces that may have directly led to CXMT's ascension to 10% of the global DRAM market.

According to leaked court documents, the prosecution says that Project Hefei was CXMT's entire DRAM development plan and was spearheaded by the firm's head of development (formerly Samsung's DRAM development lead), around August 2016 — not much longer after CXMT itself was created in June 2016.

In brief, the purported plan was to nab Samsung's Process Recipe Plan (PRP) by September 2016, poach key Samsung engineers by October 2016, have R&D complete in July 2017, and start making DRAM wafers by August 2018 at a rate of 10,000 a month. NoCut says the PRP dataset comprises 620 steps in DRAM manufacturing and includes data on equipment, consumables, and production methods.

The report states that in August 2016, CXMT first attempted to make wafers of 18nm chips by relying on the collective memories of the Samsung engineers it had hired away. Those recollections apparently proved insufficient, so after allegedly gaining illicit access to Samsung's PRP, CXMT prepared its own document in September 2016. The leaked data even included specific equipment suppliers and model numbers.

CXMT's "new" PRP was then handed out to key specialists, many of them ex-Samsung engineers, whom the prosecution says ought to have immediately recognized the data as originating from the Korean firm. The document apparently included notation and notes on process developments that were all unique to Samsung. A convicted ex-Samsung researcher with the surname Jeon, previously sentenced to 7 years in prison for manually copying parts of the PRP before leaving for CXMT, testified in this case as a witness.

The whole CXMT debacle has been playing out in South Korean courtrooms since January 2024 and is arguably far bigger than just "a company stole some tech from another." A decade ago, most of the DRAM market was taken by the Big Three: Samsung, Micron, and SK hynix. CXMT was created in June 2016 in Hefei (hence the project name), with a modest government investment of around $1.9 billion USD, allegedly with no R&D facilities whatsoever or any plan for research.

Going from zero facilities and institutional expertise to DRAM wafer production in little over two years would be an unprecedented feat, and presumably nigh impossible without the alleged IP theft; getting just the memory fab up and running usually takes two to four years, let alone any time for research. The firm claimed in 2019 that it designed its then-new 8 Gb DDR4 chips entirely in-house as a "leapfrog, independent" technology and began selling DRAM chips locally.

Then the AI locusts charged in and ate every chip on the planet. This demand resulted in explosive growth for CXMT, from an estimated 4% of the global DRAM market in Q2 2025 to around 10% in Q2 2016, marking the first time in over a decade that the Big Three held less than 90% of the pie.

Production capacity expanded to three 12" wafer fabrication facilities, expected to churn out a collective 350,000 wafers until the year is done — close to the same figure that Micron produces, of 375,000 to 385,000. CXMT is also planning to open a second fab in Beijing, aiming to produce over 600,000 wafers per month once it's online.

Furthermore, CXMT's gains aren't coming just from its DRAM market share. Revenue grew 716% in Q2 2026 alone, and its IPO on the Shanghai STAR Market in July 2026 saw its stock climb 466%, netting the firm a cool $8.6 billion USD and making it the most valuable chipmaker in the Chinese stock market.

About 70% of that money is reportedly going towards further expansion of DRAM production, rather than pricier, more complicated HBM. However, the firm has supplied HBM3E samples to Alibaba's T-Head and Cambricon, even as Samsung and SK hynix enter HBM4 production.

As of the South Korean prosecution's last tally in December 2025, Samsung's damages due to CXMT's alleged machinations ascended to "at least tens of trillions of won." A back-of-the-envelope extrapolation, considering quite a while has passed, might suggest a figure in the range of ₩40 trillion, or $29.5 billion, and rising exponentially.

The lasting impact on the memory market and technology in general is going well beyond plain number descriptors, though. All things considered, if the allegations are true, then CXMT's machinations resulted in a geopolitical-scale economic event. Dr. Evil would be proud.

The goal of next-generation HBM5 memory specification is to double performance and increase power efficiency compared to HBM4E, Samsung announced at the 'Memory Executive Summit,' an event that precedes 'Semicon Taiwan 2026.' Considering that it is barely realistic to double the data transfer rate of HBM4E in just one generation, the comment made by Samsung may imply that HBM5 will double the number of interface pins to boost bandwidth.

The goal of HBM5, which is currently under development, is to double the performance and improve the performance per watt by 20% compared to the HBM4E generation, according to Choi Jang-seok, the head of the product planning team of the memory business department of Samsung Electronics DS division. Previously, Samsung announced that its HBM5 memory stacks will feature a heat path block (HPB), which will reduce thermal resistance by 20% and simplify cooling of HBM5 modules.

Doubling HBM5’s per-stack memory bandwidth would result in peak bandwidth of around 4 TB/s per stack already in 2028 – 2029. TSMC expects AI accelerators to get to 20 – 24 HBM5/HBM5E per package configurations by the end of the decade, which means that these systems-in-packages will get a whopping 80 TB/s – 96 TB of memory bandwidth just several years down the road.

Although both DRAM makers like Micron, Samsung, or SK hynix as well as developers of HBM controllers and PHYs like Cadence, Rambus, or Synopsys already offer HBM4/HBM4E controllers and interfaces rated for 16 GT/s data transfer rates, the official JEDEC transfer rate for HBM4E will be around 12 GT/s.

If Samsung expects HBM5 to deliver twice the bandwidth of HBM4E, the HBM5 specification must either double the per-pin data transfer rate from 12 GT/s to 24 GT/s, double the interface width from 2,048 to 4,096 bits, or combine a wider interface with a higher data transfer rate. Increasing HBM5 memory stack interface width to 4,096 bits has so far been envisioned by KAIST and Marvell; however, this is certainly not an even semi-official confirmation of the specification's target.

From a performance-per-watt perspective*, widening the interface is generally easier than doubling the per-pin signaling rate. Higher per-pin speeds require faster drivers, receivers, clocks, equalization, tighter timing margins, and a more sophisticated PHY since maintaining signaling integrity at speeds well beyond 20 GT/s is not easy. But while a wider HBM interface moves more bits in parallel at a lower speed per wire, going from 2,048 to 4,096 pins means twice as many TSV/I/O paths, drivers, receivers, bumps, more complicated routing, and extremely complicated base die. So while a 4,096 I/O at moderate speed is probably best for pJ/bit, the interface/package complexity gets so extreme that it may offset the gains. Furthermore, such a wide interface Perhaps a 3,072-bit interface combined with a moderate increase in data transfer rate would be a reasonable engineering compromise, though engineers involved in JEDEC’s decision-making process may think otherwise. In any case, for now, any discussion of HBM5 specifications remains speculative.

Nonetheless, the target to double the bandwidth of HBM4E (2 TB/s per stack) within one generation is clearly a very aggressive one.

*It should be noted that achieving a 20% higher energy efficiency can be achieved not only by increasing performance, but by improving DRAM process technology, optimizing base die, lowering TSV I/O voltages, architectural changes, or power management.

Samsung has unveiled a three-phase roadmap to progressively transform high-bandwidth memory (HBM) into an integrated memory-and-compute system, culminating in the company's zHBM architecture, which places the processor directly beneath the DRAM stack and eliminates the conventional 2.5D interposer link between the two. Detailing the roadmap at Hot Chips 2026, Samsung's Sangwook Han, of the company's DRAM design team, identified the base die as the key enabler of the evolution, which began with the company’s decision to manufacture the HBM base die on an advanced logic process.

In conventional HBM, the base die (B-die) was fabricated on the same DRAM process node as the core dies (C-dies) in the stack above. Starting with HBM4, Samsung moved the base die to a 4nm logic process, primarily to reduce power draw and minimize die area. Additionally, it gave Samsung a much more capable piece of silicon.

The company contends that a die built on the same class of logic process as XPUs could do much more than serve as a data interface. Samsung now plans to progressively offload more functions into the base die, eventually removing the physical gap between memory and the XPU entirely.

The current state of HBM and its growing constraints

The current HBM architecture comprises multiple DRAM core dies stacked vertically on a base die and connected through thousands of TSVs. The stack sits beside an XPU on an interposer, with the base die bridging the memory and compute silicon.

Bandwidth has been the main driver of HBM’s evolution. The current HBM4 stack has roughly 1 to 5 TB/s of bandwidth obtained through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each. These figures are expected to rise with upcoming HBM generations. The problem is that conventional ways of scaling bandwidth present significant challenges.

TSV signaling speed is difficult to increase, so HBM generations have added more TSVs instead. However, this consumes area and forces tighter TSV pitches. The PHY has also grown more demanding. HBM4 doubled the data I/O count from 1,024 to 2,048 DQs, and signaling speed keeps rising. Power is an even bigger issue. While energy per bit is improving, total HBM power continues to rise as bandwidth is scaling faster. Samsung says this is why HBM4 moves the base die to an advanced logic process, as the denser, more efficient logic reduces power draw.

This move underpins and enables the three-phase plan. An advanced logic node shrinks the interface circuitry while enabling the HBM base die to perform functions previously handled by the processor. Samsung calls this direction custom HBM, or cHBM, which keeps the conventional DRAM stack but customizes the logic underneath it for a specific accelerator.

Phase 1: Reclaim XPU area

The first phase is about handing processor area back to compute in what Samsung calls “XPU area reclamation.” AI accelerators are hitting familiar scaling walls, such as slowing process scaling and dies pressing against reticle and interposer limits. To expand compute, Samsung plans to evict non-compute blocks, moving their functions to the base die’s underutilized silicon.

The first target is the HBM Physical Interface (PHY), one of the largest blocks on the base die. Samsung proposes replacing the traditional interface with a much smaller die-to-die (D2D) link. On an 11 × 12.8mm HBM4 base die, the conventional PHY occupies more than 8 × 4mm, while the custom HBM D2D block is about 8.5 × 1.5mm, with channel depth cut from 5.5mm to 2mm. Because the matching interface on the XPU shrinks too, Samsung also reclaims processor silicon.

Conversely, shrinking the same power into less silicon increases power density and creates hotspots. Samsung’s answer is a Heat Path Block (HPB) that provides an alternative route for heat to exit the concentrated interface region. The company says an HPB covering more than half of the PHY can slash peak temperature by more than 35%.

The bigger Phase 1 change is moving the memory controller from the XPU to the custom HBM base die. Han estimated controllers account for 5 to 10% of an XPU's area — space that, refilled with compute, could yield a 10–20% performance gain. Moving the controller next to memory also enables a new SRAM-based repair scheme in which failed C-die addresses can be redirected to SRAM on the base die, avoiding the need to sacrifice an entire spare row or column for a single defective cell.

Phase 2: Making the die a more useful smart memory subsystem

Even with the controller moved in, Samsung says a substantial portion of the base-die area remains unused. Phase 2 fills that space with more functions, first with some relatively straightforward additions. The company proposes SoC-like telemetry and reliability features, including thermal, voltage, process, and aging sensors, as well as more advanced self-test hardware.

It also wants to use the edge of the base die for direct memory expansion, arguing that capacity is becoming as important as bandwidth. Dedicated controllers and PHYs could connect a secondary tier of external memory directly to custom HBM, rather than going through conventional PCIe expansion. Han said that extra memory could be LPDDR or even HBM, offering higher bandwidth and lower latency than PCIe-based memory extension.

Last in Phase 2 is compute — right on the base die. Samsung wants to place selected processing elements (PEs) under the DRAM, offloading memory-bound work while compute-heavy operations remain on the GPU. It calls this broader 2.5D architecture advanced HBM (aHBM), citing benefits such as less traffic across the interposer and reduced latency and I/O power draw.

Phase 3: zHBM goes fully 3D, placing the processor underneath the memory

Phase 3 appears to be Samsung's most radical step, with the company halting HBM architecture optimization and rebuilding it instead. Introducing zHBM, Samsung's “ultimate solution” for maximizing bandwidth under future AI's brutal power limits.

The zHBM concept eliminates the conventional side-by-side arrangement of XPU and HBM across an interposer. Instead, the processor sits directly beneath the DRAM stack in a true 3D structure. This architecture allows Samsung to replace the large edge PHY with distributed I/Os spread across the die. Data no longer has to travel laterally across an interposer, thereby shortening the physical path and eliminating the need for conventional HBM PHY and D2D link interfaces.

Samsung says the biggest payoff is power. Its projections show zHBM cutting I/O power by around 70% compared with HBM5. In another example, Samsung models roughly 2.3X more DRAM bandwidth while reducing memory power by about 100W compared to a four-stack HBM4E system.

On the flip side, thermals are the obvious complication. Han said Samsung is targeting roughly four-high zHBM stacks, compared with the much taller 12-high or 16-high configurations possible with conventional HBM, specifically because of heat. Distributed I/O helps by spreading the circuitry rather than concentrating it into hotspots, but zHBM is a balancing act involving capacity, bandwidth, heat, and physical integration.

Manufacturing zHBM will also require advanced wafer-on-wafer bonding and hybrid copper bonding to meet the required I/O density, with a much tighter co-design process between the DRAM and SoC teams. Samsung did not provide a firm launch date or timeline for the phases. However, HBM4’s 4nm logic base die is the concrete starting point, while cHBM and aHBM are nearer-term extensions, with zHBM as the long-term endpoint.

China's DRAM champion ChangXin Memory Technologies (CXMT) has started risk production of HBM3E memory, The Information reports. Although CXMT remains a generation behind the big three memory manufacturers, which are mass producing HBM4, it goes without saying that reaching the HBM3E milestone highlights the company's rapid technological progress.

Specifications of CXMT's HBM3E products are unknown, though keeping in mind that we are dealing with risk production, specifications of actual HBM3E products from CXMT may differ from risk production samples. Meanwhile, general JEDEC specifications are well known: HBM3E modules feature a 1,024-bit-wide memory interface, supports data transfer rates up to 9.6 GT/s per pin, and can stack 8 or 12 memory devices. Depending on the exact speed bins, HBM3E can provide up to 1.228 TB/s of memory bandwidth.

Capacity of actual memory stacks depends on the number of DRAM dies used in that stack: HBM3E products can offer 24GB of capacity using an eight-die stack or 36GB using a 12-die stack when built with 24Gb DRAM devices.

Several Chinese developers of advanced processors are already evaluating CXMT's HBM3E with their processors, including Alibaba Group's T-Head and Cambricon Technologies, according to the report. If testing and qualification proceed as planned, these companies could begin using CXMT's HBM3E in commercial products as early as next year.

Since every HBM package requires multiple large DRAM dies, growing HBM output could consume considerable DRAM manufacturing capacity, which is when CXMT's aggressive capacity expansion will be useful.

CXMT's manufacturing of HBM3E is important for multiple reasons and arguably the HBM3E generation itself matters less than CXMT's ability to manufacture usable HBM at all.

Firstly, HBM is one of the critical components of modern AI accelerators, so if CXMT's HBM3E qualifies with processors from Cambricon, T-Head, and other Chinese designers, China becomes less dependent on Micron, Samsung, and SK hynix for building high-performance AI hardware.

Secondly, despite being a generation behind HBM4, HBM3E is still very capable memory and can provide several TB/s of bandwidth, sufficient for powerful AI accelerators. In fact, many Chinese developers of AI accelerators do not necessarily need HBM4/HBM4E to build useful AI systems.

Thirdly, HBM is substantially harder than making ordinary DRAM. CXMT needs not only competitive DRAM dies, but also high-yield stacking, through silicon vias (TSVs), very fine interconnects, thermal management, packaging, and testing. Reaching HBM3E risk production proves that China's memory ecosystem is advancing beyond simply manufacturing commodity DRAM.

Finally, there is also an important geopolitical angle. Export restrictions constrain China's access to advanced AI processors and HBM, so a combination of Chinese-designed accelerators, CXMT HBM3E, and advanced domestic packaging indicates that China becomes one step closer to semiconductor self-sufficiency.

ChangXin Memory Technologies (CXMT) has announced in a social media post that it has started mass production of LPDDR6 memory for a Xiaomi smartphone, Reuters reports. This is not entirely unexpected given the general LPDDR6 mass-production timeline, but the announcement is still surprising because two China-based companies are ahead of industry announcements. Yet, there are caveats.

LPDDR6 is perhaps the most substantial upgrade to the GDDR-class memory ever. Firstly, it uses PAM3 signaling, which encodes 3 bits of information across two symbols, compared with the NRZ signaling used by LPDDR5/LPDDR5X. Second, the data transfer rate increases to 43.2 GT/s. Third, the reduced I/O width from 32 bits to 24 bits requires rework at both the hardware and software levels.

Given the differences between LPDDR5 and LPDDR6, the most important factor here is not exactly LPDDR6 manufacturing, but a broader view.

On the one hand, CXMT reached mass production of LPDDR6 roughly at the same time as the established DRAM leaders, meaning it is on par with them, if not ahead. This marks a substantial change from earlier generations, when Chinese DRAM technology generally lagged considerably behind Samsung, SK hynix, and Micron.

On the other hand, reaching mass production does not necessarily mean that CXMT has achieved full technological or manufacturing parity with its larger rivals. The official announcement covers only one smartphone maker and one model, meaning CXMT's LPDD6 still has to pass validation for other handsets and other makers.

Still, the significance of CXMT's announcement is hard to understate. CXMT is no longer merely catching up by introducing a new memory generation years after its international competitors. With LPDDR6, CXMT is entering the market during the standard's initial commercialization, which means the technology gap between China's leading DRAM producer and the industry's established players has narrowed considerably.

Which brings us to the question of whether CXMT can maintain this pace. Developing a competitive LPDDR6 device is one thing, producing it at high yields and in sufficient volumes to supply major customers is another. For now, we are talking about a niche smartphone with memory operating at undisclosed performance.

If CXMT can mass-produce LPDDR6 for the whole market and manufacturers, we may well have seen the change of the industry leader. Yet, given one niche device, we certainly cannot say so for now.

China's leading DRAM producer ChangXin Memory Technologies (CXMT) has filed a lawsuit against the U.S. Department of Defense in an attempt to overturn its classification as a company linked to China's military, Reuters reports. CXMT claims that it has no connection to the Chinese People's Liberation Army, and argues that the Pentagon's decision lacks supporting evidence, violated due-process requirements, and has damaged both its business and reputation.

The Pentagon initially classified CXMT as a Chinese military company in January 2025, when Joe Biden was the president. The Trump administration subsequently maintained the designation when the Defense Department updated the list in June. CXMT says it spent more than a year supplying information to the Defense Department in an attempt to overturn the classification and remove itself from the list.

The company claims the DoD published a notice in February indicating that CXMT would be taken off the list but withdrew that notice later the same day without any explanation. In June, the Pentagon classified CXMT as 'directly affiliated with MIIT and indirectly affiliated with SASAC and MIIT.' MIIT is China's Ministry of Industry and Information Technology, whereas SASAC is the State-owned Assets Supervision and Administration Commission of the State Council, an organization that formally owns the government's stakes in non-financial state-owned enterprises.

While CXMT memory can certainly be found in systems used by the PLA or China's secret services, this does not automatically make CXMT a direct supplier to these entities and therefore does not prove that CXMT is a Chinese military company.

CXMT points out the Pentagon's original motivation to include the DRAM maker in its list was a remarkably weak-looking 'military grade' argument. According to the complaint, DoD's 2024 report said CXMT contributed to China's defense industrial base partly because its DRAM is dual-use and cited an advertisement describing CXMT products as 'military grade.' CXMT says that advertisement came from an unauthorized distributor, which later admitted the characterization was erroneous.

In addition, CXMT claims that its DRAM products conform to JEDEC commercial standards and lack the requirements imposed on Chinese military-grade semiconductor components involving areas such as temperature, packaging, testing, and military oversight. Also, it says that should its products be made in the U.S., they would be classified as for 'purely civilian uses' and that it 'does not hold any licenses to manufacture products for military use.'

Inclusion on the Pentagon's list of companies linked to the Chinese military can result in restrictions involving U.S. government contracts, something that CXMT barely seeks. But more importantly, it can affect a company's commercial relationships (as many companies do not want to be affiliated with companies linked to the Chinese military) and reputation. Indeed, CXMT claims that since January 2025 the designation has continuously hurt it commercially and reputationally, and that the lawsuit is intended to protect its business interests.

The ongoing DRAM crisis has led to a sharp increase in laptop prices, with manufacturers facing exponentially high component costs, particularly memory and SSDs. The situation has created a growing gap in the affordable gaming laptop segment, with most entry-level models becoming increasingly expensive. In its response, MSI has introduced the new Katana 15 HX C14 that features Intel’s 14th-gen Raptor Lake Refresh processors along with support for both DDR5 and DDR4-3200 memory.

Depending on the region, MSI will be offering the value-focused gaming laptop in two variants, featuring dual SO-DIMM slots with either DDR4 or DDR5 compatibility. For context, a 32GB (2x16GB) DDR4-3200 SO-DIMM memory kit can be purchased for around $200, while a DDR5-6000 kit goes for over $400. MSI did not specify the DDR4 capacity as standard, only that the laptop supports up to 96GB, which seems unlikely given no 48GB DDR4 SO-DIMMs exist.

Configurable with up to a 24-core Intel Core i9-14900HX processor, the laptop should offer plenty of CPU performance for demanding tasks besides gaming. It will be available with up to an Nvidia RTX 5070 laptop GPU offering support for the latest AI features, GDDR7 memory, DLSS 4.5, and real-time ray tracing. MSI claims that the Katana 15 HX C14 is tuned for up to 170W of combined CPU and GPU power, while the cooling system with dual fans, three heat pipes, and four exhaust outlets helps in sustained performance. There are also dual-PCIe Gen 4x4 M.2 slots, allowing gamers to add a separate SSD dedicated to their gaming library.

Display options include a 15.6-inch IPS panel available with either QHD (2560x1440) resolution that supports up to a 165 Hz refresh rate or FHD (1920x1080) resolution with up to a 144 Hz refresh rate. In terms of design, the laptop comes in a stealthy black finish with textured slash patterns inspired by traditional Japanese blades along with bright red logos. The chassis measures 22.9mm in terms of thickness and weighs 4.62 pounds, making it fairly compact for a 15-inch gaming notebook.

Other notable features include support for Wi-Fi 6E and Bluetooth 5.4, a 4-Zone RGB gaming keyboard with 1.7mm key travel, a 240W power adapter, USB Type-C with Power Delivery 3.0, a 60Whr battery, and DTS-enhanced dual 2W speakers. According to MSI, the new Katana 15 HX C14 will be available globally, although there's no pricing information at the moment.

High-bandwidth memory (HBM) is one of the key components of AI systems that is not currently assembled in the U.S., but this is going to change in 2029, when SK hynix initiates packaging of HBM memory modules at its facility in Indiana. This week, the company held a groundbreaking ceremony for its HBM production base in America and intends to start construction of the plant shortly.

SK hynix's HBM production site in West Lafayette, Indiana, will specialize in advanced packaging, testing, and R&D of HBM. The facility is set to cost the company around $4 billion, which highlights its advanced technology capabilities as well as vast capacity. The DRAM maker expects to open the cleanroom by October 2028 and begin volume production of next-generation HBM in the second half of 2029, which is about a year later than originally envisioned. Once commercial operations kick off, SK hynix expects the Indiana site to employ around 1,000 people.

Despite being described as an HBM production base, the Indiana site will not manufacture the DRAM wafers, but will package HBM stacks using DRAM wafers produced in South Korea and base dies produced in South Korea, Taiwan, or the U.S. Nonetheless, SK hynix intends to market the resulting devices as its first U.S.-made next-generation HBM products. Meanwhile, as custom HBM-class memory gains traction in the second half of the decade, assembling such stacks close to American customers may be particularly important both for SK hynix and its clients, as it enables SK hynix to shrink the feedback loop significantly.

In addition to building the advanced packaging and testing plant, SK hynix will also establish an Advanced Packaging R&D Testbed next to the manufacturing lines. The facility will enable SK hynix to work with customers, universities, and commercial partners on future packaging technologies, build prototypes, and quickly validate their performance and manufacturability in an actual production environment. In the era of customized HBM, such a facility could become a significant competitive advantage for SK hynix.

SK hynix also signed a memorandum of understanding with Purdue University to jointly research system integration and advanced packaging technologies, including HBM.

"The United States is the epicenter of AI innovation, bringing together premier customers, top-tier R&D capabilities, and partners and Indiana fab will become a gateway to deliver first Made in USA HBM products," said Kwak Noh-Jung, CEO of SK hynix. "We will expand our investments and collaboration in the U.S., grow together, and become the most trusted partner in shaping the future of AI in America."

Nvidia's NVLink Fusion program gives the company's partners the building blocks necessary to connect custom chips with the NVLink scale-up domain used to join many separate processors into a single coherent system like the Vera Rubin NVL72 rack-scale accelerator. Today, Nvidia is adding a new building block to that toolkit: NVHBM, a custom implementation of the high-bandwidth memory that underpins practically every AI accelerator in use today.

As Nvidia describes it, NVHBM is a custom HBM base die that promises higher bandwidth, lower power usage, and a smaller on-die footprint than traditional HBM4e. Nvidia says it's designed and validated with "leading memory vendors," so it promises custom silicon developers faster time-to-market than implementing commodity HBM from the ground up. But it's worth re-emphasizing that this isn't an HBM replacement. Instead, it's a new building block that Nvidia is only offering to its custom silicon partners.

Memory bandwidth is everything for AI accelerators, and NVHBM promises up to 30% higher bandwidth per stack than standard HBM4e. For memory-bandwidth-bound AI workloads, that higher bandwidth translates into higher throughput, such as a higher tokens-per-second rate for AI inference.

The custom NVHBM base die also reduces the footprint of memory-related circuitry on the main custom accelerator die. Traditionally, the HBM memory controller has been incorporated into the primary silicon die on the package. NVHBM instead moves the memory controller into the base die of the HBM stack and provides a smaller custom PHY that NVLink Fusion customers can then integrate into their designs.

Nvidia says this approach frees up precious package real estate that can then be used for additional compute die area — up to 30% more compute on the primary silicon die. NVHBM further promises to simplify the interposer routing used to join multiple chips together for designs using advanced packaging techniques.

NVHBM also provides power savings versus off-the-shelf HBM4e stacks. As Nvidia has continuously hammered home in the Vera Rubin roll-out, every watt that isn't going into token production is a watt wasted. Nvidia says NVHBM uses 15% less power than commodity HBM4e, and that power savings can be banked for performance-per-watt improvements, reallocated into more functional units for a custom accelerator design, or translated into higher sustained performance within the same power budget.

Higher bandwidth at lower power is a huge win for AI accelerators that are moving massive data structures like model weights and KV caches around, especially when those savings are multiplied across many thousands of chips. The energy saved on data movement can be plowed back into higher performance from the accelerator itself or reallocated to support larger numbers of accelerators within the same fixed power envelope.

But these are, as of now, reasons for Nvidia's prospective partners to consider incorporating NVLink Fusion and NVHBM into their custom designs, not benefits that will materialize in the Rubin rack-scale systems already in production.

Along with NVHBM itself, Nvidia announced that Amazon's Annapurna Labs will be its first partner on NVHBM. , and Annapurna VP Nafea Bshara says: “We look forward to this technology collaboration to benefit future AWS infrastructure designs.” Annapurna's next-generation Trainium 4 AI chips will already support the NVLink Fusion scale-up interface, so it seems likely that follow-on chips will support NVHBM, too.

d-Matrix presented Raptor, which it calls the first 3D DRAM accelerator for generative inference, at Hot Chips 2026 this week, showing a TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed DRAM die that delivers 100 TB/s of bandwidth from 32GB per card.

Co-founder and CTO Sudeep Bhoja put the vertical interface's energy cost at 0.37 pJ/bit against roughly 2.4 pJ/bit for moving data into an HBM4 base die, calling it "a measured number" from working silicon, and the accompanying ISCA 2026 paper, written with the University of British Columbia, projects around 4.7 times higher throughput per card than HBM-based designs. Bhoja, however, didn't disclose who manufactures the DRAM die.

CEO Sid Sheth told CNBC in June that Raptor is slated to launch in 2027, but at Hot Chips the company gave no firm date or information on volume and pricing, and every performance figure shown, including 988 tokens per second per user on the 2.8-trillion-parameter Kimi K3 model at 1M-token context, is a d-Matrix projection built on early silicon.

The custom DRAM die

Raptor inverts the usual 3D stacking arrangement by putting the logic die on top and the DRAM underneath, so a cold plate sits directly on the compute silicon and the DRAM die doubles as the interposer, carrying PCIe and die-to-die signals down through its TSVs. "For the same amount of power, you can drive the bandwidth up," Bhoja said during the session, "and so we were able to drive the bandwidth up here to 100 terabytes per second."

The one-high stack achieves a power density of roughly 0.5W per square millimeter, which liquid cooling can handle, but the DRAM is designed for a junction temperature of 105°C, where retention collapses from a standard 32ms to 4ms, and the memory must refresh eight times more often. d-Matrix absorbed that penalty by shrinking each microbank to 1,366 rows and about 5.33MB, so a full refresh sweep costs only 1.37% of overall bandwidth.

The die carries 840 banks per chiplet, of which 72 (around 9%) are spares wired into a two-level mux chain the company calls bank chaining, letting any two failed banks anywhere on the die be switched out while channels stay symmetric. A [132,128] Reed-Solomon code on the logic die corrects two symbol errors per 128 bytes, with a CRC behind it. The interface has no PHY, no burst structure, and no sideband pins, so conventional data-bus inversion was impossible; d-Matrix instead compares each 128-byte flit to the previous one and stores a 1-bit inversion tag alongside the ECC metadata, recovering roughly 20% of the I/O power DBI would have saved. At full tilt, the vertical interface still burns 296W of the 422W per-package budget the ISCA paper discloses.

The bank geometry, spare-bank mux tree, refresh behavior, and interleaved ECC columns were all co-designed with the compute die. The 0.37 pJ/bit figure exists only because of that pairing, and no memory maker has anything like this die in its catalog.

Who's supplying it?

d-Matrix has named TSMC for the N4P logic die and Alchip as its ASIC design and 2.5D/3D packaging partner, but neither company operates a DRAM fab, and across the Hot Chips talk, the ISCA paper, and every public announcement since the Pavehawk 3DIMC test silicon came online last September, the firm has never identified who fabricates its custom DRAM. Only three companies make leading-edge DRAM at volume, and all three are allocating capacity to HBM4 lines that are effectively sold out through 2026.

J.P. Morgan estimates DRAM prices will have risen more than 400% between the start of 2024 and the end of 2026. In addition, analysts have recorded contract price increases of 90% to 95% in Q1 2026 alone, and SK hynix CEO Kwak Noh-jung told Reuters in July that "customer demand will remain higher than our supply capacity even beyond 2030."

Nvidia, the memory makers' largest and most leveraged customer, is reportedly testing Rubin Ultra configurations with as little as 192GB because it may not be able to source enough HBM4E. A startup with roughly $450 million raised, asking a memory maker to run a bespoke die with non-standard bank geometry on capacity that could otherwise print HBM, is negotiating from a far weaker position than that, and until the supplier is named, Raptor's 2027 volume plan rests entirely on an unknown, undisclosed dependency.

The die's 11.4 MB/mm² density is roughly half of HBM4's 21.9 to 26.3 MB/mm², Bhoja acknowledged during the Q&A: "A lot of the drop for us was also because we used a not-so-advanced DRAM. And so if we used a more mainline DRAM, just like the HBM4 guys are doing, we would be able to push that up almost all the way to the HBM4 numbers." The density penalty therefore tracks back to whatever foundry arrangement d-Matrix currently has.

32GB per card

Raptor's 32GB per card stands against 192GB to 288GB for HBM4-equipped accelerators, so d-Matrix sizes deployments at rack scale instead: 72 cards carry 2.3TB, enough to hold Kimi K3's weights at 4-bit precision with headroom for around 54 concurrent users at 1M context, by its own calculations. "Even with 32 gigabytes of memory capacity, we are able to solve SOTA models in a scale-up network, so no bits are wasted," Bhoja said.

KV cache growth works against that arithmetic over time, and co-presenter Aayush Ankit, who led Raptor's SoC architecture at d-Matrix before joining Meta's MTIA team, explained the failure mode while dismissing SRAM alternatives: "We are making this unit of compute blazingly fast. Communication becomes a bottleneck soon enough." Once models and context no longer fit a single rack, inference spills into the inter-card synchronization overhead that the vertical bandwidth was meant to eliminate, which the ISCA paper concedes.

Cerebras claimed 969 tokens per second on Llama 3.1 405B in November 2024, with third-party firm Artificial Analysis verifying the figure on live hardware, and that remains the closest published reference point for Raptor's numbers. d-Matrix's 988 tokens per second per user on a model seven times larger would be a step change if it holds water, but no third party has measured Raptor, and the comparison points in the ISCA paper are simulations anchored to early silicon characterization.

Asked by an Nvidia employee about multi-layer stacking plans, Bhoja said: "Our roadmap is still a work in progress, and we have a hard enough time trying to get one-high to work and work around all of the thermal issues of that." Samsung brought its own version of the idea to Hot Chips with zHBM, a concept that stacks HBM directly on the processor and carries a claimed 70% power-efficiency gain over an HBM4E setup, with no production timeline before HBM5. The problem for d-Matrix is that Samsung runs its own DRAM fabs; d-Matrix doesn't. Whether it can get wafers at volume remains to be seen.

Full d-Matrix Hot Chips 2026 presentation

Earlier this month, Samsung introduced the industry's first LPDDR5X-PIM memory, adding in-memory logic to the low-power memory standard, and at Hot Chips 2026, it dove into the memory technology that we've previously seen at play through HBM stacks.

PIM, or Processing-in-Memory, is a technology Samsung demoed as early as 2021, piloted through HBM stacks in AMD accelerators. It's a small bit of logic that sits alongside DRAM cells, allowing basic calculations to happen directly in-memory. By handling those basic calculations locally, Samsung is able to eliminate the processor as a bottleneck and speed up, in particular, AI inference. In inference tasks, Samsung says its LPDDR5X-PIM is 2.28x faster than standard LPDDR5X, in fact.

The reason for adding in-memory processing to LPDDR5X is pretty clear: HBM is too damn expensive. Micron warned just a day earning at Hot Chips that the HBM wafer demand is only getting worse, and Samsung opened its presentation with something we're all well aware of. Memory makes up the bulk of AI chip costs, and its share of the pie continues to grow. Add on top of that the power demands of DDR5, much less HBM, and LPDDR5X seems like an ideal target for PIM.

Samsung introduced HBM-PIM in 2023, and at the time, introduced the concept of LPDDR5X-PIM. What it shared at Hot Chips is a real product, taking the concept of LPDDR5X-PIM and putting it through validation. Samsung is also looking ahead for LPDDR6X-PIM, and the company says it hopes to have an initial specification from JEDEC this year.

Bringing in-memory processing to Samsung LPDDR5X

Above, you can see a basic layout of how Samsung integrated PIM into LPDDR5X. Each memory bank has its own PIM, which is an advancement over HBM-PIM, where Samsung had to cut banks to fit the logic. The memory bank, scale register file, and source register file feed parallel MAC trees. Once calculated, the output (either integer or floating point output) is written to a vector register file.

Samsung says its LPDDR5X can operate in two modes: single-bank (traditional DRAM) or multi-bank (PIM). Traditional DRAM controllers work, with commands switching between standard read/write or a PIM read/write depending on the mode. The challenge, according to Samsung, was reordering with conventional DRAM.

Samsung uses what it calls Address Align Mode (AAM) to get around the reordering issue. It maps DRAM addresses to MAC instructions, assigning the VRF/SRF address based on the RA/CA address, respectively, and not the Instruction Register File.

To demonstrate how data moves through the memory cells and calculations are performed, Samsung provided an example of a MAC operation, assuming weight parameters for the data are already written into the cell, and the memory is operating in multi-bank (PIM) mode.

Storing 512 bytes of FP8 activation data, it's first broken down into 16, 256-bit packets, which are written into each of the banks in and noted in the Source Register File.

A PIMX_RD reads the weight data from the DRAM bank, feeding into the MAC trees alongside the data from the SRF. Once the calculation is done, the output vector from each operation is written into the Vector Register File.

Once the calculation is done, a PIMX_WR command transfers the output data back to the DRAM bank. Samsung noted there doesn't need to be a 1:1 relationship between reads and writes, but it's useful for this example. With a VRF size of 1 kbit, a maximum of four calculations can be written to the VRF.

With the output written back to memory banks, the host just needs to read the data from memory. The host switches to single-bank (conventional DRAM) mode and executes 16 reads to gather the output from all of the memory banks.

Samsung LPDDR5X specs and preliminary performance

Samsung's LPDDR5X-PIM looks a lot like LPDDR5X. It uses a standard 561-ball array for packaging, just like LPDDR5X, and Samsung uses two 64-bit ranks with 16 GB modules. The critical number here is bandwidth. With LPDDR5X-9600, peak bandwidth is 76.8 GB/s, but that's increased by eightfold with PIM to 614 GB/s by reducing data movement and keeping basic logic local.

Samsung uses four dies per rank, for a total of eight dies. Not the various registers above, as well, as they're important for the illustration of data flow through Samsung's LPDDR5X-PIM memory.

In Samsung's preliminary benchmarks, LPDDR5X-PIM is impressive. In model run time, Samsung say a 2.28x improvement with PIM, and in tokens per second (TPS), PIM offered a 3.01x increase in performance.

The slide above shows what happened behind the scenes to gather these numbers, with Samsung using an edge AI accelerator — we're not sure which, but perhaps an early Gaia SoC — and testing Llama 3.1 with 8 billion parameters. Notably, the output is different, which one attendee pressed Samsung about. The company says optimizations are ongoing to improve accuracy, but it expects the performance benefit to remain the same.

One of the main advantages of LPDDR5X is right there in the name: low power. With PIM, power consumption becomes more of a concern, but Samsung says it doesn't expect higher power consumption overall compared to conventional DRAM. The presenter noted that peak power consumption will be "much higher" due to the bursty power draw of the PIM, but Samsung still expects overall power draw to be lower than conventional DRAM.

That comes down to extra reads/writes. Although PIM represents a power increase, decreasing the number of times data needs to move between DRAM and the host will lead to overall lower power consumption. "We're not having significant power increase," as Samsung's Karam Hwang put it.

LPDDR5X has, until recently, only had applications in consumer products. However, SOCAMM2 serviceable modules allowed Nvidia to use LPDDR5X as the memory of choice with its Vera CPU. And Intel uses LPDDR5X with its new Crescent Island AI accelerator.

Even with PIM, LPDDR5X doesn't come remotely close to the bandwidth with available with HBM, but it has a lot of applications elsewhere. Samsung's targets of server, client, and mobile are telling, with LPDDR5X-PIM accelerating edge AI on mobile and client devices, as well as arriving in lower-scope accelerators like Crescent Island.

Full Samsung Hot Chips 2026 presentation

When it comes to building a gaming PC, DDR5 RAM clocked at speeds of 6,000 MT/s is often touted as the sweet spot for specs. While slower and faster speeds are available, it's very much the benchmark for both price and performance, which is why it's noteworthy that this particular configuration now costs $400, a more than 400% increase from the low prices we've seen in the past.

• $401 for Corsair Vengeance 32GB DDR5 600 ($215 off)

In addition to our ongoing RAM price tracking, we perform daily spot checks on pricing for discounts or deals for 32GB (2x16GB) of DDR5 RAM, given its aforementioned significance as the "benchmark" when it comes to capacity. In recent weeks, the price of 32GB DDR5 6000 RAM has been creeping ever closer to that unfortunate $400 milestone, and in the last few hours we've just crossed the threshold. That's not to say that prices might fluctuate back down in a day or two, but generally the traffic is only moving in one direction.

You can buy 32GB of DDR5 RAM at slower speeds for less — this Corsair Vengeance DDR5 4800 is "just" $359 — but good RAM is now harder (and more expensive) to come by than ever before.

According to data from PCPartPicker, this particular 32GB DDR5 6000 kit from Corsair has been as little as $80 in years gone by at Newegg, marking a full 400% price increase on the lowest we've ever seen on this model.

RAM prices elsewhere have climbed by as much as 500%, with 128GB of DDR5 now costing $3,399 in stores. The causes of the PC component crisis are numerous and well-documented. AI buildouts are consuming much of the world's NAND and flash manufacturing capacity, which is having a knock-on effect for consumer production. Famously, Micron even wound up its consumer brand Crucial in favor of serving more enterprise customers.

All signs point to the memory shortage, and thereby pricing, getting worse in the coming months. As such, bundles and pre-built PCs remain one of the only ways to insulate yourself from cost increases if you're in the market for new hardware. As mentioned, slower memory speeds are available at lower prices, but compromising for 4,800 MT/s RAM to save $40 when building a PC is an extremely tough state of affairs.

Memory will account for roughly 30% of hyperscaler capex this year, up from about 8% in 2023 and 2024. Conventional DRAM contract prices rose 90% to 95% in a single quarter, and Meta is already running recycled DDR4 behind CXL across millions of servers, cutting server counts by up to 25% for some inference workloads. Into that market, Marvell has brought a three-tier "AI memory infrastructure" portfolio, announced at FMS 2026 in Santa Clara on August 4 and pitched to EE Times last week, where product marketing VP Khurram Malik put DDR4 reuse at the top of the CXL use-case list.

Only one piece of it is new: the Bravera SC6 PCIe 6.0 SSD controller, which samples in Q4. Structera X has been shipping since 2024, the Structera S switch was announced at OFC in March, and the Photonic Fabric optical memory tier came with the Celestial AI acquisition in February. Meta, the reference customer for the use case Marvell is selling, did it with an ASIC of its own design rather than anything from Marvell.

What's new (and what isn't)

The Bravera SC6 is a PCIe 6.0 x4 controller with 16 NAND channels, eight chip enables per channel, a 3,600 MT/s ONFI and Toggle interface, and 12 Arm Cortex-R82 cores plus three Cortex-M7s, according to Marvell's product blog.

Marvell says it doubles the Bravera SC5, supports NAND from multiple suppliers, and uses a host-managed flash translation layer, meaning cloud operators control write placement, garbage collection, and wear leveling themselves, with KV cache spillover from HBM to SSD as the primary workload. Sampling starts in Q4 2026, which puts drives in 2027 at the earliest on the timeline Tom's Hardware Premium laid out for the PCIe 6.0 controller field, where Phison and Silicon Motion are chasing the same Gen6 drive launches.

Structera X 2404 and X 2504, the DDR4 and DDR5 expansion controllers, were announced in July 2024, and Marvell's FMS blog says both are in hyperscaler deployments, with inline LZ4 compression that Malik told EE Times yields roughly 2 to 2.5 times the effective capacity.

The Structera S 30260 switch, announced at OFC in March, carries 260 PCIe 6.0 and CXL 3.x lanes, connects 16 or 32 CPUs or GPUs to up to 48TB of shared memory at 4 TB/s aggregate bandwidth and under 460ns round trip, and begins sampling this quarter. Photonic Fabric came in with the $3.25 billion Celestial AI acquisition that closed in February, with Marvell now describing it as a shared-memory tier reaching up to 50 meters with up to 32 TB of warm KV cache and a claimed 2 to 3 times token throughput inside existing footprints. Marvell also took a $2 billion investment from Nvidia in March, tied to NVLink Fusion, the proprietary scale-up fabric CXL pooling has to sit alongside.

DRAM contract prices have tripled since Structera launched

Conventional DRAM contract prices rose 90% to 95% quarter-on-quarter in Q1 2026, the steepest increase on record for every DRAM category. Q2 added another 58% to 63%, and server DRAM is set to climb a further 13% to 18% in Q3, held in check mainly by the long-term agreements U.S. hyperscalers signed to cap pricing through 2027 and 2028. Server DRAM buyers in the U.S. and China were receiving about 70% of their orders late last year as suppliers diverted wafers to HBM.

Samsung, SK hynix, and Micron have all been winding down DDR4 output since last year, and TrendForce put the legacy memory rally at up to 50% for DDR4 in Q1 alone. A module pulled from a decommissioned 2021 server is now worth a multiple of what it was when Structera X was announced, and the DDR5 that would replace it has roughly doubled in price twice. When Marvell first pitched DDR4 reuse in 2024, it was a sustainability line item, but two years later, the memory crunch has turned it into a capex line item.

Meta's recycling numbers

Meta's Vistara ASIC, presented at ISCA 2026 in late June, is a CXL 2.0 Type-3 expander on a PCIe 5.0 x16 link that bridges two DDR4 channels to a host and runs at 128GB per chip using 32GB modules recovered from retired machines. Each MemServer pairs a 158-core AMD EPYC Turin with 768GB of local DDR5-6400 and 256GB of CXL-attached DDR4-2400, and Meta claims idle round-trip latency of around 50ns on the controller path.

The paper states that around 40% of Meta's fleet is memory-capacity bound, that its servers last three to five years while the DRAM inside them is good for seven to 10, and that the deployment cuts server counts by up to 25% for disaggregated ML inference, average latency by 29% for distributed caching, and job failures by 33%, The Register from the paper ahead of the talk.

Malik told EE Times, "The first and foremost important use case within CXL is the recycling of DDR4," and Marvell's FMS release says Structera X was "developed in close collaboration with leading hyperscalers" without naming one. Meta's paper describes an in-house ASIC, an in-house MemServer chassis, and an in-house Linux page-placement stack, the full path one would take when volume justifies its own silicon, while Astera Labs' Leo controllers reached Microsoft Azure's M-series preview in November last year.

CXL's deployment gap

SemiAnalysis declared CXL dead for AI in March 2024 because Ethernet-style SerDes such as NVLink carry roughly three times the bandwidth per millimeter of die edge as PCIe 5.0 or 6.0, so every CXL lane on an accelerator costs scale-up bandwidth that could have gone to the GPU-to-GPU fabric instead.

Marvell's CXL pitch accordingly targets CPU-side capacity and KV cache staging rather than the GPU-to-GPU path where you’ll find NVLink Fusion. Yole estimated two-thirds of servers sold in Q1 2025 were CXL-capable and expects more than 90% to be by the end of this year, yet it puts the share of servers actually using CXL at close to zero today and only 13% by 2030.

Marvell's benchmarks for the Structera S show a 16TB pooled DRAM tier delivering 4.8 times the inference throughput and an 82.7% cut in time to first token in GPU configurations, attributed to keeping KV cache in DRAM instead of recomputing or reloading it. Those are vendor numbers with no disclosed model or baseline, and the switch only starts sampling this quarter. Nvidia, AMD, and the SSD makers all offer their own routes for the same cache spillover.

Nvidia has told some of its largest customers that the prices of servers containing its AI chips will rise by more than 15% in many cases, Bloomberg reported on Saturday. The increases will take effect on Grace Blackwell and Vera Rubin systems shipping early next year, according to people familiar with the matter, who commented on communications that have not yet been made public. The size of each increase will depend on the chip generation and the memory configuration involved. Companies that build servers under contract for large data center operators, including Microsoft, Google, and Oracle, have recently notified their customers of the forthcoming increases, the people told Bloomberg.

This is another example of the so-called "RAMageddon" that's gripping the DRAM market, with contract prices having risen at record rates this year. Analysts projected that conventional DRAM contract prices would climb 58% to 63% quarter-over-quarter in Q2 2026, following a Q1 surge of 90% to 95%, as suppliers reallocated capacity toward HBM and server products. SK hynix said in October last year that it had already sold out its entire 2026 memory production capacity, and Samsung and SK hynix raised 2026 HBM3E supply prices by close to 20% before the year began.

AI systems carry enormous memory loadouts, with Nvidia's Rubin GPU shipping with up to 288GB of HBM4 per package, and the NVL72 rack-scale system combines 72 of those GPUs, putting more than 20TB of HBM in a single rack before accounting for the LPDDR attached to its Vera CPUs. With HBM production consuming roughly four times the wafer area of equivalent conventional DRAM, memory has become one of the largest line items in an AI server's bill of materials, and it's continuing to rise at a stratospheric pace.

Ironically, the supply crunch that's now inflating Nvidia's systems is the same one its demand helped to create. The three major memory makers spent this and last year shifting advanced nodes and new capacity toward HBM and high-capacity server DRAM, starving commodity markets in the process. Consumer DDR5 pricing has more than doubled since late 2025 as a result, with a mainstream 32GB DDR5-6000 kit selling for around $392 in August against $110 to $140 a year earlier, according to our RAM price tracker.

Nvidia has already passed rising costs through to consumers, raising prices on GeForce graphics cards earlier this month. The Bloomberg report indicates the same unrelenting pressure has now reached the top of the Nvidia stack, where hyperscalers as well as PC builders will be absorbing the increase. A 15% rise on rack-scale systems that sell for several million dollars each adds hundreds of thousands of dollars per rack across deployments that run to thousands of racks.

Nvidia runs a gross margin of roughly 75% non-GAAP, among the highest in the semiconductor industry, and the reported hikes indicate the company intends to pass memory cost inflation on to customers rather than absorb it, which it can more than afford to do. Meanwhile, supply of its accelerators from TSMC still can't meet demand, which limits buyers' immediate leverage.

Whether the increases push hyperscalers further toward AMD's accelerators or their own custom silicon will depend on how quickly those alternatives can absorb displaced demand, and all of them draw HBM from the same three constrained suppliers.

Bad bots account for 91% of the traffic reaching one retailer's DDR5 memory product pages, roughly 10 automated requests for every legitimate visit, according to a LinkedIn post this week from Jérôme Segura, VP of threat research at bot-mitigation firm DataDome. The figure updates research DataDome published in March, which measured the ratio at about 6:1 across several e-commerce sites.

Over the same period, the cheapest 128GB DDR5-6400 kit tracked by Tom's Hardware has reached $3,399, ten times its record low pricing. The Thales 2026 Bad Bot Report puts bad bots at 40% of all web traffic, less than half the share Segura reports on DDR5 listings.

DataDome's March report documented a single operation that generated more than 10 million blocked requests, with a one-hour sample showing 91 DDR5 listings each polled around 551 times, or once every 6.5 seconds. The requests carried cache-busting parameters to defeat cached stock data and targeted industrial module makers such as Micron and Apacer, as well as DIMM socket suppliers Amphenol and TE Connectivity, alongside consumer brands.

Segura wrote on LinkedIn that retailers carrying memory should assume their "traffic analytics are probably understating the problem significantly."

Keep in mind that the 91% figure comes from one unnamed retailer, and DataDome hasn't published a sample window or its methodology. DataDome also sells the product that blocks this traffic, and page requests ultimately aren't purchases, so the ratio measures monitoring pressure on listings rather than how much stock bots actually end up securing, which can’t easily be quantified.

Apacer CEO C.K. Chang said in July that DRAM supply to independent module makers could fall to 30% of 2026 levels next year, and TrendForce expects conventional DRAM contract prices to rise another 13% to 18% in Q3 after roughly 60% in Q2. Hyperscale buyers have reportedly placed deposits against most of 2027's DRAM output.

A 32GB DDR5-6000 kit that averaged $72 this time last year now averages $392 on PCPartPicker. While graphics card and console scalping in 2020 and 2021 ran against scheduled restocks that eventually outpaced resale demand, no equivalent restock date exists for consumer DDR5 before 2027 at the earliest.

Framework stopped selling standalone RAM in November last year, citing scalpers, and Micro Center sells its CPU, motherboard, and 32GB DDR5 bundles in-store only with a one-per-household limit. Newegg and Amazon have run repeated CPU-plus-memory bundles that price a 32GB kit well below its standalone cost, which ties each kit to a processor a reseller then has to move as well. On eBay, we found G.Skill's Trident Z5 Neo 32GB kit listed at $836.54 in December against a $429.99 retail price, roughly double, and about seven times the $117.99 it sold for before the shortage.

ChangXin Memory Technologies (CXMT), China's largest maker of dynamic random access memory (DRAM), planned to obtain Samsung's IP related to its memory process technologies in a bid to develop its own production nodes, according to testimony given in a South Korean criminal case involving leaked Samsung technology, reports Maeil Business. The company's managers allegedly had no intention to develop an in-house process technology from scratch, so obtaining IP from Samsung was a strategic decision.

The intention was a key part of CXMT's business plan rather than an opportunistic attempt to acquire Samsung's technology after the start of its own DRAM process development, according to the testimony of a former Samsung engineer identified as Jeon, who worked at Samsung for 28 years before jumping ship to CXMT sometimes around 2016. This April, Jeon was sentenced to seven years in prison for illegally obtaining a 600-step Process Recipe Plan (PRP) information concerning Samsung's DRAM fabrication processes in general and the 18nm-class node in particular.

"From the beginning, CXMT CEO and CTO tried to develop DRAM by stealing Samsung Electronics' Process Recipe Plan (PRP) information," Jeon told the court this week, according to Maeil Business. "CXMT had no research institutes or facilities at the time of its establishment, and had no intention of developing technology through its own research."

Copying the recipe does not automatically give you a working process. Nonetheless, a detailed process recipe can dramatically shorten development of any production node because it reveals things like the sequence of steps, deposition or etch conditions, anneals, cleans, implant parameters, temperatures, pressures, tool types, and so on. For a memory process, a ready process recipe can remove a huge amount of trial-and-error and reveal how the process integration is supposed to work. Meanwhile, even to ensure that the recipe works as intended, one needs to obtain the same or compatible tools as well as adjust their characteristics accordingly.

However, while a process recipe can potentially help to ramp any fabrication technology, a process recipe itself does not necessarily reveal the complete transistor architecture or physical design. For that, perpetrators also want things like cross-sectional structures, masks/layout information, design rules, device dimensions, capacitor geometry, process window, and so on. Such details are not easy to get for a brand-new fabrication technology, but they can be obtained by reverse engineering of shipping products. By combining process recipe with reverse engineering, experienced DRAM engineers can reconstruct much of the technology. Meanwhile, process integration engineers can save years of trial-and-error with actual fab tools.

Normally, it takes DRAM companies around 3 – 5 years to design a process node from device development to yield ramp. For a new player, development time from scratch will probably be around five years rather than three unless pre-competitive IP is licensed or certain heavy-lifting is done elsewhere. In fact, the Maeil Business report claims it took Samsung five years to develop its 18nm-class node.

Meanwhile, CXMT began mass production of DDR4 SDRAM in 2019 using a 22nm-class node. Mass production of memory using a 18nm-class process technology began in 2023. Such a timeline raises a question of whether CXMT's 22nm-class G1 was derived/adapted from the knowledge of Samsung's process technologies and/or their process recipes, the more advanced 18nm-class node, or did the allegedly obtained Samsung IP primarily help CXMT develop the later 18nm generation? In any case, there is a court ruling that CXMT stole IP from Samsung to boost its own memory production capability.

After posting record profits amid high memory prices, SK hynix ran into a dispute with employees over profit sharing and wage increases, which threatened to escalate into collective action by the company's union. This week, SK hynix management and the labor union reached a preliminary 2026 wage and collective bargaining agreement that significantly changes how the company's profit-sharing bonuses will be distributed, reports Maeil Business citing Yonhap. The good news is that no strikes are planned at the memory maker.

The tentative labor package reportedly calls for a 6.3% wage increase and an increase in welfare points provided by the company. In addition, under the proposed arrangement, employees will receive 40% of their performance-based profit distribution in cash, while the remaining 60% will come in the form of SK hynix shares. The proposal changes SK hynix's 2025 profit-sharing scheme, which allocated 10% of the previous year's operating profit to employee profit-sharing program, but the bonus was to be paid complete in cash: employees received 80% in cash immediately and remaining 20% over the next two years.

The union argued that stock-based bonuses expose employees to potential losses if SK hynix shares decline and could create tax complications, as income tax may be calculated using the share price when the stock is awarded. Specifically, the workers argued that performance bonuses normally paid in cash should not be converted into assets that carry investment risk. Yet, the SK hynix management and union have agreed to remove the 10% ceiling, potentially providing more money to employees, maintain the mechanism for 10 years, and pay the bonuses in cash and stock.

If SK hynix meets current market expectations and earns 25 trillion won ($17.897 billion) in operating profit this year, the profit-sharing pool would amount to 2.5 trillion won ($1.79 billion) based on the 10% formula. SK hynix reportedly has approximately 35,000 employees, so on average every employee will get 70 million won, or $50,120 ($20,048 in cash and $30,072 in stock). Yet, actual compensation will differ depending on an employee's position and individual performance assessment.

On August 4, before the fifth round of negotiations, an SK hynix union told members that if management did not present a revised proposal, it would be difficult to settle the dispute through negotiations alone and the union would have to take necessary action, which was obviously a way to threaten the management with a strike. Yet, the parties have come to terms.

The dispute comes as Samsung Electronics has faced similar labor action over compensations.

Pine64 has stopped producing Linux devices entirely, announcing this week on its official Telegram news channel that "there isn't [sic] any plans to continue producing more Linux devices in the near future" because of the ongoing DRAM and eMMC shortage. The stoppage covers the company's full lineup of Arm and RISC-V single-board computers, the PinePhone family, the PineTab2 tablet, and the PineNote e-reader, with remaining PineNote and PineTab2 stock estimated to last around three months.

Microcontroller-based products, such as the PineTime smartwatch, PineVoice smart speaker, and Pinecil soldering iron, won't be affected, and production will continue as usual. Development on the upcoming PineTime Pro will also continue: Pine64 said its demo firmware now has basic drivers for the display, touch, motion sensing, GPS, and audio, though some issues need fixing before a pilot batch enters production. The company also hasn't ended software support for existing Linux hardware.

The AI-driven memory crunch has raised prices on everything from DDR5 kits — which have sold on eBay for more than $2,000 — to prebuilt PCs from Dell, CyberPowerPC, and Maingear. Unfortunately, Pine64 buys the single worst-supplied part in the entire NAND market. TrendForce reported in April that the eMMC/UFS segment faces the tightest supply gap of any NAND category, because its production capacity overlaps with far higher-margin enterprise SSDs, making it the last in line for supplier allocation.

Phison CEO Khein-Seng Pua said in February that 8GB eMMC modules had risen from $1.50 to $20 in a year, a 13-fold increase, and warned the shortage could shut down entire consumer electronics companies in 2026. Pine64 hasn't shut down, but a whole product category has, and it's the first named vendor to kill a lineup outright instead of repricing it.

Other small-board makers have taken the opposite route. Raspberry Pi has raised prices repeatedly, pushing the Pi 5 16GB to $205 and the 500+ to $410, while launching a 3GB Pi 4 and leaning on a stockpile of older LPDDR2 to hold prices on legacy boards. Framework followed in January, raising its desktop pricing to cover LPDDR5x costs, which, since Strix Halo boards use soldered RAM, it couldn't pass to users any other way.

Pine64 sells its hardware near cost as a community service, so it has no margin to absorb higher component prices and, evidently, believes its buyers won't, either. Its mid-2027 checkpoint aligns with supply forecasts that don't expect new memory fab capacity to arrive in volume before late 2027 or 2028.

Pine64 said any decision on resuming production depends on component pricing after mid-2027, meaning its Linux hardware could be off the market for two years — or more.

What could possibly go wrong when you try to steal trade secrets from a restricted facility using a 360-degree action camera hidden in snacks? Forgetting to turn off the device’s Bluetooth and Wi-Fi transmitters, as it turns out.

A senior engineer at Nanya Technology has been indicted in Taiwan for allegedly copying 32 files containing information about the company's DRAM manufacturing process, reports Freedom Times. The engineer was reportedly in talks with Chinese recruitment agencies and allegedly planned to pass Nanya's trade secrets to its next employer in the People's Republic in exchange for higher compensation.

Yeh Yen-wei, a senior engineer in the Advanced Process Development Division at Nanya, joined the company in 2022 and began to communicate with Chinese recruiters in 2025 to explore employment opportunities in the People's Republic. Sometime in mid-February 2026, he submitted his resignation. However, before leaving the company in mid-April, on March 28, April 4, and April 5 — during weekends and either late at night or early in the morning — he visited the company's restricted office areas with his Insta360 X4 Air action camera hidden among snacks to get it past security checks.

Once inside, Yeh used his legitimate account credentials to access Nanya's virtual machines and opened various internal research and development documents. He then used the camera to capture photographs and video of information associated with Nanya's DRAM process technologies and production methods. It goes without saying that he retained the information when he officially resigned from Nanya in mid-April.

However, his actions did not go unnoticed. Nanya's IT security team detected 'abnormal' wireless signals inside the company's restricted facilities (i.e., identified the device using its Bluetooth and/or Wi-Fi signals) and tied them to the employee's access records and activity logs. Eventually, Nanya reported the suspected theft to Taiwanese authorities, which led to an indictment.

The New Taipei District Prosecutors Office charged Yeh under Taiwan's Trade Secrets Act with unauthorized reproduction of trade secrets intended for use in China, an offense for which he faces up to 10 years in prison, as well as with breach of trust under the Criminal Code. Meanwhile, forensic examination of the seized equipment uncovered no evidence that Yeh had successfully transmitted Nanya's confidential information to a Chinese company or anyone outside the company, so he could potentially get off easy.

Since late 2025, RAM, storage, and graphics card prices have shot through the roof, making items that were once affordable out of reach for many people. Anyone still in the market for those parts has to rely on combo deals for any reasonable pricing. Newegg has an excellent 3-item combo running where you essentially get the 16GB of DDR5 RAM for FREE with a huge $274 discount. For only $658.99, you get the powerful Ryzen 9 9900X processor, a quality Asus X870E-Plus Wi-Fi 7 motherboard, and 2x8GB Team Group DDR5-5200 RAM, along with a free Cooler Master 240mm AIO.

● Check out this deal at Newegg

The star of the combo has to be the ‘free’ RAM. The combo offers 16GB (2x8GB) of TeamGroup’s T-Force Vulkan DDR5-5200. And while the RAM speed is outside of AMD’s sweet spot, you’d be hard-pressed to notice a performance difference without looking at a frame counter. These black, non-RGB sticks will also look great with the included motherboard. If you apply the ~$274 discount to the RAM, you’re getting it for free. And if 16GB isn’t enough, buy the same kit again net 32GB for only $240.

Although we didn’t review AMD’s Ryzen 9 9900X, we know the non-X3D chips, like its big brother, the Ryzen 9 9950X, were generally well received by our reviewer and the public alike. Its strong multicore and single-threaded performance, native AVX-512 support, and backward compatibility with AM5 motherboards make this CPU an excellent choice for someone who uses their PC for more than just gaming and can make use of the additional cores and threads, as you can see from our benchmark data:

The Ryzen 9 9900X is a 12-core, 24-thread processor built on TSMC’s 4nm FinFET process (6nm for the I/O die) with a base clock of 4.4 GHz and boost up to 5.6 GHz. It has a TDP of 120W and is relatively easy to manage the thermals, even when overclocking the fully unlocked processor. While overclocking isn’t what it used to be, you can still squeeze out a couple of hundred more GHz, and sometimes you can get there, even when lowering the voltage. In short, there’s a lot of performance out of the box, and even a bit more headroom left if you want to overclock.

Last, the Asus TUF Gaming X870E-Plus Wifi 7 is a solid all-around motherboard for the AM5 platform. It delivers sufficient power to support flagship-class processors and easily handles the 9850X3D in the combo, even with some overclocking. It comes with four M.2 sockets (one PCIe 5.0) and two SATA ports for storage, fast networking with integrated Wi-Fi 7 and 2,5 GbE, ample USB ports on the rear IO (13, including two USB4 40 Gbps Type-C), and a quality audio solution based on the last-gen Realtek flagship (ALC1220P). Asus’ AI solutions (AI Cache Boost, Overclocking, Cooling II, and Networking II) and the DIY-friendly design make it easy to build and get the most out of your system.

If you’re in the market for an AM5-based system that isn’t based on an X3D chip, this $658.99 combo (an incredible $274 savings) is one of the better deals available at Newegg right now. And you even get a free 240mm Cooler Master AIO. Getting RAM for what essentially amounts to ‘free’ is not something we see frequently. You can even upgrade to 32GB and still find yourself well ahead versus buying alone. Get this deal while it lasts.

Yangtze Memory Technologies (YMTC) shipped 14% of the world's NAND flash in the second quarter of 2026, entering the global top three for the first time and narrowly displacing Kioxia, according to Counterpoint Research's Memory & Storage Tracker published today. Samsung led with 25%, SK hynix followed at 22%, and Micron rounded out the top five. The Chinese vendor's climb comes during a quarter when enterprise SSDs absorbed 48% of every NAND bit shipped worldwide, up from 26% a year earlier, and industry revenue grew fivefold year over year by Counterpoint's count.

In terms of revenue, however, YMTC sits fifth behind both Kioxia and Micron, with nearly all of its output going into consumer products. Consumer bits now sell for a fraction of what hyperscaler buyers pay for enterprise eSSDs holding KV caches and inference datasets. The company has been included on the U.S. Entity List since December 2022, which bars it from achieving Western server qualification, where the big bucks are earned, limiting its addressable market to the Chinese domestic channel plus whatever consumer demand the incumbents leave behind.

They're leaving behind plenty — Samsung's shipment share has dropped from 32% in Q2 2024 to 25% as it caps NAND output in favor of higher-margin DRAM, SK hynix subsidiary Solidigm grew bit shipments 40% quarter over quarter on server demand, and Kioxia's entire 2026 production is already sold out, largely to enterprise customers. Kioxia itself sends over 30% of its bits into servers, per Counterpoint, but its customers pulled back as prices climbed, and slower growth cost it the number three spot it held a quarter earlier.

With NAND contract prices up roughly 75% in Q2 alone, the vacuum in the consumer channel is a segment that YMTC is perfectly set up to serve. The company grew shipments 22% year over year and 5% sequentially while mass-producing 267-layer 3D NAND on its Xtacking architecture, with development underway on devices exceeding 300 layers. Meanwhile, its third Wuhan fab has cleared Beijing's 50% domestic-tooling threshold and is due to begin production late this year, with two follow-on fabs planned.

Counterpoint says that it expects eSSDs to pass half of all NAND bits by year-end, meaning the consumer pool YMTC dominates is shrinking as a share of the total market even as YMTC's slice of it grows. According to the firm, YMTC plans to shift its mix toward eSSDs in the second half, backed by what it called growing avenues for capital support. That shift depends on winning server customers it currently can't reach outside China, and holding a number-three spot earned on cheap bits will get harder if it can't.

Intel CEO Lip-Bu Tan has revealed that new memory architectures — once thought a commodity business — are now strategically interesting and one of his pet projects, while speaking about the comeback of the American chip industry. He further noted that the memory industry is ripe for innovation, and also hinted at exploring ways to stack memory on top of a CPU.

After years of being a commodity, memory became a strategic asset in recent quarters and will likely remain one for a while, so suddenly, leading makers of 3D NAND and DRAM became highly profitable companies, something the Intel CEO is keenly aware of:  "I used to be, 'do not invest in memory because it is a kind of commodity business,' but now it has become different," Tan said. […] "There is a lot of new technology coming out. So, we are kind of looking at one of my pet projects, some of the new memory architecture. I think you just saw the news: I hired my good friend, Seok-Hee Lee, who used to run SK Hynix. So, you kind of know something that I am thinking about. We are not ready to unfold it."

Tan did not reveal anything about the pet project and did not even specify whether the project is one of his personally favored strategic initiatives at Intel, or an initiative in one of the companies that he has invested in. He did mention that stacking memory on top of a CPU could make a lot of sense, though did not elaborate. Tan's remarks also follow the revelation of an Intel XBM patent that does away with the silicon interposer of HBM.

" I think CPU and memory, I think there are a lot of ways we can really do stacking together," Tan said. "And also try to find some new architecture for memory. I think in some way the memory, a lot of innovation are not there. So, there is some really good area."

Not everyone in the industry remembers, but Intel started as a memory company in 1968 and was quite a successful memory maker until the eighties, when Japanese companies took the lead, and Intel had to exit the market completely after suffering severe losses. Since then, the company has attempted either to return to the memory market with NAND and Optane, or at least to capitalize on a new type of memory with RDRAM. In all three cases, the company abandoned its memory initiatives without incurring significant losses.

Given the current profitability of 3D NAND and DRAM makers, producing memory is certainly a good business again and will remain profitable for some time. However, to re-enter it, companies like Intel would need capital to build at least one fab, R&D to develop competitive process technologies, and time. While licensing a technology — assuming that a company has capital — is an option, we strongly doubt that at this point Intel may be inclined to invest capital in memory and not in its core products and foundry businesses. Furthermore, it is unclear how investors react to such investments given the fact that the company struggles to become a strong competitor in the foundry market and has exited 3D NAND and 3DXPoint/Optane businesses after failing to achieve strategic targets.

Apple reportedly has around $1 billion in "processor wafers on the shelves awaiting packaging" amid ongoing memory shortages, putting pressure on the firm as it nears the launch of the iPhone 18. Tim Culpan of Culpium says Apple is "scrambling" for memory supply ahead of release, working with suppliers to get memory ready so it can finish packaging the A20 Pro and C2 chips that are reportedly inside the iPhone 18 lineup.

It's an interesting peek behind the curtain of the current supply chain limitations, which reach beyond simply DRAM chips. With fully-integrated SoCs across both desktop and mobile, Apple is uniquely vulnerable to supply chain limitations, not only in DRAM supply, but also in packaging capacity to bring together DRAM chips with processor wafers.

According to Culpan, Apple primarily sources DRAM from Micron, with smaller engagements from SK Hynix and Samsung. Micron (along with the other major memory players) has reportedly sold capacity for DRAM and HBM through 2027. A flurry of long-term agreements (LTAs) have cropped up over the past several months, guaranteeing supply to certain companies for several years.

The A20 Pro is the first chip to use TSMC's N2 process, and it has been progressing well, with TSMC reportedly sitting on around $1 billion worth of Apple wafers awaiting packaging with DRAM. Packaging happens with TSMC's new Wafer-Level Multi-Chip Module (WMCM) process, according to Culpan, which is similar to the CoWoS packaging but for mobile parts.

Culpan reports that "Apple and its assemblers remain confident that they can meet initial demand," but DRAM shortages could put pressure on shipments past the initial launch. Apple reportedly plans to ship around 200 million iPhone 18 units across the lineup throughout the device's lifespan. The iPhone 17 range saw record shipments last year, surpassing 245 million devices shipped in 2025.

Apple is one of several companies reportedly looking to alternative suppliers for DRAM, namely China's CXMT. The Chinese memory supplier has become a hot topic in the halls of the U.S. government over the past several weeks, with Apple reportedly lobbying for clearance as the government weighs the option to ban CXMT.

This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.

Here's a breakdown of each type of technology that the company announced.

• zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
• zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
• BV-NAND (aka Samsung’s 10^th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).

This article is a preview of the type of content that readers can expect from our subscription service, Tom's Hardware Premium. If you're interested in more technical content that spans across the hardware industry, subscribe for as little as $29 per year, or $7 per month.

zHBM: Placing HBM stack on top of logic

Around the time we first heard about HBM4's 2,048-bit interface, we read a 'semi-official' report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung's zHBM appears to be a continuation of that effort.

Samsung's zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the 'performance of HBM5', while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.

While Samsung's claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a 'next-generation interface system incorporating zHBM' will deliver 'approximately eight times the performance of HBM5,' it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as '8x higher bandwidth.'

Instead, the general term 'performance' may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn't reveal which die stacking/bonding technology it will use for zHBM.

In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.

For now, Samsung hasn't disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.

zNAND-O(on-device): Put storage close to compute

Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company's V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.

Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.

Since the technology is in development, Samsung hasn't shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions 'improved I/O performance and low-latency,' it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.

BV-NAND: Good old V-NAND gets a new treatment

With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.

Samsung formally announced its 400-layer-class V-NAND (aka 10^th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm² with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung's 10^th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk's BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.

Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.

Samsung's new brand strategy

As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.

Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company's new tech, like zHBM and zNAND-O, is years away.

Following its massive $8.6 billion initial public offering (IPO) in July, ChangXin Memory Technologies (CXMT) began considering building its sixth DRAM fab in China to boost memory output in the coming years, Reuters reports. If all announced projects proceed as planned, the company's production capacity could more than double in the mid-term future, the report claims. Meanwhile, investment banker Dan Niles believes China could capture 30% of the DRAM market by 2030, according to P Equity Research.

Growing at a rapid pace

CXMT currently operates three 300-mm DRAM fabs: two near Hefei and one in Beijing's Yizhuang district. Unofficial reports claim that each fab is capable of processing around 100,000 wafers per month, so the company's output may be around 300,000 wafer starts per month (WSPM).

The company is pursuing an aggressive expansion strategy and is currently building additional fabs near Shanghai and Hefei, according to Reuters. The company's sixth fab will reportedly be located in Beijing's Yizhuang area, adjacent to its existing facility. Once these projects are fully operational, the company’s total manufacturing capacity could exceed 600,000 WSPM, which will double its current output, according to Reuters. Meanwhile, researchers from Citrini believe that CXMT could exit 2026 with a capacity of 350,000 WSPM, which is just 25,000 WSPM shy of what Micron targets by the end of the year. Citrini Research models that by 2030, CXMT will have production capacity of around 950,000 WSPM.

Building three big DRAM fabs is a big deal, from both financial and execution points of view. However, it is not a secret that virtually all fabs owned by Chinese companies are built using money from local and federal governments under the 'Hefei model,' which aims to transform cities into economic juggernauts by leveraging high-risk projects. So it is not surprising that both Shanghai and Beijing have provided financial assistance and other forms of support to attract CXMT to their regions, according to Reuters.

CXMT's existing Beijing fab, operated by Changxin Jidian, received backing from E-Town Capital and Beijing E-Town Technology, both affiliated with the Yizhuang development zone, according to a person familiar with the matter cited by Reuters. In fact, the district has evolved into a relatively major semiconductor manufacturing hub that already hosts CXMT, SMIC, Naura Technology, and Xiaomi, the report claims.

The right timing

The proposed fab would be located in Beijing's Yizhuang district, roughly 20 kilometers southeast of the city center, where CXMT already operates a 300-mm DRAM manufacturing facility. The planned production capacity and total capital investment for the project have not yet been disclosed, although Reuters points out that a leading-edge DRAM fab typically costs well over $10 billion.

Sources cited within the report said the company is seeking at least 60 million yuan ($8.9 million) in financial support from the Beijing Economic-Technological Development Area, and additional state-owned technology companies have also expressed interest in participating. Discussions remain preliminary, and neither the overall size nor the structure of the financing package has been finalized.

From CXMT's point of view, this is the right time for financial influxes as the company can sell all of its DRAM output at good prices to a variety of customers. Those being domestic PC and server makers (including Lenovo), and global brands such as Micron, Samsung, and SK hynix, which prioritize shipments of their DRAM output to the AI sector.

Apple, Dell, and HP have all reportedly qualified CXMT's memory and are ready to deploy it in their devices sold in China, while Acer and Asus have already begun to use DRAM from the Chinese maker. If CXMT signs long-term supply contracts with the world's leading PC makers, it is nearly guaranteed to sell out its output to these vendors in the coming years, which justifies investments in its expansion.

30% of DRAM market by 2030?

Dan Niles, founder of Niles Investment Management, believes that many investors underestimate how much share CXMT could capture over the coming years and how much share China may seize in the coming years.

His argument stems from historical DRAM market leadership shifts. In 1975, U.S. companies controlled 95% of the DRAM market, with Intel alone holding 75%. Japan then turned DRAM into a commodity business, increased its share to 80% by 1985, while the U.S. fell to 10% and then just 2% by 1990. Then South Korea repeated that playbook in the mid-1980s and eventually displaced Japanese suppliers, and today it accounts for roughly 62% of the global DRAM production.

With Micron's investments of hundreds of billions of dollars in U.S. DRAM capacity, the country is set to regain its massive presence on the global DRAM scene; China could capture 30% of the market by 2030, according to Niles.

China already consumes around 30% of global memory output, as it produces hundreds of millions of PCs and smartphones both for domestic and global consumption; it is reasonable to expect the country to produce as much commodity memory locally as possible. Keeping in mind China's push for semiconductor self-sufficiency and willingness to invest huge amounts of money in domestic fabs, it is possible to expect the country to rapidly gain DRAM output and share. China is already pushing its chipmakers hard to start DRAM production, and the government reportedly asked CXMT to share its process technologies with others.

Not that easy

There are multiple factors — both technological and political — that may, if not stop, but greatly slow down CXMT's and China's DRAM expansions in the coming years.

First up, there are export controls in place that prevent Chinese entities from getting sophisticated wafer fab equipment required to make DRAM using 18nm-class process technology or more advanced. If the proposed MATCH Act passes, then limitations on Chinese companies will get more severe, which will reduce their expansion ability.

Secondly, even if CXMT (or another Chinese DRAM maker) finds a way to produce more advanced DRAM using relatively outdated tools (i.e., use old tools for sub-16nm nodes), they will need to acquire those tools in quantity to increase their output. Meanwhile, companies like ASML have relatively limited production capacities, and CXMT is certainly not the only memory maker seeking to expand its production capacity in the coming years. While SMEE and SiCarrier are developing lithography tools in China, they will be unlikely to ramp up production of immersion DUV scanners to higher levels any time soon.

Thirdly, building fabs is one thing; operating leading-edge DRAM production at high yields is another. China has recruited engineers from Micron, Samsung, SK hynix, and TSMC for years, but scaling from three to six or more fabs requires thousands of experienced process, yield, device, lithography, and integration engineers. Building fabs adjacent to existing sites enables CXMT and other chipmakers to share experience and knowledge internally, which helps to develop experienced talent. But will it be enough for the long term?

Next, expanding wafer capacity alone is insufficient. DRAM producers must continuously migrate to finer process technologies (e.g., 16nm-class, 14nm-class, 12nm-class) to remain cost-competitive. If export controls delay access to equipment or materials needed for these nodes, Chinese fabs could end up producing more wafers at a higher cost per bit than competitors.

Finally, some American lawmakers want to prohibit U.S.-based companies from acquiring memory from CXMT and other Chinese vendors. They have every reason to believe that China wants to take control of a sizeable DRAM market share in a bid to use it in its strategic interest and have leverage over the market, something the country already has with rare earth metals. If the lawmakers manage to turn the proposal into law, demand for CXMT's and other China-made DRAM will drop. It will probably be sufficient inside China, but whether it will be enough to justify 10 or more big DRAM fabs is a different question.

Pushback against Micron's planned manufacturing complex in Clay, New York, which comprises four separate fabs, is once again at the center of an environmental lawsuit. Filed by Neighbors for a Better Micron and Jobs to Move America — the same groups that filed a separate lawsuit against Micron in January — filed a new complaint Friday, claiming that approved wastewater and air permits aren't valid and will allow Micron to leak "forever chemicals" into the Oneida River.

"The Permits were issued against eh backdrop of the significant environmental consequences already acknowledged through the course of the Micro Project's State Environmental Quality Review Act (SEQRA) review. including the release of PFAS and other highly persistent and hazardous chemicals," the complaint reads. "Rather than fully and meaningfully evaluate and address those consequences and impose the necessary protections before granting final authorization, [the Department of Environmental Conservation] issued permits that defer essential analyses, controls and limitations, and mitigation decisions until after issuance or until future regulations and studies have been conducted."

The lawsuit names the New York State Department of Environmental Conservation (DEC), Onondaga County (where Clay is located), and Micron. Its claim is that, despite Micron receiving wastewater and air permits from the DEC, those permits aren't adequate to regulate the plant's emissions. In one part of the lawsuit, the petitioners claim the permits are "not routine operating approvals," and in another, claim the loose permit guidelines "are not collateral or technical omissions."

Per- and polyfluoroalkyl substances, otherwise known as PFAS or "forever chemicals," are synthetic chemicals that are essential to semiconductor manufacturing. The chemicals are present throughout nearly the entirety of the manufacturing chain, necessitating strict water and air containment management to align with environmental regulations. "The SPDES permit authorizes the acceptance and discharge of Micron's industrial wastewater containing identified emerging contaminants, including PFAS compounds, but it imposes no substantive controls on those harmful contaminants beyond monitoring their presence and concentration."

In January, the two petitioners named in this complaint filed another lawsuit against Micron, claiming that the project failed to comply with the state's environmental review process. Last month, Micron asked a judge to dismiss the lawsuit. It's still set for oral arguments on August 25, however.

This lawsuit currently doesn't have a date set for oral arguments, if it ever reaches that point. The petitioners are seeking the nullification of both wastewater and air permits, which would force Micron back under the environmental review process, and costs associated with the suit.

Storage and memory manufacturer Lexar has listed a new 32GB (2x16GB) DDR5-7200 CL38 memory kit in China with a price tag of 3,999 yuan (roughly $592). Part of the second-generation Thor RGB series, the kit features a sandblasted aluminum heat spreader, thermal pads, and eight LEDs that support a variety of RGB lighting effects. It is rated for 38-48-48-86 timings at 1.40V and supports both Intel XMP 3.0 and AMD EXPO profiles.

Lexar says the modules use carefully selected domestically produced DRAM, although it does not specify the actual manufacturer. While there is no confirmation, the company may be using DRAM chips made by CXMT (ChangXin Memory Technologies). Lexar has also published a compatibility list covering 43 motherboards, including 30 Asus models and 13 MSI models across Intel Z890, Intel B860, and AMD B850 platforms. The compatibility list also includes supported boards for a faster 32GB (2x16GB) DDR5-7600 CL38 memory kit.

Interestingly, none of AMD's X870 or previous-generation motherboards appear on the list. That said, the kit should work on most DDR5 boards that Lexar hasn't tested, but the absence of AMD's flagship consumer chipset from the compatibility list is a bit odd. Notably, major motherboard manufacturers, including MSI and Gigabyte, have already started optimizing their motherboards to support CXMT memory ICs.

A few months ago, Corsair began adopting CXMT DDR5 chips in select memory kits, including its popular Vengeance lineup. Likewise, major PC manufacturers such as HP and Dell have started qualifying CXMT DRAM, while Acer and Asus have reportedly asked their Chinese manufacturing partners to source locally made memory chips.

The arrival of CXMT-made DDR5 chips earlier this year raised hopes that a new DRAM supplier could ease supply constraints and eventually lower memory prices. So far, there seems to be little evidence of that happening. At around $592, Lexar's new DDR5-7200 kit is priced in line or only slightly below many comparable 32GB DDR5-7200 kits currently available in the U.S. Similar kits from brands such as G.Skill, Corsair, and Kingston are currently selling anywhere from $585 to $700.

There’s been a shift toward using a single DIMM of DDR5 to skirt the worst of the RAM pricing crisis. AMD has suggested to us previously, at least, that it’s an option PC builders are exploring, and it’s a wrinkle that’s shown up in dozens of prebuilts; one that we’ve been careful to avoid when recommending products, particularly during peak shopping events. But just how much gaming performance are you giving up with a single DIMM when using one of the best CPUs for gaming?

The conventional wisdom is that you’re giving up quite a bit of performance, resting on the ideas of previous DDR generations, where going down a single stick will cut your bandwidth in half. The same is true with DDR5, but things are a bit messier, which we’ll dig into later.

At a high level, using a single DDR5 DIMM doesn’t compromise gaming performance by nearly as much as you might expect. We saw drops of around 8% to 10% across Intel and AMD CPUs, and less than a 5% difference with AMD’s Ryzen 7 9800X3D.

A proper dual-channel configuration is still the way to go for optimal performance. However, our testing shows that even a single DDR5 DIMM offers superior performance to dual-channel DDR4 on CPUs that support both memory generations.

Using a single DIMM isn’t ideal, and it brings up compatibility issues if you plan on adding another DIMM down the line (another area we’ll touch more on in-depth later). But as a stopgap measure amid surging DRAM prices, a single DIMM of DDR5 holds up surprisingly well in gaming scenarios, and it represents a nice on-ramp into a DDR5 platform while prices are out of control.

Testing single-DIMM DDR5 in games

The geomean below speaks for itself. Moving down to a single DIMM drops some performance, but it’s not nearly as stark as I expected. There are some important notes about how we tested before dissecting the results, however.

As usual, we tested at 1080p with a mixture of High and Ultra settings, using Nvidia’s RTX 5090 Founder’s Edition to minimize the influence of the GPU. That’s even more important here, as we’re not evaluating CPUs but the memory that feeds the CPU. We're looking at a separate GPU and CPU here, as well; dual-channel memory is vital if you're using an iGPU.

We also wanted to create a realistic testing scenario. Assuming you’re going for a 2x16GB configuration, that means starting with a single 16GB DIMM, not a 32GB one. That’s what we did here. Our single-DIMM configurations run with just 16GB of memory, while dual-DIMM configurations run with 32GB. Capacity isn’t a major limitation for our testing here, though it will pose performance issues if you’re running several applications alongside your game.

The Ryzen 5 7600X was our biggest loser, dropping 10.9% of its average performance across our 13-game geomean with a single 16GB DIMM. The Core Ultra 7 270K Plus, meanwhile, dropped 8.7% of its average performance, while the Core i5-14600K similarly dropped 8.3% of its performance. The 1% lows are especially notable here, scaling with average performance rather than falling off a cliff.

Unsurprisingly, the Ryzen 7 9800X3D fared the best, dropping just 2.8% of its performance on average. As you’ll see through our individual game tests, the Ryzen 7 9800X3D shows identical performance with two DIMMs and a single DIMM in multiple games. The large and speedy L3 minimizes the impact of using a single DIMM, giving AMD’s 3D V-Cache CPUs another notch in their belt (as if they needed another).

Our other geomeans don’t say much. A single-DIMM configuration consumes a few watts less, leading to slightly lower efficiency when balanced against the lowered performance.

007 First Light, the newest game in our test suite, shows good scaling across our test pool, so it’s a good place to start. The Core Ultra 7 270K Plus dropped 8.9% of its performance with a single DIMM, while the 9800X3D dropped 6.5%. The 14600K is worth highlighting here. A single DIMM lost us 7.9%, but that’s still better than dual-channel DDR4, and by a decent 6.8% margin.

This trend is fairly consistent, too. Starfield is punishing for single-DIMM configurations, with the 14600K losing 10.6% of its average performance. Even then, a single DDR5 DIMM is 6.9% faster than dual-channel DDR4. Intel platforms can scale up to high data rates, and we use 7,200 MT/s for Intel chips. With slower speeds, the performance will equalize. Still, I’d strongly consider a single DDR5 DIMM if you’ve been eyeing an LGA 1700 platform with DDR4, assuming you’re primarily focused on gaming.

Starfield shows the benefits of 3D V-Cache in this single-DIMM configuration clearly. While the performance losses with other CPUs are brutal in this title, the 9800X3D dropped just a few frames, a 1.6% decrease in average performance.

Doom: The Dark Ages is similarly harsh on single-DIMM configurations. The Ryzen 5 7600X dropped 17.3% of its average performance, and the 270K Plus fell by 14%. The 9800X3D holds up well, however, with just a 4.2% average performance loss. Marvel’s Spider-Man 2 (in the gallery below) shows a similar dynamic.

However, the addition of 3D V-Cache mainly helps in these games where we see bigger losses with other CPUs. There are several games in our suite where the performance loss between a single DIMM and dual-channel configuration was minor, particularly in GPU-heavy titles. The Last of Us Part One shows that in action.

Similarly, the performance loss is minor in Counter-Strike 2, just a handful of frames even north of 600 FPS. Even the Core i5-14600K, which was hit the hardest by far, dropped just 5.9% of its average performance (and it’s still faster than a dual-channel DDR4 configuration).

You can browse the results of the other games we tested in the gallery above, though they tell much the same story as the titles we highlighted. The two biggest learnings from this testing are that a single, fast DDR5 DIMM often outpaces dual-channel DDR4, and that AMD’s 3D V-Cache can smooth over the rough edges of using a single DIMM, particularly in those memory-sensitive titles.

How we tested

We tested on our normal test bed that we use for CPU reviews, with the only difference being dropping one of our DIMMs. As usual, we enabled XMP/EXPO for testing, both on single- and dual-DIMM configurations, opting for higher speeds on Intel platforms. AMD’s sweet spot is around 6,000 MT/s.

The data rate is noteworthy for the DDR4 comparison, in particular. With slower DDR5, we expect the delta between dual-channel DDR4 and single-DIMM DDR5 to decrease.

In addition to enabling XMP/EXPO, we disable Virtualization-Based Security (VBS), enable Resizeable BAR, and disable any automatic overclocking features that aren’t covered by warranty, including AMD’s Precision Boost Overdrive and Intel’s Extreme performance profile.

Complexities of DDR5

DDR5 has much higher data rates compared to DDR4 (2x or more), and that’s the result of significantly more complexity on DDR5 DIMMs compared to DDR4. Notably for this testing are the two 32-bit subchannels of DDR5, as well as enlarged prefetch and bank groups. You are getting half the total bandwidth with a single DDR5 DIMM, absolutely, but it’s a little more nuanced than simply running your memory in a single-channel configuration.

DDR4 uses a single 72-bit channel, and 64 of those bits transfer data (the additional 8 are for ECC). With DDR5, you get two 40-bit subchannels, 32 of which are used for data transfer. Critically, these subchannels have their own Command/Address (CA) interface, allowing them to operate independently of each other.

In addition, DDR5 doubles the prefetch size to 16N, doubles the number of banks and bank groups, and increases burst length from 8 bytes to 16 bytes. The math here is straightforward enough. With DDR4, you can transfer 64 bits of data over the interface at a burst of 8 bytes, giving you 64 bytes of data and aligning with cache line sizes. Each of the subchannels in DDR5 can transfer 64 bytes of data, as well, with a 32-bit width and burst length of 16 bytes.

It’s pseudo-dual-channel memory on a single DIMM. There are two independent memory operations that can happen each cycle, both of which transfer 64 bytes of data. That is a big reason why even a single DDR5 DIMM (particularly one with a higher data rate) can outpace even a proper dual-channel DDR4 configuration.

The common wisdom about using a single DIMM comes mainly from previous DDR generations, where you can only get that single 64-byte transfer each cycle, necessitating a second DIMM to have two independent operations.

Let me be clear: two DDR5 DIMMs are still better. Instead of two operations per cycle, you can perform four. The main difference is that, for modern CPUs and games, just those two operations give you the vast majority of your performance, and you don’t run into a massive performance bottleneck as you do with just a single operation via DDR4. After all, there are still a lot of DDR4 systems out there.

On the issue of compatibility

The elephant in the room with upgrading to a DDR5 platform with a single DIMM is compatibility. If you get a single DDR5 DIMM now, you should plan to add another in the future. Unfortunately, there aren’t a lot of easy answers when it comes to combining two DIMMs that aren’t in a kit together. It should work, but mixing and matching can lead to stability issues and/or lowered performance.

Generally, combining two DIMMs of the same spec should work. For instance, if you bought this Patriot Viper Venom DDR5-6000 CL30 DIMM to start your new build, and then bought a second one later, it should work. “Should” carries a lot of weight on its shoulders, however. Maybe Patriot sources DRAM from multiple places, or your second DIMM’s timings don’t completely align with your first. That could cause stability or performance issues.

There have been some attempts to get past this hurdle, such as the ROG Certified program with select Asus motherboards, but it’s impossible to know for sure if two separate DIMMs will work together or not without testing. The best you can do is to make sure you buy the same brand of memory, with the same spec, if you add a second DIMM. Make sure to keep your receipt handy in the event you need to return it, as well.

Once you have your second DIMM, make sure to test it first at stock JEDEC speeds/timings (no XMP/EXPO). Run games or applications you normally run, and then use a utility like MemTest64 to check for stability. I’d recommend keeping your PC running in this state for a few days to see if any BSODs, application crashes, or poor performance issues pop up. After that’s done, repeat the process with XMP/EXPO enabled, assuming you’re using matching DIMMs (incompatible XMP/EXPO profiles won’t work together).

Assuming DRAM prices continue at an elevated rate before you upgrade, you may want to consider investing in a dual-channel kit down the line and selling your single DIMM. Even kits can run into compatibility issues, though the likelihood is far, far lower.

Memory supply from major DRAM manufacturers to independent module makers could drop to just 30% of the amount supplied in 2026 next year, according to C.K. Chang, CEO of Taiwanese memory vendor Apacer, further tightening an already squeezed supply chain.

Chang made the comments during the company's 1H 2026 investor conference on July 24, and in subsequent media interviews after the conference. Although memory price increases are expected to slow during the second half of 2026 — reportedly due to consumers deciding that RAM is too expensive — he believes severe shortages will persist into at least the middle of 2027, and that DRAM will remain the most constrained segment.

According to Chang, the greatest risk facing Apacer, which buys memory wafers from manufacturers such as SK Hynix and Samsung and turns them into finished memory products, is no longer overpaying for the chips, but failing to obtain any supply at all.

In preparation for growing shortages and to prevent a wider shortfall next year, the company says it grew its inventory to NT$12.4 billion ($383.2 million USD) at the end of June, up from NT$8.38 billion ($259 million USD) one quarter earlier, representing an increase of approximately 48%. The company is also arranging a five-year syndicated loan of up to NT$4 billion ($123.6 million USD) to purchase additional chips whenever manufacturers make them available, among other needs.

Chang’s projection does not mean worldwide DRAM production will fall by more than 70%. His statement specifically refers to the volume major chip manufacturers may allocate to downstream module companies such as Apacer, which purchases memory chips and packages them into DIMMs, SSDs and embedded storage products. DRAM manufacturers are increasingly reserving their output for high-bandwidth memory (HBM), server memory, and other products purchased directly by large AI and cloud customers.

Samsung, SK Hynix and Micron — the world's biggest memory chip makers — are prioritizing higher-margin HBM and advanced server memory as AI infrastructure spending consumes an increasing share of available manufacturing capacity. Chang estimates that approximately 60% of DRAM capacity is now directed toward server-related applications, leaving conventional DDR4 and DDR5 products competing for a shrinking portion of the market.

DDR5 RDIMM server modules have received some of the most aggressive price increases and retain the greatest potential for future mark-ups, according to Chang. Demand from AI servers, enterprise storage, industrial computers and edge AI systems remains strong, while consumer PC and smartphone demand is considerably weaker and more sensitive to rising component costs. That weaker demand is, of course, mostly in comparison to the AI industry. Consumer demand remains strong enough to mop up the shrinking supply. The RAM shortage is now reportedly affecting the price of cars, far beyond consumer electronics.

NAND flash is also being pulled into the AI boom. High-capacity enterprise SSDs are increasingly being used for model storage, data staging and key-value cache offloading, allowing colder portions of AI workloads to spill out of expensive DRAM. Flash cannot replace DRAM outright because it offers considerably lower bandwidth, but it can still serve as a tier within AI memory systems, increasing demand for enterprise SSDs and NAND alongside server memory.

Chang expects DRAM contract prices to rise by approximately 30% during the third quarter of 2026 and NAND flash to increase by more than 20%. He expects price growth to moderate again during the fourth quarter.

Elsewhere, analysts project a 40% increase in DRAM prices in Q3 2026, even as demand extends to the oldest standards still in production. Samsung and SK Hynix, both South Korean companies — who together with US-based Micron Technologies control over 90% of the global DRAM market — had earlier warned that shortages could last beyond 2027. And the CEO of Adata projects that the global DRAM shortage will run for another 10 years.

Chinese manufacturers are not expected to provide immediate relief. Chang said Chinese memory maker CXMT’s DDR5 products had become competitive and that both CXMT and Chinese NAND producer YMTC had narrowed their pricing gaps with established international suppliers. However, domestic demand in China already exceeds available supply, while capacity expansion, manufacturing yields, product validation and platform compatibility continue to limit their ability to change the global balance. Furthermore, the prices of new DRAM modules from CXMT are reportedly similar to those of the big three.

Stockpiling memory inventory at historically high prices carries the risk of substantial losses if the market suddenly reverses. Apacer, however, says it has seen no evidence of an approaching collapse. For now, the company is betting that possessing expensive memory in 2027 will be considerably better than having no memory to sell at all.

Unless you already have a kit of DDR5, or deep pockets for PC hardware, you’re stuck right now. Despite seeing some of the best CPUs for gaming released just in the past year, the DDR5 tax represents a major hurdle to building or upgrading your PC. Intel’s LGA 1700 CPUs hold an unintended solution, offering support for both DDR4 and DDR5. We wanted to see if this on-ramp to a next-gen platform was really as smooth as it looks at first glance.

The idea is simple. If you already have a DDR4 kit, you can upgrade to a relatively new CPU while keeping the door open for a transition to DDR5 without buying a new chip. It’s inexpensive, and a bit more of a practical solution than upgrading to DDR5 with a single DIMM and worrying about pairing it with another later.

Our testing shows how much of a performance difference there is with DDR4 in games. We’re focused on games here for a few reasons. First, in non-gaming applications, memory speed is highly dependent on the specific workload you’re running. Games, despite using different engines, are largely similar workloads that stress the hardware in similar ways. Further, those workloads are continually evolving as new games, new technologies, and new hardware targets are released.

We kept our testing focused on Intel’s LGA 1700 CPUs because they’re the only options that give us a true apples-to-apples comparison between DDR4 and DDR5. We don’t have any AMD CPUs in our test pool because there aren’t any chips that support both DDR4 and DDR5. This isn’t intended to be a competitive analysis between AMD and Intel. That conversation opens up a much broader conversation about total platform cost.

Testing DDR4 vs. DDR5 on Intel’s LGA 1700 CPUs

To test DDR4 and DDR5’s gaming performance, we ran Intel’s main LGA 1700 stack through a 15-game gauntlet of benchmarks. Notably, we don’t have results for the Core i9-12900K, as our sample has a janky memory controller that won’t boot on DDR5 systems. You can read a full breakdown of how (and why) we tested in the way we did in the section below.

We ran all of the games through our 16-game benchmark suite, though we cut Doom: The Dark Ages from the results here. An update for the game rolled out mid-way through testing and skewed our results, so we’re omitting it. The 15 remaining games still paint a clear picture of the performance difference between DDR4 and DDR5.

As usual, we tested with the RTX 5090 Founder’s Edition at 1080p with a mixture of High and Ultra settings. We test at 1080p to maximize the differences between CPUs, and it remains the most widely-used resolution for gaming. Deltas between CPUs will decrease as the resolution climbs and the GPU becomes a larger influence in performance.

Below is our geomean from testing across the suite. Given that we’re looking to compare a single CPU’s performance with DDR4 and DDR5, we’ve highlighted some CPUs with the same color (13700K is always dark red, for instance, while 14700K is always dark blue).

The chart above is a bit difficult to parse, mainly because we’re often jumping several entries to get to a comparison point. For the stack of chips we tested, here’s a clearer overview of the performance difference with DDR4:

As we’ll get into with the individual game tests below, the drop in performance between DDR4 and DDR5 can be much larger than the comparison in our geomean (and, in turn, smaller in other games). What’s important for the overall performance drop is the trend as we move to newer chips. You can see a 9% drop grow to 14%, as DDR4 becomes a more significant bottleneck when the processor it’s feeding becomes more powerful.

That trend is one of the main driving forces behind our look at DDR4 and DDR5 gaming performance today. We looked at DDR4 and DDR5 performance extensively near the Alder Lake launch, and even more recently last year, evaluating performance across a wide range of applications. The testing here is focused solely on gaming to answer a critical question of building a PC today: Are you really giving up that much gaming performance with DDR4?

The answer is, yes, you’re giving up around 11% to 14% of your gaming performance overall when the memory is the only variable that changes. That’s a consistent drop, as well. Older titles care see less of a benefit from DDR5 generally, but we saw a steady decrease of around 11-14% across the games we tested, with some titles pushing above a 20% drop.

007 First Light is the newest game we tested, and it outpaces our averages. The 14900K sees a 16.5% drop with DDR4, while the 13600K drops 12.7% of its performance. Especially among the most powerful CPUs here, you can see DDR4 level off performance in a way that’s undesirable. The 14900K, for instance, is just 1.7% faster than the 13900K with DDR4, but it’s 4.6% faster with DDR5.

Similarly, in Crimson Desert, you can see the 13700K lose 13.7% of its performance with DDR4, and the 14600K drop 13.2% of its performance. It’s worth noting that neither of these games are particularly sensitive to memory speed. You can see in our recent Ryzen 7 5800X3D re-review that even a boost from 3D V-Cache doesn’t give CPUs with a robust memory chain an automatic advantage.

Perhaps the most consequential of the newer games we tested is Marvel Rivals, not only because it shows a much larger gap between DDR4 and DDR5, but also because it’s the most-played game in our test suite by a long shot (short of Counter-Strike 2). For weaker chips like the 12600K, the gap is 13.9%, just slightly above our geomean. For the more powerful 14700K, however, it shows a gap of 25.3%. Even the 14600K drops 17.4% of its performance with DDR4.

Counter-Strike 2 is less extreme, perhaps as a consequence of having such a high floor for average frame rates. You can see that the Alder Lake chips don’t care much about DDR4, with the Core i7-12700K performing identically across both memory standards. That gap grows with more powerful CPUs, however, with the 14700K creeping up toward a 10% delta.

In Spider-Man 2, we can see more consistent drops across the stack of chips we tested, with most CPUs dropping around 18% of their average performance with DDR4. That’s true even on the weaker 12700K, which lost 15% of its performance. The 14900K, meanwhile, was 18.7% slower with DDR4.

Even in an older, GPU-heavy title like Cyberpunk 2077, we can see a consistent drop. You can see in this game that we become completely bound by the GPU at the top of the rankings, but that’s a level these chips can’t hit when paired with DDR4. The 14700K drops about 14% of its performance, and the 13600K, about 13% of its performance.

You can browse through our remaining benchmarks using the gallery above, but most games tell a similar story. The gap between DDR4 and DDR5 persists, of course, but there’s another angle to look at the data. DDR4 flattens off performance, creating a bottleneck with faster CPUs. That could be justification for buying a weaker chip if you can only afford DDR4 memory right now.

Outside of performance, one important aspect of using a DDR4 system compared to DDR5 is power consumption. With DDR4, power consumption of the CPU increases, as you can see in the chart above. The jump is generally only a few watts, but it’s worth noting nonetheless. In games, we’re well below the operating temperature of all the chips in our test pool, but when pushing toward maximum power draw, DDR4 will post yet another limitation.

How (and why) we tested DDR4 vs. DDR5 now

DDR5 is way too expensive, and Intel’s LGA 1700 CPUs represent a unique value proposition given the unprecedented increases in memory prices over the past several months. The idea is that you can upgrade to a newer platform while sticking with DDR4, giving you a stopgap for an eventual DDR5 upgrade. It seems Intel recognizes this value proposition, as well, as it’s reportedly slated to launch Raptor Lake Next CPUs on the LGA 1700 socket.

We tested the main stack of chips, short of the Core i9-12900K, as described above. We didn’t test variants like KS releases to keep our testing focused, as well as lower-end SKUs like the 12100F or 14400. The memory controllers in these lower-end chips are weaker, sustaining lower DDR5 speeds, so expect less of a difference in performance with them.

Below, you can see the test benches we used. In addition to keeping hardware consistent, we use a frozen OS image with an identical software stack. We’re running the same version of the same apps on the same OS update, with identical drivers.

In the BIOS, we enabled XMP for both kits of memory. We also tested with Resizeable BAR turned on, and Virtualization-Based Security (VBS) turned off. Most motherboard vendors off a profile with the power limits removed on Intel CPUs, which can push the processor outside of warrantied specifications. We stuck with the default “Performance” profile for our testing here.

Is DDR4 still worth it?

It makes sense that we’ve seen a shift back toward DDR4. Although DDR4 prices have risen in lockstep with DDR5 prices, they started from a much lower base. A kit of DDR4 today is not much more expensive than a DDR5 kit of similar capacity a year ago. And, with estimates that the memory shortage could persist through 2030, there’s a strong argument for going with a DDR4 system if you’re in need of an upgrade.

The performance trade-off alone isn’t as big of a problem as it appears at first glance. You’re going to lose about 15% of your average gaming performance with Intel’s LGA 1700 CPUs (particularly Raptor Lake chips). You’ll spend more than twice as much on a 32GB kit of DDR5-6000 as you will on a 32GB kit of DDR4-3200, as you can see in our RAM price tracker. And, you might already have a DDR4 kit, cutting that cost completely out of an upgrade. Dollars spent for performance gained, DDR4 makes complete sense.

However, performance isn’t the only factor at play, and that’s the unfortunate reality of using a DDR4 platform right now. It’s a dead end, both for performance and upgrade potential. As we saw in our recent testing of the Ryzen 7 5800X3D, there’s a performance wall in games with DDR4, one which the 5800X3D often runs up against. The memory is a bottleneck, and it doesn’t seem like there’s a way around that problem without upgrading to DDR5.

We also aren’t seeing any new DDR4 CPUs, at least right now. AMD re-released the Ryzen 7 5800X3D, and there are murmurs of Raptor Lake Next. But given the current landscape, we don’t expect a CPU that will radically change the performance you can get out of a DDR4 platform.

Instead of sticking with DDR4 for a better CPU, the best course of action right now is to bite the bullet on DDR5 and buy a weaker CPU, particularly if gaming performance is your main concern. Given that memory prices are out of control, there are excellent deals on DDR5 CPUs right now, allowing you to offset the cost of an upgrade and giving you a kit of DDR5 to carry forward in future builds.

As an example, AMD’s recently-released Ryzen 7 7700X3D is $80 cheaper than the re-released Ryzen 7 5800X3D, despite coming in nearly 20% faster in average gaming performance. The $230 Ryzen 5 7600X3D shows similar gains, and it’s even more affordable.

In Intel’s camp, the Core Ultra 7 270K Plus and Core Ultra 5 250K Plus represent some of the best all-around value in the CPU world right now, with compelling gaming performance and chart-topping application performance, all for around $300.

You will spend more on a cheaper CPU and a kit of DDR5. There’s no indication that the memory shortage is ending soon, however. We’ve actually seen prices continue to increase despite the surge leveling off. Opting for DDR5 today buys you better gaming performance, but more importantly, it gives you a kit of memory that you can continue to use as new CPUs and platforms are released.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.