Nikon will try to win back lithography customers by selling argon fluoride (ArF) tools for less than market leader ASML, the company's new president and chief executive, Yasuhiro Ohmura, told Nikkei Asia in a recent interview. Ohmura, who took the role in April, said Nikon is talking to several large chipmakers in the U.S. and Asia about fresh ArF orders, with discussions "nearing purchase orders."

Nikon’s pitch to customers comes after a brutal stretch for the business: Nikon shipped 11 ArF systems in its fiscal year ending March 2024 and none across the first three quarters of its 2025 fiscal year, according to company figures reported by TrendForce, against ASML's grip on more than 80% of the lithography market.

Competing on price like this targets a segment of the market that ASML doesn’t outright dominate. While it holds an obvious monopoly position on extreme ultraviolet (EUV) systems used for the most advanced chipmaking processes, ArF immersion is a type of mature deep ultraviolet (DUV) work, and the majority of patterning steps, even on a 3nm chip, still run on it. ASML's advanced ArF immersion machines average around $82.5 million per unit, leaving room for a cheaper rival. Nikon walked away from EUV in 2008.

In February, Nikon said that it would launch a new ArF immersion platform in its 2028 fiscal year, fitted with a new lens and wafer stage, and built for compatibility with ASML's installed tools. "We manufacture many parts in-house, giving us an advantage in cost competition," Ohmura told Nikkei Asia.

Nikon and ASML are the only two companies that build ArF lithography equipment, and demand is climbing as the AI bubble strains tool supplies. ASML shipped 48 EUV and 131 immersion DUV systems in 2025 and closed the year with a €38.8 billion order backlog. Ohmura argues that chipmakers would rather buy from two suppliers than depend on one to keep a lid on equipment costs.

Whether price alone will pull customers back remains to be seen. Nikon's ArF market share has kept sliding since ASML pulled ahead through long-term R&D partnerships and exclusive handling of cutting-edge tools, and Intel, which once accounted for 80% of Nikon's ArF orders, has cut spending amid its own manufacturing troubles.

Nikon posted a net loss of 86 billion yen ($540 million) for the year ended March, its worst ever, dragged down by weak equipment orders and a struggling metal 3D printing unit. Ohmura says he plans to narrow Nikon's focus to cameras and chipmaking tools.

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

The Dutch company holds a 100% monopoly on EUV lithography and approximately 83% of the global lithography market overall, and its roadmap now spans four distinct generations of technology: DUV immersion systems that still handle the majority of layers on every advanced chip, low-NA EUV scanners that enabled the 5nm and 3nm era, High-NA EUV tools now entering early production at Intel and Samsung, and a Hyper-NA concept that remains in feasibility studies for the 2030s.

Each step up this ladder delivers finer resolution at exponentially higher cost and complexity, and just how aggressively the industry's largest chipmakers adopt each generation will determine the pace of transistor scaling for the next decade and beyond.

DUV immersion and low-NA EUV

ASML's DUV immersion systems are still the backbone of semiconductor manufacturing when it comes to volume production. The company sold 131 immersion DUV tools in 2025. Even a chip built on TSMC's 3nm node uses EUV on only a handful of critical layers; the majority of patterning steps still run on DUV immersion tools like the TWINSCAN NXT:2100i, which delivers 295 wafers per hour at 1.35 NA with 1.3nm overlay.

DUV single-exposure is also the standard in mature nodes powering automotive and industrial chips. While DUV multi-patterning can push down to 7nm and even 5nm, it comes at an enormous cost of up to 34 patterning steps at 7nm versus nine with EUV.

Chinese customers purchased an estimated 70% of ASML's DUV immersion systems in 2024, stockpiling ahead of tightening Dutch export restrictions that now cover the NXT:1970i and newer models. SMIC demonstrated 7nm production using DUV multi-patterning for Huawei's Kirin 9000S, according to TechInsights. But the process requires significantly longer cycle times than EUV-based production, and questions exist around whether yields are sufficient for volume commercialization.

On the EUV side, ASML's low-NA systems operate at 0.33 numerical aperture with 13.5nm wavelength light, achieving 13nm single-exposure resolution. The TWINSCAN NXE:3600D, introduced around 2021, delivers 160 wafers per hour with 1.1nm matched-machine overlay. Its successor, the NXE:3800E, began shipping in March 2024 and pushes throughput to 195 wafers per hour, upgradable to 230 — following ASML's recently updated roadmap — while tightening overlay below 1.1nm. Each NXE:3800E costs roughly $180 million. It shares its bottom module, including wafer handler and faster stage mechanics, with the High-NA EXE platform, a decision that reduces ASML's manufacturing complexity and provides fabs with a degree of serviceability continuity when they upgrade.

ASML's roadmap extends low-NA further, with the NXE:3800F expected around 2027. It targets a ≤0.9nm overlay and over 260 wafers per hour. A subsequent NXE:4200G targets a ≤0.8nm overlay and over 300 wafers per hour, with an NXE:4200H beyond that at a ≤0.7nm and 330 wafers per hour. Further out, ASML has disclosed a High Productivity platform, the NXE:4600, targeting 400 wafers per hour or more.

TSMC has confirmed that it will not use high-NA EUV for its A16 (1.6nm) or A14 (1.4nm) nodes, instead relying on low-NA with multi-patterning. Kevin Zhang, TSMC's Deputy Co-COO and Senior Vice President of Business Development, said at the company's European Technology Symposium last May that TSMC would adopt high-NA "whenever we see high-NA will provide meaningful, measurable benefit," adding that the technology team continues to extend the life of current EUV.

Computational lithography is one reason low-NA can stretch further, with ASML's Brion subsidiary developing inverse lithography technology and curvilinear mask optimization software that computationally corrects for optical distortion beyond specification, effectively squeezing better resolution from existing 0.33 NA optics without hardware changes.

TSMC has been a major user of these techniques, and their continued advancement narrows the gap between low-NA double patterning and High-NA single exposure. ASML's installed base management business, which services and upgrades the global fleet of lithography tools, reached €8.2 billion in revenue in 2025, up 26% year-over-year. That recurring revenue stream grows with every tool shipped and is increasingly important as fabs push older systems to higher utilization rates.

High-NA EUV

The jump to 0.55 numerical aperture with high-NA is the largest optical leap in EUV's history, shrinking minimum resolution from 13nm, which itself was down from 30nm with DUV, to 8nm and enabling approximately 2.9 times higher transistor density in a single exposure. ASML's first High-NA tool, the EXE:5000, shipped to Intel in December 2023 as a development platform.

Each unit of the production-capable EXE:5200B weighs in at 150,000 kilograms, requires 250 shipping crates, and takes six months and 250 engineers to assemble on-site, says Intel. Priced at approximately $380 million, the EXE:5200B delivers 175 wafers per hour at 50 mJ/cm² dose with 0.7nm overlay. ASML told Reuters in early 2024 that it had taken 10 to 20 orders by that point and planned to deliver 20 annually by 2028.

Intel announced that it had completed acceptance testing of its EXE:5200B in December 2025 at its Hillsboro D1X fab and that the tool will be used for the development of Intel's 14A fabrication process. 14A is expected to be the first production node to rely on High-NA for its most critical layers, with risk production targeted for 2027.

In September, SK hynix became the first memory manufacturer to install a commercial High-NA system at its M16 fab in Icheon, South Korea. Samsung, meanwhile, received its first EXE:5200B in October, with a second unit due in the first half of 2026 for its 1.4nm foundry node. Imec, the Belgian research institute, secured an EXE:5200 last month with a Q4 2026 qualification target for sub-2nm process development.

ASML's near-term High-NA roadmap includes the EXE:5200C, targeting 190 wafers per hour without stitching and 160 with stitching at sub-0.8nm overlay, followed by the EXE:5200D at 195/175 wafers per hour and eventually the EXE:5400E at 210/180 wafers per hour with sub-0.7nm overlay. A High Productivity variant, the EXE:5600, targets 250 wafers per hour or more.

Analysts from SemiAnalysis believe TSMC won’t adopt High-NA EUV until its 1nm-class A10 node, which would place volume deployment around 2029 to 2030, because existing low-NA EUV systems can match High-NA's 8nm resolution using double patterning, and SemiAnalysis estimates that approach may still cost less than High-NA single patterning. High-NA tools also require substantial changes to existing fab buildings to accommodate their size.

Hyper-NA and pellicles

ASML placed Hyper-NA on its official roadmap for the first time at imec's ITF World in May 2024, with former CTO Martin van den Brink commenting a few months prior that an NA above 0.7 "is certainly an opportunity that will become more visible from around 2030." The primary target is 0.75 NA, with 0.85 NA also under investigation. Zeiss has begun preliminary lens designs. Estimated tool cost: roughly $720 million per system, according to TrendForce.

At 0.75 NA, however, polarization effects begin destroying imaging contrast because one polarization orientation effectively cancels light at extreme incidence angles, thereby necessitating the use of polarizers that block photons and reduce efficiency. Depth of focus shrinks further, and resists must be made even thinner than the sub-30nm films used for high-NA, worsening etch selectivity and stochastic defects from photon shot noise. On top of all that, an electron blur of approximately 2nm may impose a solid resolution barrier regardless of optical improvements.

Pellicle development is another bottleneck. These ultra-thin membranes protect masks from particle contamination during exposure but must transmit EUV light efficiently at rising source power levels. ASML's current composite silicon-based pellicle achieves over 90% transmission at 380 W source power, but for future systems running at 600 W to 1,000 W, carbon nanotube pellicles are the next-gen technology, achieving up to 97% transmission while withstanding temperatures above 1,500 C. Mitsui Chemicals is building dedicated CNT pellicle production capacity targeting 5,000 sheets per year and commercialization aimed for this year.

Export controls and Canon NIL

EUV systems have never been sold to China, blocked since 2019 under U.S. pressure despite existing orders from Chinese customers. In addition, Dutch export controls, effective since late 2023, required licenses for advanced DUV immersion systems (NXT:2000i and newer), and by September 2024, the restrictions expanded to include the NXT:1970i and NXT:1980i.

Servicing restrictions also prohibit ASML from improving overlay accuracy or increasing throughput by more than 1% on installed Chinese systems. China represented 49% of ASML's revenue at the peak of stockpiling in Q2 2024, falling to roughly 36% for full-year 2024. ASML's management guided China to approximately 20% of revenue in 2025 and 2026, which has seen South Korea and Taiwan emerge as the primary growth markets, with SK hynix alone placing a record $7.9 billion EUV order last month covering roughly 30 systems over two years.

Canon's FPA-1200NZ2C nanoimprint lithography system, announced in October 2023, represents the only credible alternative patterning approach. At roughly $15 to $20 million per system with 90% lower power consumption than EUV, it uses direct mechanical pattern transfer rather than optical exposure. Canon delivered the first commercial unit to the Texas Institute for Electronics in September 2024, and its current specs show some significant limitations: 80 to 100 wafers per hour (versus 195+ for low-NA EUV), 14nm minimum linewidth, and 2.4 to 3.2nm overlay (versus sub-1.1nm for EUV).

Japan's Dai Nippon Printing (DNP) is targeting 2027 mass production of 1.4nm-class nanoimprint templates, but no major foundry has committed to NIL for high-volume logic manufacturing. The technology's likely niche remains repetitive memory patterns, particularly high-layer-count 3D NAND, where its cost advantage could outweigh the throughput and overlay penalties. Defect density from direct physical contact between template and resist remains the fundamental barrier to logic adoption, where a single misplaced particle can kill an entire die.

ASML revenues continue climbing

ASML's 2025 results reflect the sheer scale of its roadmap, with €32.7 billion in revenue (up 16% year-over-year), 52.8% gross margin, and €9.6 billion net income. EUV became the leading source of system revenue at 48%, or €11.6 billion, up 39% from 2024. Net bookings surged 48% to €28 billion, with Q4 2025 alone delivering a record €13.2 billion in orders. The company recognized revenue on two High-NA systems during the year.

ASML's Q1 2026 results, published April 15, show €8.8 billion in total net sales at 53% gross margin, with €2.8 billion net income. The company shipped 16 EUV and 17 immersion DUV systems in the quarter, with South Korea accounting for 45% of system sales by region and China at 19%. ASML raised its full-year 2026 revenue guidance to €36 to €40 billion, with 51% to 53% gross margins

Each NA increase delivers diminishing resolution gains at exponentially rising cost and complexity. The most likely trajectory is not a clean generational handoff but an extended coexistence: low-NA handling the bulk of EUV layers well into the 2030s, High-NA reserved for the most critical pitches at sub-2nm nodes, and Hyper-NA arriving as a targeted tool for the most extreme features, subject to workarounds for the bottlenecks we’ve discussed above.

A group of U.S. lawmakers this week sent a letter to the U.S. State and Commerce Departments calling to reinforce restrictions on wafer fab equipment (WFE) exported to China. The group calls to restrict the sale of virtually all chipmaking tools to China. With the exception of those that can be manufactured domestically in the People's Republic of China (PRC). In addition, the group demands the U.S. to work with allied nations and ensure that they implement similar export policies, thus banning sales of all advanced chipmaking tools to the PRC.

The group led by House Select Committee on China Chairman John Moolenaar and House Foreign Affairs Committee Chairman Brian Mast sent the letter to Secretary of State Marco Rubio and Secretary of Commerce Howard Lutnick demanding to impose more robust curbs on exports of semiconductor production tools to China and use diplomacy to make allied nations follow. Right now, American companies need an export license to ship WFE tools to China-based entities. These tools that can be used to make logic chips on 14nm/16nm manufacturing technologies, produce DRAM on 18nm-class half-pitch fabrication process, and fabricate 3D NAND with 128 or more layers. At the same time, American companies can obtain an export license and supply these very tools to entities that formally do not produce the aforementioned semiconductors. The new set of rules proposed by the group prohibit to sell any WFE to China-based entities except tools that can be manufactured locally in China.

The lawmakers argue that existing controls remain incomplete as certain foreign-produced 'chokepoint tools' (i.e., advanced lithography systems by ASML and sophisticated etching and deposition tools by Tokyo Electron) are restricted only when destined for specific Chinese entities rather than being subject to broad country-level limitations.

They note that once equipment enters China, enforcement becomes difficult because verification visits require approval from Chinese authorities, which can take weeks or months to arrange, and are conducted under supervision. As a result, Chinese companies like SMIC can continue develop their process technologies using advanced manufacturing tools, whereas various entities funded by Huawei or even the federal government can reverse engineer these machines to build similar systems locally.

Reverse engineering of existing tools and subcomponents is another point of concern raised by the lawmakers. Despite the efforts of the U.S. government, Chinese companies retain access to the subcomponents of chipmaking equipment, which not only enables them to fix existing tools, but also reverse engineer these parts. Without tighter export controls on spare parts, China could eventually replace foreign equipment with locally developed alternatives, lawmakers believe.

"We urge the Administration to press allies to implement countrywide controls on key chokepoint semiconductor manufacturing equipment and subcomponents: that is, all equipment and subcomponents that China cannot produce indigenously," the letter reads. "This engagement should include clear and reasonable deadlines, after which the United States should be prepared to act to close remaining gaps itself if necessary, including by prohibiting the use of U.S.-origin components in the production of chokepoint tools destined to China."

The letter also mentions servicing of WFE as a potential area for even tighter regulation as now these rules adhere to export control rules, which means that certain restricted advanced systems can still be serviced as long as they are installed at an approved buyer. As these systems require ongoing maintenance and technical support to remain operational, limiting servicing could be a way to reduce practical lifespan of already installed equipment.

"The window to secure America's semiconductor advantage is narrowing," the letter concludes. "We request a briefing within the next month on the Administration's strategy for securing allied cooperation on countrywide controls on chokepoint semiconductor manufacturing equipment and components and the timeline for achieving this goal. We stand ready to work with you on a bipartisan basis to ensure our export control regime and the alliances that support it are equal to this challenge."

Chinese fabs are quietly extending the useful life and performance of older ASML deep ultraviolet lithography systems by upgrading key subsystems, as Beijing pushes to sustain advanced chip output under tightening U.S. and allied export controls, according to the Financial Times. The effort concerns installed immersion DUV tools, particularly ASML’s Twinscan NXT series. It’s understood that these activities have been underway over the past year at several leading-edge Chinese fabs, including those operated by SMIC and other state-backed manufacturers.

With access to EUV scanners cut off and new restrictions narrowing what ASML can legally service or upgrade, Chinese firms are increasingly turning to reverse engineering and grey-market components to improve overlay accuracy, stability, and throughput on tools originally designed for older process nodes. While this upgrade activity will never bring older DUV machines to parity with newer EUV machines, it could provide Chinese manufacturers with a meaningful recovery of capacity at advanced DUV-based nodes that remain commercially viable.

A growing ecosystem

Export controls imposed by the U.S. and its allies were primarily designed to prevent the export of cutting-edge technologies to China. For lithography, that meant blocking EUV outright and, more recently, placing tighter licensing requirements on the most capable immersion DUV scanners.

While these measures have worked as intended at the point of sale, they haven’t eliminated the installed base of immersion scanners already operating inside China. Over the past decade, Chinese fabs acquired dozens of high-end DUV tools, which now form the backbone of China’s most advanced production lines, particularly for 14 nm, 10 nm, and experimental 7 nm-class processes that rely heavily on multipatterning. Despite tens of billions in capital expenditure on chipmaking tools, China remains more than a decade behind current market leaders.

Under current rules, ASML is allowed to provide basic maintenance and support to keep these tools running, but it is restricted from performing upgrades that would materially improve performance beyond narrow thresholds. That has created a gap between what the original equipment manufacturer can legally do and what fabs are technically capable of doing with the right parts and expertise.

Into that gap has stepped a growing ecosystem of third-party suppliers and engineers. According to the report, Chinese fabs have sourced replacement or upgraded components such as wafer stages, optical elements, sensors, and control subsystems through secondary markets. Some of these parts originate from dismantled tools outside China, while others are produced by suppliers that operate in regulatory grey zones. Installation and calibration work is carried out by independent engineers, including former lithography specialists, rather than by ASML personnel.

This might sound inconsequential on the face of it, but with an outright ban on exports of new tooling, marginal improvements to existing tools compound quickly across high-volume lines. A small improvement in overlay stability can translate into higher yields across dozens of layers.

Overcoming overlay challenges

The primary challenge Chinese fabs will face in upgrading older DUV machines is overlay — the precision with which each new lithography layer aligns with previously-exposed layers. At older nodes, modest overlay errors are tolerable, but not at advanced nodes manufactured without EUV. Multipatterning schemes such as self-aligned double or quadruple patterning dramatically increase the number of exposures required per layer, and each exposure introduces additional misalignment risk.

ASML’s own product pages for the NXT immersion platform make clear how tightly overlay and system stability are linked. Wafer stage accuracy affects not only positioning but vibration and thermal drift, both of which become limiting factors as pattern density increases. Upgrading or replacing these subsystems can claw back some performance that would otherwise be lost to wear and aging. Even without changing the core exposure wavelength or numerical aperture, better stages and sensors can improve effective overlay and reduce the number of wafers scrapped due to misalignment.

This does not eliminate the structural disadvantages of DUV at 7nm-class geometries: Cycle times remain longer than EUV-based processes, costs per wafer are higher, and yields are generally lower. But for products where absolute cost is less critical than domestic supply and technical continuity, these penalties are acceptable.

Limits of enforcement

From a policy perspective, the actions of these firms highlight a shift in which enforcement pressure must be applied to constrain output. Blocking new tool shipments has already occurred, so the harder problem is constraining the flow of parts, expertise, and process knowledge that keeps existing tools competitive — at least for now.

Updates to U.S. BIS rules last year point in this direction, with expanded controls on semiconductor manufacturing equipment components, software, and services. Restrictions increasingly target not only lithography scanners themselves but also metrology tools, process control software, and advanced sensors that indirectly affect yields. The logic is to close the pathways that allow incremental upgrades to accumulate into meaningful capacity gains.

Even so, enforcement potential is limited. Lithography tools are complex systems with long service lives, and many components are designed to be replaceable. Distinguishing between a like-for-like replacement and a performance-enhancing upgrade is technically and legally difficult, particularly when work is performed by third parties rather than the OEM.

China, for its part, seems to be pursuing parallel strategies. Stretching DUV capability through upgrades is one track; developing domestic lithography tools is another. SMIC has tested homegrown immersion DUV prototypes, and state-backed programs continue to fund long-term EUV research, even if breakthroughs remain distant.

At the end of the day, we’re not about to see a sudden leap in Chinese semiconductor capability because a few fabs have upgraded their machines. What we could see, however, is a slower erosion of the gap that export restrictions were designed to maintain.

DUV will continue to significantly lag EUV-based competitors on both cost and efficiency, but they are unlikely to stagnate at their initial performance levels. Incremental improvements in yield and throughput can sustain meaningful volumes of advanced chips for domestic use, particularly in areas such as networking silicon and specialized processors.

Japan’s Dai Nippon Printing (DNP) claims to have developed a nanoimprint lithography template capable of patterning logic with a feature size of 1.4nm, with plans for mass production in 2027. Canon, which has spent years pursuing nanoimprint lithography as a lower-power alternative to EUV, is already shipping its first 300mm tools to early research partners.

Together, the companies are pointing to imprinting as a way to cut lithography power consumption by up to 90% for advanced nodes. With TSMC and Samsung preparing for 1.4nm mass production within the next few years, DNP’s announcement comes just as EUV’s cost and energy demands are escalating the fastest in leading-edge fabs. The technology promises a dramatic shift in the economics of chipmaking, but whether it can meet the defectivity, overlay, and throughput requirements of high-volume logic remains an open and pressing question.

Skyrocketing energy use

The industry has grown accustomed to talking about how much power finished AI chips consume, yet the energy needed to fabricate those chips has grown at a comparable pace. EUV scanners each consume as much power as a small city — 1,400 kilowatts per tool — meaning that modern fabs that run several dozen EUV units must reserve enormous electrical capacity before a single wafer is exposed. This rising power use is compounded by the fact that shrinking features below 2nm increase the number of passes and exposures required, raising energy consumption per wafer for next-gen high-NA EUV.

Canon, which has long argued that the industry needs an alternative, offers a nanoimprint lithography (NIL) system that patterns wafers by stamping a pre-formed template directly into resist rather than projecting a pattern optically. That equipment can be priced much lower than EUV, and Canon has claimed that the technology uses up to 90% less power. Just last year, the company delivered its first commercial FPA-1200NZ2C tool to the Intel- and Samsung-backed Texas Institute for Electronics, 20 years after NIL research began.

NIL has been looked upon with some skepticism in recent years due to its incompatibility with both DUV and EUV, and the more conventional view that NIL could not meet the overlay stability or defectivity requirements needed for tightly packed logic at sub-2nm geometries. DNP’s new template material is the first attempt to challenge that assumption with concrete specifications and a timeline to commercialization.

The 1.4nm window

DNP’s template reportedly achieves 10nm line widths and is being evaluated ahead of planned mass production in 2027. Meanwhile, TSMC’s 1.4nm-class node is scheduled for risk production in the same year, with broader output in 2028, and Samsung has targeted a similar window. Both companies are expected to rely on EUV for the majority of patterning steps, but neither will be blind to the cost pressures. A secondary patterning pathway that reduces EUV load would be welcome, provided it clears the engineering hurdles.

Canon has pitched nanoimprint not as a replacement for EUV but as a complementary tool for specific layers and structures. Advanced patterning at sub-2nm often relies on techniques such as self-aligned double and quadruple patterning to extend resolution beyond single-exposure limits, and some researchers have explored how alternative lithography approaches, such as NIL, fit into these schemes. Nobody is claiming that a 1.4nm chip can be manufactured entirely through imprinting; rather, the proposal is that certain layers, currently exposed with EUV, could be transferred to a lower-cost, lower-power workflow.

That could have important ramifications for cost control, as every EUV step adds both energy consumption and process time. If a handful of those can be replaced by nanoimprint without sacrificing uniformity or yield, fabs gain extra flexibility. And when we’re talking about a 1.4nm production line churning tens of thousands of wafers per month, even marginal reductions in EUV dependency could translate to huge savings.

If DNP’s template can achieve the required precision for 1.4nm logic, the largest remaining obstacle is manufacturing scale. Imprint relies on a mechanical master pattern that must remain dimensionally perfect throughout its life. Even slight abrasion or contamination forces a replacement, and templates are both expensive and slow to produce. Running nanoimprint at volume will therefore necessitate a reliable supply of near-perfect masters and a way to verify their integrity rapidly enough to avoid passing defects downstream.

Advanced logic layers also require alignment precision on the order of a few nanometers across a 300 mm wafer. Achieving that through an act of mechanical contact is orders of magnitude more demanding than aligning an optical projection. Canon’s system tackles this with a step-and-repeat approach and local deformation control, but real-world results have yet to be demonstrated on the layers where tolerances are tightest.

Throughput is another potential constraint. While Canon’s multi-cell architecture improves parallelism, measured performance still trails EUV. Findings from Semi-analysis indicate that one cell of a Canon NIL tool processes approximately 25 wafers per hour, and a cluster of four reaches 100 wafers per hour. By contrast, ASML’s EUV scanners are typically in the 200-330 wafers per hour range in production. These shortfalls can compound rapidly when fabs operate 24 hours a day at scale, so any technology that slows the cadence of critical layers risks invalidating the cost savings gained elsewhere.

A narrow but meaningful opportunity

NIL isn’t going to displace EUV across an entire 1.4nm process flow, but it doesn’t need to. Some layers tolerate looser overlay and defect margins than the most critical gate and interconnect levels. Contact layers, certain pitch-split steps, and other non-critical mask levels are the most realistic candidates. Those are the points in the flow where DNP’s templates could be inserted without forcing a redesign of the full stack. Each layer moved off EUV reduces peak power draw inside the fab and lowers dependence on tools that dominate both capital and operating budgets.

That trade-off becomes more pronounced as logic designs grow more complex. Advanced GPUs and AI accelerators rely on unusually long lithography sequences, with repeated standard EUV exposures contributing heavily to cycle time and cost. Removing even a small number of those steps changes how fabs provision EUV capacity and how they allocate capital across new lines.

But reaching that point by 2027 — that could be tricky. DNP’s new template material looks promising, and Canon now has an NIL tool in production, but no chip foundry has committed to high-volume manufacturing. Meanwhile, overlay accuracy, template lifetime, and defect control at scale remain unresolved, and those constraints tend to tighten rather than relax as feature sizes shrink.

Lowering defect densities and increasing yields are the key challenges for chipmakers and chip designers who use hundreds of methods for both tasks. This is because semiconductor fabrication technologies involve thousands of steps, and each can affect defect rates and yields. A recent discovery by researchers at Chinese universities has revealed how resists behave during development and how the post-exposure bake (PEB) step can reduce defect density by up to 99% in some cases, according to a paper published in Nature. However, despite these bold claims, the study has dubious practical use.

Researchers from Peking University and Tsinghua University have managed to visualize how photoresist molecules dissolve, migrate, and entangle within developer liquid during the pattern-forming (development) step. To do so, the team used cryogenic electron tomography (cryo-ET) to reconstruct the true 3D structure of photoresist polymers in their hydrated state at sub-5nm resolution.

The study revealed that most photoresist molecules accumulate in clusters at the gas–liquid interface rather than being evenly distributed in solution, which generates defects. The scientists claim that a slight increase in post-exposure bake (PEB) temperature — from 95°C to 105°C in their case — and maintaining a continuous developer layer prevented these clusters, cutting defect density on 300mm wafers by over 99% using existing resists and DUV equipment.

However, it is worth noting that chipmakers carefully select PEB temperatures for each process technology to achieve the best possible results, which limits the practical implications of the research.

To make it easier to understand what was discovered, here's a sequence of steps within a lithography step.

1. Coating: The wafer is spin-coated with photoresist.
2. Exposure: Ultraviolet (UV) or Extreme Ultraviolet (EUV) light passes through a mask to selectively expose regions of the resist.
3. Post-Exposure Bake (PEB): The exposed resist is gently heated to activate the acid-catalyzed chemical reactions that change solubility.
4. Development: The wafer is rinsed with a developer solution (often TMAH in water for DUV), which dissolves the exposed or unexposed parts of the resist, depending on the resist type, to create a thin liquid film of developer and form the patterns. This step was the focus of the research.
5. Rinse and Dry: The remaining pattern is cleaned and dried for subsequent processing.

The study in the development phase discovered that these photoresist molecules form weak, reversible entanglements that lead to microscopic clusters, which turn out to be the hidden source of pattern defects seen on processed semiconductor wafers.

A hidden process

In immersion and EUV lithography, the developer's liquid film dissolves light-exposed regions of the resist, transferring the pattern to the wafer. While the process is well known across the industry, until now there was no clear understanding of the microscopic behavior of chemically amplified resists (CARs) during pattern development, as existing methods such as scanning electron microscopy (SEM) could only observe dried residues or indirect effects. As a result, process engineers usually rely on trial-and-error tuning of resist chemistry and developer composition, since nobody has observed the real-time behavior of photoresists during development.

Instead of using SEM or atomic-force microscopy, the researchers used a cryo-electron tomography tool — usually used in structural biology to study cells, protein complexes, or viruses in frozen states — to visualize the behavior of photoresists inside a developer liquid at nanometer resolution. To do so, they had to go to great lengths in sample preparation, vitrification speed (the cooling rate at which a liquid changes state without crystallizing), and electron-beam control.

For their research, the scientists used a poly(methacrylate)-based CAR, which is widely used in 193nm immersion and 13.5nm EUV lithography.

An observation

Cryo-ET imaging revealed that the CAR polymers — frozen in their natural liquid state — were preserved as flexible, thread-like chains with random coiled shapes. Analysis of the polymer density revealed that the concentration decreased sharply with depth: in 25nm– 100 nm-thick films, about 80% of the polymer mass accumulated near the gas–liquid interface. Hence, contrary to long-standing assumptions, the resist polymers were not evenly dispersed in the developer but were concentrated at the film surface, where they later formed clusters that caused pattern defects. The same pattern was observed with other resists (e.g., designed for 248nm and 365nm exposures) demonstrated the same pattern, but this was never a problem until recently. Control samples with only the developer showed no surface signal, confirming that the effect came from the polymers themselves.

Further 3D reconstructions (combination of hundreds of low-dose electron images taken at different tilt angles) showed that inside the film, 12nm-long polymer chains stayed mostly separate, while near the surface they gathered into 30 – 40nm clusters, dimensions well above the sizes of killer defects in modern technologies.

However, these clusters are reversible by heat and are not observed in real life. In fact, killer defects in modern nodes are an order of magnitude smaller, which implies that the clusters of CAR molecules are already mitigated by leading chipmakers in their cutting-edge nodes.

Furthermore, while increasing post-exposure bake (PEB) temperature from 95°C to 105°C disrupts the cohesive interactions and helps to get rid of some defects with certain manufacturing technologies, this is an absolute yield killer for modern fabrication processes that rely on EUV lithography.

Good for DUV, catastrophic for EUV

In Deep Ultraviolet (DUV, 193nm immersion) lithography, a PEB at around 105°C is well within the normal operating range for CARs based on poly(methacrylate). These resists form features roughly 20 nm – 40 nm wide, and their photoacid diffusion lengths (about 10 nm – 20 nm) remain small enough relative to those features to preserve resolution. At 105°C, the additional thermal energy slightly increases polymer mobility and acid diffusion, enabling more complete chemical reaction and smoother dissolution during development, which helps reduce residues and improve pattern uniformity, thus reducing defects and maintaining yields. However, in some cases a a PEB at around 105°C increases line-edge roughness (LER) and line-width roughness (LWR), which leads to degradation of critical dimension uniformity (CDU), which means that it should not be used for critical layers.

However, in EUV (13.5 nm) lithography, the situation is completely different. EUV resists are typically baked at 80°C–95°C to carefully balance acid mobility and reaction completion, maintaining critical-dimension control. EUV CARs must define features as small as 13nm, so even a few nanometers of acid spread can destroy pattern fidelity. Raising the PEB temperature to 105°C would greatly accelerate acid diffusion, broaden the reaction zone, and significantly increase LER/LWR, thereby blurring the fine features defined by the EUV exposure and potentially creating defects. It also increases stochastic variation by over-reacting CAR polymer chains unevenly, which leads to other defects.

The lowdown

While the study offers valuable microscopic insight into how photoresist polymers behave in developer films, its practical impact on semiconductor manufacturing is limited, to put things mildly. Increasing the PEB to 105°C is already within the normal safe range for DUV lithography and therefore not a breakthrough, which is why we do not see 30nm–40nm defects with modern DUV-based nodes. Meanwhile, the same temperature adjustment is unsuitable for EUV processes, as such temperatures can severely degrade resolution and yield.

As a result, the work is scientifically impressive, as it confirms mechanisms that chipmakers have long managed empirically. However, it offers no new solutions applicable to advanced nodes. Then again, if scientists from Intel, Samsung, or TSMC use cryo-ET as well, they might come up with something that leads to an actual breakthrough.

A European think tank suggests retaliatory trade measures against China, and the trigger appears to be Beijing’s threat to restrict exports of rare earth materials. But the suggested counterstrike would hit closer to home by expanding controls on semiconductor tooling, with ASML's DUV machines in the direct line of sight.

According to a recent report by Bloomberg, a European think tank named the European Council on Foreign Relations (EFCR) has begun mapping out “trade options” should diplomacy fail, amid growing frustration over asymmetric pressure tactics from Beijing.

In other words, if China weaponizes rare earths, the EFCR has suggested responding by tightening controls over legacy chip tools still flowing to Chinese fabs. Such measures considered by the EFCR, (which has no formal attachment to the European Commission) would put ASML — the only company in the world that can supply EUV scanners and one of just three capable of building advanced DUV machines — in a difficult position.

25% of revenue weighed up

In Q3 2025, ASML generated €2.4 billion in sales from China, accounting for 42% of system sales revenue and just over 25% of total revenue. More than 90% of those Chinese orders were for DUV systems like the Twinscan NXT:2000i and NXT:1980Di platforms, both of which remain exportable under current Dutch rules.

Unlike ASML’s EUV tools, which are already banned for export to China, these immersion DUV machines are used to fabricate chips on older nodes, and are critical to everything from automotive MCUs to AI accelerators built on older logic.

While the current licensing regime already restricts EUV exports, the think tanks suggest that the same controls could eventually extend to advanced DUV systems. Those tools are not exempt by default — they’ve simply been licensed on a case-by-case basis, and that door could close if diplomatic talks with Beijing break down. Bloomberg's report states that the EFCR is actively exploring those options, mapping out escalation scenarios in parallel with attempts to de-escalate.

If the EFCR's consideration of a ban on DUV exports catches the ear of Dutch authorities who follow through, it could force ASML to walk away from a quarter of its revenue overnight. While ASML has told investors it expects 2026 sales to hold steady even with a decline in China-bound shipments, that guidance assumes a controlled taper, not a blanket ban, as explored by the think tank.

Additionally, ASML continues to fulfil DUV orders that were secured before licensing rules tightened, many of which came from Chinese foundries racing to build up capacity while they still can. If those orders are cancelled or blocked midstream, the company could be left with idle capacity or orphaned inventory that isn’t easily redirected.

It’s tempting to write off DUV as yesterday’s technology. EUV gets all the attention, especially as TSMC and Intel push toward 2nm and beyond. But for China’s domestic foundries — SMIC, HuaHong, Nexchip, and others — DUV is the workhorse platform. Even Huawei’s Kirin 9000S, fabricated at a nominal 7nm, was likely stitched together using multi-patterned DUV.

The problem is that while China has developed domestic alternatives for some fab gear, it still lacks a credible substitute for ASML’s DUV steppers. Canon and Nikon, the other two players in the DUV space, are either capacity-limited or unwilling to challenge Dutch export policy. That would leave Chinese fabs with few options, particularly for immersion lithography.

Deepening tech isolation

If such a ban, as considered by the ECFR, were to pass, it would deepen China’s tech isolation, but also accelerate the buildout of domestic alternatives. SMEE, China’s state-backed lithography firm, has already shipped early-generation tools and is working on immersion platforms.

Meanwhile, SMEE spinoff AMIES recently showcased its latest lithography equipment at an industry event in Shenzhen. Even if performance is years behind, China has shown a willingness to subsidize inefficient infrastructure for the sake of supply chain resilience.

For ASML, cutting off China means forfeiting a quarter of its revenue and potentially triggering retaliatory action against its installed base of thousands of tools currently running across Chinese fabs, which all depend on ASML parts and servicing.

If the think tank's exploration were to pass, a full ban would hurt China in the short term, but hand it a longer-term incentive to accelerate tooling independence. It would squeeze ASML’s financials just as demand from customers in the West begins to normalize. And it would force the Netherlands to pick sides in a trade war it didn’t start.

Update 10/23/2025 8:12am PT: Article amended to reflect that the report came from a think tank.

When Dutch officials revoked ASML’s license to export Twinscan NXT:2050i and NXT:2100i extreme ultraviolet (EUV) lithography systems to China under U.S. pressure, it closed the door to the only machines capable of producing sub-7nm chips at scale.

That single policy decision has defined what some analysts are calling the semiconductor cold war, where SMIC and its peers cannot buy the equipment needed for modern AI accelerators, and every shipment of advanced tools is now scrutinized as if it were a weapons transfer.

What the blockade hasn’t done is stop China’s fabs. Instead, it has forced an awkward reliance on older deep ultraviolet (DUV) machines (via TrendForce) and sparked a parallel race to design local replacements. It’s a strategy of necessity, one that accepts higher costs and lower yields in exchange for continuity and independence.

Sanctions and the scramble for workarounds

EUV machines are some of the most complex industrial systems in existence. Packed with thousands of U.S.-origin components and priced at hundreds of millions of dollars a piece, they are the foundation of every 5nm and 3nm chip shipping, or planning to ship in the future. China has none, and the U.S. has made sure of that.

Successive rounds of sanctions since 2022 have blocked not just EUV exports, but also the most advanced immersion DUV systems, including ASML’s Twinscan NXT:1970i and NXT:1980i. The Netherlands and Japan joined those restrictions, and even service contracts for ASML machines installed in China are being scrutinized. ASML itself has admitted that a China-based employee stole proprietary EUV data, highlighting how valuable the technology has become.

The policy has pushed chip procurement into murky territory. Grey-market Nvidia GPUs continue to flood in through Hong Kong and Singapore despite being explicitly banned, with seizures measured in the hundreds of millions of dollars. But smuggling a workstation card is one thing; sneaking in a 180-ton lithography scanner is another. On that front, Washington’s chokehold on export controls has held up.

The DUV fallback plan

Deep ultraviolet lithography predates EUV by decades. Using 193nm argon-fluoride lasers, immersion DUV systems comfortably support 28nm nodes, with yields and costs increasing dramatically as nodes shrink further. With multi-patterning (exposing the same wafer multiple times with different masks) they can be stretched down to 7nm-class geometries. Intel’s disastrous 10nm rollout proved how costly and yield-sensitive that approach can be, but it remains the only path available to Chinese fabs.

SMIC’s Kirin 9000-class parts, built for Huawei, already demonstrate the limits of this strategy. It’s widely believed that they were fabricated with DUV and heavy use of multiple patterning. The chips work, but at lower volume and efficiency than anything coming out of Taiwan or South Korea.

For now, Chinese fabs are leaning on their existing ASML DUV fleets. Nearly half of ASML’s second-quarter equipment tooling shipments in 2024 went to China, despite the political pressure in Washington. Those sales are a reminder of just how dependent Beijing still is on imported tools. But the window is closing, and the focus is shifting.

Shanghai Micro Electronics Equipment announced in 2023 that it had built a 28nm immersion scanner, the SSA800-10W. It’s crude compared to ASML’s Twinscan line, but it represents the first domestically developed immersion tool, and critically, it was designed without U.S. intellectual property. According to a TrendForce report, SMIC is testing a prototype from Yuliangsheng, a Huawei-linked affiliate of SiCarrier, which also rated for 28nm, but with ambitions to scale toward 7nm with multi-patterning.

A fully domestic DUV scanner, even if mired in yield problems, would insulate Chinese foundries from future Western policy decisions. Let’s not forget that China has previously made it clear that strategic self-sufficiency matters more than perfect parity with TSMC or Samsung.

China is playing the long game

Chinese chipmakers have been gradually shifting some of their production to tools made in China in a bid to support the local wafer fab equipment ecosystem and reduce reliance on tools produced abroad. China already has several well-known manufacturers of chipmaking tools that specialize in one or two types of equipment, which set sales records in 2024. However, there is a little-known Huawei-linked company, Si Carrier Technologies, that has revealed it has almost all types of wafer processing tools in its catalog published at Semicon China and re-published by Zhininren. 

SiCarrier Technologies is a startup widely discussed at this year’s Semicon China, but is little known outside of the People’s Republic. The company is closely linked to Huawei and was founded four years ago in Shenzhen to develop world-class fab tools that would compete against front-end chip production equipment made by market leaders ASML, Applied Materials, KLA, and Lam Research, according to Nikkei. SiCarrier's main investor is Shenzhen Major Investment Group, a government-backed fund supporting other chip ventures connected to Huawei, including PengXinWei Integrated Circuit Manufacturing and SwaySure Technology. 

SiCarrier currently operates R&D centers in Shanghai, Beijing, Xi’an, Wuhan, Chengdu, Hangzhou, and overseas. Its end-to-end development chain covers materials, components, and full systems. To support rapid development, the company aggressively recruits senior engineers from top global companies like ASML and Applied Materials. 

The SiCarrier catalog presented at Semicon China includes a wide range of semiconductor manufacturing equipment, metrology tools, and inspection systems. The catalog does not include any lithography tools (possibly to keep its lithography advancements a secret), but Nikkei reports that the company already has litho tools capable of processing 300-mm wafers on 28nm process technologies and older. Even without lithography machines, the company lists dozens of tools that can perform the vast majority of steps in the front-end semiconductor production flow. The company also has metrology, inspection, and testing tools. 

On the process side, the catalog includes tools used for atomic layer deposition (ALD) for dielectrics and metal gates, chemical vapor deposition (CVD), physical vapor deposition (PVD) blanket film deposition and metal contact deposition, epitaxy, etching, and annealing. The catalog does not explicitly characterize tools and their capabilities in terms of actual fabrication processes, but it does frequently refer to ‘advanced process nodes’ as well as ‘future advanced nodes.’ 

On the metrology and inspection front, the catalog includes tools for the optical inspection of both patterned and unpatterned wafers, atomic force microscopy for morphology inspection at nanoscale resolution, and advanced measurement systems for thin film thickness, element composition, and crystallinity. 

Finally, SiCarrier also has various testing machines, including wafer electrical performance tests, known-good die tests, and functional tests. However, these tools are currently aimed mostly at power semiconductors. 

For now, it is unclear whether all of the tools that SiCarrier lists can be ordered and acquired. It is also unclear whether these machines are compatible with existing production flows that rely on machines from ASML, Applied, KLA, Lam, TEL, and others. 

However, Nikkei claims that SiCarrier has partnered closely with Huawei, which has assembled a large internal team focused on semiconductor manufacturing and equipment, and that they are working to improve process implementation and identify technical challenges across production lines. This could mean that SiCarrier and Huawei intend to build tools for a ‘proprietary’ production flow involving exclusively Chinese tools. If this is the case, it could take years before the first fab with such a flow comes online. Nonetheless, given SiCarrier’s pace so far, it could well impress the industry.

Researchers from the Chinese Academy of Sciences (CAS) have created a "breakthrough" solid-state deep ultraviolet (DUV) laser emitting coherent 193-nm light used for semiconductor photolithography in a lab, reports the International Society for Optics and Photonics (SPIE).

If the light source technology can be scaled, this device could be used to build lithography tools that make chips using advanced process technologies. However, perspectives on scaling solid-state lasers are unknown.

Before we discuss how the CAS method works, let's recap the de facto industry-standard method of creating light with a 193-nm wavelength used by ASML, Canon, and Nikon for their DUV litho machines. Also, keep in mind that the CAS system is in its early stages of development, and we are talking about a test vehicle at best.

Traditional approach

DUV lithography machines by ASML, Canon, and Nikon generate 193-nm light using an argon fluoride (ArF) excimer laser. The laser chamber contains a gas mixture of argon and fluorine and a buffer gas like neon. When high-voltage electrical pulses are applied, the argon and fluorine atoms become excited and briefly form an unstable molecule called ArF (or excimer), which quickly returns to its ground state, releasing a photon with a wavelength of 193 nm.

The laser emits these photons as short, high-energy pulses at an output power of up to 100W—120W and at frequencies between 8 kHz and 9 kHz for modern immersion DUV tools. The 193-nm beam is then directed through an optical system that shapes, guides and stabilizes the light. It passes into the lithography scanner, where it shines through a photomask containing the chip pattern.

The CAS approach

The test device developed by the Chinese Academy of Sciences generates 193 nm light using a fully solid-state approach, avoiding gas-based excimer lasers entirely. It begins with a homemade Yb:YAG crystal amplifier, which produces a 1030-nm laser beam. This beam is then split into two optical paths, each undergoing a different optical process to create the components needed for 193-nm generation.

In the first path, the 1030-nm beam is converted into a 258-nm beam through fourth-harmonic generation (FHG, a nonlinear optical process that transforms a laser beam to one-fourth of its original wavelength, in this case, a 258-nm beam). This part delivers an output power of 1.2 W. In the second path, the other half of the 1030-nm beam is used to pump an optical parametric amplifier, resulting in a 1553-nm beam with a power of 700 mW.

These two beams — 258 nm and 1553 nm — are combined in cascaded lithium triborate (LBO) crystals to generate a coherent light with a 193 nm wavelength with an average power of 70 mW operating at a frequency of 6 kHz. CAS says that the test system has a linewidth narrower than 880 MHz, a performance comparable in spectral purity to that of commercial systems used today.

A comparison?

The CAS system produces 193 nm light using a solid-state laser with a 70 mW average power and a 6 kHz frequency, achieving a narrow linewidth below 880 MHz. The test system's output is orders of magnitude lower than ASML's ArF excimer-based production systems, which deliver 100 – 120W at a 9 kHz frequency.

While the initial CAS system demonstrates capabilities, its low power output makes it unsuitable for commercial semiconductor manufacturing, where high throughput and process stability are essential. It's likely that multiple generations of development would be needed to make this a viable chipmaking light source.

Although advancements that SMIC and Huawei have made in the semiconductor sector in recent years are pretty impressive, the companies are 10 to 15 years behind industry giants like Intel, TSMC, and Samsung, said Christophe Fouquet, chief executive of toolmaker ASML. It's well known that even with the best-in-class DUV tools, Chinese fab SMIC will be unable to match TSMC's process technologies cost-effectively. This is because Chinese companies cannot access leading-edge EUV lithography tools.

"By banning the export of EUV, China will lag 10 to 15 years behind the West," said Christophe Fouquet in an interview with NRC (machine translated). "That really has an effect."

ASML has never shipped its EUV tools to China due to the Wassenaar Arrangement, despite SMIC's reported order for one EUV machine. The details remain unclear, but ASML did not deliver the machine to the Chinese foundry due to US sanctions. However, ASML kept shipping advanced DUV lithography tools, such as the Twinscan NXT:2000i, which are capable of producing chips on 5nm and 7nm-class process technologies.

As a result, SMIC has been producing chips for Huawei using its 1st-generation and 2nd-generation 7nm-class process technology for years now. This has certainly helped the Chinese high-tech giants weather U.S. government sanctions.

Having understood that EUV tools are not coming to China, Huawei and its partners have explored extreme ultraviolet lithography themselves with the aim of building their own lithography chipmaking tools and ecosystem, which will take 10 – 15 years at best. For reference, it has taken over 20 years for ASML and its partners from foundational work to complete commercial machines to build the EUV ecosystem. Keeping in mind that many of the technologies developed in the early/mid-1990s are openly known, Chinese companies will not have to develop everything from scratch. However, by the time the Chinese semiconductor industry develops Low-NA EUV tools, the Western chip industry will have High-NA EUV lithography and even Hyper-NA EUV equipment.

However, the main concern is not that Chinese companies may develop their own EUV lithography tools some 15 years down the road, but that they might copy ASML's mainstream DUV machines (such as Twinscan NXT:2000i) over the next several years.

The American government is pressuring ASML to halt the maintenance and repair of its advanced DUV systems in China, which will make it consistent with existing sanctions against China's semiconductor sector. However, the Dutch government has not agreed to this demand so far. ASML aims to retain control over its machines in China to prevent the risk of sensitive information leaking, which could happen if Chinese companies take over maintenance to keep their chip factories operational.

For now, Chinese companies are among the main customers of ASML, and the company earns billions selling DUV litho tools to SMIC, Hua Hong, and YMTC. What happens if (or rather when) Chinese makers of lithography equipment build their own DUV lithography systems (or just copy those developed by ASML) is unknown. On the one hand, they could reduce purchases from ASML, but on the other hand, they could start selling these tools outside of China, essentially competing with ASML. While it is unlikely that they will build a Twinscan NXT:2000i-like machine any time soon, replicating something less advanced could be much easier.

The Netherlands recently saw a huge jump in wafer fab equipment sales to China -- including a 1,050% increase in value this November, reports the South China Morning Post (via Yahoo! Finance). While the information can be considered 'semi-official,' it possibly points to China's continued effort to access advanced wafer fab tools to build its semiconductor sector.

In November, China brought a total of 42 lithography systems worth $816.8 million. Sixteen lithography systems came from the Netherlands; their value totaled $762.7 million, a tenfold increase from the previous year. In addition, China imported 21 systems from the Netherlands in October. Japanese companies Canon and Nikon also supplied China with lithography tools.

The main supplier of these lithography systems to China is ASML, and most of those wafer fab tools do not need an export license from the U.S. or Dutch government. This import surge is happening even as the U.S. tries to limit China's access to cutting-edge chip-making tech. Despite these efforts, it seems Chinese firms are still getting their hands on advanced equipment.

Despite its own push for wafer fab equipment and development, China's business with ASML, Canon, and Nikon shows how much China relies on foreign tech for its semiconductor production. As of 2021, less than 5% of the lithography systems in Chinese factories were made locally, the report from SCMP claims.

The U.S. recently changed its export rules, particularly the "de minimis" rule related to certain deep-ultraviolet lithography tools that contain U.S. technology. This change has made it tougher for ASML to ship its Twinscan NXT:1980Di systems to some of China's advanced chipmakers. But, according to ASML's CEO, Peter Wennink, most Chinese customers are not affected by these changes because they mostly focus on mature process technologies, such as 28nm and older.

Analysts have different takes on why China's imports spiked. Some think it might be because of quick shipments made before the latest U.S. export rules came into effect. Meanwhile, SMIC, the biggest chipmaker in China, is upping its 2023 CapEx budget to $7.5 billion despite a drop in revenue. 

Researchers from St. Petersburg Polytechnic University (SPbPU) have developed a domestic lithographic complex for mask-less chip production using etching, an important towards Russia's microelectronics self-sufficiency, reports CNews, citing state-owned RIA Novosti. One of the tools costs five million rubles ($49.5 thousand), the price of a modern car, and the cost of another is unknown.

The complex consists of two tools. The first device is designed for "maskless nanolithography," it projects images onto substrates without a mask. The second tool, which builds on the substrate patterns made by the first, is responsible for forming nanostructures using etching. Furthermore, this installation can craft silicon membranes for applications such as ship overpressure sensors. Notably, these membranes are touted to be more reliable and sensitive than those produced by other methods.

Russia's advancements in microelectronics come amidst its broader struggle to keep pace with global chip-making standards. Currently, the nation is limited to a 65nm process technology in chip production. Global standards, meanwhile, have already scaled down to a 3nm process. Another noteworthy endeavor is by the Nizhny Novgorod Institute of Applied Physics (IAP RAS), which aims to pioneer a lithograph capable of 7 nm chip production, albeit not until 2028. Adding to the momentum, the Ministry of Industry and Trade has invested 1.1 billion rubles in developing lithographic materials specific to microelectronics.

Beyond making chips or silicon membranes, these two installations can significantly benefit other industries. For instance, they can increase the lifespan of radar equipment by over 20 times. In the realm of green energy, these tools can miniaturize solar panels, making them lighter and enhancing their efficiency. 

The developers have grand visions for their invention. They are considering incorporating artificial intelligence into both machines to amplify their capabilities. However, it remains unclear if Russian chip manufacturers have expressed interest in these devices, and there's no timeline for when the tools will be deployed in real-world production.