Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

ASML has told Tom's Hardware that claims one of its extreme ultraviolet (EUV) lithography systems has ended up in China despite export restrictions is both inaccurate and damaging to its reputation. It follows a report that Commerce Secretary Howard Lutnick questions senior leadership, concerned that one of the machines had ended up in China in breach of export restrictions.

The company is refuting a recent report claiming the U.S. government believes that one of ASML's extreme ultraviolet (EUV) lithography systems may have somehow reached China despite export restrictions, according to Bloomberg, citing sources familiar with negotiations between the U.S. officials and ASML executives. ASML denies any wrongdoing and claims that it knows the location of every EUV tool it has ever built.

The issue reportedly emerged during meetings between U.S. Commerce Secretary Howard Lutnick and ASML executives. According to people familiar with the discussions cited by Bloomberg, Lutnick questioned whether an EUV system may have found its way into China. Such a development would represent a major breach of export controls because, under the Wassenaar Arrangement, ASML can not ship EUV lithography equipment to Chinese customers. In fact, the only EUV tool that China-based Semiconductor Manufacturing International Corp. (SMIC) has bought remains in the Netherlands. As a result, ASML calls the accusations 'unfounded' and 'damaging.'

"In recent years, ASML has refuted several unfounded rumors regarding non-compliance with export controls concerning China which were inaccurate and damaging to our reputation," a spokesperson for ASML told Tom's Hardware.

The U.S. government has not publicly produced evidence that a complete EUV scanner is operating in China. Yet, several senior administration officials told Bloomberg that they possess information indicating that ASML exported equipment associated with EUV systems, including specialized systems used to 'transport EUV machines.' Those officials declined to disclose any evidence, citing sensitivity concerns.

"ASML has never shipped an EUV machine to China, nor have we shipped to China any component, module or equipment specially designed to be used in an EUV machine," the spokesperson told us.

An ASML EUV scanner is made of 100,000 components and weighs 180 tons. It is transported only by air on multiple planes, and it would be impossible to intercept such a shipment without causing an international scandal. Meanwhile, given the complexity of the machine, it is impossible to build one using spare or scrap parts or reverse engineer it using its components, as we reported back in December.

Bloomberg claims that ASML has circulated an internal presentation titled 'No indication of any ASML EUV System in China,' which reportedly states there are 314 EUV systems currently operating worldwide and another 26 that have been retired. According to the document, none are located in China. The presentation further notes that EUV scanners continuously communicate with ASML, so the company can detect interruptions, abnormal activity, or connectivity issues. In addition, customers cannot simply dismantle, transport, and reinstall an EUV scanner without direct assistance from ASML due to specialized logistics and handling requirements.

ASML certainly understands concerns of the West regarding China, so claims it has never shipped an EUV tool to the People's Republic initially due to the Wassenaar Arrangement and then due to more recently imposed export controls.

"ASML regularly engages in transparent and open dialogue with government leaders globally," ASML told us. "We recognize the national security considerations behind export control regulations in the U.S. and the Netherlands. As a company, we are fully committed to abiding by all laws and regulations applicable to our business activities, including all applicable relevant export control regulations, and we have consistently adjusted our business to any development in export controls to comply to any new rules."

As chipmakers push EUV lithography toward its physical limits at 2nm and below, the advanced chemicals used to pattern those circuits have become a critical bottleneck. Photoresists, the light-sensitive materials that transfer circuit designs onto silicon wafers, must be reformulated for each new process node, and the most advanced EUV-grade resists are produced almost exclusively by a handful of Japanese suppliers. With AI chip demand driving record orders at leading foundries, those suppliers are now racing to build production capacity closer to their biggest customers.

JSR, the Japanese chemical maker that holds roughly a quarter of the global photoresist market, established a joint venture with Taiwanese partners Wah Lee Industrial and LCY Chemical in early April to build its first photoresist production facility in Taiwan. The plant, located in Yunlin County, is expected to come online as early as 2028 and will co-develop advanced photoresists with TSMC, ending the company's status as the last of Japan's three leading EUV-class resist suppliers without a Taiwanese manufacturing base.

The expansion comes as JSR simultaneously ramps the world's first production-scale facility for metal oxide resist (MOR) in South Korea, a next-gen EUV chemistry that the company acquired through its $514 million purchase of Inpria in 2021. Together, the two plants represent a coordinated push to lock JSR into the development pipelines of the world's most important chipmakers before Chinese competitors can close the gap at the leading edge.

JSR under new ownership

JSR is no longer a publicly traded company. Japan Investment Corporation (JIC), a government-backed fund, completed a tender offer at ¥4,350 per share in April 2024, securing more than 84% of outstanding stock. JSR delisted from the Tokyo Stock Exchange on June 25, 2024, and the merger was finalized in December. The deal valued the company at roughly ¥909 billion ($6.4 billion).

Under JIC's ownership, JSR has moved aggressively to concentrate on semiconductor materials. The company divested non-core assets to Resonac and Tokuyama in early 2025 and exited its biotech business entirely. In May 2024, it acquired Kyoto-based Yamanaka Hutech, adding chemical vapor deposition (CVD) and atomic layer deposition (ALD) precursor expertise. Then, in September last year, JSR settled long-running patent litigation with Lam Research and converted it into a cross-licensing agreement covering dry-resist EUV patterning and etch precursors.

JSR's decision was driven by a direct request from TSMC, according to CommonWealth Magazine. New CEO Tetsuro Hori, who took over in April 2025, told the publication that "speed is critical," noting that local production would eliminate the need to ship wafers out of Taiwan during co-development cycles.

JSR had been shipping resist samples from facilities in Japan, the U.S., and Belgium, with each development cycle taking weeks for round-trip shipping alone. A week after the joint venture was announced, JSR opened a separate advanced planarization research center in Hukou, Hsinchu County, in partnership with TSMC and Applied Materials.

Location, location, location

A Photoresist is the light-sensitive material that transfers circuit patterns onto silicon wafers during lithography. At advanced process nodes, resist formulations need to be precisely tuned to work with specific exposure wavelengths, dose profiles, etch chemistries, and integration workflows. Each new node requires hundreds of iterative test cycles between the resist supplier and the foundry.

JSR's two largest Japanese rivals have had a co-development presence in Taiwan for years. Tokyo Ohka Kogyo (TOK) and Shin-Etsu Chemical, the first- and third-largest photoresist suppliers respectively, both operate production facilities on the island where their engineers work directly alongside TSMC's process teams.

Shin-Etsu runs a line in Douliu, also in Yunlin County, and is building a new ¥83 billion facility in Isesaki, Gunma Prefecture, while TOK has been present in Taiwan for more than a decade and announced a ¥20 billion photoresist plant in South Korea in late 2025 to serve Samsung. This means that every major Japanese materials supplier is now either manufacturing in Taiwan or actively building out capacity to do so.

JSR's Taiwan plant will produce photoresist for TSMC, but in the longer term, the company will focus on metal oxide resist (MOR). MOR uses tin-oxide-based chemistry rather than the organic polymers and photoacid generators found in CARs, which rely on chemical amplification to compensate for the few high-energy photons produced by the light source at 13.5nm EUV wavelengths. However, that amplification introduces acid-diffusion blur and worsening line-edge roughness as feature sizes shrink.

Tin-oxide MOR absorbs EUV photons roughly five times more efficiently than organic CARs, according to Inpria, and uses molecular building blocks roughly five times smaller, while etch resistance is 10 to 100 times higher. At SPIE Advanced Lithography 2025, Inpria reported MOR patterning down to pitch-18 with full etch transfer, while Imec demonstrated additional dose-response improvements by adjusting oxygen concentration during the post-exposure bake step.

JSR's MOR production plant in Cheongju, South Korea, built through its JSR Micro Korea subsidiary, is expected to begin mass production this year, supplying Samsung Electronics and SK hynix with tin-based MOR for EUV layers in next-gen DRAM. Both memory makers are reportedly planning to adopt MOR on selected layers for their 1c (sixth-gen 10nm-class) DRAM nodes.

JSR plans to market MOR to TSMC as well, according to Nikkei. TSMC has stated repeatedly that it won’t adopt high-NA EUV through its A14 (1.4nm-class) node in 2028, instead extending low-NA with multi-patterning, which pushes the largest MOR opportunity at TSMC's logic fabs out toward 1.0nm-class processes and beyond.

Chinese competition at the lower end

Japanese companies collectively control roughly 80% of the global photoresist market, and dominance at the EUV level is even more concentrated: JSR, TOK, and Shin-Etsu account for nearly 85% of EUV resist production volume, according to industry estimates. Chinese firms have made progress at the KrF and i-line level, but penetration at ArF and above remains negligible. Domestic Chinese supply of ArF and EUV resist sits below 5%.

The names to watch are Hubei Dinglong, Xuzhou B&C Chemical (backed by Huawei's Hubble Investment arm), Jiangsu Nata Optoelectronic, and Shanghai Sinyang. Xuzhou B&C claimed it achieved a 14nm wet-process photoresist breakthrough in 2024 and targets advanced mass production within five years, according to TrendForce, but analysts view that timeline as optimistic given the multi-year customer-qualification cycles that resist adoption requires.

"Chinese players are a threat, but it'll still be some time before they can catch up with us and take market share," Toru Kimura, a senior officer at JSR who heads the company's electronic materials business, told Nikkei. Specific capacity figures, the output mix between MOR and conventional resists, and the exact scope of the Yunlin plant haven’t been disclosed.

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

The Dutch company holds a 100% monopoly on EUV lithography and approximately 83% of the global lithography market overall, and its roadmap now spans four distinct generations of technology: DUV immersion systems that still handle the majority of layers on every advanced chip, low-NA EUV scanners that enabled the 5nm and 3nm era, High-NA EUV tools now entering early production at Intel and Samsung, and a Hyper-NA concept that remains in feasibility studies for the 2030s.

Each step up this ladder delivers finer resolution at exponentially higher cost and complexity, and just how aggressively the industry's largest chipmakers adopt each generation will determine the pace of transistor scaling for the next decade and beyond.

DUV immersion and low-NA EUV

ASML's DUV immersion systems are still the backbone of semiconductor manufacturing when it comes to volume production. The company sold 131 immersion DUV tools in 2025. Even a chip built on TSMC's 3nm node uses EUV on only a handful of critical layers; the majority of patterning steps still run on DUV immersion tools like the TWINSCAN NXT:2100i, which delivers 295 wafers per hour at 1.35 NA with 1.3nm overlay.

DUV single-exposure is also the standard in mature nodes powering automotive and industrial chips. While DUV multi-patterning can push down to 7nm and even 5nm, it comes at an enormous cost of up to 34 patterning steps at 7nm versus nine with EUV.

Chinese customers purchased an estimated 70% of ASML's DUV immersion systems in 2024, stockpiling ahead of tightening Dutch export restrictions that now cover the NXT:1970i and newer models. SMIC demonstrated 7nm production using DUV multi-patterning for Huawei's Kirin 9000S, according to TechInsights. But the process requires significantly longer cycle times than EUV-based production, and questions exist around whether yields are sufficient for volume commercialization.

On the EUV side, ASML's low-NA systems operate at 0.33 numerical aperture with 13.5nm wavelength light, achieving 13nm single-exposure resolution. The TWINSCAN NXE:3600D, introduced around 2021, delivers 160 wafers per hour with 1.1nm matched-machine overlay. Its successor, the NXE:3800E, began shipping in March 2024 and pushes throughput to 195 wafers per hour, upgradable to 230 — following ASML's recently updated roadmap — while tightening overlay below 1.1nm. Each NXE:3800E costs roughly $180 million. It shares its bottom module, including wafer handler and faster stage mechanics, with the High-NA EXE platform, a decision that reduces ASML's manufacturing complexity and provides fabs with a degree of serviceability continuity when they upgrade.

ASML's roadmap extends low-NA further, with the NXE:3800F expected around 2027. It targets a ≤0.9nm overlay and over 260 wafers per hour. A subsequent NXE:4200G targets a ≤0.8nm overlay and over 300 wafers per hour, with an NXE:4200H beyond that at a ≤0.7nm and 330 wafers per hour. Further out, ASML has disclosed a High Productivity platform, the NXE:4600, targeting 400 wafers per hour or more.

TSMC has confirmed that it will not use high-NA EUV for its A16 (1.6nm) or A14 (1.4nm) nodes, instead relying on low-NA with multi-patterning. Kevin Zhang, TSMC's Deputy Co-COO and Senior Vice President of Business Development, said at the company's European Technology Symposium last May that TSMC would adopt high-NA "whenever we see high-NA will provide meaningful, measurable benefit," adding that the technology team continues to extend the life of current EUV.

Computational lithography is one reason low-NA can stretch further, with ASML's Brion subsidiary developing inverse lithography technology and curvilinear mask optimization software that computationally corrects for optical distortion beyond specification, effectively squeezing better resolution from existing 0.33 NA optics without hardware changes.

TSMC has been a major user of these techniques, and their continued advancement narrows the gap between low-NA double patterning and High-NA single exposure. ASML's installed base management business, which services and upgrades the global fleet of lithography tools, reached €8.2 billion in revenue in 2025, up 26% year-over-year. That recurring revenue stream grows with every tool shipped and is increasingly important as fabs push older systems to higher utilization rates.

High-NA EUV

The jump to 0.55 numerical aperture with high-NA is the largest optical leap in EUV's history, shrinking minimum resolution from 13nm, which itself was down from 30nm with DUV, to 8nm and enabling approximately 2.9 times higher transistor density in a single exposure. ASML's first High-NA tool, the EXE:5000, shipped to Intel in December 2023 as a development platform.

Each unit of the production-capable EXE:5200B weighs in at 150,000 kilograms, requires 250 shipping crates, and takes six months and 250 engineers to assemble on-site, says Intel. Priced at approximately $380 million, the EXE:5200B delivers 175 wafers per hour at 50 mJ/cm² dose with 0.7nm overlay. ASML told Reuters in early 2024 that it had taken 10 to 20 orders by that point and planned to deliver 20 annually by 2028.

Intel announced that it had completed acceptance testing of its EXE:5200B in December 2025 at its Hillsboro D1X fab and that the tool will be used for the development of Intel's 14A fabrication process. 14A is expected to be the first production node to rely on High-NA for its most critical layers, with risk production targeted for 2027.

In September, SK hynix became the first memory manufacturer to install a commercial High-NA system at its M16 fab in Icheon, South Korea. Samsung, meanwhile, received its first EXE:5200B in October, with a second unit due in the first half of 2026 for its 1.4nm foundry node. Imec, the Belgian research institute, secured an EXE:5200 last month with a Q4 2026 qualification target for sub-2nm process development.

ASML's near-term High-NA roadmap includes the EXE:5200C, targeting 190 wafers per hour without stitching and 160 with stitching at sub-0.8nm overlay, followed by the EXE:5200D at 195/175 wafers per hour and eventually the EXE:5400E at 210/180 wafers per hour with sub-0.7nm overlay. A High Productivity variant, the EXE:5600, targets 250 wafers per hour or more.

Analysts from SemiAnalysis believe TSMC won’t adopt High-NA EUV until its 1nm-class A10 node, which would place volume deployment around 2029 to 2030, because existing low-NA EUV systems can match High-NA's 8nm resolution using double patterning, and SemiAnalysis estimates that approach may still cost less than High-NA single patterning. High-NA tools also require substantial changes to existing fab buildings to accommodate their size.

Hyper-NA and pellicles

ASML placed Hyper-NA on its official roadmap for the first time at imec's ITF World in May 2024, with former CTO Martin van den Brink commenting a few months prior that an NA above 0.7 "is certainly an opportunity that will become more visible from around 2030." The primary target is 0.75 NA, with 0.85 NA also under investigation. Zeiss has begun preliminary lens designs. Estimated tool cost: roughly $720 million per system, according to TrendForce.

At 0.75 NA, however, polarization effects begin destroying imaging contrast because one polarization orientation effectively cancels light at extreme incidence angles, thereby necessitating the use of polarizers that block photons and reduce efficiency. Depth of focus shrinks further, and resists must be made even thinner than the sub-30nm films used for high-NA, worsening etch selectivity and stochastic defects from photon shot noise. On top of all that, an electron blur of approximately 2nm may impose a solid resolution barrier regardless of optical improvements.

Pellicle development is another bottleneck. These ultra-thin membranes protect masks from particle contamination during exposure but must transmit EUV light efficiently at rising source power levels. ASML's current composite silicon-based pellicle achieves over 90% transmission at 380 W source power, but for future systems running at 600 W to 1,000 W, carbon nanotube pellicles are the next-gen technology, achieving up to 97% transmission while withstanding temperatures above 1,500 C. Mitsui Chemicals is building dedicated CNT pellicle production capacity targeting 5,000 sheets per year and commercialization aimed for this year.

Export controls and Canon NIL

EUV systems have never been sold to China, blocked since 2019 under U.S. pressure despite existing orders from Chinese customers. In addition, Dutch export controls, effective since late 2023, required licenses for advanced DUV immersion systems (NXT:2000i and newer), and by September 2024, the restrictions expanded to include the NXT:1970i and NXT:1980i.

Servicing restrictions also prohibit ASML from improving overlay accuracy or increasing throughput by more than 1% on installed Chinese systems. China represented 49% of ASML's revenue at the peak of stockpiling in Q2 2024, falling to roughly 36% for full-year 2024. ASML's management guided China to approximately 20% of revenue in 2025 and 2026, which has seen South Korea and Taiwan emerge as the primary growth markets, with SK hynix alone placing a record $7.9 billion EUV order last month covering roughly 30 systems over two years.

Canon's FPA-1200NZ2C nanoimprint lithography system, announced in October 2023, represents the only credible alternative patterning approach. At roughly $15 to $20 million per system with 90% lower power consumption than EUV, it uses direct mechanical pattern transfer rather than optical exposure. Canon delivered the first commercial unit to the Texas Institute for Electronics in September 2024, and its current specs show some significant limitations: 80 to 100 wafers per hour (versus 195+ for low-NA EUV), 14nm minimum linewidth, and 2.4 to 3.2nm overlay (versus sub-1.1nm for EUV).

Japan's Dai Nippon Printing (DNP) is targeting 2027 mass production of 1.4nm-class nanoimprint templates, but no major foundry has committed to NIL for high-volume logic manufacturing. The technology's likely niche remains repetitive memory patterns, particularly high-layer-count 3D NAND, where its cost advantage could outweigh the throughput and overlay penalties. Defect density from direct physical contact between template and resist remains the fundamental barrier to logic adoption, where a single misplaced particle can kill an entire die.

ASML revenues continue climbing

ASML's 2025 results reflect the sheer scale of its roadmap, with €32.7 billion in revenue (up 16% year-over-year), 52.8% gross margin, and €9.6 billion net income. EUV became the leading source of system revenue at 48%, or €11.6 billion, up 39% from 2024. Net bookings surged 48% to €28 billion, with Q4 2025 alone delivering a record €13.2 billion in orders. The company recognized revenue on two High-NA systems during the year.

ASML's Q1 2026 results, published April 15, show €8.8 billion in total net sales at 53% gross margin, with €2.8 billion net income. The company shipped 16 EUV and 17 immersion DUV systems in the quarter, with South Korea accounting for 45% of system sales by region and China at 19%. ASML raised its full-year 2026 revenue guidance to €36 to €40 billion, with 51% to 53% gross margins

Each NA increase delivers diminishing resolution gains at exponentially rising cost and complexity. The most likely trajectory is not a clean generational handoff but an extended coexistence: low-NA handling the bulk of EUV layers well into the 2030s, High-NA reserved for the most critical pitches at sub-2nm nodes, and Hyper-NA arriving as a targeted tool for the most extreme features, subject to workarounds for the bottlenecks we’ve discussed above.

SK hynix disclosed in a regulatory filing on Tuesday that it will purchase 11.9 trillion won ($7.9 billion) worth of EUV lithography equipment from ASML by the end of 2027, as reported by Bloomberg. The deal is the largest single EUV order ever publicly disclosed by an ASML customer, and it runs through December 2027. SK hynix said the tools are intended for mass production of next-gen products as the company races to expand capacity for AI-driven memory demand.

Bernstein analyst David Dao estimates that the order covers approximately 30 new EUV machines over two years, slightly above his prior forecast of 26. The scanners will be deployed across two facilities: SK hynix's M15X plant in Cheongju, which is focused on producing HBM chips, and the new Yongin Semiconductor Cluster, which will handle advanced DRAM. Ryu Young-ho, a senior analyst at NH Investment & Securities, told Reuters that the equipment is expected to serve both HBM and advanced DRAM production.

SK hynix accelerated the Yongin timeline earlier this year, moving the first cleanroom opening from May to February 2027. The company committed a total of 31 trillion won ($21.5 billion) to the Yongin Phase 1 fab, which will eventually house two building shells and six cleanrooms. M15X, meanwhile, began deploying wafers in February after its first clean room opened in October of last year.

ING analyst Marc Hesselink noted in a client note that the order contains a "pull-in element" designed to lock down ASML equipment supply ahead of competitors. SK hynix is likely to increase spending on the less advanced DUV lithography machines separately, where lead times are shorter at three to six months, Hesselink added.

ASML, which announced plans to cut some 1,700 managerial roles back in January, reported a €38.8 billion order backlog at the end of 2025. Samsung and TSMC are also major buyers of EUV equipment, and all three major memory makers are expanding capacity as AI infrastructure buildout continues to strain global DRAM and HBM supply.

SK hynix currently holds more than 60% of the global HBM market and is a primary supplier to Nvidia, but Samsung is ramping its own EUV-based HBM production aggressively. SK hynix announced a separate $13 billion advanced packaging facility in Cheongju earlier this year to handle the downstream assembly of HBM chips produced at M15X.

IBM and Lam Research have announced a five-year research collaboration to develop the materials and fabrication processes needed to scale logic chips beyond 1nm using high-NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's NY Creates Albany NanoTech Complex in New York, with Lam's Aether dry resist technology at the center of the effort alongside its Kiyo and Akara etch platforms and Striker and ALTUS Halo deposition systems.

The two companies have collaborated for over a decade on 7nm process development, nanosheet transistor architecture, and early EUV process integration. Notably, IBM unveiled what it described as the world's first 2nm node chip in 2021, marking a significant milestone in the ongoing partnership.

Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist.

Aether and high-NA EUV

Standard EUV lithography utilizes chemically amplified resists, which are spin-coated onto wafers and developed using wet chemistry. That approach, however, has a fundamental problem at the geometries high-NA EUV scanners are designed to print: stochastic noise. This is a statistical variation in photon absorption per unit area, which drives defect rates up as features shrink.

Aether’s process, however, sidesteps wet chemistry entirely by depositing the resist via vapor-phase precursors and developing it using plasma-based dry processes. According to Lam, its metal-organic compounds absorb three to five times more EUV light than conventional carbon-based resist materials, reducing the exposure dose required per wafer pass and keeping single-print patterning viable at nodes where wet-process alternatives would require more expensive multi-patterning.

Fewer process steps between exposure and etch also reduce the number of points at which pattern fidelity can degrade, which is a compounding advantage as geometries continue to tighten. The renewed collaboration between IBM and Lam is specifically focused on proving that Aether can get high-NA EUV patterns reliably transferred into real device layers at production yield. Ultimately, that’s what needs to be done before sub-1nm processes can credibly move toward a production fab.

Nanosheet transistors, which stack multiple thin sheets of silicon to increase drive current without widening the transistor footprint, are one of the primary device architectures the teams will be validating. IBM’s press release also confirms work on nanostack devices and backside power delivery, which routes power connections through the back of the wafer rather than the front, freeing up front-side metal layers for signal routing and reducing the resistance losses that compound at high transistor densities.

Three deals in 14 months

The IBM announcement marks the third significant Aether-related move Lam has made since January last year. The company confirmed that month that Aether had been selected by an unnamed leading memory manufacturer as the production tool of record for its most advanced DRAM processes. Then, in September, Lam signed a cross-licensing and collaboration agreement with JSR Corporation and its subsidiary Inpria, integrating JSR's metal oxide resists and patterning materials with Lam's etch, deposition, and dry resist capabilities for high-NA EUV.

Across 14 months, Lam has moved from production adoption in memory to a materials supply chain partnership for high-NA EUV patterning to a five-year logic research commitment with IBM, assembling a dry resist ecosystem ahead of wider high-NA EUV adoption. ASML began shipping its first high-NA EUV systems in 2023, and as those tools move toward broader foundry adoption, the choice of resist process will become one of the more consequential materials chipmakers face. JSR and Inpria's existing metal oxide resist expertise is a direct complement to Aether's vapor deposition approach, giving Lam coverage across both dry resist and metal oxide patterning materials heading into sub-1nm.

Lam isn’t the only equipment company circling high-NA EUV. Applied Materials has its own patterning materials and process integration capabilities, and ASML's dominant position in lithography gives it natural leverage over how the resist ecosystem develops around its tools. Lam's partnerships with IBM and JSR/Inpria are, at least in part, an effort to establish dry resist as the default process integration path before tooling decisions are embedded within foundries.

IBM's research complex

IBM Research's Albany NanoTech Complex is a process development facility, not a production fab, so the output of this collaboration will be validated process flows and materials knowledge that commercial foundries can adopt.

This follows the same model as the companies' prior work on 7nm and nanosheet, with the research that was demonstrated at Albany eventually feeding into production processes at TSMC and others. Sub-1nm process work starting in 2026 is therefore unlikely to reach volume manufacturing before the early 2030s.

The collaboration also presents a huge opportunity for Lam. If it’s able to establish Aether as the validated dry resist solution for high-NA EUV logic, it stands to add a significant new revenue category on top of the etch and deposition tools it already sells to nearly every advanced chipmaker.

A five-year commitment with IBM builds process familiarity and customer confidence well before foundries are making resist process decisions for their sub-1nm nodes. Lam's commercial customers — TSMC, Samsung, Intel, and others — are the ones who will ultimately adopt whatever process knowledge comes out of Albany as a result of this new research effort.

China's most senior semiconductor executives issued a public call this week for a consolidated national effort to build a domestic alternative to Dutch lithography giant ASML, warning that the country's chip equipment industry remains too "small, fragmented, and weak" to overcome U.S. export restrictions on its own.

In remarks co-authored by SMIC co-founder Wang Yangyuan alongside leaders of memory giant YMTC, chip equipment maker Naura, and EDA software developer Empyrean, three specific areas where U.S. export controls have choked China's semiconductor ambitions were identified: electronic design automation software, silicon wafers, and manufacturing equipment — particularly extreme ultraviolet (EUV) lithography, which enables the sub-7nm chip production that China currently cannot replicate.

As reported by the South China Morning Post, the authors urged the industry to "abandon illusions and prepare for struggle," and argued that fragmented public funding was dispersing resources across too many competing efforts without producing results.

China is currently drafting its 15th Five-Year Plan, which is set to be revealed to the National People’s Congress within the next week and covers 2026 to 2030. It’s widely expected that this iteration of the plan will prioritize lithography breakthroughs and EDA tool development as national targets. Big Fund III, a state-backed vehicle with roughly $47.5 billion earmarked for semiconductors, has already redirected fresh capital toward lithography and EDA as substitutes for ASML and Synopsys tools, respectively.

The sheer candor about fragmentation from this collection of executives is difficult to ignore, however, given just how often we see big, bold tech claims coming from Chinese media, but it aligns with an increasingly obvious challenge. China's most advanced domestically produced DUV lithography system, from Yuliangsheng, is technically comparable to ASML's Twinscan NXT:1950i — a machine ASML originally designed for 32nm-class processes back in 2008.

Even if SMIC manages to integrate that tool into a 28nm process by 2027, reaching sub-10nm would require redesigned scanners and several additional years of development. A prototype EUV machine has reportedly been completed in a Shenzhen lab, but EUV's commercial viability requires solving yield challenges that took ASML nearly two decades to overcome after its own prototype.

That’s all before we’ve even considered ASML’s accumulated know-how as, in Yangyuan’s words, “merely the integrator.” The company’s EUV dominance rests on a supply chain of more than 5,000 subcontractors, along with decades of high-volume manufacturing data. No amount of reverse engineering can quickly replicate that. While it’s true that Chinese firms have made real gains in adjacent equipment categories — Naura, for example, is one of the world’s top ten semi equipment vendors by revenue — lithography remains well out of reach.

Imec has demonstrated that the photo-speed of metal-oxide resist (MOR) can be improved significantly when oxygen concentration is raised beyond atmospheric levels during the EUV post-exposure bake (PEB) step. Faster photo-speed means the resist reaches target dimensions at a lower EUV dose, which directly improves EUV scanner throughput and reduces exposure cost. Gas composition in the PEB chamber has not been widely treated as an EUV optimization knob, which makes the announcement significant, but it remains to be seen whether this can be industrialized.

Scientists from Imec discovered that raising oxygen levels from 21% (ambient air) to 50% during the EUV PEB step results in a 15% – 20% increase in photo-speed, which means that the metal-oxide resist can reach its target dimension at a lower EUV dose. Lower dose cuts exposure time, which in turn increases an EUV scanner's throughput per hour and can reduce the cost of EUV step per wafer and ultimately per chip, though do not expect the lowered exposure cost to have a significant impact on the cost of the final product. The improvement was confirmed for both experimental MOR formulations and commercially available MOR materials, according to Imec.

Metal-oxide resists have become leading candidates for advanced process technologies that rely on Low-NA EUV and eventually on High-NA EUV lithography as their high-resolution capability, lower line-edge roughness, and favorable dose-to-size characteristics outperform those of chemically amplified resists (CARs), which are widely used today. The high resolution and reduced LER directly translate into better pattern transfer capability for the smallest features of critical layers set to be printed using High-NA EUV litho systems. Now, Imec’s findings suggest that MOR's performance can be amplified with environmental conditions during the PEB step.

It should be noted that post-exposure bake is one of the most sensitive steps in the entire lithography flow. PEB activates and drives reactions triggered by photons during the exposure, so small variations of temperature, heating ramp rate, bake time, and atmosphere can have drastic effects on critical dimension (CD), line-edge roughness (LER), and stochastic defect levels, which means that one combination of settings can lead to yield improvement, another can be a yield killer. Changing gas composition inside the PEB module is a big deal not only from the pure semiconductor manufacturing flow point of view, but also from such points of view as long-term material stability, tool oxidation, and safety considerations, just to mention a few.

In standard EUV production environments, wafers are exposed in a vacuum and then transferred to a bake module operating under normal cleanroom air containing 21% of oxygen. So, to conduct its experiments, Imec developed a special tool called BEFORCE*, which isolates wafer handling and baking from the surrounding fab environment. The system integrates gas injection and blending capabilities along with built-in photo-speed metrology, which enabled researchers to regulate oxygen contents in the chamber while controlling photoresist performance. To put Imec's discovery into use, foundries will have to ask their fab tool makers to replicate what BEFORCE does during the PEB step.

"This is just a first result from the BEFORCE tool: the controlled gas composition provides an additional knob to study the origins of environmental effects on the lithographic variability of MOR materials," said Ivan Pollentier, Senior Researcher at imec. "Equipment manufacturers can use these insights as a guideline to adapt their tools for improved EUV lithography throughput and stability."

*Bake and EUV system with FTIR and Outgas measurement for Resist evaluation in Controlled Environment.

ASML this week reaffirmed that it is on track to release a Twinscan NXE extreme ultraviolet lithography system that features a 1000W EUV power source and can process up to 330 wafers per hour. The system, projected for sometime in 2030 or beyond, offers 50% more power than the current best EUV tool, the NXE:3800E. Such machines will greatly increase productivity and decrease costs per wafer for chipmakers, but to make them possible, ASML has had to achieve several breakthroughs.

"What was achieved — one kilowatt — is pretty amazing," Michael Purvis, ASML's lead technologist for its EUV source light, told Reuters. "We see a reasonably clear path toward 1,500 watts, and no fundamental reason why we couldn't get to 2,000 watts."

However, to get to a 1000W-class EUV source in the 2030s, ASML must develop a new three-pulse EUV light generation method that it disclosed in late 2024. The new method involves a 1μm pre-pulse that flattens the droplets, followed by a 1μm rarefaction pre-pulse that rarefies them, after which the main 10μm CO2 laser pulse turns them into EUV plasma. Previously, ASML filed a patent application for an EUV light source producing three laser pulses, according to Asianometry. For now, this three-pulse source is not a part of any shipping machine, though expect it to end up in a Twinscan NXE:4000-series scanners due later this decade.

Yet, the actual 1000W EUV radiation source will also be equipped with a new tin droplet that will almost double the number of tin droplets to 100,000 every second. This unit is also currently under development, and it will take years before it is commercialized, according to an ASML spokesperson speaking with Tom's Hardware.

Building a new laser system that comprises of a CO2 laser with a 10μm wavelength for the main pulse and two non-CO2 lasers for with ~1μm wavelength for pre-pulses and a new tin droplet generator that doubles performance as well as a new tin droplet generator with twofold performance sounds easy on paper, both these devices as well as devices that accompany them to make their work possible represent numerous major technological breakthroughs.

Increasing the number of tin droplets automatically means increasing the amount of debris that can end up on a wafer (or rather a pellicle), so they must be promptly removed, which means an all-new debris collector. While producing 1000W of EUV radiation is hard, transferring it onto a wafer is even harder, so ASML had to invent all-new high transmission projection optics, which are meant to scale all the way to over 450 wafers per hour, or toward something like 1500W. Also, increased productivity and higher performance light sources require new wafer and reticle stages, which will also be upgraded in systems featuring a 1000W light source. Last but not least, a 1000W EUV light source also calls for new resists and pellicles, so in addition to ASML itself, the whole industry needs to prep for the arrival of the company's tools featuring its latest innovations.

ASML has long planned to increase the productivity of its EUV lithography scanners to 330 wafers per hour by around 2030, a productivity level tied to a 1000W light source. Therefore, the announcement made this week outlines the technology the company invented to achieve that roadmap goal.

ASML is yet to integrate its 1000W EUV light source into its Low-NA EUV and High-NA EUV roadmaps. The company's next-generation Low-NA Twinscan NXE:4000F litho system with a production capacity of over 250 WpH and a matched machine overlay (MMO) performance of 0.8 nm for 1.x-nm-class nodes is due in 2027, followed by the NXE:4200G with productivity of over 280 WpH in 2029. On the High-NA EUV front, ASML preps the Twinscan EXE:5200C with an over 185 WpH output and a <0.9nm MMO performance next year, followed by the EXE:5400D with productivity of over 195 wafers per hour in 2029.

ASML this week posted its highest yearly result ever as demand for its chipmaking tools set records. The company's revenue for the fiscal year 2025 totaled €32.7 billion ($39 billion USD), up 15% from the previous year. As expected, sales of lithography and other wafer fab equipment to China-based entities decreased in 2025 due to export rules imposed by the U.S. and the Netherlands. When it comes to sales of lithography systems, EUV tools became the leading source of ASML's revenue.

Fewer sales in China

Driven by the Made in China 2025 program and the buildout of the Chinese semiconductor industry amid tightening export curbs by the U.S. in recent years, ASML's sales to the People's Republic set records and culminated with 41% of the company's system unit share in 2024. Last year, sales of ASML's fab tools to China dropped, but 33% of ASML's tools (in terms of units) were sold to the PRC, meaning that Chinese chipmakers kept buying dozens of lithography and other machines for their fabs that use trailing nodes. Some of those older DUV systems are reportedly being upgraded by grey-market means.

China is followed by sales of wafer fab equipment to customers in South Korea (25%) and Taiwan (22%). By contrast, only 12% of ASML-produced tools (by unit count) were shipped to the U.S.

High-end EUV

U.S.-based Intel bought the world's first High-NA EUV Twinscan EXE:5200B lithography tool with 0.55 numerical aperture optics, designed for mass production of chips using next-generation process technologies, such as Intel's 14A (1.4nm-class). Another system was assembled at SK hynix's fab M16 in Icheon, South Korea. Meanwhile, ASML has supplied eight High-NA EUV tools (including six EXE:5000 and two EXE:5200B machines) to additional partners so far.

Speaking of EUV lithography systems, it's important to note that both current-generation Low-NA EUV scanners and next-generation High-NA EUV machines accounted for 48% of ASML's system revenue in 2025 (or €11.6 billion / $13.8 billion USD), up from 38% a year earlier. For the whole year, the company shipped 48 EUV systems and 131 immersion DUV tools, up from 44 EUV scanners and 129 immersion DUV machines in 2024.

Sales of EUV and sophisticated DUV tools are primarily driven by leading-edge logic fabs that build chips for AI infrastructure as well as smartphones and PCs. In fact, logic fabs accounted for 66% of ASML's system sales, whereas memory accounted for 34%. Although both logic and memory makers strive to increase their output and procure new tools, logic producers buy more expensive EUV systems.

"In advanced Logic, our foundry customers have become more positive on the long-term sustainability of demand on a number of fronts," said Fouquet. "AI accelerators are migrating from the 4nm node to the more litho-intensive 3nm node. At the same time, customers continue to ramp the 2nm node in support of next-generation HPC and mobile applications."

However, as DRAM vendors adopt more sophisticated fabrication processes that rely on EUV, they will also intensify procuring EUV scanners, which will significantly increase demand for this type of equipment as memory makers tend to operate very large fleets to fab commodity products in the most cost-efficient way.

"In memory, our customers are reporting very strong demand for both HBM and DDR products with supply remaining very tight through at least 2026 as they ramp both their 1b and 1c nodes in support of the demand," Fouquet added. "In addition, DRAM customers continue to adopt more EUV layers on these nodes. This is expected to continue on their future nodes as they migrate more multi-patterning DUV to single-exposure EUV, resulting in an increase in litho intensity."

Record results

ASML closed 2025 with a record fourth quarter and its strongest year ever. In Q4 2025, the company's revenue totaled €9.7 billion ($11.5 billion USD), its gross margin reached 52.2%, and net income hit €2.8 billion ($3.3 billion USD).

For the full year, the company generated €32.7 billion ($39 billion USD) in net sales, up from €28.3 billion ($33.8 billion USD) in 2024, with a 52.8% gross margin and €9.6 billion ($11.4 billion) in net income.

ASML's net bookings reached €28.0 billion ($33.4 billion USD), whereas their year-end backlog grew to €38.8 billion ($46.3 billion USD), another record for the company.

During the final quarter of 2025, the company supplied 94 new photolithography systems as well as eight used lithography machines. For the whole year, ASML sold 300 new lithography tools and 27 used lithography systems.

For the first quarter of 2026, ASML expects revenue of €8.2 billion – €8.9 billion ($9.7 - $10.6 billion USD), which is up year-over-year but down sequentially. Full-year 2026 revenue is projected to be between €34 billion and €39 billion ($40 billion - 46 billion USD), this reflects growing demand for lithography tools and EUV scanners, primarily due to the wide AI infrastructure buildout. Gross margins at ASML are projected to be between 51% and 53%.

"In the last months, many of our customers have shared a notably more positive assessment of the medium-term market situation, primarily based on more robust expectations of the sustainability of AI-related demand," said Christophe Fouquet, chief executive of ASML. "This is reflected in a marked step-up in their medium-term capacity plans and in our record order intake. Therefore, we expect 2026 to be another growth year for ASML's business, largely driven by a significant increase in EUV sales and growth in our installed base business sales. We continue to invest in people and footprint to support that growth in 2026 and beyond."

Looking ahead

Being the only supplier of EUV and advanced DUV tools on the planet, ASML has every reason to expect sales of these scanners to increase in the coming years. The number of EUV layers increases with the upcoming process technologies, driving its revenue all the way to €44 billion - €60 billion ($52 billion - 71 billion USD) in 2030. Indeed, EUV tools accounted for 65% of ASML's backlog in late 2025, up from 62% a year before. If the demand for their tools continues apace, then ASML will be sitting as one of the most important companies in the ongoing AI boom, right alongside Nvidia.

Samsung Foundry is reportedly on track to hit the 'first light' milestone with ASML's EUV lithography systems at its Taylor Fab 1 in the coming month and commence risk production at the facility in the second half of the year, according to Hankyung. The new fab will not be Samsung's first fab with EUV scanners; however, it seems that the facility will be the company's largest logic fab when fully ramped. It will also be the first fab to adopt pellicles for EUV patterning, something that drastically changes production flows. Implementing pellicles and the sheer scale of the fab signal that it may well be a breakthrough facility for the company.

Samsung's biggest campus yet

When Samsung announced plans to build a new leading-edge semiconductor production facility near Taylor, Texas, the intention was to build a sophisticated fab that would cost $17 billion, with construction starting in 2022, and operations beginning in 2024.

Back then, the company only said that the new site would span more than 5 million square meters (1235 acres), which is larger than the company's domestic South Korea-based campuses near Pyeongtaek and Hwaseong. To put that number into context, Intel's Silicon Desert campus near Chandler, Arizona, which houses Fab 52 and Fab 62, is around 700 acres.

Samsung did not announce which nodes the new site would use initially, aside from mentioning that it would use advanced technologies to make chips for 5G, AI, HPC, and other demanding applications. Meanwhile, the whole project got bigger in April 2024, when Samsung disclosed plans to invest as much as $44 billion in the campus, building two advanced semiconductor fab modules, an advanced packaging facility, and an R&D center. In fact, given the area of the site, it is reasonable to expect Samsung to eventually build additional fab modules.

While the shell of the first fab module was completed in late 2024 – early 2025, the company delayed moving in expensive wafer fab equipment (WFE) because it was uncertain about the node strategy, volume demand, and the lack of a big-ticket customer. Following Tesla's announcements to use Samsung Foundry's Texas capacity to build AI6 chips through 2033 and AI5 chips before that, the questions surrounding a large customer and volume were answered. So, Samsung began to install advanced tools. The company is on track to reach the 'first light' milestone with ASML's EUV tools this March.

With the Tesla contracts signed, Samsung Foundry is now targeting 50,000 wafer starts per month (WSPM) of capacity using the SF2/SF3P process technology at the Taylor fab (according to TrendForce.) Though it is unclear whether this number only describes the first module, or the capacity of the whole $44 billion project that includes two fab modules.

In any case, 50,000 WSPM capacity is much higher compared to what Intel's Fab 52 can offer (40,000 WSPM), as well as higher than what TSMC's typical fab modules can process (around 20,000 WSPM). As a result, Samsung's Taylor fab will likely be the company's largest logic production site that the company has ever operated.

Possible Pellicle pilot

But in addition to being one of Samsung Foundry's largest fabs ever, the new facility will be the company's first fab to use pellicles for EUV lithography (according to Citrini analyst via @jukan05), something it has never done before, which will fundamentally change manufacturing flow at the fab.

Industry sources reportedly indicate that Samsung has ordered dedicated EUV pellicle attachment, detachment, and inspection systems for the Taylor fab. The contract, reportedly worth 25 billion won ($17.5 million), was awarded to FST, a Korean equipment supplier that has been developing pellicle handling solutions for several years.

These are production-grade systems designed to insert pellicles into a high-volume EUV flow. Readiness of these tools should confirm that Samsung intends to qualify pellicles for mass production rather than limited pilot use; however, this has not been officially confirmed by Samsung, and should therefore be taken with a grain of salt. The tools are said to support both conventional metal-silicide (MeSi) EUV pellicles and next-generation carbon nanotube pellicles, which gives Samsung an upgrade path.

For those not familiar, an EUV pellicle is an ultra-thin protective membrane mounted above a photomask during exposure to prevent particles from landing on the mask surface and printing defects onto the wafer. While pellicles have long been standard in deep ultraviolet lithography, EUV pellicles are far more difficult to make and use due to strict requirements for optical transmission, thermal durability, and mechanical stability under EUV radiation. For this reason, Samsung has so far avoided EUV pellicles because they were a net negative for its manufacturing economics and tool stability.

Early EUV pellicles transmitted only around 80% – 88% of 13.5-nm light, causing a 12–20% loss of photons at a time when ASML EUV sources had a performance of around 250W (early NXE:3400B/3400C machines), which would have cut wafer throughput and raised cost per wafer significantly due to longer exposures. At the same time, first-generation pellicles suffered from limited lifetime and thermal instability: they warped or even cracked as well as degraded under sustained EUV radiation, which increased downtime and pellicle failure risk.

Each pellicle can cost from tens of thousands to hundreds of thousands of dollars, so if its replacement cycle were short enough, it would inflate Samsung's costs to something that Samsung's margin structure could absorb. So instead of using pellicles, Samsung bet on a pellicle-free EUV flow based on ultra-clean mask handling, frequent reticle inspection and cleaning, and short mask reuse cycles, which preserved throughput and kept defect risk manageable for smaller dies and few EUV layers. However, the flip side of this decision is reportedly inconsistent yields and variability.

Now, ASML has delivered much more capable Twinscan NXE:3600D and NXE:3800E machines with much more powerful light sources and higher throughput. Also, the industry has introduced metal-silicide (and even carbon-nanotube pellicles, but Samsung will reportedly stick to MeSi pellicles) with better transmittance and durability, so using pellicles makes the most sense right now.

Furthermore, as Tesla's AI5 and other chips use SF2/SF3P and other advanced nodes use many more EUV layers than earlier EUV-based designs, the usage of pellicles becomes compulsory even for Samsung.

Pellicles sharply reduce stochastic mask-borne defects, which are increasingly dominant at the 2nm scale. For large logic dies (such as Tesla's AI5), a single particle on a critical EUV mask layer can destroy an entire chip or even repeat across multiple fields. By shifting the particle plane out of focus, pellicles dramatically lower this risk, thus improving yields and, more importantly, yield stability, something that Tesla clearly demands.

Fundamental shift for Samsung

Ultimately, Samsung will use its Taylor fab to make chips for other clients in addition to Tesla and perhaps introduction of pellicles to the flow will greatly improve the company's positions on the foundry market as inconsistent wafer-to-wafer and lot-to-lot yields and performance variability is what has historically plagued Samsung Foundry's EUV-based nodes and prevented their usage by clients with larger dies.

TSMC's average selling prices (ASPs) for its wafers have increased 15.9% annually from 2019 to 2025. Additionally, gross profit margins per wafer rose rapidly to 3.3x throughout 2025, according to SemiAnalysis. This increased margin reflects TSMC fully leveraging its market-leading position and broad ecosystem to command higher product pricing, which in turn drives downstream effects, including higher end-product pricing. The increases come after a decade during which TSMC earned minimal profit, keeping pricing low as it cornered the market and expanded its market share.

The new era of extreme ultraviolet (EUV) chipmaking began in 2019, with TSMC positioned as the top contract chipmaker. Equipped with robust production capacity and an ecosystem of partners leveraging this new technology, TSMC has seen significant ASP growth. The company is expected to maintain this momentum into 2026 and beyond, driven by several factors.

The rise of TSMC

Since its inception in 1987, through to the 2010s, TSMC was considered a leading foundry, but not a leading chipmaker. At the time, Intel was the undisputed champion of the semiconductor industry, with microelectronics pioneers like IBM also remaining competitive. However, TSMC has been consistently expanding its ecosystem over the years. In 2008, the company established its Open Innovation Platform (OIP) program — uniting TSMC with chip designers, IP providers, and EDA tool developers — essentially setting the stage for its current success.

Things changed suddenly for TSMC in the mid-2010s, when Apple outsourced production of its chips to TSMC, departing from Samsung, which had since become a significant rival to Apple in the smartphone segment. For Apple, going with TSMC guaranteed no IP theft and no plans to compete in the smartphone segment. TSMC also offered a continually evolving roadmap of process technologies and capacity availability, which, among other things, persuaded Apple to back TSMC.

Landing orders from the world's largest manufacturers of consumer electronics (including Huawei, Sony, and Panasonic) gave TSMC the financial capacity required to invest in R&D and new tools to produce chips for customers at high volumes. With Intel's hiccups with its 10nm fabrication process, TSMC entered 2019 with all of the factors needed to become a market leader.

The company was offering services that no other chipmaker could match, bagging big-name customers like Apple, Huawei, and Nvidia in the process. This offered TSMC not only informal recognition of leadership but also the financial resources to expand its turf.

Expensive tools? Even more expensive chips

As a result, after more than a decade of stagnation, TSMC's wafer pricing model fundamentally changed in 2019, as it had to buy, deploy, and depreciate ASML's Twinscan NXE tools, which cost around $235 million each. While these tools from ASML were less expensive in 2019, they steadily increased in price, as the machines became more advanced.

Since TSMC had no real competition, and an increase in the costs of machinery, these factors set the stage for market dominance. Paired with the massive OIP infrastructure, TSMC managed to expand gross profit per wafer by roughly 3.3x throughout 2025, based on data from SemiAnalysis. The report claims that quotes are rising at a far faster pace than production costs, which sets a new economic baseline for leading-edge foundry manufacturing.

EUV revolutionizes fab industry

From 2005 to 2019, TSMC's wafer ASPs remained largely flat because leading-edge foundry capacity was still relatively elastic due to competition, according to SemiAnalysis. Over those 15 years, ASPs increased by only $32 per wafer, with an annual growth rate of approximately 0.1%. Process nodes advanced rapidly using DUV lithography, so capital intensity increased gradually (i.e., in accordance with the growth of customer requirements) rather than exponentially.

During this period, the company largely operated under a cost-pass-through model, using modest pricing adjustments to offset rising manufacturing expenses. This approach limited margin expansion even as process complexity increased. Consequently, market conditions dictated wafer pricing, rather than the capital requirements of foundries.

However, customer economics limited this value-based pricing. Leading-edge demand was dominated by smartphones and consumer SoCs with tightly constrained bill-of-materials (BOM) targets, and no ballooning AI or HPC segment was generating massive gross margins. Yield learning curves were rapid; performance-per-watt gains were predictable; tool and mask costs were rising at a pace that allowed rivals to follow TSMC with capacity and competitive nodes; and there was no structural shortage of production capacity.

As a result, TSMC, just like other foundries, prioritized utilization, scale, and long-term ecosystem dominance over margin expansion. This strategy kept ASP growth near zero until TSMC began to adopt EUV for high-volume manufacturing, forcing their hand and intensifying capital expenditures. These factors coincided with the beginning of the AI and HPC megatrends we've observed in recent years.

In the six years that followed, wafer ASPs at TSMC rose by approximately 133%, equivalent to a 15.2% compound annual growth rate, while the cost of goods sold increased by only 78%. As a result, TSMC's gross profit per wafer increased sharply. Regression analysis made by SemiAnalysis illustrates the shift clearly: before 2019, every $1 increase in cost of goods sold (COGS) translated into $1.43 in ASP, yielding $0.43 in incremental profit; after 2019, the same $1 cost increase generated $2.31 in ASP, or more than $1.30 in incremental profit.

As noted above, the inflection coincided with the industry's transition to EUV-based process technologies, which dramatically altered supply dynamics, as TSMC became the only viable choice for big companies. While Samsung began using EUV tools for HVM in 2018, it used them only for its own chips, primarily due to tool scarcity and yield constraints.

The use of EUV tools at TSMC increased capital intensity and slowed capacity expansion, as EUV systems are physically larger than older DUV scanners and place their light source beneath the tool, making the addition of leading-edge output even more difficult. As a result, advanced-node wafers ceased to be interchangeable commodities and became capacity-constrained assets for tens of competing high-tech giants.

This allowed TSMC to price its output well above incremental cost without eroding demand. AI and HPC processors produced for customers like AMD, Broadcom, Google, Intel, or Nvidia carry significantly higher margins than legacy mobile or consumer chips. As a result, TSMC anchors pricing to customer value rather than manufacturing expense, which highlights the post-2019 divergence between ASP growth and COGS inflation.

In fact, big customers like AMD, Broadcom, Nvidia, and Marvell are willing to pay TSMC extra to lock in production capacity with the best process technologies to produce AI accelerators.

Advanced packaging further strengthened TSMC's position. By integrating leading-edge logic with sophisticated packaging technologies, the company increased customer lock-in and raised barriers for competitors. Notably, rising wafer costs now work in TSMC’s favor by discouraging new entrants and widening the competitive moat, rather than compressing margins as they did in earlier eras.

A new foundry model

The data published by SemiAnalysis indicates that TSMC has transitioned from a traditional foundry model focused on scale, utilization, and cost recovery to one defined by systematic undersupply, extreme capital intensity, and value-based pricing.

Leading-edge wafers are no longer commodities that can be obtained from multiple sources, but constrained assets required by trillion-dollar corporations. Given the current situation, pricing is increasingly anchored in the economic value delivered to customers rather than in incremental manufacturing costs. As a result, TSMC is thriving, and it will continue to do so until a viable challenger emerges. Neither Intel Foundry nor Samsung Foundry can currently compete against TSMC's leading-edge production capabilities, at least not yet.

It should be noted that TSMC's pricing power did not appear overnight. It emerged after decades of sustained capital investment, consistent yield leadership across successive nodes, and the gradual consolidation of the industry's most valuable supplier onto a single chip development and manufacturing platform under the OIP brand. Also, TSMC has attracted most of the world's leading chip designers, including Intel, which has its own manufacturing capacities.

These factors created both technical and economic lock-in, resulting in rising costs that reinforce competitive barriers rather than shrinking margins. This highlights a fundamental reality of advanced semiconductor manufacturing in general: TSMC's lasting pricing power has emerged from long-term structural investments along with stable performance increases and yields, and cannot be replicated in the short term.

A report this week claimed that a covert laboratory in China had managed to reverse-engineer an extreme ultraviolet (EUV) lithography scanner, one of the most complex machines on Earth, shocking many industry observers. However, China's 'Frankenstein' EUV chipmaking tool is known to be cobbled together from many disparate parts and not fit for manufacturing of any sort. In fact, the experiment hasn't even produced a single chip.

When you have been around long enough in the tech industry, one thing that you learn is that all the breakthroughs that happen around are a result of years, if not decades, of hard work of multiple teams. Then, bringing these breakthroughs to mass production takes another five to 10 years, depending on the involvement of big companies like Intel, which are well-suited to translate scientific innovations into production as quickly as possible. Here's why China's experimental EUV machine is still many years away from producing even a single chip.

Can you steal a blueprint for an EUV tool?

The report about a reverse-engineered EUV lithography machine that produces EUV radiation using the same CO2 laser-produced plasma (LPP) method that ASML uses reminded me of a scene in Christopher Nolan's movie 'Oppenheimer', when Lewis Strauss implies that the blueprints of the American nuclear bomb were stolen based on the fact that Russians have used a plutonium implosion device, like the one built in Los Alamos.

Indeed, blueprints and detailed scientific information from the U.S. Manhattan Project were stolen by Soviet spies. But while in the case of the atomic bomb, there were actual blueprints and detailed scientific information in Los Alamos, so seven convicted Russian spies had somewhere to steal from, there is no single detailed blueprint of an EUV scanner, according to a source with knowledge of the matter.

This may be correct, as the current Twinscan NXE platform is a product developed worldwide by a constellation of partners. While there is no doubt that China has a widespread spy network, stealing blueprints from multiple ASML facilities worldwide is difficult. What's even more challenging is stealing blueprints of parts from thousands of ASML suppliers worldwide, then assembling a functioning EUV lithography tool.

To add some context, Cymer — the inventor of ASML’s EUV LPP-based light source — is an American company (subject to all imaginable export controls) that ASML acquired in 2012. Cymer is now an internal part of the ASML supply chain. It provides the complete EUV light-generation subsystem, including the LPP source (which generates 13.5-nm radiation), a high-performance CO2 laser system, tin-droplet generation with a targeting unit, a debris-mitigation unit, and the EUV radiation collector. The hardware itself is precious, but so are the associated proprietary firmware, control software, and diagnostic tools required to continuously deliver stable, high-performance EUV radiation to the scanner for high-volume manufacturing (HVM).

Even then, Cymer's EUV source relies on a high-end ultra-precise mirror, coated with multilayer molybdenum-silicon (Mo/Si) stacks developed and made by Carl Zeiss in Germany. Since EUV radiation can be absorbed by almost anything, it also requires specialized mirrors from Carl Zeiss.

Without illuminator optics (which shape and uniform the beam using faceted mirrors) and projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors), the EUV source itself is useless in isolation. Even if one can steal blueprints of Carl Zeiss optics, replicating them is hard, if not impossible, because it requires utmost precision, and for now, Carl Zeiss is the only company in the world that can produce such precise optics hardware.

Can you steal an entire high-tech supply chain?

Beyond optics, ASML relies on thousands of suppliers across the United States, Japan, and Europe to deliver critical subsystems, which it then integrates into a single machine.

In the U.S., ASML’s Cymer division develops the laser-produced plasma light source, as mentioned above. Japanese companies supply ultra-precision mechanical components, sensors, and materials, including EUV photoresists, while European firms provide vacuum systems, precision structures, and specialty materials. Each supplier owns proprietary process technology that ASML itself does not fully control, which highlights that EUV lithography is ultimately sustained not by one company, but by an ecosystem whose collective intellectual property and integration experience form one of the deepest and most crucial technological chains in the semiconductor industry.

ASML's key ability is to orchestrate this ecosystem and integrate tens of thousands of externally developed parts with its own hardware and software into a machine that operates at nanometer-scale tolerances in high-volume manufacturing. Therefore, replicating an EUV lithography tool requires far more than copying a scanner's design (which is impossible as there is no single blueprint of an EUV machine and the company does its best to keep knowledge of its engineers the unit compartmentalized): it demands recreating an entire global supplier network, the co-development culture that binds it together through groups such as imec (which no longer works with Chinese clients), and the decades of trial-and-error that transformed fragile subsystems into a tool that is widely used for high-volume chipmaking.

Can you even DIY a lithography tool?

Considering the versatility of ASML's scanner design, as well as its omnipresence throughout the industry, there are numerous loopholes in obtaining certain parts of the machinery. Banks or chipmakers usually auction off older lithography equipment, and spare parts for advanced tools can be found on open markets (even eBay yields results for spares).

There is an additional rumor claiming that China intercepted a Cymer EUV radiation source while it was in transit, recorded the part numbers, then obtained them from various sellers or acquired refurbished scrap parts, and assembled a machine in a covert lab. Because not all parts can be acquired on the open market and their condition is unknown, this Frankenstein EUV tool does not work, according to Reuters.

Yet, because ASML's tools are designed to be easily serviced or upgraded in the field and spares appear readily available, Chinese chipmakers — such as SMIC — have managed to upgrade some of their existing tools using components obtained from third parties. For example, they have obtained stage and overlay performance data for the Twinscan NXT DUV lithography tools to make them more suitable for producing chips at advanced nodes, such as 7nm-class process technologies. It goes without saying that such Frankensteined upgrades and tools may not meet all of ASML's stringent standards for quality and reliability. If they increase SMIC's output of advanced wafers by 10%, such modifications may be worth the risk.

The modular nature of ASML's Twiscan platforms simplifies production and upgrade processes. Still, it also means that many of those components can be purchased by unauthorized buyers, such as China-based chipmakers sanctioned by American and European governments. In theory, this means that a Chinese chipmaker could DIY their advanced lithography tools from ASML using components available openly or refurbished in-house, which would, of course, take an incredible amount of time and effort, but would still get them the necessary hardware. However, even obtaining the hardware itself does not guarantee that it functions as intended, as ASML's tools are controlled by proprietary software and firmware that are not publicly available. As a result, even if Chinese specialists obtain the hardware, they will not be able to fully reverse-engineer it to meet ASML's standards.

All in all, it is not surprising that while Chinese scientists have managed to lay their hands on some of the components of ASML's EUV scanner, they have struggled to replicate the tool itself, as they lack a supply chain to produce high-tech parts. They also lack software and firmware that control these components, and therefore, a deep understanding of how they function when working in concert.

Chinese fabs are quietly extending the useful life and performance of older ASML deep ultraviolet lithography systems by upgrading key subsystems, as Beijing pushes to sustain advanced chip output under tightening U.S. and allied export controls, according to the Financial Times. The effort concerns installed immersion DUV tools, particularly ASML’s Twinscan NXT series. It’s understood that these activities have been underway over the past year at several leading-edge Chinese fabs, including those operated by SMIC and other state-backed manufacturers.

With access to EUV scanners cut off and new restrictions narrowing what ASML can legally service or upgrade, Chinese firms are increasingly turning to reverse engineering and grey-market components to improve overlay accuracy, stability, and throughput on tools originally designed for older process nodes. While this upgrade activity will never bring older DUV machines to parity with newer EUV machines, it could provide Chinese manufacturers with a meaningful recovery of capacity at advanced DUV-based nodes that remain commercially viable.

A growing ecosystem

Export controls imposed by the U.S. and its allies were primarily designed to prevent the export of cutting-edge technologies to China. For lithography, that meant blocking EUV outright and, more recently, placing tighter licensing requirements on the most capable immersion DUV scanners.

While these measures have worked as intended at the point of sale, they haven’t eliminated the installed base of immersion scanners already operating inside China. Over the past decade, Chinese fabs acquired dozens of high-end DUV tools, which now form the backbone of China’s most advanced production lines, particularly for 14 nm, 10 nm, and experimental 7 nm-class processes that rely heavily on multipatterning. Despite tens of billions in capital expenditure on chipmaking tools, China remains more than a decade behind current market leaders.

Under current rules, ASML is allowed to provide basic maintenance and support to keep these tools running, but it is restricted from performing upgrades that would materially improve performance beyond narrow thresholds. That has created a gap between what the original equipment manufacturer can legally do and what fabs are technically capable of doing with the right parts and expertise.

Into that gap has stepped a growing ecosystem of third-party suppliers and engineers. According to the report, Chinese fabs have sourced replacement or upgraded components such as wafer stages, optical elements, sensors, and control subsystems through secondary markets. Some of these parts originate from dismantled tools outside China, while others are produced by suppliers that operate in regulatory grey zones. Installation and calibration work is carried out by independent engineers, including former lithography specialists, rather than by ASML personnel.

This might sound inconsequential on the face of it, but with an outright ban on exports of new tooling, marginal improvements to existing tools compound quickly across high-volume lines. A small improvement in overlay stability can translate into higher yields across dozens of layers.

Overcoming overlay challenges

The primary challenge Chinese fabs will face in upgrading older DUV machines is overlay — the precision with which each new lithography layer aligns with previously-exposed layers. At older nodes, modest overlay errors are tolerable, but not at advanced nodes manufactured without EUV. Multipatterning schemes such as self-aligned double or quadruple patterning dramatically increase the number of exposures required per layer, and each exposure introduces additional misalignment risk.

ASML’s own product pages for the NXT immersion platform make clear how tightly overlay and system stability are linked. Wafer stage accuracy affects not only positioning but vibration and thermal drift, both of which become limiting factors as pattern density increases. Upgrading or replacing these subsystems can claw back some performance that would otherwise be lost to wear and aging. Even without changing the core exposure wavelength or numerical aperture, better stages and sensors can improve effective overlay and reduce the number of wafers scrapped due to misalignment.

This does not eliminate the structural disadvantages of DUV at 7nm-class geometries: Cycle times remain longer than EUV-based processes, costs per wafer are higher, and yields are generally lower. But for products where absolute cost is less critical than domestic supply and technical continuity, these penalties are acceptable.

Limits of enforcement

From a policy perspective, the actions of these firms highlight a shift in which enforcement pressure must be applied to constrain output. Blocking new tool shipments has already occurred, so the harder problem is constraining the flow of parts, expertise, and process knowledge that keeps existing tools competitive — at least for now.

Updates to U.S. BIS rules last year point in this direction, with expanded controls on semiconductor manufacturing equipment components, software, and services. Restrictions increasingly target not only lithography scanners themselves but also metrology tools, process control software, and advanced sensors that indirectly affect yields. The logic is to close the pathways that allow incremental upgrades to accumulate into meaningful capacity gains.

Even so, enforcement potential is limited. Lithography tools are complex systems with long service lives, and many components are designed to be replaceable. Distinguishing between a like-for-like replacement and a performance-enhancing upgrade is technically and legally difficult, particularly when work is performed by third parties rather than the OEM.

China, for its part, seems to be pursuing parallel strategies. Stretching DUV capability through upgrades is one track; developing domestic lithography tools is another. SMIC has tested homegrown immersion DUV prototypes, and state-backed programs continue to fund long-term EUV research, even if breakthroughs remain distant.

At the end of the day, we’re not about to see a sudden leap in Chinese semiconductor capability because a few fabs have upgraded their machines. What we could see, however, is a slower erosion of the gap that export restrictions were designed to maintain.

DUV will continue to significantly lag EUV-based competitors on both cost and efficiency, but they are unlikely to stagnate at their initial performance levels. Incremental improvements in yield and throughput can sustain meaningful volumes of advanced chips for domestic use, particularly in areas such as networking silicon and specialized processors.

A secret laboratory in China has quietly assembled a prototype extreme ultraviolet (EUV) lithography system and is now testing it stealthily, which means that the country may be close to replicating the most advanced technology that currently exists on Earth, reports Reuters.

The tool was reportedly developed by reverse engineering existing scanners from ASML and is said to be on-track to make prototype chips in 2028. If the information is correct, then Chinese scientists have made numerous breakthroughs across multiple disciplines in just a few years instead of decades, a scenario that appears extremely unlikely. Further analysis of the report indicates that China's laboratory is far from completing the tool, meaning that the country is years away from making chips using EUV lithography.

China's alleged EUV scanner

The system was reportedly completed in early 2025 inside a highly secured facility in Shenzhen and occupies nearly an entire factory floor. The Chinese machine reportedly generates EUV light with a wavelength of 13.5nm using the same laser-produced plasma (LPP) method as ASML Twinscan NXE machines, not the particle accelerator-based steady-state microbunching (SSMB) method designed at Tsinghua University or discharge-produced plasma (DPP) technology developed at Harbin Institute of Technology (HIT), which might prove the point that the system was reverse-engineered or at least contains a substantial amount of technologies pioneered by ASML.

ASML's laser-produced plasma (LPP) method uses tiny molten tin droplets, roughly 25–30 microns in diameter, which are injected into a vacuum chamber at a rate of about 50,000 droplets per second. Then, a high-power CO₂ laser first fires a low-intensity pre-pulse at each droplet, flattening it into a disk-like shape, followed by a more powerful main pulse that vaporizes the flattened tin and creates a superheated plasma with temperatures exceeding 200,000°C. This plasma emits isotropic EUV light, which is then collected by a large multilayer collector mirror and directed into the lithography system's reflective optics for patterning silicon wafers. This process repeats tens of thousands of times per second.

The machine is reportedly larger than the original, but it is operational in the sense that it can generate EUV radiation. However, it has not progressed to make usable chips as it still struggles to replicate 'the precision optical systems' features by Twinscan NXE systems. Furthermore, there is no word about power of the EUV light source, a crucial parameter that defines whether a tool can or cannot be used for volume production.

Not operational, for now

The report clearly states that the Chinese EUV scanner cannot currently be used to make chips, but the Chinese government reportedly wants the first chip prototypes to emerge in 2028, two or three years down the road. However, a more realistic target is 2030, four or five years from now, which is a long time. Meanwhile, from the report, it is not completely clear what stage the Chinese team is at today.

The report does not disclose which specific components of the optical system are the primary bottlenecks, as the article groups them rather generally. In particular, it is uncertain if the alleged EUV tool struggles to replicate the ultra-precise collector mirror system coated with multilayer molybdenum-silicon (Mo/Si) stacks, illuminator optics (which shapes and uniforms the beam using faceted mirrors), or projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors). ASML outsources the development and production of these components to Carl Zeiss from Germany. If the developers failed to replicate the collector itself, then the rest of the machine can hardly be called an EUV lithography system, as technically, the only thing they have is some kind of light source that they have yet to learn how to use. Yet, even if the developers cannot replicate illuminator optics or projection optics (suggesting that the collector itself is there), it still means they do not have even a poorly working EUV lithography tool, but rather a set of certain components.

When talking about advanced lithography equipment, we must keep in mind that such tools rely on seamless integration of sophisticated light sources, advanced optics, ultra-precise mechanical engineering, complex control software, and specialized materials, all of which must function reliably within nanometer-scale tolerances demanded by modern chip manufacturing. The story has no word about the state of the mechanical systems of the alleged tool: we know nothing about the wafer stocker system, wafer stages, or reticle stages, all of which are crucial for operation and yields.

To put China's EUV efforts into perspective, the secret lab is not even close to building an alpha tool. For now, what the Chinese lab has cannot even put the light on a wafer, save for printing lines and spaces, something ASML's tool could do in 2006, about 11 years before the company shipped its first Twinscan NXE:3400B system meant for high-volume manufacturing. Of course, reverse engineering certain components can give Chinese engineers a speed boost, but it remains to be seen how significant this one is going to be.

Reverse engineering an ASML Twinscan NXE?

According to Reuters's sources familiar with the effort, the Chinese EUV tool was 'developed' by a team that includes former engineers from ASML and recent university graduates, who allegedly reverse-engineered the company's EUV machines. The secret lab was so stealthy that its employees were given fake IDs to avoid detection of their concentration in one place by foreign spies.

Yet, it is unclear how any engineers from China could reverse engineer an EUV lithography scanner, as the Dutch company has never supplied one to China and hardly taught personnel from China how to service its EUV systems that are not allowed to be shipped to the People's Republic.

Reverse engineering a machine that contains over 100,000 parts is a hard task that takes hundreds of engineers with knowledge of the matter, which is why the secret entity led by the Government of China hired not only former engineers from ASML China, but also former employees of the Dutch company from elsewhere, presumably from Europe, Taiwan, and the U.S. For example, Lin Nan, formerly responsible for EUV light source technology at ASML, now leads a team at the Chinese Academy of Sciences’ Shanghai Institute of Optics that has filed eight EUV-related patents in just 18 months. Yet, this may mean that he uses his experience and knowledge rather than trying to replicate what he did at ASML or reverse engineer what he did at ASML due to the absence of an EUV scanner in his lab.

“It makes sense that companies would want to replicate our technology, but doing so is no small feat,” a statement by ASML published by Reuters reads.

The report says that around 100 recent university graduates are tasked with reverse-engineering parts from EUV and DUV lithography tools, with each workplace monitored by a dedicated camera that records the disassembly and reassembly process, an important part of the whole China's lithography program, according to the report. Employees who successfully put components back together receive bonuses. Yet again, a Twinscan NXE tool is a mechanism consisting of over 100,000 parts working together, not just a sum of all parts.

To sum up, China has reportedly built a secret prototype EUV lithography system and begun testing it, which suggests that the country may be closer to reproducing the most advanced chipmaking technology in existence than previously believed. However, details provided by the report indicate that China is still years — if not a decade — away from making chips using EUV lithography.

The machine can generate 13.5-nm EUV light using the same laser-produced plasma (LPP) method employed by ASML, which may demonstrate extensive reverse engineering of Western technology rather than the use of alternative domestic approaches. However, the tool is significantly larger than commercial systems available today, it cannot produce usable chips, and appears to struggle with other elements of EUV lithography, particularly ultra-precise optics supplied to ASML by Carl Zeiss. In fact, details about the system like light source power, optical subsystem maturity, and the state of critical mechanical components remain unclear.

While China expects first prototype EUV chips to emerge in 2028, Reuters's sources suggest 2030 is more realistic. Yet, the whole effort relies heavily on recruiting former ASML engineers and reverse engineering parts from existing EUV and DUV tools, which are not only hard to develop, but are extremely hard to make. Meanwhile, there is no word whether the current team responsible for disassembling and reassembling components can actually make an ultra-complex machine consisting of over 100,000 parts work flawlessly to produce semiconductors in high volumes.

Intel announced that it had installed ASML's Twinscan EXE:5200B, the industry's first High-NA lithography tool with 0.55 numerical aperture projection optics made for commercial chip production. The tool has passed acceptance testing and will be used for development of Intel's 14A fabrication process, which will be the world's first node to rely on High-NA EUV scanners for its most critical layers. The achievement indicates that High-NA EUV lithography is moving beyond early experimentation toward high-volume manufacturing (HVM).

ASML's Twinscan EXE:5200B builds on the 1st Generation EXE:5000 platform that Intel received in 2023 for its Oregon R&D fab. The new tool can 'print' chips with an 8nm resolution, enabling scaling beyond which is currently possible with Low-NA EUV tools that offer a 13nm resolution without using multi-patterning. Unlike the EXE:5000, the EXE:5200B is capable of processing 175 wafers per hour at a 50 mJ/cm² dose (up from 185 wafers per hour at at a 20 mJ/cm² dose) and achieves overlay accuracy of 0.7 nanometers, a critical parameter as feature dimensions continue to shrink.

To boost performance, the scanner integrates a higher-power EUV light source to enable faster wafer exposures at a 50 mJ/cm² dose. This in turn supports workable resist/process windows with strong image contrast while minimizing line-edge roughness (LER) and line-width roughness (LWR), which tend to be challenging with modern production nodes.

ASML and Intel did not limit their work to the optics and light source. They also reworked the wafer stocker system, which is responsible for how wafers are stored, queued, and moved in and out of the scanner. For next-generation tools, this component of the system has a direct impact on both productivity and patterning accuracy.

The updated stocker design improves lot flow and wafer handling to make sure that wafers arrive at the exposure stage in a more predictable state. At the same time, it provides tighter thermal control, keeping wafers and carriers at stable temperatures before and after exposure, an important factor as even tiny temperature variations can cause wafer expansion or contraction, leading to overlay errors, which in turn leads to an increase in defects and decrease of yields.

In addition, by reducing thermal and mechanical variation, the new architecture helps to minimize drift over long runs, thus enabling the scanner to maintain stable behavior and reducing the necessity for frequent recalibration. This stability will be particularly important for multi-pass and multi-exposure patterning, which will be inevitably used in the coming years for sub-1nm process technologies.

One of EXE:5200B's parameters that is hard to overestimate is its overlay performance of 0.7 nm, which was achieved by advancements of stage control, sensor calibration, and environmental isolation. Overlay performance is crucially important for next-generation process technologies as even tiny alignment errors can translate into yield losses.

It is necessary to note that ASML's Twinscan EXE:5200B is not just another EUV scanner in Intel's fab, but rather a foundation that is expected to enable Intel to regain its leadership in the semiconductor industry.

To use the new lithography tool, Intel is conducting parallel work on masks, etch processes, resolution enhancement techniques, and metrology that must be co-optimized to extract the maximum value from High-NA EUV patterning.

Intel says that its High-NA tools will enable more flexible design rules, reduce the number of patterning steps, lower mask counts, shorter cycle time, and increased yields thanks to lack of multipatterning with 14A and more advanced process technologies. Meanwhile, as Intel learns how to use High-NA EUV tools and gains valuable HVM experience, it will be able to insert High-NA EUV multi-patterning when it needs to in the sub-1nm era without significant effect on yields.

Japan’s Dai Nippon Printing (DNP) claims to have developed a nanoimprint lithography template capable of patterning logic with a feature size of 1.4nm, with plans for mass production in 2027. Canon, which has spent years pursuing nanoimprint lithography as a lower-power alternative to EUV, is already shipping its first 300mm tools to early research partners.

Together, the companies are pointing to imprinting as a way to cut lithography power consumption by up to 90% for advanced nodes. With TSMC and Samsung preparing for 1.4nm mass production within the next few years, DNP’s announcement comes just as EUV’s cost and energy demands are escalating the fastest in leading-edge fabs. The technology promises a dramatic shift in the economics of chipmaking, but whether it can meet the defectivity, overlay, and throughput requirements of high-volume logic remains an open and pressing question.

Skyrocketing energy use

The industry has grown accustomed to talking about how much power finished AI chips consume, yet the energy needed to fabricate those chips has grown at a comparable pace. EUV scanners each consume as much power as a small city — 1,400 kilowatts per tool — meaning that modern fabs that run several dozen EUV units must reserve enormous electrical capacity before a single wafer is exposed. This rising power use is compounded by the fact that shrinking features below 2nm increase the number of passes and exposures required, raising energy consumption per wafer for next-gen high-NA EUV.

Canon, which has long argued that the industry needs an alternative, offers a nanoimprint lithography (NIL) system that patterns wafers by stamping a pre-formed template directly into resist rather than projecting a pattern optically. That equipment can be priced much lower than EUV, and Canon has claimed that the technology uses up to 90% less power. Just last year, the company delivered its first commercial FPA-1200NZ2C tool to the Intel- and Samsung-backed Texas Institute for Electronics, 20 years after NIL research began.

NIL has been looked upon with some skepticism in recent years due to its incompatibility with both DUV and EUV, and the more conventional view that NIL could not meet the overlay stability or defectivity requirements needed for tightly packed logic at sub-2nm geometries. DNP’s new template material is the first attempt to challenge that assumption with concrete specifications and a timeline to commercialization.

The 1.4nm window

DNP’s template reportedly achieves 10nm line widths and is being evaluated ahead of planned mass production in 2027. Meanwhile, TSMC’s 1.4nm-class node is scheduled for risk production in the same year, with broader output in 2028, and Samsung has targeted a similar window. Both companies are expected to rely on EUV for the majority of patterning steps, but neither will be blind to the cost pressures. A secondary patterning pathway that reduces EUV load would be welcome, provided it clears the engineering hurdles.

Canon has pitched nanoimprint not as a replacement for EUV but as a complementary tool for specific layers and structures. Advanced patterning at sub-2nm often relies on techniques such as self-aligned double and quadruple patterning to extend resolution beyond single-exposure limits, and some researchers have explored how alternative lithography approaches, such as NIL, fit into these schemes. Nobody is claiming that a 1.4nm chip can be manufactured entirely through imprinting; rather, the proposal is that certain layers, currently exposed with EUV, could be transferred to a lower-cost, lower-power workflow.

That could have important ramifications for cost control, as every EUV step adds both energy consumption and process time. If a handful of those can be replaced by nanoimprint without sacrificing uniformity or yield, fabs gain extra flexibility. And when we’re talking about a 1.4nm production line churning tens of thousands of wafers per month, even marginal reductions in EUV dependency could translate to huge savings.

If DNP’s template can achieve the required precision for 1.4nm logic, the largest remaining obstacle is manufacturing scale. Imprint relies on a mechanical master pattern that must remain dimensionally perfect throughout its life. Even slight abrasion or contamination forces a replacement, and templates are both expensive and slow to produce. Running nanoimprint at volume will therefore necessitate a reliable supply of near-perfect masters and a way to verify their integrity rapidly enough to avoid passing defects downstream.

Advanced logic layers also require alignment precision on the order of a few nanometers across a 300 mm wafer. Achieving that through an act of mechanical contact is orders of magnitude more demanding than aligning an optical projection. Canon’s system tackles this with a step-and-repeat approach and local deformation control, but real-world results have yet to be demonstrated on the layers where tolerances are tightest.

Throughput is another potential constraint. While Canon’s multi-cell architecture improves parallelism, measured performance still trails EUV. Findings from Semi-analysis indicate that one cell of a Canon NIL tool processes approximately 25 wafers per hour, and a cluster of four reaches 100 wafers per hour. By contrast, ASML’s EUV scanners are typically in the 200-330 wafers per hour range in production. These shortfalls can compound rapidly when fabs operate 24 hours a day at scale, so any technology that slows the cadence of critical layers risks invalidating the cost savings gained elsewhere.

A narrow but meaningful opportunity

NIL isn’t going to displace EUV across an entire 1.4nm process flow, but it doesn’t need to. Some layers tolerate looser overlay and defect margins than the most critical gate and interconnect levels. Contact layers, certain pitch-split steps, and other non-critical mask levels are the most realistic candidates. Those are the points in the flow where DNP’s templates could be inserted without forcing a redesign of the full stack. Each layer moved off EUV reduces peak power draw inside the fab and lowers dependence on tools that dominate both capital and operating budgets.

That trade-off becomes more pronounced as logic designs grow more complex. Advanced GPUs and AI accelerators rely on unusually long lithography sequences, with repeated standard EUV exposures contributing heavily to cycle time and cost. Removing even a small number of those steps changes how fabs provision EUV capacity and how they allocate capital across new lines.

But reaching that point by 2027 — that could be tricky. DNP’s new template material looks promising, and Canon now has an NIL tool in production, but no chip foundry has committed to high-volume manufacturing. Meanwhile, overlay accuracy, template lifetime, and defect control at scale remain unresolved, and those constraints tend to tighten rather than relax as feature sizes shrink.

Lowering defect densities and increasing yields are the key challenges for chipmakers and chip designers who use hundreds of methods for both tasks. This is because semiconductor fabrication technologies involve thousands of steps, and each can affect defect rates and yields. A recent discovery by researchers at Chinese universities has revealed how resists behave during development and how the post-exposure bake (PEB) step can reduce defect density by up to 99% in some cases, according to a paper published in Nature. However, despite these bold claims, the study has dubious practical use.

Researchers from Peking University and Tsinghua University have managed to visualize how photoresist molecules dissolve, migrate, and entangle within developer liquid during the pattern-forming (development) step. To do so, the team used cryogenic electron tomography (cryo-ET) to reconstruct the true 3D structure of photoresist polymers in their hydrated state at sub-5nm resolution.

The study revealed that most photoresist molecules accumulate in clusters at the gas–liquid interface rather than being evenly distributed in solution, which generates defects. The scientists claim that a slight increase in post-exposure bake (PEB) temperature — from 95°C to 105°C in their case — and maintaining a continuous developer layer prevented these clusters, cutting defect density on 300mm wafers by over 99% using existing resists and DUV equipment.

However, it is worth noting that chipmakers carefully select PEB temperatures for each process technology to achieve the best possible results, which limits the practical implications of the research.

To make it easier to understand what was discovered, here's a sequence of steps within a lithography step.

1. Coating: The wafer is spin-coated with photoresist.
2. Exposure: Ultraviolet (UV) or Extreme Ultraviolet (EUV) light passes through a mask to selectively expose regions of the resist.
3. Post-Exposure Bake (PEB): The exposed resist is gently heated to activate the acid-catalyzed chemical reactions that change solubility.
4. Development: The wafer is rinsed with a developer solution (often TMAH in water for DUV), which dissolves the exposed or unexposed parts of the resist, depending on the resist type, to create a thin liquid film of developer and form the patterns. This step was the focus of the research.
5. Rinse and Dry: The remaining pattern is cleaned and dried for subsequent processing.

The study in the development phase discovered that these photoresist molecules form weak, reversible entanglements that lead to microscopic clusters, which turn out to be the hidden source of pattern defects seen on processed semiconductor wafers.

A hidden process

In immersion and EUV lithography, the developer's liquid film dissolves light-exposed regions of the resist, transferring the pattern to the wafer. While the process is well known across the industry, until now there was no clear understanding of the microscopic behavior of chemically amplified resists (CARs) during pattern development, as existing methods such as scanning electron microscopy (SEM) could only observe dried residues or indirect effects. As a result, process engineers usually rely on trial-and-error tuning of resist chemistry and developer composition, since nobody has observed the real-time behavior of photoresists during development.

Instead of using SEM or atomic-force microscopy, the researchers used a cryo-electron tomography tool — usually used in structural biology to study cells, protein complexes, or viruses in frozen states — to visualize the behavior of photoresists inside a developer liquid at nanometer resolution. To do so, they had to go to great lengths in sample preparation, vitrification speed (the cooling rate at which a liquid changes state without crystallizing), and electron-beam control.

For their research, the scientists used a poly(methacrylate)-based CAR, which is widely used in 193nm immersion and 13.5nm EUV lithography.

An observation

Cryo-ET imaging revealed that the CAR polymers — frozen in their natural liquid state — were preserved as flexible, thread-like chains with random coiled shapes. Analysis of the polymer density revealed that the concentration decreased sharply with depth: in 25nm– 100 nm-thick films, about 80% of the polymer mass accumulated near the gas–liquid interface. Hence, contrary to long-standing assumptions, the resist polymers were not evenly dispersed in the developer but were concentrated at the film surface, where they later formed clusters that caused pattern defects. The same pattern was observed with other resists (e.g., designed for 248nm and 365nm exposures) demonstrated the same pattern, but this was never a problem until recently. Control samples with only the developer showed no surface signal, confirming that the effect came from the polymers themselves.

Further 3D reconstructions (combination of hundreds of low-dose electron images taken at different tilt angles) showed that inside the film, 12nm-long polymer chains stayed mostly separate, while near the surface they gathered into 30 – 40nm clusters, dimensions well above the sizes of killer defects in modern technologies.

However, these clusters are reversible by heat and are not observed in real life. In fact, killer defects in modern nodes are an order of magnitude smaller, which implies that the clusters of CAR molecules are already mitigated by leading chipmakers in their cutting-edge nodes.

Furthermore, while increasing post-exposure bake (PEB) temperature from 95°C to 105°C disrupts the cohesive interactions and helps to get rid of some defects with certain manufacturing technologies, this is an absolute yield killer for modern fabrication processes that rely on EUV lithography.

Good for DUV, catastrophic for EUV

In Deep Ultraviolet (DUV, 193nm immersion) lithography, a PEB at around 105°C is well within the normal operating range for CARs based on poly(methacrylate). These resists form features roughly 20 nm – 40 nm wide, and their photoacid diffusion lengths (about 10 nm – 20 nm) remain small enough relative to those features to preserve resolution. At 105°C, the additional thermal energy slightly increases polymer mobility and acid diffusion, enabling more complete chemical reaction and smoother dissolution during development, which helps reduce residues and improve pattern uniformity, thus reducing defects and maintaining yields. However, in some cases a a PEB at around 105°C increases line-edge roughness (LER) and line-width roughness (LWR), which leads to degradation of critical dimension uniformity (CDU), which means that it should not be used for critical layers.

However, in EUV (13.5 nm) lithography, the situation is completely different. EUV resists are typically baked at 80°C–95°C to carefully balance acid mobility and reaction completion, maintaining critical-dimension control. EUV CARs must define features as small as 13nm, so even a few nanometers of acid spread can destroy pattern fidelity. Raising the PEB temperature to 105°C would greatly accelerate acid diffusion, broaden the reaction zone, and significantly increase LER/LWR, thereby blurring the fine features defined by the EUV exposure and potentially creating defects. It also increases stochastic variation by over-reacting CAR polymer chains unevenly, which leads to other defects.

The lowdown

While the study offers valuable microscopic insight into how photoresist polymers behave in developer films, its practical impact on semiconductor manufacturing is limited, to put things mildly. Increasing the PEB to 105°C is already within the normal safe range for DUV lithography and therefore not a breakthrough, which is why we do not see 30nm–40nm defects with modern DUV-based nodes. Meanwhile, the same temperature adjustment is unsuitable for EUV processes, as such temperatures can severely degrade resolution and yield.

As a result, the work is scientifically impressive, as it confirms mechanisms that chipmakers have long managed empirically. However, it offers no new solutions applicable to advanced nodes. Then again, if scientists from Intel, Samsung, or TSMC use cryo-ET as well, they might come up with something that leads to an actual breakthrough.

A European think tank suggests retaliatory trade measures against China, and the trigger appears to be Beijing’s threat to restrict exports of rare earth materials. But the suggested counterstrike would hit closer to home by expanding controls on semiconductor tooling, with ASML's DUV machines in the direct line of sight.

According to a recent report by Bloomberg, a European think tank named the European Council on Foreign Relations (EFCR) has begun mapping out “trade options” should diplomacy fail, amid growing frustration over asymmetric pressure tactics from Beijing.

In other words, if China weaponizes rare earths, the EFCR has suggested responding by tightening controls over legacy chip tools still flowing to Chinese fabs. Such measures considered by the EFCR, (which has no formal attachment to the European Commission) would put ASML — the only company in the world that can supply EUV scanners and one of just three capable of building advanced DUV machines — in a difficult position.

25% of revenue weighed up

In Q3 2025, ASML generated €2.4 billion in sales from China, accounting for 42% of system sales revenue and just over 25% of total revenue. More than 90% of those Chinese orders were for DUV systems like the Twinscan NXT:2000i and NXT:1980Di platforms, both of which remain exportable under current Dutch rules.

Unlike ASML’s EUV tools, which are already banned for export to China, these immersion DUV machines are used to fabricate chips on older nodes, and are critical to everything from automotive MCUs to AI accelerators built on older logic.

While the current licensing regime already restricts EUV exports, the think tanks suggest that the same controls could eventually extend to advanced DUV systems. Those tools are not exempt by default — they’ve simply been licensed on a case-by-case basis, and that door could close if diplomatic talks with Beijing break down. Bloomberg's report states that the EFCR is actively exploring those options, mapping out escalation scenarios in parallel with attempts to de-escalate.

If the EFCR's consideration of a ban on DUV exports catches the ear of Dutch authorities who follow through, it could force ASML to walk away from a quarter of its revenue overnight. While ASML has told investors it expects 2026 sales to hold steady even with a decline in China-bound shipments, that guidance assumes a controlled taper, not a blanket ban, as explored by the think tank.

Additionally, ASML continues to fulfil DUV orders that were secured before licensing rules tightened, many of which came from Chinese foundries racing to build up capacity while they still can. If those orders are cancelled or blocked midstream, the company could be left with idle capacity or orphaned inventory that isn’t easily redirected.

It’s tempting to write off DUV as yesterday’s technology. EUV gets all the attention, especially as TSMC and Intel push toward 2nm and beyond. But for China’s domestic foundries — SMIC, HuaHong, Nexchip, and others — DUV is the workhorse platform. Even Huawei’s Kirin 9000S, fabricated at a nominal 7nm, was likely stitched together using multi-patterned DUV.

The problem is that while China has developed domestic alternatives for some fab gear, it still lacks a credible substitute for ASML’s DUV steppers. Canon and Nikon, the other two players in the DUV space, are either capacity-limited or unwilling to challenge Dutch export policy. That would leave Chinese fabs with few options, particularly for immersion lithography.

Deepening tech isolation

If such a ban, as considered by the ECFR, were to pass, it would deepen China’s tech isolation, but also accelerate the buildout of domestic alternatives. SMEE, China’s state-backed lithography firm, has already shipped early-generation tools and is working on immersion platforms.

Meanwhile, SMEE spinoff AMIES recently showcased its latest lithography equipment at an industry event in Shenzhen. Even if performance is years behind, China has shown a willingness to subsidize inefficient infrastructure for the sake of supply chain resilience.

For ASML, cutting off China means forfeiting a quarter of its revenue and potentially triggering retaliatory action against its installed base of thousands of tools currently running across Chinese fabs, which all depend on ASML parts and servicing.

If the think tank's exploration were to pass, a full ban would hurt China in the short term, but hand it a longer-term incentive to accelerate tooling independence. It would squeeze ASML’s financials just as demand from customers in the West begins to normalize. And it would force the Netherlands to pick sides in a trade war it didn’t start.

Update 10/23/2025 8:12am PT: Article amended to reflect that the report came from a think tank.

When Dutch officials revoked ASML’s license to export Twinscan NXT:2050i and NXT:2100i extreme ultraviolet (EUV) lithography systems to China under U.S. pressure, it closed the door to the only machines capable of producing sub-7nm chips at scale.

That single policy decision has defined what some analysts are calling the semiconductor cold war, where SMIC and its peers cannot buy the equipment needed for modern AI accelerators, and every shipment of advanced tools is now scrutinized as if it were a weapons transfer.

What the blockade hasn’t done is stop China’s fabs. Instead, it has forced an awkward reliance on older deep ultraviolet (DUV) machines (via TrendForce) and sparked a parallel race to design local replacements. It’s a strategy of necessity, one that accepts higher costs and lower yields in exchange for continuity and independence.

Sanctions and the scramble for workarounds

EUV machines are some of the most complex industrial systems in existence. Packed with thousands of U.S.-origin components and priced at hundreds of millions of dollars a piece, they are the foundation of every 5nm and 3nm chip shipping, or planning to ship in the future. China has none, and the U.S. has made sure of that.

Successive rounds of sanctions since 2022 have blocked not just EUV exports, but also the most advanced immersion DUV systems, including ASML’s Twinscan NXT:1970i and NXT:1980i. The Netherlands and Japan joined those restrictions, and even service contracts for ASML machines installed in China are being scrutinized. ASML itself has admitted that a China-based employee stole proprietary EUV data, highlighting how valuable the technology has become.

The policy has pushed chip procurement into murky territory. Grey-market Nvidia GPUs continue to flood in through Hong Kong and Singapore despite being explicitly banned, with seizures measured in the hundreds of millions of dollars. But smuggling a workstation card is one thing; sneaking in a 180-ton lithography scanner is another. On that front, Washington’s chokehold on export controls has held up.

The DUV fallback plan

Deep ultraviolet lithography predates EUV by decades. Using 193nm argon-fluoride lasers, immersion DUV systems comfortably support 28nm nodes, with yields and costs increasing dramatically as nodes shrink further. With multi-patterning (exposing the same wafer multiple times with different masks) they can be stretched down to 7nm-class geometries. Intel’s disastrous 10nm rollout proved how costly and yield-sensitive that approach can be, but it remains the only path available to Chinese fabs.

SMIC’s Kirin 9000-class parts, built for Huawei, already demonstrate the limits of this strategy. It’s widely believed that they were fabricated with DUV and heavy use of multiple patterning. The chips work, but at lower volume and efficiency than anything coming out of Taiwan or South Korea.

For now, Chinese fabs are leaning on their existing ASML DUV fleets. Nearly half of ASML’s second-quarter equipment tooling shipments in 2024 went to China, despite the political pressure in Washington. Those sales are a reminder of just how dependent Beijing still is on imported tools. But the window is closing, and the focus is shifting.

Shanghai Micro Electronics Equipment announced in 2023 that it had built a 28nm immersion scanner, the SSA800-10W. It’s crude compared to ASML’s Twinscan line, but it represents the first domestically developed immersion tool, and critically, it was designed without U.S. intellectual property. According to a TrendForce report, SMIC is testing a prototype from Yuliangsheng, a Huawei-linked affiliate of SiCarrier, which also rated for 28nm, but with ambitions to scale toward 7nm with multi-patterning.

A fully domestic DUV scanner, even if mired in yield problems, would insulate Chinese foundries from future Western policy decisions. Let’s not forget that China has previously made it clear that strategic self-sufficiency matters more than perfect parity with TSMC or Samsung.

China is playing the long game

Researchers at Johns Hopkins University have unveiled a new approach to chipmaking that uses lasers with a 6.5nm ~ 6.7nm wavelength — also known as Soft X-rays — that could increase the resolution of lithography tools to 5nm and below, reports Cosmos, citing a paper published in Nature.

The scientists call their method 'beyond-EUV' — suggesting that their technology could replace industry-standard EUV lithography — but the researchers admit they are currently years away from building even an experimental B-EUV tool.

Soft X-Rays can challenge Hyper-NA. On paper

The most advanced chips nowadays are made using EUV lithography, which operates at a wavelength of 13.5 nm and can produce features as small as 13nm (Low-NA EUV of 0.33 numerical aperture), 8nm (High-NA EUV of 0.55 NA), or even 4nm ~ 5nm (Hyper-NA EUV on 0.7 – 0.75 NA) at the cost of extreme complexity of the lithography systems that have very advanced optics that cost hundreds of millions of dollars.

By using a shorter wavelength, researchers from Johns Hopkins University can get an intrinsic resolution boost even with lenses with moderate NA. However, they face many challenges with B-EUV.

Firstly, B‑EUV light sources are not yet ready. Various researchers have tried multiple methods of generating 6.7 nm wavelength radiation (e.g., gadolinium laser-produced plasma), but there is no industry-standard approach. Secondly, these shorter wavelengths — due to their high photon energy — interact poorly with traditional photoresist materials used in chipmaking. Thirdly, because 6.5nm ~ 6.7nm wavelength light is absorbed rather than reflected by pretty much everything, multilayer-coated mirrors for this type of radiation haven't been produced before.

Finally, these lithography tools must be designed from scratch, and currently, there is no ecosystem to support the designs with components and consumables. To sum up, building a B-EUV machine (or Soft X-ray machine?) requires breakthroughs in light sources, projection mirrors, resists, and even consumables like pellicles or photomasks.

Solving challenges one at a time

Researchers at Johns Hopkins University, led by Professor Michael Tsapatsis, explored how certain metals can improve the interaction between B-EUV (around 6 nm wavelength) light and resist materials used in chipmaking (i.e., they did not work on other challenges associated with Soft X-rays).

The team discovered that metals like zinc are able to absorb B-EUV light and emit electrons, which then trigger chemical reactions in organic compounds called imidazoles. These reactions make it possible to etch very fine patterns onto semiconductor wafers.

Interestingly, while zinc performs poorly with traditional 13.5nm EUV light, it becomes highly effective at shorter wavelengths, highlighting how important it is to match the material with the right wavelength.

To apply these metal–organic compounds to silicon wafers, the researchers developed a technique called chemical liquid deposition (CLD). This method creates thin, mirror-like layers of a material called aZIF (amorphous zeolitic imidazolate frameworks), growing at a rate of 1nm per second. CLD also allows for fast testing of different metal–imidazole combinations, making it easier to discover the best pairings for different lithography wavelengths. While zinc is well suited for B-EUV, the team noted that other metals might perform better at different wavelengths, offering flexibility for future chipmaking technologies.

This approach gives manufacturers a toolbox of at least 10 metal elements and hundreds of organic ligands to create custom resists tailored to specific lithography platforms, the researchers disclosed.

Summary

TSMC is by far the largest operator of ASML's EUV lithography tools in the industry, with a second-to-none supply chain of both hardware and raw materials. The company's requirements for EUV pellicles (a thin membrane that protects the photomask, which acts as a stencil for chip patterns) have gotten incredibly high. The requirements are so extreme that TSMC intends to retrofit one of its 200-mm fabs to produce proprietary EUV pellicles exclusively, according to DigiTimes.

However, TSMC's proprietary pellicles, which outperform ASML's own offering, are just the tip of the iceberg, as TSMC pushes efforts to improve the efficiency of its fabs and ASML's EUV lithography tools.

When TSMC first deployed EUV in 2019 on its N7+ process for Huawei's HiSilicon Kirin 9000-series processors for smartphones, it already controlled 42% of the global install base of EUV lithography machines, despite TSMC not being the first foundry to formally announce the use of EUV tools.

By 2020, as ASML accelerated shipments and introduced its N5 process technology, which uses EUV for several layers, TSMC captured 50% market share of all EUV machines; this increased to 56% in mid-2024, with 130 machines to its name. Now, TSMC likely controls around 200 EUV machines globally, across many of its fabs.

While the number of EUV systems increased at TSMC by over 10 times compared to 2019, the number of wafers the company processes increased by over 30 times over six years, which indicates that TSMC did an incredible job to reduce downtime and service time, while increasing the throughput of its EUV scanners, which ultimately leads to higher productivity.

Tool productivity

TSMC said at its Technology Symposium in mid-2024 that it had doubled the wafer output per EUV tool per day since 2019 by fine-tuning both the exposure dose and the photoresist materials used in its lithography process. But, to define how TSMC has managed such efficiency, we speculate how the company may have achieved this.

On the exposure side, TSMC refined dose-to-size and dose-to-clear thresholds to reduce scanner dwell time per exposure field, while preserving critical dimension (CD) uniformity and ensuring line-edge roughness (LER) according to spec, which enables faster patterning without compromising yield in EUV lithography.

Typically, lowering these doses reduces the scanner's dwell time per field, enabling more wafers to be processed each day. However, this must be carefully balanced to maintain pattern fidelity, including CD control and LER. TSMC has succeeded, at least if we decoded its description correctly. Since TSMC has not disclosed the exact details, this is speculation, based on publicly available information.

On the materials side, TSMC upgraded its photoresist systems, possibly adopting high-sensitivity chemically amplified resists (CARs) and potentially incorporating metal-oxide resists (MORs) to improve absorption at 13.5 nm wavelength. These materials can enable lower exposure doses without degrading resolution. However, the company has yet to disclose which materials were used and exactly how they may have been implemented.

In parallel, TSMC also improved scanner utilization efficiency by deploying predictive maintenance models, optimizing job scheduling, servicing tools in advance, enhancing vibration control, and improving cooling performance. These changes reduced unplanned downtime and increased daily tool availability, enabling each EUV system to process more wafers in a stable environment.

Particular Pellicles

One of the most important advances has been in pellicle technology. These thin membranes protect EUV photomasks (reticles) from contamination, but have long been a bottleneck due to durability and defect issues. ASML itself developed two generations of its reticles, but it appears as though TSMC has managed to outpace them.

Back in mid-2024, TSMC reported dramatic improvements of its in-house developed EUV pellicle performance, including a four times longer lifespan, four and a half times more wafer output per pellicle, and an 80x reduction in defects. This likely points to TSMC's full-stack engineering approach that spans materials, mechanics, and fab integration.

On the materials side, TSMC may have adopted advanced pellicle films such as ultra-thin silicon-based membranes (e.g., SiNx, ZrSi₂) or hybrid multilayers with optimized EUV transmittance, thermal stability, and mechanical strength. These materials withstand EUV radiation, minimize thermal deformation, and reduce outgassing. To further suppress particle adhesion and resist contamination-induced failures, TSMC likely treated the surface with anti-reflective coatings or plasma passivation; however, this is speculation and not officially confirmed.

There are additional ways to improve the lifespan of pellicles and reduce defects. For example, tighter cleanroom protocols would reduce the chance of particle transfer onto pellicles or reticles. However, TSMC has yet to disclose these methods.

Photomasks

In addition to pellicles that protect photomasks, TSMC is also refining the photomasks themselves. To meet the A14 node's lithography demands, TSMC improved mask accuracy and defect control to reduce defect density, boost yield, and ultimately increase throughput.

TSMC claims that its engineers had improved CD uniformity, pattern fidelity, and overlay precision for curvilinear features by modifying EUV mask blanks, increasing the resolution of multi-beam writers, and optimizing mask fabrication processes. These steps ensured a more consistent pattern transfer and better alignment across layers.

Defect control was a major focus, too. TSMC strengthened its pellicle inspection, reticle cleanliness, and developer rinse chemistry to suppress defects like bridging and pattern collapse. TSMC deployed advanced e-beam inspection techniques to detect sub-visible membrane defects and degradation early, enabling predictive maintenance and proactive replacement before catastrophic failures, which improves yields and lowers performance variability.

In the future, TSMC plans to develop next-generation blank materials and new process flows to support future EUV requirements.

Planarization

Improving photomasks and pellicles are not the only ways to lower defect density, increase yields, and reduce performance variability, particularly for 2nm and sub-2nm-class process technologies, according to TSMC. The company is working to improve polarization for its A16 and A14 fabrication processes.

Planarization is crucial in advanced EUV lithography because it ensures a uniformly flat wafer surface, which is critical for maintaining focus and pattern fidelity at sub-2nm nodes like TSMC's A16 and A14. EUV systems have an extremely shallow depth of focus, which is why any topographical variation could be a source of defocus, CD variation, or LER. Uneven surfaces also lead to non-uniform resist thickness, which affects dose absorption and etch uniformity. Also, overlay errors increase if subsequent layers are patterned on non-planar foundations.

TSMC likely improves this through advanced chemical mechanical planarization (CMP), optimizing slurry chemistry, pressure profiles, and endpoint detection to achieve tight within-wafer and wafer-to-wafer planarity control.

Energy efficiency

EUV scanners are known for heavy energy use, and here too TSMC has made progress. It says it reduced power consumption of EUV tools by 24% 'through innovative energy saving techniques.' The company's future target is a 1.5 times improvement in energy efficiency per wafer by 2030.

Reduction in EUV scanner power consumption was likely achieved through a combination of hardware-level and system-level optimizations, though which optimizations were made has not been disclosed. For example, TSMC could enhance the laser-to-EUV conversion efficiency, where a significant amount of energy is lost. Another key area is thermal management. TSMC likely refined liquid cooling systems, optimized coolant flow rates, and improved heat exchanger design to lower auxiliary power consumption while maintaining thermal stability.

On the system side of things, firmware and scheduler optimizations may have reduced idle-state energy use and improved synchronization between subsystems, reducing power draw during non-exposure operations. Predictive maintenance and better utilization analytics would help avoid performance degradation from inaccurate positioning, synchronization, or overheating, which prevents inefficient tool operation.

TSMC's position strengthens

Prinano Technology, a China-based developer of nanoimprint tools, has delivered its first semiconductor-grade step-and-repeat nanoimprint lithography system to a Chinese customer that is focused on specialty process technologies. Instead of using traditional light-based lithography techniques, this type of chipmaking tool 'stamps' a chip design onto the wafer with a quartz mold that's imprinted with the circuit design. 

Prinano's PL-SR-series machine is the first nanoimprint lithography tool (NIL) developed in China and set to be used for actual chip production once it passes all necessary tests at Prinano's client. Prinano is the second company in the world to deliver an actual nanoimprint lithography tool to a customer after Canon.

China's NIL tool seems to work

Prinano's PL-SR step-and-repeat nanoimprint lithography tool patterns wafers by physically pressing a rigid quartz mold engraved with nanoscale circuit designs into a thin layer of liquid resist deposited on the wafer surface. Instead of using light and projection optics like photolithography, the PL-SR directly replicates the mold's features at full scale. It applies the resist using a high-precision inkjet system that dynamically adjusts droplet volume for different pattern densities to ensure a thin, uniform residual layer (under 10nm, with less than 2nm variation). 

Prinano's PL-SR system processes 300mm wafers and achieves less than 10nm linewidth capability. During operation, the system aligns the mold and wafer to presumably sub-10nm precision, makes full contact without a vacuum, and imprints each field sequentially (which is why it is called a 'step-and-repeat' system), stitching them together to cover the full 300mm wafer. 

The machine features a proprietary template profile control mechanism — an important innovation for NIL — that promises to compensate for curvature mismatches between the rigid quartz mold and silicon wafer to enable transfer of features with aspect ratios over 7:1 without any distortions to maximize yields and reduce performance variations. After imprinting, the resist pattern is cured and later etched to form the final circuit structures.

With good results

While we cannot directly compare the NIL lithography machine with EUV tools, its linewidth capability can be compared to the resolution enabled by EUV scanners. Modern EUV systems with 0.33 NA optics operate at a 13.5nm wavelength and typically achieve 13nm minimum half-pitch in a single exposure, which is good enough to print a 26nm minimum metal pitch with a single exposure patterning. 

To achieve resolutions below 10nm (e.g., printing 3nm-class process technology features at 21nm – 24nm), EUV tools necessitate multiple patterning steps, thereby adding cost and complexity. NIL's single-step reproduction of sub-10 nm lines is potentially simpler than EUV’s multipatterning for the same size, but only if the quartz mold can be manufactured with matching accuracy and defects can be kept low. 

As for <10nm residual layer thickness with less than a 2nm variation, EUV lithography (EUVL) scanners do not create a 'residual layer' in the same sense as nanoimprint lithography systems, but it makes sense to compare these dimensions to EUV's critical dimensions uniformity (CDU). Modern EUVL tools achieve CDUs within 1nm – 2nm across the wafer, so in this sense, NIL and EUVL systems are similar. 

Prinano does not disclose overlay performance of its NIL tools, but its whitepaper about the tool says that the 'industry requires' overlay accuracy 'below 10 nm, and even approach the 1nm level' in the future. The latest ASML Twinscan NXE:3800E can achieve overlay performance in the range of 1.5nm – 2.0nm for high-volume manufacturing, depending on process conditions. Considering that Prinano does not directly disclose its overlay accuracy, we can only speculate that its target for now is between 1nm and 10nm.

But not for high-volume output

But competitive resolution is only one part of the equation. One thing to keep in mind is that NIL step-and-repeat imprinting is inherently slower than EUV or DUV projection lithography because each wafer field must be physically contacted, imprinted, cured, and separated before moving to the next. This mechanical cycle limits wafer-per-hour rates to the tens for fine features, whereas modern EUV tools can process around 200 wafers per hour. The slower pace makes NIL less suited for high-volume, leading-edge logic or memory production, even if its resolution is competitive.

And not for logic (at least for now)

Creating a powerful, reliable, and manufacturable light source for modern chipmakers is one of the most complex challenges in today's industry. Among all makers of litho systems, only ASML has successfully created EUV light to print the smallest chip features — but one startup has a radical new idea to change the status quo.

Inversion Semiconductor, a San Francisco startup backed by venture capital firm Y Combinator, plans to develop a light source based on a compact particle accelerator, which it claims would be 33 times more powerful than ASML's existing technology and could pave the way for producing finer chip features.

At the heart of Inversion's tech is a 'tabletop' particle accelerator that is 1,000x smaller than traditional particle accelerators and yet can deliver output power of up to 10 kW. Despite its tiny dimensions, Inversion claims that its light source, leveraging the laser wakefield acceleration (LWFA) method, can either speed up chipmaking 15 fold (assuming one 10 kW light source powers one lithography system) or power multiple chipmaking tools simultaneously, thereby cutting costs.

There are major challenges for the budding startup, however, as this specific type of accelerator requires petawatt-class lasers, which are both costly and power hungry. Additionally, unless Inversion Semiconductor collaborates with ASML (or perhaps other manufacturers of lithography machines), it would need to develop its own lithography systems and create a new ecosystem for its scanners, a time-consuming and expensive endeavor.

Given that Inversion Semiconductor has no experience building high-volume, 24/7 fab tools, the company's ambitions are lofty, and there's no guarantee it will fulfill the promise it's making on paper.

10 times more power-hungry than ASML

Inversion Semiconductor was founded in 2024 by Rohan Karthik (CEO) and Daniel Vega (CTO), both of whom hold master's degrees in mechanical engineering and applied physics. The company is backed by Y Combinator. Inversion's goal is to develop a compact, high-performance light source based on a particle accelerator that would offer an output power of 10 kW, which is 10 times more powerful than what ASML plans to achieve over the next decade.

This particle accelerator could produce lasers with wavelengths between 20nm and 6.7nm, including 13.5nm light used by ASML for both Low-NA EUV and High-NA EUV lithography tools today.

Light with a sub-10nm wavelength is called a soft X-ray, which is not currently used for chip production due to its high absorption rates by most materials. So, while sub-10nm wavelengths are not currently used in chip production, it might prove to be a promising field for research in the long-term future.

Inversion's ambitions do not end with the development of just a light source, but span all the way to building complete lithography tools to compete against ASML directly.

Using particle accelerators as light sources for lithography tools is a widely discussed and researched topic in the industry, but Inversion Semiconductor plans to use what it calls 'tabletop particle accelerators' that can accelerate electrons to extremely high energies over centimeters, rather than kilometers, as seen in accelerators such as the Large Hadron Collider used by CERN.

Riding on the wakefield waves

Immersion intends to use accelerators relying on the laser wakefield acceleration (LWFA) technique, which is significantly different compared to methods used by ASML and CERN. LWFA uses powerful, ultra-short (femtosecond-scale) laser pulses interacting with plasma, consisting of free electrons and positively charged ions.

When an intense laser pulse travels through plasma, it creates strong electric fields by pushing electrons aside and generating plasma waves, or 'wakefields' behind it. Electrons can become trapped and accelerated rapidly within these waves, gaining substantial energy in a very short distance as they rush back to their original position. The plasma wave accelerates electrons in fields that are 100 – 1000 times stronger than those found in a conventional accelerator, according to the Imperial College London.

The accelerated electrons can then be used for various practical applications, including compact X-ray sources and semiconductor lithography, just to name a few. Unlike traditional EUV sources, the LWFA method generates radiation that is coherent, monochromatic, and precisely tuneable, enabling wavelengths shorter than 13.5 nm (e.g., 6.7 nm target, which is far from industrial deployment), which could be instrumental for next-generation lithography systems.

The LWFA mechanism accelerates electrons to energies reaching multiple giga-electron volts (GeV) over distances as short as a few centimeters, thus miniaturizing high-energy electron acceleration systems dramatically, from large facilities down to tabletop-sized devices, which could spark further innovation for the semiconductor industry.

Immersion Semiconductor's immediate goals

Immersion Semiconductor's progress to date includes setting up a small laser laboratory within the Y Combinator offices to develop new laser stabilization techniques, and building initial LWFA prototypes capable of producing short-wavelength radiation. They have also partnered with the Lawrence Berkeley National Laboratory and the BELLA Center to collaborate on the BELLA-LUX project, focusing on refining laser stability and improving the generation of suitable light for semiconductor use.

The company's immediate goal is to develop Starlight: a high-power, tunable light source capable of producing 1 kW of soft X-ray light in the 20 nm to 6 nm wavelength range. If successful, the device could find use in applications like industrial X-ray imaging and semiconductor mask inspection. Companies such as Tesla and Applied Materials have expressed interest in these early-stage developments, according to Immersion Semiconductor.

In parallel, the company is working on advanced mirror systems to reflect and focus the generated EUV light (i.e. higher than 10nm), which are necessary to direct the light precisely for wafer patterning. The first lithography system based on this technology — designated LITH-0 — will be powered by Starlight, with the goal of demonstrating practical silicon wafer patterning capabilities. However, no-one knows when Inversion Semiconductor's LITH-0 will be complete, and fully-functional.

Are there any Caveats? Many!

On paper, Inversion Lithography's plans seem sound and the LWFA method of generating EUV radiation (or light) seems almost perfect. However, there are many caveats.

First up, an LWFA accelerator chamber may be small, but it requires a petawatt-class, ultrafast laser systems which are extremely complex, large, and expensive. Cooling and maintaining such lasers for reliable, non-stop fab operation is something that nobody has tried. It is also unclear whether Immersion Semiconductor's setup can fire those lasers at a consistent repetition rate per second.

Secondly, even researchers from the John Adams Institute for Accelerator Science at Imperial College London admit that LWFA produces electron beams with large energy spread (variation in electron energies) and beam divergence (wider spread of trajectories) at beyond 1 GeV.

For lithography, the generated light must be highly stable in wavelength, direction, and coherence to achieve precise and repeatable patterning. Instability translates into poor resolution leading to performance variability and yield loss.

Thirdly, while today LWFA-based tools featuring a laser with 13.5nm light source can use mirrors and optics developed for ASML's Low-NA and High-NA EUV tools, should they move to shorter wavelengths, they are poised to use new mirrors and optics. This will be a problem, of course, if Inversion Lithography actually decides to develop its own lithography systems, but, this means it will have to develop a whole new ecosystem.

A more realistic variant could be making its LWFA-based source compatible with existing tools from ASML. However, there is a problem too. Integrating an LWFA light source with existing EUV lithography scanners would be complex as it would require developing new beam shaping, focusing, and metrology systems, just to name a few challenges. While ASML has solved all the challenges associated with its Cymer light sources, we can only wonder whether the company is interested in making its tools work with a third-party tool. As for other makers of litho machines — Canon and Nikon — they have not managed to go beyond KrF and ArF lasers and tools, respectively, so chances that they will manage to build EUV (or beyond EUV) scanners are low. Also, keeping in mind that we are talking about an at least 1 kW light source, the industry will also need new resists, pellicles, and other expendables to make everything work.

Perhaps the biggest challenge for Inversion Lithography is that it does not have any experience in production of rapidly-serviceable mass-produced tools that are engineered for fabs operating 24/7 and are highly compatible with other production equipment in the building.

Summary

Inversion Lithography aims to develop a compact, LWFA-based light source that 10 times more powerful than ASML's current EUV light sources while also targeting even shorter wavelenghts. Inversion says that its light sources will be tunable and will create coherent radiation for finer semiconductor patterning. Eventually the company aims to build a light source with a 10 kW performance (10 times more powerful compared to what ASML plans over the next decade), it can either greatly speed up production of chips (by 15 times, the company claims), or power multiple lithography systems with one light source, thus cutting down costs.

However, there are major challenges as an LWFA-based accelerator require a petawatt-class laser, which consumes a lot of power and is expensive. Also, unless Inversion teams up with ASML (an unlikely scenario) or other makers of litho tools like Canon and Nikon (also unlikely) and develops its own scanners, it will have to develop an all-new ecosystem for its machines, which is timely and extremely costly. Also, if the company goes down this path, it will have to gain experience in creating and maintaining high-volume production 24/7 fab tools.

Intel has made significant strides in implementing High-NA EUV lithography by installing two High-NA litho machines, developing custom reticles as well as all-new optical proximity correction, and processing 30,000 wafers. However, major hurdles remain: the $380 million – $400 million tool cost and potential necessity to overhaul photomask supply chain limits economic viability of the technology. Furthermore, a single High-NA EUV exposure costs 2.5 times more than a single Low-NA EUV exposure, which raises further questions about economic feasibility over the next few years, reports SemiAnalysis.

Puzzling economics

ASML's Twinscan EXE:5000 weighs 150 tons and is priced around $380 million – $400 million, roughly double that of its Low-NA Twinscan NXE predecessors. At the SPIE conference earlier this year IBM presented simulation data comparing different approaches to patterning. It showed that replacing three or four Low-NA masks with one High-NA exposure could yield cost savings. For example, IBM estimated a four-mask self-aligned double patterning flow is 1.7 to 2.1 times more expensive than a single High-NA exposure. But when only two Low-NA passes are replaced, High-NA becomes more expensive by 2.5 times, which means that High-NA is only cost-efficient when it can eliminate three or more exposures.

This does not mean that the industry will not need High-NA tools. It means that the industry will have tangible benefits of using High-NA EUV lithography when it needs triple or quadruple patterning with Low-NA EUV scanners, which will depend on process technologies that the industry adopts and aggressiveness of process scaling going forward.

According to Intel, this may happen sooner rather than later. The company showed imaging results, made economic comparisons, and discussed patterning alternatives, and ecosystem readiness, painting a detailed picture of where High-NA EUV stands in 2025 at the SPIE Advanced Lithography conference earlier this year.

The imaging results included key device layers such as metal and contact levels. In the case of metal layers, Intel used one High-NA exposure to replace a previous scheme requiring three separate Low-NA exposures and around 30 total process steps. This simplification could reduce cost and defectivity for complex interconnect structures. In contact holes, yield from early High-NA tests matched that of established multi-patterning flows, despite the initial masks being early-stage test versions. These outcomes suggest High-NA EUV lithography is technically viable for some of the most challenging layers at upcoming nodes.

Intel itself is expected to selectively implement High-NA EUV lithography for a few layers within its Intel 14A (1.4nm-class) process technology, though ecosystem readiness could impact the company's plans. For Intel, the good news is that it is at the helm of that ecosystem development and will therefore have a lead over rivals.

Parallel development

By acquiring and installing two ASML Twinscan EXE:5000 lithography tools ahead of competitors, Intel is ahead of the industry in gathering process data and proving viability for high-volume manufacturing. Intel did everything it could to get its High-NA EUV scanners as early as possible. It received the first Twinscan EXE:5000 machine over a year ago and skipped ASML's typical factory tool qualification, which includes assembly of the tool at an ASML facility — opting instead for assembly and startup at its own D1D fab near Hillsboro, Oregon. This early decision gave Intel a head start in validating the system and building process readiness. To support its development efforts, Intel exposed over 30,000 wafers across both High-NA tools, making it the most experienced user of this new platform.

But getting a new scanner and assembling it are only some of the challenges associated with making it work properly. In addition, Intel needed to develop process technology itself, photomasks, resists, and optical proximity correction (OPC) software enhancement techniques. Normally, since all these things are co-dependent, they are developed serially. However, Intel adopted a parallel development strategy to meet the tight timeline for its 14A (1.4nm-class) node, which is expected to be production ready in 2026. The company shared details how it managed to do so at this year's SPIE Advanced Lithography conference.

Intel began to develop OPC well before it got its High-NA EUV tool running. The company used simulations and exposures on conventional EUV tools to extrapolate and fine-tune models intended for High-NA EUV. This strategy bypassed the usual delay in mask preparation and enabled immediate pilot line operation once the High-NA scanners were up. Results exceeded expectations: source power reached 110% of target (a first for an ASML scanner at launch) and overlay alignment measured at 0.6nm, which is comparable (yet, not as precise) to mature Low-NA systems.

By now, Intel has made significant strides in developing production ready photomasks, resists, OCP, and other elements of High-NA EUV production flow. However, it looks like the obstacles associated with adoption of High-NA EUV tools by the industry are not only engineering challenges, but also economic hurdles associated both with infrastructure development and usage scenarios.

Not yet ready for prime time

One of the challenges with High-NA EUV lithography is the two times smaller exposure field compared to Low-NA EUV lithography due to higher numerical aperture of projection optics: 26 mm × 16.5 mm vs. 26 mm × 33 mm.

This is a major challenge for large chips like GPUs and CPUs, which often exceed the 13×26 mm limit of a single High-NA exposure. Therefore, to pattern these dies, two or more overlapping exposures (stitched fields) must be used (an alternative is to use a multi-chiplet designs). This introduces alignment complexity, risks of overlay errors, and yield loss in the stitched regions. Also, with fewer chips fit per exposure field, more passes per wafer are required, which reduces the wafer-per-hour rate and increases cost per wafer.

ASML proposes to use accelerated stages (i.e., accelerate how the wafer moves under the photomask) to compensate for higher number of exposures. However, Intel has long proposed to use a larger 6×12-inch photomask instead of industry-standard 6×6-inch photomask. A larger photomask solves the half-field problem by doubling the reticle area, allowing it to hold two adjacent half-field images side by side. When used with appropriately configured High-NA optics, this enables the system to expose a full 26 mm × 33 mm field in one scan pass, restoring the field size to that of Low-NA tools. This obviously eliminates the need for stitching and all the challenges associated with it.

However, the shift to larger photomasks would require a complete overhaul of the mask supply chain, from blank preparation and e-beam writing to handling and fab integration. ASML acknowledged that internal studies on larger masks are in progress but has not committed to bringing the capability to market. The change would disrupt the company's platform unification strategy for Low-NA, High-NA, and eventually Hyper-NA tools and potentially reduce sales of higher-end tools.

In photoresist development, metal-oxide resists are gaining ground as the preferred option for High-NA, according to the Intel's presentation at SPIE. These materials provide better performance in terms of resolution, line-edge roughness, and dose sensitivity, especially important given the thinner films required by the thin depth-of-focus associated with High-NA optics. Traditional chemically amplified resists struggle with etch resistance at the thicknesses now needed, while metal-oxide formulations retain sufficient durability during pattern transfer. Most SPIE 2025 data shared for High-NA tools used metal-oxide resists rather than legacy organics, according to SemiAnalysis.

The method of applying and developing photoresist is another point of industry concern. Tokyo Electron currently dominates the standard wet process with spin-on coating and wet development in its track tools. Lam Research is attempting to gain share by promoting a dry deposition and dry development approach, done in its proprietary tools.

Conclusion

Legendary Intel CTO and CEO Pat Gelsinger is now serving as executive chairman at xLight, a startup developing a free electron laser (FEL) technology as a light source for extreme ultraviolet (EUV) lithography systems.

Using a particle accelerator to generate light for litho machines has been discussed previously, but xLight claims it can produce such a source by 2028 — while maintaining compatibility with existing tools.

"As part of my new role at Playground Global, I have joined xLight as executive chairman of the board," Gelsinger wrote in a LinkedIn post. "I will be working closely with Nicholas Kelez and team to build the world’s most powerful Free Electron Lasers (FEL) by leveraging particle accelerator technology."

EUV lithography is an advanced technique used for semiconductor manufacturing to create extremely small — we are talking about an 8nm resolution for High-NA EUV and a ~13nm for Low-NA EUV — circuit patterns on silicon wafers that uses EUV light with a 13.5nm wavelength. At present, only ASML can build EUV litho systems and these use an intricate way of producing light with a 13.5nm wavelength.

There is more than one way to create a light with an extremely short wavelength to produce chips with an 8nm ~ 13.5nm resolution, however. One of them is to use a particle accelerator as a laser produced plasma (LPP) light source.

xLight has created an LPP source that delivers four times the power of the most advanced systems available today, according to the Gelsinger's post. ASML's Twinscan NXE:3600D has a 250W LPP source, whereas the NXE:3800E is equipped with a ~300W source.

While ASML has demonstrated EUV source powers above 500W in research settings, these higher power levels are not yet available in commercially deployed systems. Yet ASML continues to work towards increasing EUV source power, with plans to double output to 600W and a roadmap extending beyond 1,000W.

Apparently, xLight and Gelsinger claim that the company has an LPP source that is beyond 1,000W today and that will be ready for commercial applications by 2028.

Gelsinger claims that xLight's technology cuts per-wafer costs by around 50% and lowers both capital and operating expenses by threefold, which is a major leap in manufacturing efficiency. While we do know the approximate price of ASML's Twinscan NXE:3800E (around $240 - $250 million), we do cannot really guess the price of the light source alone.

Meanwhile, the claim that the new LPP source can lower capital expenses and operating costs by three times can potentially mean a substantial decrease of a FEL-based litho tool cost compared to today's machines from ASML.

Speaking of ASML, it is important to note that xLight does not aim to replace ASML's EUV litho tools, but produce an LPP source that "will be connected to an ASML scanner and running wafers by 2028." This may mean that xLight's LPP source will be compatible with existing ASML tools, but it is unclear whether it will be compatible with next-generation High-NA EUV tools (most probably yes, as they use the same LPP sources as existing Low-NA EUV tools). It also remains to be seen whether xLight's LPP source can be attached to TwinScan machines in fab environments.

Remember that fabs are built to accommodate specific tools and in case of Low-NA EUV systems it means that the light source is located below the machine itself, whereas in case of High-NA EUV tool its LPP source is located on the same level, so any 'third party' LPP source has to take these facts into account. For now, the particle accelerator looks rather big for existing fabs, so FEL is probably applicable for next generation of fabs if it is proved efficient.

It is noteworthy that while xLight believes that its FEL technology represents a multi-billion-dollar opportunity in the long term, it also opens near-term revenue in other key areas. The company believes that its systems are well-suited for high-power metrology and inspection tools. Perhaps, even beyond semiconductors, as it can address challenges in national security and biotech: from point defense and space debris control to medical imaging and scientific research.

ASML and Imec this week established a five-year partnership designed to enable Imec's researchers and developers access to ASML's latest tools. The move is focused on sub-2nm process technologies that will require ASML's latest lithography (including High-NA), metrology, and inspection tools. Imec will ensure that engineers from academia and various companies have the latest equipment for their research, whereas ASML will ensure that its tools are incorporated into leading-edge process technologies.

Under the partnership, Imec will gain access to ASML's comprehensive range of advanced wafer fabricating equipment (WFE), including range-topping Twinscan NXT (DUV), Twinscan NXE (Low-NA EUV tools with a 0.33 numerical aperture optics), and Twinscan EXE (High-NA EUV tools with a 0.55 numerical aperture optics) lithography systems. Additionally, imec will incorporate ASML's YieldStar optical metrology solutions and HMI’s single- and multi-beam inspection tools into its facilities.

These tools will be installed in Imec's pilot line in Belgium and incorporated in the EU- and Flemish-funded NanoIC pilot line.

The latest-generation of equipment from ASML will be used to develop next-generation semiconductor production technologies, particularly sub-2nm fabrication technologies. It is believed that for efficient manufacturing at fabrication nodes below 2nm, lithography tools must support an 8nm resolution with a single exposure, something that only High-NA EUV tools can achieve. However, each High-NA EUV system costs $350 million, which makes it impossible for new players or researchers to obtain one.

ASML and Imec researchers previously worked with High-NA (0.55 NA EUV) tools primarily at ASML’s dedicated research facilities in Veldhoven, Netherlands. ASML installed these first-generation High-NA EUV machines at its own sites for initial tests, evaluations, and collaborative research with Imec and other partners.

Now, under the new agreement, Imec will have direct, on-site access to High-NA equipment within its own research lines in Leuven, Belgium, specifically in its state-of-the-art pilot facility and the EU- and Flemish-funded NanoIC pilot line. This marks the first time Imec researchers can use the High-NA EUV technology directly at their own facility, which will speed up their work.

Providing Imec with access to the High-NA EUV technology was included in the Next Gen-7A project (IPCEI22201) and financed by the Dutch government as an Important Project of Common European Interest (IPCEI).

"We are excited to continue our longstanding unique partnership with ASML, offering the industry access to the most advanced patterning solutions for over 30 years," states Luc Van den hove, President and CEO at Imec.

"The inclusion of ASML’s full product portfolio will allow us to expand and further mature the capabilities of our pilot line, providing the entire semiconductor ecosystem with the most advanced R&D to tackle the challenges of AI-driven technological advancements. Since Imec has a strong focus on sustainable innovation, having this explicitly included in our partnership is a great addition."

In addition to working collaboratively on next-generation sub-2nm nodes for logic chips, ASML and Imec plan to collaborate on DRAM process technologies, silicon photonics, and advanced packaging solutions.

Micron introduced its 16Gb DDR5 devices made on its new 1γ (1-gamma) fabrication process that uses EUV lithography, a first for Micron, today on March 25. The new IC not only delivers higher performance than its predecessor, but it also consumes less power and is poised to be cheaper to make. The company also said that its 1γ manufacturing technology (6th Generation 10nm-class node) will eventually be adopted for other DRAM products.

DDR5 at 9200 MT/s

Micron's lead 1γ product is the company's 16Gb (2GB) DDR5 IC that is rated for a 9200 MT/s data transfer rate at an industry-standard voltage of 1.1V. Compared to its predecessor — a 16Gb DDR5 IC made on 1β fabrication process — the new device consumes 20% less power and features a 30% higher bit density, which may translate into a comparable decrease in production cost once the new chips achieve yields comparable to that of 1β 16Gb DRAM devices. 

While Micron rates its latest 16Gb DDR5 ICs at 9200 MT/s, this speed bin is significantly higher than anything in the latest edition of the DDR5 specification. The company stresses that the chip can run at JEDEC-compliant speed grades just fine, and the higher speed bin will enable some future proofing and compatibility with next-generation CPUs. Micron also suggests that CUDIMMs or CXL-based memory modules could leverage higher-than-JEDEC speeds. DIMMs for enthusiasts will also likely adopt the new DRAMs for their post-10,000 MT/s modules.

Micron is currently sampling its 16Gb DDR5 ICs made on 1γ technology and products on their base (i.e., chips and modules) with laptop and server manufacturers and expects their qualifications to be completed in one or two quarters. That means we should see Micron's latest memory devices in retail products starting mid-2025. The company expects all types of memory modules — for desktops, laptops, and servers — to adopt its new memory chips.

Considering the fact that Micron's 1γ-based DRAMs offer a combination of valuable qualities for all market segments — enhanced performance for desktops as well as lower power consumption for notebooks and servers — we indeed expect the firm's latest 16 Gb DDR5 ICs to become quite popular when they hit the market.

Over time, Micron will use its 1γ fabrication technology to make other types of memory products, including GDDR7, LPDDR5X (at up to 9600 MT/s), and data center-grade products, so the node will become a workhorse for the company.

1γ manufacturing technology

Micron's 1γ manufacturing process is the company's first technology to adopt extreme ultraviolet lithography (EUV), something that other leading memory makers adopted years ago. It's been a while in coming and looks to offer significant benefits relative to existing product lines.

Micron did not disclose how many EUV layers the new production node uses, but we can speculate that the company uses EUV for critical layers that would otherwise require the usage of multi-patterning, which lengthens production cycles and can affect yields. Micron does say that 1γ uses EUV in conjunction with multi-patterning DUV techniques. Also, Micron's 1γ DRAM process technology adopts next-generation high-K metal gate technology and an all-new back-end-of-line (BEOL) circuitry.

" In addition to EUV adoption in 1γ, we have introduced our next generation high-K metal gate CMOS and advanced back-end-of-line processes, which together enable the 9200 MT/s [data transfer rate], a 15% performance improvement over 1β DRAM […] while reducing power by about 20% over 1β," said Shigeru Shiratake, senior vice president of DRAM Technology Development at Micron.

For now, Micron produces its 1γ DRAMs at its fabs in Japan, where the company's first EUV tool was installed in 2024. As the company ramps up production of 1γ memory, it will add more EUV systems to its fabs in Japan and Taiwan.

Intel has started using two leading-edge ASML High-NA Twinscan EXE:5000 EUV lithography tools, the company revealed on Monday at an industry conference, Reuters reports. The company uses these systems for research and development purposes, and so far, Intel has processed tens of thousands of wafers using them. 

Intel installed and started using two High-NA EUV lithography tools from ASML at its D1 development fab near Hillsboro, Oregon, last year and has now processed as many as 30,000 wafers using these systems, Intel engineer Steve Carson revealed at the SPIE Advanced Lithography + Patterning conference. Intel was the first leading chipmaker to get High-NA EUV machines (which are believed to cost €350 million each) last year and plans to use them to produce its 14A (1.4nm-class) chips several years down the road. 

Adopting an all-new manufacturing tool ahead of competitors is important, as it enables Intel to develop various High-NA EUV manufacturing aspects (such as glass for photomasks, pellicles for photomasks, chemicals, etc.) that could eventually become industry standards. Also, ASML is poised to develop its Twinscan EXE:5000 High-NA EUV tools with feedback provided by engineers from Intel, which could give the American giant an edge over competitors over time. 

Processing 30,000 wafers in a quarter is far below what commercial-grade systems can do. However, the number is massive for R&D usage, demonstrating how serious Intel is about becoming the leading chip maker in the High-NA EUV era.

Although ASML considers its Twinscan EXE:5000 High-NA EUV lithography tools to be pre-production tools not designed for high-volume manufacturing, Intel has reportedly said these systems are “more reliable than earlier models.” Still, the report does not elaborate on whether ASML’s Twinscan EXE:5000 is more reliable than the company’s pre-production Twinscan NXE:3300 tool from 2013, which was used to develop the existing EUV ecosystem, or the production-grade Twinscan NXE:3600D or NXE:3800E that are used for high-volume manufacturing (HVM) today. Considering that ASML uses similar light sources for NXE and EXE machines, they may indeed be very reliable. 

ASML’s Twinscan EXE High-NA EUV lithography tools can achieve a resolution of down to 8nm with a single exposure, a substantial improvement compared to Low-NA EUV systems that offer 13.5nm resolution with a single exposure. While current-generation Low-NA EUV tools can still achieve an 8nm resolution with double patterning, this lengthens the product cycle and can affect yields. High-NA EUV tools reduce the exposure field by half compared to Low-NA EUV systems, which require chip developers to alter their designs. Given the costs and peculiarities of High-NA EUV litho systems, all chipmakers have different strategies for their adoption. Intel clearly wants to be the first adopter, whereas TSMC is a little more cautious.

Rapidus plans to install as many as 10 EUV lithography tools into its upcoming fabs in Japan, reports TrendForce, citing Nikkan Kogyo Shimbun. The tools will be used for mass production of chips on 2nm-class process technology starting in 2027. 

Rapidus plans to install 10 EUV lithography machines in its IIM-1 and IIM-2 semiconductor production facilities, according to Atsuyoshi Koike, the chief executive, who spoke with Nikkan. In December 2024, the first EUV lithography equipment for Japan arrived at New Chitose Airport, marking a key milestone in Rapidus's development and the revival of the Japanese semiconductor industry. 

Atsuyoshi Koike did not disclose the schedule at which the company will install its EUV tools, but it is logical to expect some leading-edge lithography systems to be installed at IIM-1 over the next couple of years, with the remaining set to be installed at IIM-2 later. 

The company also did not disclose which machines it is going to use, but since it is installing ASML's Twinscan NXE:3800E, it is likely that it will use these tools at IIM-1. One Twinscan NXE:3800E scanner can process up to 220 wafers per hour at a dose of 30mj/cm^2, or 5280 wafers per 24 hours, assuming that it is available all the time, which does not usually happen as tools require service.

It is hard to estimate the actual production capacity of Rapidus's IIM-2 based on the number of installed tools. At 3nm, the total number of mask layers can land in the 100 – 120+ range, depending on the complexity of the design. Of them, 20 – 25 are EUV layers (though this varies by foundry and design). Assuming that Rapidus's 2nm-class process technology will feature 20 EUV layers, then with five EUV tools (with decent uptime) the foundry can support approximately 17,000 - 20,000 wafers per month at IIM-1. Of course, this is a very rough estimate, and there are many moving parts here, so it should be taken with a grain of salt. 

The company aims to start 2nm trial production at a pilot line IIM-1 in April 2025. By June 2025, Rapidus reportedly aims to deliver 2nm chip samples to Broadcom, a major contract developer of AI and communication processors that works with companies like Google and Meta. Rapidus aims to start mass production of 2nm products at IIM-1 in 2027. The IIM-2 facility will come online later.

Fujifilm Holdings, a major maker of raw materials for semiconductor production and one of a few suppliers of ultra-pure photoresists for EUV lithography, plans to invest ¥100 billion ($640.5 million) by March 2027 to increase its semiconductor materials production globally, according to Nikkei. The company reportedly aims to expand capacities in the U.S., Japan, and South Korea as major chipmakers are building up new advanced fabs in the said countries. Yet, Fujifilm has yet to confirm the plan.

The outlined spending will double its investment from the last three years, aiming to meet growing demand driven by new fabs in the U.S. (Intel, TSMC), Japan (Kioxia, Micron, TSMC), and South Korea (Samsung, SK hynix) as well as production of ultra-high-end processors for AI and HPC sectors. In addition, the company also plans to tap the Indian market as India is a country that seeks to make microelectronics as well.

Fujifilm ranks fifth globally in photosensitive semiconductor materials and it supplies major chipmakers like TSMC and Samsung. It is also one of five makers of ultra-pure EUV photoresists along with JSR, DuPont, Tokyo Ohka Kogyo (TOK), and Shin-Etsu Chemical. As EUV operates at an extremely short wavelength of 13.5nm, photoresists must meet stringent requirements in terms of sensitivity, resolution, line-edge roughness, and compatibility with EUV photomask materials.

Onshoring of advanced chip production has a drastic effect on the whole semiconductor industry as not only actual chipmakers like Intel and TSMC are establishing new manufacturing facilities, investing tens of billions of dollars, but their ecosystem partners follow, which is the case with Fujifilm.

Fujifilm plans to enhance production near key clients to strengthen partnerships and better serve the rapidly growing semiconductor market. In Japan, Fujifilm is constructing a new facility in Shizuoka for ¥13 billion ($83.27 million). In South Korea, a facility in Pyeongtaek will receive new equipment that is going online by autumn. Additionally, in Cheonan, a plant for producing abrasive agents will boost output capacity by 30% once mass production begins by spring 2027.

The company is also exploring opportunities in India, where it may partner with local firms or establish a joint venture to produce chip materials. Depending on client activity, Fujifilm could build its own facilities there, after fiscal 2027.

Fujifilm identifies chipmaking materials as a key area for growth and plans to double its sales in this sector, targeting ¥500 billion ($3.2 billion) by fiscal 2030, up from the fiscal 2024 level. The expansion aligns with Japan's dominant position in this critical supply chain as currently the country controls half of the market for essential semiconductor materials.

Research by Fuji Keizai cited by Nikkei predicts the global chipmaking materials market will expand by 35%, reaching $58.3 billion by 2029 compared to 2023 levels.

The Lawrence Livermore National Laboratory is working on a petawatt-class thulium laser that is said to be 10 times more efficient than the CO2 lasers used in EUV tools and could replace CO2 lasers in lithography systems many years down the road. 

The LLNL-led initiative will evaluate the Big Aperture Thulium (BAT) laser technology to enhance EUV source efficiency by approximately tenfold compared to the current industry-standard CO2 lasers. This advancement could pave the way for a new generation of 'beyond EUV' lithography systems that produce chips quicker and with less power. Of course, implementing BAT technologies into semiconductor production will require significant infrastructure changes, so it remains to be seen how long it will take to come to fruition; the current EUV systems were developed over the course of decades. 

One of the peculiarities of extreme ultraviolet lithography is the extreme power consumption of the current-gen Low-NA EUV and next-gen High-NA EUV litho systems: the tools consume 1,170 and 1,400 kilowatts, respectively. EUV lithography tools consume such vast amounts of power because they rely on high-energy laser pulses to evaporate tiny tin droplets (at 500,000ºC) to form a plasma that emits 13.5-nanometer light. Generating these pulses at tens of thousands per second demands massive laser infrastructure and cooling systems. Generating and manipulating tin droplets also requires power. 

In addition, vacuum requirements to prevent the absorption of EUV light by air add to the overall energy use. Finally, as advanced mirrors in EUV tools reflect only a fraction of EUV light, lasers must become more powerful to increase production capacity. 

Lawrence Livermore's team of researchers is testing whether technologies behind the BAT laser — built around thulium-doped yttrium lithium fluoride and capable of petawatt-class output — can raise the energy efficiency of current EUV tools. Unlike CO2 lasers that operate at a wavelength of about 10 microns, this system operates at around 2 microns, according to LLNL. This theoretically enables higher plasma-to-EUV conversion efficiency when interacting with tin droplets. Also, diode-pumped solid-state technology used in BAT systems can offer better overall electrical efficiency and heat management compared to gas-based CO2 setups. 

Initially, the researchers aim to pair the compact, high-repetition-rate BAT laser (with different types of pulses) with systems that produce EUV light to test how a laser delivering joule-level pulses at a 2-micron wavelength interacts with tin drops.

“We have performed the theoretical plasma simulations and proof of concept laser demonstrations over the past five years that lay the foundations for this project,” said LLNL laser physicist Brendan Reagan. “Our work has already had quite an impact in the EUV lithography community, so now we’re excited to take this next step.”

The power consumption of modern EUV tools and fabs has led industry analyst firm TechInsights to raise the alarm over the power consumption of semiconductor fabs. These fabs are projected to consume 54,000 gigawatts (GW) of power per year by 2030 — more than Singapore or Greece consume per annum. If next-gen Hyper-NA EUV lithography comes to market, the power consumption may be even higher. As such, we can expect the industry to continue to search for more power-efficient technologies to power future EUV machines. 

Although advancements that SMIC and Huawei have made in the semiconductor sector in recent years are pretty impressive, the companies are 10 to 15 years behind industry giants like Intel, TSMC, and Samsung, said Christophe Fouquet, chief executive of toolmaker ASML. It's well known that even with the best-in-class DUV tools, Chinese fab SMIC will be unable to match TSMC's process technologies cost-effectively. This is because Chinese companies cannot access leading-edge EUV lithography tools.

"By banning the export of EUV, China will lag 10 to 15 years behind the West," said Christophe Fouquet in an interview with NRC (machine translated). "That really has an effect."

ASML has never shipped its EUV tools to China due to the Wassenaar Arrangement, despite SMIC's reported order for one EUV machine. The details remain unclear, but ASML did not deliver the machine to the Chinese foundry due to US sanctions. However, ASML kept shipping advanced DUV lithography tools, such as the Twinscan NXT:2000i, which are capable of producing chips on 5nm and 7nm-class process technologies.

As a result, SMIC has been producing chips for Huawei using its 1st-generation and 2nd-generation 7nm-class process technology for years now. This has certainly helped the Chinese high-tech giants weather U.S. government sanctions.

Having understood that EUV tools are not coming to China, Huawei and its partners have explored extreme ultraviolet lithography themselves with the aim of building their own lithography chipmaking tools and ecosystem, which will take 10 – 15 years at best. For reference, it has taken over 20 years for ASML and its partners from foundational work to complete commercial machines to build the EUV ecosystem. Keeping in mind that many of the technologies developed in the early/mid-1990s are openly known, Chinese companies will not have to develop everything from scratch. However, by the time the Chinese semiconductor industry develops Low-NA EUV tools, the Western chip industry will have High-NA EUV lithography and even Hyper-NA EUV equipment.

However, the main concern is not that Chinese companies may develop their own EUV lithography tools some 15 years down the road, but that they might copy ASML's mainstream DUV machines (such as Twinscan NXT:2000i) over the next several years.

The American government is pressuring ASML to halt the maintenance and repair of its advanced DUV systems in China, which will make it consistent with existing sanctions against China's semiconductor sector. However, the Dutch government has not agreed to this demand so far. ASML aims to retain control over its machines in China to prevent the risk of sensitive information leaking, which could happen if Chinese companies take over maintenance to keep their chip factories operational.

For now, Chinese companies are among the main customers of ASML, and the company earns billions selling DUV litho tools to SMIC, Hua Hong, and YMTC. What happens if (or rather when) Chinese makers of lithography equipment build their own DUV lithography systems (or just copy those developed by ASML) is unknown. On the one hand, they could reduce purchases from ASML, but on the other hand, they could start selling these tools outside of China, essentially competing with ASML. While it is unlikely that they will build a Twinscan NXT:2000i-like machine any time soon, replicating something less advanced could be much easier.

EDIT 12/23/2024 11am PT: Corrected the article to reflect that all products available in the employee shop are only sold to ASML employees, a long-standing practice.

Corrected article:

ASML is canceling orders for the $230 Lego kit version of its $380 million High-NA EUV machine coming from non-ASML employees, as @jonmasters discovered. This limited-edition Twinscan EXE:5000 Lego Kit commemorates the world’s first High-NA EUV machine designed to build the next generation of semiconductors, and it has become a sought-after collector's item that has apparently been inadvertently sold to numerous non-ASML employees over the last few months. 

Despite its high price, there seems to be high demand for this kit as ASML has limited orders to just one per employee. Unfortunately, it appears that more people than anticipated are buying this kit due to non-ASML employees purchasing the kit. The company is now enforcing the policy of only selling to employees, as existing purchases for the Twinscan EXE:5000 Lego Set by non-employees have apparently been identified and canceled. The company also added a note at the bottom of the product description that a valid ASML email is required to purchase the Lego set. This limitation also extends to the cheaper Twinscan Lego Set, which would set you back by around $166. It is also only available to ASML employees.

The Twinscan EXE:500 Lego set measures over a foot wide, about two and a half inches deep, and is almost four inches tall. Although it’s not that massive compared to other Lego sets that are as tall as an adult, it still has 851 pieces of original Lego parts. The more affordable Twinscan Lego set is even more extensive, measuring around 14 x 10 x 3.5 inches; however, it only has 600 pieces. But whichever model you choose (if you were an ASML employee), it should be enough for one afternoon of building fun, making it an excellent gift for yourself or that tech enthusiast.

The company's employees can also purchase ASML-themed Christmas gear, such as a set of three holiday ornaments featuring a miniature NXT machine, a cleanroom employee, and an ASML logo made from hand-crafted glass. It’s also much cheaper at just $29, so they don’t need to break the bank to celebrate the holidays with a chip-making machine.

Aside from the Christmas ornaments and limited-edition Lego sets, the ASML Store has several other ASML-themed items, like shirts, coffee cups, tumblers, lapel pins, socks, and more. However, these items are also only available to ASML employees. 

Rapidus has successfully begun installing ASML's Twinscan NXE:3800E EUV lithography system at its Innovative Integration for Manufacturing (IIM-1) facility in Chitose, Hokkaido, marking a significant milestone for Japan’s semiconductor industry. In 2025, the tool will be used to make prototype chips using a 2nm process technology and then for commercial semiconductor production starting in 2027.

ASML's Twinscan NXE:3800E lithography system is currently the company's most advanced lithography tool explicitly designed to produce chips at 2nm-class process technologies and beyond. The machine features ASML's latest high-power light source, a new wafer handler, faster wafer stages, and other components needed to support increased throughput, enabling the performance of over 220 wafers per hour at a 30 mJ/cm² dose.

The system — which weighs 71 tonnes and stands 3.4 meters tall — must be assembled in four stages. Rapidus expects to conclude installation by the end of the month (according to Nikkei) and set a new milestone for Japan's semiconductor industry, as this is the country's first EUV machine intended to produce logic chips using EUV-based process technologies.

Rapidus's IIM-1 plant is set to begin pilot operations in April 2025. The pilot line will implement a single-wafer processing system across all production stages, which will help the company's engineers and fab workers better understand how each tool works and adjust the manufacturing process accordingly. Thus, lower defect densities (and, therefore, better yields on test wafers) will be achieved faster.

Rapidus has partnered with IBM to develop its 2nm-class process technology for logic chips that rely on gate-all-around transistors. The company hopes to start mass production of 2nm semiconductors by 2027, putting it 1.5–2 years behind Intel and TSMC, which are set to begin commercial production of 1.6nm and 2nm-class chips in the second half of 2025. While this may not sound like a breakthrough for a chip contract manufacturer, it will be a major breakthrough for the Japanese semiconductor industry.

Rapidus also plans to offer its customers a "secret sauce" for advanced chip packaging services. First, Rapidus will package chips in the same fab where it will produce them. Second, Rapidus aims to automate chip packaging, thus shrinking cycle times. In contrast to the highly automated front-end lithography process, back-end production remains labor-intensive. While this reliance on manual work allows for some adaptability, it also limits production speed.

Existing advanced packaging facilities still have not fully implemented automation either. By introducing automation to this stage, Rapidus aims to significantly enhance the efficiency and pace of chip packaging, which it hopes will be a critical improvement as advanced packaging technologies become increasingly intricate. Additionally, the company is working closely with several Japanese suppliers to procure materials needed for back-end operations, which will boost the local semiconductor industry.

Rapidus's Innovative Integration for Manufacturing (IIM-1) facility will cost around $32 billion when fully built and equipped, but the company must still secure funding. Japanese banks are reluctant to provide money to a company with no track record.

Edit 12/20/2024 4:20am PT: Corrected title to reference correct year. 

Russia has unveiled a roadmap to develop its own lithography machines, aiming to create less costly and complex equipment than ASML's systems, according to CNews. These machines will use lasers operating at a wavelength of 11.2 nanometers instead of the standard 13.5 nm used by ASML. This wavelength will be incompatible with existing EUV infrastructure and require Russia to develop its own lithography ecosystem, which will likely take years, if not a decade or more.

EUV tools with a 11.2nm wavelength

The Russian semiconductor initiative is led by Nikolay Chkhalo from the Russian Academy of Sciences’ Institute of Microstructure Physics. The plan is to build EUV machines that offer competitive performance while lowering manufacturing and operational expenses compared to ASML's EUV tools. 

Unlike ASML's EUV lithography systems, Russian EUV scanners will use a xenon-based laser source with an 11.2 nm wavelength instead of ASML’s tin-based systems. Chkhalo says the 11.2nm wavelength offers a 20% improvement in resolution, allowing for finer detail while simplifying the design and reducing the costs of optical components. This adjustment significantly decreases contamination of optical elements, extending the lifespan of critical parts like collectors and protective pellicles. The design also allows for silicon-based photoresists, which are expected to perform better at the shorter wavelength. 

The Russian lithography machines will be less powerful than ASML's, with a throughput approximately 2.7 times lower due to using a 3.6 kW light source. However, this performance is deemed sufficient for small-scale production. 

Although 11.2 nm still falls within the extreme ultraviolet spectrum, this shift is not a minor adjustment. It means that all optical elements — such as mirrors, coatings, mask designs, and resists — must be specifically designed and optimized for the new wavelength. The laser source, resist chemistry, contamination control, and other supporting technologies would also need re-engineering to work efficiently at 11.2 nm. 

As a result, tools based on 11.2nm will not be directly compatible with the existing EUV infrastructure and ecosystem built around 13.5 nm. In fact, even electronic design automation tools will have to be updated for EUV tools with 11.2nm lasers. Although existing EDA tools can still handle the fundamental steps, such as logic synthesis, placement, and routing, the lithography-aware steps like mask data preparation, optical proximity correction (OPC), and resolution enhancement techniques (RET) would need to be recalibrated or updated with new process models tailored for 11.2 nm. 

Three stages.

Development will proceed in three stages. The first stage will focus on foundational research, identifying key technologies, and testing initial components. The second stage will involve creating a prototype capable of processing sixty 200-mm wafers per hour and integrating it into domestic chip production lines. The third stage aims to deliver a factory-ready system capable of processing sixty 300-mm wafers per hour. It is unclear which process technologies the new lithography tools will support. Also, the roadmap does not specify the timelines for completing these stages. 

Keeping in mind that usage of lasers with a 11.2nm wavelength requires development of an all-new ecosystem that does not exist today, it may well take a decade or more to design these EUV lithography systems.

One of the world's leading chip-making equipment manufacturers has released a new Lego set. Veldhoven, Netherlands-based ASML has added the TWINSCAN EXE:5000 Lego set to its growing portfolio of gifts. At $227.95 this "masterpiece in technology" might sound rather expensive, but please remember that real ASML lithography systems cost sums approaching $400 million. Also, even if you are drooling over this gift, you would probably admit it is a niche item.

Regular readers of Tom's Hardware will be well aware of ASML's pivotal position in the world of semiconductor manufacturing. The company supplies chipmaking icons like Intel, TSMC, and Samsung, and its tools are essential for the most advanced lithography.

The ASML TWINSCAN EXE:5000 is one of the leading extreme ultraviolet (EUV) lithography tools available in 2024. ASML tested a machine in-house earlier this year and boasted about its projection optics that feature a 0.55 numerical aperture (High-NA). Intel is also working with this machine for R&D on its Intel 18A (1.8nm-class) process technology.

OK, but what about the Lego set? It is also a marvel of human creativity, but will only output to your dreams. The ASML TWINSCAN EXE:5000 Lego set features 851 Lego bricks/parts, so will be a bit of an engineering feat for a home tech enthusiast to complete. When you have laid your final brick the result will be a 13.86 x 3.9 x 2.52-inches model. That's quite small considering the price.

ASML seems to be pretty confident that the demand for the new TWINSCAN EXE:5000 Lego set will be strong. Orders are limited to one set per customer, with warnings of canceled orders for those asking for more. However, this "iconic" set isn't the first or only ASML Lego product released. The firm previously launched the Lego ASML Skyline and the Lego TWINSCAN NXE:3400C sets. One alternative Lego set is still available for sale here, at $166.70.

Also, if you are in the mood for Christmas, a set of three unique, hand-crafted glass tree ornaments is available for $29. These consist of a glass ASML logo, a cleanroom employee, and an NXT machine (pictured below).

The worlds of PC tech and Lego often intermingle. Looking back through the Tom's Hardware archive we see we reported on an RTX 4080 Super-powered Lego Fortnite PC back in August, and last year a life-size Lego Intel Arc graphics card project caught our eye.

Nikkei Asia's sources say that Taiwan Semiconductor Manufacturing Corporation (TSMC), the largest semiconductor fab in the world, is set to receive the ASML’s most advanced chipmaking machine this year. The high numerical aperture extreme ultraviolet (High NA EUV) machine, which is said to cost more than $350 million apiece, will allow chip makers to print features smaller than before. Nikkei Asia reports that TSMC is considering using its High NA EUV lithography machines to make processors that use angstrom 10 (A10) technology, about two generations ahead of the 2nm node that it plans to put into production by the end of next year. This means that we likely won’t see this machine used for mass production until after 2030.

Although TSMC is the biggest semiconductor manufacturer globally, it’s not the first company to get ASML’s latest, most advanced machine. Intel was the first to adopt the machines, having received the very first High NA EUV machine in the first quarter of 2024 at its Oregon facility. It also received a second machine during the second quarter of this year — a testament to the company's focus on regaining its technological edge over the competition, especially in AI chip manufacturing. Sources also say that Samsung will install its own High NA EUV machine sometime between today and the 1Q25.

This news of installations of ASML’s most advanced machines doesn’t mean that we’re getting sub-nm nodes next year, however. Instead, companies are investing hundreds of millions of dollars to develop the technologies needed to harness its ability to pack in transistors in record-breaking densities. That’s because High NA EUV has a smaller imaging field versus current NA EUV machines, so chip manufacturers need to adjust their designs based on that. Furthermore, High NA EUV machines are significantly larger than current lithography machines, so these fabs must reorganize their production lines or build a new factory from the ground up to accommodate ASML’s most advanced offering.

At the moment, these three companies — Intel, Samsung, and TSMC — are the only ones that are known to be working on more advanced chips that will take advantage of ASML’s High NMA EUV lithography machine. This is especially true as Chinese firms have been blocked from accessing ASML’s products and services by America’s bans and sanctions. Nevertheless, the company says that it already has received 10 to 20 orders for these multimillion-dollar machines.

ASML has a practical monopoly on advanced EUV lithography machines. It’s the only one that has know-how and capability to manufacture these machines required for making the next generation of semiconductors. But even if ASML is based in the Netherlands — a known American ally — the U.S. is still investing EUV research so that it could bring its semiconductor supply chain home. While it will take years, if not decades, for this move to bear fruit, this should at least give chipmakers more options in the future, furthering technological advancements through healthy competition

The Biden White House is investing $825 million in Albany, New York, to build the flagship facility of the National Semiconductor Technology Center (NSTC). The NSTC is America’s premier research and development center; it aims to bolster innovations in semiconductor technology, develop a skilled workforce to support these new developments, and collaborate with the private sector and academe.

The U.S. Department of Commerce says that the site will focus on extreme ultraviolet (EUV) lithography — technology for manufacturing the most advanced nodes required for the next generation of chips and processors.

NSTC’s first facility, to be called CHIPS for America Extreme Ultraviolet (EUV) Accelerator, will take shape within the Albany NanoTech Complex—a high-tech site boasting over 1.65 million square feet of space—operated by the non-profit New York Center for Research, Economic Advancement, Technology, Engineering, and Science (NY CREATES). As the name suggests, this development is funded under the CHIPS and Science Act, which is America’s most significant investment in its semiconductor industry over the past 28 years combined.

“With this first proposed flagship facility, CHIPS for America is providing access to cutting-edge research and tools to the NSTC and its launch represents a key milestone in ensuring the United States remains a global leader in innovation and semiconductor research and development,” said Secretary of Commerce Gina Raimondo.

Raimondo states that “the research and development component of the CHIPS and Science Act is fundamental to our long-term national security and ensuring the U.S. remains the most technologically competitive place on earth. Thanks to President Biden and Vice President Harris, we are not just producing the world’s most advanced semiconductors; we are building a resilient ecosystem that will power everything from smartphones to advanced AI, safeguarding U.S. national security and keeping America competitive for decades to come.”

EUV technology enables companies to push the boundaries of Moore’s Law, which states that the number of transistors in an integrated chip doubles every year. As the latest processors have already hit over 100 billion transistors on a single chip, we need further advancements in EUV lithography to allow us to pack in even more transistors in the same amount of space.

The investment comes as the U.S. aims to bolster its semiconductor supply chain to safeguard its chip sources while also fostering innovation in the semiconductor industry. Currently, the Netherlands-based ASML is the only company in the world that produces the EUV machines needed to make the latest generation of chips. The new center aims to further research and development by giving researchers access to EUV technology to help reduce the costs and time to prototype new chip designs while also fostering a semiconductor workforce. 

Extreme ultraviolet (EUV) lithography is vital for modern process technologies and semiconductor manufacturing for years to come. However, at 1,400 kilowatts per EUV tool — enough to power a small city — EUV lithography systems have become a substantial consumer of power that impacts the environment. TechInsights believes that the power consumption of all fabs equipped with EUV tools will exceed 54,000 gigawatts (GW) of power per year by 2030, which is more than what many countries, like Singapore or Greece, consume per year.  

Current Low-NA EUV scanners require up to 1,170 kW, and next-gen High-NA tools are projected to need as much as 1,400 kW per unit (according to TechInsights). The number of these machines installed at fabs operated by Intel, Micron, Samsung, SK hynix, and, of course, TSMC, increases every year. 

TechInsights believes that by 2030, the number of fabs with EUV scanners will increase from 31 today to 59, and the number of tools in operation will approximately double. As a result, all the installed EUV systems will consume 6,100 GW/year of power, which suggests that hundreds of the machines will be operational by then.  

6,100 GW/year — power consumption comparable to Luxemburg's — is not a lot. However, each advanced chip takes over 4,000 steps to make, and there are hundreds of tools in a fab. EUV equipment accounts for approximately 11% of the total electricity use in a fab, with other tools, HVAC, facility systems, and cooling equipment making up the rest. As a result, the power consumption of all fabs equipped with low-NA and high-NA EUV tools is estimated to increase to 54,000 GW/year. 

To put the number into context, 54,000 gigawatts a year of power is around five times more than Meta's data centers consumed in 2023. It is also more than Singapore, Greece, or Romania consume annually and more than 19 times the power consumed by the Las Vegas Strip per year. However, while this is a substantial amount of power, it is only 0.21% of the global power consumption in 2021 (25,343,000 GW/year), a rather small share. 

It is fairly easy to deduce that if 59 leading-edge semiconductor production facilities with EUV tools consume 54,000 GW/year, each one will consume 915 GW/year, comparable to the power consumption of the most advanced data centers. 

As the number of EUV-equipped fabs is projected to almost double by 2030 and power consumption will more than double as well, power infrastructure will face significant challenges as even today, companies like AWS, Google, Meta, and Microsoft are struggling to find places where to build their megawatt and gigawatt-scale datacenters as power grids must be able to handle them.  

Nowadays, chipmakers like Intel tend to consume only sustainable green energy, but their power consumption is limited for now. With the rising power demand for AI data centers, AWS, Microsoft, and Oracle plan to use nuclear power plants to feed their data centers. Perhaps chipmakers will have to consider using nuclear power in a few years as well. However, it remains to be seen whether power grids will be ready to power AI data centers, advanced fabs, households, and other industries in just six years. 

"To ensure a sustainable future, the industry will need to invest in energy-efficient technologies, explore renewable energy sources, and collaborate with policymakers to address the challenges of power infrastructure," TechInsights concludes. "By doing so, they will be able to extend the power of semiconductors while minimizing their environmental impact."

Corning has introduced its new ultra-low expansion (ULE) material that is designed to withstand ever increasing power of upcoming Low-NA (Numerical Aperture) and High-NA EUV lithography systems. The new Extreme ULE material is projected to be used for next-generation photomasks and lithography mirrors that will be used with next-generation fab tools. 

A key feature of the Extreme ULE material is its extremely low thermal expansion, which provides exceptional consistency for photomask use. In addition, its superior flatness helps to minimize "photomask waviness", reducing unwanted variability in chip production. These properties enable the application of advanced pellicles and photoresists to boost yields and performance. 

As extreme ultraviolet lithography tools attain higher performance in terms of wafer per hour (WPH) processing, they adopt more powerful light sources, and the more powerful light sources expose photomask pellicles, photomasks, and ultimately resists and wafers to higher dosage of EUV radiation and heat.  

In an EUV tool, the plasma source that generates EUV light emits a lot of heat, but the heat is mostly confined to the source chamber, which is separated from the photomask. The light is carried by a set of lithography mirrors that are susceptible to heat. As for the photomask itself, it is made of multilayer reflective materials designed to reflect EUV light. While these layers are highly reflective, some absorption still occurs, leading to a slight heating of the mask. Considering how intricate modern circuits are, even a slight deformation or inconsistency could lead to yield-killing defects or performance variabilities. 

This is where Corning's ULE glass, a family of titania-silicate glass material with near-zero expansion characteristics comes, into play. The Extreme ULE is an evolution of the original ULE family that is meant to offer extreme thermal stability and a uniform glass material for next-generation High-NA EUV tools as well as future Low-NA EUV tools that adopt the same light sources. 

"As the demands of integrated chipmaking grow with the rise of artificial intelligence, glass innovation is more important than ever," said Claude Echahamian, Vice President & General Manager, Corning Advanced Optics. "Extreme ULE Glass will expand Corning's vital role in the ongoing pursuit of Moore's Law by helping enable higher-powered EUV manufacturing as well as higher yield." 

Corning will showcase Extreme ULE Glass at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference, held in Monterey, California, from September 30 to October 3, 2024.

ASML, the world's only maker of EUV lithography chipmaking tools, has never shipped an EUV tool to its primary Chinese customers due to the Wassenaar arrangement and the most recent export regulations, it doesn't mean that Chinese makers will never be able to build their own EUV chipmaking tools. This week, it turned out that Shanghai Microelectronics Equipment (SMEE) had applied for a patent covering an EUV lithography machine, reports the South China Morning Post.

The patent, which was submitted by SMEE in March 2023, focuses on 'extreme ultraviolet (EUV) radiation generators and lithography equipment.'  Based on the SCMP's description, SMEE is attempting to patent the key set of components of an EUV tool: a laser-produced plasma (LPP) EUV source. An LPP EUV source comprises a CO2 light source that is applied to tiny tin droplets around 30 microns in diameter in a special chamber to create ionized gas plasma at electron temperatures of several tens of electron volts, which is then collected with a special mirror coated with several layers of molybdenum and silicon to selectively reflect the of 13.5 nm EUV light. 

Shanghai Microelectronics Equipment (SMEE) is China's leading producer of lithography equipment. For now, the company supplies customers in China with its most advanced litho tool, the SSX600, which can be used to make chips on 90nm, 110nm, and 280nm process technologies. Last year, the company said it was on track to demonstrate a 28nm-capable system in 2023, though it is unclear whether it started mass production of this tool. 

EUV lithography is used to make chips on advanced process technologies, such as 7nm, 6nm, 5nm, 4nm, and 3nm. Currently, SMIC produces processors on its 2nd Generation 7nm-class process technologies using immersion DUV lithography and multi-patterning, which is inefficient from a production cycle point of view and poses many risks in terms of yields. However, SMIC and its partner Huawei have no choice but to keep using DUV lithography with multi-patterning for 7nm and then for 5nm and maybe even 3nm-class production nodes. 

SMEE's patent filing represents a significant step forward in China's efforts to develop its own EUV lithography tools. Though it is hard to say when the company will build at least one production EUV system that can be used to make chips in high volumes, it is evident that it is making strides towards EUV litho tools. 

Shanghai Microelectronics Equipment is not the only company in China that has filed a patent concerning EUV lithography. Huawei filed an EUV system-related patent in China back in 2022. These patents mark an important milestone in China's push to develop independent semiconductor manufacturing capabilities. If SMEE ever produces advanced DUV and EUV tools, it will help China reduce its reliance on foreign firms like ASML and strengthen its position in the global semiconductor market. 

It should be kept in mind that in many cases, patents are filed well before commercialization. An EUV lithography tool is an ultra-complex machine that uses dozens of high-tech breakthroughs made over three decades. Could SMEE make the same breakthroughs in just several years? Time will tell.

TSMC was ahead of Intel with the adoption of EUV lithography tools for mass production, but when it comes to High-NA EUV systems, it looks like the company is behind its American rival. While Intel is already using its ASML High-NA EUV machine for R&D purposes, intending to use High-NA EUV lithography in the next two or three years, TSMC will only begin installation of its first High-NA EUV tool for R&D later this month, according to reports by DigiTimes and United Daily News. 

TSMC's first ASML Twinscan EXE:5000, a High-NA lithography system designed specifically for R&D purposes, is set to be installed at TSMC's global research and development center in Hsinchu, Taiwan. The world's No. 1 contract chipmaker will begin to receive components of the machine later this month. It is going to take TSMC several months to assemble and calibrate the tool before it will be able to test the next-generation semiconductor production technology at its R&D facility in Taiwan. 

TSMC's upcoming process technologies — N2 (2nm-class) and A16 (1.6nm-class) — will rely solely on traditional EUV equipment with optics featuring a 0.33 numerical aperture (Low-NA). The earliest opportunity for TSMC to insert High-NA EUV tools with optics featuring a 0.55 NA will be with its A14 (1.4nm-class) process technology sometime in 2028 or likely later, though the company yet has to confirm this. However, since High-NA EUV lithography tools reduce the reticle size by half, their use will introduce additional challenges for both chip designers and manufacturers, which is perhaps why TSMC is not exactly accelerating usage of High-NA EUV tools. 

Another reason why TSMC is not jumping to High-NA EUV tools is because of their price. As the company's Kevin Zhang, who is in charge of the development of new process technologies, pointed out earlier this year: he liked the performance of High-NA tools, but did not like the price. 

Each High-NA litho tool costs around $400 million, but TSMC's president, C.C. Wei, personally negotiated a near 20% discount. This price reduction was achieved by combining the purchase of the new machine with the purchase of other ASML gear. Keeping in mind that TSMC is already the leading user of EUV lithography systems, holding an estimated 65% of the global EUV production capacity, ASML is certainly inclined to make deals with the foundry as it is one of its largest customers already.

Japan's National Institute of Advanced Industrial Science and Technology (AIST) is partnering with Intel to establish a new research and development center focused on advanced chip production, reports Nikkei citing sources with knowledge of the matter. This facility is expected to be operational within three to five years and will focus on process technologies that use EUV lithography. 

The new R&D center will cost hundreds of millions of dollars (as each EUV litho machine costs around $200 million) and will provide an opportunity for various industry players in Japan to collaborate with AIST and Intel by jointly using EUV equipment for prototyping and testing. The move will enable chip designers in Japan to adopt the latest process technologies, such as those relying on EUV tools, which will ultimately make them more competitive with industry peers based elsewhere. 

Currently, many Japanese companies must rely on foreign research centers, such as Belgium's IMEC, to access EUV equipment for product development. By establishing a domestic facility, Japan aims to reduce this reliance on overseas resources, thereby speeding up the development process and improving the competitive standing of its semiconductor industry. 

Notably, Japanese companies like Lasertec and JSR are already global leaders in several areas of EUV technology. Lasertec dominates the market for EUV inspection equipment, while JSR excels in photoresists used in chip production. Through the new research center, Intel aims to strengthen its collaboration with these companies to solidify its own capabilities while also strengthening Japan's position in the global semiconductor supply chain.   

Another advantage that Intel gets by working closely with Japanese companies is to ensure that its existing rival TSMC (and upcoming rival Rapidus with a presence in Japan) can't secure key strategic advantages, such as customer relations or better tools and/or raw materials. 

Nikkei also believes that a joint R&D center between an American company and Japan’s AIST is strategically significant given the increasing tensions between the U.S. and China. The U.S. has imposed stricter export controls on EUV-related technologies to China, complicating the process of transferring research data back to Japan. A domestic EUV facility will help Japan circumvent these challenges, providing greater security and efficiency in semiconductor development.

As with process technologies used to make logic chips, DRAM ICs need the usage of EUV lithography as transistors get smaller. Nowadays, Samsung and SK hynix use EUV for a few layers, which is expensive. To make EUV considerably cheaper, DRAM makers will have to adopt three-dimensional transistors and new DRAM structures, said a researcher from SK hynix at an industry conference, reports The Elec.

DRAM makers constantly strive to make their memory cells as small as possible and make their ICs as small as likely to be more competitive. To do so, they usually adopt new process technologies and, once or so, adopt new DRAM cell structures (once a decade or so). Today's DRAMs use 6F^2 (6F2) cell design, for example, which has been using FinFET three-dimensional transistors for over a decade; DRAM has been using plain transistors mainly because each new process node introduced new ways to shrink DRAM cells, which was all memory makers needed.

But preserving the 6F^2 cells and plain transistors with EUV does not seem as fruitful as once thought, according to SK hynix researcher Seo Jae Wook, who spoke at an industry event. He says that with vertical channel transistors (VCTs), or 3D DRAM, 'the process can be designed to reduce the cost of EUV processes by half.'

Meanwhile, The Elec says that SK hynix is gearing up to wed VCT and 4F^2 (4F2) cell design to make ultra-dense DRAMs (arguably, a risky but ambitious move). However, the memory maker has not confirmed such plans publicly. Therefore, when SK hynix starts to use EUV more extensively several years later, it will have experience both with VCTs (e.g., FinFET or even gate-all-around transistors) and with 4F^2 cell structures. The latter promises to reduce DRAM density by 30% compared to 6F^2 at the same node.

Fab tool maker Tokyo Electron anticipates that DRAMs using vertical channel transistors (VCTs) and a 4F^2 cell design will begin to appear around 2027 to 2028. The company also expects that to produce these VCT-based DRAMs, memory manufacturers will need to adopt new materials for capacitors and bitlines.

SK hynix and Samsung reportedly aim to apply 4F^2 cell design with their sub-10nm process technologies, though details are scarce. Samsung's first-generation sub-10nm DRAM fabrication process is still two generations away. Currently, Samsung's most advanced DRAM production node is its 5th Generation 10nm-class (12nm) technology, which it began to use in mid-2023. According to a slide leaked earlier this year, Samsung plans to develop two more 10nm-class fabrication processes before introducing the first-generation sub-10nm node, which is expected to debut in the decade's second half.

In addition to using EUV, 4F^2 cell design, and VCT transistors, Samsung plans to implement stacked DRAM process technology in the early 2030s, which will further boost the density of its memory devices over the next decade.

Samsung is set to start installing its first EUV lithography tool with a 0.55 numerical aperture (High-NA) in Q4 2024 – Q1 2025, reports Seoul Economic Daily, citing its sources. The device will be used primarily for research and development purposes as the company works on its next-generation process technologies that require resolutions enabled by High-NA EUV tools. Samsung also works on a High-NA ecosystem with Lasertec, JSR, Tokyo Electron, and Synopsys.

Samsung's first ASML Twinscan EXE:5000 High-NA lithography system will be installed at the company's Hwaseong campus, where it will develop its next-generation fabrication technologies for logic and DRAM. The unit is projected to be operational by mid-2025. As a result, Samsung will have its first High-NA EUV tool operational about a year later than Intel, but it will still be ahead of its rivals TSMC and SK hynix. When Samsung adopts High-NA EUV for mass production, it remains to be seen, but it is not expected until well into the decade's second half.

Samsung plans to develop a robust ecosystem around high-NA EUV technology. In addition to acquiring the high-NA EUV litho equipment, Samsung is collaborating with Japan's Lasertec to develop inspection equipment specifically for high-NA photomasks. According to DigiTimes, Samsung has reportedly purchased Lasertec's high-NA EUV mask inspection tool, the Actis A300.

"Using [High-NA EUV-specific tool] to inspect semiconductor masks has improved the contrast ratio by over 30% compared to conventional [EUV-specific tool]," said Dr. Min Cheol-ki from Samsung Electronics' Semiconductor Research Institute at the 2024 Lithography + Patterning Symposium.

According to DigiTimes, Samsung is also collaborating with JSR, a maker of photoresists, and Tokyo Electron, a maker of etching machines, to prepare for commercial implementation of High-NA EUV tools by 2027. Samsung is also working with Synopsys to shift from traditional circuit designs to curvilinear patterns on photomasks. This change is expected to improve the precision of circuits imprinted on wafers, which is critical for further refinements of process technologies.

ASML's High-NA EUV Twinscan EXE tool is set to achieve an 8nm resolution, substantially improving the current Low-NA EUV systems that max out at 13nm with a single exposure. This advancement will make transistors about 1.7 times smaller, nearly three times the transistor density. While Low-NA systems can also reach this level of resolution and density, they require the costly and complex double patterning process. The shift to High-NA EUV technology is expected to eliminate the need for double patterning, simplify production, potentially improve yields, and reduce costs.

Achieving these 8nm critical dimensions is crucial for producing chips with sub-3nm process technologies. Yet, at 2nm-class nodes, virtually all chipmakers will be using double patterning. Intel is also adopting pattern-shaping tools for its 20A node. The American chip giant only plans to use High-NA EUV with its 14A node.

Meanwhile, the leap to high-NA brings its own set of challenges. High-NA EUV tools are more expensive ($380 million—$400 million) and have a halved imaging field, which will require significant changes in chip design. Additionally, the larger size of high-NA EUV systems compared to low-NA systems means chipmakers will need to rethink their fab layouts to accommodate these new machines.

Professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has proposed an all-new and greatly simplified EUV lithography tool that is cheaper than those developed and made by ASML. If the device hits mass production, it could reshape the chipmaking equipment industry, if not the whole semiconductor industry.

The new system uses only two mirrors in its optical projection setup, a significant departure from the conventional six-mirror configuration. The challenge of such an optical system is that it involves aligning these mirrors in a straight line, which ensures that the system maintains high optical performance without the usual distortions associated with EUV light. The new optical path allows more than 10% of the initial EUV energy to reach the wafer, compared to about 1% in standard setups, an improvement which is a major breakthrough.  

Professor Shintake's team solved two major challenges in EUV lithography: preventing optical aberrations and ensuring efficient light transfer. OIST's 'dual-line field' method illuminates the photomask without interfering with the optical path, which minimizes distortions and enhances image precision on the silicon wafer.

One of the key advantages of this minimalist design is that it enhances reliability and reduces maintenance complexities. Another advantage of this EUV lithography tool design is a drastic reduction of its power consumption. Thanks to the optimized optical path, the system operates with an EUV light source of just 20W, leading to a total power consumption of less than 100kW. In contrast, traditional EUV lithography systems often require over 1MW of power. Because of lower power consumption, the new litho system does not require a sophisticated and expensive cooling system.

The performance of this new system has been rigorously verified using optical simulation software, confirming its capability for producing advanced semiconductors. The technology's potential has led to a patent filing by OIST, indicating readiness for commercial deployment.

OIST is committed to advancing its EUV tool design further, aiming to bring it to practical application. The institute sees this innovation as a vital step toward solving global challenges, such as the costs of chip production and power consumption of semiconductor fabs, which affect the environment.

The economic implications of this invention are promising. The global EUV lithography market is expected to grow from $8.9 billion in 2024 to $17.4 billion by 2030. With this simplified design of EUV tools, the industry could adopt more EUV systems in the coming years. However, it is unclear how close OIST is to commercialization of its tool.