Nvidia and SK hynix have inked a multi-year collaboration agreement under which the companies will co-develop next-generation memory technologies for Nvidia's upcoming platforms, and SK hynix will supply them to Nvidia. The deal is designed to ensure that Nvidia will get the memory it needs from a prominent supplier and will guarantee that SK hynix will be able to sell its output in a predictable manner.

The key part of the agreement is indeed the co-development of advanced memory products designed for Nvidia's future platforms. Currently, Nvidia uses HBM, LPDDR5X, DDR5, and 3D NAND memory in various systems, so going forward, SK hynix will develop its new memory with Nvidia in mind. The joint press release says nothing about customization of memory for Nvidia, and while we cannot exclude such a possibility, it looks like the companies will continue to co-develop industry-standard solutions, but will ensure that they are compatible with Nvidia's processors.

In addition, the agreement is intended to address the increasingly long lead times and massive capital expenditures required for the production of advanced types of memory. The two companies will coordinate roadmaps over multiple years. Nvidia will gain greater visibility into future memory availability, while SK hynix secures a guaranteed role in Nvidia's next-generation platforms (i.e., guaranteed demand).

The initial part of the cooperation covers memory destined for NVIDIA Vera Rubin AI systems (HBM4, LPDDR5X, 3D NAND), standalone Vera processors (LPDDR5X), RTX Spark-powered personal computers (LPDDR5X, 3D NAND), and Jetson Thor robotic computing systems (LPDDR5X, 3D NAND).

The deal also extends to semiconductor research and design. SK hynix is deploying Nvidia's CUDA-X libraries to speed up complex chip development workloads, such as technology computer-aided design (TCAD) and computational lithography (CuLitho). In addition, the memory maker is adopting Nvidia PhysicsNeMo to accelerate proprietary simulation software as well as AI-driven physics models used during semiconductor development. In addition, the companies see an opportunity to expand these capabilities into general electronic design automation (EDA) and simulation ecosystems and potentially create tighter relationships within the industry.

Last but not least, SK hynix is creating digital twins of its semiconductor fabs using Nvidia Omniverse and OpenUSD technologies. These virtual facilities enable engineers to model production lines, test changes, and optimize operations before making adjustments in real fabs. The company also plans to use Nvidia's cuOpt and Metropolis platforms to improve the movement of autonomous robots and other factory equipment. In the future, SK hynix aims to connect these digital twins with existing manufacturing software and AI systems and enable them to analyze fab data, automate routine tasks, and help make production decisions.

Samsung’s production numbers reportedly plummeted significantly during a one-day strike by the company’s labor union. According to Seoul Economic Daily, citing union officials, the company’s memory fab output fell by 18% while its contract chip foundry plunged by 58.1%. These numbers only affected the night shift after the April 23 strike, with the “Joint Struggle Headquarters” saying that it will conduct a larger 18-day labor action if company management fails to reach a deal with workers. The union estimates that the walkout, which would last for more than two weeks, will cost the company KRW 30 trillion, or over $20 billion. It also threatened to mobilize personnel assigned to the fabs’ “safety protection facilities.”

The disagreement between the union and management stems from the company’s refusal to allocate 15% of its operating profit as a bonus for its workers, amounting to around $27 billion (about KRW 40 trillion), and would net chip fab workers around $400,000 each. Aside from this, the union also demanded a 7% increase in pay and a removal of the 50% bonus cap. The management made a counteroffer of a 10% operating profit bonus, 6.2% wage increase, and preferential mortgage loans, among other benefits, but it seems that this wasn’t enough for the union.

The group pointed out that SK hynix, Samsung’s biggest domestic chip rival, has given its workers a performance bonus amounting to 10% of its annual operating profit and removed the cap on the amount. This means that their bonuses only equate to less than 30% of what the SK hynix workers get, even though Samsung is 60% larger in terms of market capitalization.

Initial estimates from the police suggested that over 30,000 people attended the strike, but the union said that about 40,000 of its members were present in yesterday's action. This is a massive number and is said to represent nearly a third of the company’s semiconductor fab workforce. A general strike lasting several days would cripple operations, reducing Samsung’s advantage of being the first company to mass-produce and deliver HBM4 memory to its customers. It could also potentially exacerbate the global memory chip shortage, resulting in longer delivery times and potentially higher prices for everyone.

Unless the two sides come to an agreement, the union will kick off the general strike on May 21. Supra-Company Union Samsung Electronics chapter head Choi Seung-ho also said that he has submitted a notice to the Seoul Yongsan Police Station that the group will hold a rally in front of the residence of Samsung Chairman Lee Jae-yong on the same day.

AMD and Samsung this week signed a rather unprecedented memorandum of understanding (MOU) that involves the strategic supply of memory for AMD's next-generation EPYC and Instinct MI455X products, as well as discussions of a potential foundry partnership. The MOU aims to ensure that AMD gets enough memory for its next-generation CPU and AI accelerator products throughout their life span, whereas Samsung will get a chance to serve as a foundry for a leading supplier of CPUs, AI GPUs, and other products.

Samsung has been the primary supplier of HBM3E for AMD's Instinct MI350X and MI355X AI accelerators, so it is not surprising that the core of the new agreement is Samsung’s role as a primary supplier of HBM4 memory for AMD's upcoming Instinct MI455X accelerator. As demand for all types of memory in general and HBM4 in particular exceeds supply, AMD must ensure that its next-generation MI455X accelerator (and possibly other Instinct MI400-series products) gets enough memory.

AMD's Instinct MI455X is projected to use 12 HBM4 12-Hi memory stacks for a total of 432 GB. Given such demands, it makes great sense for AMD to sign a strategic memory supply deal, though for now the two companies limited themselves to the MOU. Meanwhile, Samsung said that its HBM4 memory stacks are based on memory devices produced using its 1c (6^th Generation 10nm-class) process technology and use a base die made on a 4nm-class logic process, which enables them to achieve a rather unprecedented data transfer rate of 13 GT/s (thus provide up to 3.3 TB/s of bandwidth per stack), which is well above JEDEC's recommended 8 GT/s for HBM4. Yet, memory speeds supported by Instinct MI455X are considerably slower.

In addition to HBM4, the MOU between the two companies also includes DDR5 supply for AMD's 6^th Generation EPYC processors codenamed 'Venice,' as well as AMD's Helios rack-scale systems for AI data centers that rely on EPYC 'Venice' and Instinct MI455X. Again, the move aims to ensure a steady memory supply for next-generation AI systems running AMD's CPUs and AI accelerators to ensure a competitive position against Nvidia's Rubin-powered machines.

Perhaps the most intriguing part of the announcement is that the MOU can open the door for a potential foundry relationship, under which Samsung could manufacture future AMD products. While no specific nodes or chips were disclosed, this signals a willingness to expand cooperation into logic production alongside memory supply. To put this into context, AMD has been drifting away from GlobalFoundries since late 2018, and by now virtually all of its advanced products are made at TSMC. Shifting certain advanced production to Samsung is costly, though if this ensures that the South Korean company will provide much-needed memory to support AMD's AI efforts, then it looks like the developer of EPYC CPUs and Instinct accelerators may be willing to adopt a dual-source foundry strategy and make at least some of its products at Samsung Foundry.

"Samsung and AMD share a commitment to advancing AI computing, and this agreement reflects the growing scope of our collaboration," said Young Hyun Jun, Vice Chairman & CEO of Samsung Electronics. "From industry-leading HBM4 and next-generation memory architectures to cutting-edge foundry and advanced packaging, Samsung is uniquely positioned to deliver unrivaled turnkey capabilities that support AMD’s evolving AI roadmap."

Micron has announced that it has entered high-volume production of its HBM4 36GB 12-Hi memory, designed for Nvidia's Vera Rubin GPU platform. Making the announcement at GTC 2026, the memory giant simultaneously confirmed high-volume production of the industry's first PCIe 6.0 data center SSD and a new SOCAMM2 module, making it the first memory supplier to bring all three products to volume shipment for the Vera Rubin ecosystem at the same time.

The HBM4 36GB 12H stack runs at over 11 Gb/s pin speeds, delivering bandwidth greater than 2.8 TB/s. Compared to Micron's HBM3E at the same 36GB 12H configuration, that represents a 2.3 times bandwidth increase alongside more than 20% improvement in power efficiency, according to Micron's internal power calculator data.

"The next era of AI will be defined by tightly integrated platforms developed through joint engineering innovations across the ecosystem. Our close collaboration with NVIDIA ensures that compute and memory are designed to scale together from day one," said Sumit Sadana, executive vice president and chief business officer at Micron Technology, in a press release. "With HBM4 36GB 12H, alongside the industry's first SOCAMM2 and Gen6 SSD now in high-volume production, Micron's memory and storage form a core foundation that unlocks the full potential of next-generation AI."

Micron has also shipped samples of a 48GB 16H HBM4 stack to customers. The additional four die layers give the 16H configuration a 33% capacity increase per HBM placement over the 36GB 12H product, a milestone that points toward denser configurations in future AI accelerator generations.

Last month, the company announced that the 9650 SSD had entered mass production, marking the first time that a PCIe 6.0 SSD had entered that stage of production. The drive supports up to 28 GB/s sequential read throughput and 5.5 million random read IOPS, doubling PCIe 5.0 read performance at 100% higher performance per watt. Unsurprisingly, it targets AI inference, training, and agentic workloads in liquid-cooled environments and is optimized for Nvidia's BlueField-4 STX reference architecture.

Meanwhile, the 192GB SOCAMM2 module is designed for Nvidia Vera Rubin NVL72 systems and standalone Vera CPU platforms, with Micron's SOCAMM2 portfolio spanning 48GB to 256GB capacities. The Vera Rubin platform supports up to 2TB of memory and 1.2 TB/s of bandwidth per CPU using the module.

Intel Foundry this week released a promotional document aimed at detailing its leading-edge front-end and back-end offerings for AI and HPC applications, and showcased its 'AI chip test vehicle' that demonstrates the company's current packaging capabilities. Indeed, they are quite impressive as the company is showing off an 8 reticle-sized system-in-package (SiP) that features four logic tiles, 12 HBM4-class stacks, and two I/O tiles. More importantly, unlike the massive concept with 16 logic tiles and 24 HBM5 stacks the company presented last month, this one is actually manufacturable today.

First and foremost, it is necessary to note that what Intel Foundry is showcasing is not a working AI accelerator, but rather an 'AI chip test vehicle' that shows how future AI and HPC processors can be physically built (or rather assembled). To a large degree, the company is demonstrating its entire construction method that combines large compute tiles, stacks of high-bandwidth memory, ultra-fast chip-to-chip links, and a new class of power delivery into one manufacturable package. This package differs significantly from what TSMC offers today (more on this later). In short, the concept shows that next-generation heavy-duty AI processors are multi-chiplet designs, and Intel Foundry can build them.

At the heart of this platform are four large logic tiles allegedly built on Intel 18A process technology (hence featuring RibbonFET gate-all-around transistors and PowerVia backside power delivery) that are flanked by HBM4-class memory stacks and I/O tiles and presumably stitched together with EMIB-T 2.5D bridges embedded directly in the package substrate. Intel uses EMIB-T, which adds through-silicon vias inside the bridges so that power and signals can pass vertically as well as laterally, to maximize interconnection density and power delivery. Logically, the platform is designed for UCIe die-to-die interfaces running at 32 GT/s and beyond, which are also seemingly used to attach presumably C-HBM4E stacks.

The test vehicle also previews Intel's move toward vertical integration. The company's roadmap includes Intel 18A-PT process technology developed specifically for chiplets that stack other logic dies or memory on top and therefore must feature backside power delivery, pass-through TSVs, and hybrid bonding. In the case of the 'AI chip test vehicle', 18A-PT base dies sit under 18A/18A-P compute dies and either act as large caches or perform some additional work. To connect chiplets vertically, Intel uses its Foveros family — Foveros 2.5D, Foveros-R, and Foveros Direct 3D — packaging technologies to enable fine-pitch copper-to-copper bonding between active dies. Together with EMIB bridges, these methods enable Intel to build a hybrid lateral-and-vertical assembly that Intel positions as an alternative to large silicon interposers with higher wafer utilization and yield.

For multi-chiplet AI and HPC accelerators, power delivery is the principal design constraint. To that end, Intel's platform should be able to combine all of Intel's latest power-related innovations, including PowerVia, on-die Omni MIM capacitors, bridge-level decoupling in EMIB-T, base-die eDTC and eMIM-T capacitors, and embedded CoaxMIL inductors to support 'semi' integrated voltage regulators (IVR) that are located beneath every stack and below the package itself (as opposed to IVRs in the case of TSMC's CoWoS-L, which are a part of the interposer). This layered network is designed to support fast current swings of generative AI workloads without collapsing voltage margins and deliver maximum clean power when needed.

Showing an 'AI chip test vehicle' is a way for Intel to attract customers. Yet, it remains to be seen whether the company's codenamed Jaguar Shores AI accelerator, due in 2027, will use the architecture that Intel is showcasing today.

SK hynix, the world's biggest supplier of high-bandwidth memory (HBM), this week approved a ₩19 trillion ($12.896 billion) investment to build P&T7, a new advanced packaging and test facility in South Korea, dedicated solely to HBM. The plant will likely be the biggest HBM assembly and test facility in the world, but it will almost certainly not be the last HBM packaging and test facility of the same scale and cost going forward, considering the booming demand for memory, which has caused DRAM pricing to skyrocket.

Being the world's largest supplier of any type of product means you need to stay ahead of the whole industry, in terms of technology and production capacity, and the devil is in the details.

A massive facility

The company plans to construct what it calls P&T7 (Packaging & Testing 7) facility at the Cheongju Technopolis Industrial Complex, on a site measuring approximately 70,000 pyeong (approx. 231,405 square meters or 2,490,822 square feet). Construction is scheduled to begin in April 2026, and completion is targeted for the end of 2027, which is when the building will be finished, and is when SK hynix will begin installing equipment. Due to the equipping phase, expect the plant to come online toward the end of the decade on time for HBM4E, HBM5, and HBM5E types of memory.

The facility's dimensions are massive, resulting in a campus-scale site, rather than a back-end factory plot. For packaging and testing, the Fab P&T7 plot is unusually large; this may reflect the importance of HBM (and other exotic types of memory) assembly for the AI industry specifically, and the memory industry as a whole.

To put the scale into context, Intel's Ocotillo Campus near Chandler, Arizona, spans over 362,727 square meters, but it houses multiple front-end fab buildings, such as Fab 12, Fab 22, Fab 32, Fab 52, and Fab 62. Both Fab 52 and Fab 62 are expected to be capable of processing up to 40,000 wafer starts per month each when fully ramped, which makes them bigger than typical logic fabs run by TSMC.

While HBM packaging is a back-end activity, it still requires complex techniques like etching, lithography, hybrid bonding, and many other steps and tools used in logic production. This explains why HBM testing and packaging facilities are larger than typical back-end facilities.

Nonetheless, HBM packaging is inherently simpler than producing logic, so the scale of SK hynix's P&T7 plant is enormous, even by HBM standards. Its dimensions and investments dwarf SK hynix's HBM testing and assembly plant in West Lafayette, Indiana, which will cost the memory maker $4 billion and will span 39,948 square meters. Yet, keeping in mind that SK hynix expects the compound annual growth rate (CAGR) of HBM to be 33% from 2025 to 2030, it needs all the front-end DRAM and back-end packaging facilities it can build.

A strategic location

A key element of the project is its operational linkage with Fab M15X, a major SK hynix semiconductor manufacturing facility currently located in Cheongju that is currently being equipped with fab tools. The company expects the combined operation of M15X and P&T7 to create a tightly coupled manufacturing ecosystem capable of building HBM dies (which are three to four times larger than commodity DDR5). Therefore, SK hynix can test and package HBM in close proximity, essentially creating a vertically integrated manufacturing facility for HBM or other exotic types of memory that use multi-chip packaging.

The adjacency of Fab M15X and P&T7 is intended to elevate Cheongju into a new core base for SK hynix's AI memory operations, which will optimize production and packaging and can potentially enable the company to respond to market demand for HBM faster than it can today.

As a bonus, the close proximity of the front-end memory fab and the advanced packaging and testing facility will shorten feedback loops between engineers at both facilities, which might positively affect yields and/or performance. In fact, as the industry transits to more sophisticated types of memory for AI accelerators — such as HBM4 with a 2,048-bit interface — the bigger and more sophisticated assembly and testing plants for high-bandwidth memory located close to front-end DRAM fabs make sense.

From a strategic planning perspective, SK hynix says it had evaluated multiple domestic and international locations before selecting Cheongju for P&T7. The decision reflects multiple objectives. Firstly, the vast majority of SK hynix's memory is produced in South Korea, so it is reasonable to build its most advanced testing and packaging facility for AI DRAM nearby. Secondly, P&T7 working in proximity with M15X will reinforce the overall competitiveness of South Korea's semiconductor industry. Thirdly, a large project also supports regional development, a policy promoted by the government.

SK hynix notes that the site selection decision was not purely cost-driven; the company evaluated proximity to existing fabs, infrastructure readiness, and long-term supply-chain resilience. Cheongju was ultimately chosen as the location that balanced industrial efficiency best.

Although SK hynix never mentions it, there is one more factor that likely affected its decision to build its biggest HBM packaging facility in South Korea. Because the vast majority of AI accelerators are made in the region, not only in South Korea, but in Taiwan by TSMC.

Since SK hynix and TSMC share a lot of customers, the two companies work closely with one another. However, due to geopolitical and regional competitive reasons, SK hynix isn't likely to build a major facility in Taiwan, making South Korea the next-best option.

Technological importance

Building an extremely big HBM testing and packaging facility is important for SK hynix, not only from strategic and logistical points of view, but also from a technology development point of view.

Advanced packaging is as critical to HBM as the DRAM front-end fab because of HBM's inherent characteristics — extreme bandwidth, power efficiency, and density. These elements are enabled by the DRAM itself and packaging technology. A single DRAM die does not expose a 1,024-bit or 2,048-bit interface: it's enabled by stacking 8 – 16 dies, each featuring a 128-bit I/O, interconnected with Through Silicon Vias (TSVs), and routed through base dies and Redistribution layers (RDLs). To make everything work properly and according to specification, packaging must ensure bonding accuracy, optimal TSV resistance, and RDL integrity.

Power efficiency and thermals are also largely determined by packaging, as they define things like TSV and RDL parasitics, micro-bump or hybrid-bond quality, and interposer losses. Some packaging technologies have increased I/O voltage requirements and higher switching losses, which force manufacturers to reduce data transfer rates compared to offerings from their rivals.

Heat-extraction is also a big deal, and it entirely depends on packaging process technology (underfill and mold materials, as well as package-level thermal paths), as the better heat dissipation is between memory dies, the easier it is to cool the whole stack. SK hynix leads the industry with its mass reflow-molded underfill (MR-MUF).

Yield economics also increase the importance of packaging technology: even if a front-end DRAM fab achieves a 99% good die yield, if yield loss during packaging is significant (due to TSV defects, bond misalignment, and/or RDL defects), it hits margins across both the expensive DRAM fab and relatively inexpensive back-end packaging facility. Reliability qualification — burn-in, thermal cycling, and long-duration stress testing — is also performed at the package level and cannot be handled by generic back-end lines.

As HBM scales toward more dies per stack, wider interfaces, tighter pitches, and hybrid bonding, packaging complexity and costs of packaging and testing facilities will rise to logic-fab-class levels, which is probably what we are dealing with here.

Eventually, advanced packaging facilities — which already have costs similar to logic fabs from 2010 to 2015 — will become considerably more expensive, and DRAM makers will have to be willing to spend $20 billion or more on such facilities, as this will be the only way to enhance the bandwidth, efficiency, yields, and reliability of HBM memory going forward.

Packaging is a crucial process

Although HBM packaging is a back-end process, its reliance on lithography, etching, hybrid bonding, and other steps common in front-end fabs explains the cost of modern packaging facilities like logic fabs from the previous decade. Furthermore, increasingly complex next-generation types of HBM, starting from HBM4 and onwards, will encourage memory makers to build facilities like P&T7 costing tens of billions of dollars and located adjacent to DRAM fabs.

Avid readers of Tom’s Hardware have read a lot about the upcoming HBM4 and GDDR6 memory technologies, but as neither is used on mass production devices, few of us get to see actual HBM4 and GDDR6 memory packages. Good news, SK Hynix demonstrated them at CES, and our own Matt Safford has managed to grab some pictures.

SK Hynix demonstrated the industry’s first 16-Hi HBM4 memory package at the trade show, highlighting both the density that could not be achieved without its MR-MUF molding technology as well as HBM4’s 2,048-bit interface. SK hynix's HBM4 memory stacks are said to operate at 10 GT/s, which is 25% faster than the official JEDEC specification. Meanwhile, adopters like Nvidia want to have headroom for both extra performance in scale-up deployments (if customers are willing to) and for performance efficiency in hyperscaler applications.

HBM3/HBM3E and HBM4 share the same ~10.5 × 12.0 mm footprint, but HBM4 allows taller stacks — up to ~950 µm for 16-Hi versus ~750 µm for 12-Hi HBM3 — while packing far denser I/O and power bumps. When it comes to packaging, the company continues with its advanced mass Reflow molded underfill (MR-MUF) approach: multiple memory dies are mounted on a base substrate and bonded in a single reflow step, then encapsulated with mold material between DRAM layers, the base die, and the substrate.

Looking at the backsides of HBM4 and HBM3E, the difference between them becomes obvious, even taking the general pin count aside. HBM3E and HBM4 feature the same dimensions/footprint, so the backside indeed shows a much denser and more uniformly packed BGA pin field with noticeably higher bump density across the entire footprint. This is not particularly surprising as the jump from a 1,024 to a 2,048-bit I/O takes its obvious toll and requires substantially more signal bumps as well as additional power and ground pins to support higher bandwidth and tighter signal integrity margins. By contrast, HBM3E's backside has a sparser bump layout with more visible separation between regions, which is consistent with its 1,024-bit interface and lower aggregate I/O demand.

Meanwhile, HBM4's power delivery and ground contacts are also visibly different compared to the less advanced type of memory. Perhaps HBM4 allocates a larger fraction of its backside area to power and ground bumps; they are arranged more evenly across the package, something that could reduce noise and IR drop at data rates that are as high as 8 GT/s per standard or 10 GTs, given the listed capability.

Yet, we may be speculating here purely based on the fact that HBM3E features fewer power pins and shows clearer zoning between I/O and power regions. In fact, even without precise specs, the backside alone shows that HBM4 is designed for much higher I/O bandwidth and power delivery requirements.

In any case, these HBM4 modules use custom DRAM dies manufactured on the proven 1b-nm (5th-generation 10-nm-class) process to wed a large DRAM die with low defect density, reduced variability, and eventually high yield, something that makes them cheaper, yet it is hard to estimate how that lower cost could translate to the end user.

According to a report, HBM4 memory was not expected to reach volume production any earlier than the end of Q1 2026, according TrendForce. However, an Nvidia spokesperson told Tom's Hardware Premium: "Our HBM4 memory partners remain on track for production shipments in the second half of this year as originally planned", disputing the report that production has slid as a result of a redesigned spec.

While Nvidia denies the claim that HBM4 production has slid, if the report holds, it may have stemmed from two converging factors: Nvidia’s decision to revise its memory requirements upward for its next-gen Rubin GPU platform, and the company’s short-term strategy to aggressively extend shipments of its current Blackwell architecture. All three major HBM suppliers were reportedly forced to redesign their HBM4 products to meet the new specifications, pushing mass manufacturing back by at least one quarter.

This shift keeps HBM3 and HBM3e as the prevailing standards across AI and high-performance GPU deployments through at least Q1 2026. Samsung may be first to qualify, given that it has reportedly passed Nvidia’s qualification tests, but SK hynix is still expected to maintain the majority share as the primary supplier to Nvidia. Micron, a more recent entrant in the HBM market, has already begun sampling 11 Gbps-class HBM4 parts, but is still building out volume readiness.

Aligning with internal cadence

The changes also realign Nvidia’s internal cadence, with the Rubin GPU line, which will use HBM4 exclusively, now set for volume availability in the second half of 2026. Rubin’s target specs are the main reason HBM4 was reportedly behind schedule, though Nvidia insists that the timeline remains on track.

According to TrendForce, Nvidia pushed for speeds higher than 11 Gbps per pin, which required all three vendors to retool their designs. Each HBM4 stack carries 2,048 data I/Os, so a 13 Gbps upgrade pushes aggregate per-stack bandwidth to over 2.6 TB/s. That level of throughput places new stress on base die logic and thermals.

SK hynix and Samsung began delivering engineering samples to Nvidia in late 2025, but with Nvidia allegedly demanding last-minute spec changes, those parts will now be insufficient for Rubin's requirements. Samsung is said to have a slight edge on qualification, due to its newer base die process and integration stack. Still, SK hynix is expected to retain the bulk of Nvidia’s business into 2026, given its existing allocation contracts.

This is not just about specs, however, but also Nvidia's broader control over memory ecosystems. Its sheer amount of purchasing power gives the company the leverage to shape JEDEC standards, dictate packaging needs, and pace supplier production cycles. NVIDIA accounts for over 60% of global HBM consumption in 2024, according to Morgan Stanley, and TSMC’s advanced packaging nodes — especially CoWoS — are already fully committed to Nvidia’s Blackwell and Grace Hopper-class parts. Moving to Rubin and HBM4 implies even greater substrate complexity, requiring further capacity expansion at both the foundry and substrate partner levels

Nvidia confirmed at CES that Rubin silicon is already in full production; however, system-level availability won’t follow until much later in the year, which may be due to memory and interconnect bottlenecks. Rubin will ship with up to 288 GB of HBM4 and will rely on revised versions of Nvidia’s NVLink interconnect, optimized for the increased bandwidth profile. Early Rubin configurations are expected to pair with Grace CPUs via a refreshed NVLink architecture, allowing up to 900 GB/s of coherent bandwidth per link.

HBM suppliers recalibrate for 2026 volumes

The delay offers both a challenge and a reprieve for vendors. The challenge lies in redesigning HBM4 dies to meet Nvidia’s updated timing and signal integrity requirements, but the reprieve comes in the form of extra runway — most HBM3 and HBM3e nodes are now sold out through late 2026, and the additional time allows vendors to optimize yields and scale packaging operations.

SK hynix will continue shipping the lion’s share of HBM volume throughout the quarter; it has a deep allocation pipeline with Nvidia and has committed the majority of its high-end DRAM lines to HBM production. Samsung, which initially expected HBM4 to arrive by 2025, has increased its cadence significantly and is now expected to reach high-volume HBM4 qualification sometime in Q2 2026. Micron is simultaneously ramping 11 Gbps-class HBM4 and sampling early HBM4E products with up to 16 dies and extended bandwidth ceilings.

JEDEC ratified the HBM4 standard in April 2025, specifying 2048-bit interfaces and per-pin speeds beginning at 6.4 Gbps, scaling up to over 12 Gbps. With Rubin and other high-performance AI accelerators now targeting 13 Gbps or higher, vendors are pushing the upper limits of thermal and power envelopes. Micron has said that it expects 64GB stacks to become common with HBM4E sometime after late 2027. Meanwhile, each Rubin GPU package on the NVL72 will have eight stacks of HBM4 memory delivering 288GB of capacity and 22 TB/s of bandwidth.

The delay also allows some equilibrium to form in packaging. TSMC’s CoWoS-L capacity has been under severe pressure due to Nvidia’s Blackwell and AMD’s MI300 ramp. By spacing out Rubin’s arrival, Nvidia is implicitly giving its suppliers time to expand interposer and bumping operations without triggering yield degradation or substrate shortages.

Implications for AMD, Intel, and downstream designs

Nvidia may exert outsized influence over HBM4 production, but it is not the only company exposed to delays. AMD has leaned heavily on HBM3 and HBM3e across the MI300 and MI350, with the upcoming MI400 designed around 432 GB of HBM4. If HBM4 volume production slips further, it would not just reshape Nvidia’s cadence but also place direct pressure on AMD’s MI400 rollout.

Intel’s Habana Gaudi line is still anchored on HBM2e, with 128 GB per accelerator in the Gaudi 3. The company is known to be planning a Gaudi 4-class device codenamed “Jaguar Shores”, likely for release in 2027, using HBM4E, so its current timeline remains unaffected by Nvidia’s spec shift. Intel’s packaging flows for AI silicon are distinct from Nvidia’s, and its later entry into HBM4 adoption may allow it to bypass early yield limitations.

The real downstream impact may surface in how HBM availability shapes product segmentation. Nvidia’s highest-end Blackwell and Rubin GPUs will continue to monopolize advanced memory stacks and interposer capacity, effectively limiting HBM4 to premium datacenter SKUs. There is currently no sign of HBM4 migrating into consumer GPUs or gaming cards, given the absence of any new GPU announcements at CES. Even as GDDR7 supply tightens, Nvidia has not shown any intent to merge AI and GeForce memory standards.

With Rubin silicon now in full production and mass memory availability locked to late Q1 or early Q2 2026, the HBM race continues — just a quarter later than planned.

Update 01/13/2026 6:51am PT: Article amended to add quote from Nvidia spokesperson.

SK hynix is expanding its U.S. presence with a new office in the Seattle metropolitan area, placing the world’s leading HBM supplier within minutes of Nvidia, Amazon, and Microsoft.

According to industry sources cited by DigiTimes, the South Korean company has leased approximately 5,500 square feet at City Center Bellevue, just east of Seattle. While modest in size, the location and timing make the expansion far more consequential than a routine regional office opening.

SK hynix is sitting squarely in the middle of the ongoing AI hardware boom, supplying the majority of the HBM used in Nvidia’s data center accelerators and increasingly serving hyperscale customers building their own AI silicon. Establishing a physical foothold in the Pacific Northwest puts the company closer to the customers driving its fastest-growing and most important business.

Moving closer to the center of AI development

SK hynix has spent the past two years transforming itself from a cyclical commodity DRAM vendor into a leading supplier for AI infrastructure. That's visible in High Bandwidth Memory (HBM), where SK hynix was first to mass-produce HBM3 and has remained ahead in yield and volume as customers transitioned from HBM2E. In August 2025, the company overtook Samsung in global DRAM revenue for the first time, a change largely attributed to HBM shipments for Nvidia’s H100 and H200 AI accelerators.

Seattle and its surrounding suburbs have become one of the densest concentrations of the AI industry ecosystem outside of Silicon Valley. While Nvidia maintains a significant engineering presence in the region, Amazon’s AWS Skills Center is based nearby, and Microsoft’s Azure silicon and systems groups are spread across Redmond and Bellevue.

HBM is not a plug-and-play component. Memory stacks are co-designed with GPUs and AI accelerators, and performance, power, and reliability targets are refined through repeated cycles of joint validation. Physical proximity will allow faster iteration when issues arise, whether related to signal integrity, thermals, or packaging tolerances.

Amazon’s recent launch of its Trainium3 AI accelerator, which integrates 144GB of HBM3E, shows how quickly hyperscalers are increasing their reliance on stacked memory. Microsoft and Google are following similar paths with custom accelerators. Each of those programs depends on close coordination between the silicon designer and the memory supplier; a Seattle-area office gives SK hynix a seat at that table.

Broader U.S. localization

The Bellevue office also fits into a wider U.S. expansion that extends beyond customer support. In 2024, SK hynix announced plans for a $4 billion advanced packaging facility in Indiana, its first manufacturing investment in the United States. That site is intended to handle advanced HBM packaging and testing, with production targeted for 2028. While the Indiana project focuses on manufacturing, it appears the Seattle office will be oriented toward R&D, applications engineering, and customer engagement.

Taken together, these moves suggest SK hynix is deliberately localizing more of its AI-related operations in the U.S., where the bulk of demand is being generated. Advanced packaging has become as important as wafer fabrication for AI accelerators, and the ability to package memory near customers reduces both logistical complexity and geopolitical risk. It also aligns with U.S. industrial policy aimed at securing domestic supply chains for critical technologies.

There has been periodic speculation that SK hynix could eventually build a full DRAM fab in North America, though the company has not committed publicly to such a plan. Even without a fab, expanding engineering and packaging capabilities in the U.S. strengthens SK hynix’s position with American customers at a time when memory supply is extremely tight, thereby making long-term capacity planning a competitive differentiator.

The race to HBM4

SK hynix’s Seattle expansion also reflects intensifying competition in the HBM market. Samsung remains a formidable rival with deep manufacturing resources and its own U.S. investments, including advanced packaging capacity tied to its Texas operations. Micron, the sole U.S.-based DRAM manufacturer, is pursuing high-end server and automotive markets and sampling its own HBM4 designs, though its near-term capacity expansion is more constrained.

Meanwhile, SK hynix has already completed development of HBM4 and is understood to have delivered samples to Nvidia. Early engagement is particularly important with HBM4 because the transition involves higher stack counts, tighter power budgets, and more complex thermal challenges. Winning those designs early could easily lock in multi-year supply relationships.

Ultimately, with its Seattle expansion, SK hynix is telling Samsung and Micron that it intends to be embedded in the AI ecosystems of its largest customers rather than a distant component supplier. Being physically close to Nvidia and Amazon’s engineering teams during the transition to HBM4 will greatly improve the company’s odds of maintaining its lead, while also supporting adjacent efforts such as joint work with Nvidia on AI-optimized SSDs.

JEDEC, the organization responsible for defining the specifications of industry-standard memory types, is close to finalizing SPHBM4, a new memory standard designed to deliver full HBM4-class bandwidth with a 'narrow' 512-bit interface, higher capacities, and lower integration costs by leveraging compatibility with conventional organic substrates. If the technology takes off, it will address many gaps in the markets HBM could serve, but as we'll explain below, it isn't likely to be a GDDR memory killer.

Although high-bandwidth memory (HBM) 1024-bit or 2048-bit interfaces enable unbeatable performance and energy efficiency, such interfaces take a lot of precious silicon real estate inside high-end processors, which limits the number of HBM stacks per chip and therefore memory capacity supported by AI accelerators, impacting both the performance of individual accelerators as well as the capabilities of large clusters that use them.

HBM in a 'standard' package

The Standard Package High Bandwidth Memory (SPHBM4) addresses this issue by reducing the HBM4 memory interface width from 2048 bits to 512 bits with 4:1 serialization to maintain the same bandwidth. JEDEC doesn't specify whether '4:1 serialization' means quadrupling the data transfer rate from 8 GT/s in HBM4, or introducing a new encoding scheme with higher clocks. Still, the goal is obvious: preserve aggregate HBM4 bandwidth with a 512-bit interface.

Inside, SPHBM4 packages will use an industry-standard base die (probably made by a foundry using a logic fabrication process and therefore not cheaper as routing 'wide' DRAM ICs into a 'narrow' base die will probably get nasty here in terms of density and there will be clocking challenges due to slow wires from DRAMs and fast wires from the base die itself). It will also use standard HBM4 DRAM dies, which simplifies controller development (at least at the logical level) and ensures that capacity per stack remains on par with HBM4 and HBM4E, up to 64 GB per HBM4E stack.

On paper, this means quadrupling SPHBM4 memory capacity compared to HBM4, but in practice, AI chip developers will likely balance memory capacity with higher compute capability and the versatility they can pack into their chips, as silicon real estate becomes more expensive with each new process technology.

A GDDR7 killer?

An avid reader will likely ask why not use SPHBM4 memory with gaming GPUs and graphics cards, which could enable higher bandwidth at a moderate cost increase compared to GDDR7 or a potential GDDR7X with PAM4 encoding.

Designed to deliver HBM4-class bandwidth, SPHBM4 is fundamentally engineered to prioritize performance and capacity over other considerations, such as power and cost.

Although cheaper than HBM4 or HBM4E, SPHBM4 still requires stacked HBM DRAM dies that are physically larger and therefore more expensive than commodity DRAM ICs, an interface base die, TSV processing, known-good-die flows, and advanced in-package assembly. These steps dominate cost and scale poorly with volume compared to commodity GDDR7, which benefits from enormous consumer and gaming volumes, simple packages, and mature PCB assembly.

That said, replacing many GDDR7 chips with a single advanced SPHBM4 may not reduce costs; it may increase them.

The art is in the implementation details

While a 512-bit memory bus remains a complex interface, JEDEC says SPHBM4 enables 2.5D integration on conventional organic substrates and does not require expensive interposers, significantly lowering integration costs and potentially expanding design flexibility. Meanwhile, with an industry-standard 512-bit interface, SPHBM4 can offer lower costs (thanks to the volume enabled by standardization) compared to C-HBM4E solutions that rely on UCIe or proprietary interfaces.

Compared to silicon-based solutions, organic substrate routing enables longer electrical channel lengths between the SoC and the memory stacks, potentially easing layout constraints in large packages and accommodating more memory capacity near the package than is currently possible. Still, it is hard to imagine routing of a 3084-bit memory interface (alongside data and power wires) using conventional substrates, but we'll see about that.

Although the performance of high-bandwidth memory (HBM) has increased by an order of magnitude since its inception around a decade ago, many elements have remained fundamentally unchanged between HBM1 and HBM3E. But as the demands for bandwidth-hungry applications evolve, the technology must also change to accommodate them.

In new information revealed at TSMC's European OIP forum in late November, HBM4 and HBM4E will offer four major changes. HBM4 will receive a 2,048-bit interface and base dies produced using advanced logic technologies. Meanwhile, HBM4E will be able to utilize customizable base dies, which can be controlled with custom interfaces. These are dramatic shifts, which will have a big impact sooner than you might think.

HBM4, HBM4E, and C-HBM4E are on track to hit the market in 2026 and 2027, boasting the aforementioned 2048-bit standard interface with data transfer rates of up to 12.8 GT/s. Additionally, the customizable base dies will be able to use advanced logic technologies up to 3nm-class. This offers higher area efficiency, which TSMC claims represents a 2.5 times increase in performance.

HBM4: The next big thing

HBM4 — whose specification was officially published earlier this year — is the standard that sets the stage for a number of upcoming innovations in the AI and HPC memory market.

Each HBM4 memory stack features a 2,048-bit interface that officially supports data transfer rates of up to 8 GT/s, though controllers from controller specialists like Rambus and HBM4 stacks from leading DRAM vendors already support speeds of 10 GT/s or higher, since implementers want to have some reserve for additional peace of mind.

A stack with a 2,048-bit interface operating at 12 GT/s can deliver bandwidth of 2 TB/s, so an AI accelerator with eight HBM4 stacks will have access to potential bandwidth of 16 TB/s. And 12 GT/s could be just the beginning. Note that Cadence is already offering an HBM4E physical interface (PHY) with 12.8 GT/s support.

Internally, HBM4 doubles concurrency to 32 independent channels per stack (each split into two pseudo-channels), which reduces bank conflicts and raises efficiency throughput under highly parallel access patterns.

HBM4 stacks also support 24 Gb and 32 Gb DRAM devices and offer configurations for 4-Hi, 8-Hi, 12-Hi, and 16-Hi stacks, thus enabling capacities of up to 64 GB, which allows to build accelerators for next-generation AI models with trillions of parameters. Micron expects 64 GB stacks to become common with HBM4E sometime after late 2027, which aligns with Nvidia plans to equip its Rubin Ultra GPU with 1 TB of HBM4E memory.

The electrical specification of HBM4 broadens operating voltages with vendor-specific VDDQ options between 0.679V and 0.963V and VDDC of 0.97 V or 1.07 V, which enables DRAM makers to bin their offerings for efficiency or frequency while maintaining compatibility with the specification. On the security side of things, HBM4 supports directed refresh management (DRFM) to mitigate row-hammer attacks.

Because HBM4 expands its interface to 2,048 bits, it is supposed to have double the I/O contacts compared to previous-generation HBM stacks. Since it was close to impossible to produce a base die with proper routing using DRAM process technologies, memory makers like Micron, Samsung, and SK hynix collaborated with TSMC early on to ensure compatibility with CoWoS packaging technologies and to produce HBM4 base dies using 12FFC or N5 fabrication technologies.

Back then, it was thought that 12FFC would be used for 'regular' HBM4 base dies, which would be integrated with their host processors using advanced 2.5D process technologies, whereas N5 base dies would be used for HBM4 memory, which would then be integrated using direct bonding on logic chips.

At the European OIP 2025 forum, neither TSMC nor its partners mentioned N5-based HBM4 base dies for integration using hybrid bonding or similar technologies, which likely means that the project is not exactly a priority for now.

Potentially, the integration of HBM4 memory stacks on top of a high-performance processor creates significant thermal density, which would make it difficult to cool. It's also possible that hot compute chips can damage hot DRAM devices, and vice versa, but this is merely speculation.

There may also be hybrid-bonded SoIC-X 3D integrations, with stacked HBM4 on top of compute chiplets in development, but their developers do not want to share results just yet.

In any case, HBM4 base dies made by TSMC on its low-power 12FFC or N5 process technologies, as well as custom C-HBM4E base dies produced on TSMC's N3P node use lower voltages (0.8V – 0.75V vs 1.1V in case of HBM3E), and are up to two times more power efficient than base dies of HBM3E memory manufactured using DRAM technologies, according to TSMC.

On the other hand, since HBM4 requires a more sophisticated controller and a larger, more complex PHY compared to HBM3E (15mm^2 vs 11mm^2, according to GUC). HBM4's memory subsystems will be more power hungry than HBM3E subsystems, too. However, due to considerably higher bandwidth, enabled by HBM4, they will be considerably more power and area-efficient than predecessors.

As for IP readiness, GUC has taped out its HBM4 PHY IP on N3P in March 2025. This will be validated with HBM4 memory samples in Q1 2026, when the company will be formally able to claim that it has a silicon-proven and validated HBM4 memory solution. Additionally, the IP will be compatible with all types of CoWoS packaging (-S, -R, -L) and can address a variety of applications. HBM4 memory controllers are available from a range of companies, including Rambus. EDA developers like Cadence, Siemens EDA, and Synopsys.

HBM4E: 2.5X higher bandwidth than HBM3E

With the introduction of HBM4's 2,048-bit memory interface, JEDEC members had to slash maximum data transfer rates to 8 GT/s from around 9.4 GT/s supported by HBM3E, which still enables a dramatic bandwidth increase. However, HBM4E is set to push electrical and signaling limits higher by supporting per-pin data rates to 12 GT/s (by refining PHY for better signal margin and jitter control at higher frequencies) and extending total stack bandwidth to around 3 TB/s, while keeping the 2,048-bit interface and 32-channel architecture. As a result, the bandwidth offered by HBM4E stacks will be 2.5X higher compared to HBM3E, and even when area and PHY power are taken into account, HBM4E will be 1.7X more power efficient and 1.8X area efficient, according to GUC.

Standard HBM4E solutions will likely be able to use HBM4 base dies, though some memory makers may migrate to base dies using the N5 or N3P process technologies for higher performance and efficiency.

C-HBM4E: The first custom type of memory for AI and HPC

Virtually all leading DRAM makers have introduced proprietary DRAM solutions with certain levels of customization over the past decade, but none of them have gained traction. Starting with HBM4E, HBM memory will get a separate branch of customized solutions, which is set to feature unique capabilities and proprietary interfaces.

On a high level, C-HBM4E is an HBM4E memory stack with a custom base die. The stack retains standard HBM4E memory devices, which comply with clock and electrical requirements set by JEDEC. However, the base die can now be customized in several different ways, thus shifting emphasis from raw bandwidth to the integration of custom logic directly into memory devices, which can be achieved using several methods.

The easiest way — described by Rambus — is to retain the standard HBM4E interface, alongside built-in custom logic and/or caches on the base die, to add features or performance. As long as the HBM4E protocol with supporting firmware and software stacks is compliant, this may increase the performance of memory subsystems beyond increasing transfer rates or widening I/O.

A more complex method— envisioned by TSMC and Rambus — is to place the HBM4E memory controller and a custom die-to-die interface directly into the logic base die. A large part of the industry's focus is on reducing the number of traces required between the processor and the HBM base die, and a custom D2D interface will do just that. By shrinking the interface width, each memory stack consumes fewer I/O pins, which enables a single SoC to attach a greater number of HBM stacks without increasing package size or complexity.

A custom die made using TSMC's N3P technology would allow packing in an HBM4E memory controller, a custom D2D PHY, and potentially some additional logic. For example, KAIST envisions integration of near memory compute (NMC) processors, which will make at least some C-HBM4E solutions system-on-chips (SoCs) with basic processing capabilities.

If near-memory compute logic is indeed integrated into C-HBM4E, the software stack must evolve to become topology-aware and memory-aware, rather than treating a C-HBM4E stack as 'just' memory. Without changes to toolchains, drivers, and runtimes, near-memory compute becomes invisible silicon—present in hardware, but unused by software.

Runtime systems and compilers will need explicit knowledge of bank structure, channel placement, and in-memory execution units so that workloads can be scheduled where data physically resides, instead of being moved across the fabric. In addition to this, programming models will also need extensions to work with in-memory compute, or multi-tier memory systems in general. Finally, operating systems must support heterogeneous memory domains with non-uniform latency and asymmetric coherence, while profilers must observe and optimize execution occurring inside memory devices.

A vision beyond

If the figures published by TSMC and GUC are to be believed, then HBM's raw performance is set to increase by around 2.5 times within the next few years, thanks to HBM4E. This development opens the doors to memory subsystems with a 1 TB capacity and a whopping bandwidth of 48 TB/s. If custom compute logic inside base dies of HBM gets adopted by the industry, this might be the biggest shift in how computers work in decades.

Micron has confirmed it will partner with TSMC to manufacture the base logic die for its next-generation HBM4E memory, with production targeted for 2027. The announcement, made during the company’s fiscal Q4 earnings call on September 23, adds yet more detail to an already busy roadmap.

Micron is shipping early HBM4 samples at speeds above 11 Gbps per pin, providing up to 2.8TB/s of bandwidth, and it has already locked down most of its 2026 HBM3E supply agreements. But the big takeaway is that Micron will hand TSMC the task of fabricating both standard and custom HBM4E logic dies, opening the door to tailored memory solutions for AI workloads.

The decision also places Micron squarely in the middle of the next wave of AI system design, aligning with previous reporting on HBM roadmaps across Micron, SK hynix, and Samsung, and with earlier analysis of how Micron views HBM4E as a platform for customization.

A semi-configurable subsystem

The industry is already familiar with the HBM cadence: HBM3E today, HBM4 in 2025–2026, and HBM4E around 2027, and each new generation brings higher per-pin data rates and taller stacks. SK hynix has already confirmed 12-Hi HBM4 with a full 2048-bit interface running at 10 GT/s, while Samsung is plotting similar capacities with its own logic processes. Micron is shipping its own HBM4 stacks and claims more than 20% better efficiency than HBM3E.

HBM4E is the extension of that roadmap, but Micron is treating it as something more. The company highlighted that the base die will be fabricated at TSMC, not in-house, and that custom logic-die designs will be offered to customers willing to pay a premium. By opening the base die to customization, Micron is effectively turning HBM into a semi-configurable subsystem. Instead of a one-size-fits-all interface layer, GPU vendors could request additional SRAM, dedicated compression engines, or tuned signal paths.

That approach mirrors what we have seen from SK hynix, which has already described customizable base dies as part of its HBM4 strategy. Given that customized memory is stickier, more profitable, and more important for customers trying to squeeze every watt and every cycle out of an AI accelerator, this is likely to become a lucrative segment of the market.

The importance of AI

SK hynix has completed development of its HBM4 memory and prepared it for high-volume manufacturing of memory stacks, the company said on Friday. HBM4 stacks from SK hynix go beyond specifications set by JEDEC by 25% in terms of performance, though it remains to be seen whether producers of next-generation AI accelerators — such as AMD, Broadcom, or Nvidia — will use that potential on their 2026 products.

SK hynix’s HBM4 memory stacks feature a 2,048-bit I/O, doubling the width of the HBM interface for the first time since 2015, and a 10 GT/s data transfer rate, which is 25% higher compared to the official JEDEC standard (more on this later). The company's HBM4 memory stacks use specially designed DRAM dies built using proven 1b-nm (5th Generation 10nm-class) process technology that combines decent performance efficiency with node maturity (i.e., low defect density and variability).

For its HBM4 modules, SK hynix continues to use its proven Advanced Mass Reflow Molded Underfill (MR-MUF) method. In this process, multiple memory chips are placed on a base substrate and bonded together in a single reflow step. Right after that, spaces between the stacked DRAM layers, base die, and substrate are filled with a mold material to secure and protect the structure. Advanced MR-MUF enables the company to keep the height of its 12-Hi HBM stacks within specification and improve heat dissipation of power-hungry memory modules.

SK hynix has taken to Twitter/X to compare its delicately stacked HBM4 to some deliciously layered s’mores. No, its social media team hasn’t gone mad. The semiconductor giant was simply piggybacking some HBM4 PR on the unlikely coattails of National S’mores Day.

We hope SK hynix paid a human to craft this delicious looking s’mores image. The impeccable typography must have at least been edited by a graphic designer.

Digging deeper into the s’more analogy, there are quite a few reasons why we should forgive SK hynix for this on-the-surface silly comparison. As per the infauxgraphic from the South Korean memory giant, making s’mores has at least five similar process steps as making HBM4.

The most obvious similarity involves the use of “cracker-like chips” coated with “marshmallow-like flux” ahead of multi-layered bonding. But I am personally very happy to have never eaten any marshmallows that resemble flux. SK hynix’s infographic also likens the heating and reflow processes with toasting and heating your s’mores ingredients. Pressure is necessary for both HBM4 and s’more bonding.

Traditional s’mores in the U.S. are a delicious fusion of Graham Crackers, marshmallows, and chocolate. These three basic ingredients take on a new level of deliciousness due to the action of heat and pressure.

This isn’t the first HBM recipe juxtaposition

Principal analyst, CEO, and founder of the Silicon Valley-based Constellation Research, Ray Wang, penned a paper about how China was closing the HBM gap this April. From the grains of wisdom within the substack post, Lennart Heim seemed delighted to share Wang’s likening of the HBM fabrication process to baking baklava.

In case you aren’t familiar with baklava, it is another layered desert, this time with its centuries old roots in pre-Ottoman Turkey. In his comments on Wang’s ChinaTalk piece about the process made by CXMT, Heim was keen to agree that “I mean the "HBM is like baklava," quite literally.”

National Play in the Sand Day, Julienne Fries Day?

High Bandwidth Memory (HBM) is the unsung hero behind the AI revolution. As the industry seeks to extract the most performance from frontier AI models, HBM powers the world's fastest GPUs and AI accelerators by keeping the intense computational engines fed with data at breakneck speed. This critical technology has rapidly matured over the past several years, and lately the pace of innovation has quickened, as industry behemoths like Nvidia and AMD look to facilitate the creation of more advanced artificial intelligence models.

All three major DRAM makers (Micron, Samsung, and SK hynix) have started volume production of 8-Hi HBM3E stacks, the newest form of the technology. And more robust and powerful forms of HBM memory are already in development.

Unfortunately, shortages of sophisticated HBM memory have hampered the supply of AI GPUs, which has manufacturers racing to add more production capacity to address any shortfalls. Meanwhile, the development of next-gen HBM products continues apace, hand-in-hand with new performance-enhancing technologies, which will power the next wave of AI accelerators.

Let's take a look at what's next on the HBM roadmaps for Micron, Samsung, and SK hynix based on official information and other sources.

Speeds and feeds

Memory bandwidth is a critical bottleneck in AI systems — AI models, particularly deep learning models, ingest tremendous amounts of data as they chew through workloads. But most forms of modern memory can't satiate AI's ravenous appetite for more data. That's where HBM steps in.

Traditional memory based on DDR, LPDDR, or GDDR uses 128–bit to 512-bit wide interfaces and employs high data transfer rates to provide bandwidth from 100 GB/s to 2 TB/s.

Unlike traditional memory, high-bandwidth memory (HBM) uses a very wide interface—1024 bits in the case of HBM2 and HBM3, or 2048 bits with HBM4—which multiplies bandwidth up to 4 TB/s—8 TB/s. Given the bandwidth-constrained nature of high-intensity parallel computation in GPUs and accelerators, this increased bandwidth translates directly to more performance.

However, the wide interface makes HBM difficult to produce, requiring multiple specialized DRAM devices interconnected using through-silicon vias (TSVs) stacked on top of a base die. HBM makers also vary the number of stacked memory dies to increase capacity, denoted by terminology such as 8-Hi for eight stacked dies, or 12-Hi for 12 stacked dies.

Due to its huge bandwidth, HBM is, and will continue to be, the de facto memory standard for AI systems, HPC ASICs, and GPUs.

12-Hi HBM3E is almost here

Today's highest-end AI accelerators — including Nvidia's H200 (141 GB), B200 (192 GB), and AMD's Instinct MI300X (192 GB) — use 24 GB 8-Hi HBM3E stacks based on 24 Gb DRAM devices. The next step for the industry is to adopt higher-capacity 36 GB 12-Hi HBM3E packages featuring 24 Gb memory dies. These will be used by Nvidia's upcoming B300-series and AMD's next-gen MI325X AI accelerators.

SK hynix has begun mass production of 36 GB 12-Hi HBM3E chips, whereas Micron has been sampling similar products since September, with mass production of the new packages understood to be imminent.

Samsung, on the other hand, was late to the party with its 8-Hi HBM3E certification, and its 12-Hi HBM3E dies also suffered from a slight delay. Samsung's delay is likely caused by sticking with its 1α fabrication technology, unlike Micron and SK hynix, which use a 1ß (5th Gen, 10nm-class) DRAM process to make their HBM3E DRAM ICs. By the time Nvidia's B300 enters mass production, Samsung will likely be able to compete with 12-Hi HBM3E 36 Gb offerings of its own.

HBM4: 2048-bit I/O and up to 16 layers

While manufacturers are still wrapping their hands around the upcoming HBM3E rollout, HBM4 and HBM4E are both already on the horizon.

The preliminary HBM4 specification (unveiled in July 2024) introduces a wider 2048-bit interface for HBM stacks. It also specifies 24 Gb and 32 Gb DRAM layers at up to 6.40 GT/s. The spec supports 4-Hi, 8-Hi, 12-Hi, and 16-Hi configurations, ensuring greater flexibility and potentially enabling even larger 64 Gb HBM4 packages.

Meanwhile, HBM4E may also boast high interface speeds of around 9 GT/s, as Rambus' HBM4 memory controller IP exceeds the announced capabilities of HBM4's JDEC-standard 6.40 GT/s speeds.

With HBM4E, memory makers will be able to customize base dies of packages (which SK hynix envisioned in early 2024) by adding additional functions, which could potentially extend to enhanced caches, custom interface protocols, and more.

All three leading memory manufacturers, Micron, Samsung, and SK hynix, have confirmed their intentions to produce HBM4 and HBM4E memory, but their overall rollout strategies may differ.

HBM4: 16-Hi stacks, but no 32 Gb devices on horizon

For now, none of the prominent DRAM producers have HBM4 or HBM4E stacks based on 32 Gb memory devices on their roadmaps. As such, all HBM4 and HBM4E products are expected to utilize smaller 24 Gb DRAM dies when they first roll out.

Micron is expected to keep using its proven 1ß (5th Gen, 10nm-class) process technology to make 24 Gb memory ICs for HBM4 stacks; however, Samsung plans to transition to 24 Gb DRAM dies made on its 1γ (6th Gen, 10nm-class) process with HBM4 and HBM4E. This will likely offer Samsung substantial performance, power efficiency, and cost advantages. SK hynix also intends to use 1ß for HBM4 DRAM ICs and may transition to a 1γ process for the HBM4E offering.

When it comes to layers, Micron lists 12-Hi and 16-Hi versions of its HBM4 and HBM4E offerings, whereas Samsung and SK hynix may go straight to 16-Hi HBM4 stacks. With the standard appearing to be 24 Gb DRAM devices and 12-Hi or 16-Hi stacks, HBM4 will increase per-package capacity to 48 Gb, a noticeable leap over HBM3E's 36Gb.

It's possible that by the time HBM4E finally arrives, the number of supported layers may exceed 16, with rumors that South Korean manufacturers could adopt a 20-layer design (which should be taken with a grain of salt). By then, DRAM makers may have also adopted a 32 Gb package for high-bandwidth offerings.

HBM4 & HBM4E production nodes

It should be no surprise that HBM4 and HBM4E memory stacks will rely on base dies produced by logic manufacturers using logic process technologies, thus boosting transfer speeds and signal integrity. TSMC and SK hynix were the first to disclose that they plan to use TSMC’s 12FFC+ and N5 base dies for HBM4. It's likely that Micron will also use TSMC's base dies (as the two companies are partners), though this has not been officially confirmed.

Samsung is expected to use its own Samsung Foundry nodes for HBM4 and HBM4E base dies. There is still uncertainty around the exact node it will employ, though it is reasonable to expect similar process technologies to TSMC's 12FFC+ and N5 processes.

HBM4 is coming in 2026 & HBM4E expected a year later

Samsung and SK hynix are rumored to introduce their first HBM4 offerings around Q3 2025, whereas Micron is projected to follow in Q4 2025. In both cases, 'introductions' likely mean the delivery of the first working samples to partners like AMD and Nvidia, not high-volume manufacturing.

Considering that the mass production of actual processors that support HBM4 is not expected until 2026, Micron's slight delay does not seem like a major issue.

Curiously, Micron began discussing HBM4E around a year before the planned mass production of HBM4 was set to commence. Typically, 'extended' variants of HBM specifications are introduced years after the original standard. According to Micron's official roadmap, HBM4E is set to arrive in late 2027.

HBM4E is likely to be used in the generation after the release of Nvidia's upcoming Rubin architecture and AMD's MI400 AI accelerator. Both are slated to support HBM4 in 2026.

If the industry requires customizable memory, HBM4E might land earlier than expected, but don't hold your breath — HBM development is notoriously challenging.

KAIST, a leading Korean national research institute, has released a 371-page paper that details the evolution of high-bandwidth memory (HBM) technologies through 2038, showing increases in bandwidth, capacity, I/O width, and thermals. The roadmap spans from HBM4 to HBM8, with developments in packaging, 3D stacking, memory-centric architectures with embedded NAND storage, and even machine learning-based methods to keep power consumption in check. 

Keep in mind that the document is about the hypothetical evolution of HBM tech given the current direction of the industry and research, not an actual roadmap of a commercial company. 

HBM capacity per stack will increase from 288 GB to 348 GB for HBM4, to 5,120 GB to 6144 GB for HBM8. Also, power requirements will scale with performance, rising from 75W per stack with HBM4 to 180W with HBM8. 

Between 2026 and 2038, memory bandwidth is projected to grow from 2 TB/s to 64 TB/s, while data transfer rates are set to rise from 8 GT/s to 32 GT/s. The I/O width per HBM package is also set to increase from the 1,024-bit interface of today's HBM3E to 2,048 bits with HBM4 and then all the way to 16,384 bits for HBM4. 

We already know pretty much everything about HBM4 and we know that HBM4E will add customizability to base dies to make HBM4E more tailored for particular applications (AI, HPC, networking, etc.). 

Expect such capabilities to remain in HBM5, which will also deploy stacked decoupling capacitors and 3D cache. With a new memory standard comes increased performance, so HBM5, expected to arrive in 2029, will retain HBM4's data rate but is projected to double the I/O count to 4,096, thereby raising bandwidth to 4 TB/s and per-stack capacity to 80 GB. 

Per stack power is expected to grow to 100 W, which will require more advanced cooling methods. Interestingly, KAIST expects HBM5 to continue using microbump technology (MR-MUF), although the industry is reportedly already looking at direct bonding with HBM4. In addition, HBM5 will also integrate L3 cache, LPDDR, and CXL interfaces on the base die, alongside thermal monitoring. KAIST also expects AI tools to start playing a role in optimizing physical layout and jitter reduction with the HBM5 generation.

HBM6 is projected to take over in 2032, increasing transfer speed to 16 GT/s and per-stack bandwidth to 8 TB/s. Capacity per stack is expected to reach 120 GB, and power climbs to 120W. Researchers at KAIST believe that HBM6 will adopt direct bonding without bumps, along with hybrid interposers combining silicon and glass. Architectural changes include multi-tower memory stacks, internal network switching, and extensive through-silicon via (TSV) distribution. AI design tools expand in scope, incorporating generative methods for signal and power modeling.

HBM7 and HBM8 will push things further, with HBM8 reaching 32 GT/s and 64 TB/s per stack. Capacities are projected to expand to 240 GB. Packaging is believed to adopt full 3D stacking and double-sided interposers with embedded fluid channels.

While HBM7 and HBM8 will still formally belong to the family of high-bandwidth memory solutions, their architectures are expected to dramatically differ from what we know as HBM today. While HBM5 will add L3 cache and interfaces for LPDDR memory, these generations are projected to incorporate NAND interfaces, enabling data movement from storage to HBM with minimal CPU, GPU, or ASIC involvement. That will come at the cost of power consumption, which is expected to be 180W per stack. AI agents will manage real-time co-optimization of thermal, power, and signal paths, according to KAIST.

Micron introduced its 16Gb DDR5 devices made on its new 1γ (1-gamma) fabrication process that uses EUV lithography, a first for Micron, today on March 25. The new IC not only delivers higher performance than its predecessor, but it also consumes less power and is poised to be cheaper to make. The company also said that its 1γ manufacturing technology (6th Generation 10nm-class node) will eventually be adopted for other DRAM products.

DDR5 at 9200 MT/s

Micron's lead 1γ product is the company's 16Gb (2GB) DDR5 IC that is rated for a 9200 MT/s data transfer rate at an industry-standard voltage of 1.1V. Compared to its predecessor — a 16Gb DDR5 IC made on 1β fabrication process — the new device consumes 20% less power and features a 30% higher bit density, which may translate into a comparable decrease in production cost once the new chips achieve yields comparable to that of 1β 16Gb DRAM devices. 

While Micron rates its latest 16Gb DDR5 ICs at 9200 MT/s, this speed bin is significantly higher than anything in the latest edition of the DDR5 specification. The company stresses that the chip can run at JEDEC-compliant speed grades just fine, and the higher speed bin will enable some future proofing and compatibility with next-generation CPUs. Micron also suggests that CUDIMMs or CXL-based memory modules could leverage higher-than-JEDEC speeds. DIMMs for enthusiasts will also likely adopt the new DRAMs for their post-10,000 MT/s modules.

Micron is currently sampling its 16Gb DDR5 ICs made on 1γ technology and products on their base (i.e., chips and modules) with laptop and server manufacturers and expects their qualifications to be completed in one or two quarters. That means we should see Micron's latest memory devices in retail products starting mid-2025. The company expects all types of memory modules — for desktops, laptops, and servers — to adopt its new memory chips.

Considering the fact that Micron's 1γ-based DRAMs offer a combination of valuable qualities for all market segments — enhanced performance for desktops as well as lower power consumption for notebooks and servers — we indeed expect the firm's latest 16 Gb DDR5 ICs to become quite popular when they hit the market.

Over time, Micron will use its 1γ fabrication technology to make other types of memory products, including GDDR7, LPDDR5X (at up to 9600 MT/s), and data center-grade products, so the node will become a workhorse for the company.

1γ manufacturing technology

Micron's 1γ manufacturing process is the company's first technology to adopt extreme ultraviolet lithography (EUV), something that other leading memory makers adopted years ago. It's been a while in coming and looks to offer significant benefits relative to existing product lines.

Micron did not disclose how many EUV layers the new production node uses, but we can speculate that the company uses EUV for critical layers that would otherwise require the usage of multi-patterning, which lengthens production cycles and can affect yields. Micron does say that 1γ uses EUV in conjunction with multi-patterning DUV techniques. Also, Micron's 1γ DRAM process technology adopts next-generation high-K metal gate technology and an all-new back-end-of-line (BEOL) circuitry.

" In addition to EUV adoption in 1γ, we have introduced our next generation high-K metal gate CMOS and advanced back-end-of-line processes, which together enable the 9200 MT/s [data transfer rate], a 15% performance improvement over 1β DRAM […] while reducing power by about 20% over 1β," said Shigeru Shiratake, senior vice president of DRAM Technology Development at Micron.

For now, Micron produces its 1γ DRAMs at its fabs in Japan, where the company's first EUV tool was installed in 2024. As the company ramps up production of 1γ memory, it will add more EUV systems to its fabs in Japan and Taiwan.

SanDisk on Wednesday introduced an interesting new memory that could wed the capacity of 3D NAND and the extreme bandwidth enabled by high bandwidth memory (HBM). SanDisk's high-bandwidth flash (HBF) memory enables access to multiple high-capacity 3D NAND arrays in parallel, thus providing plenty of bandwidth and capacity. The company positions HBF as a solution for AI inference applications that require high bandwidth and capacity coupled with low power requirements. The first-generation HBF can enable up to 4TB of VRAM capacity on a GPU, and more capacity in future revisions. SanDisk also foresees this tech making its way to cellphones and other types of devices. The company hasn't announced a release date yet.

"We are calling it the HBF technology to augment HBM memory for AI inference workloads," said Alper Ilkbahar, memory technology chief at SanDisk. "We are going to match the bandwidth of HBM memory while delivering 8 to 16 times capacity at a similar cost point."

Conceptually, HBF is similar to HBM. It stacks multiple high-capacity, high-performance flash core dies interconnected using through-silicon vias (TSVs) on top of a logic die that can access flash arrays (or rather flash sub-arrays) in parallel. The underlying architecture of HBF is SanDisk's BICS 3D NAND using the CMOS directly bonded to Array (CBA) design that bonds a 3D NAND memory array on top of an I/O die made using logic process technology. That logic may be a key to enabling HBF.

"We challenged our engineers and said, what else could you do with this power of scaling," said Alper Ilkbahar. "The answer they came up with […] was moving to an architecture where we divide up this massive array into many, many arrays and access each of these arrays in parallel. When you do that, you get massive amounts of bandwidth.  Now, what can we build with this? We are going to build high bandwidth flash."

Traditional NAND die designs often treat the core NAND flash memory array as planes, pages, and blocks. A block is the smallest erasable area, and a page is the smallest writable area. HBF seems to break the die into 'many, many arrays' so they can be accessed concurrently. Each sub-array (with its own pages and blocks) presumably has its own dedicated read/write path. While this resembles how multi-plane NAND devices work, the HBF concept seems to go far beyond them.

For now, SanDisk says that its 1st-Gen HBF will use 16 HBF core dies. To enable such devices, SanDisk says that it has invented a proprietary stacking technology that features minimal warpage to enable stacking 16 HBF core dies, and a logic die that can simultaneously access data from multiple HBF core dies. The complexity of logic that can handle hundreds or thousands of concurrent data streams should be higher than that of a typical SSD controller.

Unfortunately, SanDisk does not disclose the actual performance numbers of its HBF products, so we can only wonder whether HBF matches the per-stack performance of the original HBM (~ 128 GB/s) or the shiny new HBM3E, which provides 1 TB/s per stack in the case of Nvidia's B200.

The only thing we know from a SanDisk-provided example is that eight HBF stacks feature 4 TB of NAND memory, so each stack can store 512 GB (21x more than one 8-Hi HBM3E stack that has a capacity of 24 GB). A 16-Hi 512 GB HBF stack means that each HBF core die is a 256 Gb 3D NAND device with some complex logic enabling die-level parallelism. Funneling hundreds of gigabytes of data per second from 16 3D NAND ICs is still quite a big deal, and we can only wonder how SanDisk can achieve that.

What we are sure about is that HBF will never match DRAM in per-bit latency, which is why SanDisk stresses that HBF products are aimed at read-intensive, high-throughput applications, such as big AI inference datasets. For many AI inference tasks, the critical factor is high throughput at a feasible cost rather than the ultra-low latency that HBM (or other types of DRAM) provides. So, while HBF may not replace HBM any time soon, it might occupy a spot on the market that requires high-capacity, high-bandwidth, NAND-like cost but not ultra-low latency. To simplify the transition from HBM, HBF has the same electrical interface with some protocol changes, though HBF is not drop-in compatible with HBM.

" We have tried to make it as close as possible mechanically and electrically to the HBM, but there are going to be minor protocol changes required that need to be enabled at the host devices," said Ilkbahar.

SanDisk didn't touch on write endurance. NAND has a finite lifespan that can only tolerate a certain number of writes. While SLC and pSLC technologies offer higher endurance than the TLC and QLC NAND used in consumer SSDs, this comes at the expense of capacity and adds cost. NAND is also typically written to at block granularity, whereas memory is addressable at the cache line level (i.e. typically 128KB for NAND blocks versus 32 bytes for a cache line). That's another key challenge.

SanDisk has a vision of how its HBF will evolve over three generations. Nonetheless, for now, SanDisk's HBF is largely a work in progress. SanDisk wants HBF to become an open standard with an open ecosystem, so it is forming a technical advisory board consisting of 'industry luminaries and partners.

SK hynix this week posted record earnings, operating profits, and net income for 2024. The company managed to more than double its revenue and return to profitability mainly due to increased demand for premium types of dynamic random access memory (DRAM) such as HBM3/HBM3E as well as enterprise-grade SSDs.

SK hynix earned ₩66.193 trillion in revenue ($46.054 billion), ₩23.467 trillion in operating profit ($16.327 billion), and ₩19.797 trillion ($13.776 billion) net profit for the whole of 2024. That compares to ₩32.765 trillion in revenue ($22.8 billion) and a net loss of ₩9.138 trillion ($6.36 billion) in 2023. The company's operating margin was 35% in 2024, up from -24% in 2023. Although the company's revenue climb slowed in the fourth quarter, which is in line with seasonality and dropping 3D NAND prices, SK hynix operating margin still increased during the quarter as it ramped up production of premium HBM3E memory.

The company attributes its success to increased sales of AI memory products, including HBM3 and HBM3E for the latest accelerators like Nvidia's H100, H200, and B100/B200 as well as enterprise-grade solid-state drives that are used for AI training and inference systems. High-end AI servers tend to also contain a lot of memory, so while SK hynix did not explicitly mention high-density server-grade DDR5 chips and modules, they clearly played a role in its great results.

"With significantly increased portion of high value-added products, SK hynix has built fundamental to achieve sustainable revenues and profits even in times of market correction." said Kim Woohyun, Vice President and Chief Financial Officer (CFO) at SK hynix. "While maintaining the profitability-first commitment, the company will make flexible investment decisions in line with market situation."

Looking ahead, SK hynix expects continued growth in AI-driven markets, fueled by global investments in AI servers for training and inference. While the consumer market — client PCs and smartphones — is expected to slow down, AI-equipped devices will drive growth in the second half of the year.

To meet this demand, SK hynix will increase HBM3E supply, develop HBM4, and transition to advanced processes for DDR5 and LPDDR5 production. For 3D NAND flash memory, the company will prioritize profitability and flexible sales strategies.

Today, Micron Technology has started constructing its multi-billion-dollar packaging facility for high-bandwidth memory (HBM) in Singapore. The company will invest $7 billion in the plant, as it expects demand for HBM3E, HBM4, and HBM4E memory to skyrocket in the coming years amid the AI boom. The facility is set to start operations in 2026.

Micron's packaging facility for high-bandwidth memory (HBM) is located next to Micron's existing fabs in Singapore that produce 3D NAND and DRAM. The new HBM assembly plant will commence production in 2026 and then plans to substantially increase its capacity in 2027. The facility will use advanced AI-driven automation to boost operational efficiency, though the company does not disclose where and how artificial intelligence will be used.

While Micron is leading the industry with premium HBM3E memory, when it comes to HBM market share, the company is still an underdog compared to Samsung and SK hynix. To some degree, this is conditioned by the fact that Micron does not have as vast DRAM manufacturing capacity as its rivals from South Korea (while HBM memory dies take up more capacity than conventional memory ICs). Still, to a certain degree, this can be attributed to the lack of vast HBM assembly capacity.

Micron is gradually increasing its HBM3E output at its existing facilities, hoping to grab a mid-20% HBM market share in mid-2025. However, with the new Singapore assembly facility coming online in 2026, the company hopes to get an even larger chunk of the market.

"As AI adoption proliferates across industries, the demand for advanced memory and storage solutions will continue to increase robustly," said Sanjay Mehrotra, president and CEO of Micron. "With the continued support of the Singapore government, our investment in this HBM advanced packaging facility strengthens our position to address the expanding AI opportunities ahead."

Although the new facility will be tailored for assembling HBM stacks, it can also be used to assemble 3D NAND packages since assembly technologies with through-silicon vias (TSVs) are generally similar.

The project will initially create around 1,400 jobs; the expansion could potentially increase that number to 3,000. These roles will include packaging development, assembly, and testing operations.

"This is Singapore’s first high-bandwidth memory advanced packaging facility, allowing us to contribute to global AI growth," said Png Cheong Boon, Singapore Economic Development Board Chairman. "It expands Singapore’s partnership with Micron and further strengthens the semiconductor ecosystem in Singapore."

TSMC is on track to qualify its ultra-large version of chip-on-wafer-on-substrate (CoWoS) packaging technology that will offer an interposer size of up to nine reticle sizes and 12 HBM4 memory stacks in 2027, the company announced at its European Open Innovation Platform (OIP) forum this month. The new packaging method will address the most performance-hungry applications and let AI and HPC chip designers build processors the size of the palm of a hand. 

TSMC introduces new process technologies every year, doing its best to meet its customers' needs for power, performance, and area (PPA) improvements. But some customers need even more performance, and for whom an EUV litho tool reticle limit of 858 mm^2 is not enough. These customers choose to use multi-chiplet solutions packaged using TSMCs CoWoS technology, and in recent years, the company offered multiple iterations of this method. 

The original CoWoS enabled chip packages of around 1.5-reticle size in 2016, then evolved to 3.3-reticle size today, which enables placing eight HBM3 stacks into a package. Next up, TSMC promises 5.5-reticle size packages with up to 12 HBM4 memory stacks in 2025 – 2026. However, this pales behind the company's ultimate version of CoWoS, enabling system-in-packages (SiPs) of up to nine reticle sizes with 12 and potentially more HBM4 modules onboard.  

That 9-reticle 'Super Carrier' CoWoS (offering up to 7,722 mm^2 for chiplets and memory) with 12 HBM4 stacks is planned to be qualified in 2027, so it is reasonable to expect it to be adopted in 2027 – 2028 for ultra-high-end AI processors.  

TSMC fully expects companies adopting its advanced packaging methods to also vertically stack their logic using its system-on-integrated chips (SoIC) advanced packaging technologies to further boost transistor counts and performance. In fact, with 9-reticle CoWoS, TSMC expects its clients to place a 1.6nm-class die on top of a 2nm-class die, so we are talking about very high transistor density. 

However, there is a major challenge with those ultra-large CoWoS packages. The 5.5-reticle CoWoS package will require an over 100x100 mm substrate (which is approaching the size constraints of the OAM 2.0 standard, which measures 102×165mm), whereas the 9-reticle CoWoS will go beyond a 120x120 mm substrate. Such major substrate dimensions will have an influence on how systems are designed and how data centers are equipped to support them. In particular, power and cooling. When it comes to power, we are talking about hundreds of kilowatts per rack, whereas when it comes to cooling, we are talking about liquid cooling and immersion methods to manage high-power processors effectively.

Nvidia has asked SK hynix to move up its delivery timeline for next-generation HBM4 memory chips by six months, according to SK Group Chairman Chey Tae-won, reports Reuters.

Initially, SK hynix planned to ship its HBM4 chips to customers in the latter half of 2025. Following Nvidia CEO Jensen Huang's request, the timeline was shortened, though the exact new schedule was not specified. Nvidia is currently working on its next-generation GPUs for AI and HPC that will use HBM4 memory (presumably codenamed Rubin). So the company must lay its hands on next-generation high-bandwidth memory sooner rather than later.

SK hynix continues to solidify its lead in the HBM market, propelled by increased demand from the AI industry. The company supplied Nvidia with 8-Hi and 12-Hi HBM3E for the company's current-generation products and, looking ahead, SK hynix plans to launch 12-layer HBM4 next year and aims to roll out a 16-layer version by 2026, aligning with anticipated industry needs.

Initially, SK Hynix was leaning towards using 1b DRAM technology for its HBM4 layers, but Samsung's choice of the more advanced 1c production technology has reportedly prompted SK hynix to reevaluate its approach.

The upcoming HBM4 standard will introduce memory layers of 24Gb and 32Gb, along with stacking options of 4-high, 8-high, 12-high, and 16-high TSV stacks. The exact configurations of initial HBM4 modules are still uncertain, Samsung and SK hynix plan to begin mass production of 12-high HBM4 stacks in the latter half of 2025. Speed bins of these modules will vary, depending on numerous factors, but JEDEC's preliminary standards set speeds of up to 6.4 GT/s.

To manufacture base dies for its HBM4 modules, SK hynix is partnering with TSMC. At the European Technology Symposium 2024, TSMC disclosed that it would produce these base dies using its 12FFC+ (12nm-class) and N5 (5nm-class) process technologies. The N5 process will enable higher logic density and finer interconnect pitches, which will allow memory to be directly integrated into CPUs and GPUs. Alternatively, the 12FFC+ process will provide a more cost-effective solution by using silicon interposers to connect memory with host processors, striking a balance between performance and affordability.

Leading memory chip manufacturers Samsung Electronics and SK hynix are reportedly shifting their strategies to focus on high-value technologies like High Bandwidth Memory 4 (HBM4) and Compute Express Link (CXL). This move is driven by an increasingly competitive memory market, where Chinese companies are expanding their production capabilities and employing aggressive pricing strategies to capture market share.

The memory market is transforming as AI becomes a critical driver of technological progress. Traditional approaches emphasizing cost efficiency and price competition in DRAM and NAND Flash give way to a new paradigm centered around high-performance, high-value-added products.

Samsung and SK hynix’s strategic focus on high-value technologies comes in response to mounting pressure from Chinese competitors. Companies like Changxin Memory Technologies (CXMT) are rapidly expanding their production capacities, making inroads into the global memory market. According to market research firm Tech Insight, CXMT has increased its DRAM production capacity by nearly fivefold over the past four years, securing a 9% market share and becoming the world’s fourth-largest memory producer.

This expansion is backed by China's significant investment in memory technology development, a trend further accelerated by U.S. export controls on semiconductors to China. These measures have pushed Chinese firms to ramp up their production efforts and refine their pricing strategies, creating stiff competition for established players like Samsung and SK hynix.

To counter these competitive pressures, Samsung and SK hynix are doubling down on advanced memory technologies like HBM4 and CXL. These innovations offer substantial performance enhancements and are well-suited to AI-driven applications' high-demand, high-performance requirements.

Samsung recently showcased its advances in CXL technology at the OCP (Open Compute Project) Global Summit. The company plans to mass-produce a 256GB CMM-D compliant with the CXL 2.0 protocol by the end of 2024. CXL, a technology designed to enhance the efficiency and speed of data transfers between CPUs, GPUs, and memory, is poised to play a crucial role in next-generation AI and computing workloads.

Meanwhile, SK hynix has reaffirmed its commitment to producing HBM4, with plans to start mass production in the second half of 2025, followed by the launch of HBM4E in 2026. The company is also exploring the potential of hybrid bonding technology, which could provide further performance boosts. These high-end memory solutions are expected to command premium prices, differentiating Samsung and SK hynix from their lower-cost competitors.

While the shift toward high-value technologies offers opportunities, it also presents particular challenges. Developing cutting-edge memory solutions like HBM4 and CXL requires significant research and development investment. The complexity of these technologies increases the cost of production, making the competition not just about market share but about technological leadership.

Although JEDEC still needs to finalize the HBM4 specification, the industry seems to need the new memory technology as soon as possible, as demand for high-performance GPUs for AI is insatiable. To enable chip designers to build next-generation GPUs, Rambus has unveiled the industry's HBM4 memory controller IP, which surpasses the capabilities of HBM4 announced to date.

Rambus's HBM4 controller not only supports the JEDEC-specified 6.4 GT/s data transfer rate for HBM4 but also has headroom to support speeds up to 10 GT/s. This enables a memory bandwidth of 2.56 TB/s per HBM4 memory stack with a 2048-bit memory interface.

The Rambus HBM4 controller IP can be paired with third-party or customer-provided PHY solutions to create a complete HBM4 memory system.

Rambus is collaborating with industry leaders like Cadence, Samsung, and Siemens to ensure this technology integrates smoothly into the existing memory ecosystem, facilitating the transition to next-generation memory systems.

A preliminary version of JEDEC's HBM4 specification indicates that HBM4 memory will come in configurations featuring 4-high, 8-high, 12-high, and 16-high stacks supporting memory layers of 24 Gb and 32 Gb. A 16-high stack using 32 Gb layers will provide a capacity of 64 GB, allowing systems with four memory modules to reach up to 256 GB of total memory. This setup can achieve a peak bandwidth of 6.56 TB/s through an 8,192-bit interface, significantly boosting performance for demanding workloads.

If someone manages to make an HBM4 memory subsystem run at 10 GT/s, then four HBM4 stacks will provide bandwidth of over 10 TB/s. Still, support for enhanced (beyond-JEDEC) speeds enabled by Rambus and memory makers are typically offered to provide headroom and ensure stable and power-efficient operations at standard data transfer rates

"With Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission critical to meeting the real-time performance requirements of AI training and inference," said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus. "As the leading silicon IP provider for AI 2.0, we are bringing the industry’s first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators."

Since HBM4 will offer double the channel count per stack compared to HBM3, it will require a more extensive physical footprint due to a 2048-bit interface width. Also, interposers for HBM4 will be different from those for HBM3/HBM3E, which will again affect their data transfer rate potential.

Samsung is set to tape out its first HBM4 memory devices later this year with sampling set to begin in early 2025, reports nN Elec citing industry sources. The company is projected to use its latest-generation 10nm-class DRAM fabrication process to make HBM4 DRAM devices as well as its 4nm-class logic technology to produce HBM4 base dies, the report says. 

After Samsung tapes out its first HBM4 memory devices and base dies, its memory and logic fabs will have to produce and assemble them, which will take a couple of months or more. After that, Samsung will test these HBM4 stacks internally and then will start sampling them with its major customers, which in the case of HBM4 means leading producers of AI and HPC processors. Samsung declined to comment on its HBM4 timeline. Samsung may start mass production of HBM4 by late 2025, though it remains to be seen when actual products using the technology emerge. 

The company is set to use its latest-generation 10nm-class DRAM fabrication process (10c nm, 12nm) to make HBM4 memory layers as well as its 4nm-class logic production node to make HBM4 base dies with a 2048-bit interface, the report claims. Base dies made on such a fine manufacturing technology can be installed directly on processors using Samsung's own SAINT-D or similar techniques. 

The upcoming HBM4 standard will define 24 Gb and 32 Gb layers as well as 4-high, 8-high, 12-high, and 16-high TSV stacks. It is hard to predict the configuration of Samsung's initial HBM4 modules, though the report says that the company would mass produce 12-High HBM4 stacks in the second half of next year. Speed bins of these modules will depend on multiple factors, though JEDEC's preliminarily settled speed bins reach up to 6.4 GT/s.

Samsung's arch-rival SK Hynix is also set to mass produce HBM4 in the second half of the year, the report says, though it does not disclose when SK Hynix's HBM4 sampling is set to start. While SK Hynix initially leaned towards using 1b DRAM technology for HBM4 memory layers, Samsung's decision to go with 1c production has prompted reconsideration, according to The Elec. 

SK hynix will collaborate with TSMC to build base dies for its HBM4 memory modules. At the European Technology Symposium 2024, TSMC revealed plans to produce these base dies using its advanced 12FFC+ (12nm-class) and N5 (5nm-class) process technologies. TSMC's N5 logic technology will allow for denser logic integration and finer interconnection pitches to place memory directly on CPUs and GPUs. By contrast, base dies made with TSMC's 12FFC+ process will enable cost-effective base dies that use silicon interposers to connect memory to host processors.

SK hynix has inked a memorandum of understanding with the U.S. Department of Commerce to secure up to $450 million in direct funding and access to $500 million in loans under the CHIPS and Science Act to build its advanced memory packaging facility in West Lafayette, Indiana. If the project becomes a success, then the U.S. will have its own supply of high-bandwidth memory (HBM), which is crucial for AI and HPC processors.

If SK hynix proceeds with its project, the advanced packaging facility is set to begin operations in 2028 and will generate up to 1,000 jobs. With an estimated cost of $3.87 billion, this plant will rank among the largest advanced packaging facilities worldwide. But the project is impossible to complete without U.S. government support of up to $450 million in direct funding and access to $500 million in loans. Additionally, SK hynix intends to seek a tax benefit of up to 25% of the qualified capital expenditures through the Investment Tax Credit program.

Given the timeline of SK hynix's Indiana advanced packaging facility, the fab will likely produce HBM4 or rather HBM4E memory, which will require quite sophisticated packaging techniques. In particular, some HBM4/HBM4E devices will be integrated with processors using advanced interposers, others will be planted directly onto processors, which will require strong technological capabilities.

Building and integrating HBM4/HBM4E memory in the U.S. is strategically important both for SK hynix and for the U.S. government (as part of its broader initiative to bolster the U.S. semiconductor industry and to produce advanced processors in the U.S.), so both parties are inclined to build this packaging facility. It should be noted that actual memory devices (HBM4 layers) will still be made by SK hynix outside of the U.S., in South Korea.

In addition to producing HBM4 memory (and successors) in Indiana, SK hynix also plans to partner with local research institutions, including Purdue University, to advance semiconductor research and development in general and advanced chip packaging in particular.

"We deeply appreciate the U.S. Department of Commerce's support and are excited to collaborate in seeing this transformational project fully realized," said Kwak Noh-Jung, SK hynix CEO in a press release. "We are moving forward with the construction of the Indiana production base, working with the State of Indiana, Purdue University and our U.S. business partners to ultimately supply leading-edge AI memory products from West Lafayette. We look forward to establishing a new hub for AI technology, creating skilled jobs for Indiana and helping build a more robust, resilient supply chain for the global semiconductor industry."

On Friday, the JEDEC Association published preliminary specifications for the 4th Generation high-bandwidth memory (HBM4) as it is getting closer to completing the HBM4 DRAM standard. As reported, the new spec supports a 2048-bit interface per stack amid a lower data transfer rate than HBM3E. In addition, HBM4 supports a broader range of memory layers to make the new memory better address different types of applications.

The new HBM4 standard will specify 24 Gb and 32 Gb layers and offer configurations for 4-high, 8-high, 12-high, and 16-high TSV stacks. The committee has initially agreed on speed bins up to 6.4 GT/s, with ongoing discussions about achieving an even higher data transfer rate.

A 16-Hi stack based on 32 Gb layers will offer a capacity of 64 GB, which means that a processor with four memory modules can support 256 GB of memory with a peak bandwidth of 6.56 TB/s using an 8,192-bit interface.

Although HBM4 will feature a doubled channel count per stack compared to HBM3 and a larger physical footprint to ensure compatibility, a single controller can work with HBM3 and HBM4. However, different interposers will be needed to accommodate the various footprints. What is noteworthy is that JEDEC did not say anything about integrating HBM4 memory directly on processors, and that is perhaps the most intriguing part about the new type of memory.

Earlier this year, SK hynix and TSMC announced a collaboration to develop HBM4 base dies. Later on, at the European Technology Symposium 2024, TSMC confirmed it would use its 12FFC+ (12nm-class) and N5 (5nm-class) process technologies to manufacture these dies.

 TSMC's N5 process allows for more integrated logic and features, with interconnection pitches from 9 to 6 microns, which is crucial for on-die integration. The 12FFC+ process, derived from TSMC's 16nm FinFET technology, will enable the production of cost-effective base dies that connect memory to host processors using silicon interposers.

HBM4 is primarily designed to meet the demands of generative AI and high-performance computing, which require handling large datasets and performing complex calculations efficiently. Therefore, we are hardly going to see HBM4 on client applications, such as graphics cards.

Samsung is set to introduce 3D packaging services for high-bandwidth memory (HBM) this year, according to a report from the Korea Economic Daily that cites the company's announcement at the Samsung Foundry Forum 2024 in San Jose, as  well as 'industry sources.' The 3D packaging for HBM essentially paves the way for HBM4 integration in late 2025 – 2026, but we are not sure what kind of memory Samsung is set to package this year. 

For 3D packaging, Samsung has a platform called SAINT (Samsung Advanced Interconnect Technology) that includes three distinct 3D stacking technologies: SAINT-S for SRAM, SAINT-L for logic, and SAINT-D for DRAM stacking on top of logic chips like CPUs or GPUs. The company has been working on SAINT-D for several years (and formally announced it in 2022) and it looks like the technology will be ready for prime time this year, which will be a notable milestone for the world's largest memory maker and a leading foundry. 

Samsung's new 3D packaging method involves stacking HBM chips vertically on top of processors, which differs from the existing 2.5D technology that connects HBM chips and GPUs horizontally via a silicon interposer. This vertical stacking approach eliminates the need for the silicon interposer but requires a new base die for HBM memory that is made using a sophisticated process technology. 

The 3D packaging technology offers significant benefits for HBM, including faster data transfers, cleaner signals, reduced power consumption, and lower latencies, but at relatively high packaging costs. Samsung plans to offer this advanced 3D HBM packaging as a turnkey service, where its memory business division produces HBM chips, and the foundry unit assembles actual processors for fabless companies. 

What remains unclear is what exactly Samsung plans to offer with SAINT-D this year. Putting HBM on a logic die requires an appropriate chip design and we are not aware of any processors from well-known companies that are designed to hold HBM on top and are set to launch in 2024 – 1H 2025.

Looking ahead, Samsung aims to introduce all-in-one heterogeneous integration technology by 2027. This future technology will enable the integration of two layers of logic chips, HBM memory (on interposer), and even co-package optics (CPOs).

Earlier this year SK hynix and TSMC announced a collaboration to develop and build base dies for HBM4 memory, but refrained from revealing any official details. At the European Technology Symposium 2024 this week, TSMC said that it would build HBM4 base dies using its 12FFC+ (12nm-class) and N5 (5nm-class) process technologies, reports AnandTech. The use of such advanced nodes will enable HBM4 to offer unprecedented performance and energy efficiency. 

"We are working with key HBM memory partners (Micron, Samsung, SK hynix) over advanced nodes for HBM4 full stack integration," said the Senior Director of Design and Technology Platform at TSMC. "12FFC+ cost effective base die can reach HBM for performance and N5 base die can provide even more logic with much lower power at HBM4 speeds."

TSMC's N5 process technology is currently one of the most advanced production nodes available. It is used to make some of the best CPUs and best GPUs, so using it for memory is a big deal. What such an advanced node allows is to pack more logic and features into the HBM4 base die as well as enable very fine interconnection pitches (we are talking about pitches from 9 to 6 microns), which are essential for direct bonding on logic chips, thus boosting memory performance for AI and HPC processors.

Base dies made on TSMC's 12FFC+ process (derived from the company's established 16nm FinFET technology) will enable to build 12-Hi and 16-Hi HBM4 memory stacks that will offer capacities of 48 GB and 64 GB, respectively. Use of 12FFC+ will enable 'cost effective' base dies that will use silicon interposers to connect memory to host processors.

TSMC's Production Nodes for HBM4 Base Dies

TSMC is also optimizing its packaging technologies, particularly CoWoS-L and CoWoS-R, to support HBM4 integration. These advanced packaging methods enable the building of interposers of up to eight reticle sizes and facilitate the assembly of up to 12 HBM4 memory stacks. New interposers will feature up to eight layers to ensure efficient routing of more than 2,000 interconnects while maintaining proper signal integrity. By now, experimental HBM4 memory stacks have reached data transfer rates of 6 GT/s at 14mA, according to a TSMC slide. 

"We are also optimizing CoWoS-L and CoWoS-R for HBM4," the TSMC representative said. "Both CoWoS-L and CoWoS-R [use] over eight layers to enable HBM4's routing of over 2,000 interconnects with [proper] signal integrity. We collaborate with EDA partners like Cadence, Synopsys, and Ansys to certify HBM4 channel signal integrity, IR/EM, and thermal accuracy."

TSMC's collaborative efforts with leading memory producers like Micron, Samsung, and SK hynix, as well as EDA partners including Cadence, Synopsys, and Ansys, are crucial to enable HBM4 memory subsystems a few years down the road. 

SK hynix late on Wednesday announced that it had decided to build its new advanced memory packaging facility in Indiana, which will start operations in the second half of 2028. Given the timeline, the facility will almost certainly work on HBM4 and HBM4E memory products. In addition, SK hynix inked an R&D deal with Purdue University.

The advanced memory packaging facility will require roughly $3.87 billion in investments from SK hynix and is said to come online sometime in the back half of 2028. The plant will not process wafers with memory circuits, but will get them from elsewhere (presumably from SK hynix's South Korean fabs), and then assemble HBM from known good stacked dies (KGSDs) consisting of multiple memory dies on top of a base die.  

HBM memory is used on some of the most advanced processors for AI and HPC, including AMD's Instinct MI300-series and Nvidia's H100/H200 and B100/B200-series products. Having an HBM packaging facility in the U.S. will make the supply chain of high-bandwidth memory somewhat more resilient, but SK hynix will keep making HBM memory devices in South Korea, based on the company's current announcements. 

The expected cost of the fab greatly exceeds the costs of packaging facilities built by Intel and TSMC (around $3 billion), so the SK hynix facility in Indiana will be among the most advanced semiconductor packaging plants in the world when it comes online. Meanwhile, given that HBM4 and HBM4E memory stacks will feature a 2048-bit interface, their packaging will be considerably more complex than the packaging of existing HBM3/HBM3E, which is why SK hynix will require very sophisticated packaging tools. Also, heterogeneous integration of HBM4/HBM4E with logic processors will require advanced equipment, too. 

"We are excited to become the first in the industry to build a state-of-the-art advanced packaging facility for AI products in the United States that will help strengthen supply-chain resilience and develop a local semiconductor ecosystem," said SK hynix CEO Kwak Noh-Jung. "With this new facility, we hope to advance our goal of providing AI memory chips with unmatched capabilities, serving the needs of our customers."

The plant will be located in West Lafayette, Indiana, which seems a somewhat strange place to build an advanced memory packaging facility. SK hynix says that the location was chosen because of Indiana's robust industrial infrastructure: an R&D ecosystem led by Purdue University and Ivy Tech Community College; the presence of experts in the semiconductor field; availability of skilled talent from Purdue University; and significant support offered by state and local governments. 

Also, SK hynix intends to collaborate with Purdue University for future research and development (R&D) projects. Furthermore, West Lafayette, Indiana, is located about 250 miles west of Columbus, Ohio, where Intel is building its Silicon Heartland production site that will consist of multiple fab phases and will require investments of over $100 billion to be fully built. Also, Intel has an advanced chip packaging facility in Arizona, whereas TSMC is expected to construct its own advanced logic packaging facility in the same state, eventually. 

To ensure that it will have enough qualified engineers at its advanced memory packaging facility, SK hynix intends to work in partnership with Purdue University and Ivy Tech Community College to create training programs and multidisciplinary degree courses aimed at nurturing a skilled workforce in high-tech fields and establishing a consistent stream of emerging talent. 

"SK hynix is the global pioneer and dominant market leader in memory chips for AI," Purdue University President Mung Chiang said. "This transformational investment reflects our state and university's tremendous strength in semiconductors, hardware AI, and hard tech corridor. It is also a monumental moment for completing the supply chain of digital economy in our country through chips advanced packaging. Located at Purdue Research Park, the largest facility of its kind at a U.S. university will grow and succeed through innovation."

SK hynix is planning to build a $4 billion chip packaging facility in West Lafayette, Indiana, reports the Wall Street Journal. The fab is set to start operations in 2028 and create up to 1,000 jobs. This move, potentially backed by state and federal tax breaks, is part of SK hynix's efforts to strengthen its positions as a manufacturer of non-commodity memory.

The investment in the Indiana facility represents a strategic step for SK hynix to improve its advanced chip packaging capabilities. Such advanced memory packaging technologies could be used to build high-bandwidth memory, which is an important ingredient in many artificial intelligence and high-performance computing applications.

"[SK hynix] is reviewing its advanced chip packaging investment in the U.S., but hasn’t made a final decision yet," a company spokeswoman told the WSJ.

If the project gets the greenlight from SK hynix, the advanced pacakaging facility will start operations in 2028 and will create up to 1,000 jobs. Given the planned cost of the fab — $4 billion — the plant will be one of the world's largest advanced packaging facilities. Government support is crucial for this investment, with possible state and federal tax incentives, the report says. These incentives are part of a larger effort to strengthen the U.S. semiconductor industry and reduce reliance on foreign suppliers.

SK hynix is one of the suppliers of HBM memory to Nvidia, which builds AI GPUs that are vital for powering advanced AI services like ChatGPT. The recently revealed Nvidia Blackwell B200 will use eight HBM3e chips per GPU. This collaboration highlights SK hynix's role in the supply chain of critical components for the AI industry.

The broader context of this investment highlights the U.S. government's efforts to advance domestic chipmaking capabilities using initiatives like the CHIPS and Science Act. This act, which recently provided $8.5 billion in direct government funding to Intel, is instrumental for enhancing the U.S. semiconductor industry's competitiveness, especially amid rising competition and trade wars with China. SK hynix's planned facility in Indiana is a significant development in this context, contributing to the growth and resilience of the U.S. semiconductor sector.

Government funding for various domestic chip manufacturing and packaging endeavors has been a bit sluggish, so the current situation represents more of a statement of intent rather than a finalized deal. Whether it will move on to the construction phase remains to be seen.

China-based Wuhan Xinxin Semiconductor Manufacturing (XMC) is kicking off a project focused on developing and manufacturing high-bandwidth memory (HBM), as this type of DRAM is a crucial element for AI and HPC processors, reports DigiTimes. XMC is controlled by Yangtze Memory Technology Co. (YMTC), China's leading producer of 3D NAND, which is controlled by state-owned Tsinghua Unigroup, which means that China's government is behind the effort.

XMC, which produces logic, CIS, and NOR flash memory and is an integral part of YMTC's 3D NAND production, has reportedly issued invitations for bids to build assembly lines and develop sophisticated packaging technology for its HBM initiative. The project plans to employ 3D chip stacking technology and acquire 16 sets of equipment to reach a monthly production target of 3,000 wafers. Meanwhile, XMC is not even a member of the JEDEC standard-setting organization, which means that it formally cannot access or use HBM specifications. The good news, though, is that its owner, YMTC, is.

Yangtze Memory uses fabs originally built by XMC to make both 3D NAND memory cells using memory-oriented process technology and 3D NAND periphery logic (address decoding, page buffers, etc.) using a production node aimed at high-performance logic. This is how it manages to make 3D NAND chips with ultra-fast I/O ahead of all of its rivals.

Presumably, Tsinghua Unigroup decided it makes sense for XMC (or YMTC?) to enter the HBM business. This move signifies a strong effort by China's government to accelerate the domestic development of HBM technology and become self-sufficient in high-speed memory for its AI and HPC processors.

XMC is not the only company in China that is interested in producing HBM memory. For example, CXMT has been exploring HBM technology in general for some time (we first reported about it in August and then more recently in February).

DigiTimes claims that about 20 companies from the People's Republic, including material suppliers and packaging houses, are eyeing a slice of the HBM pie. Technology is complex, and competition is fierce, but there is much money to make, especially with high demand and rising prices.

Major Chinese packing companies like JECT, Tongfu Microelectronics, JCET, and SJ Semiconductor already have HBM packaging technology. JECT recently showed off its XDFOI high-density fan-out package solution, which is designed for HBM. Tongfu Microelectronics has reportedly teamed up with a significant Chinese DRAM maker (presumably CXMT) to work on HBM projects.

HBM4 memory is expected to drastically increase peak memory bandwidth thanks to its 2048-bit interface, which will be very useful for bandwidth-hungry artificial intelligence (AI) and high-performance computing (HPC) processors. But HBM4 will require a lot of changes to how high-bandwidth memory is made and integrated, which requires an even closer collaboration between logic foundries and memory makers. TSMC and SK Hynix certainly know that, which is why they reportedly formed an alliance to co-produce HBM4. 

Maeil Business News Korea reports that TSMC and SK Hynix have formed the so-called AI Semiconductor Alliance that will combine the strengths of both companies in their respective field and align their strategies under the 'one-team strategy' principle. The report says that TSMC will handle 'some of HBM4' processes, which most likely means producing HBM4 base dies using one of its advanced process technologies that SK Hynix does not have. This corroborates with an earlier report claiming that HBM4 will require base dies made on a 12nm-class production node. Another report claims that SK Hynix and Nvidia are working on a technology that would stack HBM memory directly on top of processors without a substrate. 

Bot collaboration over HBM4 base dies is not the only aspect of TSMC's and SK Hynix's joint work. As part of its 3DFabric Memory Alliance, TSMC is working with all three makers of HBM, including Micron, Samsung, and SK Hynix. When it comes to SK Hynix, the companies are collaborating on CoWoS packaging for HBM3 and HBM4, Design Technology Co-Optimization (DTCO) for HBM, and even UCIe for HBM physical interface, according to a TSMC presentation demonstrated last year. 

One of the reasons for the collaboration between TSMC and SK Hynix is that they need to work very closely to ensure that HBM3E and HBM4 memory from SK Hynix works with chips made by TSMC. After all, SK Hynix leads the HBM market, whereas TSMC is the world's largest foundry. 

Meanwhile, Maeil Business News Korea also notes that the collaboration between TSMC and SK Hynix is meant to 'to establish a united front against Samsung Electronics,' which competes against both companies as it makes logic and memory chips. Reports like this are not uncommon and should be taken with a grain of salt. It is hard to imagine that TSMC would intentionally limit the compatibility of its packaging technologies to SK Hynix's memory, so it is likely that TSMC and SK Hynix are simply working a little deeper together than TSMC does with Samsung.

HBM3E memory with a whopping 9.6 GT/s (9.6 gigatransfers, or billions of transfers a second, a typical measurement of memory bandwidth) data transfer rate over a 1024-bit interface has just hit mass production. But the demands of artificial intelligence (AI) and high-performance computing (HPC) industries are growing rapidly, so HBM4 memory with a 2048-bit interface is just about two years away. A vice president of SK Hynix recently said that his company is on track to mass produce HBM4 by 2026, reports Business Korea.

"With the advent of the AI computing era, generative AI is rapidly advancing," said Chun-hwan Kim, vice president of SK hynix, said at SEMICON Korea 2024. "The generative AI market is expected to grow at an annual rate of 35%." 

The rapid growth of the generative AI market calls for higher-performance processors, which in turn need higher memory bandwidth. As a result, HBM4 will be needed to radically increase DRAM throughput. SK Hynix hopes to start making next-generation HBM by 2026, which suggests late 2025. This somewhat corroborates Micron's plan to make HBM4 available in early 2026. 

With a 9.6 GT/s data transfer rate, a single HBM3E memory stack can offer a theoretical peak bandwidth of 1.2 TB/s, translating to a whopping 7.2 TB/s bandwidth for a memory subsystem consisting of six stacks. However, that bandwidth is theoretical. For example, Nvidia's H200 'only' offers up to 4.8 TB/s with H200, perhaps due to reliability and power concerns.

According to Micron, HBM4 will use a 2048-bit interface to increase theoretical peak memory bandwidth per stack to over 1.5 TB/s. To get there, HBM4 will need to feature a data transfer rate of around 6 GT/s, which will allow to keep the power consumption of next-generation DRAM in check. Meanwhile, a 2048-bit memory interface will require a very sophisticated routing on an interposer or just placing HBM4 stacks on top of a chip. In both cases, HBM4 will get more expensive than HBM3 and HBM3E.

SK Hynix's sentiment regarding HBM4 seems to be shared by Samsung, which says it is on track to produce HBM4 in 2026. Interestingly, Samsung is also developing customized HBM memory solutions for select clients.

"HBM4 is in development with a 2025 sampling and 2026 mass production timeline," said Jaejune Kim, Executive Vice President, Memory, at Samsung, at the latest earnings call with analysts and investors (via SeekingAlpha). "Demand for also customized HBM is growing, driven by generative AI and so we're also developing not only a standard product, but also a customized HBM optimized performance-wise for each customer by adding logic chips. Detailed specifications are being discussed with key customers."

ChangXin Memory Technologies (CXMT), China's leading domestic DRAM maker, plans to build high-bandwidth memory (HBM) used by AI and high-performance computing (HPC) processors, reports Nikkei. The company is currently procuring necessary equipment, so it isn't going to roll out its HBM products for another year or two, but the effort to compete against established players in the top league emphasizes how badly China wants self-sufficiency in memory. 

According to Nikkei's sources, CXMT has placed orders and obtained manufacturing and testing gear for HBM memory assembly and testing from suppliers in the U.S. and Japan. Notably, top U.S. equipment makers, such as Applied Materials and Lam Research, were granted export licenses by the U.S. authorities to export fab tools to the Chinese chip manufacturer in mid-2023, as reported by two Nikkei informants. 

HBM3 stacks eight or 12 memory devices with wide interfaces on top of each other, interconnects them using through silicon vias (TSVs), and then places them on a base logic die that uses a 1024-bit interface to connect to a host processor at an unmatched bandwidth. While the architecture seems simple enough in general, it is not by far, and making HBM is a complicated task. 

Production of HBM known good stack dies (KGSDs) is fundamentally different from making traditional memory devices as HBM makers have to produce memory devices and test them, produce a base die and test it, assemble the package, and connect all the ICs with TSVs, and then test the whole stack. It takes a lot of tools and expertise to produce HBM DRAM, but this type of memory beats everything on the market in terms of bandwidth and in terms of power efficiency. 

CXMT is already running one DRAM fab near Hefei, China, and is raising money to build the second one. The second Hefei plant is believed to adopt more sophisticated process technologies (albeit behind leading offerings from Micron, Samsung, and SK Hynix) and will likely also be used to build HBM DRAM devices and packages. Meanwhile, CXMT has yet to develop its own HBM production and packaging technologies. Furthermore, some of China's chipmakers are still developing technologies to integrate HBM with logic chips (such as TSMC's CoWoS). One of SMIC's executives said a few years ago that the company would have to develop advanced packaging nodes, so it is likely that, by now, the company has gathered enough know-how in this direction. 

"When your DRAM technology already lags behind global rivals, that puts your HBM technology at a disadvantage to be competitive in a fully commercial market," Brady Wang, a semiconductor analyst with Counterpoint, told Nikkei. "Not to mention that HBM production requires complex design and manufacturing expertise to materialize. […] It could be a steep climb." 

One thing to note here is that while current HBM3 and HBM3E with a 1024-bit interface use interposers to connect to host processors, many industry experts indicate that HBM4 with its 2048-bit interface will need to be placed directly on host processors, which will further complicate production, but will bring performance and power efficiency further. It is unclear whether CXMT is developing HBM3, HBM3E, or HBM4E products. Still, we would expect the firm to start from HBM3/HBM3E, which will not enable it to challenge Micron, Samsung, and SK Hynix in the next few years, but it will likely be good enough to fulfill some of China's domestic needs.  

CXMT's efforts to secure crucial equipment for HBM production highlight the company's plan to compete in the lucrative AI computing market. Meanwhile, financing the effort (part of CXMT's second fab project) by investors backed by local governments can be considered a part of China's broader strategy to mitigate the impact of U.S. export controls and reduce dependency on foreign technologies. 

Today, TrendForce shed some light on the future of high bandwidth memory (HBM) technology and HBM4, specifically, which is expected to debut in 2026. This upcoming technology promises to extend its interface to 2048 bits and substantially change the architecture. TrendForce claims that HBM4 will significantly depart from traditional standardized DRAM technologies to more customized solutions. 

HBM4 will be the first to use a 12nm logic process technology for its base die, which foundries, not DRAM makers, will now make. This development will be a collaborative effort between foundries and memory suppliers, which essentially means a symbiotic relationship to advance high-speed memory technology. The increased performance and enhanced feature set of HBM4 are tailored to meet the demands of future processors for artificial intelligence (AI) and high-performance computing (HPC) from key industry players such as AMD, Nvidia, and Intel. 

The shift towards customization in the HBM4 market is a crucial aspect identified by TrendForce. This deviates from the traditional, standardized approach of commodity DRAM, which signifies a major shift in the industry. Buyers are increasingly seeking custom specifications and are exploring innovative options, such as stacking HBM directly on top of the system-on-chips (SoCs).

This trend towards customization is expected to bring new design and pricing strategies to the HBM industry. As memory technology becomes more specialized and tailored to specific needs, it paves the way for a new HBM technology era characterized by innovation, specialization, and a departure from the one-size-fits-all approach today. This evolution in HBM4 and beyond indicates a dynamic and rapidly advancing landscape in high-speed memory technology.

Another standout feature of HBM4 is its transition from the current 12-layer (12Hi) stacks to more advanced 16-layer (16Hi) stacks, increasing memory module capacity. This transition, expected to be completed by 2027, will necessitate using new hybrid bonding techniques to increase layer count while maintaining the integrity of the memory stacks. 

But while HBM4 will revolutionize the memory market, it is still years away. As a result, HBM3E is going to have quite a long lifespan. 

SK Hynix has started recruiting design personnel for logic semiconductors such as CPUs and GPUs, reports Joongang.co.kr. The company is apparently looking to stack HBM4 directly on processors, which will not only change the way logic and memory devices are typically interconnected but will also change the way they are made. In fact, if SK Hynix succeeds, this may transform the foundry industry.

Nowadays HBM stacks integrate 8, 12, or 16 memory devices as well as a logic layer that acts like a hub. HBM stacks are placed on the interposer next to CPUs or GPUs and are connected to their processors using a 1,024-bit interface. SK Hynix aims to put HBM4 stacks directly on processors, eliminating interposers altogether. To some degree, this approach resembles AMD's 3D V-Cache, which is placed directly on CPU dies. But HBM will feature considerably higher capacities and will be cheaper (albeit slower).

SK Hynix is reportedly discussing its HBM4 integration design method with several fabless companies, including Nvidia. It's likely that the two companies will jointly design the chip from the beginning and produce it at TSMC, who will also put SK Hynix's HBM4 device on logic chips using a wafer-bonding technology. A joint design is inevitable in order for memory and logic semiconductors to work as one body on the same die. 

The HBM4 memory will use a 2,048-bit interface to connect to host processors, so interposers for HBM4 will be extremely complex and expensive. This makes the direct connection of memory and logic economically feasible. But while placing HBM4 stacks directly on logic chips will somewhat simplify chip designs and cut costs, this presents another challenge: thermals.

Modern logic processors, such as Nvidia's H100, consume hundreds of watts of power and dissipate hundreds of watts of thermal energy. HBM memory is also rather power-hungry. So cooling down a package containing both logic and memory could require very sophisticated methods, including liquid cooling and/or submersion.

"If the heating problem is solved two to three generations later than now, HBM and GPU will be able to operate like one body without an interposer," said Kim Jung-ho, a professor in the Department of Electrical and Electronics at KAIST.

But the integration of memory directly on processors will also change how chips are designed and made. Producing DRAM using the same process technology as logic and on the same fab will guarantee ultimate performance, but will increase memory costs dramatically, so this is not an option that is seriously considered right now. Nonetheless, it looks like memory and logic are poised to get closer, both literally and on the process technology level. 

"Within 10 years, the 'rules of the game' for semiconductors may change, and the distinction between memory and logic semiconductors may become insignificant," an industry insider told Joongang.co.kr.

Micron on Thursday introduced its new 128GB DDR5-8000 RDIMM memory modules based on monolithic 32Gb DRAM ICs aimed at servers and shared its vision for future high-performance and high-capacity memory technologies set to arrive over the next five years. The company also shared a roadmap that includes several technologies not previously discussed publicly, including 256 GB DDR5-12800 sticks, HBM4E, CXL 2.0, and LPCAMM2.

Bandwidth Hungry Applications

When it comes to bandwidth-hungry applications, Micron expects them to keep using HBM and GDDR types of memory in the coming years. 24GB 8-Hi HBM3E stacks are set to arrive in early 2024 and offer bandwidth of over 1.2 TB/s per stack, which is set to tangibly increase the performance of AI training and inference. The company plans to refine its HBM3E lineup with 36GB 12-Hi HBM3E stacks by 2025, which will further increase memory capacity for HBM-supporting processors, but will not boost bandwidth. For example, Nvidia's H100 could use 216GB of HBM3E memory if the company had these stacks. In 2025, they would be used by a post-Blackwell GPU for AI and HPC compute. 

The true revolution for HBM will be HBM4, which is set to arrive by 2026. These stacks will feature a 2048-bit interface, requiring memory, processor, and packaging makers to work together closely to make it work properly. Yet, the reward promises to be quite tangible as each stack is expected to feature bandwidth of over 1.5 TB/s. As for capacity, Micron envisions 36GB to 48GB 12-Hi and 16-Hi stacks in the 2026 to 2027 timeframe. HBM4 will be followed by HBM4E in 2028, according to Micron. The extended version of HBM4 is projected to gain clocks and increase bandwidth towards 2+ TB/s and capacity to 48GB to 64GB per stack. 

HBM will remain the prerogative of the most expensive and bandwidth-demanding applications. Cheaper products, such as AI accelerators for inference and graphics cards, will keep using GDDR. Based on Micron's roadmap, the next version of GDDR — GDDR7 — is set to arrive by late 2024, boasting a data transfer rate of 32 GT/s (128 GB/s bandwidth per device) and capacities of 16 to 24Gb. As GDDR7 becomes more mature, it will speed up to 36 GT/s (144GB/s bandwidth per device) and gain per IC capacities higher than 24Gb (think 32Gb, 48Gb) sometime in late 2026.

Capacity

Servers need memory, and Micron's 128 GB DDR5-8000 RDIMM is just the beginning of Micron's 32Gb DRAM ICs. Expect the company to come up with more products based on these devices. 

In a bid to bring together capacity and performance, Micron expects to offer 128GB – 256GB MCRDIMM modules with a data transfer rate of 8800 MT/s in 2025, and then MRDIMMs with capacities of over 256GB and a data transfer rate of 12800 MT/s in 2026 or 2027.

For machines that need further memory expansion, Micron is poised to ship CXL 2.0-supporting expanders featuring 128GB – 256GB capacities and up to 36 GB/s of bandwidth over a PCIe interface. These will be followed by CXL 3.x-compliant expanders with over 72 GB/s of bandwidth and capacities of over 256 GB.

Low Power

For low-power applications, the industry will keep using LPDDR memory and based on Micron's roadmap, LPDDR5X with 8533 MT/s or 9600 MT/s data transfer rates will stay with us for a while. Meanwhile, for laptops and other applications that benefit from memory on modules, Micron is set to offer LPDDR5X-8533 16 to 128GB LPCAMM2 modules starting in 2025, and then LPDDR5X-9600 LPCAMM modules with capacities of 192GB and higher starting in mid-2026.

We've heard about HBM4 memory several times over the past few months, and this week Samsung revealed that it expects HBM4 to be introduced by 2025. The new memory will feature a 2048-bit interface per stack, twice as wide as HBM3's 1024-bit.

"Looking ahead, HBM4 is expected to be introduced by 2025 with technologies optimized for high thermal properties in development, such as non-conductive film (NCF) assembly and hybrid copper bonding (HCB)," SangJoon Hwang, EVP and Head of DRAM Product and Technology Team at Samsung Electronics, wrote in a company blog post.

Although Samsung expects HBM4 to be introduced by 2025, its production will probably start in 2025–2026, as the industry will need to do quite a lot of preparing for the technology. In the meantime, Samsung will offer its customers its HBM3E memory stacks with a 9.8 GT/s data transfer rate that will offer bandwidth of 1.25 TB/s per stack.

Earlier this year Micron revealed that 'HBMNext' memory was going to emerge around 2026, providing per-stack capacities between 32GB and 64GB and peak bandwidth of 2 TB/s per stack or higher — a marked increase from HBM3E's 1.2 TB/s per stack. To build a 64GB stack, one will need a 16-Hi stack with 32GB memory devices. Although 16-Hi stacks are supported even by the HBM3 specification, nobody has announced such products so far and it looks like such dense stacks will only hit the market with HBM4.

To produce HBM4 memory stacks, including 16-Hi stacks, Samsung will need to polish off a couple of new technologies mentioned by SangJoon Hwang. One of these technologies is called NCF (non-conductive film) and is a polymer layer that protects TSVs at their solder points from insulation and mechanical shock. Another is HCB (hybrid copper bonding), which is a bonding technology that uses copper conductor and oxide film insulator instead of conventional solder to minimize distance between DRAM devices as well as enable smaller bumps required for a 2048-bit interface.

The Japanese Ministry of Economy, Trade, and Industry is increasing its subsidies for Micron's fab in Hiroshima from $320 million to $1.29 billion, according to a Nikkei report. The increase ensures that the company builds its fab on time. For the Japanese government, the grant is a part of a broader plan encompassing several billion yen invested in various chip companies designed to enhance Japan's semiconductor prowess. 

Micron secured $320 million in funding for its fab in Hiroshima almost exactly a year ago. Meanwhile, Micron's total investments in the new production facility were meant to be about ¥500 billion ($3.618 billion). While $320 million is a lot of money, it might not be enough given Micron's reduced capital expenditures compared to 2022 levels. As a result, it looks like Micron and the Japanese government have reached an agreement to increase subsidies, according to Nikkei.  

Micron aims to initiate high-volume manufacturing of sophisticated memory chips using its 1γ process (its 3rd Generation 10nm-class node) that relies on extreme ultraviolet (EUV) lithography by 2026, so the company needs money as soon as possible. 

The Ministry's vision is not limited to Micron. A sweeping budget of ¥2 trillion ($13.385 billion), spread over two years, is reserved explicitly for subsidies related to semiconductor investments. Casting the net wider, Taiwan's TSMC will receive up to ¥476 billion ($3.1857 billion) for its fab operations in Kumamoto. Additionally, a collaborative effort between Kioxia and the U.S-based Western Digital in Mie prefecture is backed by a subsidy worth ¥92.9 billion ($621.72).

This significant financial infusion into semiconductor companies underscores Japan's commitment to decreasing its reliance on overseas chip suppliers and rebuilding its domestic semiconductor sector. Japan aims to circumvent potential risks linked with international supply chain interruptions by strengthening domestic capabilities, thereby ensuring a smooth and robust internal supply of critical technological components.

High-bandwidth memory (HBM) has come a long way in less than 10 years it has been on the market. It dramatically increased its data transfer rate, increased capacity by orders of magnitude, and gained a plethora of features. There is another major change incoming and this one is going to be drastic: next generation HBM4 memory stacks will feature a 2048-bit memory interface, according to a DigiTimes report citing Seoul Economy.

Increasing interface width from 1024-bit per stack to 2048-bit per stack will be the biggest change HBM memory technology has ever seen. Since 2015, all HBM stacks have featured a 1024-bit interface. But since the information comes from an unofficial source, it should be taken with a grain of salt.

It is unclear whether memory makers will be able to maintain a ~9 GT/s data transfer rates supported by HBM3E stacks for HBM4 stacks with a 2048-bit interface, but if they can, the increase in bus width will double peak bandwidth from 1.15 TB/s per stack to 2.30 TB/s per stack. It is also unclear how widening of a per-stack memory interface will affect the number of stacks that a processor and interposer will handle. 

Today's massive processors such as Nvidia's H100 support six 1024-bit wide HBM3/HBM3E known good stacked dies (KGSDs) using a massive 6144-bit wide interface, But if the interface of a single KGSD increases to 2048 bits, it remains to be seen whether processor developers will keep using the same number of HBM4 stacks, or reduce them.

There is also a concern that yields of KGSDs with a 2048-bit interface will decrease as it is harder to produce memory stacks with thousands of through silicon vias (TSVs), but the report says that Samsung and SK Hynix are confident that they will be able to achieve a '100%' yield with the new type of memory.

For now, memory stacks with a 2048-bit interface look pretty fantastic and we would consider this information with caution. Yet, there is no smoke without fire.

Having understood the importance of the local semiconductor supply chain for long-term homegrown microelectronics industry development, the Japanese government kicked off a program to subsidize local chipmakers. On the heels of its $680 million subsidy for Kioxia and Western Digital in July, the Japanese govt announced plans to support Micron's Hiroshima operations with ¥46.5 billion ($320 million). This cash infusion might help Micron bring extreme ultraviolet (EUV) lithography to Japan.

Micron will receive the funding from Japan's Ministry of Economy, Trade and Industry, reports Bloomberg. However, the conditions that Micron must meet to get the subsidy were unavailable via the ministry's website at the time of writing. The grant will help Micron 'mass produce cutting-edge memory chips' at its fabs near Hiroshima, Japan, which the company obtained when it acquired Elpida in 2013.

Micron produces a significant portion of its DRAM products at its site near Hiroshima, Japan, and runs important R&D operations in the country. To keep DRAM fabs up-to-date, Micron and other memory makers must constantly install new equipment to adopt new manufacturing technologies and increase capacity, which requires hefty investments. Since capital expenditures (CapEx) are getting extremely high in the semiconductor industry these days, chipmakers like Micron are seeking support and incentives from governments. They plan their own spending based on what they might receive in grants and various enticements.  

$320 million is a lot of money, though it remains to be seen how much money Micron will be willing to spend on Hiroshima site expansion. Just yesterday, the company said that it cut down its fiscal year 2023 CapEx budget by 30% year-over-year to around $8 billion. To reduce its capital expenditures, the company trimmed its wafer fab equipment (WFE) CapEx by nearly 50% YoY, which will result in a much slower ramp of its 1ß DRAM and 232-layer 3D NAND versus prior expectations as the ramp requires more new tools at the fabs. Meanwhile, the company "more than doubled" its construction CapEx (i.e., building new fab shells) year-over-year to meet demand for the second half of this decade and retained plans to procure EUV lithography systems to support its 1γ (1-gamma) node development.  

The $320 million subsidy from the Japanese government could be used to bolster the Hiroshima site's WFE CapEx budget to ramp up 1ß DRAM node in Japan next year or procure new EUV tools and ramp up EUV-enabled 1γ DRAM fabrication technology in Japan sometime in 2024. Keeping in mind that many things for 1ß DRAM manufacturing process should be arranged by now (i.e., which tools go where), the grant might indeed be used for the next round of Micron's Hiroshima site expansion, the one that involves ASML's EUV scanners and the company's 1γ DRAM. 

For now, we have more questions than answers, but it looks like the subsidy from the Japanese government comes at a time when Micron is slowing down upgrades of its current fabs by cutting down its WFE CapEx.

Micron on Thursday said it would build an all-new leading-edge memory fab near Boise, Idaho, the company's home city. The fab will cost Micron $15 billion and will come online by the end of the decade. 

The new Micron memory fab will be located adjacent to the company's main R&D center near its headquarters in the city, which is expected to enhance operational efficiency, accelerate technology deployment and improve time to market. In fact, this new fab will be among the world's few semiconductor production facilities that are located near a major R&D center. Another similar site — with both R&D and high-volume manufacturing operations — that Micron has is located near Hiroshima, Japan. 

Micron will invest $15 billion in the new manufacturing facility, it also anticipates to get federal grants and credits made possible by the Chips and Science Act as well as the incentives provided by the state of Idaho. That said, the total cost of the fab will be higher than $15 billion. 

Micron calls its new project a 'leading-edge memory manufacturing fab' without disclosing which type of memory it will produce. Meanwhile, it says that it will employ 2,000 workers and will become operational by the end of the decade, which may mean 2026 if the company starts construction in early 2023, or 2029 if the construction begins later. In any case, a DRAM production facility designed to make memory throughout the next 10 years or so is destined to be ready for extreme ultraviolet (EUV) lithography tools. 

Micron did not reveal what it plans to produce 3D NAND memory of DRAM device at its new fab. High volume production of 3D NAND requires more chemical vapor deposition (CVD) and etching machines, whereas DRAM needs more lithography tools, so different kinds of memory need different cleanroom configurations. In the recent years Samsung and SK Hynix built fabs that could be reconfigured from 3D NAND to DRAM and vice versa, but we do not know whether this is the case with Micron. 

At present Micron has five wafer fabrication facilities worldwide: two 3D NAND fabs in Singapore, a DRAM fab in Japan near Hiroshima, and two DRAM fabs in Taiwan (near Taichung and near Taoyuan).  

Micron's $15 billion investment in its Boise, Idaho, fab is a part of the company's plan to invest $40 billion in leading-edge memory manufacturing in the U.S. through the end of the decade. If the company manages to invest this amount of money in new fabs in the U.S., the majority (or at least a very significant portion) of Micron's semiconductors (e.g., 3D NAND or DRAM devices) will be made in America about ten years from now.