Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.

Earlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.

Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial.

Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.

"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."

Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.

ASML this week reaffirmed that it is on track to release a Twinscan NXE extreme ultraviolet lithography system that features a 1000W EUV power source and can process up to 330 wafers per hour. The system, projected for sometime in 2030 or beyond, offers 50% more power than the current best EUV tool, the NXE:3800E. Such machines will greatly increase productivity and decrease costs per wafer for chipmakers, but to make them possible, ASML has had to achieve several breakthroughs.

"What was achieved — one kilowatt — is pretty amazing," Michael Purvis, ASML's lead technologist for its EUV source light, told Reuters. "We see a reasonably clear path toward 1,500 watts, and no fundamental reason why we couldn't get to 2,000 watts."

However, to get to a 1000W-class EUV source in the 2030s, ASML must develop a new three-pulse EUV light generation method that it disclosed in late 2024. The new method involves a 1μm pre-pulse that flattens the droplets, followed by a 1μm rarefaction pre-pulse that rarefies them, after which the main 10μm CO2 laser pulse turns them into EUV plasma. Previously, ASML filed a patent application for an EUV light source producing three laser pulses, according to Asianometry. For now, this three-pulse source is not a part of any shipping machine, though expect it to end up in a Twinscan NXE:4000-series scanners due later this decade.

Yet, the actual 1000W EUV radiation source will also be equipped with a new tin droplet that will almost double the number of tin droplets to 100,000 every second. This unit is also currently under development, and it will take years before it is commercialized, according to an ASML spokesperson speaking with Tom's Hardware.

Building a new laser system that comprises of a CO2 laser with a 10μm wavelength for the main pulse and two non-CO2 lasers for with ~1μm wavelength for pre-pulses and a new tin droplet generator that doubles performance as well as a new tin droplet generator with twofold performance sounds easy on paper, both these devices as well as devices that accompany them to make their work possible represent numerous major technological breakthroughs.

Increasing the number of tin droplets automatically means increasing the amount of debris that can end up on a wafer (or rather a pellicle), so they must be promptly removed, which means an all-new debris collector. While producing 1000W of EUV radiation is hard, transferring it onto a wafer is even harder, so ASML had to invent all-new high transmission projection optics, which are meant to scale all the way to over 450 wafers per hour, or toward something like 1500W. Also, increased productivity and higher performance light sources require new wafer and reticle stages, which will also be upgraded in systems featuring a 1000W light source. Last but not least, a 1000W EUV light source also calls for new resists and pellicles, so in addition to ASML itself, the whole industry needs to prep for the arrival of the company's tools featuring its latest innovations.

ASML has long planned to increase the productivity of its EUV lithography scanners to 330 wafers per hour by around 2030, a productivity level tied to a 1000W light source. Therefore, the announcement made this week outlines the technology the company invented to achieve that roadmap goal.

ASML is yet to integrate its 1000W EUV light source into its Low-NA EUV and High-NA EUV roadmaps. The company's next-generation Low-NA Twinscan NXE:4000F litho system with a production capacity of over 250 WpH and a matched machine overlay (MMO) performance of 0.8 nm for 1.x-nm-class nodes is due in 2027, followed by the NXE:4200G with productivity of over 280 WpH in 2029. On the High-NA EUV front, ASML preps the Twinscan EXE:5200C with an over 185 WpH output and a <0.9nm MMO performance next year, followed by the EXE:5400D with productivity of over 195 wafers per hour in 2029.

Intel announced that it had installed ASML's Twinscan EXE:5200B, the industry's first High-NA lithography tool with 0.55 numerical aperture projection optics made for commercial chip production. The tool has passed acceptance testing and will be used for development of Intel's 14A fabrication process, which will be the world's first node to rely on High-NA EUV scanners for its most critical layers. The achievement indicates that High-NA EUV lithography is moving beyond early experimentation toward high-volume manufacturing (HVM).

ASML's Twinscan EXE:5200B builds on the 1st Generation EXE:5000 platform that Intel received in 2023 for its Oregon R&D fab. The new tool can 'print' chips with an 8nm resolution, enabling scaling beyond which is currently possible with Low-NA EUV tools that offer a 13nm resolution without using multi-patterning. Unlike the EXE:5000, the EXE:5200B is capable of processing 175 wafers per hour at a 50 mJ/cm² dose (up from 185 wafers per hour at at a 20 mJ/cm² dose) and achieves overlay accuracy of 0.7 nanometers, a critical parameter as feature dimensions continue to shrink.

To boost performance, the scanner integrates a higher-power EUV light source to enable faster wafer exposures at a 50 mJ/cm² dose. This in turn supports workable resist/process windows with strong image contrast while minimizing line-edge roughness (LER) and line-width roughness (LWR), which tend to be challenging with modern production nodes.

ASML and Intel did not limit their work to the optics and light source. They also reworked the wafer stocker system, which is responsible for how wafers are stored, queued, and moved in and out of the scanner. For next-generation tools, this component of the system has a direct impact on both productivity and patterning accuracy.

The updated stocker design improves lot flow and wafer handling to make sure that wafers arrive at the exposure stage in a more predictable state. At the same time, it provides tighter thermal control, keeping wafers and carriers at stable temperatures before and after exposure, an important factor as even tiny temperature variations can cause wafer expansion or contraction, leading to overlay errors, which in turn leads to an increase in defects and decrease of yields.

In addition, by reducing thermal and mechanical variation, the new architecture helps to minimize drift over long runs, thus enabling the scanner to maintain stable behavior and reducing the necessity for frequent recalibration. This stability will be particularly important for multi-pass and multi-exposure patterning, which will be inevitably used in the coming years for sub-1nm process technologies.

One of EXE:5200B's parameters that is hard to overestimate is its overlay performance of 0.7 nm, which was achieved by advancements of stage control, sensor calibration, and environmental isolation. Overlay performance is crucially important for next-generation process technologies as even tiny alignment errors can translate into yield losses.

It is necessary to note that ASML's Twinscan EXE:5200B is not just another EUV scanner in Intel's fab, but rather a foundation that is expected to enable Intel to regain its leadership in the semiconductor industry.

To use the new lithography tool, Intel is conducting parallel work on masks, etch processes, resolution enhancement techniques, and metrology that must be co-optimized to extract the maximum value from High-NA EUV patterning.

Intel says that its High-NA tools will enable more flexible design rules, reduce the number of patterning steps, lower mask counts, shorter cycle time, and increased yields thanks to lack of multipatterning with 14A and more advanced process technologies. Meanwhile, as Intel learns how to use High-NA EUV tools and gains valuable HVM experience, it will be able to insert High-NA EUV multi-patterning when it needs to in the sub-1nm era without significant effect on yields.

Researchers at Johns Hopkins University have unveiled a new approach to chipmaking that uses lasers with a 6.5nm ~ 6.7nm wavelength — also known as Soft X-rays — that could increase the resolution of lithography tools to 5nm and below, reports Cosmos, citing a paper published in Nature.

The scientists call their method 'beyond-EUV' — suggesting that their technology could replace industry-standard EUV lithography — but the researchers admit they are currently years away from building even an experimental B-EUV tool.

Soft X-Rays can challenge Hyper-NA. On paper

The most advanced chips nowadays are made using EUV lithography, which operates at a wavelength of 13.5 nm and can produce features as small as 13nm (Low-NA EUV of 0.33 numerical aperture), 8nm (High-NA EUV of 0.55 NA), or even 4nm ~ 5nm (Hyper-NA EUV on 0.7 – 0.75 NA) at the cost of extreme complexity of the lithography systems that have very advanced optics that cost hundreds of millions of dollars.

By using a shorter wavelength, researchers from Johns Hopkins University can get an intrinsic resolution boost even with lenses with moderate NA. However, they face many challenges with B-EUV.

Firstly, B‑EUV light sources are not yet ready. Various researchers have tried multiple methods of generating 6.7 nm wavelength radiation (e.g., gadolinium laser-produced plasma), but there is no industry-standard approach. Secondly, these shorter wavelengths — due to their high photon energy — interact poorly with traditional photoresist materials used in chipmaking. Thirdly, because 6.5nm ~ 6.7nm wavelength light is absorbed rather than reflected by pretty much everything, multilayer-coated mirrors for this type of radiation haven't been produced before.

Finally, these lithography tools must be designed from scratch, and currently, there is no ecosystem to support the designs with components and consumables. To sum up, building a B-EUV machine (or Soft X-ray machine?) requires breakthroughs in light sources, projection mirrors, resists, and even consumables like pellicles or photomasks.

Solving challenges one at a time

Researchers at Johns Hopkins University, led by Professor Michael Tsapatsis, explored how certain metals can improve the interaction between B-EUV (around 6 nm wavelength) light and resist materials used in chipmaking (i.e., they did not work on other challenges associated with Soft X-rays).

The team discovered that metals like zinc are able to absorb B-EUV light and emit electrons, which then trigger chemical reactions in organic compounds called imidazoles. These reactions make it possible to etch very fine patterns onto semiconductor wafers.

Interestingly, while zinc performs poorly with traditional 13.5nm EUV light, it becomes highly effective at shorter wavelengths, highlighting how important it is to match the material with the right wavelength.

To apply these metal–organic compounds to silicon wafers, the researchers developed a technique called chemical liquid deposition (CLD). This method creates thin, mirror-like layers of a material called aZIF (amorphous zeolitic imidazolate frameworks), growing at a rate of 1nm per second. CLD also allows for fast testing of different metal–imidazole combinations, making it easier to discover the best pairings for different lithography wavelengths. While zinc is well suited for B-EUV, the team noted that other metals might perform better at different wavelengths, offering flexibility for future chipmaking technologies.

This approach gives manufacturers a toolbox of at least 10 metal elements and hundreds of organic ligands to create custom resists tailored to specific lithography platforms, the researchers disclosed.

Summary

Creating a powerful, reliable, and manufacturable light source for modern chipmakers is one of the most complex challenges in today's industry. Among all makers of litho systems, only ASML has successfully created EUV light to print the smallest chip features — but one startup has a radical new idea to change the status quo.

Inversion Semiconductor, a San Francisco startup backed by venture capital firm Y Combinator, plans to develop a light source based on a compact particle accelerator, which it claims would be 33 times more powerful than ASML's existing technology and could pave the way for producing finer chip features.

At the heart of Inversion's tech is a 'tabletop' particle accelerator that is 1,000x smaller than traditional particle accelerators and yet can deliver output power of up to 10 kW. Despite its tiny dimensions, Inversion claims that its light source, leveraging the laser wakefield acceleration (LWFA) method, can either speed up chipmaking 15 fold (assuming one 10 kW light source powers one lithography system) or power multiple chipmaking tools simultaneously, thereby cutting costs.

There are major challenges for the budding startup, however, as this specific type of accelerator requires petawatt-class lasers, which are both costly and power hungry. Additionally, unless Inversion Semiconductor collaborates with ASML (or perhaps other manufacturers of lithography machines), it would need to develop its own lithography systems and create a new ecosystem for its scanners, a time-consuming and expensive endeavor.

Given that Inversion Semiconductor has no experience building high-volume, 24/7 fab tools, the company's ambitions are lofty, and there's no guarantee it will fulfill the promise it's making on paper.

10 times more power-hungry than ASML

Inversion Semiconductor was founded in 2024 by Rohan Karthik (CEO) and Daniel Vega (CTO), both of whom hold master's degrees in mechanical engineering and applied physics. The company is backed by Y Combinator. Inversion's goal is to develop a compact, high-performance light source based on a particle accelerator that would offer an output power of 10 kW, which is 10 times more powerful than what ASML plans to achieve over the next decade.

This particle accelerator could produce lasers with wavelengths between 20nm and 6.7nm, including 13.5nm light used by ASML for both Low-NA EUV and High-NA EUV lithography tools today.

Light with a sub-10nm wavelength is called a soft X-ray, which is not currently used for chip production due to its high absorption rates by most materials. So, while sub-10nm wavelengths are not currently used in chip production, it might prove to be a promising field for research in the long-term future.

Inversion's ambitions do not end with the development of just a light source, but span all the way to building complete lithography tools to compete against ASML directly.

Using particle accelerators as light sources for lithography tools is a widely discussed and researched topic in the industry, but Inversion Semiconductor plans to use what it calls 'tabletop particle accelerators' that can accelerate electrons to extremely high energies over centimeters, rather than kilometers, as seen in accelerators such as the Large Hadron Collider used by CERN.

Riding on the wakefield waves

Immersion intends to use accelerators relying on the laser wakefield acceleration (LWFA) technique, which is significantly different compared to methods used by ASML and CERN. LWFA uses powerful, ultra-short (femtosecond-scale) laser pulses interacting with plasma, consisting of free electrons and positively charged ions.

When an intense laser pulse travels through plasma, it creates strong electric fields by pushing electrons aside and generating plasma waves, or 'wakefields' behind it. Electrons can become trapped and accelerated rapidly within these waves, gaining substantial energy in a very short distance as they rush back to their original position. The plasma wave accelerates electrons in fields that are 100 – 1000 times stronger than those found in a conventional accelerator, according to the Imperial College London.

The accelerated electrons can then be used for various practical applications, including compact X-ray sources and semiconductor lithography, just to name a few. Unlike traditional EUV sources, the LWFA method generates radiation that is coherent, monochromatic, and precisely tuneable, enabling wavelengths shorter than 13.5 nm (e.g., 6.7 nm target, which is far from industrial deployment), which could be instrumental for next-generation lithography systems.

The LWFA mechanism accelerates electrons to energies reaching multiple giga-electron volts (GeV) over distances as short as a few centimeters, thus miniaturizing high-energy electron acceleration systems dramatically, from large facilities down to tabletop-sized devices, which could spark further innovation for the semiconductor industry.

Immersion Semiconductor's immediate goals

Immersion Semiconductor's progress to date includes setting up a small laser laboratory within the Y Combinator offices to develop new laser stabilization techniques, and building initial LWFA prototypes capable of producing short-wavelength radiation. They have also partnered with the Lawrence Berkeley National Laboratory and the BELLA Center to collaborate on the BELLA-LUX project, focusing on refining laser stability and improving the generation of suitable light for semiconductor use.

The company's immediate goal is to develop Starlight: a high-power, tunable light source capable of producing 1 kW of soft X-ray light in the 20 nm to 6 nm wavelength range. If successful, the device could find use in applications like industrial X-ray imaging and semiconductor mask inspection. Companies such as Tesla and Applied Materials have expressed interest in these early-stage developments, according to Immersion Semiconductor.

In parallel, the company is working on advanced mirror systems to reflect and focus the generated EUV light (i.e. higher than 10nm), which are necessary to direct the light precisely for wafer patterning. The first lithography system based on this technology — designated LITH-0 — will be powered by Starlight, with the goal of demonstrating practical silicon wafer patterning capabilities. However, no-one knows when Inversion Semiconductor's LITH-0 will be complete, and fully-functional.

Are there any Caveats? Many!

On paper, Inversion Lithography's plans seem sound and the LWFA method of generating EUV radiation (or light) seems almost perfect. However, there are many caveats.

First up, an LWFA accelerator chamber may be small, but it requires a petawatt-class, ultrafast laser systems which are extremely complex, large, and expensive. Cooling and maintaining such lasers for reliable, non-stop fab operation is something that nobody has tried. It is also unclear whether Immersion Semiconductor's setup can fire those lasers at a consistent repetition rate per second.

Secondly, even researchers from the John Adams Institute for Accelerator Science at Imperial College London admit that LWFA produces electron beams with large energy spread (variation in electron energies) and beam divergence (wider spread of trajectories) at beyond 1 GeV.

For lithography, the generated light must be highly stable in wavelength, direction, and coherence to achieve precise and repeatable patterning. Instability translates into poor resolution leading to performance variability and yield loss.

Thirdly, while today LWFA-based tools featuring a laser with 13.5nm light source can use mirrors and optics developed for ASML's Low-NA and High-NA EUV tools, should they move to shorter wavelengths, they are poised to use new mirrors and optics. This will be a problem, of course, if Inversion Lithography actually decides to develop its own lithography systems, but, this means it will have to develop a whole new ecosystem.

A more realistic variant could be making its LWFA-based source compatible with existing tools from ASML. However, there is a problem too. Integrating an LWFA light source with existing EUV lithography scanners would be complex as it would require developing new beam shaping, focusing, and metrology systems, just to name a few challenges. While ASML has solved all the challenges associated with its Cymer light sources, we can only wonder whether the company is interested in making its tools work with a third-party tool. As for other makers of litho machines — Canon and Nikon — they have not managed to go beyond KrF and ArF lasers and tools, respectively, so chances that they will manage to build EUV (or beyond EUV) scanners are low. Also, keeping in mind that we are talking about an at least 1 kW light source, the industry will also need new resists, pellicles, and other expendables to make everything work.

Perhaps the biggest challenge for Inversion Lithography is that it does not have any experience in production of rapidly-serviceable mass-produced tools that are engineered for fabs operating 24/7 and are highly compatible with other production equipment in the building.

Summary

Inversion Lithography aims to develop a compact, LWFA-based light source that 10 times more powerful than ASML's current EUV light sources while also targeting even shorter wavelenghts. Inversion says that its light sources will be tunable and will create coherent radiation for finer semiconductor patterning. Eventually the company aims to build a light source with a 10 kW performance (10 times more powerful compared to what ASML plans over the next decade), it can either greatly speed up production of chips (by 15 times, the company claims), or power multiple lithography systems with one light source, thus cutting down costs.

However, there are major challenges as an LWFA-based accelerator require a petawatt-class laser, which consumes a lot of power and is expensive. Also, unless Inversion teams up with ASML (an unlikely scenario) or other makers of litho tools like Canon and Nikon (also unlikely) and develops its own scanners, it will have to develop an all-new ecosystem for its machines, which is timely and extremely costly. Also, if the company goes down this path, it will have to gain experience in creating and maintaining high-volume production 24/7 fab tools.

Intel has made significant strides in implementing High-NA EUV lithography by installing two High-NA litho machines, developing custom reticles as well as all-new optical proximity correction, and processing 30,000 wafers. However, major hurdles remain: the $380 million – $400 million tool cost and potential necessity to overhaul photomask supply chain limits economic viability of the technology. Furthermore, a single High-NA EUV exposure costs 2.5 times more than a single Low-NA EUV exposure, which raises further questions about economic feasibility over the next few years, reports SemiAnalysis.

Puzzling economics

ASML's Twinscan EXE:5000 weighs 150 tons and is priced around $380 million – $400 million, roughly double that of its Low-NA Twinscan NXE predecessors. At the SPIE conference earlier this year IBM presented simulation data comparing different approaches to patterning. It showed that replacing three or four Low-NA masks with one High-NA exposure could yield cost savings. For example, IBM estimated a four-mask self-aligned double patterning flow is 1.7 to 2.1 times more expensive than a single High-NA exposure. But when only two Low-NA passes are replaced, High-NA becomes more expensive by 2.5 times, which means that High-NA is only cost-efficient when it can eliminate three or more exposures.

This does not mean that the industry will not need High-NA tools. It means that the industry will have tangible benefits of using High-NA EUV lithography when it needs triple or quadruple patterning with Low-NA EUV scanners, which will depend on process technologies that the industry adopts and aggressiveness of process scaling going forward.

According to Intel, this may happen sooner rather than later. The company showed imaging results, made economic comparisons, and discussed patterning alternatives, and ecosystem readiness, painting a detailed picture of where High-NA EUV stands in 2025 at the SPIE Advanced Lithography conference earlier this year.

The imaging results included key device layers such as metal and contact levels. In the case of metal layers, Intel used one High-NA exposure to replace a previous scheme requiring three separate Low-NA exposures and around 30 total process steps. This simplification could reduce cost and defectivity for complex interconnect structures. In contact holes, yield from early High-NA tests matched that of established multi-patterning flows, despite the initial masks being early-stage test versions. These outcomes suggest High-NA EUV lithography is technically viable for some of the most challenging layers at upcoming nodes.

Intel itself is expected to selectively implement High-NA EUV lithography for a few layers within its Intel 14A (1.4nm-class) process technology, though ecosystem readiness could impact the company's plans. For Intel, the good news is that it is at the helm of that ecosystem development and will therefore have a lead over rivals.

Parallel development

By acquiring and installing two ASML Twinscan EXE:5000 lithography tools ahead of competitors, Intel is ahead of the industry in gathering process data and proving viability for high-volume manufacturing. Intel did everything it could to get its High-NA EUV scanners as early as possible. It received the first Twinscan EXE:5000 machine over a year ago and skipped ASML's typical factory tool qualification, which includes assembly of the tool at an ASML facility — opting instead for assembly and startup at its own D1D fab near Hillsboro, Oregon. This early decision gave Intel a head start in validating the system and building process readiness. To support its development efforts, Intel exposed over 30,000 wafers across both High-NA tools, making it the most experienced user of this new platform.

But getting a new scanner and assembling it are only some of the challenges associated with making it work properly. In addition, Intel needed to develop process technology itself, photomasks, resists, and optical proximity correction (OPC) software enhancement techniques. Normally, since all these things are co-dependent, they are developed serially. However, Intel adopted a parallel development strategy to meet the tight timeline for its 14A (1.4nm-class) node, which is expected to be production ready in 2026. The company shared details how it managed to do so at this year's SPIE Advanced Lithography conference.

Intel began to develop OPC well before it got its High-NA EUV tool running. The company used simulations and exposures on conventional EUV tools to extrapolate and fine-tune models intended for High-NA EUV. This strategy bypassed the usual delay in mask preparation and enabled immediate pilot line operation once the High-NA scanners were up. Results exceeded expectations: source power reached 110% of target (a first for an ASML scanner at launch) and overlay alignment measured at 0.6nm, which is comparable (yet, not as precise) to mature Low-NA systems.

By now, Intel has made significant strides in developing production ready photomasks, resists, OCP, and other elements of High-NA EUV production flow. However, it looks like the obstacles associated with adoption of High-NA EUV tools by the industry are not only engineering challenges, but also economic hurdles associated both with infrastructure development and usage scenarios.

Not yet ready for prime time

One of the challenges with High-NA EUV lithography is the two times smaller exposure field compared to Low-NA EUV lithography due to higher numerical aperture of projection optics: 26 mm × 16.5 mm vs. 26 mm × 33 mm.

This is a major challenge for large chips like GPUs and CPUs, which often exceed the 13×26 mm limit of a single High-NA exposure. Therefore, to pattern these dies, two or more overlapping exposures (stitched fields) must be used (an alternative is to use a multi-chiplet designs). This introduces alignment complexity, risks of overlay errors, and yield loss in the stitched regions. Also, with fewer chips fit per exposure field, more passes per wafer are required, which reduces the wafer-per-hour rate and increases cost per wafer.

ASML proposes to use accelerated stages (i.e., accelerate how the wafer moves under the photomask) to compensate for higher number of exposures. However, Intel has long proposed to use a larger 6×12-inch photomask instead of industry-standard 6×6-inch photomask. A larger photomask solves the half-field problem by doubling the reticle area, allowing it to hold two adjacent half-field images side by side. When used with appropriately configured High-NA optics, this enables the system to expose a full 26 mm × 33 mm field in one scan pass, restoring the field size to that of Low-NA tools. This obviously eliminates the need for stitching and all the challenges associated with it.

However, the shift to larger photomasks would require a complete overhaul of the mask supply chain, from blank preparation and e-beam writing to handling and fab integration. ASML acknowledged that internal studies on larger masks are in progress but has not committed to bringing the capability to market. The change would disrupt the company's platform unification strategy for Low-NA, High-NA, and eventually Hyper-NA tools and potentially reduce sales of higher-end tools.

In photoresist development, metal-oxide resists are gaining ground as the preferred option for High-NA, according to the Intel's presentation at SPIE. These materials provide better performance in terms of resolution, line-edge roughness, and dose sensitivity, especially important given the thinner films required by the thin depth-of-focus associated with High-NA optics. Traditional chemically amplified resists struggle with etch resistance at the thicknesses now needed, while metal-oxide formulations retain sufficient durability during pattern transfer. Most SPIE 2025 data shared for High-NA tools used metal-oxide resists rather than legacy organics, according to SemiAnalysis.

The method of applying and developing photoresist is another point of industry concern. Tokyo Electron currently dominates the standard wet process with spin-on coating and wet development in its track tools. Lam Research is attempting to gain share by promoting a dry deposition and dry development approach, done in its proprietary tools.

Conclusion

ASML and Imec this week established a five-year partnership designed to enable Imec's researchers and developers access to ASML's latest tools. The move is focused on sub-2nm process technologies that will require ASML's latest lithography (including High-NA), metrology, and inspection tools. Imec will ensure that engineers from academia and various companies have the latest equipment for their research, whereas ASML will ensure that its tools are incorporated into leading-edge process technologies.

Under the partnership, Imec will gain access to ASML's comprehensive range of advanced wafer fabricating equipment (WFE), including range-topping Twinscan NXT (DUV), Twinscan NXE (Low-NA EUV tools with a 0.33 numerical aperture optics), and Twinscan EXE (High-NA EUV tools with a 0.55 numerical aperture optics) lithography systems. Additionally, imec will incorporate ASML's YieldStar optical metrology solutions and HMI’s single- and multi-beam inspection tools into its facilities.

These tools will be installed in Imec's pilot line in Belgium and incorporated in the EU- and Flemish-funded NanoIC pilot line.

The latest-generation of equipment from ASML will be used to develop next-generation semiconductor production technologies, particularly sub-2nm fabrication technologies. It is believed that for efficient manufacturing at fabrication nodes below 2nm, lithography tools must support an 8nm resolution with a single exposure, something that only High-NA EUV tools can achieve. However, each High-NA EUV system costs $350 million, which makes it impossible for new players or researchers to obtain one.

ASML and Imec researchers previously worked with High-NA (0.55 NA EUV) tools primarily at ASML’s dedicated research facilities in Veldhoven, Netherlands. ASML installed these first-generation High-NA EUV machines at its own sites for initial tests, evaluations, and collaborative research with Imec and other partners.

Now, under the new agreement, Imec will have direct, on-site access to High-NA equipment within its own research lines in Leuven, Belgium, specifically in its state-of-the-art pilot facility and the EU- and Flemish-funded NanoIC pilot line. This marks the first time Imec researchers can use the High-NA EUV technology directly at their own facility, which will speed up their work.

Providing Imec with access to the High-NA EUV technology was included in the Next Gen-7A project (IPCEI22201) and financed by the Dutch government as an Important Project of Common European Interest (IPCEI).

"We are excited to continue our longstanding unique partnership with ASML, offering the industry access to the most advanced patterning solutions for over 30 years," states Luc Van den hove, President and CEO at Imec.

"The inclusion of ASML’s full product portfolio will allow us to expand and further mature the capabilities of our pilot line, providing the entire semiconductor ecosystem with the most advanced R&D to tackle the challenges of AI-driven technological advancements. Since Imec has a strong focus on sustainable innovation, having this explicitly included in our partnership is a great addition."

In addition to working collaboratively on next-generation sub-2nm nodes for logic chips, ASML and Imec plan to collaborate on DRAM process technologies, silicon photonics, and advanced packaging solutions.

Intel has started using two leading-edge ASML High-NA Twinscan EXE:5000 EUV lithography tools, the company revealed on Monday at an industry conference, Reuters reports. The company uses these systems for research and development purposes, and so far, Intel has processed tens of thousands of wafers using them. 

Intel installed and started using two High-NA EUV lithography tools from ASML at its D1 development fab near Hillsboro, Oregon, last year and has now processed as many as 30,000 wafers using these systems, Intel engineer Steve Carson revealed at the SPIE Advanced Lithography + Patterning conference. Intel was the first leading chipmaker to get High-NA EUV machines (which are believed to cost €350 million each) last year and plans to use them to produce its 14A (1.4nm-class) chips several years down the road. 

Adopting an all-new manufacturing tool ahead of competitors is important, as it enables Intel to develop various High-NA EUV manufacturing aspects (such as glass for photomasks, pellicles for photomasks, chemicals, etc.) that could eventually become industry standards. Also, ASML is poised to develop its Twinscan EXE:5000 High-NA EUV tools with feedback provided by engineers from Intel, which could give the American giant an edge over competitors over time. 

Processing 30,000 wafers in a quarter is far below what commercial-grade systems can do. However, the number is massive for R&D usage, demonstrating how serious Intel is about becoming the leading chip maker in the High-NA EUV era.

Although ASML considers its Twinscan EXE:5000 High-NA EUV lithography tools to be pre-production tools not designed for high-volume manufacturing, Intel has reportedly said these systems are “more reliable than earlier models.” Still, the report does not elaborate on whether ASML’s Twinscan EXE:5000 is more reliable than the company’s pre-production Twinscan NXE:3300 tool from 2013, which was used to develop the existing EUV ecosystem, or the production-grade Twinscan NXE:3600D or NXE:3800E that are used for high-volume manufacturing (HVM) today. Considering that ASML uses similar light sources for NXE and EXE machines, they may indeed be very reliable. 

ASML’s Twinscan EXE High-NA EUV lithography tools can achieve a resolution of down to 8nm with a single exposure, a substantial improvement compared to Low-NA EUV systems that offer 13.5nm resolution with a single exposure. While current-generation Low-NA EUV tools can still achieve an 8nm resolution with double patterning, this lengthens the product cycle and can affect yields. High-NA EUV tools reduce the exposure field by half compared to Low-NA EUV systems, which require chip developers to alter their designs. Given the costs and peculiarities of High-NA EUV litho systems, all chipmakers have different strategies for their adoption. Intel clearly wants to be the first adopter, whereas TSMC is a little more cautious.

The Lawrence Livermore National Laboratory is working on a petawatt-class thulium laser that is said to be 10 times more efficient than the CO2 lasers used in EUV tools and could replace CO2 lasers in lithography systems many years down the road. 

The LLNL-led initiative will evaluate the Big Aperture Thulium (BAT) laser technology to enhance EUV source efficiency by approximately tenfold compared to the current industry-standard CO2 lasers. This advancement could pave the way for a new generation of 'beyond EUV' lithography systems that produce chips quicker and with less power. Of course, implementing BAT technologies into semiconductor production will require significant infrastructure changes, so it remains to be seen how long it will take to come to fruition; the current EUV systems were developed over the course of decades. 

One of the peculiarities of extreme ultraviolet lithography is the extreme power consumption of the current-gen Low-NA EUV and next-gen High-NA EUV litho systems: the tools consume 1,170 and 1,400 kilowatts, respectively. EUV lithography tools consume such vast amounts of power because they rely on high-energy laser pulses to evaporate tiny tin droplets (at 500,000ºC) to form a plasma that emits 13.5-nanometer light. Generating these pulses at tens of thousands per second demands massive laser infrastructure and cooling systems. Generating and manipulating tin droplets also requires power. 

In addition, vacuum requirements to prevent the absorption of EUV light by air add to the overall energy use. Finally, as advanced mirrors in EUV tools reflect only a fraction of EUV light, lasers must become more powerful to increase production capacity. 

Lawrence Livermore's team of researchers is testing whether technologies behind the BAT laser — built around thulium-doped yttrium lithium fluoride and capable of petawatt-class output — can raise the energy efficiency of current EUV tools. Unlike CO2 lasers that operate at a wavelength of about 10 microns, this system operates at around 2 microns, according to LLNL. This theoretically enables higher plasma-to-EUV conversion efficiency when interacting with tin droplets. Also, diode-pumped solid-state technology used in BAT systems can offer better overall electrical efficiency and heat management compared to gas-based CO2 setups. 

Initially, the researchers aim to pair the compact, high-repetition-rate BAT laser (with different types of pulses) with systems that produce EUV light to test how a laser delivering joule-level pulses at a 2-micron wavelength interacts with tin drops.

“We have performed the theoretical plasma simulations and proof of concept laser demonstrations over the past five years that lay the foundations for this project,” said LLNL laser physicist Brendan Reagan. “Our work has already had quite an impact in the EUV lithography community, so now we’re excited to take this next step.”

The power consumption of modern EUV tools and fabs has led industry analyst firm TechInsights to raise the alarm over the power consumption of semiconductor fabs. These fabs are projected to consume 54,000 gigawatts (GW) of power per year by 2030 — more than Singapore or Greece consume per annum. If next-gen Hyper-NA EUV lithography comes to market, the power consumption may be even higher. As such, we can expect the industry to continue to search for more power-efficient technologies to power future EUV machines. 

One of the world's leading chip-making equipment manufacturers has released a new Lego set. Veldhoven, Netherlands-based ASML has added the TWINSCAN EXE:5000 Lego set to its growing portfolio of gifts. At $227.95 this "masterpiece in technology" might sound rather expensive, but please remember that real ASML lithography systems cost sums approaching $400 million. Also, even if you are drooling over this gift, you would probably admit it is a niche item.

Regular readers of Tom's Hardware will be well aware of ASML's pivotal position in the world of semiconductor manufacturing. The company supplies chipmaking icons like Intel, TSMC, and Samsung, and its tools are essential for the most advanced lithography.

The ASML TWINSCAN EXE:5000 is one of the leading extreme ultraviolet (EUV) lithography tools available in 2024. ASML tested a machine in-house earlier this year and boasted about its projection optics that feature a 0.55 numerical aperture (High-NA). Intel is also working with this machine for R&D on its Intel 18A (1.8nm-class) process technology.

OK, but what about the Lego set? It is also a marvel of human creativity, but will only output to your dreams. The ASML TWINSCAN EXE:5000 Lego set features 851 Lego bricks/parts, so will be a bit of an engineering feat for a home tech enthusiast to complete. When you have laid your final brick the result will be a 13.86 x 3.9 x 2.52-inches model. That's quite small considering the price.

ASML seems to be pretty confident that the demand for the new TWINSCAN EXE:5000 Lego set will be strong. Orders are limited to one set per customer, with warnings of canceled orders for those asking for more. However, this "iconic" set isn't the first or only ASML Lego product released. The firm previously launched the Lego ASML Skyline and the Lego TWINSCAN NXE:3400C sets. One alternative Lego set is still available for sale here, at $166.70.

Also, if you are in the mood for Christmas, a set of three unique, hand-crafted glass tree ornaments is available for $29. These consist of a glass ASML logo, a cleanroom employee, and an NXT machine (pictured below).

The worlds of PC tech and Lego often intermingle. Looking back through the Tom's Hardware archive we see we reported on an RTX 4080 Super-powered Lego Fortnite PC back in August, and last year a life-size Lego Intel Arc graphics card project caught our eye.

Nikkei Asia's sources say that Taiwan Semiconductor Manufacturing Corporation (TSMC), the largest semiconductor fab in the world, is set to receive the ASML’s most advanced chipmaking machine this year. The high numerical aperture extreme ultraviolet (High NA EUV) machine, which is said to cost more than $350 million apiece, will allow chip makers to print features smaller than before. Nikkei Asia reports that TSMC is considering using its High NA EUV lithography machines to make processors that use angstrom 10 (A10) technology, about two generations ahead of the 2nm node that it plans to put into production by the end of next year. This means that we likely won’t see this machine used for mass production until after 2030.

Although TSMC is the biggest semiconductor manufacturer globally, it’s not the first company to get ASML’s latest, most advanced machine. Intel was the first to adopt the machines, having received the very first High NA EUV machine in the first quarter of 2024 at its Oregon facility. It also received a second machine during the second quarter of this year — a testament to the company's focus on regaining its technological edge over the competition, especially in AI chip manufacturing. Sources also say that Samsung will install its own High NA EUV machine sometime between today and the 1Q25.

This news of installations of ASML’s most advanced machines doesn’t mean that we’re getting sub-nm nodes next year, however. Instead, companies are investing hundreds of millions of dollars to develop the technologies needed to harness its ability to pack in transistors in record-breaking densities. That’s because High NA EUV has a smaller imaging field versus current NA EUV machines, so chip manufacturers need to adjust their designs based on that. Furthermore, High NA EUV machines are significantly larger than current lithography machines, so these fabs must reorganize their production lines or build a new factory from the ground up to accommodate ASML’s most advanced offering.

At the moment, these three companies — Intel, Samsung, and TSMC — are the only ones that are known to be working on more advanced chips that will take advantage of ASML’s High NMA EUV lithography machine. This is especially true as Chinese firms have been blocked from accessing ASML’s products and services by America’s bans and sanctions. Nevertheless, the company says that it already has received 10 to 20 orders for these multimillion-dollar machines.

ASML has a practical monopoly on advanced EUV lithography machines. It’s the only one that has know-how and capability to manufacture these machines required for making the next generation of semiconductors. But even if ASML is based in the Netherlands — a known American ally — the U.S. is still investing EUV research so that it could bring its semiconductor supply chain home. While it will take years, if not decades, for this move to bear fruit, this should at least give chipmakers more options in the future, furthering technological advancements through healthy competition

Extreme ultraviolet (EUV) lithography is vital for modern process technologies and semiconductor manufacturing for years to come. However, at 1,400 kilowatts per EUV tool — enough to power a small city — EUV lithography systems have become a substantial consumer of power that impacts the environment. TechInsights believes that the power consumption of all fabs equipped with EUV tools will exceed 54,000 gigawatts (GW) of power per year by 2030, which is more than what many countries, like Singapore or Greece, consume per year.  

Current Low-NA EUV scanners require up to 1,170 kW, and next-gen High-NA tools are projected to need as much as 1,400 kW per unit (according to TechInsights). The number of these machines installed at fabs operated by Intel, Micron, Samsung, SK hynix, and, of course, TSMC, increases every year. 

TechInsights believes that by 2030, the number of fabs with EUV scanners will increase from 31 today to 59, and the number of tools in operation will approximately double. As a result, all the installed EUV systems will consume 6,100 GW/year of power, which suggests that hundreds of the machines will be operational by then.  

6,100 GW/year — power consumption comparable to Luxemburg's — is not a lot. However, each advanced chip takes over 4,000 steps to make, and there are hundreds of tools in a fab. EUV equipment accounts for approximately 11% of the total electricity use in a fab, with other tools, HVAC, facility systems, and cooling equipment making up the rest. As a result, the power consumption of all fabs equipped with low-NA and high-NA EUV tools is estimated to increase to 54,000 GW/year. 

To put the number into context, 54,000 gigawatts a year of power is around five times more than Meta's data centers consumed in 2023. It is also more than Singapore, Greece, or Romania consume annually and more than 19 times the power consumed by the Las Vegas Strip per year. However, while this is a substantial amount of power, it is only 0.21% of the global power consumption in 2021 (25,343,000 GW/year), a rather small share. 

It is fairly easy to deduce that if 59 leading-edge semiconductor production facilities with EUV tools consume 54,000 GW/year, each one will consume 915 GW/year, comparable to the power consumption of the most advanced data centers. 

As the number of EUV-equipped fabs is projected to almost double by 2030 and power consumption will more than double as well, power infrastructure will face significant challenges as even today, companies like AWS, Google, Meta, and Microsoft are struggling to find places where to build their megawatt and gigawatt-scale datacenters as power grids must be able to handle them.  

Nowadays, chipmakers like Intel tend to consume only sustainable green energy, but their power consumption is limited for now. With the rising power demand for AI data centers, AWS, Microsoft, and Oracle plan to use nuclear power plants to feed their data centers. Perhaps chipmakers will have to consider using nuclear power in a few years as well. However, it remains to be seen whether power grids will be ready to power AI data centers, advanced fabs, households, and other industries in just six years. 

"To ensure a sustainable future, the industry will need to invest in energy-efficient technologies, explore renewable energy sources, and collaborate with policymakers to address the challenges of power infrastructure," TechInsights concludes. "By doing so, they will be able to extend the power of semiconductors while minimizing their environmental impact."

Corning has introduced its new ultra-low expansion (ULE) material that is designed to withstand ever increasing power of upcoming Low-NA (Numerical Aperture) and High-NA EUV lithography systems. The new Extreme ULE material is projected to be used for next-generation photomasks and lithography mirrors that will be used with next-generation fab tools. 

A key feature of the Extreme ULE material is its extremely low thermal expansion, which provides exceptional consistency for photomask use. In addition, its superior flatness helps to minimize "photomask waviness", reducing unwanted variability in chip production. These properties enable the application of advanced pellicles and photoresists to boost yields and performance. 

As extreme ultraviolet lithography tools attain higher performance in terms of wafer per hour (WPH) processing, they adopt more powerful light sources, and the more powerful light sources expose photomask pellicles, photomasks, and ultimately resists and wafers to higher dosage of EUV radiation and heat.  

In an EUV tool, the plasma source that generates EUV light emits a lot of heat, but the heat is mostly confined to the source chamber, which is separated from the photomask. The light is carried by a set of lithography mirrors that are susceptible to heat. As for the photomask itself, it is made of multilayer reflective materials designed to reflect EUV light. While these layers are highly reflective, some absorption still occurs, leading to a slight heating of the mask. Considering how intricate modern circuits are, even a slight deformation or inconsistency could lead to yield-killing defects or performance variabilities. 

This is where Corning's ULE glass, a family of titania-silicate glass material with near-zero expansion characteristics comes, into play. The Extreme ULE is an evolution of the original ULE family that is meant to offer extreme thermal stability and a uniform glass material for next-generation High-NA EUV tools as well as future Low-NA EUV tools that adopt the same light sources. 

"As the demands of integrated chipmaking grow with the rise of artificial intelligence, glass innovation is more important than ever," said Claude Echahamian, Vice President & General Manager, Corning Advanced Optics. "Extreme ULE Glass will expand Corning's vital role in the ongoing pursuit of Moore's Law by helping enable higher-powered EUV manufacturing as well as higher yield." 

Corning will showcase Extreme ULE Glass at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference, held in Monterey, California, from September 30 to October 3, 2024.

TSMC was ahead of Intel with the adoption of EUV lithography tools for mass production, but when it comes to High-NA EUV systems, it looks like the company is behind its American rival. While Intel is already using its ASML High-NA EUV machine for R&D purposes, intending to use High-NA EUV lithography in the next two or three years, TSMC will only begin installation of its first High-NA EUV tool for R&D later this month, according to reports by DigiTimes and United Daily News. 

TSMC's first ASML Twinscan EXE:5000, a High-NA lithography system designed specifically for R&D purposes, is set to be installed at TSMC's global research and development center in Hsinchu, Taiwan. The world's No. 1 contract chipmaker will begin to receive components of the machine later this month. It is going to take TSMC several months to assemble and calibrate the tool before it will be able to test the next-generation semiconductor production technology at its R&D facility in Taiwan. 

TSMC's upcoming process technologies — N2 (2nm-class) and A16 (1.6nm-class) — will rely solely on traditional EUV equipment with optics featuring a 0.33 numerical aperture (Low-NA). The earliest opportunity for TSMC to insert High-NA EUV tools with optics featuring a 0.55 NA will be with its A14 (1.4nm-class) process technology sometime in 2028 or likely later, though the company yet has to confirm this. However, since High-NA EUV lithography tools reduce the reticle size by half, their use will introduce additional challenges for both chip designers and manufacturers, which is perhaps why TSMC is not exactly accelerating usage of High-NA EUV tools. 

Another reason why TSMC is not jumping to High-NA EUV tools is because of their price. As the company's Kevin Zhang, who is in charge of the development of new process technologies, pointed out earlier this year: he liked the performance of High-NA tools, but did not like the price. 

Each High-NA litho tool costs around $400 million, but TSMC's president, C.C. Wei, personally negotiated a near 20% discount. This price reduction was achieved by combining the purchase of the new machine with the purchase of other ASML gear. Keeping in mind that TSMC is already the leading user of EUV lithography systems, holding an estimated 65% of the global EUV production capacity, ASML is certainly inclined to make deals with the foundry as it is one of its largest customers already.

Samsung is set to start installing its first EUV lithography tool with a 0.55 numerical aperture (High-NA) in Q4 2024 – Q1 2025, reports Seoul Economic Daily, citing its sources. The device will be used primarily for research and development purposes as the company works on its next-generation process technologies that require resolutions enabled by High-NA EUV tools. Samsung also works on a High-NA ecosystem with Lasertec, JSR, Tokyo Electron, and Synopsys.

Samsung's first ASML Twinscan EXE:5000 High-NA lithography system will be installed at the company's Hwaseong campus, where it will develop its next-generation fabrication technologies for logic and DRAM. The unit is projected to be operational by mid-2025. As a result, Samsung will have its first High-NA EUV tool operational about a year later than Intel, but it will still be ahead of its rivals TSMC and SK hynix. When Samsung adopts High-NA EUV for mass production, it remains to be seen, but it is not expected until well into the decade's second half.

Samsung plans to develop a robust ecosystem around high-NA EUV technology. In addition to acquiring the high-NA EUV litho equipment, Samsung is collaborating with Japan's Lasertec to develop inspection equipment specifically for high-NA photomasks. According to DigiTimes, Samsung has reportedly purchased Lasertec's high-NA EUV mask inspection tool, the Actis A300.

"Using [High-NA EUV-specific tool] to inspect semiconductor masks has improved the contrast ratio by over 30% compared to conventional [EUV-specific tool]," said Dr. Min Cheol-ki from Samsung Electronics' Semiconductor Research Institute at the 2024 Lithography + Patterning Symposium.

According to DigiTimes, Samsung is also collaborating with JSR, a maker of photoresists, and Tokyo Electron, a maker of etching machines, to prepare for commercial implementation of High-NA EUV tools by 2027. Samsung is also working with Synopsys to shift from traditional circuit designs to curvilinear patterns on photomasks. This change is expected to improve the precision of circuits imprinted on wafers, which is critical for further refinements of process technologies.

ASML's High-NA EUV Twinscan EXE tool is set to achieve an 8nm resolution, substantially improving the current Low-NA EUV systems that max out at 13nm with a single exposure. This advancement will make transistors about 1.7 times smaller, nearly three times the transistor density. While Low-NA systems can also reach this level of resolution and density, they require the costly and complex double patterning process. The shift to High-NA EUV technology is expected to eliminate the need for double patterning, simplify production, potentially improve yields, and reduce costs.

Achieving these 8nm critical dimensions is crucial for producing chips with sub-3nm process technologies. Yet, at 2nm-class nodes, virtually all chipmakers will be using double patterning. Intel is also adopting pattern-shaping tools for its 20A node. The American chip giant only plans to use High-NA EUV with its 14A node.

Meanwhile, the leap to high-NA brings its own set of challenges. High-NA EUV tools are more expensive ($380 million—$400 million) and have a halved imaging field, which will require significant changes in chip design. Additionally, the larger size of high-NA EUV systems compared to low-NA systems means chipmakers will need to rethink their fab layouts to accommodate these new machines.

TSMC says its newest process tech doesn't need ASML's High-NA EUV chipmaking tools that have been championed by Intel, but the foundry is exploring the tech for future use.

According to Reuters, Zhang told attendees of the event that the A16 process technology will not need the next-generation EUV lithography tools. This implies means that TSMC has found ways to cost-efficiently use EUV double patterning and pattern shaping to increase the achievable critical dimension of a modern Low-NA litho system beyond 13nm. In contrast, Intel plans to insert High-NA EUV tools with its 14A manufacturing technology after it learns how to efficiently use them with its 18A production node.

TSMC is not standing still, though. The company is exploring High-NA EUV lithography for its future process technologies. The A14 node will follow A16, and as TSMC noted in its 2023 Annual Report, A14 development is well underway. 

"TSMC started development and made good progress on 14 Angstrom (A14) technology, which aims to further improve speed, power, density and cost," the company's Annual Report reads. "Looking ahead to A14 and beyond, TSMC R&D will continue to explore next generation EUV (extreme ultraviolet) lithography scanners, conduct research on mask pellicles and blanks to support leading-edge technology and extend Moore's Law."

Using High-NA EUV lithography systems greatly increases fab costs as each tool costs $385 million or more depending on the configuration. Chipmakers tend to re-use as many tools as possible, so TSMC may not be inclined to use High-NA EUV before it runs out of ways to introduce improvements to its production capabilities using Low-NA EUV tools. For example, last year, the company improved the critical dimension and pattern fidelity as well as lowered defect density by modifying photoresist and blank materials as well as optimizing mask process recipes. It also uses deep learning for inspection and discovering defects.

"In 2023, to achieve the wafer yield and productivity for lithography requirements at 2nm node, the R&D team improved the critical dimension, pattern fidelity, overlay stability, exposure durability, and defect mitigation of curvilinear patterns by EUV photoresist and blank material modification, multi-beam writer resolution enhancement, mask process recipe optimization, and advanced deep learning inspection," TSMC said in the report. "Future improvements will focus on developing new blank materials and new mask process technology at the A14 node and beyond."

TSMC's announcement of its A16 process technology (1.6nm-class) with Super Power Rail backside power delivery came as a surprise at the company's North America Technology Symposium 2024. Kevin Zhang, Vice President of Business Development at TSMC, said that the world's largest contract chipmaker had to speed up development of the production node due to rising demand from the AI sector, reports Reuters.

Intel Foundry announced Thursday that it had completed the assembly of the industry's first commercial High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) machine in its D1X fab in Oregon -- an important milestone as the company readies research and development for its 14A process in 2025. 

Intel Foundry is the lead customer for toolmaker ASML's Twinscan EXE:5000 machine, beating commercial rival TSMC and others to begin R&D with the machine. Tom's Hardware spoke with Intel's Director of Lithography Hardware and Solutions to learn more about the new technology, and cost concerns that surround it.

The High-NA lithography tool will enable Intel to print features up to 1.7X smaller than possible with existing EUV tools, eventually allowing Intel to shrink to smaller transistors than possible with standard, Low-NA EUV machines, thus yielding up to a 2.9X transistor density improvement for a single exposure. In fact, ASML announced yesterday that the only other assembled High-NA machine, its pathfinding machine located in Veldhoven, Netherlands, had set a record for an EUV system by printing the first 10nm dense lines with a full-field lithography system.

Intel famously spent decades helping the industry develop first-gen Low-NA lithography technology, but chose not to use it for its 10nm process due to cost concerns. Instead, Intel chose to use quad-patterning with standard deep ultraviolet (DUV) lithography machines, requiring four DUV exposures for a single chip layer instead of a single exposure with EUV. As a result, Intel encountered numerous difficulties with yields, leading to five years of delays for its 10nm process. 

As such, Intel remained mired on the 14nm node while long-time rival TSMC adopted EUV and took the lead in process node tech from Intel for the first time. TSMC then armed Intel's rivals, like AMD, with its better process tech, leading to significant market share losses for the product side of Intel's business.

Intel finally adopted EUV technology with its 'Intel 4' process node, but the years of delays left it lagging several nodes behind TSMC. Intel says it is now on a course to retake the lead by launching five nodes in four years (5N4Y), an audacious initiative that remains on track for completion by the end of the year. 

However, the job is never done and Intel is keen to make sure it adopts the latest technology to avoid the mistakes of the past. Intel is now looking to develop its newly announced 'Intel 14A' (1.4nm-class) process node and the follow-on 10A node (1nm) with High-NA EUV. Intel will first de-risk the tech by developing product proof points with its 18A node in 2025 and then begin developing its 14A node. Intel also plans to be an early adopter of ASML's second-gen Twinscan EXE:5200B system, which produces more than 200 wafers per hour (WPH), a marked improvement over the current-gen High-NA machine's 185 WPH throughput. Both of those machines are faster than ASML's flagship Low-NA EUV machine, which offers up to 160 WPH. Intel also says that ASML has three generations of its High-NA machines already in development. 

Intel says it sees a runway to use High-NA for at least three process nodes, and perhaps more, so this technology will become a foundational component of its chipmaking operations for an extended period of time. Let's take a closer look at the tool. 

ASML Twinscan EXE:5000 High-NA EUV Machine

The original introduction of EUV faced numerous delays, and the first-generation tools weren't production-ready when they first launched. In fact, the first shipping Low-NA tools required upgrades and took multiple years to be suitable for production.

EUV technology has matured, and ASML's approach to building the new High-NA Twinscan EXE:5000 is significantly more optimized. ASML's existing Low-NA Twinscan NXE:3600 EUV machines were used as a building block for the new High-NA machine. ASML's Low-NA models employ a modular design, allowing the company to leverage proven technology and modules for its new machine while improving other modules, thus speeding the development of the new machine. This modularity also allows the machines to be upgraded with newer, improved modules in the field. 

ASML has also built test stands that allow each module to be tested individually, thus ensuring that each module delivers the basic functionality before the system is fully assembled. ASML builds many of the critical modules in the US. For instance, the light source module is built in San Diego, California, and the top module is built in Wilton, Connecticut.

In the past, ASML sent the completed modules for its development systems to its Veldhoven, Netherlands facilities, assembled the machine, ensured its functionality, dissembled the machine, and then shipped it to its partner. Naturally, shipping the modules back and forth across continents slowed the deployment process.

In contrast, ASML employed a parallel field integration strategy for Intel's High-NA machine that involved sending the pre-tested modules directly to Intel's Oregon fab. ASML shipped the modules to Intel via 350 crates placed inside 43 freight containers, which were then flown to Seattle in multiple cargo planes. Intel then used 20 trucks to bring the more than 150 metric tons of equipment to its Oregon fab. Intel CEO Pat Gelsinger recently said the machine cost '400-ish million' dollars. 

The process of installing and calibrating the machine will span six months. Intel has already reached the critical milestone of assembling the machine, with the next major milestone being the 'First Light.' This checkpoint involves conducting the basic function of exposing the resist on the wafer and signifies that the light source, mirrors, and optics are all functioning properly and aligned. ASML achieved First Light with its High-NA machine in February, and Intel will soon follow. 

To speed the development of the High-NA tool, ASML preserved much of the existing foundation of its NXE machines. The High-NA tool employs the same 13.5nm EUV light wavelength, so the proven light source module required a new interface to support a minimal change to the source's angle that optimizes the optical transmission through the illuminator to maximize efficiency. However, the new system has a halved exposure field compared to Low-NA machines, meaning printing a single wafer could take twice as long. To solve this problem, ASML employed an optimized wafer stage for the NXE:5000 and it now accelerates at 8g — twice as fast as the prior generation. ASML also improved the reticle stage for a 4X speed improvement over the prior generation — this stage now accelerates roughly the same as a car going from zero to 60 MPH in 0.09 seconds.

The smaller exposure field still halves the maximum size of a single die that can be created with a single exposure. Intel says it is working with its EDA partners (many of which joined the company on stage at its IFS Direct event) to integrate stitching tools into the software used for chip design, thus allowing stitching together two separately exposed regions of the wafer to create a single larger die. This effort will take time to come to fruition because it has to be addressed during the design phases of a processor, but optimized EDA software will enable printing larger die sizes for Intel and its customers. It will also allow Intel to better utilize its other full-field tools.

Much of the existing technology, such as basic mask technology, multi-layer optics coatings, and basic resist technology, also carries over to the new machine.

The biggest challenge was developing new optics. Reducing the tools' critical dimension (CD—the smallest feature that can be printed) typically requires either reducing the wavelength of the light source or adjusting the numerical aperture (NA—a measure of the ability to collect and focus light). A higher NA delivers higher imaging contrast and enables using less light per exposure, speeding production. ASML employs the same 13.3nm light wavelength for its High-NA machine as it does with Low-NA, so the biggest advance was moving from 0.33 NA with Low-NA tools to 0.55 NA with the High-NA tool. 

ASML and Zeiss worked together to develop the new anamorphic optics and improved the printing resolution by using bigger mirrors and reducing the angle of the light hitting the reticle. These adjustments reduced the CD from 13nm with Low-NA to 8nm with High-NA. This advance enables printing the smallest features for sub-3nm process nodes with a single exposure.

Intel will initially use the High-NA machine largely for research and development, but will eventually use it for production. Intel says it is designing its 14A process from the ground up to unlock the benefits of High-NA in an unspecified number of critical layers of the design.

ASML has revealed that it has orders for 10 to 20 High-NA EUV machines and announced yesterday that it has begun shipping a second machine to an undisclosed customer. 

Addressing High-NA Cost Concerns 

The arrival of High-NA has been met with industry reports that it will be more expensive to use High-NA than multi-patterning with existing Low-NA EUV machines. Low-NA systems cost in the neighborhood of $185 million, whereas the new High-NA machine is said to be around $400 million, so cost has been thrust into the limelight. I asked Mark Phillips, Intel Fellow and Director of Lithography Hardware and Solutions, if the company sees this as the most cost-effective path forward. 

Modern semiconductors are comprised of multiple layers, with each layer featuring various levels of complexity and different feature sizes. Phillips told us that Intel only plans to use High-NA for an unspecified number of critical layers that require the smallest feature sizes. In contrast, Intel will use older Low-NA EUV, 192nm ArFI, and even 248nm KrF DUV patterning for other layers, with the latter being employed for the upper interconnect layers with larger feature sizes. Intel is designing its 14A node from the ground up to leverage the superior single-exposure High-NA resolution in a few of the tightest-pitch critical layers. Phillips contends that High-NA is more cost-effective for these layers than multi-patterning. 

Intel will also employ Applied Materials' Centura Sculpta pattern shaping tool to improve its patterning capabilities and reduce costs. As you can see in this video, this directional etching technology 'pushes' features (Phillips notes this is preferable only in a single direction) to complement and improve the single-patterning capabilities of EUV lithography. 

"And I would just add, it's not like ASML built this tool and then came to us and asked us if we want to buy it. We started working with ASML more than a decade ago, having these discussions about the business case for the tool," Phillips said. "What are the right tradeoffs of the tool cost versus the capability in order to make it a viable tool? So we knew those capabilities, those specs, and we knew the price when we committed to these tools years ago. And really, there haven't been surprises," said Phillips. He also said the tools perform to the agreements Intel made with ASML long in advance.

Phillips also noted that the High-NA tool would be useful in maximizing the impact of Intel's other new technologies, like its PowerVia Backside Power Delivery. "Backside power delivery, by being able to strip out all the metal lines on the front side stack that carry power and moving them to the backside, then we're able to re-optimize the metal stack on the front side of the wafer," Phillips said.

"It turns out that puts a number of layers right in the sweet spot for the use of the high end tool. So, if you use it for the things that it was designed to do, and you've had enough confidence that it was going to stay on schedule to plan your process to take advantage of them, then yes, it certainly is cost-effective." Phillips also sees High-NA as critical to developing interconnects for the vertically-stacked CFET transistors that will usher in the next wave of density increases (Intel hasn't put that revolutionary tech on its formal roadmap yet).

Intel also has extensive experience with its Directed Self-Assembly (DSA) technology, which uses special materials that can naturally self-assemble molecules into small and regular patterns on a wafer. This technology allows Intel to print with lower EUV light doses and then repair defects, like line edge roughness, thus boosting the speed of the patterning process while improving yields and lowering costs. Phillips says DSA isn't required to make High-NA economically viable. Intel also has several other complementary internal capabilities in its tool chest, such as its mask shop, which built the first EUV masks.

Intel plans to hit the ground running. ASML's High-NA machine in Veldhoven will come online first, and Intel plans to start working on its long lead time items, like its Optical Proximity Correction (OPC) models, on that machine as it waits for the full bring-up of its machine in Oregon. 

Intel's next step in the process of deploying High-NA will be reaching the First Light milestone. The company hasn't set a date for that checkpoint yet, but it is obviously close to that goal. The tool will be used for the development of the 'Intel 14A' process in 2025.

ASML on Wednesday said that it had begun to ship its second High-NA EUV lithography system to another customer. The announcement highlights that there is a major interest for next-generation extreme ultraviolet (EUV) lithography among leading chipmakers. Meanwhile, it is not clear which of ASML's customers is the second company to get an EUV tool with a 0.55 numerical aperture projection optics. 

"Regarding High-NA, or 0.55 NA EUV, we shipped our first system to a customer and this system is currently under installation," said Christophe Fouquet, chief business officer of ASML, at the company's earnings conference call with analysts and investors. "We started to ship the second system this month and its installation is also about to start."

ASML began to ship its first High-NA EUV litho tool — the Twinscan EXE:5000 — to Intel at the end of 2023. Intel will use the system to learn how to use such machines and will insert the system into mass production with its Intel 14A fabrication process, which is a few years away. By starting to work on its High-NA EUV-based process technologies early enough, Intel will be able to develop industry-standards for next-generation lithography, which is poised to become a competitive advantage in the coming years. 

"During the SPIE industry conference in February, we announced first light on our High-NA system located in our joint ASML-Imec High-NA lab in Veldhoven," said the CBO. "We have since achieved first images, with a new record resolution below 10nm and expect to start exposing wafers in the coming weeks. All High-NA customers will use this system for early access to process development."

While TSMC and Rapidus do not seem to be in hurry to adopt High-NA EUV lithography systems for mass production, they ill still have to do it sometime down the road, which is why ASML is optimistic about the future of this technology. In fact, the world's largest maker of wafer fab tools is exploring Hyper-NA, EUV lithography tools with projection optics featuring numerical aperture with higher than 0.7. 

"The customer interest for our [High-NA] system lab is high as this system will help both our Logic and Memory customers prepare for High-NA insertion into their roadmaps," said Fouquet. "Relative to 0.33 NA, the 0.55 NA system provides finer resolution enabling an almost 3x increase in transistor density, at a similar productivity, in support of sub-2nm Logic and sub-10nm DRAM nodes."

ASML has announced that its first extreme ultraviolet (EUV) lithography tool with projection optics featuring a 0.55 numerical aperture (High-NA) has printed its first patterns. The announcement is a major milestone for both ASML and for High-NA EUV lithography technology in general. 

"Our High-NA EUV system in Veldhoven printed the first-ever 10 nanometer dense lines," a statement by ASML reads. "Imaging was done after optics, sensors and stages completed coarse calibration. Next up: bringing the system to full performance. And achieving the same results in the field."

There are currently two High-NA EUV litho systems in the world: one is being built by ASML in Veldhoven, Netherlands — where ASML is headquartered and where the company has a joint High-NA lab with Imec, a leading semiconductor research institute in Belgium; another is being assembled at Intel's D1X fab near Hillsboro, Oregon.

ASML seems to be the first company to announce successful patterning using a High-NA EUV lithography system, which is a major milestone for the entire semiconductor industry. ASML will only use its Twinscan EXE:5000 for its own development and for refining its own technology. 

By contrast, Intel will use its Twinscan EXE:5000 to learn how to use High-NA EUV lithography for mass producing chips. Intel will adopt this tool for R&D purposes with its Intel 18A (1.8nm-class) process technology, and plans to deploy the next-generation Twinscan EXE:5200 scanners to make chips on its 14A (1.4nm-class) production node.

ASML's Twinscan EXE:5200, which is equipped with a 0.55 NA lens, is designed to print chips with an 8nm resolution — a significant improvement over the current 13nm resolution of EUV tools. This technology allows for printing transistors that are 1.7 times smaller and achieve 2.9 times higher transistor densities with a single exposure, versus Low-NA tools. 

Although Low-NA systems can match this resolution, they have to use a costly double-patterning technique. Achieving 8nm is critical for manufacturing sub-3nm process chips, which are set to arrive in 2025–2026. The introduction of High-NA EUV technology is set to eliminate the need for EUV double patterning — thereby streamlining production processes, potentially enhancing yields, and cutting costs. However, High-NA tools cost up to $400 million each and introduce numerous challenges, which have complicated the transition to leading-edge process technologies (set to happen in the second half of the decade). 

At the SPIE Advanced Lithography + patterning conference in San Jose, California, experts from different sectors of the lithographic ecosystem discussed the prospects of Low-NA and High-NA extreme ultraviolet (EUV) lithography. Their views ranged from highly optimistic to cautious, particularly regarding High-NA EUV. For memory production, a Samsung rep noted worried about the costs associated with High-NA EUV.

Young Seog Kang, a Fellow at Samsung involved with memory production, said that Low-NA EUV is already operational, and chip manufacturers might prefer using double patterning with Low-NA EUV or resorting to advanced packaging techniques as more economical alternatives rather than using High-NA EUV. For memory, he predicted a shorter lifespan for EUV in general, citing potential challenges in performance and cost when trying to extend the technology. However, he acknowledged that EUV might remain relevant longer for logic chips due to their more complex layouts.

"As a user, I am always concerned with total cost," Kang said.

One of the challenges with post-3nm production technologies is the necessity to lower critical dimensions (i.e., increase resolution) produced by lithography systems from 13nm to 8nm. This could be done by employing EUV machines with projection optics featuring a 0.55 numerical aperture (High-NA); using double patterning with EUV systems with projections optics featuring a 0.33 NA (Low-NA); or by using pattern shaping systems like Applied Materials's Centura Sculpta (which allows reducing EUV double patterning steps but does not eliminate them or the use of High-NA EUV); and by enhancing other process-related factors, such as photoresist properties, illumination settings, and mask enhancements.

Intel plans to adopt High-NA EUV lithography and Applied's Centura Sculpta for its upcoming process technologies (Centura Sculpta starting at 20A and High-NA EUV starting at 14A); other chipmakers are researching High-NA EUV.

There are other potential paths to increased capabilities and lower costs with EUV — Intel's Frank Abboud, vice president and general manager of mask operations, discussed employing phase shift masks to enhance EUV lithography. Such masks, beneficial in DUV lithography, use phase differences to improve image resolution. Although phase shift masks have not yet been developed for EUV, Abboud believes they are achievable.

Jan van Schoot, director of system engineering at ASML, outlined several approaches to enhance the resolution and extend the utility of EUV lithography. In addition to increasing the numerical aperture of projection optics, it is possible to optimize k1, a coefficient that represents a lithography system's resolution capability. This could be done using various methods, including photoresist qualities, illumination settings, and mask enhancements. He said ASML is actively working on a new illuminator and other strategies to improve k1, and the company has some promising ideas in the pipeline.

Mark Slezak, the president of JSR USA (a photoresist supplier), suggested that EUV technology could last 20 years. He drew parallels with the extended use of DUV lithography, which lasted much longer than anticipated due to innovations like immersion lithography and multi-patterning. Slezak believes similar advancements could prolong EUV's relevance, with High-NA EUV being a potential example.

Late last year, ASML began shipping its first high-NA extreme ultraviolet (EUV) lithography system to Intel, and this past weekend, the processor giant published a video covering the installation of the tool into its fab near Hillsboro, Oregon. The machine will be used primarily for research and development purposes.

ASML's Twinscan EXE:5000 High-NA EUV machine is indeed absolutely massive. In total, 250 crates are required to transport the machine, which weighs in the neighborhood of 330,000 pounds. 

A cargo plane transported the container in the video from The Netherlands to Portland, Oregon, and then a truck delivered one of the key components of the tool. As you can see in the video below, the unit has been installed at the fab, but it will take 250 ASML and Intel engineers about six months to install the machine completely.

But even when the Twinscan EXE:5000 High-NA EUV machine is fully assembled, ASML and Intel engineers will still need to calibrate it. This will take weeks if not months. At first, the two companies will have to 'light up' the device, which is when photons hit resist on wafers, which ASML engineers recently achieved with their High-NA EUV tool in Veldhofen, the Netherlands.

ASML's High-NA EUV Twinscan EXE tool can print at an 8nm resolution, significantly enhancing the performance of currently used Low-NA EUV scanners, which are limited to 13nm resolution with a single exposure. This advancement enables building transistors that are about 1.7 times smaller than today, resulting in almost triple the transistor density. Achieving 8nm critical dimensions is crucial for producing chips using sub-3nm process technologies, a target the industry hopes to reach between 2025 and 2026.

Intel will use its Twinscan EXE:5000 lithography tool mainly to learn how to use High-NA EUV technology. The company plans to test the usage of High-NA lithography with its Intel 18A process technology (albeit not for high-volume production) and eventually adopt it for high-volume manufacturing with its Intel 14A fabrication process.

ASML previously announced that its next-generation High-NA EUV chipmaking tool would be more than double the price of its current Low-NA EUV lithography tools, or approximately $380 million (€350 million). However, the exact price will depend on the actual configuration of the device — Intel CEO Pat Gelsinger recently said the machine cost '400-ish million.'

In comparison, existing Low-NA Twinscan NXE EUV systems are priced at around $183 million (€170 million), with variations based on specific models and configurations. Intel may be the first to receive this cutting-edge fabrication tool, but ASML has disclosed “10 to 20” orders for its High-NA EUV machines from companies like Intel, Samsung, SK Hynix, and TSMC.

ASML and Intel said this week that the latter had achieved a significant milestone with ASML's High-NA lithography system by turning on its light source and making the light reach resist on a wafer, according to a report from Reuters. This indicates that the light source and mirrors are aligned correctly, a critical step in the bring-up process. This 'first light' milestone indicates that one of the main components of the Twinscan EXE:5000 system is operational, though not yet at peak performance. 

ASML's Twinscan EXE High-NA EUV litho machines with projection optics featuring a 0.55 numerical aperture can achieve resolution of down to 8nm with a single exposure — down from typical Low-NA EUV systems that offer a 13.5nm resolution with a single exposure. The first of these systems is currently housed at ASML's laboratory in Veldhoven, Netherlands, while a second is being assembled at an Intel facility near Hillsboro, Oregon. 

"Technically, this 'first light' actually is 'first light on the wafer,'" explained Marc Assinck, a spokesman for ASML. "The light source was already working, now we have the photons 'in resist' on the wafer." 

ASML specialists are still calibrating the High-NA tool in the Netherlands, so the machine yet has to print its first test patterns.

The development was initially disclosed by Intel's Ann Kelleher at the ongoing SPIE lithography conference in San Jose, California. Intel is currently assembling its first Twinscan EXE:5000 lithography machine at its site near Hillsboro, Oregon. The machine will be used primarily for process development purposes when it is assembled several months down the road.

In a recent test, the Veldhoven machine successfully demonstrated its capabilities on a silicon wafer prepared with photoresists, indicating its readiness for circuit pattern printing. This achievement, referred to as 'first light on the wafer' marks a significant step forward in the field of High-NA EUV lithography.

High-NA EUV lithography is anticipated to be adopted by leading chipmakers, including Intel, Samsung, and TSMC, within the next few years. Intel has already expressed intentions to utilize the system for its upcoming Intel 14A node-based generation of chips.

Light source is among the most complex part of any extreme ultraviolet (EUV) lithography tools. Neither ASML nor Intel disclose maximum performance (wattage) of Twinscan EXE's light source.

Shrinking transistor dimensions is critical for continued scaling of chip performance, so the semiconductor industry is working on various ways to make transistors smaller. In the coming years, chipmakers are set to adopt ASML's latest high-NA extreme ultraviolet (EUV) lithography tools, which will be particularly useful for post-3nm-class fabrication nodes. But what's next? ASML says that Hyper-NA is currently being explored for as-yet-undefined new tools that would arrive in the 2030s to power future generations of chips.  

"Hyper-NA with an NA higher than 0.7 is certainly an opportunity that will become more visible from around 2030," wrote Martin van den Brink, chief technology officer of ASML, in ASML's 2023 Annual Report (via Bits & Chips). "It is likely to be most relevant for Logic — and it will need to be more affordable than [High-NA EUV] double patterning — but it may also be an opportunity for DRAM. For us, the key thing is that Hyper-NA is driving our overall EUV capability platform to improve both cost and lead time." 

ASML's current crop of EUV tools consists of Low-NA models, which feature 0.33 NA optics and can achieve a critical dimension (CD) of 13.5 nm. That's sufficient to produce a minimum metal pitch of 26 nm and an approximate interconnect space pitch of 25–30nm tip-to-tip with a single exposure patterning. These dimensions are good enough for 4nm/5nm-class production nodes. Still, the industry will need 21-24nm pitches for 3nm, which is why TSMC's N3B process technology is designed to use Low-NA EUV double patterning to print the smallest possible pitches. This approach is considered very expensive.  

Next-gen High-NA EUV systems with 0.55 NA optics will achieve a CD of 8nm, which will be enough to print a minimum metal pitch of around 16nm, which will be useful for nodes beyond 3nm and is expected to be good enough even for 1nm, at least according to figures envisioned by Imec.

But metal pitches will get even smaller beyond 1nm, so the industry will need more sophisticated tools than ASML's High-NA devices. This leads us to Hyper-NA tools with even higher numerical aperture projection optics. ASML's CTO, Martin van den Brink, confirmed in an interview with Bits & Chips that the viability of Hyper-NA technology is being investigated. Still, no final decision has been made yet. 

Increasing the numerical aperture of projection optics is a costly process involving significant changes to the design of the lithography tools. In particular, this includes the machine's physical dimensions, the need to develop many new components, and the impact of increased costs. A Low-NA EUV Twinscan NXE machine costs $183 million or higher depending on configuration, and a High-NA EUV Twinscan EXE tool will be priced at $380 million or higher depending on configuration, ASML recently disclosed. Hyper-NA would cost more than that, so ASML has to answer two questions: whether it can be done technologically and whether it will be economically viable for the leading logic chipmakers.

Only three leading-edge chipmakers are left: Intel, Samsung Foundry, and TSMC. Japan-based Rapidus has yet to develop into a feasible competitor. So, while Hyper-NA EUV lithography is needed, it has to be reasonably affordable. 

"The introduction of Hyper-NA will be determined by the extent to which we can reduce costs," Martin van den Brink told Tweakers.net last year. "I have traveled around the world several times and have spoken with customers about the necessity and desirability of Hyper-NA. In recent months, I have gained the confidence and insight that customers want to drive the resolution down so much further, that the possibility for the use of Hyper-NA for mass production of logic and memory chips is there. That would be around the next decade change. But it depends on the costs."

Unlike Intel, TSMC hasn't announced when it plans to start using ASML's next-gen High-NA extreme ultraviolet (EUV) chipmaking tools, which has naturally led to plenty of speculation about its intentions. A month ago, an analyst wrote in a note to clients that TSMC would wait to use High-NA tools until it begins producing its 1nm process technology. This week, DigiTimes added its voice to that story with its own sources at fab toolmakers confirming that TMCS would wait until 1nm to use the next-gen tool, though we do have to caution that TSMC hasn't officially announced the news. 

TSMC's delay could boil down to cost concerns. Analysts from SemiAnalysis believe that TSMC will only begin to use High-NA EUV systems with its 1nm-class process technology (known as A10), which, assuming TSMC retains its current cadence of introducing new nodes, would happen sometime in 2029 – 2030 (production start – availability). 

Intel is set to use High-NA EUV tools for its post-18A process technology, which probably means it will begin using them in the 2026 – 2027 range (though Intel has not formally confirmed the timeframe). Meanwhile, all of the leading makers of logic and memory have purchased High-NA EUV tools for their research and development (R&D) efforts but have not set any deployment schedules publicly. 

High-NA EUV lithography tools allow the achievement of 8nm dimensions with a single exposure, significantly improving over the 13nm featured by existing Low-NA EUV tools. However, not all chipmakers are in a rush to deploy these chipmaking tools commercially because existing EUV systems can achieve an 8nm resolution with double patterning, ostensibly for lower overall cost. High-NA EUV tools are also exceedingly expensive and require substantial changes to existing fabrication facilities to accommodate their immense size. 

One thing to keep in mind is that plans tend to change based on the performance of existing technologies as well as other market factors. That said, while it might not look like TSMC is set to insert High-NA EUV tools any time soon, the plans aren't official, and if they were, the company's plans are always subject to change.

ASML has now fired back at criticism from analysts at SemiAnalysis who believe that, for at least some chipmakers, using the company's next-gen High-NA chipmaking tools makes little financial sense. However, in a recent interview with Bits and Chips, the company's CFO said that High-NA is on track and healthy and that the analyst firm has underestimated its benefits. During the company's recent earnings call, ASML's CEO also responded to questions about the report, saying the new tech is "very clearly the most cost-effective solution both in logic and memory.”

ASML's Twinscan EXE High-NA EUV lithography tools are vital for producing next-generation process technologies smaller than 2nm. But they are also significantly more expensive than existing Twinscan NXE Low-NA extreme ultraviolet (EUV) lithography tools — some say they cost between $300 million and $400 million. They also have other peculiarities, such as halved reticle size and large dimensions, which is part of the reason some analysts contend the tools aren't economically viable for all production lines.

As one would expect, ASML disagrees with that assessment, with the company's CFO telling Bits and Chips that orders are matching the company's expectations and that SemiAnalysis has underestimated the value of reducing process complexity by avoiding costly double- and quadruple-patterning. He also said that one could simply speak with Intel about the complications imposed by double-patterning, a reference to Intel's failures with 10nm which were at least partially due to a lack of EUV technology, to gain an understanding of the difficulties. In fact, Intel is the lead customer for High-NA today, having recently received the first parts of the first High-NA machine shipped to a customer. Let's take a closer look at the issues.

Simpler Manufacturing

Double- and quadruple-patterning involves repeatedly exposing the same layer of a wafer multiple times to create smaller features than normally possible, but it introduces chances for defects, which impacts yields and is more costly than simply printing the layer with one step.

The overall cost of double- and quadruple-patterning with Low-NA tools, and how that compares to single-patterning with a High-NA tool, appears to be one of the primary points of contention between ASML and the analysts.

By now, an eager reader would have probably asked why all the hassle with High-NA EUV if Low-NA EUV tools can achieve the same critical dimensions as the former by using double patterning and/or pattern shaping tools? Indeed, Intel is inserting Applied Materials's Centura Sculpta pattern shaping tool into its Intel 20A flow to avoid costly EUV double patterning in some cases. Meanwhile, Intel 18A indeed relies on both Centura Sculpta pattern shaping and Twinscan NXE double patterning. 

But EUV double patterning may not be that bad. Apple uses TSMC's N3B process technology, which reportedly uses double-patterning, for its mass-market products, which include hundreds of millions of iPhone 15 Pros and M3-based Macs.

ASML believes that implementing double patterning incurs certain drawbacks: EUV double patterning leads to longer production times, creates more chances for defects to occur, and potentially impacts the performance variability of produced chips. However, with the EXE:5000's critical dimension (CD) of 8nm, chipmakers can streamline their manufacturing processes. 

Foundries certainly understand both the pros and cons of using High-NA EUV scanners, so they are starting their research and development work already.  

"Our customers will start their R&D in 2024–2025 and move into high-volume manufacturing in 2025–2026," a statement by ASML reads.

ASML recently shared more details about its new High-NA machines; here's the rundown of how the tools work. 

New Tools are Incoming (and Needed)

ASML's next-generation Twinscan EXE has a 0.55 numerical aperture (NA) lens, so it's set to achieve a resolution of 8nm (critical dimension), marking a substantial advancement from the current EUV tools that offer a 13nm resolution. That means it can print transistors 1.7 times smaller – and therefore achieve transistor densities 2.9 times higher – than they can with Low-NA tools with a single exposure.

Low-NA litho systems can achieve a similar resolution, albeit with two exposures, with a costly double-patterning process. Achieving critical dimensions of 8nm is crucial for the production of chips using sub-3nm process technologies, which the industry plans to adopt between 2025 and 2026. 

High-NA EUV implementation promises to enable fabs to sidestep the need for EUV double patterning, simplifying the processes, possibly improving yields, and reducing costs. But it brings a lot of challenges, too.

Halved Exposure Field

Meanwhile, ASML's Twinscan EXE lithography tools, equipped with a 0.55 NA lens, completely differ from existing machines. The main and obvious difference is indeed the new and larger lens. But the adaption of a bigger lens requires larger mirrors, which is why Twinscan EXE tools also feature an anamorphic optics design.  

This approach addresses the issue of larger mirrors causing light to strike the reticle at a steeper angle, which reduces reflectivity and hinders pattern transfer to the wafer.

Instead of uniformly shrinking the pattern, the anamorphic optics magnify it differently: 4x in one direction and 8x in the other. This reduces the light's angle of incidence on the reticle, solving the reflectivity problem. Additionally, this method allows chipmakers to continue using standard-sized reticles, minimizing the impact on the semiconductor industry. This approach has a problem: it halves the size of the imaging field (from 33mm x 26mm to 16.5mm x 26mm), often referred to as High-NA halving the reticle size. 

The halved imaging field size prompts chip manufacturers to revise their chip design and production strategies. This change is especially crucial as high-end GPUs and AI accelerators are increasingly challenging the limits of reticle/imaging field sizes. 

Faster Stages

Due to their anamorphic optics and exposure fields half the size of Twinscan NXE systems, Twinscan EXE tools need to perform twice as many exposures per wafer, which halves the productivity of existing machines. To maintain (and eventually increase) productivity, ASML significantly increased the speed of the wafer and reticle stages. The EXE's wafer stage accelerates at 8g, double that of the NXE, while its reticle stage accelerates four times faster at 32g. 

 This enhancement allows the Twinscan EXE:5000 (which is, so to speak, largely a test system) to print over 185 wafers per hour at a dose of 20 mJ/cm², exceeding Twinscan NXE: 3600C's output of 170 wafers at the same dose.

ASML plans to increase this output to 220 wafers per hour by 2025 with the Twinscan EXE:5200 tools to ensure the economic viability of High-NA technology in chip manufacturing. Meanwhile, new nodes (i.e., lower resolution/critical dimensions) require higher doses, so Twinscan NXE: 3600D increases the dose to 30 mJ/cm², albeit at 160 wafers per hour. For some reason, ASML does not mention the performance of its EXE systems at a dose of 30 mJ/cm².

Bigger Fabs

ASML's High-NA EUV Twinscan EXE lithography tools are physically larger than Low-NA EUV Twinscan NXE litho machines. Existing and widely deployed ASML's Twinscan NXE place their light source under them, which requires a very specific fab building configuration and makes it trickier to service these tools. By contrast, High-NA Twinscan EXE machines place their light source horizontally, simplifying fab building and servicing but requiring larger cleanroom space. This, on the other hand, makes it trickier to upgrade existing fabs. 

Meanwhile, TSMC already has multiple fabs built specifically for Low-NA EUV Twinscan NXE litho machines. Upgrading these fabs to High-NA Twinscan EXE tools is a complicated task.

Considering the costs of the tools themselves, halved reticle size, complications with installing these tools into existing fab shells, very good performance of existing Low-NA tools, and many other specific factors that cannot be taken into account within the framework of one story, we can understand why analysts from China Renaissance believe that TSMC is not ready to adopt High-NA EUV tools for a while.  

Summary

The adoption of High-NA scanners with their enhanced resolution, larger dimensions, and halved exposure field necessitates the development of new photoresists, metrology, pellicle materials, masks, inspection tools, and perhaps even building new fab shells. In essence, the transition to High-NA tools will entail significant investments in the new tools and supporting infrastructure, so adoption won't be simple. 

However, High-NA EUV is the future, and the question of whether or not it is financially viable for large-scale deployments won't be answered definitively until we see how many chipmakers push the tools into production, and when. 

This week, Intel began to receive its first ASML's extreme ultraviolet (EUV) lithography tool with a 0.55 numerical aperture (High-NA), which it will use to learn how to use the technology before deploying the machines for a post-18A production node in the next couple of years or so. By contrast, TSMC is in no rush to adopt High-NA EUV any time soon, and it might be years before the company jumps on this bandwagon in 2030 or beyond, according to analysts from both China Renaissance and SemiAnalysis.

"In contrast to Intel's use of High-NA EUV soon after its shift to GAA (planned for [20A] insertion), we expect TSMC'sHigh-NA EUV insertion in the post N1.4 era (the inflection likely at N1, scheduled for post-2030 launch)," wrote Szeho Ng, an analyst with China Renaissance.

Intel's aggressive process technology roadmap includes the insertion of RibbonFET gate-all-around (GAA) transistors and PowerVia backside power delivery network (BSPDN) starting from 20A (20 angstroms, 2nm-class), then refining them with 18A, and then start using High-NA EUV tools for a post-18A node to offer the power, performance, and area characteristics and the lowest cycle time.

Modern EUV litho tools equipped with 0.33 numerical aperture lenses (Low-NA) provide an achievable critical dimension in the range of 13 to 16 nm for mass production, which is sufficient to produce a minimum metal pitch of 26 nm, and an estimated 25 to 30 nm tip-to-tip interconnect space pitch using single exposure patterning. This is sufficient for a 3nm-class process technology (with metal pitches between 21 and 24nm), but at 2nm and beyond, metal pitches will shrink to about 18–21nm (according to imec), which will call for the usage of EUV double patterning, pattern shaping equipment, or High-NA single patterning.

Intel plans to insert pattern shaping starting from 20A (which is about to enter HVM) and then High-NA EUV starting from a post-18A node, enabling the company to reduce the complexity of its process flow and avoid the usage of EUV double-patterning. However, High-NA EUV litho tools are significantly more expensive than Low-NA EUV scanners, but the High-NA EUV has many peculiarities, including a 2x reduced exposure field.

As a result, analysts from SemiAnalysis and China Renaissance believe that usage of High-NA EUV machines may be costlier than usage of Low-NA EUV double patterning, at least initially, which is why TSMC might not be inclined to use it for a while to ensure low costs albeit at the cost of production complexities and perhaps lower transistor density.

“Low-NA EUV multiple patterning, despite lower throughput on more exposure passes, may still cost less than high-NA EUV in the initial GAA foray; the higher source power of high-NA EUV to drive finer CD (critical dimension) speeds up wear on projection optics and photomasks, outweighing higher throughput benefits,” explained Szeho Ng. “This ties with TSMC’s practice to target the volume market with the most cost-competitive technologies.”

TSMC began to use extreme ultraviolet (EUV) lithography tools for high-volume production of chips in 2019, months after Samsung Foundry but years before Intel. Intel wants to be ahead of Samsung Foundry and TSMC with High-NA EUV, which could ensure some tactic and strategic benefits. The only question is, will TSMC be able to maintain its process technology leadership if it adopts High-NA litho only in 2030 or later (i.e., four to five years after Intel)?

ASML on Thursday announced that it had begun shipping the industry's first extreme ultraviolet (EUV) lithography tool with a 0.55 numerical aperture (High-NA) to Intel. The initial High-NA machine will be used to learn how it works on Intel's 18A (18 angstroms, 1.8nm-class) fabrication process, which promises to provide the CPU giant a lead over its rivals TSMC and Samsung.

"We are shipping the first High NA system and announced this in a social media post today," a spokesperson for ASML said. "It goes to Intel as planned and announced earlier."

As announced in September, ASML this week began to (literally) ship its High-NA EUV lithography tool to Intel. The unit will be shipped from Veldhoven, the Netherlands, to Intel's site near Hillsboro, Oregon, and will be installed there over the next few months. The machine is so big that it takes 13 huge containers and 250 crates to ship it. It is believed that each High-NA EUV scanner costs somewhere around $300 to $400 million.

The High-NA EUV tool that ASML ships is pilot Twinscan EXE:5000 machine which Intel acquired in 2018. This unit will be used by Intel to better learn high High-NA EUV tools work on its 18A process technology and gain valuable experience before the company will deploy commercial-grade Twinscan EXE:5200 machines for high-volume chip manufacturing beginning in 2025 using a post-18A production node.

High-NA EUV lithography tools equipped with a 0.55 NA (High-NA) lens can achieve a resolution of 8nm, a notable advancement over standard EUV tools with a 0.33 NA (Low-NA) lens that offer a 13nm resolution. High-NA technology are projected to play a crucial role for post 2nm-class process technologies that will either need to use Low-NA EUV double patterning or High-NA EUV single-patterning.

Since High-NA lithography tools have a number of differences with Low-NA litho machines that will require a lot of infrastructural changes, deploying a Twinscan EXE quarters ahead of its rivals could be a huge advantage for Intel. On the one hand, Intel will have plenty of time to adjust its post-18A process technologies. On the other hand, the company will adjust High-NA infrastructure for itself, which will give it another advantage over its competitors. 

Intel will be the first company to get an extreme ultraviolet (EUV) lithography tool with a 0.55 numeric aperture (high-NA) from ASML this year and it's also going to obtain the majority of the company's machines in 2024, according to a report by TrendForce. These tool procurement tactics indicate that Intel is poised to use Twinscan EXE machines extensively, going forward. 

Intel is about to get its first Twinscan EXE:5000 pilot scanner from ASML and plans to use it to learn how to better apply high-NA EUV lithography into commercial production of chips. The company initially planned to use this litho technology for its Intel 18A (18 angstroms, 1.8nm-class) production node to print the smallest features possible, but instead opted for EUV multi patterning as high-NA tools are coming later than expected. 

The additional six high-NA EUV litho tools that the company is going to get next year — Twinscan EXE:5200 scanners — will be used for mass production of chips using Intel's 18A or other process technologies in 2025 and onwards.

Usage of the Twinscan EXE may positively affect the company's production cycles, though it is hard to say whether this will have a positive effect on Intel's costs as these machines will be considerably more expensive (some say between $300 million and $400 million) than ASML's Twinscan NXE:3600D or NXE:3800E — which already exceed $200 million. Furthermore, because high-NA litho tools have two times smaller reticle size, their usage will be different from what we see with typical EUV machines.

Intel will be ahead of its rivals when it comes to high-NA learning, which will give it several advantages. Specifically, because Intel will likely be the first company to initiate high-volume production with high-NA tools, the fab tool ecosystem will inevitably follow its requirements. Said requirements will likely translate to industry standards, which will probably give Intel strategic advantages over rivals from TSMC and Samsung Foundry.

But Intel's rivals are also looking to obtain high-NA tools. Samsung Electronics' vice chairman and head of the company's device solutions division Kyung Kye-hyun said this week that the company reached an agreement with ASML regarding procuring high-NA tools. 

"Samsung has secured a priority over the high-NA equipment technology," Kyung Kye-hyun said, according to SamMobile. "I believe we created an opportunity for us to optimize the usage of high-NA technology for our production of DRAM memory chips and logic chips in the long term."

ASML is on track to ship the industry's first extreme ultraviolet (EUV) lithography scanner with a 0.55 numerical aperture (NA) this year, the company's chief executive said this week. ASML's Twinscan EXE:5000 machine will be primarily used for development purposes and getting the company's customers familiar with the new technology as well as its capabilities. Commercial usage of High-NA tools is slated for 2025 and beyond. 

"A few suppliers had some difficulties in actually ramping up and also giving us the right level of technological quality, so that led to some delay," said Peter Wennink, chief executive of ASML, in a conversation with Reuters. "But in fact, the first shipment is still this year.

This year ASML will ship its Twinscan EXE:5000 scanner to one undisclosed customer. The client will likely be Intel as the company once publicly disclosed plans to use High-NA scanners for its 18A process technology — but eventually had to opt for a different solution involving EUV double patterning and pattern shaping using Applied Materials' Centura Sculpta system (as commercial Twinscan EXE:5200 scanners would only be available in 2025).

Intel will likely adopt ASML's High-NA tools for its post-18A process technologies, whereas its rivals from TSMC and Samsung will use them later in this decade. But those scanners are not going to be cheap. It is estimated that they may cost over $300 million per unit, which will further rise costs of leading-edge fabs.

ASML's contemporary EUV scanners with a 0.33 NA and a 13nm resolution can print chips with metal pitches of around 30nm with single exposure patterning, which is good enough for production nodes like 5nm or 4nm-classes. For everything finer, chipmakers either need to use EUV double patterning or pattern shaping techniques, which is what they are going to be doing for the next couple of years. But beyond that they plan to use ASML's next-generation High-NA EUV scanners with a 0.55 NA and a resolution of around 8nm.

It is necessary to note that 0.55 NA EUV tools will not supplant the current deep ultraviolet (DUV) and EUV equipment in contemporary fabs, just like introduction of 0.33 NA EUV did not phase out DUV lithography. ASML will keep advancing its DUV and 0.33 NA EUV scanners for the foreseeable future. Concurrently, High-NA EUV lithography will play a pivotal role in shrinking transistor dimensions and boosting their performance.

ASML on Wednesday posted record revenue and profits as demand for chip production equipment hit records despite slowdown of PC and smartphones sales. The company's backlog for its products — including deep ultraviolet (DUV) lithography scanners and extreme ultraviolet (EUV) litho tools — now exceeds $38 billion as chipmakers continue to invest in wafer fab equipment (WFE). ASML continues to sell its DUV tools to Chinese customers. Furthermore, all current EUV customers have committed to High-NA EUV tools. 

Record Demand

ASML's third quarter sales came in at €5.8 billion as it sold 80 new lithography systems as well as six used scanners, including 12 EUV tools (in line with Q2) as well as 74 DUV machines (down from 79 in Q2).

The company's profits reached €2.994 billion in the quarter, while its gross margins hit 51.8%. Some of TSMC clients prefer so-called fast shipments — a shipment process that omits some of the testing at ASML's facilities and brings final testing and formal acceptance to the customer site — so some of the company's Q3 2022 sales will be recognized in the following quarter(s).  

While demand for PC, smartphone, and consumer electronics chips is getting weaker, chipmakers expect sales of their products to start increasing in 2024 ~ 2025, which is when they are going to need new production capacity with installed tools. At present there are multiple fabs being built by such leading companies such as Intel, Micron, Samsung, and SK Hynix that will need equipment in the coming years. For ASML this meant record bookings of around €8.9 billion in the third quarter, of which €3.8 billion were EUV litho tools, including those with 0.33 numerical aperture as well as High NA systems with 0.55 numerical aperture.

As of today, ASML's backlog exceeds $38 billion (up from $33 billion in Q2), which includes well over 600 DUV scanners as well as well over 100 EUV scanners.  

"85% of that order book really is for EUV and for immersion, so really caters to the more advanced and strategic part of semiconductor manufacturing," said ASML's chief financial officer Roger Dassen. "They really are building capacity also beyond 2023. And also there is still this element of tech sovereignty that we have been talking about. The fact that governments want to be more self-sufficient in their semiconductor manufacturing. So those secular trends are still very much intact, and I think that creates a situation that we are seeing where the lion's share of the customers are really still pushing us to get the tools sooner rather than later."

It will take years for the company to deliver these tools, as its target production capacity for 2023 is over 375 DUV machines and over 60 EUV machines. 

"ASML expects fourth quarter net sales between €6.1 billion and €6.6 billion with a gross margin around 49%," said Peter Wennink, chief executive of ASML. "For the full year, we expect revenue of €21.1 billion with a gross margin approaching 50%."

ASML to Keep Shipping to China, For Now

Unlike WFE suppliers from the U.S., ASML did not lower its guidance for Q4 due to U.S. sanctions against the Chinese semiconductor sector that prohibit American chip production technologies from being shipped to China without a special export license from the U.S. Department of Commerce. 

ASML is based in the Netherlands and does not use many parts designed or produced in the U.S. inside its DUV tools — therefore it can ship most, if not all, of its DUV tools to companies such as Semiconductor Manufacturing International Co. (SMIC), Hua Hong, and Yangtze Memory Technology Co. (YMTC), according to its chief financial officer Roger Dassen. 

"We are still in the process of evaluating the [U.S. restrictions against China's chip industry]," said Dassen. "Our initial appreciation is that the direct implication for us is fairly limited. […] We will do whatever it takes to follow [the new U.S. export laws]. […] But the fact that we are a European company with limited U.S. technology in [our tools] of course creates this situation where a direct impact on us is fairly limited. We can continue to ship non-EUV lithography tools out of Europe into China." 

ASML could not ship EUV scanners to its Chinese customers due to the Wassenaar Arrangement and now cannot ship them to China because they use Cymer's light sources designed and produced in the USA. Since ASML never expected to ship its Twinscan NXE scanners to its clients in China (which is why potential shipments EUV shipments to China were never counted in any guidance) and the impact of U.S. crackdown of Chinese semiconductor industry on ASML is projected to be limited, the company did not update its expectations for the fourth quarter and for the year 2022. 

Meanwhile, ASML admits that there might be indirect impact on sales of its DUV tools to its Chinese clientele. Fabs need different kinds of machinery to operate, so if a customer does not get tools from Applied Materials or KLA, it may not need ASML's lithography scanners and may cancel its orders. This is somewhat unlikely as companies like SMIC and YMTC have billions in government subsidies and will probably continue to buy new litho tools while they can, and attempt to procure used American tools or parts made for U.S.-made equipment on the secondhand market.

And even if Chinese customers cease buying lithography tools from ASML, demand still outpaces supply and its backlog is so huge that sales to other clients will more than offset sales to companies in China.

All EUV Customers Committed to High-NA EUV

More good news for ASML this quarter are additional orders for its first commercial High-NA scanner, the Twinscan EXE:5200. At least one of the orders came from its current EUV customer that previously has not ordered this tool, which means that all companies that use (or plan to use) extreme ultraviolet lithography with 0.33 numerical aperture will eventually migrate to next-generation EUV lithography with 0.55 NA. 

Previously the company said that three Logic and two Memory customers had ordered its High-NA scanners, and while ASML did not disclose names of its 0.55 NA EUV clients, we can deduce that it meant Intel, Samsung Foundry, and TSMC (Logic) as well as Samsung and SK Hynix (Memory). ASML does not disclose the name of its latest High-NA EUV customer for obvious reasons, but it is reasonable to assume that Micron ordered its first High-NA scanner in the third quarter. 

Currently Micron is building two leading-edge memory fabs in the U.S. — in Utah and New York — that are set to start ramping up DRAM production in a 2025 – 2026 timeframe. Initially both fabs will use Twinscan EXE 0.33 EUV tools, but eventually Micron will need something even more advanced, which is why it is going to need 0.55 EUV scanners. Apparently the company has already begun preparing for the next generation. 

Micron yet has to comment on its High-NA EUV commitment, but we have all reasons to believe that the company is looking forward ASML's next-generation High-NA EUV production tools.

Summary

While demand for logic and memory chips aimed at PCs, smartphones, and consumer electronics got lower in the recent months and are unlikely to rebound in the next two or even three quarters, chipmakers continue to invest in their fabs — thus bringing their money to ASML. Demand for WFE is so high that ASML's backlog for advanced equipment increased to $38 billion in Q3, or by $5 billion in just one quarter. 

While American companies now require a special export license from the U.S. DoC to sell their wafer fab equipment to customers in China, ASML believes that it can export its DUV scanners to the People's Republic without any restrictions. While it remains to be seen whether U.S. sanctions against China's semiconductor industry will hit ASML indirectly, demand for the company's tools around is so strong that even complete loss of Chinese clients might not be seen for at least a couple of years. 

Leading makers of logic and memory chips that currently use EUV scanners that cost $160 – $170 per unit all plan to adopt even more advanced High-NA EUV machines in the future, ASML said.

Intel is clearly behind its rivals TSMC and Samsung with the first generation of extreme ultraviolet (EUV) lithography technology, but it certainly wants to be the first to adopt the next-generation EUV tools featuring a 0.55 NA (or high-NA) that provides higher resolution and productivity. This week Intel announced that it had ordered its second experimental High-NA tool from ASML.  

Intel announced plans to adopt ASML's High-NA Twinscan EXE scanners for high-volume manufacturing (HVM) starting in 2025, which is when the company intends to start using its 18A (~1.8 nm) fabrication technology. To do so, Intel has experimented with High-NA tools since 2018 when it obtained ASML's Twinscan EXE:5000, the industry's first EUV scanner with a 0.55 numerical aperture. This week the company ordered ASML's next-generation High-NA tool, the Twinscan EXE:5200. 

"Compared to the current EUV systems, our innovative extended EUV roadmap delivers continued lithographic improvements at reduced complexity, cost, cycle time and energy that the chip industry needs to drive affordable scaling well into the next decade,” said ASML President and CTO Martin van den Brink. 

High-NA EUV tools are crucial for higher resolution (<8 nm vs ~13 nm for 0.33 NA EUV) that enables smaller transistors and higher transistor density. In addition to a completely different optics design, High-NA scanners promise to offer significantly faster reticle and wafer stages as well as higher productivity. For example, the productivity of the ASML Twinscan EXE:5200 is over 200 wafers per hour (WPH). In contrast, ASML's top-of-the-range 0.33 NA EUV machine, the Twinscan NXE:3600D, produces around 160 WPH with a 13.5nm light wavelength.

"Intel's focus is to stay at the forefront of semiconductor lithography technology and we’ve been building our EUV expertise and capacity over the last year," said Dr. Ann Kelleher, executive vice president and general manager of Technology Development at Intel. "Working closely with ASML, we will harness High-NA EUV's high-resolution patterning as one of the ways we continue Moore's Law and maintain our strong history of progression down to the smallest of geometries." 

Just like the adoption of 0.33 NA EUV did not eliminate the usage of deep ultraviolet (DUV) lithography, 0.55 NA EUV will not replace the existing DUV and EUV tools used in modern fabs. In fact, ASML plans to continue developing more advanced DUV and 0.33 NA EUV scanners for years to come. Meanwhile, High-NA EUV lithography will be a key technology to reduce transistor sizes and increase transistor density.