On June 12th, the U.S. Commerce Department issued an export-control directive barring Anthropic from supplying Fable 5 or Mythos 5 to any foreign national, forcing the company to disable both models worldwide. The next day, Beijing-based Z.ai, formerly Zhipu AI, began rolling out GLM-5.2, an open-weight model it released under a permissive MIT license. The new model was purportedly trained entirely on Huawei Ascend chips with no Nvidia hardware.

Within a week, GLM-5.2 had climbed to the top of the openly available leaderboards, Z.ai's market value had passed HK$1 trillion (about US$128 billion), and the most capable model many users outside the U.S. could legally access was a free download from a company that sits on Washington's trade blacklist.

Trailing Anthropic

GLM-5.2’s results are both strong and uneven, taking first place on Design Arena's human-preference coding board, finishing roughly 10 Elo points ahead of Fable. It also ranks as the top openly available model on Artificial Analysis's Intelligence Index v4.1, where its score of 51 sits ahead of MiniMax-M3, DeepSeek V4 Pro, and Google's Gemini 3.1 Pro Preview. On the SWE-bench Pro, it scored 62.1, compared to GPT-5.5's 58.6.

In terms of longer work, such as Code Arena’s front-end board, the picture changes somewhat, with GLM-5.2 landing second behind Fable 5. On Artificial Analysis's AA-Briefcase test, which scores multi-week knowledge tasks built from thousands of fragmented inputs, Fable 5 led with 1,587 Elo, followed by Opus 4.8 at 1,356, and GLM-5.2 in third place at 1,266, before the export ban took Fable out of contention.

It also trails on raw terminal work, scoring 81.0 on Terminal-Bench 2.1 against Opus 4.8's 85.0 and GPT-5.5's 84.0, while clearing Google's Gemini 3.1 Pro at 74.0. GLM-5.2 holds the top accessible position today, partly because the models that beat it on these benchmarks are largely an Anthropic pair, and Fable is now switched off.

No Nvidia

GLM-5.2’s training stack is a slap in the face of Washington’s efforts to curtail Chinese model development. Z.ai has been on the U.S. Entity List since January 2025, cutting it off from Nvidia's H100, H200, and B200 accelerators, and it says the GLM-5 family was trained on roughly 100,000 Huawei Ascend 910B processors using the MindSpore framework, with no Nvidia silicon at any stage. The export controls on advanced AI chips were designed to keep this kind of result out of reach, but they’ve evidently failed to do so.

That said, the Ascend 910C sits at roughly 60% of an Nvidia H100’s inference performance, per a December report from the Council on Foreign Relations, with a wide gap on efficiency and cluster scale. The same report projects that by as early as next year, the best U.S. chips could be more than 17 times more powerful than Huawei's top parts.

At the same time, Huawei has claimed that a 1,000-chip Ascend cluster handled full-parameter post-training of DeepSeek's V4. If true, this shows that Chinese domestic silicon can now carry training-class jobs, just not at Nvidia’s per-chip throughput or scale. So, while GLM-5.2 demonstrates that a frontier-class open model can be produced on a fully domestic stack, it doesn’t demonstrate that the chips underneath have caught up with Nvidia; model parity =/= hardware parity.

The Fable 5 shutdown

Anthropic released Fable 5 to the public on June 10th, a safety-restricted build of its Mythos 5 model designed to block the cyber and bio capabilities of the underlying system. Just two days later, the Commerce Department suddenly and unexpectedly ordered access to be pulled for all foreign nationals, including Anthropic's own non-citizen staff, after officials cited a technique for bypassing Fable 5's safeguards.

Anthropic said in an announcement following the restriction that the jailbreak it understood to be at issue was narrow rather than universal, surfaced only previously known minor vulnerabilities, and produced behavior also obtainable from other public models, including OpenAI's GPT-5.5. The company said in its statement that it believes the order rests on a “misunderstanding” and is working to restore access. But because the directive covered all foreign nationals, Anthropic had no way to keep the models live for U.S. users alone and disabled them for everyone.

Meanwhile, GLM-5.2’s MIT license lets anyone download, fine-tune, and self-host its weights, which is the basis for calling it a freely available model. Running it, however, is a separate matter: the model carries around 744 billion total parameters, 40 billion of them active per token, with a one-million-token context window. That’s no small footprint and calls for enterprise GPU clusters or high-memory workstations — it’s not something you’re ever going to get running on a desktop — and throughput drops sharply once context runs past tens of thousands of tokens.

The most practical way to use GLM-5.2 is via the API, where Z.ai prices the model at about $1.40 per million input tokens and $4.40 per million output, against $5 and $25 for Claude Opus 4.8, or $10 and $50 for Fable 5. On the AA-Briefcase runs, Fable 5 averaged $31 per task to GLM-5.2's $2.40, a roughly 13-times spread that holds even where Fable scored higher.

The market moved fast with GLM-5.2’s release. Z.ai, which is listed on the Hong Kong exchange as Knowledge Atlas Technology, saw its shares jump as much as 42% intraday on June 22nd to HK$2,980, carrying its market capitalization past HK$1 trillion. Founder Tang Jie has said publicly that a Chinese model matching Fable 5 will arrive sooner than the first-quarter timeline Elon Musk recently floated. There's a nearer date, too. On July 8th, the lock-up on Z.ai's first cornerstone investors expires, freeing a large block of shares to trade, which will give the GLM-5.2 rally its first real test.

Qualcomm has announced that it will bring all four of its Dragonfly data center product lines to China, including custom AI accelerators engineered to stay below U.S. export thresholds, CEO Cristiano Amon told Nikkei Asia on the sidelines of the company's investor day in New York on Wednesday. China supplied 46% of Qualcomm's revenue in 2025, almost all of it from smartphone silicon, and Amon’s data center plan could revive the same export-compliant strategy that cut Nvidia's China accelerator sales to almost zero.

Dragonfly covers AI accelerators, data center CPUs, custom silicon, and connectivity chips, and Amon said versions of every line will ship into China within the export rules. “We have versions of all of our products that comply with those guidelines,” he told Nikkei Asia, adding that Qualcomm is “engaged in conversations,” presumably with Chinese customers. The first accelerator, the AI250, is due next year and uses the company's HBC near-memory design instead of the HBM stacks that Nvidia and AMD racks rely on, a packaging choice that could pay off in a market where HBM is and will remain tight for the foreseeable future.

Qualcomm told investors that the data center unit is expected to generate $300 million this fiscal year and $5 billion in fiscal year 2027, figures the company designates as the early ramp of a total addressable market it projects will exceed $1 trillion by 2029. The push into China relies on Amon's argument that Qualcomm's existing relationships with Chinese phone makers and automakers extend to the data center, the same customer base behind its AI200 and AI250 inference accelerators announced last October.

China, however, isn’t a neutral buyer for Qualcomm at the moment: The country’s market regulator opened an antitrust investigation into its Autotalks acquisition in October, and has pressed domestic data center operators to source at least 50% of their chips locally while steering Alibaba, ByteDance, and Tencent toward Huawei and Cambricon parts.

Those dynamics have already gutted the export-compliant model that Qualcomm is looking to emulate. Nvidia’s H20, for example — the part it built specifically for China — had generated only about $50 million by late last year, and CEO Jensen Huang has said Nvidia has “zero” China market share left. Qualcomm is entering that lane voluntarily with hardware that won’t reach customers until at least fiscal year 2027, by which point Huawei's Ascend line and Cambricon's accelerators are scheduled to scale production well past current volumes.

Qualcomm has at least one confirmed buyer outside China, with Saudi Arabia's Humain already taking delivery of AI100 systems and committing to 200MW of Qualcomm racks. Inside China, the company still has to convince customers that Beijing is pushing away from foreign silicon.

China's LineShine supercomputer has dethroned El Capitan as the world's number one supercomputer, going straight to the top of the charts after the National Supercomputer Center in Shenzhen (NSCS) submitted its results.

LineShine hit 2.198 FP64 ExaFLOPS in the Linpack benchmark and became the industry's first machine in the Top 500 list to sustain more than 2 ExaFLOPS of double-precision performance using only CPUs. The system is deployed at the National Supercomputing Centre in Shenzhen and was built by the Shenzhen Cloud Computing Center using semi-custom 304-core LX2 processors based on the Armv9 instruction set architecture and running at 1.55 GHz. The machine employs 13.79 million cores in total, uses proprietary LingQi interconnect, and consumes 42.2 MW of power.

From a performance-per-watt point of view, the LineShine machine delivers 52.07 GFLOPS/W, which is below El Capitan's 60.94 GFLOPS/W. However, LineShine by far outperforms Fugaku — another CPU-only supercomputer that used to be the No.1 HPC system several years ago — that can only deliver 14.78 – 16.84 GFLOPS/W depending on whether its efficiency is optimized or not.

LineShine also moved to the top of the HPCG ranking with 22.00 HPCG-PFLOPS. However, the supercomputer achieved 7.92 mixed-precision EFLOPS in HPL-MxP, which puts it behind El Capitan, Frontier, and Aurora. This limits LineShine's usability for AI training and inference, but this can be justified with its exceptional performance for traditional supercomputer tasks.

Each LX2 CPU relies on two compute chiplets and has a total of 304 CPU cores organized into eight CPU clusters containing 38 cores each. Every core includes Arm SVE (Scalable Vector Extension) and SME (Scalable Matrix Extension) units that accelerate vector and matrix operations used in AI training and scientific computing that support FP64, FP32, BF16, FP16, and INT8 data formats. The chip features a rather unusual memory architecture that pairs 32 GB of on-package HBM, offering up to 4 TB/s of bandwidth with as much as 256 GB of external DDR5 memory to maximize both bandwidth and capacity.

Despite this, the processor only gains 3.6X performance when moving from FP64 to mixed-precision data, which is lower compared to systems that integrate low-precision accelerators, such as AMD's Instinct MI300A or Intel's Ponte Vecchio. While an Armv9 CPU with SVE/SME can accelerate FP16/BF16/INT8 workloads, its mixed-precision uplift remains limited compared to systems with accelerators due to many reasons, including memory bandwidth, software maturity, and interconnect efficiency. That said, it may be too early to make final conclusions about the LX2 and its usability for mixed-precision workloads.

In any case, the very fact that a Chinese supercomputer has achieved extraordinary FP64 performance is remarkable. Furthermore, the fact that NSCS has actually submitted results to Top 500 indicates that the organization is confident that the LineShine supercomputer relies exclusively on domestic technologies and the U.S. government cannot affect the production of these technologies.

German industrial and engineering giant Bosch has agreed to pay a $36 million penalty for selling goods and software to banned Chinese company Huawei between 2020 and 2024. According to the Bureau of Industry and Security (BIS), the company sold more than $72 million worth of MEMS sensors and automotive software during this period — items that required an export license from the Department of Commerce because they contained U.S.-origin technology, software, or intellectual property. These limitations apply to Bosch’s non-U.S. subsidiaries as well, which the company said unintentionally sold the products to Huawei.

The U.S. Justice Department (DOJ) said that it’s suspending its investigation into Bosch after it disclosed its own misconduct and that it won’t prosecute the company for this offense. “This declination reflects the clear benefits for ‌companies ⁠that promptly disclose potential violations and fully assist in our investigations,” Assistant Attorney General for National Security John A. Eisenberg said in a statement. “Bosch’s cooperation and timely remediation met the high standards set by the Corporate Enforcement Policy, supporting a fair and efficient resolution.”

Bosch will also surrender nearly $11.5 million in profits that it made with the Huawei sales. The BIS said that the DOJ has partially suspended this disgorgement, meaning the German firm will only pay $3.6 million, and that it will also count this towards its own $36 million fine on the company.

“Bosch had several opportunities to avoid these violations had they exercised the increased vigilance BIS has repeatedly said it expects of companies whose transactions are governed by the EAR (Export Administration Regulations),” Assistant Commerce Secretary for Export Enforcement David Peters said. “Today’s action should serve as a warning to embrace compliance and as an example of the benefits of voluntary self-disclosure.”

For its part, Bosch said in a statement to Reuters that it will improve its trade compliance program to prevent future violations.

The U.S. has been stepping up the enforcement of its export controls and have been prosecuting companies and individuals caught breaking them. The U.S. Senate previously found in 2024 that the BIS was underfunded and that it relies on voluntary compliance by the firms that it watches over, but it seems that this has since changed. In 2025, Cadence Design Systems, a leading electronic design automation (EDA) firm, paid a $140 million penalty for selling software to Chinese military institutions. Applied Materials was also fined $252 million earlier this year for allegedly exporting tools to Chinese chipmaker SMIC. Four Supermicro employees, including its co-founder Yih-Shyan “Wally” Liaw, have also been arrested for allegedly smuggling banned Nvidia GPUs into China.

SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm, tighter than the 36nm pitch shipping in Intel’s Panther Lake chips on 18A. The analysis was conducted on a HiSilicon Kirin 9030, the processor found inside Huawei’s Mate 80 phones and built on the N+3 process, which SemiAnalysis says trails Intel’s 18A high-density library by 38%. The SemiAnalysis Teardown Engineering & Evaluation Lab (STEEL) has been opened in Hillsboro, Oregon, and built to take on TechInsights in advanced-node reverse engineering.

A 36nm pitch is what Panther Lake ships with, but the 18A process on the whole supports a 32nm minimum metal pitch. With Panter Lake, Intel opted to relax the pitch because routing power through the back of the wafer — via PowerVia — clears the front-side metal stack for signal wiring.

Intel has said doing this buys roughly 10% higher density and looser front-side pitches, which is how a node built on GAA RibbonFET transistors and backside power can ship a wider local pitch than a DUV Chinese process and maintain a wide overall lead. SMIC reached 32.5nm without EUV lithography, leaning on DUV tools and quadruple-patterning that needs extra masking and etch passes.

Counting transistors per area, SemiAnalysis put N+3 at 113.4 million per square millimeter, just ahead of TSMC's mature N6 at 107.7 million and well behind 18A. SMIC got there by spending every density trick available without EUV: two fins per transistor, contacts landed directly over the active gate, and single diffusion breaks between cells.

Each of those workarounds obviously adds complexity and cost, with N+3’s ceiling ultimately showing a huge trade-off. The Kirin 9030 Pro's prime core runs at 2.75 GHz and lands near Arm's 2021-era Cortex-X2 per clock, leaving the chip roughly level with Android flagships from three years ago and behind current parts from Apple, Qualcomm, MediaTek, and Samsung. Huawei’s roadmap does say that it’s targeting 5 GHz by 2031, but, as SemiAnalysis notes, that’s “far beyond what planar scaling alone could deliver.”

SemiAnalysis said it spent the past 18 months building the lab and has already earned revenue analyzing datacenter silicon. “We have already generated revenue on advanced datacenter chip teardowns, including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack.”

The company is taking aim at the Ottawa-based TechInsights, which is backed by private equity and held by the likes of Oakley Capital and CVC Growth. SemiAnalysis claims its rival is up for sale and has underinvested in equipment as a result, though that hasn’t been officially confirmed. The teardown also found the Kirin 9030 Pro carrying Samsung LPDDR5X memory, with 16 GB variants turning up DRAM from Chinese maker CXMT as well.

China is drafting a plan to spend roughly 2 trillion yuan ($295 billion) over five years on a nationwide web of AI data centers. The goal is for at least 80% of the underlying technology, AI chips included, to be sourced from domestic suppliers such as Huawei, according to a Bloomberg report citing people familiar with the discussions.

The National Development and Reform Commission is responsible for the blueprint of this network, while state carriers China Mobile and China Telecom will operate most of the facilities and link them up to a single computing grid by 2028. The build-out of this grid leans heavily on sovereign debt and ultra-long special government bonds. Folding in power grid upgrades could push the total capital requirement beyond 5 trillion yuan, those sources told Bloomberg.

Funding the build-out is easy, though; filling them with domestic accelerators is a different story. The 80% domestic sourcing requirement effectively locks out Nvidia and AMD accelerators, so China will be capped by whatever amount of chips SMIC can physically produce. The foundry’s most advanced stable node remains its N+2 process, which is roughly equivalent to 7nm and is currently running above 93% utilization, leaving little headroom as every government-certified Chinese chipmaker competes for the same wafer slots.

Another major chokepoint is high-bandwidth memory. Highly limited domestic HBM supply constrains how many Ascend-class accelerators Huawei can assemble. Huawei alone shipped around 812,000 chips last year and projects some $12 billion in processor revenue for 2026, a pace that its own supply chain has struggled to sustain. It’s estimated that China’s domestic suppliers will cover only around 76% of all Chinese AI chip demand by 2030, even as that market grows toward $67 billion.

Beijing has massively tightened its restrictions on foreign silicon in a series of new controls. Last August, Beijing introduced a requirement that data centers source at least 50% of chips locally, and by November, state-funded projects were barred from foreign accelerators entirely, with builds less than 30% complete reportedly told to strip out Nvidia, AMD, and Intel parts.

China's own industry has questioned whether domestic hardware can keep pace. SMIC co-CEO Zhao Haijun has cautioned that the rush to add capacity risks leaving data centers idle, comparing it to building highways ahead of the traffic. Chinese chip executives have separately conceded the country trails the leading edge in AI data center silicon by five to 10 years. When DeepSeek was steered toward Huawei hardware for model training, it eventually reverted to Nvidia hardware, lending credence to the idea that domestic parts still struggle with the heaviest training workloads, even where they suffice for inference.

A research group that includes Huawei Technologies says it completed full-parameter post-training of DeepSeek's V4-Pro, a 1.6-trillion-parameter model. The group used a cluster of at least 1,000 Huawei Ascend 910C chips, according to the Shenzhen municipal government, as reported by the South China Morning Post.

The revelation is evidence that Chinese accelerators can now handle a training-class workload on domestic silicon, the part of the AI pipeline Chinese firms have had the most trouble moving off Nvidia hardware under U.S. export controls. Huawei carried out the work with the Shenzhen Loop Area Institute, the Shenzhen campus of Harbin Institute of Technology, and the Shenzhen Research Institute of Big Data.

The Ascend 910C is Huawei's current flagship AI accelerator, a dual-die part that returned roughly 60% of an Nvidia H100's inference performance in earlier DeepSeek testing. Chinese chips have been competitive at inference, where a finished model answers prompts, but weak at training, where a model's weights are recalculated across large datasets. The team says it ran full-parameter post-training, meaning every weight was updated rather than a thin adapter layer added on top.

Post-training is essentially the “tuning” stage that follows the much larger pre-training phase. Pre-training builds a model's core capabilities by working through enormous text corpora, and DeepSeek's documentation puts V4-Pro's pre-training corpus at more than 32 trillion tokens.

Post-training then shapes behavior through instruction-following, safety alignment, and task-specific data. Completing it on Ascend silicon is a genuine result for the platform, but it doesn’t demonstrate that the chips can pre-train a frontier model from scratch, which is the heavier and costlier job.

Back in August, it was reported that DeepSeek couldn’t complete a single successful training run for its R2 model in Ascend chips, even with Huawei engineers on site, blaming unstable performance, slow chip-to-chip interconnects, and gaps in Huawei's CANN software stack, its substitute for Nvidia's CUDA. The company fell back on Nvidia GPUs for training and left Ascend on inference. DeepSeek-V4-Pro, released in April, was the first DeepSeek model built around Ascend from the outset.

As for the claim coming out of Shenzen, it carries no benchmarks, gives no figure for how long the run took, how it compared to the same job on Nvidia hardware, or how efficiently the 1,000-chip cluster was used. It’s ultimately just another addition to a series of dubious claims that have come from the Chinese state without anything to back them up; DeepSeek itself hasn’t commented.

Huawei’s current Rotating Chairman and Deputy Chairman Xu Zhijun said during an interview that the company is thankful for the pressure that the U.S. has applied on it and China, in general. The comment came after someone asked how Huawei came up with the groundbreaking LogicFolding chip architecture the company developed, and Xu said that he was grateful toward the U.S. for allowing the company to achieve that, reports Huawei Central.

“If the United States hadn’t forced our country, our companies, and our industry, we wouldn’t have done something like this. But we are also grateful to the US for enabling our country’s semiconductor industry chain to truly grow,” the Huawei Rotating Chairman said. “Now the momentum is very good, and everyone recognizes and supports it.”

Huawei was one of the first major Chinese tech companies to get a blanket ban from the U.S., after it, along with several other Chinese tech companies, was excluded from the North American market in 2019 by the first Trump administration. In 2022, President Joe Biden enacted export controls on AI GPUs, essentially banning China-based firms from acquiring powerful hardware like the Nvidia A100 and H100, as well as AMD Instinct MI250 and MI250X chips.

Both companies eventually created less potent versions of their top hardware to comply with White House regulations. But even then, President Donald Trump enacted a complete export ban during his second term, forcing Nvidia to write-off $5.5 billion in GPUs and costing AMD $800 million in sales. Trump eventually made a 180-degree turn, allowing Chinese companies to acquire H200 chips as long as they can get an export license from the U.S. and that AMD and Nvidia pay a 25% fee to the federal government, but the semiconductor landscape has already changed by then.

While some firms resorted to smuggling and the black market to get their needed chips, the export controls forced the majority of them to look toward domestic alternatives instead. Even though these chips aren’t as powerful or efficient as what Nvidia or AMD offer, it's still better than having no chips at all. This means that local Chinese chip companies are getting more revenue, allowing them to reinvest their earnings into their R&D efforts. Because of this, they have started releasing chips that could somehow compete against what U.S. chipmakers can offer in terms of performance (although they still consume a lot more power).

This development is compounded by Beijing’s push for gaining semiconductor independence. So, even though many Chinese tech companies still want to buy Nvidia chips, likely because of its CUDA platform, the central government ordered these firms to purchase homegrown chips instead. It even went as far as instructing customs officers to block H200 AI chips at the border, and even recently extended the ban to the RTX 5090D V2 gaming GPU.

Nvidia CEO Jensen Huang has always been against AI chip export bans, arguing that keeping American technology readily available across the world is key to extending its influence. Furthermore, he said that cutting Chinese firms from U.S. hardware would only force domestic chipmakers to innovate and build solutions that would compete against what Nvidia has. True enough, Nvidia’s AI chip market share in China has fallen to “zero percent,” compared to the 95% it previously held before the AI chip bans. And even if that’s the case, Chinese firms still continue making frontier AI models and remain competitive against American AI tech companies.

The chip ban did have a negative effect on Chinese AI development, in that it delayed its progress for a few years. But in that short span, many homegrown firms stepped up and took on the challenge of developing alternatives to American tech. Today, we’re starting to see the fruits of their labor and investment, which wouldn’t have accelerated if Chinese tech companies could readily buy American chips.

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool built specifically for Huawei's LogicFolding architecture, according to the South China Morning Post. The tool takes what researchers described as a "true-3D" approach, optimizing an entire multilayer chip as a single vertical structure rather than designing each layer in two dimensions and stacking them afterward. In early tests of open-source circuit designs, the university reported a 30% reduction in total internal wire length, along with improvements in performance and thermal management, compared to conventional EDA workflows.

The announcement came two days after Huawei presented LogicFolding and its accompanying Tau Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai. Huawei's goal is to produce chips with transistor density equivalent to 1.4nm processes by 2031, all without access to the extreme ultraviolet (EUV) lithography equipment restricted under U.S. export controls.

LogicFolding works by folding traditional 2D circuit layouts into vertical 3D stacks, shortening the physical paths that electrical signals travel through a chip. That reduces resistance and capacitance on critical wiring, compressing signal propagation delay. Huawei's Kirin smartphone processors launching later this year will be the first commercial chips to use the architecture.

Synopsys and Cadence both offer 3D IC design platforms for multi-die stacking and advanced packaging. But those tools address a different problem: integrating separate chiplets or dies within a package. LogicFolding folds transistor-level logic within a single chip into vertical layers, an intra-die optimization that requires place-and-route tools to work across the full vertical structure simultaneously instead of partitioning separate dies.

Peking University's prototype reportedly addresses this by treating the multilayer structure as a unified design space from the start, but whether their claim of 30% wire-length improvement holds up at production scale remains to be seen.

Synopsys, Cadence, and Siemens EDA command 31%, 30%, and 13% of the global EDA market, respectively, and their combined share within China exceeds 80%, according to EE Times China. The U.S. imposed and then lifted EDA export restrictions last year as part of a rare-earth materials deal. Still, the episode highlighted how dependent Chinese chipmakers remain on Western tools.

China's domestic EDA companies, including Empyrean Technology and Primarius, have made progress in analog, mixed-signal, and physical verification, but none offer a full digital design flow competitive with the Western incumbents at advanced nodes.

A university prototype is a very long way from production-grade commercial software. EDA tools require years of development, extensive process design kit integration with foundries, and validation across thousands of tape-outs before chipmakers trust them. "No single company can independently find all the answers along the path of semiconductor evolution," He Tingbo, chairwoman of the Huawei Scientist Committee and president of the company's semiconductor business department, said at a media briefing on Monday.

Huawei has announced a new chip design framework aimed at closing the technology gap with global semiconductor leaders like TSMC and Nvidia, targeting '1.4nm-class' transistors and a 55% increase in transistor density. The firm also unveiled a new 'Tau Scaling Law' that's designed to replace Moore's Law for future chip scaling. Unveiled at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai on Monday, this new design method is intended to circumvent strict US trade sanctions. It allows the company to develop high-performance smartphones and AI processors without relying on restricted Western manufacturing equipment like extreme ultraviolet (EUV) lithography machines.

Delivering a keynote address at the symposium, He Tingbo — a Huawei board member and President of its semiconductor division, HiSilicon — unveiled the company's new, proprietary “LogicFolding” architecture. The cutting-edge design blueprint is built directly upon the newly introduced Tau Scaling Law.

He revealed that Huawei has spent the last six years quietly refining the methodology, secretly designing and mass-producing 381 chips based on the principle. The company will debut the LogicFolding architecture in flagship Kirin smartphone processors this autumn.

Traditional chipmaking relies on Moore's Law (geometric scaling), which involves shrinking physical transistor sizes. However, as US sanctions blocked China's access to the extreme ultraviolet lithography machines required to implement this approach, HiSilicon has pivoted to a completely different methodology: the Tau scaling law.

Tau Law is a "temporal scaling" framework that prioritizes signal speed, optimizing how fast data moves across a system rather than how small the components are. To execute this theory on a commercial level, Huawei engineered the LogicFolding architecture, a blueprint that physically folds and stacks logic circuits into a dual-layer framework. By drastically shortening internal wiring to eliminate signal delay, the resulting hardware achieves a 55% increase in transistor density and a 41% boost in power efficiency, enabling Huawei to build cutting-edge processors that rival foreign counterparts without Western equipment.

The company’s upcoming Kirin smartphone chips — highly anticipated for the flagship Huawei Mate 90 series — will be the first commercial processors to feature the LogicFolding architecture. The company aims to scale this architecture to its Ascend AI processors and high-capacity data center clusters by 2030. This will provide local alternatives to restricted Nvidia hardware. By 2031, Huawei confidently projects it can design high-end chips with a transistor density equivalent to a 1.4-nanometer (nm) process.

Huawei's announcement comes as China continues its push to end dependence on foreign semiconductor players — amid sanctions and concerns about over-reliance — by aggressively investing in domestic companies and alternative technologies.

Following the announcement, shares for China's largest contract chipmaker, SMIC, surged by 7.6%. The breakthrough is a major symbolic and practical win for Beijing’s push toward complete technological self-sufficiency. While global foundry leader TSMC expects to mass-produce true 1.4nm chips by 2028, Huawei's alternative path means China can dramatically close the performance gap by packaging and structuring chips differently — significantly mitigating the impact of the US clampdown.

Huawei just released a new storage device designed for AI inference and data centers with capacities of 61.44TB and 122.88TB; a 245TB variant is expected to arrive in the future. What made these SSDs interesting, though, was not their massive capacities but the technology behind them. Since the company cannot acquire high-layer-count 3D NAND chips from foreign suppliers needed for high-capacity storage, it instead uses Die-on-Board (DoB) packaging to mount more NAND dies directly on the PCB. Blocks & Files reported that this allowed the company to cram more NAND dies without stacking, thereby increasing density to circumvent BGA/TSOP packaging limits.

Samsung already announced 3D NAND with more than 400 layers, but these chips use American technology that is off-limits to Huawei. The U.S. Department of Commerce added Huawei to its Entity List in 2019, effectively cutting off the company from U.S.-origin technology. Aside from making it difficult, if not impossible, to buy American hardware, software, and IP, it also barred the company from accessing any technology based on or made with U.S. input. So, because the most advanced 3D NAND chips use American technology, even non-U.S. companies making them, like Samsung or SK hynix, cannot sell these chips to Huawei.

YMTC, China’s premier storage chip maker, offers its Xtacking 4.0 3D NAND tech, but it’s limited to 232 layers. This less-dense layout puts Huawei at a disadvantage, as its SSDs would have less capacity than competitors’ offerings that use more advanced 3D NAND. But instead of waiting on its suppliers to catch up, the Chinese tech giant’s researchers used their creativity to build an alternative that skirted Washington’s sanctions through DoB packaging.

DoB ditches traditional NAND packaging and puts the NAND dies directly on the SSD’s PCB. This allows Huawei to increase the capacity of its storage devices while using YMTC’s less dense NAND dies. Aside from that, it’s also more cost-effective than traditional NAND packaging as it eliminates several expensive processes. Still, Huawei had to address several challenges when using DoB, such as thermal management and signal integrity, but it seems to have addressed them with the launch of its OceanDisk 1800.

Even though Huawei has been locked out of American tech for several years now, it continues to thrive and remains one of the biggest tech companies in China and around the world. It has also continued to innovate in response to the limitations that Washington placed on it, sometimes relying on sheer numbers to achieve parity. For example, the AI CloudMatrix cluster could beat the Nvidia GB200 in performance, but it uses 4x the power to do so.

As Beijing continues to block the Nvidia H200 at the border, even expanding the import ban to the RTX 5090D V2, Chinese AI firms have no choice but to buy locally made AI chips like those from Huawei. This, in turn, would funnel a ton of revenue toward Chinese chipmakers, allowing them to invest more in research and development and to decouple from U.S. tech.

Sberbank CEO German Gref said on Wednesday that Russia's largest bank hopes to use Chinese-made processors to run GigaChat, the country's flagship AI model, according to Reuters. Gref made the remarks on Russian state broadcaster Channel One during President Vladimir Putin's two-day visit to Beijing, while sanctions continue to prevent Russia from procuring advanced Western AI hardware.

Gref didn’t specify which Chinese chips Sberbank is interested in, but the most likely candidate is Huawei's Ascend 950 family, which is also a target of intense buying competition among China's own tech giants.

Sberbank’s timing is doubtless problematic for Huawei, which has huge orders to fulfil from ByteDance, Alibaba, and Tencent. ByteDance alone committed $5.6 billion in orders for the Ascend 950PR earlier this year. Huawei is targeting 750,000 units of the 950PR in 2026, but production at SMIC is constrained by weak yields on the foundry’s 7nm-class DUV process and an estimated eight-month cycle time from wafer start to finished processor.

The 950PR sits between Nvidia's H100 and H200 in inference performance and outperforms the restricted H20 by a claimed factor of 2.8 times, though that figure is unverifiable because Hopper-era hardware lacks native FP4 support. Even so, every chip Huawei can produce faces overwhelming domestic demand, so a sanctioned Russian buyer would be competing for allocation against companies that collectively represent the backbone of China's internet economy.

Sberbank launched GigaChat Ultra in March with a new reasoning mode, and the underlying model family has grown through GigaChat 2.0 and GigaChat Max over the past year. Running those models at scale requires both inference and training hardware, and the Ascend 950PR is optimized for the former, specifically the prefill stage of serving LLMs.

Huawei's training-focused counterpart, the 950DT, isn’t expected to ship until Q4 2026 and carries 144 GB of Huawei's proprietary HiZQ 2.0 memory with 4 TB/s bandwidth. Sber's existing infrastructure relies on a combination of stockpiled Western GPUs, Chinese alternatives, and domestic Russian production that hasn’t yet reached competitive capability for frontier AI workloads. If Sberbank wants a fully Chinese-supplied AI compute stack for GigaChat, it’s going to need both chips at volume.

Sberbank acquired a 41.9% stake in Element, Russia's largest electronics producer, in January for 27 billion rubles ($356 million). Element manufactures integrated circuits and semiconductor devices that account for roughly half of Russia's microelectronics output, but its production focuses on defense and industrial applications, not data-center AI accelerators. Russia's most advanced domestic chipmaking targets 65nm lithography by 2030, which is roughly 25 years behind the leading edge.

The Putin-Xi joint declaration signed on Wednesday called for closer bilateral cooperation in AI and backed China's proposal for a global AI governance body. Whether that translates into actual chip allocation for a sanctioned buyer vying for space on Huawei's already oversubscribed order book remains to be seen.

SMIC founder Richard Chang and AMEC chairman and CEO Dr. Gerald Yin appeared together on CCTV's Dialogue program on May 17th to make a coordinated case for Chinese chipmakers to give homegrown equipment more production-line trial time, according to DigiTimes.

The strange joint TV appearance came days after Chinese industry figures told Securities Times that the next three to five years will determine whether domestically built tools can move from functional prototypes to equipment that meets the yield, throughput, and uptime demands of volume manufacturing.

China's semiconductor equipment vendors collectively posted record revenues in 2025, but profitability is under pressure from domestic price competition, and the hardest remaining bottleneck, lithography, has no credible near-term domestic solution. U.S. export controls, meanwhile, continue to tighten.

Record revenues, falling margins

China's equipment industry grew incredibly fast last year. AMEC, the country's leading etch-tool maker, reported full-year revenue of $1.74 billion USD (12.38 billion RMB), up 36.6% year-on-year, with net profit totaling around $310 million (2.11 billion RMB), up 30.6%.

Naura Technology, the broadest-line domestic supplier, posted $3.91 billion (27.14 billion RMB) in revenue across just the first three quarters, while Piotech, which specializes in thin-film deposition, roughly doubled its nine-month revenue to $617 million (4.22 billion RMB). ACM Research, the U.S.-listed cleaning-equipment maker with the bulk of its operations in Shanghai, booked $901.3 million for the full year, up 15.2%.

Despite these lofty revenues, margins moved in the opposite direction: AMEC’s full-year 2025 gross margin fell 1.9 percentage points to 39.2%, with the third quarter alone dropping 5.8%, and ACM Research's gross margin slid from 50.1% in 2024 to 44.4% in 2025. The pattern was consistent across the sector.

This squeeze is coming from domestic competition rather than foreign pressure. With U.S., Japanese, and Dutch export controls restricting shipments of advanced tools to Chinese fabs, domestic vendors are competing fiercely with each other for orders that previously went to Applied Materials, Lam Research, and Tokyo Electron; Needham & Co. analyst Charles Shi recently told Nikkei Asia that this internal price war is the primary driver of margin erosion.

Chinese fabs are now thought to be sourcing roughly 35% of their equipment domestically, up from about 25% a year ago. Beijing's informal target for new fab construction is 50% domestic content, a threshold that YMTC's third Wuhan fab has reportedly already cleared, but the gains are concentrated in mature-node tool categories. Etch localization at mature nodes sits at roughly 50% to 60%, and resist stripping exceeds 80%. According to data from Ijiwei thin-film deposition runs from 20% to 30%, and lithography sits below 5%.

A public appeal

The Chang-Yin CCTV appearance was ultimately a strange, public, state-sanctioned appeal to Chinese fabs. Chang argued that domestic equipment can’t improve without real production-line trials and said fabs should start with small wafer batches of up to 100 wafers before scaling up to limit the risks of early adoption. Meanwhile, Yin said that Chinese customers still default to foreign tools out of habit, and even new systems from the world's largest equipment vendors typically require two to three years of tuning when first deployed at leading fabs.

Industry-standard timelines for qualifying a new etch or deposition tool on a leading-edge production line run 18 to 24 months from installation to qualified production status. The process tests reliability, particle contamination, process drift, and throughput under sustained operation, not just whether the tool can produce a working wafer under controlled conditions.

An example highlighted by Yin is that of AMEC, which, in December 2023, decided to enter the large flat-panel display equipment segment, a category he said was previously 100% imported. The tool in question weighs roughly 150 tonnes and measures 15 by 15 meters, but AMEC reportedly built a working prototype in 12 months, met a customer's next-gen specifications four months later, and shipped the tool to a production line within 18 months total. Needless to say, those claims haven’t been independently verified and shouldn't be taken at face value.

AMEC also claims SMIC has purchased at least 800 of its tools, a figure Chang cited on the same broadcast, and that its etch technology is used in TSMC's supply chain at nodes from 65nm down to 5nm and 3nm. TSMC hasn’t publicly confirmed the scope of AMEC's role in its production lines, however.

Recent disclosures show that SMIC faced yield losses tied to equipment maintenance and validation stalls in 2025, the exact production-line qualification problem Chang acknowledged on CCTV. The foundry has reportedly acquired some foreign tools that are sitting idle because spare parts and field service from sanctioned suppliers are no longer available under normal terms.

Still no lithography solution

None of China's equipment progress addresses the most critical chokepoint: lithography. Shanghai Micro Electronics Equipment (SMEE), the only Chinese supplier of lithography scanners in any volume, produces a 90nm-class ArF system. While a 28nm-class tool has been reported in development, it’s not confirmed in mass production, and details are scarce.

One project to watch, however, is the Shanghai Yuliangsheng immersion DUV scanner under test at SMIC. That tool, linked to Huawei-backed SiCarrier under the codename "Mount Everest," resembles ASML's Twinscan NXT:1950i from 2008, two product generations behind the NXT:2000i used in current 7nm and 5nm production. SMIC is thought to be targeting the Yuliangsheng tool for its 28nm production flow in 2027, but sub-10nm lithography on purely domestic equipment is unlikely before 2030.

In Q3 2025, 42% of ASML's system sales by revenue went to Chinese customers, confirming that Chinese fabs are buying DUV scanners as fast as current export rules allow. But Washington is working to narrow this window further, with the MATCH Act, which was introduced last month. It names and designates the likes of AMEC, Naura, Piotech, ACM Research, SiCarrier, and SMEE, among SMIC, YMTC, Hua Hong, CXMT, and Huawei, as “Covered Facilities” and would impose a country-wide prohibition on exporting DUV immersion lithography tools to China.

The House Foreign Affairs Committee passed the bill 36 to 8 in late April after removing a proposed ban on cryogenic etch tools, which would have affected Lam Research and Tokyo Electron. The DUV immersion ban remains in the bill as it heads toward a Senate floor vote. As of the time of writing, it’s currently sitting in a Senate Committee.

China criticized the legislation less than a week before the duo’s state-sanctioned television address to chipmakers. The broadcast itself is ultimately best viewed as part of Beijing's response: a coordinated message that domestic fabs need to accelerate qualification of Chinese-built alternatives before the remaining supply lines are cut.

The vast majority of leading supercomputers and AI clusters today use CPUs for general-purpose tasks and orchestration and AI GPUs for massive parallel computing workloads to achieve exceptionally high ExaFLOPS-class performance. But in China, we are seeing a different trend, as in recent years the country has deployed a number of CPU-only supercomputers for AI and HPC workloads, largely due to the bans on GPUs from the US preventing the country from sourcing enough for supercomputers. For example, China's National Supercomputing Center recently deployed its 1.54 ExaFLOPS-class machine that uses 20,480 Armv9-based CPUs.

The LineShine LX2 processor

The LineShine supercomputer is based around custom Armv9-based LX2 processors designed specifically for large-scale AI and HPC workloads. China's National Supercomputing Center (NSCC) in Shenzhen does not disclose the developer of the LX2 CPU, though Jon Peddie from Jon Peddie Research outright calls it the 'Huawei LX2' processor. Meanwhile, the CPU could be a custom Huawei HPC CPU, a joint NSCC/Huawei design, or an entirely separate Chinese government-backed HPC processor developer.

Each LX2 processor uses two compute chiplets and has a total of 304 CPU cores organized into eight CPU clusters containing 38 cores each. Every core includes Arm SVE (Scalable Vector Extension) and SME (Scalable Matrix Extension) units that accelerate vector and matrix operations used in AI training and scientific computing that support FP64, FP32, BF16, FP16, and INT8 data formats. Each core is equipped with 32 KB L1 instruction cache and 32 KB L1 data cache, while every cluster shares a 28.5 MB L2 cache.

The processor uses a highly unusual memory subsystem that combines 32 GB of on-package HBM that delivers up to 4 TB/s of bandwidth and up to 256 GB of off-package DDR5 memory. A similar memory subsystem was used by Fujitsu's Arm-based A64FX processor that powers the Fugaku supercomputer, though the LX2 is probably the industry's first Armv9-based CPU for AI and HPC that uses such a memory subsystem.

Each chiplet contains four HBM domains and four DDR domains; there are 16 NUMA domains per processor. HBM access is highly sensitive to locality, whereas DDR memory access is more uniform within a die and is shared between clusters. Such behavior forced developers to design topology-aware memory placement and scheduling techniques (which are particularly handy for AI training), which are executed by a dedicated SDMA engine to move data between DDR and HBM.

When it comes to performance, a single LX2 processor delivers 60.3 TFLOPS FP64 performance, 240 TFLOPS BF16/FP16 throughput, and 960 TOPS INT8 performance. Unlike conventional server CPUs, the architecture appears heavily optimized for dense AI and matrix workloads despite remaining a CPU-centric design. The paper notes that sustaining high utilization of the SME matrix engines required extensive co-design of kernels, runtime scheduling, cache residency management, and tensor placement across the HBM and DDR hierarchy.

The LineShine supercomputer

The LineShine supercomputer comprises 20,480 compute nodes, each node contains two LX2 processors, and each LX2 processor has 304 CPU cores. Therefore, the whole system uses 40,960 LX2 processors packing 2,451,840 CPU cores in total. The supercomputer is interconnected by the LingQi high-speed network (LQLink) with 1.6 Tb/s per node.

The machine delivers 1.54 ExaFLOP/s of BF16 training performance and peaks at 2.16 ExaFLOP/s during training of a 6.3-billion-parameter Earth observation generative compression model. Since companies like xAI do not publish peak performance of their AI clusters that use hundreds of thousands of AI GPUs from Nvidia, we cannot compare the performance of LineShine to that of Colossus or other advanced AI clusters. Yet, theoretical peak performance of xAI's Colossus is believed to be 497.9 ExaFLOPS, so even with a model FLOPS utilization of around 15% (like the LineShine does), it can deliver around 75 ExaFLOPS.

When it comes to theoretical peak FP64 performance, these 40,960 LX2 processors can deliver 2.47 ExaFLOPS, though we have no idea about the actual FP64 throughput of the machine, as it heavily depends on multiple factors.

Loads of advantages, but with a caveat

CPU-only AI and HPC supercomputers offer several advantages over conventional heterogeneous CPU+GPU systems, specifically for complex scientific tasks that combine AI training with massive data ingestion, preprocessing, storage interaction, simulation, and orchestration.

Since everything runs on the same processor and memory space, they avoid many of the complications associated with heterogeneous computing, such as costly and bandwidth-hungry CPU-to-GPU data transfers, complex programming models, GPU memory limitations, and accelerator-specific software stacks.

Furthermore, homogeneous CPU-based systems can expose much larger coherent memory pools by combining HBM with large DDR capacities, which is useful for handling massive scientific datasets, retrieval-augmented generation, and long-context windows.

In addition, they are attractive for AI-for-science applications that involve irregular control flow, distributed I/O, communication-heavy pipelines, and execution patterns that do not map efficiently to GPUs.

Also, CPU-only systems can integrate more naturally with traditional HPC environments and perform regular supercomputer tasks (e.g., simulations), which is particularly useful for those who need both AI training/inference and HPC.

Last but not least, such systems reduce dependence on foreign accelerators and platforms like Nvidia's GPUs and the CUDA software ecosystems, which is important for China.

There is a big tradeoff, though: CPU-only systems are usually less power-efficient and deliver lower dense AI throughput than GPU-based supercomputers, which is why the industry bets on heterogeneous CPU+GPU architectures.

Huawei expects revenue from its AI processors to reach roughly $12 billion in 2026, up from $7.5 billion last year. The projection, based on orders already received from major Chinese technology firms including Alibaba, ByteDance, and Tencent, would represent at least 60% year-over-year growth and position Huawei as the dominant supplier in a domestic AI chip market that Morgan Stanley estimates could reach $67 billion by 2030. The surge has coincided with Nvidia CEO Jensen Huang confirming that Nvidia's share of the Chinese AI accelerator market has collapsed to zero percent.

These numbers describe a market that has bifurcated with unusual speed. Just 18 months ago, Nvidia supplied the vast majority of AI training and inference silicon used by Chinese cloud providers. Today, Huawei's Ascend 950PR is the primary procurement target for China's largest tech companies, and a training-focused successor named the 950DT is scheduled for Q4 this year.

The impact of DeepSeek V4

This raging demand can be largely attributed to the release of DeepSeek’s V4 LLM in April, which has been optimized specifically for Huawei's Ascend architecture and its CANN software framework rather than for Nvidia's CUDA ecosystem. Huawei engineers, per reporting from South China Morning Post, are said to have collaborated directly with DeepSeek ahead of the model’s launch, and the company confirmed that its full Ascend SuperNode product line was adapted for V4 inference on day one. Alibaba Cloud and Tencent Cloud both deployed V4 services within hours of release.

The 950PR is currently the only Chinese-made AI processor that supports FP8, a compressed numerical format that allows more operations per second and lowers per-query costs. V4 uses a Mixture-of-Experts architecture with up to 1 trillion total parameters but activates only around 37 billion per inference pass. That favors inference-efficient hardware, which plays to the 950PR's strengths over its limitations in raw training throughput.

DeepSeek gave Huawei early optimization access, but didn’t extend the same to Nvidia or AMD. While V4's open weights are released in standard formats compatible with CUDA-based frameworks, DeepSeek's own infrastructure runs on Huawei Ascend silicon. The collaboration has pulled forward procurement timelines across the Chinese cloud industry, and chip prices for the 950PR have reportedly risen by about 20% as a result of the demand.

SMIC capacity and production

Huawei's ability to fill those orders depends on SMIC, China's leading foundry. SMIC manufactures the 950PR on its N+3 process, a 7nm-class node built without EUV lithography. Huawei is said to be targeting production of roughly 750,000 950PR units this year, with full-scale shipments expected in the second half following samples that were shipped to customers in January, but that figure is expected to fall short of demand.

Meanwhile, SMIC has been working on expanding its advanced-node capacity for more than a year. The goal is a five-fold increase over a period of two years that’ll lift 7nm and 5nm production to 100,000 wafers per month and half a million by 2030. In addition, the combined capacity for 22nm and below could rise from 30,000-50,000 wafer starts per month in 2025 to 50,000-60,000 or higher this year. Huawei is adding two dedicated fabrication plants, though ownership structures remain unclear. Once fully operational, those facilities could exceed the current output of comparable lines at SMIC.

Yields remain a thorn in China’s side, with SMIC’s 7nm-class process delivering substantially fewer good dies per wafer than TSMC’s equivalent nodes, and the 950PR is likely to be a much larger chip than a TSMC equivalent. SMIC’s cycle time from wafer start to finished and packaged as an Ascend processor is also a problem, currently sitting at around eight months, according to estimates from JP Morgan. For similar nodes at TSMC, it’s around three months.

Then there’s HBM — Huawei announced in September that it had developed its own HBM chips with up to 1.6 TB/s bandwidth, HiBL 1.0, and HiZQ 2.0, in partnership with CXMT, but how quickly CXMT can ramp production of competitive HBM remains an open question.

Nvidia's collapse in China

Huang's admission that “In China, we have now dropped to zero,” came during an interview with the Special Competitive Studies Project's "Memos to the President" podcast. He criticized U.S. export policy as having "already largely backfired," arguing that conceding a market the size of China doesn’t make strategic sense.

The H200, which Nvidia received U.S. licenses to sell to China earlier this year, hasn’t shipped a single unit despite receiving orders. Contradictory regulatory requirements from Washington and Beijing created a stalemate at customs: U.S. regulators require that H200 chips ordered by Chinese customers be used only inside China, while Beijing has instructed domestic technology companies to limit Nvidia hardware to overseas operations.

Nvidia confirmed in its FY2026 10-K filing that it’s "effectively foreclosed from competing in China's data center computing market" and is not assuming any data center compute revenue from the region in its current outlook. Bernstein analysts estimated earlier this year that Nvidia’s share of the China AI GPU market could fall to roughly 8% in the coming years, down from 66% in 2024, both due to U.S. restrictions and because domestic vendors are being pushed to cover up to 80% of demand from domestic sources. TrendForce projected in December that China's high-end AI chip market would grow by more than 60% in 2026, with domestic suppliers capturing about half of the total.

950PR performance

The 950PR performs somewhere in between Nvidia’s H100 and H200, and outperforms the restricted H20 by an estimated factor of 2.8 times, but trails the H200 in both compute and memory bandwidth. That 2.8 figure can’t be verified, however, since Hopper-era hardware doesn’t support FP4 natively.

Huawei compensates by linking large numbers of processors via optical interconnects. Its CloudMatrix 384 system combines twelve racks of Ascend modules into a 384-processor fabric delivering roughly 300 PFLOPS, though at nearly four times the power draw of Nvidia's comparable GB200-based configurations.

The 950PR is primarily an inference chip, though; the training-focused 950DT, expected in Q4, is designed for deep learning workloads and could narrow the gap with Nvidia's Hopper generation for model training tasks. Until it ships, Chinese firms that need to train large foundation models domestically face constraints that inference silicon can’t fully solve.

As for Huawei's CANN software ecosystem, it’s now thought to have more than four million developers, but it remains far smaller than Nvidia's CUDA install base. Whether CANN can attract enough third-party development to become self-sustaining remains to be seen. For now, commercial momentum is running in Huawei's favor inside China, driven by the simple absence of alternatives.

DeepSeek on Friday released a preview of its V4 large language model, the Hangzhou-based startup's most powerful to date, with 1.6 trillion parameters and a 1 million token context window. The model is the first major frontier release optimized for Huawei's Ascend AI processors rather than Nvidia hardware, and it arrived on the same day Reuters reported that the U.S. State Department had sent a diplomatic cable to embassies worldwide instructing staff to warn foreign governments about alleged IP theft by DeepSeek and other Chinese AI firms.

V4 comes in two variants: V4-Pro, the flagship, which costs $3.48 per million output tokens, and V4-Flash, a smaller 284 billion parameter version, which costs $0.28. OpenAI currently charges $30 per million output tokens for GPT-5.4, and Anthropic charges $25 for Claude Opus 4.6. DeepSeek, however, acknowledges V4 “falls marginally short” of those closed-source models by roughly three to six months of development, but outperforms every other open-source competitor in agentic coding and reasoning benchmarks.

DeepSeek trained its earlier V3 model on 2,048 Nvidia H800 GPUs, and the company has faced multiple investigations over whether it acquired restricted Nvidia hardware through intermediaries in Singapore.

V4 sidesteps that supply chain entirely by training on domestic Ascend chips. Huawei confirmed day-zero compatibility across its full Ascend SuperNode product line, including its latest 950 series processors, and DeepSeek said V4-Pro pricing could fall further once Huawei scales up Ascend 950 production in the second half of this year.

The diplomatic cable, per Reuters, instructed embassy staff to speak to their foreign counterparts about “concerns over adversaries’ extraction and distillation” of U.S. models, naming DeepSeek alongside Moonshot AI and MiniMax. Two days earlier, the White House Office of Science and Technology Policy published a memo accusing Chinese entities of running "deliberate, industrial-scale campaigns" to distill American frontier AI systems.

Those accusations build on claims Anthropic made in February, when the company said DeepSeek, Moonshot, and MiniMax had used 24,000 fraudulent accounts to make 16 million exchanges with its Claude model. OpenAI has also accused DeepSeek of distilling its models.

China's foreign ministry called the accusations "groundless," according to Reuters, and DeepSeek has previously said its V3 model relied on naturally occurring data collected through web crawling and didn’t intentionally use synthetic data generated by OpenAI. The diplomatic cable and the V4 launch both come just weeks before President Trump is scheduled to visit Chinese President Xi Jinping in Beijing for a summit expected to cover semiconductor export controls and IP disputes.

China's mission to become entirely self-reliant in the field of artificial intelligence has reached a new milestone. Announced at the Huawei China Partner Conference 2026 in Shenzhen, the company has just unveiled its latest AI accelerator: the Atlas 350. This new NPU is based on an in-house Ascend 950PR chip, representing a significant upgrade over the last-gen Ascend 910-class silicon.

Huawei is marketing the Atlas 350 as a high-efficiency workhorse designed for the prefill stage (inference) of AI deployment. As such, it delivers 1.56 PFLOPS of FP4 throughput, which Huawei claims is 2.87 times higher than Nvidia's China-only H20. That number can't be verified because Hopper-era cards don't support FP4 natively, while the Atlas 350 is the first homegrown Chinese accelerator to be optimized for FP4 precision.

That's already a significant achievement because even Nvidia only recently started to support the format with its Blackwell GPUs. FP4 allows for larger models to be deployed on the same hardware while requiring less memory. Speaking of which, the Atlas 350 comes with 112GB of Huawei's proprietary HBM known as "HiBL 1.0."

Even though the Ascend 950PR otherwise features 128 GB of memory with a 1.6 TB/s bandwidth, current reports for the Atlas 350 say it maxes out at 1.4 TB/s. The memory access granularity has been reduced from 512 bytes to just 128 bytes. It also supports 2 TB/s interconnect bandwidth using the new LingQu protocol, which is 2.5x higher than the previous Ascend 910 series. The Atlas 350 is rated at 600W, 200W more than the H20.

Those specs paint an impressive picture for a homegrown chip, especially one that's made with U.S. sanctions in place. Huawei is not allowed to access TSMC's CoWoS tech that Nvidia uses to stack HBM near the GPU, so the company is leveraging some other advanced packaging. The memory itself is in-house and is supposed to compete with the likes of SK Hynix and Micron, though we don't know who the actual supplier is.

Precise availability wasn't announced — it rarely is with AI accelerators — but Huawei has kept its prior promise of a Q1 2026 release for the Ascend 950PR. BigGo Finance says the NPU is priced at 111,000 Yuan (~$16,000) versus Nvidia's H20 which can range from anywhere between $15,000 to $25,000 in the region. Street pricing doesn't really exist for AI GPUs, so take this particular bit with a grain of salt.

There are a lot more Ascend chips in the pipeline that we've covered in a dedicated article before. Despite the ambition to gain independence from foreign hardware, Chinese companies still source Nvidia GPUs (and not the nerfed ones), which makes sense considering how local silicon is not quite as competitive yet and because the CUDA software stack is so mature. Huawei's latest efforts, therefore, represent a serious step in trying to bridge that gap.

Chinese tech giant Huawei has lined up a magical-looking Wi-Fi 7 router featuring the world’s first "metal mesh crystal antenna" (machine translation) on Japanese crowdfunding site GreenFunding. As well as the glowing crystal mountain at the center of the design, the router boasts a ‘shark fin’ heat exhaust system. It might be the nearest a home tech appliance has yet got to the gadget holy grail of combining sharks and laser beams.

The lighting of the router and the mesh nodes can be configured or automatically change according to the time of day. Touch controls on the devices allow quick visual adjustments. A partner app facilitates greater control.

You will have formed your own idea about the visual appeal of the new Huawei WiFi Mesh X3 Pro. Whatever your opinion of its glowing physical presence, it seems like a bold move for Huawei to promote a piece of tech that is usually hidden away into the limelight. Actually, moving the router out of a hidden corner, into a central ornamental statement piece, will probably be good for the Wi-Fi signal in your home.

Beneath the “sophisticated amber glow,” the 10-inch (250mm) tall WiFi Mesh X3 Pro packs in some attractive technology. For example, it supports technologies such as "MLO", "4K-QAM", and "Multi-RU" to stretch its Wi-Fi 7 capabilities. There are also two 2.5 Gbps Ethernet ports on the main unit. All this is driven by the custom Huawei Gigahome SoC.

To maintain the router’s throughput across its six high-performance antennas, the “Shark Fin Heat Exhaust System” comes into play. Huawei boasts it can prevent any thermal throttling affecting which could adversely affect long hours of online gaming or large data transfers.

Huawei has made a matching mesh node/satellite unit, which is included in some of the crowdfunder bundles. This is a truncated but complementary glowing design, again encouraging the owner not to deploy it in a hidden recess.

Seemingly a Japan exclusive for now, the crowdfunding is going very well – raising 8,600% over target – so perhaps Huawei will see fit to roll out the visually appealing WiFi Mesh X3 Pro in more markets. Then we'll be able to check whether it stands up to comparisons with the best Wi-Fi routers we've tested. Converting the (regular non-early bird) Japanese Yen price to USD would suggest a U.S. price of $170 for the main router alone. Not that bad for what Huawei claims is a piece of “art.”

China's leading chipmakers are working hard to increase the output of chips made using leading-edge process technologies by five times in two years to satisfy the demand of the domestic AI sector, reports Nikkei. This is going to be particularly hard to achieve given that China-based chipmakers do not have access to leading-edge tools from American, Japanese, and European companies.

The country aims to lift production of chips using 7nm- and 5nm-class fabrication technologies from below 20,000 wafer starts per month today to roughly 100,000 within one to two years, according to Nikkei. The longer-term plan includes increasing output of semiconductors produced on leading-edge nodes with an additional 500,000 wafer starts per month by 2030, Nikkei reports, citing sources familiar with the matter.

For now, the only company in China capable of making chips on 7nm-class manufacturing processes is Semiconductor Manufacturing International Corp. (SMIC). SMIC has been gradually expanding its leading-edge manufacturing footprint across Shanghai, Shenzhen, and Beijing fabs for years, according to SemiAnalysis, which models that the company was on track to approach roughly 50,000 wafer starts per month on advanced production nodes in 2025. The ramp has been supported by its ongoing ability to procure wafer fabrication equipment from foreign companies despite sanctions, as well as by the limited impact of export controls and their enforcement.

If the 50,000-wafer starts per month figure is correct, then doubling that number to 100,000 within a couple of years might seem like a realistic plan as long as the company has the right equipment and could put it into production. However, this is not the case. Zhao Haijun, co-CEO of SMIC, recently complained that some tools the company had procured will not be put to use this year as the foundry has troubles procuring other equipment.

"However, due to the impact of external factors, the company has procured some key equipment in advance, while the supporting equipment may not be purchased yet," said Zhao Haijun during a conference call with financial analysts and investors. "This timing difference has brought an even situation that the procured equipment may not be able to form production lines this year."

Although SMIC cannot use some of its (presumably) advanced tools, it expects to continue adding capacity, though not necessarily to its advanced product lines, but rather to those producing chips on trailing nodes.

"Based on the current situation, it is estimated that by the end of this year, the increase in monthly capacity will be around 40,000 12-inch equivalent wafers compared to the end of last year," Zhao Hauijun said.

China's second-largest contract chipmaker, Hua Hong Semiconductor, historically focused on mature nodes, but has now joined the push into advanced logic manufacturing under pressure from central and regional authorities, and is now reportedly ramping its 28nm and 22nm-capable capacities. Huawei has provided technical assistance to support this transition, according to Nikkei.

Beyond these two major foundries, Huawei-linked entities such as PengXinWei and Dongguan Guangmao Technologies are building out pilot lines and development capacity, including efforts targeting nodes more advanced than 10nm.

When it comes to 22nm/28nm nodes and below, UBS estimates that China's existing capabilities are around 30,000 – 50,000 wafer starts per month, which suggests that SMIC's 7nm-capable production lines produce considerably fewer wafers per month than that. At the same time, UBS seems to be optimistic about China's ability to boost its 22nm/28nm and below capacities in the coming years.

"Our industry discussions suggest the combined capacity expansion of multiple 'advanced' fabs could be 50K – 60K wpm or even higher in 2026E from 30K – 50K wpm in 2025," a recent UBS note for clients reads. "Our prior industry discussions suggested China targets to reach 150K -160K wpm advanced note capacity by end-2027."

Montage Technology, a server and data center connectivity specialist, this week made its initial public offering (IPO) on the Hong Kong stock exchange. Following the listing, the company's shares climbed 64% on the first day of trading after a $902 million offering, reports Bloomberg. Montage is not alone in its successful IPO, which underscores continued investor enthusiasm for Chinese semiconductor companies tied to artificial intelligence and data center growth.

A 64% jump in one day

The company priced its shares at HK$106.89 ($13.67)— the upper end of the proposed range — and sold 65.9 million shares in the offering. The stock finished its debut session at HK$175, and the company raised well over $902 million initially planned, which represents one of the strongest first-day performances among Hong Kong listings in the last five years, according to Bloomberg. The pricing in Hong Kong was a discount relative to Montage's Shanghai-listed shares, which had closed at 170.90 yuan ($15.61) on the day before the offering.

Montage's Shanghai-listed shares have more than doubled over the past year, offering the company an approximate valuation of $29 billion. The firm recently reported projected net income of 2.15 billion yuan ($311.105 million) to 2.35 billion yuan ($340.045 million) for 2025, according to Bloomberg. Analysts surveyed by the news agency expect earnings to reach about 3.3 billion yuan ($477.51 million) in 2026, as demand associated with AI and data center expansion continues to grow.

Montage produces a variety of products for server and data center connectivity, including DDR5 memory PMICs and SPDs, PCIe retimers, CXL controllers, clock chips, and many others. The crown jewel in Montage's lineup is its Jintide platform, which sits next to an Intel Xeon CPU and adds Chinese encryption and hardware root of trust (HRoT) support, as well as a proprietary I/O hub to the leading x86 processor. Because Montage is particularly strong in China, Frost & Sullivan believes that the Shanghai-based company held more than one-third of global revenue share in the memory interconnect chip segment in 2024. Keeping in mind China's attempt to become self-sufficient in terms of semiconductor supply, investing in China-based Montage is a safe bet.

A broader picture

Montage is not the only high-tech company from China that seeks capital, gets more than it had planned, and sees its stock rising significantly in just a few days or months, as demand for Chinese AI, data center, and microelectronics-related stocks is high among investors in Hong Kong and Shanghai.

Since roughly late-2024 through early-2026, there has been a noticeable wave of IPO activity among Chinese AI, semiconductor, and AI-adjacent tech companies in Hong Kong. The most notable companies include Biren Technology (+76% gain on debut), GigaDevice Semiconductor (rose 93% since January), Iluvatar CoreX (with modest performance), Minimax Group (rose 196% since January), OmniVision Integrated Circuits Group (which raised $600 million on the day of listing), and Zhipu AI (+13.3% on first day, market capitalization of around $7 billion).

Biren and Iluvatar CoreX produce AI accelerators, and their business is expected to prosper now that the Chinese government does not want to allow AI GPUs from AMD and Nvidia into the country. Still, both companies face strong competition from local vendors like Cambricon (first listed in 2020) and Huawei, which are bigger financially and have stronger software stacks.

Minimax is one of China's rapidly growing startups focused on generative AI models and applications, just like Zhipu AI. Since the U.S. government no longer allows the export of such AI models and AI model weights to China, both companies now lack major competitors on a rapidly growing market.

Investor confidence in Biren, Iluvatar, Minimax, and Zhipu AI has been supported by domestic policy backing aimed at strengthening China's artificial intelligence ecosystem. Meanwhile, the success of GigaDevice and OmniVision stems from different sentiments.

A part of the AI boom without developing AI

GigaDevice produces analog products, controllers, embedded memory, and microcontrollers that are used across the entire microelectronics supply chain, including among devices that use AI. The company had established revenue, profitability, and predictable demand from NOR flash and MCU products prior to IPO, which made its earnings easier to model compared to loss-making AI models or accelerator companies. Furthermore, given China's plan to achieve self-sufficiency in chip production, it has also benefited from domestic substitution trends and lower geopolitical risk, which are set to continue.

OmniVision is a semiconductor company primarily focused on designing CMOS image sensors and related imaging solutions used in automotive cameras, industrial equipment, smartphones, security systems, and increasingly AI-enabled vision applications. As a result, investor interest around OmniVision's IPO was driven less by AI hype itself and more by its positioning as a major supplier to the rapidly expanding machine-vision ecosystem. This ecosystem is about to explode due to autonomous driving, smart surveillance, robotics, and edge AI devices that rely on visual data processing.

Again, unlike AI startups, OmniVision offers established revenue streams, diversified end markets, and proven manufacturing relationships, which reduces AI-associated risks while remaining in the broad AI domain, which certainly made it attractive to investors.

The future of Chinese AI

Montage Technology’s strong IPO performance reflects continued investor enthusiasm for Chinese semiconductor companies linked to AI and data center growth. Meanwhile, as demand for infrastructure supporting AI continues to expand, there are more companies — representing both the AI sector and adjacent sectors like Montage — to conduct successful IPOs in China and raise hundreds of billions of dollars.

Even though Nvidia's AI GPUs and rack-scale solutions remain the most sought-after AI accelerators, curbs set on exports of Nvidia's AI processors to China, first by the White House and then by Beijing, are having a drastic effect on the company's presence in the People's Republic. As a result, the company's share in China could drop to just 8% in the coming years as domestic suppliers can satisfy around 80% of local demand, reports Nikkei, citing analysis from Bernstein.

"The new products meet the needs of domestic developers," said Zhang Jianzhong, chief executive of Moore Threads, at a news conference while announcing the codenamed Huashan product, the company's first GPU dedicated solely for the acceleration of AI workloads. "There will be no more need to wait for advanced products from overseas."

Analysts from Bernstein cited by Chinese media expect Nvidia's share of China’s AI processor market to drop to around 8% this year from 66% in 2024 as Huawei, Cambricon, and other local independent hardware vendors (IHVs) together approaching 80%. The rise of Chinese hardware accelerators is a result of a combination of events, including restrictions set on Nvidia hardware, progress of hardware from companies like Huawei, Cambricon, Moore Threads, and MetaX, as well as substantial improvements in their software stacks.

Moore Threads' Huashan can compete against Nvidia's Hopper H100 and H200 products, the company's previous-generation AI accelerators that the U.S. recently allowed to export to China, but with some serious strings attached. However, they are considerably slower than Nvidia's existing Blackwell B200 and B300 GPUs, which are barred from export to the People's Republic.

Meanwhile, Huawei's AI CloudMatrix 384 can beat both GB200 NVL72 and GB300 NVL72 systems in BF16 FLOPS, a popular format used for AI training, albeit with four times more power consumption. The company's next-generation Atlas 950 SuperCluster, based on 524,288 Ascend 950DT AI accelerators, is projected to offer up to 524 FP8 ExaFLOPS for AI training and up to 1 FP4 ZettaFLOPS for AI inference (MXFP4 to be more specific) sometimes in 2026 – 2027 and 4 ZettaFLOPS by the end of 2028. This is still behind leading Blackwell-based clusters, such as Oracle's OCI Supercluster running 131,072 B200 GPUs and offering peak performance of up to 2.4 FP4 ZettaFLOPS for inference, but it is evident that Chinese developers are rapidly increasing the performance of their AI hardware.

Given the progress, the remaining hurdle is completing the transition from an ecosystem long centered on Nvidia to a fully domestic hardware and software stack, which may not be that easy to achieve, as many existing AI deployments use Nvidia hardware and Nvidia CUDA software stack and porting them to Chinese hardware and software is hard and expensive.

Yet, transition to domestic AI hardware (and domestic hardware in general) is China's long-term national goal. A draft five-year plan reportedly circulated by the Communist Party in October calls for semiconductor self-reliance under a 'new national system' that directs state bodies, private companies, and financial institutions. At the heart of this effort are the so-called 'four little dragons' of Chinese GPUs: Moore Threads, MetaX, Biren Technology, and Suiyuan Technology (Enflame).

Large hyperscalers are also intensifying their custom silicon programs. Baidu's Kunlunxin unit plans to introduce five AI processors by 2030, and Alibaba is also not giving up on its own silicon efforts. Yet, to a large degree, China's AI industry is limited by SMIC's ability to produce chips on its 7nm-class process technologies in sizable quantities. If the company cannot increase its output substantially in the coming years, then either China's AI sector will fall behind America's dramatically, or it will find a way to obtain high-performance GPUs from Nvidia to keep up.

China’s GPU cloud market is consolidating rapidly around a small number of domestic champions, with Baidu and Huawei emerging as the clear leaders, as access to Nvidia’s most advanced accelerators remains restricted.

A recent Frost & Sullivan report places Baidu and Huawei together at more than 70% of China’s "GPU cloud" market — defined specifically as cloud services built on domestically designed AI chips rather than imported GPUs — reflecting a deliberate shift by Chinese Internet and telecom giants to vertically integrate AI hardware, software frameworks, and cloud services, while a parallel wave of AI chip start-ups races to public markets to fund the next stage of domestic silicon development.

This is all unfolding against the backdrop of U.S. export controls that continue to limit China’s access to leading-edge Nvidia and AMD accelerators. Since late 2022, Chinese firms have been forced to plan AI infrastructure growth around constrained supplies of downgraded GPUs or around entirely domestic alternatives. This has led to a GPU cloud market that looks increasingly different from its Western counterparts, with architectural choices and performance trade-offs shaped as much by geopolitics as the engineering itself.

Vertical integration replaces scaling

Baidu and Huawei’s dominance rests on a shared strategy of full-stack control. Rather than acting as neutral cloud providers that source GPUs from global vendors, both companies design their own AI accelerators, optimize their own software frameworks, and deploy those components at scale inside proprietary data centers.

Baidu’s AI cloud is built around its Kunlun accelerator line, now in its third generation. In April 2025, Baidu disclosed that it had brought online a 30,000-chip training cluster powered entirely by Kunlun processors. According to the company, that cluster is capable of training foundation models with hundreds of billions of parameters and simultaneously supporting large numbers of enterprise fine-tuning workloads. By tightly coupling Kunlun hardware with Baidu’s PaddlePaddle framework and its internal scheduling software, Baidu is compensating for the absence of Nvidia’s CUDA ecosystem with vertical optimization.

Huawei has taken a similar but more industrial-scale approach. Its Ascend accelerator family now underpins a growing share of AI compute deployed by state-owned enterprises and government-backed cloud projects. Huawei’s latest large-scale configuration, based on Ascend 910-series chips, emphasizes dense clustering and high-speed interconnects to offset weaker per-chip performance and lower memory bandwidth compared to Nvidia’s H100-class GPUs. Huawei has been explicit about this trade-off internally, framing cluster-level scaling as the primary path forward while advanced process nodes and EUV lithography remain out of reach.

Both companies are also pursuing heterogeneous cluster designs. Chinese cloud providers have increasingly experimented with mixing different generations and vendors of accelerators within a single training or inference pool. This approach reduces dependence on any single chip supply source but raises software complexity, requiring custom orchestration layers to manage uneven performance characteristics. Baidu and Huawei are among the few firms in China with the engineering resources to make such systems viable at production scale, which further entrenches their market position.

Domestic chips close the gap

Domestic accelerators, such as Huawei’s Ascend 910B, Baidu’s Kunlun II, and the third-generation Kunlun P800, have narrowed the theoretical performance gap with Nvidia’s A100 and H100, but efficiency, yields, and memory subsystems continue to lag.

Huawei's Ascend 910B, manufactured at SMIC on an advanced yet yield-constrained process, delivers competitive compute density on paper; however, it has been produced in limited volumes. Huawei’s next-generation Ascend 910C, which uses a multi-die design to boost throughput, improves performance further but at the cost of significantly higher power consumption per rack. In large clusters, this translates into higher operating costs and more complex cooling requirements, which limit where such systems can be economically deployed.

Kunlun II, meanwhile, was broadly comparable to Nvidia’s A100 in certain workloads, while the newer P800 focuses on scalability and cloud integration rather than headline benchmarks. Baidu has been more restrained in its performance claims, instead emphasizing system-level throughput and service availability to enterprise customers.

Fueling the next phase

While Baidu and Huawei consolidate the cloud layer, a growing ecosystem of AI chip designers is moving aggressively into public markets to fund next-gen domestic silicon. Over the past year, Chinese regulators have accelerated approvals for tech IPOs, and AI chip firms have been among the biggest beneficiaries.

Companies such as Moore Threads and MetaX have debuted on domestic exchanges at valuations that imply extraordinary future growth, despite limited current market share and ongoing losses. Investor enthusiasm is being driven by policy alignment, with Beijing having made it clear that semiconductors and AI infrastructure are national priorities, and public markets are being used as a mechanism to channel capital into these sectors at scale.

This influx of funding is already reshaping competition beneath Baidu and Huawei. Several newly listed chipmakers are positioning their products explicitly for cloud deployment, with architectures optimized for large clusters rather than edge devices or consumer graphics. The risk, however, is fragmentation. Without a dominant software platform equivalent to CUDA, many of these startups depend on cloud providers like Baidu and Huawei to provide integration and market access, thereby reinforcing the central role of the GPU cloud leaders, even as it broadens the underlying hardware supply base.

A structurally different AI cloud market

China’s GPU cloud market is evolving into a structurally different system from those in the U.S. and Europe. Instead of competing primarily on access to the latest Nvidia hardware, Chinese providers are competing on integration depth, domestic supply security, and alignment with Beijing’s policy goals.

Tightening control over GPU cloud infrastructure strengthens the bargaining position across the AI value chain for both Baidu and Huawei. They are not just service providers but gatekeepers for domestic AI compute, with influence over which chips, frameworks, and tools gain traction at scale.

In the near term, this model is hardly going to displace Nvidia’s dominance globally. Chinese firms still prefer Nvidia accelerators where they are legally and practically available, and performance-per-watt remains a decisive advantage for U.S.-designed GPUs. But within China, GPU cloud growth will be driven by domestic stacks, even if they are less efficient, because they are controllable.

Huawei used its New Year message to highlight progress across its Ascend AI and Kunpeng CPU ecosystems, pointing to the rollout of Atlas 900 supernodes and rapid growth in domestic developer adoption as "a solid foundation for computing." The message arrives as China continues to accelerate efforts to replace Western hardware in critical AI workloads, and as Huawei positions itself as the closest thing the country has to a vertically integrated AI compute vendor.

Huawei’s message offers a snapshot of a strategy that has been unfolding for several years, shaped by U.S. export controls, constrained access to leading-edge manufacturing, and a domestic market increasingly mandated to adopt local silicon. Under those conditions, Huawei’s Ascend and Kunpeng platforms have evolved into something distinct from their Western counterparts: less focused on single-chip supremacy and more on building large, tightly coupled systems that compensate for weaker nodes with scale, networking, and software control.

Ascend’s architecture and the limits of the node

At the center of Huawei’s AI effort is Ascend, built around its proprietary Da Vinci architecture. The original Ascend 910, introduced in 2019, was manufactured on TSMC’s 7nm process and delivered roughly 256 TFLOPS of FP16 performance at a quoted 350W. That put it in the same broad class as Nvidia’s Volta-era accelerators, though without the same software ecosystem or interconnect maturity.

Sanctions that came in the years following Ascend’s launch significantly changed the playing field, forcing subsequent Ascend generators onto SMIC’s N+1 and N+2 processes, which are roughly comparable to older 7nm-class nodes without EUV. The Ascend 910C, now the backbone of Huawei’s latest clusters, is a dual-die package with two large chiplets combined into a single accelerator card. On paper, Huawei claims up to 780 TFLOPS of BF16 compute, but die area and power efficiency tell a more complicated story.

Huawei suggests the 910C’s combined silicon footprint is around 60% larger than Nvidia’s H100, with lower performance per square millimeter and per watt. In isolation, that would be a losing proposition, but Huawei has leaned hard on interconnects and clustering. The company uses a proprietary high-speed fabric alongside standard PCIe and RoCE networking to bind hundreds or thousands of Ascend accelerators into a single logical training or inference system.

This approach is evident in Huawei’s claims around Atlas 900 and CloudMatrix systems. Rather than competing card-for-card with Nvidia’s H100 or AMD’s MI300X, Huawei emphasizes aggregate throughput. A CloudMatrix 384 system, linking 384 Ascend 910C accelerators, has been positioned as competitive with Nvidia’s large NVLink-based pods on selected workloads, particularly inference. But there’s a trade-off here in terms of physical scale: where Nvidia can deliver multi-exaflop-class FP4 performance in a handful of racks, Huawei requires an order of magnitude more floor space, power delivery, and cooling.

Inference is where Ascend looks strongest, and reports out of China indicate that 910C delivers roughly 60% of H100-class performance on inference tasks, but training remains more challenging.

Scaling out as a design philosophy

As for the Atlas 900 supernode, highlighted in Huawei’s New Year message, it is probably best viewed as a piece of architectural showmanship rather than a product that’s likely to come to the Chinese market any time soon. It reflects Huawei’s belief that AI compute can be industrialized through standardized clusters built from domestically controlled components, even if each component lags the global leading-edge.

This is where Huawei’s background in telecom networking comes into play, though. The company has decades of experience building carrier-grade systems that prioritize reliability, deterministic performance, and large-scale orchestration. Ascend clusters apply that mindset to AI, with the emphasis on predictable scaling behavior and integration with Huawei’s own AI frameworks rather than leading benchmarks.

That also explains why Huawei describes the supernode technology as a "more readily accessible" technology for forming a "solid AI computing backbone." Huawei is not pitching Ascend as a drop-in replacement for CUDA, but an alternative stack, from silicon to interconnect to compiler, that customers adopt wholesale. That’s something that could be attractive to Chinese cloud providers that are facing up to some pretty harsh procurement and compliance realities in the face of export restrictions and geopolitical uncertainty.

Kunpeng and the supporting CPU layer

Ascend does not stand alone. Huawei’s Kunpeng CPUs provide the general-purpose compute layer for these systems, and they follow a similar trajectory. Kunpeng chips are Arm-based, built around Huawei’s Taishan core designs. Earlier generations, such as Kunpeng 920, offered up to 64 Taishan V110 cores and targeted server and cloud workloads with respectable throughput but modest per-core performance.

Meanwhile, recent reporting suggests that the upcoming Kunpeng 930 generation is scaling core counts aggressively, pointing to 120-core designs built from multiple chiplets, while Huawei’s own roadmap references Kunpeng 950 and 960 variants with 192 cores and 384 threads. Per-core performance appears to be roughly in the Zen 3 class, which places Kunpeng behind current Xeon and EPYC parts but potentially competitive in highly parallel, throughput-oriented workloads.

That’s probably good enough for Huawei. Kunpeng’s role is to feed data to accelerators, manage I/O, and run infrastructure software in an environment where power and rack space are already dominated by Ascend clusters. Tight integration matters more than single-thread speed, and Arm gives Huawei architectural independence from x86 licensing and export risk.

Taken together, Ascend and Kunpeng show us how China’s AI hardware strategy has shifted from chasing individual best-in-class chips to assembling viable end-to-end platforms under constraint. Chinese government guidance discouraging new purchases of Nvidia hardware, combined with domestic subsidies and procurement rules, creates a large guaranteed market for "good enough" alternatives.

But "good enough" comes with obvious tradeoffs: Huawei’s clusters consume more power, occupy more space, and rely on heavy overprovisioning to match the throughput of more advanced Western systems. But when push comes to shove, those costs are evidently acceptable in a market where sovereignty and long-term continuity outweigh efficiency.

For much of the past few years, U.S. export controls on advanced AI chips have been justified publicly as a matter of urgency. Policymakers warned that Chinese chipmakers, backed by massive state support and forced into self-reliance, were on the verge of closing the gap with Nvidia in AI hardware. That fear has shaped decisions in Washington, including recent efforts to loosen restrictions on certain Nvidia silicon bound for China.

Now, a new report from the Council on Foreign Relations paints a very different picture. Based on performance data, manufacturing constraints at China’s leading foundry, and realistic production volume estimates, the analysis concludes that Huawei’s AI chip capabilities lag behind Nvidia’s by a wide margin, and that the gap is not narrowing. Indeed, by several measures, it is accelerating.

The report’s findings are especially significant because they directly address U.S. AI policy. If Huawei cannot plausibly catch Nvidia on AI hardware in the medium term, the rationale for export controls weakens. The question is not whether China is investing heavily in AI silicon. It clearly is. The question is whether those investments are translating into competitive hardware at scale. Right now, this report suggests they are not.

Huawei stuck several generations behind

Huawei’s flagship AI accelerators come from its Ascend line, most recently the Ascend 910C. On paper, the 910C is impressive. It is a large, power-hungry accelerator aimed squarely at data center AI training and inference. In practice, however, its performance ceiling is far below Nvidia’s current generation.

The CFR analysis estimates that the Ascend 910C delivers roughly 60% of the inference performance of Nvidia’s H100 under comparable conditions. That comparison already favors Huawei because Nvidia has moved beyond H100. The H200, which entered volume shipments in 2024 and was recently re-cleared for export to China, substantially increases memory capacity and bandwidth, while Nvidia’s Blackwell generation pushes further still.

Process technology is a major part of the problem. Huawei no longer has access to TSMC and must rely on SMIC for fabrication. SMIC’s most advanced production technology is widely understood to be a 7nm class process achieved without EUV lithography. Yield rates are low, and costs are high, and whether SMIC can scale beyond that node remains uncertain.

Nvidia, by contrast, continues to use TSMC’s leading-edge processes and advanced packaging. Its latest accelerators pair large compute dies with massive pools of HBM using CoWoS interposers. That combination is critical for today’s AI workloads, where memory bandwidth and capacity ultimately dictate how the GPUs perform in deployment.

Huawei’s Ascend chips simply cannot match that memory subsystem. Without access to large volumes of HBM and advanced packaging capacity, Ascend accelerators rely on slower memory configurations that bottleneck performance, particularly for LLMs. Even Huawei’s own roadmap highlights the issue, admitting that next year’s Ascend 950PR and 950DT both have lower total processing performance than the Ascend 910C.

According to projections cited in the CFR report, Huawei’s next-gen Ascend chips would at best approach H100-class performance around 2026 or 2027. By then, Nvidia will be multiple product cycles ahead. The report estimates that by 2027, the best U.S. AI chips could be more than 17 times more powerful than Huawei’s top offerings.

Manufacturing scale choke points

Performance gaps in isolation don’t paint a complete picture, though. Dominance in AI is as much about volume as throughput, and on this front, Huawei’s position appears even more untenable.

Nvidia ships AI accelerators by the millions each year, with an annual output of 3.76 million and a 98% revenue share in 2023. These chips are supported by a mature global supply chain that includes advanced memory suppliers, packaging houses, and system integrators.

Meanwhile, Huawei’s production scale is constrained at every step. SMIC’s limited yields cap the number of usable dies, and U.S. export controls on advanced memory further restrict Huawei’s ability to assemble complete accelerators, even when compute dies are available. The CFR analysis, citing figures from SemiAnalysis, estimates that Huawei may be able to produce only a few hundred thousand high-end AI chips annually under optimistic assumptions, with a figure of 200,000 to 300,000 in 2025.

Even if Huawei were to double its output year over year, it would still trail Nvidia’s installed base by a wide margin. When aggregate compute capacity is considered, rather than single-chip performance, Huawei’s position deteriorates further, with the report estimating that Huawei’s total AI compute capacity will amount to only 2% of Nvidia’s through the second half of the decade. “It is virtually impossible for Huawei to close this gap: even a hundredfold increase in AI chip production by 2027 would not even bring Huawei to half of Nvidia’s output,” the report says.

Ultimately, large-scale AI development is driven not by isolated accelerators but by clusters, and Nvidia’s strength lies not only in GPUs but also in its ability to deliver tightly integrated systems with high-speed interconnects and mature software support. Huawei can assemble clusters of Ascend chips, but at a far smaller scale and with lower efficiency. Chinese cloud providers have borne the brunt of this gap, with several having acknowledged that their biggest constraint in deploying large AI models is a lack of access to sufficient hardware. That bottleneck persists despite years of investment and aggressive state support.

Export control fears may be overstated

The CFR report goes against speculation that the recent decision to loosen U.S. export restrictions was driven, in part, by Huawei representing an imminent threat to Nvidia’s dominance in AI hardware.

While Huawei has made some progress under pressures imposed by said export restrictions, particularly in designing workable accelerators without Western fabrication partners, that has its limits. Without EUV lithography, advanced packaging capacity, and unrestricted access to HBM, Huawei’s chips remain fundamentally constrained.

Relaxing export controls in response to fears of Huawei catching up risks is fundamentally misreading the situation. Allowing additional shipments of advanced Nvidia accelerators into China may generate short-term revenue and preserve some market leverage, but it does little to alter the underlying competitive balance between the two companies; Nvidia’s lead is rooted in manufacturing depth and ecosystem maturity, not merely in product availability.

The U.S. and its allies also control key choke points in advanced semiconductor manufacturing. China’s efforts to bypass those choke points have produced some incremental gains, but nothing close to any breakthroughs that would suggest the scales tipping in Huawei’s favor — or any other Chinese firm for that matter.

The CFR’s analysis makes clear that U.S. and allied export controls on advanced chipmaking equipment and high-end AI accelerators continue to constrain China’s ability to produce competitive AI hardware at scale, thereby forcing domestic production onto less advanced nodes and slowing aggregate AI compute capacity growth relative to U.S. producers.

However, none of this implies that China’s AI ambitions should be dismissed entirely. Huawei will continue to improve its designs, and SMIC will continue to push its process technology as far as possible. But improvement is not the same as parity. Based on current trajectories, Huawei is running uphill against a competitor that is leaving it in the dust.

A secret laboratory in China has quietly assembled a prototype extreme ultraviolet (EUV) lithography system and is now testing it stealthily, which means that the country may be close to replicating the most advanced technology that currently exists on Earth, reports Reuters.

The tool was reportedly developed by reverse engineering existing scanners from ASML and is said to be on-track to make prototype chips in 2028. If the information is correct, then Chinese scientists have made numerous breakthroughs across multiple disciplines in just a few years instead of decades, a scenario that appears extremely unlikely. Further analysis of the report indicates that China's laboratory is far from completing the tool, meaning that the country is years away from making chips using EUV lithography.

China's alleged EUV scanner

The system was reportedly completed in early 2025 inside a highly secured facility in Shenzhen and occupies nearly an entire factory floor. The Chinese machine reportedly generates EUV light with a wavelength of 13.5nm using the same laser-produced plasma (LPP) method as ASML Twinscan NXE machines, not the particle accelerator-based steady-state microbunching (SSMB) method designed at Tsinghua University or discharge-produced plasma (DPP) technology developed at Harbin Institute of Technology (HIT), which might prove the point that the system was reverse-engineered or at least contains a substantial amount of technologies pioneered by ASML.

ASML's laser-produced plasma (LPP) method uses tiny molten tin droplets, roughly 25–30 microns in diameter, which are injected into a vacuum chamber at a rate of about 50,000 droplets per second. Then, a high-power CO₂ laser first fires a low-intensity pre-pulse at each droplet, flattening it into a disk-like shape, followed by a more powerful main pulse that vaporizes the flattened tin and creates a superheated plasma with temperatures exceeding 200,000°C. This plasma emits isotropic EUV light, which is then collected by a large multilayer collector mirror and directed into the lithography system's reflective optics for patterning silicon wafers. This process repeats tens of thousands of times per second.

The machine is reportedly larger than the original, but it is operational in the sense that it can generate EUV radiation. However, it has not progressed to make usable chips as it still struggles to replicate 'the precision optical systems' features by Twinscan NXE systems. Furthermore, there is no word about power of the EUV light source, a crucial parameter that defines whether a tool can or cannot be used for volume production.

Not operational, for now

The report clearly states that the Chinese EUV scanner cannot currently be used to make chips, but the Chinese government reportedly wants the first chip prototypes to emerge in 2028, two or three years down the road. However, a more realistic target is 2030, four or five years from now, which is a long time. Meanwhile, from the report, it is not completely clear what stage the Chinese team is at today.

The report does not disclose which specific components of the optical system are the primary bottlenecks, as the article groups them rather generally. In particular, it is uncertain if the alleged EUV tool struggles to replicate the ultra-precise collector mirror system coated with multilayer molybdenum-silicon (Mo/Si) stacks, illuminator optics (which shapes and uniforms the beam using faceted mirrors), or projection optics (a series of aspheric mirrors for 4X – 8X reduction imaging with sub-nanometer wavefront errors). ASML outsources the development and production of these components to Carl Zeiss from Germany. If the developers failed to replicate the collector itself, then the rest of the machine can hardly be called an EUV lithography system, as technically, the only thing they have is some kind of light source that they have yet to learn how to use. Yet, even if the developers cannot replicate illuminator optics or projection optics (suggesting that the collector itself is there), it still means they do not have even a poorly working EUV lithography tool, but rather a set of certain components.

When talking about advanced lithography equipment, we must keep in mind that such tools rely on seamless integration of sophisticated light sources, advanced optics, ultra-precise mechanical engineering, complex control software, and specialized materials, all of which must function reliably within nanometer-scale tolerances demanded by modern chip manufacturing. The story has no word about the state of the mechanical systems of the alleged tool: we know nothing about the wafer stocker system, wafer stages, or reticle stages, all of which are crucial for operation and yields.

To put China's EUV efforts into perspective, the secret lab is not even close to building an alpha tool. For now, what the Chinese lab has cannot even put the light on a wafer, save for printing lines and spaces, something ASML's tool could do in 2006, about 11 years before the company shipped its first Twinscan NXE:3400B system meant for high-volume manufacturing. Of course, reverse engineering certain components can give Chinese engineers a speed boost, but it remains to be seen how significant this one is going to be.

Reverse engineering an ASML Twinscan NXE?

According to Reuters's sources familiar with the effort, the Chinese EUV tool was 'developed' by a team that includes former engineers from ASML and recent university graduates, who allegedly reverse-engineered the company's EUV machines. The secret lab was so stealthy that its employees were given fake IDs to avoid detection of their concentration in one place by foreign spies.

Yet, it is unclear how any engineers from China could reverse engineer an EUV lithography scanner, as the Dutch company has never supplied one to China and hardly taught personnel from China how to service its EUV systems that are not allowed to be shipped to the People's Republic.

Reverse engineering a machine that contains over 100,000 parts is a hard task that takes hundreds of engineers with knowledge of the matter, which is why the secret entity led by the Government of China hired not only former engineers from ASML China, but also former employees of the Dutch company from elsewhere, presumably from Europe, Taiwan, and the U.S. For example, Lin Nan, formerly responsible for EUV light source technology at ASML, now leads a team at the Chinese Academy of Sciences’ Shanghai Institute of Optics that has filed eight EUV-related patents in just 18 months. Yet, this may mean that he uses his experience and knowledge rather than trying to replicate what he did at ASML or reverse engineer what he did at ASML due to the absence of an EUV scanner in his lab.

“It makes sense that companies would want to replicate our technology, but doing so is no small feat,” a statement by ASML published by Reuters reads.

The report says that around 100 recent university graduates are tasked with reverse-engineering parts from EUV and DUV lithography tools, with each workplace monitored by a dedicated camera that records the disassembly and reassembly process, an important part of the whole China's lithography program, according to the report. Employees who successfully put components back together receive bonuses. Yet again, a Twinscan NXE tool is a mechanism consisting of over 100,000 parts working together, not just a sum of all parts.

To sum up, China has reportedly built a secret prototype EUV lithography system and begun testing it, which suggests that the country may be closer to reproducing the most advanced chipmaking technology in existence than previously believed. However, details provided by the report indicate that China is still years — if not a decade — away from making chips using EUV lithography.

The machine can generate 13.5-nm EUV light using the same laser-produced plasma (LPP) method employed by ASML, which may demonstrate extensive reverse engineering of Western technology rather than the use of alternative domestic approaches. However, the tool is significantly larger than commercial systems available today, it cannot produce usable chips, and appears to struggle with other elements of EUV lithography, particularly ultra-precise optics supplied to ASML by Carl Zeiss. In fact, details about the system like light source power, optical subsystem maturity, and the state of critical mechanical components remain unclear.

While China expects first prototype EUV chips to emerge in 2028, Reuters's sources suggest 2030 is more realistic. Yet, the whole effort relies heavily on recruiting former ASML engineers and reverse engineering parts from existing EUV and DUV tools, which are not only hard to develop, but are extremely hard to make. Meanwhile, there is no word whether the current team responsible for disassembling and reassembling components can actually make an ultra-complex machine consisting of over 100,000 parts work flawlessly to produce semiconductors in high volumes.

China is considering an additional $70 billion in investment for its domestic chip industry, as reported by Bloomberg. This would be on top of existing government investment initiatives like the Big Fund III from earlier this year, and could accelerate chip fabrication design and development to help it compete with the likes of Nvidia, even as the Trump administrative re-approves sale of H200 GPUs in the region.

Over the past year, China has announced a number of major projects and initiatives in an attempt to bolster its own domestic chip supply, reduce reliance on mercurial U.S. supplies, and fix its share of the global chip shortage. Some of these have encouraged domestic chip production, while others were designed to discourage the use of hardware from international sources. Smuggling efforts are still rampant, however, and with Chinese chip designs several years and generations behind the best Nvidia and AMD have to offer, China still has a long way to go before it can replace these external sources.

An investment of this size would help close the gap, though. The figures and exact companies to receive the funds (and in what fashion) are reportedly still being worked on, but the numbers being thrown around are extremely large, regardless. The low end is said to be $28 billion, but it could be as large as $70 billion, which exceeds the amount of direct industry investment the Biden administration instigated with the US CHIPS Act. Indeed, if enacted in its entirety, such an investment would be the largest governmental expenditure on semiconductor manufacturing anywhere in the world.

This tracks with Chinese President Xi Jinping's approach to domestic chip manufacturing. He reportedly called for a "whole-nation" approach to bolstering it, seeing it as both a strategic imperative for defence, and to break the economic stranglehold the US has on cutting-edge silicon manufacturing.

China has previously offered energy subsidies to companies using domestic silicon and mandated that Chinese companies utilize at least 50% domestically produced chips in their data centers. That's only for running AI using inference workloads, though. When it tried to force DeepSeek to use Huawei chips for training, they swiftly went back to Nvidia. The performance, effectiveness, and efficiency just weren't there.

There have been rapid advances made in China's chip technology, with some firms claiming to have used advanced assembly and packaging technologies to enhance the performance of older process nodes. That has yet to be proven, and there are still concerns over heat output and manufacturing yield, but China is pulling out all the stops to become independent for future semiconductor manufacturing. This latest investment vehicle plan is just the latest example.

China has begun to assemble a list of government-approved AI hardware suppliers that is designed to encourage public sector organizations to prioritize locally developed artificial intelligence processors, reports the Financial Times. At present, the list only includes Cambricon and Huawei, but does not list any foreign companies, such as AMD or Nvidia, perhaps highlighting China's government attitude towards President Trump's plans to let Nvidia sell its H200 processors to customers in China.

The new list, which will be distributed to ministries, state-owned companies, and public institutions, expands the Information Technology Innovation List (Xinchuang) to include domestic AI processors alongside previously added categories such as local x86-replacement CPUs and homegrown operating systems that replace Microsoft Windows. This list effectively outlines which hardware and software platforms government bodies may purchase, which, to a large degree, defines where billions of dollars per annum are spent by Chinese government-controlled entities.

The Ministry of Industry and Information Technology did not comment on the updated procurement rules, FT reports, but the policy direction seems clear: China intends to accelerate displacement of U.S.-designed AI accelerators with homegrown alternatives within the state sector.

For China, developing its AI prowess and semiconductor self-sufficiency at the same time creates a dilemma. On the one hand, Nvidia's hardware offers higher performance and a better software stack, which greatly helps Chinese companies train larger AI models. Furthermore, many public-sector workloads remain tightly integrated with Nvidia's CUDA ecosystem, which complicates migration to alternative architectures, such as those designed by Cambricon or Huawei. On the other hand, using domestic hardware and software for building homegrown AI ecosystem enables Chinese companies to set up their own AI standards and eventually develop more competitive AI accelerators.

Commercial companies such as Alibaba and Tencent use Nvidia's hardware to maintain their competitiveness — for them, building their AI ecosystem is more important than China's semiconductor self-sufficiency. While the Chinese government may ban American AI accelerators (like it did with Nvidia's H20), these companies can still use them in the cloud, avoiding U.S. sanctions and sustaining their dependance on American technology.

To make it more appealing for China's cloud giants to use domestic hardware not only for inference, but also for training, China has expanded energy subsidies for these companies. Operators of large-scale data centers can now receive a 50% discount on electricity when deploying Chinese-made AI accelerators. This measure is designed to compensate the lower power efficiency of Chinese AI processors relative to Nvidia's AI GPUs while preserving performance they need to train larger AI models and then execute them.

Perhaps the biggest question is not whether Chinese public and private companies are willing to replace a significant portion of AI hardware developed in America with domestic solutions, but rather whether the Chinese industry can actually produce enough AI processors to satisfy the potential demands of the domestic AI sector.

At present, the only company in China that can make chips that can compete against those fabbed by TSMC is SMIC. SMIC's capacity is utilized by 95.8% and it cannot increase its output significantly, as, thanks to sanctions imposed by the U.S. and Dutch governments, it cannot buy advanced fab tools. It is expected that eventually Huawei will also build its own fab that will rely primarily on domestic equipment, so the country's output of advanced chips will increase, though it is completely unclear when this fab is set to come online.

The U.S. can now export Nvidia's H200 AI accelerator to China, with a 25% fee attached. However, following the authorization of the chips, a new report suggests that the decision was made to ensure American tech dominance globally. Reportedly, a major part of the decision is Huawei's recent advancements with its CloudMatrix 384 and Ascend 910C systems, which are on par with both the H200 and Nvidia's GB200 NVL72, a new Bloomberg report suggests.

This decision would enable China to continue to access Nvidia's CUDA-based AI accelerators, as many AI systems still rely on that particular software stack. While China is attempting to standardize an instruction set of its own, the open-source CANN, it has been noted that Nvidia chips are preferable for companies such as Deepseek for training advanced AI models.

According to sources speaking to Bloomberg, multiple scenarios were considered, including flooding the market to "overwhelm" Huawei, to exporting no AI accelerators, which would mark a dramatic shift, if the previously-approved Nvidia H20 (a cut-down H200) were to be affected. Ultimately, the decision rests somewhere in the middle.

China won't get access to Nvidia's latest Blackwell architectures, but it will retain access to the full-fat H200. The White House likely hopes that this move keeps the latest Nvidia chips, while also keeping the country locked into Nvidia's carefully crafted CUDA-shaped moat. "The Trump administration is committed to ensuring the dominance of the American tech stack - without compromising on national security", said White House spokesman Kush Desai, in a statement to Bloomberg.

White House officials are reported to have reviewed the performance of Huawei's AI accelerator ecosystem, in particular, the CloudMatrix 384 system, which utilizes 384 Ascend 910C chips. The CloudMatrix 384 is positioned directly against Nvidia's (export-controlled) GB200 platform, but with obvious tradeoffs in performance and efficiency.

While Bloomberg notes recent rumblings that Huawei is preparing to up its 910C chip production to 600,000 units next year, the report claims U.S. officials concluded "that Huawei would be capable in 2026 of producing a few million of its Ascend 910C accelerators," according to the insider.

The AI race is now bound by pure performance, and the Trump Administration clearly hopes that retaining its architectural advantage by restricting Blackwell will keep Western frontier AI models at the forefront of the industry.

Just last week, Nvidia CEO Jensen Huang commented that he would be uncertain whether or not Chinese companies would even end up purchasing the H200. Huang has long since been a vocal detractor against export controls of AI GPUs, as Nvidia wrote off $5.5 billion in AI chips in April 2025. Whether or not the availability of H200 systems on the Chinese market will be enough to recover the shortfall remains to be seen.

In addition to announcing its first AI cluster with 1 FP4 ZettaFLOPS performance, Huawei also revealed a detailed roadmap of its upcoming Ascend neural processing units (NPUs) that accelerate AI workloads at the Huawei Connect 2025 event.

The company does not have access to TSMC’s leading-edge process technologies or high-end HBM4 and GDDR7 memory from global leaders. So to boost the performance of its Ascend processors, it will need to rely on a new architecture and new types of memory, kicking off with the Ascend 950-series and onwards. Huawei expects its new NPUs to enable multi-ZettaFLOPS performance toward the end of the decade.

When it comes to features, Huawei’s Ascend 910-series AI accelerators have barely changed in years: The latest dual-chiplet Ascend 910C offers higher performance and optimized manufacturability compared to the original Ascend 910 from 2019. The unit uses a SIMD architecture and supports conventional formats, such as FP32, HF32, FP16, BF16, and INT8, which are good enough for AI training, but are ‘heavy’ for AI inference by modern standards.

The new Ascend 910C delivers up to 800 TFLOPS of FP16 performance (around the same as an Nvidia H100), carries 128 GB of HBM, and features 3.2 TB/s of memory bandwidth. While the performance of the Ascend 910C would be competitive in 2023, by modern standards, it's significantly behind Nvidia’s Blackwell-based GPUs. That said, Huawei needs both new architecture and new processors.

So, the company is cooking up a lineup of NPUs — the Ascend 950PR and 950DT, Ascend 960, and Ascend 970 — which use an all-new instruction set architecture and support modern data formats required for next-generation AI workloads. The new AI accelerators will also use Huawei's proprietary HBM-like memory technologies: the cheaper HIBL 1.0 and higher-performance HiZQ 2.0.

The Ascend 950

The next major step in the Huawei Ascend roadmap is the Ascend 950 series, comprising two variants: the Ascend 950PR, optimized for prefill and recommendation stages, and the Ascend 950DT, optimized for decoding and training.

Both Ascend 950-series products use the same silicon, based on the company's new SIMD+SIMT architecture that weds vector-based processing and thread-level parallelism to maximize performance. They feature a GPU-like memory subsystem with reduced DRAM access granularity from 512 to 128 bytes. This reduces wasted bandwidth and improves memory efficiency. All Ascend 950-series processors will add support for FP8, MXFP8, HiF8, and MXFP4 data formats (on top of what is already offered by the Ascend 910C) to offer the right balance of performance and precision.

Both processors also have the same 1 FP8 PFLOP and 2 FP4 PFLOPS of compute performance and interconnect bandwidth (2 TB/s). The only differences between the Ascend 950PR and the Ascend 950DT are their memory subsystems and launch timeframes.

The 950PR features 128 GB of Huawei's proprietary HiBL 1.0 with a bandwidth of 1.6 TB/s, which is a low-cost HBM-like solution optimized for compute-intensive, memory-light tasks like recommendations and prefill. The processor will be available in Q1 2026.

The Ascend 950DT for training and decoding workloads will come with 144 TB of HiZQ 2.0 memory, which offers a claimed bandwidth of 4.0 TB/s. The unit is expected to arrive in Q4 2026.

All AI processors from Huawei, starting from Ascend 950, will rely on the company's UnifiedBus (UB) interconnect protocol. UnifiedBus claims to offer 2.1 microsecond latency, 100 times improved optical reliability, and TB/s-scale bandwidth — critical for binding thousands of NPUs into a single logical system. Huawei supports UB deployment over standard Ethernet via UBoE (UnifiedBus over Ethernet), which reduces hardware costs and improves MTBF (Mean Time Between Failures), relative to RoCE (Remote Direct Memory Access over Converged Ethernet)-based solutions.

Huawei will use its Ascend 950-series AI accelerators for its Atlas 950 SuperPoD and Atlas 950 SuperCluster systems for large-scale AI infrastructure, as well as for other AI workloads (including AI workstations for developers).

The Ascend 960

The Ascend 960 NPU will succeed the Ascend 950 NPU sometime in Q4 2027, according to Huawei's roadmap presented at the symposium. The new unit will add support for HiF4, a Huawei-developed 4-bit format for AI inference, and is said to double performance, memory capacity, and memory bandwidth compared to its predecessor.

The AI accelerator is projected to deliver 2 FP8 PFLOPS and 4 FP4 PFLOPS of performance, featuring 288 GB of memory with 9.6 TB/s bandwidth.

While doubling may imply the usage of two Ascend 950 chiplets, this is not the case. The new Ascend 960 processor supports a new data format, and its interconnect bandwidth is limited to 2 TB/s, far from the expectations of the predecessor.

While it is reasonable to assume that Huawei will continue to use its HiZQ memory with the Ascend 960, the company did not explicitly confirm this during the presentation.

A million of the Ascend 960 processors will form the compute backbone of the Atlas 960 SuperCluster, which is projected to offer 2 FP4 ZettaFLOPS of performance for AI inference.

The Ascend 970

Huawei plans to release the Ascend 970, which will again double the performance of its predecessor, targeting 4 FP8 PFLOPS and 8 FP4 PFLOPS. The NPU will still come with 288 GB of memory, albeit with a 14.4 TB/s bandwidth. While detailed specifications of the Ascend 970 are still in development, the chip is designed to support models scaling to 10 trillion parameters and beyond, and is expected to land as early as late 2028.

Huawei may announce another set of Atlas SuperPods and Atlas SuperClusters, built around its Ascend 970 NPUs. However, the company did not disclose such devices, perhaps because its next-next-generation platform's scale-up world size and scale-out world size are a work in progress, possibly because they can only rely on Huawei's proprietary UBoE (UnifiedBus over Ethernet) protocol, rather than on industry-standard RoCE, which is still an option for the Atlas 960 SuperCluster.

Massive scale of AI systems

Before we proceed with analyzing Huawei's upcoming zettascale platform discussion, let us once again remind you that this multinational giant is blacklisted by the U.S. and does not have access to the advanced manufacturing capacities of Intel Foundry, Samsung Foundry, or TSMC.

While the company could come into possession of such chips through other murky means, Huawei no longer deems this a proper long-term strategy. While this was not disclosed specifically, the announcement of clusters featuring 0.5 – 1 million AI accelerators points to a major change of strategy, from scaling chips in accordance with the cadence of Moore's Law, to scaling up/scaling out of systems. As a result, we are going to see completely different performance scaling challenges, both in terms of hardware and software, from Huawei and Nvidia in the coming years.

Huawei's scale-up world size refers to the number of AI chips that can be integrated into a single compute domain. The Atlas 950 SuperPod packs up to 8,192 Ascend 950DT NPUs. Meanwhile, the Atlas 960 SuperPod will scale to 15,488 NPUs, all connected via Huawei's proprietary UnifiedBus (UB) interconnect with 2.1 µs latency and up to 2 TB/s chip-to-chip bandwidth or RoCE, using industry-standard components, but with lower performance.

These SuperPods are meant to function as one logical system, optimized for large-model training and inference, with synchronized compute, unified memory access, and token throughput scaling beyond 80 million tokens per second. At this point, we can only wonder whether this will indeed work as planned.

To contrast, Nvidia currently limits its scale-up world size to 72 GPU packages per NVL72 GB200/GB300 racks, all connected with NVLink 5.0 and NVSwitch within a single rack. For future systems like NVL144 or NVL576 (Blackwell and Blackwell Ultra), Nvidia also maintains a modular pod-based structure, with no extension of NVLink domains beyond one rack. Interestingly, the number of logical GPU packages remains unchanged at 72.

In terms of scale-out world size, Huawei connects dozens of SuperPods into a SuperCluster using UnifiedBus over Ethernet (UBoE) or RoCE, enabling deployments like the Atlas 950 SuperCluster with 524,288 NPUs, and the upcoming Atlas 960 SuperCluster with over 1 million NPUs. These clusters aim to operate cohesively, with improved fault tolerance, low inter-pod latency, and the ability to train multi-trillion-parameter models when interconnected using UBoE, according to Huawei.

Nvidia's design offers flexibility, modularity, and ease of integration, but lacks Huawei’s end-to-end coherence and latency control at extreme scale, potentially limiting performance scaling for systems with hundreds of thousands or millions of GPUs. Then again, Nvidia and its clients may not need clusters with over a million compute GPUs (we are talking about GPU packages rather than GPU chiplets) for AI, given the fact that Nvidia’s GPUs that Huawei’s NPUs will compete against in 2027 – 2028 will be inherently more powerful.

Software implications

Without any doubt, orchestrating hundreds of thousands of AI accelerators is an incredible engineering achievement. But scaling out hundreds of thousands of NPUs is not only complicated from a hardware development point of view, but it also complicates software development.

Nvidia's clusters are generally easier to program for because they require fewer accelerators to reach a target performance level, thanks to the high compute density of each GPU, like an NVL72 pod, which integrates 72 Blackwell GPUs connected via NVLink 5.0 and NVSwitch.

These pods operate as single, tightly coupled domains with shared memory coherence, reducing the need for complex distributed parallelism. Many large-scale AI workloads, including multi-trillion-parameter model training, can run effectively on just a few NVL72 pods, enabling developers to work within stable, local system boundaries.

Nvidia's modular scale-out model — NVL72/NVL144 (Rubin)/NVL576 (Rubin Ultra) → into a cluster, makes distribution more manageable.

Software stacks like NCCL, Megatron-LM, TensorRT-LLM, and DeepSpeed can assume consistent interconnect topologies and latency domains, with limited cross-pod communication. Taking into account Nvidia's vertically integrated and mature CUDA ecosystem, developers benefit from unified tooling, extensive documentation, and robust abstractions, making it possible to scale AI workloads with minimal custom engineering.

Huawei, by contrast, aims for scale through very large monolithic systems, such as the Atlas 950 SuperPod (8,192 NPUs) and Atlas 960 SuperPod (15,488 NPUs), which function as single logical compute domains. These SuperPods use Huawei’s UnifiedBus (UB) interconnect with 2.1 µs latency and up to 2 TB/s of tight chip-to-chip bandwidth to several thousand NPUs.

Token throughput is projected to exceed 80 million tokens/s (for Atlas 960 SuperPods), and memory access is synchronized across the entire system. This architecture supports tightly coupled training and inference at a massive scale, but also introduces far greater complexity in synchronization, memory partitioning, and job orchestration within each node.

In the scale-out model, Huawei connects multiple SuperPods via UBoE (UnifiedBus over Ethernet) or RoCE to build SuperClusters with 524,288 NPUs (Atlas 950) or over 1 million NPUs (Atlas 960). This large-scale interconnection requires developers to write software that performs well across tens or hundreds of thousands of accelerators, even for workloads that Nvidia can handle within a few pods.

While Huawei's vertical integration and proprietary toolchain (e.g., MindSpore) offer optimization opportunities, the lack of software maturity (according to Chinese companies, which still prefer to use Nvidia hardware despite issues with availability) and the massive scale involved make distributed scheduling, failure handling, and workload decomposition significantly harder, especially for tight synchrony requirements in multi-trillion-parameter models.

The future of Huawei's AI scale-up

At Huawei Connect 2025, the company revealed its shift to system-level scaling via massive AI clusters in a bid to stay competitive in the rapidly developing AI industry. Huawei is unable to access advanced foundry nodes or HBM4 memory. But, it introduced a quite impressive Ascend NPU roadmap that includes the 950PR, 950DT, 960, and 970, all based on a new SIMD+SIMT architecture, featuring support for modern low-precision formats (FP8, MXFP4, HiF8, HiF4), and using proprietary memory like HiBL 1.0 and HiZQ 2.0.

Starting with the Ascend 950 series (1 PFLOPS FP8), Huawei’s SuperPods will scale up to 15,488 NPUs per SuperPod system and over half a million NPUs per SuperCluster. Such massive clusters enable Huawei to achieve multi-ZettaFLOPS performance levels comparable to those of clusters used by market leaders like Google, Meta, OpenAI, and xAI.

However, Huawei's large, monolithic clusters present major software scaling challenges, unlike Nvidia’s modular NVL72/NVL144/NVL576 systems, which are easier to program due to consistent pod sizes, mature tooling, and fewer nodes needed to reach the same performance targets.

Wei Shaojun, vice chairman of the China Semiconductor Industry Association and professor at Tsinghua University, said at an industry event that AI accelerators consisting of 14nm logic chiplets and 18nm-based DRAMs developed in China could rival Nvidia's Blackwell processors that are made using a custom 4nm-class process technology at TSMC, reports DigiTimes.

Speaking at the ICC Global CEO Summit, Wei Shaojun indicated that the key to performance efficiency breakthrough would be advanced 3D stacking used to build Chinese accelerators.

Wei Shaojun — who previously said that goals set by China in the 'Made in China 2025' program were unachievable and who later called on the country to cease using foreign AI accelerators like Nvidia H20 and use domestic solutions instead — described a hypothetical 'fully controllable domestic solution' that would combine 14nm logic with 18nm DRAM using 3D hybrid bonding. There is no evidence that such a solution exists or could be built using technologies that are available in China, so the speech is strictly hypothetical.

According to Wei, this hypothetical configuration is intended to approach the performance of Nvidia's '4nm GPUs' despite using outdated technologies. He believes that such a solution could offer performance of 120 TFLOPS, without revealing specific precision. Furthermore, he claims that it would consume only about 60W of power, thus offering higher performance efficiency (2 TFLOPS per Watt) compared to Intel's Xeon CPUs, according to Wei. To put the number into context: Nvidia's B200 processor delivers 10,000 NVFP4 TFLOPS at 1200W, thus delivering 8.33 NVFP4 TFLOPS per Watt. B300 delivers 10.7 NVFP4 TFLOPS per Watt, which is five times higher than what the non-existent AI accelerator could offer.

The key technologies that are meant to significantly improve the performance efficiency of a hypothetical AI accelerator developed in China are 3D hybrid bonding (copper-to-copper and oxide bonding), which replaces solder bumps with direct copper interconnects at sub-10 µm pitches, as well as near-memory computing. Hybrid bonding with sub-10 µm pitches can enable tens to hundreds of thousands of vertical connections per mm^2, alongside micrometer-scale signal paths for high-bandwidth low-latency interconnects.

One of the best examples of 3D hybrid bonding design is AMD's 3D V-Cache, which delivers 2.5 TB/s of bandwidth at 0.05 pJ/bit I/O energy, so Wei is likely looking toward a similar figure for his hypothetical design. 2.5 TB/s per device is considerably higher than what HBM3E can deliver, so it could be a breakthrough for AI accelerators that rely on the near-memory computing concept. Wei also said that the concept could theoretically scale toward ZetaFLOPS-level performance, though he did not outline when and how such levels could be reached.

Wei identified Nvidia's CUDA platform as a key risk not only for the hypothetical alternative he described, but also for non-Nvidia hardware platforms, as once software, models, and hardware converge on a single proprietary platform, alternative processors become difficult to deploy. Keeping in mind that he envisioned near-memory computing as a way to significantly increase the competitiveness of AI hardware being developed in China, any alternative platform that does not rely on this concept (including Chinese AI accelerators like Huawei's Ascend series or Biren's GPUs) may be considered a problem.

Huawei has introduced Flex:ai, an open-source orchestration tool designed to raise the utilization rate of AI chips in large-scale compute clusters. Announced on Friday, November 21, the platform builds on Kubernetes and will be released through Huawei’s ModelEngine developer community. It arrives amid continued U.S.export restrictions on high-end GPU hardware and reflects a growing shift inside China toward software-side efficiency gains as a stopgap for constrained silicon supply.

Aside from being equipped to help China “...create an analogue AI chip 1000 times faster than Nvidia’s chips,” Huawei claims Flex:ai can raise average utilization by around 30%. It reportedly does this by slicing individual GPU or NPU cards into multiple virtual compute instances and orchestrating workloads across heterogeneous hardware types.

Smaller tasks that might otherwise underuse a full accelerator are stacked alongside one another, while larger models that exceed the capacity of a single device can span multiple cards. The tool includes a smart scheduler, dubbed Hi Scheduler, that redistributes idle resources across nodes in real time, automatically reassigning compute to wherever AI workloads are queued.

Flex:ai’s architecture builds on existing open-source Kubernetes foundations but extends them in ways that are still uncommon across open deployments. Kubernetes already supports device plugins to expose accelerators and schedulers, such as Volcano, or frameworks like Ray can perform fractional allocation and gang scheduling. Flex:ai appears to unify them at a higher layer while integrating support for Ascend NPUs alongside standard GPU hardware.

The launch resembles functionality offered by Run:ai, an orchestration platform acquired by Nvidia in 2024, which enables multi-tenant scheduling and workload pre-emption across large GPU clusters. Huawei’s version, at least on paper, makes similar claims but does so with a focus on open-source deployment and cross-accelerator compatibility. That may give it broader relevance in clusters built around Chinese silicon, particularly those using Ascend chips.

The open-source code has not yet been released, and Huawei has not published documentation or benchmarks. When it does become available, key questions will include the granularity of slicing, how Flex:ai interacts with standard Kubernetes schedulers, and, crucially, whether it supports widely used GPU types via standard plugins. The company has said that researchers from Shanghai Jiao Tong, Xi’an Jiaotong, and Xiamen University contributed to the tool’s development.

Huawei’s in-house Ascend processors and their surrounding supplier network are being positioned as the foundation of a national effort to build an independent, fully domestic semiconductor ecosystem in China. That includes everything from high-end AI chips and custom optical networks, through to packaging materials, photoresists, and gas delivery systems.

More than 60 semiconductor companies are now backed by Huawei’s investment arm Hubble, while local partners like Empyrean are advancing design toolchains to support a parallel AI software ecosystem independent of Nvidia and other U.S. vendors, according to reporting by Nikkei Asia and Trendforce,

This growing web of suppliers was showcased at the China Hi-Tech Fair in Shenzhen, where Huawei’s CloudMatrix 384 system, an AI server rack integrating 384 Ascend 910C processors, was positioned as a direct alternative to Nvidia’s GB200 platform Though obvious performance and efficiency trade-offs remain, the system highlights how far Huawei has come since the U.S. first restricted its access to foundry services and IP in 2019.

Competing with Blackwell by scale

The foundation of Huawei’s server strategy is the Ascend 910C, a dual-chiplet accelerator built using stacked HBM2E memory and a DaVinci NPU architecture tailored for AI workloads. The chip delivers up to 780 TFLOPS of dense BF16 compute, with the entire package consuming 350 watts

That trails Nvidia’s Hopper-based H100 or Blackwell-based B200 in both peak throughput and power efficiency, but Huawei offsets the difference by scaling up. The CloudMatrix 384 system, for example, combines twelve racks of Ascend modules with four optical interconnect racks, creating a 384-processor fabric that delivers around 300 PFLOPS in total. The network is entirely optical, with 6,912 pluggable transceivers forming a high-bandwidth, all-to-all topology.

The system draws around 559 kilowatts at peak load, which is nearly four times the power draw of Nvidia’s GB200-based DGX system. But Chinese data centers face fewer regulatory constraints on energy use, and local power costs remain significantly lower than in the U.S. That trade-off, paired with large-scale domestic chip availability, makes the Ascend stack a viable foundation for training large-scale AI models in-country. Huawei’s internal tests claim CloudMatrix outperforms Nvidia H100 platforms on specific model classes, although public benchmarks remain scarce.

The software stack around Ascend is also maturing. Huawei’s CANN programming environment and MindSpore framework support common model architectures through a translation layer that can ingest PyTorch or TensorFlow graphs. While CUDA remains dominant globally, Huawei is planning to open-source more of its toolchain to accelerate local development and draw interest from non-domestic partners where export controls permit.

Building the supply chain from the bottom up

What makes Huawei’s AI hardware strategy notable is how tightly integrated it has become with the broader Chinese chip supply chain. Hubble, Huawei’s private equity arm, has taken minority stakes in dozens of component and material suppliers since its formation. These firms are now expanding capacity or acquiring competitors, often with local government backing, to ensure domestic resilience against future sanctions.

Jiangsu-based HHCK Advanced Materials, in which Huawei holds a 2% stake, is one example. In November, the company acquired a rival producer of heat-resistant epoxy resins for around $255 million. In parallel, Vertilite, 4%-owned by Huawei, opened a new compound semiconductor facility in Jiangsu. It produces lasers and modulators for high-speed optical links, key to Huawei’s full-rack optical mesh interconnects. Meanwhile, Shanghai Winscene Technology is scaling up production of photoresists, which are essential to lithographic processes. Aerotech, another Huawei-linked firm, is expanding capacity for gas flow systems and valves used in chipmaking equipment.

Each of these firms targets a known vulnerability in China’s chip manufacturing pipeline. Huawei has also been linked to domestic efforts in electronic design automation. While Huawei is not believed to have an equity stake in Empyrean Technology, China’s leading EDA developer, sources say the two collaborate closely on tool development and circuit verification.

To compensate for its lack of access to EUV lithography tools, Huawei and its affiliate SiCarrier have jointly developed DUV-based multi-patterning techniques that could push logic nodes to the 5nm range, albeit with significant yield and cost penalties. SiCarrier holds patents in this area, and Huawei is reportedly helping validate the approach in early production.

A parallel stack, but not a level playing field

Despite progress, Huawei still lags behind Nvidia in per-chip performance, software adoption, and global market share. Nvidia’s GPUs remain standard in nearly all major machine learning frameworks and benefit from tight integration with CUDA, cuDNN, and optimized libraries for training and inference. Huawei’s MindSpore framework is still developing comparable capabilities and lacks widespread support outside China.

Ascend’s per-chip performance is also behind. Each 910C delivers roughly one-third the BF16 throughput of Nvidia’s B200. Even though Huawei can match or exceed total system performance by scaling horizontally, it still takes more silicon and more power to achieve parity. As of now, that cost is one Huawei is willing to absorb, especially as it builds a stack for use within China’s own borders and regulations.

Foundry access is another constraint. SMIC and other Chinese fabs are pushing 7nm-class production using DUV techniques, but yields remain behind TSMC or Samsung, and Huawei cannot currently access the latter’s advanced nodes. However, recent reporting by Bloomberg found that Huawei could be receiving backdoor foundry support through foundry networks, given that smuggled dies and Samsung HBM memory were recently found in Huawei’s new Ascend 910C AI chip.

In policy terms, the growth of Huawei’s semiconductor network fits neatly into China’s next five-year plan. The current draft, which runs through 2030, names chip self-reliance as a strategic priority. The national Big Fund, now in its third phase, has committed over $47 billion to semiconductor development. Hubble, Huawei and other private actors operate within this framework, often co-investing with local governments and state-owned capital vehicles.

The result is a vertically integrated, Huawei-centric supply chain that can design and deploy AI chips at volume without U.S. or European support. Whether it will deliver leading-edge performance and efficiency in the future remains uncertain. What is clearer is that the company, and the country around it, now have a credible fallback plan if sanctions tighten further or if access to key imports collapses.

Huawei has introduced two new desktop systems in the Chinese domestic market. The Qingyun W515y and W585y leverage Huawei's homemade Kirin 9000X processor, complemented by the Tongxin UOS V20 or Galaxy Kylin V10 operating systems that aim to unseat Windows in the Chinese market.

The company has not officially unveiled the Kirin 9000X chip to the public yet. However, reports indicate that the octa-core, 16-thread processor, developed by HiSilicon, features a 2.5 GHz base clock. The Kirin 9000X succeeds the Kirin 9000C, which aligns with the recent release of the Qingyun W515y and W585y as direct replacements for the Qingyun W515x and W585x, respectively.

The original Kirin 9000, based on the Arm architecture, comprises three Cortex-A77 cores—one operating at 3.13 GHz and three at 2.54 GHz—and four Cortex-A55 cores at 2.05 GHz. Furthermore, the chip incorporates a 24-core Mali-G78 iGPU. Huawei has released multiple variants of the Kirin 9000 to accommodate various devices, including smartphones, laptops, and desktops. TSMC previously manufactured the Kirin 9000 for Huawei, using the 5nm+ FinFET EUV (N5) process node before the imposition of U.S. trade restrictions.

Huawei has not disclosed the complete specifications of the Qingyun W515y and W585y models. The manufacturer only states that these devices are equipped with quad-channel LPDDR5x memory, an unspecified SSD and hard drive, and offer the option to install an optical drive (DVD-RW). Both the Qingyun W515y and W585y have identical dimensions —11.5 x 3.7 x 12.4 inches (293 x 93 x 315.5 mm) —and weigh 7.9 pounds (3.6 kg) when the optical drive and hard drive are not included. They are the same size as their predecessors but just a bit lighter.

Huawei has been vigorously promoting its HarmonyOS operating system across its product range for some time. Consequently, it is surprising that neither of these utilizes this operating system. The previous Qingyun W515x and W585x didn't use HarmonyOS, either. Instead, these devices offer consumers a choice between UOS V20 (Unified Operating System), developed by UnionTech (Tongxin), and Galaxy Kylin V10. Both operating systems are based on Linux with their respective modifications.

The designs of the Qingyun W515y and W585y haven't changed from their predecessors. The case still features a front panel equipped with one USB Type-C port, three USB 3.2 Gen 1 Type-A ports, and a combined 3.5mm microphone and headphone jack. Conversely, the rear panel is furnished with four USB 3.2 Gen 1 Type-A ports, a Gigabit Ethernet port, a serial port, three 3.5mm audio connectors, one VGA port, and one HDMI port.

Huawei includes the K100 wired keyboard and M100 wired mouse with the Qingyun W515y and W585y models. The manufacturer has not disclosed the pricing or the availability dates for the new desktops.

Beijing’s strategic push for semiconductor self-reliance depends heavily on key companies like Huawei — and China just proved how far it will go to defend them.

China added several prominent Western companies to its Unreliable Entity List on Thursday, including the research firm TechInsights. This Canadian company was one of the institutions that revealed Huawei used TSMC to build the Ascend 910B chip despite American sanctions — resulting in a possible $1-billion fine for the Taiwanese chip maker.

According to the announcement by the Ministry of Commerce [machine translated] (via Bloomberg), organizations and individuals within China are prohibited “from engaging in transactions, cooperation, and other activities with the aforementioned entities, especially transmitting data or providing sensitive information to these entities.”

TechInsights and all its subsidiaries across the globe are included in the ban. But what’s interesting is that the research firm has been specifically mentioned in the government announcement, and that most of the other companies on the list are defense contractors and aerospace companies like Elbit Systems of America and BAE Systems. There’s also a smattering of anti-drone companies, like Dedrone and Epirus, which developed the Leonidas microwave system that can take down drone swarms.

“Foreign entities such as Dedrone by Axon and TechInsights and their affiliates have defied China’s strong objections to engage in activities such as so-called military-technical cooperation with Taiwan, made malicious remarks concerning China, and assisted foreign governments in suppressing Chinese companies,” China said in another statement.

It’s understandable for China to add all the other companies to its Unreliable Entity List, especially given that most of them have defense projects and work with the military forces of the nation’s rivals, like the U.S. and Taiwan. But TechInsights isn’t a military or defense contractor — it’s primarily a semiconductor intelligence firm that specializes in reverse engineering and teardowns, plus market analysis.

The primary reason why it may have been added to the list is that it investigated Huawei, one of China’s crown jewels when it comes to tech companies. Although the country’s semiconductor industry has taken strides in recent years, TechInsight’s investigations in 2023 and 2024 revealed Huawei’s reliance on technologies and chips from TSMC, Samsung, and SK hynix, which might’ve contradicted Beijing’s strategic push for semiconductor self-reliance.

Because it’s located outside of China, TechInsights will likely still be able to make teardowns of Chinese tech it can acquire and publish its findings. Still, we’re unsure how China’s announcement will affect its business operations, especially as the company has not released any statement at the time of writing.

Chinese AI firm DeepSeek has released its latest large language model, DeepSeek-V3.2-Exp, with first-day optimizations for Huawei’s Ascend hardware and CANN software stack. The launch marks a shift in priorities to ensure leading-edge models run on domestic accelerators rather than relying on Nvidia’s CUDA ecosystem.

DeepSeek announced the model on September 29, posting code and checkpoints to Hugging Face alongside a technical report. The company describes V3.2-Exp as an “intermediate step toward our next-generation architecture,” designed to cut costs on long-context inference. It features a sparse attention mechanism that trims memory and compute requirements while maintaining output quality.

Huawei’s Ascend team and the wider vLLM-Ascend community moved swiftly to integrate DeepSeek-V3.2-Exp. In the vLLM-Ascend repo, a new issue outlines custom operator installation steps and kernel packaging for Ascend NPUs to support V3.2-Exp. The CANN team also published an inference recipe, positioning the model for immediate deployment across Huawei hardware.

Other Chinese chipmakers have joined in, including Cambricon, which released an update to its vLLM-MLU fork with compatibility for V3.2-Exp, claiming the combination of its inference engine and the model’s sparse attention cuts costs for processing long sequences. Hygon also announced that its DCU accelerators had been tuned for “zero-wait” deployment through its DTK software stack.

Huawei has unveiled its next-generation data-center scale AI solution that can offer 1 FP4 ZettaFLOPS performance for AI inference and 524 FP8 ExaFLOPS for AI training at its Huawei Connect 2025 conference on Thursday. The new SuperCluster 950 system runs hundreds of thousands of the company's Ascend 950DT neural processing units (NPUs) and promises to be one of the most powerful supercomputers for artificial intelligence on the planet. Huawei expects its SuperCluster to compete with Nvidia's Rubin-based systems in late 2026.

Massive performance

Huawei's Atlas 950 SuperCluster will consist of 64 Atlas 950 SuperPoDs, which are the company's rack-scale AI solutions akin to Nvidia's GB300 NVL72 or the next-generation Vera Rubin NVL144. The Atlas 950 SuperCluster will be built upon 524,288 Ascend 950DT AI accelerators distributed across over 10,240 optically interconnected cabinets.

The supercomputer purportedly offers up to 524 FP8 ExaFLOPS for AI training and up to 1 FP4 ZettaFLOPS for AI inference (MXFP4 to be more specific), which puts it just behind leading-edge AI supercomputers, such as Oracle's OCI Supercluster running 131,072 B200 GPUs and offering peak performance of up to 2.4 FP4 ZettaFLOPS for inference introduced last year. Keep in mind these figures pertain to peak performance numbers, so it remains to be seen whether they can be achieved in real life.

This SuperCluster is designed to support both RoCE (Remote Direct Memory Access over Converged Ethernet) and Huawei's proprietary UBoE (UnifiedBus over Ethernet) protocols, though it remains to be seen how fast the latter will be adopted. According to Huawei, UBoE offers lower idle-state latency, higher hardware reliability, and requires fewer switches and optical modules than traditional RoCE setups.

Huawei positions its Atlas 950 SuperCluster to support training and inference workloads for AI models with hundreds of billions to tens of trillions of parameters. Huawei believes this platform is well-suited for the next wave of large-scale dense and sparse models, thanks to its combination of compute throughput, interconnect bandwidth, and system stability. Though given its size, it is unclear how many companies will be able to accommodate the system.

Massive footprint

Huawei admits that it cannot build processors that would challenge Nvidia's GPUs in terms of performance. Therefore, to achieve 1 ZettaFLOPS with the Atlas 950 SuperCluster, it intends to use a brute force approach, utilizing hundreds of thousands of AI accelerators to compete against Nvidia Rubin-based clusters in 2026–2027.

A common building block of Huawei's Atlas 950 SuperCluster is the Atlas 950 SuperPoD that integrates 8,192 Ascend 950DT chips, representing a 20-fold increase in processing units compared to the Atlas 900 A3 SuperPoD (also known as the CloudMatrix 384) and a massive increase in compute performance — 8 FP8 ExaFLOPS and 16 FP4 ExaFLOPS.

Performance of the Atlas 950 SuperCluster is truly impressive on paper; it is said to be massively higher compared to Nvidia's Vera Rubin NVL144 (1.2 FP8 ExaFLOPS, 3.6 NVFP4 ExaFLOPS), a product that the company compares it to. However, that performance comes at a price, namely size. The Atlas 950 SuperCluster setup includes 160 total cabinets — 128 for computation and 32 for communications — spread across 1,000 square meters, which is about the size of two basketball courts. By contrast, Nvidia's Vera Rubin NVL144 is a rack-scale solution that consists of one compute rack and one cable and switch rack that requires just several square meters of space.

As for Huawei's Atlas 950 SuperCluster — which consists of 64 Atlas 950 SuperPoDs and should measure around 64,000 m2 — its size is comparable to 150 basketball courts, or nine regulation soccer fields. Keep in mind, though, that a real campus would likely require additional space for power rooms, chillers/cooling towers, battery/UPS systems, and support offices, so the total site footprint could be significantly larger than 64,000 m².

The road ahead

Chinese companies Huawei and Cambrincon have begun to ramp up their production of AI accelerators at China-based fabs, according to J.P. Morgan (via @rwang07) and SemiAnalysis. If everything goes as planned, China will get over a million domestically developed and produced AI accelerators in 2026 from these two companies alone. This will hardly be enough to dethrone Nvidia's AI GPUs in the People's Republic, but it will certainly be a major step towards AI self-sufficiency.

However, it remains to be seen whether Chinese industry can produce millions of AI accelerators, as there seem to be two major bottlenecks — advanced semiconductor fab capacity and HBM memory supply. Furthermore, it remains to be seen whether these processors can deliver sufficient performance for China's AI industry.

No more TSMC for Chinese AI companies (well, almost)

Although it was widely believed that Huawei produced a significant portion of its Ascend 910B accelerators at Semiconductor Manufacturing International Corp.'s (SMIC) fabs in China, the company actually used shell companies to place orders with TSMC and deceive the world's largest foundry to make Ascend 910B silicon.

In fact, virtually all of the China-based developers of AI accelerators — from Cambricon Illuvatar CoreX to Biren and Enflame — have either used, or continue to use, TSMC's services. However, only Huawei has managed to deceive TSMC and have a high-performance AI processor fabricated in Taiwan despite being on the U.S. Department of Commerce's Entity List that prohibits TSMC (and other companies) from working with the Chinese high-tech giant.

Since blacklisting Huawei in 2020, which obliges companies to obtain an export license from the U.S. government to ship any device containing American technology to the company, the U.S. government has put numerous China-based developers of AI accelerators and CPUs into its Entity List and introduced quite serious sanctions against China's AI/HPC and semiconductor sectors. As a consequence, only a handful of companies from the People's Republic can use TSMC services involving more or less sophisticated process technologies. Those who can still work with TSMC now produce simplified designs (up to 30 billion transistors on 16nm-class production node) packaged by a trusted OSAT provider, targeting entry-level systems.

Time for SMIC to step in

While SMIC apparently did not produce AI accelerators for Huawei until fairly recently, the company has been making the company's HiSilicon Kirin 9000S and similar system-on-chips (SoC) for smartphones. This has not only helped Huawei to return to the market of high-end smartphones without using restricted processors and models from Qualcomm, but also enabled SMIC to polish off its 7nm-class (also known as N+2) fabrication technology. Keeping in mind that Kirin 9000S has a die size of around 107 mm², whereas the AI accelerator Ascend 910B has a die size of 665 mm², it makes a lot of sense to pipe clean the node using the former.

Both SemiAnalysis and analyst Lennart Heim estimate that Huawei illicitly acquired approximately 3 million Ascend 910B dies from TSMC in 2024, which would be sufficient to assemble around 1.4 to 1.5 million Ascend 910C neural processing units (NPUs) that use two Ascend 910B dies. 1.5 million Ascend 910C NPUs are sufficient for Huawei to continue equipping its own AI data centers with in-house AI accelerators and potentially supply them to third parties.

SemiAnalysis believes that Huawei would have run out of silicon by now, but its partner SMIC began to ramp up production of Ascend 910B (or whatever it is called) in the third quarter of 2024, gradually increasing output to alleged hundreds of thousands of units in the first half of 2025. That ramp is set to continue, enabling Huawei to build as many as 1.2 million Ascend 910B dies in the fourth quarter of this year, according to SemiAnalysis.

SMIC appears to have made progress with 7nm-class production technologies and can now produce significant volumes of Ascend dies. Analysts estimate that as few as 20,000 wafer starts per month (WSPM) could enable production of several million chips annually. SMIC's total advanced-node capacity is projected to reach 45,000 wafers per month by the end of 2025, expand to 60,000 by 2026, and 80,000 by 2027.

Of course, SMIC's 7nm-class yields remain below those of TSMC, especially for large chips like the Ascend NPUs. However, if SMIC allocates 50% of its output for Ascend, even at a below 50% yield, Huawei will get over 5 million Ascend 910B dies in Q4 2026, according to SemiAnalysis. The big question is whether even 2.25 million Ascend 910C processors will be enough to meet AI performance requirements in late 2026.

SMIC has bottlenecks

JP Morgan is a bit more conservative with its predictions about the production of Chinese AI accelerators, saying that Huawei will get 600 – 650 thousand of '700 mm²-equivalent' dies from local producers (which may include SMIC and perhaps Huawei's own fab, though it is unlikely that this fab is good enough to produce data center-grade chips at this point) this year and 800 – 850 thousand dies in 2026.

We do not know the die size of the Ascend 910B produced at SMIC, but it is likely that it is larger than that of the same processor made at TSMC, likely close to 700 mm², so JP Morgan's estimates should be close to the number of actual NPUs that Huawei may get. The analysts also estimate that Cambricon can get 25 – 30 thousand large chips from SMIC this year, 300 – 350 thousand in 2026, and 450 – 480 thousand in 2027. Keep in mind that the current unit estimates reflect wafer-level production after wafer-in.

JP Morgan seems to be quite cautious about SMIC's output in general. Analysts from the company claim that it takes about six months from wafer start to chip completion, plus two more months for packaging and module assembly, so it essentially takes SMIC eight months to produce an Ascend 910C.

To put it into context, for TSMC’s 7nm-class process nodes (such as N7, N7+, N6), the typical wafer cycle time — from starting wafer to completed processed wafer — ranges between 90 to 100 days, depending on factors like process complexity and customer priority. For CoWoS-S advanced packaging, the lead time is somewhere between 30 and 60 days, depending on complexity.

SMIC's production cycle at 7nm-class nodes is roughly twice as long as TSMC's, primarily due to its reliance on DUV-only lithography with heavy multi-patterning. TSMC's N7 and N7P process technologies also relied on DUV lithography (only N7+ and N6 incorporate EUV, enabling them to simplify critical layers and reduce overall process steps), but their cycle was not that long. Perhaps, SMIC has fewer higher-end Twinscan NXT:1980i or NXT:2000i litho tools than TSMC, which creates a major bottleneck for large chips like the Ascend 910B, or maybe its fab is less efficient (e.g., has slower tools, less automation) in general. It is also unclear whether SMIC has advanced packaging in-house or has to turn to companies like JCET to fully assemble an Ascend 910C module.

If JP Morgan's assessment is accurate and SMIC/Huawei have major fab bottlenecks for 7nm-class fabrication technology and large chips, then ramping the fab up may be problematic without access to ASML's fairly advanced scanners like the Twinscan NXT:1980Di (unrestricted for China, restricted for SMIC) or NXT:2000i (a restricted tool for China).

As Huawei clearly knows that SMIC's capacity may not be enough to satisfy its demands for mobile application processors, CPUs, and AI accelerators, the company is simultaneously investing heavily in its own fabrication facilities. To equip them, it facilitated the creation of SiCarrier, a maker of fab tools with big ambitions, and bought $9 billion worth of fab tools in recent years to install them into fab(s), reverse engineer them, and build at SiCarrier.

If Huawei's fab project becomes a success, it will not only enable the company's greater control over its supply chain but will potentially free up SMIC capacity for other Chinese chipmakers such as Cambricon. However, rebuilding the whole wafer fab equipment supply chain may be too hard a task even for a company like Huawei because even to build a sophisticated DUV lithography system, it will need to replicate several industries, not just a tool from ASML or Nikon.

If there were no restrictions on advanced fab tools for China, companies like Huawei and SMIC would likely attempt to address the 7nm and possibly even 5nm and 3nm-class challenges with a brute force approach by simply procuring more tools. However, even if these companies manage to obtain plenty of ASML's NXT:1980Di for their fabs, they will still have to perfect techniques like self-aligned quadruple patterning (SAQP) and achieve decent yields, which could take years.

HBM bottleneck

But while the lack of advanced fab tools and production capacity for sophisticated nodes is something to be expected from the Chinese semiconductor industry, there is another, less obvious bottleneck for the People's Republic AI accelerators: HBM memory supply.

SemiAnalysis reports that Huawei's AI accelerator output could be limited not only by fab capacity, but by a shortage of HBM. The company had built up a large stockpile of HBM stacks — approximately 11.7 million units, with 7 million of those shipped in just one month by Samsung before U.S. export restrictions on HBM2E (and more advanced) were enforced in late 2024. While this stockpile has supported Huawei's Ascend 910C production so far, it is expected to be depleted by the end of 2025, which will stop production of these NPUs unless new sources are found.

China's main domestic DRAM supplier, CXMT, is racing to develop its own HBM capacity. The company has benefited from poached engineers, foreign equipment, and government funding, and can now manufacture DDR5 and early-stage HBM products. However, its projected output of ~2.2 million HBM stacks in 2026 will only support around 250,000 to 400,000 Ascend 910C packages, which is considerably less than what Huawei needs. While CXMT is rapidly expanding, including advanced packaging partnerships with JCET, Tongfu Microelectronics, and Xinxin, it still lacks the scale and efficiency of global leaders like Samsung and SK hynix.

As a result, Huawei and other Chinese companies may attempt to smuggle HBM produced by market leaders into the country to keep building their AI processors. However, given this constraint, China’s AI hardware industry may not be able to scale further unless it can overcome the HBM bottleneck.

What about self-sufficiency?

Being unrestricted in terms of access to advanced process technologies and HBM supply, Nvidia can produce millions of high-performance AI processors for China. As long as its products meet U.S. export controls requirements, the company can funnel millions of GPUs — whether these are relatively low-performance H20 or high-performance B30A — to China to meet demands of its partners like Alibaba or ByteDance.

Since both H20 and B30A seem to be cut-down versions of high-end H100 and B300, Nvidia's supply of such processors could also be limited, as the company would rather sell more full-fat GPUs. On the one hand, this means that China-based customers or Nvidia could acquire additional capacity from cloud service providers. On the other hand, this means that there is unsatisfied demand for AI processors in the People's Republic, a market that may well be addressed by domestic AI hardware companies.

However, recent rumors suggest that China's government wants Chinese companies to buy domestic AI hardware to strengthen the domestic industry. If China truly sets the goal for AI hardware self-sufficiency, then it may well use the brute force approach to production of AI hardware — both compute and memory — and make them regardless of yields and cost. However, given uncertainties with advanced fab capacity and HBM supply, this strategy may not work.

Furthermore, there are other obstacles like fragmented ecosystems and ubiquity of Nvidia's CUDA software stack that may prevent China from becoming self-sufficient in terms of AI hardware and software in the foreseeable future.

Huawei used its Hot Chips 2025 slot to introduce UB-Mesh technology designed to unify all interconnections across AI data centers — both inside nodes and outside nodes — with a single protocol. The company also said that it will announce it is opening up the protocol for all users for free at its event next month.

The technology is meant to replace PCIe, CXL, NVLink, and TCP/IP protocols with one single protocol to cut latency, control costs, and improve reliability in gigawatt-class datacenters. To push the initiative, Huawei plans to open-source the specification. But will it gain traction?

"Next month we have a conference, where we are going to announce that the UB-Mesh protocol will be published and disclosed to anybody like a free license," said Heng Liao, chief scientist of HiSilicon, Huawei's processor arm. "This is a very new technology; we are seeing competing standardization efforts from different camps. […] Depending on how successful we are in deploying actual systems and demand from partners and customers, we can talk about turning it into some kind of standard."

From a cluster to SuperNode

While AI data centers for training and inference should perform like one big inherently parallel processor, they consist of individual racks, servers, CPUs, GPUs, memory, SSDs, NICs, switches, and other components that connect to each other using different buses and protocols, such as UPI, PCIe, CXL, RoCE, NVLink, UALink, TCP/IP, and upcoming Ultra Ethernet, just to name a few. Protocol conversions require power, increase latency and cost, and introduce potential points of failure, all factors that can scale catastrophically in gigawatt-class data centers with millions of processors.

Instead of juggling a plethora of links and protocols, Huawei proposes one unified framework called UB-Mesh that enables any port to talk to any other without translation. That simplicity cuts out conversion delays, streamlines design, and still leaves room to operate over Ethernet when needed, essentially converting the whole data center into a UB-Mesh-connected coherent SuperNode.

Huawei defines SuperNode as a data center-scale AI architecture that unifies up to 1,000,000 processors (whether these are CPUs, GPUs, NPUs), pooled memory, SSDs, NICs, and switches into one system with per-chip bandwidth rising from 100 Gbps to 10 Tbps (1.25 TB/s, beyond what even PCIe 8.0 is set to provide), hop latency reduced from microseconds to ~150 ns, and overall design shifting from asynchronous DMA toward synchronous load/store semantics.

This structure is designed to lower latency, allow all high-speed SERDES connections to be reused flexibly, and even support operation over Ethernet for backward compatibility.

New technical challenges

However, Huawei admits that scaling this concept across a data center introduces new challenges, particularly the move from copper (which still connects inside the rack) to pluggable optical links. Fiber optics are unavoidable for long distances but comes with error rates that are way higher than electrical connections. To manage this, Huawei proposes link-level retry mechanisms, backup lanes within optical modules, and crossover designs that connect controllers to multiple modules. These measures are designed to ensure continuous operation even when individual links or modules fail, though they obviously increase costs.

The network topology in UB-Mesh is hybrid. At the top level, a CLOS structure would tie together racks across a hall. Beneath that, multi-dimensional meshes would link tens of nodes inside each rack. This hybrid model is meant to avoid the runaway expense of conventional designs as systems grow to tens or hundreds of thousands of nodes.

Also, reliability has to be implemented beyond individual links. Huawei outlined a system model where hot-spare racks automatically take over when another rack fails. Then faulty racks are repaired and rotated back in to maintain availability. This design extends mean time between failures by orders of magnitude, a scale of improvement necessary for million-chip systems, according to Huawei.

Lower costs

From a cost perspective, the difference is stark, based on data from Huawei. Traditional interconnects tend to see linear growth in costs as the number of nodes increases, which means that they can eventually eclipse the price of AI accelerators (such as Nvidia's H100 or B200) themselves. UB-Mesh, by contrast, scales in a sub-linear fashion, adding capacity without proportionally increasing cost. Huawei even pointed to a practical 8,192-node system combining CLOS and 2D mesh elements as proof of feasibility.

Strategic implications

With UB-Mesh and the SuperNode, Huawei is offering a systems-level architecture designed to support massive AI clusters in China and abroad. If the technologies take off, then Huawei will reduce (or rather cease) dependence on Western standards like PCIe, NVLink, UALink, and even TCP/IP inside its next-generation data centers. Rather than competing with AMD, Intel, and Nvidia on CPUs, GPUs, or even rack-scale solutions, Huawei is trying to build a data center-scale offering.

But the question is, will the initiative be adopted by anyone beyond Huawei, as it remains to be seen whether the company's customers will be interested in getting their data center infrastructure from a single supplier. To that end, Huawei is opening up the UB-Mesh link protocol for the world to evaluate. If Huawei is successful with its own deployments and there is enough interest from third parties, then it can turn UB-Mesh into a standard and perhaps even standardize the SuperNode architecture itself.

However, it remains to be seen whether the industry is interested. Nvidia relies on its own NVLink connections inside the rack and Ethernet or InfiniBand across the data center. Other companies like AMD, Broadcom, and Intel are pushing UALink for inter-pod communications and Ultra Ethernet for data center-wide connections. Both technologies are standardized and supported by a wide range of companies, enabling flexibility and reducing costs.

Last week saw major twists in China's AI landscape: Trump imposed a 15% sales tax on AMD and Nvidia hardware sold to China, Beijing froze new Nvidia H20 GPU purchases over security concerns, and DeepSeek dropped plans to train its R2 model on Huawei’s Ascend NPUs — raising doubts about China's ability to rely on domestic hardware for its AI sector.

As part of its recurring five-year strategic plans, China's long-stated goal has been to gain its own technological independence, particularly in new and emerging segments that it sees as key to its national security. However, after years of plowing billions into fab startups and its own nascent chip industry, that country still lags behind its Western counterparts and has struggled to build its own truly insulated supply chain that can create AI accelerators. Additionally, the country lacks an effective software ecosystem to rival Nvidia's CUDA, creating even more challenges. Here's a closer look at how this is impacting the country's AI efforts.

China wants to rely on its own hardware

China has had a self-sufficiency plan for its semiconductor industry in general since the mid-2010s. Over time, as the U.S. imposed sanctions against the People's Republic's high-tech sectors, the plan evolved to address supercomputers (including those capable of AI workloads) and fab tools. In 2025, China has created several domestic AI accelerators, and Huawei has even managed to develop its rack-scale CloudMatrix 384.

However, ever since the AI Diffusion Rule was canned, and the incumbent Trump administration banned sales of AMD's Instinct MI308 and Nvidia's HGX H20 to Chinese entities, the PRC doubled down on its efforts to switch crucially important AI companies to using domestic hardware.

As a result, when the U.S. government announced plans to grant AMD and Nvidia export licenses to sell their China-specific AI accelerators to clients in the People's Republic, U.S. President Trump announced an unprecedented 15% sales tax on AMD's and Nvidia's hardware sold to China.

China's government then made shipments of Nvidia's HGX H20 hardware strategic, and instructed leading cloud service providers to halt new purchases of Nvidia’s H20 GPUs while it examines alleged security threats, a move that could potentially bolster demand for domestic hardware. This may be good news for companies like Biren Technology, Huawei, Enflame, and Moore Threads.

There's a twist in this tale, though — DeepSeek reportedly had to abandon training of its next-generation R2 model on domestically developed Huawei's Ascend platforms because of unstable performance, slower chip-to-chip connectivity, and limitations of Huawei's Compute Architecture for Neural Networks (CANN) software toolkit. This all begs the question: can China rely on its homegrown hardware for AI development?

Nvidia is dominating

Nvidia has been supplying high-performance AI GPUs fully supported by a stable and versatile CUDA software stack for a decade, so it's not surprising that many, if not all, of the major Chinese AI hyperscalers — Alibaba, Baidu, Tencent, and smaller players like DeepSeek currently use Nvidia's hardware and software. Although Alibaba and Baidu develop their own AI accelerators (primarily for inference), they still procure tons of Nvidia's HGX H20 processors.

SemiAnalysis estimated that Nvidia produced around a million HGX H20 processors last year, and almost all of them were purchased by Chinese entities. No other company in China supplied a comparable number of AI accelerators in 2024. However, analyst Lennart Heim believes that Huawei had managed to illegally obtain around three million Ascend 910B dies in 2024 from TSMC, which is enough to build around 1.4 – 1.5 million Ascend 910C chips in 2024 – 2025. This is comparable to what Nvidia supplied to China in the same period. However, while Huawei may have enough Ascend processors to train its Pangu AI models, it appears that other companies have other preferences.

DeepSeek trained the R1 model on a cluster of 50,000 Hopper-series GPUs. This consisted of 30,000 HGX H20s, 10,000 H800s, and 10,000 H100s. These chips were reportedly purchased by DeepSeek's investor, High-Flyer Capital Management. As a result, it's logical that the whole software stack of DeepSeek — arguably China's most influential AI software developer — is built around Nvidia's CUDA.

However, when the time came to assemble a supercluster to train DeepSeek's upcoming R2 model, the company was reportedly persuaded by the authorities to switch to Huawei's Ascend 910-series processors. However, when it encountered unstable performance, slower chip-to-chip connectivity, and limitations of Huawei's CANN software toolkit, it decided to switch back to Nvidia's hardware for training, but use Ascend 910 AI accelerators for inference. Speaking of these exact accelerators, we do not know whether DeepSeek used Huawei's latest CloudMatrix 384, based on the latest Ascend 910C, or something else.

Since DeepSeek has not disclosed these challenges officially, we can only rely on a report from the Financial Times. The publication claims that Huawei's Ascend platforms did not work well for DeepSeek. Why they were deemed to be unstable is another question. It's a distinct possibility that DeepSeek only began to work with CANN this Spring, so the company simply has not had enough time to port its programs from Nvidia's CUDA to Huawei's CANN toolkit.

Steps into right directions

It is extremely complicated to analyze high-tech industries in China, as companies tend to keep secrets closely guarded and fly under the U.S. government's radar. However, two important factors that may have a drastic effect on the development of AI hardware in China occurred this summer. Firstly, the Model-Chip Ecosystem Innovation Alliance was formed, and secondly, Huawei made its CANN software stack open source.

The Model Chip Ecosystem Innovation Alliance includes Huawei, Biren Technologies, Enflame, and Moore Threads and others. The group aims to build a fully localized AI stack, linking hardware, models, and infrastructure, which is a clear step away from Nvidia or any other foreign hardware. Its success depends on achieving interoperability among shared protocols and frameworks to reduce ecosystem fragmentation. While low-level software unification may be difficult due to varied architectures (e.g., Arm, PowerVR, custom ISAs), mid-level standardization is more realistic.

By aligning around common APIs and model formats, the group hopes to make models portable across domestic platforms. Developers could write code once — e.g., in PyTorch —and run it on any Chinese accelerator. This would strengthen software cohesion, simplify innovation, and help China build a globally competitive AI industry using its own hardware. There is also an alliance called the Shanghai General Chamber of Commerce AI Committee, which focuses on applying AI in real-world industries; this also unites hardware and software makers.

Either as part of the commitment to the new alliance, or as part of the general attempt to make its Ascend 910-series the platform of choice among China-based companies, Huawei open-sourced CANN in early August, which is specifically optimized for AI and its Ascend hardware.

Until this summer, Huawei's AI toolkit for its Ascend NPUs was distributed in a restricted form. Developers had access to precompiled packages, runtime libraries, and bindings, which allowed TensorFlow, PyTorch, and MindSpore to run on the hardware. These pieces worked well enough to allow users to train and deploy models, but the underlying stack, such as compilers or libraries, remained closed.

CANN goes open-source

Now, this barrier has been removed. The company released the source code for the full CANN toolchain; however, it did not formally confirm what exactly it unseals, so we can only wonder or speculate. The list of opened up technologies likely includes compilers that convert model instructions into commands that Ascend NPUs understand, such as low-level APIs, libraries of AI operators that accelerate core math functions, and a system-level runtime. This will allow the management of memory, scheduling, and communication. This isn't officially confirmed, but merely an educated guess as to what CANN's open-sourcing might enable.

By opening up CANN, Huawei can attract a broad community of developers from academia, startups, and other enterprises to its platform, and enable them to experiment with performance tuning or framework integration (beyond TensorFlow and PyTorch). This will inevitably speed up CANN's evolution and bug fixing. Eventually, these efforts could bring CANN closer to what CUDA offers, which will be a useful string in Huawei's bow.

For Huawei, opening up CANN ahead of other Model-Chip Alliance members was beneficial, as it already had the most mature AI hardware platform in production, and needed to position its Ascend platform as the baseline software ecosystem others could rely on. This move makes CANN the default foundation for domestic models and hardware developers (at least for now). By taking this first step, Huawei set a reference point for interoperability and signalled a commitment to shared standards, which could help reduce fragmentation in China's AI software stack.

What about hardware availability?

But while unification of the software stack is a step in the right direction, there is an elephant in the room regarding China's AI hardware self-reliance. The People's Republic still cannot produce hardware that is on par with AMD or Nvidia in volume domestically. The hardware that can be made in China is years behind the processors developed on U.S. soil.

All leading developers of AI accelerators in China, like Biren, Huawei, and Moore Threads, are in the U.S. Department of Commerce's Entity List. This means that they do not have access to the advanced fabrication capabilities of TSMC. To that end, they have to produce their chips at China-based SMIC, whose process technologies cannot match those offered by TSMC. While SMIC can produce chips on its 7nm-class fabrication process, Huawei had to obtain the vast majority of silicon for its Ascend 910B and Ascend 910C processors by deceiving TSMC. Companies like Biren or Moore's Threads do not disclose which foundry they use, but they do not have the luxury of choice.

Of course, neither Huawei nor SMIC stands still. The two companies are working to advance China's semiconductor industry and build a local fab tools supply chain that will replace the leading-edge equipment that SMIC cannot acquire. Before this happens, SMIC is expected to start building chips on its 6nm-class process technology and even 5nm-class production node, so it may well build advanced AI processors for Huawei and other players. But the big question is whether volumes will manage to meet the demands of AI training and inference, especially if Nvidia hardware is largely unobtainable in China.

China's Chicken and egg dilemma

China’s courts take tech secret pilfering seriously, if one of its homegrown companies appears to be the victim. The South China Morning Post (SCMP) reports that a Shanghai court has sentenced 14 former Huawei employees, who were accused of taking a number of “chip-related business secrets” with them, when they scooted off to form a new startup called Zunpai Communication Technology.

Apparently, the precise punishment to be meted out upon the accused remains uncertain, as the verdict is yet to be published online. However, sources indicate that the ex-Huawei engineers will face financial penalties and up to six years in jail.

The above case is reportedly a talking point in China. The topic of Intellectual property theft, its impacts on competitive industry, and on the people who work at these companies, have been thrust into the public psyche. However, the plaintiff in this case, Huawei, has yet to comment.

Ex-Huawei engineers form Zunpai

Zunpai was founded in 2021 by Zhang Kun, a former researcher at HiSilicon. Zhang had left Huawei in 2019, and in the interim, apparently headhunted talent from his old employer, with some success.

It is alleged that Zhang managed to attract some of his old colleagues over to Zunpai with high salaries and attractive stock options. But there’s no such thing as a free lunch, and these potential employees were also reportedly expected to copy secrets before they quit Huawei.

Ex-Zunpai engineers form chain gang

China's aggressive push to develop a domestic semiconductor industry has largely been successful. The country now has fairly advanced fabs that can produce logic chips using 7nm-class process technologies as well as world-class 3D NAND and DRAM memory devices. However, there are numerous high-profile failures due to missed investments, technical shortcomings, and unsustainable business plans. This has resulted in numerous empty fab shells — zombie fabs — around the country, according to DigiTimes.

As of early 2024, China had 44 wafer semiconductor production facilities, including 25 300-mm fabs, five 200-mm wafers, four 150-mm wafers, and seven inactive ones, according to TrendForce. At the time, 32 additional semiconductor fabrication plans were being constructed in the country as part of the Made in China 2025 initiative, including 24 300-mm fabs and nine 200-mm fabs. Companies like SMIC, HuaHong, Nexchip, CXMT, and Silan planned to start production at 10 new fabs, including nine 300-mm fabs and one 200-mm facility by the end of 2024.

Plenty of zombie fabs

However, while China continues to lead in terms of new fabs coming online, the country also leads in terms of fab shells that never got equipped or put to work, thus becoming zombie fabs. Over the past several years, around a dozen high-profile fab projects, which cost investors between $50 billion and $100 billion, went bust.

Many Chinese semiconductor fab projects failed due to a lack of technical expertise amid overambitious goals: some startups aimed at advanced nodes like 14nm and 7nm without having experienced R&D teams or access to necessary wafer fab equipment. These efforts were often heavily reliant on provincial government funding, with little oversight or industry knowledge, which lead to collapse when finances dried up or scandals emerged. Some fab ventures were plagued by fraud or mismanagement, with executives vanishing or being arrested, sometimes with local officials involved.

To add to problems, U.S. export restrictions since 2019 blocked access of Chinese entities to critical chipmaking equipment required to make chips at 10nm-class nodes and below, effectively halting progress on advanced fabs. In addition, worsening U.S.-China tensions and global market shifts further undercut the viability of many of these projects.

So, let's go over some of China's most ambitious fab projects, many of which have fallen into oblivion, or have become a dreaded zombie fab.

Failures to learn from

Leading chipmakers, such as Intel, TSMC, Samsung, or SMIC have spent decades developing their production technologies and gain experience in chips on their leading-edge nodes. But Chinese chipmakers Wuhan Hongxin Semiconductor Manufacturing Co. (HSMC) and Quanxin Integrated Circuit Manufacturing (QXIC) attempted to take a shortcut and jump straight to 14nm and, eventually, to 7nm-class nodes by hiring executives and hundreds of engineers from TSMC in 2017 – 2019.

HSMC was founded in late 2017 with a plan to build 14nm and 7nm-capable logic fabs in Wuhan with an initial investment of around $19 billion. However, a land-use dispute halted construction in November 2019, and by mid‑2020, it suffered severe underfunding of billions of dollars. By March 2021, the local government seized the project, fired all employees, and confirmed no chip production had ever occurred.

QXIC similarly aimed at 14nm-class production when it was founded in 2019 as a sister venture to HSMC in Jinan, Shandong. The company was born after issues with HSMC occurred. Despite government backing, the project never progressed beyond hype: there were no equipment orders, no factory construction, and by 2021, operations were suspended. Interestingly, Cao Shan, who served as chief executive of QXIC, was also a former board member of HSMC.

Perhaps, the most notorious China fab venture failure — the first of many — is GlobalFoundries' project in Chengdu. GlobalFoundries unveiled plans in May 2017 to build an advanced fabs in Chengdu in two phases: Phase 1 for 130nm/180nm-class nodes and Phase 2 for 22FDX FD-SOI node. The company committed to invest $10 billion in the project, with about a billion invested in the shell alone.

Financial troubles forced GlobalFoundries to abandon the project in 2018 (the same year it ceased to develop leading-edge process technologies) and refocus to specialty production technologies. By early 2019, the site was cleared of equipment and personnel, and notices were issued in May 2020 to formally suspend operations.

The site and unfinished building remained uninhabited for five years before Shanghai Huali Microelectronics Corp. (HLMC), controlled by the Hua Hong Group, announced it would take over the dormant site in mid-2023. HLMC is one of a few Chinese companies that intend to develop a sub-10nm-class fabrication process. However, it is unclear whether the Chengdu fab will be used as its flagship facility. GlobalFoundries’ Chengdu project serves as a rare example of a recovery among China’s stalled semiconductor projects. A rare exception to the numerous failures that China has encountered thus far.

Dehuai Semiconductor, an analog and mixed signal IDM startup, was not so lucky. The company was launched in 2019 with the help of local authorities. Dehuai did not present a clear roadmap, and made false claims about how its project was proceeding. By mid-2021, local anti-corruption authorities arrested key executives after investigations revealed that no fab had been built: only initial site preparation had begun. The project was one of the most notorious examples of fraud and mismanagement among China’s failed semiconductor ventures.

The fate of Fujian Jinhua Integrated Circuit (JHICC) is a bit different. Formally, this is not a failed project, but it is not a living one either. JHICC was launched with an ambition to build China's first large-scale DRAM fab in 2016. The company magically began trial production about two years after its inception, but it was soon discovered that it had stolen process technology from Micron using the help of UMC. Eventually, the U.S. Commerce Department put Fujian Jinhua into its Entity List, cutting its access to any American technology. This essentially stops the development of new process technologies and bans the procurement of any advanced tools. As a result, while JHICC has formally survived and exists on paper, it is a spectre of its former ambitions.

Another memory project that has failed in China is Jiangsu Advanced Memory Semiconductor (AMS). The company was established in 2016 with the plan to lead China's efforts in phase-change memory (PCM) technology. The company aimed to produce 100,000 300-mm wafers annually and attracted an initial investment of approximately $1.8 billion. Despite developing its first in-house PCM chips by 2019, AMS ran into financial trouble by 2020 and could no longer pay for equipment or employee salaries. It entered bankruptcy proceedings in 2023, and while a rescue plan by Huaxin Jiechuang was approved in 2024, the deal collapsed in 2025 due to unmet funding commitments.

Producing commodity types of memory is a challenging business. Tsinghua Unigroup was instrumental in developing Yangtze Memory Technology Co. and making it a world-class maker of 3D NAND. However, subsequent 3D NAND and DRAM projects were scrapped in 2022, after the company faced financial difficulties one year prior.

Tsinghua Unigroup’s second 3D NAND project aimed to mirror YMTC's model. But, at the time, even YMTC itself was still far from challenging multinational 3D NAND makers. So, the logic of building another costly fab (potentially reaching $24 billion) and possibly developing a new 3D NAND process technology was questionable.

For its DRAM efforts, Tsinghua brought in former Elpida CEO Yukio Sakamoto, who had experience competing with Samsung and Micron. However, he left in 2021 as Tsinghua approached bankruptcy, before he could contribute. Given the years and billions needed to develop DRAM technology — compounded by tool supply risks — Tsinghua scrapped its DRAM ambitions.

Logic and memory require rather sophisticated process technologies, and fabs that cost billions. By contrast, CMOS image sensors (CIS) are produced using fairly basic production nodes and on relatively inexpensive (yet very large) fabs. Nonetheless, this did not stop Jiangsu Zhongjing Aerospace, Huaian Imaging Device Manufacturer (HiDM), and Tacoma Semiconductor from failing. None of their fabs have been completed, and none of their process technologies have been developed.

China's failures could come back to haunt future ambitions