The patent application for the floppy disk was granted to two IBM engineers on this day in 1972. U.S. patent number 3668658A was for a “magnetic record disk cover” that described a rotary magnetic medium housed in a protective cover that cleaned and protected the surface. These first floppy disks were a rather large 8 inches in diameter, but had a capacity of just 80 kilobytes. They were actually floppy, like the 5.25-inch disks that readers may be more familiar with, and in contrast to the rigid plastic-encased 3.5-inch ‘save icons.’

So, floppy disks are officially 54 years old, based on the patent application's grant and publication dates. However, work on this portable storage medium began in 1967 as part of IBM’s Project Minnow. This project proposed “a flexible Mylar disk coated with magnetic material that could be inserted through a slot into a disk drive mechanism and spun on a spindle” as a form of portable/removable media, instead of tape or punched cards. Big Blue was also targeting a device cost under $200 and a media cost under $5.

IBM put these first 8-inch floppies into production in 1971, a year ahead of the patent date we are commemorating, alongside compatible drives, to offer a full solution. So folks were using these for several months ahead of the patent. Both the floppies and drives received their U.S. patents in 1972, as our headline states.

Despite its ungainly size, this first floppy disk format would be rather short on capacity, even compared to later, smaller form factors. IBM notes that it was first marketed to customers as capable of holding the same amount of data as 3,000 punched cards. That fits the era in which it was launched. However, other sources note this was equivalent to 80 kilobytes.

The next floppy disk milestone came in 1977, according to the IBM blog, when the Apple II was launched with 5.25-inch floppy drives. Steve Wozniak developed a recording scheme known as Group Coded Recording, which allowed 140 kilobytes of storage, quite a lot more than the standard single-density 90 kilobytes. Then Tandon introduced a double-sided drive in 1978, with DSDD-format floppies offering up to 360-kilobyte capacity.

In 1984, IBM would trump that with the high-density format with up to 1.2 megabytes of data storage on a 5.25-inch disk. In the same year, Apple launched the original Macintosh with a 400-kilobyte 3.5-inch floppy disk mechanism from Sony installed. IBM would refine this much more pocketable, rigid, portable disk with its 1.44 megabyte standard 3.5-inch floppy disks in 1986.

Floppies had a superb run, as far as computer technologies go. At their peak, “more than 5 billion floppy disks were sold annually,” notes IBM. Apple was again instrumental in change when, in 1998, it left tech journalists aghast by not equipping the new iMac with a built-in floppy drive.

In 2026, floppies are mere nostalgia for most computer enthusiasts. Though from time to time we still uncover surprising niches that time and new tech have forgotten, like the San Francisco Muni Metro, in New Jersey prisons, and the German Navy.

An IBM ThinkPad user boasts that they can install “(almost) all versions of Windows from NT 4 to 10 22H2,” with driver support, without resorting to virtual machine (VM) technology. The ThinkPad T43 from 2005, used by Redditor MatiHalek, was already a firm favorite among retro tech enthusiasts and well known for being IBM’s final design prior to the Lenovo acquisition. The confirmation that it can run 26 years of Windows OSes certainly adds to the T43’s considerable charms.

I installed (almost) all versions of Windows from NT 4 to 10 22H2 on my ThinkPad T43 with drivers! from r/windows

So, what did Mati actually do? In the post embedded above, you can see they posted a gallery with 10 Windows screenshots, most of which show an iteration of the System > About control panel as evidence of the version of Windows installed and running. This gallery will take many readers on a journey down memory lane as the Windows UI evolves through the eras.

Mati says that they didn’t use VMs to install any of these Windows versions. They were all real software-to-metal installs on the single-core Pentium M CPU, though it wasn’t always an entirely straightforward process getting Windows to behave. We’d assume most difficulties would be due to support and drivers for graphics and storage interface hardware.

The Redditor didn’t install the 26 years of OSes sequentially in a strictly experimental fashion. “When I got this laptop, XP was installed, so I decided to dual-boot Vista with that XP. Then I did the upgrade path Vista-7-8-8.1-10RTM,” they explained. Subsequently, Windows 22H2 wrinkles forced them into doing a clean install for this pretty recent OS from Microsoft. However, modern OSes don’t appear to be Mati’s passion as “after that, I wiped the hard drive and multi-booted 98, NT 4, and 2000.” They end their post by indicating they will be keeping this 20th-century OS trio on the IBM ThinkPad T43, simply out of preference. It's probably the most responsive choice, given the hardware.

IBM ThinkPad T43 hardware

As we mentioned in the intro, the ThinkPad T43 was the final laptop from IBM’s stables, before Lenovo took the reins. Mati was correct to assert that it originally shipped with Windows XP, and it launched just a few months before Vista hit the scene.

Key components of the T43 were as follows:

• Intel Pentium M processor
• ATi Mobility Radeon X300 or X300SE graphics
• 14.1-inch screen in resolutions up to 1,400 x 1,050 pixels
• Support for up to 2GB of DDR2
• Storage config between 40GB and 100GB HDD
• Wi-Fi, Bluetooth, Ethernet, and modem connectivity options
• Ports included 2x USB 2.0 ports, a parallel port, VGA, S-Video, a PC Card slot, and a docking station port

Beyond the hardware tech specs, the IBM ThinkPad T43 earned a lot of praise due to its durable, perhaps legendary, build and keyboard quality. It isn’t light for a 14-incher in 2026 terms, of course, weighing in at approximately 2.3 kg (5.1 pounds).

Do any readers still cherish an IBM ThinkPad T43? If so, do you still run an older version of Windows like Mati does, or have you moved to an alternative OS like Linux?

IBM has announced that it will create Anderon, a standalone company and America's first pure-play quantum chip foundry, backed by a proposed $1 billion CHIPS Act R&D award from the U.S. Department of Commerce and a matching $1 billion cash investment from IBM itself.

Headquartered in Albany, New York, Anderon will operate a 300mm quantum wafer fab and offer its manufacturing services to competing quantum hardware vendors. The deal was the centerpiece of a broader $2.013 billion federal quantum portfolio split across nine companies, the largest single quantum R&D commitment in U.S. history.

In launching Anderon, IBM is attempting to build the quantum computing industry's equivalent of TSMC, a neutral third-party manufacturer that’ll fabricate superconducting qubit wafers for other companies as well as IBM's own processors. No such foundry exists anywhere in the world today, with every operational quantum computer having been built by a vertically integrated company that designs, fabricates, and operates its own hardware.

A nine-company package

IBM's $1 billion award accounts for roughly half of the entire DoC quantum package. GlobalFoundries received a separate $375 million allocation to launch a "Quantum Technology Solutions" foundry covering multiple qubit architectures, including superconducting, trapped-ion, photonic, and silicon-spin designs. The remaining seven recipients each received smaller awards: D-Wave, Rigetti, Atom Computing, Infleqtion, PsiQuantum, and Quantinuum were each awarded $100 million, while Australian silicon-spin startup Diraq will receive up to $38 million.

Those seven non-foundry companies are required to give the federal government a minority, non-controlling equity stake in exchange for funding. Rigetti has also disclosed in a memorandum of understanding that the government will receive common stock at a 15% discount, while GlobalFoundries separately disclosed a 1% federal equity stake.

IBM's announcement contains no equivalent equity-stake disclosure for Anderon, a somewhat conspicuous omission given that the Trump administration converted part of Intel’s CHIPS Act manufacturing award into a roughly 10% government equity stake last year.

300mm wafer fabrication

IBM said back in November that all of its current and upcoming quantum processors are built on 300mm silicon wafers at the Albany NanoTech Complex, the largest public-private semiconductor R&D facility operated by the nonprofit NY CREATES. Jay Gambetta, IBM's Director of Research, wrote that the shift from 200mm to 300mm produces device output roughly 30 times faster by multiplying device complexity tenfold and tripling devices per line.

IBM's current production processor, Heron r2, holds 156 fixed-frequency qubits, while the Nighthawk processor, which went live via early access on IBM's quantum cloud in January, packs 120 qubits in a square lattice with 218 tunable couplers and a record median T1 coherence time of approximately 350 microseconds. IBM's fault-tolerance roadmap targets the Starling processor in 2029 at roughly 200 logical qubits running 100 million gates, followed by Blue Jay in 2033 at 2,000 logical qubits and 1 billion gates.

All of those chips need 300mm fabrication, and a dedicated foundry with established process design kits, in-line wafer testing, and baseline production routes could let other superconducting quantum companies skip the years and capital required to build their own cleanrooms. Anderon's initial process will support superconducting wiring, through-silicon vias, and bump interconnects, with plans to expand into other qubit modalities over time.

There’s an obvious comparison to TSMC here, which IBM is lapping up, but there’s also a fundamental difference: TSMC succeeded partly because its founder, Morris Chang, made an explicit promise not to compete with the companies that outsourced their fabrication. IBM obviously can’t credibly make that promise; it claims more than 90 operational quantum computers and an ecosystem spanning over 325 Fortune 500s, universities, and government agencies.

Quantum hardware startups considering Anderon will need to weigh 300mm production access against the risk of sharing process knowledge with their largest competitor. Google, which builds its own superconducting chips at its Santa Barbara facility and recently demonstrated quantum advantage on its 105-qubit Willow processor, is unlikely to outsource fabrication to IBM. IonQ and Quantinuum use trapped-ion architectures with almost no process commonality with superconducting silicon, and Microsoft's topological qubit program is on a different fabrication path entirely.

The near-term addressable market for Anderon is limited to other superconducting companies: Rigetti, IQM, SEEQC, and a handful of smaller companies, plus IBM itself. Whether any will actually outsource to a facility owned by their largest rival remains to be seen.

As for the choice of Albany, it carries some irony given that IBM's chip manufacturing presence in the region was effectively sold off in 2014 when the company paid GlobalFoundries $1.5 billion to take over its East Fishkill 300mm fab and Essex Junction 200mm fab. Those operations were losing roughly $700 million per year combined. GlobalFoundries later sold East Fishkill to ON Semiconductor in a deal finalized in 2023, and IBM and GlobalFoundries settled years of litigation over the original terms in January 2025.

The Albany NanoTech Complex, which sits on the SUNY Polytechnic campus, has received more than $25 billion in cumulative technology investment and hosts tenants including GlobalFoundries, Samsung, Applied Materials, ASML, Tokyo Electron, and Lam Research. In 2023, New York State committed $1 billion toward a High-NA EUV Accelerator at the complex as part of a broader $10 billion public-private partnership.

An escalating global spending race

The $2 billion U.S. quantum package comes amid a rapidly escalating global spending race. China's National Venture Guidance Fund, launched last March, authorized 1 trillion yuan, roughly $138 billion, across “hard technology” sectors, including quantum, with direct Chinese quantum investment estimated at $15 billion or more already deployed. Meanwhile, Japan has committed roughly $7.4 billion to semiconductors and quantum combined under its 2025 “Quantum Sun” industrialization agenda.

The EU Quantum Flagship is a rather paltry-by-comparison €1 billion, 10-year program. Combined with prior National Quantum Initiative spending and separate DARPA and Department of Energy programs, the CHIPS quantum package brings cumulative U.S. public quantum funding closer to parity with Europe and Japan but does little to close the gap with China.

BCG's widely cited estimate that quantum computing could generate up to $850 billion in economic value by 2040, which IBM referenced in its press release, is the optimistic end of a $450 to $850 billion range and describes end-user economic value, not vendor revenue. McKinsey's 2025 Quantum Technology Monitor projects a smaller $28 to $72 billion quantum computing revenue market by 2035, while Nvidia CEO Jensen Huang has publicly argued that practical quantum computing is 20 years away as a minimum.

It’s also worth noting that the Anderon deal isn’t yet finalized. CHIPS Act award histories show proposed amounts can shrink during due diligence: Samsung's manufacturing incentive, for example, fell from a proposed $6.4 billion in April 2024 to a finalized $4.75 billion by December 2024. Definitive documents between IBM and the DoC haven’t been executed.

What do Google Sheets experts do for fun? In the case of the staff at sheets.works, they have built The Listening Museum for mechanical keyboard audio aficionados. This is a collection of 36 iconic to modern classic keyboards that have been multisampled and put into an interactive site. Just click on any of the keyboards represented on the page, turn up your speakers, and bash away. The museum features keyboard models, including the IBM Model M, a multitude of Cherry MX models, and popular modern product samples from the likes of SteelSeries and Logitech.

I’ve owned, and still own, some great keyboards, with some vintage models dating back to the 1980s, and newfangled models with hall-effect adjustable actuation switches. However, there are plenty of samples at the Listening Museum that I can’t recall testing/hearing.

The interface at the online museum is pretty good. Clicking on the IBM Model M (for example), a soft keyboard panel appears to the right, so you can make keystrokes by mouse clicking. I did this as I’m currently using a CoolerMaster CK720, which has pretty noisy Cherry MX Blues and Greens across its various zones.

Back to the IBM, and I do believe it would be even noisier than my compact modern input device with gaskets and foam dampening layers. The museum makers assert that the Model M is “the archetypal ‘clacky’ keyboard and the reason people collect vintage boards.”

Its characteristic sound comes from the way “the coiled spring buckles sideways and slaps a pivoting hammer into the membrane. The spring resonates like a tuning fork inside the hollow ABS barrel; the steel backplate amplifies that ring; the big case acts as a soundbox,” explains the Model M section of the museum. “That is why nothing modern sounds like it.”

Audio accuracy?

As I’m actually using Cherry MX Blues while perusing the Listening Museum, I had to check out the accuracy – in the context of my ears, speakers, and environment. There are three MX Blue sampled keyboards to check through, and I must say none of them sounded like my CK720.

That’s a bit of a shame, considering the work put into making the museum. The curators have thought about such disparity, though. If you scroll down to the bottom section of the main page, you can read the headlined plea “A note before you flame us.”

There, it is made clear that “sound tests are inherently limited: microphone, room, host board, keycap set, codec, and your speakers all color the result.” And key sound can vary a lot between hosts for numerous other reasons. Fair enough, and I was never tempted to flame the curators...

Despite those observations, The Listening Museum could still be a valid resource for understanding the plethora of keyboards and keyswitches out there – and their audible feedback, which is a major part of the experience. If you are interested in exploring keyboards and don’t have a big electronics mall handy, YouTube is another good place to hear lots of well-known and obscure keyboards in action.

Check out our frequently updated Best Gaming Keyboards 2026: We've Tested Full-size, TKL, Mini, and more features to see what the cream of the crop is right now, according to our experts.

40 years ago today IBM was in the news for becoming the first computer company to make use of 1-megabit memory chips. Thus, the megabit memory era began with an American company and its Vermont fab leading the way, pushing back stubbornly against the seemingly unstoppable Japanese takeover of the memory market.

IBM’s 3090 (Sierra series) mainframe computers were the first to adopt this new high-density memory. However, the New York Times reported the occasion as “a rare, if fleeting, moment of glory,” as it thought the Japanese semiconductor industry would inexorably rise beyond its already impressive 75% market share.

The NYT’s take contrasted with IBM’s triumphant tone. “This is a signal of our semiconductor technology leadership,” said IBM SVP, Jack D. Kuehler, at the time. He went on to emphasize how these DRAM chips were built in the USA. Some of the newspaper’s cynicism came from the fact that it already knew the likes of Fujitsu, Hitachi, Mitsubishi, NEC, and Toshiba were busy sampling their own 1-megabit DRAM chips. Once they were satisfied and moved them to mass production, it was expected the Far East tiger economy would roar back to pole position.

If we turn the clock back to 1986, most computing devices in use might have packed memory chips of the 64 kilobit variety. The state-of-the-art Japanese memory tech at the time was churning out 256 kilobit memory chips. In that context IBM’s 1-megabit chips, fabricated on a 1.2 micron process, were very impressive, bringing a leap in both density and efficiency.

The arrival and establishment of 1-megabit memory chips would enable memory makers to produce 30-pin SIMMs with 1MB RAM capacity, using eight to nine chips in a single-side configuration. Such SIMMs will be very familiar to users of home and personal computers from the mid-1980s to the mid-1990s. Additionally, you would be able to use the same SIMMs in printers, on sound cards, and even graphics cards like the Tseng ET3000 / ET4000, Trident TVGA 8800 / 8900, and Cirrus Logic GD542x series.

IBM and Arm on Thursday announced a strategic collaboration to co-develop dual-architecture enterprise platforms that would enable software designed for the Arm ecosystem to work on IBM Z mainframes and LinuxONE systems in emulation mode. The collab is designed to enable enterprises to run AI and cloud-native workloads originally developed for Arm on mission-critical IBM Z enterprise hardware with ultimate reliability, availability, and security.

Nowadays, a lot of AI frameworks as well as data-intensive cloud-native applications are developed for the Arm ecosystem, whereas IBM Z platforms (based on the Z390x or z/Architecture ISA) excel in reliability, availability, and serviceability but have a narrower native software stack. This is why enterprises increasingly operate a mix of legacy transaction processing alongside AI inference and microservices, which are typically deployed on separate Arm or x86 servers, according to IBM.

Running Arm workloads on IBM Z is designed to enable running a broad software ecosystem on IBM's Z mainframe systems, particularly those that are based on the Telum II processor and Spyre AI accelerator, through virtualization or emulation without porting them to IBM Z, which is costly, time consuming, and not common for the modern industry that relies more on x86 and Arm and less on IBM Z. Therefore, by bringing these newer workloads onto the same system, IBM reduces architectural complexity, lowers integration overhead, and simplifies operations.

Furthermore, this approach keeps workloads close to where critical data already resides: financial systems, government databases, and high-value transactional engines, which reduces latencies, minimizes security and compliance risks, and eliminates the need to replicate datasets across external platforms.

"IBM's defining role in shaping enterprise infrastructure spans decades, showcasing the breadth and commitment required to support our clients' most intensive and sensitive workloads," said Christian Jacobi, Chief Technology Officer and IBM Fellow, IBM Systems Development. "This moment marks the latest step in our innovation journey for future generations of our IBM Z and LinuxONE systems, reinforcing our end-to-end system design as a powerful advantage."

The model is not intended for performance-hungry applications. In addition, emulation and virtualization introduce a host of additional performance penalties, so do not expect IBM Z systems running Arm workloads on Telum II CPUs and Spyre accelerators to demonstrate leading performance. That being said, enterprise decision-making does not prioritize performance per se, but rather total cost of ownership, operational stability, reliability, risk mitigation, and scalability.

As a result, the trade-off may well be justified, particularly for those companies that already use IBM Z for mission-critical workloads and yet have to run additional workloads on different types of hardware. At the end of the day, IBM customers do not want to replace all of their hardware and mission-critical applications, but rather want their already deployed hardware and software to evolve, which includes running modern applications alongside legacy software. Whether or not this could lead to eventual inclusion of Arm-based CPUs or accelerators into IBM servers is something that remains to be seen, but IBM does not talk about it at this point.

IBM and Lam Research have announced a five-year research collaboration to develop the materials and fabrication processes needed to scale logic chips beyond 1nm using high-NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's NY Creates Albany NanoTech Complex in New York, with Lam's Aether dry resist technology at the center of the effort alongside its Kiyo and Akara etch platforms and Striker and ALTUS Halo deposition systems.

The two companies have collaborated for over a decade on 7nm process development, nanosheet transistor architecture, and early EUV process integration. Notably, IBM unveiled what it described as the world's first 2nm node chip in 2021, marking a significant milestone in the ongoing partnership.

Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist.

Aether and high-NA EUV

Standard EUV lithography utilizes chemically amplified resists, which are spin-coated onto wafers and developed using wet chemistry. That approach, however, has a fundamental problem at the geometries high-NA EUV scanners are designed to print: stochastic noise. This is a statistical variation in photon absorption per unit area, which drives defect rates up as features shrink.

Aether’s process, however, sidesteps wet chemistry entirely by depositing the resist via vapor-phase precursors and developing it using plasma-based dry processes. According to Lam, its metal-organic compounds absorb three to five times more EUV light than conventional carbon-based resist materials, reducing the exposure dose required per wafer pass and keeping single-print patterning viable at nodes where wet-process alternatives would require more expensive multi-patterning.

Fewer process steps between exposure and etch also reduce the number of points at which pattern fidelity can degrade, which is a compounding advantage as geometries continue to tighten. The renewed collaboration between IBM and Lam is specifically focused on proving that Aether can get high-NA EUV patterns reliably transferred into real device layers at production yield. Ultimately, that’s what needs to be done before sub-1nm processes can credibly move toward a production fab.

Nanosheet transistors, which stack multiple thin sheets of silicon to increase drive current without widening the transistor footprint, are one of the primary device architectures the teams will be validating. IBM’s press release also confirms work on nanostack devices and backside power delivery, which routes power connections through the back of the wafer rather than the front, freeing up front-side metal layers for signal routing and reducing the resistance losses that compound at high transistor densities.

Three deals in 14 months

The IBM announcement marks the third significant Aether-related move Lam has made since January last year. The company confirmed that month that Aether had been selected by an unnamed leading memory manufacturer as the production tool of record for its most advanced DRAM processes. Then, in September, Lam signed a cross-licensing and collaboration agreement with JSR Corporation and its subsidiary Inpria, integrating JSR's metal oxide resists and patterning materials with Lam's etch, deposition, and dry resist capabilities for high-NA EUV.

Across 14 months, Lam has moved from production adoption in memory to a materials supply chain partnership for high-NA EUV patterning to a five-year logic research commitment with IBM, assembling a dry resist ecosystem ahead of wider high-NA EUV adoption. ASML began shipping its first high-NA EUV systems in 2023, and as those tools move toward broader foundry adoption, the choice of resist process will become one of the more consequential materials chipmakers face. JSR and Inpria's existing metal oxide resist expertise is a direct complement to Aether's vapor deposition approach, giving Lam coverage across both dry resist and metal oxide patterning materials heading into sub-1nm.

Lam isn’t the only equipment company circling high-NA EUV. Applied Materials has its own patterning materials and process integration capabilities, and ASML's dominant position in lithography gives it natural leverage over how the resist ecosystem develops around its tools. Lam's partnerships with IBM and JSR/Inpria are, at least in part, an effort to establish dry resist as the default process integration path before tooling decisions are embedded within foundries.

IBM's research complex

IBM Research's Albany NanoTech Complex is a process development facility, not a production fab, so the output of this collaboration will be validated process flows and materials knowledge that commercial foundries can adopt.

This follows the same model as the companies' prior work on 7nm and nanosheet, with the research that was demonstrated at Albany eventually feeding into production processes at TSMC and others. Sub-1nm process work starting in 2026 is therefore unlikely to reach volume manufacturing before the early 2030s.

The collaboration also presents a huge opportunity for Lam. If it’s able to establish Aether as the validated dry resist solution for high-NA EUV logic, it stands to add a significant new revenue category on top of the etch and deposition tools it already sells to nearly every advanced chipmaker.

A five-year commitment with IBM builds process familiarity and customer confidence well before foundries are making resist process decisions for their sub-1nm nodes. Lam's commercial customers — TSMC, Samsung, Intel, and others — are the ones who will ultimately adopt whatever process knowledge comes out of Albany as a result of this new research effort.

IBM and Lam Research have announced a five-year collaboration to develop the materials and fabrication processes needed to scale logic chips beyond 1nm using High NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's facilities at the NY Creates Albany NanoTech Complex in Albany, New York.

The two companies have worked together for more than a decade, contributing to 7nm process development, nanosheet transistor architecture, and early EUV process integration, with IBM unveiling what it described as the world's first 2nm node chip in 2021 as part of that ongoing partnership. Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist.

Conventional EUV lithography relies on chemically amplified resists, wet-process materials that struggle with the tighter tolerances demanded by high-NA EUV scanners. Meanwhile, Lam's Aether technology is a dry resist, deposited via vapor-phase precursors rather than spin-coating, and developed using plasma-based dry processes.

Aether’s metal-organic compounds absorb three to five times more EUV light than traditional carbon-based resist materials, which reduces the exposure dose needed per wafer pass and helps maintain single-print patterning at advanced nodes without resorting to more expensive multi-patterning. In January, Lam announced Aether had been selected by a leading memory manufacturer as the production tool of record for its most advanced DRAM processes, though it did not name the manufacturer.

According to the joint announcement, the collaboration seeks to enable High NA EUV patterns to be reliably transferred into real device layers at high yield, and to accelerate industry adoption of High NA EUV for next-generation interconnect and device patterning. That yield-at-transfer problem is where Lam's Aether dry resist technology has an edge over conventional wet processes, because fewer steps between exposure and etch mean less opportunity for pattern degradation at tighter geometries.

Meanwhile, nanosheet transistors stack multiple thin sheets of silicon to increase drive current without widening the device footprint. The press release confirms the teams will build and validate full process flows for both nanosheet and nanostack devices, alongside backside power delivery, which routes power through the back of the wafer to free up front-side interconnect layers for signal routing.

“Together, these capabilities are aimed at allowing High‑NA EUV patterns to be reliably transferred into real device layers with high yield and enabling continued scaling, improved performance, and viable paths to production for future logic devices,” says the press release.

IBM is tripling its entry-level hiring in the U.S. in 2026, according to a new report. This stands in stark contrast to many of the country’s largest firms, especially in the tech world, which have conducted large-scale layoffs, often for the claimed reasons of AI efficiency savings or pivoting the company's focus towards AI. IBM is explicit about its reasoning for the new roles, too, citing the importance of human-to-human interaction and the AI nativism of younger workers. As a result, IBM is bucking the wider industry trend, Bloomberg reports.

Speaking at the 2026 Leading with AI summit in New York last week, IBM’s chief human resources officer, Nickle LaMoreaux, described the false economy of layoffs in a world of AI-driven innovation and advancement. While firing those replaced by AI and reducing entry-level hiring may drive cost savings in the near term, LaMoreaux said that risked creating a longer-term scarcity of mid-level managers and experienced workers within the organization.

Without the ability to develop their own experienced employees, this would force companies like IBM to look outward in a more costly search for professionalism and expertise. New hires poached from other companies bring their own institutionalized baggage and can take longer to get up to speed on internal working practices and culture than those who have been fostered internally.

But it’s not just the case that IBM is restarting its standard hiring practices or doubling up on old job listings. It’s aware that AI has genuinely undercut the kind of positions that entry-level developers would take on. That doesn’t make those workers redundant, it just makes the work they’re needed for a little different, and arguably more specialized to what humans are particularly good at: Interfacing with other humans.

“The entry-level jobs that you had two to three years ago, AI can do most of them,” LaMoreaux explained to attendees at the Charter AI Summit. “So, if you’re going to convince your business leaders that you need to make this investment, then you need to be able to show the real value these individuals can bring now. And that has to be through totally different jobs.”

“Yes, it’s for all these jobs that we’re being told AI can do,” she said, but that workers would focus on the human-aspect of them.

That means entry-level developers are spending some time coding with AI tool assistance, but more time working with customers to define what it is they want from a coding project. New HR hires now work to refine responses from AI chatbots that answer a greater number of enquiries than HR workers could themselves. The entry-level positions are middle managers in their own right, acting as a go-between for the AI frontline and higher-level decision makers.

The wider trends

The past few years have seen an increasing number of layoffs across major industries. Although there are a growing number of studies which suggest that the reason these layoffs may be more “AI washing,” than AI innovation, it’s clear that AI is causing workplace changes. Entry-level positions, particularly in programming, that were once dominated by new graduates and younger workers who can then develop into positions of capabilities and authority, are being squeezed by new AI capabilities. That’s reduced the number of opportunities, which threatens to collapse the supply chain of new, experienced workers that every industry needs to continue developing and innovating.

With industry leaders like the CEO of Anthropic, Dario Amodei, claiming that up to half of entry-level jobs may vanish by 2030, and Microsoft’s head of AI saying that white-collar jobs could vanish in less than two years, there’s serious concern for many about what the future of work might look like. While those companies pushing AI advancement certainly have a strong stake in the narrative of AI godhood within the workplace, other major companies like IBM see the future of work as still intrinsically human.

Not isolated thinking

What’s encouraging for entry-level workers, and for anyone who’s felt the spectre of AI looming over their employment security, is that LaMoreaux isn’t an island of thought in this case. People in leadership positions are also taking note.

IBM CEO Arvind Krishna told CNN in October, “People are talking about either layoffs or freezing hiring, but I actually want to say that we are the opposite. I expect we are probably going to hire more people out of college over the next 12 months than we have in the past few years, so you’re going to see that.”

Others see the AI nativism of young and inexperienced new hires as one of their greatest strengths, too.

“It’s like they’re biking in the Tour de France and the rest of us still have training wheels,” said Melanie Rosenwasser, chief people officer at cloud storage platform Dropbox, at the Leading in AI summit. “Honestly, that’s how much they’re lapping us in proficiency.”

Dropbox also announced an expansion of its internship and graduate training programs by 25% in 2026 to make the most of younger workers’ capabilities when it comes to using AI.

Catering to these younger, hungry workers has been a core part of Dropbox’s strategy. For the past five years, it’s prioritized a “Virtual First” culture, which encourages and facilitates remote work, allowing it to focus on talent and capability over physical location.

While that’s not something all companies can do, it’s a real advantage for Dropbox and shows it in stark contrast to several other firms which have made a point of driving workers back into centralized offices since the pandemic. Mozilla, Hubspot, Crowdstrike, Zapier, and Spotify are all doing the same, which could give them a real competitive advantage for remote-first workers who have known little else over the past half-decade.

The uncertain future of labor

There’s an emerging dichotomy in the future of employment, and it seems increasingly split down the line between those working to develop AI and those looking to take advantage of it. Those driving AI forward the most: Anthropic, Microsoft, OpenAI, are all claiming the world of work is going to come crashing down, and even though none of them are making any profit with AI, they want the world to believe that AI is going to be everything, with no room for the human workers it’s replacing.

But those without a profit incentive to make AI everything seem to feel differently. It’s not AI that’s now generating new productivity, its experienced workers with AI. For companies like IBM and Dropbox, AI isn’t going to make work redundant; it’s going to change it, like many automation drives throughout the history of work.

Maybe the AI companies secretly know that, too. Even Anthropic is hiring human SEO experts, afterall.

The companies that see humans as the face of work for the future are making sure they have those people on hand to realize it. If the major tech firms are going to fire everyone and not hire as many skilled graduates, there are other companies more than happy to attract them without AI fear-mongering and easier employment options, like remote-first workplaces.

In a rush to automate everything, the smartest bet still seems to be on people, though the result of that dice roll still has yet to play out.

The Electronic Numerical Integrator and Computer (ENIAC) was first unveiled to the public today in 1946. Constructed and operated at the The Moore School of Electrical Engineering at the University of Pennsylvania, ENIAC became a huge milestone in computing as “the first general-purpose electronic computer.” ENIAC was massive in stature, a Goliath in power consumption, and unassailable in compute power at launch. However, in 2026, its 18,000 vacuum tube-powered performance seems laughable compared to even the lowliest throwaway consumer electronics.

ENIAC’s performance

While we can no longer marvel at ENIAC’s compute prowess, it was around 1,000x faster than its nearest rivals in the mid 1940s. ENIAC could perform around 5,000 calculations per second, allowing humans to tap into math at electronic speed for the first time.

This first general-purpose electronic computer was used to perform a variety of tasks. However, as ENIAC was funded by the U.S. military, some of its best-known compute tasks include calculating artillery trajectories.

“The ballistics calculation that previously took 12 hours on a hand calculator could be done in just 30 seconds,” notes the Penn Engineering blog. ENIAC was also used in H-bomb calculations, ballistic missile and rocket calculations, for weather prediction experiments, and more.

Programming ENIAC was done via a combination of plugboard wiring and a trio of portable function tables, each bristling with 1,200 ten-way switches. So, mapping a problem to run on ENIAC was a far from trivial task, which usually took highly trained teams several weeks, plus extensive testing, verification, and debugging.

ENIAC specifications

Though its architecture is rather different from that of a modern computer, it is interesting to look at the construction and component specs that formed the ENIAC.

In terms of its physical presence and build, an ENIAC Top Trumps card might be an ace… It featured 8,000 vacuum tubes, 70,000 resistors, 10,000 capacitors, and 500,000 soldered joints, with dedicated power lines delivering 150kW of electricity. Naturally, ENIAC was huge and heavy, too. The Penn Engineering blog says that it occupied a 30 x 50 foot room and weighed 30 tons.

Composed of 40 panels in a U-shape, some of the original ENIAC is still to be found situated on the ground floor of the Moore Building. Students nowadays sit in the shadow of this beastly relic's Cycling Unit, the Master Programmer Unit, a Function Table, an Accumulator, and Digit Trays. Surely, an inspiring presence.

ENIAC needed a lot of maintenance, with several of its vacuum tubes burning out each day. Wikipedia sources estimate it was “nonfunctional about half the time.” Though things improved over time, as engineers became more used to ENIAC’s characteristics.

ENIAC's legacy

The ENIAC was officially retired on October 2, 1955. By that time, its binary stored-program architectural successor, EDVAC, was operational. Also in the early 1950s, the UNIVAC I was introduced, and IBM broke onto the scene with its mass market systems and FORTRAN programming. Computers advanced into the IBM PC age in the early 80s, and this came about “all thanks to the ENIAC,” Penn Engineering cheekily asserts.

Today, in 1982, Intel introduced its “showstopping” 80286 processor. This 16-bit fully x86 software compatible CPU delivered some major performance and architectural advancements over the Intel 8086 and 8088, and would continue to be produced and feature in PC systems well into the 1990s.

Development of the 80286 began in 1978, the same year Intel introduced its 8086 CPU. Intel studiously completed six months of field research among customers to steer the next-gen CPU’s direction. Then, in 1982, the 80186 (an update to the 8086) and our headlining 80286 were rolled out, but only the latter would “dramatically reconceptualize the microprocessor's possibilities for personal computing,” says Intel.

The Intel 80286 design featured 134,000 transistors, and the architecture was 16-bits with 24-bits internally. It was the first x86 CPU with protected mode, a memory management unit (MMU), and was multitasking-friendly in advanced operating systems like OS/2 and Unix derivatives.

Memory support was also boosted to 16MB, from the 1MB max addressable by the older 8086 systems. The 80286 could be augmented with an optional 80287 math coprocessor, speeding up apps that benefited from fast floating point unit (FPU) calculations, like CAD, heavy-duty spreadsheets, code compilation, as well as some statistical and scientific software packages.

Compared to the 8-bit Intel 8086, the 80286 CPU also brought both impressive performance and efficiency gains. Clock-for-clock, many sources say it was 100% faster than its predecessor. However, the 286 also ran at far higher clock speeds, with Intel and chipmaking rivals like AMD boosting the 286 clock speeds up to 25 MHz eventually. A typical 8086 ran at 5 MHz, with the most potent revisions touching 10 MHz. So, eventually, 286 PCs might offer 300-500% performance gains on their 8086 ancestors.

Though it was introduced in 1982, momentum behind the 286 would increase significantly after IBM rolled out the PC/AT standard in 1984. This advanced replacement for the PC/XT would also inspire a tidal wave of clones. The PC/AT redefined the IBM PC as a flexible business workstation with a hard drive as standard, multiple 16-bit expansion slots, and a host of ‘AT’ standards, which persisted into the Pentium era and still live on in direct descendants like ATX standard components.

By May 1988, Intel’s Fab 3 proudly boasted that it had made and shipped 10 million 80286 chips. The processor continued to be used in PCs into the 1990s.

Intel's 80286: nearly a decade of x86 dominance

Intel’s next-gen 80386 processor was introduced in 1987, debuting in the Compaq Presario 386, and would quickly dominate in performance systems. However, commodity pricing of 286 systems and ‘good enough’ performance made the transition a long one. Speedy clones helped eke out some more time at the top of the popularity table for the 286.

As the major PC OS in this era was still DOS, though, much of the 386’s potential would remain untapped by apps of the day. In effect, you could say that the dominance of DOS stunted the 386’s adoption – alongside a chasm in pricing.

Intel’s intro of the more affordable 386SX would start to turn the tide. Meaning 286’s significant cost advantage would be lost in 1991-ish. Then, in 1992, Windows 3.1 helped turn the tide. This new GUI operating environment would be a key Windows release due to its soaring popularity. Win 3.1 also eliminated Real Mode (8086/8088) support, and its updated minimum requirement of a 386SX CPU finally kicked the 286 off the playing field and cemented the Wintel hegemony in place.

Louis Gerstner, the executive who engineered one of the most important corporate turnarounds in the history of the high-technology sector, died at the age of 83 on Saturday. Gerstner took control over IBM in 1993 when it was at the brink of breakup and bankruptcy, rebuilt the company into a services-led enterprise, and restored its strategic relevance by 2002. Multiple prominent high-tech leaders worked at IBM under Gertner's leadership, spreading his skills across the industry nowadays.

IBM's first CEO not from IBM

Louis Gerstner was the first IBM chief executive — and so far, the only — to be hired from outside of the company. When he took the helm in April 1993, IBM was bleeding money, and the previous CEO planned to split the company into multiple semi-independent units to make them more flexible to compete against immediate rivals without being tied to IBM's corporate requirements. Instead of dismantling the company, he did the opposite. He preserved IBM as a single integrated organization with a strong R&D division while radically changing how it operated.

The most important technical shift was a decisive move away from hardware-centric economics toward business services, systems integration, and enterprise software. Under his direction, IBM abandoned its long-standing practice of selling IBM PCs with the IBM's mainframe operating systems, and proprietary applications that its customers were slow to adopt in the 1980s, but which were quickly losing any relevance in the 1990s.

Moreover, product lines that failed to gain market traction were eliminated (e.g., IBM abandoned Token Ring LAN products), so only the fittest survived. After dropping OS/2, IBM became a neutral integrator that supported heterogeneous hardware and software environments and did not force customers into proprietary ecosystems. Furthermore, PCs ceased to be strategically important products, which set the stage for selling the PC unit to Lenovo in 2004. But while hardware was no longer the focus, IBM changed its approach to processes and supply chain discipline to make this business more flexible and stable.

As IBM was kept together, the company continued to offer complete IT solutions for various customers as it had unique pieces that others did not. At the core of IBM's complete solutions were its database software, transaction processing systems, and management tools that sat between hardware and applications, something that still encouraged customers to buy IBM hardware, but this time without unpopular products like OS/2. Furthermore, IBM also put emphasis on the Internet, enterprise networking, servers, and services; forerunners of cloud services in the 1990s.

IBM's strategic reset was paired with sweeping operational changes. Gerstner cut costs aggressively: he sold real estate and eliminated 35,000 positions from a workforce of roughly 300,000. Compensation was restructured to reflect overall corporate performance instead of divisional metrics, and management accountability shifted from annual reviews to continuous performance tracking, which dramatically affected corporate culture. Despite cuts and downsizing, IBM returned to growth in the 1990s, and in 2002 its workforce grew to 315,000 – 320,000, which is more than the company employed when Gerstner assumed leadership.

Over Gerstner's nine-year tenure, IBM's market capitalization expanded from approximately $29 billion to around $168 billion (that is after the dot com crash in 2000 and September 11, 2001). By the time he stepped down in 2002 and passed the baton to Sam Palmisano, IBM had been transformed into a unified, services-driven technology company.

Gerstner later chaired Carlyle Group, but his most important legacy remains the reinvention of IBM as an integrated enterprise built around future needs of its customers, a culture later inherited by many successful high-tech companies.

The industry mourns the passing of Louis Gerstner

A number of current high-ranking executives of American high-tech companies — including Apple's Tim Cook, AMD's Lisa Su and Mark Papermaster, Cadence's Anirudh Devgan, IBM's Arvind Krishna and Gina Rometty, Microsoft's John Thompson, and even legendary chip designer Jim Keller — served at IBM earlier in their careers during Louis Gerstner's tenure at the company.

During the Gerstner era, IBM quietly produced a significant share of today's top-tier U.S. tech leadership, particularly in semiconductors, enterprise, software, and supply chain spaces, something that very few companies in the industry can brag about. To that end, many former IBM employees mourn the death of Louis Gerstner.

"I am saddened to share that Lou Gerstner, IBM's chairman and CEO from 1993 to 2002, passed away yesterday," wrote Arvind Krishna, the current chairman and chief exec of IBM. "Lou arrived at IBM at a moment when the company's future was genuinely uncertain. The industry was changing rapidly, our business was under pressure, and there was serious debate about whether IBM should even remain whole. His leadership during that period reshaped the company. Not by looking backward, but by focusing relentlessly on what our clients would need next."

"I was privileged to learn and experience the leadership of Lou Gerstner early in my career at IBM," wrote Lisa Su, chairman and chief executive of AMD. "He was amazingly curious and insightful about technology. So honored to have had a chance to work with him. My condolences are with Lou's family and the extended IBM family."

"Yesterday, we lost Lou Gerstner, IBM's iconic and legendary CEO from 1993 to 2002," wrote Gina Rometty, the former CEO and chairman of IBM. "Lou was my very dear friend and mentor. Much will be written about Lou's immense contributions to IBM and his philanthropic efforts, but I would like to speak about Lou the person. I first met Lou in the 1990s, and admired him immediately. He was a brilliant, principled leader who led with intellect, not fear. Lou could cut through to the heart of any issue with penetrating questions. One of the most valuable things he taught me was the importance of preparation. Not long after we met, we were getting ready for a client meeting when Lou told me that he’d been reading a book, The Greatest Generation, because it included a chapter on the CEO we were going to visit. I couldn’t believe he was researching so diligently, and I thought, 'if the CEO takes time to prepare, so should I.' […]"

On December 5, 1995, IBM took the wraps off its Deep Blue prototype, a supercomputer designed to beat the world’s greatest chess players. IBM would manage to achieve its goal two years later, after a host of software and hardware revisions. In 1997, Deep Blue famously triumphed over an at-his-peak chess Grandmaster Garry Kasparov, during a rematch in New York City. The win was a turning point for IBM, who was increasingly characterized as a has-been, with a dire share price to match. It was also a cornerstone in the company's approach to computing, pivoting from mere chunks of hardware to ‘thinking systems.’

Interestingly, Deep Blue originated from work on a chess chip, which started a decade earlier at Carnegie Mellon University. That hardware research project was dubbed Deep Thought, which will tickle The Hitchhiker’s Guide to the Galaxy fans.

The first Deep Blue prototype revealed consisted of “an IBM RS/6000 workstation with 14 chess search engines as slave processors,” says the Chess Programming Wiki. According to the source, the collective chess-power this first Deep Blue incarnation had at its disposal was enough to analyze “between 3 and 5 million positions per second.”

1995: Losing versus a game running on a Pentium 90

Millions of moves per second sounds like a lot of brute force to crack a chess nut. However, it wasn’t yet enough to beat the best human players, nor even the best chess gaming computer programs of the era.

At its first outing at WCCC in 1995, Deep Blue would lose a decisive match against computer chess program Fritz running on a Pentium 90 PC. The loss showed IBM’s brute force technique couldn’t easily roll over Fritz’s well-curated opening book of game moves, positional heuristics, and chess knowledge.

Chess Grandmaster Kasparov faced Deep Blue for the first time in 1996. This time it showed it could do somewhat better – the IBM machine won Game 1 against the reigning world champ. After its promising start, the tables turned, though, with Kasparov triumphing 4-2.

1997: IBM brings moar brute force

IBM exacted its revenge in 1997, with Deep Blue victorious in a marathon 6-game rematch. Chess Programming says that the win was marginal, at 3½-2½ in favor of the machine. Some sources say that Kasparov accused IBM of cheating and demanded a rematch – an invitation that wasn’t accepted by Deep Blue, once it had grasped the headlines. IBM quotes the chess champ as grudgingly admitting, “I have to pay tribute, the computer is far stronger than anybody expected.”

The 1997 Deep Blue build was quite a significantly beefed-up build compared to the prototype specs we sketched out earlier. In this version of Deep Blue, the 1997 chess challenger was built using 30 workstation nodes of PowerPC processors controlling 16 chess chips each. IBM’s blog says this breakthrough design could “evaluate 200 million chess positions per second, achieving a processing speed of 11.38 billion floating-point operations per second. [FLOPS]”

Looking back at Deep Blue from the AI era

In 1997, we perhaps saw the first real signs of machines being able to rival the power of human thought and intuition – admittedly using a very different technique for success.

Fast-forward to the AI era, and as we approach the end of 2025, we have to comment on the fact that the AI-LLM industry is still pretty bad at chess. As the rapid pace of AI data center buildout and adoption continues, Deep Blue is a prescient reminder of where it all came from. We can only hope that there will be some RAM left over for the rest of us.

IBM CEO Arvind Krishna used an appearance on The Verge’s Decoder podcast to question whether the capital spending now underway in pursuit of AGI can ever pay for itself. Krishna said today’s figures for constructing and populating large AI data centers place the industry on a trajectory where roughly $8 trillion of cumulative commitments would require around $800 billion of annual profit simply to service the cost of capital.

The claim was tied directly to assumptions about current hardware, its depreciation, and energy, rather than any solid long-term forecasts, but it comes at a time when we’ve seen several companies one-upping one another with unprecedented, multi-year infrastructure projects.

Krishna estimated that filling a one-gigawatt AI facility with compute hardware requires around $80 billion. The issue is that deployments of this scale are moving from the drawing board and into practical planning stages, with leading AI companies proposing deployments with tens of gigawatts — and in some cases, beyond 100 gigawatts — each. Krishna said that, taken together, public and private announcements point to roughly one hundred gigawatts of currently planned capacity dedicated to AGI-class workloads.

At $80 billion per gigawatt, the total reaches $8 trillion. He tied those figures to the five-year refresh cycles common across accelerator fleets, arguing that the need to replace most of the hardware inside those data centers within that window creates a compounding effect on long-term capex requirements. He also placed the likelihood that current LLM-centric architectures reach AGI at between zero and 1% without new forms of knowledge integration.

Krishna pointed to depreciation as the part of the calculation most underappreciated by investors. AI accelerators are typically written down over five years, and he argued that the pace of architectural change means fleets must be replaced rather than extended. “You've got to use it all in five years because at that point, you've got to throw it away and refill it,” he said.

Recent financial-market criticism has centred on similar concerns. Investor Michael Burry, for example, has raised questions about whether hyperscalers can continue stretching useful-life assumptions if performance gains and model sizes force accelerated retirement of older GPUs.

The IBM chief said that ultimately, he expects generative-AI tools in their current form to drive substantial enterprise productivity, but that his concern is the relationship between the physical scale of next-gen AI infrastructure and the economics required to support it. Companies committing to these huge, multi-gigawatt campuses and compressed refresh schedules must therefore demonstrate returns that match the unprecedented capital expenditure that Krishna outlined.

IBM has detailed its most significant quantum computing advances to date, revealing new hardware and software designed to push the limits of what today’s superconducting qubits can do. The announcements, made during IBM’s Quantum Developer Conference on November 12, include a new 120-qubit chip, updates to the Qiskit software stack, and a testbed architecture for running quantum error correction in hardware. Together, the new tools represent a serious step forward on the path to fault-tolerant quantum computing.

Nighthawk expands IBM’s hardware

At the center of IBM’s near-term roadmap is the Nighthawk chip, a 120-qubit superconducting processor built to execute deeper circuits more efficiently than its predecessors. The chip moves away from IBM’s earlier “heavy-hex” qubit layout and instead uses a dense square lattice design. Each qubit connects to four neighbors via tunable couplers, for a total of 218 coupler pairs. That marks a 20% increase in inter-qubit connections over IBM’s Heron chip and reduces the number of swap gates needed to implement complex entangling operations.

IBM says this increase in qubit connectivity directly translates into larger algorithmic workloads. According to IBM, Nighthawk will support circuits with 30% greater complexity than Heron while maintaining comparable fidelity. That estimate is based on live metrics from Heron-class machines already deployed in IBM’s quantum cloud, which recently achieved two-qubit gate fidelities above 99.9% for over 50% of the tested pairs. In benchmarking terms, the chip family reached 330,000 circuit layer operations per second (CLOPS), a 65% gain over its 2024 performance. IBM expects similar or better numbers from Nighthawk once it becomes available to the public.

The new processor will play a central role in IBM’s campaign to demonstrate a verified quantum advantage, which the company now says it expects to achieve by the end of 2026. To support that claim, it has backed the formation of an open “quantum advantage tracker,” inviting third-party researchers to test candidate workloads against classical baselines. Early example circuits from partners, including Algorithmiq and the Flatiron Institute, have already been submitted, focusing on observable estimation and constrained optimization problems.

IBM’s timeline includes further performance gains beyond the current 5,000-gate target. The company expects iterative improvements to push that figure to 7,500 gates in 2026 and 10,000 by 2027, without increasing qubit count. These are incremental steps, but they align with the broader strategy IBM has laid out for gradually improving fidelity and circuit depth while using real benchmarks to validate progress against classical solvers.

Loon lays the groundwork for fault-tolerance

While Nighthawk represents IBM’s best shot at a near-term quantum advantage, the company’s ambitions rest on a longer arc toward fault-tolerant quantum systems. IBM’s engineers believe they’ll get there by the end of the decade, and this week’s preview of the “IBM Quantum Loon” test chip hints at what that system might look like.

Loon is a proof-of-concept superconducting test chip built to validate the hardware components required for scalable quantum error correction. IBM says the processor will include architectural features such as long-range inter-qubit couplers — known as “C-couplers” — designed to enable the efficient implementation of quantum low-density parity-check (qLDPC) codes.

IBM has previously demonstrated its ability to achieve 6-way qubit connections, increase layers of routing on the chip surface, and build reset gadgets that reset the qubit to ground state. “With Loon, for the first time, we test all these features together, aided by new electronic design automation (EDA) to realize more complex architectures than ever before,” says Ryan Mandelbaum, Editor in Chief of IBM Quantum.

On the control side, IBM also announced that its latest classical decoder design, implemented on an AMD FPGA, can process error syndromes in under 480 nanoseconds. That performance is roughly ten times faster than previous iterations and meets the latency threshold required for practical error correction on superconducting hardware. The company says this milestone was reached a year ahead of schedule and will form the basis of future real-time decoding logic for larger fault-tolerant systems.

IBM’s hardware roadmap calls for a series of increasingly modular systems starting in 2026. That includes “Kookaburra,” the company’s first prototype for logical qubit storage, and “Cockatoo,” a 2027 multi-chip device intended to demonstrate entanglement between separate processors. By 2029, the company expects to ship “Starling,” a 1,000-qubit system with 200 error-corrected logical qubits capable of performing more than 100 million operations per job.

Software stack matures further

In parallel with its hardware roadmap, IBM has continued expanding its Qiskit software stack to support more advanced compilation, error mitigation, and classical integration. The latest version, Qiskit 2.2, includes several technical improvements that appear designed to close the gap between theoretical algorithm design and practical execution on real hardware.

Key among those features is full support for dynamic circuits, which allow quantum programs to include mid-circuit measurements and conditional operations based on real-time results. At the conference, IBM demonstrated dynamic circuit execution involving more than 100 qubits, with real-time feedback operations and idle qubit stabilization through pulse-based techniques. According to the company, these methods produced a 25% improvement in output accuracy compared to static circuits, while reducing total gate count by over 50%.

IBM also introduced a new Qiskit tool called Samplomatic, which allows users to add custom annotations to specific regions of a quantum circuit. These annotations are compiled into templates and a new object called the samplex, which defines semantics for circuit randomization. Samplomatic integrates with a new executor primitive to enable composable and efficient error mitigation. According to IBM, applying these techniques in combination with tools like propagated noise absorption and shaded light cones allowed developers to reduce the sampling overhead of probabilistic error cancellation by a factor of 100.

IBM’s latest quantum computing updates reflect a deliberate strategy that balances incremental improvements with long-term architectural goals. The company is not alone in its pursuit of fault tolerance — Google, Intel, and IonQ have laid out their own paths to scale — but IBM’s approach is unusually comprehensive, combining chip design, fabrication, software, and system-level integration under a single roadmap.

Whether the company can hit its 2026 goal remains to be seen. Verified advantage is still a high bar, and the best classical algorithms continue to improve. But Nighthawk appears to offer a legitimate increase in accessible circuit complexity, and IBM’s move to open benchmarking suggests it is willing to let independent comparisons define that moment. On the other side of the equation, Loon offers a credible early platform for testing the essential components of fault-tolerant logic.

As the Xbox 360 turns 20, the first images showing an exclusive edition of the console, which some claim kicked off the HD gaming era, have been shared on social media. Larry Hryb, Xbox GamerTag Major Nelson, and long-time Xbox community figurehead at Microsoft, posted a quartet of photos showing his prized ‘Launch Team 05’ console. However, perhaps sacrilegiously, Hryb admits this custom personalized machine has never ever been powered on. We hope it doesn’t have the Red Ring of Death (RRoD)…

Larry Hryb moved to Unity Technologies in 2023 and currently works as the firm’s Director of Community.

Expect official festivities to mark the 20^th anniversary of the Xbox 360 launch on November 22. If we’re lucky, Microsoft will have some classic 360 titles, game bundles, and more in promotions. If we’re very lucky, the firm might even have some ‘anniversary’ hardware prepared for launch to appeal to fans of the 2005 classic design.

HD(MI) era claims on shaky ground

The Xbox 360 was indeed an important console gaming milestone, beyond the HD-era claims of Major Nelson. However, even on this precise point, one could argue that the Sony PlayStation 3 was the HD-era pioneer as its 2006 release was the first major console to come packing HDMI at launch. It wouldn’t be until 2007 that Microsoft added HDMI to the new Xbox 360 Elite edition, and it subsequently trickled down to later revisions. The PS3 also famously included Blu-Ray, a huge advantage it held over Xbox.

While HD-era claims might ring a little hollow, it is hard to deny the importance of other Xbox 360-led movements. It could be credited with pioneering online console gaming as we know it, with the popularisation of Xbox Live and its achievement systems. In a similar always-connected vein, the 360 popularized digital downloads, DLC, and the era of consoles being entertainment hubs (supporting services like Netflix and YouTube).

An architectural escapade

Though it might have been of little interest to gamers at the time, one of the most fascinating things about the Xbox 360 from a technological standpoint was its architecture. The designers went on quite a side quest if you consider the console’s generational timeline.

The original Xbox (2001) was somewhat PC-like, with its Intel Pentium III CPU and an Nvidia GPU as its key performance components. Similarly, the Xbox One (2015) used PC-like components as the thrusters behind its gaming performance. However, the Xbox 360 (2005) was based on a triple-core IBM PowerPC CPU, with ATI GPU graphics acceleration.

Nevertheless, Microsoft ensured it supported some level of original Xbox backwards compatibility, via built-in emulation. The 360’s muscle was a significant step above the original, moving from a single CPU core to triple, with an advanced GPU featuring unified shaders and embedded DRAM. There was a huge jump in system RAM (from 64GB DDR to 512GB GDDR3), too. Its complex, lesser-known architecture would make it a little trickier for devs to cross-develop games and learn how to optimize for the 360. But the same was true of Sony’s PlayStation 3 and its notorious asymmetric Cell processor, a collaborative work between Sony, IBM, and Toshiba.

Kinect-ic energy

Kinect, which debuted in the Xbox 360’s reign (2009), could also have been a killer innovation for Microsoft. At launch, gamers were mesmerized by its possibilities, and a record-breaking eight million units were sold in its first two months.

Sadly, this controller-free gaming experience didn’t live up to its potential. That was partly due to its innovative motion tracking hardware being a little too laggy and inaccurate for gaming in some genres. Compounding Microsoft’s misstep on the hardware side was the limited supporting game library, centered around party games and fitness apps.

By the time of the Xbox One (2013), Microsoft’s efforts to make motion controllers a standard, with the Kinect 2.0 forcibly bundled at launch, weren’t greeted happily by console gamers. The accessory was eventually unbundled to make the Xbox One more competitive with the PS4, and even the dedicated port was removed in later models. By then, the significant damage to Xbox fandom and sales seems to have been done.

Compaq took the wraps off its first product in November 1982, revealing the computing world's first true IBM PC clone, and an all-in-one portable model at that. The Compaq Portable featured a legally reverse-engineered IBM BIOS and delivered near 100% compatibility with those all-important IBM PC applications.

Kickstarting the IBM PC Clone business

Before Compaq splash-landed on the PC scene, the market was dominated by IBM and a rival group of PC work-a-like machines with varying degrees of compatibility. These ‘almost compatibles’ would use the same Intel 8088 as the incumbent IBM, and would run a version of DOS. However, the adoption of these challenger products was held back by incompatibility wrinkles and their makers being in precarious disputes with IBM over copyright claims.

Key features of the Compaq Portable

Compaq negotiated these sticky hurdles with its reverse-engineered BIOS, using zero IBM code, heading off legal disputes. The rest of the Compaq Portable, like the IBM PC it copied, was basically off-the-shelf hardware components. More importantly, the reverse-engineered BIOS did such a good job that it could be marketed with claims of 100% compatibility.

Meanwhile, Compaq’s luggable also came with Compaq DOS. This OS was basically a version of MS-DOS that could run a standalone BASIC interpreter without IBM Cassette BASIC being present in the system ROMs.

Compaq Portable hardware

Compaq’s groundbreaking Portable could easily break your foot if dropped. Weighing in at 28 pounds, the device’s keyboard popped off to reveal the built-in screen and removable disk drives. The first model featured a single half-height 5.25-inch 360KB diskette drive and was priced at $2,995 (~$9,500 today). Though there was a dual-drive model for an extra $600-ish. Later revisions would offer hard disk options.

Specs:

• CPU: Intel 8088, 4.77 MHz
• RAM: 128KB, 640KB max
• Display: 9-inch monochrome green monitor
• Video: Support for CGA graphics with 80 X 25 character display
• Storage: Two 320K 5-1/4" disk drives, 10MB HDDs in later revisions
• Ports: 1 parallel port (via expansion card)
• OS: Compaq-DOS 1.12 to 2.00

Legacy of this ‘luggable’

The Compaq Portable was a massive success; it truly kick-started the PC clone industry and sparked an era of PC enthusiasts and DIYers that still thrives today.

This portable PC would break business records for three years running. “Compaq sold 53,000 units in the first year with a total of $111 million in revenue, an American Business record,” notes our source. The youthful computer company would continue to break US/industry records in years two and three.

Of course, Compaq’s success would inspire others to join in the PC-clone making feast, lighting the way to hundreds of millions of dollars in annual revenue.

IBM copied back

It would take IBM almost a year, after the Compaq Portable hit the market, to prepare a true rival to the popular luggable. IBM’s Portable Personal Computer arrived in February 1984, at a price of $4,225 (~$12,200 today).

For the money, you got the assurance of the IBM brand, and ‘no one got fired for buying IBM.’ It still had the same Intel 8088 at 4.77 MHz, though, plus the same storage and monitor/CGA video configuration – and weight. However, it came with 256KB of RAM by default.

Surely, IBM’s embattled sales force welcomed even a more expensive product to show potential customers.

Compaq's star shone bright, then HP snuffed it out

Despite being announced in November 1982, Compaq wouldn’t ship any of its Portables until March 1993. However, it still set the stage for the PC industry revolution ahead, and inspired customers with its bold first product being a ‘portable.’

Sadly, the Compaq brand was retired in 2013 in North America, about a decade after the firm was acquired by HP in what turned out to be a $25 billion catch-and-kill operation.

Hot on the heels of Google's breakthrough in the practical application of quantum computing, IBM is now poised to announce a quantum leap of its own. According to a Reuters report, a team of IBM researchers will publish a paper on Monday, October 27, detailing how they performed quantum error correction on standard AMD chips. That should smooth one of the major roadblocks to the practical usability of quantum computers, namely, result accuracy.

The error-correction algorithm reportedly not only runs in real time but also runs 10x faster than necessary atop AMD FPGA chips. This latest development is likely the result of the collaboration with AMD that IBM announced at the end of August, one that sent AMD shares rising sharply at the time.

Reuters quotes IBM's director of research, Jay Gambetta, as saying this work with the freshly minted algorithm was completed a year ahead of schedule. This bit of news should be welcome to enthusiasts and investors alike, as it could push forward the schedule of IBM's Starling large-scale quantum computer, originally set for 2029.

FPGAs are Field Programmable chips, meaning their internal structure can be reconfigured via software. They trade general-purpose usability and raw performance for the ability to run highly specialized tasks efficiently. They're most everywhere in computing, but you're bound to have heard of them in the consumer space inside vintage console, arcade, and PC emulators.

As for the software itself, it's almost certainly the Relay-BP (Relay Belief Propagation) algorithm, first published in a paper in June. IBM then proudly announced in August that its quantum research team had achieved good results running it on FPGAs, calling it the only quantum LDPC (Low-Density Parity-Check) error correction algorithm that "is not only flexible and compact, but also faster and more accurate than all known alternative methods."

Error correction is one of the key elements in making a usable quantum computer. As an oversimplification, quantum computers can run a highly limited set of programs. Still, they can do so considering every possible input at once, thanks to its qubits being 0 and 1 simultaneously. However, reading the result is extremely complicated, as altering it would not change the result, and the result is not deterministic anyway; think of 2+2 = 3.999 or 4.001. Reducing the margin of error is a cornerstone of practicality, and both IBM and Google have made great progress in this area.

HDDs aren’t dead yet, and thus today we can celebrate the aging spinning rust data storage medium’s 69^th birthday. On this day in 1956, IBM announced the RAMAC 350 Disk Storage Unit, packing an awe-inspiring 3.75MB of data across 50 magnetic platters, each spanning 24-inches in diameter and spinning at 1,200 RPM. This magnetic disk-based storage, which earned the nickname the ‘baloney slicer,’ was designed to partner with IBM’s RAMAC 305 mainframe vacuum-tube based computer system.

RAMAC is short for Random Access Method of Accounting and Control. The IBM RAMAC 305 computer system paired with the 350 disk, for its high speed random access to information, and delivery of “exponentially faster” performance and efficiency vs prior storage technologies.

This innovation was revolutionary for businesses, who often used on systems reliant on punch cards, for example. RAMAC 350 would allow businesses to get rid of their old tub files full of punch cards, and many human filing operatives. IBM’s historical blog post about the RAMAC notes the device became the “progenitor of all hard disk drives… paved the way for the invention of the relational database… and ultimately laid the groundwork for everything from spaceflight and ATMs to search engines and e-commerce.”

In some of the old images and videos showing off the RAMAC 350 you can see operators feeding it punch cards. The 3.75MB of storage this direct hard disk ancestor put on random-access tap was equivalent to approximately 62,500 punch cards – or about five million characters of text.

IBM refined the RAMAC 350 by working on the seek speeds of the multi-arm read/write heads across all its huge platters. Only after it achieved 800ms data seeking perfromance did the first of these disk storage units get rolled out to customers.

Though its digital data storage capacity seems tiny when compared to modern technologies, the RAMAC 350 was incredibly bulky. So indeed, when it was rolled out, it actually had to be rolled around like a piano.

Computer enthusiasts are always looking to push the boundaries of technology. This urge seems to apply mainly to the latest hardware and software, but some, like Bob Pony, also have a soft spot for ancient technology. A case in point is provided by Pony’s recent escapade, where he recounts successfully installing Windows 8.1 on a system restricted by the ancient EGA graphics standard. Not a simple task. And the result, though somewhat functional, wasn't aesthetically pleasing.

EGA technology recap

It is worth providing some context regarding EGA and outlining its key features. IBM introduced this PC graphics mode in October 1984, and its initials are an acronym for Enhanced Graphics Adapter. The first EGA graphics cards (I keep stopping myself from typing EVGA by accident) originated from IBM, and they were heralded as the successor to the even more restrictive Monochrome Display Adaptor (MDA) and Color Graphics Adaptor (CGA) standards. EGA would be eclipsed by the perhaps better-known VGA standard in 1987.

An unscaled EGA screen on a modern monitor would cover just a small patch of your display. Standard modes available from this 40-year-old graphics adaptor maxed out at just 640 × 350 pixels, using 16 colors from a paltry palette of 64. Later in its life, third-party EGA ISA graphics card makers would boost the resolution available to up to 800 x 600 pixels.

Pony leaps hurdles in emulator

According to the diminutive equine tech enthusiast, getting his emulated EGA system working, with virtualized era-appropriate parts, wasn’t quick. In the video above, you will notice that some of the setup process was sped up 5,300%. Pony blamed the sluggish performance on an ‘Intel Generic CPU’ selected in the PCBox emulator.

Boot screens are mainly absent from the startup process, a quirk of the emulated system. However, we have some really awful-looking color-clashing setup screens ahead of the awful-looking Windows 8.X UI.

SuperEGA?

You may also notice that the video card emulated was one that expanded upon IBM’s standard by boosting VRAM from 64KB to 256KB, among other tweaks, according to a DOS Days article. The upshot was that this Chips & Technologies Inc. design, which debuted in 1987 (the same year VGA arrived), could address up to 800 x 600 pixels in 16 colors. Wowsers.

Despite my recitation of those specs, when we pay attention to Pony’s video of the Windows 8.1 installation and setup, you can see that the OS lists the graphics adapter mode as having 256MB, not KB, of memory. Moreover, it allows for a 640 x 480 pixels, True Color (32-bit) display mode at 64 Hz. Something may be wrong with the OS’s display hardware reporting…

Regardless, the specs appear to still be well below the official Windows 9 requirements published by Microsoft in 2012. For example, the OS requires a display with a minimum resolution of 1,366 x 768 pixels, powered by an adapter with DirectX 9 support and a WDDM driver. Such specs only became mainstream multiple eras beyond EGA’s heyday.

IBM has shared its roadmap to deliver the “world's first large-scale, fault-tolerant quantum computer.” It claims that, due to be delivered to clients in 2029, IBM Starling will also be 20,000 times more powerful than today’s leading quantum computers. Furthermore, IBM says that to merely represent the computational state of Starling “would require the memory of more than a quindecillion (10⁴⁸) of the world's most powerful supercomputers.” However, we are used to rather lofty claims in the world of Quantum Computing, so let’s take a closer look.

On its newly published roadmap, IBM has set out several milestones, which will be powered by a handful of quantum computers and processor architectures ahead of the arrival of Starling. In 2026, we will see the first tantalizing demonstration of what IBM calls ‘quantum advantage.’ This is defined as the milestone where classical computers start to be outclassed by quantum computers in practical computing applications.

IBM Quantum Loon is set to debut later this year alongside the first Nighthawk chip, so we will assume that it will be the vehicle to demonstrate this first glimpse at quantum advantage. According to IBM, this will be a platform designed to test architecture components for its new quantum low-density parity check (qLDPC) code.

IBM Quantum Kookaburra will be passed the baton sometime in 2026, says IBM. This will feature the firm's first modular processor designed to store and process encoded information. Innovations in this design will be key to scaling fault-tolerant systems beyond a single chip.

Penultimately, IBM Quantum Cockatoo is expected to roll out in 2027. IBM’s press release says that this architecture “will link quantum chips together like nodes in a larger system, avoiding the need to build impractically large chip.” That is another important nod to scalability that it hopes to put into practice by leveraging the entanglement of component modules.

All the above milestones are hoped to culminate in Starling in 2029. They bring together testing and demonstrations based on two new technical papers IBM published today, providing background detail to its proposed large-scale, fault-tolerant architecture, and direction for its roadmap.

You read the astounding claims for this hardware innovation in the intro. But for more perspective, it is claimed that Starling will be capable of “running 100 million quantum operations using 200 logical qubits.”

When it arrives, Starling will “solve real-world challenges and unlock immense possibilities for business,” indicates Arvind Krishna, Chairman and CEO, IBM. Behind it there will be an architecture that can run “hundreds or thousands of logical qubits could run hundreds of millions to billions of operations,” reckons IBM. The most obvious beneficiaries of this computing power will include organizations involved in such as drug development, materials discovery, chemistry, and optimization.

IBM Starling isn’t quite the endpoint of the IBM Quantum roadmap, as published today. Its second-gen fault-tolerant quantum computing ISA will be Blue Jay. When this arrives, the computing platform may have scaled up to an astounding 1 billion gates and 2,000 logical qubits. Blue Jay isn’t expected to be here until 2033+.

Quantum advantage vs quantum supremacy

In a quite unexpected turn of events, it is claimed that OpenAI’s ChatGPT “got absolutely wrecked on the beginner level” while playing Atari Chess. Citrix Architecture and Delivery specialist, Robert Jr. Caruso, discovered this gameplay skill anomaly over the weekend. Caruso pitted the 1979 Atari Chess title, played within an emulator for the 1977 Atari 2600 console gaming system, against the might of ChatGPT 4o.

A little computer vs Chess history

The concept of computing performance being graded by chess-playing ability is one firmly embedded in nerd lore. Chess computer games were popular from the early days of consoles and home computing, with computing and chess enthusiasts going to great lengths to grade available chess-engine abilities versus a Grandmaster of ‘the game of kings.’

IBM’s Deep Blue supercomputer made history in 1997 when it defeated Garry Kasparov, the reigning world chess champion at the time. Instrumental to its victory, Deep Blue leveraged brute force techniques and evaluated 200 million possible chess moves per second. However, Kasparov struck back after losing the first of the scheduled six chess matches, with the eventual score of 4-2 in his favor.

In 2025, the Deep Blue supercomputer’s processing power of approximately 11.4 GFLOPS seems puny compared to even entry-level modern processors. So, one might expect an Atari Chess running in an almost 48-year-old games console emulation instance to easily be beaten by ChatGPT…

ChatGPT humbled by an Atari 2600

IBM has introduced the z17, its newest mainframe system, designed for mission-critical business transactions with advanced security capabilities enhanced with AI. The system is based on the Telum II processor that offers both 70% higher general-purpose performance over its predecessor as well as 50% improved AI capabilities. For those who need even higher AI performance, IBM offers to install additional Spyre accelerators. 

IBM's Telum II processor is the heart of the company's new z17 mainframe. The Telum II CPU features eight advanced cores operating at 5.5 GHz, featuring enhanced branch prediction, store writeback, and address translation. The chip is equipped with 36MB of L2 cache, a 40% increase compared to the earlier version. It offers support for virtual L3 and L4 cache levels, expanding available cache to 360 MB and 2.88 GB, respectively. Additionally, Telum II integrates a data processing unit (DPU) to accelerate transactional workloads, which the company says increases overall system responsiveness. The chip is manufactured using Samsung’s 5HPP fabrication process and contains 43 billion transistors. 

However, the Telum II does not only boast enhanced performance. A central element of this processor is its upgraded AI unit, which delivers four times the compute capability of the previous generation, reaching 24 trillion operations per second with INT8 data precision. Perhaps, 24 TOPS wasn't very impressive. However, the NPU is designed for mission-critical time-sensitive application that supports ensemble AI methods (traditional machine learning with a large-language model) to detect suspicious activities and fraud attempts. 

It should be noted that every AI unit within a processor drawer can accept tasks from any of the CPU cores. This ensures even distribution of processing demands and enables the full use of the available 192 trillion operations per second per drawer when all accelerators are active. 

IBM understands that some workloads will require more AI performance. Hence, alongside its Telum II, IBM unveiled the Spyre AI accelerator card with a PCIe interface. This 26-billion transistor processor packs 32 AI cores and features an architecture that closely resembles that of the AI accelerator architecture found in Telum II and, therefore, can be used to dynamically expand AI capabilities and performance of z17 drawers. 

"The industry is quickly learning that AI will only be as valuable as the infrastructure it runs on," said Ross Mauri, general manager of IBM Z and LinuxONE, IBM. "With z17, we are bringing AI to the core of the enterprise with the software, processing power, and storage to make AI operational quickly. Additionally, organizations can put their vast, untapped stores of enterprise data to work with AI in a secured, cost-effective way." 

To support AI workloads at the system level, IBM intends to introduce its z/OS 3.2 in Q3 2025, an updated version of its mainframe operating system. The new OS is designed to work with hardware acceleration and supports NoSQL and hybrid cloud data. 

Traditionally, for IBM's z mainframes, the new z17 features robust security capabilities, including a new tool called IBM Vault, originally developed by HashiCorp to handle credentials, keys, and tokens across hybrid environments. 

The system also includes hardware-level support for data classification and anomaly detection using the inference capabilities of the Telum II CPU. 

As for storage, IBM's z17 will use the company's IBM DS8000 Gen10 system, which is designed to support high-speed transactions, availability, and scalability for mission-critical operations. 

The IBM z17 will be available starting June 18, 2025, with the Spyre Accelerator arriving later in the year.

IBM is cutting thousands of jobs across multiple locations in the U.S., and its Cloud Classic unit hit especially hard, reports The Register. The company has not publicly acknowledged these layoffs, but insiders suggested to The Register it is part of an ongoing effort to restructure and shift jobs offshore, particularly to India. 

The report estimates that about 9,000 positions may be at risk, including a quarter of the Cloud Classic group and 10% of the Cloud group, which is a separate business unit. The job cuts are happening in cities like Dallas, New York, Raleigh, and various locations in California. Employees from several departments, including consulting, cloud infrastructure, corporate social responsibility, internal IT, and sales, have been affected. Some learned of their termination through individual notifications, while others heard about it in internal meetings. 

IBM's Classic Cloud is the company's original cloud infrastructure platform, formerly known as SoftLayer, which IBM acquired in 2013. This platform provides a range of services, including bare metal servers, virtual servers, storage, and networking solutions, all operating within a traditional cloud environment. While IBM continues to support and maintain its Cloud Classic infrastructure, the company has also introduced a more advanced cloud environment called IBM Cloud VPC (Virtual Private Cloud). This platform offers improved hardware, increased network performance (200 Gbps vs 25 Gbps), greater flexibility in resource management, and enhanced security features compared to the Classic. It is reasonable to expect IBM's Classic Cloud customers to shift to the Cloud VPC, which makes downsizing the unit logical. 

The company is making it difficult to determine how many people work in the Cloud Classic division, but The Register's sources indicate an aggressive push to relocate jobs overseas. For example, IBM has significantly more open roles in India than in the U.S., which reinforces suggestions that much of the work is being outsourced. 

The layoffs extend beyond Cloud Classic, though. IBM recently cut positions in its marketing and communications department, as revealed in an internal meeting led by a senior executive. It also cut some 10% of staff in the Cloud group, as noted above. 

IBM has been using multiple tactics to reduce its workforce, including official layoffs labeled as 'Resource Actions,' as well as policies that encourage employees to leave voluntarily. One such policy is a new requirement for workers to be physically present in offices at least three days a week, with badge swipes being tracked. Only medical exemptions are allowed, but even those are reportedly discouraged by the middle management, according to the report. Also, instead of laying workers off, IBM asks them to sign a separation agreement, which reduces the company's risks. 

The Register's sources suggest that IBM's restructuring is far from over. The company is expected to continue layoffs as it chases acquisitions and phases out roles deemed obsolete or better suited for offshore teams. Employees remaining after this round of cuts are bracing for further reductions as IBM shifts its workforce strategy.

Tech giant IBM secured a patent from the U.S. Patent and Trademark Office on its technology for transporting microparticles using a 4D-printed smart material. According to the patent, these smart materials can use shape-memory alloys or polymers that respond to external forces like temperature, light, magnetism, or electrical currents.

After being deformed, the smart materials return to their original shape, allowing the researchers to induce movement in them and use them to transport minute-sized particles that would be difficult or impossible to transport using traditional delivery methods.

The user must initially set the delivery path and its environmental conditions and note the item's size, shape, weight, and composition to be delivered. Once completed, the machine learning algorithm applies the proper stimulus to move the material. This could be heat or light that causes one part or the other of the 4D material to respond, generating an action that results in an equal but opposite reaction.

Aside from following the user's initial path, IBM’s machine language monitors the 4D-printed smart material for any deviations or blockages. It will resolve the situation, allowing the operation to proceed with little human intervention. All external stimuli are removed when it reaches its destination, allowing the smart material to deliver its payload.

This design allows for the delivery of microparticles between 1 and 100 microns in diameter. Furthermore, its different control methods mean it can travel through various media, making it useful for medical and industrial applications. For example, doctors and medical technologists could use this technique to deliver drugs to specific cells via the blood or the gastrointestinal tract. It could also be used for miniature electronics manufacturing and perhaps introduce a new semiconductor manufacturing method.

4D printing builds upon 3D printing technology, wherein the filament used for printing reacts to external stimuli. Researchers can then use this to generate movement, much like how a single-celled organism can move by using chemical reactions within its cell membrane.

GlobalFoundries and IBM have resolved all their legal disputes, including the ongoing lawsuits over contract violations, trade secrets, and intellectual property issues. The two companies signed a confidential settlement agreement, opening the door for future collaboration.

IBM and GlobalFoundries filed multiple lawsuits against each other. The lawsuits span from breach of contract obligations by GlobalFoundries to intellectual property usage by IBM. The conflict traces back to 2015 when IBM sold its semiconductor manufacturing business to GlobalFoundries. As part of the deal, IBM agreed to pay $1.5 billion to GlobalFoundries to take over its microelectronics operations and would continue developing advanced process technologies for IBM's processors for mainframes and other applications.

However, GlobalFoundries ceased to develop advanced production nodes in 2018 as it did not have enough high-profile clients to justify multi-billion investments. As a result, it did not have a 7nm-class process technology to make IBM's Z processors meet its partner's needs. As a result, IBM alleged that GlobalFoundries failed to deliver on its promises in 2021. IBM claimed that the semiconductor manufacturer left IBM without high-performance processors necessary for mainframes and sought compensation for damages and negative impact on its business.

In 2023, GlobalFoundries filed its lawsuit, accusing IBM of disclosing sensitive intellectual property to third parties, including Intel and Rapidus. The IP was related to next-generation process technologies and was developed together with GlobalFoundries, so according to the company, IBM had no right to share it after selling its microelectronics unit. The chipmaker argued that IBM could profit from licensing technologies it no longer owned by disclosing the IP.

After years of conflict, the two companies announced a settlement this week. While the terms of the agreement remain confidential, both IBM and GlobalFoundries expressed a desire to move forward and explore potential areas of collaboration.

"We are pleased to have reached a positive resolution with IBM, and we look forward to new opportunities to build upon our long-standing partnership to further strengthen the semiconductor industry," said Dr. Thomas Caulfield, president and CEO of GF.

"Resolving these disputes is a significant step forward for our companies and will allow us to both focus on future innovations that will benefit our organizations and customers," said Arvind Krishna, Chairman and CEO of IBM.

Researchers from IBM, IMEC, Samsung, and TSMC will present their latest work on vertically-stacked complementary field-effect transistors (CFETs) at the upcoming International Electron Devices Meeting (IEDM) in December 2024, reports eeNewsEurope. CFET is usually seen as a successor to gate-all-around transistors that will enable future technology scaling, but the industry has yet to adopt GAA FETs for mass production.

The idea of CFETs, which stack n-type and p-type transistors on top of each other, was first proposed by the IMEC research institute in 2018. Even today, the actual implementation of CFET is still broadly in the field of research. According to IMEC's own roadmap, CFETs might reach widespread production by the A5 node, projected for around 2032 if everything goes well. Nonetheless, companies like Intel and TSMC began to demonstrate their advances in the field of CFETs in recent years, so it makes sense to take a look at what the IEDM brings.

TSMC will discuss its development of a monolithic CFET inverter on a 48nm gate pitch, equivalent to a 5nm process. The inverter features stacked n-type and p-type nanosheet transistors with backside contacts and achieves a voltage transfer up to 1.2V and a subthreshold slope between 74 and 76mV/V for both transistor types. Although this marks a significant milestone, TSMC acknowledges that the technology is not ready for commercial production at present.

Key innovations of TSMC's design include a vertical drain-side local interconnect, a backside metalized drain (BMD), and a backside gate via (BVG), which collectively improve signal routing and optimize power, performance, and area (PPA).

Technically, this architecture provides a pathway for continued advancements in performance and power efficiency, as well as transistor density increases in the coming years. Still, TSMC's CFET advancements are in the lab and it will take years before they reach the company's fabs.

IBM Research and Samsung will present a 'Monolithic Stacked FET' that features a stepped channel design where lower channels are wider than upper ones, which reduces stack height and mitigates challenges associated with high aspect ratios. This research also covers isolation techniques for channels and source/drain areas, along with the use of dual work function metal. Details about metal or gate pitch will be revealed at the conference.

IMEC will present its work on a 'Double-Row CFET' designed to further scale CFETs both vertically and horizontally. IMEC believes that such transistor design could become viable at the 7a-class (7 angstroms) fabrication process, which is six or seven generations away. Interestingly, the 'Double-Row CFET' does not feature direct backside power contacts and they are explored with a 60nm gate pitch, similar to a 7nm node.

While the papers to be presented at the conference indicate that significant progress has been made in the CFET technology, such transistors are years away from mass production as challenges related to manufacturing complexity must still be overcome.

The IEDM conference will be held from December 7-11, 2024, in San Francisco, with recorded presentations accessible online afterward.

IBM has announced its next-generation Telum II processor with a built-in AI accelerator for next-generation IBM Z mainframes that can handle both mission-critical tasks and AI workloads. The new processor can potentially improve performance "by up to 70% across key system components," compared to the original Telum, released in 2021, according to an email we received from IBM.

The Telum II processor packs eight high-performance cores with improved branch prediction, store writeback, and address translation operating at 5.5GHz as well as 36MB of L2 cache, a 40% increase over its predecessor. The CPU also supports virtual L3 and L4 caches expanding to 360MB and 2.88GB, respectively. A key feature of Telum II is its improved AI accelerator, which delivers four times the computational power of its predecessor, reaching 24 trillion operations per second (TOPS) with INT8 precision. The accelerator's architecture is optimized for handling AI workloads in real time with low latency. In addition, Telum II has a built-in DPU for faster transaction processing. Telum II is made on Samsung's 5HPP process technology and contains 43 billion transistors.

System-level improvements in Telum II allow each AI accelerator within a processor drawer to receive tasks from any of the eight cores, ensuring balanced workloads and maximizing the available 192 TOPS per drawer across all accelerators when fully configured. 

In addition to Telum II, IBM introduced its new Spyre AI accelerator add-in-card developed in collaboration with IBM Research and IBM. This processor contains 32 AI accelerator cores and shares architectural similarities with the AI accelerator in Telum II. The Spyre Accelerator can be integrated into the I/O subsystem of IBM Z through PCIe connections to boost the system's AI processing power. Spyre packs 26 billion transistors and is made on Samsung's 5LPE production node.

Both the Telum II processor and the Spyre Accelerator are designed to support ensemble AI methods, which involve using multiple AI models to improve the accuracy and performance of tasks. An example of this is in fraud detection, where combining traditional neural networks with large language models (LLMs) can significantly enhance the detection of suspicious activities, according to IBM.

Both the Telum II processor and Spyre Accelerator will be available in 2025, though IBM does not specify whether it will be early in the year or late in the year.

In a virtual meeting this morning, employees at IBM's China-based research and development department were told of the impending closure of the regional operations. The current China-based R&D and testing functions will be moved to other overseas facilities, they were told. According to a Wall Street Journal report on the news, citing people who had attended the virtual meeting, the China function closure will affect over 1,000 people.

Readers will likely know the growing geopolitical tensions between the U.S. and China and their respective tech firms. Trade and equipment sanctions and stories about getting around these barriers are often in our news. However, IBM did not mention geopolitics when explaining its decision to employees.

The executive who hosted the virtual meeting, Jack Hergenrother, instead pointed at IBM's declining infrastructure business as the root cause behind the firm's China exodus. This bad news took some IBMers by surprise. The WSJ reports a swell of optimism at IBM China recently, with talk of the firm benefitting from its cloud computing and AI expertise and the current enthusiasm for such products. Nevertheless, improved competition from domestic suppliers and government directives such as Document 79, colloquially known as 'Delete America,' seems to have taken a heavy toll on the company.

Pondering over IBM's yearly revenue charts shared by the source makes the firm's China operations look unsustainable. Over the last ten years, Big Blue has consistently made less and less revenue in China. There was a slight rise in revenue in the post-Covid era, but in 2022, China's revenue was down 22.7%, and it fell a further 19.6% in 2023. Meanwhile, IBM's global revenue has seen positive growth.

IBM's China R&D operations are scattered across several major cities in China, including Beijing and Shanghai, and the source report suggests that they will all be closing, resulting in 1,000+ job losses. The WSJ hints that the staff may be able to continue their work for Big Blue by telling some of the employees that it is looking to expand R&D in other regions, such as in Bengaluru, India. With the complications involved, we don't think such a seismic change will appeal to many IBMers in China.

It isn't just foreign-owned businesses that have recently had financial troubles in China. Last December, we reported on a record number of Chinese chip-related companies shutting down during 2023 – around 30 a day on average throughout the year. This summer, a major Chinese semiconductor company went bankrupt, too, with billions in investments down the drain. And remember, this is all happening while markets are tech and AI are crazy worldwide. However, some well-placed Chinese firms are thriving, with companies like SMIC thriving as the chip war intensifies.

A transformative transistorized milestone in the history of computing could be yours, as an IBM 7090 Mainframe computer system has gone up for auction at Christie’s. Before the arrival of the IBM 7090, commercially available computers relied on valves rather than transistors, and this machine is said to have delivered a remarkable speed, efficiency, and reliability boost compared to its predecessor due to embracing the newest solid-state technology.

This auction lot is an extensive collection of IBM tech gear, cutting edge in 1959, and you would need a sizeable spare room or garage to house it all. Christie’s says the hardware on auction is from the Paul G. Allen (Microsoft co-founder) Collection, and he acquired it in 2017 from a ‘Weapons Research Establishment’ in South Australia. The mainframe is currently in Seattle, and the guide price is $40,000 - $60,000, with 19 days left of the auction period. Purchasing an IBM 7070 new, back in the 1950s, was a much bigger investment, at $813,000.

Despite the move away from vacuum tube technology, the IBM 7070 was still a hulking beast. Capable of processing about 229,000 instructions per second, the machine used approximately 14,000 Standard Modular System cards. These cards housed about 30,000 alloy-junction germanium transistors and 22,000 germanium diodes. Due to this bulk, an IBM 7070 system weighs over 23,000 pounds (10,430kg).

The mainframe system being sold by Christie’s includes many functional equipment and peripherals for the IBM 7070 user. According to the listing, the lucky auction winner will also end up owning:

• 1x IBM 7151 console control unit with IBM 7155 switch control console attached to side
• 1x IBM 711 card reader
• 2x IBM 7617 Data Channel Consoles
• 1x IBM 7608 power converter
• 13x IBM 729 magnetic tape units
• 1x IBM 1401 mainframe computer
• 1x IBM 7302 core storage
• 1x IBM 7606 multiplexer
• 1x IBM 7108 instruction processing unit
• 1x IBM 7109 arithmetic sequence unit
• 1x IBM 7607 I data channel
• 1x IBM 7607 II data channel
• 1x IBM 7618 power control
• 1x IBM 1403 printer
• 1x IBM 1402 card read punch
• 1x IBM 716 printer

The lot also includes a trolley of instruction manuals, many archival boxes of punched cards, three boxes of archival folders of user manuals, and twelve boxes of printouts.

What you would do with a hulking mainframe system like this in 2024 is harder to fathom. We mentioned that the IBM 7070 up for auction was used in some weapons research role. They were also positioned as useful for research fields spanning aerospace engineering, weather forecasting, and nuclear sciences.

However, in 2024, the smartphone in your pocket or a humble Raspberry Pi will comprehensively outgun this type of machine in terms of processing power. Thus, it is probably destined to be bought up by a museum, educational institution, or exhibition space. It might also be a good purchase for TV/Movie studios for some historical or retro-science scenes.

Even at the upper limit of the guide price, it would represent great value per pound. If you win this auction, please get in touch with us and tell us what you intend to do with it.

IBM has ambitions to take the lead in quantum computing, with a new governmental partnership inbound to make this a reality. Japanese news outlet Nikkei reports on a leaked joint effort by IBM and Japan's National Institute of Advanced Industrial Science and Technology (AIST) that seeks to produce a quantum computer containing 10,000 qubits by 2029, vastly outclassing today's class-leading 133-qubit machines. 

Quantum computing has been a major focus of IBM for a few years now, and this newest step forward is a notable one. The 10,000 qubit machine explodes past IBM's current quantum roadmap, which doesn't even reach 2,000 qubits in commercial products until 2033 and beyond. (IBM had previously planned on a 2025 release of a 1,000 qubit computer, Condor, but the prototype has been shelved.) The goal of the 10,000-qubit machine is to run quantum calculations without a traditional supercomputer as backup, as modern 133-qubit machines often make enough mistakes to need support computers checking their work. 

IBM and AIST are set to announce the deal with a signed memorandum "in the coming days", according to Nikkei's source. The partnership has some major goals already set forth. IBM and AIST will seek to develop semiconductors and circuits that function in near-absolute zero temperatures. Quantum computers work more efficiently and correctly the closer to zero Kelvin they get, and today's largest machines have to have their qubits and chips/circuits in separate rooms or chambers, so creating components that function at extreme temperatures is a necessary step for advancing quantum research. 

AIST will leverage its patents, AI knowledge base, and connections to Japanese part-makers in the production of the forthcoming supercomputer. AIST will also help ensure future quantum supercomputers get into the hands of Japanese companies and industries, by providing training to companies and lobbying for the adoption of quantum by Japanese companies. This access to the lifeblood of Japanese industry is reportedly why IBM made the deal, the company's largest deal with a governmental industry in the quantum field.

It is important to note that much like every other part of computing, one massive number does not a great machine make. Qubit quality and efficiency increase quickly, which is why IBM has shelved recent attempts at 1,000-qubit computers in favor of their 133-qubit machines which beat 1,000-qubit prototypes in quality and efficiency. And just as traditional CPUs utilize hyper-threading and caching for better performance, quantum computing has other methods that increase its performance beyond simply boosting qubit numbers forever. After all, quantum computers become less stable at higher qubit counts, so the future of quantum will rely on smart engineering in keeping the 10,000-qubit and beyond computers of the future stable and inexpensive to run.

IBM and AIST's partnership may turn out to have a serious impact on quantum computing's growth and adoption. But today's quantum is still in its infancy, and has a long way to go before it becomes useful for consumers or professionals. IBM's 2021 quantum processor was recently out-classed by a team of researchers and a Commodore 64, proving IBM and the industry have a long road ahead of them to reach the point of true quantum utility.

Just after Computex 2024, AMD CEO Lisa Su sat down with Stratechery to conduct an extended interview about solving hard problems throughout her career— including her time at IBM and contributing to the legacy of PlayStation from both there and AMD afterward. As she notes, "I've been working on PlayStation for a long time, if you think about it. PlayStation 3, 4, 5...[like the common thread] across multiple companies, yes."

Now, even if you're familiar with the PlayStation 3 and its nature as being difficult to program thanks to its IBM PowerPC-based Cell processor, you most likely didn't know Lisa Su had any involvement with it before this week. Details are few and far between, but we did manage to find the earliest statement where pre-AMD CEO Lisa Su commented on the matter.

According to Lisa Su, then-Director of Emerging Products at IBM in 2001, "We [IBM] started with a clean sheet of paper and sat down and tried to imagine what sort of processor we'd need five years from now." The decision that IBM, Sony, and Toshiba made was to create a CPU with an extreme focus on parallelization. 

Today, that approach is fairly common through multicore CPUs, Simultaneous Multi-Threading (SMT, or Hyper-threading under Intel marketing), and even dedicated Efficiency cores, but SMT wouldn't emerge until 2002, and the first consumer multicore CPUs from AMD and Intel wouldn't be seen until 2005. And, of course, the first-ever multicore was released by IBM for workstation and server use in 2001— the same year they were planning the PS3's Cell processor.

The interviewer points out that Sony's PlayStation 3 is viewed as one of its least successful consoles, which is true. The PlayStation 3 pretty much lost the generation handily to Nintendo's cheap, casual-friendly Wii and Microsoft's less powerful but easier Xbox 360. The complexity of the architecture meant that cross-platform games didn't always perform as well as they should on PS3, though as developers (particularly first-party devs) mastered the hardware, it did result in the most visually stunning console games of the latter half of the generation being Sony exclusives, like Uncharted 3 and its ilk.

Lisa said, "The Cell processor was extremely ambitious at that time, thinking about the type of parallelism it was trying to get out there. Again, I would say, from a business standpoint, it was certainly successful. As you rank things, I think history will tell you that there may be different rankings."

"My perspective is, the console era has gone through phases [...] but once you went to HD, you had tremendous increase in cost of asset creation, you had developers heavily motivated to support multiple processors, you had game engines coming along. Suddenly, no one wanted to go to the burden of differentiating on the Cell; they just wanted to run on the Cell," Su explained.

Interestingly, the seventh generation of home consoles (PlayStation 3, Xbox 360, Nintendo Wii/Wii U) also marks a shift in AMD's allegiances to console manufacturers. AMD produced graphics chips for both Nintendo and Xbox, and all three console manufacturers used the PowerPC CPU architecture. But come to the eighth-gen (PS4, XB1, Switch), both Xbox and PlayStation had switched fully to AMD-powered x86 CPU and GPU architecture. The Switch also saw Nintendo pivot to an Nvidia-powered SoC design (with Arm CPU cores) for their new hybrid console focus.

With the added context of this interview, one can't help but wonder if Lisa Su's unifying thread throughout the last three generations of PlayStation hardware isn't a coincidence. It could just be corporate happenstance, but going from a humble Product Director and Engineer working on the PS3 at IBM to Senior vice president (in 2012, CEO in 2014) at AMD, setting the future course of both PlayStation and Xbox hardware, is truly impressive. 

It's also a great win for AMD, in general, to provide the hardware behind the two biggest consoles on the market for two consecutive (and a third upcoming) console generations. No matter who wins between Sony and Microsoft and their console war, AMD wins, and that's the kind of thinking that earns you a CEO spot.

Following last week's open sourcing of MS-DOS 4 and critique, Twitter user VirtuallyFun shared their cutting-edge 16 MHz Intel i386 MS-DOS 4 install on the 1987 IBM Personal System/2, which mainly lives on today in its legacy PS/2 peripheral connectors. In its time, the IBM PS/2 could also have been paired with IBM's PC DOS or Microsoft-collab Operating System/2.

This MS-DOS 4 install wasn't done with the main Microsoft GitHub repo but instead VirtuallyFun's own dos400 branch. Dos400 forces the 4.0 version of MS-DOS and patches out issues like a bug in msload.asm that prevented booting from the hard drive. This bug was diagnosed by Michal Necasek, who readers of the previous story will recognize as the owner of OS/2 Museum and noted critic of the initial MS-DOS 4 release.

With bugs fixed through his own GitHub branch, Virtually Fun was able to share a full video demonstrating MS-DOS 4 compilation using DOSBox and Qemu. The video is seventeen minutes long and includes ongoing commentary on exact workarounds being used and bugs being addressed.

VirtuallyFun's IBM PS/2 Build and Known Specs

• Operating System: MS-DOS 4.0
• CPU: Intel i386, a 32-bit single core CPU with a maximum clock rate of 40 MHz
• GPU: An XGA-2 (Extended Graphics Array-2) Adapter
• RAM: 16 KB
• Storage: Gotek Floppy Emulator for USB

It's worth noting that VirtuallyFun, aka Neozeed, has quite a presence on both YouTube and GitHub as a retro hardware enthusiast. This includes a video testing out the rare pre-release Microsoft OS/2 build we mentioned earlier, and tons of small applications or software branches. Considering the development background, we wouldn't be surprised to see Neozeed start playing games like Alien Rampage (1996), the most visceral MS-DOS 4 action exclusive.

Or Neozeed did all of this just to see if it would work, and having satisfied their curiosity with a working MS-DOS 4 install on their very own IBM PS/2, they don't need anything else. Though considering MS-DOS 4's notorious RAM demands of up to 92 KB, maximum gaming performance is likely best with a "downgraded" operating system. Somehow, that paradigm still rings true today.

IBM is set to channel over $730 million in expanding its semiconductor packaging and testing plant in Bromont, Quebec, aiming to strengthen its semiconductor supply chain. This investment, spread over the next five years, will enhance the largest facility of its type in the region and is anticipated to generate 280 new skilled jobs, Bloomberg reports. 

The Bromont facility, occupying 800 acres approximately 50 miles east of Montreal, is an important player in semiconductor production in North America as far as its applications are concerned. It also hosts Canada’s first universal quantum computer. IBM's expansion will enable the transformation of chips into microelectronic components to occur onshore, reducing the current dependence on offshore packaging services, particularly from Taiwan. 

The expansion strategy includes an initial investment phase of C$227 million, in collaboration with IBM's partner, the MiQro Innovation Collaborative Centre. This phase, funded by C$100 million by the Canadian and Quebec governments, focuses on extending the existing plant and establishing a new research and development lab. These enhancements are crucial for adapting to the evolving demands of the semiconductor industry. 

IBM cites global supply chain disruptions and the importance of reducing reliance on Taiwan as the global foundry for everyone. In fact, East Asia accounts for 75% of global semiconductor manufacturing — including memory — a concentration that poses risks to supply continuity as experienced during recent COVID-related global challenges. The planned developments at Bromont aim to mitigate these risks by fostering a more resilient supply framework within North America. 

The expansion, of course, also closely aligns with the governmental strategy to bring semiconductor manufacturing back to the U.S.

Canada's approach, while supportive, aims not to duplicate U.S. efforts but to complement them by focusing on specialized sectors like aerospace and healthcare, the report says. This strategy indicates a selective enhancement of the semiconductor industry, designed to bolster specific high-tech fields rather than mass-producing generic components.

A paper released during the SIGBOVIK 2024 conference details an attempt to simulate the IBM ‘quantum utility’ experiment on a Commodore 64. The idea might seem preposterous - pitting a 40-year-old home computer against a device powered by 127-Qubit ‘Eagle’ quantum processing unit (QPU). However, the anonymous researcher(s) conclude that the ‘Qommodore 64’ performed faster, and more efficiently, than IBM’s pride-and-joy, while being “decently accurate on this problem.”

At the beginning of the paper, the researchers admit that their ‘Qommodore 64’ project is “a joke,” but, sadly for IBM, its proof of quantum utility was also built upon shaky foundations, and the Qommodore 64 team came up with some convincing-looking benchmarks. There was some controversy about IBM’s claims at the time, and we are reminded it took just five days for the quantum experiment to be simulated on an ordinary MacBook M1 Pro laptop. The jokey Quantum Disadvantage paper (PDF link, headlining section starts at page 199) ports this experiment to a machine packing the far more humble MOS Technology 6510 processor.

To get deep into the weeds with the quantum theory and math behind the quantum utility experiment, please follow the above PDF link. However, to summarize, the C64-based experiment uses the sparse Pauli dynamics technique developed by Beguŝić, Hejazi, and Chan to approximate the behavior of ferromagnetic materials. Famously, IBM claimed such calculations were “too difficult to perform on a classical computer to an acceptable accuracy, using the leading approximation techniques,” recalls the paper. Not quite, and as already mentioned above, an ordinary laptop can obtain similar results.

The anonymous C64 user(s) provide some interesting details of their quantum-defeating feat. Their aggressively truncated and shallow depth-first search model used just 15kB of the spacious 64kB available on the iconic Commodore machine. Meanwhile, the final code consisted of about 2,500 lines of 6502 assembly, stored on a cartridge that fitted in the C64’s expansion port. This code was handled by the mighty 1 MHz 8-bit MOS 6510 CPU. The C64 took approx 4 minutes per data point. (Testing the same code on a modern laptop achieved roughly 800μs per data point.)

In conclusion, the researcher(s) asserts that the ‘Qommodore 64’ is “faster than the quantum device datapoint-for-datapoint… it is much more energy efficient… and it is decently accurate on this problem.” On the topic of how applicable this research is to other quantum problems, it is snarkily suggested that “it probably won’t work on almost any other problem (but then again, neither do quantum computers right now).” Overall, it is difficult to know whether the results are entirely genuine, though a lot of detail is provided and the linked research references in the paper seem genuine.

We know many readers are retro computing enthusiasts, as well as DIYers and makers. So it is good to know that the author(s) of this paper say that they will provide source code to allow others to replicate their results. However, source code will only be supplied in one of three formats, they say: “a copy handwritten on papyrus, a slide-show of blurry screenshots recorded on a VHS tape, or that I dictate it to you personally over the phone.” So please add an extra pinch of salt to this story for that.

Microsoft's new Copilot key might launch a recently added feature, but behind the scenes, the way the key works is quite old. In fact, it registers itself as a key that was most prevalent on IBM keyboards from the Reagan era. 

While some folks, including me, don't find Copilot on Windows helpful, Microsoft is going all-in on its new AI-powered assistant, going so far as to create a dedicated Copilot key which some new laptops have next to the right Alt key on their keyboards. In fact, in order to meet the official definition of an "AI PC," a laptop certification that Microsoft created, the computer must have a CPU with a Neural Processing Unit (NPU), Copilot installed in Windows and the Copilot key on its keyboard.

We recently got a couple of the first laptops with Copilot keys, a Dell XPS 14 and XPS 16, in for testing and I decided to find out exactly how this new button works. I wondered if it could do anything more than just open the Copilot panel and, more importantly, how the key reports itself to the OS. Is it a brand new key with a new scan code, the menu key with a different sticker, or something else? If you know how Windows sees the key, you can remap it or program macros for it.

So I used AutoHotkey, a keyboard macro scripting program that can also be used to log key strokes, to find out how the Copilot key registers. To my shock and surprise, I discovered that, under the surface, the Copilot key is a combination of three keys pressed at once: Left Shift + Windows key + F23. 

Yes, that's F23, the twenty-third function key. If you're looking down at your PC keyboard today, you almost certainly have just 12 function keys and compact, 65-percent keyboards don't have a function row at all. However, in the days when many business users worked on terminals that were connected to mainframes, there were some 122-key keyboards that had an additional function row that ran from F12 to F24. The most popular of these was the IBM Model M 122, which launched in 1985. 

IBM stopped making these keyboards in the 1990's and sold its entire PC business to Lenovo in 2005. However, a company called Unicomp has a license from IBM and continues to manufacture 122-key, IBM-style keyboards for those who want them. 

Because there are keyboards in the world that have F13 - F24, Windows and other operating systems recognize those as valid keys. If you have a macro keypad, you can program those keys (or any other keys you wish) to identify themselves as F13 - F24. And since so few people have the extra function row, most applications don't already have shortcut assignments for those keys.

So, rather than creating a brand new key with a brand new scan code (every key has a scan code it sends to the OS), Microsoft simply made the Copilot key return a combination of Left Shift + Windows key + F23, a combo that almost no one on earth is going to already have assigned.  We asked and Dell confirmed that this key assignment is standard for the Copilot key and done at Microsoft's direction; it's not unique to Dell's laptops.

Unfortunately, the Copilot key doesn't do much. It just launches the Copilot panel on the right side of the desktop, which is the same exact thing you get if you click the Copilot icon or hit Windows key + C. Since it is already a combination of two modifiers and a function key, it cannot serve as a modifier. Hitting Copilot + A or Copilot + any other key does the same thing as hitting Copilot by itself.

How to Remap Your Copilot Key

The good news is that, now that we know how the OS sees the Copilot key, we can easily use a program like AutoHotkey to remap it to do almost anything we want. We can turn it into another key, we can have it launch a favorite app or website, and we can even program a complicated macro for it to perform. 

We can have it output a key combination such as Ctrl + C, but we can't have it serve as a bare modifier key (Ctrl, Alt, Shift or Win), because holding it down along with another key will register as Ctrl + Windows + F23 + [the other key you pressed].  Here's how to get started.

1. Download and install AutoHotKey. Go with version AutoHotKey 2, the latest, over version 1.

2. Set up or download a text editor for writing AutoHotKey V2 scripts. I like using Notepad++ with the AutoHotKey add-ons.

3. Create a new file called copilot-remap.ahk (or anything you want with a .ahk extension) and save it in your Windows Startup folder, which is located at C:\Users\[YOUR USERNAME]\AppData\Roaming\Microsoft\Windows\Start Menu\Programs\Startup.

4. Place the following lines at the top of your AHK file. They aren't absolutely necessary but help make sure you only have one version of the file running at a time. 

#Requires AutoHotkey >=2.0#SingleInstance force

5. Enter the following code to trigger something to happen when the program sees someone hit Shift + Windows key + F23. After the two colons is where you'll put the action you want.

+#f23::

The + represents the shift key and the # represents the Windows key. Now you need to decide what you want Windows to do. After the ::, you must put your action. Do not add a line break.

Here are some ideas:

• Launch a website by using Run "https://webaddress" after the key code. You can turn the Copilot key into a ChatGPT key by having it navigate to chat.openai.com or turn it into a Gemini key by having it launch gemini.google.com
  
• Open an app by using Run "pathto exe file" so, for example, Run "notepad.exe" would open notepad.
  
• Send a keyboard combo by entering that key set after the ::. For example, ^c would be Ctrl + C. You can see a complete list of keys and modifiers on AutoHotKey's site. ^ is Ctrl, ! is Alt, # is Win and + is Shift.
  
• Enter common text such as your email address or a Linux command by using Send "mytext" with the copy you want.

Here's what these would look like in your code. Only choose one of these, as entering more than one would cause them to conflict.

; Launch ChatGPT Website in your default browser+#f23:: Run "https://chat.openai.com/"; Launch Tom's Hardware+#f23:: Run "https://www.tomshardware.com"; Open Windows Explorer+#f23:: Run "explorer.exe"; Make it hit Ctrl + Z (which is undo)+#f23:: ^z; Enter the "sudo" command (or other text)+#f23:: Send "sudo"

6. Run your script, either by double clicking on it or, if you have installed the Runme plugin in Notepad++, by hitting Shift + F5.

The action should work instead of launching Copilot. In all of our tests, AutoHotKey managed to intercept the keystroke before Windows used it to open the Copilot pane. 

However, if for some reason, Windows 11 changes in an update and manages to fire the Copilot instruction before AutoHotKey intercepts the keystroke, you'd have it both open Copilot and perform your desired task. 

That seems unlikely, but if it were to happen in the future, you could use Sharpkeys, a program which remaps keys in the registry, to map F23 to F13 and then change your Autohotkey script to fire on +#f13:: instead of +#f23::. We tested and this works. 

On March 12, researchers from VUSec and IBM made a new form of speculative execution attack publicly known on Twitter, linking to a corresponding GhostRace disclosure paper hosted by VUSec. We'll be discussing the full GhostRace disclosure document and its attached documentation in more detail below, but first, let's take some time to clarify what a "speculative execution attack" even is.

If you remember the scourge of Meltdown and Spectre, back in 2016, this is very much in the same category of major CPU security exploits. Spectre V1 was explicitly a speculative execution attack, even. Speculative execution in and of itself isn't a bad thing— it's actually a core function of modern CPUs, which allows CPU threads to more effectively share resources. 

The issue is, that speculative execution can also result in "race conditions", where separate threads attempting to access shared resources create major security vulnerabilities by doing so in a poorly-synchronized matter. This exploit is focused on taking advantage of those scenarios, so it's appropriately named GhostRace.

Before making GhostRace public, the researchers informed major hardware vendors and the Linux kernel of the issue (in late 2023), since GhostRace applies to all major OSes and CPUs, even Arm. The notice given should hopefully have given vendors the time they needed to develop their fixes and workarounds, however, the researchers also included some tips for mitigating the issue in the public document. An early fix attempt by the Linux kernel seemed promising, but experiments done by the researchers proved the fix didn't completely cover the vulnerability. 

For now, it seems Linux kernel devs are primarily concerned with performance, and don't want to risk majorly crippling it with a rushed fix. We read that the proposed mitigation for Linux provided in the original documentation is tested as only having a roughly ~5% performance overhead in LMBench. No patching performance penalty is ever welcome, but perhaps a patiently developed fix can do better.

No mitigations are provided in the document for other platforms. However, AMD points out that existing Spectre v1 mitigations should still apply to potential GhostRace exploits— and since vendors have already had to tackle that, it should only be a matter of time. AMD has acknowledged the issue, according to the public disclosure paper.

Martin Goetz (image credit: Madhyamam), the man who secured the first U.S. software patent in 1968, has passed away at 93. Goetz was known not only for earning the first U.S. software patent, but also for fighting against industry giants like IBM, helping to shape the modern software industry. His actions led to significant legal and commercial changes, making it easier for smaller software developers to succeed, reports the New York Times.

In 2007, Computerworld recognized Goetz as an overlooked innovator in the computing industry, while mainframezone.com honored him with the title "Father of Third-Party Software." Goetz's work helped create an industry where people could come up with new software ideas and have them protected by law. The industry grew massively, earning around $610 billion worldwide in 2022, showing how impactful his contributions were. His idea that software could and should be patented helped to drive this massive growth and innovation.

Martin Goetz's big achievement came in 1968 when he secured a patent for data-sorting mainframe software. Before this, people did not think of software as something that could be patented. The move stopped big companies like IBM from just copying his work, helping to level the playing field for everyone else in the industry.

"He not only got what he wanted," his daughter Karen Jacobs told NYT. "A.D.R. started selling more products and opened the doors to the independent software industry."

Goetz was not afraid to stand up to the big players in the industry. His company, Applied Data Research, sued IBM, accusing them of unfair practices by bundling software with hardware. The lawsuit helped to break this bundling practice, making the industry more accessible for smaller companies and encouraging more competition and innovation.

The fight against IBM was a big deal, and it helped open doors for smaller companies in the software industry. By challenging IBM's practices, Goetz made it possible for other software companies to operate being not dominated by the industry's giants, which led to a diverse software market that we have today. 

A retro-computing enthusiast was inspired to create a heady mix of old and new, crafting an 8-bit ISA graphics card with an HDMI output. Yeo Kheng Meng detailed his ISA HDMI card shenanigans on his blog. Meng based his work largely on a prior ISA card dubbed the Graphics Gremlin (GG), by Eric Schlaepfer, which delivered Monochrome Display Adapter (MDA) and Color Graphics Adapter (CGA) compatibility to monitors via composite out and VGA ports.

A problem often faced by retro-computing enthusiasts is when and how to mix their old, lovingly cared for hardware with new components. Some purists insist on using only period-correct components and peripherals, but most don't mind sprinkling a little modernity into the mix, usually for the sake of performance and / or convenience.

Meng began his work on the Graphics Gremlin modifications at least two years ago, possibly more. He faced a common problem for users of the IBM 5155 and similarly vintage PCs: These old PCs have a tricky time connecting to the luscious and expansive monitors we now have available in 2023.

It's not just the physical connection that needs to be worked out. The old MDA and CGA standards also used techniques like scan doubling and some refresh rates that aren't compatible with more modern monitors, including VGA.

The Graphics Gremlin was a good starting point for an MDA and CGA compatible ISA graphics card with HDMI, as it had already brought those standards in line with VGA several years earlier. However, Meng had a couple of other modifications on his wish list. He wanted to be able to use both ports on the card simultaneously, and he wanted to avoid putting a video quality sapping VGA to HDMI converter in the chain.

If you want to dig deep into the electronics and software work required to modify the Graphics Gremlin into an HDMI connected card, you can reference both the maker's blog post and open-sourced GitHub repository.

Above you can see the original Graphics Gremlin design (left) and the new model with HDMI and other improvements (right). Meng seems to be pleased overall with his adapted card, based around a Lattice iCE40HX4K FPGA and 512KB of VRAM. Specifically, the HDMI is as clear as can be with its direct digital TTL signal feed from a TI TFP410 DVI transmitter. Also the analog composite output can now work at the same time as the other output.

Other goodies that Meng managed to work into his Graphics Gremlin HDMI redesign include:

• Added LED power indicators
• Selectable MDA colors
• Added a CGA 70 Hz mode
• Modified scan doubler code for better compatibility

Despite his headlining success, a few issues remain with Meng's modified Graphics Gremlin card. Probably the most noticeable wrinkle is with CGA brown being "displayed incorrectly as dark yellow." This is clearly manifested on the IBM 5155 running the CGA Compatibility Tester color palette check.

Meng appears to indicate fixing the adaptor's handling of palette value “I:0 R:1 G:1 B:0” would need a different FPGA, one with more pins. We don't know if a subsequent tweaked design will be made to address this coloring issue.

IBM, which has been at the forefront of quantum computing and a number of other research fields, recently showcased what it feels the solution to AI processing (and its costs) could be. And if IBM's vision translates into something, the future isn't centered around GPUs: instead, it takes place within mixed-signal, analog chips that could bring about massive improvements in energy efficiency while offering competitive performance against the market's current go-tos.

According to a research paper published in Nature Electronics last week, IBM believes the future of AI inferencing could pass through a chip combining phase-change memory (PCM) alongside digital circuits. According to the paper, matrix-vector multiplication (one of the main workloads for AI inferencing) could be performed directly on chip-stored weights.

In this scenario, the reduced power requirements of passive, analog circuitry (which don't require a continuous electrical current to maintain the bit value they're holding) should allow for a reduction in the overall power required to successfully perform matrix calculations — or, at the very least, allow for the surplus energy budget of the (now) analog sections of the chip to be repurposed towards its remaining digital circuits for added throughput. The design takes clues from learnings from research in neuromorphic computing.

Developed as part of IBM's Hermes project, the latest version of the chip counts with 64 compute tiles, which communicate with each other through a Network-on-Chip (NOC) approach that's similar in concept to AMD's Infinity Fabric. There's also fixed-function hardware that's specialized in the processing of convolutional layers (which aim to reduce complexity of the underlying information in order to accelerate processing speed and increase efficiency). Being a research chip, it's been fabricated at a 14-nm fabrication process; perhaps IBM has room to further improve power efficiency, if the analog cells can be further miniaturized.

The phase-change-memory (PCM) cells themselves are distributed throughout each of the 64 tiles arranged in a crossbar, which can store a 256x256 matrix-vector multiplication space. To be fair, there are certain performance constraints in such a mixed analog-digital design: signals need to be converted from analog to digital (and vice-versa), which incurs penalties in both latency and energy utilization. But with appropriate scheduling optimizations, the final result is higher efficiency compared with a fully-digital chip (such as Nvidia's A100 and H100). According to IBM, a single ResNet-9 input was processed in 1.52 μs (micro-seconds) and consumed 1.51 μJ (micro-Joules) of energy. According to Abu Sebastian at the IBM Rüschlikon Center (as covered by EE Times), the current iteration of the chip achieves a peak matrix-vector-multiplication throughput of 16.1 to 63.1 TOPC (trillion operations per second) at an energy efficiency of 2.48 to 9.76 TOPS W-1.

The still-ongoing AI "revolution" has sparked volcanic moves in the High Performance Computing (HPC) market. But besides driving home the marvel of GPUs (the general processing units responsible for accelerating most of that particular market), the gold rush for AI accelerators has showcased just how dependent on a single player the market still is (read: Nvidia), while also bringing back to the forefront questions of energy efficiency.

Analog chips that break apart the power efficiency barriers would certainly be a welcome move, but as with any new technology, analog AI inferencing chips will have to fight to survive against the already-entrenched technologies, software stack, and techniques deployed today. Network effects and market share are real, and Nvidia's grip on the HPC market through both its hardware and CUDA software stacks is... vice-like, to say the least.

Behind the simple but not-unappealing website of Brutman Labs, there are some surprising features and statistics. In a recent update posted to the site, it was revealed that the server behind the web destination has run for an impressive "2,500 hours of continuous runtime." However, probably far more eyebrow-raising is the fact that the web server is a 39-year-old IBM PCjr that's packing a 4.77 MHz CPU.

The Brutman Labs web page is subtitled "retrocomputing performance art," and we think that may be due to the incongruence between the ancient hardware and the capable and steady web serving achieved. At the time of writing, the server status page reveals that the beige IBM computing fossil has continuously been doing its duty for 2,541 hours+. That is over 105 days straight, with no restarts.

The achievement outlined above deserves closer inspection, so what are the specs behind the BrutmanLabs.Org server? You can see the hardware and software listed in the image below:

The 39-year-old IBM PCjr acting as a web server here has had some significant modernizations. Probably the biggest upgrade has been delivered to the storage subsystem, with an IDE adapter and a 240GB SATA SSD installed. Also, the RAM is maxed out to 736 KB, which may have been unusual on this machine 39 years ago. Nevertheless, the beating heart of this system remains the NEC V20 CPU, a chip that is code and pin compatible with the fabled Intel 8088, running at 4.77 MHz.

If you visit BrutmanLabs.Org today, the machine serving the web pages you read is served by this old very IBM PCjr. The site is also worth visiting for lots of information on related and side projects.

Brutman Labs Server Uptime in Context

It may be impressive that the retro-server mentioned above has been continuously running for 2,541+ hours, or 105+ days, but it is just a minnow in the uptime league tables.

Last month we reported an AMD Epyc Rome bug, which the red team admitted could cause "a core to hang after about 1,044 days." That's about 2.93 years. The issue that affected second-gen Epyc processors meant a workaround of restarting your system more regularly than every 1,044 days was suggested. Alternatively, users could disable the CC6 sleep state.

Sadly for Epyc Rome users, AMD's bug meant systems based around the CPU wouldn't have a chance to rank highly in the uptime league. 2.93 years might sound like a long time between restarts, but the computer in the Voyager spacecraft has been running for over 48 years (and counting) without a reboot, for example. If we look at only terrestrial computers, the record seems to be over 16 years for a server decommissioned in 2018.

If you have a computer system uptime you are proud of; it may be worth comparing notes with the throng on the uptimeporn subreddit. These listings aren't just for computers, but for all kinds of devices. We noticed a fascinating post about a Cisco router, which was claimed to have run continuously for over 19 years.

A team of IBM researchers in association with UC Berkeley and Purdue University have managed to extract useful quantum computing out of one of today’s NISQ (Noisy Intermediate Scale Quantum) computers. The team used one of IBM’s latest Quantum Processing Units (QPU), Eagle, to perform calculations that were expected to fail in the midst of qubit noise. However, using a clever feedback mechanism between IBM’s 127-qubit Eagle QPU and supercomputers with UC Berkeley and Purdue University, IBM managed to prove it could derive useful results from a noisy QPU. The door to quantum utility is open – and we’re much earlier than expected.

Our NISQ-era quantum computers are roped-in to our standard supercomputers – the most powerful machines known to mankind, capable of trillions of operations per second. Powerful as they are, it’s a universal truth that when two subjects are roped together, they only move as fast as the slowest of them allows. And the supercomputer was already stretched thin for this experiment, using advanced techniques to keep up with the simulation’s complexity.

When the qubits’ simulation became too complex for the supercomputer to simply “brute force” the results, the researchers at UC Berkeley started using compression algorithms – tensor network states. These tensor network states (matrixes) are essentially data cubes, where the numbers that comprise the calculations are represented in a three-dimensional space (x, y, z) that’s capable of handling more complex information relationships and volumes than a more usual 2D solution - think of a simple Excel 2D table (x, y) and the many more rows you’d have to search through in that configuration if you had to consider another plane of information (z).

This means that there’s already some utility that can be extracted from NISQ quantum computers – there are matters where they can produce results that would be beyond the reach – at least in terms of time and money – to standard supercomputers, or where the hoops required to obtain those results would make the effort bigger than the gain.

There’s now a back and forth happening between solutions given by our NISQ-era quantum computers that feature a few hundred qubits (at best), and our standard supercomputers that feature trillions of transistors. As the number of available, useful qubits increases, circuits with depths deeper 60 used in the paper will be explored. As the number and quality of qubits increase, standard supercomputers too will have to keep up, crunching the numbers and verifying as deep a queue of quantum computing’s results as it possibly can.

“It immediately points out the need for new classical methods,” said Anand. And they’re already looking into those methods. “Now, we’re asking if we can take the same error mitigation concept and apply it to classical tensor network simulations to see if we can get better classical results.”

Essentially, the more accurately you can predict how noise evolves in your quantum system, the better you know how that noise poisons the correct results. The way you learn how to predict something is simply to prod at it and observe what happens enough times that you can identify the levers that make it tick. 

Some of these levers have to do with how and when you activate your qubits (some circuits use more qubits, others require those qubits to be arranged into more or less quantum gates, with more complex entanglements between certain qubits… ) IBM researchers had to learn precisely how much and what noise resulted from moving each of these knobs within its 127-qubit Quantum Eagle – because if you know how to introduce noise, then you begin to control it. If you understand how it appears in the first place, you can account for it, which in turn allows you to try and prevent or take advantage of that happening.

But if you’re only running calculations on your noisy computer, how can you know those calculations are, well, correct? That’s where standard supercomputers – and the search for a ground truth – comes in.

The IBM team got access to two supercomputers - Berkeley National Lab’s National Energy Research Scientific Computing Center (NERSC) and at the NSF-funded Anvil supercomputer at Purdue University. These supercomputers would calculate the same quantum simulations that IBM ran on its 127-qubit Eagle QPU – divvied up as needed within them, and in ways that would allow the comparison of both results from the supercomputers. Now, you have a ground truth – the solution you know to be correct, achieved and verified by standard supercomputers. Now the light is green to compare your noisy results with the correct ones.

“IBM asked our group if we would be interested in taking the project on, knowing that our group specialized in the computational tools necessary for this kind of experiment,” graduate researcher Sajant Anand with UC Berkeley said. “I thought it was an interesting project, at first, but I didn’t expect the results to turn out the way they did.”

Then it’s “just” a matter of solving a “find the differences” puzzle: once you realize how exactly the presence of noise skewed the results, you can compensate for its presence, and glean the same “ground truth” that was present in the standard supercomputers’ results. IBM calls this technique Zero Noise Extrapolation (ZNE).

It’s a symbiotic process: the IBM team responsible for the paper is also looking to bring its error mitigation techniques – and equivalents to Zero Noise Extrapolation – to standard supercomputers. Between raw power increase from the most recent hardware developments and algorithm and technique optimizations (such as the usage of smart compression algorithms), raw supercomputing power will grow, allowing us to verify our quantum computing work just that little bit further into the era of post-NISQ quantum computers and their deployment of quantum error correction. 

That’s the moment where the rope breaks, and quantum will be relatively free of the need to verify its results with classical techniques. That’s what’s slowing quantum computing down (beyond the absence of error correction that will allow qubits to perform the calculations themselves, of course).

In an interview with Tom’s Hardware for this article, Dr. Abhinav Kandala, manager at Quantum Capabilities and Demonstrations at IBM Quantum, put it beautifully:

Except with quantum, you can then increase the problem’s complexity beyond what supercomputers can handle – and because you have correctly modeled how noise impacts the system, you can still perform the cleanup steps on your noisy results… with some degree of confidence. The farther you are from the “conclusively truthful” results provided by standard supercomputers, the more likely you are to introduce fatal errors into the calculations that weren’t (and couldn’t be) accounted for on your noise model.

But while you can trust your results, you’ve actually delivered quantum processing capabilities that are useful, and beyond what can be achieved with current-gen, classical Turing machines like the supercomputer at Berkeley. It’s also beyond what was thought possible in our current NISQ (Noisy Intermediate Stage Quantum)-era computers. And it just so happens that many algorithms designed for near-term quantum devices would be able to fit within the 127 qubits in IBM’s Eagle QPU, which can deliver circuit depths in excess of 60 steps “worth” of quantum gates.

Dr. Kandala then added: “What we're doing with error mitigation that is running short depth quantum circuits and measuring what are called expectation values measuring properties of the state this is not the only thing that people want to do with quantum computers right I mean to unlock the full potential one does need quantum error correction and the the prevailing feeling was that for anything useful to be done one can only access that once you have an error corrected quantum computer

“The critical piece was being able to manipulate the noise beyond pulse stretching,” said Dr. Kandala. “Once that began to work, we could do more complicated extrapolations that could suppress the bias from the noise in a way we weren’t able to do previously.”

ZNE is likely to become a staple of any quantum computing approach – error mitigation is an essential requirement for the error-prone NISQ computers we currently have and will likely be required even when we arrive at the doorstep of error correction – an approach that sees certain qubits tasked with functions related to correcting errors in other qubits’ calculations.

The work done by IBM here has already had impact on the company’s roadmap – ZNE has that appealing quality of making better qubits out of those we already can control within a Quantum Processing Unit (QPU). It’s almost as if we had a megahertz increase – more performance (less noise) without any additional logic. We can be sure these lessons are being considered and implemented wherever possible on the road to a "million + qubits".

It's also difficult to ignore how this work showcases that there isn't really a race between quantum and classical: the future is indeed Fusion, to game a little with AMD's moto of old. That Fusion will see specific computing elements addressing specific processing needs. Each problem, no matter how complex, has its tool, from classical to quantum; and human ingenuity demands that we excel at using all of ours.

That proverbial rope between standard supercomputers and quantum computers only stretches so far – but IBM is finding cleverer and cleverer ways to extend its length. Thanks to this research, quantum computers are beginning to see that little bit ahead already. Perhaps Dr. Kandala will get to see what he hopes sooner than even he expects: the playground to quantum utility is now open ahead of schedule. Let's see what humans can do within it, shall we?

GlobalFoundries (GF) on Wednesday said it had sued IBM for revealing its trade secrets related to jointly developed chip technologies to Intel and Japan's Rapidus consortium. The lawsuit also alleges that IBM is actively poaching GF's engineers. The foundry demands compensation, punitive damages, an order to prevent further unapproved disclosures, and an injunction to cease inopportune enrollment practices.

GlobalFoundries alleges that IBM has illicitly revealed its proprietary IP and trade secrets that it got after acquiring IBM's microelectronics division in 2015. The complaint asserts that IBM's top management has portrayed the Intel and Rapidus collaborations as relying on technology developed over several decades from research conducted at the Albany NanoTech Complex. However, GlobalFoundries considers that IP its property following its acquisition of IBM's microelectronics business eight years ago. 

IBM is currently working with Japan's Rapidus consortium on the latter's 2nm fabrication process and with Intel on various semiconductor-related technologies as part of their partnership announced in 2021. Manufacturing technologies currently developed by Intel and Rapidus rely on gate-all-around (GAA) transistors. This type of transistor has been explored by various researchers at the Albany NanoTech Complex for years. 

It is unclear what exactly IBM disclosed to Intel and Rapidus as part of their collaboration, but it is plausible that at least some of the IP it might have shared originated from its microelectronics division research. To that end, GlobalFoundries claims that IBM is unfairly getting 'potentially hundreds of millions of dollars in licensing income and other benefits' by sharing this IP with Intel and Rapidus. As a result, GlobalFoundries is seeking compensatory and punitive damages.  

Another concern that GlobalFoundries has is that IBM is actively recruiting its engineers from Fab 8 and that these efforts have accelerated since IBM/Rapidus announcement in December 2022. GF now asks the court to put an end to these recruitment practices that the company calls unlawful. 

GlobalFoundries quit developing leading-edge process technologies in 2018. It is unclear whether it will need IP developed before 2015 at Albany NanoTech Complex. However, at some point, the company will have to design its own sub-10nm and GAA-based production nodes to satisfy the growing needs of its customers.

IBM claims that GlobalFoundries' accusations are meritless, and the plaintiff filed the complaint in a bid to obtain leverage against IBM in the legal dispute concerning the sudden change of GF's roadmap in 2018 and IBM's inability to produce its processors at GF using leading-edge process technologies.

"GlobalFoundries filed this meritless lawsuit after a court rejected the company's attempt to dismiss IBM's legitimate fraud and breach of contract claims," a statement by IBM published by Reuters reads. "Their allegations are entirely baseless, and we are confident that the court will agree."

A hobbyist software developer and retro computing enthusiast has succeeded in bridging the ChatGPT and IBM PC-XT computing divide. On the lookout for a challenge, Yo Kheng Meng wondered if he could write a ChatGPT client for MS-DOS. Specifically, he targeted a 1984 vintage IBM 5155 Portable PC, which is powered by a 4.77 MHz Intel 8088 CPU and has 640KB of RAM (enough for anyone, right?). Several technological obstacles needed to be surmounted to make the project a success.

Typically, most people access ChatGPT via a web browser, but it seems to be a growing trend to access this AI resource via a client. We have reported on some notable and fun clients like a ChatGPT Smartwatch powered by a Raspberry Pi and Microsoft’s much maligned Clippy with an AI brain transplant. However, getting ChatGPT to work on one of the most ancient of PCs might be even more ambitious.

Meng started his quest by finding a compiler which could span the 40 years or so gap between the target computer and ChatGPT. The Open Watcom C/C++ compiler fit the bill. To test the DOS application during development he decided to run it in a virtual machine (Virtualbox virtual machine running DOS 6.22) on a modern PC.

One of the biggest hurdles with DOS was with the networking required to connect to the ChatGPT service. Meng found that MTCP, written by Michael B. Brutman, would facilitate the connection to ChatGPT’s Chat Completion API. However, to communicate with this API required the developer to “construct the entire POST request by hand in C.”

A few further hurdles the developer had to pass included JSON parsing, changing the ChatGPT output from HTTPS to HTTP, and working with the lack of multi-threading in DOS. You can read more about how this was achieved in his full blog post.

OpenAI’s conversational AI ChatGPT (Chat Generative Pre-Trained Transformer) has gained lots of attention in and outside of the tech world since its debut late last year. It has spurred intense new competition between web titans like Google and Microsoft, it has helped clarify the potential of AI (and some downsides), and it has caused a mini-boom for many related businesses.

China is neither the world's largest developer of chips nor the world's largest maker of semiconductors. However, its swiftly-developing microelectronics industry seems to be generating patent applications at a rapid pace. Last year, Chinese companies filed over half of all semiconductor-related patents globally, according to a report from Mathys & Squire, an intellectual property law firm.

"Global powers such as the U.S., China and the E.U. are competing to be leaders in semiconductor technology," said Edd Cavanna, Managing Associate at Mathys & Squire. "That says it all regarding their importance for the future of the economy."

A record 69,190 microelectronics-related patents were filed during 2022, a sharp 59% increase from 43,380 just five years ago. This development emphasizes how rapidly this industry is developing and how chips influence all aspects of modern life. 

With 18,223 applications, Chinese companies accounted for 55% of the filings globally, while firms from the U.S. came second at 26%. By contrast, the UK accounted for 179 patents, or 0.26% of the global total, reports Mathys & Squire.

Meanwhile, TSMC was the largest individual filer, with 4,793 patents or 7% of all semiconductor-related patents globally. Applied Materials filed for 209 patents (more than all UK-based companies combined), SanDisk filed for 50, and IBM filed for 49.

It should be noted that Mathys & Squire only reported on the number of patents, and while the unit count is important, the content of those patents is even more crucial. Unfortunately, analyzing the importance of tens of thousands of patents is impossible. Yet, the number of filed patent applications speaks about the pace of the microelectronics industry development.

"Governments are increasingly concerned about the fragility of global supply chains and are taking steps to promote semiconductor research and production domestically," said Cavanna. "New technologies which emerge from this global technology race will be protected by patents which are likely to be fiercely enforced."

Intrepid Thinkpad fan Karl Buchka replaced the internals of the 701C with the much more powerful Framework mainboard. The best official specs for this laptop rated it at a 486 DX4, not something that can cope with the demands of the 21st century. Unlike today's best laptops, the best laptops of the mid-1990s featured chunky cases, DSTN screens, and a slew of proprietary ports. But IBM was always eager to please its road warrior customers, and from this desire came the 701C. The Thinkpad 701C features a novel "butterfly" keyboard that slides out to reveal a larger typing area. 

Buchka's project has been ongoing for the past six months. The project begins with a broken IBM Thinkpad 701C, bought on a whim. Buchka decided to use the broken Thinkpad as a base on which to build something glorious and decided on the Framework hardware as a base. Currently, the project is fully working but in a "mock-up" state for testing. But as we can see in the pictures, Buchka has successfully booted Ubuntu.

The original spec of the 701C is laughable today. But in its heyday, it was a productivity monster. The butterfly keyboard gave writers a comfortable typing experience while folding down into a smaller package. So how does it square up to the brain transplant?

Buchka's project is much more than just throwing a Framework motherboard into the 701C's case. Buchka managed to squeeze the Framework mainboard into the back half of the case. In the front is the battery to power the laptop. The lower part of the case is a 3D printed draft, which could easily be printed on some of the best FDM 3D printers. For high quality and strength, the final case will be printed using MJF (Multi Jet Fusion). The hinge bracket is to be printed using DMLS (Direct Metal Laser Sintering), which fuses layers of metallic powder using high-powered lasers.

It turns out that Apple's iPad 7 display is an almost perfect fit for the 701C's TFT screen. The iPad screen is adapted to use the eDP connector on the mainboard. The large 2160 x 1620 display is vast compared to the 701C's 640 x 480. Buchka notes that there is no space for Framework's expansion cards. USB-C dongles that sit flush with the Framework laptop and provide extra ports. Instead, they have chosen to expose two USB-C ports on the right side of the case. On the left, a custom USB-C port replicator exposes two USB-A ports. Buchka is still working on the CAD models for this part of the build.

The star of the show has to be the butterfly keyboard, and it continues to shine thanks to a Teensy 3.6 microcontroller that provides both keyboard and trackpoint as USB devices thanks to a customized QMK build. In the final build, the keyboard and trackpoint electronics will become a custom PCB, right now it is a self-confessed mess of wires.

This project is wonderful. We love the old Thinkpad aesthetic but crave the power of the latest CPUs. This project marries the two very well. More details can be found on Buchka's Framework community profile page. 

While unit shipments of hard drives were down by at least 34% in 2022 compared to the prior year and capacity of HDDs also dropped year-over-year, sales of LTO (Linear Tape Open) tapes increased once again last year, according to Trendfocus data cited by Blocks & Files and Storage Newletter. In fact, analysts from Trendfocus believe that shipments of tapes used to store archives and for cold storage will keep growing at least through 2027. Analysts believe that aggregated capacity of all tape drives shipped in 2022 totaled 79.3 exabytes, up 14% year-over-year (YoY). This is significantly below total HDD capacity sold in 2022 as we are probably looking at at least 1 zetabyte even considering shipments declines due to weakness of nearline hard drive market in the second half of the year. But the point here is that sales of HDD capacity declined, whereas shipments of tape capacity grew.

Trendfocus forecasts that capacity of tape drives will keep growing in the coming years with a compound annual growth rate of 21%. In 2027, aggregated capacity of LTO tapes will total 207.1EB. 

LTO tapes from companies like IBM, HPE, and Quantum are used by various operators of cloud datacenters to store archives that are barely ever accessed. Meanwhile, since the amount of data that needs to be stored continues to increase every year, demand for LTO tapes is increasing and will keep increasing for the foreseeable future. When it comes to capacity costs, LTO tapes are the cheapest way to store data. For example, the latest LTO-8 tape cartridges with a Strontium Ferrite (SrFe) magnetic layer enable tapes to store up to 580TB of data — almost 30 times as much as the highest capacity HDDs. Of course, they are considerably slower than hard drives due to higher latency, since tapes can only read or write sequentially, but for archives and backups this technology is good enough. While shipments of LTO tape cartridges increased in 2022, unit sales of hard drives declined again not only in the consumer space, but also in the datacenter space, something that has never happened before, according to Trendfocus. Seagate, Toshiba, and Western Digital shipped 35.2–36.4 million HDDs last year, down around 40% YoY. Exabyte shipments of nearline HDDs declined to 165EB–170EB in Q4 2022, down around 30% year-over-year due to the slowing economy and inventory corrections. 2023 is shaping up to be a rough year in the storage sector, both for SSDs and HDDs. But don't be surprised if, come next year, we once again see growth in the LTO tape storage segment.

At its Quantum Summit today, IBM announced the successful development of its 'Osprey' QPU (Quantum Processing Unit) — its 433-qubit 2022 roadmap target. The new QPU significantly increases the number of working qubits within a single QPU — the previous-gen 'Eagle' QPU only carried 127 of them. 

The new launch is another confident step for IBM's aggressive quantum computing roadmap, which aims to deliver QPUs with tens of thousands (perhaps even hundreds of thousands) of qubits by 2030.

"The new 433 qubit 'Osprey' processor brings us a step closer to the point where quantum computers will be used to tackle previously unsolvable problems," said Dr. Darío Gil, Senior Vice President, IBM and Director of Research. 

"We are continuously scaling up and advancing our quantum technology across hardware, software and classical integration to meet the biggest challenges of our time, in conjunction with our partners and clients worldwide. This work will prove foundational for the coming era of quantum-centric supercomputing."

Osprey's launch is a significant one for IBM: smack in the middle of IBM's roadmap, it carries the biggest boost in number of qubits within a single chip. Compared to Eagle, Osprey increases qubit counts by 3.4 times; it's an even larger increase in qubit counts than the company expects to achieve in three years' time, when it is planning to introduce the 4,158 qubit Kookaburra QPU. It's also higher than any other qubit jump since the introduction of Falcon and its 27 qubits back in 2019.

Due to Osprey's positioning within IBM's roadmap — right before the company starts exploring quantum scaling by interconnecting multiple QPUs next year with Heron and its p couplings — the increase in qubit counts without a compromise in quality is exceptionally relevant. But perhaps more impressive is the fact that this jump in qubit counts was engineered at the same time that IBM laid most of the groundwork for its future modular products. 

The company is looking to 2023 to introduce its 133-qubit, scalable Heron QPUs, which will leverage p-couplings to interconnect several Heron chips. The idea is that it's easier to scale qubits within a given package and link separate packages than it is to create a monolithic QPU. 

It does bring about challenges regarding workload distribution — there are a number of ways to cut up a higher-volume quantum problem so that it fits the chip (or chips) you have available to run the quantum circuits on, and the way this is done severely impacts performance. But multi-chip scaling is a necessity, and adopting this approach meant re-engineering the entire control electronics subsystem — the bridge between classical and quantum computing.

According to Dr. Oliver Dial, Chief Hardware Architect at IBM Quantum, a significant improvement came from changing the qubit control mechanism inside the company's dilution refrigerators — the hardware responsible for cooling the superconducting qubits towards near absolute zero (−273.15 °C). 

Before Osprey, IBM employed coaxial cables to transmit microwave control information towards the operating qubits. Now, the coaxial cables have given way to flexible ribbon cables (the same sort that's used wherever there are electronics and hinges, such as in your laptop). These ribbon cables themselves occupy much less space and offer much higher throughput than the previous solution while costing less time and resources to deploy. Dr. Dial says they allowed IBM to increase control density by 70% while reducing costs fivefold.

Another important element to this new quantum generation from IBM was increased FPGA (Field-Programmable Gate Array) performance within the control subsystem. 

While the future of IBM's qubit control passes through quantum-specific ASICs (Application-Specific Integrated Circuits), FPGAs have so far been handling the grunt of the work due to their flexibility — IBM can prototype different control schemes within the FPGA's programmable design. This allows for quick experimentation and iteration until such a time when the company is confident enough to go the full ASIC route. Dr. Dial says this change will deliver another monumental improvement on power efficiency by cutting down the wattage required to control a single qubit from around 100 W down to just 10 milliwatts.

Crucially, Dr. Dial says the superconducting qubits in Osprey have shown coherence times comparable to the company's best (despite the tremendous increase in qubit count), meaning that pure quantum volume (a quantum computing performance estimate that IBM and other industry players support) is bound to increase in-line with qubit counts. 

According to IBM, the number and quality of qubits in Osprey are such that a classical system attempting to describe its qubits' computational state would require more available bits than there are atoms in the universe. It would seem that we've already entered the quantum advantage stage of the equation.

Of course, qubits may improve in both their count and quality, but there's little that pure quantum hardware solutions have to offer the average user. Dr. Dial was quick to point out that anyone — truly anyone — can now spin up IBM's quantum tech via the company's cloud offering. 

Quantum computing requires a severe abstraction effort that allows non quantum-specialists to interact with these systems, and IBM has also doubled down on its Quiskit Runtime software to make it easier for users to do so — trading runtime for accuracy is as easy as changing a software setting.

Through improvements in its drivers, Quiskit runtime, and parametrized circuit improvements throughout 2022 led IBM to scrape through its 1,400 CLOPS score up to around 15,000 CLOPS — if AMD's driver-based performance improvements on its GPUs have earned it the "fine wine" moniker, I wonder what metaphor would be appropriate for this almost 11x performance increase.

Hardware improvements are a necessary half of developing any new technological system; but the other half is actually putting that hardware to use. To that end, IBM at its Quantum Summit also announced its 100x100 Challenge, an initiative that aims to put a 100 qubit x 100 gate operation depth in the hands of users by 2024. By leveraging the company's next-generation modular quantum architecture, Heron, IBM aims to challenge users with a "what fits here?" question — what sort of quantum computational problem can be processed within these constraints?

For all we know about quantum computing, something really special could come out of this challenge — it's not a matter of whether humanity will see significant gains when it starts solving problems with quantum computation. It's merely a matter of how and when — and this challenge gives IBM a surefire way to keep that conversation ongoing. Which is, after all, one of the company's concerns for its Quantum Summit 2022.

"The IBM Quantum Summit 2022 marks a pivotal moment in the evolution of the global quantum computing sector, as we advance along our quantum roadmap. As we continue to increase the scale of quantum systems and make them simpler to use, we will continue to see adoption and growth of the quantum industry," said Jay Gambetta, IBM Fellow and VP of IBM Quantum. "Our breakthroughs define the next wave in quantum, which we call quantum-centric supercomputing, where modularity, communication, and middleware will contribute to enhanced scaling computation capacity, and integration of quantum and classical workflows."

On the back of those remarks and IBM's rate of quantum development (and perfect execution, according to its roadmap), it seems the company's bet on superconducting qubits is paying off. As IBM has showcased, there's much life yet in optimizing the company's quantum systems, apart from the increase in qubit densities and coherence times that have enabled the jump from the 127-qubit Eagle to the 433 qubit Osprey. 

Osprey has now taken flight, but IBM has never stopped looking towards the future of quantum — and that continues with the 2023, 1,121 qubit Condor.