Intel and AMD have mostly been rivals for decades, but for the first time in years, they may soon share a wafer. According to a new report, AMD is in early discussions with Intel to build some of its chips at Intel Foundry. No agreement has been signed, and both companies are still weighing technical feasibility. But even preliminary talks mark a notable shift in direction.

AMD has spent the last decade as one of TSMC’s most consistent anchor customers. The fact that it's now considering Intel as a second source shows how the semiconductor ecosystem has changed, and how much pressure is building on AMD to diversify.

For Intel, along with the recent Nvidia partnership announcement, this is the most promising sign yet that its foundry business is being taken seriously. Intel Foundry Services (IFS) has been in a holding pattern since launch, having not signed a tier-one customer at a meaningful scale and experienced serious troubles in bringing its 18A and 14A nodes to volume. IFS is burning billions in operating losses each quarter, so something needs to give soon.

AMD needs options

The appeal for AMD is fairly straightforward. TSMC is still the most advanced foundry in the world, and AMD is closely aligned with its roadmap. But supply constraints and geopolitical risk have become harder to ignore. The U.S. government has said it wants at least half of all chips bound for American markets to be manufactured domestically. Most of AMD’s volume is still built in Taiwan, and TSMC’s Arizona fabs — assuming they stay on schedule — will not be able to support AMD’s high-end products until 2027 at the earliest.

TSMC’s N3 production remains oversubscribed, and the company’s US-based capacity is still limited to mature or partially customized nodes. If AMD wants to start shifting even a small share of its production to U.S. soil, it needs alternatives. Samsung is an option, but volume yields on Samsung’s most advanced nodes have trailed behind TSMC. Intel is the only other player in the market building advanced-node fabs on U.S. soil at scale.

None of this means AMD is about to put Zen 5 or RDNA 4 on an Intel process. Intel’s current nodes are not competitive with TSMC N4P or N3 in terms of density or performance per watt. But AMD’s chiplet strategy gives it flexibility. Supporting dies, like I/O chiplets and certain accelerators, do not require the most advanced nodes. These are already produced on older processes, and some are built on U.S. soil via subcontractors. Intel’s 20A or even a mature 7nm-class node could be viable for these parts if the yield and packaging stack are competitive.

Intel needs validation

Internally, Intel has said that if its upcoming 18A and 14A nodes do not attract enough external interest, it may abandon them entirely. Getting AMD on board, even in a limited fashion, would help de-risk that roadmap. So far, IFS has largely served Intel itself. Even in its own disclosures, Intel has admitted that most IFS revenue to date has come from internal programs and legacy nodes. Intel's current foundry strategy heavily depends on signing customers that can commit meaningful volume on future nodes. This includes Nvidia, which announced a major partnership last month, and now potentially AMD.

What Intel needs more than anything is external validation. If AMD moves even a portion of its portfolio to Intel Foundry, it sends a signal to the rest of the industry that Intel’s nodes can be trusted. That is especially true in this case, where the two companies are direct competitors. If AMD is willing to let Intel manufacture parts of its supply chain, it lowers the reputational barrier for every other foundry customer.

That validation could also keep Intel in the running for U.S. government contracts and longer-term subsidy programs. The Department of Commerce has already announced up to $7.9 billion in support for Intel’s Arizona and Ohio fabs. If Intel fails to attract the necessary demand for those facilities, it will become increasingly difficult to justify additional investment. AMD’s participation would help bolster the case that Intel’s foundry business is viable, especially if it begins shipping chips before TSMC’s U.S. fabs reach volume.

A deal is possible, but not certain

It has been a busy few weeks for the semiconductor industry. Apple debuted its next-generation silicon, Nvidia launched an unprecedented partnership, and TSMC denied rumors of a major tie-up with Intel. But across all these developments, one name has remained conspicuously absent: Intel Foundry.

Take the biggest stories of the month. Apple’s new A19 and A19 Pro chips launched on TSMC’s 3nm N3P node. No mention of Intel, no sign of Intel Foundry. That’s obviously not surprising — it's been a few years since we last saw Intel inside of Apple — but it’s a reminder of who controls the high ground in chip manufacturing, and how little visible traction Intel has gained despite years of pledges.

Then came Nvidia’s surprise announcement of a sweeping new partnership with Intel to build x86 CPUs with integrated Nvidia GPU chiplets, linked over NVLink and packaged with Intel’s Foveros technology. Jensen Huang and Lip-Bu Tan appeared together via a joint press conference shortly afterwards, and yet, when asked about moving Nvidia’s GPU foundry to Intel’s fabs, Tan replied: “In terms of Intel’s foundry, we continue to make progress… at the right time, Jensen and I will review that.”

Nvidia CEO Jensen Huang was even more blunt, calling TSMC “magic.” It was a remarkable thing to hear during a live Q&A co-hosted by Intel, as part of a joint announcement, but not entirely unsurprising, given Nvidia and Intel's good working relationships with TSMC.

A roadmap without traction

Intel Foundry was established with the goal of directly competing with TSMC and Samsung in contract chip manufacturing. But in the years since its launch in 2021, Intel Foundry has been dominated by delays, customer dropouts, and a brutally honest admission in Intel’s latest filings that Intel Foundry has so far failed to attract significant customers.

Intel previously said its 1.8nm-class 18A process was on track for foundry in 2025 — indeed, risk production began in Q1 — and it continues to build toward 14A beyond that. But internally, Intel now says that 18A’s first and most important customer isn’t some blue-chip hyperscaler or chip startup but rather, Intel itself.

That’s not necessarily a bad thing. Many successful foundries start by proving their nodes with internal products. However, it highlights how far Intel still is from market leaders. TSMC is already producing 3nm chips for Apple and working toward 2nm volume next year. Samsung, despite customer churn, is also advancing its roadmap.

Intel Foundry's biggest problem remains yield. The 18A process still struggles to produce usable chips at high enough rates to be viable at scale, and that cost parity with TSMC is still out of reach. Intel’s own earnings show Intel Foundry losing billions per quarter, with operating losses of more than $3 billion reported for Q2 2025 alone.

Packaging first, foundry later

What Intel has succeeded in doing is packaging, and Lip-Ban Tu knows it. The joint Nvidia-Intel announcement was in many ways framed as a potential packaging breakthrough, with Jensen Huang highlighting Intel’s ability to connect Nvidia’s GPU chiplets with Intel CPUs using Foveros, calling it the kind of multi-technology integration that other foundries simply can’t deliver in the same way.

That packaging capability may well become Intel’s biggest near-term advantage. Foveros and EMIB give the company a mature chiplet integration stack, well-suited to an era where performance gains come more from heterogeneous integration than monolithic scaling. And with Nvidia, Intel finally has a marquee partner willing to bet on that stack, even if not (yet) on the foundry behind it.

There’s another reason Intel is focusing on packaging — it buys time. Unlike bleeding-edge wafer production, packaging doesn’t demand the same kind of node-level maturity. It allows Intel to use proven dies, whether its own or those of its partners, while demonstrating value through integration and system-level efficiency. It also aligns with the broader U.S. industrial strategy, which increasingly sees chip packaging as a national priority.

And because Foveros can integrate chiplets from multiple sources, Intel isn’t locked into its own process nodes. As Huang noted, Nvidia’s chiplets still come from TSMC, but the package doesn’t have to. Intel’s unique cross-foundry packaging model could be a future-proof wedge into multi-vendor systems.

Packaging is also a fast on-ramp for revenue generation for Intel Foundry. Qualifying new chip designs with customers can be a years-long process that takes time to yield revenue and profit, whereas the lead times for chip packaging often only take a few months before revenue generation begins.

A quiet retreat?

A federal judge on Wednesday dismissed a lawsuit against Intel, which accused the company and its management of hiding financial troubles of its semiconductor manufacturing division in 2023, reports Reuters. The U.S. District Judge Trina Thompson in San Francisco ruled that plaintiffs failed to present evidence that Intel and its executives committed any wrongdoing. The case was dismissed without prejudice, meaning the plaintiffs can file an amended complaint with stronger evidence.

Plaintiffs had argued that Intel and its then-CEO Pat Gelsinger and then-CFO David Zinsner concealed a $7 billion loss of its Intel Foundry unit in 2023, which led to stock inflation as well as a consequent massive $32 billion drop of the company's market capitalization in April 2024, when the company disclosed losses of its newly formed Intel Foundry division for 2023 and Q1 2025.

Starting in Q1 2024, Intel implemented its 'internal foundry' model, making its product divisions and external clients purchase manufacturing and packaging services from Intel Foundry, a separate division within the company. Before this, Intel only reported results for Intel Foundry Services (IFS), which catered exclusively to external customers.

On April 2, 2024, Intel fully disclosed its segment reporting changes and had to recast past financials, revealing that Intel Foundry lost $7 billion in 2023. This revelation triggered a sharp decline in Intel's stock. The court determined this loss was not solely tied to Intel Foundry Services, the division responsible for making chips for outside companies, contradicting investors' claims, but was attributed to Intel Foundry, a division that worked with both Intel and external customers

The lawsuit also challenged statements by Gelsinger and Zinsner, particularly Gelsinger's claim of 'significant traction' and 'growing demand' for the foundry business. The court ruled these statements were not misleading because they referred to specific customer engagements rather than overall financial health of Intel and Intel Foundry.

Plaintiffs also pointed to Intel's 26% stock drop after announcing layoffs and a dividend suspension in mid-2024, claiming it was evidence of misleading practices. However, the court ruled that a stock decline alone is not proof of fraud, as Intel has always had competitive challenges and publicly discussed its cost-saving strategy and restructuring plans.

Although the lawsuit was dismissed, the judge will allow investors to revise their complaint and refile. Intel declined to comment on the ruling, while legal representatives for the shareholders did not immediately respond to inquiries.

Intel CEO Pat Gelsinger held a question and answer session here today at the company's IFS Direct Connect 2024 event, and in response to a question from Tom's Hardware, he reiterated that Intel is willing to build chips for anyone -- including long-time rival AMD.

Intel Foundry will not only build chips for external customers using Intel's crown jewel process nodes, but also the full complement of all of its IP, including its leading-edge packaging technology. That raises the question of how the company would deal with competitors that are armed with its very own technology - and perhaps beating Intel's own internal product teams with better processor designs. While Gelsinger didn't answer my entire question, he certainly gave us plenty to ponder.

"Intel will now offer its process nodes to some of its competitors, and there may be situations wherein your product teams are competing directly with competitors that are enabled by your crown jewels," I asked. "How do you plan to navigate those types of situations and maybe soothe ruffled feathers on your product teams?"

"Well, if you go back to the picture I showed today, Paul, there are Intel products and Intel foundry, There's a clean line between those, and as I said on the last earnings call, we'll have a setup separate legal entity for Intel foundry this year, " Gelsinger responded."We'll start posting separate financials associated with that going forward. And the foundry team's objective is simple: Fill. The. Fabs. Deliver to the broadest set of customers on the planet."

"We hope that that includes Jensen (Nvidia), Christiano (Qualcomm), and Sundar (Google), and you heard today it includes Satya (Microsoft), and I even hope that includes Lisa (AMD) going forward. I mean, we want to be the foundry for the world, and if we're going to be the Western foundry at scale, we can't be discriminating about who’s participating in that. So, unequivocally, it is to be the foundry for the world. Commit supply chains, your leadership technology - the doors to the ala carte menu are wide open for the industry."

"And some of those [garbled] that we build, like Clearwater Forest that I showed today, hey, that's a construct that was innovated by my Xeon team: How to do hybrid bonding, Intel 3 base die, Intel 18A top die, being able to solve a lot of the CoWoS/Foveros problems using EMIB and hybrid bonding. That will become a set of collaterals that will benefit the foundry team. They're going to go sell that constructional opportunity as a better way to build AI chips. So clearly, I'm taking product group intellectual property and leveraging it on the foundry side of the business."

While this may seem to be counterintuitive, it isn't entirely unexpected: Intel is opening its doors to the industry at large with the goal of being 'the world's foundry,' and Gelsinger has previously stated his desire to work with everyone in the industry and named names. 

There were other signs of cats and dogs living together at the Intel Foundry event, too: Intel Foundry head Stu Pann called long-time rival Arm the company's most important customer, and then invited Arm CEO Rene Haas to the stage for a joint presentation. We certainly couldn't have seen that coming five years ago. In fact, Intel is already working on fabbing Arm Neoverse processors. 

In case you thought Gelsinger wasn't being clear, he doubled down on the statement in a later answer, saying, "So I want my foundry to be used by everybody. Period. We want to help build Nvidia chips, and AMD chips, and TPU chips for Google, and inference chips for Amazon. Period. We want to help them and give them the most powerful, performant, and efficient technologies for them to build their systems. Period. Full stop."

Gelsinger outlined the rest of his rationale in his extended response to my question.

"I also expect some customers are going to say hey, I really liked some of those Intel products, but I want it with a different chiplet that I do. And we're gonna say yes to that. Great. Let's go build unique versions of Clearwater Forest, and we’ll put your security chip on it or some other IO chip or networking component as well. We definitely see both complementing each other and we're gonna have soft, hard, and chiplet-based IP that we’ll produce that'll be available for our foundry customers as well going forward. But ultimately, we have to build and earn the trust of the foundry customer. And for that, it'll be the best of Intel's available to them, and their intellectual property and supply chains will be protected and contractually committed to," Gelsinger said. 

Gelsinger's desire to serve all customers comes as the company appears to be on track to regain its process node leadership over TSMC next year. With the goal of five nodes in four years nearly completed, the new Intel certainly doesn't look much like the old Intel that floundered for several years through its missteps on the 10nm node, ultimately losing its crown to TSMC. 

Intel unveiled a new roadmap that includes a new 14A node, the industry’s first to use High-NA EUV, here at its Intel Foundry Services (IFS) Direct Connect 2024 event. IFS also added new extensions to its existing lineup of process nodes and announced that it is now producing wafers of its Clearwater Forest processors on its 18A node. That’s yet another proof point that Intel’s audacious goal of delivering five nodes in four years (5N4Y) is on track for completion by the end of the year, thus giving Intel confidence that it will take back the process node leadership crown from TSMC with its 18A node in 2025. Microsoft also announced that it is building chips on Intel's 18A process node. 

As part of the coming out party, Intel has also renamed IFS to Intel Foundry. Intel Foundry has a goal of being the second-largest foundry in the world by 2030, and IFS Direct Connect 2024 is the company’s coming out party as a ‘systems foundry,’ an Intel-defined term that quantifies its experience with system-level design and includes all its technology development, manufacturing, supply chain, and the Intel Foundry Services under one umbrella. This includes not only producing processors of varying types, but also providing customers with packaging and connectivity fabric solutions - and even helping with cooling solutions. Intel Foundry caters to both external customers and internal customers from within Intel, with the goal of serving both equally (an important distinction) with a resilient and sustainable supply chain.

Additionally, Intel announced new capabilities in its Intel Foundry Advanced System and Test (ASAT) portfolio that will help its customers build their own AI chips using Intel’s full complement of technologies.

Now, on to the roadmaps (we also have an Intel vs TSMC and Samsung roadmap further below).

Five nodes in four years remains on track

We’ll get to the new roadmap next, but as you can see above, Intel CEO Pat Gelsinger’s original 2021 plan for five nodes in four years remains on track. The Intel 7 and Intel 4 nodes are now in market, and Intel 3 is ready for high volume manufacturing (HVM). Intel’s 20A (2nm) and 18A (1.8nm) are also on track for arrival as the first chips in the industry with both its PowerVia backside power delivery, which provides optimized power routing to improve performance and transistor density, and Intel’s first node with RibbonFET gate-all-around (GAA) transistors, which also provides better transistor density along with faster transistor switching, but in a smaller area. Intel’s 18A is now ready for its customers to design with the 0.9 PDK from Intel’s EDA (design software) and IP partners now, with the full 1.0 PDK arriving in the April/May timeframe.

Intel has now taped out Clearwater Forest, meaning that the chips’ final design is ready for production. Clearwater Forest is the company’s first high-volume 18A chip. As revealed in the above slide, Clearwater Forest is comprised of CPU tiles fabbed on the 18A node which are then bonded together with an Intel 3 base die using 3D Foveros packaging technology. The base die also includes cache. 

The Clearwater Forest design ropes in many of the architectural concepts we’ve seen with the Granite Rapids and 288-Core and 144-core Sierra Forest processors, but the new addition of 3D Foveros packaging is key. This tactic of bonding logic dies with a base die will also be critical in chip designs that use HBM4, which we’re told will require an active base die to ensure optimal signal integrity. As such, this tech will be incredibly important for the next wave of memory bandwidth-hungry AI chips.

Clearwater Forest is the first high-volume chip to use the Universal Chiplet Interconnect Express (UCIe), a new industry interface for connecting chips together. UCIe is a pivotal advance here that shouldn’t be overlooked: the interface is supported by Intel, AMD, Arm, Nvidia, TSMC, Samsung, and 120 others, to standardize the die-to-die interconnects between chiplets with an open-source design, thus reducing costs and fostering a broader ecosystem of validated mix-and-match chiplets from multiple chipmakers. Intel’s all-in approach with UCIe for Clearwater Forest signals not only that this tech is moving apace, but also that Intel is leading the industry charge.

Beyond 5N4Y – The arrival of Intel 14A and customized node extensions

The Post-5N4Y chart shows us what’s next – the Intel 14A process. This will be the first process node in the industry that will use a High-NA EUV lithography tool from ASML. This new chipmaking tool will allow chipmakers to print smaller features than ever before, which Intel says will enable higher performance. In fact, Intel is the first company in the industry to receive a cutting-edge High-NA tool, while TSMC is said to have delayed using the tool until 2030 due to cost concerns. Intel Foundry head Stu Pann tells us that the tool is cost-effective for Intel’s purposes, mirroring ASML’s comments on the matter.

Intel isn’t sharing performance or density targets for 14A yet, saying that it doesn’t want to give its competitors a target yet. However, we do know that it will come with next-gen PowerVia backside power delivery (likely Source-on-Contact) and RibbonFET GAA transistors. Intel has two flavors of 14A on its roadmap – the standard 14A, and then a follow-on extension called 14A-E. The E stands for a feature extension, which is part of Intel’s new approach of delivering different customizations of existing process nodes to extend their lifecycle, just like TSMC and Samsung (more on that below).

Intel isn’t committing to a date for the first 14A revision, though we do know that it arrives after 2024. The second 14A-E revision will go to risk production, meaning the first test chips will be made on A0 silicon, in the 2027 timeframe. Given Intel’s return to a Tick-Tock-like cadence and the timing of 14A-E, we think it’s safe to assume that 14A will arrive in 2026. As with Intel’s other leading-edge nodes, 14A will be developed in Oregon and then mass produced at other facilities (these remain unspecified for now).

Intel will also extend its Intel 7, Intel 3, and Intel 16 node with new ‘line extensions.’ Intel plans to deliver a new node every two years, and then sprinkle in line extensions every other year, much like its old Tick-Tock model. These line extensions are denoted by new suffixes.

The P suffix indicates a new revision of the node with performance improvements, the T suffix is for TSV-equipped nodes that can used with hybrid bonding/3D Foveros, and E suffixes indicate specialized new features, like tuned operating/voltage ranges. Intel will also have PT revisions that indicate both performance and special features, and we expect that other combined revisions will emerge over time. This technique will allow Intel Foundry to extract further use from existing nodes to serve specific customer use cases.

Intel will also have its new Intel 12 node arrive in the coming years, which comes as the fruits of its new manufacturing collaboration with UMC. Intel Foundry is also producing mature-node 65nm chips for Tower Semiconductor. Both of these collaborations are key to building further scale for Intel’s IFS operations while allowing the company to extract more value for its already depreciated tooling and facilities.

Intel vs TSMC vs Samsung process node roadmap

The above roadmap is based on publicly available information, but be aware that it doesn’t include several of the most important PPAC (Power, Performance, Area and Cost) metrics. However, it does give us a solid timeline of future process nodes from Intel, TSMC, and Samsung. You can also see that TSMC and Samsung also use multiple line extensions of the same node, just like Intel now does as well (for instance, TSMC’s N3B, N3E, and N3P)

Samsung was the first to bring gate-all-around (GAA) transistors to market back in 2022, but its implementation hasn’t been very performant and suffered from poor yields, leading to further market share losses to TSMC. This also highlights that having a technology doesn’t always assure success – the implementation matters.

Intel’s 20A and 18A come with both GAA (PowerVia) and the backside power delivery network (BSPDN), Intel will have backside power delivery two and a half years before TSMC and will also beat TSMC to market with GAA by a year and a half. As we’ve seen with Samsung, which remains the dark horse of the leading-edge foundry industry, having these technologies doesn’t always ensure a win. However, if the critical PPAC metrics align correctly, Intel’s early adoption of these technologies will give it a significant advantage over TSMC.

Finally, as we can see, 14A will mark Intel Foundry as being the first foundry to use the most advanced High-NA EUV lithography machines, with TSMC reportedly waiting until 2030 to adopt the new tools. High-NA will certainly not be an inexpensive path, and an industry report indicates it isn’t as cost effective as using Low-NA EUV with dual patterning. Intel is confident that the cost metrics align within its expectations, but naturally, says it would adjust strategy if needed.

EDA chip design software and a full suite of packaging options

Intel secured four large 18A customer commitments in 2023, and one includes a large prepay for foundry capacity, implying that it is for a very significant quantity of processors. Microsoft has also announced that it will fab a chip on Intel's 18A process, a major buy-in from one of the industry's largest players.

The company has also won design wins across its Intel 16 and Intel 3 nodes and has won significant deals for its Intel Foundry ASAT packaging services, including lucrative advanced packaging contracts with EMIB, Foveros, and Foveros Direct.

The Intel Foundry Services Accelerator program helps chip designers and companies easily adopt Intel’s manufacturing technologies. This program includes 34 partners spread across four alliances: IP, EDA, design services, and USMAG (US Military, Aerospace and Government). This wide range of partners include EDA industry heavyweights like Ansys, Cadence, Synopsys, Siemens and Keysight, along with a wide range of IP partners that include Arm, RISC-V, SiFive, Rambus, and others.

Thoughts

Intel 18A is meant to mark the turning point where the company regains process node superiority over TSMC, and all outward signs point to this node being firmly on track. As noted in our Intel vs TSMC vs Samsung foundry roadmap, Intel will be the first to incorporate backside power delivery into its process nodes, giving it an extensive lead over TSMC on the technology side. Intel will have backside power delivery two and a half years before TSMC and will also beat TSMC to market with GAA by a year and a half. If the critical PPAC metrics align correctly, Intel’s early adoption of these technologies will give it a significant advantage.

As mentioned in the preceding section, Intel Foundry has significant customer wins with all of its foundry offerings. Microsoft has also announced that it will fab a chip on Intel's 18A process, a major buy-in from one of the industry's largest players. 

Intel also has extensive experience in chip packaging and test along with an impressive portfolio of leading-edge packaging technologies for its customers, as we recently saw firsthand when we toured the company’s packaging facilities in Penang, Malaysia, which has led to a sudden increase in packaging contracts for AI chips.

Intel CEO Pat Gelsinger recently noted that five years ago packaging comprised 15% of the total cost of a leading-edge processor, but that has now jumped to 35 to 40% of the total cost. As such, Intel’s advances in its packaging business should not be ignored, particularly given that it also helps the company establish new ties with customers that might elect to also use the company’s chip-making services.

Intel Foundry is also partnering with Arm to bring Neoverse chips to its foundries, a critical step to gaining production volume, and its work with the Department of Defense on the RAMP-C program that has already yielded a billion-dollar award, along with possible future contracts from the US defense industrial base. That’s not to mention its existing partnerships with RISC-V and SiFive, among others.

Intel’s extensive portfolio of EDA and IP partners will now provide industry-standard design tools for Intel Foundry customers, thus offering an easy on-ramp for companies to quickly adopt the Intel process nodes. Paired with a bevy of process nodes and a wide range of packaging services coupled with systems-level design experience, IFS is clearly poised to compete fiercely with TSMC and Samsung for third-party foundry customers in the coming years.

You can read more about those efforts in our interview with Stu Pann, the SVP and GM of Intel Foundry Services, who is tasked with making Intel Foundry the world’s second-largest foundry by 2030.

Intel’s previous struggles to develop new process node technologies resulted in the company eventually ceding its semiconductor manufacturing advantage to its rival TSMC. In the years since, Intel has worked to reverse that deficit with CEO Pat Gelsinger’s audacious turnaround plan, which hinges on delivering five new process nodes in four years. Critically, the plan also hinges on pivoting the company to a new IDM 2.0 philosophy that includes creating a third-party foundry, Intel Foundry Services (IFS), that produces chips for external companies while also allowing the company to retain the inherent advantages of being an IDM.

Intel’s revitalization requires hundreds of billions of dollars in investments that span the globe as it builds out additional chipmaking and packaging capacity to fuel IFS, an organization helmed by Stu Pann, the SVP and GM of Intel Foundry Services, who is tasked with making IFS the world’s second-largest foundry by 2030. 

Tom's Hardware had a chance to speak with Pann in the lead-up to the company’s inaugural IFS Direct Connect 2024 event this week (update: see the roadmap from IFS here now and news about Microsoft's 18A chip), with our interview covering important topics such as Intel’s new tactic of making Arm chips for external customers, the impact of the CHIPs Act, potential development of custom nodes, collaboration plans with UMC and Tower, and the threat of China to the mature node market.

IFS Direct Connect 2024, which kicks off tomorrow, features not only the best and brightest of Intel, like CEO Pat Gelsinger and EVP and GM of Technology Development Dr. Ann Kelleher, but also other industry luminaries, including Microsoft CEO Satya Nadella, OpenAI CEO Sam Altman, Arm CEO Rene Haas, and U.S. Secretary of Commerce Gina Raimondo.

Intel also has a full complement of representatives from its partners and customers, like UMC President Jason Wang, MediaTek President Eric Fisher, and Broadcom’s VP of Central Engineering Yuan Xing Lee, along with representatives from the incredibly important EDA suppliers, such as Synopsys, Cadence, Siemens and Ansys, that will be instrumental in Intel’s efforts to enable a robust set of industry-standard design tools that allow its IFS customers to easily design chips around its new process nodes.

IFS Direct Connect will generate plenty of news around new developments, but today, we have an interesting question and answer session with Stu Pann to discuss several of the latest IFS developments. Pann also spoke about some of the company’s not-yet-disclosed future plans -- but we’ll have to add those additional comments after the embargo lifts tomorrow. 

Paul Alcorn: I know it’s been announced that IFS is open to making Arm chips for quite some time now, but seeing the recent news hit the wire that Intel is now building an Arm chip with Faraday -- it's kind of like a splash of cold water on the face; it’s still surprising to me: You're now doing Arm Neoverse chips on Intel process nodes. Can you tell me how important that is, and about the message that it delivers to the industry?

Stu Pann: I think it's hugely important. If you look at where Arm is at today with the current Neoverse lineup, they're powering all the hyperscalers and TSMC runs those wafers. If we're going to play in that market, we have to have a strong relationship with Arm, and the Faraday announcement that we did with their server infrastructure team is proof that we want to do this kind of business. 

Just the fact that [Arm CEO] Rene Haas and I are going to be on stage talking about the Arm partnership at an Intel conference with 1,100 people in attendance - that’s proof positive that we're serious about doing this business. You can't really go back on this kind of stuff. We're committed, and we're going to move forward. We recognize that Arm has won a lot of sockets, and we want to work with them closely to make sure that whatever they do with Neoverse is optimized for 18A. And expect Rene to say more on that next week [at the event]. 

Paul Alcorn: TSMC creates a custom N4 process node for Nvidia for its GPUs. Is IFS open to doing that level of collaborative work with a third party?

Stu Pann: Absolutely. […] You can't do it just by yourself; you have to do it with an EDA partner. So, our investment with Synopsys and our investment with Cadence absolutely allows for that kind of customization, should a customer want it, but they have to commit to it. It'll be a mutual commitment to go forward. Absolutely, we're open to that. 

We’re already learning so much for our existing customers, like things about process corners, that we didn't realize. And so just the entire foundry engagement is helping Intel, I think, just to be a better company in general, because everybody does things a little differently. You take what you get, and you learn a lot from it, and then you start integrating it into your thinking around process flows and foundational IP. So we're already seeing ways we hadn't thought of to do things better as now becoming pretty clear as people press us for different things.

Paul Alcorn: Intel has recently said that 75% of the fifty IFS customer test chips are currently on 18A. Did you expect such a skew toward the leading edge? You do offer other nodes that aren't necessarily leading edge, but they aren’t mature nodes, either. It seems like the uptake is really on the leading edge of what you're offering. Did you expect more in those other nodes, or do you expect more pickup in those?

Stu Pann: No, this is what we wanted. If you look at 18A as a process technology, it is full-on EUV, and it has backside metal. It was designed from the ground up to be a foundry node with the most complete set of IP around it for processes and tools, flows, and methods. Part of the reason you see both Cadence and Synopsys on stage with us [at the event] is that everyone has a different way of doing things. To be complete, we have to have relationships with all four of the folks that are on stage with us [EDA partners]. 

People mix and match -- I don't want our customers to have to choose to do something differently with a different flow. I’d rather make it easy and friction-free for them to say, “Ok, I can use this place and route from Cadence, and this IP from Synopsys,” or whatever configuration they want. We want to make sure it's available, and we're able to do that fully on 18A. 

Paul Alcorn: IFS has the goal of being the number two foundry by the end of the decade. That's a big goal. Just in terms of sheer scale, do you think that will hinge a lot on this build-out of more mature node capacity with UMC and the collaboration with Tower?

Stu Pann: No, but it does clearly contribute to it. There are some huge wafer BOMs [large volume orders] associated with UMC and the Tower deal. We want to have these mature nodes, and we learn a lot from being engaged with UMC and Tower - and how to do low-cost things. We learn a lot from UMC in terms of doing line extensions, because they do line extensions to all of their products today.

That's a really powerful partnership for us, but our real thrust has to be around 18A. The market price for a 12nm wafer is very different than the market price of an 18A or an N3P wafer. So, if you’re going to get to that kind of goal, you have to be able to build the most high-performance process on the planet, which can then command the best price on the planet. 

Now, clearly, we have to compete with TSMC, and we're going to have to be aggressive on pricing. But it's still a better place to be, and it's got all the attributes we need to be competitive on our own. We have our own process technology, our own packaging technology, and we know how to make the tools work. And we have the ability to compete for that business by applying our systems expertise and helping our customers out, which is something that's unique to us. 

We just have a much higher degree of winning significant customer orders on 18A, which is why we're focused there. [...] I’ll give you an example: You probably know the dates for Samsung's backside power with their 2nm process, and you know TSMCs dates for backside power with 2nm. You'll see our dates, and then you compare and say, okay, where’s Intel at versus where the other guys are. Then you can look at our footprint and our track record and then decide who's likely to be successful with these customers.

Paul Alcorn: Speaking of building capacity brings us to the CHIPs Act. It feels like the US government is taking its time with the subsidies; it's taken a lot longer than most people expected. How instrumental do you think that is as a booster for IFS?

Stu Pann: It's hugely important to us. We’ve worked closely with the CHIPS office. Pat was personally responsible, I think more so than any American executive, in making the CHIPS Act a reality. Since its inception, we've been in the middle of this. 

And yeah, the CHIPS guys who we've worked with really closely are being very diligent stewards of the country’s spending. They've got a very thorough process, they're very well-researched, and they have a lot of questions. They want to make sure that they give us the kind of money that we're asking for and that it's going to be money well spent, and that process takes time. 

This is the biggest piece of industrial policy legislation since World War Two. They’re building the plane as they're flying it right now. And we're hopeful we can conclude some level of agreement with them, but it'll conclude when it concludes. Secretary Raimondo will be the one who says, ‘Okay, I'm now ready to talk about it.’ But the fact that she is coming to the event says that she wants to talk about Intel's role for the US and its allies in terms of being a national champion for US semiconductors. That was the message she delivered on Cramer’s broadcast four or five weeks ago. We'll see what she says next week. But she is keenly interested in making sure that the most important semiconductor supplier in the United States is helped by this effort.

Paul Alcorn: This brings us to RAMP-C. Can you tell me what initiatives like that do and how important is it for the Department of Defense (DoD) and Intel to build that relationship?

Stu Pann: Yeah, during the earnings call, we announced that we had a billion-dollar reward from the US government in terms of supplying advanced semiconductors to the DoD. Where they go, and what they do, we obviously would never talk about, but they don't make a billion-dollar commitment without serious research and serious commitment. Not only on their part, but on the part of the defense industrial base. 

If you look at RAMP-C, Lockheed Martin and Northrop Grumman are a part of it, and Boeing has expressed an interest. All the defense industrial base right now is looking at RAMP-C and what it means very carefully. And in fact, we actually have a government session the day after Foundry Day, just for those customers because they have a very specific set of requirements. So that's been a big deal for us, just for establishing us as a mainstream supplier of the US government in a lot of different applications. 

One of the DoD senior scientists said this kind of capability gives our soldiers an asymmetric advantage on the battlefield because they're now able to use leading-edge technology versus technology that’s ten years old. So, the DoD has been a huge booster because they want this capability for our soldiers and our troops protecting the US national interests.

In terms of the other things that RAMP-C bought us, the announced partners of RAMP-C are IBM, Microsoft, and Nvidia. They're all running test chips, and they’re running test chips with funding from RAMP-C. So they’re able to operate with immature PDKs, which normally they wouldn't do. 

The government funding allows them to operate with much lower-sophistication PDKs than somebody would normally run test chips with. And so that's been really instrumental in helping us learn how our customers view our process/performance, the classic PPAC (power, performance, area, and cost): those test chips tell you what the PPAC looks like. So that gives us at least a head start with those customers in terms of developing a track record, allowing them to use immature PDKs, and covering their expenses. Hopefully that leads to more design wins down the road, but we’re not ready to announce those today.

Paul Alcorn: Can you address the persistent rumors that IFS is doing packaging work with Nvidia, or for Nvidia?

Stu Pann: I can't. I am aware of the rumor. In this business, especially now, our customers are asking for confidentiality; they don't want to disclose. They will decide when and where they want to disclose and what they'll disclose. I’m not speaking with Nvidia in mind, but just generically – all the customers feel that way. When they're ready to talk, they will talk, and they will let us know when they're going to talk. I would love to be more visible, but I also have to respect what they want.

Paul Alcorn: I know you just had the Rio Rancho site come online for advanced packaging. However, IFS is already doing packaging work for its external customers. Where is that packaging taking place? Is that within your existing fab network, and is all of that based in the US?

Stu Pann: The plan right now is to do a lot of the really sophisticated packaging in New Mexico, Oregon, and some in Arizona. Depending on the product and what kind of packaging we're doing, it will oscillate around those. We could do a final assembly and test in Costa Rica, for example, with server [processors], because Costa Rica does the bulk of our assembly/test for our server parts. If somebody wanted a fully integrated, tested, packaged, everything kind of deal, they could do that, but they could also send us TSMC wafers, for example, and we can package them up and get them sent back to their OSAT (outsourced assembly and test) for final assembly/test.

We're willing to configure whatever our customers want us to and do whatever parts of the packaging process they want us to play in, provided we have some form of competitive advantage. We’re winning customers on EMIB, which is Intel proprietary. We’re winning customers based on a technology that really is a Foveros kind of thinking - not the way Meteor Lake is done, but it is hybrid bonding. So, we're working on the supply chains to go do all of that. But we're trying to be as customer-sensitive as we can be.

A lot of customers want at least a ‘Made in the Americas’ kind of setup. And if we do a wafer fab in the US for an 18A logic device, for example, we can package something in the Americas in its entirety without having to have it cross the Pacific Ocean. Now, having said that, we’ll do packaging in Malaysia and obviously open up packaging in Poland over time. So, it'll be resilient, but if you want to dictate a certain flow, if we can make it work in our network, we're sure going to try.

Paul Alcorn: One thing that really sticks out about how TSMC operates is their OIP program, where they have this big arsenal of tools that are available for their customers. Is IFS looking to develop a similar approach or program in that vein?

Stu Pann: I hired the guy that did that program a while ago. We're going to have a slide about that in my deck, which will describe our answer to OIP. The fact that we have 33 ecosystem vendors who have booths everywhere [at the event], it’s just like the duty-free shops in the airport -- you have to walk past all that to get to the main stage.

Paul Alcorn: We’re starting to see a lot of fab build-outs in China, primarily around mature nodes, and a lot of CAPEX is going into that. A lot of industry leaders have signaled an increasing alarm. I think Secretary Raimondo herself has said they're worried about China flooding the market with mature chips. I know in the sphere of big foundry players with extensive mature node capacity, like TSMC or maybe GlobalFoundries, that could potentially really hurt. What about for IFS? How do you think this impacts IFS and its competitive position?

Stu Pann: Yeah, this is mostly mature node stuff. Doing a deal with Tower, where we take advantage of fully depreciated factories and fully depreciated tools, and where they contribute some newer tools to that. We duplicate their process flow, and we give Tower a US-based source of capacity that they could not do on their own for cost and timing reasons. Same with UMC; We have an available building in Arizona, a lot of depreciated tools from our 14nm and 10nm process technology, and we have the people there. And the building is not EUV-capable. So, we have a set of assets, and we are able to sweat those assets more effectively by doing collaboration agreements with them – these aren’t really formal partnerships. Collaborating with them in the supply chain gives us a great cost base, and we can do line extensions in US-based capacity. 

At the end of the day, the mature factories in China are just that -- they're in China. They’re not here. So we can be decently competitive on a cost basis. Now, if they do other methods of pricing, what can we do? But once again, they're in China, not in the US. Tower and UMC do a lot of business with US multinationals, so that’s the play for us. Now, competing with China inside of China? That would be a tough one - but we're not there.

Intel's plan to move 'oversized equipment' for its new fab in New Albany, Ohio, is being delayed, reports NBC4i. The move, which was supposed to start this past weekend, has been pushed back to no earlier than February 17 because of bad weather and the huge size of the 'overweight and oversized loads' of the equipment. The project to move the equipment is expected to last over nine months, meaning this phase of Intel's construction could be done near the end of 2024. There isn't a firm indication of how much work remains to be done at the site after the equipment is delivered. Still, it clearly will take much longer for the plant to become operational: Intel recently confirmed that its initial plans to begin producing chips in Ohio in 2025 were too optimistic. 

Intel needs to transport and install plenty of fab tools at the site in the coming months. The current project involves transporting 18 oversized loads on trailers over 200 feet long, which could take up to nine months to finish. It is unclear which tools Intel will transport, but since the site in Ohio is brand new, it could be anything from advanced lithography machines to turbine generators. 

The equipment is vital for constructing Intel's fab and was initially set to be transported through Franklin County starting Saturday. However, the Franklin County Engineer’s Office has now delayed the start date. Groveport police mentioned that the move might even get pushed to late February or early March, showing there's still some uncertainty on when the move will happen. 

Weather issues, especially a flooded dock in Manchester, Adams County, are partly to blame for the delay. This dock, where the equipment will be taken off barges, is currently underwater, complicating the start of the transport. 

Because the trailers carrying the loads are so large, they cannot go under overpasses, which is why the move requires using back roads, and the exact route they will take has not been announced yet. With a project this big expected to last nine months, the delay in getting started is a notable setback. 

While the setback of a few weeks is rather minor given the long three- to five-year timelines associated with building a modern fab, as Intel recently told us, the company is already facing more significant setbacks on the project.

"While we will not meet the aggressive 2025 production goal that we anticipated when we first announced the selection of Ohio in January 2022, construction has been underway since breaking ground in late 2022, and we have not made any recent changes to our pace of construction or anticipated timelines," an Intel representative told Tom's Hardware. "Typical construction timelines for semiconductor manufacturing facilities are 3-5 years from groundbreaking, depending on a range of factors."

We reached out to Intel to confirm a report that the company is pushing back the timeline for its $20 billion fabs in Ohio to late 2026 due to market issues and delays in U.S. government funding, a story that was originally reported by the Wall Street Journal. The Intel representative neither confirmed nor denied the delay and also didn't provide a firm date for the fab opening. However, the representative did indicate that it is normal for big fab projects to require three to five years. 

"While we will not meet the aggressive 2025 production goal that we anticipated when we first announced the selection of Ohio in January 2022, construction has been underway since breaking ground in late 2022, and we have not made any recent changes to our pace of construction or anticipated timelines," an Intel representative told Tom's Hardware. "Typical construction timelines for semiconductor manufacturing facilities are 3-5 years from groundbreaking, depending on a range of factors." 

Relying heavily on government funds, Intel's first two fabs at its Ohio site, nicknamed the 'Silicon Heartland' by Intel CEO Pat Gelsinger, were originally set to start producing chips next year. But now the project is expected to wrap up construction by late 2026 or even later, the report claims, citing two sources familiar with the matter. WSJ's sources cite two reasons for the postponement: challenges with demand and the slow rollout of the U.S. government funding under the CHIPS Act. 

Intel started to build the first two fabs at its Ohio site in September 2022. Normally, it takes about a year and a half to construct a semiconductor production facility shell and between a year or two (depending on the size of the facility) to install wafer fab tools into that shell. That said, Intel's original plans to start making chips at its Ohio fabs in 2025 were more than reasonable.  

"We remain fully committed to the project and are continuing to make progress on the construction of the factory and supporting facilities this year," the representative explained to Tom's Hardware. "As we said in our January 2022 site-selection announcement, the scope and pace of Intel's expansion in Ohio may depend on funding from the CHIPS Act and other business conditions." 

Currently, 800 people are working on the project, and it is expected that this number will grow significantly by the end of the year, WSJ claims. Yet, it is unclear when the construction is set to be complete and when Intel plans to initiate equipment move-in. 

Intel intends to make its Ohio site a $100 billion semiconductor production hub. The site is projected to host multiple fabs built on Intel's own money, subsidies of the Ohio state, and grants from the government under the CHIPS Act. Ohio has already shown its support with $600 million in grants (on the condition that the fabs will be completed by December 31, 2028) that are available to Intel and which can be used to fund construction costs. 

The delay in the project, while a setback, is part of dealing with the realities of strategic financial planning for large-scale manufacturing. In essence, Intel's Ohio project delay appears to be a strategic response to external funding delays and market dynamics. Intel remains committed to the project, seeing it as a key piece in strengthening its manufacturing prowess in particular and the U.S. semiconductor industry in general.

It is noteworthy that Intel is not the only company that's been said to delay its large-scale fab projects in the U.S. Both Samsung Foundry and TSMC had to delay deployment of their fabs in Texas and Arizona for various reasons.

TSMC admitted in mid-2023 that demand for its chip-on-wafer-on-substrate (CoWoS) has exceeded its production capacity, and the company vowed to double capacity by the end of 2024. But while TSMC is building up its CoWoS capabilities, Nvidia would like to ship as many of its high-demand AI processors as possible — which is why it's tapping Intel to use its advanced packaging technology (in addition to TSMC's), according to a report from money.UDN.com, citing industrial sources. As with all unconfirmed reports, we'll have to take this with a grain of salt until the companies involved comment. The deal is purportedly for 5,000 wafers per month, and according to quick back-of-the-napkin math, that would equate to 300,000 of Nvidia's H100 chips (assuming perfect yield and that the contract is for H100) per month. 

TSMC is projected to remain the main supplier, providing around 90% of Nvidia's advanced packaging capacity. But starting from Q2, Nvidia is also poised to use Intel's capacity for at least some of its products, the report claims. If this information is accurate, adding Intel's capacities will let Nvidia produce more GPUs for AI and HPC workloads, satisfying demand for its existing products quicker. There is a catch, however.

All of Nvidia's current and previous generation products, such as the A100, A800, A30, H100, H800, H200, and GH200 rely on TSMC's CoWoS-S packaging process, which relies on a silicon interposer. The closest advanced packaging technology that Intel has is called Foveros, which also relies on an interposer, albeit a different one (CoWoS-S presumably uses a 65nm interposer, and Foveros uses a 22FFL interposer).  

To use Intel's Foveros, Nvidia will need to validate the technology and then qualify actual products, which will likely have slightly different characteristics (because interposers are made on different process technologies and have different bump pitches) than those packaged by TSMC, so the company's partners will probably also need to qualify them before deployment. If this is the case, it will be interesting to see whether Nvidia outsources only select products to Intel, or all of them. 

Intel is expected to join Nvidia's supply chain in the second quarter, producing about 5,000 Foveros wafers monthly (if the report is accurate). This is quite a significant number for Nvidia alone. To put this into context, TSMC could produce as many as 8,000 CoWoS wafers per month as of mid-2023 (which is when Nvidia consumed the lion's share of this capacity) and aimed to increase the output to 11,000 by the end of 2023 and then to around 20,000 by the end of 2024. If Nvidia gets an additional 5,000 advanced packaging wafers per month, this will give it a significant edge over rivals.  

Outsourcing some of its advanced packaging to Intel Foundry Service can be seen as a strategic move for Nvidia to diversify its supply chain. As an added bonus, by employing IFS's packaging capacities, Nvidia will also ensure that these capacities cannot used by rivals — allowing Nvidia to solidify its position in the market.

A German budget crisis threatened the federal funding of Intel's, TSMC's, and Wolfspeed's fabs as well as multiple other high-tech projects in the country. But as the year comes to an end, the coalition came to an agreement to fund building up these important facilities and this week the government formally announced that investments have been secured.

"The agreement of the 'traffic light coalition' is good for East Germany," said Michael Kellner, Parliamentary State Secretary at the Federal Ministry of Economics, reports Zeit Online (via ComputerBase). "The investments for the transformation projects are secured. With these funds, we secure our future economic power. This benefits our entire country, people like the middle class." 

Previously, Chancellor Olaf Scholz (SPD), Economics Minister Robert Habeck (Greens), and Finance Minister Christian Lindner (FDP) had announced an agreement in the budget dispute, according to Zeit.

"It is an important signal that the investments for the semiconductor industry in East Germany are secured," said Carsten Schneider, the Federal Government's Commissioner for the New Federal States. "Both Intel in Magdeburg and TSMC in Dresden can rely on the Chancellor's commitments."

Germany has pledged $22 billion in incentives to chipmakers, including Intel, TSMC, and Wolfspeed, who agreed to build new fabrication plants in the country. However, the approval of Germany's 2024 Federal Budget has experienced delays due to a ruling by the Federal Constitutional Court, which ruled that the reallocation of unused funds from the Coronavirus crisis to the Climate and Transformation Fund in 2022 was unconstitutional. The German government had planned to use this fund to subsidize chip production, leading to a postponement in the finalization and approval of the budget.

This judicial decision has cast some uncertainty over the funding. Yet, both federal and regional governments remain committed to supporting the establishment of the new fabs, which is why they agreed to fund the projects.

The global foundry industry was on the rise in Q3 2023, led by TSMC, Samsung, SMIC, and Intel Foundry Services (IFS), based on a TrendForce report. The combined revenue of the Top 10 foundries reached approximately $28.29 billion, a notable 7.9% rise from the previous quarter due to a resurgence of demand for smartphones and PCs. TSMC was certainly a star of the report as it continued to dominate the market, IFS made its debut in the Top 10 rankings for the first time in some time, whereas SMIC did not show any particular financial gains from its 2nd generation 7nm ramp for Huawei.

3nm Drives Revenues Up for TSMC

TSMC's revenue reached $17.249 billion in the third quarter of 2023, which allowed the company to claim a 57.9% market share of the whole foundry sector (by revenue). The surge in TSMC's growth can be attributed to the high demand in several key areas, notably in the PC and smartphone markets. Meanwhile, a significant contributor to TSMC's financial success in the quarter was its 3nm fabrication technology, which is used to make Apple's A17 Pro, M3, M3 Pro, and M3 Max processors for smartphones and PCs. As TSMC began to formally recognize its 3nm revenue during the quarter, the technology immediately contributed 6% of its earnings per quarter. Meanwhile, 60% of the foundry's earnings stemmed from its more advanced manufacturing processes (7nm and thinner).

Samsung Foundry is another contract maker of semiconductors who has a 3nm fabrication process in its fleet. Meanwhile, the company only produces smaller chips for cryptocurrency mining on this technology, so the node has yet to become a significant revenue contributor. Samsung Foundry posted a $3.69 billion revenue for the quarter, a 14.1% increase quarter-over-quarter, according to TrendForce. While Samsung attributes this rise to a growing demand for its advanced process technologies (which certainly made a significant contribution), TrendForce believes that Samsung's revenue growth was due to a variety of other factors, including orders for Qualcomm's 5G application processors for mid-to-low range smartphones, 5G modems, and the well-established 28 nm OLED display driver ICs.

7nm Barely Has Impact on SMIC

China's semiconductor champion Semiconductor Manufacturing International Corp. (SMIC) did not make it into the Top 3 foundry's list, though its revenue — $1.62 billion, up 3.8% quarter-over-quarter — was not significantly behind those of GlobalFoundries and UMC, two specialty foundries. But it made quite a breakthrough in the third quarter when it started shipments of Huawei's HiSilicon Kirin 9000S application processor based on SMIC's 2nd generation 7nm process technology. Unfortunately for SMIC, this did not really drive its revenue significantly upwards, based on numbers from TrendForce,

TrendForce attributes this to the shift of SMIC's client base: the share of revenue coming from Chinese customers rose sharply to 84%, driven by the government's emphasis on local sourcing and a surge in orders for smartphone parts from Chinese makers. On the other hand, revenue from American clients saw a decline, attributed to a diversification in the supply chain and the movement of American customers to production locations outside of China. It is possible that the shift in the nature of orders played a role as well, with Chinese firms possibly placing more orders for lower-cost chips compared to their American counterparts.

Intel Is Back to Top 10

A standout development in the contract chipmaking segment is the re-entry of Intel Foundry Services (IFS) into the Top 10 foundries for the first in several quarters. In Q3 2023, IFS reported a revenue of $311 million, marking a significant 34.1% increase from the previous quarter. This substantial growth may be attributed to IFS's collaboration with Amazon Web Services, which ramped up production and assembly of its Graviton4 and Trainium2 system-in-packages in Q3. These SiPs require advanced packaging technologies, such as Intel's Foveros 3D, therefore likely contributing to IFS's recent financial success.

Mixed Bag for Others

Other foundries demonstrated mixed results: some remained flat with the previous quarter, others demonstrated declines of revenues.

GlobalFoundries showed steady performance, with its revenue remaining stable at about $1.85 billion, in line with its previous quarter's earnings. The company's sales were mostly drive by the Internet of Things (IoT) products for home and industrial applications alongside major orders from the U.S. aerospace and defense industries, according to TrendForce.

As for UMC, although its overall revenue dipped slightly by 1.7% to $1.8 billion, the company witnessed a noticeable rise in its 28/22 nm orders. This almost 10% revenue boost from these production nodes helped to offset a minor drop in total wafer shipments.

Tower Semiconductor saw a marginal increase in revenues of 0.3% quarter-over-quarter, essentially maintaining a steady status with $358 million, while Vanguard International Semiconductor recorded a 3.3% increase over the same period to $333 million. 

In contrast, HuaHong Group faced a downturn, with a 9.3% decrease in revenue quarter-over-quarter, dropping to around $766 million. PowerChip Semiconductor Manufacturing Corp (PSMC) also experienced a decline in revenue by 7.5% to $305 million. This was largely due to reductions of nearly 10% and 20% in revenues from PMIC and power discrete products, respectively, impacting its overall financial results, as noted by TrendForce.

The German government is committed to supporting the construction of chip fabs by Intel, TSMC, and Wolfspeed, despite facing financial challenges due to a budget crisis, reports HardwareLuxx. In fact, Intel and Wolfspeed have already received firm funding commitments from the government.

"The decisive sentence is, all projects that we have conceived must be made possible," said Robert Habeck, Minister of Economy, emphasizing strong support for the fab projects.

Germany has committed $22 billion in incentives to semiconductor companies such as Intel, TSMC, and Wolfspeed, leading to commitments to build new fabs in Germany. However, the 2024 Federal Budget in Germany is facing delays due to a decision by the Federal Constitutional Court, which found reallocation of unspent Corona crisis funds to the Climate and Transformation Fund in 2022 unconstitutional. The German government had intended to use this fund to subsidize chip manufacturing, which is why they had to postpone the final discussions and approval of the budget.

This court ruling has introduced uncertainties into the funding, but it looks like both federal and local authorities are dedicated to support the construction of new fabs. There is a strong consensus among political parties and state governments about the importance of these semiconductor projects for the future of German industry.

The government is now looking for ways to fund these projects. They are considering using the current federal budget and possibly suspending the debt brake for this and next year. They are also mulling cutting budgets in other departments. In addition, Saarland, which promised subsidies to Wolfspeed, is facing constitutional legal challenges with its credit-financed fund that demand revisions to its financial planning.

To address these financial challenges, the Bundestag approved a supplementary budget for 2023, allowing for the raising of an additional €45 billion. However, this amount is still not enough to cover the total cost needed for these semiconductor projects and other spending, indicating that the German government still has financial hurdles to overcome.

Intel's biggest foundry customer right now is arguably Ericsson, a company that deals in networking and 5G chips. Ericsson's latest RAN Compute processors are utilizing the Intel 4 process node, the same node that's used for Intel's upcoming Meteor Lake CPU tile, and Ericsson apparently beat Intel to market. This new partnership is the latest bit of good news for Intel's IDM 2.0 strategy, which aims to make Intel the second-best foundry in the world by 2030 — TSMC being first.

That Ericsson was teaming up with Intel to fab processors isn't anything new, as the company announced in July that a future generation of 5G chips would be fabbed on 18A, which is due in 2025. This Intel 4-fabbed processor was actually hinted at all the way back in February 2022 on a roadmap, but we didn't know it was being made on Intel 4 at the time. Now it's official.

According to Ericsson's internal testing, its RAN Compute chips made on Intel 4 use "30 to 60 percent less power compared to industry benchmarks." That info isn't as useful as a chip-to-chip comparison would be, but Ericsson's message is clear enough: Its new processors are very efficient. It's implied that Intel 4 is a key reason why these chips are so efficient, but Ericsson's press release doesn't come out and say it explicitly.

The new chips also have much improved performance, with the high-capacity 6672 and 6372 processors having four times the capacity of their predecessors. The efficiency-focused 6678 and 6671 routers also add AI technology into the mix, which has been 2023's top tech buzzword. Ericsson also boasts about its Open RAN architecture, which seeks to make networking less proprietary, more open, and able to work with a variety of server chips, whether they're running x86 or ARM or something else.

Although AMD is pretty skeptical of Intel's IFS business and its ability to succeed, this Ericsson-Intel partnership is a clear win for Intel. It also won a defense company contract for 18A chips back in 2021, an order from a big datacenter client to make processors on the Intel 3 node in January of this year, and last April even scored a deal with Arm to fab smartphone chips on 18A. If IFS continues to bear fruit, Intel could be in great shape over the coming years.

Subsidies that multinational chipmakers are set to receive to build their fabs in Europe will come from two sources: the European Union itself, as part of the European Chips Act approved in July, and individual states. So far, Germany has promised $22 billion in incentives to chipmakers like Intel and TSMC, which is why the companies announced plans to build fabs there. But it looks like a stalled German budget approval has slowed down billions for the chipmakers, according to a report from ComputerBase.de.

Both Intel and TSMC vowed to invest billions in their projects in Germany, so without timely government money, the companies may need to invest additional money themselves (i.e., increase their CapEx or reallocate funds from other projects), scale down their projects, slow buildout, or find additional investors.

The German Federal Budget for 2024 has been delayed in response to a ruling by the Federal Constitutional Court, which deemed reallocation of unused Corona funds to the Climate and Transformation Fund in 2022 as unconstitutional. The German government planned to use the Climate and Transformation Fund to subsidize chipmaking as these are sustainable economic projects — but now that it cannot be done, the ruling coalition (consisting of the SPD, Greens, and FDP) has postponed the final discussions and approval of the budget.

This means that the budget will not go to the Bundestag for a vote next week (as planned) and will most likely no longer be signed by the Federal President in time before the end of the year. While the coalition aims to finalize the budget within the year, the exact timeline for the approval of the 2024 budget remains uncertain due to these complications.

Given the delay and revisions in the budget thanks to the constitutional court ruling, all areas of government spending, including potential subsidies for chipmakers, might be under review. This could lead to adjustments in the allocation of funds or even the cutting of subsidies altogether. This means that Intel and TSMC may not get subsidies on time — or at all — next year, which will have implications on how the companies conduct business. But at this point it is hard to tell how exactly the German budget crisis will affect Intel, TSMC, and others.

A senior AMD executive has implied that the most significant strategic change implemented at Intel under the stewardship of Pat Gelsinger was misguided. Intel's newfound enthusiasm for being a contract chip manufacturer for other companies, a key part of its IFS strategy, goes against the grain for a successful modern chip design company, hinted Darren Grasby, EVP for strategic partnerships and president of AMD EMEA. Grasby's comments on Intel's strategy, highlighted by The Register, were made at the recent Canalys EMEA Forum 2023. When asked whether or not Intel's IFS strategy will succeed, AMD's exec responded "Of course not."

AMD's business has made strides in recent years, and its fortunes have enjoyed particular growth since it divested in manufacturing. It has also started to look increasingly strong compared to its Goliathan rival, with first-mover advantages in more refined semiconductor processes, pioneering multi-chip packages, and adding potent iGPUs. 

During the aforementioned forum, Grasby said that AMD's choice to go fabless was "the turning point of the company that allowed us to invest those R&D dollars into the roadmap." That implies Intel could enjoy greater success if it did the same. Grasby's key observation was that strategic R&D investments made in products end up being the ones that bring the best returns.

Failure or Passing Grade?

During questioning at the Canalys EMEA Forum 2023, Grasby delivered a direct and damning comment on AMD's biggest CPU-making rival and its current strategy. Asked whether the Intel IFS strategy will succeed, the AMD exec bluntly responded, "Of course not."

Last week, Pat Gelsinger was reportedly quite uncharacteristically humble about Intel's IFS venture, saying, "I would give us a passing grade, two and a half years into the [IFS] journey."

Intel's significant investments in production facilities at home and worldwide might look a little scary. However, it is using government funding to take some of the risk out of these massive investments.

At home and abroad, we have seen CHIPS Act-style funding grasped by Gelsinger on tour. The extra billions in backing and the will of the states involved should help make these significant industrial initiatives more likely to succeed. Moreover, news indicates that Intel has high-profile customers lined up. We've previously reported on its courting of the fourth largest chip designer, MediaTek. It also already has some prepay 18A IFS customers, and Intel-built Nvidia GPUs are looking more likely.

When Intel and Tower Semiconductor terminated a merger agreement in August, the two companies said they would find a way to collaborate going forward. Well, the two companies announced on Tuesday that Intel Foundry Services would produce chips for Tower. 

Under the terms of the deal, Tower commits to investing as much as $300 million to purchase wafer fab tools and other 'fixed assets' that will be installed at Intel's Fab 11X in Rio Rancho, New Mexico. In exchange, Intel will provide a "capacity corridor" of more than 600,000 photo layers monthly to accommodate Tower's anticipated expansion. 

For now, Intel will make power management chips for Tower using its 65nm power management BCD (bipolar-CMOS-DMOS) flows, but the two companies also mention 'other flows at Intel's Fab 11X.' This collaboration will pave the way for Tower's increased capacity and ensure it can meet the projected customer needs for 300mm advanced analog processing.

"This collaboration with Intel allows us to fulfill our customers' demand roadmaps, with a particular focus on advanced power management and radio frequency silicon on insulator (RF SOI) solutions, with full process flow qualification planned in 2024," said Russell Ellwanger, chief executive of Tower. "We see this as a first step towards multiple unique synergistic solutions with Intel." 

Tower's 65nm BCD technology provides clients with enhanced power efficiency, reduced die size, and cost savings due to its top-tier Rdson performance metric. The expanded capacity from this deal will allow Tower to tackle bigger projects using current technologies and strengthen collaborations with top-tier industry clients, paving the way for robust future technology blueprints.

"We launched Intel Foundry Services with a long-term view of delivering the world's first open system foundry that brings together a secure, sustainable, and resilient supply chain with the best of Intel and our ecosystem," said Stuart Pann, Intel senior vice president and general manager of Intel Foundry Services. We are thrilled that Tower sees the unique value we provide and chose us to open their 300mm U.S. capacity corridor."

Due to regulatory approval challenges in China, Intel Corporation and Tower Semiconductor have jointly chosen to halt their acquisition discussions. As a result, Intel will compensate Tower with a $353 million termination fee. Despite this setback, Intel remains committed to its foundry initiatives, Intel Foundry Services (IFS), and has expressed interest in potential future collaborations with Tower.

When Intel announced plans to take over Tower Semiconductor in February 2022, the deal made great strategic sense for its Intel Foundry Services division. Firstly, the company would gain seven fabs tailored to build products on specialized nodes. Secondly, IFS would gain dozens of specialty process technologies. Thirdly, IFS would acquire tens or hundreds of customers with long-term contracts. Fourthly, Intel would get many seasoned foundry industry veterans with vast experience in contract manufacturing of chips, something the company does not have. Finally, IFS would immediately find itself in the Top 10 foundries list should it absorb Tower Semiconductor.

Some would argue that without 150-mm and 200-mm mature process technologies, clients with long-term contracts, and management with vast experience in the foundry business, it will be considerably harder for IFS to grow and become the world's second-largest foundry by 2030. Furthermore, after failing to acquire GlobalFoundries in 2021 and Tower Semiconductor in 2023, Intel will have to focus entirely on serving customers who need leading-edge production nodes, at least until its own technologies mature, which means cut-throat head-to-head competition against mighty TSMC and Samsung Foundry. But Intel remains quite optimistic about its foundry division future primarily because it is the only company that can offer vertically integrated services, from wafer-in to product-out.

"Since its launch in 2021, Intel Foundry Services has gained traction with customers and partners, and we have made significant advancements toward our goal of becoming the second-largest global external foundry by the end of the decade," said Stuart Pann, senior vice president and general manager of Intel Foundry Services (IFS). "We are building a differentiated customer value proposition as the world's first open system foundry, with the technology portfolio and manufacturing expertise that includes packaging, chiplet standards and software, going beyond traditional wafer manufacturing." 

So far, IFS has been having quite a bumpy ride. On the one hand, Intel's collaboration with the U.S. Department of Defense, Arm, and MediaTek showcases its expanding footprint in the industry. Notably, Intel secured a pivotal role in the Department of Defense's RAMP-C initiative. Furthermore, it entered into a comprehensive agreement with Arm to optimize Arm's IP for IFS's upcoming 18A process technology (1.8nm-class). In addition, MediaTek is now committed to using Intel's leading-edge nodes.  Perhaps most importantly, the company is now building advanced fabs in three parts of the world: the U.S., Europe, and the Middle East.

On the other hand, IFS generated $786 million in revenue in 2021 and lost $23 million that year. Still, in 2022 it earned $703 million (after restating its revenue and losses for Q1 and Q2 in 2023) and lost $291 million (after restatements). So far this year, Intel's foundry unit generated $415 million in revenue (up 13% from H1 2021 and up 94% from H1 2022), but lost $283 million. Furthermore, two years after inception, only MediaTek has committed to using IFS's leading-edge fabrication technologies (which is not a big problem per se).

In general, the success of IFS now fully depends on how competitive Intel 20A and Intel 18A nodes are and whether there is enough support from EDA and IP developers to enable flawless usage of these technologies by fabless chip designers.

"We are executing well on our roadmap to regain transistor performance and power performance leadership by 2025, building momentum with customers and the broader ecosystem and investing to deliver the geographically diverse and resilient manufacturing footprint the world needs," said Pat Gelsinger, CEO of Intel. "Our respect for Tower has only grown through this process, and we will continue to look for opportunities to work together in the future."

Intel and Synopsys this week extended their EDA and IP partnership to the company's Intel 3 and Intel 18A manufacturing technologies. In line with the agreement, Synopsys is set to develop its standardized interface IP for Intel's 3nm and 1.8nm-class production nodes, which will be beneficial for Intel Foundry Services (IFS) customers adopting these fabrication processes. Meanwhile, a standout aspect of this announcement is Intel's intention to extend its 3nm-class node to a wider array of external clients.

While chip designers tend to invest a lot into differentiating their IP, most of them tend to license IP-like interfaces and memory controllers. To that end, the availability of an industry-standard IP portfolio of interfaces from Synopsys is crucial for the success of new process technologies, such as the upcoming Intel 3 and Intel 18A, as it enables chip developers to streamline their work and shrink the time-to-market. Unfortunately, it is unclear when exactly Synopsys is set to be ready with its IP for Intel 3, even though that is set to be ready for manufacturing this year. Intel 18A has a bit more time, as it's set to be ready for production in 2H 2024.

The intriguing part is that Intel is now extending its IFS offerings to the Intel 3 fabrication process, which is a major refinement of its Intel 4 node and does not use any of the company's ambitious innovations like gate-all-around RibbonFET transistors or the backside power rail called PowerVia. Compared to its predecessor, Intel 3 promises a 18% higher performance per watt, a denser high-performance library, reduced via resistance, and increased intrinsic drive current, which is beneficial primarily for datacenter system-on-chips. Indeed, Intel has announced zero Intel 3-based client products so far, but three datacenter SoCs: Xeon-branded Granite Rapids and Sierra Forest processors, as well as a custom SoC for a major cloud datacenter provider.

The extension of the IP partnership with Synopsys will enable Intel to make its Intel 3 node — a fabrication technology that Intel barely advertised as an offering for IFS customers — more accessible to a wider range of interested parties. That also implies that there are potentially such interested parties.

As for the Intel 18A node, this is a superior version of the company's Intel 20A process technology that promises up to a 10% improvement in performance per watt, a refined RibbonFET architecture, and line width reduction, which implies a higher transistor density. It will be crucial for Intel 18A to have industry-standard interface IP readily available as soon as possible, as developing things like memory or PCIe controllers and PHY on a 1.8nm node is both expensive and time consuming.

Intel's proposed acquisition of Tower Semiconductor has been approved by regulators across the world except in China, which is why the deal has not closed nearly 19 months after its announcement in mid-February of 2022. The deadline for Intel to close the deal after another extension is tomorrow, August 15, 2023, but the two companies cannot close it without approval from China. Meanwhile, it is unclear whether the companies will extend the closure period and refile with other regulators.

When Intel originally announced plans to take over Tower Semiconductor, it said that it would close the transaction in 12 months, by mid-February, 2023. But because China's State Administration for Market Regulation (SAMR) had not approved the deal, the companies extended the acquisition period until mid-June and then extended it again to August 15. So far, SAMR has not formally greenlit the transaction and if it does not OK it by tomorrow, Intel and Tower will either have to extend the closure period one more time, or call the deal off.

Pat Gelsinger, chief executive of Intel, recently flew to China in a bid to convince Chinese regulators to approve the deal, but the outcome is currently unknown. Since the Chinese semiconductor sector is suffering from major sanctions from the U.S. government, China's government is not really inclined to support Intel's plan to acquire Tower and its dozens of customers and mature fabrication processes. Tower competes against China-based contract chipmakers, such as SMIC and Hua Hong, whereas Intel Foundry Services (IFS) division is barely competing against these foundries. Yet, once Tower becomes a part of Intel, the new entity would be a formidable rival for Chinese chipmakers.

To that end, SAMR is slowing down approval of the deal, even though it does not create a monopoly of any kind. In theory, companies can agree to extend the closure period of an acquisition for as long as they mutually decide. However, in practice, there are several factors that limit the feasibility of indefinitely extending the closure period.

For example, in many jurisdictions, regulatory bodies approve mergers and acquisitions for certain periods. If companies keep extending the closure period, it might raise red flags or lead to additional scrutiny. It is possible that to prolong the closure periods, Intel and Tower will have to refile their proposals with regulators in the USA or Europe if the transaction is not approved in China by August 15.

Intel has one day left to close the Tower Semiconductor acquisition, extend the closure period, or cancel plans to take over the contract maker of chips. 

Backside power delivery network (BS PDN) for next-generation chips is a well-known and widely discussed advantage of future process technology. While Intel and TSMC have talked about BSPDN for a while, Samsung only recently shared details about its backside power delivery experiments. It appears the company expects quite noticeable advantages from this innovation.

In a paper presented at the VLSI Symposium in late June, Samsung Electronics reported that the application of a backside power delivery network resulted in a 14.8% reduction in the area of an undisclosed processor compared to the traditional frontside PDN, reports The Elec (via @harukaze5719). Meanwhile, the paper specifically highlighted two Arm circuits, where they observed area reductions of 10.6% and 19%, respectively. A 10% to 19% die area reduction is a major advantage as it enables one to either pack 10% to 19% more transistors and gain performance or reduce the costs of a given chip.

Another thing that Samsung mentioned in its paper was a 9.2% reduction in the wiring length. The backside power rail typically enables thicker wires with lower resistance and, therefore, can drive higher currents for higher performance. A further reduction of wiring length will also bring additional performance advantages.

Additional benefits facilitated by backside power delivery that Samsung revealed were design technology co-optimization knobs that enabled 3.6% Fmax improvement, a 2.4% reduction of standard block area, and 1.6% standard block performance improvement.

Earlier this year, Intel detailed its PowerVia backside power delivery network that will be used for its 20A (2nm-class) fabrication technology and beyond. The benefits of using a backside power rail are widely recognized, and Samsung's findings prove the theory. Power wires can be made more substantial by shifting power rails to the rear and isolating them from I/O wiring. This thickening reduces resistances in the final production stages, enhancing performance and decreasing energy use. Additionally, this separation leads to a reduced logic area, resulting in cost savings.

Samsung has not disclosed when it plans to implement its BS PDN and with which node. The company is currently polishing off its 2nd Generation 3nm-class gate-all-around transistors-based SF3 fabrication technology and aims to use it for mass production in 2024. The company also has SF3P and 2nm-class SF2 due in 2025. While it is unlikely that Samsung will use a backside power rail for SF3 next year, the company may consider implementing its BS PDN in SF3P or SF2 in 2025.

The European Council on Tuesday formally approved European Chips Act, a regulation aimed to strengthen semiconductor sector in the bloc and increase market share of chips produced in Europe from around 10% today to approximately 20% by 2030. The program will provide €43 billion ($47 billion) to chipmakers building new fabs in Europe. This is the final step in the decision-making procedure.

The European Chips Act is meant facilitate development of the European semiconductor industry by providing subsidies, attracting investments, and encouraging research and development. The program is designed to 'mobilize' €43 billion, including €3.3 billion from the EU budget, in public and private investments to achieve these goals.  

The ultimate objective is to double the EU's global market share in semiconductors from the current 10% to 'at least' 20% by 2030. In addition, the initiative also aims to strengthen the domestic semiconductor supply chain and prevent chip shortages in critical sectors such as the automobile industry, something which happened in 2020 – 2021.

The very decision of the European Union to provide incentives to chipmakers has already made chipmakers to revisit their position regarding building chips in Europe. Intel has committed to build a leading-edge fab near Magdeburg, Germany, and an advanced chip packaging facility in Poland, whereas TSMC is expected to announce a specialty fab producing MCUs for automakers on the German soil in the coming weeks.

"With the Chips Act, Europe will be a frontrunner in the world semiconductors race," said Héctor Gómez Hernández, Spanish Minister for Industry, Trade and Tourism. "We can already see it in action: new production plants, new investments, new research projects. And in the long run, this will also contribute to the renaissance of our industry and the reduction of our foreign dependencies."

Among other things, the European Union is aiming to reduce dependence on foreign-made advanced processors for supercomputers. Nowadays such CPUs and SoCs are produced in the U.S., Taiwan, or South Korea. 

To do so, the European Chips Act is intended to attract companies like Intel, Samsung Foundry, and TSMC to make such advanced products in Europe. Meanwhile, contrary to initial plans to fund solely state-of-the-art fabrication facilities, the EU authorities have broadened their focus to include the entire supply chain, supporting mature chip production and research and development centers too.

The regulation, already adopted by the Council and the European Parliament, will come into force three days after being published in the Official Journal of the European Union.

AMD transferred production of virtually all of its substantial products to TSMC in the recent years and it is in no hurry to add other manufacturing partners, according to Lisa Su, chief executive officer of AMD, who recently visited Taiwan. Despite rumors that AMD might shift some of its orders to Samsung Foundry, the head of AMD does not seem to be ready to make any concrete comments on the matter. 

"We typically do not publicly comment on the details of specific products and orders, but TSMC is an important partner," Su said in Taiwan when asked to comment on the rumors about working with Samsung Foundry, according to a report by BusinessKorea. "The Instinct MI300, a world-class accelerator for generative AI that AMD plans to launch later this year, has high complexity."

While on paper fabless chip designers can work with multiple foundries, this is usually associated with a lot of curbs. First, modern process technologies from different contract chipmakers are not compatible — a 5nm-class chip made by TSMC has to be redesigned to be produced at Samsung Foundry. When we are dealing with complex products such as AMD's Instinct MI300, such redesign costs may get too high. 

Second, fabless chip developers tend to reuse IP across different product lines to save costs and usage of multiple foundries limits this capability or at least reduces its appeal. Third, when you buy in huge volumes from one supplier, you are going to enjoy various benefits, including tailoring of process technologies for your needs and discounts. Of course, some companies — such as Qualcomm — can afford to work with multiple contract chipmakers and benefit from it, but this is because they buy huge amount of chips from everyone. 

"We will continue to work with our Taiwanese partners because we cannot launch this product without good partners like TSMC," Su added, underlining the importance of TSMC for the company. 

However, Su sounded less resolute when she visited Tokyo later that week. 

The head of AMD told Nikkei that the company would "consider other manufacturing capabilities" besides TSMC to produce its chips to "ensure that we have the most resilient supply chain."

Meanwhile, TSMC is building up fabs in the U.S. and Japan, which will inevitably ensure resiliency of its supply chain. Therefore, AMD may not be exactly inclined to work with TSMC's rivals like Samsung Foundry and Intel Foundry Services for the reasons mentioned above. At least for now.

Intel Foundry Services has introduced a broad range of tools for customers of its new 16nm-class process technology called Intel 16 that addresses mobile, RF, IoT, consumer, storage, military, aerospace, and government applications. The new technology complements Intel's 22nm FFL process and is said to be an inexpensive FinFET-based node.

According to press releases from Synopsys, Cadence Digital, Siemens, and Ansys, the companies now have a range of tools for IFS's Intel 16, which is specifically designed to address a wide variety of customers' applications RF and analog capability (Wi-Fi, Bluetooth), mmWave, consumer electronics, storage, military, aerospace, and government applications. The 16nm-class technology promises to offer higher transistor density, higher performance, lower power, fewer masks, and simpler back-end design rules compared to planar production nodes used for these applications today.

There are hundreds of widely used applications with long lifecycles that rely on mature process technologies, particularly in fields like application processors, controllers, analog, consumer electronics, and radio. Many of them use planar transistors-based process technologies due to costs, design simplicity, and high yields. While industry experts at large tend to admire massively powerful processors like AMD's Instinct MI300 or Nvidia's H100, there are plenty of chips — even in industries like artificial intelligence and high-performance computing — that are considerably smaller and consume only a fraction of power.

In many cases, these mature and emerging applications can still benefit from newer FinFET-based production technologies, which is why TSMC offers its N12e node, whereas IFS is now rolling out its Intel 16 process technology.

All four leading providers of electronic design automation (EDA) and IP — Ansys, Cadence, Siemens, and Synopsys — already support Intel 16 process technology with their certified software flows and IP. For example, Cadence has ported a variety of its IP blocks to Intel 16, including PCIe 5.0; 25G-KR Ethernet multi-protocol PHY; multi-protocol PHY for consumer applications supporting standards such as PCIe 3.0 and USB 3.2; multi-standard PHY for LPDDR5/4/4X memory; andMIPI D-PHY v1.2 for cameras and displays. Meanwhile, Synopsys offers its AI-enabled Synopsys.ai set of tools for faster chip implementation.

Fabless chip developers can start using design, verification, and simulation tools to produce their designs.

Intel on Monday detailed its implementation of a backside power delivery network (BS PDN) that will be a part of its Intel 18A and 20A (18/20 angstroms, 1.8/2.0nm-class) fabrication processes. In addition, the company also revealed more information about the benefits this technology provided for its internal Intel 4 + PowerVia node designed specifically to best BS PDN.

Backside Power Delivery

Intel's 18A and 20A manufacturing technologies will introduce two key innovations: RibbonFET gate-all-around field-effect transistors (GAAFETs) and PowerVia backside power delivery network. The advantages of GAA transistors have been discussed previously and are beyond the scope of today's announcement. We'll focus instead on backside power delivery.

The backside power rail aims to separate power and I/O wiring, shifting power lines to the back of the wafer. This method tackles problems such as increased via resistances in the back-end-of-line (BEOL), ultimately improving the performance of transistors and lowering their power consumption. It also eliminates any possible interference between the data and power wires and increases logic transistor density.

Over time, BD PDN will become a standard chip feature, but for now Intel considers it a major breakthrough innovation akin to strained silicon at 90nm in 2003, Hafnium-based high-K metal gate at 45nm in 2007, and FinFET at 22nm in 2012.

Intel says that when implemented in a test chip on an internal process node, its backside PDN enabled it to increase clock speed by over 6%, reduced IR voltage droop by 30%, and increased cell utilization over large areas of its E-core die to over 90%. Despite the benefits, implementing and building a backside power delivery is a challenge for several reasons. 

Building PowerVia Backside PDN

Building a backside PDN is very different from traditional frontside power delivery. Production of even the most advanced chips is pretty straightforward these days. Fabrication of every wafer starts from the most complex M0 transistor layer with pitches as small as 30nm (for Intel 4 node) using the most sophisticated manufacturing tools like EUV scanners. Then chipmakers build less complex transistor layers on top of the first one, gradually increasing sizes as they need to connect all the layers and power all the transistors.

The actual physical wires for I/O and power look gigantic when compared to the transistor layers, and it gets harder and costlier to route them properly with every new generation.

Processing a wafer with chips featuring Intel's PowerVia BS PDN involves producing all the complex logic layers as well as signal wires, then flipping the wafer and building the power delivery network 'on top' of the logic. On paper, such a 'flip' does not look like a big deal. However, it adds quite a number of process steps, including removal of 'excess' silicon from the wafer to build the PDN on top of the logic transistors, CMP clean, metrology, lithography, and etching, to name a few.

Such a process loop may not require the most advanced tools in the fab, but it still costs money. Indeed, an Intel slide indicates that the Intel 4 process technology uses 15 metallic layers and a redistribution layer (RDL), whereas Intel 4 + PowerVia uses 14 front side layers, four back side layers, and an RDL, which increases total number of layers to 18 + RDL.

"Transistors are built first, as before, with the interconnect layers added next," said Ben Sell, vice president of Technology Development at Intel. "Now the fun part: flip over the wafer and polish everything off to expose the bottom layer to which the wires […] for power will be connected. We call it silicon technology, but the amount of silicon that's left on these wafers is really tiny."

There are several factors to consider with a backside PDN. First up, it changes the manufacturing process drastically, so Intel had to find a way to ensure high yields despite radical changes. Second, Intel had to ensure that the backside PDN is as reliable as its current PDN and performs as intended. Third, as I/O and power wires are now located on both sides of transistors, it will get more challenging to cool down chips going forward. Fourth, it gets significantly harder to debug chips as now Intel has to remove backside power interconnects to access transistor layers.

There is another peculiarity about Intel's PowerVia process too. Because Intel removes excessive silicon from the back of the wafer, it believes it loses rigidity, which is why it bonds a carrier wafer on the signal side of the wafer to hold the construction together. That carrier wafer also gets thinned down eventually, but its addition is also a complicated (and probably necessary) process step.

Another thing about Intel's PowerVia backside PDN is that it doesn't use buried power rails with BS PDN, but instead will rely on nanoscale through silicon vias (TSVs) to deliver power right to the transistor layer. This is obviously why the company calls its technology PowerVia.

Testing Backside Power Delivery Network

Now that Intel is no longer the indisputable leader of the chip market with the best process technologies, the company could not risk a potential point of failure in one of its next generation nodes. So, it decoupled development of RibbonFET GAA transistors and PowerVia BS PDN to make the development process a little bit easier by working on RibbonFETs with a regular PDN and then debugging PowerVia with proven FinFETs.

To test its PowerVia backside power delivery network, Intel built a special manufacturing process based on its Intel 4 node that uses proven FinFET transistors, but it comes with a backside power rail instead of a traditional power rail. This process is naturally called Intel 4 + PowerVia and it is used for one test chip codenamed Blue Sky Creek.

Intel's Blue Sky Creek test chip uses two dies, each featuring four energy-efficient cores based on the Crestmont microarchitecture. These are designed to operate at 3 GHz at 1.1 Volts. The test vehicle was designed for two purposes only: explore the advantages of the PowerVia BS PDN and remove risk from the future 20A/18A process technologies by testing all of the things associated with the novel power delivery network, including yields, reliability of PDN and the chip, cooling, and debugging.

When it comes to yields, Intel says that the defect density of the test chip implemented on Intel 4 and on Intel 4 + PowerVia are nearly the same. Reliability and transistor characteristics goals also met expectations required for production. Furthermore, thermals of the test vehicle were in line with expectations. Meanwhile, Intel admits that cooling will be a challenge with backside PDN, so it has developed new thermal mitigation schemes to cool down next-gen chips.

"Normally you use the silicon side also for heat dissipation," explained Sell. "So, now you have sandwiched your transistors and the question is, 'Do we have a thermal problem? Do we get a lot of local heating?' At this point you can probably guess the answer: no."

Debugging was arguably one of the most complicated parts, but luckily Intel's validation engineers have found a way to overcome the difficulties.

"There were a lot of concerns and hesitancy and that was probably the hardest thing to figure out — how to do debug on this new backside power delivery," said Sell. "To make things even more challenging, the test chip design team intentionally added some 'easter egg' errors to the chip, unbeknownst to the validation team. The good news? They found the bugs. We have made tremendous progress over the last couple of years in developing those debug capabilities and proving them on Blue Sky Creek."

Intel's PowerVia BS PDN Coming in 2024

Intel's first publicly available process technologies to use its PowerVia backside power delivery network will be its 20A and 18A nodes that will be production ready in 2H 2023 and 1H 2024, respectively. Intel's first client CPU to be made on the 20A fabrication process is Arrow Lake, which is expected to launch near mid-2024 or earlier.

Intel's 18A and 20A manufacturing technologies are developed both for the company's own products and for customers of Intel Foundry Services, so PowerVia promises to be a benefit both for Intel and its IFS clients. Whether or not PowerVia BS PDN will be a tangible benefit is something only time will tell, but it is noteworthy that Intel is the first company that is ready to make chips with backside power delivery, as TSMC is only expected to offer a similar technology in late 2026 to early 2027.

Intel's backside power delivery network (PDN) dubbed PowerVia is expected to be one of the main advantages of Intel's upcoming 18A and 20A process technologies. To learn how to implement it and demonstrate its advantages to parties interested in using Intel Foundry Services, the company implemented it in a test chip that is produced on its Intel 4 node, previously known as 7nm. 

Intel's experimental chip with backside power delivery is based on unnamed energy-efficient 'E-cores' (we would speculate about Crestmont, though this is an educated guess at the moment) and is implemented on the Intel 4 process technology. Intel's findings, which will be revealed at the 2023 Symposium on VLSI Technology and Circuits, showed that Intel's PowerVia enabled an over 90% standard cell utilization in large portions of the core, while also providing a more than 5% clock speed improvement due to reduced IR drop. An image that Intel is set to demonstrate seems to prove the point, though it is impossible to evaluate how a similar core will behave in real-world workloads.

"Post-silicon debugging was successful, with slightly increased but still acceptable throughput times," a description of the presentation reads. "Moreover, the thermal properties of the PowerVia test chip were in line with the higher power densities anticipated from logic scaling."

Backside PDN aims to separate I/O and power wiring by relocating power rails to the backside of the chip, which helps address issues such as increased via resistances in the back-end-of-line (BEOL). This enhances transistor performance and reduces power consumption, while also eliminating potential interference between data and power connections. In addition, decoupling PDN and data wires contributes to area reduction, potentially leading to higher transistor density compared to existing production nodes. 

For now, the only thing that Intel is set to demonstrate in mid-June is that its PowerVia PDN works and can improve frequency as a result of reducing IR. This leads to the conclusion that Intel's next-generation 18A and 20A process technologies will have at least one proven advantage over competing production nodes that will rely on traditional power delivery in the 2024 – 2025 timeframe.

The European Union has agreed on the plan to invest €43 billion ($47 billion) in its semiconductor sector in a bid to significantly increase production of chips locally and bring in advanced fabrication processes to its member countries. The move is also designed to build up the local semiconductor supply chain and avoid chip shortages for important sectors such as automotive.

"We have a deal on EU #ChipsAct," Thierry Breton, European Commissioner on internal markets tweeted. "In a geopolitical context of de-risking, Europe is taking its destiny into its own hands. By mastering the most advanced semiconductors, EU will become an industrial powerhouse in markets of the future."

Nowadays only around 10% of chips produced globally are made in the European Union. Meanwhile, most of the chips for EU's automotive, IT, and telecom industries are made outside of Europe, which creates challenges for companies like Ericsson, Volkswagen, and Nokia. The European Chips act is designed to increase the share of chips produced in the EU to 20% (by value) by 2030.

One of the things that the European Union is particularly concerned about is that all advanced processors, such as those that power world's fastest supercomputers (including Finland's Lumi, the most powerful supercomputer in Europe) are made either in the U.S., Taiwan, or South Korea. The European Chips Act is designed to lure chip manufacturers with leading-edge process technologies to the bloc.

Meanwhile, it's not just leading producers who will get money from the EU. While originally the European Commission suggested financing solely state-of-the-art fabs, by now EU authorities and legislators have expanded the range to encompass the entire value chain, incorporating mature chip production and research and development centers, reports Reuters.

"The European vision to double our global market share by 2030 to 20%, and produce the most sophisticated and energy-efficient semiconductors in Europe, is already attracting substantial private investment," Breton said in a statement published by Bloomberg. "Now we are mobilizing considerable public funding and the regulatory framework to turn this vision into reality."

In the past, year EU member countries have already done quite a lot to attract leading chipmakers. Intel will continue to use its most advanced production nodes at its Ireland fabs and will build an all-new production campus in Germany, where it will make its most advanced processors.

"We have a Chips Act," said Margrethe Vestager, Executive Vice-President of the European Commission for a Europe fit for the Digital Age, in a Twitter post. "We need chips to power digital and green transitions or healthcare systems. Lots of promise and a lot of day-to-day convenience. Today's Trilogue agreement boosts EU capacity to produce our own chips. And to be a partner in the global chips supply chain."

By now, all major chip producing countries, including Taiwan, South Korea, Japan, and the U.S., have either legislated their semiconductor funding laws, or are about to pass them. As a result, it's not going to be easy for EU to catch up with the market leaders.

Arm and Intel Foundry Services on Wednesday announced plans to conduct design technology co-optimization (DTCO) and system technology co-optimization (STCO) for Arm's mobile IP on the Intel 18A fabrication technology (1.8nm-class). The plan will enable clients of Arm and IFS to maximize performance, lower power consumption, and optimize die sizes of their upcoming SoCs involving Arm's IP.

Under the agreement, Intel Foundry Services and Arm will co-optimize Arm's IP and Intel's 18A fabrication process to increase the performance, power, area, and cost advantages of the new node. The two companies will initially focus on mobile SoC designs, but may eventually expand their collaboration to automotive, aerospace, datacenter, Internet of Things, and government applications. As part of the pact, Arm and IFS will develop reference design and optimized process developers kits for mobile SoCs.

Modern chip manufacturing technologies and processor designs are extremely complex and expensive. To maximize advantages of each new node for a particular design, foundries and chip developers these days optimize transistor design, libraries, standard cells, chip layout, and interconnects — just to name a few of the things involved in DTCO methodology. 

When it comes to Intel's 18A fabrication process, there are a lot of things that can be optimized on node and design level to extract more PPAC advantages out of the node. One of the key innovations of Intel 18A is usage of gate-all-around (GAA) transistors that Intel calls RibbonFET. In GAA transistors, the channels are horizontally oriented and completely enclosed by gates. These GAA channels are created through epitaxy and selective material removal, enabling designers to fine-tune them by altering the transistor channels' width to get higher performance or lower power consumption. If everything works well, such control allows them to reduce transistor leakage current and performance variability — this provides great opportunities for DTCO.

Yet another advantage of Intel's 18A is its backside power delivery network (PDN) called PowerVia. In order to efficiently provide power and respond quickly to the behavior of a modern processor, which can vary significantly depending on the workload, the PDN needs to be customized for a specific design and process technology, which gives plenty of opportunities for DTCO. Client and smartphone SoCs should be optimized for burst behavior, while datacenter SoCs should be optimized for constant high loads — which is why it is important that (for now) Intel and Arm will only address smartphone SoCs.

"Intel's collaboration with Arm will expand the market opportunity for IFS and open up new options and approaches for any fabless company that wants to access best-in-class CPU IP and the power of an open system foundry with leading-edge process technology," said Intel CEO Pat Gelsinger.

One important thing that to note about Intel's 18A is that this process technology will be used to make chips at different locations that IFS will operate around the world. This will be an advantage of this fabrication process as there are fabless chip designers seeking for localization of chip production. 

"As the demands for compute and efficiency become increasingly complex, our industry must innovate on many new levels. Arm's collaboration with Intel enables IFS as a critical foundry partner for our customers as we deliver the next generation of world-changing products built on Arm," said Arm CEO Rene Haas.

When Intel announced its proposal to acquire Tower Semiconductor for $5.4 billion in February 2022, it said it expected to close the transaction in 12 months. But the transaction is still not closed more than 13 months after the announcement since China's State Administration for Market Regulation still has not cleared it. But Intel remains optimistic that it will take over Tower by end of June. 

The first quarter is about to end and so Intel Israel this week issued a statement saying that the company will continue to work toward closing the deal by the end of next week, but the transaction may not be cleared until later — sometime in the first half of this year (by the end of June 2023). 

Israeli BizPortal cited the full statement, which was issued to Bloomberg:

"While we continue to work to close the Tower transaction within the first quarter of 2023, the transaction may close in the first half of 2023, subject to certain regulatory approvals and customary closing conditions," the statement reads.  

By acquiring Tower Semiconductor, Intel can achieve multiple goals. First, it will get a contract maker of semiconductors with dozens of loyal customers and a stable revenue stream, which will be a good addition to the company's existing IFS clients. Second, it will get fabs with a host of mature process technologies that are widely adopted — importance of mature nodes should not be underestimated. Third, it will gain a team of seasoned executives with vast experience in contract chipmaking — something that the company currently lacks.  

Intel's main problem with the acquisition of Tower Semiconductor is the stance of China's State Administration for Market Regulation (SAMR), which suspended the clock in its review of the transaction in January. Intel is about to get grants from the U.S. government's CHIPS and Science fund on the condition that it will not invest in China for the next 10 years after the receival. Meanwhile China wants Intel to keep investing in Chinese assets and is trying to leverage this by potentially blocking the transaction. 

Earlier this week Intel appointed its own veteran to lead its Intel Foundry Service unit. It was widely believed that Intel planned to assign a Tower executive to that role after Randhir Thakur stepped down in November, so the recent appointment seemed to signal that Intel was not very confident in the outcome of the transaction. 

Intel on Tuesday appointed its veteran Stuart Pann as general manager of Intel Foundry Services. Stuart Pann has never worked in the foundry industry, but he has vast experience in supply chain management, planning, and strategic allocation of resources. Apparently, Intel believes that these are the skills that IFS needs to become one of the world's leading contract makers of chips by 2030.

Stuart Pann replaces Randhir Thakur, who was instrumental in establishing Intel's foundry operations from 2021–2022, but who stepped down from the position last November. Previously, it was widely believed that Intel would appoint someone from Tower Semiconductor after it closes the takeover deal to lead IFS, but it looks like the company decided to hire its own veteran for the role. Now that IFS got its head, it begs the question of how Intel will employ executives from Tower, who bring decades of foundry experience to the company.

Pann previously served as Intel's chief business transformation officer and general manager of the company's Corporate Planning Group after he returned to the company in 2021. He knows the structure of Intel and the structure of IFS. Among other things, Pann established IDM 2.0 acceleration office.

"With deep expertise in capital and capacity strategies, supply chain management, and sales and operations planning across internal and external manufacturing, Stuart is an ideal leader to accelerate this momentum and drive long-term growth for IFS," said Pat Gelsinger, chief executive of Intel.

Before re-joining Intel, Pann held the positions of chief supply chain officer and chief information officer at HP. Prior to that, he worked at Intel as the corporate vice president and general manager of the Business Management Group, where he oversaw the pricing, revenue, and forecasting functions for Intel's microprocessor and chipset businesses.

In fact, Stuart Pann spent some 33 years at Intel from 1981 to 2014 and held various sales management positions before becoming the director of pricing and operations for the Intel microprocessor business in 1999, his LinkedIn profile reads. An important detail about the new executive of IFS is that, throughout his career, he has never worked with a foundry as a customer. He has never been responsible for chip production at Intel, and he has never worked at any contract chipmaker.

"Intel Foundry Services is a critical pillar of our IDM 2.0 strategy, and it’s been exciting to watch it grow from an idea to an operating business with a world-class IP portfolio and significant customers in less than two years," Pann said. "I am committed to championing the interests of our foundry customers and to helping them take advantage of Intel’s leading-edge process technology and full stack of open systems foundry offerings so they can succeed in a world that demands ever more computing."

While the appointment of Stuart Pann is a bit surprising, it's good to see that Intel's IFS finally has a leader. At the very least, the business unit will get a strategy for how to reach its strategic goal and become the world's No. 2 foundry by the end of the decade. And if it can manage that, then it can start thinking about how to overtake TSMC and regain its former lead in process technology.

While the Semiconductor Industry Association (SIA) — the organization that represents 99% of chip companies in America — understands how important national security is, it believes that curbs against potentially hostile nations could hurt the U.S. semiconductor industry as a whole. 

After the U.S. government imposed strict sanctions against Chinese chip and supercomputer sectors, various semiconductor companies lost some $240 billion of stock value nearly overnight. Among those who suffered are various companies, including developers of electronics design automation (EDA) tools, chip designers, wafer fab equipment (WFE) producers, and chipmakers themselves. Without money from Chinese clients, the U.S. semiconductor industry will certainly live and prosper, but with them, it would develop quicker, SIA notes.

"U.S. semiconductor companies are dependent on a “virtuous cycle” of innovation that includes large investments into research and development and access to global markets," a press release by SIA reads. "Historically, U.S. semiconductor companies have consistently invested about one-fifth of their revenues in research and development, among the highest shares of any industry." 

China is a big business for all parties involved. Here are some examples. 

Cadence supplies thousands of Chinese chip and motherboard developers with EDA tools, Applied Materials sells boatloads of WFE tools to entities like SMIC and Hua Hong, whereas Nvidia sells boatloads of artificial intelligence and high-performance computer accelerators to companies like Baidu. Finally, U.S. citizens working at Chinese companies earn hefty paychecks while serving in executive roles. Yet, all of them were affected by the strict curbs imposed by the U.S. government. 

SIA makes several points in its press release, which are explained quite well in the more detailed filing with the U.S. Department's Bureau of Industry and Security (BIS). One of those is job cuts at Lam Research: some 1,300 people will be cut (however, some of this appears to be due to outsourcing tool production to other countries). This only seems to be beginning,  American WFE companies like Applied Materials have yet to release their reports, yet the expectations are not good.

One of the least-noticed highlights of Intel's earnings call this week was the announcement that its Intel Foundry Services contract chipmaking division landed an order from a major "cloud, edge, and datacenter solutions provider" for producing chips on Intel 3 production node. While this is a significant win for IFS, problems linger, as the Chinese antitrust agency has suspended its review of the Intel-Tower transaction.

A Major Win

"I am very happy that we were able to add a leading cloud, edge, and datacenter solutions provider as a leading-edge customer for Intel 3," said Pat Gelsinger, Intel CEO. "Including prior customers such as MediaTek, we now have a lifetime deal value of greater than $4 billion for IFS." 

The company has always tailored its Intel 20A and Intel 18A (2nm and 1.8nm-class, respectively) for its foundry customers. In contrast, its current and upcoming Intel 7 (10nm Enhanced SuperFin), Intel 4 (7nm with EUV), and Intel 3 (7nm+ with EUV) nodes were designed primarily with Intel in mind. So winning a major customer with Intel 3 — which is set to be production ready in 2024 — is clearly an achievement for the processor giant.  

Meanwhile, it is possible that Intel will be producing a semi-custom version of its Xeon processor for a major client, just like it envisioned when announcing its IDM 2.0 business model a little less than two years ago. 

Intel's IFS has been steadily gaining momentum. The foundry unit has already signed Qualcomm and Amazon Web Services (AWS) as initial customers and won a contract from the U.S. Department of Defense. In addition, Intel says it is actively working with many of the largest fabless chip designers on specific engagements, which is quite an achievement for a contract chipmaker that has been in the business for less than two years. 

"We also have an active pipeline of engagements with seven out of the 10 largest foundry customers coupled with consistent pipeline growth to include 43 potential customers and ecosystem partner test chips," said Gelsinger. "Additionally, we continue to make progress on Intel 18A, and have already shared the engineering release of PDK 0.5 (process design kit) with our lead customers and expect to have the final production release in the next few weeks."

A Major Bump

However, not everything is rosy for Intel Foundry Services. The proposed $5.4 billion acquisition of Tower Semiconductor, a specialty foundry with a vast portfolio of clients, has hit a bump. According to Seeking Alpha, China's State Administration for Market Regulation (SAMR) suspended the clock in its review of the transaction. 

It is believed that Intel will not invest in its Chinese operations as U.S. authorities prohibit investments in China for companies that receive money or other benefits from the CHIPS fund. Meanwhile, if the deal is not approved by SAMR, it will not move forward. 

Intel needs Tower to gain an experienced foundry executive team and a huge portfolio of clients. In fact, the former head of IFS already stepped down back in November as Intel planned to close the deal in Q1 2023. Now that the deal cannot close, IFS is operating without a head, which is not particularly good for business. However, Intel remains optimistic about the Tower buyout. 

"In addition, we are working hard to complete the Tower acquisition, which will further amplify our momentum as our foundry business becomes even more compelling to customers," said the head of Intel.

TSMC remains poised to produce CPUs, GPUs, SoCs, and FPGAs for AMD on its leading-edge fabrication processes for years to come. However, AMD will keep outsourcing production of its older products to GlobalFoundries and Samsung Foundry, according to DigiTimes. Given the current geopolitical situation, one might speculate that the chip designer is exploring SF as a potential alternative not only to GF, but to TSMC as well. 

Older Products for Now

DigiTimes claims that TSMC will make Zen 4 and Zen 5-based products for AMD using its N5/N4 (5nm and 4nm-class) and N3 (3nm-class) fabrication processes in the coming years. Meanwhile, GlobalFoundries and Samsung Foundry will produce AMD's processors based on older Zen and Zen+ microarchitectures as well as previous-generation GPUs using SF 14LPP and GF 12LP production nodes.  

This is not the first time we've heard of AMD working with Samsung Foundry to produce some of its chips. For example, last August, TechGoing reported that AMD would outsource some of its older products to Samsung Foundry. Keeping in mind that GlobalFoundries licensed Samsung's 14LPE and 14LPP technologies, it is easy for AMD to dual-source some of its older products. In fact, AMD confirmed to analyst Patrick Moorhead in 2016 that it could use Samsung Foundry's capacities if needed.  

GlobalFoundries is busy producing chips for various customers, including Intel, Qualcomm, MediaTek, and NXP. So AMD might want to secure additional 12nm/14nm-class capacity at Samsung Foundry for a just-in-case scenario. Meanwhile, considering the current geopolitical situation, AMD may explore Samsung Foundry as a potential alternative to TSMC. Here is why.

Possibly Something New Later

Once AMD's leading production partner, GlobalFoundries ceased to develop leading-edge process technologies in 2018 as it pivoted to specialty production nodes. When the company switches to a specialized sub-10nm fabrication process, the bulk of AMD's primary requirements will probably shift to 5nm-class or even 3nm-class manufacturing technologies. As a result, AMD might outsource some of its parts requiring specialty nodes to GlobalFoundries, but we would not expect GF to produce mass-market products for AMD soon. 

By contrast, Samsung Foundry keeps developing leading-edge fabrication technologies as it competes fiercely against TSMC. While Samsung Foundry's yields on leading-edge fabrication processes are reportedly not as high as those of TSMC, the company can offer its services to chip designers that require leading-edge technologies. 

For now, the skies are blue for TSMC. But if tensions between China, Taiwan, and the U.S. lead to a military conflict or even China's invasion of Taiwan, AMD will need an alternative to the world's largest foundry. For now, the only other option for TSMC is Samsung Foundry, as Intel Foundry Services' (IFS) 20A technology won't be available to fabless chip designers until 2024.  

Of course, AMD is almost certainly exploring IFS and its future nodes, just like other leading chip developers.

Some Thoughts

DigiTimes and TechGoing both reported about AMD's outsourcing to SF within a matter of six months. Working with Samsung Foundry allows AMD to learn how to collaborate with this contract maker of chips, how to use its packaging, and what to generally expect from SF. 

AMD's possible intention to use Samsung Foundry's leading-edge production nodes if something occurs to TSMC is our speculation not confirmed by any industry source at this point. To use Samsung Foundry's advanced technologies, AMD would need to redesign its chips for SF's nodes, which costs hundreds of millions of dollars, which is a lot of money even for AMD. Yet, if the situation between China, Taiwan, and the U.S. becomes dire, AMD's experience with GlobalFoundries could become more than valuable. 

At the IEDM conference, Intel shared its process technology roadmap and its vision for chip designs that will be available in the next three to four years. As expected, Intel's next-generation fabrication processes — Intel 4 and Intel 3 — are on track to be used for high-volume manufacturing (HVM) in 2023 and 2024, respectively. Furthermore, the company's 20A and 18A production nodes will be ready for HVM in 2024, which means that 18A will be made available ahead of schedule, a slide published by IEEE Spectrum suggests.

Intel's Technologies Between Now and 2025

NOTE: Process technology readiness does not mean HVM start.

Intel 4 Ready Today, Intel 3 Due in H2 2023

Next year Intel will release its 14th Generation Core codenamed Meteor Lake CPU, its first mass-market client processor featuring a multi-chiplet (or multi-tile) design with each chiplet set to be made using a different process technology. Intel's Meteor Lake products will comprise four tiles: the compute tile (CPU cores) made using Intel 4 process technology (aka 7nm EUV), the graphics tile produced by TSMC presumably using its N3 or N5 node, the SoC tile, and the I/O tile. In addition, the tiles will be interconnected using Intel's Foveros 3D technology.

Meteor Lake's compute tile is arguably the most exciting part of the package because it will be made on Intel 4 (previously known as 7nm), the company's first production node that will use extreme ultraviolet (EUV) lithography. This fabrication process is ready for mass production, according to Intel, though it will be deployed for the HVM of Meteor Lake's compute chiplet only several months from now. Keeping in mind that Intel powered on this compute tile in October 2021, it is not surprising that the node is ready for production by now. What is a bit unexpected is that Intel does not confirm that this process technology is used to make Ponte Vecchio's Xe-HPC compute GPU tiles, as planted two years ago.

Intel will start using EUV nearly four years after TSMC, which began to produce chips on its N7+ node in Q2 2019. Intel needs to ensure that its 4nm-class node performs up to expectations and delivers good yields, as it will be the first node to arrive after the company's rather unlucky 10nm family of processes that did not perform as expected early in its lifecycle and which costs are higher than the company hoped several years ago.

Since Intel has to catch up with its rivals Samsung Foundry and TSMC, its Intel 4 process technology will already be joined by its Intel 3 fabrication node (3nm-class) in 2023 ~ 2024. This process will be manufacturing-ready in the second half of 2023, based on data shared by Intel. It will be used to make Intel's codenamed Granite Rapids and Sierra Forest processors, which are high-profile products for the company. Sierra Forest is expected to be the company's first data center CPU to use energy-efficient cores and will compete against various Arm-based offerings with high core counts.

Intel already has to work on Xeon 'Granite Rapids' samples, so it looks like the design of the CPU is ready, and the node itself is on track for HVM 2024.

"The first stepping of Granite Rapids is out of the fab, yielding well, with Intel 3 continuing to progress on schedule," said Pat Gelsinger, chief executive of Intel, at the most recent earnings call. "Emerald Rapids is showing good progress and is on track for the complete year 2023, Granite Rapids is very healthy running multiple OSs across many configurations, and with Sierra Forest, our first E-core product providing world-class performance per watt, are both solidly on track for 2024."

Intel's 18A Moved in to H2 2024

Playing catch up with TSMC and Samsung is important, but to return its process technology leadership, Intel will have to leapfrog both of its rivals. This is set to happen sometime in 2024 when the company unveils its 20A (20 angstroms, or 2nm) node that will use its gate-all-around transistors branded RibbonFET as well as backside power delivery called PowerVia. Intel expects its 20A node to be manufacturing ready in the first half of 2024; it will be used to make — among other things — chiplets for the company's codenamed Arrow Lake processors for client PCs in 2024.

Intel's 20A will be the industry's first 2nm-class node, and it will also extensively use EUV to maximize transistor density, provide decent performance improvements, and lower power consumption. In 2024, it is set to compete against TSMC's third-generation 3nm-class (N3S, N3P) process technologies designed for enhanced transistor density and performance. It remains to be seen how these three nodes stack against each other. Still, Intel is setting the bar very high for its 20A process as it simultaneously introduces two major innovations (GAA, BPD).

And yet, 20A is not the most advanced process technology that Intel plans to start using by late 2025. The company is also readying its 18A (18 angstroms, 1.8nm) production node that promises to further increase PPA (performance, power, area) advantages for Intel and its Intel Foundry Services customers.

For 18A, Intel originally planned to use EUV tools with 0.55 numerical aperture (NA) optics, which is set to provide an 8nm resolution (down from 13nm in the case of currently used EUV tools with a 0.33 NA). But ASML's production of High-NA EUV equipment will only be ready in 2025, whereas Intel targets its 18A to be prepared for manufacturing in the second half of 2025, ahead of its rivals.

Since it is possible to get to an 8nm resolution for post-3nm-nodes with multi-patterning using current-generation EUV tools (though this will lengthen production cycles and could potentially affect yields), Intel is willing to take some additional risks with 18A and use ASML's Twinscan NXE:3600D or NXE:3800E to make chips on this node as it believes that it will bring it undisputed market leadership.

As it turns out, the first 20A and 18A test chips have been taped out already.

"On Intel 20A and Intel 18A, the first nodes to benefit from RibbonFet and PowerVia, our first internal test chips and those of a major potential foundry customer have taped out with silicon running in the fab," said the head of Intel. "We continue to be on track to regain transistor performance and power performance leadership by 2025."

System Technology Co-Optimization

Both 20A and 18A production nodes will extensively use EUV tools (and potentially even High-NA EUV tools), making chips produced on these technologies extremely expensive. Even today's large monolithic 4nm and 5nm chips are costly to develop, validate, and produce, which is why multi-tile designs like Intel's Ponte Vecchio are gaining popularity. At 2nm and 1.8nm, it will make sense to disaggregate high-performance designs further.

To do so, Intel believes that an all-new new 'outside-in' design approach will be needed. Intel envisions that several years down the road, chip designers will be able to disaggregate functions of a single chip into a multi-chiplet design and then produce chiplets using the most optimal technology to meet their performance, power, and cost goals. Intel calls such approach system technology co-optimization (STCO). For example, since logic scales better than SRAM, it makes sense to produce logic and caches using different nodes (for optimal costs and performance) and then stitch them together using technologies like Foveros or EMIB.

Given such an approach, a successful foundry will have to offer various nodes for different chiplets and competitive packaging technologies. This is why Intel needs to provide the best logic technology (i.e., 20A and 18A) ahead of its rivals to ensure that it makes the most lucrative parts of those upcoming multi-tile designs.

Rising inflation and a weakening global economy had forced many, if not most, chipmakers to lower aggressive expansion plans set when demand for chips exceeded supply. Nonetheless, even with the semiconductor industry's decreased capital expenditures (CapEx), the 2022 forecast stands at $181.7 billion, a new record high, according to IC Insights.

Capital expenditures of semiconductor manufacturers have been increasing since 2020 due to strong demand for everything digital, from smartphones and PCs to giant televisions and self-driving cars. The report claims that CapEx budgets increased by 35% in 2021 to $153.1 billion and are poised to grow 19% in 2022 to $181.7 billion.

But now that companies like Intel and Micron are reviewing their CapEx plans for 2023, IC Insights revises its forecasts and believes that the industry's spending will drop by 19% in 2023 to $146.6 billion. This is just 4.25% lower than the $153.1 billion in 2021 and is significantly above capital spending in 2020.

Meanwhile, IC Insights believes that the memory industry will suffer more than the logic industry as major producers will reduce their capital expenditures by 25%. Also, Chinese semiconductor companies will have to cut their budgets by around 30% as the U.S. sanctions against the People's Republic's chip sector will inevitably affect their ability to procure new production tools.

Anyhow, a 19% decline in capital spending year over year is the steepest decline since the global financial crisis in 2008 – 2009, notes IC Insights.

Indeed, semiconductor industry CapEx spending dropped 40% year-over-year in 2009 but only grew to 107% in 2010 when the global economy showed signs of a rebound. Given how quickly semiconductor CapEx budgets have increased in recent years, we would not expect them to grow by around two times from $146.6 billion in 2023. Meanwhile, virtually all makers of chips (including logic and memory chips) expect demand for their products to rebound in 2024 ~ 2025. As a result, they think they need expanded production capacities to meet that demand in the middle of the decade. As a result, spending on new fabs will grow significantly in 2024 ~ 2025.

Fabs already being constructed or equipped, including those in the U.S. by companies like Intel, Micron, Samsung Foundry, TSMC, and Texas Instruments, will come online on time, as delaying such projects is expensive.

Interestingly, IC Insights does not believe that funding U.S. semiconductor suppliers as part of the U.S. CHIPS and Science Act will give a significant boost to their spending in 2023 as they will use the money they are going to receive in grants in a bid to replace their own money they would have spent on their new fabs.

"In other words, the CHIPS and Science Act money is not expected to be 'additive' funding to planned semiconductor industry spending, but instead is likely to replace the money a semiconductor producer was going to budget if CHIPS and Science Act funding was unavailable," wrote Bill McClean, the president of IC Insights.

Randhir Thakur, the head of Intel's contract chip production unit, has resigned, according to a report from The Register that was confirmed by Intel. He will continue to lead Intel Foundry Services through Q1 2023 to ensure a smooth transition to a new leader. 

Pat Gelsinger, chief executive of Intel, sent an email to the company's employees thanking Randhir Thakur for helping establish IFS and being instrumental to the company's IDM 2.0 business model. 

"Randhir has been a key member of the Executive Leadership Team for the past two and a half years and has served in several senior leadership roles since he joined us in 2017," Intel's CEO wrote in the email quoted by The Register. "His contributions to our [Integrated Device Manufacturing] 2.0 transformation are many, but most notable is his leadership in standing up our IFS business." 

Indeed, Randhir Thakur has done quite a lot to be proud of at IFS. During his tenure, Intel announced the pending acquisition of Tower Semiconductor (which would immediately make Intel one of the biggest contract makers of chips). He was also instrumental in inking deals with giant chip developers like MediaTek, which also happens to be one of TSMC's largest customers. This contract was a major win for IFS, and the outfit also won a contract with the U.S. Department of Defense for the Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. 

But IFS is far from an ideal contract chipmaker, at least based on what we know about Intel's process technology roadmap through 2025. The company's plans announced so far largely align its production nodes to its own fabrication processes, which is good for Intel as an IDM (Integrated Design Manufacturer) player, but might not be enough to persuade companies like Apple, AMD, and Nvidia to use IFS services for their high-volume products. 

Intel's most logical next move is perhaps to hand the foundry division over to the management of Tower Semiconductor. The transaction is set to close in February 2023, which is around the time Randhir Thakur is set to leave. Tower Semiconductor has developed its roadmap together with its customers for years, so the management experience will be critical for the future of IFS.

The Intel Foundry Services business unit earned $171 million in the company’s fiscal third quarter of 2022, which may not sound much given that it is about 1.1% of the company’s revenue. The company has yet to offer its leading-edge technologies to big customers.

When Intel established its Intel Foundry Services division in early 2021, it was clear that it needed the contract chipmaking unit to be on par with Samsung and Taiwan Semiconductor Manufacturing Co. in terms of scale as fabs and production nodes are getting costlier. The goal was ambitious from the start, and it looks like the company intends to be rather aggressive too as it plans to become the second largest foundry by 2030.

Big Ambitions

"Our ambition is to be the No. 2 foundry in the world by the end of the decade, and [we] expect to generate leading foundry margins," said Randhir Thakur, the president of Intel Foundry Services, in an interview with Nikkei Asia. 

Getting to the No. 2 spot on the global foundry market means that Intel will have to beat Samsung Foundry (the current No. 2, according to TrendForce), which generated over $20 billion in revenue in 2021 and is on track to exceed this results in 2022. As of Q1 2022, Samsung Foundry controlled some 16.3% of the global foundry revenue, being dramatically behind market leader TSMC (53.6%), but significantly ahead of its closest peers UMC (6.9%) and GlobalFoundries (5.9%) 

By contrast, Intel's IFS business unit has generated $576 million in revenue this year so far. Once the acquisition of Tower Semiconductor closes in early 2023, the Intel will add some $1.5 billion revenue per year to its IFS division. This will immediately make IFS the world's No. 7 or No. 8 foundry, but it will be still considerably smaller than Samsung Foundry in terms of revenue. 

To become the world's second largest contract maker of chips, Intel will have to adopt a multi-faceted strategy that involves the following:

• Development of leading-edge process technologies which are competitive to those of Samsung Foundry and TSMC in terms of power, performance, and area (PPA); yields, and time-to-market. 
• Building plenty leading-edge capacity for IFS clients. Essentially, the company will have to own more advanced capacity than Samsung Foundry does by late 2020s.
• Maintain operations and competitive positions of Tower Semiconductor by innovating on the mature technologies front.
• Land orders primarily from clients that use TSMC and Samsung Foundry, perhaps steal someone from GlobalFoundries and SMIC too.

Require Big Actions

So far, Intel has revealed a rather aggressive process technology roadmap that involves high volume production of chips on its 18A (18 angstroms or 0.18nm-class technology) in 2025 and employ High-NA extreme ultraviolet lithography tools for 18A if possible. Intel's production node plan is considerably more aggressive than that of Samsung Foundry and TSMC, which both plan to start making 2nm-class (20 angstroms-class) chips in 2025 (which means that these will be available in very late 2025 at the earliest, or rather in 2026). 

On the semiconductor capacity front, Intel's plans are no less aggressive. The company is building its 20A-capable Fab 52 and Fab 62 at its camp near Chandler, Arizona; constructing the first two 18A/20A-capable modules of its site near Columbus, Ohio; building its $3.5 billion facility for advanced packaging operations; finishing up a new Intel 4-capable module at its site near Leixlip, Ireland; and constructing an all-new fab near Magdeburg, Germany. Overall, Intel plans to invest (or rather co-invest with governments and semiconductor co-investment partners like Brookfield) around $100 billion in new semiconductor fabrication facilities in the coming years. 

But Samsung is no less aggressive with its CapEx spending. In fact, while Intel cut its capital expenditures from $27 billion in 2022 to $25 billion recent, Samsung will invest over $33 billion in new semiconductor production capacity this year and will retain its spending at around the same level next year, the company announced recently. Of course, it is unclear how much of these sums is going to be invested in memory (3D NAND and DRAM) production facilities and how much will be used to expand logic capacity of Samsung Foundry, but the South Korean company is clearly very aggressive with its semiconductor business, so it will be particularly hard for Intel to match SF's advanced capacities. 

Stealing clients from TSMC and Samsung Foundry will be even harder as large customers like Nvidia or Qualcomm have supply agreements with their foundry partners that span for years. Furthermore, it remains to be seen whether Intel's fabs located in Europe and America will be able to offer the same pricing as TSMC's and Samsung Foundry's fabs located in Taiwan and South Korea.

Geographical Advantage

It is particularly noteworthy that Intel is building up production capacity in the U.S. and Europe and so far, has not announced any plans to build fabs in Taiwan or South Korea (it will continue to operate a Tower Semiconductor fab in Japan though). While operating fabs in Europe and America is costlier than operating them in Taiwan or South Korea, building new fabs in the U.S. and Europe makes sense both from customer relationship and geopolitical points of view.  

On the one hand, U.S. customers will be eager to use fabs in America due to logistics, risk management, and other factors. There are not so many chip designers in Europe that need leading-edge production technologies, but at the end of the day Intel's own product portfolio is expanding, so it will need new fabs for itself anyway. Many of Intel's potential foundry clients see advantages in fabs located in America or Europe, according to Intel. 

"As we have engaged with foundry customers since launching IFS, it has become abundantly clear that many of these companies see the need for a more resilient and geographically balanced semiconductor supply chain," Thakur told Nikkei Asia.

Yet, since both TSMC and Samsung Foundry are building up new leading-edge fabs in Arizona and Texas, geographical advantages of Intel's new fabs in America may be overestimated. 

On the other hand, since politicians in Europe and the U.S. want to build domestic semiconductor supply chains so not to rely on Taiwan so significantly, which is why they are eager to co-invest in new facilities with Intel. 

Make or Break

For Intel, foundry business is a way to quickly increase its production volumes and therefore match its CapEx financial capabilities with those of TSMC and Samsung. Getting a new revenue stream is important for Intel, but it is not as important as increasing production volumes. 

Therefore, if the company succeeds in landing orders from many clients that need advanced production technologies, this will be a success by itself as it will allow it to keep in investing in development of leading-edge nodes and increasingly expensive fabs. If it does not, it may probably cease to be a leading integrated design manufacturer (IDM) and CPU supplier over time. If the company manages to become the world's second largest foundry in the process of setting up its foundry business pursuing its main target, this will be an even bigger success. But volumes is the primary target.

Intel is set to hold a ground-breaking ceremony for its first two fabs in a campus located in Licking County near Columbus, Ohio. The all-new manufacturing site will be able to house up to eight chip fabrication facilities and will require investments of around $100 billion over time. President Joe Biden and Ohio governor Mike DeWine will join Intel's Pat Gelsinger at the ceremony. 

The first two fabs in Intel's Ohio, Silicon Heartland manufacturing site will cost Intel around $20 billion, and will be built simultaneously. These fabs are expected to come online in 2025. The new campus will span around 1,000 acres (4 square kilometres) and will be able to house up to eight semiconductor fabs as well as support operations and ecosystem partners. To buildout the site, Intel will need to invest some $100 billion, the company once said.  

Intel does not disclose which production nodes will be used at its new fabs, but given that they are projected to come online in 2025, we summize that the facilities will be able to make chips on Intel's 20A and 18A fabrication technologies and will be ready for more advanced manufacturing processes. That said, expect the new fabs to extensively use current-generation extreme ultraviolet (EUV) lithography with 0.33 numerical aperture as well as utilize next-generation EUV tools with 0.55 NA.

These fabs will employ a staff of 3,000 across manufacturing and engineering, producing chips both for Intel as well as its Intel Foundry Services (IFS) clients. Furthermore, the new facilities could create about 7,000 local construction jobs.  

The Ohio campus will be Intel's first all-new manufacturing site in decades. Recently Intel built new fabs at its existing sites in Arizona, Ireland, Israel, New Mexico, and Oregon. By contrast, the Silicon Heartland campus in Ohio is set to be built from scratch and is expected to add significant manufacturing capacity for Intel as well as its ISF customers, thus being instrumental to execution of Intel's IDM 2.0 strategy. Also, the site (along with Intel's fabs in Arizona and other companies' fabs) will play an important role in bringing leading-edge semiconductor manufacturing back to the U.S.

"Today marks a pivotal moment in the journey to build a more geographically balanced and resilient semiconductor supply chain," said Pat Gelsinger, Intel's chief executive. "The establishment of the Silicon Heartland is testament to the power of government incentives to unlock private investment, create thousands of high-paying jobs, and benefit U.S. economic and national security. We would not be here today without the support of leaders in the administration, Congress and the state of Ohio, who share a vision to help restore the United States to its rightful place as a leader in advanced chipmaking." 

To support Intel's Silicon Heartland, a number of Intel’s partners, including Air Products, Applied Materials, LAM Research and Ultra Clean Technology have indicated plans to establish local presence to support the new operations.

The U.S. share of global semiconductor manufacturing capacity has decreased from 37% in 1990 to 12% in 2021, according to the Semiconductor Industry Association (SIA), but some 47% of the chips sold worldwide are designed in the U.S. This disparity poses major risks to American national security and the economy, which is why both industry insiders and politicians recently began to call for building semiconductor fabs in the USA.  

Their calls have been heard, and today five major chipmakers — GlobalFoundries, Intel, Samsung Foundry, TSMC, and Texas Instruments — are building new semiconductor production facilities in the U.S. These efforts will inevitably be bolstered by a new wave of funding provided by the newly-approved CHIPS act. This U.S. subsidy initiative will pump $52 billion into new US-based chip fabs and provide fresh tax incentives. Those funds will spur a wave of new investment over the coming years, and its sorely needed. 

There are many reasons why countries like Taiwan, South Korea, and Singapore became leading producers of logic and memory chips in the 1990s and 2000s. In addition to lower labor costs in these states, those governments and their local authorities provided various incentives to chipmakers, which is why it was significantly cheaper to build fabs in Asia than in the U.S. and Europe.  

New York and Saratoga County authorities understood this early and offered AMD significant incentives in 2006 when the company made plans for what is now known as GlobalFoundries Fab 8. Unfortunately, other states and the federal government weren't that agile, which is why the deployment of brand-new fabs became a rare occurrence in America. In fact, Intel even adjusted its manufacturing capacity strategy, culminating in it delaying the Fab 42 equipment move in by five years and its coming online by six years. 

While we can't say that the semiconductor production industry in the U.S. didn't add capacity in recent years — both Intel and GlobalFoundries gradually expanded their production capacities in the late 2010s — brand-new leading-edge fabs haven't been deployed in the U.S. for a while. That's about to change. Here's how and where those changes will take place. 

Intel: Spending Over $40 Billion on Chip Facilities in the U.S. 

Intel is certainly one of the oldest chipmakers in the U.S. and one of the world's biggest. It also happens to be the only company spending more than $40 billion on new semiconductor fabs in the U.S. Unlike some of its industry peers that set long-term plans and option new fabs, Intel is investing tens of billions of dollars into four U.S. fabs that will come online in three years. Currently, Intel is building four chip production plants, two in Arizona and two in Ohio, and one advanced packaging facility in New Mexico.  

Arizona 

Intel broke ground on Fab 52 and Fab 62 in the Ocotillo campus near Chandler, Arizona, in late September 2021, and the construction of those buildings is well underway. The fabs are designed to produce chips using Intel's 20A fabrication technology both for Intel and its Intel Foundry Services customers.

Intel's 20A production node will be the company's first process to incorporate RibbonFET gate-all-around field-effect transistors (GAAFETs) and PowerVia backside power delivery. These radical improvements are expected to bring significant power, performance, and area (PPA) improvements. 

Intel's Fab 52 and Fab 62 will come online in 2024 and cost around $20 billion. These fabs will be instrumental for Intel's IDM 2.0 strategy that will find the company manufacturing chips for other companies, a first. 

Ohio 

Intel is building two fabs in Ohio that are yet to be named, but their significance for Intel and the U.S. chip industry is hard to overestimate. For years, Intel has gradually expanded its mega sites in Arizona, New Mexico, and Oregon. Expanding existing campuses makes a lot of sense since the semiconductor supply chain is very complex. Intel needs support from partners (e.g., raw materials suppliers, parts, etc.) with a local presence.  

In Ohio, Intel wants to establish yet another mega site that will house up to eight semiconductor manufacturing facilities (we would include an advanced packaging facility, too, but Intel has not confirmed this). The site will require investments of around $100 billion to be fully built over the next decade. Furthermore, the new campus will require Intel's partners to establish a local presence, which essentially means a major expansion of the U.S. semiconductor supply chain. Actually, of all the chipmakers building new plants in the U.S., only Intel is willing to build a new mega-site from scratch. 

The first two new fabs are near Columbus, Ohio, and are expected to produce chips on Intel's 18A/20A nodes sometime in 2025 when they come online. Intel's 18A manufacturing technology was meant to be the first fabrication process to take advantage of ASML's Twinscan EXE 0.55 High-NA extreme ultraviolet (EUV) lithography scanners. However, earlier this year, Intel said it could keep using current-gen Twinscan NXE 0.33 NA EUV tools for 18A by adopting multi-patterning. But even without High-NA tools, the new technology promises to bring a variety of power, performance, and area (PPA) advantages as it will rely on Intel's 2nd-Gen GAA RibbonFETs. 

Intel's mega fab project will initially cost over $20 billion and will be Ohio's biggest economic development project in history. To lure Intel to Ohio, the state had to provide Intel with about $2.1 billion in various incentives. In addition, Intel is requesting funding from the federal government as part of the CHIPS act, but it isn't clear how much funding it will receive.  

In fact, government funding is crucial for Intel's Ohio mega site project. Fab buildings are not expensive (but have the longest lead time), but semiconductor production tools are (e.g., one EUV scanner costs about $160 million). Intel can build shells, but then it needs to equip them with tools in a timely manner to meet its production schedules. Equipping a fab for a leading-edge node means buying all kinds of lithography (including immersion and EUV scanners), coating, etching, deposition, resist removal, inspection, and other tools, which cost billions of dollars.   

If it takes too long to equip a brand-new chip plant due to a lack of financial resources, Intel can add extra tools to an existing facility to produce chips on a certain new node. But this means that Intel will have to put its new building on hold and wait for another opportunity to equip it, which means that it will generate costs without producing any earnings. 

While Intel officially considers spare fab shells as a 'smart capital strategy' that gives it flexibility in how and when it brings additional capacity and tools online, it is still better to equip the buildings after they are constructed. This is why Intel CEO Pat Gelsinger warned the U.S. authorities and legislators that if the CHIPS act bill was not passed and the company didn't get financial incentives and support from the government, he might move the company's next mega site project to Europe. 

New Mexico 

Intel's advanced packaging facility in New Mexico will enable the company and its clients to build complicated multi-chiplet designs (a-la Meteor Lake) that will become widespread in the coming years in the U.S. 

Since sophisticated packaging technologies like embedded multi-die interconnect bridge (EMIB) and Foveros require a cleanroom, it is safe to call the packaging operations in New Mexico a fab. In fact, the equipment for the packaging facility will cost Intel $3.5 billion, the price of a new fab a couple of decades ago.  

The advanced packaging operations will be instrumental for producing sophisticated designs in the U.S. when it becomes operational in 2023 ~ 2024, so this is yet another Intel project whose importance for the U.S. semiconductor industry is hard to overrate. 

TSMC: 5nm Coming to the U.S. 

TSMC made quite a splash when it announced plans to build its 5nm-capable fab near Phoenix, Arizona, in mid-2020. Throughout its history, the company has only built two fabs outside of Taiwan — the WaferTech plant in Camas, Washington (which still processes 200-mm wafers using mature nodes) and Fab 16 in Nanjing, Jiangsu Province, China (which makes chips using TSMC's 28nm nodes). Therefore, the intention to build a fairly advanced fab in Arizona was considered a major shift in strategy. 

Being the world's largest contract chipmaker, TSMC certainly has hundreds of customers in the USA, so bringing a fab closer to them might be beneficial. Yet, the first phase of the fab will have a capacity of around 20,000 WSPM (wafer starts per month) when it becomes operational in early 2024, which is significantly lower than the fabs that TSMC operates in Taiwan. Consequently, many observers view the project as a method to address some very specific customers serving the U.S. government and military institutions, as well as a way to please the U.S. government that wants to diversify chip supply chains amid its tensions with China. 

Later, it transpired that TSMC considers its Fab 21 project as yet another multi-phase fab, albeit co-financed by the state of Arizona and the U.S. government. TSMC will build its Fab 21 in six phases over many years to come. The first phase will come online in early 2024 and produce chips using TSMC's N5 (N5, N5P, N4, N4P, N4X) family of process technologies, but it is logical to expect subsequent phases to adopt more advanced nodes. 

In any case, a TSMC fab coming to Arizona will strengthen the U.S. semiconductor industry. Meanwhile, it is necessary to note that the world's No. 1 foundry chose Arizona because this state already hosts an Intel mega site, which means access to experienced talent and a variety of relevant suppliers. 

GlobalFoundries: New Facilities for Specialty Chips

Since 2012, when GlobalFoundries's completed its Fab 8, the company has been gradually increasing the production capacity of the facility either by expanding its cleanroom space or by installing more advanced equipment with higher productivity.

Last year, the company announced plans to invest $1 billion to increase Fab 8's capacity from 47,500 wafer starts per month (WSPM) to 60,000 WSPM. Interestingly, GlobalFoundries only shipped 35,700 wafers from Fab 8 in 2021. 

GlobalFoundries's Fab 8 processes wafers using a host of fabrication technologies, including various FinFET-based nodes (14LPP, 14HP, 12LP, 12LP+) as well as NVM, RFSOI, and Silicon Photonics, which are important nodes not only for GloFo's U.S.-based customers but also for the country's national security as the military uses many of GF's chips.  

In addition, GlobalFoundries said it would build an all-new fab in Malta, New York, in a private-public partnership to support growing demand. The company hasn't revealed any information about this upcoming production facility, but given GlobalFoundries's focus on specialty nodes, expect the new chip plant to be aimed at various advanced specialty manufacturing technologies. 

Recently Thomas Caulfield, chief executive of GlobalFoundries, said that GloFo would need financial support from the U.S. government provided under the CHIPS act to build and equip the new fab in New York quickly.  

Samsung Foundry: SF's Leading-Edge Nodes Return to the U.S. 

The Samsung Foundry division was quietly established in the U.S. in 2005 (with U.S.-based Qualcomm being the first customer). Since 2009, it has produced chips for Samsung and third-party customers in Austin, Texas. 

Since Samsung was a part of IBM's common platform alliance (together with AMD/GlobalFoundries, Chartered, Freescale, and Infineon), at some point, it made sense for Samsung Foundry to produce chips using leading-edge technologies co-developed with its partners at its S2 plant in Austin, Texas. As a result, Samsung made its advanced 32nm, 28nm, and 14nm SoCs in Texas. In fact, cross-fab compatibility (and hence flexibility) between S2, S1 (Giheung, South Korea), and GF's Fab 8 provided Samsung with many advantages and put the Texas production facility in a unique position with its 14nm node.

Since IBM's fab club essentially ceased to exist and Samsung needed EUV lithography both for its DRAM and SoCs, it eventually moved its leading-edge node production to South Korea, leaving its S2 fab in Texas with older trailing nodes (14nm/11nm ~ 65nm). But Samsung still has many customers in the U.S. that need leading-edge nodes, so in late 2021 the company announced plans to build an all-new fab near Taylor, Texas. The project will cost $17 billion, and the new facility will come online in the second half of 2024. 

Samsung hasn't formally disclosed which process technologies it will use at its new fab in Texas. Meanwhile, the company indicated that it would use the facility to manufacture chips for 5G, mobile, high-performance computing (HPC), and artificial intelligence (AI) applications starting in the second half of 2024. Timing and target applications clearly indicate that we are dealing with an advanced fab. 

While this is pure speculation, we would expect Samsung to use its Taylor fab to produce chips on various 3nm-class fabrication nodes that rely on GAA transistors. As a result, Samsung will bring its leading-edge nodes back to Texas, which is good news for the company's customers in the U.S. and the country's semiconductor industry. 

But Samsung Foundry apparently has big plans for Texas that span through 2042. The contract chipmaker recently filed 11 applications seeking tax breaks in Austin and Taylor for building new chip plants in the Manor and Taylor school districts. The total cost of the fabs is $192 billion (i.e., $17.5 billion per fab). The initial facilities will come online in 2034, whereas the remaining will start operations by 2042. 

For now, the applications look like a means to secure incentives under the Chapter 313 incentives program that expires this year. Also, this is a good way to demonstrate to various authorities the intentions to invest in the U.S. semiconductor industry. Yet, these applications can hardly be considered even as optioned fabs as semiconductor fabrication facilities will cost significantly more in the looming High-NA EUV era. 

Texas Instruments: $30 Billion for Specialty and Trailing Nodes 

Although Texas Instruments is usually credited for inventing the microprocessor nearly simultaneously with Intel, the company has never become a supplier of general-purpose mass-market CPUs. It even wound down its OMAP mobile SoC business in 2012. But Texas Instruments is the world's largest maker of analog chips. For example, Apple's shiny new MacBook Pro comes with TI's audio amplifiers and USB-C power delivery controllers (these power controllers are used very widely these days). With a portfolio of over 45,000 products, Texas Instruments serves virtually all imaginable applications that need analog chips. 

Texas Instruments runs its own fab as well as outsources some of the components it supplies. Like other chipmakers, TI faced unprecedented demand for its devices during the pandemic and is facing strong demand driven by contemporary industry megatrends (5G, AI, HPC, edge computing, autonomous vehicles). To meet the growing demand for its products, Texas Instruments started to build its new massive fab near Sherman, Texas, this May.  

The new chip plant will be built in four phases, with the first fab coming online in 2025. The endeavor will be the largest economic project ever in Texas; it will cost TI about $30 billion and span a decade. Local authorities approved an incentive package that abates 90% of TI's property taxes for the fab's first 30 years to encourage TI to invest in Sherman and Grayson County. 

There were other reasons why TI preferred Texas over other locations, though. The company already has three 300-mm semiconductor production facilities in the state (including DMOS6 in Dallas, RFab Phase 1 in Richardson, and the soon-to-be-completed RFab Phase 2 in Richardson), so it can share engineering talent between the sites. Furthermore, the company's suppliers are located locally too, so it will be easier to get materials and other goods for the new chip plant. 

Summary 

After years of stagnation, the U.S. is finally getting brand-new chip plants. Intel, GlobalFoundries, TSMC, and Samsung Foundry are set to spend well over $70 billion on U.S. fabs by 2025. If Texas Instruments's massive fab project (that comes online in 2025 and spans for several more years as new phases are built) and subsequent TSMC Fab 21 phases are added, we are looking at investments that might hit the $200 billion mark (or even exceed it) over the next decade. 

To a large degree, such massive investments are made possible by several factors: incentive packages from local authorities, government subsidies enabled by the CHIPS act, availability of engineering talent, and the existing semiconductor production supply chain. Other reasons include geopolitical tensions and the necessity to diversify manufacturing bases. 

The big question is whether the new American fabs are enough to compete against the massive upcoming Gigafab projects in South Korea and Taiwan. The answer isn't clear yet - new chip plants in the U.S. will build chips mostly developed in the U.S. and such centralization might bring some interesting rewards that we yet have to recognize. Meanwhile, the forthcoming fabs in Asia will produce chips designed in the U.S. and China, as South Korea and Taiwan (as countries) haven't yet developed their own chip designing capabilities.  

Intel has hired Suk Lee, a TSMC veteran, to lead its newly established Ecosystem Technology Office. Suk Lee will be responsible for expanding the design technology ecosystem at the Intel Foundry Services division by bringing in additional partners. Ecosystem development is crucial for the long-term success of IFS, Intel's contract chip production business. 

"Very excited to join Intel today," Suk Lee, vice president, Ecosystem Technology Office at Intel, wrote in a LinkedIn post (via news.mynavi.jp/@momomo_us). "Look forward to seeing you soon!" 

Intel currently has its IFS Accelerator program that provides chip designers validated EDA tools optimized for its manufacturing nodes, process-specific silicon-verified IP portfolio, and design service partners. But the IFS Accelerator alliance only included 17 members as of February 2022, so Suk Lee will have to improve it. 

At TSMC, Mr. Lee was vice president of design infrastructure management division. He was responsible for establishing and developing the company's Open Innovation Platform (OIP), the ecosystem of companies enabling the development of chips to be made by TSMC. The OIP design technology ecosystem includes a variety of participants that offer electronic design automation (EDA) tools, IP blocks, design services (front-end and back-end), packaging services, and logistics services. In fact, TSMC's OIP helped numerous chip design startups to become well-known fabless chip suppliers (think Bitmain, Graphcore, and several other developers of chips for emerging applications). 

When Intel established its IFS contract chipmaking business unit last year, it did not really have a lot to offer to potential clients.  

Intel's manufacturing technologies have always been developed with its own products in mind. While Intel decoupled nodes and CPU development to ensure timely product launches, its fabrication processes were still primarily aimed at particular designs (e.g., CPU cores). Many Intel nodes are still CPU-specific, so using them for mobile system-on-chips (SoCs) may not make much sense from a cost and power perspective. Developers of Intel processors have always used proprietary EDA tools with a flow, meaning that a third-party company would have to adopt them (an expensive process) in a bid to work with IFS. Also, Intel did not have any experience with the foundry business or enough internal people to run it. 

For over a year, Intel has been working diligently to make IFS work. It hired many new people and even acquired Tower Semiconductor to obtain more talent, a set of clients, and mature/specialty process technologies. Poaching a high-ranking TSMC executive is a landmark event and is another example of how serious Intel is about its contract manufacturing business. 

Before joining TSCM in 2009, Suk Lee worked at Synopsys, Cadence, and Texas Instruments.

When Intel outlined its IDM 2.0 strategy last year, it said that to build competitive semiconductor manufacturing facilities in the U.S. and Europe it needed governments to subsidize about one third of the investments. Now, Intel is getting massive incentives from local and federal authorities with its latest fabs in the United States and European Union and intends to re-emphasize its position in front of the U.S. Senate next week. 

Earlier this year Intel established its next major manufacturing site in Ohio. Intel intends to invest about $20 billion in two fabs at the site initially with the first fab coming online in 2025. When the site is fully built out, it can house as many as eight fabs that will cost about $100 billion. The site will be Ohio's biggest economic development project in history, but to get the fab, the state had to provide Intel about $2.1 billion in various incentives. In addition, Intel is expected to get funding from the federal government as part of the CHIPS act. Overall, a significant portion of Intel's $20 billion investment will come from government coffers.

But that sums look insignificant when compared to subsidies that Intel is getting from Germany for its $18.7 billion fab project near Magdeburg. The company is reportedly getting about $5.5 billion in state aid, according to officials familiar with the matter cited by Bloomberg. $5.5 billion is about 29.4% of the project's cost. 

But according to Intel CEO Pat Gelsinger, government subsidies are crucial for revival of semiconductor manufacturing in Europe and the U.S. Gelsinger will join Sanjay Mehrotra, the head of Micron, to testify  before the U.S. Senate Commerce Committee on March 23, reports Reuters. 

The two CEOs will substantiate government support for semiconductor fabs by pointing out vulnerabilities of the chip supply chain and its impact on economy at large, advantages of high-tech manufacturing for economy in general, competitiveness with China and national security.  

Intel and Micron are two profitable U.S.-based semiconductor companies that need to invest in new manufacturing capacities to be competitive against Asian-based rivals. But modern semiconductor production facilities are extremely expensive — they may cost well above $20 billion. Companies like Samsung, TSMC, and SMIC receive huge support from their governments either in the form of low taxes or directly. As a result, they can produce huge volumes of chips at relatively low cost. Therefore, to be competitive against these giants, Intel and Micron need government aid, which is what heads of these two companies will tall the Senate next week.

Intel has confirmed its $5.4 billion plans to acquire Tower Semiconductor, just hours after the first unofficial information about the move broke. The deal will boost Intel's IDM 2.0 strategy that involves outsourcing some production to foundries while making chips for third parties at Intel's fabs. The move will also bring in additional capacity of 2 million wafer starts per year to the semiconductor giant's Intel Foundry Services division.

Intel will fund the $5.4 billion transaction for Tower Semiconductor with cash from the balance sheet. The deal is expected to close in 12 months. For $5.4 billion, Intel will get a host of specialty process technologies, including radio frequency (RF), power, silicon-germanium (SiGe) and industrial sensors, extensive IP, electronic design automation (EDA), and customers partnerships. 

"Tower's speciality technology portfolio, geographic reach, deep customer relationships and services-first operations will help scale Intel’s foundry services and advance our goal of becoming a major provider of foundry capacity globally," said Pat Gelsinger, Intel CEO. "This deal will enable Intel to offer a compelling breadth of leading-edge nodes and differentiated specialty technologies on mature nodes – unlocking new opportunities for existing and future customers in an era of unprecedented demand for semiconductors." 

In addition, Intel will get seven fabs: a 150-mm and a 200-mm fab in Migdal Haemek, Israel; two 200-mm fabs in the United States (Newport Beach, California and in San Antonio, Texas); two 200-mm fabs in Japan; and one 300-mm fab in Japan. The fabs in Japan are formally controlled by TPSCo, a joint venture between Tower (51%) and Nuvoton (49%). For now, Intel does not say whether it intends to buy Nuvoton’s stake, or will continue collaborating with the company. Tower Semi’s production capacity is about two million wafers starts per year. 

Intel's acquisition of Tower Semiconductor not only greatly boosts the company's IFS division, but marks another important step in consolidation of the chip industry. Traditionally, Intel has strived to be the leader when it comes to leading-edge nodes and its fabrication processes are still among the most advanced in the industry. The acquisition of Tower Semi is not consistent with Intel's usual strategy, but with Intel's intention to seriously enter the foundry business, Tower Semiconductor broadens its scope with specialty technologies and will help attract appropriate talent, clients, contracts, and partnerships.

"Tower has built an incredible range of speciality analog foundry solutions based upon deep customer partnerships, with worldwide manufacturing capabilities," said Russell Ellwanger, Tower CEO. "Together with Intel, we will drive new and meaningful growth opportunities and offer even greater value to our customers through a full suite of technology solutions and nodes and a greatly expanded global manufacturing footprint. We look forward to being an integral part of Intel’s foundry offering."

Tower competes against GlobalFoundries, Vanguard International Semiconductor, and United Microelectronics Corp. Meanwhile, Intel's IFS will compete against TSMC and Samsung Foundry. The takeover of Tower naturally expands IFS's portfolio of technologies as well as its clients base. That said, it remains to be seen how TSMC and Samsung Foundry will respond to Intel's acquisition. 

Intel is reportedly in talks to buy Tower Semiconductor, a specialty foundry with one 150-mm fab, five 200-mm fabs, and one 300-mm fab. The acquisition will add numerous clients to Intel's foundry business and specialists with extensive experience serving fabless chip designers if the reporting is accurate. 

According to the Wall Street Journal, Intel could announce plans to acquire Tower Semiconductor for approximately $6 billion as early as this week. As a result, Intel would gain access to seven semiconductor production facilities located in three countries. There's a 150-mm and a 200-mm fab in Migdal Haemek, Israel; two 200-mm fabs in the United States (Newport Beach, California and in San Antonio, Texas); two 200-mm fabs in Japan; and one 300-mm fab in Japan. The fabs in Japan are controlled by TPSCo, which is co-owned by Tower (51%) and Nuvoton (49%). It remains to be seen what will happen to TPSCo following the transaction. 

Tower specializes in producing various chips (including analog, sensors, MEMS, mixed-signal, RFCMOS, silicon photonics, PMICs, etc.) using so-called specialty process technologies like BiCMOS, SiGe, and SOI. These technologies aren't cutting edge, but the intended applications do not need to use the latest and greatest nodes. Instead, reliably pumping out large volumes is the primary motivation.  

The specialty foundry business is generally very stable since the lifecycles of products such companies make are very long. In fact, even Intel outsources some of its products to Tower Semiconductor. Meanwhile, specialty foundries do not need to invest hefty amounts of money in research and development (R&D).   

Tower competes against GlobalFoundries, Vanguard International Semiconductor, and United Microelectronics Corp. Some of Intel's products are also made at GlobalFoundries and UMC. Tower is the industry's sixth-largest contract maker of semiconductors, according to TrendForce, and its annual sales were around $1.3 billion in 2020. 

Intel on Wednesday reported its fourth-quarter and full-year 2021 financial results. Fueled by strong demand for CPUs aimed at PCs and servers, the company reported its highest quarterly and full-year revenue ever. Yet, there are some alarming signs, too, as Intel's PC platform volumes continued to drop in terms of units due to supply chain issues, but surged in terms of dollars.

Strong Results, Cautious Outlook

Intel earned $20.5 billion in the fourth quarter of 2021, exceeding its guidance by $1.3 billion and up 3% year-over-year (YoY). Intel's revenue totaled $79 billion for the whole year, up from $77.9 billion in the prior year (GAAP data). One thing to keep in mind is that Intel no longer includes the results of its NAND division in its reports.

As far as the gross margin is concerned, it was 53.6% in Q4 2021 (down 3.2% YoY) and reached 55.4% for the full year (down 0.6% from 2020). Intel has warned that since its 10nm-class process technologies are significantly more complex than its 14nm-class nodes, this generation of manufacturing processes will not allow it to reach gross margin levels of around 60% that were common in recent years. 

As for profits, Intel's net income in Q4 totaled $4.6 billion, down significantly from $5.9 billion in Q4 2020. As for the whole year, Intel's net income for 2021 decreased to $19.9 billion from $20.9 billion in 2020.

"Q4 represented a great finish to a great year," said Pat Gelsinger, Intel CEO. "We exceeded top-line quarterly guidance by over $1 billion and delivered the best quarterly and full-year revenue in the company's history. Our disciplined focus on execution across technology development, manufacturing, and our traditional and emerging businesses is reflected in our results. We remain committed to driving long-term, sustainable growth as we relentlessly execute our IDM 2.0 strategy."

Intel expects to earn $18.3 billion in revenue in the first quarter, which will be in line with Q1 2021. However, since the ongoing quarter includes an additional week due to 2022 being a 53-week year, it looks like the company expects its sales to be lower than in the same period in the prior year. Furthermore, the company's gross margin will drop to 49% (down from 52% in Q1 2021 and down from its 51% ~ 53% guidance for the upcoming years) due to new product ramp-ups, higher costs, and possibly pre-payments for upcoming products.

Client Computing Group: Volumes Down, Prices Up, Again 

Intel's Client Computing Group (CCG), the main cash cow, earned $10.1 billion in Q4 2021, down 7% year-over-year when platform adjacencies are considered, which is unusual for a world that suffers from an undersupply of chips amid growing demand for PCs.

Intel's notebook components volumes dropped by 16% YoY (which is more than what one would expect from Apple's transition to its own SoC and subsequent drop of Intel's sales because of that), but unit sales of desktop components increased 19% compared to the same period a year ago. Because demand for PCs in general and premium systems, in particular, is high, Intel's notebook average selling prices (ASPs) were up 14%, whereas the company's desktop ASPs increased by 11% YoY, which somewhat offset Intel's lower client volumes in Q4.

During the fourth quarter, Intel shipped over 30 million premium Tiger Lake CPUs for notebooks as well as began shipments of its 12th-Gen 'Alder Lake' processors for desktops and laptops. Since all companies tend to ship more expensive SKUs first, the majority of ADL chips Intel sold were probably higher-end models, which naturally drove its ASPs.  

"We are extending our leadership position further with products like our 12th-Gen 'Alder lake,' the fastest client processor ever, which is now shipping to over 140 customers in 30 countries around the world," said Gelsinger. 

Furthermore, the company started shipping its Arc 'Alchemist' discrete GPUs, a product category that barely existed at Intel in Q4 2020. Unfortunately, Intel didn't give details about its discrete GPU volumes and ASPs. 

As for the whole year 2021, Intel's CCG's revenue reached $40.5 billion, up 1% from 2020, which is surprisingly low growth amid the ongoing PC boom. 

Datacenter Group: Growth Is Back, ASPs Moderately Up

While Intel's CCG is the company's cash cow, its Datacenter Group (DCG) is without any doubt its profit generator due to very high ASPs. While the competition from AMD is strong, Intel's DCG continues to perform very well due to the growing demand for servers. 

"We had a record quarter for DCG, where we grew 20% year and year and where we continue to be the partner of choice for cloud and datacenter customers," said Gelsinger.

In Q4, Intel's DCG sales increased to $7.3 billion (excluding Optane, AI accelerator, Ethernet, and silicon photonics products), up from $6.1B in the same period a year ago. Intel says that DCG's shipments to enterprises and governments skyrocketed by 53% YoY nand sales to telco companies surged by 22%, but supplies to hyperscale cloud service provided decreased by 5%. In general, unit volumes were up 17%, whereas ASPs were up 4%. 

All of these organizations primarily bought Intel's 3rd Generation Xeon Scalable 'Ice Lake' processor made using the company's second-generation 10nm technology. Because this particular node brings lower profitability than its predecessors and because of very strong competition from AMD, Intel has to adjust the pricing of its mainstream and higher-end server products. To that end, DCG's operating margin dropped from 34% in Q4 2020 to 24% in Q4 2021, whereas operating profit fell from $2.1 billion to $1.7 billion.  

While Intel continues to control the lion's share of servers made and deployed these days, AMD is gaining share, so Intel chose to reemphasize its position in a rather unusual way. 

"We expect that our Xeon shipments in December alone exceeded the total server CPU shipments by any single competitor for all of 2021," said the head of Intel, implying that AMD's unit share in the server market is still less than 10%. 

But mentioning the whole year might not be a particularly good idea as DCG's earnings for the whole of 2021 totaled $25.8 billion, down 1% year-over-year, a clear indicator that the competition is getting stronger.

Summary

Intel continues to increase revenues and remain profitable as it transits from one business model to another (IDM 2.0) in a bid to regain undisputed leadership in the semiconductor market. For 2021, the company earned $79 billion in revenue (up 1.4% YoY) and posted a $19.9 billion net profit. 

Intel continues to have competitive products in its lineup, but its growth is slowing. Intel's client computer group's revenue for 2021 totaled $40.5 billion, up 1% from 2020, whereas its datacenter group earned $25.8 billion, down 1% year-over-year. The company's profit margins also suffered because of higher 10nm costs, investments in next-generation nodes, outsourcing of some products, and strong competition.  

Despite temporary difficulties, Intel remains optimistic about its long-term growth as it invests heavily in product R&D as well as next-generation process technologies. In the coming weeks, the company will host its Investors Day, where it intends to outline its future plans. 

"As we look back on 2021, we have made tremendous progress across all areas that we have laid out," said Gelsinger. "We still do have a lot of work to do, but we are focused, energized, and our momentum is building. I look forward to sharing our progress with you as we continue on this amazing journey. Our Investor Day is coming up, we are going to lay out the strategy, we got a lot to say."

Intel have today said that it will build its next major manufacturing site in Ohio. The new 'mega site' will be similar to the company's other campuses in Arizona and Oregon, will house up to eight semiconductor production facilities and will cost up to $100 billion when fully built over the next decade. The construction will begin later this year and the first fab will go online in 2025. The initial investment will total $20 billion. 

Intel does not disclose which fabrication technologies will be used by the new fabs, but judging by the timeline of the new site, we can expect the new fabs to be capable of making chips using Intel 25A and Intel 18A nodes (which will be among the most advanced manufacturing technologies in 2025), though we are speculating here. Manufacturing capacity of the new fabs is also unclear at this point since it will depend on actual production process, but it is evident that the new facility will be instrumental to support Intel’s IDM 2.0 strategy that involves internal manufacturing as well as contract production of chips for third parties. 

"Intel's actions will help build a more resilient supply chain and ensure reliable access to advanced semiconductors for years to come," said Pat Gelsinger, CEO of Intel. "Intel is bringing leading capability and capacity back to the United States to strengthen the global semiconductor industry. These factories will create a new epicenter for advanced chipmaking in the U.S. that will bolster Intel's domestic lab-to-fab pipeline and strengthen Ohio’s leadership in research and high tech."

The new manufacturing site will be located near Columbus in Licking County and will span around 1,000 acres (4 square kilometres). Intel says that the new campus will be able to house up to eight semiconductor fabs as well as support operations and ecosystem partners. Initially Intel will invest $20 billion in two fabs at the site, but at full buildout and eight fabs constructed and equipped, the total investment in the site could reach a whopping $100 billion.  

In fact, this new campus will be the largest private investment in Ohio ever and will be one of the making it one of the largest semiconductor manufacturing sites in the world. The initial phase of the project is expected to create 3,000 Intel jobs, 7,000 construction jobs, and tens of thousands of indirect local long-term jobs. In addition to investing billions in its new fabs, Intel will also spend $100 million over the next decade on partnerships with local educational organizations to help local research programs and educate local talent. 

"A semiconductor factory is not like other factories," said Keyvan Esfarjani, Intel senior vice president of Manufacturing, Supply Chain and Operations. "Building this semiconductor mega-site is akin to building a small city, which brings forth a vibrant community of supporting services and suppliers. Ohio is an ideal location for Intel's U.S. expansion because of its access to top talent, robust existing infrastructure, and long history as a manufacturing powerhouse. The scope and pace of Intel's expansion in Ohio, however, will depend heavily on funding from the CHIPS Act."

Intel will immediately start planning for the first two fabs and intends to begin construction in late 2022. It typically takes about a year or more to construct main and supporting buildings and then a further year or more to equip semiconductor fabs. Keeping in mind that the new fabs in Ohio will extensively use extreme ultraviolet (EUV) lithography tools that are larger than modern deep ultraviolet (DUV) scanners and take more time to install, Intel expects that the new facility will become operational in 2025. 

Speaking of manufacturing equipment and materials used by the new manufacturing site, it is necessary to note that Intel’s partners plan to establish local presence to support the new operations. A number of Intel’s partners, including Air Products, Applied Materials, LAM Research and Ultra Clean Technology have indicated such plans.

Thermaltake today announced a new ATX mid-tower chassis featuring a 3.9" LCD screen in front for monitoring PC information or displaying customized images (or GIFs). The case is known as the Divider 550 TG Ultra Chassis and features a tempered glass side and front panels.

Full specifications are not known just yet, but we know is that the chassis is classified as a mid-tower ATX case. It'll feature support for up to 360mm radiators and comes with three ARGB fans that synchronize with all the popular RGB programs today, such as Asus Aura Sync, Gigabyte RGB Fusion, MSI Mystic Light, and AsRock Polychrome.

According to the images shown, it appears the LCD screen is fully mobile and can be attached to either the interior of the case or displayed on the front panel itself. However, this functionality has not been confirmed just yet.

Thermaltake also promises extra GPU positioning with the Divider 550 TG Ultra, allowing for both horizontal and vertical graphics card position with the requirement of purchasing an add-on accessory.

The chassis' aesthetics are similar to most cases on the market, featuring a black interior and black exterior. The only other colors contrasting the black aesthetic will be the ARGB fans pre-installed inside the case.

Pricing and availability of the Divider 550 TG Ultra remain unknown at this time; however, expect more details of this case during Thermaltake's coverage of CES 2022 today. 

Intel has delayed its decision for its new multi-billion chip manufacturing sites in Europe and the U.S. until 2022. The delay will have little impact on an industry that cannot meet the demand for its products now, but it emphasizes the complexity of these decisions.

Intel hoped to announce the next locations in the United States and Europe early next year, which Reuters quotes chief executive Pat Gelsinger as saying at a press conference dedicated to a new chip packaging facility in Malaysia.   

When Intel announced its IDM 2.0 strategy early this year to increase the scale of its semiconductor manufacturing beyond its own products and become a competitive foundry player, Intel needed to build several new production facilities, including several brand-new sites in Europe and the U.S.

These sites, which will cost up to $200 billion, were meant to be unveiled by the end of 2021, but Intel delayed its decisions for unknown reasons and now plans to make the announcements in early 2022. 'Early 2022' is quite vague and could mean any date between January and April. 

This year Intel broke ground on two new semiconductor production facilities — Fab 52 and Fab 62 — at its Ocotillo camp near Chandler, Arizona. These fabs will cost around $20 billion and enhance the production capacity of an already existing site. But building additional fabs on a well-established site and establishing a brand-new site are two very different things. 

Intel admitted earlier this year that its brand-new small city-sized fab complex in the U.S. would cost $60 to $120 billion. The site will eventually host between six and eight fab modules that will make chips using its leading-edge nodes and package them using Intel's proprietary technologies like EMIB and Foveros. 

Intel's plans for European fabs look very similar. The company wants to establish a new site in mainland Europe, build a $20 billion fab there and then construct additional modules, increasing total investments to around $100 billion over time. 

Planning fab sites that will require $100 billion in funding over a decade is complex. Intel needs to build its new manufacturing facilities on land with access to communications and talent, which essentially means proximity to big cities. Furthermore, Intel is looking forward to getting subsidies and incentives from federal and local governments over many years, and fab modules and persuading authorities is hard.  

The brand-new large manufacturing sites are important for Intel and its foundry business as they will enable the company to scale its production capacities in TSMC's manner — relatively quickly and predictably. Yet, the amount of negotiations, considerations, preparations, and arrangements for such fab complexes is incredible, which likely factors into why Intel delayed the decisions and announcements until 2022.

For many consecutive quarters, Intel's revenue has beat estimates. The company's gross margins were high due to strong demand for premium products and conservative spending, whereas the outlook was consistently optimistic as far as revenues and margins were concerned. But this was not quite the case with Intel's third quarter results.

Good Results, Moderate Outlook

Fuelled by strong demand for its datacenter and higher-end client products, Intel's revenue increased to $19.2 billion in Q3 FY2021, some $870 million (or 3%) increase over the same period in FY2020. Meanwhile, Intel's adjusted revenue that excludes its divested NAND storage business totalled $18.1 billion, which fell short of analysts' revenue forecasts of $18.24 billion as well as Intel's own guidance of around $18.2 billion. 

Intel's gross margin in Q3 2021 was 56% (57.8% if NAND business is excluded), up from 53.1% in the same quarter a year ago, but down from historical highs of over 60%. The chipmaker's net income totalled $6.8 billion, down from $7 billion in Q3 2020. 

Yet, investors were disappointed with Intel not only because of lower net income, but due to several other reasons. Intel's results were affected by global components shortage that slowed sales of both client and datacenter parts. Furthermore, the company lost some 20% of cloud datacenter revenue, a direct hit to margins.

"Despite the highly constrained industry-wide supply environment, Q3 revenue was $18.1 billion, slightly below our guidance due to shipping and supply constraints that impacted our businesses," said George Davies, CFO of Intel. 

Given the challenging environment, Intel said it expected revenue of $19.2 billion ($18.3 billion excluding storage business) and a 51.4% gross margin in the fourth quarter. The company maintained its rather bullish revenue forecast for the year at $77.7 billion ($73.5 billion excluding storage unit), but said that its gross margin will decrease to 55% (from 56% in 2020). 

In fact, Intel advised its investors to expect a 51% ~ 53% gross margin for the next two to three years as profitability will be constrained by massive increases of CapEx, R&D, and MG&A spending. For example, this year Intel's CapEx is expected to total $18 billion – $19 billion. But next year the company will increase CapEx to $25 billion – $28 billion, which will be on par with TSMC's and Samsung Foundry's spending on semiconductor production facilities. 

Client Computing Group: Volumes Down, ASPs Up

Intel's Client Computing Group (CCG) remains the company's biggest revenue source. In the third quarter 2021, the business unit earned $9 billion revenue, up $200 million from the same period a year ago. Operating income of the BU was $3.3 billion, down from $3.6 billion in Q3 2022.

"Demand remains strong in our PC business with particular strength in commercial, desktop, and higher end consumer notebooks offset by inventory digestion in lower end consumer and education," said Davies.

During the quarter Intel sold 16% more chips for desktop PCs (including CPUs and chipsets, but excluding various adjacencies) than in the same quarter a year ago and their average selling prices (ASPs) were 4% higher. Yet, unit sales of the company's notebook chips dropped 14% year-over-year and 26% quarter-over-quarter, while their ASPs increased 10%. To some degree, Intel's mobile CPU shipments were affected by Apple's move to its own SoCs, but industry-wide problems perhaps had an even more significant impact.

"CCG revenue was $9.7 billion [including adjacencies], down 2% year over year on a challenging environment and continued industry-wide component shortages that are restricting lower-end system sales," the CFO said. "Note that when excluding the impact of ramping down our Apple CPU and modem businesses, CCG revenue is up approximately 10% year over year."

Intel executed quite well and quickly ramped up its Tiger Lake processor for notebooks in 2020. So far, the company has supplied over 70 million of Tiger Lake CPUs and in Q3 2021 Intel had plenty of competitive chips to sell. Yet PC makers like Dell, HP, and Lenovo did not buy all the CPUs they could have bought due to insufficient supply of other components required to build a PC. On the bright side, Intel sold more high-end processors and enjoyed higher ASPs as computer makers focus on premium models. Yet on the other hand, this means that there are a surplus of lower-end parts in stock.

Datacenter Group: Growth Slowing, ASPs Down

Intel's Datacenter Group has been the jewel in Intel's crown for quite a while. Due to growing demand from hyperscale cloud service providers, strong ecosystem, weak competition from AMD, and little to no competition from other developers. In the last couple of years AMD's Epyc platform and ecosystem became significantly stronger, which is why Intel's share in sales of datacenter processors is dropping. Yet, DCG continues to post strong results.

In Q3 DCG's sales were $5.7 billion (excluding Optane, AI accelerator, Ethernet, and silicon photonics products), up from $5.2 billion in the same timeframe a year ago. Operating income of the business unit was $2.1 billion, up $200 million year-over-year. 

"These results were slightly below expectations due to industry-wide components supply constraints that primarily impacted our enterprise customers and areas of softness in PRC, including cloud as customers adapt to new regulations," said Davies.

Unit shipments of Intel's Xeon Scalable processors surged 8% YoY and ASPs grew 3% YoY. The company shipped over a million of Ice Lake-SP products since April, which probably had a positive effect on margins. 

"Our 3rd Gen Xeon Scalable processor 'Ice Lake' has shipped over a million units since launching in April," said Pat Gelsinger, chief executive of Intel. We expect to ship over one million units again in Q4 alone. All of our OEMs are currently shipping systems, and we expect all our major cloud customers to have announced [Ice Lake-based] instances by the end of the year."

During the quarter Intel's sales to enterprise and governments customers increased by 70% YoY, whereas shipments to hyperscalers dropped by 20%. Intel attributes this drop to new regulations in China, but considering the fact that its rival AMD is gaining share particularly in the cloud datacenter space, it is obvious that AMD is eating Intel's lunch.

Another significant challenge for Intel is that even some server vendors were affected by the shortages, which limited their ability to ship systems and lowered their CPU procurements. Nonetheless, Intel remains very optimistic about its long-term datacenter prospects.

"I remain confident about the long-term of the data center," said Gelsinger. "Despite regulatory changes in China and short-term ecosystem supply constraints impacting some customers, customers continue to choose Intel for the datacenter needs," 

CapEx Spending to Increase: $25 - $28 Billion in 2022

Intel's focus is on high-margin CPU products. Great yields of CPUs on 14nm nodes, and conservative spending on new manufacturing capacities drove Intel's gross margins above 60%. But this is going to change as Intel deploys its IDM 2.0 business model that includes in-house manufacturing, outsourcing, and contract production of chips for third-parties. 

To be competitive against TSMC and Samsung Foundry, Intel will need to invest heavily in new fabs. Next year the company will spend up to $28 billion on new production facilities and it looks like the chip giant will not hesitate to invest even more if it needs to. This will hit margins, but in a bid to be competitive both with chip designers like AMD and Nvidia as well as with foundries like TSMC, Intel needs these investments. 

"We are repositioning the company for long-term growth and we are analyzing the investment plans required to achieve our goals and provide attractive long-term results for our shareholders," said the head of Intel. "It is abundantly clear to us that we must invest in our future right now to accelerate past the rest of the industry and regain unquestioned leadership in what we do. Our investment plan is aligned with our IDM 2.0 strategy to rapidly build our manufacturing capacity and response to the expanding market, grow our share, and accelerate innovation, enabling Intel to leap ahead with new businesses and capabilities." 

Good news is that Intel's Foundry Services unit is developing fast and in Q3 it even shipped some products for revenue as it provided advanced packaging services to AWS.  

"Since March, we have shipped our first IFS packaging units for revenue and engaged with well over a hundred potential customers, including several large customers who are working with us on our leading-edge Intel 18A [node]," said Gelsinger.

Summary

While Intel missed its revenue guidance for Q3 2021, the company still posted higher YoY revenue and profits. Unfortunately for the company, its financial results were affected by industry-wide shortage of components that constrained CPU sales to PC and server makers, which adds uncertainty to Intel's short-term business prospects. Meanwhile, as Intel's partners focus on higher-end products, Intel's ASPs remain high. 

As Intel is deploying its capital-intensive IDM 2.0 business model, the company's CapEx spending will surge and so will R&D expenses, which will affect the company's margins. Intel assures investors that its gross margin will not drop below 50%, though only time will tell whether IDM 2.0 model will be financially successful for Intel. Meanwhile, Intel's CEO is very confident that the company will be able to leapfrog the whole industry and set new records in profitability. 

"Leadership products beget leadership pricing, which begets leadership margins," said the head of Intel.

Intel has revealed some additional details about its upcoming brand-new fab complex in the U.S. Patrick Gelsinger, chief executive of Intel, said that the new fab campus will cost between $60 billion and $120 billion, will include multiple modules capable of processing wafers using Intel’s advanced process technologies, and chip packaging facilities. In addition, the company aims to build it adjacent to a university to simplify the hiring of new personnel. 

As part of its IDM 2.0 strategy, Intel is set to decide on the exact location of its next major semiconductor manufacturing hub in the U.S by the end of this year. The fab will include between six and eight modules that will produce chips using the company’s leading-edge fabrication processes, will be able to package chips using Intel’s proprietary techniques like EMIB and Foveros, and will also run a dedicated power plant, Pat Gelsinger said in an interview with the Washington Post.  

Each semiconductor fabrication module will cost between $10 billion and $15 billion, so Intel’s investments into the hub over the next decade could be as ‘low’ as $60 billion and could top $120 billion.

“We are looking broadly across the U.S.,” Gelsinger told the Washington Post. “This would be a very large site, so six to eight fab modules, and at each of those fab modules, between 10- and $15 billion. It's a project over the next decade on the order of $100 billion of capital, 10,000 direct jobs. 100,000 jobs are created as a result of those 10,000, by our experience. So, essentially, we want to build a little city.”

At this point, Intel does not disclose which nodes the first module of the fab will support. Yet, since it will start operations sometime in 2024 at the earliest, the new facility will probably produce chips using the Intel 4 and the Intel 3 manufacturing technologies. Eventually, the fab complex will adopt more advanced fabrication technologies. The production capacity of the upcoming fab is unknown, so is its location. Intel needs to build its next manufacturing in a location with well-developed infrastructure, adequate supply of water and energy. Also, the company plans to build it near big cities with universities in a bid to higher qualified personnel. 

“We're engaging with a number of states across the United States today who are giving us proposals for site locations, energy, water, environmentals, near universities, skill capacity, and I expect to make an announcement about that location before the end of this year,” Gelsinger said.

Earlier this year, Intel outlined plans to spend $20 billion on advancing its manufacturing operations in Arizona. In addition, the company will announce a location for its brand new fab hub, such as those the company has in Arizona and Oregon.

A minister of the German state of Bavaria has confirmed that the state is in discussions with Intel about building a local fab, Reuters reported today. Economy Minister Hubert Aiwanger did not detail how the negotiations were proceeding but indicated that Bavaria offered Intel at least one possible location.

Pat Gelsinger, Intel's CEO, visited Europe in April to discuss building a state-of-the-art semiconductor fab there to support the company's IDM 2.0 strategy comprised of vast in-house manufacturing, some outsourcing and offering contract manufacturing services under the Intel Foundry Services moniker. 

Intel hopes to get some €8 billion ($9.7 billion) in government subsidies, which may include incentives like tax breaks and direct investments. This could be a hint that the chip giant plans to build a fairly large fab in continental Europe that could cost around $25 billion or more.

Intel's actual plans for the fab are yet to take shape, but Bavarian officials have already proposed an abandoned air base in Penzing-Landsberg near Munich as a potential location for the fab.

"I strongly support this," Aiwanger said as per Reuters. "The possible location of a large international semiconductor manufacturer in Bavaria is an outstanding opportunity."

Intel has been operating its fabs near Leixlip, Ireland since the 1980s, so the company is not new to Europe. Adding an additional location, however, would help it ensure sufficient production capabilities for existing clients and future fabless customers when Intel starts to offer manufacturing services. 

Intel plans to disclose formal plans for its fab in mainland Europe by the end of 2021. Besides Germany, the company is also considering Belgium, the Netherlands and Luxemburg.

Intel is committed to building a leading-edge fab in Europe, but to do so the company will need almost $10 billion in subsidies, CEO Pat Gelsinger said in an interview with Politico Europe, as confirmed by Reuters. The exec pointed to the need for $9.7 billion in subsidies during a visit to Europe, where he met with politicians and business executives and landed on Germany and Benelux as good candidates for Intel's new fab. 

"Geopolitically, if you're in Europe, you want to be in continental Europe," Gelsinger told Politico. "We think of Germany as a good candidate -- not the only, but a good candidate -- for where we might build our fabrication capabilities." Other candidates include Belgium, Netherlands and Luxemburg. 

Building semiconductor production facilities in Europe and the U.S. is tricky financially. Intel has to compete against South Korean and Taiwanese rivals that enjoy lower taxes, labor costs and government incentives. In fact, incentives and subsidies have historically made Taiwan a semiconductor boon.  

"What we are asking from both the U.S. and the European governments is to make it competitive for us to do it here compared to in Asia," Gelsinger said in an interview with Politico Europe, according to Reuters.

A plan to get some €8 billion ($9.7 billion) in subsidies, which may include incentives like tax breaks and direct investments, indicates that Intel is looking to build a fairly large and advanced fab in Europe. The project hasn't begun to take shape yet, so it's hard to accurately speculate on the fab's specific purposes. However, wouldn't be surprised to see a $25-$35 billion fab used to make both Intel's own and third-party products. 

Intel already has a site in Ireland that has been home for the company's advanced fabs since the late 1980s. Right now, Intel is constructing a new EUV-ready fab at the site that will make chips using Intel's 7nm fabrication technology. So far, Intel has invested approximately $22 billion (€18.6 billion) in its camp near Leixlip, Ireland.  

But Intel needs more capacity as it engages into its IDM 2.0 strategy that involves internal manufacturing, outsourcing and offering contract manufacturing services under the Intel Foundry Services brand. As part of its IDM 2.0 plan, Intel already announced intentions to invest $20 billion in two new manufacturing facilities in Arizona.  

This week, Gelsinger also reportedly met with execs from BMW, Deutsche Telecom and Volkswagen. He also met with Peter Altmaier, German Economy Minister, to discuss options. In addition, he met with executives from BMW and Deutsche Telecom, two long-time Intel customers. Some sources also noted that Gelsinger visited headquarters of Volkswagen Audi Group, though the chip giant has not confirmed this.