Intel on Thursday published its financial results for the second quarter of 2026, posting revenue of $16.1 billion — a 25% rise year-over-year — amid high demand for client and data center products. The company also said that due to extraordinary demand for its own CPUs, it will initiate mass production using its 14A (1.4nm-class) fabrication technology in 2028, which is in line with TSMC's plans for its A14 process technology.

"With encouraging external customer progress and increased demand for our internal products, we remain on track for 14A risk production for our internal products in the second half of 2027, and we made the decision in Q2 to fully commit to high volume ramp in 2028," said Lip-Bu Tan, chief executive of Intel, during the company's earnings call with financial analysts and investors.

Typically, companies initiate high-volume manufacturing (HVM) using a new process technology about a year after initiating risk production. Assuming that Intel intends to start risk production using 14A in the second half of 2027, it is reasonable to expect the company to start 14A HVM in the second half of 2028. It remains to be seen whether by the 'second half' Intel means July or December. If Intel initiates high volume ramp in November or December 2028, actual products made using the technology will emerge in 2029. In any case, Intel typically begins manufacturing using its leading-edge nodes in its development fab in Oregon and while it formally calls it HVM, actual volumes produced at such fabs are relatively low.

Another thing to note about Intel's 14A is that in 2028 it will start making its own products using this process, not products from external customers. Apparently, Intel still does not have any external clients that have committed to use the technology to make their products.

TSMC typically initiates production using its latest nodes in December and usually calls it the 'second half of the year.' Assuming that it follows the same pattern with A14 (though the progress of the node can enable the company to pull mass production in provided that customers' designs are ready), then the volume ramp will occur in 2029. TSMC claims that multiple customers have already taped out their ICs on A14.

Intel reported a strong second quarter as its revenue reached $16.1 billion, up 25% year-over-year and $1.8 billion above the midpoint of its guidance. Formally, Intel's GAAP losses reached a whopping $11 billion. However, this was driven by the $13.619 billion of mark-to-market losses on Escrowed Shares related to Intel's CHIPS Act Secure Enclave agreement with the U.S. government. Meanwhile, the company's non-GAAP net income was $2.2 billion, which reflects profitable underlying operations. The company's GAAP gross margin increased to 40.1%, up from 27.5% in Q2 2025. Intel's Operating cash flow totaled $7.0 billion, prompting the company to raise its capital spending outlook for both 2026 and 2027 as AI-driven demand continues to exceed available supply.

Intel's Client Computing and Physical AI Group (CCPG) generated $8.9 billion in revenue, up 13% year-over-year. The company confirmed that the CCPG result was not driven by increased unit sales, but was a result of higher average selling prices (ASP) due to supply constraints.

"Client obviously exceeded expectations. I would say it was largely ASP, of which some of that was mix related, some of that was our own like-for-like changes in ASPs where we thought we had seen some inflation on our cost and needed to pass that on to the end customer," said David Zinsner, chief financial officer of Intel, during the call.

The Data Center and AI (DCAI) business delivered the strongest growth as its sales climbed 59% year-over-year to $6.3 billion amid surging demand for Xeon processors, expanding AI infrastructure deployments, and rapidly growing purpose-built silicon sales.

"Q2 year-over-year server growth was the strongest on record, Xeon 6 continue to be one of the fastest ramping products in Intel history, reflecting improving execution and strong customer demand," Tan said.

"We also continue to see strong momentum in our purpose-built silicon product line, with revenue up roughly 20% sequentially and nearly tripling year-over-year," Zinsner said. "Purpose-built silicon revenue nearly tripled year-over-year."

Intel Foundry posted $5.8 billion in revenue, an increase of 31% year-over-year, as Intel 18A production ramped. At the same time the production units losses dropped to $2.1 billion — down from $2.4 billion in the previous quarter and $3.2 billion in the same quarter a year ago. External foundry revenue reached $293 million.

"Intel Foundry operating loss in Q2 was $2.1 billion and $348 million better quarter-over-quarter as higher yields improved cycle times and increased factory scale across Intel 4, Intel 3, and 18A drove improved wafer costs," Zinsner said.

Intel guided its third-quarter revenue to $15.8 billion – $16.8 billion and a projected non-GAAP gross margin of 42% and an EPS of $0.38.

Intel has resolved wafer-to-wafer yield variability issues with its 18A process technology, according to a report from BlueFin Research Partners. If the report coming from an unofficial source is accurate, then Intel can expect consistent and predictable yield improvements for its products made using the latest 1.8nm-class node from now on.

"Intel 18A wafer-to-wafer yield issue resolved; ramp to 12-15K wpm at both sites ongoing," BlueFin Research Partners wrote in a note to clients.

If the information is accurate, then products made using Intel's 18A process technology will no longer be plagued by wafer-to-wafer variability, an issue where good wafers and poor wafers are produced in the same production flow. However, wafer-to-wafer variability is only one contributor to yield loss, so fixing it means that Intel can now consistently improve product yields, but it does not necessarily mean overall yield is where Intel wants it to be.

Generally, a die yield defined by multiple factors, including defect density (which in turn is defined by random defects and systematic defects), within-wafer variability (differences between the center and edge of the same wafer when it comes to things like critical dimensions uniformity, line edge roughness, or stochastics; something that Intel has been improving recently), wafer-to-wafer variability (die yield and/or parametric yield differ from wafer to wafer), and packaging yield. When it comes to actual products, we should mention parametric yields (dies may be defect-free, but they do not meet performance and/or power specifications) as well as reliability screening (dies are functional and meet required specifications but fail burn-in tests).

That said, saying that Intel has 'fixed wafer-to-wafer yield issues' most likely means the process is now much more consistent from wafer to wafer, which clearly reduces lot-to-lot variation and makes production more predictable. However, it does not mean that defect density has reached target levels, parametric yield is optimal, and overall economic yield is where Intel wants it to be. What it does mean is that at a consistent yield improvement level (Intel once mentioned 7% per month for 18A), Intel is set to reach its target goals within a predictable timeframe.

In addition, the report claims that Intel now has capacity of around 30,000 wafer starts per month across its D1X development fab (presumably module 3) in Oregon and Fab 52 high-volume fab in Arizona (confirmed by @Alex_Intel_), which is a solid result at this point of the ramp cycle. However, without information about overall die yields and parametric yields of Intel's 18A products, it is hard to assess whether Intel can now produce enough Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' processors. Meanwhile, it should be noted that using a development facility for high-volume manufacturing (HVM) is costlier than using a fab that was designed to be an HVM fab from the start.

Meanwhile, it looks like Intel is set to continue such a practice with its next-generation 14A (1.4nm) fabrication process, according to BlueFin. The company plans to make 'D1X the initial HVM fab for 14A,' whereas the first phase of Intel's Ohio One semiconductor manufacturing site in Ohio will serve as the second HVM facility to make 14A chips, BlueFin claims. Intel recently confirmed that it intends to initiate high-volume production of chips using 14A in 2029. Ohio One first phase (Mod 1) is set to be completed in 2030, which means that it will come online 'between 2030 and 2031,' according to Intel.

Tesla has hired Gary Jiang, an Intel veteran who most recently was responsible for installing equipment and transferring Intel's leading-edge 18A technology process from development fab in Oregon to the company's high-volume fab in Arizona, as spotted by Electrek.co. The appointment marks the first publicly identified senior leadership hire for Elon Musk's semiconductor production project, Terafab, which demonstrates Tesla's effort to build an experienced semiconductor manufacturing organization from the ground up by hiring veterans from other companies.

Tesla poaches an Intel veteran

Gary Jiang joined Tesla in June 2026 after spending over 17 years at Intel, according to his LinkedIn profile. Interestingly, there is little to glean about his current role from his LinkedIn profile, aside from noting that he is a director at Tesla. His final position at Intel was as Factory Manager, where he oversaw the construction of the production facility, the installation of fabrication equipment, factory startup, product certification, preparation for high-volume manufacturing, and, ultimately, the transfer of Intel 18A technology from the development fab in Oregon to high-volume Fab 52 in Arizona.

Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies (which include Intel 10nm SuperFin and 10nm Enhanced SuperFin/ Intel 7) at Fab 32 and Fab 42.

Tesla has been looking for a Technical Program Manager (TPM) for semiconductor infrastructure, focused on end-to-end fab program delivery, since March, but without any success, as the job listing is still listed on the company's website. Therefore, Terafab — the joint initiative between Tesla, SpaceX, and xAI — still does not have a formal leader who is going to lead the whole project.

In his most recent role at Intel, Gary Jiang worked closely with supply chain, finance, and materials logistics for new factory planning for output, wafer cost, yield, and profit & loss, according to his LinkedIn profile. He also managed the billion-dollar capital equipment and startup of the fab. Hence, without any doubt, Jiang appears to have been one of the senior manufacturing leaders responsible for building and equipping Intel's new 18A-capable manufacturing facilities in Arizona (primarily Fab 52, and potentially Fab 62 as the campus expands). However, it would still be inaccurate to say he was the person responsible for building Fab 52 alone.

Jiang's skills roughly match what one would expect from a senior manufacturing executive helping commission a new leading-edge fab, so he will be instrumental in turning a newly constructed fab shell (or even cleanroom) into a production-ready semiconductor manufacturing facility.

However, he did not oversee the entire Fab 52/Fab 62 program and was not responsible for every stage of the project — from permitting and groundbreaking to construction, tool installation, and the ramp to high-volume manufacturing. Likewise, he is unlikely to lead the Terafab project as a whole. Nonetheless, given that Terafab is set to license Intel's 14A process technology, Gary Jiang is probably among the best candidates to equip a fab for an Intel manufacturing node.

One major caveat

In fact, one of the most confusing parts about Tesla's hiring people to work at Terafab is that Tesla itself will not own any high-volume semiconductor production facilities; SpaceX will, according to Elon Musk.

In the near term, Tesla plans to build a $3 billion semiconductor R&D center at its Texas campus. The facility will house a small pilot line capable of processing a few thousand wafers per month to develop and validate new manufacturing technologies before they are scaled for commercial production.

Once the pilot line shows signs of success, SpaceX is expected to construct a full-scale high-volume manufacturing fab. However, coordinating a joint project between Tesla and SpaceX will add complexity, as major decisions require approval from both companies' boards and must undergo conflict-of-interest reviews, which will likely slow execution.

That said, given that Gary Jiang was hired by Tesla, not SpaceX, his responsibilities could be to equip and ramp a development facility at its Gigafactory Texas campus rather than build, equip, and ramp a high-volume fab for SpaceX. In any case, we are speculating here, and nothing can really stop SpaceX from hiring Jiang at some point down the line.

SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm, tighter than the 36nm pitch shipping in Intel’s Panther Lake chips on 18A. The analysis was conducted on a HiSilicon Kirin 9030, the processor found inside Huawei’s Mate 80 phones and built on the N+3 process, which SemiAnalysis says trails Intel’s 18A high-density library by 38%. The SemiAnalysis Teardown Engineering & Evaluation Lab (STEEL) has been opened in Hillsboro, Oregon, and built to take on TechInsights in advanced-node reverse engineering.

A 36nm pitch is what Panther Lake ships with, but the 18A process on the whole supports a 32nm minimum metal pitch. With Panter Lake, Intel opted to relax the pitch because routing power through the back of the wafer — via PowerVia — clears the front-side metal stack for signal wiring.

Intel has said doing this buys roughly 10% higher density and looser front-side pitches, which is how a node built on GAA RibbonFET transistors and backside power can ship a wider local pitch than a DUV Chinese process and maintain a wide overall lead. SMIC reached 32.5nm without EUV lithography, leaning on DUV tools and quadruple-patterning that needs extra masking and etch passes.

Counting transistors per area, SemiAnalysis put N+3 at 113.4 million per square millimeter, just ahead of TSMC's mature N6 at 107.7 million and well behind 18A. SMIC got there by spending every density trick available without EUV: two fins per transistor, contacts landed directly over the active gate, and single diffusion breaks between cells.

Each of those workarounds obviously adds complexity and cost, with N+3’s ceiling ultimately showing a huge trade-off. The Kirin 9030 Pro's prime core runs at 2.75 GHz and lands near Arm's 2021-era Cortex-X2 per clock, leaving the chip roughly level with Android flagships from three years ago and behind current parts from Apple, Qualcomm, MediaTek, and Samsung. Huawei’s roadmap does say that it’s targeting 5 GHz by 2031, but, as SemiAnalysis notes, that’s “far beyond what planar scaling alone could deliver.”

SemiAnalysis said it spent the past 18 months building the lab and has already earned revenue analyzing datacenter silicon. “We have already generated revenue on advanced datacenter chip teardowns, including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack.”

The company is taking aim at the Ottawa-based TechInsights, which is backed by private equity and held by the likes of Oakley Capital and CVC Growth. SemiAnalysis claims its rival is up for sale and has underinvested in equipment as a result, though that hasn’t been officially confirmed. The teardown also found the Kirin 9030 Pro carrying Samsung LPDDR5X memory, with 16 GB variants turning up DRAM from Chinese maker CXMT as well.

Intel is ramping up production of its CPUs on its 18A (1.8nm-class) process technology with promising results, but at the same time, the work on its enhanced version called 18A-P is well underway with production readiness looming in the coming quarters. The company's 18A-P introduces two new types of transistors, tighter process variability control, and improved thermals to enable higher performance and lower power consumption. This is perhaps why Apple and other fabless chip designers are rumored to be considering using 18A-P.

When compared to Intel's baseline 18A, 18A-P fabrication process promises to enable chip developers to either increase the performance of their designs by 9% (at the same power) or lower their power consumption by 18% (at the same performance and complexity), according to a paper Intel released at the VLSI 2026 conference. To achieve these improvements, Intel introduced new types of gate-all-around RibbonFET transistors, including high-performance devices with enhanced contacts as well as new low-power devices. Designers can now push higher frequencies on critical paths and reduce power consumption in less demanding regions, which greatly improves overall performance efficiency.

Meanwhile, 18A-P retains contacted poly pitch (50nm) and library heights (180nm and 160nm) of 18A as well as design compatibility with the base process, meaning that a chip originally designed for 18A can be ported to 18A-P and benefit from certain process-level improvements (which do not rely on new transistor types), though to fully realize performance and efficiency gains requires design re-optimization.

Another major improvement of 18A-P over 18A is -30% skew corner tightening, which also reduces variability and improves yield efficiency. The enhancement narrows the spread between fast and slow silicon and makes it closer to 'typical' silicon as well as center-to-edge variation across the wafer. Also, the production node adds extra threshold voltage (VT) options (over 5+ pairs of logic VTs compared to 4 pairs in 18A) to enable finer-grained binning and more consistent chip behavior, which increases the proportion of dies that meet target specifications. This improves parametric yield and enables chip designers to get more higher-end silicon from a single wafer. Meanwhile, tightening of process corners does not affect defect density as existing challenges with line-edge roughness (LER) and stochastic variability remain intact.

While Intel's 18A-P retains the contacted pitch of the base node, the company still tweaked the resistance and capacitance of its metal stack, which impacts signal speed, power consumption, and timing. Yet, Intel does not characterize the changes.

Last but not least, 18A-P introduces enhancements in thermals, reliability, and voltage behavior that are critical for an advanced process technology aimed at both client and data center applications. Intel says it improved thermal conductivity by 50%. Lower thermal resistance helps manage higher power densities associated with GAA transistors, which is important for client applications. Improved logic negative-bias temperature instability (NBTI) enhances long-term device stability under high-voltage stress, which is critical for data center processors. Finally, 18A-P better aligns logic and SRAM minimum operating voltage (Vmin) to improve low-voltage operation and stability.

Intel's 18A-P is a heavily optimized version of 18A-P that not only promises higher performance efficiency but also addresses things like parametric yields, thermals, and reliability. Altogether, these enhancements make 18A-P a more mature and attractive version of 18A, not only for Intel, but also for potential external customers like Apple.

One of the highlights of Intel's first-quarter earnings report last week was improved sales of its client and data center processors as a result of improved output and yield, as well as high demand. Last week, industry analyst Ben Bajarin said the company was now selling what would normally be 'scrap' or 'low-expectation' CPUs, which helped boost margins. We followed up with industry veteran Dan Hutcheson for more details, and he notes that some of the company's recent yield gains are less about breakthrough inventions and more about disciplined execution improvements under its new manufacturing leadership.

Dan Hutcheson, vice chair of TechInsights, told Tom's Hardware that while techniques like binning and statistical process control (SPC) have been standard practice at Intel for about 40 years, recently — starting from around late 2024 when Naga Chandrasekaran, the current head of Intel Foundry, joined the company — Intel focused on tightening yield distribution across the wafer by reducing edge-related variability.

Specifically, Intel now runs a continuous process improvement (CPI) program after a node enters high-volume manufacturing, so by now it has implemented certain edge-specific process correction methods in a bid to reduce quality variability from the center to the edge of a wafer to get more sellable silicon from a single wafer.

"When it comes to manufacturing, it takes a year or two to make these kind of dramatic changes," Hutcheson told Tom's Hardware. "There’s just nothing new here. Intel has binned lots since the 1980s. Yield distributions are always heteroscedastic from the center to the edge of the wafer. Actually, one of the things Naga Chandrasekaran's yield management efforts have changed is to narrow the spread to the edge of the wafer. Hence, they are getting more revenue-per-wafer for little cost. The beauty of it is that the improvements are node independent."

As a result, Intel can now extract more high-quality dies from a single wafer and, perhaps even more importantly, more sellable dies from a single wafer, which improves output and productivity. Essentially, chips that previously might have been scrapped or too marginal to sell are now binned into lower-tier SKUs and sold because the demand is strong, according to Ben Bajarin, chief executive and principal analyst at Creative Strategies.

"Got some clarity from Intel IR on additional lift to margins," Bajarin wrote in an X post. "Intel got an unexpected margin lift from better yield salvage. Chips that would normally have been lower-value edge-die on the wafer were binned down and still sold into usable SKUs, turning what may have been scrap or low-expectation output into incremental revenue. Customers did not care, just said 'I will take it all.' That is the demand environment we are in for CPUs."

This can be interpreted in different ways, but it is feasible that the yield distribution improvements have made lower-quality chips now viable products, or that the company created even lower-tier SKUs to harvest even more chips.

More importantly, the aforementioned tightening yield distribution improvements are said to be largely node-independent, which means they benefit multiple process technologies rather than the existing nodes, such as Intel 7/4/3. Indeed, there are many ways to reduce edge-related variability, and many of them are node independent, which means some of the methods developed at Intel should be applicable to 18A (though that isn't confirmed). In fact, one of the comments Intel made during its earnings call is that the yield curve of 18A progresses at a pace that is higher than expected.

"Lip-Bu had a [18A yield] target as we came into this year for the end of this year, and we are probably going to hit that probably the middle of this year," said David Zinsner, chief financial officer of Intel. "So, you know, he has done a very good job working the team to drive a better response there."

Intel on Thursday published its financial results for the first quarter, and its stock rocketed 28% in after-hours trading, hitting an all-time high of $80.01. The results saw Intel significantly beating its own outlook by $1.4 billion due to rising demand for data center-grade CPUs, decent demand for client products, and increased output and productivity at Intel's own fabs. Despite results that are well above seasonality, the company still posted a rather massive $3.7 billion loss as it wrote down Mobileye goodwill and restructuring charges. However, the results can be considered positive as on a non-GAAP basis, the company recorded $1.5 billion in net income.

"We delivered robust Q1 results, reflecting the growing and essential role of the CPU in the AI era and unprecedented demand for silicon, as well as our disciplined execution to expand available supply," said David Zinsner, Intel CFO. "We remain focused on maximizing our factory network to improve available supply and meet our customers’ needs throughout the year."

In the first quarter of 2026, Intel earned $13.6 billion in revenue, up 7% year-over-year (YoY), and flat with the fourth quarter of 2025, meaning that the results are well above seasonality. The company's R&D and SG&A expenses totaled $4.4 billion, down 8% from $4.8 billion in the same quarter a year ago, whereas its gross margin increased to 39.4% from 36.9% in Q1 2025. In addition, Intel generated $1.1 billion in cash from operations. Nonetheless, the company recorded a $3.7 billion GAAP loss in the first quarter of 2026, up massively from $800 million in Q1 2025.

However, the loss is a result of a $4.07 billion 'restructuring and other charge,' which includes a $3.447 billion (primarily) Mobileye goodwill impairment charge and $623 million restructuring and other charges. That said, the losses were largely driven by accounting charges required under GAAP, rather than weakness in Intel’s core product business, although the company’s foundry division continues to generate significant operating losses.

Intel Products: Better than before, worse than could have been

At a high level, Intel's product business is clearly stabilizing. Among improved demand, the company attributes its improved business results to higher output and productivity of its own fabs that make chips on its Intel 7/4/3 process technologies. Nonetheless, Intel admits that it cannot meet all the demand, which limits its growth.

The Client Computing Group (CCG) generated $7.7 billion in revenue, $2.5 billion operating income, and 32.6% operating margin in Q1 2025, which is clearly up from $7.6 billion revenue, $2.4 billion operating income, and 30.9% operating margin in the same quarter a year ago. Keeping in mind that sales of PCs in the first quarter were affected by the turmoil on the DRAM and storage markets as well as demand outstripping supply (partly because Intel continues to shift some capacity from client to data center products) CCG's results can be considered good.

" Even with improved factory output demand outstripped supply against a client TAM that remains resilient despite industry-wide component shortages and inflationary pressures," Zinsner said. "Our AI PC revenue grew 8% sequentially and now represents greater than 60% of our client CPU mix."

The Data Center and AI (DCAI) increased its earnings to to $5.1 billion, up 22% year-over-year and up $400 million quarter-over-quarter. Perhaps more importantly, the business unit's operating margin increased to 30.5%, and it generated $1.5 billion in operating profit (up from $0.6 billion a year before).

This growth reflects a meaningful shift in demand: hyperscalers are deploying more CPUs alongside accelerators as AI workloads move from training toward inference and agentic workloads. Intel claims this marks a structural change in the AI stack as CPUs reclaim their role in the data center and are set to increase attach rates per GPU, which remain primary compute engines. In addition, Intel cited yield and productivity improvements at its Intel 3-capable facilities that produce Xeon 6 processors as major factors for increased margins and profitability of DCAI.

Intel's 'All Other' segment — which includes Mobileye and IMS mask writing services — remains small after deconsolidation of Altera in Q3 2025. During the quarter, its revenue totaled $628 million, down 33% year-over-year (largely due to the deconsolidation of Altera), but at the same time, the segment generated $102 million in operating income, which is good news as it lost $8 million in the previous quarter.

Intel Foundry: Produces gems, absorbs losses

Intel's Foundry division produces the company's most profitable products for client and data center applications and also absorbs all the losses of the company. The division generated $5.4 billion in revenue last quarter (up from $4.7 billion in Q1 2025), but posted an operating loss of roughly $2.4 billion (up from $2.3 billion in Q1 2025), which means an operating margin near -45%.

The current result reflects higher output (which drives revenue) as well as the early 18A ramp (which generates higher losses). Essentially, Intel Foundry absorbs the full cost of ramping 18A, including low yields, high depreciation, as well as heavy R&D spending on future nodes like 14A. While Intel highlighted improving yields across all of its latest nodes (7/4/3) and growing advanced packaging backlog, external foundry revenue remains minimal, and meaningful customer-driven volume is unlikely before late 2026 or 2027 with 18A or even later with 14A. One thing to keep in mind here is that EUV-based Intel 3/4/18A nodes still represent a minor share (over 10%, probably less than 20%) in Intel's total product mix, which leaves a lot of space for growth.

Intel's messaging during the conference call with investors and analysts emphasized Foundry's progress: better yields, improving factory output, and increasing customer engagement, including partnerships with companies like Google and participation in large-scale initiatives such as TeraFab. While these are important signals, they do not yet translate into financial success for the foundry business.

Q2 2026 outlook

Intel expects its second quarter of 2026 to show modest sequential growth and projects revenue to be from $13.8 billion to $14.8 billion and non-GAAP gross margin of 39%.

The company's management expects demand for data center CPUs to remain strong, as well as demand for client processors to remain robust, as many PC makers have accumulated enough DRAM and 3D NAND for their systems. However, Intel warns that demand may outstrip supply and also says that in the second half of the year, memory and SSD supplys will be depleted, forcing PC makers to obtain their memory at spot prices, passing increased costs to consumers, which will hit PC sales. In addition, as Intel will increase output of its Core Ultra 3-series Panther Lake processors by six or seven times in Q2, its margins will take a hit.

Intel this week announced that Shawn 'Seung Hoon' Han will join the company as senior vice president and general manager of Foundry Services, where he will be responsible for working with external customers. Shawn Han will join the company from Samsung Foundry, where he had similar responsibilities, and will bring decades of valuable experience at a contract chipmaker, something that Intel Foundry needs these days.

"I am excited to welcome Shawn Han to our leadership team," wrote Naga Chandrasekaran, executive vice president and the head of Intel Foundry, in a LinkedIn post. "Shawn will be joining us in May as senior vice president and general manager of Foundry Services, reporting to me. Shawn brings valuable expertise in the semiconductor industry from his three decades at Samsung, including most recently overseeing sales at Samsung Foundry. He also offers impressive technical acumen from his work on multiple logic process nodes beginning in 1996."

As the head of Foundry Services — a structure within Intel Foundry responsible for working with customers in general and external customers specifically — Shawn Han will be responsible for sales and customer relations, which includes landing external customers. More recently, Shawn Han served as executive vice president of Samsung Foundry, which he joined from Samsung Semiconductor in 2021.

Shawn Han will become the highest-ranking executive focused on foundry customer engagement that Intel has hired to date. While the company has traditionally hired leaders focused on product or process technology development, Han has spent the last five years specifically on customer-facing roles.

The hire indicates that Intel Foundry understands its next bottleneck is not just process technology, but customer acquisition, trust, and long-term relationships. While Intel Foundry may have a great value and technology proposition with 18A, 14A, EMIB, and Foveros, external foundry customers do not sign multi-year deals because the node deck looks good, but because they believe Intel Foundry can behave like a real contract chipmaker offering predictable PDKs, realistic timelines, predictable yields, sufficient capacity, and responsive support. Hiring someone who has already lived in a customer-centric foundry world is a good way to achieve that trust and relationships with customers. At the end of the day, Intel yet has to persuade its potential customers that Intel Foundry can offer the same discipline, neutrality, and customer obsession that pure-play foundries have in their blood.

The timing of the hire seems to be right, too. Intel has been trying to land customers with its 18A, 18A-P,14A nodes, and advanced packaging for a while now, and while the company continues to say that the interest towards its process technology is high, interest is not the same thing as booked wafer volume. Therefore, one of Han's main tasks will be converting technical curiosity into committed business.

For sure, Shawn Han's knowledge of potential customers' needs as well as his personal relationships with Samsung Foundry customers will be added bonuses to Intel's Foundry Services. Kevin O'Buckley, the previous head of Foundry Services, left for Qualcomm in late February.

TSMC's chief executive has warned that Intel Foundry is a 'formidable' rival in the chipmaking industry at the company's most recent earnings call. Despite not yet landing many high-volume external customers, Intel's semiconductor production operations remain among the largest in the industry, a fact now more keenly felt by TSMC.

"We view Intel as our formidable competitor and do not underestimate them," said C.C. Wei, chief executive of TSMC, during the company's latest earnings call this week. "But having said that, there are no shortcuts. The fundamental rules of the foundry game never change: they need the technology leadership, manufacturing excellence, customer trust, and most of all, the service [to win market share]."

Although TSMC produces a significant percentage of Intel's products, the company still makes the bulk of its products, including its data center-grade server CPUs, at its own fabs. Intel's Xeon processors command a larger server CPU market share than AMD's EPYC products (even though AMD has captured the most lucrative parts of the market thanks to high core count and performance), so Intel is not an underdog.

Furthermore, the company is now ramping up production of client Core Ultra 3-series 'Panther Lake' and data center Xeon 6+ 'Clearwater Forest' CPUs at its Fab 32 in Arizona using its 18A fabrication process (1.8nm-class) that relies on gate-all-around RibbonFET transistors and boasts a backside power delivery network called PowerVia. While TSMC's N2 production is now ramping at two fabs and also uses GAA nanosheet transistors, it does not support a BSPDN, which makes Intel's technology somewhat more progressive, at least for some designs. TSMC's A16 will bring an even better BSPDN implementation called Super Power Rail (SPR), but this will happen only in late 2026.

When it comes to revenue from chip production and packaging (and associated services), TSMC earned $33.731 billion in Q4 2025, whereas revenue of Intel Foundry was $4.5 billion, which makes Intel Foundry the world's second-largest foundry, but a long way off first place. TrendForce estimates that Samsung Foundry earned $3.399 billion in Q4 2025, SMIC's revenue was $2.489 billion, UMC's earnings totaled $1.993 billion, whereas GlobalFoundries followed with $1.83 billion in the fourth quarter of last year. While Intel Foundry primarily serves the Intel Products division and provides advanced packaging for AWS and some other companies, so does Samsung Foundry, as its parent company's LSI and Semiconductor divisions are its key customers.

It remains to be seen whether Intel's 14A process technology will gain traction with external customers and whether the company will ever have production capacity comparable to that of TSMC. Yet, at this point, there are only three companies in the world — Intel, Samsung, and TSMC — that still have ambitions and the capability to produce logic chips on leading-edge process technologies, which is another reason why TSMC calls Intel a formidable rival. At the end of the day, being one of the three semiconductor champions already deserves respect.

With production of Core Ultra 300 'Panther Lake' and Xeon 6+ 'Clearwater Forest' ramping at Intel's fab in Arizona, Intel is seemingly on the right track to recovery in the coming years. While it's not out of the woods yet, Intel's market capitalization on Thursday was its highest in over 25 years, or since the dot-com boom went bust, according to CompaniesMarketCap.com.

Intel's market capitalization increased to $305 billion on Thursday, up 3.5X from mid-April 2025, and up 2.8X from August 20, 2025, when the U.S. government announced plans to acquire a 10% stake in Intel. The company is now the world's 48th most valuable company by market capitalization. While it trails ASML, AMD, Applied Materials, Lam Research, and other semiconductor peers, it is well ahead of KLA, IBM, Siemens, and Texas Instruments.

The sharp increase follows Intel's announcement of Google's commitment to use Xeon processors for years to come, which emphasizes relevance of Intel's CPUs; the TeraFab partnership, which gives a nod to Intel's capabilities in design, produce, and package high-performance processors at scale; and a host of various AI-related narratives meant to demonstrate applicability of the company's products in the rapidly growing artificial intelligence sector.

Intel's peak market capitalization was $502.71 billion at the height of the dot-com cycle in August 2000, when the company dominated both PCs and web servers. In today's dollars, that would be around $1.0 trillion. Formally, Intel's current capitalization of $305.25 billion is higher than its $219.1 billion capitalization in late 2003 when the company took the rapidly growing laptop market by storm with its Centrino platform and re-accelerated its growth.

Nonetheless, $305 billion is higher than Intel's peaks in recent years: $257.23 billion in mid-2018 due to Intel's dominance in the growing data center sector $273.43 billion in early 2020 due to the cloud computing boom, and $262.87 billion in April 2021 due to the PC market and cloud computing growth amid the pandemic. That said, Intel is indeed going in the right direction, at least if you ask investors.

Still, Intel's valuation history reflects a transition from a dominating CPU vendor commanding PCs and servers to a mature, execution-sensitive semiconductor company. Intel's market capitalization today is driven more by its strategic narratives associated with AI, foundry, and process technology ambitions, and mid-term product roadmaps than by its earnings. The recent climb toward ~$300 billion indicates renewed investor optimism, but unlike the 2000 peak, this optimism is based on expectations of a turnaround rather than on the already achieved dominance and expectations for skyrocketing sales.

Intel's 2026 roadmap is unlike any the company has published in recent years, because its manufacturing ambitions and its product launches have to succeed simultaneously.

Panther Lake, the Core Ultra Series 3 laptop processor unveiled at CES in January, is the first consumer chip built on Intel 18A — the company's new process node combining RibbonFET GAA transistors with PowerVia backside power delivery. Clearwater Forest, the next-generation Xeon E-core server CPU formally introduced March 3 at MWC 2026, is the server counterpart to it, and both are proof points for a foundry business that Intel has publicly stated could not justify proceeding to its next node, 14A, without first securing a major external customer.

Meanwhile, Intel is currently shipping the AI data center chip Gaudi 3, which has been available through cloud partners since late 2024. The chip was supposed to be followed by Falcon Shores, but Intel cancelled it for commercial release and confirmed it would deploy the chip internally instead, redirecting its GPU roadmap toward inference workloads. That produced Crescent Island, an inference-focused data center GPU which is expected to enter customer testing in the second half of 2026, with a potential successor in ‘Jaguar Shores’, due 2027.

Meteor Lake to Nova Lake

Since 2023, Intel's consumer CPU roadmap has focused on architectural consolidation, including the abandonment of the monolithic die. Meteor Lake, which launched in December 2023 as the first Core Ultra series processor, moved Intel's consumer laptop chips onto Intel 4 with Foveros 3D packaging, splitting compute, graphics, SoC, and I/O functions across separate tiles connected via hybrid bonding. That was an inflection point, with every subsequent generation iterating on that foundation rather than departing from it.

Then came Lunar Lake, the Core Ultra 200V series that launched in September 2024, which Intel hailed as its most power-efficient x86 platform, targeting the Copilot+ PC category with a fourth-generation NPU and the debut of the Xe2 graphics architecture. Arrow Lake followed in October 2024 as the desktop counterpart under the Core Ultra 200S branding.

While both share the multi-tile approach, they diverge at the process level. Arrow Lake consumer parts don’t use Intel 20A; Intel publicly confirmed the decision to use external nodes instead — almost certainly from TSMC — for the consumer desktop line. Intel originally said that 20A would be the node that would introduce RibbonFET and PowerVia, but the company moved those technologies to 18A instead and treated 20A as a stepping stone it bypassed for production.

Panther Lake, announced at CES in January 2026 as Core Ultra Series 3, is the first client platform built on Intel 18A. Intel cited over 200 system designs in development across laptop partners, alongside a claimed 60% better multi-threaded performance versus Lunar Lake at similar power, and up to 180 total platform TOPS — 120 of which come from the Xe3 integrated GPU and 50 from the NPU 5 architecture. Those figures are Intel estimates tied to specific workloads and comparison generations; the NPU alone meets Microsoft's 40 TOPS threshold for Copilot+ PC certification, but the 180 TOPS figure reflects all three compute engines combined.

Nova Lake is next, with Intel's Q4 2025 earnings guidance initially targeting an end-of-2026 launch. This, as we understand, is likely to be delayed to 2027; process node and die configuration details remain unconfirmed, and it’s far too early to speculate given that the upcoming Arrow Lake refresh (Core Ultra 200K Plus) is still to come.

Xeon and data center CPUs

Xeon 6 formalized a split Intel had been building toward for several years: P-core variants targeted at compute-intensive and AI inference workloads, and E-core variants aimed at density, throughput-per-watt, and scale-out workloads like containerized cloud infrastructure.

Sierra Forest launched in June 2024 as the first Intel 3 server product. Its E-core design packs a high thread count into a constrained thermal envelope, making it well-suited for high-density rack deployments. Granite Rapids, the P-core counterpart, followed in September 2024, targeting scientific computing, high-performance databases, and AI inference on large models. Both families share a common platform foundation — a unified I/O die connected via EMIB packaging — which reduces platform churn for OEMs and provides a validation reuse advantage across derivative SKUs.

Meanwhile, Clearwater Forest, introduced March 3 at MWC 2026, is Intel's first 18A server CPU. Expected to be released later this year, the chip packs 288 Darkmont E-cores across 12 compute chiplets in its maximum configuration, each with 24 cores all built on 18A. Those compute tiles are stacked on three active base dies fabricated on Intel 3 using Foveros Direct 3D, while two I/O tiles on Intel 7 handle connectivity, and lateral integration across the package is handled by EMIB.

EMIB 3.5D then extends this further by combining those Foveros-stacked modules with Intel's second-generation EMIB bridges — scaled from 55-micron to 45-micron bump pitch — to link heterogeneous tiles laterally across the package, whether those are identical compute modules or disparate I/O and memory dies. The result is a package whose total silicon area far exceeds what a conventional silicon interposer could accommodate. A clean Clearwater Forest launch would therefore validate both Intel 18A and its advanced packaging simultaneously.

Finally, Diamond Rapids will arrive as an exclusively 16-channel platform after Intel cancelled the 8-channel SKUs that were originally planned for the Xeon 7 lineup. The remaining parts are expected to pack up to 192 P-cores across four compute tiles in an LGA9324 package, with 2nd-generation MRDIMM support pushing memory bandwidth to roughly 1.6 TB/s — nearly double Granite Rapids' ~844 GB/s. Intel has indicated a 2H 2026 launch window, but has said nothing more solid at this stage.

AI accelerators

Intel’s AI accelerator portfolio hasn’t followed as clean a generational progression as its CPUs have. Gaudi 3, as previously mentioned, is the current shipping product and has been available through cloud partners and direct customers since late 2024, with Intel expanding availability throughout 2025.

Intel has marketed Gaudi 3 around openness and software portability, with the argument being that customers locked into Nvidia’s CUDA ecosystem face procurement and pricing constraints that a chip running on open frameworks like PyTorch and oneAPI can avoid. While this has let the chip find some traction, Gaudi 3 hasn’t achieved a meaningful share in large-scale training clusters where Nvidia’s accelerators still dominate by a huge margin.

The most concrete successor to Gaudi 3 in the near-term is Crescent Island, which Intel announced as an inference-focused data center GPU in October 2025 at the OCP Global Summit, with customer sampling due to begin in the second half of 2026. The card is built on the Xe3P architecture, a performance-enhanced version of the Xe3 GPU used in Panther Lake, and carries 160 GB of LPDDR5X memory.

That memory choice is a deliberate departure from the HBM stacks used by Nvidia and AMD in their high-end accelerators: Intel is positioning Crescent Island as a power- and cost-optimized part for air-cooled enterprise servers, with Intel CTO Sachin Katti citing "tokens-as-a-service" providers as the primary target. No performance figures have been disclosed.

When and if it does sample later this year, it will be going up against AMD's Instinct MI450 and Nvidia's Vera Rubin architecture, both of which use HBM4 and target a broader range of workloads. Crescent Island's narrower inference focus could make it competitive on cost-per-token, but the 160GB LPDDR5X configuration offers substantially less memory bandwidth than HBM-based competitors, which remains the main bottleneck for large model inference.

Jaguar Shores, meanwhile, has been confirmed by Intel as a product, though technical details about it remain sparse. Intel products chief Michelle Johnston Holthaus stated during the company's Q1 2025 earnings call that Jaguar Shores remains on the AI roadmap despite the cancellation of its predecessor, Falcon Shores, and described it as a rack-scale design incorporating silicon photonics interconnects. Intel has also confirmed, via a slide shown at its AI Summit, that Jaguar Shores will carry the Gaudi brand and use HBM4 memory from SK hynix.

Should it launch, Jaguar Shores would be Intel’s first return to HBM-based AI acceleration since Ponte Vecchio, but specifications remain unconfirmed, and we’re very unlikely to see a release until 2027 at the earliest. That would put it up against Nvidia’s Vera Rubin successors and AMD’s Instinct MI500 series — and whether it can be competitive by then depends heavily on software maturity, an area where Intel’s track record in AI acceleration has been consistently weak.

Process nodes and packaging

Intel 4, which debuted with Meteor Lake, was Intel's first EUV-enabled manufacturing node, claiming 21.5% higher frequencies at the same power as Intel 7, or 40% lower power consumption at the same frequency, alongside a 2x transistor density improvement for high-performance libraries. Intel 4 also introduced second-generation Contact-over-Active-Gate, enhanced copper interconnects with cobalt cladding for better performance and electromigration resistance, and doubled MIM capacitance density to reduce voltage droop.

Production ran at Intel's D1 facility in Hillsboro, Oregon, with Fab 34 in Ireland coming online for Intel 4 volume production in late 2023. Notably, only Meteor Lake's compute tile used Intel 4; the graphics, SoC, and I/O tiles were sourced from TSMC and older Intel nodes, reflecting the limited scope of Intel 4 as a chiplet-specific node.

Intel 3 followed as an 18% performance-per-watt improvement over Intel 4, with broader EUV usage, improved transistor cells, and both I/O and high-density cell libraries suited for server workloads. Sierra Forest, which launched in June 2024 as the first E-core Xeon 6, was its first flagship product, followed by Granite Rapids with P-cores in September 2024. Unlike Intel 4, Intel 3 was designed as a more general-purpose node from the start, underpinning Intel's server ramp and serving as the base die for Clearwater Forest's heterogeneous packaging.

Intel 20A, meanwhile, was the planned introduction point for RibbonFET and PowerVia in production, and Intel confirmed it entered production readiness in 2024. But Intel also confirmed the decision to shift Arrow Lake consumer parts away from Intel 20A to external nodes. The only logical explanation for this is that Intel concentrated its 20A engineering on proving the key technologies it needed for 18A rather than committing a high-volume product line to an intermediate node.

Every product on Intel's 2026-2028 roadmap runs on Intel 18A, the company's first node to combine RibbonFET gate-all-around transistors with PowerVia backside power delivery. RibbonFET wraps the gate entirely around the channel on all four sides, improving electrostatic control and reducing leakage compared to the FinFET structures Intel used through its 10th Gen era. PowerVia routes power through the back of the silicon wafer, freeing front-side routing resources for signal interconnects. 18A entered high-volume manufacturing in October, but yields remain below profitable levels and, per CFO David Zinsner, will not reach desired cost thresholds until the end of 2026 at the earliest.

Intel 14A, which uses High-NA EUV — which Intel is the first to deploy — remains contingent on securing a major external foundry customer. The good news is that Intel has said it has two prospective customers in the works following early PDK access, and CEO Lip-Bu Tan reckons that firm supplier decisions will be made in the “second half of this year… extending into the first half of 2027.” A lot is riding on these prospective customers, with Intel having publicly discussed the possibility of slowing or cancelling 14A and subsequent nodes if external foundry revenue does not materialize at scale. Without it, the capital expenditure required to develop and ramp leading-edge nodes past 18A will become extremely difficult to justify.

The future of Intel

Whether Clearwater Forest's 2026 launch materializes will be a solid indication of whether 18A performs at the scale Intel has projected, while Panther Lake's rollout through laptop OEMs will test whether 18A volume manufacturing is genuinely ramping up or still constrained to early production quantities.

Meanwhile, any announcement from Intel Foundry on an external customer committing to 18A or beginning 14A engagement could substantially change the economics of Intel’s roadmap.

During the 10nm era, Intel's manufacturing problems were visible and protracted over several years. Today's timeline is more compressed, and Intel’s public milestones — Panther Lake and Clearwater Forest shipping on 18A in close succession — are specific enough to hold the company to account.

When Lip-Bu Tan came to Intel last year, he considered stopping the promotion of the company's 18A (1.8nm-class) fabrication technology among potential external customers and making it yet another internal-only node, as he did not believe the manufacturing process made a lot of sense for external clients. Less than a year later, he seems to have changed his mind about the prospects of the fabrication process to a large degree because some external customers expressed interest in 18A-P, a performance-enhanced version of 18A. Yet, Intel admits that 18A continues to suffer from process variability.

"While Lip-Bu was, I think, thinking that we probably should focus on 14A as a foundry node and make 18A really just an internal node, now that we have seen some real progress there, I think he is now starting to recognize that this is actually a good node to offer to external customers as well," said David Zinsner, chief financial officer of Intel, Morgan Stanley Technology, Media & Telecom Conference 2026. "We have been getting some kind of inbound interest in 18A-P as a foundry node. So, I think that is pretty positive."

When Lip-Bu Tan joined Intel in early 2025, both the functional and parametric yields of chips made using 18A were low and unpredictable. As a result, Tan reportedly considered shifting the company's foundry efforts to 14A (1.4nm-class) instead in a bid to focus on large clients who make strategic decisions about production nodes many years in advance and had opted to not use 18A at the time.

Intel made some progress on 18A yields in late 2025, in time to start low-volume production of the company's Core Ultra 300-series 'Panther Lake' CPU tiles at a development facility in Oregon while beginning to ramp high-volume manufacturing at its Fab 32 in Arizona. Intel admitted that 18A yields were only set to reach industry standard levels in 2027, but insisted that it was on the right trajectory. While it may indeed be on the right trajectory, Intel still suffers from process variability (though again, we do not know whether Intel means functional or parametric yields, though the latter is more likely), which is typical for early stages of HVM ramp.

"There is a lot of volatility, […] some wafers are yielding a lot less and some are yielding a lot more," Zinsner said. "[Tan] is actually focused a lot on trying to minimize the volatility wafer to wafer, and we have made good improvement there. […] I think we would expect a pretty steady yield progression as we go through this year, probably a bit ahead of schedule."

If wafer-to-wafer parametric variation is high but improving, this is not something unusual, especially keeping in mind that Intel's 18A introduces gate-all-around RibbonFET transistors and backside power delivery, two previously unknown technologies. However, depending on how significant process variability is, parametric yield volatility creates capacity unpredictability, which makes supply planning hard. As a result, it is not surprising that Intel's CEO thought about ceasing the promotion of 18A as a foundry node, as the company did not have visibility on when it could offer it to external customers without creating supply constraints for itself.

Based on the recent rumors, a number of big fabless chip designers have evaluated Intel's 18A and 18A-P process technologies, though none have made any publicly-announced commitments to use the node. Nevertheless, it is possible that at least some of America's chip developers may outsource production of some of their non-core products to Intel in the coming years to increase production of their silicon in the U.S. to reduce their geopolitical risks associated with Taiwan and potential tariffs on chips made outside of America.

In an unexpected turn of events, Kevin O'Buckley, the head of Intel Foundry, decided to jump ship for Qualcomm after just two years at the company. From now on, Intel Foundry will be headed by Naga Chandrasekaran, who was previously in charge of front-end process technology development and manufacturing.

"We thank Kevin O'Buckley for his contributions to Foundry Services and wish him the very best as he pursues an opportunity outside the company," an Intel spokesperson told Tom's Hardware. "Intel Foundry remains one of Intel's highest strategic priorities, and under Naga Chandrasekaran's leadership the organization is focused on disciplined execution and delivering for customers."

As Chief Technology and Operations Officer as well as the head of Intel Foundry, Chandrasekaran now oversees both development of advanced process technologies and day-to-day execution of Intel's global manufacturing network, a role that Intel previously lacked as both O'Buckley and Stuart Pann before him were responsible for day-to-day execution and expansion efforts, but not development of advanced fabrication technologies.

By contrast, Chandrasekaran is in charge of creating and rolling out next-generation silicon logic nodes, advanced packaging solutions, and test technologies, while also supervising front-end wafer fabrication and back-end assembly and packaging operations worldwide. In addition, Chandrasekaran leads Intel Foundry's customer engagement and ecosystem initiatives, as well as strategic planning, corporate quality and reliability programs, and the company’s supply chain operations. In short, he runs the technology roadmap and the factories.

As executive vice president and chief technology and operations officer of Intel Foundry, Naga Chandrasekaran has been in charge of Intel Foundry and Foundry Services since September, so making him the GM of the whole Intel Foundry organization looks like a logical move for Intel. Naga Chandrasekaran was previously the head of technology and operations at Intel Foundry, overseeing front-end process technology development and manufacturing. In this capacity, he was already in charge of both the Technology Development (TD) group and the Foundry Manufacturing and Supply Chain (FMSC) organization, which he has been overseeing since mid-2024.

Navid Shahriari will continue to be responsible for packaging development and operations at Intel Foundry.

As for O’Buckley, he will be executive vice president in charge of Qualcomm's Global Operations and Supply Chain and will lead the company's worldwide chip production activities, overseeing manufacturing engineering, relationships with contract manufacturers, and component vendors. O'Buckley will report directly to Akash Palkhiwala, Qualcomm’s executive vice president, CFO and COO. After spending seven years at IBM Microelectronics and GlobalFoundries and then a little less than two years at Intel Foundry, O'Buckley will now supervise how Qualcomm turns its designs into finished silicon.

Whether or not Intel Foundry will produce any of Qualcomm's future designs is something that remains to be seen.

Intel expects its Core Ultra series 4 processors, codenamed Nova Lake, to change its fortunes on the desktop and laptop markets and finally offer performance that is higher compared to direct competitors from AMD. However, another important factor to consider will be the costs of these CPUs, and if the alleged Nova Lake compute chiplet die sizes leaked by @9550pro are accurate, these processors will be anything but cheap to make.

When implemented on TSMC's N2 manufacturing technology, Nova Lake's compute tile with eight high-performance Coyote Cove P-cores and 32 energy-efficient Arctic Wolf E-cores measures over 110 mm^2, whereas the same tile equipped with 144 MB of big last-level cache (bLLC) measures over 150 mm^2, if the numbers from @9550pro are correct. To put the number into context, it is believed that the size of Arrow Lake's compute tile —implemented on TSMC's N3B technology and housing eight Lion Cove P-cores and 16 Skymont E-cores — is believed to be around 117 mm^2.

TSMC's N2 is projected to be a more expensive process technology to use than N3B, as, despite the fact that it is expected to feature roughly the same number of EUV layers (20 ~ 23), it is also believed to use EUV multipatterning for at least some critical layers, which adds costs. This, and other factors, contribute to manufacturing costs, so it is safe to say that Nova Lake's compute tile without bLLC will be a bit more expensive to make than Arrow Lake's compute tile, assuming an accurate die size for the former. The compute tile with bLLC will be significantly more expensive, though, considering that these tiles will be used for expensive CPUs aimed at gamers and enthusiasts, this will hardly be a problem for Intel.

Just like most of Intel's latest processors in recent years, Nova Lake will use a multi-tile design that will include a compute tile (or two), a system-on-chip (SoC) tile, a GPU tile, an I/O tile, and a base tile. The main chiplet — the compute tile — will be made using both Intel's own 18A fabrication technology at the company's Fab 32 in Arizona as well as TSMC's N2 manufacturing process at the foundry's Fab 22 in Taiwan.

Intel has never publicly revealed which versions of Nova Lake will be used for desktops and which will be used for laptops, and whether there will be any difference at all. However, given that Intel expects to make the majority of Nova Lake silicon in-house and keeping in mind that laptop CPUs outsell desktop CPUs 7:3 these days, it is reasonable to expect that the bulk of laptop CPUs will be made at Intel's own fab in Arizona. To that end, the company's balance sheet will barely suffer from the high costs of its Nova Lake compute tiles with bLLC at TSMC.

The cost of a chip is a function of process technology, die size, functional yield, and parametric yield. While we may well speculate that TSMC's N2 is more expensive than N3B, without factors like parametric yields, our assumptions about the costs of the actual compute tile will be highly speculative, to put it mildly.

Following Intel's keynote at CES 2026, where it formally launched consumer Panther Lake products, our resident CPU reporter Jake Roach attended a press Q&A at CES in Las Vegas, featuring some of the senior staff behind Intel's Panther Lake architecture. The following article is a transcript of that Q&A session. We've edited some elements for flow and clarity, and have made notes where we couldn't quite make out what was being said. As speakers did not introduce themselves at the beginning of our transcript, we have denoted them as Journalists, denoted in the sequence that they spoke in.

Some highlights include Intel being particularly proud of making the lineup significantly easier to understand, combining the benefits of Arrow Lake and Lunar Lake, while also making fewer SKU denotations, making the lineup easier to parse as a whole. Additionally, while Intel did not announce any EVO processors at CES 2026, the company is still keeping the brand alive, with 'stricter' qualifications in place for the future.

Ahead of reading this press Q&A session, be sure to familiarize yourself with all the elements of Intel's new Panther Lake architecture by checking out some of our coverage, or watch the keynote yourself below.

So, now that you've learnt a little bit more about what Panther Lake offers, here's our full, slightly edited press Q&A session. This session was around 25 minutes long, and while recording in a noisy, ambient environment, some things can get lost in the audio mix, and have been denoted as such in the copy.

Shalini Singh: Hi. My name is Shalini, Technical Marketing, Intel CCG (Client Computing Group, with me, Damien, who leads technical marketing as well. [laughs]

Damien Triloet: Yep, Technical Marketing, a lot of time spent on graphics and [inaudible]

Mitch Lum: I'm Mitch Lum, I'm the Product Manager for both Core Ultra Series 3 and Core Series 4.

Client Product Team Lead: I'm [inaudible], I lead the client product team.

Journalist 1: So, my first question is, you guys are using a lot of panthers in the presentation. It was nice. And we are used to [having], like, the codename. And when we have the product, the codename disappears. You guys don't use the code name anymore just presenting the unique architecture [...] But you guys are using a lot of panthers in design. [...] Are you guys using [Panthers] to represent this generational product for clients? The guys actually buying the product?

Client Product Team Lead: I was just gonna say, you did see the panther walk away. We will focus on [the naming convention of] Core Ultra Series 3.

Shalini Singh: Like previously, [you] will see many places where we'll continue to use the codename. Then there's just no going behind it. But the brand police will come to us and tell us "you always have to use the [inaudible] Core Ultra 3 [laughs]."

Mitch Lum: What's your advice?

Journalist 1: I know it's easier to understand names when it's just a numeral sequence, you know? But you can see how it's easy to identify this. Oh, this is a new thing. This is the Panther thing, and whatever the next thing is, the new codename [...] and you can [...] see the difference in generations this way as well. It's a good visual representation of the product.

Damien Triolet: It's a good visual representation of the product.

Journalist 1: Yeah, especially when [it's] a nice thing, a panther is a cool thing. So if you're using cool things as code names, maybe it works.

Shalini Singh: And also, for you guys, after you've seen so many panthers, it's difficult to unsee it.

Journalist 1: I mean, I mean, 300 series, 400 series. I can see where this is going, but it's a number. It's not as cool, I guess.

Client Product Team Lead: Oh yeah, we'll have it in the [press pack] that will look different, so that there'll be all the retail differentiators, and in any tech related areas, you'll see it's called call out as Panther Lake, but in end user facing [materials and assets] is going to be Core Ultra Series 3, Series 4. So, that's the least offensive way of describing the products, and I could keep going. But they'll have codenames.

Journalist 2: Do you guys see any sort of ripple effects from the ongoing price hikes, with RAM and storage as an example, like [...] Copilot+ PCs, I believe, have a minimum spec of 32 gigabytes [this is not correct, and was quickly clarified as a 16GB requirement]. So if that's true, does that affect the sales of AI PCs or Copilot PCs, going into the new year?

Client Product Team Lead: So in general, a lot of the OEMs, and you can talk to them in detail, they plan for nine months to 12 months in terms of allotment of their [products] so in the beginning through towards the end of the year, I think a lot of them are going to be reasonably okay in terms of memory. But, in general, we have to wait and see. It's like, if we can predict the memory prices, we would all also invest in the stock market, that kind of thing. So it is going to be a challenge, which we are carefully monitoring and trying to work as much as we can closely [presumably meaning with OEMs].

Journalist 3: Are we really going to be seeing developers using [inaudible, but the question pertains to AI TOPS and NPU performance]

Damien Triolet: One interesting detail about NPU 5 is that our first [inaudible, potentially Blackwell?] compatible, and PYP. So it will help developers move the roles they've done on NPU 4, and then keep investing into NPU so we see increasing traction.

Client Product Team Lead: A lot of the time, we want to make sure they're using the right engine for the right workload. So from an Intel perspective, it's not just about the NPU. AI means it's the GPU, NPU, and CPU. So as long as they're using the right engine, we're good. And from an NPU 5 perspective, our biggest thing was we shrunk it down in size so that we can fit a lot more inside Panther Lake. So from Lunar Lake to Panther Lake, the peak TOPS, it's fairly similar.

Mitch Lum: It's 40% more die area, if you think about Lunar Lake and the kinds of systems that it went into. Now we're going into many more kinds of laptops, and we wanted to make sure that we had that scalability.

Shalini Singh: But, it's probably the only x86 product to have fully featured XPU engines to run a performance GPU. You will not see that from any of our competitors.

Damien Triolet: And you will see that in the mlperf data that we have in the project, you should have a look later. When you look at the way our different engine, GPU and NPU, behaves in approach like LLM are very consistent. Both engines have, like, full access, memory bandwidth, a ton of compute for AI. That's not something you will see on the company's source product. They will either have the GPU enable something, or the NPU enable something. We fully enable both of them. And this gives a niche set [of tools] to developers [offering] the flexibility to target the right engine, for the right competitors.

Shalini Singh: In most cases, when they don't have either the fully labeled GPU or the NPU. They even have hybrid solutions, CPU plus NPU. You probably know that, right. But our GPU and NPU solutions in most cases [inaudible].

Journalist 4: I also expect this will require all four of you to answer. Why did you add X to the names?

Client Product Team Lead: In terms of X's, there was [...] strong retail feedback. There are 12 [Xe3 cores]. They needed an easy way for customers walking to be able to identify that. So those [products with X in the name] will have the 12 Xe [cores], the bigger graphics, Arc graphics. So that is an easy way to identify that.

Shalini Singh: It's also the highest-end config. So most of the data that you see in the press deck will be based on that config.

Tom's Hardware: I have two questions focused on the Ultra 5 range. First, we know the core split for the eight-core configurations, and the 16-core configurations. I'm just wondering what the core split is for the 12-core configurations. And then there is a core Ultra 5 that has 10 Xe3 cores in it, but it didn't get that Core Ultra X5 branding, and I'm just wondering why that's the case.

Mitch Lum: Yeah, so, on that one, the 10 xe3 [cores], it [has] our B370. There's B390, it's 12 Xe, 370 is 10 Xe. We wanted to make sure it was really clear with the X designation that we were really referring to our top configuration, which is the B390. So that's the first piece. And then I think your second question was that [Core] Ultra 5, we've got a 12-core configuration. That's 4P, 4E and 4LP-E.

Journalist 4: I had a question on the Xe cores and the GPU. Now, are you finding most of your improvements from just increasing the number of cores? Or, were the cores redesigned? And what sort of improvements are you seeing internally today?

Damien Triolet: So the bigger part of the improvement is coming from a larger configuration. But as you've seen, some of the general numbers that we share is over 70% so there's obviously a little bit more coming to that. There's a clock increase, that's part of it, and then the IP improvements, as we've detailed, at ITT if you were there.

Mitch Lum: And, also the bigger cache, so the GPU has a bigger cache.

Client Product Team Lead: 50% more cores, double the amount of cache.

Journalist 5: Yes, you guys told us that on stage, that Panther Lake [has] 15% better performance per watt compared to last year's chips. How is that translated in real use cases, like how many more hours [of battery life] people can have on their laptops?

Shalini Singh: We expect to deliver Lunar Lake level efficiency. The exact battery life translation will obviously depend on the overall design. It depends on the display, the battery capacity, [and] other components that they will have on the PC. But in most cases, at the most when we when we measure power at the SOC level, Panther Lake is more efficient than Lunar Lake.

So we are seeing power savings compared to Lunar Lake itself. If you have one, or if you tested it, you probably know it's really good on battery life. So Panther Lake is very similar, and so it's basically a combination; Lunar Lake efficiency and Arrow Lake performance, right?

So, you'll see about a 60% increase in multithreaded performance, battery life, and all the SOC, power savings are going to translate to a similar to better battery life [when] compared to what you had in Lunar Lake, because it also has a [higher] number of cores. So there's going to be a little bit of a balance there.

Mitch Lum: There was the 15% number from the very beginning of the keynote, when we were talking about process technology. [...] I think that was specifically comparing at a transistor level, 18A transistor performance per hour, versus [the previous generation].

Client Product Team Lead: The Lunar [to] Arrow numbers would be much higher. It's in the press deck [inaudible].

Shalini Singh: Yeah, you'll see that in the press deck. Basically, we're delivering similar performance [to] both Lunar and Arrow at 40% lower power. So [in] Arrow Lake, obviously, there is a big efficiency [gain] to be had, versus Arrow Lake, but even versus Lunar Lake, like you said, was quite good as it is. To be able to drive the efficiency further was amazing.

Journalist 5: So I was really impressed with the integrated graphics FPS [...] so I guess my question is; Do you see [integrated graphics] being kind of the future of gaming laptops, not needing that GPU anymore because you have [...] more efficiency, less heat... How do you guys see the industry moving?

Client Product Team Lead: At the highest level, I mean, this is more like the [entry-level], right? Similar to [the RTX 4050]. Clearly, there is a lot higher [power] discrete graphics, mobile display graphics available.

So, we don't see that going away anytime soon. That said, this is the first step in terms of getting to that discrete graphics level. And over time, there is going to be also creation where a lot of AI systolics in that integrated graphics [segment] is going to help. So we see this as a new breed of things that we want to build and see where AI is going to enable [Intel] to take it to another level... But in the near future? It's not going to go away. You will still see discrete graphics.

Shalini Singh: No, just to add, basically, you know, we do expect this level of graphics performance to be able to replace entry-level discrete cards, right? In some cases, even something a little bit more than that, like a 4050, like 4060, whatever. But yes, like he said, the high-end, we don't expect that to go anywhere. So those will continue to be there, but [Intel will] absolutely challenge the entry [level] domain.

Mitch Lum: And we will have Core Ultra Series 3 laptops that have big discrete graphics in them [inaudible].

Damien Triolet: As Shani mentioned, at the entry level for discrete, it is a good point for integration, for the simple reason that memory capacity for entry-level discrete is relatively limited, and more modern workloads require way more memory. So integration is a thing about how to get more accessible at that.

Client Product Team Lead: Speaking of the previous question on memory shortages... [laughs]

Journalist 6: So is Arc built into the entire [Core Ultra] Series 3 components?

Mitch Lum: There are some SKUs that are Intel graphics, and then there are some SKUs that are Arc.

Journalist 6: What about Iris, is that Intel Graphics?

Mitch Lum: Iris is a brand that we EOL'd.

Journalist 6: Is that dead?

Mitch Lum: Yeah, we end-of-life'd that brand... probably three generations ago.

Journalist 6: I'm really up to speed on that, I was asking for a friend [laughs]

Client Product Team Lead: Just to the previous point, that 'X' is there for that reason. Anything with an 'X', like X9 [or] X7, is going to have Arc integrated graphics.

Mitch Lum: So if it doesn't, there's no Arc.

Client Product Team Lead: It'll be Intel Graphics, the 4 Xe version of the...[inaudible]

Mitch Lum: There's one nuance of that at the Core Ultra 5 level with the 10 Xe/ B370, the one place you might see that is in mobile workstations.

Damien Triolet: The smaller, non-Arc Intel graphics are using exactly the same technology, but [with a] smaller configuration, because of the smaller...

Journalist 6: The same as Arc, or Iris?

Damien Triolet: The same as Arc. Between Arc and Intel Graphics on Core Ultra Series 3 is the same technology. A smaller configuration on Intel graphics, and because of that, you're not going to get the type of experience that we want to be part of the Intel Arc [product line]. We want a certain level of performance to define.

Mitch Lum: So we bifurcated. There's a 4 Xe native configuration, and 12 Xe... Because not everybody needs that 'Arc' level of performance. If you think about your general purpose IT machine not doing a lot of 3D rendering.

So, customers have said, "Hey, can we get something that has more modest graphics", or systems that are putting in discrete graphics [...] So, on Intel Graphics, you're just running Office and that kind of stuff. I mean, you can actually run games at like, okay, [framerates], but it's just not really [something to] write home to your friends about.

Client Product Team Lead: So all the IPs in terms of the system. IPs, in terms of systolic AI [...] are still very powerful AI engines. So, it will be used for a lot of AI use-cases, and all the other basic graphics.

Tom's Hardware: I just want to clarify, it's Xe3 across the board, right?

Mitch Lum: Yes, absolutely.

Journalist 6: One of the numbers that jumped out was the battery savings [while] streaming, or energy efficiency. Can you shed a little more light on those processes? And, how much was there [inaudible].

Shalini Singh: Basically, the way we measured it... the process was simple. We just did a pure rundown, right? Just ran the workload until the time the laptop died.

Journalist 6: [What about] the engineering process behind getting that efficiency?

Damien Triolet: Part of the role [...] on the engineering side was to make the communication between the different engines, the media engine, the CPU, the display engine, more efficient. And, for example, when we do a lot of the video processing, we don't need to activate the GPU part at all. The media engine can communicate directly with the display engine. And these are the types of things that we use to reduce...

Mitch Lum: Architectural [changes] impacts graphics. Media and display would be a consolidated tile. Now, our graphics tile is for rendering and the [inaudible], whereas we have display and media on the actual compute tile, so you can power the IP that you don't even need at all, much more power efficiently.

Client Product Team Lead: and also, [regarding] the overall architecture, your P-Cores... Now we have [them] in the performance cluster, which has access to L3 cache, so when you need to balance power, you don't always default to the P-cores. You can run it on the E-cores. And we also bring the Lunar Lake efficiency cluster with it. So a lot of those are just building on all the technologies which we already have. And we are also doubling down on some platform technology. So Intel Intelligent Display [and] Intel Wi-Fi cut [a] significant amount of power when it runs. So all of those are going to be exclusive to Intel platforms, and they help displays a big part of [inaudible].

Shalini Singh: The low-power island basically adds to what he's saying. We started this journey back with Meteor Lake. [...] You know, the low-power island had 2 E-Cores, then with Lunar, we had doubled the quantity, and we had four [E-cores in Lunar Lake]. This time, we have eight [total E-cores, including LP-E]. So it's continuing to be like a significant portion, where workloads can now be sustained on that low-power island.

Journalist 7: Usually, we have a process watch, will we hear a little about EVO?

Client Product Team Lead: Yes. Short answer. In this generation, [...] our focus is going to be more quality than quantity. So there will be less EVO devices, but we will have stricter specs to showcase the best.

Journalist 7: You said, stricter, stricter, KPIs, like, what do they exactly look like?

Client Product Team Lead: Like in terms of resolution, in terms of battery life [...] instead of having two different cut-off points [For EVO SKUs], there will be [fewer] exceptions.

Journalist 8: When you guys were doing the comparisons between Lunar and Panther Lake, you said 77% faster gaming and 60% for other stuff, but we looked into the small print, it says that you're comparing the V SKUs to other H SKUs. One's more GPU efficient, one's more AI efficient, so [inaudible]

Damien Triolet: So if you go to the press deck, you're gonna see the comparison between all of them, right? In the keynote, we simplified. We take a few points. In general, you will see that both AI and gaming are faster [in Panther Lake SKUs] than the previous generation. The 70% plus [performance uplift in Panther Lake] for gaming, for example, applies to both Arrow Lake H and Lunar Lake, so you will see the same type of improvements. On AI in general, the improvement versus Alder Lake H is higher than versus Lunar Lake, especially on the NPU side. In Lunar, we're already at a relatively large NPU.

Mitch Lum: And maybe implicit to your question is the PL setting. So when we compare [the] Core Ultra Series Three versus the 288V. It's at 25 watts.

Shalini Singh: It's basically peak performance, right? So Lunar Lake's peak performance was about 25 to 30 watts.

Mitch Lum: So we compared it, apples to apples. So 25 watts versus Lunar Lake, 45 watts versus Arrow Lake.

Client Product Team Lead: And this is where the core name versus the [inaudible] company, all of Lunar Lake had the V-series. Arrow Lake had H. So when we compare talking Lunar Lake, it's always going to be V. right, and then that's why Damien said we have both numbers in the press deck, you'll see some Arrow Lake H.

Journalist 8: So all of these [CPUs] that are announced today, H?

Client Product Team Lead: We have H and non-H. So in Panther Lake, there are products that have an H, and there [are] products without an H suffix.

Journalist 8: Okay, what [are] the ones without the suffix?

Shalini Singh: You just have a number. You do not have [an] H. But think about it this way, the product transition for Panther Lake is basically [that] there were two products we announced last year, Lunar Lake and Arrow Lake, right? Arrow Lake was generally for higher performance, more cores, at a little bit of a higher PL1 (sustained power limit). Lunar Lake was more [about] power efficiency, battery life, good performance, and a lower power level. Both of those are basically transitioning to Panther Lake this year. So whether Yes, so whether you go with the suffix or...

Journalist 8: Why do you guys make this so confusing? So, now this series will have H, and...

Shalini Singh: Non-H. We're not doing any more V-series.

Journalist 8: [...] There's no more HX?

Client Product Team Lead: HX is in a higher category. [...] So the way to think about it is, U,V,Y,H, all of this creates an overlapping power level. With Panther Lake, we are going at a similar TDP. So all of Panther Lake starts at 15, and goes to 45 or 65 [Watts] depending on the SKUs. So what we did is we tried to simplify it, and in that range, you just have H or no [H suffix], that's it. So you don't have any more V's, no Y's, no U's. [...]

Mitch Lum: Just to tie up on that, so the parts with no suffix are basically eight-core based. You know how we show the die package combination? Those are eight-core based, the 16-core base all starts with H, so that's how you know you get more [inaudible].

Tom's Hardware: So, on gaming performance [of Panther Lake], you were comparing to Arrow Lake H, which I believe is not at ISO power...

Shalini Singh: It is.

Tom's Hardware: Is that ISO at 45?

Shalini Singh: Yes, 45. We're actually comparing to Arrow [Lake], we're comparing to Lunar [Lake], we're also comparing to Nvidia.

Tom's Hardware: Do you have numbers at peak power, for 115 [Watts] on Arrow Lake H, compared to 65 [Watts] on...

Shalini Singh: No, we're doing it at sustained PL1. So, 45 to 45, 45 to 25, and then for the competition, whatever their out-of-the-box sustained power is.

Tom's Hardware: Yeah, I was just curious for efficiency.

Client Product Team Lead: Arrow Lake H peak power, as in the high-end PL1 is 55...

Tom's Hardware: Max turbo?

Client Product Team Lead: 110 et cetera, will be the system power, if you're putting in discrete graphics. The CPU itself is 55 [this is incorrect, as many Panther Lake SKUs have PL1 of 65W].

[Session ends]

Stay tuned to Tom's Hardware Premium, where we'll be posting much more from CES 2026 over the coming days.

President Donald Trump and Commerce Secretary Howard Lutnick went on social media to praise Intel and its CEO, Lip-Bu Tan, after the successful launch of the Panther Lake processors. Trump called Tan “the very successful Intel CEO” on his social media platform, saying that the 10% stake the White House took in Intel is already showing a good return for the government. Both the president and Lutnick also mentioned how the company is helping the U.S. regain its lead in cutting-edge chip manufacturing.

“The United States Government is proud to be a Shareholder of Intel, and has already made, through its U.S.A. ownership position, Tens of Billions of Dollars for the American People — IN JUST FOUR MONTHS,” the U.S. president said on Truth Social. “We made a GREAT Deal, and so did Intel. Our Country is determined to bring leading edge Chip Manufacturing back to America, and that is exactly what is happening!!!” The Commerce Secretary also posted on X, “Just four months after the United States invested in Intel, that investment is already delivering tens of billions in value for the American people. That momentum continues with Intel’s new 1.8-nanometer processor, a major step in bringing semiconductor manufacturing back home.”

Intel has been struggling in the past year, with the company announcing a disastrous quarterly report in July 2024, resulting in a $39 billion drop in market cap overnight. It has resulted in thousands of layoffs, with Pat Gelsinger unexpectedly retiring in December 2024. He was replaced by Lip-Bu Tan in March 2025, who had some controversies relating to his past leadership of Cadence, leading to Trump calling on him to resign from his position.

However, Tan was able to turn things around when he visited the White House and talked to the president, which led to the $8.9-billion investment in the company in August. This was followed by a massive deal in September, in which Nvidia announced it was purchasing $5 billion worth of Intel stock while working alongside it to develop x86 RTX SOCs for PCs. This announcement led to a 25% increase in stock price overnight, with Intel keeping up its momentum with the launch of Intel Core Ultra Series 3 chips at CES 2026, which used its cutting-edge 18A node.

Intel’s latest chips seem to be promising, with initial reports showing increased gaming performance from its integrated GPU that can match discrete RTX 4050 graphics cards. Pre-release testing also showed that it can hit 80 fps in Cyberpunk and 100 fps in F1, but the software still needs a bit more tweaking. Aside from its chip consumer business, the company also needs to break even in its foundry business, which isn’t expected to happen until 2027 with the Intel 14A node. Nevertheless, the success of the Intel 18A node is another step in the right direction for the company. In remarks at CES 2026, CEO Lip-Bu Tan said Intel is "going big time into 14A."

Intel was the first company to build an explicitly disaggregated chiplet design, comprising 47 chiplets, with its Ponte Vecchio compute GPU for AI and HPC applications. This product still holds the record for the most populous multi-tile design, but Intel Foundry envisions something considerably more extreme: a multi-chiplet package that integrates at least 16 compute elements across eight base dies, 24 HBM5 memory stacks, and scales to 12X the size of the largest AI chips on the market ( 12x reticle size, beating TSMC's 9.5x reticle size). Of course, we can only wonder about the power consumption and cooling requirements for such beastly processors.

Intel's conceptual 2.5D/3D multi-chiplet package demonstrates 16 large compute elements (AI engines or CPUs) produced on Intel's 14A or even more sophisticated 14A-E process technology (1.4nm-class, enhanced features, second-gen RibbonFET 2 gate-all-around transistors, improved PowerVia Direct backside power delivery).

These sit on top of eight (presumably reticle-sized) compute base dies made on 18A-PT (1.8nm-class, performance enhanced with through-silicon vias (TSVs), and backside power delivery) that can either do some additional compute work, or pack plenty of SRAM cache for the 'main' compute dies, as Intel shows in its example.

*Expand the tweet above to watch the fly-through video.

The base dies are connected to the compute tiles using Foveros Direct 3D, leveraging ultra-high-density sub-10 µm copper-to-copper hybrid bonding to deliver maximum bandwidth and power to the top dies. Intel's Foveros Direct 3D is currently the pinnacle of Intel Foundry's packaging innovations, underscoring the very sophisticated design.

The base dies leverage EMIB-T (an enhanced version of Embedded Multi-Die Interconnect Bridge with TSVs), with UCIe-A on top, for lateral (2.5D) interconnections among themselves and with I/O dies made on 18A-P (1.8nm-class, performance-enhanced), and custom base dies, for up to 24 HBM5 memory stacks.

It is noteworthy that Intel proposes to use EMIB-T with the UCIe-A on top to connect customized HBM5 modules rather than use JEDEC-standard HBM5 stacks with an industry-standard interface, possibly to get more performance and capacity. Given the concept nature of the demonstration, the use of custom HBM5 stacks is not a design requirement; it is simply a way to show that Intel integrates such devices as well.

The whole package can also carry PCIe 7.0, optical engines, noncoherent fabrics, 224G SerDes, proprietary accelerators for things like security, and even LPDDR5X memory for added DRAM capacity.

Note that the video Intel Foundry posted on X shows two conceptual designs: a 'mid-scale' one featuring four compute tiles and 12 HBM, and an 'extreme' one with 16 tiles and 24 HBM5 stacks, which our story focuses on. Even the mid-scale design is fairly advanced by today's standards, but Intel can produce it today.

As for the extreme concept, this may emerge toward the end of the decade, when Intel has perfected not only Foveros Direct 3D packaging technology but also its 18A and 14A production nodes. Being able to produce such extreme packages towards the end of the decade will put Intel on par with TSMC, which plans something similar and even expects at least some customers to use its wafer-size integration offerings in circa 2027 – 2028.

Making the extreme design a reality in just a few years is a significant challenge for Intel, as it must ensure the components do not warp when attached to motherboards and do not deform even with minimal tolerances due to overheating after prolonged use. Beyond that, Intel (and the whole industry) will need to learn how to feed and cool monstrous processor designs the size of a smartphone (up to 10,296 mm^2) that will have an even larger package, but that's a different story.

Intel is trying to catch up with TSMC in terms of process technologies and advanced global production capacity, but when it comes to the U.S., the chip giant remains unrivalled. Intel's Fab 52 is more advanced than TSMC's current Fab 21 phase 1 and upcoming Fab 21 phase 2 facilities and its production capacity is comparable to both modules combined, according to a report by CNBC.

Intel's Fab 52 is designed to produce chips on Intel's 18A (1.8nm-class) and more advanced process technologies that use gate-all-around (GAA) RibbonFET transistors as well as PowerVia backside power delivery network. The facility's production capacity is 10,000 wafer starts per week, corresponding to approximately 40,000 wafer starts per month* (WSPM) at full ramp-up, which is considered a very large fab indeed by today's standards.

At present, Fab 52 is equipped with four ASML Twinscan NXE Low-NA EUV lithography systems (as observed by @IntelProMUltra), including at least one NXE:3800E — ASML's most advanced Low-NA EUV machine that borrows wafer handler, faster wafer stages, and light source from next-generation High-NA EUV tools and therefore can process up to 220 wafers per hour at a 30 mJ/cm^2 dose. The plant also has three NXE:3600D systems, which can process 160 wafers per hour at a 30 mJ/cm^2 dose.

In total, there will be at least 15 EUV scanners at Intel's Silicon Desert campus in Ocotillo, Arizona. However, we can only wonder how many of them will be High-NA EUV lithography tools and how many will be installed in the upcoming Fab 62. In any case, the words 'at least' imply that Intel has enough space to install more than 15 EUV lithography machines at its Arizona facilities.

When compared to TSMC's Fab 21 phase 1 (which produces chips on the company's N4 and N5 process technologies), Intel's Fab 52 can make chips on considerably more advanced nodes (down to 1.8nm-class and beyond), and it can process two times more wafers per month. In fact, given that TSMC tends to build fab modules with production capacity of around 20,000 WSPM, even when TSMC completes its N3-capable Fab 21 phase 2, Intel's Fab 52 will remain on par or even a bit ahead of TSMC's facilities in Arizona when all three are fully ramped.

In fact, given that Intel's 18A production node is considerably more sophisticated than TSMC's N4 or N4P, the straightforward comparison of production capacities is not completely accurate, as Intel's fab has to do more work to create the node (even using the more advanced Twinscan NXE:3800B).

There is a caveat regarding Intel's Fab 52 ramp schedule, however. At present, it is ramping up production of Intel's Panther Lake processors using 18A technology, which is still in an early stage of its yield curve. Intel expects 18A yields to reach world-class levels in early 2027. Before then, Intel will not increase CPU production on this node beyond a certain level, so the fab will not be fully utilized initially, and some portion of its production capacity will remain unused. By contrast, TSMC ramps chip production using proven process technologies in the U.S., enabling rapid ramp-up and a quick increase in fab utilization to near 100%.

*Note that there are more than four weeks in an average month, so the maximum capacity of Intel's Fab 52 when fully ramped can be higher than 40,000 WSPM, depending on factors like planned maintenance and unplanned downtime.

Intel faces serious threat in the laptop market, not just from its nemesis AMD but also Qualcomm and Apple, thanks to the arrival of high-performance, highly efficient ARM cores that have forced the chipmaker to up every part of its game to compete. With 50% more oomph and 30% less power draw, the Core Ultra 3-series 'Panther Lake' processor is a robust response to those rivals — and at a financial event on Tuesday, Intel announced enormous progress toward delivering the goods.

When Intel announced mass production of Panther Lake about a month ago, the company openly admitted that all wafers for the initial CPUs would be made at pilot production lines in Oregon; the new Arizona fabs built on CHIPS ACT money would catch up later. Later means Q1, apparently, and the Arizona fabs should ramp up, the company said. This means costs might stay low, and crucially, yields will grow quickly (though likely remain low in 2026), all of which spells good news for anyone considering a new laptop.

“We now have a predictable path for yield improvement,” said John Pitzer, corporate vice president of corporate planning and investor relations at Intel.

Panther Lake is one of the first products to be fabricated on Intel's leading-edge 18A node, likely the industry's first high-volume process to incorporate two major innovations meant to enable future scaling and power efficiency gains: gate-all-around (GAA) transistors, which Intel calls RibbonFETs, and a backside power delivery network, which Intel calls PowerVia.

Efficient, cutting edge, and on time? For Intel, Panther Lake may be a rare animal indeed.

Low yields, high costs, but a good improvement pace

"Initially on any new process, we take wafers from Oregon," said John Pitzer, corporate vice president of corporate planning and investor relations at Intel, at RBC Capital Markets Global Technology, Internet, Media & Telecommunications Conference 2025. "Oregon is where we do all of our technology development and then move into quasi high-volume manufacturing."

"Those wafers tend to be pretty expensive. Most, if not all, of the Panther Lake wafers this year are coming from Oregon. As we transition into Q1, you will start to see wafers coming in from Arizona [which] has a much better and different cost structure, and that ramps throughout the year," Pitzer said.

Most likely, Intel has not yet initiated mass production of Panther Lake's compute tiles using its 18A process technology at Fab 52 in Arizona due to low yields. The company wants to achieve the highest yield possible on its pilot lines at the D1X fab in Ohio, where developers of the production nodes and process engineers are, and only then transfer the recipe to its production facility in Arizona. As a result, Intel is poised to use low-yield, high-cost wafers for the initial batches of Panther Lake, which is not good news for its costs – but a normal situation in the chip-making world.

There’s good news here about Intel's 18A yields: They are finally increasing at a predictable pace of 7% per month, which is common for the middle phase of every process ramp. Intel does not divulge whether these are functional or parametric yields, which somewhat devalues the claim, but it still reflects Intel's vision about the progress of its 18A node.

"I think one of the things that has changed dramatically over the last seven or eight months, is, we now have a predictable path for yield improvement," Pitzer said. "We have [said] in the past that the industry average yield improvement on a new ramp is about 7% per month and we are now on that curve for Panther Lake, which is giving us some confidence as we launch the product this quarter."

18A is on the right curve, but Panther Lake will be a rare animal

When a new leading-edge production technology like 18A enters volume production, yields typically rise by a predictable improvement curve every month. A 7% yield improvement per month is normal for the middle phase of the ramp, though it is generally lower in the early and late phases as yield-curves tend to be S-shaped.

Intel says that 18A is now following this exact 7% trend for Panther Lake, which is important because past Intel nodes failed to do so and demonstrated chaotic yield improvements or even drops. This is famously why Intel cancelled 20A a little over a year ago; using chips with such a risky yield meant the product schedule was insecure. Hitting the 'industry-normal' yield ramp means the process is stable, and Intel can predict where it is going to be with Panther Lake yields a quarter or two down the road.

An avid reader might ask why Intel measures yield improvement per month, while modern process technologies (e.g., TSMC N3 or Intel 18A) have cycles that are around 120 days long. This actually happens because fabs track the defect density (D0) and process quality at the moment wafers enter the line, not when they finish.

Chipmakers tend to implement fixes — lithography tuning, etch-uniformity adjustments, systematic-defect removal — that immediately change defect density and the projected final yield of wafers started that month, even though those wafers will not complete for another three or four months. Since these changes reduce defects continuously, chipmakers can calculate the expected yield right away using standard yield models. Hence, once Intel's models show continuous improvements for 18A in general and Panther Lake compute tile in particular, the company can safely launch the CPU commercially.

Of course, when we talk about any yield-improvement curve, an elephant in the room is the starting point. If we start from 25% and improve yields by 7% per month, we reach an industry normal 85% good die yield in 8.5 – 9 months, sometime in early fall 2026. Meanwhile, Intel itself claims that 18A will reach industry standard yields in early 2027, which means that for now, yields are probably 10% to 15%.

Costly at first, but for whom?

Starting quasi volume production with low yields at a development fab is a good way to skyrocket costs; D1D's pilot lines are designed not for efficiency but rather for maximum flexibility, to maximize yields. Intel notes that it will start making compute tiles for Panther Lake in early 2026 at Fab 52, which given the S-shaped good-die yield curve, will be around the time when PNL's GDY hits stable 20% – 25%.

While initiating mass production with such a yield means high costs, retaining production at pilot lines is still more expensive, so moving production of Panther Lake's compute tiles to Arizona makes great sense for Intel. Furthermore, high-volume fabs tend to reveal systematic issues that occur with a process technology, which lets the company perform continuous process improvements to ramp yields and lower performance variations through statistical process control, something impossible to do at pilot lines.

Of course, using a high-volume fab with low yields will hit Intel's bottom line heavily, but this is inevitable.

Taiwanese authorities have opened a national-security-related inquiry involving a former TSMC R&D executive who may have passed the company's trade secrets to a foreign company. The person in question is Wei-Jen Lo, according to a spokesperson for the High Prosecutors Office, who spoke to Nikkei Asia. Yet, for now the investigation is focused on finding out whether there was an intentional or unlawful transfer of TSMC's trade secrets to a foreign entity.

Wei-Jen Lo, a long-time executive at TSMC and Intel, this year retired from the Taiwanese foundry giant after spending 21 years at the company and building one of the strongest semiconductor R&D teams in the industry. However, instead of enjoying life, he unexpectedly surfaced at Intel in late October. Furthermore, he allegedly took a large collection of confidential materials related to TSMC's leading-edge process technologies with him, reports Liberty Times. Keep in mind that we are dealing with unofficial information, and both Intel and TSMC have declined to comment on the matter.

Wei-Jen Lo reportedly rejoined Intel as 'vice president of R&D' in late October, about three months after departing TSMC, according to a TrendForce report. But before leaving TSMC, Lo allegedly used his authority as the senior vice president of corporate strategy development to instruct subordinates to provide him copies of restricted technical documents covering TSMC's N2, A16, A14, and post-A14 process technologies and their derivatives, according to Liberty Times. Since Lo was a high-ranking executive, such requests appeared routine, so no internal security flags were raised at the time, Liberty Times asserts.

If the report from Liberty Times is to be believed, then Wei-Jen Lo is responsible for 'advanced equipment and module development from R&D up to pre-mass-production' at Intel, which does not look like a description of a 'VP of R&D' position. However, if the information is correct, it essentially means he is overseeing new production equipment and process modules before they are handed over to full-scale production. At first glance, such responsibilities may be too low for a VP as large chipmakers tend to have 'module owner,' or 'process owner,' responsible for a particular line of work within a broader process technology development process. However, as equipment tuning and the right tool settings are incredibly important for semiconductor performance and yields, Intel might establish a position overseeing new fab tools before they are used for mass production.

If this is indeed the case, could TSMC's secret documents covering the company's N2, A16, A14, and post-A14 process technologies help Wei-Jen Lo and Intel? Hardly. Intel's 18A process technology is already in mass production, and only Intel engineers can tune it to get lower defect density, improve CD uniformity, etc.

Furthermore, 18A is different from both N2 and A16 across so many aspects (e.g., 18A uses pattern shaping, N2 does not, A16 uses Super Power Rail backside power delivery that connects power directly to each transistor's source and drain, 18A's PowerVia delivers power to transistor contacts) that TSMC's experience is hardly significantly valuable for Intel's engineers, but is valuable for the company's competitive analysis team. As for information about more sophisticated nodes, Intel's 14A and TSMC's A14 will again be very different, as the former plans to use High-NA EUV lithography tools for critical layers, whereas the latter will rely on Low-NA EUV litho tools and multipatterning.

Meanwhile, as one of the leaders of advanced technology development at TSMC in recent years, he could bring valuable cultural input to Intel's process development, process integration, and manufacturing organization

Lo's departure was originally treated as a celebratory milestone. TSMC held a farewell event honoring his 21 years of service, and after leaving, he received the ITRI Fellow distinction, presented in person by Vice President Hsiao Bi-khim. Since TSMC believed he was retiring, it appears he was not asked to sign a non-compete agreement, a customary requirement for departing executives that expressly forbids employment at competing firms for 18 months, with half-salary compensation. However, now TSMC is reportedly investigating whether Lo indeed took trade secrets with him.

Most recently, Wei-Jen Lo served as senior vice president, overseeing technology development within the R&D organization at TSMC. He joined the company in 2004, initially taking charge of Operations II as a vice president. From 2006 through 2009, he led the R&D division, after which he transitioned into a role managing the firm’s Advanced Technology Business along with manufacturing-technology operations. Under his leadership, his organization has accumulated over 1,500 patents worldwide, including approximately 1,000 filed in the United States.

Before moving to TSMC, Dr. Lo held senior technical and production roles at Intel, including oversight of the company's development site in Santa Clara between 1997 and 2000, according to The Org. His earlier career included teaching at an American university and research positions at Motorola's R&D organization and the Xerox Microelectronics Center.

Intel's management revealed during the company's Q3 2025 earnings call that while its 18A fabrication process is progressing predictably, with usable yields, enabling the company to begin ramping production of the Core Ultra 300-series processors, codenamed Panther Lake. However, the ramp-up of 18A processors will be slow due to relatively low yields, and Intel will not expand available 18A capacity at a rapid pace. Currently, 18A's yields are not yet comfortable from a commercial point of view.

"We are making steady progress on Intel 18A, we are on track to bring Panther Lake to market this year," said Lip-Bu Tan, chief executive of Intel. "18A yields are progressing at a predictable rate, and Fab 52 in Arizona, which is dedicated to high-volume manufacturing, is now fully operational."

Intel's 18A process technology is the company's first production node that relies on RibbonFET gate-all-around (GAA) transistors as well as features PowerVia backside power delivery. Intel will use 18A to produce Panther Lake processors for consumer PCs, then for Xeon 6+ 'Clearwater Forest' and 'Diamond Rapids' processors for data centers, as well as for Nova Lake CPUs, which target the enthusiast market.

18A ramp will be slower than planned

David Zinsner, Chief Financial Officer at Intel, told analysts that yields are sufficient to support Panther Lake product shipments, but not yet high enough to deliver normal profit margins. Yields should reach Intel's desired cost level by the end of 2026, with industry-standard results in 2027, according to Zinsner.

"Yields are adequate to address supply, but they are not where we need them to be in order to drive the appropriate level of margins," said Zinsner. "By the end of next year we will probably be in that space, and certainly the year after that they will be at what would be an industry-acceptable level."

This means that Intel will ramp up production of its Panther Lake processors more slowly than initially planned, and will focus on building more advanced models first (assuming it can make enough chips with higher-end specifications), to sell them at higher prices.

Zinsner also emphasized that Intel does not plan to add significantly more 18A capacity in 2026. Lip-Bu Tan added that the company will add capacity only when it has commitments from its own products division or to external customers. The executives expect 18A supply to peak by the end of the decade.

"I would not expect significant capacity increases in the near term [next year]," Zinsner said. "We do not get to peak supply for 18A until the end of the decade, and we do think this node will be a fairly long-lived node for us."

Intel certainly has big plans for 18A, and its performance-enhanced variant 18A-P. The company's chief executive emphasized that 18A will serve as the foundation for at least three future generations of consumer and server products, which include secure-enclave programs with the U.S. government, and for external foundry clients. Last quarter, the company also released an 18A-P process development kit (PDK), which opens the door for external customers to design chips on this fabrication technology.

When Intel and Microsoft announced their plan to build a 'custom processor' on Intel's 18A fabrication process in early 2024, neither of the companies even hinted at the purpose of that silicon, leaving a lot of space for guesswork and interpretation by industry observers. Today, SemiAccurate reportedly broke the silence about Intel Foundry's 18A foundry customers, reporting that Intel Foundry (IF) is on track to produce an AI processor on 18A or 18A-P for Microsoft.

So far, Intel Foundry has officially landed only one major external customer for its 18A manufacturing technology, which is Microsoft. But while we tend to think about Microsoft as a cloud and software giant, the company has quite a potent hardware development (or at least hardware definition) team that builds custom silicon for a variety of data center applications, including Cobalt CPUs, DPUs, and Maia AI accelerators, just to name some. As it turns out, one of Microsoft's next-generation AI processors will reportedly be made by Intel Foundry.

If true, the deal would give Microsoft access to a US-based chip supply chain that isn't as exposed to the capacity constraints that we see with both chip manufacturing and advanced packaging at TSMC. Additionally, the deal could be seen as favorable to Microsoft in other ways, given the US government's investment in Intel.

For the lack of details, we can only speculate which of the next-generation Maia processors will be produced by IF, but this would be a big development for Intel. Since we are dealing with data center-grade silicon, we are talking about processors with a fairly large die size. Hence, if they are on track to be produced at Intel Foundry, then the company's 18A (or 18A-P with 8% higher performance) fabrication process is projected to be good enough not only for Intel itself (which is on track to ramp its Xeon 6+ 'Clearwater Forest in 2026), but also for its foundry customers. The contract could be a sign of good yields on Intel's node: Yields would have a significant impact on a large processor like the Maia, meaning Microsoft would have likely opted for using a product based on a smaller die instead if there were yield issues with Intel's node.

Microsoft's original Maia 100 processor is a massive 820 mm^2 piece of silicon that packs 105 billion transistors, and which is larger than Nvidia's H100 (814 mm^2) or B200/B300 compute chiplets (750 mm^2). While the lion's share of Microsoft's Azure offerings for AI run on Nvidia's AI accelerators, the company is investing a lot to co-optimize its hardware and software to achieve higher performance while increasing efficiency and thus lowering the total cost of ownership. As such, Maia is an important project for Microsoft.

Assuming that Microsoft's AI processors, to be made by Intel Foundry, continue to use near-reticle-sized compute dies, then Intel's 18A manufacturing process is on track to achieve a defect density that is low enough to ramp such chips with decent yields. Of course, Microsoft could partition its next-gen AI processor into several smaller compute chiplets linked through Intel's EMIB or Foveros technologies, but that could impact performance efficiency, so we are most likely talking about a big die or dies close to the reticle size of EUV tools, which is 858 mm^2.

To de-risk such a large component, Intel and Microsoft are almost certainly running DTCO loops, where Intel tunes transistor and metal stack parameters for Maia's workloads and performance targets. In addition, Microsoft could embed spare compute arrays or redundant MAC blocks into next-gen Maia layout to enable post-manufacturing fusing or repair, which is what companies like Nvidia do with their designs.

Meanwhile, the big question is what exactly Intel Foundry will produce for Microsoft and when. Based on the latest rumors, Microsoft is currently working on its next-generation codenamed Braga (Maia 200?) processor that will use TSMC's 3nm node and HBM4 memory, supposedly due in 2026, as well as Clea (Maia 300?) due later.

Intel has started volume production of its Core Ultra 3-series 'Panther Lake' processors, the company said on Thursday. Intel's Panther Lake is a crucial CPU for the company, designed to demonstrate Intel's ability to develop a competitive processor and produce it internally using its leading-edge manufacturing technology. This is intended to enhance the company's reputation among clients, the general public, and potential foundry customers.

While the official start of 18A production is a win for the company, as it is technically the first with a 2nm-class node in production, it still faces a potent foe in TSMC — the new node merely represents catching up rather than taking the lead. Here's how the two nodes stack up.

Intel 18A vs. TSMC's N2

Intel's 18A (1.8 nm-class) fabrication process is one of the key features of the company's next-generation Panther Lake platform, serving as both its technological showcase and strategic milestone.

The 18A production node itself is designed to prove that Intel can not only create a compelling CPU architecture but also manufacture it internally on a technology node competitive with TSMC's best offerings. The node is also the first 1.8 nm-class (or, as Intel brands it, 2 nm-class) process to enter high-volume production anywhere in the world, preceding TSMC's N2 by weeks or even months.

18A employs Intel's RibbonFET gate-all-around transistors and PowerVia backside power delivery, two technological breakthroughs implemented simultaneously. Intel de-risked these two innovations separately in different internal nodes, but implementing them simultaneously for the first time in a production node is still a somewhat risky move intended to demonstrate that Intel can leap forward and introduce these innovations at once.

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**According to TechInsights.
*** According to WikiChip.

Analysts believe that Intel's 18A will lead the industry in terms of performance and power efficiency. However, TSMC's N2 is projected to offer considerably higher high-density (HD) standard-cell transistor density (313 MTr/mm^2) compared to Intel's 18A (238 MTr/mm^2), according to reports.

While most modern designs use a mix of high-density (HD), high-performance (HP), and low-power (LP) standard cells, higher HD transistor density could still mean lower per-transistor costs for the foundry. However, it is unclear whether these savings will be passed on to the company's clients.

Furthermore, it should be noted that when comparing the transistor density of Intel's 18A, which features a backside power delivery network, with TSMC's N2, which uses a traditional frontside PDN, the comparison is not entirely accurate. Intel's 18A leaves the front side almost entirely for signal interconnects and logic transistors, whereas TSMC's N2 uses plenty of transistors on the front side for power distribution (power-gating header/footer switches, ESD, MOS decaps, on-die regulators, etc.). As a result, 18A's and N2's effective transistor densities could be very close.

However, flipping the wafer and producing a power delivery network on the backside costs money, so Intel's 18A is likely a more expensive process technology to fabricate than TSMC's N2, which will not be a problem for premium products, though.

While 18A looks good in general on paper, the competitiveness of Intel's Core Ultra 3 'Panther Lake' and Xeon 6+ 'Clearwater Forest' is an important step for Intel toward regaining manufacturing credibility and attracting external foundry customers for 18A, 18A-P, and future 14A nodes.

Production slip and Intel 18A yields

Intel says Panther Lake's compute tiles on 18A 'began early production' at its development and low-volume fabs in Oregon, and 'is now ramping toward high-volume production in Arizona.' As expected, Intel first began to ramp Panther Lake manufacturing at Fab 52. Apparently, Fab 62 is still under construction and will be ramped up when demand for 18A picks up.

The first Panther Lake CPU model is 'slated to ship before the end of the year and broad market availability starting January 2026.' Such an announcement signals a delay, as originally Intel indicated the availability of Panther Lake processors in 2025. Furthermore, the announcement may also highlight a slower-than-expected volume ramp, as the company previously indicated that additional Panther Lake models (not just the halo SKU) would be rolled out in the first quarter of 2026. This time around, Intel didn't reveal when it expects the whole Panther Lake product lineup to ramp up.

Intel revealed new information about its upcoming Panther Lake chips made on its new 18A node at an event in Arizona, including claims that the chips can deliver 50% more performance at similar power to its Lunar Lake chips or reduce power by 30% in multi-threaded work compared to its Arrow Lake-H processors. Going by past Intel launch cycles, we're likely to hear more about these chips at CES 2026. Intel says "broad market availability" will start in January 2026.

These sorts of improvements are badly needed because, in recent years, Intel has faced a triple threat in the laptop processor market. AMD, Qualcomm, and Apple all want a piece of the lucrative premium laptop pie, and especially in the case of Qualcomm and Apple, the arrival of high-performance, highly efficient Arm cores on SoCs boasting powerful NPUs and GPUs has forced Intel to up every part of its game to stay competitive on performance and battery life.

Meteor Lake and Lunar Lake Core Ultra CPUs proved that relatively short battery life wasn't an inherent problem of Intel x86 products, but the highly integrated design of Lunar Lake SoCs (combining both compute and memory on a single package) meant that laptop OEMs didn't have nearly as much flexibility and control over system configurations and costs as they might get with a Meteor Lake or Arrow Lake CPU and discrete memory packages, whether in soldered or SO-DIMM flavors.

In exchange for that greater flexibility in memory configurations, Arrow Lake-H SoCs come with tradeoffs of their own. Arrow Lake systems certainly don't have bad battery life, but Lunar Lake is still the best thing going for unplugged efficiency from Intel CPUs.

Lunar Lake also includes a GPU built on Intel's latest Xe2 graphics architecture, while Arrow Lake-H CPUs use an older, larger Xe-LPG+ GPU, which has its roots in first-gen Arc Alchemist products, to deliver relatively similar performance (but likely with worse power efficiency).

Arrow Lake-H also carries over Meteor Lake's rather limited pair of Crestmont E-cores in its low-power island, even as its on-die E-cores got an upgrade to the more advanced Skymont microarchitecture that also underpins the quartet of low-power E-cores on Lunar Lake. Are you lost yet?

This dizzying mix of performance levels, power efficiency targets, architectural generations, and system configuration restrictions across Intel mobile platforms is a headache for consumers and laptop makers alike.

Enter Panther Lake, the great unifier that Intel hopes will bring the best of Lunar Lake's power efficiency improvements and Arrow Lake's performance scalability together in one common package.

Panther Lake SoCs are all built up from the same cutting-edge P-cores, E-cores, and iGPU architecture, while affording laptop makers more freedom to tailor their products to a wider range of buyers and price points. And as Intel's first product to ship with a compute tile fabricated on the latest 18A process node, Panther Lake has a ton to prove.

At its most recent Tech Tour event, held in the backyard of its leading-edge fabs in Chandler, Arizona, Intel walked us through everything that makes Panther Lake tick. Here’s the story so far.

Intel's 18A process ramps up

Panther Lake's compute tile is one of the first products to be fabricated on Intel's leading-edge 18A node. As a quick refresher, 18A is Intel's (and likely the industry's) first high-volume process to incorporate two major innovations meant to enable future scaling and power efficiency gains: gate-all-around (GAA) transistors, which Intel calls RibbonFETs, and a backside power delivery network, which Intel calls PowerVia.

Intel describes its RibbonFETs as "the ultimate transistor," since their gate structure allows for what the company calls "complete control" over the channel. Compared to FinFETs, whose gate structure doesn't extend to the bottom of the channel and therefore has a "weak point" for controlling leakage current, the RibbonFET gate structure entirely wraps around the channel (as defined by the stack of silicon nanosheets at the heart of the device), minimizing undesirable leakage current when the transistor is off. Among other important characteristics, less leakage current means less energy wasted while a chip is operating.

Intel also claims that RibbonFETs are more flexible for designers than FinFETs. The number of ribbons, as well as their widths, can be adjusted to tailor the transistor's performance characteristics to the needs of a given cell.

PowerVia, Intel's implementation of a backside power delivery network, introduces a second novel approach to chip fabrication. As silicon processes have gotten denser and denser, efficiently routing both signal and power wires above the transistors has gotten more and more challenging as those wires compete for ever more precious real estate.

Instead of building up both power and signal wires above the transistor, the backside power delivery approach first creates the transistors and signal wiring on the front side of the wafer. In the next production step, the wafer gets flipped over, and the back side gets polished away until the transistor contacts are revealed. The power delivery metal layers are then connected directly to the transistors.

Intel says that PowerVia allows for 10% higher density and relaxed routing on the front side of the wafer. For power delivery, the back-side metal layers reduce power loss from the package to the transistor by 30%.

All in all, 18A allows for a 15% higher frequency at the same power as Intel 3 and a 1.3x density improvement compared to the same process. Designers can also choose to harness 18A's advances to deliver a 25% power reduction at the same performance level compared to Intel 3.

Cougar Cove P-cores and Darkmont E-cores: evolution, not revolution

Intel didn't go into fine detail on the changes it made to the Cougar Cove P-core on Panther Lake versus Lunar and Arrow Lake's Lion Cove, or Panther's Darkmont E-core versus Skymont. The improvements the company did discuss for the Cougar Cove P-core are typical refinements of an existing CPU architecture, such as an improved branch predictor and a more capacious translation lookaside buffer (TLB). As Intel says, "we didn't go in and change the width, we didn't change the depth, we optimized."

At a high level, Intel says that Cougar Cove now employs an "AI-based" power management approach that can adjust the aggressiveness of certain functional units, such as the prefetcher, on the fly in response to the demands of diverse workloads.

Another change in Cougar Cove is improved prediction behavior in some cases of memory disambiguation. As Intel puts it, when a processor is executing a program, it will perform load and store instructions for memory accesses; sometimes those instructions are connected. Cougar Cove has improved logic to predict when a load and store are connected and use that information to schedule the load correctly. When this prediction is correct, it can result in higher IPC.

Intel also notes that the move to the 18A process gave it the ability to grow some fundamental structures in Cougar Cove, and the TLB was one of the primary beneficiaries. A bigger TLB means that more complex workloads run faster and more reliably, according to Intel.

Cougar Cove also carries forward and refines branch prediction changes introduced with Lion Cove in Lunar Lake. Lion Cove featured improved branch prediction algorithms and delivered low-latency predictions even for branches far ahead in the instruction stream. Intel says Cougar Cove incorporates lessons it learned from shipping Lion Cove silicon to improve performance. It refined some branch prediction algorithms and grew the sizes of each level in the predictor to further lower latency. Cougar Cove can also store better metadata about past prediction results to improve accuracy.

Intel says this all means the Cougar Cove branch predictor can deliver lower latency, more prediction bandwidth, and higher prediction accuracy. These improvements positively impact energy efficiency and performance— a more accurate and more responsive predictor means the CPU core spends less time doing wasteful work and more time doing useful work.

Improvements in the Darkmont E-core are also largely evolutionary versus Lunar Lake’s Skymont. As with Cougar Cove, Darkmont can now use a dynamic algorithm to adjust the aggressiveness of its prefetcher to better balance responsiveness and power efficiency in response to the demands of varying workloads.

Like Cougar Cove, Darkmont offers improved branch prediction accuracy. It also saves power in the front end by employing loop stream detection, a technique that allows the front end of the chip to power down during certain instruction sequences. Darkmont also broadens the cases where the chip can employ nanocode sequences to execute complex instructions that traditionally would have been handled by an x86 CPU's microcode engine. Nanocode was introduced in Skymont to improve both performance and power efficiency.

As Intel puts it, the microcode sequencer is a giant ROM that comes into play when certain complex x86 instructions need to be executed. Loading from that ROM is a serial process, and it can only service one decoder at a time, meaning that other front end units will be blocked if they were also to need instruction sequences from the microcode ROM at the same time. Nanocode prevents this blocking behavior by taking some of those microcode instructions and embedding them into programmable logic arrays in each of the three front-end decoders of the E-core.

Since those PLAs are present in each of the three front-ends of the Darkmont core, Intel says the core can run instructions that formerly resided in microcode as "parallel, out-of-order microcode-like sequences." Intel says Darkmont has more cases and more optimized cases where its front-ends can employ nanocode and leave the microcode sequencer alone.

Mix and match

Not every part of a Panther Lake SoC uses 18A, of course. Intel uses the same "disaggregated architecture" concept that debuted in Meteor Lake and was refined on Lunar Lake and Arrow Lake. This approach separates different functional units of an SoC into individually fabricated "tiles" that are made in Intel's own fabs or at foundries like TSMC, then joined together using Intel's Foveros packaging technology.

In turn, each Panther Lake compute tile, fabricated in-house on 18A, is built up from three basic core complexes. A compute tile can (so far) include up to four Cougar Cove P-cores, up to eight Darkmont E-cores, and a separate "low-power island" cluster of four more Darkmont E-cores that are meant to "confine" suitable workloads to a lower-power compute domain for extra battery life, an idea introduced in Meteor Lake and refined further in Lunar Lake.

Meteor Lake and Arrow Lake both relied on a pair of Crestmont E-cores in this island that were limited in both power and clock speeds to maximize energy savings, but their limited performance meant that more power-hungry parts of the chip might be awakened more often if a task exceeded their limited capabilities. Lunar Lake got four Skymont E-cores in this island with their own power rail, which allowed them to be clocked higher and do more demanding work before tasks had to be shifted to the P-cores on that SoC.

As an evolution of Skymont, Panther Lake's Darkmont low-power E-cores allow more demanding tasks to stay confined to the low-power island for longer, and they can contribute to multi-threaded workloads for extra parallelism when it's needed. They're not on the main ring bus that connects the main clusters of P- and E-cores on the Panther Lake SoC, however, so they don't share the L3 cache of the larger core cluster. Instead, they have access to a power-efficient 8MB "memory-side cache" that's shared with all the other compute agents on the tile.

This side cache is coherent with the rest of the cache hierarchy across the chip, and coherence among all the caches on Panther Lake is managed by a home agent that communicates with separate coherency agents on each compute domain.

The 18A compute tiles also include Intel's fifth-generation NPU, seventh-generation image processing unit (IPU) for use with premium webcams in laptops, and Xe media and display engines separated from the graphics tile.

For more information on the Xe3 graphics architecture and the two iGPUs that use it on Panther Lake, as well as software and power management improvements, check out our dedicated article.

Three's a crowd

So far, Intel has created two different 18A compute dies that it mixes and matches with two different integrated GPUs (and possibly two different I/O tiles) to create three distinct Panther Lake SoCs, each with different cost and performance targets.

The smallest Panther Lake SoC has four P-cores paired with four low-power E-cores, just like we saw with Lunar Lake. Intel didn't disclose the full specs of its cache hierarchy, but since it lacks higher-power E-core clusters with their own L3 cache, our educated guess is this chip likely only has 12MB of cache shared across its four P-cores. It includes a small Xe3 GPU that offers up to four Xe3 graphics cores. This chip can use traditional DDR5 SO-DIMMs or LPCAMM modules at speeds up to 6800 MT/s, or soldered LPDDR5X running at up to 6400 MT/s.

For storage and peripheral controllers, the platform controller tile on the baby Panther Lake SoC offers 12 PCIe lanes - four Gen 5 and eight Gen 4 - which is enough to connect a Gen 5 SSD and perhaps lower-end storage devices or a discrete GPU. Between its relatively low core count, modest graphics horsepower, and limited memory speeds, we're likely to see this chip in more entry-level laptops that prioritize light weight and battery life over absolute performance.

The midsize Panther Lake SoC adds eight E-cores on a ring bus shared with the four P-cores, in addition to the four low-power E-cores in their dedicated island. Intel says this compute die has up to 18MB of shared L3 across the P- and E-cores. This midsize SoC keeps the same 4 Xe Core graphics tile as the small SoC.

This chip can take advantage of faster memory than its smaller sibling. Like the small chip, it can use both DDR5 modules or soldered LPDDR5X, but it supports DDR5 at speeds up to 7200 MT/s and LPDDR5X at up to 8533 MT/s.

The midsize Panther Lake chip also has expanded PCIe connectivity from its larger platform controller tile: as many as eight PCIe Gen 4 lanes and 12 Gen 5 lanes. Intel wouldn't comment on particular Panther Lake OEM designs in the pipeline, but between its expanded compute resources, richer PCIe connectivity, and support for higher-speed memory versus its smaller sibling, this chip seems well-suited for pairing with a discrete GPU in thin and light laptops, an approach that some Intel partners took with Meteor Lake chips.

The largest Panther Lake SoC retains the same 4P+8E+4LPE CPU core configuration as the midsize SoC but adds a much larger and more powerful 12 Xe3 Core GPU to the package. Intel restricts the memory options that partners can employ with this chip, likely so that it can get adequate memory bandwidth to feed all of those GPU execution units. It can only use LPDDR5X memory and supports the fastest transfer rates of any Panther Lake product: up to 9600 MT/s.

This big chip drops back to the more limited I/O tile with eight PCIe Gen 4 and four PCIe Gen 5 lanes, which is likely an indication that it's targeted at the exploding handheld gaming market and premium thin-and-light laptops that can still game when needed. Pairing discrete GPUs with this version of Panther Lake doesn't make a ton of sense from a system design standpoint.

Performance projections

Intel offered a high-level preview of single-threaded performance with Cougar Cove, suggesting that the new P-core can deliver 10% higher performance at similar power to Lunar and Arrow Lake, or 40% lower power at similar performance in less demanding workloads.

The multi-threaded performance story for Panther Lake is a bit muddier. Intel claims that Panther Lake can deliver 50% more performance at similar power to Lunar Lake, or 30% lower power for multi-threaded performance similar to Arrow Lake-H.

Of course, if we consider these charts in their entirety, Panther Lake can also deliver higher absolute performance at similar power to Arrow Lake-H, emphasizing the greater performance scalability of what we assume to be the 4P+8E+4LPE package.

Beyond these broad and rosy performance projections, Intel didn't discuss any specifics on clocks or power targets for Panther Lake during its presentations, but as with any modern laptop SoC, the frequency, power and thermal targets for these chips are likely to cover such a broad range of designs that it's hard to make generalized statements about their performance, and that's before we get into individual chip models within the product stack.

We'll have to wait and see what types of systems Intel's partners typically produce with Panther Lake SoCs inside before we can even begin to establish performance ballparks. Intel says that the first Panther Lake chips will ship before the end of 2025, and that it expects broad market availability starting in January 2026. Given that timeframe, it's probably safe to say that we will hear much more about Panther Lake products at CES.

It has been a busy few weeks for the semiconductor industry. Apple debuted its next-generation silicon, Nvidia launched an unprecedented partnership, and TSMC denied rumors of a major tie-up with Intel. But across all these developments, one name has remained conspicuously absent: Intel Foundry.

Take the biggest stories of the month. Apple’s new A19 and A19 Pro chips launched on TSMC’s 3nm N3P node. No mention of Intel, no sign of Intel Foundry. That’s obviously not surprising — it's been a few years since we last saw Intel inside of Apple — but it’s a reminder of who controls the high ground in chip manufacturing, and how little visible traction Intel has gained despite years of pledges.

Then came Nvidia’s surprise announcement of a sweeping new partnership with Intel to build x86 CPUs with integrated Nvidia GPU chiplets, linked over NVLink and packaged with Intel’s Foveros technology. Jensen Huang and Lip-Bu Tan appeared together via a joint press conference shortly afterwards, and yet, when asked about moving Nvidia’s GPU foundry to Intel’s fabs, Tan replied: “In terms of Intel’s foundry, we continue to make progress… at the right time, Jensen and I will review that.”

Nvidia CEO Jensen Huang was even more blunt, calling TSMC “magic.” It was a remarkable thing to hear during a live Q&A co-hosted by Intel, as part of a joint announcement, but not entirely unsurprising, given Nvidia and Intel's good working relationships with TSMC.

A roadmap without traction

Intel Foundry was established with the goal of directly competing with TSMC and Samsung in contract chip manufacturing. But in the years since its launch in 2021, Intel Foundry has been dominated by delays, customer dropouts, and a brutally honest admission in Intel’s latest filings that Intel Foundry has so far failed to attract significant customers.

Intel previously said its 1.8nm-class 18A process was on track for foundry in 2025 — indeed, risk production began in Q1 — and it continues to build toward 14A beyond that. But internally, Intel now says that 18A’s first and most important customer isn’t some blue-chip hyperscaler or chip startup but rather, Intel itself.

That’s not necessarily a bad thing. Many successful foundries start by proving their nodes with internal products. However, it highlights how far Intel still is from market leaders. TSMC is already producing 3nm chips for Apple and working toward 2nm volume next year. Samsung, despite customer churn, is also advancing its roadmap.

Intel Foundry's biggest problem remains yield. The 18A process still struggles to produce usable chips at high enough rates to be viable at scale, and that cost parity with TSMC is still out of reach. Intel’s own earnings show Intel Foundry losing billions per quarter, with operating losses of more than $3 billion reported for Q2 2025 alone.

Packaging first, foundry later

What Intel has succeeded in doing is packaging, and Lip-Ban Tu knows it. The joint Nvidia-Intel announcement was in many ways framed as a potential packaging breakthrough, with Jensen Huang highlighting Intel’s ability to connect Nvidia’s GPU chiplets with Intel CPUs using Foveros, calling it the kind of multi-technology integration that other foundries simply can’t deliver in the same way.

That packaging capability may well become Intel’s biggest near-term advantage. Foveros and EMIB give the company a mature chiplet integration stack, well-suited to an era where performance gains come more from heterogeneous integration than monolithic scaling. And with Nvidia, Intel finally has a marquee partner willing to bet on that stack, even if not (yet) on the foundry behind it.

There’s another reason Intel is focusing on packaging — it buys time. Unlike bleeding-edge wafer production, packaging doesn’t demand the same kind of node-level maturity. It allows Intel to use proven dies, whether its own or those of its partners, while demonstrating value through integration and system-level efficiency. It also aligns with the broader U.S. industrial strategy, which increasingly sees chip packaging as a national priority.

And because Foveros can integrate chiplets from multiple sources, Intel isn’t locked into its own process nodes. As Huang noted, Nvidia’s chiplets still come from TSMC, but the package doesn’t have to. Intel’s unique cross-foundry packaging model could be a future-proof wedge into multi-vendor systems.

Packaging is also a fast on-ramp for revenue generation for Intel Foundry. Qualifying new chip designs with customers can be a years-long process that takes time to yield revenue and profit, whereas the lead times for chip packaging often only take a few months before revenue generation begins.

A quiet retreat?

Intel pulled the wraps off its first all-E-core Xeon at Hot Chips on Monday, August 25, in Cupertino, California. Dubbed Clearwater Forest, it's the first Xeon built on the company’s next-gen 18A process.

Scheduled to ship in 2026, the processor packs a punch with 288 efficiency cores and a two-socket ceiling of 576 cores, as well as over 1,152 MB combined last-level cache. On paper, it’s Intel’s next attempt to close the performance-per-watt gap in the data center, and it’s a shot across the bow at AMD’s EPYC line.

Darkmont cores bring modest IPC gains, massive scale

Architecturally, Clearwater is a spiritual sequel to Intel’s 144-core all-E-core Xeon, Sierra Forest, but with a few notable upgrades. The new Darkmont E-cores offer a wider 3x3 decode engine, deeper out-of-order windows, and enhanced execution ports, resulting in approximately 17% better IPC than the Crestmont generation.

Four cores share 4MB of L2 cache, and the chip doubles L2 bandwidth compared to the Sierra. Multiply that across 288 cores, and you’ve got a throughput monster designed to eat multithreaded web services and AI inference jobs alive.

The choice of process matters just as much as core count. Clearwater is one of the first real-world testbeds for Intel’s 18A node, which pairs RibbonFET transistors with backside power delivery.

This is effectively Intel’s answer to the density and power efficiency questions that have enabled TSMC and AMD to dominate in recent years. By separating power and signal routing, Intel claims higher cell utilization and lower IR drop, features that hyperscalers care about when power bills stretch into megawatts.

A new definition of Xeon?

Just a few days ago, Intel's upcoming Arrow Lake-S desktop refresh was leaked again, and this time, we learned that it's allegedly coming in the second half of 2025. Paired with a new NPU and higher clock speeds, the refresh would still be binned on TSMC's N3B node and bring modest improvements to the lineup. However, a new tweet from leaker Jaykihn now suggests that there won't be any upgrades to AI capability in Arrow Lake 2.0, as it's said to retain the same NPU present in the current processors.

Intel introduced the upgraded NPU 4 in last year's Lunar Lake. It leapfrogged the company's existing mobile chips to become Microsoft Copilot+ certified, as the NPU has up to 48 TOPS of AI performance. Arrow Lake, Intel's desktop lineup, has the older NPU 3, which debuted back in 2023 with Meteor Lake. As such, it falls short of the 40 TOPS minimum requirement for Copilot+ because NPU 3 is only capable of 11.5 TOPS. If the tipster is to be believed, even two years later, Intel's desktop CPUs will still be equipped with an outdated AI module that cannot compete with mobile-first offerings from AMD or Apple.

If there is no new NPU with the Arrow Lake refresh, then a slight bump to clock speeds is the only 'upgrade' the Blue Team will bring to the table, and that's just not enough. Let's be clear, AMD has somewhat gone down the same road with its gen-over-gen refresh upgrades, relying more on X3D improvements down the line, rather than major architectural breakthroughs, though that's reportedly about to change. Unfortunately, Intel's sales have been in a constant decline over the past few years, so they need a more substantial overhaul than AMD.

Last week, CEO Lip-Bu Tan said that Intel is "not in the top 10 semiconductor companies" in the world anymore — not something you'd want hear from your leader, even if it's an exaggeration. The company has Panther Lake and Nova Lake lined up as its next launches for laptops and desktops, respectively. Panther Lake will finally bring Intel's long-awaited 18A process to the market, the Blue Team's Hail Mary that should propel them a few ranks in bleeding-edge chip manufacturing. Therefore, even if Arrow Lake's refresh—regardless of it having the new NPU or not—looks underwhelming, Intel is still alive and doing exciting things we can all look forward to. After all, more competition is better, for us.

Intel isn’t done with Arrow Lake yet. After having launched a total of 22 locked and unlocked SKUs since last year's not-so-incredible launch, the company is now looking forward to the next wave. According to ZDNet Korea, a refresh of the Arrow Lake-S desktop lineup is reportedly set for release in the second half of 2025, and while it won’t introduce new core architectures, it will bring minor upgrades to (try to) stay competitive, including a bulked-up NPU that supports CoPilot+. Expect slightly higher clock speeds thanks to better silicon binning and refinements on the Intel 20A process, which introduced RibbonFET and PowerVia in Arrow Lake’s initial release.

This new report comes after a previous leak from @momomo_us, who shared motherboard reference documents revealing the existence of Arrow Lake 2.0, if you will. As such, the refresh will remain on the LGA 1851 socket and continue to use 800-series chipsets, ensuring that current motherboards remain fully compatible and extend their life for one final generation before Nova Lake replaces them next year.

Core configurations reportedly won’t change—Lion Cove P-cores and Skymont E-cores are staying the same—but firmware and tuning optimizations will likely lead to a boost in efficiency. Intel has been trying its best to gain whatever ground possible when it comes to squeezing more juice out of Arrow Lake with updates like Core Boost 200S at Computex earlier this year, and "IPO" optimized memory profiles that are currently live in China with various system integrators.

Moreover, one notable upgrade is the rumored new NPU4, which would make its debut on Arrow Lake-S refresh after its introduction in last year's Lunar Lake mobile chips. The original Arrow Lake desktop CPUs shipped with NPU3 (from Meteor Lake) which only had 13 TOPS of AI power, short of Microsoft’s Copilot+ AI PC requirements of at least 40 TOPS. The refresh is expected to surpass that with 48 TOPS, which will be able to handle the increasing demands of local AI workloads. With AI features becoming more central to consumer usage, this NPU upgrade is likely Intel’s main play. It should allow the company to brand these chips as AI-ready.

There’s no indication yet of how Intel will brand the refresh—whether it’ll fall under the same Core Ultra 200 series umbrella or branch off as a new tier—but this is more of an iterative performance uplift than a fully-blown new generation. It’s likely a strategic move to extend Arrow Lake’s shelf life while the company gears up for Nova Lake, which is still expected in 2026 on the Intel 18A node.

ZDNet Korea also reported that Intel's actual next-gen architecture is still more than a year away since the launch is currently scheduled for H2 2026. Till then, Intel's declining market share will have to cling on for dear life as the market continues to see red.

Lip-Bu Tan, the chief executive of Intel, is considering stopping the promotion of the company's 18A fabrication technology (1.8nm-class) to foundry customers, instead shifting the company's efforts to its next-generation 14A manufacturing process (1.4nm-class) in a bid to secure orders from large customers like Apple or Nvidia, reports Reuters. If this shift in focus occurs, it would be the second node in a row that Intel has deprioritized.

The proposed adjustment could result in major financial consequences and alter the trajectory of Intel's foundry operations, as it will effectively withdraw the company from the foundry market for several years. Intel informs us that the information is based on market speculation. However, the spokesperson provided some additional insight on the company's roadmap, which we've added further below.

“We are not going to comment on market rumors and speculation," an Intel spokesperson said to Tom's Hardware. "As we have said previously, we are committed to strengthening our roadmap, delivering for our customers and improving our financial position for the future."

Lip-Bu Tan proposes killing 18A as a foundry node

After taking the helm in March, Lip-Bu Tan announced intentions to cut costs in April, which is expected to involve layoffs and the cancellation of certain projects. According to the new report, by June, he began sharing with colleagues that the 18A manufacturing process — a technology designed to showcase Intel's manufacturing prowess — was losing appeal to outside customers, which is why he believed it made sense for the company to shift away from offering 18A and its performance-enhanced 18A-P version to foundry customers.

Instead, Lip-Bu Tan proposed directing more resources to the completion and promotion of 14A, the company's next-generation node, which will be ready for risk production in 2027 and for volume production in 2028. Given the timing of 14A, it is now time to start promoting it among potential third-party Intel Foundry clients.

Intel's 18A fabrication technology is the company's first node to utilize its 2nd-generation RibbonFET gate-all-around (GAA) transistors, along with a PowerVia backside power delivery network (BSPDN).

By contrast, 14A utilizes RibbonFET 2 transistors, PowerDirect BSPDN, which delivers power directly to each transistor's source and drain through specialized contacts, and features Turbo Cells for critical paths. In addition, 18A is Intel's first leading-edge technology that is compatible with third-party design tools and can be used by its foundry customers.

Massive write offs vs. depreciation costs

Dropping external sales of 18A and 18A-P would require Intel to account for a substantial write-off reflecting the billions it spent developing the manufacturing technologies, according to individuals familiar with internal deliberations cited by Reuters. Depending on how you count development costs, the resulting charge could total hundreds of millions or even billions of dollars.

Both RibbonFET and PowerVia were initially developed for 20A, but that technology was cancelled for internal products last August in a bid to focus on 18A for both internal and external products.

Intel's rationale behind the move may be rather simple. By limiting the number of potential customers for 18A, the company may potentially cut its operating costs. The majority of tools required for 20A, 18A, and 14A (except for High-NA EUV equipment) are already in place at its Fab D1D in Oregon, as well as at Fabs 52 and 62 in Arizona. However, once these tools are formally put into operation, the company will have to report their depreciation as a cost. Not putting them online potentially enables Intel to cut its costs amid uncertainties with orders from third-party clients.

In addition, by not offering 18A and 18A-P to external customers, Intel may save money on engineers dedicated to supporting the sampling, ramp, and mass production of third-party circuits at Intel fabs. Obviously, this is speculation on our side.

However, by ceasing to offer 18A and 18A-P to external clients, Intel will be unable to demonstrate advantages of its fabrication nodes to a broad range of customers with various designs, which would leave them with a single choice for next two or three years: go with TSMC and use N2, N2P, or even A16.

Although Samsung is set to formally start making chips on its SF2 (also known as SF3P) node later this year, that node is expected to be behind Intel 18A and TSMC's N2 and A16 in terms of power, performance, and area.

Essentially, Intel would not be showing up to its fight against TSMC's N2 and A16, which will certainly not help to gain the confidence of potential clients towards other Intel offerings, namely 14A, 3-T/3-E, Intel/UMC 12nm, and others.

Reuters' sources familiar with the matter explained that Lip-Bu Tan had asked Intel's specialists to prepare proposals for discussion with Intel's board this fall. Options could include ceasing efforts to sign up new clients for 18A, though given the scale and complexity of the issue, the decision might not be finalized until the board meets again later this year.

Intel itself reportedly declined to discuss hypothetical scenarios but confirmed that the main customer for 18A has always been its own Products division, which plans to begin producing codenamed Panther Lake CPUs for laptops in 2025 using this technology. Eventually, 18A and 18A-P will be adopted by Clearwater Forest, Diamond Rapids, and Jaguar Shores products.

Limited demand?

Intel's push to attract large-scale external clients to its Intel Foundry fabs remains critical to its turnaround, as only with high volumes the company will be able to pay off for its process technologies that cost billions to develop.

However, in addition to Intel itself, only Amazon, Microsoft, and the U.S. Department of Defence have formally confirmed plans to use 18A. While Broadcom and Nvidia are also reportedly testing Intel's latest process technology, they have yet to commit to using it for actual products.

Intel's 18A has one key advantage over TSMC's N2: it features backside power delivery, which is particularly useful for power-hungry processors aimed at AI and HPC applications. TSMC's A16 with Super Power Rail (SPR) will only enter mass production in late 2026, so 18A will maintain the advantage of offering backside power delivery for Amazon, Microsoft, and potentially other customers for a while.

However, N2 is expected to offer higher transistor density, which is beneficial for the vast majority of chip designs. Furthermore, while Intel has been running Panther Lake silicon at its D1D fab for quarters (so, currently Intel is still in risk production using 18A), the company's high-volume Fab 52 and Fab 62 started to run 18A test silicon this March, so they will start producing commercial chips only late in 2025, or rather in early 2025.

Intel's external customers are, of course, interested in producing their designs at high-volume fabs in Arizona rather than at development fabs in Oregon.

Summary

Intel CEO Lip-Bu Tan is reportedly considering halting the promotion of the company's 18A fabrication process to external clients and instead focusing on the next-generation 14A production node, aiming to attract large customers such as Apple and Nvidia.

Intel has published a paper about its 18A (1.8nm-class) fabrication process at the VLSI 2025 symposium, consolidating all its information about the manufacturing technology into a single document. The new 18A production node is expected to deliver significant improvements in power, performance, and area over its predecessor, increasing density by 30% while enhancing performance by 25% or reducing power consumption by 36%.

But, perhaps more importantly, 18A will be Intel's first process technology in years that will compete head-to-head with TSMC's leading-edge technology when both enter mass production in the second half of this year.

PPA advantages

Intel's 18A process node is designed for a wide range of range of products across both client and datacenter applications, and the first Intel's product to use it will be the Panther Lake CPU, which is due to be formally announced later this year. To address different applications, Intel 18A has two libraries: high-performance (HP) with 180nm cell height (180CH) and high-density (HD) with 160nm cell height (160CH) for lower-power applications.

Intel says that compared to Intel 3, its 18A fabrication technology boosts performance by 25%. It manages to achieve this without increasing voltage or circuit complexity when running a typical Arm core sub-block, implemented using a 180CH HD library at 1.1. When operating at the same clocks and 1.1V voltage, it also cuts power usage by 36% compared to the same design on Intel 3. At a reduced voltage of 0.75V, 18A offers an 18% speed increase and uses 38% less energy. Furthermore, designs fabricated on 18A occupy roughly 28% less area than those built with Intel 3.

There is a major catch about comparison of voltages between Intel 3 and 18A. The former supports <0.6V, 0.75V, 1.1V, and 1.3V, which makes it particularly suitable for data center devices. This type of workload needs to burst to high clocks, across dozens of cores when demanding peak performance. Then, it'll need to throttle down to a low-power state to save power. To contrast, 18A seems to support 0.4V, 0.75V, and 1.1V, which very good for client PCs and data center CPUs, but may not be ideal for processors that need maximum clock speeds. However, other advantages of Intel's 18A will likely offset the lack of 1.3V support for the vast majority of applications (more on this later).

As for SRAM, Intel's 18A process includes a high-density SRAM bit cell measuring 0.021 µm², translating to an SRAM density of roughly 31.8 Mb/mm². This is a major improvement over the 0.024 µm² bit cell used in Intel 4. This puts Intel 18A on par with TSMC's N5 and N3E nodes in terms of SRAM density. However, TSMC’s upcoming N2 process goes further, reducing the bit cell to approximately 0.0175 µm² and achieving a higher density of around 38 Mb/mm².

Intel's 18A relies on the company's 2nd generation RibbonFET gate-all-around (GAA) transistors, and a PowerVia backside power delivery network (BSPDN). We investigate exactly how Intel managed to implement GAA transistors and BSPSN below.

RibbonFET

In GAA transistors, the gate completely wraps around the channel, offering superior electrostatic control compared to FinFETs, which only wrap around on three sides. Such an architecture enables engineers to finely tune device characteristics for either high performance or low power consumption by adjusting the total effective channel width (Weff). This is typically achieved by varying the width and number of stacked nanosheets. More sheets, alongside wider sheets, can increase drive current and performance at the cost of power, while fewer or narrower sheets reduce both performance and power consumption.

Intel's 18A RibbonFET transistors feature four nanoribbons and support eight distinct logic threshold voltages (VTs) — four for NMOS, and four for PMOS — spanning a 180mV range. This level of VT granularity is achieved through dipole-based work-function tuning, a method that allows precise control of transistor behavior without altering its physical dimensions. This approach is especially important, given the tight spatial constraints in GAA transistor structures, such as RibbonFETs, where traditional methods, like doping adjustments, are limited.

An Intel graph from the paper shows that despite this wide VT range, the transistors exhibit strong electrical characteristics, including steep subthreshold slopes and well-behaved drive currents across both Id–Vg and Id–Vd curves. These results confirm that Intel has successfully maintained device performance and control across the entire VT spectrum, which enables flexible circuit design choices that balance frequency, power, and leakage within the same process.

PowerVia

Intel's PowerVia backside power delivery network (BSPDN) relocates power delivery from the top metal layers to the rear side of the chip, creating a physical separation between power and signal wiring. This technique addresses issues like rising resistance in the vertical connections of in the back-end-of-line (BEOL) layers, which in turn enhances transistor efficiency and reduces power usage. Additionally, it prevents signal degradation caused by power interference and allows for tighter packing of logic elements, increasing overall circuit density.

Intel's PowerVia delivers power to transistor contacts, which is a slightly less sophisticated approach compared to TSMC's Super Power Rail (coming in 2H 2026 along with A16), which connects directly to each transistor's source and drain. In addition to BSPDN, Intel also implemented its new high-density metal-insulator-metal (MIM) capacitor to enhance power supply stability.

Intel has now disclosed the key benefits of its backside power routing. First up, PowerVia increases transistor density by 8% to 10%, which is quite a sizeable part of 18A's overall 1.3X transistor density increase over Intel 3. Secondly, the front-side metal layers in its 18A process achieve approximately 12% better resistance-capacitance (RC) performance and show a 24% to 49% decrease in via resistance compared to Intel 3, thanks to improved metallization techniques and the use of ultra-low-k dielectrics. Thirdly, 18A's PowerVia reduces voltage droop compared to Intel 3 (the worst-case scenario for Intel 3) by up to 10 times. Lastly, BSPDN simplifies chip design as it simplifies the routing of signal and power wires.

PowerVia's reliability

Since PowerVia is the industry's first backside power delivery network (BSPDN) used in mass production, Intel also presented reliability test results. These demonstrate its long-term durability and chip-package interaction (CPI) performance.

According to JEDEC-standard TQV tests, PowerVia passed multiple stress conditions with zero failures, including highly accelerated stress testing at 110°C and 85% humidity for 275 hours, extended high-temperature bake tests up to 1000 hours at 165°C, and 750 cycles of temperature swings from –55°C to 125°C. These results confirm that PowerVia can withstand harsh operating environments, without compromising structural or electrical integrity.

In addition to CPI reliability, Intel evaluated the impact of PowerVia on SRAM aging and performance stability. Under conditions equivalent to 1000 hours of high-temperature operation, SRAM arrays maintained stable minimum operating voltage (Vmin) with margin, showing no signs of degradation. This suggests that PowerVia does not negatively affect sensitive on-chip memory and is robust enough to support both digital logic and embedded SRAM under extended stress. Together, these findings are meant to affirm PowerVia's readiness for deployment in high-performance, long-lifecycle computing platforms.

Manufacturability

In addition to improving performance, reducing power consumption, and enabling higher transistor density, Intel's 18A simplifies production flows and simplifies chip design.

By moving power delivery to the backside, Intel eliminates the need for a front-side power grid, which, combined with direct EUV patterning, lowers the total number of masks and simplifies the front-end metal process. By using low-n absorber reticles with tailored dimensional adjustments, Intel also enabled single-pass EUV patterning for the M0–M2 metal layers. This simplification of the lower metal layers reduces process complexity and helps offset the cost of adding extra backside metal layers, which are based on mature, low-cost fabrication techniques. As a result, the overall design process becomes easier and cheaper.

In addition, the backside metal layers of 18A's PowerVia are designed for low resistance and high thermal conductivity, which helps manage the increased power density from the GAA transistors. Also, carrier wafer bonding is optimized for heat removal through the backside, addressing the thermal challenges introduced by high-performance transistors. Finally, PowerVia is compatible with advanced packaging methods like Foveros and EMIB, though we already know this from the fact that Panther Lake uses 18A tiles as well as Foveros 3D.

Summary

Intel has announced the unveiling of three new Intel Xeon 6 P-Core CPUs that it says are designed specifically to handle the most advanced GPU-powered AI systems. The new processors will debut in Nvidia's DGX B300 AI systems.

The new processors, replete with Intel's Performance-cores, also feature new Intel Priority Core Turbo (PCT) and Intel Speed Select Technology – Turbo Frequency, which the company claims delivers customizable CPU core frequencies to improve GPU performance for demanding AI workloads.

All three are available now, and the Intel Xeon 6776P also comes integrated in the Nvidia DGX B300, the company's latest AI-accelerated systems.

Intel says that the introduction of PCT and Intel SST-TF as a pairing marks "a significant leap forward in AI system performance." PCT should allow for the dynamic prioritization of high-priority cores, enabling higher turbo frequencies. Meanwhile, lower-priority cores operate at base frequency in parallel to optimize resource distribution. PCT can reportedly run up to eight, high-priority cores at elevated turbo frequencies, according to Intel.

Intel's Xeon 6 CPUs include up to 128 P-cores per CPU and 20% more PCIe lanes than previous-generation Xeon processors, with up to 192 PCIe lanes per 2S server. Intel also claims Xeon 6 offers 30% faster memory speeds compared to the competition (specifically the latest AMD EPYC processors), thanks to Multiplexed Rank DIMMs (MRDIMMs) and Compute Express Link, and up to 2.3x higher memory bandwidth compared to the previous generation.

Intel says its P-Core Xeon 6 processors have 2 DIMMs per channel (2DPC), and says the 2DPC configuration supports up to 8TB of system memory. It also says MRDIMMs boost bandwidth and performance, all while reducing latency. The new CPUs also feature up to 504 MB L3 cache for faster data retrieval.

Intel Xeon 6 processors also feature Intel AMX, which can offload certain tasks to the CPU. Intel confirmed AMX now features support for FP16 precision arithmetic, which enables efficient data pre-processing and critical CPU tasks in AI workloads. Alongside its three new P-Core processors, Intel has also added a B-variant 6716P-B.

Intel demoed working Panther Lake Core Ultra 300 silicon for laptops, its first chips based on its crucial 18A process node, here at Computex 2025 in Taipei, Taiwan. Unlike the first public demoes at CES 2025 that merely showed the chips powered on, Intel put Panther Lake its paces in real-time rendering and AI applications, showing that the silicon is healthy and on-track for retail availability in early 2026. Intel also shared more information about its performance and power consumtpion expectations for the new chips. 

As you can see in the image above, Intel also had a Panther Lake chip on display, enabling us to see how the CPU, GPU, I/O tile, and SoC tile are arranged on the package. These chips are thought to come with Cougar Cove P-cores and Darkmont E-cores (you can see the unconfirmed leaked specifications of some of the chip models here). 

Intel says the Panther Lake chips blend the power efficiency of Lunar Lake with the performance of Arrow Lake-H, noting that while the chips will be in production in the second half of 2025, presumably launched at CES, full retail availability will not come until early 2026. Intel did tease that the chips will come with the next-gen integrated graphics with XMX graphics, but aside from saying the iGPU performance will be closer to Lunar Lake than Arrow Lake, the company didn't elaborate. These iGPUs are thought to be based on the Xe3 architecture.

Intel ran its Panther Lake benchmarks on two Reference Validation Platforms (RVP) that you can see in the above album. These platforms are used to validate the design and emulate real-world conditions. Both RVPs were equipped with a heatsink and fan, so they were presumably operating without thermal constraints. 

Intel demoed one system running the newly-resurrected Clippy as a large language model to demonstrate that the chips are running AI workloads. The presenter used the system to write game code in Python code. Intel didn't share performance metrics from the benchmark. 

Intel also demoed a system running Da Vinci to edit and manipulate video using local AI processing to process the video, enabling fast manipulation of the video clip, such as changing backgrounds, clothing colors, and adding flying text to the clip. 

Intel also displayed a running developer kit that 300+ developers with ISVs are using to enable software support for the coming chips. Intel demoed the system being used for image editing with auto-coloring and upscaling features, powered, of course, by AI. As you can see in the album, the developer system is quite compact. Intel also had a host of laptops on display from its OEM partners. 

Intel's Panther Lake appears to be on track for its launch schedule, which bodes well for the company's immensely important 18A process node. Intel teased that the next steps are to release concrete speeds and feeds along with more information about the various chip models. We expect those to come trickling our over the next several months. 

It's the final day of Computex 2025, and things are winding down here. We'll still be bringing you updates, pictures from the floor, and more, and some recaps of all the biggest and best announcements.

In the meantime, sit back, relax, and wind down with us as we close out another year of Computex.

I come to Taiwan for the tech, but the affordable, high-quality coffee is what keeps me going

Taipei is great for a lot of reasons. But as a bit of a coffee addict and snob, I really appreciate the abundance of coffee shops and roasters here. And the coffee (like most food here) is pleasantly affordable.

This iced Americano (unfortunately, the cold brew was sold out) from one of my favorite spots, Coffee Moon, was the equivalent of about $3. And that’s on the expensive end. Major chains, like Louisa Coffee (I recommend the egg and peanut butter breakfast sandwich), tend to be cheaper. There are a lot of Starbucks here as well, but I’m not a fan – especially when there are so many other options.

I picked up some fresh-ground coffee for my travel-friendly Aeropress at Ikari Coffee (I like to think this chain is the Ikari Warriors retirement plan) for about $6 – enough for a week’s worth of early mornings and late nights, and then some. It’s going to be hard to go back to the $5 Dunkin’ cold brew when I get back home, even if the sizes are much bigger.

-Matt Safford

Picked up some spicy Guai Guai at 7-11, no Lisa Su or TSMC flavors to be found

There are plenty of tasty and interesting snacks to be had at Taipei’s night markets or the many (many) convenience stores. But I could help but pick up a couple of bags of spicy Guai Guai when I saw them today.

For those not in the know, this brand of Cheetos-like (but usually sweet) snack is part of a tradition or superstition (take your pick) where engineers and tech workers place the snacks in and around important machines to help assure they function without problems. The phenomenon is so widespread that we’ve seen both TSMC- and AMD / Lisa Su-branded versions of the snacks debut (and reportedly quickly get bought up) in the last couple of years. And of course, both companies have seen new levels of success in the past several years. Maybe someone should tell Intel’s new CEO to invest in some blue Guai Guai.

Unsurprisingly, I couldn’t find any of the TSMC or Ryzen varieties of the snacks, so these spicy ones will have to do. I’m going to leave them sitting on my laptop overnight, because it has a bad habit of blue-screening every week or so. Maybe the snacks will keep that from happening until I get home (or at least until I’m done reporting from Computex). If it doesn’t work, I may have to ask AI for some help with my crash dumps.

-Matt Safford

I both love and hate Taipei’s PC and component ads

I’ve been on the ground (and sweating) in Taipei for a few days now, and one of the first things that always strikes me here is the plethora of billboards and signs for various laptops and PC components.

Sure, a lot of this gets ramped up ahead of Computex, and many are in and around the Guang Hua Digital Plaza area, where there are dozens (perhaps hundreds) of shops and storefronts that sell pretty much everything PC related, from high-end gaming laptops to obscure PC cases, and entire stores dedicated to MSI, Asus, Aorus – there’s even a store that pretty much only sells Transcend storage devices and media.

But the ads exist away from the main tech district as well. Today I was walking to a record shop in an arts district, looked up and saw, of all things, a slim vertical billboard for power supply maker, Seasonic.

And later, as I was headed into an MRT (subway) station, making my way back to my hotel, there was a big banner for AMD’s Ryzen 9000 CPUs above the train platform.

The only other place I’ve seen ads like this for PC components and the latest laptops is in Tokyo’s famous Akihabara neighborhood during a visit in 2015 – where I bought a random wafer of chips at the back junk tech store that, sadly, was far too fragile to survive the trip home.

On the one hand, it’s cool to see the PC hardware we obsess over getting the kind of treatment and attention that is more typically afforded to the latest attempt at a blockbuster movie or a tech startup flush with cash and looking to build brand recognition. And I certainly find ads for components more interesting and less annoying than most ads I see walking around our office neighborhood in Midtown Manhattan.

But considering how much I already spend on PC hardware and related tech, I am not sure I’d want to be regularly be surrounded by ads reminding me that the Ryzen 9 9950X3D exists, making my perfectly capable 7950X feel outdated and inadequate, or that my RAM or storage isn’t as fast as it could be.

Sure, signs and billboards that are more targeted to my PC interests are cool to see here in Taipei, but I really don’t need any more “help” deciding when it’s time to upgrade. After all, if I spend all my money on new tech, I won’t have any left over to buy old records.

-Matt Safford

Nvidia CEO Jensen Huang shows off Nvidia RTX 5060

The Nvidia keynote is underway and most of what CEO Jensen Huang is talking about has to do with AI development, not desktop computing. However, he just showed off the new RTX 5060 on stage, flashing an Asus-branded RTX 5060 GPU and an MSI laptop with RTX 5060 inside.

Huang didn't share any details about the cards, but lots of information has already come out. For example, we reported yesterday that the RTX 5060 is 25% faster than the 4060 with frame generation enabled.

While he spoke, Huang stood in front of a digital scene of a pond in a European city (it looked like Italy). He said that an RTX card (perhaps the 5060) was rendering only 1 out of every 10 frames in the scene, which showed candles floating over water. Instead, he said DLSS was generating 9 out of every 10 frames.

This is probably all we'll hear about PC gaming during this keynote.

"You know, when you're CEO, you have many children, and GeForce is here, and now all of our keynotes are 90% not GeForce," Huang said. "But it's not because we don't love GeForce. GeForce RTX 50 series just had its most successful launch ever, the fastest launch in our history. And PC gaming is now 30 years old. So that tells you something about how incredible GeForce is."

Intel demos Panther Lake

Day 1 of Computex 2025 is in full swing, and Intel is demoing working Panther Lake Core Ultra 300 silicon for its laptops, the first to use its 18A process node. We've been shown real-time rendering and AI applications ahead of its early 2026 launch.

• Intel demos running Panther Lake systems, touts performance and power efficiency improvements

Nvidia NVLink expansion

One of Nvidia's biggest announcements at Computex 2025 is a new NVLink Fusion program which allows customers and partners to use NVLink in their own custom rack-scale design. Here are all the details...

• Nvidia announces NVLink Fusion to allow custom CPUs and AI Accelerators to work with its products

Morning folks, Stephen here picking up the live blog until 1pm ET - we're all over the Computex trade floor bringing you the latest insights and news, so stay tuned!

Getting strong "secret government operation" vibes from this scene outside of the Grand HiLai Hotel near the main Computex buildings today. I get it, arm, you're the future of efficient computing (maybe). Please don't call the black helicopters on me.

- Matthew Safford

New Acer monitors

Acer has unveiled the new Nitro PG271K monitor, featuring 4K at 72Hz, with DFR for 1080p at 144Hz, 0.5ms response time (GTG), USB-C, and HDMI ports.

There's also a new 32-inch ProCreator and a new portable PD163QT. Gamers will love the new Nitro GA341CUR W0, a 34-inch UWQHD display with a 240Hz refresh rate.

Nvidia G-Sync comes to Samsung's big screen

Samsung has announced that it is finally adding support for Nvidia G-Sync in its 2025 OLED TV lineup, starting with the S95F.

The return of Windows 7

We've all seen broken McDonald's order consoles running Windows 98 or some other such monstrosity, but how about this Computex display board that appears to have malfunctioned, revealing Windows 7 underneath.

Intel's new Arc Pro B50 breaks cover

Intel has just unveiled its brand new Arc Pro B50, a compact graphics card for workstations with 16GB of VRAM and a starting price of $299. There's also a new Pro B60 with a hefty 24GB with a price tag of roughly $500 per unit.

• Intel launches $299 Arc Pro B50 with 16GB of memory, 'Project Battlematrix' workstations with 24GB Arc Pro B60 GPUs

MSI's new AI-powered 500 Hz beast

MSI's new X50 is a QD-OLED monitor and a 500 Hz refresh rate, but the headline is actually its new AI Care Sensor, which can detect when you're not looking at the monitor, powering down accordingly to reduce burn-in.

• MSI’s new 500 Hz QD-OLED monitor leverages AI tech to save it from burn-in

Maxsun dual-GPU card

Alongside the aforementioned new Intel Arc Pro offerings, there's a brand new partner card from Maxsun that jams two Arc Pro B60 chips onto a single graphics card, replete with 48GB of total VRAM, or 96GB in a two-card configuration.

Cheaper than a 50 Series...

Want to score some Computex swag without splashing out thousands on the best graphics card? Head on down to the Nvidia truck and buy a Jensen Huang shirt for $37 instead.

Nvidia's new supercomputer

Nvidia announced at Computex that it would be working with Foxconn to build an AI supercomputer in Taiwan featuring 10,000 Nvidia Blackwell GPUs.

• Nvidia teams up with Foxconn to build an AI supercomputer in Taiwan

MSI's new desktop AI supercomputer

As promised, MSI has unveiled its new EdgeXpert MS-C931 supercomputer, powered by Nvidia DGX Spark and capable of 1,000 TOPS FP4 performance.

• MSI unveils EdgeXpert MS-C931 desktop AI supercomputer powered by Nvidia DGX Spark

Nvidia: No evidence of AI chip diversion

Nvidia CEO Jensen Huang says there is no evidence of AI chip diversion to blacklisted nations, in response to questions at Computex. Huang said countries and companies understand the rules and want to continue doing business with Nvidia.

• Nvidia CEO Jensen Huang says ‘There’s no evidence of any AI chip diversion’

Noctua's triple-fan RTX 5080

Check out ASUS' new Noctua triple-fan RTX 5080, as well as it's new external GPU dock, which we've been having a look at over on the floor.

• Asus unveils Noctua triple-fan RTX 5080, new external GPU dock, and more at Computex

Some holiday snaps...

Computex 2025 isn't all motherboards and silicon; here are some snaps of the locale here in Taipei.

Asus's RTX 5060

The RTX 5060 (and the long-awaited RTX 5060 driver) are now here, as is Asus' new RTX 5060 laptop lineup.

• Asus adds the RTX 5060 to its gaming laptop lineup, tweaks TUF A14 with better cooling

Asus ups the ante with the 610 Hz ROG Strix Ace XG248QSG gaming monitor

The ROG Strix Ace XG248QSG is the latest among the growing trend of 500 Hz+ gaming monitors. Asus is targeting the 24.1-inch ROG Strix Ace XG248QSG at the esports gaming crowd, and you’ll need one of the best graphics cards for gaming to get the most out of its insane 610 Hz refresh rate.

While Asus touts the 610 Hz refresh rate, it is achievable through overclocking – the panel has a native refresh rate of 600 Hz. Another thing to note is that this monitor uses a TN panel. TN panels aren’t known for their prowess in color reproduction, brightness, or viewing angles. However, Asus says that the ROG Strix Ace XG248QSG uses the latest iteration of its “Super TN” panel to combat some inherent deficiencies; notably improved color and boosted brightness levels (up to 370 nits).

Although the ROG Strix Ace XG248QSG doesn’t have RGB lighting effects that we typically expect from ROG products, it does have an attractive design, and is adjustable for height, tilt, and swivel. As for connectivity, you’ll get DisplayPort 1.4, two HDMI 2.1 ports, and a 3.5mm headphone jack.

• Asus debuts 24-inch 610 Hz Full HD gaming monitor with a Super TN panel

Wood you believe it? Asus' ProArt GeForce RTX 50 family brings wood grain finishes, USB-C connectivity, and even M.2 support

Wood grain trim isn’t usually associated with PC components, let alone graphics cards. But that’s exactly what we have in store with the Asus RTX 50 Series ProArt series. All the graphics cards have a wood grain finish for the fan shroud, giving them a classy look over the more exhaustive use of RGB that we see in many high-end graphics cards.

But it goes beyond the wooden aesthetics; all four members of the ProArt RTX 5080 family include USB-C ports for connecting monitors of peripherals to offer “better versatility for content creation workflows.” The ProArt GeForce RTX 5080 OC goes one step further by including an M.2 slot for plugging in an SSD.

If you’re looking for a top-performing graphics card that offers more than just good looks as a side dish, the ProArt family seems like a good option to pursue – that is, if Asus can keep pricing in check.

• Asus RTX 5080 ProArt comes with a wood grain finish and M.2 slot option

This could be the new fastest SSD

At the moment, the Crucial T705 is the fastest consumer SSD on the market, hitting random reads and writes of 1.55 and 1.8M IOPS respectively. However, today at Computex, Crucial announced its successor, the T710 which promises to be 28 percent faster in reads and 42 faster in writes.

We have a full article with lots of details on the Crucial T710 right here.

The T710 will be available at an undetermined price in 1TB, 2TB, 4TB and 8TB capacities. It will come with and without a heatsink. The heatsink itself will be a slim 11mm thick.

The drive is one-sided and also promises low enough power to work well in a laptop, without massively draining the battery. It uses an SMI SM2508 SSD controller and 276-layer G9 TLC NAND to achieve these results.

Teamgroup is known for its radical cooling concepts that it demos at Computex every year, and 2025 is no exception. This year the company had a triple-M.2 all-in-one liquid cooler for those of you that simply can't cram enough storage into your rig. The company also had a new dual M.2 SSD and CPU cooler on display, too. Yes, the cooled liquid flows from the rad to the SSD first, thus preventing it from getting pre-heated liquid flowing from the CPU.

Good morning!

Good morning and welcome back to day two (one) of Computex 2025! Stephen here for the next eight hours, keeping you posted with everything going on at Computex, including live insight from the floor here in Taipei! While you were sleeping, here's what you missed...

• Asus debuts 24-inch 610 Hz Full HD gaming monitor with a Super TN panel
• Crucial announces T710 SSD with 14.9 GB/s of performance, X10 portable SSD up to 8TB
• MSI brings AMD-based AMD gaming handheld, updated mid-range gaming laptops to Computex

New Razer Blade 14

Razer has unveiled its new Blade 14 laptop at Computex. Sporting the Nvidia RTX 50-series (either the 5060 or 5070), it's the thinnest-ever Razer laptop of this size. There's also a new 5060 option for the larger Razer Blade 16.

• Razer unveils new Blade 14 laptop with Nvidia RTX 50 series GPUs and 3K 120Hz OLED display

Ascent GX10 special edition?

The Asus Ascent GX10 costs around $2,999 for the privilege of Nvidia GB10 packed into a tiny form factor. How much the markup is on this one is anyone's guess...

InWin celebrates 40 years with... this...

InWin is celebrating 40 years with this insane ChronoMancy case. It looks a bit like a prosthetic leg, is over 1 meter tall, and opens up like Iron Man's suit when you wave a magic wand at it. Standard...

• InWin celebrates 40 years with the ChronoMancy — futuristic 1.1m case opens with the wave of a wand

Unlimited poweeeeeeeer

The new Asus Pro Workstation is a 3000W power supply capable of powering four Nvidia GeForce RTX 5090 cards by itself. It's so powerful you can even plug it into a standard U.S. outlet...

• Asus introduces 3000-watt PSU — enough capacity to power 4 RTX 5090s

Some colorful cases

Hyte's 2025 offering is a new X50 computer case that stands out thanks to its loud, vibrant colorway and design language reminiscent of a Smeg fridge. Check out the full details...

• Hyte’s new X50 PC case comes with a rounded aesthetic, high-performance mesh, and fun colors

Cherry's next generation switch

Alongside three others, Cherry has unveiled its brand new IK inductive switch, using patented inductive sensing technology it claims yields no mechanical wear and 50% less power consumption than magnetic switches.

• Cherry unveils next-generation keyboard switches with inductive sensing technology — claims no mechanical wear and 50% power reduction

MSI drops some insane gaming laptop artwork:

NZXT's new cases

NZXT has revealed not one but two stunning new cases, the H9 Flow and the H3 Flow. The former is a dual-chamber chassis with built-in fans and a controller hub, while the H3 is a Micro-ATX case. Despite this, it still features capacity for 10 fans!

• NZXT goes big and small at Computex with the H9 Flow and H3 Flow cases

AMD up next

Keeping on top of time zones during Computex is always a challenge - next on the agenda is AMD, who will host their Computex livestream and keynote tonight/tomorrow. It kicks off at 11 am UTC+8 on May 21, or 11 pm ET on May 20 if you're stateside. You can watch along over on YouTube!

Cooler Master's new panoramic case

The new Cooler Master MasterFrame 360 Panoramic is more fish tank than PC case, with a three-sided glass design that gives you unparalleled viewing of your internal hardware. There's also a new budget version of the QUBE 500, and more...

• Cooler Master unveils new pre-built PC with a 360 x 360mm radiator, new QUBE 500, and more

Turn any device into a Stream Deck...

One definite sleeper announcement from Computex 2025 is Elgato's new Virtual Stream Deck app, which lets you turn any device into a Stream Deck...

• Elgato now lets you turn any device you want into a Stream Deck

Corsair Air 5400

New from Corsair, the Air 5400 is the company's first triple-chamber design that can accomodate up to 360mm AIO cooling solutions, dumping the heat from the CPU directly out of the case.

• Corsair’s Air 5400 features a triple-chamber design for high-performance cooling

Phison's new controller could take the SSD speed crown

Earlier this week, we reported about the Crucial T710 SSD, which uses an SMI SM2508 SSD controller and boasts 2.2 million and 2.3 million read and write IOPS respectively. However, Phison seems ready to power drives which could close the T710 out of the water, thanks to its E28 controller.

We just reported that the Phison E28 controller promises 3 million read IOPS and 2.6 million write IOPS. That's along with 14.8 GB/s and 14 GB/s sequential reads and writes.

The controller is made using TSMC's 6nm process and it supports up to 32GB of TLC NAND. The E28 also boasts an eight channel layout that runs at 4200 MT/s and support for AES-256, TCG Opal and Pyrite encryption.

We visited Phison at Computex 2025 and grabbed a picture of a test system running CrystalDiskMark. In the pic above, you can see that the sample drive on display returned a 14,942 MB/s sequential read and a 14,149 MB/s write.

TeamGroup shows off thermoelectric SSD cooler

As we talked about in our article on TeamGroup's new Computex offerings, the company is showing a new SSD cooler that uses Peltier technology aka thermoelectric cooling. The company says that its AI-Flow X cooler will offer better cooling thanks to both this technology and to AI.

This looks very promising, but thermoelectric cooling has been known to have some drawbacks, such as generating heat. We'll have to see how this implementation fares.

Thermaltake embraces wood-accented cases

At Computex, Thermaltake is showing off its latest cases, which have Nordic, wood-grain accents. You could almost say that it's like going to Ikea, but hopefully with much easier building.

The new designs are available on several case lines, including the Tower 600, TR100, View 380/ 380 XL, View 270 and View 170 lines. The wood accents are either in light or dark wood.

No word yet on exact pricing or availability.

Adata courts enterprise customers with new Trusta brand

Adata is known for its SSDs and RAM, particularly under the XPG gaming sub-brand. Now the company is launching a new sub-brand aimed at enterprise customers.

Trusta (we guess they want you to trust it) will launch with two SSD lines: the T7 and the T5. We covered these in greater detail in our article about Trusta.

The T7P5, Trusta's flagship SSD, boasts sequential read and write speeds of 13,500 and 10,400 MB/s and uses either a U.2 interface or connects via E3.S or E1.S, all enterprise standards.

The T5 series has the T5P4B, T5S3B and T5S3 models. These connect weither via PCIe Gen 4 M.2 or 2.5-ich SATA connections.

AMD Keynote Underway and We're Blogging it

AMD's Jack Huynh, SVP and GM of Computing and Graphics, is delivering the company's Computex keynote. He started his presentation by talking about gaming and FSR. We're blogging the whole event at a separate AMD Computex live blog.

Good morning!

Day 2 is well underway here in Taipei and we have got a packed schedule to bring you. Stephen here taking you through the next eight hours, but first, a look at some of the things you may have missed overnight...

While you were sleeping:

The highlight overnight was the AMD keynote. The company unveiled its new Radeon RX 9060 XT and Ryzen Threadripper 9000, as well as the new Radeon AI Pro R9700, a PCIe 5.0 GPU for workstations and pro users.

• AMD launches Radeon AI Pro R9700 to challenge Nvidia's AI market dominance

The new RX 9060 XT launches on June 5, priced at $299, priced squarely in the firing line of the Nvidia GeForce RTX 5060 which launched earlier this week.

• AMD Radeon RX 9060 XT launches on June 5, starting at $299

The AMD livestream broke before the keynote finished, but you can catch up on all of our coverage up to that point as it happened.

• AMD Computex 2025 Keynote

A display on your memory module?

A new innovation from V-Color adds a programmable LCD screen to its DDR5 DIMM modules. According to V-Color, the screen can be used to display information like capacity, speed bin, temperature, and voltage, all controlled through the company's app. The screen is on the side, so there are some obvious limitations, including how much capacity the format supports, but it still tops out at 48GB and also features programmable RGB LEDs.

• V-Color puts displays on memory modules

Another Jensen Huang signature...

The Nvidia CEO dropped by and added his mark to the flagship ZOTAC Gaming GeForce RTX 50 Series on display:

Zotac's low-profile RTX 5060

New from Zotac at Computex is this low-profile RTX 5060. They carry the same GPU and VRAM as the full-sized boards, but offer only three display outputs and a neat single-fan setup.

• Zotac preps low-profile GeForce RTX 5060, Mini-ITX RTX 5060

113 GB/s speeds

We got a demo of Phison's Apex RAID setup, and it did not disappoint. Using 32 new PCIe Gen 5 SSDs in a RAID configuration, they clocked read and write speeds of 113.6 GB/s and 104.6 GB/s, respectively...

• Phison's Apex RAID demo showed us blistering 113 GB/s speeds in Computex demo

I spent way too much money on Guai Guai merch at the Computex store

Every trade show seems to have its own shop of overpriced merch. I’ve seen them at CES, GTC, IFA, and elsewhere, and never really been tempted to buy anything – until today. When I arrived at the Nangan Convention Center this morning, a half hour before the trade show opened to press, I wandered down the narrow entrance area, looking for the giant inflatable Guai Guai bag that’s typically there every year.

What I found was not only the big bag advertising the tech-protecting snacks, but a whole table of Guai Guai-themed merchandise. And I knew instantly that I couldn’t walk away without buying something – or, more likely, some things.

But the shop wasn’t open yet, so a couple of hours later, when I had a half hour between meetings, I returned and snapped up a green glass coffee mug, two omamori magnets (the actual omamoris were sadly already sold out), and a small travel bag. At checkout, I was also given a bag of Computex 2025 Guai Guai and a foldable fan as free gifts with my purchase.

Was it the most sensible 2,644 NTD I’ve ever spent? Probably not. But I knew if walked away from this very specific trade show swag, that I would regret it. And hey, who couldn’t use something else in their lives these days that “keeps everything alright?”

If I make it back to Computex next year, I’ll consider that a success for my lucky Guai Guai Computex swag. But if I am here again in a year (Computex 2026 is scheduled to run from June 2-5), maybe I’ll skip the Computex shop for the sake of my wallet.

–Matt Safford

More Jensen autographs...

Add another Jensen Huang autograph to the roster!

Catch up on AMD

Missed the AMD Keynote at Computex? Don't worry, everyone did, because the livestream broke. Here's a great way to catch up:

New from Colorful

A G-Helmet PC case, RTX 50-Series laptops, and more, Colorful unveiled some of the most eye-catching tech of Computex 2025...

• Colorful unveils new RTX 50-Series laptops, wild G-Helmet PC case, and more at Computex

The latest from be quiet!

be quiet! showed off the latest it has to offer including new keyboards, coolers, and PC cases. There are awesome new wooden bases for the 900 series, and an upgrade to the Pure Loop 3.

• be quiet! shows off new keyboards, coolers, and PC cases at Computex 2025

Lian Li embraces tempered glass

A new range of cases and more from Lian Li reveal that the company is embracing tempered glass on its front panels, eschewing the mesh that has served it well in previous years.

We got a look at the new Lancool 4, Lancool 217 INF, O11D Mini V2, DAN Case B4, Vector V100, and Vector V200 cases, along with the HydroShift III AIO.

• Lian Li is replacing mesh front panels with tempered glass on its new Lancool cases

Check out Noctua's thermosiphon cooler

Many of us use AIO (All-in-One) coolers that have a pump on top of the CPU that circulates coolant through a radiator where a fan blows the heat away. At Computex, Noctua is showing off a different kind of AIO, one without a pump at all.

Noctua's protoype thermosiphon cooler has liquid on top of the CPU where the heat from the CPU causes the coolant to boil. When the coolant turns into a gas it naturally moves through the pump up to the radiator where it is cooled and turns back into a liquid again.

Once it's a liquid again, the coolant flows downward back to the water block on top of the CPU and the cycle continues. Noctua is demonstrating this with a 360mm radiator.

So what's the point? By eliminating the pump, you cut the noise. Is the noise from your AIO's pump significant? I guess it depends on the product and how sensitive you are to noise and how much other noise there is in your system. Even the thermosiphon cooler still needs fans (3x 120mm fans actually).

Finally, a real solution to the melting cables problem

The next-gen of Seasonic Prime power supplies will have a feature that deals with the problem of melting 12VHPWR connectors. As you may know, many people with RTX 40 and 50 series cards have had problems with melting connectors because their 12VHPWR connectors weren't plugged in properly. Then the GPU calls for an unbalanced power load and the cables melt and disaster ensues.

At Computex, Seasonic showed a prototype PSU with a set of sensors that alerts PC users of a malfunction if there's an abnormal voltage output. There will be an external device that connects to the PSU and shows this alert. The PSU will also power down to prevent melting. The PSUs with this tech, unfortunately, aren't due out until 2026.

Thermaltake shows off Minecraft-themed AIO cooler

Look at this! It's almost as good as having a Chicken Jockey ride on top of your CPU.

Thermaltake has a Minecraft-themed, 360mm AIO cooler on display at its booth and it's called the Minecube 360 ARGB. The cooler has four, 3.95-inch displays surrounding the pump. In the display, each of these had a Minecraft scene, but it seems like you could put any image you want on there.

The 360mm radiator has three Thermaltake SWAFAN EX12 ARGB fans on it that use magnetic quick connections and daisy-chain together. The entire thing is controlled by TT RGB software.

We don't have more details about the Minecube so we don't know the pricing or availability. We also don't know if it comes with any addition Minecraft-themed parts. One of the two units on display had some plastic Minecraft trees and blocks on the case, but we don't know if they come with the cooler.

Thermaltake shows off cool case mods

As usual, Thermaltake's booth was filled with case mods from some of the leading modders. The company hosts an invitational where artists from around the world turn its cases into all kinds of neat things. This year, the Black Myth Wukong case was the most impressive.

Here's what we saw.

Good morning and welcome to Thursday live from Taipei, it's a little after five local time and we've been pacing the trade floor. Stephen here for the next eight hours to take you through everything we've find. But first, we'll catch you up on what you may have missed overnight.

The return of an icon

MSI has unveiled plenty of new incredible tech at Computex, but the pick of the bunch might be the return of its iconic TwinFrozer and Cyclone cooling platforms, which have been deployed on a new RTX 5060 Ti and RTX 5060, respectively.

• MSI's RTX 5060 Ti TwinFrozer Retro and RTX 5070 Cyclone graphics cards go heavy on nostalgia

AMD FSR Redstone

New technology from AMD brings a major update to FidelityFX Super Resolution (FSR). Dubbed Redstone, it has new features it hopes to rival Nvidia's DLSS using three new features: neural radiance caching, machine learning ray regeneration, and machine learning frame generation.

• AMD's FSR Redstone uses machine learning to achieve parity with Nvidia DLSS

A new solution to melting connectors

Seasonic has unveiled new Prime power supplies that seek to solve overheating and melting power connectors by using sensors, a microcontroller, and firmware to keep on top of things, letting you monitor voltage output and current, as well as shutting down the system automatically if things get out of hand.

• Seasonic’s next-generation Prime PSUs to will try to stop connectors from melting

Old dog, new Tryx

Tryx's new Arcvision case features an embedded, curved display in the lower-left corner. The panoramic illusion is some of the most impressive stuff we've seen in case innovation at this year's event!

• Tryx's new PC case has an embedded curved display

Zalman goes with the grain

Seems like everyone is adding wood to their PC components these days, and the latest manufacturer to jump on the trend is Zalman with its new ATX and micro-ATX cases.

• Zalman shows off woodgrain ATX and Micro-ATX cases

The most egregious branding ever

Thermal Grizzly has unveiled a new bench table made in partnership with overclocking royalty der8auer. The "der8enchtable" is a modular, user-friendly benchtable is designed to facilitate fast and efficient PC hardware testing. Maybe we should get one of those...

• Thermal Grizzly’s open-air der8enchtable is designed for dedicated PC tinkerers

A $50,000 cooling solution

Enermax's immersion-cooled workstation can support four Nvidia RTX 5090s and up to 3,300 watts of power, using two-phase liquid immersion to keep temperatures under control. It looks incredible and surely performs, but the privilege will cost you $50,000 before you add any components.

• This $50,000 immersion-cooled workstation can support four Nvidia RTX 5090s

Zotac Zone 2 coming... soon?

Zotac has taken the covers off its new Zone 2 handheld, replete with a 7-inch AMOLED display and AMD Ryzen AI HX 370 APU. While we expect this to be the second iteration of its Zone handheld, it's officially a prototype at this stage and there's no pricing or launch info.

• Zotac Zone 2 demoed with Manjaro Linux and an AMOLED panel — 12-core Zen 5 CPU and 32GB RAM under the hood

HighPoint’s RocketStor 6542AW offers nearly a petabyte of external storage using eight 122TB SSDs

How does nearly a petabyte of storage sound to you? Although I’m probably going to sound like the 640K remark often (and probably mistakenly) associated with Bill Gates, I don’t think I could ever come close to filling the 976GB of storage that’s possible with the HighPoint RocketStor 6542AW.

Even though the RocketStor 6542AW is relatively compact (measuring 9.25 x 927 x 4.84 inches), it is home to eight 2.5-inch NVMe bays with hot-swap support. If you’re considering throwing in garden variety M.2 SSDs, slow your roll; it only supports U.2 and U.3 SSDs. To demonstrate the full power of the RocketStor 6542AW, Highpoint installed Solidigm D5-P5336 122TB PCIe 4.0 SSDs. Each SSD is rated for 7,400 MB/s reads and 3,200 MB/s writes. Although the external storage has a CDFP port that offers sustained transfer rates of up to 32 GB/s, the D5-P5336 SSDs are limited to “just” 28 GB/s.

If you want a RocketStor 6542AW, the price for the external storage solution is $1,799. However, if you max out at 976GB, you’ll need to add eight Solidigm D5-P5336 priced at roughly $16,000 each.

• This 976TB external storage solution with 28 GB/s transfer speeds likely costs over $130,000

Lian Li shows off power supplies with rotating power outlet

Worried about where to mount the power supply in your case? Lian Li's new RS series has you covered. The power supplies have outlets that can rotate, allowing you to put them in from either the back or the side.

These power supplies also have dual 24-in and 8-pin connectors on the front and left so you can choose to plug in from either location. There's also a mount below the rear connector set (CPU, PCIe, SATA connectors) that can hold a bundled USB hub.

The hub has both USB and fan controller ports so you can plug internal devices and coolers into it.

Good morning and welcome to the final day of Computex 2025 live from Taipei. Things are winding down here, so stay tuned for some more floor shots, recaps, and our awards.

Liquid-cooled RTX 50 series from Maxsun

Maxsun has unveiled one of its wildest graphics card yet, a concept RTX 50-series with liquid cooling and a full RGB LED shroud.

• Maxsun shows off liquid-cooled RTX 50 series GPU covered in RGB lighting

3,000W power supplies

3,000 W power supplies are taking over Computex. First we saw a 3,000 Asus PSU earlier in the week. Then we saw two from Super Flower.

• Super Flower shows off not one but two 3000W PSUs at Computex 2025

More power supplies

If 3,000W is a little over your requirements, how about this Lian Li offering with a rotatable power outlet for maximum flexibility...

• Lian Li flexes new PSU with rotatable power outlet at Computex 2025

The Best of Computex 2025

Computex is in the books, and it's the moment you've all been waiting for. Let's take a look at our winners in the Tom's Hardware Best of Computex 2025 Awards. Starting with AMD...

AMD Ryzen Threadripper 9000 Series

The new AMD Ryzen Threadripper 9000 Series is here. The flagship Ryzen 9 9995WX boasts 96 cores and 192 threads, with peak boost clocks of 5.4GHz and 300W TDP.

• AMD Announces Threadripper HEDT and Pro 9000-Series CPUs: 96 cores and 192 threads for Desktops and Workstations

AMD Radeon RX 9060 XT

The new AMD RX 9060 XT starts at $299 for the 8GB version, or $349 for the 16GB model. It has Navi 44 architecture and even beats the RX 9070 in boost clock speed (3,130 MHz). Could this be the value GPU of 2025 we've been waiting for?

• AMD Radeon RX 9060 XT launches on June 5, starting at $299

Phison E28 SSD controller

Phison's new E28 SSD controller delivers big efficiency gains thanks to a 6nm process note, but still delivers 14.8 GB/s of sequential read/write performance and 2.5 / 3.0 million random read/write IOPS. A wave of E28-powered SSDs are expected later this year.

• Phison's E28 controller's 14.8 GB/s, 3,000K IOPS, and 7W power draw could make it the new king of PCIe 5.0 performance

Asus ProArt RTX 5080

Asus wins for this creative take on the RTX 5080, accented with wood in a way that makes the card really stand out. After a week filled with wooden cases, a wooden GPU housing is a breath of fresh air.

• Asus RTX 5080 ProArt comes with a wood grain finish and M.2 slot option

Crucial T710 SSD

The new T710 promises 28 percent read speed increases and 42 percent faster write speeds over the T705, the best SSD for speeds right now.

• Crucial announces T710 SSD with 14.9 GB/s of performance, X10 portable SSD up to 8TB

Predator Triton 14 AI

The Triton 14 AI weighs 3.5 pounds and features a 14.5-inch 2880 x 1800 OLED screen. Under the hood there's a Lunar Lake Core Ultra 9 288V CPU with RTX 5070 graphics.

• Acer has a new pair of 14.5-inch laptops for gaming on the go

Corsair Air 5400

Corsair's Air 5400 case is an eye-catching design with a triple-chamber layout that dumps CPU heat directly out of the case via a 360mm AIO radiator.

• Corsair’s Air 5400 features a triple-chamber design for high-performance cooling

SilverStone FLP02

A highlight of the whole show and massive hit with our readers, SilverStone's FLP02 is a throwback case that even has faux floppy drives on the front.

• SilverStone reveals late-80s style tower PC case — proudly beige but thoroughly modern inside

Seasonic Prime Power Supplies

Seasonic's Prime Power Supplies feature sensors to detect voltage problems and even shut down your system to prevent damage, overheating, and dreaded melting connectors.

• Seasonic’s next-generation Prime PSUs to will try to stop connectors from melting

Asus ROG Falcata

The ROG Falcata is a split layout gaming keyboard with HFX V2 magnetic switches, and our limited hands on time had us massively intrigued.

• Asus ROG Falcata brings split layout and magnetic switches to competitive gaming

Cooler Master Elite case line

Cooler Master's case line-up stands out so much we have the whole lot an award. Each should cost less than $100, even the eye-catching curved glass models.

• Cooler Master plans to launch a curved-glass case for around $70 – at least outside of the U.S.

Lian Li V200

Lian Li's $110 case has two glass panels, touch controls, and a massive 8.8-inch screen embedded in the bottom chamber.

• Lian Li is replacing mesh front panels with tempered glass on its new Lancool cases

MSI X50 Gaming Monitor

MSI's X50 Gaming Monitor is a QD-OLED panel with a 500Hz refresh rate and 1440p resolution, and even has an AI sensor than can power down the panel when it senses you've walked off.

• MSI’s new 500 Hz QD-OLED monitor leverages AI tech to save it from burn-in

Asus ROG Strix Ace XG248QSG Monitor

Another incredible monitor we saw this year is the 610 Hz overclocked Asus ROG Strix Ace XG248QSG, sporting 1080p resolution.

• Asus debuts 24-inch 610 Hz Full HD gaming monitor with a Super TN panel

Thermaltake MineCube 360 Ultra ARGB AIO

Thermaltake's MineCube 360 is a 360mm AIO cooler with a 720 x 720 resolution screen that will show you delightful Minecraft screens.

V-Color Xfinity Manta DDR5 RAM

Our favorite RAM module from Computex is this V-Color Xfinity Manta DDR5 RAM that features a full-color LCD screen you can use to show stats like voltages, clock speeds, and more.

• V-Color puts displays on memory modules

Mark your calendars for Computex 2026

Computex 2025 is coming to a close. Its organizers have announced that next year's show will run from June 2 - June 5, 2026.

This year's show started on May 20, a bit earlier than usual. Next year, it's returning to a more standard timeframe.

That gives you about a year to come up with your Computex 2026 bingo card. And for our intrepid editors on the ground to recover from the jet lag.

— Andrew E. Freedman

AIO screens get even more complicated

Over at Antec's booth, we saw the Vortex View AIO cooler, which features a 360 mm radiator and a 5-inch display. While screens have been popping up on a lot of cooling pumps, this one stands out; the large screen is connected to the pump via a ball joint, allowing you to rotate it and angle it exactly how you want. It even gives you the option to place it either horizontally or vertically.

The cooler works with both Intel and AMD processors, including LGA 1851, LGA 1700, AM4, and AM5 sockets.

• Hands-on with the Antec Vortex View — a wild AIO cooler with a screen that rotates a full 360 degrees

Next on the schedule: Memorial Day

With Computex 2025 wrapped up, we turn our attention to Memorial Day sales. It's a great time to score some new hardware at bargain prices, and the deals are already coming thick and fast. Here are some of the highlights so far!

• AMD Ryzen 9950X3D: Now $699 (normally not available)
• Samsung 990 Pro (4TB): Now $309
• Alienware RTX 5090 Desktop: Now $4899
• Newegg: Up to 46% off SSDs
• Amazon: Save up to 40% on tech deals
• Best Buy: Up to $300 off laptops, monitors, & more
• Dell: Up to $700 off gaming PCs
• Lenovo: Save up to 59% on Lenovo laptops
• HP: Save over $50% on HP, HyperX, Omen, and Victus in the Memorial Day sale
• SK hynix Platinum P41 2TB PCIe 4.0 SSD: now $124 at Newegg (was $156)
• AMD Ryzen 5 9600X Processor: now $198 at Newegg (was $279)
• Samsung 990 Pro 2TB SSD: now $169 at Amazon (was $249)
• Intel Core Ultra 7 Processor 265K: now $269 at Amazon (was $404)
• Dell S3222DGM, 32-inch 2K 165 Hz Monitor: now $259 at Best Buy (was $329)
• MacBook Air 13 (2025, M4 chip): 16GB / 256GB: was $999, now $899 at Amazon
• MacBook Air 13 (M4, 2025): 16GB / 512GB: was $1199, now $1099 at Amazon

While Intel is gearing up to reveal new Battlemage products at Computex in a few days, X user Haze has shared an image of an Intel ARCade machine featuring a last-generation Alchemist A7 series GPU. Often seen as Intel marketing material for major e-sports events, this machine was reportedly found out of commission and unused at an unnamed Intel campus.

Intel was enthusiastic in the months leading up to the Alchemist launch, as evident in its marketing push for the product. This ranged from custom 60-foot air-conditioned gaming trucks to smaller Arcade machines, like the one we're seeing today. Following the delays associated with Alchemist and inevitable teething problems, Intel has maintained a relatively low profile with Arc since then. The desktop Battlemage launch is proof of this.

The ARCade is an Intel-powered arcade-style machine that has been a recurring presence at events like DreamHack. The controller layout depicts a two-player configuration for fighting games like Street Fighter and Tekken. A quick look inside reveals a GPU at its core, which carries a strong visual resemblance to Intel's Limited Edition models from the Alchemist range, likely the A770. The GPU is presumably housed in an Intel NUC 12 Extreme, but any guess is as good as ours.

Currently, Intel's Foundry division loses billions every quarter as it invests heavily in new process technologies and production capacity. However, the company hopes that the Intel Foundry unit will break even sometime in 2027, which will coincide with the rollout out Intel's 14A manufacturing technology and production start on 18A-P node. 

Intel this week reaffirmed that the first product made on its 18A (1.8nm-class) fabrication process, the client PC processor (codenamed Panther Lake), will hit the market late this year and will ramp next year. The manufacturing technology will also be adopted for Xeon 'Clearwater Forest' and some third-party products, but from Intel's Foundry business perspective, 18A is will be a proof-of-concept for external clients. If this production node is a success, more potential customers will adopt its successors, including 18A-P, and 14A (1.4nm-class). 

"I think we do need to see more external volume come from 14A versus versus 18A, said David Zinsner, chief financial officer of Intel, at the J.P. Morgan Global Technology, Media and Communications Conference. "We have […] a bunch of bunch of potential customers, and then we get test chips, and then some customers fall out in the test chips, and then there is a certain amount of customers that kind of hang in there. So, committed volume is not significant right now, for sure. But, you know, I think we have got to partly prove ourselves a little bit with our own product and eat our own dog food here, and then […] we start to see some engagement around customers." 

Zinsner admitted that if the company choses to use High-NA EUV lithography with its 14A process technology — as it plans to at the moment — its costs will go up initially. Intel hopes that advantages enabled by the new fab tools will outweigh those higher costs. 

Intel explained the rationale behind its High-NA EUV strategy at its Intel Foundry Direct 2025 conference this week. Despite persistent questions around cost-effectiveness, Intel has championed its use of the new High-NA EUV chipmaking tool with its forthcoming 14A process. However, Intel has not yet fully committed to using the new tool in production, but it has an alternative production flow of its 14A node that uses standard Low-NA EUV as a backup plan.

Intel has already received a second high-NA EUV tool, installed in its Oregon fab, and the company says the technology is progressing well. However, due to continuing development, the ~$400 million ASML Twinscan NXE:5000 High-NA EUV machines haven’t been used in a production environment yet, so Intel isn’t taking any risks.

“[..]The first one is, Intel still has the option to have either a Low-NA or a High-NA solution on our 14A technology, and its design-rule compatible, there will be no impact to the customers, depending on the path that we choose. Second, High-NA EUV is performing to the expectations, and we will introduce it at the right time," said Dr. Naga Chandrasekaran, EVP, CTOO & GM of Intel Foundry Technology and Manufacturing.

"We already have data on 18A as well as 14A that shows yield parity between our Low-NA-based solution and a High-NA-based solution. So, we are continuing to make progress on the technology front and ensuring that we have the right options available for us to make sure the solution we deliver to our customers has the lowest risk and the best reward in terms of the decisions we make,” Naga explained.

Intel will only use High-NA EUV on a small number of layers of the 14A node (the exact number isn’t known), while other machines of varying resolutions will be used for the other layers. That means the decision between the two machines will only impact a select portion of the manufacturing process, but Intel says using triple-patterning with a Low-NA EUV (more below) machine instead of High-NA produces the same results.

Because both techniques are design-rule compatible, Intel’s customers won’t have to change their designs regardless of the company’s decision on the final manufacturing flow, either with or without High-NA EUV, which helps defray concerns that customers might have with Intel embracing an as-yet unproven production technology.

Additionally, Intel’s claim that both production flows offer the same yields signals that there won’t be severe time-to-market repercussions if High-NA EUV development hits a snag, or if Intel chooses not to deploy it due to economics. Employing multipatterning often reduces yields, but Intel's claim of yield parity speaks to the advances of modern multipatterning, particularly in the field of overlay technology.

Most of the public-facing conversations about High-NA EUV have centered around cost, there's plenty of industry speculation that High-NA isn't as cost-effective as multi-patterning with Low-NA EUV, but there are still numerous technological hurdles to bringing the machines into production. Most of the challenges center around the universe of complementary technologies required to make High-NA viable, like resists, photomasks, and computational lithography, among others, which have to be optimized for the new machines.

However, Intel adopted ASML's machine first to get a leg up on the competition, and it has already produced 30,000 wafers using High-NA lithography during the development phase. As a representative explained later in the event, Intel still sees significant cost savings due to eliminating around 40 process steps.

“Finally, I want to talk about High-NA EUV. Why do we do this? It's very simple; It's lower cost. In the middle picture, you see a pattern that has been generated by a single pass High-NA EUV and a pitch that is comparable to the pitch that we need for 14A. The right-hand side shows a very similar pattern generated with a traditional approach, where we use three EUV exposures [triple patterning], and overall about 40 process steps to generate this pattern."

"So, overall, we see much shorter, simpler flow, and this is the type of application where we use High-NA in 14A, which reduces the cost compared to the multi-pass 0.33 NA EUV [Low-NA]. Additionally, this provides the option to de-populate the metal layers and get additional performance enhancement.”

Intel didn't specify whether or not its comparisons are based on a full-reticle-sized print. High-NA can only print half of a reticle at a time, requiring two prints to create one reticle-sized processor and relying upon stitching to bring the two prints together into a single cohesive unit. In contrast, die that are equal to or smaller than a half-reticle size will only require one print with High-NA EUV. In contrast, Low-NA EUV machines can process a full reticle-sized die in a single print.

Thoughts

Intel has plenty of scar tissue from its 10nm node failures that ultimately ended in the company losing its chipmaking lead over TSMC, and it chalks the 10nm issues up to making too many big bets on new manufacturing techniques and technologies at once.

The decision to develop an alternative Low-NA production flow is designed to prevent repeating those past mistakes, and Intel has also de-risked other types of advances by developing alternative solutions in the past.

For instance, the company developed its new backside power delivery system with the 18A node, an industry first, while simultaneously developing gate-all-around (GAA) transistors, a first for Intel. To ensure a backup plan, the company employed a more robust de-risking strategy with its 20A process that included developing an internal-only trial process node without gate-all-around transistors. However, development went well with both GAA and backside power delivery, so Intel pushed forward with the full version of the node.

Intel rival TSMC has confirmed it will not use High-NA with its competing A14 node, and it hasn't indicated when it will employ the new High-NA EUV tool in volume production. Intel had originally planned to use High-NA with its 18A process, which arrives before the 14A node. Intel later changed those plans, saying that the process node's unexpectedly fast development meant the machines wouldn't be ready in time.

Intel made a slew of announcements at its Intel Foundry Direct 2025 event in San Jose, California, and finally shared performance metrics for its upcoming 14A process node, slated for risk production in 2027, touting headline improvements of up to a 35% reduction in power consumption. Intel also teased its new Turbo Cell technology, a customizable design approach geared to provide maximum CPU frequency and to boost performance for critical speed paths in GPUs.

The 14A and 14A-E nodes are the next generation after the company's 18A node. Intel says 14A will deliver a 15 to 20% performance-per-watt increase over 18A, which can be leveraged as either higher clock speeds or 25-35% lower power consumption at the same performance, depending upon chip-specific tuning. Much of this improvement is due to Intel's new direct-contact backside power delivery network, which the company has dubbed PowerDirect (more here).

Intel has also sprinkled in other new features to improve the node, such as a wider threshold voltage (Vt) range that enables a more expansive voltage/frequency curve.

The 14A nodes also deliver a 1.3X increase in transistor density over the 18A node. Intel has also revamped its RibbonFET transistors for 14A, now known as 'RibbonFET 2.' Intel hasn't shared details about the new generation of RibbonFET, but the general design provides improved transistor density and faster transistor switching by utilizing four stacked nanosheets surrounded entirely by the gate (you can see the cross-section with nmos and pmos transistors above).

Turbo Cells and Critical Paths

Intel's new Turbo Cells are a standout feature, but they are a bit complicated. Turbo Cells can be used for a multitude of purposes, but Intel specifically calls out that they will be utilized in the critical paths of the CPU and GPU, often referred to as speed paths. And for good reason.

Timing paths within a processor are routes that a signal travels along, through wires and logic gates, during normal operation. However, delays to those signals can interrupt the clock timing of the processor. The critical paths are those that have the longest total delay.

Because processors operate based on clock signals, the slowest critical path dictates the highest possible frequency limit of the entire chip, serving as a bottleneck to overall performance (there are distinctions here for the various clock domains, but the general principle holds true). Chip designers often use higher-speed transistors in these areas of a chip, but this comes at the cost of reduced transistor density and increased power consumption, as faster transistors are leakier and thus consume more power. The new Turbo Cells provide chip architects with a more refined tool to mitigate critical paths.

The 14A node features three distinct standard cell libraries, which use process node-specific building blocks (standard cells constructed with transistors) of pre-designed logic gates and circuit elements. Designers use electronic design automation (EDA) software tools to utilize the libraries during the design flow and generally lay them out in rows.

Intel's 14A has three different libraries: the 'tall' library has transistor cells optimized for high frequency (low density, leaky), the 'mid-size' library is optimized for performance per watt, and the 'short' library is focused on density for area- and power-sensitive applications. Intel has not shared density information for the various libraries yet.

Short libraries are used heavily in CPUs and GPUs to pack in the most transistors possible while keeping power density at manageable levels. That's where Intel's new Turbo Cells step in.

Turbo Cells are designed to enhance performance by increasing the transistor drive current for short libraries when they're used to create double-height libraries (the height of two standard rows), all while maintaining a high-density arrangement for optimal area efficiency.

The above graphic represents four different arrangements of nmos and pmos ribbons/nanosheets (pink and green) with varying widths and configurations to optimize drive current for different scenarios. The width of the ribbons can be adjusted, or they can be merged independently to create very wide ribbons for maximum drive current delivery. The various options provide designers with a robust toolkit for tailored implementations.

Intel says Turbo Cells can ultimately be used to mix in faster and less power-efficient cells with the power-efficient cells within the same design block to create the right balance of power, performance, and area (PPA) for any given use case.

Critical paths are the ultimate bottleneck; think of them as the weakest link in the chain. Intel's new Turbo Cells are designed to boost overall processor performance by speeding up those paths, but without making the compromises often used to solve the critical path problem. We'll have to wait until 2027 to see how that pans out.

Intel's new CEO Lip Bu-Tan took to the stage at the company's Intel Foundry Direct 2025 event here in San Jose, California, to outline the company's progress on its foundry initiative. Tan announced that the company is now engaging lead customers for its upcoming 14A process node (1.4nm equivalent), the follow-on generation of its 18A process node. Intel already has several customers with plans to tape out 14A test chips, which now come with an enhanced version of the company's backside power delivery technology dubbed PowerDirect. Tan also revealed that the company's crucial 18A node is now in risk production with volume manufacturing on schedule for later this year.

Intel also revealed that its new 18A-P extension, a high-performance variant of the 18A node, is now running through the fab with early wafers. Additionally, the company is developing a new 18A-PT variant that supports Foveros Direct 3D with hybrid bonding interconnects, enabling the company to stack dies vertically on top of its most advanced leading-edge node.

The Foveros Direct 3D technology is a key development because it provides a capability that rival TSMC already uses in production, most famously in AMD's 3D V-Cache products. In fact, Intel's implementation matches TSMC's offering in critical interconnect density measurements.

On the mature-node side of the operation, Intel Foundry has its first production 16nm tapeout in the fab now, and the company is also now engaging customers for the 12nm node it is developing in partnership with UMC.

Perhaps the most important developments at the show revolve around Intel's continued expansion with EDA and intellectual property (IP) partners that provide the critical tools and IP blocks that enable its customers to develop new designs with industry-standard design flows and tools. The company has also expanded its Intel Foundry Accelerator Alliance program to include the Chiplet Alliance and Value Chain Alliance programs.

Intel Foundry's progress comes during turbulent times in the semiconductor industry as geopolitical divisions threaten to fracture the global chip supply chain. Intel is currently the only US-based domestic supplier of leading-edge process node technology and advanced packaging capacity, a key advantage as tensions between China and TSMC continue to escalate. Despite TSMC's expansion of production in the US, a recent law passed by Taiwan now prevents the company from producing its most cutting-edge tech in the United States, leaving Intel as the only domestic foundry with both leading-edge chip production and R&D.

Naga Chandrasekaran, the Chief Technology and Operations Officer of Intel Foundry, and Kevin O’Buckley, the General Manager of Foundry Services, are also slated to deliver keynotes during the event, providing more details about the technology and roadmaps. We will update this article with additional information as it becomes available, but we have plenty to share to get started. Let's take a closer look at Intel's progress.

Intel 14A Process Node

Intel 14A Process Node

Intel's 14A, the next generation after 18A, is already in the works and scheduled for risk production in 2027. If all goes to plan, 14A will be the industry's first node to employ High-NA EUV lithography. TSMC's competing A14 (1.4nm-class) node is expected to arrive in 2028, but the Taiwanese company will not utilize High-NA for production.

Intel has already shared early versions of the Process Design Kit (PDK), a set of data, documentation, and design rules that enables the design and validation of a processor design, with its lead 14A customers. Intel states that multiple customers have already indicated their intention to build chips using the 14A process node.

Intel's 14A will have a second-generation version of its PowerVia backside power delivery technology. The new PowerDirect implementation is a more advanced and complex scheme that delivers power directly to each transistor's source and drain through specialized contacts, which minimizes resistance and maximizes power efficiency. This is a more direct and efficient connection than Intel's current PowerVia scheme, which connects to the contact level of the transistors with Nano TSVs.

TSMC's N2 node does not include backside power delivery; however, with A16, the company will employ a direct-contact backside power delivery network, dubbed Super Power Rail (SPR). A16 is essentially a derivative of the N2P node with SPR. The A16 node is expected to enter production in late 2026. TSMC's A14 will not leverage a backside power design methodology.

Intel's 18A-PT process node enables die stacking

Intel's 18A-PT process node enables die stacking

Intel's 18A node is the mainstream variant, but the company also has several 'line extensions' of the node, designated by different suffixes. These flavors of the underlying node are tailored for different use cases.

Intel has a new 18A variant up its sleeve; the new 18A-PT node that will provide the same performance and efficiency benefits as the performance-oriented 18A-P, but adds in Foveros Direct 3D hybrid bonding. This bump-less copper-to-copper bonding technique (meaning it doesn't use microbumps or solder to connect the two dies) fuses chips together with through-silicon vias (TSVs). Intel's implementation will employ a pitch of less than 5 microns, a distinct improvement over its initial goal of a 10um pitch by 2023, to fuse chiplets on top of the 18A-PT die. The pitch is a measurement of the center-to-center spacing between the interconnects, and lower values indicate higher density, which is better.

Notably, AMD uses TSMC's SoIC-X technology, a similar hybrid bonding approach, to fuse an L3 chiplet atop its X3D processors with a 9 micron bump pitch. TSMC's SOIC-X tech currently ranges from 4.5 to 9 microns, but the company has a 3-micron pitch offering on the roadmap for 2027. If productized effectively and on schedule, Intel's Foveros Direct 3D will dramatically improve its positioning against TSMC's packaging technology.

Intel's Clearwater Forest will be its first to use Foveros Direct 3D packaging, but the company hasn't disclosed the pitch for that specific product yet. Notably, TSVs are typically only included in the base die, and Clearwater Forest uses Intel 3-T for the base die with the Intel 18A compute dies stacked on top. Enabling TSVs for 18A will thus allow it to also have dies stacked atop, and SRAM cache is a logical use case.

Intel 18A process node updates

Intel 18A process node updates

As we reported last month, Intel's 18A (1.8 nm-equivalent) process node has entered risk production, marking the commencement of the first low-volume production runs of the node, with High Volume Manufacturing (HVM) scheduled for the end of the year. Intel did not specify which processors had begun production, but the timing generally aligns with expectations for its Panther Lake processors, which are expected to arrive at the end of the year. Intel's first 18A production will come from its Oregon fabs, but the company has already 'run the [18A] lot' through its Arizona fab, indicating it will soon begin production there as well.

The 18A node is the first in the industry to be productized with both a PowerVia backside power delivery network (BSPDN) and RibbonFET gate-all-around (GAA) transistors. PowerVia provides optimized power routing on the back of the chip to improve performance and transistor density. RibbonFET also offers better transistor density, along with faster transistor switching, in a smaller area through the use of four vertical nanosheets surrounded entirely by the gate.

The 18A node enters HVM in roughly the same timeframe as TSMC's competing 2nm N2 node. However, TSMC's N2 node does not come with a backside power delivery network, but it does have GAA technology with three vertical nanosheets. There have been some basic comparisons between the process nodes made based on presentations at a recent industry event. The general takeaway is that Intel's node is faster and lower-power than TSMC's, though TSMC retains the edge in density (and presumably cost). However, these distinctions could vary depending on the specific implementation in different chip designs.

Intel divulged today that it has wafers of its high-performance 18A-P node in the fab. This 18A variant features an optimized power and frequency curve, providing an 8% improvement in performance per watt. This can be leveraged as either higher clock speeds or lower power consumption at the same performance, depending upon chip-specific tuning.

The 18A-P node is design rule-compatible with the 18A node, easing the design process for customers. Intel is already collaborating with Electronic Design Automation (EDA) software vendors to enable broad support for industry-standard design tools, and it is also working with Intellectual Property (IP) designers to provide the necessary IP blocks, thereby simplifying implementation.

Mature Nodes: 16nm and 12nm continue advancing

Mature Nodes: 16nm and 12nm continue advancing

Intel Foundry not only addresses the leading edge of technology, but it is also working on several mature nodes. Intel's 16nm node, which is essentially a version of its 22FFL node that leverages industry standard design tools and PDKs, has a tapeout in the fab now.

Intel is also continuing its work with partner UMC to develop a 12nm node that will be produced in three of Intel's Arizona fabs beginning in 2027. In fact, Intel is currently engaging lead customer for this node. 12nm will be used primarily for mobile communication infrastructure and networking applications.

Takeaways, for now

Takeaways, for now

Intel canceled high volume manufacturing of the 20A node as a cost-cutting measure, but the company is now on the cusp of of production with with its18A node, marking a critical milestone as it looks to regain the manufacturing lead over TSMC. The addition of new line extensions, with the die-stacking-capable 18A-PT being a particularly strong advance, will help the company to further broaden its appeal to potential foundry customers.

The development of the company's 14A node is also well underway, signifying that the company is on track to providing a steady cadence of new nodes and features to the roadmap. We haven't yet heard any new details about Intel's plans for its 10A (1nm-class) process node yet, which is expected to begin development in 2027. Intel's press release also doesn't mention any new progress on its Intel 3 node, but we expect more details to emerge throughout the day.

Intel's event is focused heavily on displaying its broad portfolio of EDA, IP, and services driven by an ecosystem of indsutry stalwarts, like Synopsys and Cadence. The new Intel Foundry Chiplet Alliance is also an important development that will enable customers to mix-and-match chiplets into their design based upon interoperable and validated designs.

Intel's advanced packaging services are also of particular importance as they provide the fastest on-ramp to meaningful revenue generation. Intel did mention that it will make its 3D stacking Foveros implementation available to foundry customers, and noted a new partnership with Amkor. However, details are slight for now. We'll update this article as more information becomes available.

An update by Intel to the perfmon platform has added support for upcoming Panther Lake CPUs, listing their core architecture codenames and CPUID, via InstLatX64. This commit unofficially confirms that Panther Lake will employ Cougar Cove Performance (P) cores, while Darkmont will serve to power its Efficiency (E), and likely Low Power Efficiency (LPE) cores as well. Panther Lake is expected to launch later this year, succeeding current-generation Arrow Lake U/H offerings.

With Intel's flagship 18A in risk production, Panther Lake is scheduled for mass production later this year. Hence, it wouldn't be surprising if the bulk of Panther Lake arrives in Q1 next year, similar to how Meteor Lake rolled out. Make no mistake: Panther Lake isn't a successor to Lunar Lake, which was uniquely focused on efficiency as a one-off product, with on-package memory, limited TDP, and a power-optimized design. Current rumors indicate Panther Lake variants will sport up to 18 hybrid cores (6P+8E+4LPE) and 12 Xe cores, based on Intel's upcoming Celestial (Xe3) graphics architecture.

Intel positions Panther Lake as combining Arrow Lake's power and Lunar Lake's efficiency, but that's still a somewhat general claim. According to leaks, most Panther Lake systems will include traditional SODIMM/soldered memory, while some laptop designs might even support next-gen LPCAMM, combining fast and upgradeable RAM. Based on their TDP (rumored: up to 64W), Panther Lake chips are expected to power a wide range of devices, including entry-level laptops, handhelds, and gaming laptops. The company is even eying bringing this architecture to automobiles.

An Intel engineer has pushed an update to the lookup table for perfmon, adding Panther Lake as a supported architecture. Panther Lake has been marked with the "GenuineIntel-6-CC" identifier, assigning it to CPU Family 6, Model 204 (0xCC). In addition, the patch reports the Cougar Cove and Darkmont architectures for Panther Lake's Performance (P) and Efficiency (E) cores, respectively.

TSMC exposed the defect density (D0) of its N2 process technology relative to its predecessors at the same stage of development at its North American Technology Symposium this week. According to the company, the defect density is below that of N3, N5, and N7 manufacturing nodes. In addition, the slide published by ComputerBase reveals that N2 is two quarters away from mass production, which means that TSMC is on-track to start making 2nm-class chips in late Q4 2025, as expected.

Although TSMC's N2 is the company's first process technology to adopt gate-all-around (GAA) nanosheet transistors, the node has lower defect density than its predecessors at the same stage of development, two quarters before mass production (MP). The predecessors — N3/N3P, N5/N4, and N7/N6 — all relied on well-known FinFET transistors. So, despite being TSMC's first node using GAA nanosheet transistors, the N2 defect density is getting lower quicker (well, steeper) than that of its predecessors before the high volume manufacturing (HVM) milestone.

The chart plots defect density against time, spanning from three quarters before mass production through six quarters after MP. Across all nodes shown — N7/N6 (green), N5/N4 (violet), N3/N3P (red), and N2 (blue) — defect densities drop significantly as production ramps, though at different rates depending on node complexity. Notably, N5/N4 displayed the most aggressive early defect reduction, while N7/N6 showed a more gradual yield improvement. The N2 curve begins with higher initial defect levels than N5/N4 but declines sharply, closely matching the defect reduction trajectory of N3/N3P.

The slide emphasizes that production volume and product diversity remain the key drivers for accelerating defect density improvements. Larger production volumes and a wide variety of products using the same process enable faster identification and correction of defect density and yield issues, enabling TSMC to optimize defect learning cycles. TSMC stated that its N2 fabrication technology got more new tape outs than predecessors (as TSMC now risks producing N2 chips for smartphone and HPC customers), so the defect density decrease curve mostly proves that.

The fact that N2's defect reduction rate aligns well with previous FinFET-based nodes is particularly significant, given the risk factors associated with introducing an all-new transistor architecture. It suggests that TSMC has successfully transferred its process learning and defect management expertise into the new GAAFET era without major setbacks (at least based on what TSMC discloses).

Intel on Thursday posted its financial results for the first quarter of 2025. The company's earnings were flat year-over-year; however, its losses deepened, and its gross margin declined despite lower operating expenses. While sales of the company's data center grade products demonstrated signs of growth, sales of client CPUs declined compared to the same quarter a year ago. Perhaps more importantly, Intel gave a bleak outlook for the second quarter due to macro challenges. 

In the first quarter of 2025, Intel reported flat year-over-year revenue of $12.7 billion, with a net loss of $821 million, nearly twice the amount compared to the same quarter a year ago. The company's gross margin declined to 36.9%, pressured by a product mix, startup costs for the 18A ramp-up, and uncertainties (which Intel referred to as macroeconomic headwinds).

The company's operating expenses — including research and development (R&D) as well as management, general, and administrative costs (MG&A) — declined to $4.8 billion in Q1 2025 from $5.9 billion in Q1 2024. However, despite this decline, the company's losses increased. 

"The first quarter was a step in the right direction, but there are no quick fixes as we work to get back on a path to gaining market share and driving sustainable growth," said Lip-Bu Tan, Intel CEO. "I am taking swift actions to drive better execution and operational efficiency while empowering our engineers to create great products. We are going back to basics by listening to our customers and making the changes needed to build the new Intel." 

Perhaps the most alarming sign is that Intel's Client Computing Group (CCG) revenues fell 8% year-over-year to $7.6 billion. This drop was attributed to weaker-than-expected PC demand, particularly in the consumer segment, competitive pricing, and unfavorable product mix that includes a plethora of products made by TSMC. Interestingly, many of Intel's customers favored older-generation products like Raptor Lake over newer, higher-cost platforms such as Meteor Lake, Arrow Lake, and Lunar Lake. 

Despite these challenges, Intel noted demand for AI PCs from business customers, as well as enterprise fleet upgrades and Windows 10 end-of-service migrations, although this was insufficient to offset the broader softness in consumer sales. 

Intel's Data Center and AI (DCAI) business unit reported $4.1 billion in revenue in Q1 2025, achieving an 8% year-over-year increase, making it one of the few growth areas for the company. The performance was primarily driven by strong demand from hyperscalers for host CPUs in AI server deployments. However, the segment faced margin pressure due to competitive dynamics from AMD, product mix, and elevated demand for older-generation parts rather than newer offerings. 

Despite the revenue growth, Intel acknowledged macroeconomic uncertainty, potential spending pullbacks, and competition from AMD and Arm-based server solutions as risks that could affect DCAI performance in the coming quarters. The company remains focused on stabilizing market segment share and increasing average selling prices (ASPs) while preparing for the ramp of its next-generation server products. 

Intel Foundry reported $4.7 billion in revenue, reflecting a 7% year-over-year increase driven mostly by internal demand, particularly from Intel's own product groups for wafers and advanced packaging services. Despite revenue growth, the Foundry segment continued to operate at a significant loss, posting an operating loss of $2.3 billion, which remained roughly flat compared to the previous quarter. 

Intel's Lip-Bu Tan reiterated at the conference call that the company's Foundry success hinges not just on manufacturing capabilities but also on building customer trust, improving process design enablement, and supporting a broader range of customer flows. For now, the key mission of Intel Foundry is to ramp up production of Intel 18A-based Panther Lake and then Clearwater Forest processors in late 2025 – 2026 to prove that IF has a node that is competitive with TSMC's N2. 

Expanding its wings into the automotive ecosystem, Intel shared its upcoming SDV (Software-Defined Vehicle) SoC designs at Auto Shanghai 2025 yesterday. Slated to be the industry's first disaggregated design, the company presented its second-generation SDV SoC, internally codenamed Frisco Lake. A detailed investigation by 3elife, a Chinese tech and news publication, purports these SoCs are derivatives of Intel's Panther Lake design, with their successor allegedly based on Nova Lake.

Software-defined vehicles are automobiles where a majority of the functionality is handled through software, rather than traditional physical, mechanical, or electronic components. Compared to desktops, x86 has seen limited adoption in the automotive industry, primarily due to stringent power consumption requirements, real-time processing demands, and safety and security concerns.

However, as ADAS, autonomous driving, in-car experiences, and the need for high-performance computing in vehicles grow, Intel is positioning itself to gain traction in this market. Last year, the company released the 225W Arc A760A, offering a PC-like experience from the comfort of your car. The Raptor-Lake-based Malibou Lake platform represents Intel's latest SDV offering, featuring up to 14 cores (6P+8E), 24MB L3 cache, 96 EUs, and support for eight cameras, slated for a Q4 2024 launch.

Yesterday, Intel shared several slides detailing Frisco Lake, officially poised to deliver 10 times better AI performance and 61% higher efficiency than current offerings, presumably Malibou Lake. In addition, the inclusion of an Xe3 (Celestial) graphics IP block strongly suggests these SoCs are indeed derived from Panther Lake, a connection that is supported by the source and kernel patches (via Harukaze at X). The use of Intel's flagship 18A process node and the jump from Raptor Cove to Cougar Cove (rumored) would explain the sharp spike in efficiency.

That's not all, as 3elife secured an alleged roadmap detailing Intel's future product offerings from a third party. Assuming this timeline is accurate, Frisco Lake was never actually intended for launch and appears to be a last-minute addition to Intel's product stack. Apparently, Malibou Lake was in line to be superseded by Grizzly Lake, which is now expected to serve as Intel's third-generation SDV SoC design.

Under the Grizzly Lake lineup, the leaked slides mention an SoC codenamed Monument Peak, reportedly offering up to 32 cores, a 7 TFLOPS-capable Xe-based integrated GPU, slated for the first half of 2027. This time frame coincides with Nova Lake, and one rumored configuration of that architecture includes 32 efficient cores (16P+32E+4LPE), likely based on the Arctic Wolf microarchitecture.

So, if these rumors hold true, Intel is porting its consumer-grade architectures to the automotive industry with a one-year cadence. Considering the extensive validation processes and typically long lifecycles of these chips, automobiles usually don't opt for the most cutting-edge core design, unlike the desktop market. It's hard to say what the future holds, but perhaps Intel's limited success in the mobile phone and AI markets might be a catalyst for this drive to establish a strong foothold in the automotive domain.

TSMC is on track to start high-volume production of chips on N2 (2nm-class), its first production technology that relies on gate-all-around (GAA) nanosheet transistors, in the second half of this year, the company revealed at its North American Technology Symposium 2025. 

This new node will enable numerous products launching next year, including AMD's next-generation EPYC 'Venice' CPUs for the data center, as well as various client-oriented processors, such as Apple's 2025 chips for smartphones, tablets, and PCs. The new 2nm node will enable tangible power savings amid higher performance and transistor density thanks to GAAFETs and enhanced power delivery. Also, follow-up process technologies — A16 and N2P — are on track for production next year.

N2: Ready for mass production in 2H 2025

N2 is the company's all-new process technology that will enable what TSMC calls 'full node improvements,' which include a 10% to 15% performance improvement, a 25% to 30% power reduction, and a 15% increase in transistor density compared to N3E. TSMC says that N2's transistor performance is close to target and 256Mb SRAM blocks are achieving over 90% average yield, which signals strong process maturity as N2 moves toward volume ramp. 

As noted above, N2 will be TSMC's first node to use GAA nanosheet transistors, which promise increased performance and lower leakage as gate wraps 360 degrees around the channel — which in the case of N2 is shaped as multiple horizontal nanosheets. Such a structure allows for maximizing electrostatic control over the channel and therefore minimizing transistor size without compromising performance or power, thus enabling higher transistor densities. 

Additionally, the N2 process incorporates super-high-performance metal-insulator-metal (SHPMIM) capacitors into the transistor's power delivery circuitry to enhance power stability and performance. These new capacitors provide over double the capacitance density compared to the company's previous super-high-density metal-insulator-metal (SHDMIM) design and achieve a 50% reduction in both sheet resistance (Rs) and via resistance (Rc) relative to the earlier generation, which should have a tangible effect on performance and power consumption. 

Advertised PPA Improvements of TSMC's New Process Technologies

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area. 
***At the same speed.

This fabrication process is on track to enter volume production in the second half of this year and will enable numerous products coming out next year, including AMD's next-generation EPYC 'Venice' CPUs for data center as well as various client-oriented processors, such as Apple's 2025 system-on-chips for smartphones, tablets, and PCs.

TSMC states that its N2 process node is experiencing significantly faster customer adoption than its predecessors, with the number of new tape-outs (NTOs) in its first year already doubling that of N5 at the same stage. This momentum continues to build, as second-year NTOs for N2 have reached approximately four times the count seen for N5, signaling strong market interest and early design activity. 

While mobile products remain the leading adopters of N2, TSMC claims that HPC and AI customers are accelerating their use of the node, driven by the need for greater energy efficiency. This early engagement from traditionally later-stage segments (see AMD Venice example) highlights N2's appeal across a wider range of applications compared to previous generations.

N2P and A16: Due in 2H 2026

Unlike Intel's 18A (1.8nm-class), TSMC's N2 does not support a backside power delivery network; however, TSMC says the new node still delivers tangible benefits even without it. In case of TSMC's nodes, BSPDN — called Super Power Rail (SPR) — arrives with the A16 fabrication process. The foundry employs the most complex and expensive, yet most efficient, approach to backside power delivery, which involves directly connecting a backside power network to each transistor's source and drain. This contrasts with Intel's 18A approach, which connects BSPDN to the cell or transistor contact, a cheaper but presumably less efficient method. 

Since TSMC's SPR backside power delivery technology is expensive to manufacture, TSMC will continue to offer nodes without SPR going forward. One such process technology is N2P, which is a performance-enhanced version of N2 with a traditional power delivery network, that promises to offer 5% to 10% higher performance, and 5% to 10% lower power compared to N2. 

In fact, to a large degree, A16 is N2P with backside power delivery, according to TSMC, which will enable chip designers to reuse IPs for different products. For client applications that do not need a dense power network, N2P could be an optimal solution, particularly from a cost perspective. For those who require dense backside power delivery, TSMC will offer the A16. 

Both N2P and A16 are set to achieve high volume manufacturing milestone in the second half of the year, so expect actual products to hit the market in 2027. 

In addition to N2, N2P, and A16, TCMC will also offer N2X, the ultimate version of N2, with enhanced voltage tolerance to enable maximum clock speeds, albeit at the cost of increased power consumption. This node will be particularly useful for high-end client CPUs and some data center offerings that require maximum single-thread performance guarantees. N2X is expected to get to mass production in 2027.

TSMC has revealed its A14 (1.4nm-class) manufacturing technology, which it promises will offer significant performance, power, and transistor density benefits over its N2 (2nm) process.

At its North American Technology Symposium 2025 on Wednesday, the company disclosed that the new node will rely on its 2nd Generation gate-all-around (GAA) nanosheet transistors and will offer further flexibility with NanoFlex Pro technology. TSMC expects A14 to enter mass production in 2028 — but without backside power delivery. A version of A14 with backside power delivery is planned for 2029.

"A14 is our full-node next generation advanced silicon technology," said Kevin Zhang, senior vice president of business development and global sales and deputy COO at TSMC. "If you look at speed, enhancement [compared to N2] is up to 15%, power reduction is at 30%, logic density is 1.23x the overall chip density, or at least 1.2x [for mixed designs]. So, this is a very, very substantial technology."

TSMC's A14 is brand-new process technology that is based on the company's 2nd Generation GAAFET nanosheet transistors and new standard cell architecture to enable performance, power, and scaling advantages. TSMC expects its A14 to deliver a 10% to 15% performance improvement at the same power and complexity, a 25% to 30% lower power consumption at the same frequency as well as transistor count, and 20% - 23% higher transistor density (for mixed chip design and logic, respectively), compared to N2. Since A14 is an all-new node, it will require new IPs, optimizations, and EDA software than N2P (which leverages N2 IP) as well as A16, which is N2P with backside power delivery.

Advertised PPA Improvements of TSMC's New Process Technologies

*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.

Unlike A16 (and just like N2 and N2P), A14 lacks Super Power Rail (SPR) backside power delivery network (BSPDN), which enables the technology to target applications that do not get tangible benefits from BSPDN — which comes at additional cost. There are plenty of client, edge, and specialty applications that can take advantage of the extra performance, lower power consumption, and transistor density enabled by TSMC's 2nd Generation GAA nanosheet transistors, but that do not need dense power wiring and are fine with a traditional front side power delivery network.

"The technology also features our […] NanoFlex Pro technology, [which is really] design technology co-optimization (DTCO) allowing designer to design their product at a very flexible fashion, allow them to achieve optimum power performance benefit," Zhang said. "This technology is going into production by 2028. The first version of this technology does not have the backside power rail."

Of course, TSMC understands the needs of its customers that develop high-performance client and data center applications, so it plans to offer A14 with SPR backside power delivery in 2029. For now, the company did not disclose the exact name of the process technology, though it is reasonable to expect it will be called A14P, following TSMC's traditional nomenclature. Going forward, expect A14 to get its max performance (A14X) and cost-optimized (A14C) versions sometimes after 2029.

One of the key advantages of TSMC's A14-series process technologies will be the company's NanoFlex Pro architecture, which will enable chip designers to fine-tune transistor configurations to achieve optimal power, performance, and area (PPA) for specific applications or workloads. With non-Pro FinFlex, developers can mix and match cells from different libraries (high performance, low power, area efficient) within one block to optimize performance, power, and area.

TSMC has not disclosed explicit technical details differentiating NanoFlex from NanoFlex Pro, so we can only wonder whether the new version allows for more granular controls over cells — or even transistors — or whether it will offer better algorithms and software enhancements to enable faster exploration and optimization of transistor-level trade-offs.

TSMC's target for production of chips on its A14 process technology is 2028, though it refrained from mentioning if it would commence high volume manufacturing on A14 in the first or second half of the year. Considering the fact that A16 and N2P will kick off HVM in the second half of 2026 (i.e., late 2026), with chips on the market in 2026, we have a feeling that A14 is targeted for the first half of 2028 — on track to serve client applications due in the second half of the year.