Intel's 14A (1.4nm-class) process technology is expected to deliver performance 'within 5%' of TSMC's A14 (1.4nm-class) production node, Naga Chandrasekaran, the chief technology and operations officer as well as general manager of Intel Foundry, told investment banking firm KeyBanc (via @Alex_Intel_). Given TSMC's track record of delivering steady performance, power, and area (PPA) gains with every new node, this might sound like entirely good news. However, the statement deserves a closer examination.

Delivering 'within 5%' performance is an ambiguous statement that may mean that 14A will be 5% faster than A14, or that 14A will be 5% slower than A14. While 'within 5%' performance compared to the direct rival of the same class may sound like a good competitive position, in recent years Intel's process technologies trailed TSMC's nodes in transistor density and remained competitive in performance or power. This was, to a large degree, attributed to Intel's historic focus on CPU performance, but not necessarily transistor density, as its own fabs have offset additional costs associated with larger dies.

In fact, actual shipping processors suggest Intel's 18A is at least competitive with TSMC's N2 in maximum achievable CPU frequency as Intel's Core Ultra X9 388H 'Panther Lake' can hit 5.10 GHz (at an 80W max turbo power), AMD's EPYC 9586F has the highest single-core clock of 5.0 GHz (at a default 500W CPU power), Apple's A20 Pro can achieve 4.93 GHz, whereas Apple's M6 can hit 4.78 GHz. These numbers should not be converted directly into a statement such as '18A is X% faster than N2,' because the processors use different architectures, voltages, standard-cell libraries, thermal envelopes, and physical implementations. However, they do provide a useful real-world reference point: the available N2 processors do not show a substantial frequency advantage over 18A. If anything, the highest observed CPU frequencies favor Intel's process.

Based on internal estimates, Intel officially states that compared to its already fast 18A, its 14A is expected to provide 15% – 20% higher performance at the same power, or 25% – 35% lower power at the same frequency and transistor count. By contrast, TSMC expects its A14 to be 10% - 15% faster than N2 at the same power, or 25% - 30% lower power at the same clocks and transistor count.

Combining the observed 18A and N2 CPU frequencies of Intel's 18A and TSMC's N2 with Intel's stated 15% – 20% 14A gain and TSMC's assumed 10% – 15% A14 gain would ordinarily suggest a modest 14A performance advantage of A14 even in most conservative scenarios for Intel. Therefore, Intel's new expectation that 14A will be 'within 5%' of A14 is notably less ambitious than one might infer from the company's published process specifications, even though the 'within 5%' statement does not tell us which process Intel expects to lead.

In fact, advantages of Intel's 14A over TSMC's A14 can be calculated using the highest observed 18A and N2 CPU clocks combined with Intel's and TSMC's official iso power performance projections.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 5.00 GHz (EPYC 9586F).

With Intel’s Core Ultra X9 388H and AMD’s EPYC 9586F as the starting points, the official iso-power performance projections imply a 2% – 11.3% potential performance advantage for 14A over A14, depending on the combination of process-performance assumptions.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 4.78 GHz (Apple M6).

Using Apple's M6 as the real-world N2 reference, a similar calculation gives Intel 14A a 6.5% – 16.2% implied advantage over TSMC A14. Even the worst possible combination for Intel — 14A achieves only +15% while A14 achieves the full +15% — puts Intel's node well beyond the 'within 5%' estimate given by Naga Chandrasekaran.

It should be clearly noted that our calculations do not predict 14A or A14 CPU frequencies, as we use clocks from current CPU architectures with improvement claims for upcoming process technologies. The calculation is useful primarily for illustrating what the companies' published numbers imply relative to today's products.

Intel's 'within 5%' assessment raises an interesting question: why does Intel expect 14A and A14 to be so close when the companies' published process gains appear to suggest a larger gap? Perhaps Intel's assessment incorporates factors that these simple calculations do not capture. Or perhaps the head of Intel Foundry took a page from his boss Lip-Bu Tan's book and now prefers to underpromise.

As the world's only supplier of EUV lithography systems, ASML is Europe's largest company by market capitalization, currently valued at around $660 billion. But it earned almost nothing in Europe this year, down from 1% of total profits in 2025 and 5% in 2024. Why? European chipmakers bought no lithography equipment from ASML in 2026 — and the company is calling on EU authorities to help create demand for European chips.

"We are selling absolutely nothing in Europe," said Frank Heemskerk, executive vice president of public affairs at ASML, while speaking at a panel discussion from the Dutch political and cultural center De Balie. "Because Europe is not investing and because no chip factories are being built in Europe. That is genuinely worrying. […] [Our revenue share in Europe is 0%], it used to be 1%."

Indeed, Europe accounted for 1% of ASML's revenue share in 2025, 5% in 2024, 4% in 2023, and 2% in 2022, based on the company's presentations for investors. In the first two quarters of 2026, however, Europe accounted for 0% of ASML's revenue, according to ASML's earnings reports.

"There simply is no demand here for these kinds of highly specialized machines," Heemskerk said. "That is the problem. So apart from trying to attract investment with capital on the supply side, we should do much more to create demand. […] So, we at ASML are also making an enormous effort, and we are talking with Ursula von der Leyen in Europe, saying: 'try to harness the market power and dynamism that ultimately do exist in Europe in a number of areas.'"

So far, the European Union has been keen on subsidizing building new fabs in Europe (something that did not help to lure Intel in). But ASML is calling on European governments to help aggregate and guarantee demand for European-made chips — which will encourage major European chip consumers to source locally, giving semiconductor manufacturers an economic reason to build or expand fabs in Europe.

"We need to make sure that some of those buyers — the customers of our customers — start talking much more closely with European manufacturers again. In areas such as artificial intelligence for industry, for example, there are still plenty of opportunities that Europe can seize. But you have to organize this collectively."

New fabs are being built…

That said, the ASML EVP may be too pessimistic about Europe's semiconductor industry.

Intel runs its massive Fab 34 near Leixlip, Ireland, and recently announced plans to invest €5 billion in the facility to expand production of CPUs on Intel 4 and Intel 3 process technologies. While the new investment dwarfs Intel's plans to invest roughly €80 billion in its Magdeburg, Germany, fab complex, with two first fabs alone accounting for over €30 billion, it still represents Intel's commitment to its Ireland campus.

In addition, ESMC — which is backed by TSMC, Bosch, Infineon, and NXP — is building a brand-new fab near Dresden that will cost around €15 billion. The fab will be capable of producing chips using 12nm/16nm-class FinFET and 22nm/28nm planar transistor-based process technologies used in a wide range of automotive applications. The same nodes are also used for various consumer electronics and edge applications.

Infineon also opened its new €5 billion Smart Power Fab in Dresden in July 2026, which marked the largest single investment in the company's history and effectively doubled its manufacturing capacity at the site. The 300mm facility produces power semiconductors as well as analog and mixed-signal chips for automotive, industrial, renewable-energy, and AI data-center applications.

Last but not least, GlobalFoundries officially broke ground on the latest major expansion and upgrade of Fab 1 in Dresden this March to increase capacity for its specialty process technologies, including 22nm FD-SOI (22FDX), embedded non-volatile memory (eNVM), and the BCD (bipolar-CMOS-DMOS) node for power management ICs. To some degree, the upgrade was forced by headwinds that GlobalFoundries faced when building the €10.4 billion joint fab with STMicroelectronics in the Grenoble, France, region.

With numerous semiconductor fab projects in place in Europe, ASML will continue to sell its tools to companies in the EU for years to come; the semiconductor industry is far from dead in the bloc. Of course, the important detail is that all of these production facilities are built by multinational corporations (sometimes in collaboration with local companies) — but this is largely a global trend rather than a major issue.

…But there's a catch

Although the fab projects in Europe are large in terms of investment, they pale in comparison with those being built in Taiwan, South Korea, the U.S., and Japan, where tens or even hundreds of billions of dollars are being invested in new semiconductor production facilities.

What is perhaps more important from ASML's standpoint is that none of the ongoing fab projects in Europe are leading-edge fabs set to use EUV and eventually High-NA EUV lithography scanners. The tools that European fabs use today and that new facilities are set to use in the future are mature tools that cost considerably less than advanced EUV or immersion DUV scanners. This is perhaps a concern for ASML, as the company is naturally interested in selling its more sophisticated and expensive equipment.

Another concern is that even advanced silicon produced in Ireland or at ESMC is then shipped to other regions for packaging, meaning that European companies have largely lost their ability to produce sophisticated chips entirely in Europe. In turn, this means that, for now, there is hardly any strategic point for European authorities to create demand for chips that are 'Made in Europe' because they are either not assembled in Europe, not produced in Europe, or not developed in Europe. We have no idea whether this is eventually going to change, but there are currently no signs that it will.

In an unexpected turn of events, Terafab has faced an odd roadblock as a small U.S.-based company called Tera-Print sent a cease-and-desist letter to SpaceX and Tesla back in May to stop using the Terafab name. The company with tera-scale ambitions has run into a tabletop-sized problem because the Tera-Fab name has already been used for about a decade by Tera-Print, according to PCMag.

As it turns out, Tera-Print sells tabletop-sized Tera-Fab-branded beam pen lithography (BPL) tools primarily aimed at bioengineering and prototyping of microfluidic devices and has used the brand for about a decade. The U.S. Department of Defense appears to be a client of Tera-print, which uses Tera-Fab.

While Tera-print claims that the Terafab name could be confused with its Tera-Fab product family, Tesla, SpaceX, and SpaceXAI counter that the operations are fundamentally different: Terafab is set to produce chips in extremely high volumes to serve AI, automotive, robotics, and eventually (at least some) space applications, whereas Tera-print's Tera-Fab is a compact lithography tool that can be used for bioengineering or prototyping of electronic or optical devices.

Formally, the trademark coverage puts both names into the same semiconductor technology bucket, albeit with different descriptions:

• Tesla's Terafab covers 'custom manufacture of semiconductor chips, memory chips, integrated circuits, and wafers' (IC 040) as well as 'distribution services, namely, delivery of semiconductor chips, chip carriers, namely, semiconductor chip housings, memory chips, integrated circuits, semiconductors, and microchips' (IC 039).
• Tera-print's Tera-Fab covers 'Polymer pen and beam pen lithography instruments in the nature of 3D micro-printers and 3D nano-scale printers' (IC 007); 'Polymer pen and beam pen lithography instruments in the nature of 2D micro-scale molecular and material printers and 2D nano-scale molecular and material printers' (IC 009), 'Light-directed photochemical synthesis tools; Industrial advanced materials synthesis tools; Advanced light projection systems; High precision force-feedback sample alignment modules; Environmental control sample chambers' (IC 009); as well as 'training services in the field of AI design and development, electronics, computer science, biology, and material science' (IC 042).

The two companies reportedly entered settlement talks, which included an offer from Tesla, but Tera-Print alleges that Tesla expressed interest in continuing negotiations instead of taking the dispute to court. Tera-Print says it will now defend its registered trademark and argues that the companies operate in related fields, which could lead to confusion.

Even as chipmakers race to build the most advanced chips inside the United States, experts are saying that their efforts are facing one monumental challenge: a massive shortage of skilled workers to run the fabs and factories. According to CNBC, global consulting firm McKinsey and the SEMI Foundation suggest the industry will have up to 157,000 positions that could remain unfilled by 2030.

“I’m concerned,” Samsung semiconductor division EVP Jon Taylor told CNBC in an interview. “We just don’t see that there’s enough technical people in the pipeline.” The McKinsey report says that only 3% of U.S. engineering graduates end up working in the semiconductor industry, and that 73% of chip companies are finding it hard to fill engineering roles. This is a huge contrast to other tech jobs, which saw record layoffs by June of this year, when over 40,000 positions were axed, ostensibly largely due to AI.

The massive demand for memory and storage chips driven by the AI boom, combined with Washington’s efforts to bring semiconductor manufacturing back to the United States, has led to the buildup of multiple fabs and facilities dedicated to it. TSMC was one of the first companies to kick off this building spree, when it started construction on its Arizona campus in 2021. The site started churning out chips last year, with the company committing another $100 billion in July 2026 to build four more 2nm fabs. Intel’s Ohio One plant, which was, at one point, America’s largest fab complex, is also underway, with the site expected to start production between 2030 and 2031.

The big three memory makers — Micron, Samsung, and SK hynix — are also planning or have recently completed major expansions in the U.S. Samsung is starting advanced semiconductor manufacturing in the U.S., with its Taylor, Texas, fab entering risk production this year. The fab is targeting an output of 50,000 wafer starts per month, and it is expected to create 3,500 jobs. “We’re hiring engineers, we’re hiring technicians, we’re hiring people in the supply chain,” Taylor told the publication. “Everybody wants and needs the same thing, and it’s a bit of a race against time right now as everything is starting to come online.”

Micron is also currently building its Boise, Idaho, memory chip fab, which began construction in 2022 and is projected to begin wafer production by 2027. The company has also formally broken ground on its $100-billion New York “megafab,” with aims to produce 40% of its global output within the U.S. by the 2040s. Aside from these massive manufacturing sites, it has also committed $10 billion toward new research labs in the U.S., to be built near the global Micron R&D center in Boise.

Finally, SK hynix also started construction of its first HBM plant in the U.S., with its West Lafayette, Indiana, campus dedicated to packaging these crucial components for AI data centers. There have also been rumors that the South Korean company is in talks with Intel to either lease space at its Ohio One factory or launch a joint venture alongside other AI hyperscalers to build memory chips in the U.S.

All these construction projects, plus the requisite supply chains, will necessitate thousands of workers. Local universities like Purdue University and Arizona State University are already investing millions of dollars to help prepare a capable workforce, with the former launching degrees in 2022 focused on semiconductors. Samsung and Intel are also investing in various programs, including internships and scholarships, to help secure a future workforce for the companies.

However, salary is one major concern listed by the SEMI Foundation. U.S. chip fabs typically pay $127,000 to $187,000, with senior staff getting $238,000 or more. While this is a more-than-competitive salary in the U.S., it’s dwarfed by the bonuses recently offered by Samsung and SK hynix in South Korea, which have reached hundreds of thousands of dollars. With the projected worker shortfall, we should expect the job offers from these semiconductor companies to catch up with their eastern counterparts if they want to secure and maintain talent here in the U.S.

One of the key challenges with the development of extreme ultraviolet (EUV) lithography scanners is building a powerful and reliable light source. ASML, which is the only company to manufacture EUV lithography tools, uses rather complicated laser-produced plasma (LPP) technology to generate EUV light. By contrast, numerous companies propose to use a free-electron laser (FEL), which relies on a particle accelerator, for EUV generation. While FEL has its advantages and is even endorsed by Elon Musk, ASML is unlikely to adopt it, according to JPMorgan.

"Given laser advances, ASML sees no reason to try new 'FEL' light source favored by Musk," reports Semi Doped, citing a JPMorgan note for clients.

Modern EUV lithography systems use laser-produced plasma light sources that fire powerful CO₂ laser pulses at tiny droplets of molten tin, around 30 microns in diameter, which turns them into ionized plasma with electron temperatures of several tens of electron volts that emits 13.5-nm EUV radiation. The light is then collected by a roughly 0.5-meter elliptical collector mirror coated with multiple layers of molybdenum and silicon, which selectively reflects as much 13.5-nm radiation as possible and directs it toward the intermediate focus at the entrance to the scanner.

Since virtually all materials absorb EUV radiation — even specialized multilayer mirrors absorb a substantial portion of it — the entire optical path must operate in vacuum and use reflective rather than conventional refractive optics, which is one reason why generating sufficient EUV source power remains challenging.

Despite major challenges, ASML has gradually increased the source power of its LPP light sources from around 250W to around 500W and plans to increase it to 1000W in the coming years. In addition, the company plans to almost double the number of generated tin droplets to 100,000 every second.

A free-electron laser (FEL) generates EUV light by accelerating electrons to nearly the speed of light and passing the electron beam through an undulator, a series of alternating magnets that force electrons to oscillate and emit radiation. Interaction between the electrons and their radiation causes them to form microscopic bunches and emit light with a 13.5-nm wavelength. This approach eliminates tin droplets and associated debris (that require usage of protective pellicles on photomasks) as well as potentially provides substantially higher EUV power than LPP sources. Furthermore, one FEL can potentially replace multiple LPP sources with a single FEL and a large EUV beam-distribution system.

Yet, there is a major tradeoff: instead of a relatively compact LPP, FEL requires a highly complex particle accelerator, an electron source, a long undulator, electron-beam control, radiation shielding, and an extremely complex distribution system featuring mirrors capable of handling and distributing very high EUV power without losing too much of it along the way. The whole machine must achieve semiconductor fab levels of availability, efficiency, and cost, something that took ASML and the rest of the industry years to achieve.

So, while there is a great enthusiasm surrounding FEL in China, the U.S., and Japan, it will likely take a decade, if not more, before FEL will be able to rival LPP in real semiconductor production facilities. The technology will likely devour billions of dollars in the meantime, so not all entities currently pursuing FEL will live that long.

PieceMakers, a Nanya-backed DRAM designer, began trading on Taiwan’s Emerging Stock Board on September 16 at a NT$740 reference price, Cnyes reported ahead of the debut. PieceMakers is not an HBM company. Instead, it bets that inference memory diverges from training memory, President Lee Hsiao-wen told Cnyes, and that DRAM stacked directly on the processor with hybrid bonding can sit between Nvidia’s SRAM-only Groq LPU and HBM. As it stands, design fees, not chips, carry the company's profit, with AI custom-design work accounting for around 40% of the company's revenue in the first half of 2026. Piecemakers Chairman Joseph Ting told TechNews that its first volume customer program will not contribute to the company's financials until 2027 at the earliest.

At roughly 60.4 million shares outstanding, that price values the company at around NT$44.7 billion (around $1.4 billion). Taiwan's Emerging Board is the Taipei Exchange's pre-listing market, not a main-board IPO, so shares trade through market makers ahead of any formal listing application. The stock ended its first session at NT$915, 23.6% above the NT$740 reference price, after opening at NT$1,035 and trading as high as NT$1,205.

Nanya Technology is the largest holder of Piecemakers, at 33.96%, after selling 715,000 shares at NT$740 to seed the float, a disposal it disclosed in a Sept. 9 exchange filing reported by Knews.

What PieceMakers sells

PieceMakers was founded in January 2006 in Hsinchu, Taiwan, led by chairman Joseph Ting and president Lee Hsiao-wen. Historically, the company has designed standard SDR/DDR DRAM and known-good-die (KGD) parts through representatives in China, Japan, France, Turkey, and Israel. Now, the company seeks to shift from direct product sales to custom design services, paid as non-recurring engineering (NRE) fees, and then to IP licensing, royalties, and turnkey production from 2027, the company said at its Sept. 7 briefing, UDN reported.

Revenue from the AI custom design unit has risen from around 4% in 2024 to almost 40% in the first half of 2026. The products behind that increase are HBLL (High Bandwidth, Low Latency RAM), a 2D die rated at 144 GB/s that was taped out in 2016 for Intel’s HPC line and published at ISSCC in 2017, and HiBaLL, the 3D-stacked version rated at more than 1 TB/s, the company claims.

The company described its customers to Cnyes as developers of cloud AI inference accelerators, international semiconductor players, and North American customers, with some programs in design and verification, and none named. Qualcomm CEO Cristiano Amon’s Computex keynote backdrop in June listed PieceMakers among Taiwan ecosystem partners, although neither company has defined the relationship. The takeaway is that the profit is in design fees and not chips. The margin curve matches a pre-royalty Non-Recurring Engineering (NRE) business, rather than a traditional memory vendor.

Why Nanya is chasing this instead of HBM

Nanya’s AI-memory strategy is custom and edge rather than HBM3E. PieceMakers is the first half of a strategy laid out in 2024. On Aug. 7, 2025, Nanya announced a joint venture with Etron Technology, a Hsinchu-based chip designer, capitalized at NT$500 million, with 80/20 ownership. The venture was envisioned to design custom high-bandwidth memory for edge AI devices rather than for data center accelerators. Nanya president Pei-Ing Lee said earlier in 2025 that the company would not compete in HBM3 or HBM3E, TrendForce reported.

Both halves of the strategy rely on Formosa Advanced Technologies, the Formosa Plastics Group’s test and assembly affiliate, for packaging. It is building the through-silicon-via (TSV) and die-stacking processes that both need. The surge in DRAM pricing has made commodity memory Nanya’s real business, which leaves PieceMakers a cheap side bet that has become a windfall. Nanya took advantage of this by selling around 3% of its stake in a move that suggests it is acting more as an investor than a parent building a memory stack.

The inference gap

Groq is an AI inference startup that Nvidia struck a $20 billion licensing-and-talent deal for on Dec. 24, 2025. Nvidia announced its first chip built from that, the Groq 3 LPU (language processing unit), Nvidia’s SRAM-based inference chip, at GTC, its annual developer conference, in San Jose earlier this year.

There is no HBM or DRAM on the Groq 3 LPU. Instead, it uses 512MB of SRAM on the die to deliver 150 TB/s of bandwidth against 22 TB/s from the 288GB of HBM4 on each Rubin GPU. It’s a decode-only co-processor with Rubin handling the prompt prefill, displacing Nvidia’s Rubin CPX from the roadmap.

At Hot Chips 2026, Nvidia’s Igor Arsovski, Groq’s former chief architect, said the rack is in production and published the first third-party benchmark: 3,431 tokens per second on a 100K-context, 31B-parameter model, at about four times the next-fastest public endpoint, in a single-request test that we noted isn’t directly comparable to the shared endpoints it was measured against. The cost is capacity: at 512MB per chip, a 256-LPU rack holds 128GB, with the model needing 62 chips at FP8 just to hold the benchmark weights. Nvidia accepted that trade for decode speed, which supports Lee’s point that the market leader’s newest inference product contains no HBM.

At Hot Chips, Samsung’s Sangwook Han laid out a three-phase HBM roadmap that ends in zHBM, which is DRAM stacked directly on top of the processor rather than beside it on an interposer. Samsung projects about 70% less I/O power usage than HBM5 with roughly 2.3x the bandwidth of a four-stack HBM4E system, with zHBM’s stacks limited to about four-high due to heat, at around 100W less. This would require wafer-on-wafer hybrid copper bonding and tight co-design between DRAM and SoC teams. SK hynix’s Jaesik Lee, VP of package engineering, said on Aug. 23 that hybrid bonding won’t be ready for HBM4E, leaving HBM5 as the earliest point. Counterpoint Research expects full-scale HBM production with the technique around 2029–2030.

PieceMakers offers a different version. Instead of the GPU-plus-HBM 2.5D layout, it bonds the DRAM stack directly onto the processor, wafer-on-wafer, with hybrid bonding instead of microbumps. This fits far more connections with the finer pitch, improving bandwidth, and the shorter path reduces both latency and power consumption. The company puts its wafer-on-wafer product at more than 2 TB/s per layer with latency under 20ns, the company figures, but the target is more capacity than SRAM at a lower cost and power than HBM. PieceMakers is not doing the TSV or hybrid bonding itself, as this is handled by the customer’s logic wafer foundry, Ting added. This custom service promises a 2027 date against Samsung's undated roadmap end and SK hynix's HBM5-at-the-earliest timing. Nvidia and Samsung have each, in their own way, settled the architecture question, with the open question being the customer.

Yield is the product

Lee also said that yield is the biggest hurdle to wafer-on-wafer mass production. The repair architecture has to be designed in, with testing before bonding, after bonding, and then after logic integration. Lee’s own example was 80% yield per layer, at which four layers come out at about 41% and eight at 17%. Our recently-published hybrid bonding state of play covers the process side in more detail.

This better puts into perspective why the company sells repair and known-good-die IP as much as it does bandwidth. It’s also why an IP-and-royalty model fits the strategy — yield IP is portable across customers while a bandwidth number is not.

What to watch

For PieceMakers, AI revenue remains primarily NRE until there is a first named customer, with the first volume program expected in 2027 at the earliest. Ting said that Nanya’s Q3 2026 results, which come in late October, will gauge the PieceMakers gain and reveal further financial information. SK hynix’s hybrid-bonding timing, which targets HBM5 at the earliest, is the current benchmark, although its 16- and 20-layer memory stacks are a separate problem from a few DRAM layers on a logic wafer. Qualcomm may also describe its relationship with PieceMakers more formally.

PieceMakers is likely to end up as an IP licensor with a small number of accelerator customers and turnkey volume through Nanya and Formosa Advanced Technologies. The technology risk is the foundry’s and the customer’s, which is why PieceMakers’ design-fee model works. PieceMakers is expected to benefit from a 2027–2028 ramp, later than Ting’s 2027. If the largest HBM maker won’t bond its own memory this way before HBM5, PieceMakers’ own 2027 date is the one it must meet.

China's progress toward technological self-sufficiency in recent years is undeniable, but there is one thing that the country has so far failed to develop: lithography tools that are on par with those offered by ASML. That shortcoming has greatly hampered its domestic semiconductor industry. But Nvidia CEO Jensen Huang believes China will develop its own advanced lithography systems in just three or four years.

"They are going to get there by 2030," Huang said in an interview with The All-In Podcast (at 43:43). "2030 is just around the corner. The way to think about China is that it is really good at high-volume production. It is just a matter of time[...] so two or three years is just a click; it is nothing. So as far as they are concerned, they are already there."

Huang tends to look optimistically at China's technological development. Specifically, he is known for calling China's AI industry as being 'right behind' American frontier labs, which may well be correct, given how much capital China is investing in AI. But when it comes to the Chinese semiconductor industry in general and its lithography sector in particular, Huang may be too optimistic.

At present, China's leading producer of lithography tools — Shanghai Micro Electronics Equipment — can mass-produce a 193-nm ArF dry scanner that can be used to build chips on 90nm-class process technology. While the company has reportedly developed a 28nm-capable ArF immersion scanner, there is no public evidence that such systems are produced in volume and are used for high-volume chip production.

Although there are reports that Shanghai Aishengna Electronic Technology Group (a unit, or an affiliate of SMEE) has delivered its first immersion scanner that may be capable of printing chips using 28nm-class process technology, these tools will require extensive qualification before they can be used for high-volume manufacturing of semiconductors, so if deployment follows standard timelines, it will take years before this unit will be used for mass producing chips.

Even assuming that the first scanners are delivered to Chinese chipmakers in 2026, widespread production use before 2028–2029 appears unlikely. Furthermore, matching the capabilities of an early-generation ASML immersion scanner would still leave Chinese lithography suppliers considerably behind ASML's contemporary systems, which makes technological parity in ArF immersion lithography by 2030 highly unlikely.

China is considerably further behind in extreme ultraviolet (EUV) lithography. While there are reports that Chinese scientists have managed to develop a laser-produced plasma source that can generate the 13.5-nanometer wavelength light required for the technology, it does not look like China is close to assembling even a prototype EUV scanner itself.

Even if China can assemble an EUV experimental exposure platform without having mastered production-quality immersion DUV, it is hard to imagine a Chinese company producing EUV scanners without solving the hardest problems common to both DUV and EUV technologies. A production lithography scanner requires extraordinary capabilities in wafer and reticle stages, alignment, overlay, projection optics, and metrology, just to name a few.

If China is still struggling to industrialize these capabilities for immersion DUV, there is little reason to assume it has somehow solved them at the substantially more demanding EUV level. But given the potentially existential stakes of the AI race, and the determination of the Chinese government to achieve technological self-sufficiency, it may just indeed be a matter of time.

South Korean memory chip manufacturer SK hynix is in talks with Intel to start manufacturing inside the U.S., according to Reuters. The company is reportedly considering multiple options, including leasing space at the under-construction Intel Ohio One site and forming a joint venture with Intel and other AI hyperscalers desperate for HBM.

This move could help alleviate the memory shortage. It would also complement the company’s expansion in Indiana, where it recently broke ground on an HBM packaging plant a few weeks after its historic $26.5-billion Nasdaq listing. It’s unclear yet if these talks are part of the results of the South Korean president’s visit to Silicon Valley in an effort to expedite negotiations between its top tech companies and their U.S. counterparts, but SK Group chairperson Chey Tae-won told reporters in July, “I think we need to build a factory in the United States. If possible, I believe we should build it.”

However, there are also concerns that Seoul might object to such investment. The South Korean government just unveiled a $520 billion investment plan to increase chipmaking capacity within its shores and keep the country competitive in the AI race; at the same time, it’s also in talks with the U.S. to finalize its $350 billion investment commitment to Washington to reduce tariffs on South Korean goods, $200 billion of which is still undecided on which projects it will be deployed on. Meanwhile, the Commerce Department has threatened to impose more tariffs on South Korean and Taiwanese tech companies if they fail to invest in U.S. manufacturing. This potentially puts SK hynix at a precarious position, especially as it balances the demands from the White House and the Blue House.

Neither company has confirmed these rumors, though. SK hynix told Reuters that it’s “reviewing various measures, including establishing additional production bases, to strengthen the competitiveness of its memory business,” but “no matters have been determined at this stage.” On the other hand, Intel called them speculation and declined to comment on the matter, only saying that it was continuing to invest in the Ohio project, which is expected to come online between 2030 and 2031.

Micron has announced a one-time cash appreciation bonus of NT$1 million (US$31,650) as part of a broader compensation/reward package for its employees based in Taiwan. According to a Reuters report, the full package — which comes amidst ongoing disputes between the U.S. memory giant and its Taiwanese workforce — will see each employee earn a minimum of NT$1.7 million ($53,809.39).

The company called the payouts the largest rewards package in company history, confirming that more than 60,000 employees globally will receive scaled rewards for fiscal year 2026, “following an extraordinary year for the company.” Across the last four quarters, Micron’s cumulative net income from sales of high-demand memory chips has crossed a staggering $50.47 billion, with its Q3 earnings representing a 346% year-over-year increase. After the announcement, the union representing workers at Micron's Taoyuan plant officially rejected the company's bonus proposal, calling the package a distraction.

Under the announced payout, every Taiwan-based employee who joined the company on or before August 29, 2025, is eligible for the flat NT$1 million cash bonus. Those hired during fiscal year 2026 will receive a prorated amount. For direct manufacturing and production-line workers, the total bonus rewards are equivalent to 35 to 68 months of basic salary. Direct labor employees will receive a minimum total cash compensation of NT$1.7 million (US$53,809), while the average total compensation for junior engineers is projected to reach NT$3.4 million (roughly US$106,250), comprising NT$2.9 million in cash and the remainder in equity grants.

The announcement — which mirrors bonus payouts by Samsung and SK Hynix amid the soaring profits from the AI boom — comes after local unions in Taoyuan and Taichung, representing 10,000 of Micron's 15,000 Taiwan workforce, began threatening a strike on September 1, demanding packages similar to the payouts that will see Samsung employees receive over $300,000 in bonuses. The Taiwanese government stepped in to force a mediation. However, unlike in Samsung's case, which also involved government intervention that narrowly averted a potential strike, the talks fell through on September 4 after both parties failed to reach a consensus, leading Micron to announce the NT$1 million bonus package a week later.

In an official statement following Micron's announcement, the union said the new package "sidestepped" the real discussion about a transparent bonus system. The union is pushing for structural change, including a permanent profit-sharing model in which 15% of the company's operating profits are allocated directly to workers and distributed quarterly. They are also demanding a larger one-off payment equivalent to roughly 83 months of salary for fiscal year 2026. Last September, South Korea’s SK Hynix reached a settlement with its union to allocate 10% of annual operating profit directly to employees as performance bonuses for the next decade, eliminating bonus caps.

Similar incidents have played out across the semiconductor industry as companies continue to pull in unprecedented profits from the AI boom. Workers in these industries believe they should share in profits and are requesting concrete institutional safeguards to ensure they are fairly compensated during high-profit AI booms, rather than relying on arbitrary, opaque bonuses decided solely by management. Samsung's unions were ready to strike before reaching an agreement with the company and even held a demonstration attended by over 30,000 Samsung union members.

In the case of Micron — which announced a record-breaking GAAP net income of $28.24 billion in just Q3 2026 — the threat of a strike continues to loom following the Union’s rejection of its proposed payout. A critical second round of mediation is officially scheduled for September 21, 2026. If that upcoming meeting falls apart, the union plans to hold a vote allowing members to strike. In an earlier internal survey, 80% of union members voted in favor of a strike.

Jiangsu Pacific Quartz, a high-purity quartz (HPQ) producer from China, is already supplying its HPQ material to leading domestic and overseas producers of chipmaking tools, including Lam Research and Tokyo Electron. More recently, the company's materials/components have passed certification by a domestic DRAM manufacturer. Analyst TP Huang, who hosts the China Tech Talk podcast, believes that the DRAM maker is CXMT.

While Pacific Quartz's achievements are significant, the company's components are used in semiconductor production equipment after the silicon wafer has been made. Meanwhile, Ingots for semiconductor wafers are grown in crucibles made from high-purity fused quartz, typically over 99.999% SiO₂ (5N+), with much tighter limits on individual critical contaminants. For now, such quartz can only be obtained in significant volumes from Sibelco and The Quartz Corp., which operate in Spruce Pine, North Carolina, and from Russian Quartz LLC, which can produce modest volumes.

Pacific Quartz has supplied Lam Research and Tokyo Electron with ultra-high-purity quartz consumables, such as LPCVD diffusion tubes, wafer boats, quartz ingots, quartz plates, and high-purity quartz tubes, since 2019–2020. Typically, quartz used for process equipment is 4N5 – 5N purity (~99.995–99.999% SiO₂). So Pacific Quartz's products are good enough for semiconductor tools.

More recently, Pacific Quartz said its quartz products manufactured from its own high-purity quartz sand passed qualification at a leading Chinese DRAM manufacturer, apparently CXMT, for use in 300-mm wafer production. This is particularly significant because it demonstrates a largely domestic supply chain for Chinese quartz that starts with Pacific Quartz's purified high-purity sand, which is then processed into semiconductor furnace-tube material that goes to a DRAM fab. While CXMT certainly uses equipment from Lam Research and Tokyo Electron, we cannot say for sure that all the quartz consumables that these tools use are made by Pacific Quartz.

Semiconductor furnace tubes are typically made from roughly 5N-class high-purity fused quartz, with stringent limits on electrically active and mobile contaminants, as they can migrate onto/into hot silicon wafers and alter transistor characteristics, ultimately creating defects and lowering yield.

While China-based Pacific Quartz can produce components for semiconductor production equipment, it still cannot produce crucibles good enough to grow silicon wafers with 9N–11N purity. Will it change in the foreseeable future? Only time will tell.

ABF substrates, the specialized insulating and wiring bases that connect tiny silicon chips above them to the much larger printed circuit boards below, sit beneath most high-end CPUs, GPUs, and AI accelerators. Featuring the Ajinomoto build-up film (ABF), these substrates have been critical to the semiconductor industry since the late 1990s, with personal computers, workstations, servers, and networking silicon driving steady demand for decades.

The artificial intelligence boom has multiplied that demand exponentially. Training and inference for frontier models now run across data centers, each housing hundreds of thousands of accelerators and providing hundreds of megawatts of compute. Nvidia alone shipped an estimated 3.2 million Blackwell GPU packages through the end of 2025, with every one of those accelerators packaged on an ABF substrate. Meanwhile, the industry is already entering the gigawatt era with humongous data center buildouts, each expected to house millions of AI accelerators.

This edifice rests on a remarkably narrow supply chain. Practically every advanced logic and AI chip made today by Intel, AMD, and Nvidia depends fundamentally on ABF substrates. These substrates are the conventional default for high-performance packaging. They are made by a small group of specialists, including Unimicron, Ibiden, Kinsus, Shinko Electric Industries, Samsung Electromechanics, and Nan Ya PCB. The upstream supply chain gets much tighter.

The one common denominator across ABF substrates, regardless of manufacturer, is the Ajinomoto build-up film itself. Each substrate maker laminates its build-up layers using dielectric film supplied by Japan's Ajinomoto, which controls a reported 95% or more of the global market. A single company, better known for food seasoning than microelectronics, sits at the base of one of the most concentrated supply chains in computing, almost singlehandedly supplying a material for hundreds of millions of semiconductor devices. Not surprisingly, demand is now growing beyond what the supply chain can comfortably supply.

Compounding this crunch, modern AI accelerators now pack multiple compute, memory, and supporting components onto a single board. As a result, the substrate is getting larger across the X-Y footprint to accommodate the expanding package. Manufacturers are also adding more build-up layers to the substrate to route the growing number of signals and power connections. Each additional layer requires another ABF layer, further multiplying demand across millions of accelerators and extending manufacturing times.

Unfortunately, the complications don't stop there. Beyond further straining the supply chain, expanding the substrates is creating technical problems, such as warpage, yield issues, and electrical losses within the component itself. This leaves the ABF substrate ecosystem facing two related challenges: producing enough advanced substrates for a rapidly expanding fleet of AI accelerators, while simultaneously re-engineering these substrates so they can continue to scale without becoming unmanufacturable or impractical.

The ABF substrate roadmap is consequently as much about supply-chain capacity as it is about the hardware itself, with suppliers such as Ajinomoto and Ibiden outlining plans to expand material and manufacturing capacity, respectively. At the same time, the wider industry — Intel, Samsung, and SK's Absolics among them — is exploring glass-core substrates and other material technologies to push past the limits of organic ABF.

ABF substrates

Silicon dies, including CPUs and GPUs, cannot communicate directly with the printed circuit board beneath them. The connection pads on a die are spaced micrometers apart, while the traces on a motherboard are spaced hundreds of micrometers to millimeters apart. Every high-performance chip, therefore, sits on an intermediary package substrate — a dense, multilayer board that fans the ultra-fine connections on the die outward into connections large enough for the motherboard to handle, while also providing signal routing, power and ground distribution, and mechanical support for the package.

ABF substrates used in AI accelerators typically consist of a rigid, glass-reinforced resin core sandwiched between successive build-up layers of copper wiring and insulating film. The core provides much of the mechanical rigidity, while the layers provide the increasingly dense wiring required close to the silicon.

To create the substrate, the manufacturer laminates the ABF dielectric onto the structure, forms microscopic vias — commonly with a CO2 laser — and then uses lithography and copper deposition to create a new wiring layer. High-end substrates typically use a semi-additive process (SAP), in which fine copper traces are plated up from a thin conductive seed layer. Another ABF layer is then laminated over it, and the process repeats. The film electrically separates successive copper layers, while plated microvias connect them vertically.

Ajinomoto developed the film in the 1990s, after which it gradually became the industry default for its low dielectric loss, fine-line capability, and smooth lamination. The company reportedly accounts for roughly 95% of the substrate film market, with its nearest competitor, Sekisui Chemical, holding only a low-single-digit share.

The manufacturing tier above the film is more populated but still concentrated. Unimicron, Ibiden, and Shinko together account for roughly three-quarters of the substrate market by most estimates, with AT&S and Nan Ya PCB rounding out the leading group. These companies take ABF and other materials and manufacture the finished multilayer substrate. Semiconductor packaging companies, such as TSMC and Amkor, then integrate those substrates into packages containing the processor, memory, and other components.

AI accelerators are pushing substrates outward and upward

To deliver the compute and memory bandwidth that frontier models demand, the industry is packing ever more silicon onto each AI accelerator. Designers now place multiple large logic dies alongside a growing number of high-bandwidth memory stacks on a single package. Nvidia's Blackwell generation mounts two reticle-sized GPU dies and eight HBM3E stacks on a single package, with its upcoming Rubin and Rubin Ultra parts pushing it further still. TSMC's CoWoS packaging is scaling from around 3.3 reticles — each roughly 830 square millimeters of silicon — a generation ago to 5.5 reticles in volume production in 2026, with a roadmap reaching 9.5 reticles in 2027 and beyond 14 reticles by 2029, when a single package is expected to carry roughly ten compute dies and twenty or more memory stacks.

This expansion of the accelerator package is driving the substrate’s expansion on two physical levels. The first expansion is the substrate's footprint in the X-Y axes. The base has to get wider and longer to accommodate the larger package footprint. Ibiden's current roadmap puts its cutting-edge substrate size at 90 × 90mm (3.54 x 3.54 inches) in 2026, 110 × 110mm (4.33 x 4.33 inches) in 2028, and 130 × 130mm (5.12 x 5.12 inches) and larger from 2030 onward. Ajinomoto independently expects the representative advanced AI packages its film goes into to grow from roughly 100 mm² in 2026 to about 120 mm² for 3D AI packages from 2031.

The second expansion is along the Z axis through additional layers. An expanded collection of compute dies and memory creates more signals to route, while the corresponding increase in power draw requires extensive power and ground distribution, all of which must be carried in a growing number of layers. Ibiden's roadmap targets a 10-X-10 buildup structure in 2026, 12-X-12 in 2028, and 14-X-14 from 2030. Here, the numbers represent the build-up layers on either side of the central substrate core: “10-X-10” means 10 build-up layers per side of the core — which is represented by the “X” — each comprising one dielectric layer (ABF) plus one patterned copper layer, working as a pair.

Nan Ya PCB's roadmap points in the same direction. From an 11+N+11 baseline, it targets 24-layer substrates in 2026 and more than 24 layers in the first half of 2027, while tightening line and space from a 9/12 µm baseline to 8/8 µm and then to 6/7 µm by early 2027. Layer-counting conventions differ between vendors, so a per-side figure and a total layer count don't necessarily line up directly.

The substrate’s expansion in both directions creates several challenges. Increasing the X-Y area makes the package harder to keep flat. Silicon, copper, the substrate core, and the polymer build-up materials that make up the substrate expand by different amounts when heated. As the package is bonded during assembly at around 250⁰C and then cooled, these mismatches cause the layers to pull against one another, leading to warping — a problem that becomes harder to control as package dimensions increase.

Excessive warpage can undermine solder-joint formation, layer-to-layer alignment, and reliability, while a larger substrate also occupies more manufacturing-panel area and exposes more area to potential defects. Organic substrates are reported to lose usable flatness once packages exceed roughly 120mm per side, a threshold that the largest AI accelerators are now reaching and that Ibiden's own roadmap — climbing toward 130mm and beyond — is set to cross.

The growing layer count along the z-axis also creates manufacturing challenges around yield, capacity, and time. Every new substrate layer requires a full manufacturing sequence of several steps, all held to sub-ten-micron tolerances. Each added layer increases the chance of a defect or alignment error that can scrap the whole substrate.

Additionally, layer count consumes manufacturing capacity and time in proportion. This is why Ibiden frames future demand in terms of semi-additive processing load rather than a simple substrate count, as a single advanced substrate now consumes far more of a line's capacity than a finished-unit tally would suggest.

Overall, the simultaneous expansion in substrate area and layer count means ABF consumption is rising much faster than processor shipments alone suggest. Ajinomoto illustrated this in its 2025 integrated report with a larger AI substrate that had about 3.5 times the board area and three times as many ABF layers as a conventional design — 18 layers against six — consuming roughly ten times as much ABF overall. This surging material consumption, set against an extremely concentrated supply base, extends the ABF substrate story beyond a technical problem into a supply-chain constraint.

The supply chain constraint

Like many components in the semiconductor industry chain before the AI boom, demand for ABF substrates periodically swung both ways. A severe bottleneck through 2020-2022 — driven by pandemic-era PC and server demand — was followed by an oversupply in 2023, as substrate manufacturers expanded capacity. However, that capacity was built for low-layer-count, smaller consumer substrates, not the large-body, multi-layer packages AI demands.

These advanced products require sufficiently large manufacturing formats, fine SAP wiring, tight layer registration, acceptable warpage, and high yields across much larger structures. Ibiden captures this by measuring demand not in finished substrates but in semi-additive-process load — the actual processing work each part imposes on a line. Indexing 2024 at 1.0, it expects the SAP load of a single AI-server substrate to reach 1.8 times that in 2026 and 2.5 times in 2028, with the company stating that substrate expansion will push total SAP demand beyond industry supply capacity, indicating a constraint in the manufacturing process itself.

The bottleneck is even tighter at the ABF material level. Ajinomoto's film capacity was already running at full load in the second quarter of 2026, at a reported two million square meters per month, although the company has outlined plans to increase capacity. A near-monopoly supplier at full capacity while consumption surges paints a clear picture of the bottleneck’s severity.

Unsurprisingly, prices have moved accordingly. Ajinomoto notified substrate manufacturers in May 2026 that it would raise ABF film prices by approximately 30%, effective in the third quarter. The hike is coming alongside comparable increases in copper-clad laminates from Resonac and Mitsubishi Gas Chemical, compounding pressure across the whole stack. Further tightening the squeeze, Ajinomoto recently cut shipments of the critical ABF film to China by 30%.

The growing ABF substrate problem cannot simply be attributed to Ajinomoto running out of film. In fact, while it's running at full capacity, the company says it has no concerns about its overall supply chain. The constraint stretches across the entire chain containing ABF, glass cloth, and other materials, SAP equipment, large-format substrate factories, yield, and customer-qualified production capacity.

The immense industry demand is progressively tightening the crunch. Several supply-chain analyses converge on an ABF supply-demand shortfall of roughly 10% in the second half of 2026, widening to around 21% in 2027 and potentially exceeding 40% by 2028, with demand for substrate area projected to grow at a compound annual rate near 39% from 2025 to 2028 as accelerators integrate more components.

The roadmap to recovery: more capacity, better materials

The industry is responding to ABF substrates' multifaceted constraints on multiple fronts: expanding manufacturing capacity to relieve near-term supply pressure while qualifying new materials and substrate architectures to break through the technical limits. Capacity expansion is already underway across the supply chain.

Ibiden is executing ¥500 billion ($3.1 billion) in capital investment across fiscal years 2026 to 2028 — the largest single substrate expansion on record — targeting 2.8 times its 2024 capacity for ASIC and AI-server substrates by 2028. Unimicron raised its 2026 capital spending to a record NT$34 billion ($1.07 billion), with a focus on ABF substrates. Meanwhile, Samsung Electro-Mechanics, Samsung's substrate arm, has committed $1.2 billion to expand ABF substrate production, with volume production expected by the third quarter of 2027.

Pegatron's substrate unit, Kinsus, has approved NT$23.5 billion ($722 million) for ABF equipment over three years and now focuses its most advanced lines almost entirely on AI clients, aiming to lift monthly output at its Taoyuan plant by roughly 25% by 2027. While these projects address the shortage directly, their lead times mean the crunch may continue for a while, as supply cannot respond instantly to the AI demand spike.

Ajinomoto is expanding upstream as well. A new plant in Gunma entered full operation in 2025. The company has invested roughly ¥25 billion ($157 million) in ABF production since 2023 and has said it will invest at least as much again by 2030, targeting a capacity increase of more than 50%. It is also adding a third Japanese base for varnish production — envisioned to provide capacity comparable to Gunma — with construction planned for 2028 and operations to begin in 2032.

However, capacity only solves the problem if the current substrate architecture can continue to scale. The material roadmap — aimed at addressing the physical constraints of ABF substrates — is therefore advancing parallel to the factory roadmap. Ajinomoto says present and future ABF generations are being engineered for larger, more multilayered substrates, high-bandwidth I/O, lower transmission loss, and improved resistance to warpage and humidity. The company expects newer, higher-value ABF grades to take an increasing share of its portfolio through 2030.

Substrate makers are addressing the problem from the process side. Nan Ya plans to move beyond 150 mm body sizes and 24 layers while shrinking copper line/space geometry toward 6/7 microns in the first half of 2027. Its materials roadmap includes an ultra-low-CTE core material with a CTE below 3 ppm/°C, alongside low-Dk, low-Df, and low-CTE dielectrics. Finer wiring allows a substrate to support more connections without relying solely on additional area or layers, while low-expansion materials help keep the growing structure flat.

Eventually, the substrate's central core itself may change to glass. Organic substrate cores are increasingly difficult to keep dimensionally stable as packages approach and surpass 100 mm. Glass can be matched more closely to silicon's thermal expansion — providing dimensional stability — and offers substantially lower dielectric loss for high-speed links. It has therefore emerged as one of the industry's main solutions to warpage.

As we detailed in our glass substrate roadmap, the move to a glass core is drawing a broad field, as it sits at the intersection of substrate-making, glass manufacturing, and advanced packaging, pulling in chip-and-packaging houses, display and glass specialists, and the incumbent substrate makers alike. Intel demonstrated a package that combines EMIB with a glass substrate at NEPCON Japan in January 2026, although the company still places commercial glass-substrate deployment in the latter half of the decade.

SK Group subsidiary Absolics is operating a low-volume glass-substrate manufacturing facility in Covington, Georgia — backed by $100 million in US CHIPS Act funding — producing prototype and qualification samples for customers, such as AMD for its MI400-series accelerators, while Samsung Electro-Mechanics is producing prototypes on a pilot line in Sejong and now plans mass production through its glass-core joint venture after 2027.

TSMC, meanwhile, is pursuing panel-level packaging through its chip-on-panel-on-substrate (CoPoS) platform, moving to a 310 x 310mm panel format, with a pilot line at its VisEra subsidiary, trial production targeted for 2027 and mass production for the second half of 2028. Glass-core substrates are a separate, later step on TSMC's roadmap, with commercial scale projected after 2030. Ibiden also puts “glass core” on its substrate technology roadmap around 2030 as a solution for warpage control.

The glass core — most likely a late-2020s-to-2030s technology — is positioned as a solution to the warpage wall. It replaces the organic core, not the ABF itself, which would remain the buildup material. A glass core may soften ABF demand per package, as glass's flatness allows finer routing and potentially fewer buildup layers, but it does not remove the material or the dependency. There's the possibility that a future dielectric material will eventually replace ABF, although that doesn't seem to be the industry's main focus currently.

Regardless, the near-term roadmap centers on more advanced SAP capacity, rapidly expanding factories, improved materials, and increased supply. Through the late 2020s, finer wiring, lower-loss ABF, lower-CTE materials, and better warpage control will enable organic substrates to stretch toward 110 mm and beyond. Around 2030, glass cores offer a path toward the 130 mm-plus packages that Ibiden and others already have on their roadmaps.

ASML, Intel, Samsung, and TSMC are teaming up to drive the industry transition to 6×12-inch photomasks (reticles). This shift is paramount for High-NA EUV lithography, as the larger stencil would enable printing large chips in a single pass, instead of having to stitch smaller designs together, as ASML explained in a press release this week.

This kind of collaboration between chipmakers isn't entirely unheard of, but it is rare. But when they face an industry-wide challenge, they set aside their rivalry and join forces to move the industry forward. This happened several times in recent decades, first with the failed transition to 450-mm wafers co-funded by GlobalFoundries, IBM, Intel, Samsung, TSMC, and New York State, then with the EUV transition, which was spearheaded by Intel, TSMC, and Samsung.

Higher resolution comes with a nuance

High-NA EUV lithography is a major step forward from today's Low-NA EUV tools. With a numerical aperture of 0.55, High-NA systems can achieve an 8nm single-exposure resolution, compared with 13nm for 0.33-NA EUV scanners. The higher resolution enables chipmakers to pattern smaller, denser features in a single exposure, replacing complex Low-NA EUV multipatterning schemes with a single High-NA exposure. This can reduce the number of masks and process steps, shorten manufacturing cycle times, and potentially improve pattern fidelity and yields, especially on critical layers of next-generation process technologies.

However, this improvement comes with a significant tradeoff. Conventional 0.33-NA EUV uses 4X reduction optics in both directions, which enables a 26×33 mm exposure field with standard 6×6-inch photomasks. By contrast, High-NA EUV uses 4X/8X anamorphic optics, so the same mask can only expose a 26×16.5 mm half-field, which is hardly a problem for client-oriented designs that are barely larger than 429 mm². However, large dies that fit within a conventional 26×33 mm EUV field must now be patterned using two High-NA exposures stitched together, or split into a multi-chiplet design.

Stitching is a workable near-term solution that all chipmakers, including Intel, Samsung, and TSMC, use, but it comes with multiple drawbacks. First, it reduces the throughput of ASML's Twinscan EXE:5200B scanner from up to 175 wafers per hour for half-field exposures to around 125 wafers per hour when stitching is used. Secondly, chip designers must account for the stitching boundary, which means additional design rules and reduced floor planning freedom.

Finally, the two exposures must be aligned with extreme precision so that features crossing the boundary connect properly. Even tiny alignment errors can distort lines and vias, or compromise interconnects and thus potentially create defects and lower yields. Such yield loss is very expensive in the context of large CPUs and GPUs produced using Low-NA EUV systems. If yield is lost on more expensive High-NA EUV tools, the costs will be even higher, which greatly lowers the appeal of using these scanners.

New photomasks are needed

To eliminate the need for stitching, the industry is exploring larger orthogonal 6×12-inch photomasks to compensate for anamorphic optics. By doubling the reticle dimension corresponding to High-NA's 8X reduction direction, these masks are set to restore the traditional 26×33 mm full exposure field and enable even reticle-sized dies to be patterned without stitching.

However, 6×6-inch photomasks have been an industry standard for around three decades since the 1990s. Even the transition from DUV to EUV did not change the basic mask dimensions: EUV replaced transmissive masks with reflective multilayer masks but retained the 6×6-inch substrate form factor. As a result, the adoption of 6×12-inch reticles would require the industry to change the entire mask-making, mask handling, and lithography infrastructure built around the existing format.

Mask-blank suppliers like AGC and Hoya would need new or modified equipment to produce larger substrates and deposit uniform reflective EUV multilayers across a much larger area. Mask shops would need new or modified writers and etch tools to pattern the larger masks, as well as inspection and metrology systems capable of precise characterization of the new format. Cleaning equipment, pellicles, and pellicle-mounting devices would also require modifications.

The mask handling infrastructure would have to change as well. Suppliers would need larger mask pods, while fabs and mask shops would require compatible storage, transport, and automated handling systems. At the same time, they would have to retain support for existing 6×6-inch masks since existing and future Low-NA EUV and DUV scanners will continue to use the established format.

Perhaps the biggest changes would be required from ASML. Its High-NA EUV scanners would need modifications or a redesign to accept, clamp, move, and position the substantially larger reticles with the extreme precision required for EUV lithography.

Intel, Micron, Samsung, SK hynix, TSMC, and other chipmakers planning to adopt High-NA EUV lithography would then have to qualify the new masks, scanners, and other tools for their process flows and ensure that the full-field exposure capability works as intended.

As a result, the adoption of 6×12-inch masks would require a coordinated effort and significant investments from chipmakers, ASML, mask makers, and numerous equipment and materials suppliers.

To make matters more complicated, 6×12-inch masks will not replace the existing 6×6-inch format altogether, as noted above. The industry would therefore have to manufacture, inspect, transport, store, and handle two mask formats in parallel, which will add cost and complexity to an already expensive transition.

Timeline

The transition to 6×12-inch reticles is an industry effort currently supported by ASML, Intel, Samsung, and TSMC. It is going to take years and will happen well after High-NA EUV enters high-volume manufacturing with today's 6×6-inch photomasks, as the semiconductor industry prefers to adopt new technologies gradually.

Intel already uses High-NA EUV scanner(s) for select Intel 18A layers (patterned at Fab D1X) and supports both floorplanning within the half-field and stitching; Samsung plans to introduce High-NA EUV into DRAM high-volume manufacturing by 2028, and TSMC intends to deploy the technology for advanced-node production starting in 2030. All three companies plan to start High-NA EUV adoption with 6×6-inch masks.

Intel seems to be leading the pack with 6×12-inch reticles as it has been working for three years to make them a reality, but the company remains tight-lipped about the timing of its adoption of the new photomasks. Meanwhile, the ASML-TSMC initiative targets a 6×12-inch photomask pilot line by 2031, which should provide the foundry with a platform to develop and qualify the new mask format and associated manufacturing infrastructure. The ultimate target is full lithography-system readiness for advanced-node production by 2033.

That said, 6×6-inch and 6×12-inch photomasks for High-NA EUV patterning will likely co-exist on the market at least for some time rather than undergo an abrupt transition. At the end of the day, square 6×6-inch reticles that enable High-NA EUV scanners to expose fields as large as 26×16.5 mm (or 429 mm²) should be sufficient for the vast majority of client processors produced in the coming years. Larger 6×12-inch masks will matter primarily for much bigger designs, such as high-end AI accelerators, data center CPUs, DPUs, high-end GPUs, and FPGAs, where the ability to expose a full 26×33 mm field without stitching becomes considerably more valuable.

For years, TSMC has tried to avoid making public comments about its plans to use EUV lithography with a 0.55 numerical aperture optics, or High-NA EUV, because the company's developers had a good idea how to keep advancing process technologies without using $400 million scanners. However, TSMC cannot rely on Low-NA EUV systems forever, so this week the company announced plans to use High-NA EUV starting from 2030.

TSMC did not formally reveal which fabrication technology will be the first to adopt High-NA EUV, though the year 2030 points to a few candidates. What TSMC did say is that it expects the number of layers processed using High-NA EUV to eventually increase as its fabrication technologies become more complex, driven by increasing complexity of transistor architectures, which is probably an implication for more sophisticated implementations of gate-all-around (GAA) transistors as well as complementary field-effect transistors (CFETs) later on.

TSMC plans to start using High-NA EUV lithography tools for high-volume manufacturing in 2030 using conventional 6×6-inch photomasks. The company then plans to build a pilot line that uses 6×12-inch photomasks in 2031 with the goal of bringing 6×12-inch High-NA lithography systems into advanced node production by 2033.

High-NA EUV lithography tools can achieve an 8nm single-exposure resolution, as opposed to a 13nm single-exposure resolution offered by today's Low-NA EUV litho systems. However, when used with conventional 6×6-inch photomasks, High-NA EUV scanners have only half the exposure field of their Low-NA counterparts, which creates challenges for manufacturing very large dies. As a result, chipmakers building massive AI accelerators must either stitch multiple exposure fields together or adopt multi-chiplet designs, two approaches that have their own other challenges, such as tool productivity and power consumption. To circumvent the 6×6-inch photomask limitations, TSMC is working with ASML to set the stage for 6×12-inch photomasks.

Changing the size of photomasks is not a trivial endeavor as it requires changing everything from EDA software to tools that produce and write masks as well as systems that handle them, which essentially means that the entire industry must work on this change. ASML seems to be optimistic about the transition as it is supported not only by Intel and TSMC, but also by Samsung.

"We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips," said Christophe Fouquet, president & CEO, ASML. "We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative."

Perhaps the biggest intrigue about TSMC's usage of High-NA EUV lithography is which process technology will be the first to use the new systems. Based on what we know about TSMC's roadmap, A10 or A11 (1/1.1nm-class) seems to be by far the strongest candidates to use High-NA EUV scanners for the most critical layers. TSMC's latest strategy separates its roadmap into annual client-oriented nodes (N2, N2P, N2X, A14, A13) and roughly biennial high-performance nodes (A16 in 2027, then A12 in 2029). The company has already confirmed that A12 and A13, due in 2029, will continue to rely on conventional EUV lithography.

Since A13 is an optical shrink of A14 that increases transistor density by only 6%, with performance and power improvements yet to be disclosed, its successor in 2030 will likely have to deliver considerably more substantial gains. It is therefore reasonable to expect A13’s successor — whether it is called A11 or A10 — to adopt more advanced lithography and/or TSMC's 3^rd Generation nanosheet GAA transistors to deliver significantly higher transistor density as well as meaningful performance and power improvements over its predecessor. Yet, we are of course speculating.

A 52-year-old Belgian-Chinese man has been arrested on suspicion of espionage for allegedly transferring specialized semiconductor intellectual property and trade secrets from Belgian chipmaker BelGaN, where he worked, to China. According to an AP News report citing details released by Belgium's federal prosecutor’s office on September 7, the Beijing-born Belgian resident was taken into custody on May 10 at a Brussels airport while attempting to board a flight to China.

The suspect — identified by Belgian media only as H.L. — previously held a senior research position at the now-defunct BelGaN, which specialized in gallium nitride (GaN) semiconductors. Investigators suspect he was concurrently leading a Chinese chip firm, GanKool, which was developing the exact same specialized gallium nitride chip technology as BelGaN. The company was established only a few months after H.L. joined BelGaN and was financed by a Chinese investment fund. The suspect now faces charges of industrial espionage, membership in a criminal organization, misuse of company assets, and unlawful disclosure of business secrets.

The espionage allegations emerged from an investigation into BelGaN's collapse. When the company collapsed into bankruptcy in the summer of 2024, Belgian authorities launched a routine financial probe into the failure. Investigators eventually uncovered highly unusual corporate activity. Instead of trying to keep BelGaN financially viable, the managers and the researcher may have actively tried to make the Belgian company “disappear” after transferring its proprietary knowledge. This led to further investigations that revealed GanKool’s existence and its connections to BelGaN.

In addition to the researcher’s role, the investigators also found evidence linking BelGaN's last CEO, a Chinese national, to the same Chinese rival. The prosecutors have said a second suspect remains at large, with Belgian media speculating that the CEO is the suspect.

The incident highlights the increasingly intense competition over technology and intellectual property in the semiconductor industry, particularly as China pushes to reduce its reliance on foreign chip technology while the U.S. continues to restrict its access to advanced processors and semiconductor manufacturing equipment. Just last month, South Korean court documents accused Chinese memory maker CXMT of using a detailed “Project Hefei” roadmap to obtain Samsung's proprietary DRAM technology, including a 620-step process recipe. A former Samsung engineer has already been sentenced to seven years in prison over the scheme.

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.

One million High-NA wafers

Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.

Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.

Sticking to stitching

Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.

Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.

6×12 mask effort progressing

To avoid using stitching, the industry — led by Intel — plans to shift to larger 6×12 masks, which will enable a 26×33 mm full field in one exposure. While this looks easy on paper, make the mask twice as long, changing the mask represents an enormous ecosystem change.

Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.

It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.

Being the world's largest contract chipmaker has its advantages for TSMC when it comes to negotiations with suppliers, as it naturally buys far more than others. However, it also has its difficulties because its requirements are dramatically larger than those of other foundries, and when they grow further, it gets exceedingly hard to source what it needs. Especially when its requirements increase nearly 2X in less than a year.

TSMC has nearly doubled its projected requirements for semiconductor production equipment since the end of last year as the foundry expands manufacturing capacity to address surging demand from the AI sector, said Cliff Hou, TSMC's deputy co-chief operating officer, during a fireside chat at Semicon Taiwan, reports FocusTaiwan. The world's largest foundry admits that it cannot meet all demand from all customers, though it is trying to catch up, according to Bloomberg.

TSMC makes projections about the number of tools it needs to purchase over the following year as well as its spending. After making that assessment late last year, the company discovered that by the end of the first quarter, the requirement had increased to 1.5 times that projection, and by July it had climbed to 1.9 times the original estimate, which means that TSMC's equipment needs had almost doubled in about six months.

TSMC itself attributes its increased needs to the number of new fabs that it is building in Taiwan and the U.S., though it should be noted that in addition to brand-new fabs, the company is also upgrading existing ones, which also need new machinery.

Interestingly, tool count does not seem to be proportional to tool cost. While TSMC increased its 2026 capital expenditure (CapEx) budget significantly in the recent eight months, it increased nowhere near 90%. Back in January, it guided 2026 CapEx to be from $52 billion to $56 billion. By April, it moved its estimate towards the high end of the original guidance, but in July it officially increased it to the range between $60 billion and $64 billion, or by around 15% if we only consider midpoints.

How exactly TSMC makes assessments about the number of tools it needs to buy the following year is something that remains to be seen, but perhaps a more pressing question for the industry is how it plans to acquire that equipment considering shortages of wafer fab tools due to massive demand from virtually all chipmakers.

Hybrid bonding, the copper-to-copper joining technique that replaces solder microbumps in 3D chip stacks, is in high-volume production on logic chips and has just been postponed for use with memory. TSMC has scaled its SoIC bond pitch from 9 microns to 6 and laid out a path to 4.5 by 2029; Intel began shipping Foveros Direct hybrid bonding in its Clearwater Forest server CPU in the first half of 2026, and AMD has used the technology in volume since the first 3D V-Cache parts. However, a JEDEC decision earlier this year to raise the HBM stack-height limit lets HBM4 stay on the less sophisticated and expense microbump technology, deferring hybrid bonding's arrival in high-bandwidth memory, and is now set to debut in HBM4E and HBM5 at the end of the decade.

The technique works by polishing two dies flat, then bonding their copper pads and surrounding dielectric directly under heat and pressure, with no solder bump in between. Because there’s no bump to collapse, the connections can be packed far tighter. AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking, and figures presented at TSMC's 2026 technology symposium put face-to-face hybrid bonding at around 14,000 signals per square millimeter against roughly 1,500 for face-to-back through-silicon-via stacking.

Wafer-to-wafer, die-to-wafer, and throughput

Microbumps have historically run at pitches around 40 microns, tightening toward 10 for the latest memory. Hybrid bonding, however, starts where microbumps end and keeps scaling: the leading edge is at 6 microns now, with 4.5- and 3-micron generations in development and sub-micron pitches demonstrated in research. Each step down multiplies the number of vertical connections between stacked dies, allowing a cache die or a compute tile to behave as if it were part of the chip rather than a separate component wired across a package.

The method is split into two different approaches: wafer-to-wafer and die-to-wafer. Wafer-to-wafer bonding joins two full patterned wafers face-to-face and dices them afterward, which allows the tightest pitch and fastest production because alignment happens once at the wafer scale. Imec and EV Group demonstrated a 200-nanometer wafer-to-wafer pitch with post-bond overlay below 40 nanometers at ECTC in May. The constraint here is that both wafers must carry identically sized dies, and every die gets bonded, including defective ones, so a single bad die on either wafer ruins the pair.

In contrast, die-to-wafer bonding places individual, pre-tested dies onto a wafer — which is what chiplet and HBM stacks require — because it allows known-good-die selection and the mixing of different die sizes and process nodes. There’s a penalty in terms of throughput with die-to-wafer as each die is picked, aligned, and placed in sequence rather than in one wafer-scale step.

The best die-to-wafer pitch shown at ECTC 2026, from CEA-Leti, was 1 micron, roughly five times looser than the wafer-to-wafer record. Because the dies are placed one at a time, the speed the bonder runs at sets the limit on how many chips it can produce. Applied Materials and Besi cite around 1,600 die placements per hour on the Kinex platform, and Besi's Chameo bonders are rated near 2,000 chips per hour, with the next generation aiming for 50-nanometer placement accuracy to reach finer pitches.

Hybrid bonding is difficult to achieve, as two surfaces have to be almost perfectly flat and clean. The dielectric holds on contact through van der Waals forces, so the polished surface can vary by no more than around 0.2 nanometers, and the copper pads have to sit a few nanometers below it, close enough that they swell into contact when the stack is heated to 200 to 300℃. A single particle smaller than a micron holds the surfaces apart and leaves a gap spanning many pads at once. So keeping the wafer clean and flat through the polishing step (known as chemical-mechanical planarization) is critical for good yields.

TSMC SoIC and Intel Foveros Direct

In terms of who’s leading hybrid bonding, TSMC’s System on Integrated Chips (SoIC) platform leads in terms of volume. At its 2026 North American Technology Symposium, the company laid out a pitch roadmap moving from 9 microns in 2023 to 6 microns in 2025 and 4.5 microns by 2029, with second-gen SoIC adding face-to-face bonding on top of the face-to-back stacking that the first generation supported. The node-stacking roadmap runs in parallel, from N3P-on-N4 today toward N2P-on-N2P by 2028 and A14-on-A14 by 2029.

With SoIC, the hybrid-bonded stack is built first as a vertical block, then placed into a CoWoS module alongside HBM on a silicon interposer, a combination the industry calls 3.5D. AMD's MI300 is the reference case, stacking compute and I/O dies by hybrid bonding before the assembly is mounted in CoWoS with its memory. SoIC handles the front-end vertical density; CoWoS handles the back-end lateral integration with memory.

Capacity is slowly growing, with TSMC building out its Chiayi AP7 site as its largest advanced-packaging campus. Output is targeted for 2026, and analysts at TrendForce have estimated SoIC capacity roughly doubling year on year from a few thousand wafers a month in 2024. Customers include AMD, whose 3D V-Cache and MI300 accelerators were the first volume SoIC products, and the Broadcom-built Fujitsu Monaka CPU.

Meanwhile, Intel's hybrid-bonding implementation, Foveros Direct, reached high volume with Clearwater Forest, the Xeon 6+ server processor built on the 18A node and demo’d at MWC back in March. The design uses a 9-micron copper-to-copper pitch to bond compute and I/O tiles onto base tiles that act as an active interposer, and Intel has described a second generation targeting a 3-micron pitch. Enabling that on a leading-edge logic node required a dedicated process variant, 18A-PT, which adds the through-silicon vias (TSVs) and bonding support that standard 18A doesn’t carry. The shift from Intel's earlier Foveros, which used solder microbumps across the Ponte Vecchio GPU's chiplets, to direct copper bonding is a generational change now playing out across its server offerings.

The unexpected HBM delay

The widely held assumption was that HBM, the stacked DRAM that sits beside every AI accelerator, would be hybrid bonding's largest market by volume. That changed back in January when JEDEC raised the HBM package height limit from 720 to 775 microns, and the extra room means 16-high HBM4 stacks can be assembled with microbumps after all. With HBM4 pad pitch at 10 microns, reporting from SemiEngineering noted that moving to hybrid bonding at that pitch wouldn’t yet make economic sense.

SK hynix has reflected that logic in its own planning, reportedly sticking with advanced mass-reflow molded underfill for 16-high HBM4 while keeping hybrid bonding as a backup and continuing to validate 12-high hybrid-bonded samples for later generations. The company demonstrated a 16-layer HBM4 sample at CES 2026, built without the all-hybrid bonding many expected the generation to require. The result pushes hybrid bonding's HBM debut toward HBM4E and HBM5, expected around 2027 to the end of the decade, where taller stacks and tighter pitches finally make the older bonding methods run out of room.

Meanwhile, the memory makers are building the packaging capacity regardless. SK hynix is investing $3.87 billion in an advanced-packaging plant in Indiana, with production targeted for 2028, and Micron broke ground on a $7 billion HBM advanced-packaging facility in Singapore early last year, with output expected around 2027. Those plants are sized for the volumes hybrid bonding will eventually carry, even as the first HBM4 generation ships on the older interconnect, meaning the equipment commitments are running ahead of the technology's confirmed deployment date in memory.

Samsung is doing the same thing from the memory side. Its SAINT packaging family includes SAINT-D, which stacks DRAM directly on a logic die, and the company has discussed a bufferless HBM4 design that removes the separate base die, with custom HBM logic dies reportedly moving to its 2nm foundry process for 2027 samples. At GTC in March, Samsung claimed hybrid bonding cuts thermal resistance by more than 20% against thermocompression bonding.

Another drag on the timeline is intellectual property. Adeia, which holds a large portfolio of bonding patents, sued AMD last year, alleging that the hybrid bonding behind 3D V-Cache infringes 10 of its patents.

China is pursuing the technique as a way around its lack of access to cutting-edge lithography. With SMIC limited to 14nm-class production and cut off from next-gen EUV, domestic researchers have identified 3D hybrid bonding as a route to competitive performance by stacking older logic and DRAM, with public claims of 14nm parts paired with domestic DRAM aimed at rivaling far newer GPUs. Given that it’s China we’re talking about here, those claims remain claims, and no foundry has demonstrated mass production of hybrid-bonded logic memory in China.

A scramble for tools

In terms of tooling, Applied Materials and Besi, partners on hybrid-bonding equipment since 2020, launched their Kinex die-to-wafer bonding system late last year, billed as the first fully integrated die-to-wafer hybrid bonder combining surface preparation, bonding, and metrology. Applied Materials has taken an equity stake in Besi, and reports from March placed Besi at the center of takeover interest from both Lam Research and Applied Materials, an indication of how important the bonding-tool market has become as logic adoption ramps and memory adoption is staged behind it.

Analyst tracking put Besi’s hybrid-bonding revenue on a path toward roughly €476 million by 2026, up from about €36 million in 2023, with second-half 2025 orders rising more than 60% against the first half on early HBM4 production-line bookings. Competing tool vendors are moving in alongside it: ASMPT has partnered with EV Group on hybrid bonding, and SK hynix is working with Hanwha Semitech on bonders targeting a commercial HBM launch in 2027. The sheer scale of this equipment build-out is a clear demonstration that the industry is treating hybrid bonding as an inevitability, even where the products that’ll use it are still years out.

Hybrid bonding is already in volume production, but its capability is outpacing its adoption. TSMC offers 6-micron pitch while its newest disclosed customer ships at 9; Intel ships at 9 with 3 on the roadmap; and the memory market that was meant to consume it in quantity has bought itself one more generation on microbumps. Two things will show where it goes next — whether any leading logic product drops below 9 microns in volume, and whether HBM4E marks hybrid bonding's first real use in memory before the end of the decade.

China's ability to produce lithography tools is comparable to that of market leader ASML sometime in 2004, an analyst with UBS wrote in a note to clients. The situation may change in the next two or five years when Chinese companies start producing immersion DUV lithography systems in mass quantities, and Chinese chipmakers begin to deploy them for production of actual chips. However, China's semiconductor industry will remain well behind Western industry. "They seem to be at a similar stage to ASML in 2004," wrote Francois-Xavier Bouvignies, an analyst with UBS, in a note for clients, reports Bloomberg.

For years, China's pursuit of semiconductor self-sufficiency stemmed from its ability to produce mainstream chips on trailing nodes using fairly advanced, though not the latest, tools from leading producers such as ASML, KLA, and Lam Research. In recent years, China found itself in a new reality in which it could no longer obtain the latest chipmaking tools and had to build them domestically. Although companies like ACM Research, AMEC, and Naura have developed world-class chemical wafer deposition, cleaning, etching, and oxidation/diffusion tools that are now mass-produced and used by Chinese chipmakers, none of the Chinese companies have managed to develop a competitive lithography machine that can be used to make chips on more or less modern nodes and initiate its mass production.

Photolithography is generally considered the most technologically complex and demanding individual process in advanced semiconductor manufacturing. Firstly, lithography systems themselves are extraordinarily complex and contain tens of thousands of individual components. Secondly, the required positional accuracy is extraordinary, as a modern lithography scanner needs excellent resolution, overlay, focus control, scanner-to-scanner matching, CD uniformity, and line edge roughness, just to name some of the requirements. Finally, a competitive litho system must guarantee predictable uptime, defect density, and performance. Perhaps the key thing here is that all of the required features must be achieved without compromises, as, for example, a machine with high resolution and ideal uniformity that can process one wafer per hour cannot be used for mass production.

Historically, over a dozen companies produced lithography tools. However, as they became more complex, only ASML, Canon, and Nikon survived, with ASML being the undisputed market leader and the only maker of EUV lithography scanners.

As China is essentially developing a parallel semiconductor ecosystem, there have been reports of multiple entities working on lithography systems, including Shanghai Micro Electronics Equipment (SMEE), AMIES (which seems to be a SMEE spin-off that includes Aishengna and Yuliangsheng units), SiCarrier (reportedly controlled by Huawei), and even Naura (which denies that it is developing litho tools). SMEE, which was established in 2002, is by far the most important established Chinese manufacturer of litho tools. Meanwhile, so far none of China-based makers of lithography have established mass production of immersion DUV scanners capable of producing chips at 45nm and below.

SMEE reportedly formally introduced its first immersion DUV lithography system called SSA/800-10W and capable of making chips on nodes down to 28nm back in 2023. However, there have been no evidence that SMEE has indeed started mass production of the SSA/800-10W and that it has been adopted by a single manufacturer for mass production of chips. While it is conceivable that not all chipmakers announce deployment of breakthrough tools, especially keeping in mind that Chinese vendors like SMEE have plenty of foreign suppliers, we would have seen at least some indirect evidence (starting from procurement/acceptance records as well as component orders all the way to job postings and scientific papers) that SMEE started shipments of the SSA/800-10W in 2023 – 2024 by now, assuming of course that there were any shipments.

Interestingly, but the reports about China-made immersion DUV scanners now mass-produced by Shanghai Aishengna Electronic Technology Group (a unit, or an affiliate of SMEE) re-emerged this July, again, without any evidence. This time around, the reports did not even mention targeted nodes or throughput capabilities. To make matters even more suspicious is the lack of reports about shipments of evaluation tools to chipmakers (like ASML does this with its High-NA EUV machines) as well as preliminary results of their process qualifications (like Intel does with ASML's High-NA EUV machines).

For a first-ever Chinese immersion scanner, it is reasonable to expect Chinese chipmakers to use it on engineering wafers, characterize it against ASML machines, develop recipes, identify drawbacks, and pass that information back to SMEE, something that should take about a year. Only once that first machine performs adequately does it make sense to order and qualify multiple SSA/800-10W units for mass production. In fact, such qualification will likely take another year for a single layer and more time for additional layers. To that end, an insertion of an all-new lithography scanner into an existing flow will take at least two years, but likely more. To that end, once SMEE (or its business units) and its customers figure out how the first Chinese immersion scanner should work, these scanners will still be far from mass deployment.

In any case, without any real indicators that Chinese makers of wafer fab tools can produce and ship immersion lithography scanners to customers, we can only state what the UBS analyst did: China's lithography industry is in a position where ASML was in the mid-2000s.

Samsung has unveiled a three-phase roadmap to progressively transform high-bandwidth memory (HBM) into an integrated memory-and-compute system, culminating in the company's zHBM architecture, which places the processor directly beneath the DRAM stack and eliminates the conventional 2.5D interposer link between the two. Detailing the roadmap at Hot Chips 2026, Samsung's Sangwook Han, of the company's DRAM design team, identified the base die as the key enabler of the evolution, which began with the company’s decision to manufacture the HBM base die on an advanced logic process.

In conventional HBM, the base die (B-die) was fabricated on the same DRAM process node as the core dies (C-dies) in the stack above. Starting with HBM4, Samsung moved the base die to a 4nm logic process, primarily to reduce power draw and minimize die area. Additionally, it gave Samsung a much more capable piece of silicon.

The company contends that a die built on the same class of logic process as XPUs could do much more than serve as a data interface. Samsung now plans to progressively offload more functions into the base die, eventually removing the physical gap between memory and the XPU entirely.

The current state of HBM and its growing constraints

The current HBM architecture comprises multiple DRAM core dies stacked vertically on a base die and connected through thousands of TSVs. The stack sits beside an XPU on an interposer, with the base die bridging the memory and compute silicon.

Bandwidth has been the main driver of HBM’s evolution. The current HBM4 stack has roughly 1 to 5 TB/s of bandwidth obtained through 1,000 to 2,000 I/Os running at about 8 to 16 Gbps each. These figures are expected to rise with upcoming HBM generations. The problem is that conventional ways of scaling bandwidth present significant challenges.

TSV signaling speed is difficult to increase, so HBM generations have added more TSVs instead. However, this consumes area and forces tighter TSV pitches. The PHY has also grown more demanding. HBM4 doubled the data I/O count from 1,024 to 2,048 DQs, and signaling speed keeps rising. Power is an even bigger issue. While energy per bit is improving, total HBM power continues to rise as bandwidth is scaling faster. Samsung says this is why HBM4 moves the base die to an advanced logic process, as the denser, more efficient logic reduces power draw.

This move underpins and enables the three-phase plan. An advanced logic node shrinks the interface circuitry while enabling the HBM base die to perform functions previously handled by the processor. Samsung calls this direction custom HBM, or cHBM, which keeps the conventional DRAM stack but customizes the logic underneath it for a specific accelerator.

Phase 1: Reclaim XPU area

The first phase is about handing processor area back to compute in what Samsung calls “XPU area reclamation.” AI accelerators are hitting familiar scaling walls, such as slowing process scaling and dies pressing against reticle and interposer limits. To expand compute, Samsung plans to evict non-compute blocks, moving their functions to the base die’s underutilized silicon.

The first target is the HBM Physical Interface (PHY), one of the largest blocks on the base die. Samsung proposes replacing the traditional interface with a much smaller die-to-die (D2D) link. On an 11 × 12.8mm HBM4 base die, the conventional PHY occupies more than 8 × 4mm, while the custom HBM D2D block is about 8.5 × 1.5mm, with channel depth cut from 5.5mm to 2mm. Because the matching interface on the XPU shrinks too, Samsung also reclaims processor silicon.

Conversely, shrinking the same power into less silicon increases power density and creates hotspots. Samsung’s answer is a Heat Path Block (HPB) that provides an alternative route for heat to exit the concentrated interface region. The company says an HPB covering more than half of the PHY can slash peak temperature by more than 35%.

The bigger Phase 1 change is moving the memory controller from the XPU to the custom HBM base die. Han estimated controllers account for 5 to 10% of an XPU's area — space that, refilled with compute, could yield a 10–20% performance gain. Moving the controller next to memory also enables a new SRAM-based repair scheme in which failed C-die addresses can be redirected to SRAM on the base die, avoiding the need to sacrifice an entire spare row or column for a single defective cell.

Phase 2: Making the die a more useful smart memory subsystem

Even with the controller moved in, Samsung says a substantial portion of the base-die area remains unused. Phase 2 fills that space with more functions, first with some relatively straightforward additions. The company proposes SoC-like telemetry and reliability features, including thermal, voltage, process, and aging sensors, as well as more advanced self-test hardware.

It also wants to use the edge of the base die for direct memory expansion, arguing that capacity is becoming as important as bandwidth. Dedicated controllers and PHYs could connect a secondary tier of external memory directly to custom HBM, rather than going through conventional PCIe expansion. Han said that extra memory could be LPDDR or even HBM, offering higher bandwidth and lower latency than PCIe-based memory extension.

Last in Phase 2 is compute — right on the base die. Samsung wants to place selected processing elements (PEs) under the DRAM, offloading memory-bound work while compute-heavy operations remain on the GPU. It calls this broader 2.5D architecture advanced HBM (aHBM), citing benefits such as less traffic across the interposer and reduced latency and I/O power draw.

Phase 3: zHBM goes fully 3D, placing the processor underneath the memory

Phase 3 appears to be Samsung's most radical step, with the company halting HBM architecture optimization and rebuilding it instead. Introducing zHBM, Samsung's “ultimate solution” for maximizing bandwidth under future AI's brutal power limits.

The zHBM concept eliminates the conventional side-by-side arrangement of XPU and HBM across an interposer. Instead, the processor sits directly beneath the DRAM stack in a true 3D structure. This architecture allows Samsung to replace the large edge PHY with distributed I/Os spread across the die. Data no longer has to travel laterally across an interposer, thereby shortening the physical path and eliminating the need for conventional HBM PHY and D2D link interfaces.

Samsung says the biggest payoff is power. Its projections show zHBM cutting I/O power by around 70% compared with HBM5. In another example, Samsung models roughly 2.3X more DRAM bandwidth while reducing memory power by about 100W compared to a four-stack HBM4E system.

On the flip side, thermals are the obvious complication. Han said Samsung is targeting roughly four-high zHBM stacks, compared with the much taller 12-high or 16-high configurations possible with conventional HBM, specifically because of heat. Distributed I/O helps by spreading the circuitry rather than concentrating it into hotspots, but zHBM is a balancing act involving capacity, bandwidth, heat, and physical integration.

Manufacturing zHBM will also require advanced wafer-on-wafer bonding and hybrid copper bonding to meet the required I/O density, with a much tighter co-design process between the DRAM and SoC teams. Samsung did not provide a firm launch date or timeline for the phases. However, HBM4’s 4nm logic base die is the concrete starting point, while cHBM and aHBM are nearer-term extensions, with zHBM as the long-term endpoint.

A team of scientists in Germany and Japan has demonstrated a solid-state cooling system that uses heat to generate the mechanical work required for refrigeration, potentially opening a route to processors and data centers that recycle some of their own waste heat for cooling. Developed by researchers at the Karlsruhe Institute of Technology (KIT) and the University of Tsukuba, the system — detailed in Nature Energy on August 28 — replaces the electrically powered actuator normally required for elastocaloric cooling with a heat-responsive shape-memory alloy, allowing the cooling cycle to run from an external heat source rather than a motor.

The prototype combines two ultra-thin metal films that serve as an actuator and a refrigerant. A 22-micrometer titanium-nickel (TiNi) shape-memory film contracts when heated, converting thermal energy into mechanical motion. This motion stretches and releases a 26.5-micrometer titanium-nickel-iron (TiNiFe) refrigerant film, triggering a reversible phase transition that produces cooling. In laboratory tests, Joule heating the actuator to 86°C produced a 12.9 K temperature span across the refrigerant film — the difference between its hottest and coldest states during the cooling cycle — and a 4.0 K span across the assembled cooling device, measured between its hot and cold sides. When the researchers replaced the resistance heating with an external 130°C heat source, the prototype still maintained a 2.2 K device-level temperature span, demonstrating that an external thermal source could drive the cooling mechanism.

Conventional refrigeration and air conditioning systems mostly use vapor-compression cooling. A compressor raises the pressure and temperature of a refrigerant, which then dumps heat in a condenser before expanding and evaporating at low pressure to absorb heat from the space being cooled. The technology is mature and efficient, but requires an electrically driven compressor and relies on refrigerants with significant global warming potential.

Solid-state cooling moves heat without the conventional compressor-and-refrigerant loop. Thermoelectric coolers, for example, use electrical current to create a temperature difference across semiconductor materials and are already common in compact electronics. However, the researchers note that thermoelectric devices typically reach only 10% to 15% of the theoretical reversed-Carnot efficiency limit, roughly one-quarter that of modern vapor-compression systems.

Elastocaloric cooling takes a different route. Certain shape-memory alloys change crystal structure when mechanically loaded and unloaded. Applying stress induces a phase transition that releases latent heat and warms the material. Once that heat is rejected, releasing the load reverses the transition, causing the material to absorb heat and cool. The solid alloy effectively becomes the refrigerant.

The problem is that the material still has to be repeatedly stretched and released. Existing elastocaloric systems generally use motors, hydraulic systems, or electromechanical actuators to provide the required force, adding electrical consumption, bulk, and mechanical complexity — particularly troublesome for miniature coolers. Instead, the KIT-Tsukuba team made one shape-memory alloy drive another. Heating the TiNi actuator film causes it to recover its original shape and contract. Mechanically coupled to the TiNiFe refrigerant film, that contraction supplies the force required for the cooling cycle. As the actuator heats and cools, it loads and unloads the refrigerant without an electric motor.

Broken down further, the system works as follows: the researchers take a shape-memory alloy (TiNiFe refrigerant film) that cools when released after being stretched. Instead of using a mechanical system to repeatedly stretch and release that alloy, they use another shape-memory alloy (TiNi) that contracts when heated and mechanically couple it to its cooling counterpart. When the TiNi is heated, it contracts, stretching and “loading” the refrigerant film. Once the heat is removed, the TiNi relaxes, releasing the film and triggering the phase transition that causes it to cool. Under cyclic heating, the TiNi alloy therefore provides the repeated stretching and releasing motion the TiNiFe requires for elastocaloric cooling.

The thermal actuator delivered a force-to-displacement ratio of 14.5 N/mm, compared with 1.1 N/mm for a commercial electromechanical actuator the researchers used as a reference. The thin films also provide a high surface-to-volume ratio for rapid heat transfer. Under Joule-heated actuation, the integrated device reached a steady 4.0 K temperature span after 20 cycles and a specific cooling power of 4.43 W/g. When driven from the external heat source, those figures fell to 2.2 K and 3.32 W/g, respectively.

This external-heat result is the real proof of concept. While the technology is still an early-stage laboratory experiment, a scaled, perfected version could have interesting implications. Typically, the heat the system needs to operate is generated from electricity or another form of energy. However, an ideal scenario would be to repurpose existing waste heat — a setup already attainable in data centers. Therefore, the technology has the potential to cool processors using the heat they generate!

However, applying it as a data center cooling technology is far from the technology's current state. The prototype produced just 2.09 milliwatts of cooling power at zero temperature lift. That is nowhere near the heat loads of modern processors, much less AI accelerators or data-center racks. The researchers also cite relatively slow actuation, limited strain rate, and the current heat-exchanger geometry among the factors constraining performance. There also needs to be a way to make the heating cyclical.

The team is now working to connect multiple films in parallel to increase cooling capacity. Further progress will require scaling the active material, improving heat transfer and operating frequency, and proving long-term durability. For now, the researchers have demonstrated the underlying energy chain in which heat can be converted into mechanical motion, and that motion can be turned into useful cooling without an electric motor driving the refrigeration cycle.

Micron Taiwan faces a potential strike as support for this labor action is increasing among its workers. Local media reports that a preliminary survey showed 80% of the people involved support such a move, with its labor union demanding that the current bonus system be replaced with a profit-sharing scheme, similar to what SK hynix employees receive. Micron, alongside Samsung and SK hynix, have been raking in a lot of cash because of the AI-driven memory chip shortage, and its workers want a piece of the action.

“Unions say peers offer far higher profit-based bonuses, with Samsung paying out 10.5% of profits and SK Hynix 10%,” Dan Nystedt said on X. “Formal mediation talks are expected to begin by mid-September at the latest, a mandatory requirement before an official strike vote can be held under Taiwan law.”

Earlier this year, Samsung narrowly avoided a strike after it agreed to a deal that gave its foundry workers bonuses that could go as high as $400,000 per employee. It seems that Micron Taiwan’s labor union is following suit, especially as the company’s last earnings call reported a revenue of $41.46 billion and a net income of $28.24 billion, with its Cloud Memory Business Unit, which provides high-bandwidth memory (HBM) to data center customers, accounting for more than 33% of the total revenue.

It’s unclear if Micron workers from other parts of the world will be affected by any deal made in Taiwan, but 60% of its global production capacity is centered around the island, with most of its HBM output coming from its facilities there. With the two sides beginning talks in September, we have yet to see what kind of deal they will reach. But given how lucrative the data center boom has been for the memory industry and the precedent set by workers at Samsung and SK hynix, it’s likely that they will have comparable demands.

While we’re unsure how much bonuses the workers in Taiwan will get, it’s likely that management will negotiate as production disruptions could mean massive losses for the company. Nevertheless, it would also raise complications for workers in other countries, as it could build jealousy and resentment among other workers who will not be part of the bargain, similar to what some Samsung workers are experiencing with the recently closed labor deal.

Intel's confidence in its 14A (1.4nm-class) fabrication process is rising as defect density drops. The company's own design teams are at work developing products that will use the technology, while external customers are now asking about 14A volumes Intel can get them, according to David Zinsner, chief financial officer of Intel, who spoke at Deustche Bank's 2026 Technology Conference. The CFO went as far as saying that 14A is Intel's best process since 22nm technology from the 2010's. But while the comment is optimistic, there is a caveat.

"When you look at the defect density, 14A is tracking better than the target curve we had for 14A," Zinsner said at Deutsche Bank's 2026 Technology Conference. "It is also doing better than any of the previous nodes in terms of how quickly we are bringing down the defects. In fact, we have not seen this performance since 22nm, which is arguably one of the best nodes Intel has ever put out."

Intel intends to begin risk production of its own products on 14A fabrication process in the second half of 2027 and then initiate its high-volume manufacturing in 2028, so 14A is two years away from mass production. So, what Intel's CFO said at the conference is that at this point in 14A's development, its defect reduction trajectory looks at least as healthy as the trajectory of the company's exceptionally successful 22nm process at a comparable point in its development (i.e., in 2010). There are a couple of catches with such phrasing, though. Firstly, the defect density on 14A now is not necessarily equivalent to a defect density on 22nm two years away from mass production. Secondly, due to advances of wafer processing and inspection equipment, what Intel counts as a defect now may not be the same thing as what it counted as a defect 16 years ago. Furthermore, defect density itself does not directly equal product yield.

Intel's 22nm was the company's first manufacturing process to rely on FinFET transistors and at the time was the most advanced process technology in the world; the rest of the industry moved to FinFET devices only with their 14nm and 16nm-class nodes in 2014 and 2015. By contrast, 14A will use second-generation gate-all-around (GAA) RibbonFET transistors, second-generation backside power delivery called PowerDirect, and will be able to use High-NA EUV lithography due to extremely complex patterning. Keeping all of that in mind, Intel's claim that 14A defect density reduction is progressing unusually well this far ahead of HVM is certainly good news.

Meanwhile, comparing 14A to 22nm's successors should be quite comforting for Intel as 14nm mass production was delayed by a year due to insufficient yield, the first-generation 10nm node was a failure, 20A was cancelled, 18A defect density was high even as it hit HVM milestone, while the company did not share almost any information about the progress of its Intel 4 and Intel 3 nodes.

There are good signs for 14A though: external customers are already developing products for this node, whereas the interest from external customers is now practical rather than theoretical.

"We are now seeing demand from our internal customers on 14A [and] they are actually probably the most cynical bunch out of anybody," Zinsner said. "The fact that they are now designing products on 14A was a good confidence boost for us as well. Then, engagements with customers externally, from a foundry perspective has significantly increased. Lip-Bu and the team are now meeting on weekly basis with customers. They are moving away from just looking at data to thinking about 'how much capacity can I get?' 'what does that supply look like?' So, we are now at a point where we have conviction around customers on 14A externally as well."

Intel initiated mass production of its 22nm-based Ivy Bridge processors in late 2011 and early 2012 and released them commercially in late April 2012. The product was highly successful (though overclockers did not like it because of inefficient thermal interface material between the die and integrated heatspreader), and 22nm fabrication technology served the company for many years, first for CPUs in 2012 through 2016, then for other products. Intel's 14A also promises to be a long-lasting node for Intel.

Glass-core substrates, the replacement for organic chip packaging that Intel promised in September 2023 with more than $1 billion behind it, are now in final qualification. However, the product is still not in a single commercial product. SKC, a material manufacturer and chemical affiliate of the SK Group, said on its July 27 earnings call that embedded glass substrate samples from its Absolics plant in Covington, Georgia, are undergoing package-level reliability evaluation in Taiwan, with results possible before year-end.

Samsung Electro-Mechanics formalized a 482.1 billion won ($310 million) glass-core joint venture with Sumitomo Chemical's Dongwoo Fine-Chem on July 2, targeting first production in the second half of 2027. Intel, which started the race, has shifted to licensing its patents and showing demo vehicles, with its own deployment now pointed at around 2030. However, and rather predictably, every timeline in the segment has slipped. Absolics originally planned mass production for the first half of 2024, and reported claims that AMD would adopt glass substrates for CPUs between 2025 and 2026 have come and gone unfulfilled.

Why glass?

The technical case for glass core substrates leans heavily on numbers Intel published a while back, such as 10 times the interconnect density of organic substrates and a 50% reduction in pattern distortion. Glass cores can be tuned to a thermal expansion coefficient of roughly 3 to 10 ppm per degree Celsius against silicon's 2.6, which cuts warpage by about half compared with organic cores, and rectangular panels in the emerging 510mm x 515mm format use more than 75% of their area for large die against roughly 50% for round 300mm wafers. Through-glass vias have been demonstrated at six microns in diameter with aspect ratios beyond 15:1 at ECTC 2025, and Georgia Tech has shown stacked glass running at 220 GHz with 0.3 dB of loss.

Glass also chips and cracks at the edges during drilling and dicing, and MIT Technology Review reported in March that early Absolics production runs broke hundreds of panels every couple of days during early testing days. Edge-coating work has cut measured edge stress from 95 MPa to 49 MPa, and low-temperature dielectrics that cure below 180°C have been developed to reduce thermal stress during build-up, but metallizing vias below 10 microns and holding nanometer-scale flatness across half-meter panels remain open manufacturing problems.

Intel's program

Intel demonstrated a working system booting Windows on a glass-core substrate in early 2025, and Rahul Manepalli, Intel's VP of module engineering, told MIT Technology Review that the benefits of glass cores are "undeniable" and that Intel wants "to be one of the first ones who do it." The commercial plan around that engineering has changed shape, however. DigiTimes reported in late July that Intel is in early-stage talks with Chinese cover-glass maker Lens Technology about a packaging partnership, but there has been no solid agreement made to date.

At NEPCON Japan in January, Intel Foundry showed its first thick-core glass substrate with two EMIB bridge dies embedded directly in the glass: a 78mm x 77mm package with two 800-micron-class glass layers, 10 redistribution layers on each side, and around 1,716 mm2 of silicon on top, roughly two full reticles, with no micro-cracking reported in testing.

There’s currently no production time to this, however, with TrendForce placing Intel’s commercialization somewhere around 2030, alongside co-packaged optics prototypes built on glass at its Rio Rancho, New Mexico site. Meanwhile, Amkor, Intel's packaging partner on the optics work, put commercialization within three years at an industry event in Seoul in April.

Korea aiming for 2027

Samsung Electro-Mechanics moved its glass program from advanced R&D into a business-execution unit in February and has been sampling from a pilot line at its Sejong plant since late 2024. The GLASEM joint venture announced on July 2 splits ownership: 66% to Samsung Electro-Mechanics and 34% to Dongwoo Fine-Chem, with site production in Pyeongtaek, and targets an operating plant in the second half of 2027, with the joint venture making the drilled and metallized glass core that feeds Samsung's substrate line. Korean industry reporting says samples have gone to AMD and Broadcom, and also puts Samsung's overall glass maturity at 40 out of 100, a gap between marketing dates and process readiness worth keeping in mind.

Absolics' $600 million plant in Covington, Georgia, backed by $75 million in CHIPS Act funding plus a further $100 million through the government's advanced packaging R&D program with Georgia Tech, has a Phase 1 capacity of 12,000 m² of substrate per year, enough for roughly two to three million H100-sized packages. The company produced mass-production samples in the first quarter, began customer qualification that reportedly includes AMD and AWS, and is targeting mass production by the end of 2026. LG Innotek runs a third Korean program from its Gumi plant, with prototypes delivered in 2024 and production targeted for 2027 to 2028.

TSMC and Japan

TSMC's CoPoS line in Chiayi, built around 310mm x 310mm rectangular panels, received tools in February, completed its pilot line around June, and is aiming for pilot production in 2027, with mass production in the second half of 2028. Equipment supplier SCHMID has described glass integration in that platform as under review, not committed, and TrendForce puts TSMC's commercial-scale glass-core production after 2030, meaning that the industry's biggest packaging operation is going panel-level first and glass later, if at all. TSMC revived glass substrate research a couple of years ago after earlier deprioritizing it, reportedly under pressure from Nvidia, whose accelerator packages are the main thing outgrowing current packaging.

Japan’s Dai Nippon Printing began phased operation of a TGV glass-core pilot line at its Kuki plant in Saitama in December 2025 on 510mm x 515mm panels, with sample shipments from early 2026 and full mass production targeted for fiscal 2028. Toppan's pilot line for glass cores and interposers at its Ishikawa plant was scheduled for commissioning in July, and Nippon Electric Glass has scaled its ceramic-reinforced GC Core panel to 515mm x 510mm at 1mm thickness. Rapidus is studying panel-level packaging on 600mm x 600mm glass as part of its 2nm program, with viability put at the late 2020s. China has its own entrants, led by display maker BOE, whose pilot line is sampling.

TrendForce estimates Nvidia's Rubin Ultra package at roughly 7,470 mm², about nine reticles' worth of silicon and memory, against around 2,739 mm² for Blackwell, and CoWoS interposer wafers cost on the order of $10,000 each, comparable to a processed 7nm wafer.

Organic substrates warp and lose dimensional stability at those sizes, and round interposer wafers waste a growing share of their area, which is what glass panels are meant to fix. SEMI's first dedicated market report on glass cores, published in May with Global Net, projects initial production around 2028 in select high-performance applications and a 67.2% compound annual growth rate from 2028 to 2040, while Yole puts the advanced IC substrate market at $31 billion by 2030 with glass cores among the drivers.

At the moment, no production design exists, and all customers that have been named or otherwise attached to the tech, including AMD, Broadcom, AWS, and Nvidia, come from wider industry reporting. Nothing has been confirmed officially. As for whether we might see more substantial progress next year, Absolics will need to publish some solid package-level reliability results by the end of this year, or a first officially named customer at any of the Korean manufacturers. We also need to hear from TSMC on whether glass cores will go into CoPoS or remain under review into the 2030s.

The Environmental Protection Agency (EPA) has recently given two new chemicals approval for use within the U.S., but the non-profit organization Earthjustice is suing the agency for not doing its job. According to a lawsuit reported by The Guardian, these chemicals are photoacid generators used for semiconductor manufacturing, but they’re also quite toxic for humans. Exposure to them could allegedly lead to “sudden death,” as well as various health risks like cancer, eye corrosion, neurological damage, and reproductive harm. It is alleged that the approvals are "part of a broader pattern around data centers."

The current administration wants to bring semiconductor manufacturing back into the United States, with President Donald Trump issuing an executive order last year to fast-track the approval of chemicals needed for data centers. It’s unclear if these two chemicals are related to the order, but Atty. Jonathan Kalmuss-Katz, who works with Earthjustice, said that the EPA “does not know the level at which the chemicals are ‘acutely lethal’ or cause other serious health damage.” It also said that “the chemicals may present an ‘unreasonable risk’ to workers and the public.” Nevertheless, the agency allegedly approved them for import and use in the U.S. with minimal and non-protective restrictions.

“If a chemical may present an ‘unreasonable risk,’ then the Toxic Substances Control Act requires the EPA to ‘prohibit or limit the manufacture, processing, distribution in commerce, use, or disposal of such substance or to prohibit or limit any combination of such activities to the extent necessary to protect against an unreasonable risk,” Kalmuss-Katz told The Guardian. He also added, “This is turning the new chemical review process on its head. You have a situation where the EPA has failed at its most fundamental obligation when it comes to new chemicals, and that is to protect the public from unreasonable risk.” Aside from the health and environmental risks posed by the photoacid generators, these chemicals also appear to be PFAS or per- and polyfluoroalkyl substances. These are synthetic chemicals with unusually strong bonds that could last a long time, even if they’re exposed to the environment, which is why they’re often referred to as “forever chemicals.”

The semiconductor industry has long been known for its use of PFAS, and researchers are working hard to find ways to help clean up these chemicals used to make chips. So, the approval of new chemicals without rules and regulations that require them to be removed from discharges is potentially disastrous for the environment. This is the same concern that a lawsuit against Micron’s planned New York fab raises, which says that the approved wastewater and air permits that the company received could still allow these “forever chemicals” to leak into the Oneida River. Environmental groups acknowledge that domestic chip production requires the use of these potentially harmful chemicals, but the EPA must ensure that these do not find their way into the water system and that the people working with them are protected from exposure.

Groq's former chief architect stood on stage at Hot Chips 2026 and presented his former company's inference chip as Nvidia silicon. Igor Arsovski, now Nvidia's VP of hardware, presented the Groq 3 LPX rack's architecture and published the first third-party benchmark of the hardware: Artificial Analysis measured it at 3,431 output tokens per second on a 100K-context Gemma 4 31B reasoning workload, roughly four times the 870 tokens per second of the next-fastest public endpoint. Arsovski said the rack is already in production, built on the LP30 chip Nvidia obtained through its $20 billion Groq deal in December 2025, the same deal that pushed the Rubin CPX it replaced off Nvidia's roadmap.

SRAM without HBM

Artificial Analysis ran the comparison on a private, pre-release Gemma 4 31B endpoint served through Google Cloud, taking the median of 50 sequential client requests at a concurrency of one, while the public providers it measured against ran shared production serverless endpoints. Serving one request at a time produces the highest per-user token rate the hardware can post, and it's not directly comparable to the multi-tenant conditions the other endpoints run under.

Nvidia's on-stage demo showed a higher figure still, 10,996 tokens per second on the same 31B model, which Igor Arsovski, Nvidia's VP of hardware, flagged on stage as "self-reported" before telling the audience the aim was "third-party verified independent benchmarks that you guys can trust." Gemma 4 31B is also a dense model small enough to sit inside a single LPX rack, and the picture at trillion-parameter mixture-of-experts scale, where memory capacity becomes the main constraint, went unaddressed.

Each LP30 carries roughly 500MB of on-die SRAM and no HBM, so a full LPX rack of 256 chips holds 128GB of memory delivering 40 PB/s of aggregate bandwidth against 315 PFLOPS of FP8 compute, with 350 ns of chip-to-chip latency in a Vera Rubin-compatible, MGX liquid-cooled rack that scales past 1,000 LPUs.

Keeping model weights resident in SRAM rather than streaming them from HBM removes the memory-access latency that dominates single-token decode, and the design drops caches, branch prediction, and out-of-order execution in favor of a fully deterministic pipeline that the compiler schedules at clock-cycle granularity. The architecture descends directly from the Tensor Streaming Processor that Groq, founded by ex-Google TPU engineer Jonathan Ross, described in a 2020 ISCA paper titled Think Fast, the same title Arsovski and Raghavan reused at Hot Chips.

A Rubin GPU carries 288GB of HBM4, roughly 576 times the memory of a single LP30, so a 31-billion-parameter model at FP8 needs on the order of 62 LPUs to hold its weights, and a large mixture-of-experts model runs into four figures of chips across several racks. Capacity is the cost of the SRAM-only design, and it's why Nvidia is describing the LPU as for decode rather than as a general-purpose replacement for its GPUs.

Determinism lets the compiler predict power draw cycle by cycle, which Nvidia uses to pre-order current from the rack's regulators ahead of demand, cutting voltage droop by more than 60% and overshoot by more than 70% against an uncompensated load. The same per-block scheduling lets the hardware equalize heat instead of throttling to the hottest tile, which Arsovski put at roughly 10% to 11% additional performance under a fixed thermal limit. "By doing this, we can actually get more utilization of the chip under the same thermal limit, basically. So we can actually get, again, about 10 to 11% more performance under the same thermal limit. So this is another benefit of deterministic execution."

Across racks, Nvidia synchronizes chips to a single virtual clock in what it calls a plesiosynchronous network, with each chip acting as both processor and router so the fabric needs no adaptive routing or congestion sensing, and clock drift between chips is compensated at the chip-to-chip links. Asked during Q&A about the blast radius of a chip that fails mid-workload, Arsovski said users "would experience the exact same as any other hardware in the industry" and would "just checkpoint it or reconfigure the hardware."

Splitting inference with Rubin

Nvidia is pitching the LPX rack as a decode co-processor bolted onto Vera Rubin NVL72, with Rubin GPUs handling the compute-heavy prefill phase and building the KV cache while the LPUs generate output tokens. Nvidia showed three ways to divide the work: disaggregated prefill and decode; attention-FFN disaggregation, which keeps attention and its cache on GPU HBM while the LPU runs the feed-forward layers; and external-draft speculative decoding, where a small model on the LPU proposes tokens that the GPU verifies in parallel, with only draft tokens crossing the link.

An FPGA bridges the synchronous LPU domain and the asynchronous world of host I/O and GPU hand-offs, and Nvidia's Dynamo runtime, together with an LPU extension to CUDA, orchestrates the split. The company put the gains from these modes at roughly three-to-five-times over Rubin alone on a two-trillion-parameter workload with a 400K-token cached context, all Nvidia-measured.

Cerebras CS4

Cerebras used the same Hot Chips session to present its CS4 wafer-scale system, which chief system architect Jean-Philippe Fricker said runs up to 30 times faster than GPUs and doubles the token rate of the CS3 while carrying 10 times the token capacity. Each CS4 rack packs three wafer-scale engines into a new modular platform Cerebras calls Nexus, built around pluggable compute "backpacks" that separate power, compute, and I/O, and Fricker put its memory bandwidth at 43 PB/s, which he told the audience was "2,000 times higher memory bandwidth than Nvidia's next-generation Rubin chip." Cerebras also has a partner for the prefill side of the same problem: it agreed in July to pair AMD Helios GPUs for prefill with its wafer-scale engines for decode, the same division of labor Nvidia now builds in-house with Groq.

Nvidia pulled the Rubin CPX, its own GDDR7-based long-context accelerator, to focus on shipping the LPU this year, a decision VP Ian Buck laid out at GTC 2026. The $20 billion deal that produced the LP30 was structured as a non-exclusive IP license plus the hiring of Ross, president Sunny Madra, and most of Groq's engineers, a form that avoided a formal merger review. Arsovski opened the Hot Chips talk by calling it "a pinch me moment for the Groq team that's now integrated into the Nvidia group."

Senators Elizabeth Warren and Richard Blumenthal wrote to the FTC and to Nvidia in early 2026, arguing the arrangement acquired Groq "in all but name," and no formal, deal-specific investigation has been confirmed as of late August.

Full Nvidia Groq Hot Chips 2026 presentation

d-Matrix presented Raptor, which it calls the first 3D DRAM accelerator for generative inference, at Hot Chips 2026 this week, showing a TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed DRAM die that delivers 100 TB/s of bandwidth from 32GB per card.

Co-founder and CTO Sudeep Bhoja put the vertical interface's energy cost at 0.37 pJ/bit against roughly 2.4 pJ/bit for moving data into an HBM4 base die, calling it "a measured number" from working silicon, and the accompanying ISCA 2026 paper, written with the University of British Columbia, projects around 4.7 times higher throughput per card than HBM-based designs. Bhoja, however, didn't disclose who manufactures the DRAM die.

CEO Sid Sheth told CNBC in June that Raptor is slated to launch in 2027, but at Hot Chips the company gave no firm date or information on volume and pricing, and every performance figure shown, including 988 tokens per second per user on the 2.8-trillion-parameter Kimi K3 model at 1M-token context, is a d-Matrix projection built on early silicon.

The custom DRAM die

Raptor inverts the usual 3D stacking arrangement by putting the logic die on top and the DRAM underneath, so a cold plate sits directly on the compute silicon and the DRAM die doubles as the interposer, carrying PCIe and die-to-die signals down through its TSVs. "For the same amount of power, you can drive the bandwidth up," Bhoja said during the session, "and so we were able to drive the bandwidth up here to 100 terabytes per second."

The one-high stack achieves a power density of roughly 0.5W per square millimeter, which liquid cooling can handle, but the DRAM is designed for a junction temperature of 105°C, where retention collapses from a standard 32ms to 4ms, and the memory must refresh eight times more often. d-Matrix absorbed that penalty by shrinking each microbank to 1,366 rows and about 5.33MB, so a full refresh sweep costs only 1.37% of overall bandwidth.

The die carries 840 banks per chiplet, of which 72 (around 9%) are spares wired into a two-level mux chain the company calls bank chaining, letting any two failed banks anywhere on the die be switched out while channels stay symmetric. A [132,128] Reed-Solomon code on the logic die corrects two symbol errors per 128 bytes, with a CRC behind it. The interface has no PHY, no burst structure, and no sideband pins, so conventional data-bus inversion was impossible; d-Matrix instead compares each 128-byte flit to the previous one and stores a 1-bit inversion tag alongside the ECC metadata, recovering roughly 20% of the I/O power DBI would have saved. At full tilt, the vertical interface still burns 296W of the 422W per-package budget the ISCA paper discloses.

The bank geometry, spare-bank mux tree, refresh behavior, and interleaved ECC columns were all co-designed with the compute die. The 0.37 pJ/bit figure exists only because of that pairing, and no memory maker has anything like this die in its catalog.

Who's supplying it?

d-Matrix has named TSMC for the N4P logic die and Alchip as its ASIC design and 2.5D/3D packaging partner, but neither company operates a DRAM fab, and across the Hot Chips talk, the ISCA paper, and every public announcement since the Pavehawk 3DIMC test silicon came online last September, the firm has never identified who fabricates its custom DRAM. Only three companies make leading-edge DRAM at volume, and all three are allocating capacity to HBM4 lines that are effectively sold out through 2026.

J.P. Morgan estimates DRAM prices will have risen more than 400% between the start of 2024 and the end of 2026. In addition, analysts have recorded contract price increases of 90% to 95% in Q1 2026 alone, and SK hynix CEO Kwak Noh-jung told Reuters in July that "customer demand will remain higher than our supply capacity even beyond 2030."

Nvidia, the memory makers' largest and most leveraged customer, is reportedly testing Rubin Ultra configurations with as little as 192GB because it may not be able to source enough HBM4E. A startup with roughly $450 million raised, asking a memory maker to run a bespoke die with non-standard bank geometry on capacity that could otherwise print HBM, is negotiating from a far weaker position than that, and until the supplier is named, Raptor's 2027 volume plan rests entirely on an unknown, undisclosed dependency.

The die's 11.4 MB/mm² density is roughly half of HBM4's 21.9 to 26.3 MB/mm², Bhoja acknowledged during the Q&A: "A lot of the drop for us was also because we used a not-so-advanced DRAM. And so if we used a more mainline DRAM, just like the HBM4 guys are doing, we would be able to push that up almost all the way to the HBM4 numbers." The density penalty therefore tracks back to whatever foundry arrangement d-Matrix currently has.

32GB per card

Raptor's 32GB per card stands against 192GB to 288GB for HBM4-equipped accelerators, so d-Matrix sizes deployments at rack scale instead: 72 cards carry 2.3TB, enough to hold Kimi K3's weights at 4-bit precision with headroom for around 54 concurrent users at 1M context, by its own calculations. "Even with 32 gigabytes of memory capacity, we are able to solve SOTA models in a scale-up network, so no bits are wasted," Bhoja said.

KV cache growth works against that arithmetic over time, and co-presenter Aayush Ankit, who led Raptor's SoC architecture at d-Matrix before joining Meta's MTIA team, explained the failure mode while dismissing SRAM alternatives: "We are making this unit of compute blazingly fast. Communication becomes a bottleneck soon enough." Once models and context no longer fit a single rack, inference spills into the inter-card synchronization overhead that the vertical bandwidth was meant to eliminate, which the ISCA paper concedes.

Cerebras claimed 969 tokens per second on Llama 3.1 405B in November 2024, with third-party firm Artificial Analysis verifying the figure on live hardware, and that remains the closest published reference point for Raptor's numbers. d-Matrix's 988 tokens per second per user on a model seven times larger would be a step change if it holds water, but no third party has measured Raptor, and the comparison points in the ISCA paper are simulations anchored to early silicon characterization.

Asked by an Nvidia employee about multi-layer stacking plans, Bhoja said: "Our roadmap is still a work in progress, and we have a hard enough time trying to get one-high to work and work around all of the thermal issues of that." Samsung brought its own version of the idea to Hot Chips with zHBM, a concept that stacks HBM directly on the processor and carries a claimed 70% power-efficiency gain over an HBM4E setup, with no production timeline before HBM5. The problem for d-Matrix is that Samsung runs its own DRAM fabs; d-Matrix doesn't. Whether it can get wafers at volume remains to be seen.

Full d-Matrix Hot Chips 2026 presentation

Just over one week after Nvidia agreed to backstop up to $105 billion in financing for its data centers, OpenAI arrived at Hot Chips on Tuesday with benchmarks claiming its first in-house chip beats Nvidia's GB300. Jalapeño, the inference ASIC OpenAI co-developed with Broadcom, delivered 1.5 times to 1.9 times more throughput per kilowatt and 1.7 times to 3.6 times lower end-to-end latency than Nvidia's GB200 and GB300 rack systems on SemiAnalysis's public InferenceX suite, with a 700W part going up against accelerators rated at 1,200W and 1,400W. OpenAI plans to begin deploying the chip in its own data centers later this year.

The tests covered three open models: GPT-OSS 120B, DeepSeek R1 670B, and Moonshot AI's 1-trillion-parameter Kimi K2.5, with OpenAI reporting its widest leads at low-latency operating points, where it claims 8.6 times to 104.3 times more throughput per kilowatt at the GB300's fastest previous time-between-tokens settings.

OpenAI normalized the results to each accelerator's published package TDP, though it said Jalapeño's measured sustained power stayed at or below 550W in testing. An appendix comparison using all-in utility power per accelerator, 1.18kW for Jalapeño against 2.55kW for the GB300, produces narrower gaps, as does pitting Jalapeño against a GB300 running multi-token prediction, where the peak efficiency lead shrinks to roughly 1.5 times.

Jalapeño wasn't tested against Vera Rubin, the Nvidia platform that's slated to power the first gigawatt of Nvidia systems OpenAI agreed to deploy in the second half of 2026. The chip also doesn't train models, the workload where Nvidia's hardware remains unchallenged. In addition, the major comparisons ran Jalapeño's single-token prediction against GB300 configurations doing the same, even though Nvidia deployments commonly use multi-token prediction in production. SemiAnalysis, which said it ran InferenceX with OpenAI engineers in the company's lab, described the part as "beating every Nvidia, AMD, and Google chip we have been able to test."

Each Jalapeño package, unveiled in June after a nine-month RTL-to-tapeout cycle, pairs its compute die with six HBM4 stacks, totaling 216 GiB at 15.4 TB/s. The GB300 carries 288GB of HBM3E at a 1,400W rating, so per watt of rated power, OpenAI's chip packs roughly 50% more memory. The company's Hot Chips presentation states that the main bottleneck its architecture targets is exposing aggregate HBM bandwidth, not adding more of it.

That memory is of course the tightest commodity in the semiconductor industry. Samsung, SK hynix, and Micron have sold their HBM capacity through 2027, a shortage so severe that Nvidia is reportedly testing cut-down Rubin Ultra configurations with as little as 192GB, and SK hynix CEO Kwak Noh-jung has warned that 2027 will be the worst year of the crunch. Micron told the same Hot Chips conference on August 23 that HBM consumes roughly three times the wafer area of DDR5 for equivalent capacity, a penalty that widens with each generation. Scaling Jalapeño across the 10GW deployment agreement that OpenAI signed with Broadcom last October would make the company a substantial new claimant to HBM4 supply, which Nvidia currently dominates through multi-year allocation deals with SK hynix.

A second-generation chip is approaching tapeout, expected within months, according to Bloomberg, and concept work on a third generation is underway. The first part reportedly uses a TSMC 3nm-class process, keeping OpenAI in the same wafer, memory, and advanced packaging queues as Blackwell and Rubin for the foreseeable future.

OpenAI is procuring those inputs while deepening its financial dependence on the company it just benchmarked. On August 17, Nvidia agreed to provide up to $105 billion in financing for an OpenAI-leased data center campus in Ohio. "Nvidia is a really good partner, and we continue to need a lot of Nvidia," Richard Ho, OpenAI's vice president of hardware, told Bloomberg in an interview following the announcement.

Raghu Sreeramaneni, Micron HBM Design Architecture Fellow, told the Hot Chips 2026 conference on August 23 that the silicon penalty HBM carries against DDR5 is growing with every generation, and that it can’t be closed without giving up performance, something that Micron won’t do. Pressed on whether newer parts narrow the gap, he said it’s "definitely not getting better," putting the current overhead at roughly three times the wafer area of DDR5 for the same capacity. That trajectory is the reason why PC memory hit record prices this year, with conventional DRAM contract prices up 90% to 95% quarter over quarter in the first quarter of 2026.

Wafer mathematics

An HBM4 die fits 256 banks against 32 on a DDR5 die, and it reaches its bandwidth by running those banks in parallel, which requires far more die area for data paths, power delivery, and the through-silicon vias (TSVs) that link each layer to the base die. A single HBM3E die can feed 256 GB/s, while one DDR5 die supplies about 8 GB/s, so matching a given bit count makes the HBM die much larger.

Micron has publicly put that overhead at about three times the wafer area of DDR5, and Sreeramaneni said it traces to an HBM3E-against-DDR5 comparison that grows with each generation as pin speeds, bank counts, stack heights, and die sizes climb higher. He called HBM "probably the most cross-functionally complex solution that we make," and noted that in a two-GPU package, memory accounts for around 90% of the silicon, roughly eight times the area of the GPU dies. HBM already sells for about five times the price of DDR5 per bit, so each wafer a maker moves to it removes a disproportionate share of commodity memory from the market, pushing consumer product prices higher as a consequence.

Conventional DRAM contract prices rose 90% to 95% quarter over quarter in the first quarter of 2026 and a further 58% to 63% in the second. To put that into perspective, a mainstream 32GB DDR5-6000 kit sold for around $392 this month, up from $110 to $140 a year earlier, and 128GB of DDR5 passed $3,399, a 500% rise over 12 months, with European prices up 345% since September last year. Back in February, HP told investors that DRAM now makes up 35% of its PC build cost, up from 15% to 18% a quarter earlier, and Gartner expects PC shipments to fall more than 10% in 2026. While it’s true that the surge eased to 13% to 18% in the third quarter, that happened because consumer electronics makers reached the ceiling of what they could pass on, not because supply improved.

Bandwidth, stacking, and heat

Micron's presentation put compute performance scaling at roughly three times every two years and HBM bandwidth at under two times, a divergence Sreeramaneni summarized by saying "the memory wall is still present, and, in fact, maybe getting worse." HBM4 doubles the host interface to 2,048 I/Os, and Micron's parts run above 11 Gb/s per pin for more than 2.8 TB/s per stack, beyond the 8 Gb/s and 2 TB/s baseline in JEDEC's HBM4 standard.

Each of those gains comes from more parallelism, which enlarges the die again and widens the silicon ratio. Sreeramaneni said there is "a good path to 16 layers of DRAM," but "after 16, there's still a lot of work to be done." Meanwhile, SK hynix used its own Hot Chips talk to describe a 775-micron total-thickness ceiling that caps stacking until the industry adopts hybrid bonding, which SK hynix doesn't expect before HBM5. Micron's HBM4E, due around 2027, moves the logic base die to a TSMC foundry process, part of a wider shift toward customization as AI workloads fragment, which Sreeramaneni described by saying "disaggregation is the buzzword now."

The base die runs hottest because it sits at the bottom of the stack, doing the highest-speed interface work while the heatsink sits at the top. Every layer added between the base and the heatsink then raises thermal resistance. Sreeramaneni said Micron is now "architecting solutions around thermals rather than the other way around," a reversal from a few years ago. Micron highlighted how Meta's Llama 3 paper attributed 17.2% of unexpected interruptions during a 54-day run across 16,384 H100 GPUs to HBM3 memory, the second-largest cause behind failed GPUs, a reliability burden that scales with the amount of HBM in each package.

Share and supply outlook

SK hynix leads the HBM market with a share that Counterpoint Research places at around 58%, down from a high of around 69%, and Micron overtook Samsung for second place last year. Micron began volume shipments of 36GB 12-high HBM4 earlier this year for Nvidia's Vera Rubin platform, with Nvidia CEO Jensen Huang saying in June that all three suppliers are qualified and in production.

Analysts expect DDR5 per-wafer profitability to overtake HBM3E by the end of this year, leaving the three makers little reason to add commodity capacity when server DRAM pays nearly as well per wafer. SK hynix said last October that it had already sold its entire 2026 output, while Apacer's chief executive told investors that supply to independent module makers could fall to 30% of 2026 volumes next year. SK hynix CEO Kwak Noh-jung has called 2027 the worst year for memory supply in the industry's history, with demand outrunning production into 2030.

In response, Nvidia has raised its DGX Spark desktop from $3,999 to $4,699 and warned large customers of AI server price rises above 15%, both tied to memory. Realistically, the squeeze will loosen only under three conditions, none of them likely before new fab capacity comes online and scales up: China's CXMT ramping competitive DDR5 in volume, hybrid bonding arriving before HBM5, which SK hynix has already all but ruled out, or DDR5 profitability slipping back below HBM.

Full Micron Hot Chips 2026 presentation

SK hynix doesn't expect hybrid bonding to be ready for HBM4E, Jaesik Lee, VP of package engineering at SK hynix America, said during a presentation at Hot Chips 2026 on August 23, pushing the industry's most anticipated memory packaging transition out to HBM5 at the earliest.

The problem, as he describes it, is that HBM cubes are capped at a total thickness of 775 microns — the standard thickness of a 300mm logic wafer — so every additional DRAM layer must come from thinner dies and narrower gaps. 16-Hi HBM4, now in customer qualification at 48GB per cube while 12-Hi is in mass production, thins its core dies to around 50 microns and halves the gap between them compared with 12-Hi. Lee's session also went into detail about the company's iHBM cooling architecture three months after its May unveiling. Attaching a constraint to it, Lee explains that the heat blocks can't be applied to any HBM generation already in design.

The 775-micron limit

The JEDEC HBM4 standard raised the package thickness ceiling from 720 microns, which held through HBM3E, to 775 microns, easing the pressures associated with adopting hybrid bonding. When a GPU package gets its cold plate attached, both the logic die and the memory stacks are ground back to expose bare silicon, Lee said, and because logic wafers are 775 microns thick, a memory cube that grew any taller would stand proud of the processor beside it. "That's the kind of limit that we can go up so far, because the logic wafer thickness is also 775 microns," Lee said.

Thinner dies leave the stack with proportionally more oxide, which conducts heat poorly compared with silicon, while pin speeds that have risen from 1 Gbps in early HBM to 8 Gbps in HBM4 concentrate more power in the same footprint. SK hynix's own figures put the thermal burden at 2.2 times higher across the HBM generations shown, while stack counts double every two generations.

The company's mass reflow-molded underfill (MR-MUF) process, which stacks all dies via pick-and-place and joins them in a single reflow, already trades away margin here: filling gaps that have shrunk by half while controlling warpage on sub-50-micron dies is, per Lee, the main manufacturing challenge of 16-Hi.

Hybrid bonding keeps slipping

Samsung publicly committed to hybrid bonding for HBM4 in May last year, with SK hynix holding the copper-to-copper technique as a backup behind advanced MR-MUF. The JEDEC thickness relaxation then removed the immediate need, and industry discussions now weigh a further move to 825 to 900 microns for 20-Hi stacks, which would push the copper-bonding crossover out again.

Back in March, it was claimed by industry sources that SK hynix placed its first mass-production hybrid bonding order, a single inline system pairing Applied Materials and Besi tools worth around 20 billion won ($15 million), and Counterpoint Research expects the technique to enter full-scale HBM production with HBM5 around 2029 to 2030.

Hybrid bonding remains at the research stage for stacks of 20 layers and above, per the deck's roadmap, and SK hynix is still deciding which product gets it first. Lee didn't name a target generation, but ruling out HBM4E leaves HBM5 as the earliest slot. The technique joins flattened copper pads and oxide surfaces at room temperature, then relies on copper's thermal expansion during a cure step to form the bond.

"This is a very simple process, but in reality it's really challenging," Lee said. "We are talking about 16 layers and 20 layers that we need to make the hybrid bonding, so it's very different from the one-layer stacking." Removing micro-bumps entirely lets core dies grow up to 24% thicker at 20-Hi, cuts thermal resistance by roughly 35% versus MR-MUF at that height, and takes bump pitch below 18 microns, per the deck, against the 30 microns where MR-MUF is today. At HBM4's bump pitch, conventional micro-bumps still work, and each time JEDEC has raised the thickness ceiling, MR-MUF has stayed viable for another generation.

iHBM

The iHBM concept embeds thermally conductive, electrically insulating blocks into the base die's die-to-die PHY region, the interface hotspot where power density peaks, for a claimed thermal resistance reduction of more than 30%.

Lee's slides benchmarked it directly against Samsung's Heat Path Block approach, which routes heat out of the stack through dedicated pillars, and Micron's base-die circuit redesign, which claims over 20% better energy efficiency. All three are vendor claims measured on different metrics, and the SK hynix and Samsung designs are both slated for HBM5, with neither expected in mass production before 2028. Because the blocks sit inside the package alongside the D2D PHY, they need optimization with the customer's design and can't be applied to generations already in design, Lee said, which makes iHBM a co-design effort. "It's a kind of good option that we can do, but this is not something that we can apply [to] the generation that we already [have] in design."

During Q&A, Tanj Bennett of SemiAnalysis argued that stacking taller dilutes the silicon's own throughput. DRAM operating at the cell level delivers on the order of 20 TB/s per square centimeter; a 20-Hi stack tops out around 4 TB/s, and HBM takes far more manufacturing capacity than equivalent DDR5 or LPDDR. "As you get to 20 high, the average speed of that memory is slower than DDR5," Bennett said. "Why is it better to be using the height of the HBM stack instead of intelligently placing cheaper memory around it?"

Lee answered that training workloads demand both bandwidth and capacity, then added that inference may split the difference, keeping the KV cache in high-bandwidth memory while offloading to LPDDR. That split already exists in products like Nvidia's Vera Rubin platform, which pools LPDDR5X with HBM4 over NVLink-C2C for exactly this purpose, and the High Bandwidth Flash spec that SK hynix co-developed with Sandisk extends the tiering idea to NAND.

"That's a kind of question that we need to also look at in the future," Lee said of the tiered approach. SK hynix holds around 70% of Nvidia's HBM orders for the Vera Rubin generation, according to reporting from January, and all of it will be stacked with MR-MUF. Which product moves off it first, Lee says, is a decision that the company hasn't made.

Full SK hynix Hot Chips 2026 presentation

A research team at Kyoto University has built a silicon carbide (SiC) transistor that operates at 600°C (873 K) using ion implantation, the doping step used across commercial chip fabs, and cut the gap between its designed and measured threshold voltage to under 0.1V at 400°C, down from more than 2V in the conventional layout. The work, announced earlier this month by Mitsuaki Kaneko, Shunya Shibata, and Tsunenobu Kimoto and published in APL Electronic Devices, pairs a bottom-gate transistor with a double-well isolation structure to keep an ion-implanted SiC junction field-effect transistor stable at temperatures where silicon stops working above roughly 250°C.

The bottom-gate layout puts the gate electrode beneath the channel, which captures the dopants that scatter deeper than intended during implantation, a channeling effect that had thrown conventional top-gate JFET thresholds off by more than 2V. With the channeling tail compensated, the design-to-measured threshold voltage gap dropped to under 0.1V at 400°C.

The double-well structure isolates each device inside a pn junction instead of leaning on the semi-insulating SiC substrate underneath, which loses its insulating behavior as it heats and bleeds leakage current through the wafer. Kaneko's group reported the remaining leakage sits close to the theoretical floor set by SiC's own material properties, so there's little room left to improve it at the device level.

In contrast, NASA Glenn Research Center has run SiC JFET integrated circuits carrying more than 175 transistors for over a year at 500°C in air, and 60 days on a simulated Venus surface at 460°C and 9.3 MPa with no shielding, per the agency's published testing. Those chips are built from epitaxial JFET-resistor devices on a bespoke process. The Kyoto researchers reached a higher device temperature through ion implantation, a method already standard across mainstream fabs, which fits existing mass production.

SiC is already scaling as a power-device wafer material, but high-temperature logic is a separate and far smaller niche. It isn't the only wide-bandgap material chased for these conditions either, with researchers recently showing devices that hold up from 500°C down toward absolute zero in other compounds.

The transistor is normally-on, so it conducts with no gate voltage applied and draws standby power. Efficient logic needs complementary pairs built from normally-off devices, which this isn't. Kimoto's group has already demonstrated complementary SiC JFET logic gates at 350°C, and its next step is to design normally-off devices in the new structure to build low-power complementary circuits. Long-duration reliability at temperature and heat-tolerant packaging are just two challenges the researchers will need to overcome before any of it reaches a gas turbine, or Venus.

As advanced packaging technologies like EMIB and CoWoS become yet another battlefield in the semiconductor industry, outsourced semiconductor assembly and test (OSAT) companies are trying new tools in a bid to offer services that others do not. This week, LG Electronics Production Technology Institute (PRI) signed a contract with an OSAT to supply it with a maskless laser direct imaging (LDI) lithography tool that can be used to build metal-interconnect patterns in semiconductor packaging, potentially with higher yields than currently available tools, reports ETNews.

LG-PRI's Laser Direct Imaging (LDI) system is a maskless lithography machine designed to pattern fine metal interconnects for advanced semiconductor packaging. While the company has developed various versions of the machine, its highest-resolution version can produce 1.5-µm line-and-space (L/S) patterns, which should be fine to 'print' wiring pitches of about 3 µm. The production equipment uses a 405-nm laser-diode light source and can process substrates as large as 600 × 600 mm, according to various media reports.

LG positions its LDI system primarily for advanced semiconductor packaging using organic and then glass substrates, displays, and MEMS. Yet, it can also be used to build high-density printed circuit boards (PCBs) for mobile devices or prototype purposes.

LG is entering an already established direct-imaging market led by KLA, Screen Holdings, Limata, and ORC, but participated in by a dozen manufacturers from Germany, France, Switzerland, Japan, and even China. What is notable is that LG is offering LDI systems with line/space capability down to 1.5-µm, which means it is targeting the higher end of the market. Yet, to establish a position, LG plans to price its LDI system competitively.

Another way to pattern substrates

There are many ways to pattern substrates, including photolithography, e-beam lithography, nanoimprint lithography, and laser direct imaging, just to name a few. LDI is a maskless lithography process in which a laser exposes a digitally generated circuit pattern directly onto a photoresist-coated substrate, rather than transferring the pattern through a physical photomask. Instead of a photomask, an LDI system uses a digitally controlled pattern generator and projection optics, which resembles how a laser cinema projector projects a digital image onto a screen, except that LDI projects a circuit pattern onto photoresist. After development, the exposed resist leaves a pattern that defines where metal interconnects will be formed in later processing steps.

LG's LDI machine can produce down to 1.5-µm line-and-space patterns, which is good enough for chip substrates and even redistribution layers (TSMC CoWoS-R/-L uses RDL interposers with a minimum 4-µm pitch, or 2-µm line width/spacing). In contrast, competing products offer 1-µm, 3-µm, and 5-µm versions for different applications. While LDI in general cannot boast the resolutions offered by modern DUV, EUV, or e-beam lithography machines, LDI trades ultimate resolution for vastly higher throughput and large-area processing, exactly what the doctor ordered for production of PCBs or chip packaging. With current-generation LDI, the RDL interposer is the most advanced thing that these devices can pattern, as both CoWoS-S and CoWoS-L/EMIB-like technologies require considerably higher resolution. Meanwhile, there is another advantage that LDI machines have over lithography systems that rely on photomasks.

Because the image is generated digitally, the system can create and calibrate patterns in real time, while projection optics, precision alignment, and stage control position the pattern accurately on the substrate. This capability is important because the dimensions/geometry of packaging substrates can vary and because organic substrates can expand, contract, or warp during processing. Given that we are talking about a 1.5-µm-scale wiring pattern, any shift from the nominal layout may result in a solder bridge or a faulty contact, which means yield loss. That said, the ability to adjust the pattern to the peculiarities of a substrate may be a game-changer for OSATs, their customers, and a major selling point for devices that can do it.

A new kid on the block? Not really

Unlike competing chaebols Samsung and SK Group, LG Group does not produce chips, even though its divisions supply various materials and components for the semiconductor industry. To that end, it is perfectly reasonable for the company to enter the market for tools for the production of chip packages or PCBs.

In fact, LG PRI is not entering the exposure-equipment business from scratch. PRI traces its history to the Goldstar Production Technology Research Institute, established in 1987, and has worked on manufacturing and productivity technologies covering semiconductors, displays, and rechargeable batteries. Specifically, LG had already commercialized LDI technology for display manufacturing and supplied such equipment to LG Display.

As a result, the semiconductor packaging-grade equipment represents an expansion of an existing LG technology into a new market rather than the development of an entirely new exposure platform from scratch and without any experience. Interestingly, LDI is the first element of LG's semiconductor equipment ambitions. The company reportedly plans to expand its portfolio into high-bandwidth memory (HBM) inspection equipment as well as through-glass-via (TGV) laser systems for glass substrates.

Prospects

Before LG expands to inspection or laser drilling tools, it will have to establish itself as a producer of reliable tools used for chip packaging, which will likely take years. For now, the significance of the deal with the undisclosed OSAT is less about business and more about the fact that an OSAT decided to give LG's LDI machine a try. Moving from university R&D installations to an OSAT mass-production facility provides LG a starting point for pursuing additional external orders.

Whether LG can establish itself alongside Applied Materials, ORC, or Screen will depend on how its equipment performs in production and whether its emphasis on competitive pricing proves sufficient to persuade more packaging companies to adopt the system.

In any case, a new Wafer Fab Equipment player is here, which is good news considering shortages of virtually all chipmaking tools. While LG's entrance will hardly have any noticeable impact on the market for at least a couple of years, another supplier could eventually add much-needed capacity, increase competition, and give chipmakers and OSATs another source of advanced packaging equipment.

Nvidia has rejected a report claiming that it plans to begin small-batch shipments of a language processing unit tailored for Chinese customers by the end of 2026, with several Chinese orders already placed. "The reporting in The Information on NVIDIA's LPU is incorrect. We have no LPU sales in the China market today, and no China-specific LPU product in our roadmap," an Nvidia spokesperson told Tom's Hardware on Thursday. The Information's story, which cited two Nvidia employees, said the chip is a variant of the Groq 3 LPU Nvidia announced at GTC in March, and that its silicon is unchanged because it already falls within U.S. export rules.

The LPU was designed as a decode co-processor for the Vera Rubin platform, and Vera Rubin can't be sold in China. The Information's sources said Nvidia rewrote the software that splits work between the GPU and the LPU so the accelerator can run alongside processors that are available in the country.

The publication said Nvidia didn't respond to requests for comment over several days before publishing, and that it's unclear whether Beijing would allow the orders to proceed. Chinese officials blocked purchases of the H20 last year and only recently told companies they'd permit some H200 imports, so U.S. compliance alone doesn't guarantee the chips can be delivered.

Back in March, it was reported that Nvidia was preparing LPUs for China, with Jensen Huang saying two days later that the story was "totally false.” Thursday's statement is narrower than Huang's, addressing current sales and a China-specific product. Nvidia hasn’t clarified whether the standard LPU will ship to Chinese buyers. Huang told CNBC in May that Nvidia had "largely conceded" China's AI chip market to Huawei.

The Groq 3 LPU is built on Samsung's 4nm process with 512MB of SRAM per die and no HBM, and Nvidia said at GTC that it would ship in Q3 2026 to customers including OpenAI. U.S. export thresholds for China are set on compute density and bandwidth, and an SRAM-only decode accelerator with no HBM stack is the kind of part that can still be exported under them without a cut-down SKU, which is the mechanism The Information's sources described.

Huawei's Ascend 950DT, which the outlet named as the LPU's direct competitor, is optimized for decode and training and is due in Q4 2026, with the prefill-focused 950PR already in production since April. ByteDance and Tencent each took delivery of roughly 10,000 H200s in recent weeks, according to a Financial Times report this week, the first meaningful Nvidia accelerator volume to enter mainland China since December's U.S. approval.

Synopsys has published silicon results for what it calls the first 3D PCIe 6.0 test chip, a 5nm PHY built into a face-to-face stacked package that runs 64 GT/s per lane and up to 128 GB/s across an eight-lane link using PAM4 signaling, with receiver eyes clearing the standard's bit error rate requirement. The company says it got there by pulling apart an existing 2D PCIe 6.0 test chip, adding through-silicon vias, and redoing circuit design and signoff against 3D process design kits, according to its blog post.

In monolithic chips, PCIe PHYs sit at the perimeter of the die, right next to the package I/O connections, helping keep traces to the substrate short so attenuation and reflections remain manageable. A 2.5D package preserves that layout by parking the PHYs along the outer edge of the outermost chiplets. Face-to-face hybrid bonding removes the option. The bottom die is flipped so its redistribution layer meets the redistribution layer of the logic die above it, which leaves the PCIe PHYs facing away from the substrate they need to reach. Instead, the signals travel down through vias cut into the silicon.

Every TSV passes through active silicon and needs a buffer around it, so the vias can't be dropped wherever the PHY happens to sit. "You rarely drill straight down into the package substrate," Manmeet Walia, executive director of product management at Synopsys, said to Electronic Design, which reported that routing has to climb to one of the upper metal layers and reverse direction before descending.

Walia told the publication that electromigration and layout rules change substantially in 3D, that via count is a tradeoff between bandwidth and signals corrupting each other, and that customer logic sitting over the PHY's path down to the substrate is a challenge that Synopsys expects to work through iteratively, design by design. PAM4 leaves less room for that kind of error than the NRZ signaling used through PCIe 5.0, since it packs two bits into each symbol.

Fujitsu's Monaka processor takes the opposite approach, instead stacking four N2 compute chiplets carrying 144 Armv9 cores face-to-face on N5 SRAM chiplets using hybrid copper bonding, then putting the memory controllers and the PHYs for its 12 DDR5 channels on a separate and comparatively large I/O die rather than inside the bonded stack.

PCIe generations arrived roughly five to seven years apart for most of the standard's life and now release about every two years, with the Gen 8 specification due in 2028 at 256 GT/s per lane. Walia told Electronic Design that a further shift is coming with 3.5D packaging, where the PCIe PHYs get stripped out of the bottom die entirely, replaced with UCIe, and relocated to a side chiplet on the interposer that acts as a multi-protocol hub for Ethernet, PCIe, and CXL. Synopsys hasn't put a date on that. Its blog says leading-edge customers are evaluating angstrom-class process technologies for the top dies in their stacks.

SMIC posted its first $3 billion quarter earlier this month, with revenue up 36.1% year on year, net profit nearly tripling to $479.2 million. Co-CEO Zhao Haijun told analysts the next day that the Shanghai foundry will charge more for wafers processed in the third quarter after price negotiations concluded in the first. Utilization hit 93.7% against demand Zhao said SMIC can't fully meet, driven by Chinese AI data center buildouts that U.S. export controls have cut off from TSMC and Samsung at the leading edge. "Since there's still a big gap between industry-leading wafer prices and SMIC's current prices, we need to negotiate with customers for fairer pricing," Zhao said on the call.

The quarter blew SMIC's own out of the water on every front. The company had guided to 14% to 16% sequential revenue growth and a 20% to 22% gross margin; it delivered 20% growth to $3.01 billion and a 25.3% margin, up from 20.1% in Q1. Wafer shipments rose 14% quarter-on-quarter to 2.9 million 8-inch equivalents, blended selling prices climbed 5.7%, and Q3 guidance calls for a 26% to 28% gross margin. China accounted for 90% of revenue.

Demand isn’t coming from GPUs, however, with Zhao commenting that the surge came mostly from AI chips other than CPUs and GPUs, such as logic ICs, BCD power-management parts, and optical transceiver components, all in short supply. Meanwhile, growth in SMIC’s AI peripheral segment is expected to be around 40% for the quarter, while industrial and automotive chips rose to 16.5% of wafer revenue from 10.6% a year earlier.

From bust to boom

SMIC's utilization sat at 68.1% in the first quarter of 2023 and averaged 75% that year as net profit fell more than 60% and gross margin dropped 16.4 points to 21.9%. As late as early 2025, it was reported that SMIC and Hua Hong were cutting mature-node prices to defend share against a wall of new Chinese capacity. The company that spent 2023 and 2024 discounting into overcapacity spent 2026 raising prices by around 10% in December, negotiating targeted increases in capacity-constrained segments in February, and applying another round to Q3 wafers.

Export controls did most of the work, with Washington’s restrictions keeping China's AI accelerator demand away from TSMC. Beijing has been redirecting that demand inward: the government wants 70% of silicon wafers sourced domestically this year, and a Bloomberg Intelligence survey of 60 Chinese tech executives in June found firms plan to spend 46% of their AI accelerator budgets on local chips over the next 12 months, up from 30% now. SMIC is the only Chinese foundry that mass-produces 7nm-class logic, which makes it the sole domestic route to silicon for Huawei's Ascend line and Cambricon's accelerators. A protected buyer pool, along with a mandated shift to domestic supply and a single qualified supplier at the leading edge, produces a textbook seller's market.

Hua Hong, China's second-largest foundry, reported utilization of 102.8% in the same week, with record revenue of $717.5 million, up 26.8% year on year. TrendForce data shows foundry prices across China rose 5% to 15% between Q1 and Q2, with a third round of increases being prepared for the second half. TSMC is reportedly raising prices across all its advanced nodes too, so SMIC's hikes track a global trend, but SMIC is doing it from a captive position TSMC doesn't have: its customers have no other choice.

China's AI chip designers post record first halves

Cambricon's first-half revenue rose 108% to 6 billion yuan (c. $890 million) with net profit up 122.6% to 2.3 billion yuan, per its Shanghai Stock Exchange filing reported by the South China Morning Post. Moore Threads grew first-half revenue 147% to 1.74 billion yuan and cut its net loss by 96%, and Biren projected first-half revenue growth of more than 1,850% off a small base ahead of a Hong Kong IPO. Memory maker CXMT raised $8.6 billion in Shanghai's biggest-ever semiconductor listing last month and surged 466% on debut to become the most valuable company on any mainland exchange. Every one of these firms sits on the U.S. Entity List or depends on suppliers that do, and every one just posted record or near-record numbers.

Beijing had until recently been blocking Chinese imports of U.S. accelerators. The US approved around 10 Chinese firms to buy Nvidia's H200 in May, but China had been blocking the purchases to protect domestic suppliers. Under Secretary of Commerce Jeffrey Kessler told a congressional hearing on July 14 that "very few" H200s had actually shipped. Officials have relented as of August 19, with ByteDance and Tencent each having received around 10,000 H200 chips, the first meaningful deliveries since the U.S. approved around 10 Chinese firms as buyers.

Some 20,000 delivered accelerators against Huawei's target of 600,000 Ascend 910Cs this year leaves Chinese cloud spending, which Goldman Sachs pegs at roughly $102 billion for 2026 in combined AI capex across Alibaba, Tencent, ByteDance, and Baidu, landing overwhelmingly on domestic silicon.

SMIC's 7nm yields and the HBM shortage

SMIC's leading-edge economics remain brutal, however, with industry sources cited by the Financial Times putting SMIC's 5nm and 7nm prices 40% to 50% above TSMC's with yields of less than a third, a consequence of running multi-patterned DUV on nodes designed for EUV. The wafers SMIC is repricing are overwhelmingly mature-node parts, where its cost position is sound; the advanced capacity that feeds Ascend production stays yield-limited and expensive per good die regardless.

Memory, not logic, caps accelerator output anyway, and SemiAnalysis estimates Huawei has been drawing down a stockpile of roughly 13 million Samsung HBM stacks acquired before the late-2024 controls, and domestic HBM from CXMT will cover only a fraction of 2026 Ascend targets.

SMIC's own profit surge also comes with a glaring asterisk: CFO Wu Junfeng said the near-tripling was boosted by a one-time gain from a subsidiary. Demand for its silicon rests largely on policy rather than proven end markets, with an analyst tally cited by Asia Times putting China's top 11 listed chip firms at a combined average of roughly 122 times projected 2026 earnings.

Japanese chemical maker Ajinomoto has reportedly told customers in mainland China that it will cut supply of ABF, the insulating build-up film that's used in nearly every high-end processor package, by 30%, according to a report from the Chinese outlet JW Insights, which cites unnamed supply chain sources.

If true, that would be painful for Chinese customers like Shennan Circuits, Xingsen Technology, and Shenghong Electronics, who rely on Ajinomoto's reported 95% global market share of the film. In contrast, China's self-sufficiency rate is thought to sit below 5%.

JW Insights attributes the cut to Ajinomoto prioritizing Japanese customers and core overseas accounts, which supply the FC-BGA substrates under Nvidia, AMD, and Intel accelerators, over mainland buyers. Whether or not the 30% figure holds up, the squeeze is well documented, and China's response was underway long ago.

A confirmed shortage

Ajinomoto's ABF production ran at roughly 2 million square meters per month at full utilization in the second quarter. The company has committed ¥25 billion (around $156 million USD) since 2023 to expand capacity by about 50% by 2030, and land purchased in Kani City, Gifu Prefecture, hosts a third plant not expected to come online until around 2032.

In the fiscal year ended March 31, Ajinomoto reported that ABF sales grew 25% with margins above 50%, and the share of its film going into servers and networking silicon reached 70%, up from 40% in fiscal 2017. According to Goldman Sachs, the gap between ABF substrate supply and demand will widen from around 10% in the second half of 2026 to 21% in 2027 and 42% in 2028.

Ajinomoto notified substrate makers in May of a roughly 30% price hike taking effect this quarter, two months after UK activist fund Palliser Capital disclosed a top-25 shareholding on March 31 and publicly demanded the company raise ABF prices by more than 30%. That hike is confirmed, even if the volume cut isn't. ABF material accounts for about 30% of a substrate's bill of materials, so the increase flows directly into the cost of every FC-BGA package built on it. We've been tracking ABF crunches since the shortage that constrained GPU production in 2021 and 2022, and the current cycle looks to be extending a pattern that's already hit BT resin substrates and T-glass cloth, where single Japanese suppliers also dominate.

China has three films in qualification

Huazheng New Material's CBF, developed with the Shenzhen Institute of Advanced Electronic Materials, is the most mature of China's three named alternatives. The film uses a modified epoxy resin with spherical silica filler, which routes around Ajinomoto's IP rather than copying it. According to reports coming from Chinese media, its mass-production yield sits at above 85%, with reliability testing reportedly having passed inside Huawei Ascend systems and validation underway at Xingsen and Shennan Circuits. Huazheng's first production line of 3 million square meters per year is said to be running at full utilization, and a second line doubling that is slated to come online at the end of 2026.

Lotus Holdings, best known in China as a producer of MSG, acquired 51% of Shenzhen Newface, the developer of NBF, in April for roughly ¥103 million. Newface is said to have qualified all products below nine build-up layers, with nine- to 11-layer films in development and validation underway at Taiwanese substrate makers. Ajinomoto itself is a food and seasonings company that derived ABF from its amino acid chemistry in the 1990s.

Hongchang Electronics' GBF, co-developed with Taiwan's Jinghua Technology, has been validated at a leading domestic OSAT and is in small-volume trial production, with scale-up targeted for the fourth quarter. All three films face the same challenge of downstream reliability qualification taking one to three years of thermal cycling, damp-heat aging, and electrical testing, often longer than the R&D itself, and the highest layer-count films under flagship AI accelerators remain unmatched domestically. Upstream inputs, including specialty resins and spherical silica filler, are themselves partly import-dependent.

Huawei's Ascend packaging sidesteps ABF

Huawei's Ascend 910C reportedly connects two compute dies on separate silicon interposers through an organic substrate, an approach SemiAnalysis has described as trading die-to-die bandwidth for yield and cost against Nvidia's CoWoS.

That architecture makes Huawei less dependent on the high layer-count ABF-based FC-BGA substrates that Nvidia's B200 and GB200, AMD's MI300X, and Intel's accelerators sit on, and Chinese reporting seems to position Ascend as the anchor qualification target for both CBF and GBF. Cambricon, Biren, Moore Threads, and Alibaba's T-Head, which package on conventional FC-BGA, are directly exposed to any mainland ABF supply disruptions.

China banned exports of dual-use items to Japanese military-linked end users back in January through Ministry of Commerce Announcement No. 1, following Prime Minister Sanae Takaichi's November remarks on a Taiwan contingency, with measurable fallout. Chinese exports of restricted rare earths to Japan fell roughly 51% year-over-year in the first half of 2026, Nikkei Asia reported, and Japan imported just 13 tons of dysprosium in the period, down 82% from two years earlier, per TrendForce.

Ajinomoto's move to cut ABF supply to China eight months later has obvious retaliatory optics, despite every account of the alleged cut attributing it to capacity allocation under AI demand. China's rare-earth controls have so far targeted materials where China holds the leverage, and ABF is a market where it holds none.

Meanwhile, BOE signed a three-year glass substrate agreement with Corning in May and designated glass-core packaging a strategic business in July, and Lens Technology announced a through-glass-via collaboration with Intel the same month, extending China's push into glass substrates as the longer-term route around Japanese film.

A glass core swaps out the middle layer of a substrate, but the chip package still needs insulating film built up on either side, so glass doesn't remove the need for ABF or its substitutes. None of China's glass projects has reached mass production either. Until that changes, China's answer to the reported cut depends on whether Shennan, Xingsen, and Shenghong qualify their domestic films.

Intel is set to raise $19.7 billion by selling new common stock in a bid to finance the building out of new production capacity, the development of next-generation leading-edge process technologies like 14A and others, and day-to-day operations. While the company does not assign money to a particular project, Intel needs to build capacity to land orders from large external clients, so capacity expansion will likely be a priority. According to Bloomberg, the share sale attracted $100 billion in demand.

Intel will sell 210,526,315 shares for $95 apiece through an underwritten public offering. In addition, participating banks have 30 days to acquire as many as 31,578,947 more shares at the same $95 price, minus applicable underwriting discounts. Should they exercise all their options, Intel could sell approximately 242.1 million shares altogether and increase the proceeds to roughly $23 billion. Without the additional shares, Intel expects net proceeds of approximately $19.7 billion after underwriting discounts, commissions, and estimated expenses. The transaction is scheduled to close on August 12, 2026.

Intel's market capitalization increased from roughly $90 billion last August to $491 billion at press time, so the time is right to sell some shares and raise some much-needed cash, as the company must compete against giants like TSMC and Samsung, which spend tens of billions of dollars every year on new fabs and advanced process technologies. Meanwhile, Intel's capitalization reached its all-time high of $673 billion on June 20, 2026.

Intel has not assigned the money it is going to raise to particular projects and says the capital can be used across the business, including for capital expenditures and working capital. The company is currently ramping up its Fab 52 in Arizona and is on track to start using adjacent Fab 62 when it needs to. In addition, the company still has to build its fab complex in Ohio, which is expected to cost over $100 billion when fully built, so it badly needs money.

In its risk disclosures, the company specifically mentioned Intel 14A — which is due to enter mass production in 2028 — and other advanced process technologies, manufacturing expansion required to support them, and the need to secure design wins and volume commitments from major external foundry customers. While Intel does caution that these long-term investments amounting to tens of billions may not generate adequate returns, it is impossible to land sizeable contracts from external customers without having production capacity readily available.

Interestingly, Intel also mentioned alternative financing arrangements, government grants, and the U.S. government's significant equity position in the company among relevant factors.

House Select Committee on China Chairman John Moolenaar has written a letter that demands the U.S. government enforce an existing export control measure designed to prevent Chinese companies from getting advanced chips produced by contract chipmakers like TSMC or Samsung Foundry.

When Joe Biden was about to leave the office in early 2025, he signed a law that required chipmakers to determine their end customers in a bid to prevent contract manufacturers from unknowingly fabricating chips using American technologies for companies that served as intermediaries for restricted organizations tied to the Communist Party or the People Liberation Army. The regulation was introduced after it was discovered that chips made by TSMC for China-based Sophgo were actually Huawei's Ascend 910B AI accelerators. However, the Trump administration announced in May 2025 that it would not enforce this semiconductor regulation known as the 'Foundry Due Diligence Rule,' which naturally created uncertainty about whether the foundry-focused requirements would be actively implemented at all.

"The announcement created ambiguity as to whether front-end fabricators like TSMC can export unpackaged advanced dies to non-approved designers located outside of China, without performing the due diligence specified in the Foundry Due Diligence Interim Final Rule (IFR)," the letter reads. "These exports enabled Huawei to obtain millions of controlled Ascend logic dies from TSMC, using its front company, Sophgo in 2023 and 2024."

Before the adoption of the 'Foundry Due Diligence Rule,' Chinese companies and/or their intermediaries could misrepresent chip specifications and end users when placing orders with TSMC or other foundries, which allowed restricted devices to be made despite U.S. export controls. Under the rule, foundries and OSAT providers exporting chips produced on 14/16nm-class process technologies or more advanced nodes must presume those devices qualify as controlled AI processors subject to a global licensing requirement, unless they meet an exemption. According to the letter, foundries have generally complied with these requirements since the rule took effect. As a result, Moolenaar essentially asks the government to enforce the existing controls rather than introduce stricter export controls.

Moolenaar believes that the Commerce Department's Bureau of Industry and Security could clarify its current stance on the Foundry Due Diligence Rule in two ways:

• By issuing guidance, which confirms that the worldwide Regional Stability (RS) licensing requirement still applies to exports from front-end foundries;
• By formally annulling the AI Diffusion IFR and amending §744.23 to explicitly restore that requirement for both foundries and OSAT providers.

Either approach would eliminate conflicting interpretations and reinforce enforcement of existing export controls, Moolenaar believes.

Apple used to be among a few companies willing to buy memory and other components worth billions of dollars under long-term supply contracts at fixed prices. But the artificial intelligence era represents a new reality with new purchasing champions, marking a tectonic shift in the high-tech world. Alphabet, Microsoft, Meta, and Amazon have purchase commitments totaling about $2 trillion, and a significant portion of these commitments are for memory, according to estimates by analyst Claus Aasholm. While the commitments are approximate, span many years, and should be generally taken with a grain of salt, they still reflect the direction the industry is moving.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

Most megafactories usually take years to go from conceptualization to construction, but a recent drone flyover of the Terafab showed that progress has already started on the ground less than five months after Musk unveiled it. However, the video doesn’t do justice to the true scale of its footprint, so X user Nic Cruz Patane created a visualization to help us understand how large the chip manufacturing facility is.

The site will reportedly have a floor space of at least 100 million square feet, making it larger than Giga Texas (10 million sq. ft), the Pentagon (6.6 million sq. ft), Apple Park (2.82 million sq. ft), and the Mall of America (5.6 million sq. ft), combined. This also makes it significantly larger than New Century Global Center in Chengdu, China, with has an interior space of “just” 18.9 million sq. ft.

While this might seem like an absurd amount of space for chip manufacturing, it appears that the Terafab will need it because it’s going to be more than just a chip fab making AI processors — instead, it will be an all-in-one facility that will produce logic and memory chips, as well as have lithography, packaging, and testing under one roof.

Elon Musk started talking about building his own chip manufacturing facility in late 2025 and officially announced the project in March of this year. The reasoning behind this project is that both SpaceX and Tesla will require at least 1TW of compute, which is more than ten times that current global chip supply.

Nvidia CEO Jensen Huang warned that a project like this will be an “extremely hard” challenge, but it appears that Musk is willing to put his massive resources on the line for this. Intel CEO Lip-Bu Tan even said that he can “think of no better partner than Elon Musk” to explore “unconventional” ways of chip manufacturing.

Musk is no stranger to both leading and funding projects that otherwise seemed impossible. Although he did not found Tesla, his investment and leadership in the company led it to become an industry trailblazer in EVs. He fundamentally changed commercial space travel with SpaceX; something that used to be the purview of NASA and other national governments, and he also broke a record when he set up 100,000 Nvidia H200 GPUs in just 19 days back in 2024 — a process which Huang said usually takes four years.

It seems that Terafab is Musk’s biggest project to date, which is estimated to require up to $119 billion in investments. But even though it seems that this project already has a secure customer base in SpaceX and Tesla, the former acknowledges that there’s a risk that this ambitious megafactory may not be successful.

SpaceX and Tesla on Thursday formally unveiled plans for the initial phase of their Terafab project. The first stage of the plan — which is expected to use Intel's 14A process technology — is expected to require $16.8 billion in investment, while the completed campus is planned to encompass more than 100 million square feet of manufacturing space. The massive semiconductor manufacturing complex will be built in Grimes County, Texas, at a location that belongs to SpaceX.

According to SpaceX and Tesla, their combined demand for semiconductors is projected to exceed 1 terawatt (TW) of compute per year, which significantly exceeds today's global supply. In fact, SpaceX, Tesla, and xAI already consume a significant portion of contract chipmaking services available today, and can potentially justify building a dedicated fab that will exclusively serve Elon Musk's companies. In particular, Terafab is envisioned to exclusively produce AI inference processors for Tesla Optimus humanoid robots and Cybercab autonomous vehicles, as well as 'high-power' processors intended for SpaceX's space-based data centers. Meanwhile, SpaceX and Tesla have not disclosed when their combined demand for compute per year will hit the 1 TW benchmark.

Unlike a conventional semiconductor fab, Terafab is envisioned as a vertically integrated manufacturing campus where advanced logic devices, memory chips, packaging, and testing operations are housed together. Normally, logic and memory are produced at different fabs using different process technologies, whereas packaging and testing services are performed at different facilities. However, the companies believe that consolidating logic, memory, packaging, and testing in one location will not only shorten the production cycle but will also shorten time-to-yield by enabling faster iterative improvements.

Given the description and the goal of the project, this will be a massive facility. Yet, SpaceX and Tesla have said little about its capabilities; The only thing they have disclosed is that the current facility in Grimes County will feature '100 million square feet of manufacturing space.' The 100 million square feet (9.3 million square meters) figure immediately stands out because it is far beyond anything ever announced for a semiconductor manufacturing facility. For example, the total area of Samsung's Pyeongtaek campus is approximately 2.89 million square meters, or 31.1 million square feet. A single Samsung fab occupies about 120,000 square meters, or 1.29 million square feet. However, the key wording is important: '100 million square feet of manufacturing space' does not mean 100 million square feet of cleanroom space.

Based on an image published by SpaceX, the Terafab facility will occupy four massive buildings. It is unclear whether these buildings will be four phases of the project (i.e., logic, memory, and packaging will be made under one roof) or will serve different purposes (i.e., one building makes logic, another produces memory, yet another does testing and packaging). In any case, when fully built, Terafab will be a massive semiconductor production campus that will require significantly more than $16.8 billion.

The announcement claims that the Terafab facility will employ at least 3,000 people, and that between 60% and 80% of them will be Grimes and nearby Brazos County residents.

Terafab is expected to use water from Gibbons Creek Reservoir instead of local groundwater and feature on-site wastewater treatment as well as water recycling and conservation measures.

The announcement follows Tesla's groundbreaking earlier this year on a research semiconductor facility at the North Campus of Tesla's Giga Texas campus, which the companies describe as a precursor to Terafab.

China has started low-volume production of domestically developed immersion DUV lithography machines, with around five systems planned for this year and roughly 20 in 2027, according to a report from July 27, which wiped roughly $44 billion off ASML's market value.

The manufacturer was named as Shanghai Aishengna Electronic Technology Group by Reuters the following day, a state-owned company established in August 2023 with 7 billion yuan (around $1 billion) in registered capital that absorbed engineering teams from Huawei-affiliated startup Yuliangsheng and state scanner maker SMEE. The first units are due at SMIC, Hua Hong, and CXMT this year for production-line validation rather than volume output, but the machines are far from matching ASML's models and still require further testing.

Five machines represent about 3.8% of the roughly 130 immersion systems ASML deploys in a typical year (a class of lithography machines that put a super thin layer of liquid over the wafer during processing), with the European giant holding an estimated 98.7% of the total immersion market. The Chinese tool reportedly prints 28nm-class features in a single exposure and reaches 7nm, and theoretically 5nm, through multipatterning, the same route SMIC already runs on its installed ASML fleet. Neither company has confirmed the report, no machine has been shown publicly, and no throughput or overlay figures have been disclosed, against the 330 wafers per hour and 2.5nm overlay of ASML's current flagship immersion tools.

SMIC’s scanner

SMIC has been running a domestic immersion scanner, developed under the codename Mount Everest, since September last year, when the Financial Times reported that China's largest foundry had begun testing the Yuliangsheng tool with production-line integration targeted from 2027 after qualification.

FT compared the machine against ASML's Twinscan NXT:1950i, a system that entered the market in 2008, which puts the design roughly a decade and a half behind the tools ASML sells today. Yuliangsheng, founded in Shanghai in 2022 with 1 billion yuan (around $149 million) in registered capital, is understood to have delivered three lithography machines to fabs for testing by late last year, but this hasn’t been officially confirmed.

Many of the critical components needed for the machines are still imported from Japan, and delays at those local suppliers are what have capped 2026 output at around five units. The 2027 target of 20 machines is therefore an ambitious target that assumes a domestic component base that hasn't been established yet, and the imported parts remain within reach of any future export-control round.

18% litho localization

SMEE's most advanced shipping product remains the SSA600 series, a 90nm-class dry ArF scanner that was in mass production as of May last year. The 28nm-capable SSA/800 immersion tool the company announced in 2023 has never been deployed, and a state-media claim of its successful development was deleted shortly after publication. In December last year, SMEE won a roughly RMB 110 million ($16 million) single-source government contract for a KrF scanner specified at 110nm resolution and 15nm overlay, a useful indicator of where its production-grade capability is at the moment.

Domestic equipment took 35% of Chinese fab purchases in 2025, beating Beijing's 30% target and up from about 10% three years earlier, according to figures from China's semiconductor industry association. Etch and thin-film deposition passed 40% localization, and metrology reached 25%, while lithography managed just 18%, most of it in trailing-edge and packaging tools. From the end of 2025, new fab capacity additions are required to source at least half their equipment domestically, a mandate that guarantees the new scanners a customer base, whatever their specs turn out to be.

Etch, deposition, and everything else

Naura Technology became the world's fifth-largest chip equipment maker by 2025 sales, trailing only ASML, Applied Materials, Lam Research, and Tokyo Electron, and moving ahead of KLA. The company booked RMB 27.14 billion ($4 billion USD) in revenue in the first three quarters of 2025 against RMB 6.05 billion ($589 million USD) for all of 2020, holds an order backlog stretching into 2027, and has started developing lithography tools for the first time. AMEC grew revenue and net profit by more than 30% in 2025, while cleaning specialist ACM Research posted $901.3 million for fiscal 2025 and guided to as much as $1.18 billion for 2026.

SiCarrier, the Shenzhen firm widely linked to Huawei, debuted around 30 tools at SEMICON China in March 2025, spanning etch, deposition, metrology, and test, and was reportedly valued at RMB 65 billion ($9.63 billion USD) by September 2025 with more than RMB 10 billion ($1.48 billion USD) in orders. The U.S. added it to the Entity List in December 2024.

The sector's own leadership is less triumphant than the numbers suggest. In March, SMIC co-founder Wang Yangyuan and the heads of YMTC, Naura, and EDA firm Empyrean jointly described China's tool industry as "small, fragmented, and weak" and called for national consolidation, with Big Fund III's $47.5 billion being redirected toward lithography and EDA. The Aishengna venture, which merged the Yuliangsheng and SMEE teams into one state-owned vehicle, looks like the first product of that pressure to consolidate. China spent a record $49.5 billion on wafer fab equipment in 2024, per SEMI, and remains the world's largest buyer through 2027, even after a pullback in 2025.

EUV lithography

A Reuters investigation in December 2025, dubbed China’s “Manhattan Project,” described an operational prototype EUV light-source machine in a high-security Shenzhen lab, completed in early 2025, that generates EUV photons but hasn't yet exposed a wafer. More than 3,000 researchers are said to work across the program, with Huawei playing the coordinating role and SMEE handling system integration.

Two teams are chasing the light source: one led by Lin Nan, a Beihang University professor who worked at ASML from 2015 to 2021, has a solid-state laser-produced-plasma design running at 3.42% conversion efficiency against the roughly 5.5% commercial viability required, while Zhao Yongpeng's laser-assisted discharge plasma group at Harbin Institute of Technology has reached around 100W of EUV output against the roughly 600W that ASML's production sources deliver.

Beijing's target is chip output from the machine by 2028, with Reuters' sources calling 2030 more realistic. A separate strand of reporting described a reverse-engineered prototype built around an intercepted Cymer light source that has likewise produced nothing. Earlier claims of a Huawei EUV trial production in 2025 and mass production in 2026, which circulated via Chinese media in March 2025, were never confirmed by any primary source. Tsinghua University's accelerator-based SSMB concept, which would need a synchrotron of a staggering 100 to 150 meters in circumference, remains an academic project.

Export controls

The MATCH Act, introduced in the House and Senate in early April, would ban not only sales of immersion DUV tools to SMIC, Huawei, Hua Hong, CXMT, and YMTC but also the servicing of machines already installed, and would give the Netherlands and Japan 150 days to align.

At this stage, it remains a bill, not a law, but servicing restrictions would strike directly at the installed ASML base that produces every advanced chip China currently makes, including SMIC's N+3 node in Huawei's Kirin 9030. Chinese fabs have been preparing for exactly that scenario by using third-party engineers and gray-market parts to Frankenstein older ASML machines.

ASML's China exposure is already shrinking on schedule, with the country representing 20% of system sales compared to 41% in 2024 and 33% last year, even as the company raised full-year guidance to €43 to €45 billion in July. Likewise, Applied Materials expects to lose $600 to $710 million in China revenue this fiscal year.

Ultimately, three markers will indicate whether China’s domestic DUV program is a legitimate rival or yet more state-sanctioned hot air. The main one would be validated production wafers from an Aishengna tool at SMIC, Hua Hong, or CXMT with published throughput and yield, followed by delivery of anything close to the 20 machines planned for 2027, and a first exposed wafer from the Shenzhen EUV prototype before the 2028 target set by Beijing.

China has revised its regulations concerning protection of integrated circuit (IC) layout designs developed domestically. The new regulations are intended to make it harder for Chinese companies to obtain legal protection for copied chip designs by tightening originality requirements, registration procedures, and infringement remedies, Reuters reports. As a result, it will get harder for underperforming China-based companies to copy ICs developed by their more successful rivals. Meanwhile, Chinese chipmakers will be allowed to produce their designs in Taiwan or South Korea.

The amended regulations apply to physical chip layout designs that define how circuit elements are arranged on silicon and represent a substantial amount of engineering work, including for companies that specialize in chip design rather than manufacturing. To qualify for legal protection of their IC layouts, applications must now demonstrate that the layout was independently developed, formally attest that the design is original, and specify which parts of the layout constitute their own creative contribution (perhaps to give authorities an idea about which were licensed or obtained from open sources). As a result, authorities will be able to filter out weak claims and distinguish companies with strong technological capabilities. Furthermore, they will also be able to determine whether a particular chip was designed and built in China, or its alleged developer obtained its product elsewhere and attempts to disguise it as a 'Made in China' silicon.

The new rules also strengthen enforcement. From mid-October and onwards, in infringement disputes, courts may determine compensation based either on losses suffered by the rights holder or profits earned by the infringing party. Punitive damages will also become an option. In addition, the regulations clarify procedures for licensing, transferring, or using IC layout-design rights as collateral. Organizations that develop protected layouts are also required to provide reasonable rewards and payments to personnel responsible for creating those designs.

Chinese policymakers were also reportedly considering measures to prevent strategically important domestic technologies from being transferred abroad, acquired by foreign companies, or produced overseas. If these strict proposals were approved by the CCP and the government, Chinese chip designers would be unable to produce their chips at TSMC in Taiwan or Samsung Foundry in South Korea, and would force them to exclusively make them domestically at Semiconductor Manufacturing International Corp., Hua Hong, and other domestic contract producers that are decades behind market leaders.

The report claims the updated regulations reflect the strategic importance China now assigns to technologies developed by its domestic semiconductor industry. For now, it is evident that China is not ready to implement overseas production of advanced designs. However, the report does not explicitly claim they are completely off the table, according to Reuters.

The updated rules were signed by Premier Li Qiang on July 23 and will take effect on October 15.

Drone flyovers of Elon Musk’s new Advanced Technology Chip Fab (ATCF) in Texas have been shared on social media. The videos and photos come courtesy of flight instructor and drone videographer Joe Tegtmeyer (@JoeTegtmeyer), who regularly documents the progress of Giga Texas and Starbase projects. Considering that the fab was only announced on March 21 this year, groundwork has been brisk, and in a follow-up post, Tegtmeyer states progress has “hit another gear.”

In the above post, the all-things-space enthusiast notes that the ATCF already appears to be very well defined. “GeoPiers are at work on the part of the foundation that has had gravel mix placed on the top soil and more work grading on the south end,” he explains.

A few days later, there was an update with progress clearly accelerating, according to Tegtmeyer. As well as commenting on the shape of the facility becoming ever clearer and construction materials continuing to be stockpiled, there are other important signs of progress. Specifically, “4 new permits were filed in the past few days for the large trailer complex that houses the general contractors and the temporary Tesla offices for the new facility,” noted the enthusiast. “[It is] a great sign that things are progressing rapidly behind the scenes to fit out the facility when construction progresses far enough to allow for equipment installation.”

Importantly, Tegtmeyer reminds his followers that the ATCF is not the Terafab that will be built ~ 100 miles or so to the East in Grimes County, Texas. Rather, the ATCF is the equally vital but “smaller development facility that is the first part of the overall AI Chip development program.”

The ATCF is a joint Tesla–SpaceX facility, and is a keystone for the Tesla, SpaceX, and xAI accelerator chips to come. It is expected that chips from the ATCF will combine logic, memory, and advanced packaging under one roof. Projects spawned from here are destined to support Tesla cars and Robotaxis, Optimus robots, and upcoming Earth-orbiting AI data centers.

That’s distinct from the much larger, multi-phase, vertically integrated, 1TW/year Terafab megaproject, which will see collabs between Tesla, SpaceX, xAI, and Intel. It has massive AI computer production ambitions to feed terrestrial and space-based AI systems. We are still awaiting evidence that the Terafab has moved beyond the pre-construction phase.

If there were any doubt about the seriousness of Musk's semiconductor design and fabrication ambitions in these and other progress reports, ASML CEO Christophe Fouquet recently confirmed talks with Musk had taken place about building one of the largest chip manufacturing operations ever attempted. SpaceX has also already filed for a $55 billion facility in Grimes County, Texas, with potential expansion costs reaching $119 billion, and phase one potentially beginning before the end of the year. Meanwhile, it is good to see the rapid progress of the smaller ATCF.

Lumentum CEO Michael Hurlston told an audience at the RAISE Summit in Paris earlier this month that indium phosphide, the compound semiconductor behind every laser in an AI data center, is heading into a supply squeeze worse than what we've already seen with DRAM / NAND, and that Nvidia's decision to fund Lumentum and its biggest competitor at the same time was a response to exactly that.

In his remarks, Hurlston said that telecom customers bought lasers in the hundreds, while Nvidia and the hyperscalers are asking for hundreds of millions. While Lumentum runs five indium phosphide fabs, it's still shipping more than 30% below what customers want. Nvidia's answer, in March, was to write $2 billion checks to Lumentum and Coherent, the two suppliers that, between them, make most of the world's high-speed datacom lasers, with purchase commitments and future capacity access attached to both.

"Between the two of us, I don't think we can service the demand that Nvidia and others are now putting on us to solve this resistance problem in the data center," Hurlston added.

Silicon doesn't emit light

Indium phosphide has a direct bandgap of roughly 1.34 eV, which lets it convert electrical current into photons efficiently. Silicon's bandgap is indirect, so it can guide, split, and modulate light but can't generate it. Every silicon photonics platform in production, including those of Nvidia, Broadcom, Marvell, and Cisco, still needs an indium phosphide laser somewhere in the package to supply the light for silicon to manipulate. Moving from pluggable transceivers to co-packaged optics changes where that laser sits and how it's mounted, but it doesn't remove it from the bill of materials.

Nvidia's marketing claims its photonics switches use four times fewer lasers than an equivalent pluggable deployment, alongside 3.5 times better power efficiency and ten times better network resiliency, all of which are vendor figures. Those savings are per port, and it's that port count that's exploding.

The high-end Spectrum-X Photonics configuration runs 512 ports at 800 Gb/s for 400 Tb/s of switching, and Quantum-X Photonics InfiniBand runs 144 ports at 800 Gb/s. Co-packaging also shifts the laser type toward high-power continuous-wave sources and external laser modules that feed multiple channels, which are harder to build than the electro-absorption modulated lasers inside a conventional pluggable. Coherent's Nvidia agreement covers that category of high-power CW lasers, external laser source modules, and fiber array units.

Capacity at Lumentum and Coherent

Lumentum posted record revenue of $808.4 million in its fiscal third quarter, up 90% year over year, with components revenue of $533 million and pump laser shipments up 80%. On the May earnings call, Hurlston told analysts the company expects its supply line to increase 50% measured from one December quarter to the next, and in the same breath said the supply-demand imbalance on EMLs had widened from the 25% to 30% given a quarter earlier to "somewhere greater than 30%," with pump lasers tighter still. A supplier growing output by half a turn per year and losing ground anyway is a clean measure of how steep the demand curve is.

Coherent's 6-inch indium phosphide line yields more than four times as many devices as its 3-inch line at less than half the cost, CEO Jim Anderson told investors on the company's fiscal Q3 call. Anderson said EMLs, CW lasers, and photodiodes are all in production on the 6-inch line with yields above the legacy 3-inch lines, and that internal capacity would double by the end of the June quarter, one quarter ahead of plan, then more than double again by the end of 2027. Coherent's revenue hit a record $1.8 billion, up 21%, with data center and communications now 75% of the total against roughly 41% a year earlier, and backlog stretching into 2028.

Logic and memory moved to 300mm wafers in the early 2000s. Indium phosphide is a brittle, expensive, small-boule material where the industry-wide upgrade currently underway is 3-inch to 6-inch, roughly the transition silicon completed in the 1980s. Lumentum's fifth fab, announced in March, is a converted Qorvo gallium arsenide plant in Greensboro, North Carolina, described as 4-inch and 6-inch compatible and ramping around 2028.

Running through China

Indium is recovered as a byproduct of zinc refining, so its output can't be scaled independently of zinc economics, no matter how much laser demand there is. The USGS Mineral Commodity Summaries 2026 put China at an estimated 760 tonnes of roughly 1,100 tonnes of global primary refined indium in 2025, about 69%, and recorded a 72% year-over-year fall in unwrought indium exports between September 2024 and September 2025 after Beijing placed the metal under export controls in February last year. The U.S. warehouse price averaged about $390 per kilogram in 2025 against $340 in 2024.

AXT's Chinese subsidiary Tongmei had to obtain Ministry of Commerce export permits, granted in June and August 2025, before it could resume shipping indium phosphide substrates out of China. The fabs Nvidia is funding sit downstream of that licensing regime, and the wafers going into them aren't made in the United States in meaningful volume.

DRAM contract prices rose 90% to 95% quarter over quarter in Q1 2026, the largest quarterly increase TrendForce has recorded, and the firm forecast a further 58% to 63% in Q2 with NAND up 70% to 75%. HBM is sold out for 2026. Hurlston is measuring his warning against a genuinely historic crunch, which makes it a strong claim rather than a throwaway one, and he runs a company whose valuation depends on the shortage persisting.

LightCounting's April 2026 market forecast puts current transceiver demand about 30% above supply, matching Lumentum's own figure, but states that the shortages should be gone by the end of 2026 and cuts expected Ethernet transceiver growth to 65% for the year after 82% in 2025 and 93% in 2024. Coherent, hitting its capacity doubling a quarter early, points the same way. The distinction from memory is that the fix here is a wafer-size transition already running in production with yields ahead of the old node, not a new fab that takes three years to build.

Reuters has named Shanghai Aishengna Electronic Technology Group as the state-owned company producing China's first domestic immersion deep ultraviolet lithography (DUV) scanners, a day after news of the program broke without identifying the manufacturer. Aishengna was established in August 2023 with RMB 7 billion, around $1 billion, in registered capital and is thought to have absorbed engineering teams from Shanghai Yuliangsheng Technology and Shanghai Micro Electronics Equipment.

Aishengna has been named by a single source who declined to be named, and its shareholders, SMEE and Yuliangsheng, didn’t respond to requests for comment. SMIC has been testing a Yuliangsheng immersion tool since September 2025, and first deliveries are slated for SMIC, Hua Hong Semiconductor, and ChangXin Memory Technologies.

Photoresist, coater tracks, and light sources

Tokyo Electron held an 89% share of the global coater/developer market in 2022, per Shared Research's analysis of the company's own disclosures, with its chief executive putting the figure near 90% and at 100% for EUV production. A scanner only exposes the wafer, however. It’s the track that's responsible for applying the resist film, baking it, and developing the pattern after exposure, and it has to be mechanically and thermally matched to the scanner in a single cluster, which is why the two are bought together. Shenyang Kingsemi has reached 28nm-class track capability and is currently targeting 14nm.

JSR, Tokyo Ohka Kogyo, Shin-Etsu, and Fujifilm hold a combined 72.5% of the ArF photoresist market, while Chinese suppliers hold under 1% of ArF immersion resist specifically. Nata Opto-electronic built a 25-ton ArF line, later expanded to 50 tons, passed customer qualification in December 2020, and completed project acceptance in 2024 with little volume to show for it. Xuzhou B&C says its ArF immersion products cover 45nm to 28nm and can stretch to 14nm, and chairman Fu Zhiwei has put mass production of China's core advanced resists five years out.

Cymer, Gigaphoton, and Coherent hold more than 80% of the ArF excimer laser market between them, and Cymer has been an ASML subsidiary since 2013. Beijing RSLaser shipped China's first high-power domestic excimer laser in 2018 under the national Project 02 program and has a 4 kHz 193nm ArF prototype aimed at 90nm and 65nm-class tools, generations behind what 28nm immersion requires.

Carl Zeiss SMT has been ASML's sole projection optics supplier since 1983, and Zeiss SMT revenue grew from €1.2 billion in 2016 to €4.1 billion in 2024. It’s not currently known what, if any, Japanese tooling is inside the Aishengna machines, but excimer sources and precision optics are areas where Chinese substitution is believed to be lacking.

CXMT

CXMT is projected to reach around 350,000 wafer starts per month by the end of 2026, roughly 25,000 short of Micron, up from 40,000 in 2020. DRAM scaling at 1a and 1b-class nodes runs on immersion multipatterning because CXMT has no EUV access, which makes any potential ramp lithography-gated rather than cleanroom-gated. DRAM contract prices rose 93% to 98% quarter on quarter in Q1 2026, and TrendForce projected a further 58% to 63% in Q2, lifting DRAM industry revenue 81% to $97 billion. A domestic immersion source is therefore worth having to CXMT, even at inferior overlay and throughput.

A DUV-only 7nm flow needs roughly 19 spacer-defined multipatterning masks from the front end through the second metal layer, against about 10 for an EUV-based N7+ process, by one published comparison of SMIC's process. SemiAnalysis has put SMIC's 7nm defect density near 0.14, around double TSMC's N5 and N6. ASML CEO Christophe Fouquet told analysts during the company's July earnings call that rising DRAM lithography intensity partly reflects "the increased replacement of multi-patterning with more cost-effective single-exposure EUV." As such, every exposure China adds to compensate for the missing EUV burns scanner hours a thin domestic fleet doesn't have.

The MATCH Act

China fell to about 14% of ASML's sales in Q2 2026 from 33% across 2025, and installed base management, the service and upgrade business, brought in €2.8 billion of ASML's €9.3 billion in second-quarter revenue. H.R. 8170 would ban both the export and the servicing of immersion DUV systems to any destination in China and designate SMIC, Hua Hong, Huawei, CXMT, and YMTC as restricted entities by statute. Former ASML chief executive Peter Wennink has said the company can service most Chinese tools, but not with spare parts of U.S. origin that fall under export control, which is the mechanism that the MATCH Act would widen.

The bill remains in committee after clearing the House Foreign Affairs Committee in April, with a Senate companion filed as S. 4281, and no floor vote yet scheduled. Its 150-day allied-alignment clause would also reach Nikon, which sold 11 ArF immersion systems in FY2024 and none in the first three quarters of FY2025, and which plans to deliver a new immersion prototype to a major chipmaker by 2027. ASML expects about 130 immersion shipments this year and intends to raise immersion capacity 30% in 2027, with a further 30% under investigation for 2028.

As for Chinese providers, SMEE prototyped its SSA600 ArF tool in 2011 and never reached sustained commercial sales, and a late-2023 shareholder claim that the company had developed a 28nm machine was subsequently retracted. SiCarrier showed etch, CVD, PVD, and ALD tools at SEMICON China 2025 without a lithography system, and a December 2025 government contract reported as a lithography award turned out to cover a KrF tool at 110nm. We’ve previously assessed that China’s toolmakers are more than a decade behind the market leaders.

The AI Futures Project's June forecast puts a commercially viable domestic 7nm-capable immersion scanner between 2032 and 2038, with a median of 2035, and claims ASML holds 98.7% of the immersion market today. Five machines in 2026 would be under 4% of ASML's annual immersion output, and each would still need a coater track, a qualified ArF immersion resist, and an excimer source to print a single wafer; China leads in none of those three.

A state-backed company in Shanghai has begun mass-producing immersion deep ultraviolet lithography machines and is due to deliver the first units this year to SMIC, Hua Hong Semiconductor, and memory maker ChangXin Memory Technologies, according to The Information, citing two people familiar with the program. Output targets around five machines in 2026 and roughly 20 in 2027, and all three named recipients sit on the list of Chinese firms that a bill now moving through Congress would cut off from ASML sales and servicing by statute.

The Information didn't name the manufacturer, but its sources described the operation as having pulled DUV development teams from several Chinese companies, one of them the state-backed startup Shanghai Yuliangsheng Technology. SMIC has been testing a Yuliangsheng immersion tool since September 2025. Most components in the new systems are domestic, though some critical parts still come from Japan, and delays at local suppliers have held back output this year.

U.S. House Resolution 8170 designates SMIC, Hua Hong, CXMT, Huawei, and YMTC as restricted entities in law, and three of those five are the named first customers for the domestic scanner. The MATCH Act, introduced in April, was reported out of the House Foreign Affairs Committee on April 22 and has a Senate companion filed as S. 4281. Its immersion DUV provisions cover servicing and technical assistance, not just new exports, which extends its scope to installed tools already operating in Chinese fabs, fabs which have spent the past two years stretching that installed fleet through secondary-channel upgrades.

ASML expects to ship about 130 immersion systems in 2026, matching 2025, CFO Roger Dassen told analysts during the company's July earnings call. Dassen added that ASML intends "to increase capacity by 30% in 2027" for immersion, and is investigating another 30% for 2028. China accounts for around 20% of ASML's net sales this year, down from 33% in 2025, driven mainly by mainstream logic demand.

Immersion DUV prints 28nm-class features in a single exposure and reaches 7nm through multipatterning, at a cost in overlay errors and yield. ASML CEO Christophe Fouquet told the same call that rising DRAM litho intensity partly reflects customers replacing multipatterning with cheaper single-exposure EUV.

Independent analysis from the AI Futures Project in June put commercial-scale Chinese immersion DUV in the mid-2030s, with ASML holding 98.7% of the immersion market. Qualifying the new machines for production lines could take many months, and they trail ASML's tools on performance and build quality. China's domestic EUV effort, which Reuters first reported as a working prototype in December, remains years away.

A new semiconductor firm, TYLsemi (pronounced Tile Semi), publicly revealed itself this month, alongside $43 million in early-stage funding and an ambitious plan to simplify the development of custom processors for AI infrastructure.

Dozens of contract chip designers can develop custom processors of different complexity. However, only a few companies can offer custom silicon design services using standard chiplets to speed up and derisk the development cycle. TYLsemi is aiming to join their ranks. We spoke to their founders to find out how the nascent business might pull it off.

Emerging from stealth

Rather than compete solely as another custom ASIC design house, TYLsemi intends to offer reusable, standards-based connectivity, power delivery, and eventually memory chiplets that customers can combine with their own differentiating compute silicon to build a unique system-in-package. For companies that do not intend to conduct semiconductor development themselves, TYLsemi will also provide an end-to-end service that includes design and implementation of a differentiating chiplet, packaging, qualification, and high-volume production, essentially enabling companies without any silicon development skills to offer their own multi-chiplet processors.

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans who have led global engineering, operations, and business teams at Alphawave, SiFive, Cadence, Rambus, and other chip companies, and who collectively have plenty of experience with both standard and custom silicon. Mohit Gupta, a co-founder and chief executive of TYLsemi, believes that the time to establish a company that specializes in pre-approved chiplets and custom ASIC design is right now.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium. "First, advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; there are options from foundries and OSATs, including TSMC, Intel, ASE, and Amkor. Second, die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, which makes heterogeneous integration much more practical. Third, supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure. Those factors have created an environment that did not exist four or five years ago."

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as we have already learned from AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said. "At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

Chiplet economics

The vast majority of AI and HPC accelerators today feature large die sizes, in many cases approaching the size of a reticle. However, as modern process technologies are becoming more complex, foundries tend to increase their quotes for new nodes. A leading-edge wafer used to cost around $15,000 to process around five years ago, but today that price is around $30,000. As a result, large chips at a size close to the reticle limit implemented on a leading-edge node become an option for a select few chip designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects such as UCIe start to make a lot more sense.

"Once dies get into the 500 – 600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices, from $350 million for a monolithic 700 mm² 3nm-class chip to $150 million for a design combining a 500 mm² 3nm-class compute die with four 100 mm² I/O chiplets built on an N-1 process. TYLsemi believes that the unit price of a monolithic chip would be $3,000, whereas the cost of an SiP would be around $600. The company attributes the saving to higher yields, reusable I/O silicon, lower IP licensing and engineering costs, and substantially lower per-unit silicon costs. However, the company stresses that the figures are illustrative estimates rather than actual manufacturing costs. Additionally, multi-chiplet designs can enable faster product refreshes compared to large monolithic dies as they are faster to develop and yield.

"Compute may move to 2nm or A14, while high-speed I/O can remain on 3nm, since I/O does not scale in the same way as logic," Gupta said. "Our power-delivery chiplets can use an even less advanced process. Customers therefore do not have to use the most expensive silicon real estate for every function. […] There is no single answer for every design. You have to determine the right disaggregation points based on the architecture, thermal requirements, package, and how multiple accelerators communicate. […] The exact partitioning will vary by application, but you still get a better total cost of ownership."

TYLsemi primarily targets AI infrastructure, so it generally envisions multi-chiplet designs to be used for AI accelerators, data-center CPUs, high-performance computing, networking and telecom silicon, and heterogeneous SoCs. However, TYLsemi has also ignored the fact that multi-chiplet designs are already widely used for consumer CPUs and GPUs.

Foundation chiplets

At the core of TYLsemi's proposition are its foundation chiplets, which are reusable building blocks intended to handle common non-compute functions in custom AI and infrastructure processors and are implemented using various process technologies from TSMC. The foundation chiplets include the following:

• TYL.IO — a family of connectivity chiplets that includes TYL. IO PCIe, a 32-lane PCIe 7.0/CXL chiplet connected to the compute die via UCIe; TYL.IO Scale, a 224G+ SerDes for ESUN/UALink scale-up connectivity; and TYL.IO EIC for co-packaged optics.
• TYL.Power — a 16nm in-package IVR chiplet with embedded passives, designed to provide power closer to compute dies and use closed-loop control and die telemetry to improve power delivery.
• TYL.Mem — a planned family of memory-connectivity chiplets. TYLsemi has not yet disclosed the architecture or specifications, though it is safe to assume they are talking about memory controllers and PHYs.

Not all of these chiplets will be available immediately, as the company has certain priorities amid limited resources.

"The first TYL.IO product disaggregates the PCIe functionality that would normally sit on a large server processor, it is a 32-lane PCIe Gen7/CXL chiplet connected to the host compute die using UCIe," Gupta explained. "The idea is that the CPU cores can move to 2nm, A14, or another leading-edge process, while the I/O chiplet remains on 3nm. The next product in the family will address scale-up connectivity between XPUs within a rack using high-speed SerDes. That device will be considerably larger, with around 72 lanes and approximately 14 TB/s of bandwidth. We also have an EIC roadmap for co-packaged optical connectivity. We expect samples of our first I/O product in the second half of 2027."

These chiplets can be used as standalone components or integrated with a customer's compute dies designed by the customer to TYLsemi through TYL.Forge, TYLsemi's end-to-end custom silicon platform.

TYL.Forge

TYL.Forge is arguably one of the key enablers of TYLsemi's business, as the program is aimed at companies that have their own compute architecture or even a compute die, but cannot build their own SiP or manage the entire semiconductor supply chain.

"There are larger custom silicon companies in the market, but many of them focus on a relatively small number of customers that can generate billions of dollars in annual business," Gupta explained. "We see an opportunity among emerging AI companies and system companies that need advanced custom silicon but also need a partner capable of taking responsibility for the entire implementation and supply chain."

Such clients can provide their proprietary compute RTL, while TYLsemi handles physical implementation and integrates the resulting compute die with its pre-validated connectivity, power, and eventually memory chiplets. The company then manages tape-out, packaging, assembly, testing, qualification, and high-volume production.

"For example, a customer building a large accelerator can bring us its matrix-multiplication engine," Gupta said. "We can implement the custom compute die and integrate it with our chiplets, so the customer does not have to reinvent the I/O and other common functions. This reduces risk and time to market."

In fact, TYL.Forge appears flexible about where the customer enters the development process. TYLsemi describes the platform as covering everything from architecture and front-end design through implementation, tape-out, assembly, qualification, and production. So instead of RTL, customers can come to TYLsemi with an architecture/concept, and then the company will help develop and implement the silicon. Nonetheless, TYLsemi does not intend to invent the customer's core compute architecture itself. In addition, customers can bring in an existing compute die, which TYLsemi can combine with its chiplets, package, test, and bring to production.

"We are also talking with companies developing Arm- and RISC-V-based server processors," Gupta said. "They can develop the architecture, while we implement the rest of the silicon and bring the product to production. That gives customers an economic and engineering advantage because they do not need to build teams for every part of the chip."

The key advantage of TYL.Forge is the reuse of pre-validated components. Instead of developing common functions such as PCIe connectivity and power delivery for every new processor, customers can use TYLsemi's pre-validated foundation chiplets and focus engineering resources on differentiated compute architectures, software, and system design. In theory, TYLsemi could integrate third-party chiplets (not from a customer, but from a third-party chiplet provider). Still, the company's focus remains on offering its own pre-validated chiplets and custom silicon with SiPs it builds.

"Potentially, [we could integrate third-party UCIe chiplets into a TYLsemi-based system], UCIe has done a very good job defining the electrical interface, but the ecosystem is still maturing at the protocol level," Gupta explained. "In some cases, if we provide a chiplet to a customer, we may also need to provide or enable the UCIe IP on the other side of the connection. We are committed to UCIe and industry standards because standardization ultimately wins. […] We can consider customization for a large strategic customer or hyperscaler, but we do not want those projects to derail our standard product roadmap. […] Even when customers buy our standalone chiplets, I expect many of them will ask us to handle packaging and testing because heterogeneous integration and supply-chain management are difficult "

TYLsemi estimates that its approach can cut development time and cost by up to 50% compared with traditional custom silicon programs. In the best-case scenario, TYLsemi envisions that the development cycle can shrink considerably compared to today's cycles that can be two, three, or more years long. According to TYLsemi, once a customer provides sufficiently mature RTL or a netlist, the company can take a custom compute die to tape-out in around six to nine months or so, which includes fabrication, assembly, testing, and qualification.

"If a customer provides mature final RTL or a netlist and uses our standardized I/O chiplet, we believe we can take the custom compute die to tape-out in approximately six months in some cases," Gupta explained. "More generally, our target is six to nine months from a mature design to tape-out. The architecture and front-end phase is more customer-dependent. For a first-generation product, that can take around six months; for a more mature second- or third-generation design, it could be closer to three months, and some of that work can overlap with implementation. After tape-out, fabrication can take roughly four to five months depending on the process, followed by perhaps another two months for assembly, testing, and qualification. If the architecture is already mature, it may therefore be possible to reach production samples in about a year."

Still, the company stresses that architecture development and implementation typically include feedback loops, which greatly slow the development process. This is why the company provides the relatively conservative '50%' figure.

TYL.IO and TYL.Power samples will be available to qualified customers in 2027, in partnership with TSMC, and the company is looking forward to designing processors for its clients in time for them to reach the market in 2029 – 2030.

Speaking of TSMC, TYLsemi will initially only offer designs and services adhered to the TSMC ecosystem, though eventually it may offer other options for packaging technologies, such as Intel's EMIB and Foveros, or Amkor's packaging methods.

"We are initially focused on the TSMC ecosystem, but we also intend to explore other advanced-packaging supply chains," Gupta said. "We do not want to limit ourselves to one packaging option. Over time, that could include other OSATs and packaging technologies. […] That could include Intel, ASE, Amkor, or others. Amkor, for example, is building significant packaging capacity in Arizona."

Intel will design, package, and fabricate Fortinet's sixth-generation Security Processor (SP6) on its Intel 4 node, the companies announced on July 21, giving the process its first named external foundry customer, roughly three years after it entered production. Intel told Tom's Hardware the agreement reflects "the strategy Intel outlined for Intel 4 several years ago," including support for custom networking ASIC workloads. Intel's own record from those years reads differently, however, with the company's 2021 roadmap having scoped Intel 4 to two internal products. And through 2022, it told engineers and investors that Intel 3, not Intel 4, would be its first process offered to foundry customers.

Intel 4's record

Intel's Accelerated announcement back in July 2021 said that Intel 4 would reach production readiness in the second half of 2022 for products shipping in 2023, naming "Meteor Lake for client and Granite Rapids for the data center." The release and its accompanying fact sheet, however, contained no reference to foundry customers, networking, or custom ASICs on the node.

At VLSI 2022, Intel disclosed that it wasn't building a high-density library for Intel 4 and that Intel 3 would be the first new node offered through what was then Intel Foundry Services. A 2024 post on Intel's own foundry blog describes Intel 3 as "Intel Foundry's first leading-edge process node," and Intel's fiscal year 2024 annual report listed the processes available to external customers as 18A, Intel 3, Intel 7, Intel 16, and a 12nm node co-developed with UMC. Intel 4 appears nowhere on that list.

Ericsson's RAN Compute processors, announced in November 2023, were built on Intel 4, so Fortinet's part won't be the first third-party silicon to come off the node. That work grew out of a bespoke Intel-Ericsson collaboration, though, and Ericsson's formal foundry agreement with Intel, announced in July 2023, covered 18A. Fortinet is the first named customer buying Intel 4 as a foundry service, and the first cybersecurity vendor on any Intel node. The Ericsson engagement is also the closest thing in the public record to networking silicon on Intel 4, two years after the strategy Intel now says it outlined for the node.

Fab 34 economics

Intel 4 entered high-volume manufacturing at Fab 34 in Leixlip, Ireland, in September 2023, producing the compute tile for Meteor Lake-based Core Ultra chips, and shares the fab with Intel 3. Intel sold a 49% stake in the facility to Apollo-managed funds for $11.2 billion in June 2024, then bought it back in April 2026 for $14.2 billion, funded with $7.7 billion in cash and $6.5 billion in new debt. That buyback returned 100% of Fab 34's wafer economics to Intel at a premium of roughly 27%, and it only pays off if the fab's EUV capacity stays loaded.

Meteor Lake is aging out of Intel's lineup as 18A-based Panther Lake ramps through 2026, which leaves open the question of what fills Intel 4 capacity next. A multi-generation firewall ASIC program is a reasonable answer with mature yields, a customer that values supply stability over bleeding-edge density, and a part Intel described as tailored for cost-sensitive applications. Intel said in April that yields were improving across Intel 4, Intel 3, and 18A.

Fortinet's supply chain

Fortinet's 2025 annual report names Renesas and Toshiba America as the contract manufacturers for its ASICs, utilizing foundries in Taiwan and Japan operated either by TSMC or by the contract manufacturers themselves. The current SP5, a monolithic 7nm Arm-based SoC announced in February 2023, sits in that supply chain, so SP6 on Intel 4 moves Fortinet's next flagship security processor out of a TSMC-linked flow and into Intel's. The disaggregated design language in the announcement points to a chiplet-based part, a first for Fortinet's SP line.

Fortinet re-engineered three FortiGate models in 2022, the 70F, 600F, and 3700F, to accept alternative components during the chip shortage, and CMO John Maddison told SDxCentral at the time that the company wouldn't wait for parts to arrive in 2023. The "resilient and diversified" supply chain used in the SP6 press tracks back to that experience. Ken Xie called Fortinet "the #1 firewall leader with a 55% unit market share" in the company's 2025 results in February, with approximately six million FortiGates deployed, so there’s real, substantial volume here even if the parts are relatively inexpensive.

Intel Foundry reported $307 million in external revenue for 2025, up from $159 million the year before, against total foundry revenue of $17.8 billion and an operating loss of $10.3 billion. External revenue in Q1 2026 was $174 million. Fortinet's hardware business runs at roughly 30% of its revenue, and, per analysis from ServeTheHome, SP6 is ultimately a component of a portion of an annual hardware stream around $2 billion, so the deal won't move Intel's foundry line materially, even at full production.

CEO Lip-Bu Tan told CNBC in May that he expected commitments from multiple foundry customers in the second half of 2026, and Intel told investors in January that two prospective customers were evaluating 14A test chips. The SP6 announcement comes inside Tan's stated window, and it finally gives Intel something its foundry marketing has lacked in a named customer with shipping volume on a node with mature yields. Meanwhile, an 18A or 14A commitment from a major external customer is still missing, and Fortinet's cost-sensitive parts on a 2023 node don't substitute for one.

Intel and Fortinet have announced a strategic collaboration to develop the Fortinet Security Processor 6 (SP6), the next generation of the custom silicon behind Fortinet's FortiGate firewalls. Intel will contribute chip design, advanced packaging, and manufacturing to the SP6 program, making Fortinet the first cybersecurity vendor named as an Intel silicon customer.

Intel told Tom's Hardware that SP6 will be built on Intel 4, the EUV process the company has so far used only for its own products, making Fortinet both the first cybersecurity vendor named as an Intel silicon customer and the first named external customer for the node. However, the announcement specifies no production timeline, and it comes in the same Q3-Q4 2026 window in which CEO Lip-Bu Tan said the company expects commitments from multiple foundry customers.

SP6 will draw on what the companies described as Intel's expertise in disaggregated semiconductor design and advanced packaging tailored for both AI-enabled and cost-sensitive applications.

That points to a chiplet-based part, which would be a departure from the current SP5, a monolithic 7nm Arm-based SoC that Fortinet launched in 2023 for its entry-level and mid-range FortiGate appliances. The deal will help Fortinet "accelerate and strengthen our ASIC strategy," said Ken Xie, founder, chairman, and CEO of Fortinet, in the announcement.

Intel 4 was the company's first process node to use EUV lithography and entered high-volume manufacturing at Fab 34 in Ireland in September 2023, where it produces the compute tile for Meteor Lake-based Core Ultra chips. The node didn't appear among the processes Intel listed for external foundry customers in its fiscal year 2024 annual report, which named 18A, Intel 3, Intel 7, Intel 16, and a 12nm process co-developed with UMC. Intel said the SP6 work reflects plans it laid out for Intel 4 several years ago, including support for custom networking ASIC workloads.

Microsoft agreed in early 2024 to build an unnamed custom chip on Intel's 1.8nm-class 18A node, a deal that reportedly covers a next-generation Maia AI processor. That announcement followed a similar pattern, with no product details, node variant, or timeline at signing and specifics emerging over the following 18 months.

Intel CFO David Zinsner said in March that the company was fielding inbound interest in 18A-P from prospective foundry customers as yields improved, and Tan told CNBC in May that foundry commitments were expected in the second half of 2026.

Fortinet does bring real volume, though, if not marquee volume. IDC ranked Fortinet first in firewall appliances shipped as of early 2023, with a 48% unit share. The company ships its own ASICs across its entry-level and high-end FortiGate ranges, and SP6 extends a silicon program now in its sixth generation.

Neither company committed to work beyond SP6, though the release described the agreement as a starting point, with further collaboration on chip technology and manufacturing under discussion.

TSMC intends to raise base quotes on advanced chip production services by up to 10%, according to Nikkei, which cites people with knowledge of the matter. The price hike reflects increased demand for sophisticated processors by the AI sector, raising costs of tools and materials, as well as amplified investments in new production capacities.

For advanced process technologies — which TSMC considers 7nm-class and below — TSMC plans to raise baseline prices by 5% to 10%, depending on the particular production node and customer, the report claims. Furthermore, customers that need additional HPC chip capacity beyond their original volume requirements will reportedly have to pay another 10% to 15% premium on top of the standard increase, which means that some services will get a price hike of around 25%, if the report is accurate.

TSMC also intends to increase prices for mature manufacturing technologies, including its 12nm, 16nm, and 28nm-class nodes as well as other legacy fabrication technologies, the report claims. Increases could reach 10%, although certain nodes will reportedly see smaller adjustments, according to Nikkei.

Advanced technologies generated around 77% of the foundry's revenue in Q2 2026, whereas mature nodes accounted for 23%, which essentially means that TSMC is hiking prices on all of its services.

The company reportedly began discussing the new pricing with customers around June and completed negotiations in July. Rather than introducing higher rates immediately, TSMC opted to implement them from the beginning of 2027 to give clients like Apple, AMD, Nvidia, and MediaTek additional time to accommodate the changes and adjust their prices accordingly.

Since TSMC produces the lion's share of advanced processors for AI, HPC, networking, and smartphone applications, its price hikes will inevitably create a ripple effect in the industry and will make almost all electronics more expensive.

TSMC is not alone in raising prices these days. Vanguard International Semiconductor has also raised prices, while UMC began implementing increases in July. Also, memory makers have increased prices significantly, making TSMC management jealous. Intel also recently increased prices of its client and data center CPUs, citing market demand.

"I am really jealous about memory companies' 86% gross margin," said C.C. Wei, chief executive of TSMC, during the company's earnings call with financial analysts and investors. "86% [margin at memory makers] – 68% [margin at TSMC], I will be happy about that."

TSMC rarely comments on its prices to a large degree because they vary based on volumes and relationship with a particular client. Nonetheless, the head of the company stressed that the company has no intentions to increase prices suddenly or dramatically.

"So we do not suddenly increase our price by which I like to have 4x or 5x," Wei said. "You cannot survive for that kind of... for your customer to survive for that kind of price increase. So we earn our value, and we make sure that our profit, our gross margin, is enough for our long-term sustaining expansion, that is to the benefit of my customers and TSMC also, that is our philosophy."