Eight years after GlobalFoundries abandoned the development of its 7nm FinFET technology, the company is preparing to return to 7nm-class performance, this time by going via a different route. Its FDX Fusion process, built on FD-SOI (fully depleted silicon-on-insulator) technology, promises 7nm-class performance using advanced planar transistors, with no EUV lithography necessary.

In an interview with Tom's Hardware Premium, GlobalFoundries' Sudipto Bose, vice president of the FD-SOI business unit, shared new details about its FDX Fusion technology, including its 8nm-class logic density, advanced planar transistors, manufacturing costs, and plans to begin commercial production in 2028. The company also explained how it intends to compete with conventional FinFET technologies and why it believes FD-SOI has a future beyond the 22nm-class generation. Some elements of this interview transcript have been edited for flow and clarity.

Sudipto Bose: I have been at GlobalFoundries (GF) for a little bit over six years, and I have been in the industry for 25+ years. I spent the rest of my career at Texas Instruments (TI), so it's really two jobs that I have done: TI and GF. Half and half engineering and business. I spent a lot of my business days in the automotive segment. This was what I was doing at GF when I joined, and now I have the FDX product line role.

Sudipto Bose: A little bit on the history of FDX at GF. GF has been investing in FD-SOI for a long time. It started [these efforts] before I joined. So I would say almost eight years now. And a lot of the investment thesis that drove us towards FDX Fusion is based on the traction that we have in the market today, right? We have quite a few customers who are ramping up. And I say quite a few; this is like high double-digit customers in the nineties that are ramping up right now.

Applications for FDX Fusion

Anton Shilov: What specific types of chips and devices is FDX Fusion designed for? Which application will benefit most from its capabilities?

Sudipto Bose: FDX Fusion will try to enhance the applications in which we play today. What do I mean by that? If you look at our current customers, they are designing chips, everything to do with connectivity. When I say connectivity, think of Wi-Fi, Bluetooth, cellular, satcom, all of that. So that is one class of customers.

There's another class of customers who are designing processors at the edge, so these are MCUs (microcontroller units) with some level of inference sitting inside. Think of customers like Alif Semiconductors. So that is another class: MCUs at the edge.

Then in automotive, we have a disproportionate exposure to radar, and this is because of the eighty-one gigahertz performance that FDX brings to the table. So we will engage with them as they try to enhance their portfolio. We also have an automotive MCU, but radar is where you will see a lot of press releases that we have done.

Last but not least, we also have exposure in the data center segment. This also goes back to the fT/fmax, the high-performance RF that we have, which is a good candidate for designing TIAs and clock recovery circuits.

Anton Shilov: By applications inside data centers, what exactly do you mean? CPUs?

Sudipto Bose: Not CPUs. It is in the connectivity space. So, if you think about GF's focus, we are very focused on two things in data centers: power and connectivity. So in the connectivity space, we have silicon photonics, or turning electrons into photons. But then when you receive them, you have the optical diode, again, a GF silicon photonics technology. After that, you need circuits that will amplify those weak electrical signals and drive them to the compute chip. This circuit, which amplifies the weak electrical signals, is right now being done by GF silicon-germanium, but once FDX Fusion is there, we'll offer them both [as] options. And so, to be very specific to your answer, these are data/signal paths inside the data center that feed into CPUs.

7nm-class FD-SOI node

GlobalFoundries' FDX Fusion is a new manufacturing technology that promises 8nm-class logic density and 7nm-class power and performance without EUV lithography or FinFET transistors, which greatly reduces design costs and manufacturing costs at the cost of significantly lower transistor density compared to 7nm-class nodes.

Instead, the process relies on advanced planar fully depleted silicon-on-insulator (FD-SOI) transistors, strained silicon substrates, and aggressive optical patterning techniques to achieve transistor dimensions comparable to those of conventional 8nm-class FinFET nodes.

FDX Fusion also retains support for adaptive body biasing and combines high-density digital logic with RF, analog, and embedded memory capabilities. The technology will be manufactured using deep ultraviolet (DUV) lithography, although its tighter gate and metal pitches will likely require extensive multipatterning for the most critical layers.

Anton Shilov: What are the key innovations of FDX Fusion compared to predecessors and other nodes that are currently used?

Sudipto Bose: The key things that we're improving from the current-generation FDX, the first one is fT/fmax, this is 500 GHz, or 0.5 THz fT/fmax. This helps the first segment that I talked about, which is connectivity. This helps automotive radar, and this definitely helps the data center segment as they try to improve data speeds. So this is not really competing with silicon germanium. Think of it as silicon germanium at the very high end, and FDX in the 100 – 200 Gb per lambda space. That is one. The second one is the inference at the edge. So we can call it physical AI, and we look at physical AI as sense, think, act, and connect. But the kind of feature set we are putting in starts with improving the digital gate density. This is 2.2 times more dense than the current generation FDX (22FDX and 22FDX+).

Sudipto Bose: We are putting in a lot of flavors of eNVM, a lot of flavors of SRAM, because in edge AI, and in fact for any AI, the real game is how much memory you can pack without increasing the cost. So we are adding a lot of flavors of those. The way we architected FDX Fusion is that we set a goal of how much performance we can deliver to our customer base without increasing their operating expenses.

If you look at classic 7nm, 6nm, they require EUV tools. The mask set is costly; the tool chain is costly. The FDX Fusion platform that we've built isn't going to use EUV tools. It is also based on planar technology. So there are two advantages to this. One is that we can support a much more competitive mask set price compared to 6nm. We can also offer [customers] a lot more flexibility in terms of cycle time and in how many places we manufacture, because FDX Fusion does not need EUV tools.

So, to summarize the answer? We are trying to improve RF and analog performance, digital gate density, and the classes of memory that we offer. What applications are we trying to target? It is connectivity, edge AI, high-frequency mmWave, automotive radar, and definitely applications inside data centers.

Anton Shilov: You just mentioned transistor density. The press release says that it has more than twice the transistor density of the original 22FDX process, but you never actually published a transistor density number for this. Could you share any numbers?

Sudipto Bose: I will share a number with you. But I will also give you a little bit of context on how our customers look at our technology portfolio. If you look at the current generation, the one that we are manufacturing today, the one where I said we have 90+ customers ramping. Not designing, ramping. This basically comes from the flexibility of FD-SOI. You have the box, the depleted channel, and you can use body bias. So we have customers who are able to achieve 16nm-class power and performance with 22FDX. What do I mean by 16nm-class power and performance?

It essentially means that although our gate density is not as close to 16mm, when you look at the system-level requirements like CPU clock, but think of it as TOPS per watt, we are matching 16nm; in some cases, we are matching 12nm-class.

[...] If I were sitting in a time machine and went back seven years, instead of calling it 22FDX, we could have called it 16FDX, right? Or we could have called it 16nm-class FDX. So with that analogy, if you come to FDX Fusion, our gate density of FDX Fusion will be exactly the same as the industry's 8nm standard today.

It is 14 million gates per square millimeter; that is the density.

Note: Assuming he uses a two-input NAND gate as its reference, each gate contains four transistors, which translates to 56 MTr/mm², which is comparable to what Samsung's 8nm-class nodes use.

Sudipto Bose: Now, why do we call it 7nm-class? Or we actually thought of calling it 6nm-class, but then we said, let's wait for some silicon before we go too far ahead. It is because digital gate density is one aspect of a solution. It defines your physical size, the die size, and that is great. But then you need power and performance. And with the adaptive body bias (ABB) capability that FD-SOI has, and with the standard cell metallization innovations that we have brought in FDX Fusion, once a device is done and you again look at TOPS per watt, it should be equivalent, if not better, than what 7nm can achieve. That is our product target. So for a customer, the value it brings [customers] is: 'I do not have to use an EUV tool line. I do not have to use a mask set that costs many millions of dollars.'

I have something which costs a few millions of dollars, has great cycle time, but at the same time, I am getting TOPS per watt, which is similar to or better than 7nm. The die size might be bigger, but again, it should not be no bigger than what 8nm is today. And that is the messaging to the industry; that is why we say 7nm-class instead of saying, 'Hey, this is 7nm density.' We are trying to reflect what our customers have told us. That in the edge world, in the physical AI world, the size of the die is one aspect, but if the die does not meet the power requirement of the application, then the whole system will not function. So that is the push.

Anton Shilov: That is perhaps why you actually called the technology FDX Fusion instead of using some fancy number.

Sudipto Bose: Yes, because the moment we put a number [out], people put us in a box. And we want to give customers the optionality of, 'Listen, you want to design a transimpedance amplifier using the fT/fmax that we have? That's an analog circuit. No one cares about digital gate density. Go build it.'

'You want to build a simple MCU, which is just SRAM and IOs? We have 14 million gates per square millimeter. Go build it.' 'You want to build a mixed-signal design like a single-chip radar, Wi-Fi, a satcom digital beamformer? Here are the few other knobs that you can turn to get the best PPA or the best system performance that you need.'

That is why we chose the name Fusion; we are trying to imply [that] we give you many options. It is the combination of all the good things the world needs to design the physical AI dream that we have put in front of ourselves, like the whole stack concept of 'sense, think, act, and connect'. Let us see if it sticks. I think it is a bold move for us to go against the grain of the way the foundry industry typically names its platforms, but we feel pretty strong about it.

Anton Shilov: So, you shared the gate density number, but could you maybe also share things like contacted gate pitch, metal pitch as well?

Sudipto Bose: In time. The reason I mention that is there is a little bit of IP involved. We want to get the first silicon out, engage with a few customers before we publish the CPP and the M(etal) layers. […] We are pushing the limits of patterning and coloring as well as gate oxide engineering to get the best CPP and metal pitches, which will enable this level of density of gates. That is, I would say in terms of R&D dollars just at a very high level, 50% of R&D dollars is on the transistor itself because we are doing strained substrates. There are multiple techniques we are using to improve the PFET and NFET performance. The other 50% is all on CPP and metal pitches.

Anton Shilov: So, are those contacted gate pitches and metal pitches comparable to conventional 7nm class FinFET process technologies?

Sudipto Bose: Comparable to 8nm.

Anton Shilov: When we talk about 8nm, basically speaking, there is only one company that actually produces chips using an 8nm-class technology. That is Samsung Foundry. TSMC and Intel Foundry do not have 8nm-class technologies. So I suppose that we should compare it to Samsung's 8nm node, right?

Sudipto Bose: That's a fair guess.

Anton Shilov: When it comes to power consumption improvements versus 22FDX and 22FDX+, how much lower power can we get using the new FDX Fusion node?

Sudipto Bose: It depends on the application, but I understand your question. So if you just normalize with [iso performance and iso power], I am giving you an answer with adaptive body bias included. If you consider current-generation FDX as the base point, the goal of FDX Fusion is to get 30% higher performance and 40% lower power. Again, it is really application-driven [in] how low you can go. But if you take the standard core, our goal is to get at least a 20% improvement.

Anton Shilov: What types of chips do you expect to benefit most from the FDX Fusion technology? You mentioned connectivity, edge AI, high RF, automotive radar, and connectivity applications inside data centers. What about application-specific AI accelerators, because you mentioned edge inference?

Sudipto Bose: From the STAC — sense, think, act, and connect — framework point of view, let me give you an example. Think of a humanoid, or a car — major applications that need to see. It needs to see and then infer what the environment is like. So the class of chips that do this vision processing at the edge to infer the surroundings will definitely be supported with FDX Fusion. The class of chips that will hear, do voice recognition, and, from voice recognition, draw conclusions, we definitely want to support [them]. Now, at the data center right now, as I said, our play is connectivity. Just translating optical to electrical signals.

If a customer wants to use a chiplet, which has a lot of memory, think of analog in-memory compute along with an inference engine, by all means we will support [such applications]. We will work with customers to see how we can play in that compute ecosystem in the data center. But in terms of pure focus, the first 10 customers that we are engaged with are either at the edge, or they are in the connectivity piece inside the data center.

Note: For those of our readers who are not familiar with ABB, this is a technique that dynamically adjusts a transistor's threshold voltage by changing the voltage applied to the transistor body. Forward body bias reduces threshold voltage to improve performance, while reverse body bias increases it to reduce power leakage. This enables chips to optimize performance and power consumption according to workload requirements. ABB is one of the key advantages of the FD-SOI technology.

Anton Shilov: Since you mentioned this, does FDX Fusion retain the active body biasing capabilities of its predecessors?

Sudipto Bose: It is an inseparable part of the platform, yes. We will launch this platform in a way that customers can use it.

New tools required

Anton Shilov: You also mentioned makers of wafer fab equipment. Will FDX Fusion use existing manufacturing equipment at the Dresden facility, or will it require substantial investments in new lithography, deposition, etching, and metrology tools?

Sudipto Bose: It will require new tools. Substantial is a relative term. If you see the amount of money being invested in semiconductors, the term 'substantial' has changed. We are going to get new tools, which is why we combined the FDX Fusion announcement event with the topping off of the Sprint expansion project. That's why we had all the luminaries from the German and the European government. There will be tool investment; we will be buying tools from the vendors. How much of it is going to be litho versus etching? Time will tell, but for sure we need new tools compared to what we have today.

Anton Shilov: But will you essentially need to completely re-equip the Dresden facility to use FDX Fusion? What percentage of the tools you have can be reused for FDX Fusion?

Sudipto Bose: We can get back to you on that exact answer because I do want to give you a proper answer, rather than a high-level answer. But I will tell you where the targets are. With the front end, the transistor fabrication tool chain, my target is to reuse as much as we can.

Anton Shilov: You also mentioned that you plan to begin manufacturing FDX Fusion in 2028. But does this refer to risk production, initial customer production, or high volume manufacturing?

Sudipto Bose: Initial customer production.

Anton Shilov: When do you expect the technology to reach mature yields and meaningful production volumes?

Sudipto Bose: I will give you my target, and then the industry will define it because we are a part of a bigger ecosystem. 2030 is when we want to get to high-volume manufacturing with FDX Fusion. But again, it depends on the first applications and the first few customers.

Readiness

Anton Shilov: Speaking of customers, you probably already have customers who are committed to production, haven't you?

Sudipto Bose: We have customers who are committed to building a chip. Of course, we have to deliver to their specs before they go to production.

Anton Shilov: I suppose the customers that you mentioned in the press release like BMW, Bosch NXP, Siemens, and Tesla, they are all plan to build chips on this technology.

Sudipto Bose: […] They have been pushing us for the last few years to do something like this, and they have given us requirements. Now we are doing it, and we have to show them what we can [deliver]. So there is a lot of push that we have received from the industry, from these companies. When I say these companies, the supply chain that leads into these companies to deliver something which will work at the edge. So we are racing against time to show them something that will meet the specs.

Anton Shilov: GlobalFoundries plans to release the initial FDX Fusion PDK in mid-2027. But when do you expect complete digital, analog, and RF design flows to become available from the three major EDA vendors?

Sudipto Bose: Yeah. I wish I could tell you… Right now we are in discussion with all the major primes, so we are in the request for information/request for quotation (RFI/RFQ) phase, but we have started discussions with the major EDA vendors. It has been almost six to nine months now.

Anton Shilov: But you do expect all the leading EDA vendors to support FDX Fusion in eight to nine months?

Sudipto Bose: Of course. We are going to engage with the whole ecosystem that we have, and once [the PDK is out], we have to support a proper flow not just for chip design, but also IPs that are required and everything else around it.

Anton Shilov: So how extensive will the initial FDX Fusion IP ecosystem be? Will customers have access to silicon-proven standard cell libraries, SRAM compilers, embedded non-volatile memory, interface IPs, maybe analog and radio frequency building blocks before 2028?

Sudipto Bose: Yes. In the first two years, we are going to engage with pilot customers. Think of these as early adopters. We have early adopters listed, and we will design standard cell, I/Os, and SRAM [...] needed for everything, so we will have those. But then the complex IPs, like PCIe Gen 4/5 or LPDDR6 or a DisplayPort, will be dictated by the first few applications that will ramp. FDX Fusion for us is the beginning of a journey. We have been on the journey of 22FDX for almost eight years. I envision FDX Fusion to be more than that. Even on our current platforms, we keep enhancing our IP portfolio. So I expect us to be adding IPs to FDX Fusion over the next ten years.

ARC, MIPS, and Fusion FDX

Anton Shilov: GlobalFoundries also highlighted its ARC and MIPS processor IP portfolios and RISC-V expertise as part of the FDX Fusion offering. Do you plan to develop processor cores and AI accelerators specifically optimized for FDX Fusion? IPs specifically optimized for FDX Fusion? Or will you primarily port existing IP to the new process?

Sudipto Bose: MIPS is an internal customer and a partner, and we will engage with them, and they will launch a platform for physical AI that is fine-tuned, in a combination of what they have and what FDX Fusion has. ARC and MIPS are key pieces of the strategy. Having an internal customer like that just enhances our development cycle by 5X because now they can start developing fast turns of test chips and give us feedback. We did not have this capability in the past. Now we do. Once they are ready, they will start announcing stuff.

Anton Shilov: So essentially, you will both port the existing IPs to the new node, but also MIPS will likely develop something brand new specifically for FDX Fusion.

Sudipto Bose: Yes.

Costs

Anton Shilov: How will the manufacturing complexity and cost per transistor of FDX Fusion compare to 22FDX+, your 12nm FinFET technology, and conventional 8nm FinFET technology?

Sudipto Bose: This would be the most advanced planar transistor that the world has seen, the most advanced non-EUV-based manufacturing line that the world has seen. So, I would say significantly more complex than our current 22nm-class FD-SOI line. More complex than what we have on the 12nm FinFET line. We are working with every tool vendor that you can think of as part of this program, and we have given them the challenges. It goes back to your question about our contacted gate pitch and metal pitch. So, we have had multiple workshops with them over the last few quarters, and each one of them is proposing a tool recipe that they think will get this to a nice and solid yield.

Sudipto Bose: So, I guess the answer to your question is: firstly, it is definitely complex, and secondly, we are really using the entire ecosystem available to us to come up with tool configurations that will deliver this. All of this is going to happen in Dresden. We have to be competitive, so price is always dictated by the market. Our goal is to have a running cost that is significantly better than a 7nm or a 6nm class of design (due to planar transistors and due to lack of EUV masks). After that, we will work with our customers to figure out what makes sense. But you are right, the value that we want to bring in is, 'dear customers, you do not have the same operating expenses load, meaning the cost of tape-out is less than 6nm.'

And you can do multiple tape-outs because this class of devices is not something where you can design one part and use it for 15 applications. You really need 15 devices for 15 applications. So, we definitely enable that. Then, when it comes to manufacturing cost, it is a discussion with our customers. We have various business models, but the goal is to make sure it is a win-win. At the end of the day, the lower the cost we are, the more flexibility we can provide to our customers. The non-EUV path is one of the things that was dictated by our decision that we must keep this a cost-competitive platform.

Anton Shilov: So, cost-wise you want to be competitive, but it's likely comparable to 8nm.

Sudipto Bose: I will have a better feel once we are complete with what we call our M-cycles inside the fab. But I would say my internal target is that we have to be better than that.

The future of FDX

Anton Shilov: GlobalFoundries describes upcoming technology as its 1st Generation of FDX Fusion. Does this mean that you envision subsequent generations with high transistor density and performance? Maybe you can share some preliminary targets or timelines for the next node?

Sudipto Bose: We have listed quite a few innovation steps that we want to enable on this platform. The FDX Fusion definition is based on the ones we believe we are more confident that we will be able to deliver in the timeframe that we have said. We have kept a few things in the innovation lab, and they are pushing the boundaries of a few things like eNVM, EDA routing, chip folding, 2.5D integration, which, once they mature, will define what the next version of FDX Fusion will look like. I do not have a timeline for the next version of FDX Fusion, though.

As we proceed through the development phase, I would say early 2028 to mid-2028 is when I expect to have a better view of when the next version will be launched. And this is also based on feedback we will get from customers. Because what we have right now is our first silicon, which is running in the lab, which we will show to customers. They will give us a lot of feedback. I am sure we will get a few things right, and at the same time, we will get a few things not so right. And that feedback, along with a few of the innovation topics I mentioned, will dictate what the next generation is going to look like. Stay tuned!

Anton Shilov: One of the reasons why I aksed about next-generation nodes is partly because TSMC typically shares its process technology roadmaps with new nodes well before it releases early PDKs for these nodes. Given that FDX Fusion is now GF's most advanced logic process, with capabilities comparable to 8nm-class technologies (i.e., more advanced than 22FDX or bulk 12nm FinFET), how frequently does GlobalFoundries plan to introduce new process technologies, and how far in advance will it disclose its roadmap?

Sudipto Bose: I would say, we are doing advanced development across the board. If you look at the work we are doing on silicon photonics, on packaging, on power transistors like GaN, RF GaN, Power GaN, these are all pretty advanced. But yes, you are right: in what the world understands as a classic, let's say, high-density process, FDX Fusion is the most advanced. We typically announce or update the industry about our roadmap every year at the GlobalFoundries Technology Symposium. Like this year at GTS, we announced FDX Fusion. So, I would say stay tuned for the GTS sessions that we have, and typically every year we do it in September or October.

CEA-Leti involvement

Anton Shilov: CEA-Leti describes FDX Fusion as a single-digit FD-SOI node. How closely is this new technology related to CEA-Leti's own research in 10nm and 7nm with their SOI nodes?

Sudipto Bose: The platform that we have right now is the outside of the substrate engineering work that we are doing with Soitec and CEA-Leti; the rest of it is GF inherent IP at this point in time. So we are bringing in the knowledge that we have from current-generation FDX, the knowledge that we have from the work that we did in 7nm before we stopped it, the work that we have done on 12nm. So it is bringing in all the innovations across all the GF fabs to figure out what is the best that we can offer. Does it mean that we will not look at what CEA-Leti has in the future? I do not have an answer right now. But for now, FDX Fusion is a very GF innovation-driven effort.

Anton Shilov: So you did not use pre-competitive IP from CEA-Leti to develop FDX Fusion? Is it a completely internally developed node?

Sudipto Bose: Correct.

Anton Shilov: The press release mentions innovations in substrate engineering along with endorsements from CEA-Leti and Soitec. What exactly does that involve, and how does it improve transistor performance? What role do Soitec and CEA-Leti play in developing FDX's strained silicon substrates, and how close is this technology to mass production?

Sudipto Bose: GlobalFoundries is working with CEA-Leti and Soitec under the FAMES program to develop strained silicon substrates for FDX Fusion. The goal is to improve charge carrier mobility and, consequently, transistor performance. Since FD-SOI technology relies on specialized silicon-on-insulator wafers supplied by Soitec, the three organizations are developing ways to introduce strain into these substrates and make the technology suitable for high-volume manufacturing. The approach has already demonstrated its viability in the laboratory, and the partners are now refining the manufacturing process to prepare it for commercial production.

[Session ends]

A Pat Gelsinger-backed Georgia Tech spinout, Nagare Labs, says its Z2RAM can put SRAM-speed memory, at DRAM density, directly on top of AI chips. The founders’ own papers show a fast-improving cell that, tested up to 85 degrees Celsius, holds data for over 300 seconds. Gen 1 is projected to have 5x SRAM density with six stacked layers, 14x DRAM speed, and 3x less read energy than SRAM.

AI chips require a lot of bandwidth, and it has been challenging to get sufficient yields of high-bandwidth memory (HBM) to feed them. Even when manufacturers can get it, some reportedly plan to settle for fewer layers for yield reasons, and heat is another. Heat is also why Samsung’s zHBM, which stacks DRAM directly on the processor, is planned at only about four layers.

Alternatives include high-bandwidth flash, still in development, which stacks NAND like HBM and would sit beside the GPU, or SRAM stacked directly on the die, which is less dense and more expensive for the capacity, but also faster. DRAM, which is more capacious, can sit on top of the compute, but heat limits how hard the logic underneath can run.

That limit is already shaping chipmakers’ design path for stacked memory. Micron’s vHBM plans, for example, include heat-spreading structures. With HBM stacked on a logic die, and DRAM needing to be kept at or below 95 degrees Celsius, the logic’s heat output is capped at 220 W/cm², or 300 W/cm² with better thermal vias, according to a 2025 simulation by co-founder Shimeng Yu’s group. Nagare Labs says peak compute has grown 70% a year over the past three decades, against 20% for memory bandwidth.

The company describes its Z2RAM as “Two transistors and a shield. No capacitor,” where a write transistor places a charge on a storage node and the shield blocks noisy neighbors. The read transistor can sense without draining. In a gain cell like this, the read transistor’s gate capacitance holds the charge, so reads are non-destructive and the cell avoids DRAM’s write-back. Nagare aims for well under a picojoule per bit.

Nagare builds Z2RAM by depositing its layers on top of the accelerator and patterning them “together on one die,” much as 3D NAND flash scales by adding layers. There’s no interposer and no bonds between the memory layers, which is part of the secret sauce. One lithography exposure covers several layers at once, and standard 300 mm tools with DUV do the job, with no EUV required. The current roadmap is aiming at over 100 layers with “hundreds of thousands” of vertical connections.

Retaining data at higher temperatures is the challenge, and one the founders have probed repeatedly with their testing. A 2020 paper from co-founder Suman Datta’s group, on a tungsten-doped indium oxide two-transistor cell, had retention of 1 second at 25 degrees Celsius and just 300 milliseconds at 85°C. An update in 2025, which has Datta as a co-author, adds a third transistor and removes the gate overlap from its transistors, managing over 1,000 seconds at 25°C, up from 200 seconds with overlapped ones. It also simulated a GPU L2 at twice SRAM’s capacity but in the same area with 75–80% lower energy-delay-area product, a combined score that multiplies energy, delay and area.

Six months later, both founders showed a “folded asymmetric boosted” three-transistor cell that held data for over 300 seconds at 85°C, as compared to only 100 milliseconds for a conventional three-transistor design. That’s still below the roughly 95°C that Nagare says DRAM must stay under, so neither the founders’ published cells nor Z2RAM have shown retention above that line yet. The boosted cell is also “refresh-free,” which means data in the GPU’s last-level cache, profiled from AI workloads, doesn’t have time to decay before it is overwritten.

Physical space is also limited for this application, and the founders project their boosted cell at 0.0168 µm² at 7nm, compared with 0.0199 µm² for a high-density SRAM cell on TSMC’s 3nm (N3) process. A separate study from Yu’s group found that a four-tier, 256MB cache of two-transistor gain cells at 7nm could reach 5.7x the bit density of 7nm SRAM in the same area, in simulation. However, the return on investment falls off past seven or eight tiers because masks scale with layers. Nagare Labs’ claim of single lithography would potentially bypass this limitation.

That has not yet been proven, and nothing published yet shows it. “Where we are is literally lab prototypes,” Datta told The Register, adding that sampling of Z2RAM tiles is targeted within four years and production shipments, if they arrive, within the next decade. Yu told the outlet that no standard yet exists for integrating this kind of memory with an accelerator, which means Nagare might have to come up with the interface itself. Datta also mentioned reliability to the outlet, as single-electron effects can shift a cell’s threshold enough to upset the stored bit. It also remains to be seen if the tested three-transistor cells work sufficiently well as a two-transistor, single-shield product.

Even if Nagare clears those hurdles, a more important one lingers: It currently has no fab. The plan to scale depends on getting partners for fabrication as well as packaging. Nagare is reportedly looking for an R&D fab partner so it can scale beyond the university clean room. Perhaps the most similar type of memory-on-compute shipping today, and the one Datta cited to the outlet as a model for working with chipmakers, is AMD’s 3D V-Cache.

Z2RAM isn’t the first capacitorless memory to promise a 5x improvement over SRAM in density; it follows in the footsteps of Innovative Silicon’s Z-RAM from 20 years ago, a technology AMD licensed, though it was not pursued. A Georgia Tech paper due at IEDM in December covers a different device, a one-transistor, one-ferroelectric-transistor cell, aimed at the same gap between SRAM latency and DRAM density.

Gelsinger, previously CEO of Intel, which started as a memory company, phased out Optane, a low-latency non-volatile memory, in favor of CXL. Optane sought to bridge the gap between slower non-volatile storage, such as HDDs and standard SSDs, and DRAM. Now he sits on Nagare’s board, and Playground Global, where he is a general partner, led the startup’s $5 million round as Nagare searches for a solution to a different but related problem.

Nagare declined to share measured retention, latency, or energy figures. The founders’ boosted cell already holds data at 85°C longer than a cache needs, but until a fab-built, multi-layer Z2RAM stack is measured, retention above 95°C included, its headline numbers remain projections.

India wants to develop its own graphics processing unit (GPU) within the next two years as the country steps up efforts to build a domestic semiconductor industry and reduce its dependence on foreign chip suppliers, reports ETGovernment. The target was outlined by S.Krishnan, secretary of India's Ministry of Electronics and Information Technology (MeitY), in a November 4 interview. "Under India Semiconductor Mission 2.0, we intend to target the development of an indigenous GPU chip. We should have a GPU chip of our own. This will not happen overnight. It is a project that will require approximately 24 months, and we intend to work towards that objective," Krishnan said.

The proposed GPU is part of a wider plan to establish an Indian hardware and software ecosystem, with Krishnan describing five layers needed to support AI development. These include: energy, accelerator chips, computing infrastructure and servers, AI models and applications. Indian companies such as VVDN, Kaynes and Avalon are already manufacturing servers, while the Centre for Development of Advanced Computing (C-DAC) has developed its Rudra server range, whose systems are designed to support AI workloads, after which the government transfers the technology to local manufacturers. Krishnan also sees AI as a potential repeat of the opportunity India's IT industry experienced during the Y2K (the year 2000 bug) transition. "AI could create a similar opportunity, although the nature of the work will be different," he said.

The comparison is big for a country whose IT-enabled service sector employs about 6 million people. A NITI Aayog paper estimates that roughly two million existing jobs could become redundant as AI adoption changes the industry, but around 4 million more jobs could emerge. Krishnan argues that Indian companies could benefit from helping businesses worldwide integrate into their AI operations, just as they benefited from the demand for software services around the turn of the century.

The country has already attracted major interest with ASML, partnering with Tata Electronics to equip India's first commercial semiconductor fabrication facility in Dholera, Gujarat. The planned facility is expected to use 300mm wafers and eventually reach a capacity of 50,000 wafers per month. Intel also announced a strategic partnership with Tata Group covering semiconductor manufacturing and packaging for the Indian market. However, the proposed GPU remains an early-stage target. Krishnan did not identify a manufacturer, chip supplier, or builder for the project. India is also looking to bring its own homegrown SHAKTI and VEGA processors to commercial markets. Both are based on the open-source RISC-V architecture, allowing local developers to build processors without relying on proprietary CPU designs. Notably, these are CPU designs, separate from the GPUs now being targeted by MeitY.

That said, it is not the first time India has attempted to build its own GPU production unit. In 2019, India's IT Madras released a software development kit that allowed developers to begin building applications before the processors were commercialized. The project included several processor classes aimed at different markets, from embedded devices and micro-controllers to workstations and server workloads. The effort has continued since then, with the Aries 3.0 development board, which uses the C-DAC’s VEGA ET301 processor, being introduced in 2024. The 32-bit chip runs up to 100MHz and includes 26KB of SRAM and is intended for relatively simple applications such as sensors, wearables, and Internet of Things devices, rather than desktop PCs or graphics-intensive workloads.

However, there are signs that the SHAKTI and VEGA platforms are nodding beyond development boards and into practical applications. At the September 26 SEMICOM India event, the government highlighted projects using the processors, including an autonomous water-cleaning robot around SHAKTI and a digital telescope using VEGA. Another VEGA-based project was designed to monitor forest environments. The government's Design -linked Incentive (DLI) program is already supporting more of that work. MeiyT says 24 companies received assistance under the scheme, and subsequently raised venture capital or other private investment. Their projects include microcontrollers, drone flight controllers, smart meter chips and CCTV cameras.

India's semiconductor market is currently valued at just about $50billion and is expected to approach 100 billion by 2030, according to a report by the India Electronics and Semiconductor Association (IESA). The government wants local companies to capture more of that growth domestically rather than remain dependent on imported components.

Micron has paused construction on its Fab 11E site at Taoyuan as the company and its Taoyuan labor union have failed to reach an agreement regarding clearer profit-sharing terms. Bloomberg reports that activity on the site has all but halted, except for minor safety work, with some sources saying that executives are concerned about uncertainties regarding negotiations with its workers. The company hasn’t released a statement about the move but has already informed local officials about the suspension.

“Taiwan plays an important role in Micron’s global footprint, and our operations today continue as normal,” Micron said. “We are confident in maintaining business continuity for our customers.” The company has recently announced a bonus that could give as much as five times the annual salary of some eligible workers, and has also wrapped up a deal with the bigger Taichung union, although some members say they were dissatisfied with the outcome. On the other hand, the Taoyuan union is still holding out for better terms, with the two parties set to meet again on November 6. It even launched a one-day strike last month to show the chipmaker its resolve and how its operations could be disrupted if it does not meet their demands.

Workers from the big three memory chip manufacturers — Micron, Samsung, and SK hynix — have been protesting recently and demanding a bigger slice of the massive profits that these companies are currently making from the AI memory chip boom. SK hynix has recently agreed to pay staff $50,00 apiece, with each employee set to receive $477,000 in bonuses this year and up to $900,000 next year. Samsung Foundry workers also fought for a $340,000 average bonus, which received approval at the last minute and averted a massive strike that would have disrupted the company’s operations. Employees from these South Korean companies expect to nab performance bonuses of up to $400,000 and are rejecting coveted overseas training programs in favor of cold, hard cash.

While the company hasn’t made a statement regarding the suspension of work on its Taoyuan site, it’s hard to believe that the move happening so close to its next meeting with the Taoyuan union is a coincidence. It should be noted that Micron is also developing other sites across the world, with plans for an HBM fab in Japan, a $24-billion development on the way in Singapore, plus facilities across the U.S. Nevertheless, the company says it is looking forward to reaching an agreement with the workers, with the Taiwan government hoping for a win-win outcome for both parties.

An explosion and fire at a PCB factory situated in Taiwan’s Silicon Valley have left two people dead and five injured, reports Reuters. The tragic incident took place at a Panasonic Industrial Devices Materials-owned facility on Wednesday. Panasonic is investigating the details and the cause of the accident. Initial reports suggested that five were injured in the post-explosion fires in the Hsinchu factory. However, an update today confirmed that two missing people had been found dead.

Local media have more details about this sizable accident. Focus Taiwan reveals that the fire broke out at 2 am local time on Wednesday. The five-story building where PCBs are produced had 20+ staff on the production lines at the time of the accident.

Five injured men were conscious and taken to hospital shortly after the incident occurred. However, as mentioned above, two were missing. 12 vehicles and 23 firefighters were dispatched to dig through factory debris using heavy machinery. Only then were the two missing employees found dead.

Panasonic’s explosion and fire-damaged facility “conducts research and development and manufactures printed circuit boards and semiconductor packaging materials,” notes Focus Taiwan. It had passed a safety inspection as recently as August. The news follows a Deadly Intel Fab 28 explosion in Israel, which killed two people last month.

Initial reports pointed to the use of flammable chemical solvents, including methanol and methyl ethyl ketone (MEK), in the plant as a probable accident vector. However, the precise cause of Wednesday’s incident is still being investigated.

While our thoughts are with the dead and injured, and their families, some will be wondering about the potential implications for the AI industry-induced PCB shortage that recently hit the headlines. We aren’t sure about how important this particular factory is to the wider electronics components supply chain. Moreover, no reports discuss how long the facility may be out of action in the wake of this tragic accident.

Marvell Technology Inc. has signed a definitive merger agreement to acquire Lumentum for an enterprise value of $115 billion, combining two of the biggest players in the data center optics market into one company. According to a joint press release on November 2nd, Lumentum shareholders will receive 4.5 Marvell shares for each share they own, which the companies put at about $1,132 per share. This figure represents a 23.9% premium over the company's unaffected closing price on October 28, the last trading day before reports of the deal affected prices.

The agreement — which leaves Marvell's current shareholders with about 67% of the combined company and Lumentum's with about 33% — is reportedly the second-largest tech transaction deal ever after the SpaceX-xAI merger, according to Bloomberg. Both boards have approved the deal unanimously, and it is expected to close in the first half of 2028, pending regulatory and shareholder approval.

The acquisition represents another significant expansion of Marvell's optical infrastructure portfolio, following its $10 billion acquisition of Inphi in 2021 and its $3.5 billion upfront purchase of optical interconnect startup Celestial AI, completed in February 2026. All three mergers and acquisitions involved companies handling different parts of one of the most critical AI infrastructures: optical connectivity.

As AI infrastructure continues to scale, optical connectivity is becoming increasingly important for moving vast amounts of data between processors, racks, data centers, and even on the accelerator board itself. With the acquisition of Lumentum, Marvell, which already supplies optical DSPs, silicon photonics, and high-speed SerDes, is positioning itself as one of the industry's major suppliers of optical interconnect technologies, spanning scale-across and scale-out networking to emerging scale-up and scale-in connections.

Why AI infrastructure is moving towards optical connectivity

Modern AI data centers house thousands of interconnected accelerators exchanging enormous volumes of data. As data volume, speed, and travel distance scale, copper interconnects, the conventional medium for inter-rack connections, hit physical limits, becoming impractical at around one to two meters. The industry's solution has been a transition to optics, moving data as light instead of electrical signals.

First, optical transceivers and fiber optics replaced copper for inter-rack connections and beyond. Pluggable transceivers containing a laser chip, digital signal processor (DSP) chips, and several optical components convert the accelerator's electrical signals into light for transmission over fiber, then convert them back into electrical signals at the receiving end.

The industry is also looking to bring optics into the accelerator package itself with co-packaged optics and near-packaged optics. In conventional packages, signals from the logic chip have to travel inches along copper traces across the board to reach the transceiver. Co-packaged optics takes the optical engine out of the pluggable module and places it as a photonic integrated circuit (PIC) chip directly on the switch or accelerator package, shrinking the electrical path.

These shifts to optics have made optical interconnects one of the most critical AI infrastructure markets, driving several multi-billion-dollar deals and major partnerships among industry players across the different technologies and processes involved.

From silicon to lasers: What Marvell and Lumentum bring to the table

The optical interconnects market encompasses several critical technologies. On the electronics side, semiconductor chips such as high-speed serializer / deserializers (SerDes) and optical DSPs prepare and process electrical data signals. Electronics also include analog components such as drivers and transimpedance amplifiers (TIAs) that interface with the optical hardware. Photonic integrated circuits (PICs) use microscopic optical components such as waveguides, modulators, and photodetectors to manipulate light, encode information onto it, and convert received light back into electrical signals, combining all of this into a single chip.

Whether an optical engine sits inside a pluggable transceiver or directly on the board, it still needs a laser, either integrated into the assembly or supplied externally, which brings us to another specialized branch of semiconductor manufacturing: laser technology. Lastly, fiber optic cables and associated passive optical components transmit and distribute light while optical circuit switches redirect optical connections through a network.

Marvell already covers most of the electrical and electronics side, with a portfolio that includes custom AI accelerators, Ethernet switches, high-speed SerDes interfaces, DSPs, optical drivers, TIAs, and silicon photonics. Lumentum, on the other hand, supplies many optical components, including high-performance lasers, modulators, photodetectors, optical transceivers, and optical circuit switches. Combining these portfolios and processes allows Marvell to develop more complete solutions, designing and optimizing electrical and optical components as part of the same system.

Perhaps the most strategically important part of Lumentum's business is its expertise in compound semiconductors, particularly indium phosphide (InP), which is critical for laser and other optical chips. Unlike conventional silicon, which has an indirect bandgap and is inefficient at generating light, InP-based semiconductor structures can efficiently emit and detect light, making the material well suited for manufacturing high-performance lasers and other optical components used in high-speed communication systems.

Lumentum is also bringing its manufacturing experience to the merger. Unlike Marvell's predominantly fabless semiconductor business, Lumentum directly controls its front-end semiconductor fabrication processes, owning and operating specialized InP fabrication facilities, which its CEO Michael Hurlston described as the world's largest InP manufacturing footprint during the acquisition announcement. If the deal closes in 2028, Marvell will transition into a hybrid model, inheriting Lumentum's internal factories while keeping its chip side outsourced. The combined company would also gain access to gallium arsenide (GaAs) technologies.

A $115 billion bet and a long road to 2028

Over the years, Marvell — already one of the biggest custom ASIC suppliers, with clients such as Google, AWS, Meta, and Microsoft — has also strategically positioned itself as a major player in the optical interconnects market, supplying the largest optical transceiver manufacturers. In March 2026, Nvidia invested $2 billion directly in Marvell in a partnership that brings Marvell’s custom XPUs and scale-up networking into Nvidia’s NVLink Fusion ecosystem.

Marvell's biggest optics competitor, Broadcom, also supplies custom AI accelerators, networking silicon, and optical connectivity components, offering both the electronic chips and the optical components. Acquiring Lumentum would give Marvell a more comprehensive portfolio similar to Broadcom's. Nvidia’s separate $2 billion stake in Lumentum would also convert into Marvell shares, consolidating its two $2 billion bets into a single holding.

A key question is how vertical integration affects existing customers, as Marvell supplies optical module manufacturers, while Lumentum sells optical components to companies that also compete with its transceiver business. Merging operations could create concerns among customers that depend on the companies for critical components. Marvell CEO Matt Murphy addressed this issue during the company's November 2 investor conference call, stating that the company intends to maintain its existing component supply model. Lumentum CEO Michael Hurlston also emphasized that supplying competitors is already an established part of the optical industry's business model.

Financially, Marvell expects the combined company’s total addressable market to reach about $550 billion by 2030 — roughly $60 billion more than the two companies’ standalone estimates combined. The companies also expect more than $1 billion in annual run-rate cost synergies, primarily from cost of goods sold. Combining Marvell’s current-quarter guidance with Lumentum’s latest results, the companies put the merged business at about $17.7 billion in annualized revenue.

According to Murphy, pairing Lumentum’s next-quarter guidance with analyst consensus for Marvell’s next quarter lifts that figure to more than $21 billion. Lumentum's recent performance shows the growing demand behind these projections. The company reported $1.26 billion in revenue for its first fiscal quarter of 2027, a 136.5% year-over-year increase. It also announced a second major near-packaged and co-packaged optics design win, which Hurlston said he expects to generate more than $5 billion in revenue.

However, the merger's huge valuation raises questions about whether future growth will justify the acquisition price. Investors reacted negatively to the announcement, with Marvell shares closing down 12.7% at $171.41 on November 2 and Lumentum falling 18.6% to $684.40. For now, the agreement is subject to a lengthy review, with an outside date of November 1, 2027, and options to extend to February 1, May 1, and finally August 1, 2028, if regulatory approvals are still pending. If the deal then fails on regulatory grounds alone, Marvell owes Lumentum $3.2 billion. However, if either board backed out or took a rival offer, Marvell would pay $5.8 billion, and Lumentum $2.9 billion.

Intel Foundry last week made available its Intel 14A process design kit (PDK) version 0.9, an important milestone in the development of this next-generation manufacturing technology. The company says that the production node is reaching performance and yield maturity expected at this stage of development, and the results are backed by silicon validation. Intel plans to release PDK 1.0 in the first quarter of 2027, which will validate the technology's readiness for high-volume manufacturing (HVM).

14A PDK v0.9 is here

A process design kit contains transistor models, design rules, and other information that enables chip designers to develop products for a particular manufacturing process using electronic design automation (EDA) tools. The accuracy and quality of the PDK are crucial for modelling how chips will perform once manufactured, and the release of PDK 0.9 is particularly important because it provides customers with a representation of Intel 14A based on actual silicon measurements rather than on theoretical models or simulations. At this stage, customers can proceed with product development with greater confidence that the technology will meet their requirements when it comes to performance and power consumption.

Intel says that PDK 0.9 lets customers develop designs intended to enter risk production around the time the process is certified, which — provided that PDK accurately reflects the characteristics of manufactured silicon — in many cases enables chip developers to greatly reduce the number of silicon revisions between initial tapeout and mass production. Of course, availability of PDK 0.9 does not indicate that Intel 14A is ready or even close to mass production, as the company expects to validate HVM readiness only with PDK 1.0, sometime in Q1 2027. Again, this does not mean that 14A will enter mass production in early 2027, as Intel itself expects to begin mass production using its 14A process technology in 2028, following risk production for its own products in the second half of 2027.

"From a customer perspective, the PDK 0.9 gives customers the confidence to design products on Intel 14A, as the technology is reaching the industry-standard performance and yield maturity expected at this stage of development, supported by silicon-backed validation," said Ben Sell, corporate vice president and general manager of front-end technology development at Intel Foundry.

Building on top of 18A

Intel 14A builds on top of architectural foundations introduced with Intel 18A but incorporates several substantial enhancements. These include 2^nd Generation RibbonFET 2 gate-all-around (GAA) transistors, PowerDirect backside power delivery (which delivers power right to the transistor source/drain regions without using intermediate connections like TSVs used by PowerVia), and Turbo Cells (high-performance standard cells designed to accelerate timing-critical paths in CPUs and GPUs), which provide chip designers with additional ways to increase performance and optimize power efficiency. Since Intel has previously outlined advantages of these technologies, the latest announcement does not provide updates regarding transistor performance, power consumption, or transistor density figures for Intel 14A.

Beyond improvements to transistor, power delivery, and interconnect technologies, Intel is applying manufacturing experience gained during 12 months of Intel 18A production to accelerate maturation of 14A. Specifically, the company says it has increased investments in inline defect detection, modeling, and simulation to identify potential manufacturing problems earlier in the development cycle. These initiatives are intended to improve manufacturing yields, process variability, ultimately transistor performance, and reduce production cycle times. Intel also says it has introduced several strategic initiatives to accelerate technology development, although it does not quantify their impact.

New collaboration model

Another important change concerns Intel's relationships with equipment and materials suppliers. The company says it has revised its collaboration model to involve technology development teams and external suppliers earlier in the process development cycle. The goal of such close collaborations is to address manufacturing defects and improve equipment capabilities before they become obstacles for yield improvements after the technology enters mass production. Intel also conducts regular yield summit meetings with suppliers to accelerate progress on critical development objectives.

"This has required evolving our collaboration model with equipment and material suppliers, and earlier engagement from our [technology development] leaders with suppliers to drive improvements in defects and equipment capabilities," Sell said.

A bonus of such early collaboration is that equipment and materials suppliers may incorporate Intel's requirements into their standard products and development roadmaps. This could give Intel an advantage over competitors, which would have to either adapt their manufacturing processes to equipment optimized around Intel's requirements or work with suppliers to develop alternative solutions from scratch.

Historically, Intel frequently set the direction for semiconductor manufacturing technologies as other chipmakers subsequently adopted similar approaches. One notable exception was immersion DUV lithography, which Intel adopted after TSMC, which led the development of immersion DUV lithography. By engaging equipment and materials suppliers earlier, Intel could regain some of its historical influence over the development of industry-standard manufacturing solutions, though the importance of this should not be overestimated.

Expanding design ecosystem

Meanwhile, Intel continues to expand the design ecosystem for its 14A technology. Cadence and Intel have established a design-technology co-optimization (DTCO) collaboration focused on next-generation AI-driven design tools and intellectual property, whereas Keysight, Siemens, and Synopsys have announced design-tool certifications for the process. Intel is also working with other software developers and IP providers to validate design flows and reusable building blocks required by prospective foundry customers.

Intel says it is encouraged by customer feedback regarding the progress of 14A development. However, the company has not identified any customers that have committed to manufacturing products using the technology, disclosed customer tape-outs, or announced specific manufacturing agreements, which is normal for the foundry industry. For Intel Foundry, attracting external customers remains particularly important because development costs of modern leading-edge process technologies can only be recoupled when they are used to make hundreds of millions of chips, way more than Intel sells these days. Meanwhile, the commercial success of Intel Foundry with advanced manufacturing technologies depends not only on transistor performance and manufacturing yields, but also on its ability to deliver predictable development schedules.

Looking ahead, Intel intends to continue improving performance, yields, variability, and manufacturing cycle times of 14A, though for now the company does not disclose any actual goals. Intel also plans additional process enhancements and performance refinements for 14A-E and 14A-P nodes after the initial technology becomes available. However, exact schedules for these nodes are not known at the moment.

"Our next major milestone is the Intel 14A PDK 1.0, expected in the first quarter of 2027," said Ali Farhang, corporate vice president and general manager of Intel Foundry's design technology platform organization. "I am looking forward to sustaining this level of quality across future releases and continuing to earn our customers' trust by delivering on our commitments with a customer-first mindset."

A memory smuggler has detailed how he gets export-controlled HBM chips from South Korea into China using a loophole. According to The Information, the smuggler owns a chip design firm that build cheap, low-performing processors that fall under the U.S. and South Korea’s export controls. They are then paired with expensive HBM from Samsung and SK hynix, that, on their own, are banned for export to China. But because export control rules only look at the performance of the server processor and not at the other components attached to it, this allows the HBM chips attached inside them to slip under the radar and make their way into China.

It’s not a risk-free operation, though. Once the mediocre processors with high-end memory chips land in Hong Kong and are smuggled across the border into Shenzhen in the luggage of commuters that cross between the two regions daily, they end up in workshops where technicians heat up the boards to soften the solder, gingerly lift the crucial memory chips, and discard the rest of the components. Despite having a high failure rate, the high price of HBM chips makes the procedure quite lucrative.

A Shenzhen-based chip broker has been making big money matching up suppliers such as the smuggler and companies that are desperate for HBM. “A year ago, a single HBM3E unit changed hands in China for several hundred dollars,” he tells the publication. “Today it’s about $4,000.” With an AI chip requiring six to eight high-end memory chips, that means the broker is raking in $24,000 to $32,000 for every AI GPU.

Chinese AI labs face this exact memory chip bottleneck when acquiring AI GPUs. While Chinese memory manufacturer CXMT has already begun risk production of HBM3E and is expected to mass produce them by the end of this year, it’s still reportedly suffering from low yield, which makes their chips expensive to produce and procure. We see this with Huawei’s Ascend 950DT, its current top-of-the-line processor that goes for about $37,000 — it offers similar pricing to Nvidia’s B200 AI GPU but only delivers half the performance of the previous-generation H100.

Huawei has reportedly said that its next-generation flagship AI processor, the 960DT, would deliver a similar performance as the H100. However, since the company cannot purchase HBM from Samsung and SK hynix, and Chinese memory manufacturers do not have the capacity to supply all its chip demands, Huawei told customers that they have to find the HBM that these servers need themselves. This would further fuel the demand for these chips, increase the price and make it more lucrative for smugglers to set up similar operations.

But given that this method of moving HBM chips into China is becoming more popular, the smuggler fears that South Korean and U.S. authorities would clamp down on their operations soon. Washington has been going down hard on activities like this, and we’ve seen high-profile arrests including some Super Micro executives and the CEO of a California-based tech company. Other countries like Taiwan and Malaysia have been ramping up their anti-smuggling activities, too, so it’s probably just a matter of time before Seoul follows suit.

Some 700 Micron employees in Taiwan will receive five years’ worth of salary in bonuses as the company announced three bonuses in a single payout. According to Digitimes, this accounts for about 17% of the over 4,300 production-line employees working at Micron Taiwan. The remaining staff will not come out empty-handed, though, as they will receive three bonuses in the month of October. The news comes as Micron continues to battle worker unrest and unions fighting for increased pay.

The lump-sum payout consists of three incentives — an annual performance bonus that’s estimated to be between 7.5 and 12.5 months of salary for the majority of workers, a mass-production bonus amounting to 20% of their annual salary, plus a one-time $31,000 (NT$1,000,000) appreciation bonus which will be prorated for employees who haven’t reached a full year of service. Micron workers across the globe also expect a new quarterly profit bonus which will be paid 50% in cash and 50% in stock. This bonus will start in January 2027, with the first one to be paid 100% in cash.

Micron is following in the footsteps of Samsung and SK hynix, which have recently paid out massive bonuses to their workers of up to $400,000. This is a direct effect of the AI-driven memory chip boom, which saw the big three memory chip manufacturers — Micron, Samsung, and SK hynix — raking in massive orders from AI hyperscalers. The record profits that these companies are drawing from the appetite for AI data centers have led workers on production lines to demand a slice of the pie. Samsung workers voted to accept a $340,000 average bonus in May 2026, while SK hynix workers are set to receive $477,000 in bonuses this year, which could potentially grow to almost $900,000 in 2027.

Despite this seemingly massive payout, the workers’ union at Micron Taoyuan is still in the midst of a dispute with management regarding their pay. Some officials of the group have already launched a one-day strike as they call for clearer profit-sharing arrangements and terms for bonuses, with nearly 70% of members at the Taoyuan site turning down management’s latest offer. The two sides are tentatively set to meet on November 6 again for further negotiations. On the other hand, the union at Micron Taichung has already agreed to a 10% employer’s contribution towards worker pensions and a tripling of their day-shift allowance.

These bonuses allow workers to get a share of the massive profits that the chipmakers are raking in at the moment, allowing them to stay competitive for chip talent. However, their reliance on performance and profit bonuses also means that these incentives could fall precipitously if AI demand falls and the demand cycle returns to normal.

The AI industry continues to gobble up manufacturing resources that were once dedicated to serving PC, smart device, and gadget makers. We’ve seen huge demand/supply driven price rises in RAM, GPUs, SSDs, and more through 2026. Now that most basic and unglamorous electronics necessity, the PCB, looks set to join them. A news report published by Nikkei Asia quotes several leading PC and PCB industry managers, making it clear we are going to see PCB (and PCB subcomponent) shortages and price rises in the coming months.

An unnamed exec from an American PC maker spoke to Nikkei about the dire shortage of PCBs. “Even though PC shipments could decline again next year, we are still struggling to secure enough PCB supplies to meet our needs,” said the manager, who asked to remain anonymous. They were talking about securing enough supplies to make plans for products in the coming year. Several commenters pointed to AI computing demand eating up production capacity.

The outlet also talked to business people further up the supply chain – the makers of PCBs and the makers of the components/materials needed to actually make PCBs. Traditional PCB demand is becoming underserved as AI products demand and pay more. One PCB maker talking to Nikkei said that a significant number of products have lead times that have doubled. Specifically, some PCB orders will take as long as 30 months to fulfill. Another PCB supply firm explained to Nikkei that a new order today would not be fulfilled until late in 2028.

Though PCB makers are planning to invest and expand, they also need to secure multiple upstream materials. These can include copper clad laminates (CCLs) and the specialized fiberglass used for PCB construction.

One Taiwanese PC maker noted that costs for CCLs have surged at least 12 times since July. Moreover, one of the world’s leading suppliers of CCLs has told the Nikkei that it has an order book that is currently filling up to 2030. This situation appears to have occurred despite its plans to triple capacity by 2028.

In closely related developments, Nikkei observed that Nvidia recently announced partnerships with several major chip substrate makers. Chip substrates are essentially the tiny and intricate PCBs that CPUs and GPUs are mounted on. Japan's Ibiden, South Korea's Samsung Electro-Mechanics, and Unimicron of Taiwan all have new agreements with the Green team. Unimicron is looking at expanding capacity by 2.5x over the next three years.

PCBs have been viewed as an unglamorous lower-tech part of the supply chain, partly due to the small numbers on the BoM. That may change. Companies are now racing to ramp up production of advanced PCBs and chip substrates to meet demand, and boost income.

Finally, the source report also notes that it is increasingly difficult to get the engineering staff required at new production facilities. Salaries have already risen 20% to 30% across the PCB industry to keep skilled employees.

HP, Asus, and Acer have reportedly moved some of their manufacturing capacity back into China as increasing component costs — driven by AI — bite into their margins. According to Nikkei Asia, increasing bill-of-materials costs have made China’s experienced workforce, relatively lower prices, and established supply chain ecosystem a more attractive option. However, they are not going back to traditional suppliers like Foxconn, who have focused their production capacity on AI data centers. Instead, they’re signing contracts with smaller Chinese contract manufacturers, like Luxshare, Huaqin Technology, and Longcheer Technology, that are trying to establish themselves in PC manufacturing.

Many PC brands slowly moved out of China in 2024 and 2025 as the U.S.’s sanctions and tariffs on China have increased prices and forced them to find friendlier nations. While these nations do not have established supply chains and expertise like China, it at least spreads the risk as manufacturers avoid getting caught up in geopolitical tensions.

However, it seems that rising component prices have forced them to move back some of their capacity into China. The biggest culprit is the AI-induced memory and storage chip shortage, which has caused memory prices to climb an unprecedented 500% in 12 months. More than that, other parts like PCBs and fiberglass cloth used in motherboard manufacturing are seeing increasing prices, which Acer chairperson and CEO Jason Chen bemoaned as suppliers hyping shortage fears to protect margins.

While tech companies aren’t abandoning their “China+1” diversification strategy, the mature industry in China is helping offset increased component costs. Aside from that, the Chinese contract manufacturers often have better access to memory chips from domestic manufacturers like CXMT. "These Chinese contract manufacturers have been telling potential clients and computer makers that working with them could be a good option for securing better access to Chinese-made memory chips," a supply chain manager in the computer ecosystem told Nikkei Asia. "They are marketing themselves as a good alternative to even help sort out the supply chain."

Moving back some manufacturing capacity into China is easing some of PC manufacturers’ cost concerns, but it’s also negatively impacting the newly established supply chains in Southeast Asia. "We built two new production lines in Thailand for the PC clients, and now they are moving substantial orders back to China,” one manager at a PC component supplier told the publication. “Those two lines have not yet turned profitable, and I don't know when they will add the orders back."

Unfortunately, building an entire supply chain for PC manufacturing is slow and expensive. The U.S. has been trying to accomplish this for years, and, so far, only Anduril has attempted to build laptops with 90% of its component costs coming from the U.S. and other allied countries. Even then, it expects its devices to be around 20% more expensive than the competition, which it could afford by offering them mostly to critical industries that demand supply chain security, like the government and the military. But if you’re a PC manufacturer vying for customers in the consumer market, you’re likely incentivized to find the lowest possible costs to be able to compete in pricing.

Solidigm, an American subsidiary of SK hynix, one of the biggest flash chip makers on the planet, is reportedly in talks with the Commerce Department over plans to invest $45 billion in a new plant to be built in the United States. But, Bloomberg reports, there's a catch — Solidigm wants to be given the go-ahead to export equipment to upgrade its existing plant in Dalian, China. The company has purportedly told officials that the upgrades would allow the Chinese plant to then help finance the cost of its U.S.-based counterpart, according to unnamed sources. It's as-yet unclear how the proposal was received, or whether the Commerce Department is inclined to agree to the deal.

The U.S. government has been keen to drive at-home manufacturing wherever possible, including for chips used in its computers and data centers. National security is regularly cited as a key reason behind the move. It's also the reason for the government's stance on exporting technologies to China, including the equipment that Solidigm says will help upgrade its Dalian plant. Similar export restrictions are in place for high-end AI data center components, with a black market having sprung up to take the place of sanctioned sales. Earlier this month, it was reported that some of Nvidia's powerful Blackwell Ultra B300 GPUs are being used in China Telecom data centers, with no explanation of how they got there. A 2025 report claimed that a cool $1 billion worth of Nvidia AI chips had been smuggled into China, a figure that is sure to have increased significantly as 2026 draws to a close.

In this case, Solidigm's planned Chinese factory upgrades could be mutually beneficial, allowing funds to be transferred to the new U.S. plant. But that requires the U.S. government to give it permission to ship the machinery in the first place, something that is far from guaranteed. The Dalian factory produces NAND flash memory, the likes of which are used in everything from relatively simple devices to full-blown data centers. It also comes at a time when global NAND production is a hot-button topic. Samsung and SK hynix are upgrading their Chinese factories to produce more of the chips used in AI data centers in an attempt to meet growing demand. Manufacturers have already slashed production of consumer-focused memory in favor of the more lucrative data center-grade components, causing prices to spike globally. This volatility in the market as a whole was given as one of the reasons SK hynix chose to cancel a planned Solidigm IPO earlier this week.

Beyond dangling a $45 billion plant, Solidigm has also allegedly told the Commerce Department that its total investment in U.S. manufacturing could reach $100 billion eventually, with construction in New York penciled in for 2027. The company is fresh from its latest earnings call, where it announced revenues of $75 billion with $60 billion in operating profit, and $28 billion in net. The company made no mention of its Dalian plant or a planned US investment, but did warn that memory shortages are set to last through 2030.

Defense contractor Anduril, which is known for its military drones, just announced that it’s building laptops in the U.S., with the company saying that it will begin taking orders in 2027. According to its press release, it will call its laptop product line BlueChip and will use a Snapdragon X Series SoC for its core computing capabilities. It also said that it already has functional prototypes, with 90% of the procurement cost of the components used to build it coming from suppliers in the U.S. and other allied countries. However, it’s also aiming for a fully domestic supply chain in the long term.

This means that Anduril is not only sourcing domestically produced semiconductors but also uses other made-in-the-U.S. parts, like batteries, the external casing, and even the glass for its screen. “Other companies might design their computers in the U.S., Anduril makes them here,” the Anduril founder Palmer Luckey said in the Anduril YouTube video. “We’re making parts out of metals that the U.S. knows how to extract, knows how to refine, knows how to process, and knows how to mill at scale at a reasonable price; and that goes for the entire laptop. The same thing goes for the battery technology.”

Luckey has been planning to launch a fully U.S.-made laptop since last year but said that it’s going to cost 20% more than a comparable device. Still, it seems that the company is targeting critical industries — government, defense, first responders, and public safety — which might be willing to spend more to ensure the security of their computer systems. Anduril is also better placed to start building a domestically designed, built, and sourced laptop today as the White House’s efforts to bring back semiconductor manufacturing have resulted in massive fabs like TSMC Arizona and Samsung’s Taylor, Texas site. Taiwan’s plan to support smaller companies key to TSMC’s supply chain by funding industrial parks in the U.S. will also likely benefit BlueChip, as it would make it easier for the company to source needed parts it would otherwise have to order from abroad.

Anduril has acknowledged the progress in the U.S.’s efforts to bring back computer manufacturing to its shores but also acknowledged the challenges that it faces when it comes to building a 100% domestic supply chain. “…manufacturing complete computers also requires circuit boards, displays, batteries, and other components still largely produced overseas. Restoring domestic computer manufacturing requires rebuilding that broader industrial base,” it said in its press release. “BlueChip will take a phased approach, beginning with expanding domestic sourcing and manufacturing, progressing toward eliminating reliance on foreign suppliers, and ultimately establishing an end-to-end American supply chain.”

TSMC is weighing raising prices for its Chip on Wafer on Substrate (CoWoS) advanced packaging technology by as much as 20%, reports Trendforce, citing supply chain sources and local media. The increase reflects strained capacity amid AI demand and longer delivery times for chipmaking tools. Such a hike would be significant, as CoWoS is already one of the tightest links in the AI supply chain. TSMC has yet to confirm the report.

CoWoS combines logic dies and high-bandwidth memory (HBM) stacks within a single package, which is how AI accelerators get the data bandwidth that demanding workloads require. Building these packages is only getting harder as chip designers cram in more compute and memory. Nvidia’s Blackwell already pairs two large GPU dies with eight HBM3E stacks, whereas the upcoming Rubin and Rubin Ultra are expected to push integration further, which will increase pressure on packaging and the supply chain that supports it.

Testing is turning into another bottleneck. Blackwell reportedly takes three to four times longer to test than Nvidia’s previous-generation Hopper, and Rubin could need as much as seven times longer. Extended test cycles keep equipment occupied for longer, which makes it harder to increase output as demand grows. GPUs are not the only products competing for capacity either, as server CPUs and custom ASICs also need advanced packaging, adding more strain to an already crowded supply chain.

Tools are also taking longer to arrive, as equipment lead times have reportedly stretched from three to six months to as long as eight months, making timely access to fab equipment increasingly important. As a result, TSMC has reportedly placed this year’s equipment orders at existing prices instead of negotiating discounts or extra features — a departure from its customary approach of using its purchasing power to secure better terms. Essentially, getting the tools on time now appears to matter more to the company than getting them cheaply.

The squeeze echoes a report from September, which said that TSMC’s projected semiconductor equipment requirements had almost doubled in six months as the company expanded production to meet AI demand. Cliff Hou, deputy co-COO at TSMC, said that by July the company’s expected equipment needs had reached 1.9 times its original estimate as AI demand accelerated. “Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes,” Hou said at the time.

TSMC is also trying to broaden its packaging supply chain. Earlier this month, GlobalFoundries agreed to produce silicon interposers for TSMC’s CoWoS in the U.S. under a five-year contract worth $2 billion, with production expected to ramp up in the first half of 2028. However, interposers are only one part of the packaging flow, so the agreement alone will not eliminate shortages.

Higher costs are not limited to packaging. TSMC is reportedly considering broader price increases for 2027, with wafer prices on advanced process technologies expected to rise by 5% to 10%. Customers using 2nm and 3nm-class nodes could face the steepest hikes, whereas those seeking capacity beyond their original allocations may have to pay additional premiums, which could push some costs up by as much as 25%.

Industry estimates cited by Trendforce put TSMC’s monthly capacity at over 106,000 wafers in 2026, with a target of 227,000 wafers in 2027 as the company works to keep pace with demand for increasingly complex AI processors. If both the packaging and wafer price increases materialize, the cost of AI hardware will likely climb further, and some of that will inevitably be passed down the chain.

On October 21, during GTC Berlin, Nvidia announced several massive, multi-billion-dollar deals with supply chain partners across substrates, advanced packaging, semiconductor testing, and optical engines to expand production capacity. Aimed at overcoming severe bottlenecks restricting the current and future AI infrastructure buildouts, the deals feature commitments and production roadmaps stretching through 2028, securing capacity for Nvidia and ensuring resiliency and redundancy in its AI accelerator supply chain. “We are in the midst of the largest infrastructure buildout in human history. Demand is extraordinary. Capacity is the constraint,” said Nvidia CEO Jensen Huang. “Our supply chain partners are the world’s best manufacturers. I’m grateful they are expanding capacity around the globe to scale production and help us deliver the AI supercomputing systems powering this new industrial revolution.”

The deals cover two major AI accelerator supply chain categories: hardware interconnects and OSAT (Outsourced Semiconductor Assembly and Test). Under hardware interconnects, Nvidia is securing capacity for both substrates and co-packaged optics. Nvidia has signed deals with Ibiden, Unimicron, and Samsung Electro-Mechanics — three of the world's five largest substrate manufacturers — to support its production capacity expansion and reserve significant portions of that capacity for the chipmaker. The company says it plans to secure 2.5x dedicated substrate capacity over the next three years. Nvidia has also signed agreements with SPIL (Siliconware Precision Industries Co., Ltd) to expand manufacturing capacity for the optical engines used in co-packaged optics by 15x by mid-2027.

On the OSAT side, Nvidia and Amkor are targeting a 300% increase in interposer wafer capacity by the end of 2028 through expanded advanced packaging capacity in South Korea, to support higher production volumes for Nvidia's platform. The company also plans to double its semiconductor testing capacity by 2027, investing $1.1 billion to reserve capacity from KYEC (King Yuan Electronics Co., Ltd.), the world's largest semiconductor testing company, which currently handles nearly all of Nvidia's chip testing.

Nvidia currently leads the AI chip market by a considerable margin, with its extremely powerful accelerators sitting in a vast majority of AI data centers globally. These deals target major bottlenecks in the AI chip supply chain, suggesting Nvidia doesn't plan to relinquish its position soon. So, why these specific deals? What are the exact details? What's the broader play? And where do Nvidia's competitors and the rest of the AI industry stand?

Uncorking bottlenecks

The substrate base, a specialized intermediary layer in every accelerator package that connects the tiny silicon chips above it to the board below, is one of the most critical bottlenecks in the AI chip supply chain. As we detailed in our comprehensive substrates roadmap, this indispensable physical layer, manufactured by only a handful of companies, is expanding in both the X-Y and Z axes as chip makers package an increasing number of components onto one board. Nvidia's Blackwell generation places two reticle-sized GPU dies and eight HBM3E stacks on a single package. Its Rubin and Rubin Ultra architectures mount even more components. As a result, each substrate now consumes much more material and production capacity, even as demand for individual substrates soars.

Fubon Research estimates that Nvidia would supply around 12.4 million data-center AI GPUs in 2028, up from a projected 8.2 million in 2026. Each one would feature a substrate layer. Nvidia is staying ahead of the curve, with a planned 2.5x capacity expansion over the next three years, led by Ibiden. Earlier this year, the company signed a deal to provide a multibillion-dollar capacity reservation advance to support Ibiden's Ono Plant in Japan, targeting 3x the plant’s current individual capacity.

To reach its 2.5x target, Nvidia has also brought on Samsung Electro-Mechanics, Samsung's substrate-manufacturing subsidiary, as a supplier. Beyond the immediate capacity from Samsung Electro-Mechanics’ existing operations, the deal will support facility upgrades and new plants in Busan and Sejong. Nvidia is projected to account for a significant portion of the substrate manufacturer’s output by 2028. To build even more redundancy, Nvidia also signed a capacity reservation agreement with Unimicron, supporting the latter's substrate manufacturing expansion in Taiwan. The expansion will reach full capacity by mid-2028 but is expected to start providing capacity by Q2 2027.

Next on Nvidia's to-expand-capacity list announced on October 21 is co-packaged optics. As next-generation speeds surpass 224 Gbps per lane, traditional copper traces on the board consume considerable power to move data even a few inches from the processor to the edge of the board. To address this, the industry is moving the optical engine into the accelerator package itself via co-packaged optics. Nvidia had long detailed its plans for silicon photonics and co-packaged optics as the standard for future AI accelerator packages. The company has signed a deal with Taiwanese optical engine manufacturer SPIL to expand production capacity by 1,400% by mid-2027, with plans to double again by the end of 2028.

A 4x increase in packaging, double the testing, and $1.1 billion specifically for U.S. facilities

Interestingly, the world's biggest semiconductor company, Nvidia, doesn't own a single Fab. After TSMC manufactures the logic chip and binds it with memory chips on a silicon interposer, final-assembly companies such as Amkor package that integrated module with the substrate and protective casing into the final accelerator package. These final steps are increasingly incorporating co-packaged photonics chips. Nvidia’s deal with Amkor aims to expand the latter's interposer wafer capacity by more than 300% by the end of 2028, through advanced packaging capacity expansions in South Korea. Amkor confirmed the deal is worth $1.3 billion, bringing Nvidia's total investment in Amkor across its Arizona and South Korea facilities to $3 billion.

After final assembly, finished Nvidia AI accelerator packages are shipped to KYEC for extreme testing. KYEC currently handles nearly all of Nvidia's chip testing. It therefore comes as no surprise that Nvidia expects semiconductor testing capacity to double from calendar 2026 to 2027 through buildouts across KYEC’s facilities in the U.S., Taiwan, and Singapore. On October 13, Nvidia signed a deal to pay KYEC $1.1 billion to reserve testing capacity at KYEC's new $1.4 billion U.S. facility, where high-volume production is slated to begin in April 2027. The funds will build domestic testing capacity and bolster the domestic supply chain. At the same time, KYEC is aggressively expanding operations in Singapore, where it expects high-volume production to begin in February 2027.

The bigger picture

Nvidia has been aggressively securing production capacity and long-term supply commitments to meet anticipated demand for its next-generation AI accelerators. According to its August 2026 financial disclosures, the company had accumulated $279 billion in outstanding supply and manufacturing-capacity commitments by July 2026. The company has since signed several additional deals. These commitments cover future component purchases and manufacturing capacity reservations, particularly for memory and chip production. Combined with its more recent agreements, Nvidia is securing nearly every stage of its AI accelerator supply chain, from semiconductor fabrication and HBM memory to substrates, advanced packaging, optical interconnects, final assembly, and testing.

Of course, the rest of the industry isn't standing by. On May 21, 2026, AMD announced over $10 billion in investments across Taiwan's semiconductor ecosystem, specifically targeting advanced packaging and manufacturing partnerships. On October 6, CEO Lisa Su confirmed that AMD intends to increase those investments further. The company is working with TSMC, packaging partners, substrate manufacturers, and memory suppliers to increase production substantially in 2027. Google and Amazon are also aggressively expanding their custom TPU and Trainium accelerator programs.

Intel, meanwhile, is positioning its foundry and advanced packaging operations as alternatives to TSMC's increasingly constrained production capacity. The company is expanding its EMIB-T packaging technology, with reports indicating that Google has already reserved Intel capacity to package more than three million TPUs in 2028. Intel is also advancing its 18A and 14A manufacturing processes as it attempts to attract major external customers.

Samsung is expanding its semiconductor operations as well. The Korean company, which held approximately 5.9% of the global foundry market by revenue in Q2 2026, is ramping up its 2nm manufacturing technology and preparing its Taylor, Texas, facility for volume production in 2027. As detailed in our comprehensive Samsung foundry roadmap, the company is investing heavily in its manufacturing operations as it attempts to close the considerable gap with TSMC.

Perhaps the most ambitious player is new entrant Elon Musk's Terafab, a joint semiconductor manufacturing project involving Tesla, SpaceX, and xAI. The project aims to eventually manufacture the equivalent of one terawatt of AI computing capacity annually, an extraordinarily ambitious target given the industry's current scale. Intel joined the project in April, and Musk later confirmed plans to use the company's 14A fabrication technology. The project aims to deliver its first experimental chips in 2027 and begin high-volume production by the third or fourth quarter of 2028.

Nvidia and other semiconductor firms are continuously fighting against emerging bottlenecks, but compute doesn't come online overnight, and fabs aren't built in a day. So, while almost every inch of the semiconductor supply chain remains constrained, it remains likely that big-name players will continue to invest heavily to ensure that products continue to flow into neoclouds and data centers alike.

Cadence, one of the largest electronic design automation (EDA) companies, has unveiled Maestro, its new portfolio of domain-specialized AI models tailored for its chip design agents, in a press release sent just ahead of earnings. In initial results compared with general-purpose AI models, Cadence claims up to a 30% improvement in the quality of results and that Maestro effectively uses fewer tokens for the same task, with up to 5x the token efficiency. The first models “are available to select early access customers” in Q4 2026, and customers may run them on Cadence’s cloud, public clouds, or customer-controlled on-premises environments and post-train them on their own “proprietary data, designs, and workflows.” To learn more about Maestro, we spoke with two Cadence executives: Rob Knoth, senior group director of strategy and new ventures, and Paul Cunningham, senior vice president and general manager.

This approach is distinct from Synopsys’ own specialized model, GPT-Synopsys, which will run on OpenAI-hosted infrastructure, without using customer data to train the model. The models of both EDA giants, announced less than a month apart, now split on where a customer’s design data goes. Where they might not differ is why: Paul Cunningham, senior vice president and general manager at Cadence, told Tom’s Hardware Premium that agent costs have “really started to explode,” adding, “And I think the world realized so.” That makes it a natural step, he said, to move more of the agents’ iterating “into the weights of the models themselves.”

Maestro takes this step through Cadence’s AI Super Agents, which “interpret design intent, decompose tasks” and “orchestrate the Maestro portfolio with other leading frontier and open-weight models,” evaluating trade-offs to guide decisions with domain expertise. It also uses reinforcement learning (RL), where Cadence’s “deterministic solvers evaluate outputs against engineering objectives, constraints and ground truth,” and, importantly, the results feed back into the models for improvement.

The models include Nvidia’s Nemotron, and customers can run the customer-data training step themselves with Cadence’s fine-tuning harness, potentially “on their own GPUs, on their own network,” Cunningham said. He added that Nemotron, specifically, was “giving really solid results and actually improving very, very fast.”

One constant that keeps popping up with agentic EDA is the need to nail down what the numbers actually measure. In chip design, quality of results usually refers to the design’s power, performance, and area, though Cadence didn’t specify what its 30% figure measures. Both it and the 5x token efficiency figure are measured against “a general-purpose foundation model,” which Cadence told us is the open-source model Maestro started from before its training. The company wouldn’t name the foundational AI model that Maestro is derived from beyond mentioning that it is “one of the leading open source models that’s very competitive with commercial frontier models.”

Cadence credits the token savings to balancing its EDA and system design automation (SDA) “tool calls with LLM invocations.” As an analogy, Cunningham said, “You don’t need to drive to Safeway in the jet engine,” and you want to use “the right model at the right time for the right task.”

Runtime does matter, too: as Rob Knoth, senior group director of strategy and new ventures at Cadence, told Tom’s Hardware Premium in September that a tool call could take anywhere from hours to days to return a value, while the AI industry’s training loops are “used to minutes.” Efficiency could also lower costs, since Maestro use counts toward Cadence’s agent pricing, a subscription with a consumption allowance and charges for use beyond it, Cunningham said. He didn’t say whether the token savings cut a customer’s bill.

Being flexible for the customer is a key element of any solution, and for Cadence’s competitor Synopsys, this lies in Autopilot, which Synopsys says allows customers to “choose among commercial, open-source, and fine-tuned language models” across “Synopsys-managed and customer-managed deployments,” with cloud or on-premises infrastructure. For agent security, such as sandboxing, Cadence says it’s working with Nvidia on an integration with Nvidia’s OpenShell Reference Architecture, which Nvidia launched last week, naming both Cadence and Synopsys. These options can help protect customer intellectual property.

Cadence has had a busy 12 months with customers and agents alike. During Cadence’s July earnings call, CEO Anirudh Devgan said ChipStack, its design and verification agent, “has more than 20 customer engagements,” and ViraStack, its custom and analog agent, “more than 25 customer engagements.” Socionext said just last week that it was applying InnoStack. Silicon Labs has also credited ChipStack with accelerating debugging, and both companies say they are watching Maestro next.

Cadence's agentic consolidation began with its acquisition of ChipStack back in November 2025. In June 2026, the company claimed that its agent had reached Level 5 autonomy, which we explored in detail. In September, Knoth teased Maestro’s ingredients to Tom's Hardware Premium a month early, two days before the GPT-Synopsys announcement: “reinforcement learning loops, domain-specific post-training of open-weight models, model routing.” Maestro is now sitting under all four super agents, targeting a similar year-end window to Synopsys’ Autopilot; the table below has the full timeline.

This rapid pace of progress means that a clear distinction has to be made between early access and general availability. Both Cadence and Synopsys can point to customer engagements, and, at least in the latter’s case for the AgentEngineer portfolio and Autopilot platform, general availability remains a goal by year’s end; Cadence hasn’t given a general availability date for Maestro. For GPT-Synopsys, though, only “early technology engagements are underway,” according to its partners. The platforms and agents remain works in progress.

For Maestro, Cunningham hopes for “more case studies, more quantifiable benefits” through Q4. The real story, as he aptly put it, is that “we’re going to bring agents and agentic AI natively into our vertical, not that our vertical is going to get embedded into general-purpose agents.” Only customer results on real workflows will test Cadence’s 30% number, but going by what both companies have shown so far, their own early figures are extremely promising and exciting for the EDA industry.

Intel and AMD have spent decades competing for the processors inside PCs and data centers, but the rivalry hasn't stopped the two companies from working together when their interests align. And now, Intel CEO Lip-Bu Tan has reportedly discussed potential areas of cooperation with AMD chief Lisa Su, adding another possible partnership to the mix as Intel tries to regain its footing in the semiconductor industry.

According to a recording (embedded below) of Tan’s October 24 fireside chat with Chinese American Semiconductor Professional Association (CASPA) President Jimmy Cheng, the Intel CEO outlined his plans to rebuild the company’s CPU business, develop chips tailored to specific customer workloads, and attract more customers to its foundry operations. However, Tan did not publicly detail the reported areas of potential cooperation with AMD CEO Lisa Su.

Intel has traditionally built its business around its own processor roadmaps, but Tan says the company needs to be more flexible as customers look for silicon designed for particular workloads. He pointed to Intel's Xeon processors as one area where that approach is changing, alongside continued development of GPUs and accelerators.

"We have to reclaim the leadership in CPU. That is something that I am very determined to do." Tan said.

He also described a change in how Intel approaches customization. "Intel is so proud they never want to modify for customer needs," he said. "I'm modifying it for customer needs, and so that, I think, to me, is a fast-growing area, and I'm double, triple down on it."

The strategy extends beyond conventional CPUs, with Tan identifying application-specific integrated circuits (ASICs), co-packaged optics (CPO), physical AI, and advanced packaging as potential growth businesses. He wants two or three of these areas to eventually contribute around 10% of Intel's revenue each.

Intel's foundry business is another major part of Tan's plans. He said the company's 18A manufacturing process had reached volume production, while development of its next-generation 14A process was progressing strongly. Intel has already released version 0.5 of the 14A process design kit (PDK), which provides chip designers with the technical information and tools needed to develop products for the process.

Tan said version 0.9 was coming next, followed by version 1.0 for volume production in early 2027. "We have multiple customers [who] really want us to really scale their business," he said, referring to interest in Intel's foundry services.

However, Intel did not identify those customers or disclose the size of any potential manufacturing orders during the discussion. Notably, in January, Intel had two prospective customers evaluating 14A test chips, with firm supplier decisions expected during the second half of 2026 and the first half of 2027. Tan also described foundry manufacturing as a business where trust matters as much as technology. Customers hand over wafers that will eventually become products on which their own revenue depends, making missed deadlines or manufacturing problems costly. "The moment we take on the foundry, take on the wafer is a lot of responsibility to make them successful," he said.

He recalled one customer who had waited six to eight months hoping he would become CEO before presenting 15 areas where Intel had fallen short. Tan said he addressed the problems individually, after which the customer agreed to deepen its relationship with Intel.

That said, the prospect of further cooperation would not be entirely new. In October 2024, Intel and AMD established the x86 Ecosystem Advisory Group alongside other technology companies to coordinate improvements to the x86 instruction set architecture and make it easier for hardware and software developers to support both companies' processors.

That cooperation has since moved into AI software. Last week, it emerged that AMD was integrating its ZenDNN optimizations into Intel's open-source oneDNN library, bringing the companies' CPU optimization work for PyTorch AI inference under a common software path. The companies have also worked together on Advanced Matrix Extensions and other x86 capabilities through the advisory group, showing that they cooperate on shared technologies while continuing to compete for customers. For now, however, neither company has announced a new agreement arising from the discussions.

Export controls have kept ASML's most advanced EUV lithography machines out of China. Instead, the country's chipmaking industry has relied on less-capable deep ultraviolet (DUV) lithography machines. By using multiple exposures on critical chip layers, these older machines are still capable of producing performant silicon. However, as multiple patterns are applied there are more chances for defects, longer manufacturing times, and higher bills. We spoke to experts like Chris Mack, co-founder and CTO of semiconductor firm Fractilia, to find out how much further DUV can go.

For years, extreme ultraviolet (EUV) lithography has been seen as China’s biggest choke point in the country’s attempts to build cutting-edge chips. The machines, made exclusively by Dutch manufacturer ASML, use 13.5nm-wavelength light to print some of the most intricate features found on modern processors. Sales of ASML’s EUV systems are subject to export restrictions, forcing Chinese manufacturers to squeeze ever more out of older deep ultraviolet, or DUV, lithography instead. The EUV gap alone between China and the West is at least half a decade, according to some analysts.

But even without access to EUV machines, China has gotten surprisingly far in recreating what it offers through existing technology.

Teardowns of Huawei’s Mate 60 Pro in 2023 found the phone’s Kirin 9000S processor had been made by SMIC using a second-generation 7nm-class manufacturing process without EUV. More recently, analysis of Huawei’s Kirin 9030 found SMIC had pushed its DUV-based process closer still to the density associated with 5nm manufacturing – although it continued to lag behind the leading processes used by TSMC and Samsung.

Multiple patterning

The trick is multiple patterning. Rather than trying to print an overly intricate chip layer in a single pass, Chinese manufacturers are dividing up the complex design into several simpler patterns. Repeat the process enough times and you can etch up something approximating the proper layer you intended.

The trick works. But according to lithography expert Chris Mack, co-founder and CTO of Fractilia, asking whether a chip can be made without EUV overlooks the trade-offs manufacturers make in order to do it.

“When this transition first began, what everyone in the industry said as conventional wisdom is that cost-wise, three exposures on a 193 immersion tool cost about the same as one exposure on an EUV tool,” Mack said in an interview with Tom’s Hardware Premium. “At three, it was about even,” Mack explained. “But as soon as you hit four masks – 193 masks being replaced by one EUV mask – then EUV became more cost-effective.”

It’s also likely to produce a higher quality product with fewer defects. Each time a wafer is patterned, that new pattern has to line up perfectly with everything that’s already been etched beneath it. The more individual exposures needed to produce a single layer, the more opportunities there are for things to go wrong. “If you have, say, four 193 masks, you've got all those different overlays, and you've got all these different process variations that start to accumulate,” Mack said.

Chip designers can try and avoid that by leaving more space around features so the finished processor can actually be manufactured reliably. But that means the chip ends up bigger – and bigger chips become expensive very quickly. Making each die larger means fewer fit on every wafer, and wafers cost a lot of money – tens of thousands of dollars each.

“You don't sell wafers, you sell die,” Mack said. “The question is: how many die can I fit onto that wafer, and how many of those die yield, and therefore how many chips can I sell per wafer?”

The efficiency gap

There is some evidence of what that efficiency gap can look like in practice – albeit in memory rather than logic chips. In a June report, Morgan Stanley estimated that Chinese DRAM manufacturer CXMT was producing only around one-third as many bits per wafer as Western competitors. The analysts believed the older process node only accounted for around a third of that shortfall, but said access to lithography was a “hard ceiling” on Chinese memory development. “For advanced logic chips, in theory there could be other innovations to engineer around EUV, but they are not likely to be very efficient and effective,” said Douglas Fuller, a researcher at Copenhagen Business School, in comments to Tom’s Hardware Premium.

It is also why claims that China has reached a particular semiconductor process “node” need to be treated with caution. “If somebody says it's X node – the seven nanometer node, the five nanometer node, the three nanometer node – these words almost have no meaning,” Mack said.

That can be seen in SMIC’s latest chips. Reporting suggests its N+3 process represents meaningful progress towards 5nm-class manufacturing – but the actual measurements show it remains significantly less scaled than established 5nm processes from Samsung and TSMC. That doesn’t mean DUV has reached the end of its useful exploitation.

Stretching DUV's efficacy

Micron is an example of how far DUV can be stretched, producing competitive DRAM chips using DUV, multiple patterning and tight process control. Its 1-alpha generation of chips was developed without EUV. “They pushed 193 farther than any of the other memory makers did,” Mack said. “They were able to make very competitive chips with 100% 193 compared to Samsung and Hynix making them with many layers of EUV.”

Morgan Stanley believes CXMT’s planned move to 1-alpha DRAM – which it wants to use for HBM3e – is achievable without access to EUV, citing Micron as evidence. Indeed, “by the end of the decade, advanced packaging will allow firms to use DUV to produce the latest generations of DRAM,” reckons Fuller.

Micron also designed its products around the manufacturing technology available to it, rather than simply trying to recreate an EUV process on older equipment – something which could be a useful lesson for Chinese manufacturers. “If the entire ecosystem of 193 immersion were available to China,” Mack explained, “then they could probably push a long way with 193 multiple patterning, especially if they optimise designs for the fact that they're going to be using that.”

But Micron was making memory, whose highly repetitive structures make close co-ordination between chip design and manufacturing easier than it is for the much more complicated logic processors found in phones and computers.

“Memory is a lot easier than logic,” Mack said.

And even Micron eventually concluded that EUV was worth using. Its newer 1-gamma DRAM process uses EUV lithography, with Micron saying the technology helps it achieve more than 30% greater bit density per wafer than its preceding 1-beta generation.

EUV is hardly a magic wand, either. Mack points to stochastic effects – tiny random variations caused by the small number of photons involved in an exposure – which mean manufacturers can improve pattern control by increasing the EUV exposure dose. But it also pushes the cost back up quickly.

Because of that, Mack believes there is ultimately a limit to how far multiple patterning can economically substitute for EUV. “I would be hard pressed to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV,” he said.

That doesn’t mean Chinese chipmakers simply hit a technological wall and stop. They can keep pushing DUV while accepting larger dies, poorer yields, longer manufacturing times – or some combination of all three.

They can also throw capacity and money at part of the problem. Morgan Stanley assumes CXMT remains stuck on its 1-alpha process without EUV, yet still increases its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 simply by building more greenfield capacity. The bank also expects China’s AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030 through new advanced-node capacity, improving yields and heavy state support – while EUV, HBM and advanced software leave a persistent gap. And so without EUV, the experts reckon China can only get partway to bridging the gap with the West. ““I would be hard pressed,” said Mack, “to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV.”

TSMC, the world's largest contract chip manufacturer, is seeking alternative machinery without rare-earth components to reduce its dependence on China-dominated materials and avoid disruptions to factory operations caused by the country's export controls. According to a Reuters report on October 22 citing people familiar with the matter, the Taiwanese company has begun approaching its equipment suppliers to explore whether they can provide factory automation equipment equipped with motors that don't require rare-earth materials.

TSMC supplies the extremely powerful Nvidia chips that are facilitating the AI boom. It also manufactures chips for Apple, Broadcom, Qualcomm, and numerous other tech and automotive companies. The company operates enormous, highly automated semiconductor fabrication plants. These factories use industrial machinery that relies on electric motors with powerful permanent magnets made from rare-earth elements such as neodymium, dysprosium, and terbium.

According to the U.S. Geological Survey (USGS), China accounts for roughly 70% of global rare earth mining. The International Energy Agency (IEA) says China also controls around 90% of refining and approximately 95% of the finished permanent magnets found in TSMC’s machines, giving Beijing a quasi-absolute monopoly over one of the most critical technology supply chains. In April 2025, the country placed seven medium and heavy rare earths and the magnets made from them under export controls, requiring exporters to seek case-by-case approval and export licenses, thereby choking shipments to manufacturers across the U.S., Europe, and Asia, including TSMC.

China expanded the controls on October 9, 2025, to include five additional rare earths, processing technology and equipment, and even products manufactured outside the country that contain more than 0.1% Chinese-origin rare earths, or are made using Chinese processing technology. It later suspended the October expansion for one year, until November 10, 2026. This has now been extended for an additional 90 days.

TSMC’s moves aim to reduce the risk that these controls will hinder production at its factories. Even with all other raw materials and machinery required to manufacture its chips, shortages of specialized motor components could complicate the maintenance, repair, or expansion of its production equipment. Several technological approaches allow motors to avoid rare earth magnets. Conventional induction motors, for example, generate torque using electromagnetic induction rather than permanent magnets. Switched-reluctance motors are another option, while some permanent-magnet motors can use ferrite magnets instead of rare-earth magnets. However, these technologies typically involve different trade-offs in efficiency, size, power density, precision, and control requirements.

Meanwhile, the rest of the world is undertaking the painstaking, drawn-out task of building a rare-earth supply chain outside China. Taiwan is reportedly pursuing domestic rare-earth production capabilities in collaboration with the United States, with both countries confirming their intent to reduce reliance on Chinese rare-earth and critical-mineral supply chains.

Taiwan's government is supporting the Industrial Technology Research Institute (ITRI) in establishing a pilot production line within three years that could supply about 50% of Taiwan's domestic rare-earth demand. Meanwhile, the U.S. is “working with Taiwan and other partners to develop alternative sources of supply, expand processing capacity and build more resilient supply chains,” according to the report. In February 2026, the Trump administration announced plans to create a $12 billion critical minerals stockpile to offset supply chain risks from China.

Intel on Wednesday announced that it had started installing production tools at its Fab 62 in Arizona, and the fab is on track for mass production by late 2028. The company also reported progress on its Ohio One manufacturing complex and confirmed that it has integrated High-NA EUV lithography into high-volume manufacturing (HVM). Meanwhile, Intel continues to invest in its leading-edge process technology R&D, advanced packaging, and photomask production capabilities in the U.S., which puts the company ahead of the competition.

"There is an important difference between technologies made in America and technologies that are truly American-made," wrote Naga Chandrasekaran, executive vice president and chief technology and operations officer, Intel Foundry. "The difference lies in the research and development process that transforms ideas into manufacturable technologies."

Fab 62 to begin operations in 2028

Intel completed construction of its Fab 62 shell some time ago; now it is time for the company to begin installing production tools, which is what it is doing now. Intel expects the new facility to become operational before the end of 2028, although it has not disclosed when it intends to begin high-volume production or which nodes it will produce.

Intel has not officially assigned Intel 14A to Fab 62, although the facility has been discussed as a potential manufacturing site for the node. Meanwhile, there is an important distinction between Intel's original plans for Fab 62 and its current commitments. When Intel announced Fab 52 and Fab 62 in Arizona, it said the two facilities would manufacture its most advanced process technologies, including Intel 20A (2nm-class) and 18A (1.8nm-class). Intel subsequently designated Fab 52 for Intel 18A manufacturing. Yet, Fab 62 remains unassigned.

Given Intel's manufacturing process roadmap disclosed earlier this year, Fab 62 will be able to make chips on 18A, 18A-P, and 14A nodes. Intel currently manufactures Intel 18A chips at the neighboring Fab 52, whereas Fab 62 could potentially accommodate either additional Intel 18A capacity or the company’s next-generation Intel 14A process technology. However, Intel has yet to confirm its plans for the facility.

The facility will become Intel's Fab 62, the sixth high-volume semiconductor manufacturing fab at its Ocotillo campus, which has served as one of the company’s primary production sites for decades.

Intel has also not revealed Fab 62's planned wafer processing capacity, or the amount of capital expenditures required to complete the facility. Nevertheless, the installation of production equipment indicates that the project has progressed beyond construction of the building itself. The new fab will expand Intel’s manufacturing footprint in Arizona, where the company already produces leading-edge processors and operates advanced packaging, assembly, and testing facilities.

Intel confirms High-NA EUV insertion into mass production

Another noteworthy disclosure concerns Intel's deployment of High-NA EUV lithography. Intel was the first chipmaker to install a commercial High-NA EUV scanner at its D1X fab near Hillsboro, Oregon, and subsequently integrated the tool into high-volume manufacturing to produce its Panther Lake and other chips.

The Gordon Moore Park at Ronler Acres in Oregon is where Intel develops its most advanced logic process technologies and initiates volume production of the latest processors. Usage of High-NA EUV to produce select tiles for Panther Lake CPUs at D1X is a natural fit for the development fab, as it helps Intel to better understand how these lithography systems work. Meanwhile, it seems (though Intel has not explicitly confirmed) that, for now, High-NA EUV scanners are used to produce the same circuits as Low-NA EUV machines, so the use of next-generation lithography systems does not necessarily provide significant advantages over existing litho scanners.

Ohio One reaches another construction milestone

Intel has also made progress with its 'Ohio One' manufacturing complex in New Albany, Ohio. Construction workers recently installed the first major structural truss at the site's first semiconductor fab, which represents a milestone in the development of the company's manufacturing operations in the state. The project is clearly an important part of Intel's long-term strategy to expand domestic production of chips using leading-edge process technologies for years to come.

Unfortunately, Intel did not provide an updated construction schedule for Ohio One or disclose when the first fab is expected to begin operations. Intel also did not reveal which process technology the facility will eventually use or the estimated manufacturing capacity it will provide. Therefore, while construction continues, which is good news, the announcement does not clarify exactly when Ohio One will contribute to Intel's output.

Other investments across the U.S.

In addition to leading-edge manufacturing capacity in the U.S., Intel continues to invest in advanced packaging technologies. Oregon serves as the company's main research and development center for advanced logic and 3D interconnect technologies, while Arizona hosts advanced packaging R&D, assembly, and testing operations. Intel uses its site in New Mexico to produce its complex multi-chiplet processors relying on advanced packaging methods — starting with modest EMIB and all the way to next-generation EMIB-T and Foveros technologies.

Also, Intel recently broke ground on a new photomask manufacturing facility in Santa Clara, California. The new facility will be an important part of Intel's supply chain in the U.S., as the company will be the only chipmaker in America to develop and produce chips using leading-edge nodes completely in the U.S. (both Samsung and TSMC currently lack leading-edge process R&D in America; they do not run their own photomask shops in the U.S., and Samsung has abandoned its plan to build an advanced packaging facility in Texas). Of course, Intel critically depends on tools from Europe and materials from Japan, but even as its major rivals invest hundreds of billions in their U.S. production capacity, Intel remains ahead.

To highlight its American supply chain, Intel disclosed that its U.S. operations involve more than 4,500 suppliers across 49 states, as its annual domestic expenditures exceed $29 billion. The company stressed that domestic semiconductor leadership requires not only wafer fabrication capacity but also research, process development, advanced packaging, and a comprehensive supply chain.

Elon Musk says ASML and other critical semiconductor equipment suppliers have expedited shipments for the ambitious Terafab semiconductor manufacturing facility, supporting his aggressive timeline for the joint megaproject between Tesla and SpaceX. He made the announcement during a live broadcast of SpaceX's Q3 2026 earnings call on X yesterday, October 20. Musk also said the company is targeting volume chip production at the project's primary facility in Gibbons Creek, Texas, by the third or fourth quarter of 2028, emphasizing that the timeline is highly aspirational and carries "big error bars."

"These are very aggressive dates, and we're very appreciative of ASML and all of our other suppliers in accelerating equipment deliveries in order to achieve this outcome," said Musk, CEO of both companies behind Terafab. SpaceX plans to manufacture its first experimental test chip at its research fabrication facility in Austin, Texas, around Q2 2027.

Aside from Terafab, Musk also outlined near-term ambitions for his AI companies during the broadcast, saying he expects them to have 2.5 to 3 gigawatts (GW) of computing capacity active by the end of 2026. He also stated he is highly confident about bringing an incremental 10 GW online in 2027, saying he "would be surprised" if they do not hit a total of 13 GW of AI compute by the end of 2027.

Meanwhile, the next-largest project by planned capacity, the now-restructured 10 GW Project Stargate, was expected to reach full capacity in the 2030s. Meta's 5 GW Hyperion also has a similar timeline. To achieve the 13 GW milestone, Musk revealed that SpaceX and xAI are aggressively procuring upcoming next-generation NVIDIA architecture. He announced plans to get a massive 440,000-GPU Nvidia "Vera Rubin" training cluster online by the end of Q2 2027.

Shifting back to Terafab, Musk also boasted that once fully scaled and operational, the sheer commercial value of Terafab's advanced chip output will place it within the top 20 global country GDPs from a single physical building. For context, the 20th country on the list is Switzerland, with a GDP of around $1.14 trillion. The facility is a planned multi-billion-dollar, vertically integrated chip factory in Texas, with an ambitious goal of manufacturing 1 terawatt (TW) of AI computing power per year. Terafab will fabricate logic, memory, and advanced packaging internal architectures in one place. The project's massive planned output has mandated various collaborations across the semiconductor supply chain. Terafab will utilize traditional extreme ultraviolet (EUV) lithography systems utilizing Intel's 14A manufacturing node technology.

Intel officially joined the Terafab venture in April 2026 to help co-develop and refactor silicon fabrication technology, providing access to its state-of-the-art 14A manufacturing process. ASML, the world's sole commercial supplier of the $400 million EUV lithography systems required for high-volume, leading-edge chip production, is perhaps the project's most critical partner. Terafab's first EUV tool was reportedly slated for delivery in mid-2027, according to unofficial sources. It remains unclear if this is the expedited timeline Musk referred to in the broadcast.

Other major suppliers include American equipment manufacturers Applied Materials, Lam Research, and KLA Corporation, as well as Japan's Tokyo Electron. These companies will provide front-end processing, metrology, and process control machinery. Tesla and SpaceX are also in talks with about 10 South Korean equipment makers, including Hanmi Semiconductor, known for advanced packaging equipment, and HPSP, a high-pressure hydrogen annealing equipment manufacturer, as well as firms providing specialized piping components and process valves.

Musk's announcement says that several of these suppliers are expediting supply to Terafab, even as capacity remains tight across the semiconductor supply chain. The facility, which aims to mitigate future shortfalls of cutting-edge AI processors from external foundries like TSMC, will supply the chips for Musk's xAI clusters, self-driving vehicles, Optimus humanoid robots, and SpaceX's orbital AI data center, as well as the broader AI industry.

However, many experts have questioned the validity of Musk's 1 TW Terafab ambition. For context, research firm Gartner estimates the total global AI-optimized data center capacity is roughly 44 GW as of late 2026, 4.4% of Terafab's planned output. Although global AI computing capacity has grown by roughly 3.3x to 3.4x per year since 2022, according to EpochAI.

Three contract workers died, and one more is in intensive care after an accident at the construction site for TSMC’s 2nm Fab 22 in Kaohsiung, Taiwan, reports Taiwan’s Central News Agency. The Southern Taiwan Science Park (STSP) Bureau suspects the cause was a broken bolt on a steel connection plate that sent the workers and steel components tumbling. Steel hoisting on the project has been halted, and the STSP has sent labor inspectors to investigate. The accident is not the first of its kind but rather follows at least a half dozen others since September 2024 at TSMC construction sites in Taiwan, according to local reports. Each of those earlier accidents killed one worker.

Local police said that the men were welding a steel beam on an upper floor and fell with it, while the STSP said the workers were performing steel-structure hoisting and installation when a third-floor connection-plate bolt apparently broke.

10 emergency vehicles were sent to the site with 22 personnel, and all four men involved in the incident were taken to the hospital. On-site medical staff gave first aid, but three of the workers died despite resuscitation efforts, and the fourth was moved to intensive care. The workers were employed by a contractor working on the fourth phase of the complex’s construction, and TSMC said the area was within that contractor’s scope of work.

According to the report, TSMC stopped the related construction work on its own and is working with authorities and supervising the subcontractor’s follow-up.

The Fab 22 complex, located in Kaohsiung’s Nanzi District, is part of the science park and is being built to accelerate 2nm manufacturing. TSMC entered high-volume 2nm, or N2, manufacturing in the fourth quarter of 2025, including at Fab 22. The complex has five phases planned, with a total investment TSMC puts at more than NT$1.5 trillion, or about $46 billion. The accident happened on the construction side, not in a producing fab. Kaohsiung’s deputy mayor said construction on Phase 4 began in August 2025, with operations expected in the fourth quarter of 2027.

Business Today reports that TSMC fab construction has increased, from four fabs a year in 2017–2024 to nine a year in 2025 and 2026. The deaths come as the company plans for 13 new leading-edge and advanced-packaging fabs in Taiwan, with company-wide capex of $60 billion to $64 billion this year.

The faster pace has encouraged the addition of a contractor’s safety record as a weight in selection and a plan for a Taiwan Semiconductor Construction Engineering Safety Association with construction partners. TSMC Chairman C.C. Wei said at last year’s shareholders meeting that safety cannot be compromised, and the company’s 2025 annual report said it will keep investing in fabs across several locations in Taiwan “with a strong emphasis on construction site safety.”

Cliff Hou, TSMC senior vice president and deputy co-COO, told Business Today that increased worker count and overlapping construction have raised the risk, requiring careful supervision, and that TSMC’s contractor lost-time injury rate had fallen about 42% from last year’s high as of late May, when the publication toured the Nanzi site to see the overhaul. It’s too early to call the program a failure, with the cause as yet unknown.

The accident comes less than a week after an explosion killed two people at Intel’s chip plant in Israel, though that was an operating fab rather than a construction site. Both accidents come as chipmakers race to meet demand, with global chip sales passing $1 trillion through August, according to the Semiconductor Industry Association.

The STSP’s findings will determine what penalties, if any, will fall under Taiwan’s Occupational Safety and Health Act, while it assists the victims’ families. No date has been given at this time for that or for the Phase 4 steel hoisting restart. Nor has TSMC commented on any schedule impact.

Intel has asked the Federal Communications Commission (FCC) to make an exception for the automated guided vehicles (AGVs) that the company uses to transport the sensitive silicon wafers and other materials, containers, and supplies needed to make the most advanced chips in its fabs. According to Bloomberg, the American chipmaker fears that its AGVs would fall under the blanket prohibition against foreign-made robots after they were added to the FCC’s Covered List.

AGVs are niche machines that chip fabs use to transport materials and supplies between tools and sections of the fab, helping ensure that the cleanroom conditions required for each manufacturing process are maintained. This makes them critical equipment for U.S. semiconductor manufacturing, but, apparently, there are no suitable domestic alternatives for these devices at the moment. Intel’s current fleet of AGVs requires continuous maintenance, including software and firmware updates, and if it’s forced to find a local supplier for its AGVs, the company says that it would take years, crippling the United States’ chipmaking efforts.

The biggest AGV suppliers are Japanese companies like Murata Machinery and Daifuku Co., while a few smaller businesses from South Korea and Taiwan are also trying to break into the market. It’s unclear why these companies haven’t applied for a conditional approval yet, which would allow them to continue selling these products in the U.S. while also promising Washington that they’ll set up a manufacturing base in the country. This is something that Netgear has already done, allowing it to continue selling its foreign-made routers despite being an American company.

Intel says that it remains unclear if updates to its AGVs would break compliance with the FCC, and that it’s asking the agency to issue a conditional waiver “out of an abundance of caution to ensure the ongoing operation of these specific AGV units.” While Team Blue is the only company concerned about AGVs at the moment, other chip manufacturers would likely need a similar waiver in the near future, especially as they build more fabs in the U.S. This includes TSMC, which is planning to build 12 more fabs and four packaging facilities in Arizona, Samsung, with its new Taylor, Texas, fab, and even Elon Musk’s Terafab, which has already begun construction.

Washington has been using the FCC to force companies to invest in American manufacturing. Its blanket bans on foreign-made products like drones and routers have affected some of the biggest brands in the U.S., including DJI and TP-Link. While these bans do not outright ban the sale of all products made by these companies, especially those that have already been approved before, they make it impossible for them to introduce new products and even release software updates to their existing product line. The FCC eventually walked back on the software update ban, but they still would not be able to register new products unless they build them in the U.S.

Taiwan is expanding its list of controlled exports to include AI servers and the latest chips in a move to align its policies with the U.S.’s trade bans. Bloomberg reports that after the export controls take effect, anyone caught smuggling these items will be criminally charged under the Foreign Trade Act, which carries a penalty of up to five years in prison and/or a fine of around $92,500.

“Going forward, some of our measures on controlled items will correspond to American ones because we have made quite some commitments in the Agreement on Reciprocal Trade,” Taiwan Minister of Economic Affairs Kung Ming-hsin said. The two parties signed the trade deal earlier this year, which saw the U.S. cutting tariffs on Taiwanese goods down to 15% in exchange for direct investments in the U.S. tech industry, among others.

The U.S. has long been trying to stamp out the smuggling of advanced Nvidia chips into China. One of the biggest cases that U.S. authorities have prosecuted so far includes three Super Micro employees, including its co-founder Yih-Shyan “Wally” Liaw, who are accused of smuggling $2.5 billion worth of AI servers. A few months after this revelation, Taiwanese authorities raided Super Micro’s Taipei offices in connection with the Nvidia B300 smuggling probe, which eventually led to the indictment of nine individuals related to the case.

Since Taiwan doesn’t treat AI chip exports to China as a crime before this new set of export controls is enacted, people violating the chip bans would have to be charged under other laws. This is what Singapore did when it arrested suspected Nvidia AI GPU smugglers — because it doesn’t have a law that prohibits the export of advanced AI chips to China, it instead charged the individuals with fraud and money laundering.

The expansion of the Foreign Trade Act will be one of the strictest measures that the Taiwanese government has put into place against exports to China, which is something that it has been considering earlier this year. This move will likely please Washington as it pressures other countries to take more steps in its controlling the flow of advanced AI chips into China. However, it will also likely provoke Beijing, which has already condemned Taipei after it applied export restrictions on Huawei and SMIC last year.

Being unable to procure EUV litho tools from ASML, China must develop such systems locally, so from time to time we learn about an EUV-related 'breakthrough' in China that will turn into an actual EUV scanner over the following several years. This week, Chinese startup Langdao Silex demonstrated a prototype extreme ultraviolet (EUV) light source with over 15W of output power, 90% domestic components, and decent uptime. The company will need another three to five years to commercialize its technology, reports TrendForce, citing various sources. Yet, a light source alone does not make an EUV scanner.

An LPP EUV source from China

Langdao Silex, which was established in 2024 by Tsinghua University's Gas Discharge Plasma Laboratory alumni, demonstrated its EUV light source prototype at the 26^th China International Industry Fair in Shanghai, for obvious reasons, without lighting it up. Just like modern light sources from ASML, the company's low-power FlintNano LPP-OXXO system uses laser-produced plasma (LPP) technology that produces EUV radiation by bombarding tiny heated metal droplets with high-energy laser pulses to create extremely hot plasma. The system features a 1,000W driving laser (presumably a CO₂ one) with an operating frequency of 1 kHz – 20 kHz and conversion efficiency exceeding 2%. Its EUV output exceeds 15W (presumably measured at the plasma rather than at intermediate focus, as the company has not demonstrated a complete EUV collection system) while its brightness reaches 100 W/(mm²·sr). The source has an étendue of 1 × 10⁻³ mm²·sr and generates plasma with a diameter of 60 μm.

According to Langdao's specifications, the FlintNano LPP-OXXO can operate continuously for over 100 hours with plasma stability of 3% RMS and EUV output power stability of 5%. These characteristics make the system suitable for semiconductor exposure experiments, although its output remains insufficient for high-volume chip production. Meanwhile, the 'over 100 hours' availability is very impressive for a pre-production light source, though we must admit that there is no way to verify the claim.

Langdao is also developing the FlintMicro-LPP high-power EUV source, which has completed proof-of-principle validation, according to reports. However, Langdao has not disclosed its output power, conversion efficiency, or operating lifetime.

On paper, Langdao's EUV source is comparable in output to some of the earliest EUV sources developed by Western and Japanese equipment makers, albeit with a major caveat: Langdao seems to measure EUV power at the plasma rather than after the collector or at intermediate focus as ASML does. ASML's early EUV demonstration equipment used approximately 10W at intermediate focus DPP sources in 2007, while Cymer's LPP sources installed in early NXE:3100 systems delivered up to 11W during wafer exposure in 2012 (note that ASML's machines are source agnostic, so some NXE:3100 prototypes used DPP sources, while others used LPP sources). By 2013, Cymer demonstrated approximately 40W at intermediate focus over extended operating periods. Meanwhile, Japan's Gigaphoton targeted 25W with its first prototype in 2013 and demonstrated 43W in early 2014. By late 2014, Gigaphoton had achieved 118W during a 10-minute test. However, since these historical figures involve different measurement conditions and operating durations, direct comparisons are vastly inaccurate.

Not quite there

Langdao Silex has not demonstrated its EUV light source in action, so all we know about it comes from the company itself. As noted, 15W power looks comparable to early EUV sources developed by Philips Extreme UV (DPP) and Cymer (LPP). Meanwhile, early NXE:3400-series machines came with 125W – 150W at intermediate focus sources, which was far from enough for high-volume manufacturing (HVM).

Modern EUV lithography equipment comes with considerably more powerful sources. ASML introduced 250W-class EUV sources for commercial production in 2018 – 2019 and has since achieved substantially higher output levels. Increasing output requires more powerful CO₂ lasers, highly accurate tin-droplet generators, effective debris mitigation, durable collector mirrors, and considerably better long-term reliability.

Langdao claims that 90% of its prototype's components are domestically sourced and that most critical parts were developed in China. However, the company has not explained whether the localization figure reflects component count, value, or another metric. Furthermore, its representatives reportedly acknowledged that increasing EUV output and improving long-term operational stability are the targets to be achieved in a bid to commercialize the source.

Not an EUV scanner

Yet, even without complete EUV scanners, Langdao's source could support EUV photoresist development, mask inspection research, development of EUV collection and illumination optics, and eventually experimental exposure testing.

Developing a complete EUV lithography scanner will require further advances in EUV collection and illumination systems, high-precision multilayer mirrors, wafer and reticle stages, overlay accuracy, and system integration. Meanwhile, all of these devices require a separate supply chain that hardly exists in China today.

Therefore, even if Langdao successfully develops its EUV source and increases its output to levels suitable for high-volume manufacturing, this would not necessarily mean that China could manufacture its own EUV lithography machines any time soon. Moreover, while Langdao's progress is impressive, it took ASML/Cymer approximately six years to increase the output of its LPP EUV source from 11W to 125W – 150W at intermediate focus, so there is no way that Langdao's LPP source could be used for anything beyond development tools in the next three to five years.

Meanwhile, Langdao has not disclosed where its reported 15W of EUV output is measured. If this figure represents radiation generated at the plasma rather than power delivered at intermediate focus, the source's usable output would be considerably lower than 15W when measured according to industry-standard practices. That said, it does not look like China got significantly closer to building its own EUV lithography scanners with the current announcement.

Taiwan is raising at least $4 billion through the Taiwan Electrical and Electronic Manufacturers’ Association to build an industrial park in Texas. According to Bloomberg, the site is designed to support the countless smaller manufacturers that major manufacturers like TSMC and Foxconn rely on.

“We are going to establish a long-term, sustainable supply chain there that can also be joined by American firms and local workers, and not just Taiwanese companies,” Taiwan Minister of Economic Affairs Kung Ming-hsin said.

Major Taiwanese companies are more than capable of spending the billions of dollars needed to set up shop in the U.S. TSMC, for example, has already spent $165 billion to put up its Arizona site, and has committed a further $100 billion to build four more 2nm fabs. However, they also rely on several smaller manufacturers that do not have the financial capability to expand operations into the U.S. independently. Nvidia CEO Jensen Huang has even recognized some of these companies in a keynote in Taipei earlier this year, nothing the crucial part that these smaller companies play in the global AI supply chain.

Support for these businesses will not be limited to the planned industrial park, too. The Taiwanese government said that it will also offer loan guarantees to the companies that want to operate on the land, plus support them in communicating with local and federal U.S. officials regarding visas, permits, and other documentation.

Taiwan has reportedly secured a piece of land in Texas specifically for this project, but the Ministry of Economic Affairs didn’t give out any details yet, saying that it will elaborate on the project later. It’s also not limiting itself to a single industrial park, with the government saying that it’s planning for “more than one” site that would cost between $2 billion and $4 billion.

While the U.S. government hasn’t commented on Taiwan’s industrial park plan, the planned $4-billion investment would follow the “Taiwan model” that would help its companies invest in America easily and shorten the AI semiconductor supply chain that relies on Taiwanese industry. But even though these companies are primarily focused on meeting the needs of Taiwanese giants like TSMC, Foxconn, and Wistron, American companies are also welcome to work with them. Kung even said that Elon Musk’s Terafab can take advantage of this prospective supply chain, although he also said that they will not transfer their technologies so that he could integrate them vertically.

The EU is currently in talks with China to lift restrictions the country imposed on Sindlhauser Materials GmbH, a German company in ASML’s supply chain, as the sanctions risk putting the company out of business. In return, the EU would remove restrictions it placed on one unnamed Chinese firm accused of aiding Russia in the war with Ukraine, according to an Oct. 14 Bloomberg report citing people familiar with the matter.

The deal was discussed during EU Commissioner for Trade and Economic Security Maroš Šefčovič’s visit to Beijing. The EU is expected to make the first move, with any delisting on its end requiring unanimous support from member states. Both sides also agreed to share more information and give advance warning on future export restrictions.

In July 2026, China put Sindlhauser, a German precision-manufacturing and advanced-coatings firm, on its export-control list, along with 13 other European companies, in apparent retaliation for the EU’s 21st Russia sanctions package, which sanctioned several Chinese firms accused of supplying Moscow with components that can be used to make weapons. Beijing’s official reason was the firms’ alleged dealings with Taiwan.

China’s selection of Sindlhauser is not random, as the company sits in ASML’s supply chain. According to Bloomberg, officials believe Beijing has spent the last year and a half gathering information on Western supply chains, and used the data to identify the seemingly obscure German firm as a pressure point on the world’s most important chipmaking-equipment company.

Sindlhauser relies almost entirely on Chinese rare earths and critical minerals. Therefore, the restrictions, which ban Chinese exporters from selling dual-use items to the firm, cut off its main source of input. They also prohibit foreign companies and individuals from passing on China-origin dual-use items to the firm, thus preventing Sindlhauser from simply sourcing the same materials through a third-party distributor.

After the listing, which initially sparked panic over the company’s survival, the German government and Bavaria’s state government stepped in, helping the company explore workarounds such as alternative suppliers and recycling existing materials. However, due to its heavy dependence on China, Sindlhauser now faces the risk of going out of business in the coming months if the sanctions remain.

EU officials in Brussels had been raising the case with Beijing for weeks, culminating in the delisting swap discussed during Šefčovič’s visit. The incident highlights China’s influence on several aspects of the global technology supply chain, including semiconductor manufacturing, which is critical to the AI boom. The country placed export restrictions on several rare earth metals, limiting their availability across the supply chain. Meanwhile, the West has been investing heavily in domestic supply chains to reduce reliance on China.

ASML this week reported record quarterly revenue of $13.06 billion (€11.66 billion) and profitability of nearly $5.79 billion (€5 billion) as demand for advanced semiconductor manufacturing equipment continues to accelerate and investments in AI infrastructure continue to increase. The company now expects demand for its lithography systems to exceed its production capacity in 2027 and 2028, despite plans to increase output substantially. Some clients are already interested in placing orders for equipment as far ahead as 2030, which makes ASML consider further capacity expansions beyond its previously announced intentions.

Record financial results

ASML reported third-quarter 2026 revenue of $13.06 billion USD (€11.66 billion), up 55% year-over-year and 25% sequentially. The company's gross margin reached a record 57.5%, up from 51.6% a year earlier, while operating income rose to $5.79 billion (€5.17 billion). Net income reached $5.56 billion USD (€4.96 billion) , although this figure includes approximately $570 million (€510 million) from the re-evaluation of the company's investment in Mistral AI.

During the quarter, ASML sold 121 lithography systems, including 113 new and eight refurbished machines, up from 91 systems in Q2 2026. The company generated $4.59 billion USD (€4.1 billion) from 17 EUV lithography systems and $4.82 billion USD (€4.3 billion) from 85 DUV (including 45 ArFi scanners) and 19 i-line litho tools. In addition, ASML recognized revenue from one High-NA EUV system in Q2. Of total equipment revenue, 54% came from logic chipmakers and 46% from memory manufacturers.

Taiwan accounted for 32% of ASML's equipment sales in Q3 2026, followed closely by South Korea at 31%. China represented another 23%, while the United States accounted for 13% and the rest of Asia contributed just 1%. Combined, Taiwan and South Korea generated 63% of ASML's equipment revenue, which reflects substantial investments in advanced logic and memory manufacturing capacity that by far exceed those in the U.S. and Japan.

ASML’s Installed Base Management business generated $3.68 billion (€3.29 billion), approximately $450 million (€400 million) above guidance, largely due to strong demand for productivity upgrades (more on this later), which contributed to the company’s record profitability.

For the fourth quarter, ASML expects revenue of $15.9 billion to $17.0 billion (€14.2 billion to €15.2 billion) and gross margin of approximately 57%. Full-year revenue should reach $49.3 billion to $50.4 billion (€44 billion to €45 billion), up approximately 36% YoY. The company projects EUV revenue should increase by more than 45% year-over-year, while memory-related equipment sales are expected to rise by approximately 75%, which indicates growing demand from DRAM producers.

Demand for litho tools spans to 2030

One of the biggest learnings from these results and accompanying statements is that semiconductor manufacturers are increasingly interested in securing lithography equipment years before they actually need it. According to ASML CEO Christophe Fouquet, customers expect demand for its products to exceed available supply through at least 2028, which encourages them to accelerate construction of new fabs as well as expand their existing capacity.

"Our leading-edge high-volume customers are sharing very good visibility as a result of the increasing number of long-term commitments they are securing with their customers," Fouquet said during the company's conference call with analysts and investors. "This extended visibility has led them to conclude that demand for their products will outpace supply through at least 2028. As a result, customers are accelerating capacity build-out plans and preparing for further expansion beyond 2028 in order to better meet the anticipated level of demand."

ASML is already receiving orders that are to be delivered in 2028, while some customers have expressed interest in equipment for 2029 and even 2030.

"As customers shift focus to their needs beyond 2027, our order momentum continues to build," Fouquet added. "We are increasingly receiving orders for 2028, and customers are also expressing interest in placing orders for 2029 and even 2030."

To address this demand, ASML plans to manufacture approximately 65 Low-NA EUV systems in 2026, up from 44 scanners shipped in 2025. Production of immersion DUV systems should remain approximately at last year's level, even though proveiously the company expected shipments of DUV tools to decline.

The company previously announced plans to increase production capacity for both Low-NA EUV and immersion DUV systems by 30% in 2027, followed by another potential 30% increase in 2028. Based on its 2026 EUV production target, this implies capacity for approximately 85 Low-NA EUV systems in 2027 and roughly 110 in 2028, assuming both increases materialize.

However, ASML now believes even this level of output will be insufficient and is investigating ways to expand its 2028 capacity beyond the previously planned 30% increase. However, the company has not disclosed revised production targets.

"Looking further ahead, we shared our intent last quarter to increase our capacity in 2027 by 30% for both Low NA EUV and DUV immersion systems, as well as to investigate adding a further 30% in 2028," explained Roger Dassen, Chief Financial Officer at ASML. "However, given the dynamics of this quarter, we now anticipate that our current planned levels of output in 2027 and 2028 will not fully meet the demand of our customers."

High-NA EUV adoption

Meanwhile, High-NA EUV adoption is progressing. Intel has already exposed more than one million wafers using High-NA systems and plans to start using High-NA EUV with its 14A process technology in 2028. Samsung plans to introduce High-NA EUV into high-volume manufacturing (HVM) in 2028 for DRAM and for logic later, while TSMC plans to use High-NA EUV scanners by 2030 – 2031. ASML says availability across its installed High-NA fleet is approaching 90%, which suggests that the tools are becoming mature enough for HVM deployment.

Interestingly, Samsung's planned 2028 introduction may create additional demand for High-NA equipment from memory manufacturers, as they will need to compete against their larger rival. However, ASML has not disclosed specific shipment targets for these tools.

New tools, more capacity

ASML also intends to increase semiconductor production capacity by introducing more productive lithography systems. Its upcoming Twinscan NXE:3800F, scheduled for introduction in early 2027, will process up to 260 wafers per hour, compared with 230 wafers per hour for the existing NXE:3800E. While this represents 'only' approximately 13% higher throughput, this translates to 21,600 extra EUV exposures per month without corresponding increases in cleanroom space. Three such tools per fab enable 90 additional EUV exposures per hour, 2,160 per day, or 64,800 per month. The company also plans to introduce a new critical-layer immersion DUV system capable of processing 330 wafers per hour.

Keep in mind that the actual fab capacity improvements depend on the number of lithography exposures required per wafer on a particular node, as well as the capabilities of other manufacturing equipment.

Another important element of ASML's strategy is its growing portfolio of productivity upgrade packages for existing EUV and DUV systems. Such upgrades enable chipmakers to increase wafer throughput without purchasing additional scanners, which can provide additional capacity considerably faster than procuring new tools or constructing new fabs.

Value-based pricing is a go

One of the controversial things that ASML discussed back in early Q2 was its value-based pricing, which many thought was a blanket price hike. This is not and CFO Roger Dassen this week confirmed that negotiations with major customers have been completed, although the financial benefits for ASML will not become visible immediately.

The company expects the first effects of higher pricing to appear during 2027, with the full impact becoming apparent in 2028 and beyond, which essentially means that the company is not setting new prices on its backlog, but generally setting new prices on new tools.

"We completed those conversations," said Dassen. "So that has been done with the key customers. The effect of that is not really visible in 2026. It will start to become visible partly in the course of 2027. The full impact of that you will start to see in 2028 and beyond."

This strategy could further improve ASML's already substantial gross margins, particularly as customers have no alternatives for advanced lithography equipment.

China remains important

Despite export restrictions that prevent Chinese chipmakers from acquiring EUV scanners and advanced DUV systems, China remains a substantial market for ASML. The company expects China to account for approximately 20% of its total revenue in 2026, which implies annual sales of roughly €8.8 billion to €9 billion based on current guidance.

Although China's share of ASML's business has declined from its levels in 2023 - 2025, the country's semiconductor manufacturers continue to invest in mature node capacity and equipment that remains available under existing export regulations. Meanwhile, it is impossible to predict what is going to happen if the U.S. lawmakers approve the MATCH Act.

Yet, ASML management emphasizes that its key growth opportunities lie with advanced logic and memory manufacturers, which are accelerating their investment in advanced lithography tools, including sophisticated DUV systems, Low-NA EUV machines, and High-NA EUV scanners.

The future of ASML

Thanks to gaining momentum in AI infrastructure investments, ASML reported record quarterly revenue of $13.06 billion (€11.7 billion) as demand for advanced lithography equipment continued to accelerate. The company expects demand to persist for years as its customers are interested in placing orders for tools to be delivered as far ahead as 2030. To meet growing demand, the company plans to expand production capacity beyond its previous targets for 2028. ASML also intends to introduce new EUV and DUV systems with higher productivity, offer productivity upgrades, and raise equipment prices to capitalize on unprecedented demand.

ASML has said that the unprecedented spending and investment brought about by the artificial intelligence (AI) boom is not slowing down at all, as customers are already lining up to place orders for its advanced chipmaking tools for 2029 and 2030, according to a Reuters report citing ASML's Q3 2026 earnings published today, October 14. ASML CEO Christophe Fouquet said that the company would struggle to meet the demand despite plans announced in July to raise capacity by 30% in 2027 and another 30% in 2028. The company also confirmed on Wednesday that it will raise prices starting in 2027, with the full effect showing in 2028.

The Dutch company's comments follow its Q3 2026 earnings report, which detailed a net profit of €4.96 billion on net sales of €11.7 billion. It projects Q4 sales of €14.2 billion to €15.2 billion ($15.9 billion to $17 billion), boosting its full-year sales projections from at least €43 billion to €44-45 billion. ASML's shares rose 2% on Wednesday, up almost 70% so far this year, with its €586 billion market valuation making it Europe's largest firm by market cap.

According to Reuters, there had been concerns that the AI investment boom was losing steam. However, positive projections from the largest manufacturer of the tools for making AI chips and advanced semiconductors signal that chipmakers will keep expanding, sustaining demand across the AI industry well into the foreseeable future. "There were concerns that the AI trade was running out of steam," Gordon Kerr, European macro strategist at KBRA, said. "Demand for chips remains strong, and infrastructure spending is likely to continue well into 2027."

ASML's customers include logic chip manufacturers such as Samsung, Intel, and TSMC, which manufactures chips for Nvidia, all of whom are heavily investing in increasing chip production. Memory chip makers SK Hynix and Micron ⁠have also announced expansion plans that involve ASML machines. Meanwhile, the company's CFO Roger Dassen said it is "still kicking the tires on the exact size of that (Terafab) opportunity," referring to Elon Musk's 100 million square feet semiconductor manufacturing facility that aims to output millions of logic and memory chips. Terafab will reportedly receive its first EUV chipmaking tool from ASML in mid-2027.

ASML's order book reflects a wave of spending across the AI industry. As of April this year, Google, Amazon, Microsoft, and Meta reportedly collectively planned to spend $725 billion on capex in 2026, up 77% from last year's record $410 billion. Since then, Alphabet has raised its 2026 capex guidance from $180–190 billion to $195–205 billion, Amazon from $200 billion to $220 billion, and Meta has raised the floor of its range from $125 billion to $130 billion, keeping its $145 billion ceiling. Some of the spending reflects rising chip prices, with Microsoft CFO Amy Hood attributing $25 billion of the company's record capex budget to higher prices for memory chips and other components. Still, analysts such as Gartner expect global AI spending to rise 49.5% in 2026 to $2.7 trillion and another 36.2% in 2027.

C.C. Wei, chief executive and chairman of TSMC, confirmed on Thursday that the company is considering expansion of its American production capacity beyond Arizona and Texas is one of the options it is evaluating. The head of the world's largest contract chipmaker also confirmed negotiations with Elon Musk regarding usage of Terafab, but stressed that to be a part of it, the fab must be managed by TSMC, which automatically excludes burgers and cigars in the cleanroom.

"We expanded our capacity consideration to see outside Arizona, whether we can get another chance to expand our capacity," said C.C. Wei during the company's earnings call with financial analysts and investors. "Texas is one [of our options]. We sent the teams to Texas to do all the evaluation.  We also talked to one of our customers, who is trying to build a fab, Terafab, let me be more specific."

Recently in transpired that Elon Musk's Terafab was in talks with TSMC over using the giant semiconductor production facility together. Elon Musk confirmed the negotiations, whereas TSMC did not comment.

"We are discussing with them to see whether we can be utilizing that actual capacity also," Wei added. "So, we are still in discussion. If we have any solid conclusion, we will share with you."

The information about negotiations between Elon Musk's Terafab and TSMC immediately triggered chatter that the parties are set to adopt TSMC's typical business model it uses for ESMC and JASM facilities under which it operates fabs co-owned with other investors. However, Musk then said that Terafab's facility would be operated by Terafab and TSMC could only sub-lease part of its cleanroom. Now, C.C. Wei said that if TSMC joins the project, it will insist on operating the fab.

"We are still in discussion," Wei replied when asked whether TSMC is not becoming a part of the Terafab project. "Let me say that. […] Either way, it will be possible, but the fab has to be run by TSMC."

The key question now is whether Musk and TSMC can agree on an arrangement that satisfies both parties. Musk wants Terafab to retain control of its manufacturing complex, whereas TSMC insists on operating any fab it uses. One potential compromise would be for Terafab to own the facility and lease a portion of it to TSMC, which would independently operate its production lines. Such an arrangement would allow Musk to retain ownership of the whole complex while giving TSMC control over select manufacturing lines. However, if Terafab itself uses Intel's 14A process technology at the facility, TSMC's presence there will be extremely complicated, if possible at all. In any case, so far the parties have not come to any agreement.

TSMC on Thursday reported revenue of $46.72 billion for the third quarter of 2026, up 41.2% year-over-year and 16.2% sequentially. The foundry's net income reached approximately $23.9 billion, an increase of 68.7% from the same quarter a year earlier, driven by elevated demand for chips used by AI infrastructure. The company's gross margin was 66.4%, which is below gross margins reported by DRAM makers, but still a historic record.

For the fourth quarter of 2026, TSMC expects revenue between $52.3 billion and $54.3 billion, which represents approximately 14% sequential growth at the midpoint. The company projects gross margin between 65% and 67%, up both sequentially and YoY.

Geopolitics and sanctions have mostly cut off the Russian public from Western hardware — at least officially. In recent ages, the country's homegrown chip designs are Arm, RISC-V, and Elbrus architectures. A handful of interesting designs were on display at the Microelectronics 26 (ME26) forum in Sochi, using retro gaming as a demonstration point. A couple of years back, the government even issued an order to create a high-end gaming console, albeit with relatively little success. The result of that initiative didn't appear to be on display at the event.

The report comes from Dmitrii Kuznetsov, a RISC-V and Rust enthusiast who displayed photos from the event. The first units on display use Baikal Electronics' BE-U1000 microcontroller. According to our digging, the chip packs a CPU with three CloudBear cores (32-bit RISC-V) — two BR-350s clocked at 200 MHz, along with a BM-310 at 100 MHz.

Given the microcontroller nature, embedded resources are intentionally sparse, with 256 KB of flash and 192 KB of SRAM — though there's support for external flash. A host of I/O interfaces, including USB 2.0, I2C, I2S, UARTs, and 48 GPIO lines, round out the 10x10 mm QFN-88 package. These parts are seemingly aimed at robotics, automation, IoT, sensors, and similar applications.

There was a business card-sized controller-and-console on display with a BE-U1000 chip, along with an "Ushka" console styled like the original NES (with matching controllers). The game on display appears to be Chip 'n Dale: Rescue Rangers.

Next up, there's the Elvis Hypercom-U, a SoC packing four Arm Cortex-A53 CPU cores at up to 1.2 GHz, dual ELcore-50 DSPs, a PowerVR GE8300 GPU, and dedicated video, image, and navigation processing blocks. The main silicon can be paired with up to 8 GB of LPDDR4, and supports USB 3.0, Gigabit Ethernet, Wi-Fi, and Bluetooth connectivity, and HDMI output.

This product is apparently aimed at multimedia, navigation, SBCs, and smart cameras. At the show, a board with the Hypercom-U was shown playing the original Super Mario as a demonstration.

Finally, there were MCST's Elbrus-based PCs, though the tweeter offered few details on which were on display. For context, Elbrus is a Russian-developed chip architecture, often poised as the basis for high-end desktop and server applications.

Our best guess is that the machines at the forum were based on the leading-edge Elbrus-16S chip with 16 cores at up to 2 GHz and up to 8 channels of DDR4-3200 RAM. The chip is manufactured on a 16 nm process and comprises 12 billion transistors. There are dual-processor server prototypes with up to 2TB of RAM using this design.

The other chip likely being demoed is the Elbrus-2S3, a chip targeted at mini-PCs and laptops. We've covered the Rostec MP21 previously, a Raspberry Pi-like machine with 8GB of RAM and SSDs up to 480GB. The 16-nm SoC is fairly decent, clocked at up to 2 GHz and capable of 196 GFLOPS. There's support for DDR4-3200 and PCIe 3.0, but power consumption can be fairly nasty, as the MP21 board can chew around 40W.

Two workers have been confirmed dead and another seriously injured after an explosion at Intel’s Kiryat Gat plant in southern Israel on Wednesday, The Times of Israel reports. Police suspect a gas cylinder malfunction caused the explosion, and Israel’s Fire and Rescue Services said the fire involved nitrogen trifluoride (NF3), a toxic gas mainly used to clean the process chambers of chipmaking tools. So far, Intel hasn’t made any statements about the victims or about any potential production impacts at the site.

The site houses Fab 28, which, per Intel, makes “processors, 5G, and AI products” on Intel 7, formerly 10nm Enhanced SuperFin. Intel 7 products include 13th and 14th Gen Core “Raptor Lake,” 5th Gen Xeon “Emerald Rapids,” and the I/O die of Xeon 6 “Granite Rapids,” although these are not explicitly linked to the site. Fab 38, adjacent to Intel’s existing Kiryat Gat fabs, was announced in December 2023 with a $3.25 billion Israeli grant but has been paused since mid-2024. Intel reportedly considered closing Fab 28 in July 2025, but no closure decision has been announced.

The Kiryat Gat police commander at the scene laid out the sequence: a blast occurred during a material transfer into the factory’s tanks after one truck had disconnected and another connected. At least eight Fire and Rescue Services teams, including hazmat, searched for trapped people, contained the fire, and monitored the hazardous substance.

“At this moment, I cannot point to any suspicion of criminal activity or negligence,” the commander added. Magen David Adom, Israel’s national emergency medical service, said two of the injured underwent resuscitation efforts and all three suffered severe burns. Ultimately, one of the injured was pronounced dead, a second later died of their wounds, and one remains hospitalized in serious condition inside the ICU, based on a statement from Soroka Medical Center in Beersheba.

The gas, although hazardous if inhaled, is not flammable. It’s not clear if the trucks were delivering NF3 or if it was directly involved in causing the explosion. Once the fire was put out, crews kept cooling the scene to prevent a secondary incident, and the commander said things appeared to be under control, with no sign so far of further leaks and no need to evacuate residents or factory workers. Kiryat Gat Mayor Kfir Suissa told residents to stay away while crews worked and added, “There is no danger to the public.”

At the time, there was no word on possible production delays, but these would be problematic as Intel 7 capacity was already tight. Last year the company’s CFO said that Intel 7 and Intel 10 constraints had limited its ability to meet demand, with shortages expected into 2026 with server wafers getting priority. Intel reports third-quarter results on Oct. 29 and will hold a call to discuss them, although the company has not mentioned whether it will address the explosion.

Advanced packaging technologies have become integral parts of advanced CPU and GPU designs, and virtually all of Intel's high-end client and data center CPUs rely on its Embedded Multi-die Interconnect Bridge (EMIB) and Foveros technologies. But what's next for these two advanced packaging methods? Before we try to see where both technologies are going, let's first take stock of where we are today.

Although Intel's advanced packaging saga began in 2017 with the Kaby Lake-G CPUs and Stratix 10 FPGAs, packaging technologies weren't quite the hot topic they are today. However, both Intel and its industry peers were working relentlessly to advance these technologies, so Intel was among the first companies to outline a detailed roadmap for multi-chiplet processors featuring its 2.5D and 3D integration technologies — EMIB and Foveros — back in 2020. Following the fiasco with its initial 10nm process technology, the company made it clear that its multi-chiplet strategy is a sustainable way to deliver performance and feature enhancements cost-efficiently and at a predictable cadence. While we certainly cannot say that all of Intel's multi-chiplet projects were a success, it is safe to say that the majority of Intel's client and data center CPU products launched in recent years use multiple chiplets and rely on EMIB and Foveros advanced packaging technology.

In fact, as Intel's advanced packaging roadmap evolves, EMIB and Foveros not only become more sophisticated to address the demands, but they also become simpler to cover cost-sensitive products. Another peculiarity about Intel's packaging duo is that they no longer seem to be two mostly separate technologies. In many cases, they complement each other and Intel's upcoming process technologies, thereby becoming key building blocks of the company's future products. The ultimate goal is to build system-in-packages (SiPs) the size of 12 reticles using both EMIB and Foveros Direct 3D, but Intel is not quite there yet, so let's take a look at where we are today and what's on the horizon.

EMIB: Fantastic bridges and where to find them

Intel's EMIB has evolved dramatically since entering high-volume manufacturing in 2017. What started as a relatively straightforward way to connect adjacent chiplets without using an expensive silicon interposer has become a sophisticated packaging technology used for data center processors and is set to enable massive AI accelerators 12 times the size of a reticle with dozens of silicon bridges, more than 24 HBM stacks, and advanced power delivery.

The basic idea behind EMIB remains unchanged almost a decade after its first introduction. Instead of placing compute and memory dies on a large silicon interposer, Intel embeds tiny silicon bridges into an organic package substrate only where high-density die-to-die connectivity is required (try to find those bridges!). This reduces silicon usage and allows the rest of the package to use conventional substrate wiring and relaxed bump pitches. Early EMIB implementations used a 55-µm first-layer-interconnect (FLI) bump pitch, which Intel subsequently reduced to 45 µm. Intel's recent roadmaps indicate further reductions to around 36 µm and ultimately 25 µm, which dramatically increases the number of connections that can fit along a chiplet's edge (shoreline density).

In addition to shrinking FLI bump pitches and increasing connection density, Intel is also adding functionality to the bridges themselves. EMIB-M incorporates metal-insulator-metal (MIM) capacitors into the bridge to improve power delivery and suppress voltage fluctuations close to compute dies. The newer EMIB-T takes this concept considerably further by adding through-silicon vias (TSVs), which enable power to travel vertically through the bridge instead of taking longer paths around it. This becomes increasingly important for multi-kilowatt system-in-packages (SiPs) and HBM4-class memory subsystems, where both current density and power integrity are major packaging constraints.

Such SiPs are not only complex, but they are physically large, so Intel's EMIB has evolved to support larger designs. Firstly, a finer FLI pitch increases the interconnect density required to build bigger SiPs. Secondly, EMIB-M addresses the power-integrity problem created by big processors, such as Intel's Xeon 6 'Granite Rapids.' Thirdly, EMIB-T simplifies power routing, lowers impedance, and reduces noise, which will get more important when faster versions of UCIe (32 GT/s and higher) become commonplace. Intel's consistent EMIB technology development has enabled the company to move from an SiP of 4X reticle size on an 80×80 mm package earlier this decade, to something closer to 8X reticles on a 120×120 mm package today, and even larger 12X SiPs on a 120×180 mm package in the future.

Eventually, Intel plans to combine finer-pitch EMIB technology with glass-core substrates. Glass offers better stability and reduced warpage compared with organic materials, which becomes increasingly important as packages grow to enormous sizes. Glass will likely be one of EMIB's biggest advancements, as it will enable improvements in multiple directions, including performance and dimensions.

Intel says EMIB-T is on track for mass production in 2027 and its yields and reliability are meeting its targets. If those ramps proceed as planned, EMIB will have evolved from an alternative to a silicon interposer into one of Intel Foundry's key technologies for building massive AI systems.

"Customer interest in EMIB-T continues to be very high – the technology is compelling, providing capabilities for advanced AI silicon solutions which are not possible with today's mainstream offerings," said Lip Bu Tan, chief executive of Intel, in an August 2026 earnings call. "We continue to have a growing EMIB-T backlog, yield and reliability are hitting targets, and we are focused on ramping the technology into high volume and high quality to support customer ramps in 2027."

Intel is scaling EMIB along several directions simultaneously: finer interconnect pitch, more bridges, larger substrates, denser power delivery, faster memory interfaces, and dramatically larger SiPs. Intel formally positions EMIB as a cost-effective advanced packaging technology that uses local silicon bridges for logic-to-logic and logic-to-HBM connections in an organic substrate instead of large silicon interposers used by solutions like TSMC's CoWoS-S. Meanwhile, there are applications that can benefit from large, rigid interposers or flexible organic redistribution layer interposers. To address these applications, Intel's Foveros portfolio includes Foveros-S, Foveros-R, and Foveros-B, which more directly mirror TSMC's CoWoS-S, CoWoS-R, and CoWoS-L packaging technologies, respectively.

Foveros 2.5D: A fistful of packages

Intel's Foveros packaging technology is evolving from its original chip-on-wafer implementation that emerged in 2019 with the Lakefield processor into a broad family of 2.5D and 3D integration technologies designed to address everything from cost-sensitive client processors to large HPC and AI systems.

The original Foveros technology used an active 22FFL-based silicon base die, or interposer, with through-silicon vias (TSVs) and active dies attached using face-to-face bonding. Intel's Lakefield and Ponte Vecchio used active base dies and 36 µm microbump pitches, whereas Meteor Lake, Arrow Lake, and Panther Lake implementations use a passive base with a 36 µm microbump pitch. Since the introduction of Foveros with active and passive base dies in 2019 – 2023, Intel has also diversified Foveros to address different cost and integration requirements. The latest Foveros 2.5D roadmap — which mentions -S, -R, and -B variants with similar characteristics — presented in mid-2025, takes Foveros considerably further from its original capabilities: it targets pitches below 25 µm, bump density increase from 772 to 1,600 connections per mm², and chip-to-chip interconnect power of 0.15 pJ/bit.

For now, the most advanced and yet production-proven Foveros 2.5D technology is Foveros-S. This packaging technology places multiple chiplets on a silicon interposer and currently supports packages up to four reticles in size, which is below what TSMC offers with CoWoS-S (up to 5.5X reticles). Since Foveros-S is essentially an evolution of the original Foveros from 2019, Intel legitimately says that it has been in volume production since 2019. Yet, going forward, Foveros-S will be evolving in multiple directions, which includes larger package sizes, interconnect density, and interconnect power efficiency.

Foveros-R removes the silicon interposer altogether and uses fan-out RDL technology to optimize cost and interconnect density. Intel says the implementation can use up to three redistribution layers. The method is designed to offer a balance between cost and interconnect density and enable heterogeneous integration of chiplets from different sources through UCIe. Like the other members of Intel's current Foveros 2.5D family, the technology uses 36 µm microbump pitches, but is designed to support pitches below 25 µm as well as bump density scaling from 772 to 1,600/mm² and chip-to-chip interconnect power of 0.15 pJ/bit. Intel says Foveros-R will be production-ready in 2027.

Foveros-B extends the concept toward larger and more complex AI/HPC designs. Instead of relying on a full silicon interposer, the technology combines RDLs with local active or passive silicon bridges that provide high-density connections only where they are needed. This potentially gives Intel an intermediate option between an RDL-only implementation and a large silicon interposer, as well as a direct competitor for TSMC's CoWoS-R.

Note that Intel does not explicitly say that Foveros-B uses EMIB bridges, though given similar microbump pitch sizes and the plan to use active local bridges in the future, Foveros-B's bridges are likely to closely resemble EMIB-M and EMIB-T bridges. If Foveros-B can indeed use EMIB bridges, future Foveros-B designs could also incorporate cache disaggregation, integrated voltage regulators (IVRs), or MIM capacitors.

As for interconnection densities and power, Foveros-B is listed as designed to support pitches below 25 µm, bump density scaling up to 1,600/mm², and chip-to-chip interconnect power of 0.15 pJ/bit. Meanwhile, Intel has not disclosed when Foveros-B will be ready for commercial production, so its actual specifications remain to be seen.

With EMIB and the Foveros 2.5D portfolio, Intel can address a broad range of applications, but Intel's scaling is not stopping. In addition to 2.5D lateral scaling enabled by EMIB or Foveros 2.5D, it can stack chiplets on top of each other using its Foveros 3D and EMIB 3.5D packaging technologies.

Foveros Direct 3D: There will be copper (and no bumps)

Unlike simple package-on-package stacking, which has existed for decades, densely interconnected 3D stacking essentially turns separate dies into parts of the same tightly coupled chip, increasing bandwidth, reducing latency, cutting interconnect power, and shrinking footprint. The challenge is manufacturing thousands of extremely fine connections between dies while maintaining yield, power delivery, signal integrity, and — perhaps most importantly — removing heat from chips buried inside the stack.

The biggest architectural step in Intel's Foveros roadmap is Foveros Direct 3D, which moves from microbump-based connections toward direct copper-to-copper hybrid bonding. Conventional microbumps cannot shrink forever, as solder bumps need sufficient dimensions to maintain manufacturing yield and reliability, while the solder itself introduces additional resistance and parasitic effects. Foveros Direct 3D eliminates solder altogether and directly bonds copper pads on one die to those on another, which enables an interconnect pitch below 10 µm — up to 10 times finer than conventional microbump technology.

Intel claims that Foveros Direct 3D can offer bonding pitch of sub-10 µm, interconnect density of up to 10,000 connections per mm², and chip-to-chip interconnect power below 0.05 pJ/bit. Such dense connectivity shortens signal paths between stacked dies, increases bandwidth, reduces latency, and cuts the energy required to move data. In addition to electrical advantages, direct bonding creates more continuous thermal paths between dies, which Intel says improves heat dissipation compared with conventional packaging, which is crucially important as vertically stacked logic pushes power density dramatically higher.

Intel's Foveros Direct 3D bonding interface supports both face-to-back and face-to-face stacking. In addition, Intel has described chip-to-wafer as well as wafer-to-wafer bonding.

As Intel's schematic drawing of a Foveros Direct 3D-based system-in-package shows (and Intel confirms), the technology is much more flexible than simply placing one logic die on top of another. The method can support different die sizes, multiple stacking levels, and can combine dies manufactured using different process technologies in one SiP.

Intel's Xeon 6+ 'Clearwater Forest' processor is the first product to use Foveros Direct 3D copper bonding in volume to attach Intel 18A compute chiplets to active base dies. The CPU uses the 1^st Generation Foveros Direct 3D with 9 µm copper bonding pitch. Meanwhile, Intel plans to shrink bonding pitch to 3 µm with its 2^nd Gen Foveros Direct 3D. To put these numbers into perspective, TSMC's 1^st Gen SoIC from 2023 supports pitches of 9 µm (AMD's 2^nd Gen 3D V-Cache uses this version), whereas the latest generation that entered volume production in 2025 features bonding pitches of 6 µm. TSMC expects to shrink SoIC's interconnection pitch to 4.5 µm by 2029.

EMIB 3.5D: Everything everywhere all at once

Finally, Foveros and EMIB do not have to operate independently. Intel can combine Foveros 2.5D or Foveros Direct 3D with substrate-embedded EMIB bridges to create what it calls EMIB 3.5D in a bid to build its ultimate products. In this architecture, Foveros provides dense local 2.5D or 3D connectivity within individual chiplet assemblies, while EMIB provides high-bandwidth horizontal connections between these modules, essentially building a massive system-in-package out of smaller SiPs. Intel says the individual SiPs can be identical to scale performance, or distinctive, to enable different functionality.

The combination of EMIB and Foveros is particularly useful because it enables Intel to scale both horizontally and vertically without placing the entire system on one massive silicon interposer. Intel says EMIB 3.5D can achieve a total silicon surface area considerably larger than what its existing silicon-interposer-based technologies can accommodate. Intel first used EMIB 3.5D to build its Ponte Vecchio compute GPU that integrated 47 active tiles manufactured on five process nodes and contained more than 100 billion transistors. Although Intel's Data Center GPU Max can hardly be called a smashing success, it certainly demonstrated what Intel can do with its advanced packaging technologies.

Going forward, the EMIB 3.5D architecture becomes considerably more promising when combined with Foveros Direct 3D. Using both will enable Intel to build tightly coupled compute modules using ultra-dense vertical copper-to-copper connections, and then link multiple modules laterally using EMIB, essentially scaling complex processors both vertically and horizontally. However, surprisingly, Intel decided not to use EMIB 3.5D for its next-generation Xeon 'Diamond Rapids' processor: while the CPU uses Foveros Direct 3D for vertical integration, UCIe-S connections are used for lateral interconnects.

Multi-die another day

While Intel's EMIB and Foveros technologies emerged to serve different kinds of scaling, the company is evolving them into a complementary platform that can scale complex processors both horizontally and vertically.

EMIB is progressing toward finer interconnect pitches, vertical power delivery, glass substrates, and packages exceeding 12 reticles with more than 24 HBM stacks, while the expanding Foveros family spans from 2.5D integration all the way to ultra-dense Foveros Direct 3D hybrid bonding. In fact, Foveros Direct 3D already enables sub-10-µm copper-to-copper connections and is headed toward even finer pitches.

Meanwhile, EMIB 3.5D combines vertically stacked modules with lateral EMIB links to create large heterogeneous system-in-packages for ultimate AI and HPC applications without using enormous silicon interposers.

What is perhaps interesting to note is that, for now, Intel lacks a system-on-wafer platform to enable Cerebras WSE and Tesla Dojo-like wafer-scale processors, though this is explainable, as demand for such technologies is too limited today and may not pick up significantly tomorrow.

Elon Musk's Terafab will get its first EUV lithography tool in the middle of next year, reports Tim Culpan, citing sources with knowledge of the matter. But considering that the shell of the firm's development fab will not be completed until late 2027 and that tools will only begin to be moved in later that year, according to SemiAnalysis, the scanner will sit idle for some time.

Tesla broke ground on its research fab on the north campus of Giga Texas near Austin this past April. SemiAnalysis expects the building to be completed in 15 months and predicts it will take Tesla a further six months to install equipment and production tools, after which it will be able to start processing wafers, or rather experimenting with chip production to get the team prepared for completion of the Terafab volume fab phase 1.

Given how hard it is to get an ASML Twinscan NXE EUV lithography tool these days, storing it for several months before putting it to use may sound like an expensive slack period, but it's not the significant financial problem for Terafab that it would be for a traditional chipmaker.

The projected delivery of a conventional EUV lithography system to Terafab also indicates that while Elon Musk has praised free electron laser (FEL) light sources for lithography tools, the first-generation efforts of his semiconductor production company will rely on more traditional equipment. This is not particularly surprising, as Terafab is set to use Intel's 14A manufacturing technology. 14A will use not only existing Low-NA EUV scanners, but also next-generation High-NA EUV machines.

Using lithography systems with unconventional and largely untested light sources would require substantial modifications to the manufacturing process, extensive equipment qualification, and potentially changes to photomasks and photoresists, which would complicate the transfer of Intel’s 14A technology and delay Terafab's production ramp.

But usage of standard lithography equipment does not mean that Musk's company has no plans to use tools that are different from those used by Intel, though for now it is too early to make guesses about what Terafab engineers might change in terms of fab configuration.

SpaceX announced that it had selected Grimes County for Terafab in early August 2026. By now, there is evidence that work has progressed beyond clearing land, as drone footage published by Joe Tegtmeyer in mid-September showed foundation excavation and rebar cage installation at the northwestern part of the site. This suggests that contractors had begun structural construction by early September, although the precise purpose of the foundation is unknown.

Right now, SemiAnalysis reports that project Terafab Grimes phase 1 will be built in 20 months, equipped in 17 months, and ramped to volume in six months. Analysts project that the fab will begin operation in late 2029 and then ramped to volume by mid-2030.

An interesting note about Terafab's volume fab is that SpaceX reportedly ordered semiconductor manufacturing equipment in April 2026, several months before officially announcing the Grimes County location. This indicates that the company committed to its manufacturing plans well before the public groundbreaking. In addition, this makes the mid-2028 equipment installation forecast plausible, given the long lead times associated with advanced semiconductor manufacturing equipment.

Intel plans to begin risk production using its 14A (1.4nm-class) fabrication process in the second half of 2027 and initiate high-volume manufacturing (HVM) in the second half of 2028 if everything goes as planned. This puts Intel's ramp into HVM at least 1.5 years ahead of SpaceX’s Terafab Grimes Phase 1.

This means that while Terafab will get a proven advanced manufacturing technology, presumably with decent yields, it will not be the absolute best production node at the time, as TSMC intends to start volume production of chips using its A12 fabrication process in late 2029. A12 is a 1.2nm-class process with TSMC's second-generation nanosheet GAA transistors and backside power delivery. Intel will be close to unveiling its 14A-P node at the same time.

Nonetheless, since Terafab will likely exclusively serve SpaceX, Tesla, and xAI, a slightly less advanced node will not be a big problem for the company, as the potential cost increases incurred by using a more sophisticated manufacturing technology will be offset by using an in-house production facility.

When GlobalFoundries abandoned development of leading-edge nodes in 2018, it also canceled the development of its 7nm-class FinFET fabrication technology that it co-developed with IBM. Almost exactly eight years later, GlobalFoundries is back with a 7nm-class manufacturing process, only this time the node relies on planar transistors and fully-depleted silicon-on-insulator (FD-SOI). It is aimed at automotive, edge AI, industrial, robotics, sensors, and other devices that prioritize low power consumption, high integration, and cost efficiency over maximum performance.

"We are delighted that GlobalFoundries has announced its next-generation 'single-digit FD-SOI; node, building on technology that CEA-Leti has been advancing for decades," said Sébastien Dauvé, chief executive of CEA Leti. "Through the FAMES pilot line, CEA-Leti continues to shape the future European roadmap for FD-SOI and works every day to promote its adoption in a wide range of applications."

FDX Fusion enters the scene

The new fabrication technology from GlobalFoundries is called FDX Fusion, and it promises 7nm-class 'digital performance' (an ambiguous claim; we will try to interpret it later) and more than twice the transistor density of its original 22FDX process introduced circa 2015. To achieve its target goals, the first generation of FDX Fusion will combine innovations in SOI substrates, transistor structures, and back-end interconnects, though keep in mind that GF has not disclosed transistor dimensions, contacted gate pitch, minimum metal pitch, or actual transistor density. GF plans to launch production of chips on FDX Fusion at its Dresden, Germany, facility in 2028, which will mark its return to the development of substantially more advanced FD-SOI fabrication processes after years of efforts to enhance its existing 22nm-class platform.

In addition to improved 'digital performance,' FDX Fusion will support RF transistors with fT/fmax of up to 0.5 THz, analog and mixed-signal circuitry, embedded nonvolatile memory, and in-memory computing capabilities. The combination is intended to enable highly integrated chips that can process information from sensors, execute AI inference workloads, control external devices, and communicate wirelessly without the need for numerous separate ICs. GF also intends to provide processor IP based on MIPS, ARC, and RISC-V architectures to accelerate the development of such products.

That being said, the main selling point of FDX Fusion is not necessarily its 7nm-class 'digital performance' and high-performance processor IP, but rather its ability to combine relatively powerful digital logic with RF, analog and mixed-signal circuitry, embedded nonvolatile memory, and in-memory computing capabilities on a single chip. This combination — which is why GloFo calls the process technology FDX Fusion — could enable highly integrated SoCs that would otherwise require multiple chips manufactured on different process technologies, which means additional tapeout costs as well as power consumption.

GlobalFoundries said it plans to deliver initial demo silicon for customer evaluation in early 2027, followed by the first process design kit (PDK) in mid-2027. The company is already collaborating with several customers on the technology, although it has not identified specific products or committed production volumes. Specifically, GF mentioned in its press release that BMW, Bosch, Infineon, NXP, Siemens, and Tesla have expressed interest in FDX Fusion, though only Infineon specifically confirmed collaboration on future 7nm-class technologies for radar and wireless communications.

Significant development

The GlobalFoundries announcement represents a significant development for GF's FD-SOI roadmap. The company introduced 22FDX in 2015 and announced its 12FDX successor in 2016, which promised performance comparable to 10nm FinFET, full-node density improvements, and up to 50% lower power consumption. Initial 12FDX customer tape-outs were expected in 2019, but the technology has never been adopted for commercial products. Instead, GF focused on enhancements to 22FDX and eventually the introduction of 22FDX+ (around the time when Samsung unveiled its 18FDS+), with additional capabilities for RF, embedded memory, and low-power applications. Interestingly, 12FDX was still a part of GF's investor roadmap in 2022.

FDX Fusion could therefore represent the realization of GF's original ambitions to scale FD-SOI beyond 22nm-class, although the company has not explained whether the new technology incorporates developments from its earlier 12FDX program. Meanwhile, CEA-Leti, which has conducted research into advanced FD-SOI technologies for years, describes FDX Fusion as a single-digit FD-SOI node. Nonetheless, GF's claim of 7nm-class 'digital performance' does not necessarily imply comparable transistor dimensions or integration density.

From an industry perspective, FDX Fusion could provide an alternative to advanced FinFET and perhaps even gate-all-around processes for applications that require reasonably powerful digital logic alongside RF, analog, and embedded memory. Such integration could reduce system complexity and power consumption, particularly in edge AI devices where energy efficiency and real-time responsiveness are critical.

Perhaps more importantly, the technology could give European semiconductor developers access to a more advanced locally manufactured process without dependence on leading-edge foundries in Asia or the U.S.

Questions remain

However, the commercial success of FDX Fusion will depend on its actual performance, density, production costs, and the availability of a competitive design ecosystem, the latter arguably being the hardest part given the lack of any comments from leading electronic design automation (EDA) and IP developers.

When GlobalFoundries claims 2X 'digital performance' comparable to that of 7nm-class technologies, it doesn't reveal whether it means transistor switching speed, standard cell performance, achievable operating frequency, or something else. In addition, the company promises more than twice the logic density of its first-generation FDX technology, although the firm does not reveal any actual numbers. Consequently, it is unclear how FDX Fusion will compare with established 7nm-class FinFET technologies, which offer mature defect density and yields, plenty of supply, an established design ecosystem, and predictable pricing among other things, in terms of transistor density, performance, power consumption, and production costs. While CEA-Leti's comment seems promising, actual numbers are always better.

The very fact that GF's FDX Fusion planned 2028 introduction will come roughly nine years after the originally anticipated first 12FDX tape-outs illustrates significant technological and/or financial difficulties associated with the development of FD-SOI beyond the 22nm generation. So, while GlobalFoundries' FDX Fusion initiative certainly looks promising, it remains to be seen how that is going to play out for the contract chipmaker and its clients.

For now, the lineup of supporters from the automotive and industrial sectors — BMW, Bosch, Infineon, NXP, Siemens, and Tesla — certainly looks promising. But what about other applications? While established semiconductor companies such as Infineon and NXP already possess extensive processor IP portfolios, smaller fabless developers could benefit from GF’s MIPS and ARC processor cores, RISC-V expertise, and custom chip design capabilities, which could substantially reduce the cost and complexity of developing specialized SoCs. Still, to attract a broader range of chip developers, GlobalFoundries will need a mature ecosystem of EDA tools, standard-cell libraries, memory compilers, interface IP, and other silicon-proven building blocks. These are the things that GlobalFoundries has not touched upon in its press release.

GlobalFoundries and TSMC have entered into a five-year manufacturing agreement valued at $2 billion under which GlobalFoundries will produce silicon interposers for TSMC's CoWoS advanced packaging technology. The arrangement will establish a U.S.-based manufacturing source for these components, which will enable TSMC's clients to brand their products as completely made and packaged in America. Volume production is scheduled to ramp up in the first half of 2028.

"By providing manufacturing service using GF's trusted U.S. manufacturing footprint, we are creating a secure, scalable source of essential advanced-packaging elements that will help customers accelerate innovation and strengthen the semiconductor supply chain," said Ed Kaste, senior vice president of CMOS Business at GlobalFoundries.

GF and TSMC team up

Under the agreement, GlobalFoundries will expand manufacturing capacity at its fabrication facility in Malta, NY, to produce silicon interposers used in TSMC's CoWoS-S packaging ecosystem. Such interposers are custom pieces of silicon that provide high-density connections between logic chiplets and high-bandwidth memory (HBM) stacks and enable the creation of complex multi-die processors for artificial intelligence (AI) and high-performance computing (HPC) applications. The companies have not disclosed the production capacity to be installed, but the agreement provides a framework for additional expansion depending on demand.

Silicon interposers used for TSMC's CoWoS-S packaging technology are customized for particular processor designs, as their configurations depend on the number, dimensions, and placement of logic chiplets and HBM stacks, as well as the interconnections between them.

In addition, interposers must meet the power-delivery requirements of specific processors, including power distribution networks and embedded deep trench capacitors (DTC), and their designs must account for signal integrity, power integrity, and thermal characteristics. Furthermore, large interposers may exceed the maximum lithographic reticle size and therefore require stitching, so it remains to be seen how well GlobalFoundries will stitch such interposers for extra-large system-in-packages (SiPs).

While certain manufacturing processes and structural elements can be standardized, the resulting interposers are generally application-specific. GlobalFoundries will not be a TSMC supplier, but a subcontractor that will manufacture multiple customer-specific interposer designs rather than standardized components that require close cooperation with TSMC. Specifically, GlobalFoundries will need to ensure compatibility between its design rules, manufacturing processes, and qualification procedures so that interposers produced by GF can be used in TSMC's CoWoS packaging flows. It remains to be seen how the companies will handle ownership and protection of intellectual property, as interposer layouts may incorporate technologies and production methods specific to TSMC and its customers.

By transferring some interposer production to GlobalFoundries, TSMC could free up some of its own manufacturing resources and increase availability of components required for advanced packaging.

Manufacturing silicon interposers is only one part of the CoWoS-S production process. The technology also requires attaching logic chiplets and HBM stacks to interposers using high-precision bonding equipment, assembling the resulting structures onto organic substrates, and then performing electrical testing. These operations require dedicated manufacturing capacity, which the agreement between the two companies does not address.

Becoming a part of TSMC's CoWoS ecosystem

Following its exit from development of leading-edge process technologies in 2018 and consequent inability to produce leading-edge AI and HPC accelerators, GlobalFoundries is now becoming a part of TSMC's advanced packaging supply chain in the U.S. that will supply custom components for AI and HPC processors.

For GlobalFoundries, the agreement represents an opportunity to participate in the manufacturing of advanced AI processors without producing their leading-edge logic dies. Although the company abandoned the development of leading-edge process technologies eight years ago, its manufacturing capabilities remain suitable for producing certain components used in sophisticated multi-chip packages, including CoWoS-S interposers. It remains to be seen though whether it can also participate in TSMC's CoWoS-L supply chain.

The agreement with GlobalFoundries is particularly important considering TSMC's plans to establish advanced packaging operations in Arizona. The company intends to introduce CoWoS and 3D-IC packaging capabilities in the state before 2029 and has signed a 10-year agreement with Amkor Technology, which is building an advanced packaging facility in Peoria, Arizona, that is scheduled to begin production in early 2028.

As GlobalFoundries ramps up interposer production in New York in the first half of 2028, TSMC could potentially establish a largely domestic CoWoS supply chain that comprises logic dies manufactured in Arizona, silicon interposers produced in New York, and advanced packaging and testing performed by TSMC and/or Amkor in Arizona. For a while, HBM stacks would still have to be sourced from memory manufacturers in Asia, though both Micron and SK hynix intend to bring HBM assembly facilities to the U.S. already this decade, so it is safe to say that the U.S. will have a vertically integrated supply chain for production of advanced AI processors by 2029 – 2030.

There is a catch, though, as GloFo and TSMC have not disclosed how CoWoS assembly operations will be divided between TSMC and Amkor, or whether GlobalFoundries' interposers will be used in Arizona at all. Yet, GF's wording about a trusted U.S. manufacturing footprint strongly implies that its interposers will be primarily aimed at SiPs fabricated entirely in the U.S. Meanwhile, expanding interposer production alone will not increase the number of finished AI processors unless sufficient chip-on-wafer assembly and testing capacity is available.

Some things remain unclear

The initial agreement covers five years and establishes a mechanism for further capacity additions. However, the companies have not disclosed the planned manufacturing volumes, capital expenditures associated with the expansion, or the breakdown of the $2 billion agreement. Furthermore, we yet have to find out how GF's manufacturing capabilities are aligned with CoWoS-S' advancements.

U.S. Semiconductor Manufacturer Wolfspeed Inc. has received a conditional 30-year, $1.5 billion loan commitment letter from the U.S. Department of War (DoW) through its Office of Strategic Capital (OSC), as the country continues its push to boost domestic semiconductor manufacturing. According to an official press release on Oct. 7, Wolfspeed — which specializes in silicon carbide (SiC) and gallium nitride (GaN) materials and devices — will use the long term-financing to upgrade its GaN epitaxy capabilities and to develop radiation hardening capabilities for current SiC and future GaN products.

The company says SiC and related technologies are “critical to next generation power and radio-frequency applications across defense, aerospace, AI, critical infrastructure and other strategic commercial markets,” and that it will focus on U.S. national security applications, including communications infrastructure and electronic warfare systems. “SiC and GaN have critical national security applications,” said Wolfspeed CEO Robert Feurle. “With this financing, the company would be well positioned to not only continue to serve the DoW but also expand its capabilities for the benefit of U.S. national security as a whole,” he continued.

Under the terms of the loan — which is subject to final agreements — Wolfspeed is required to issue the DoW warrants to buy up to 7.5% of its fully diluted equity. The warrants would be priced off the stock's volume-weighted average price (VWAP) and handed over in proportion to each tranche of the loan as it's funded. As of this report, the loan remains conditional, pending the OSC’s completion of its due diligence. Wolfspeed also needs to secure government approvals and appropriations, as well as the consent of its existing lenders. The company itself warns there's no guarantee the financing will go through.

“This conditional 30-year commitment represents another significant milestone in our ongoing efforts to optimize Wolfspeed’s capital structure and improve our financial foundation,” said Wolfspeed CFO Gregor van Issum. “Subject to the satisfaction of diligence, negotiation of definitive agreements, and other financial, legal, and investment conditions, the broader commitment is expected to provide additional long-dated capital to support our strategic priorities, improve financial flexibility, and further position Wolfspeed for long-term value creation.”

The announcement marks the U.S.’s latest move to onshore critical semiconductor manufacturing and strengthen the domestic supply chain, combining direct capital subsidies, major tax incentives, and strict regulatory changes. Through the $54.2 billion CHIPS and Science Act, the U.S. government has injected billions into massive fabrication facilities for industry leaders like TSMC, Intel, GlobalFoundries, and Micron, while simultaneously utilizing the Section 48D Advanced Manufacturing Investment Credit to offer a 25% tax credit that has led to over $827 billion in private sector announcements.

A little less than seven months since signing a memorandum of understanding (MOU) concerning memory supply and collaboration in various fields with Samsung, AMD's chief executive Lisa Su is visiting South Korea to secure additional supply of HBM memory for AI accelerators, reports Chosun.biz. Meanwhile, Samsung is seeking a broader partnership and 'hopes to turn its memory supply relationship with AMD into foundry' chip production orders, the report claims.

"We are going to talk about our broader partnership," said Lisa Su when asked by reporters about what she planned to discuss with Samsung's executives. "We have many partners at Samsung."

Before visiting Samsung headquarters, Lisa Su and Jack Huynh, senior vice president and general manager of AMD's Computing and Graphics Group, attended the AMD Gamer Day event where Su and Huynh answered some questions from South Korean journalists and called local memory makers 'important strategic partners,' something that reflects the significance of data center-grade DDR5 and HBM memory for the company's AI and data center businesses.

"Samsung Electronics and SK hynix are key supply-chain partners for AMD," Su said, Chosun reports. "AI demand is extremely high, so we are planning our long-term supply chain with our partners. […] It is important to plan three to five years ahead with our partners."

The non-binding MOU that AMD and Samsung signed this March covered four areas and remained in effect for a period of three years:

• Supply of next-generation memory products, including HBM4 and advanced DDR5;
• Co-development and optimization of memory solutions for Al and high-performance computing systems;
• Exploration of foundry manufacturing opportunities for the future AMD platforms;
• Co-optimization of advanced packaging and related semiconductor technologies.

While Samsung has become a principal supplier of HBM4 for AMD's Instinct MI400-series accelerators, expansion of collaboration beyond memory supply is considerably more complicated, as it involves considerable efforts to design chips for Samsung Foundry's process technologies as well as risks associated with a product ramp at a new contract chipmaker. Truth to be told, AMD already uses Samsung Foundry and UMC to make its "ICs in the form of programmable logic devices" however, moving production of more advanced products to Samsung is risky. Meanwhile, Samsung badly needs big customers like AMD, and the latter's dependence on HBM supply certainly gives the former leverage.

"If we transition the production of some of our products to new manufacturers, we may experience delayed product introductions, lower yields or poorer performance of our products," AMD wrote in its most recent Annual Report.

AMD has already started shipments of its Instinct MI455 accelerators with 432GB of HBM4 memory onboard as well as rack-scale Helios AI systems to interested parties.

"We have started shipping our next-generation MI455 and Helios systems," Su told journalists, according to Chosun. "These are all systems that use HBM4."

So, it looks like the company is negotiating for more memory supply. The question is, will it take a risk and adopt Samsung Foundry for something more serious than niche programmable chips in a bid to get more high-bandwidth memory and sell more expensive AI accelerators? Only time will tell.

Two former Groq engineers are suing Groq’s former board and former CEO Jonathan Ross, alleging the board handed over employees and company technology to Nvidia in a $20 billion deal. The proposed class action, filed in Delaware’s Court of Chancery by Benjamin Serebrin and Joshua Rubin and unsealed Monday, alleges the deal, with a $17 billion license fee for all backers and a separate $3 billion Nvidia stock pool for engineers who transferred, kept billions from other shareholders. Meanwhile, Groq is planning to deploy its own technology, now Nvidia’s Groq 3 LPX, the Financial Times reports.

Nvidia’s annual report (10-K) books $14.4 billion of the license as goodwill “primarily attributable to the workforce and future development of the licensed technology” plus $2.5 billion for the technology itself. The plaintiffs concede that “no Delaware decision has directly answered the question this case raises,” but the deal is already under a reported Department of Justice (DOJ) inquiry. The lawsuit’s outcome has implications for future license-plus-hire deals. Groq told CNBC the suit is “meritless” and said its licensing agreement with Nvidia “delivered exceptional value for Groq, our investors, and our employees.”

The deal involved both the LPU technology and the people who built it, including Ross, a former Google TPU engineer who founded Groq in 2016. The LP30 has 500MB SRAM per die and 150 TB/s bandwidth, uses Samsung’s 4nm process technology, and is rated by Nvidia at up to 1.23 FP8 PFLOPS. A single LPX rack has 256 LPUs with 128GB SRAM, 40 PB/s, and 315 FP8 PFLOPS in aggregate, as a decode co-processor for Vera Rubin NVL72. The LP30 appears to be the next-gen LPU Groq roadmapped in August 2023 on Samsung’s SF4X process with its first-gen Tensor Streaming architecture.

During Hot Chips in August of this year, Igor Arsovski, Groq’s former chief architect and now Nvidia VP of hardware, called the occasion “a pinch me moment for the Groq team that’s now integrated into the Nvidia group.” The rack was already in production at the time, Arsovski said. This supports the complaint’s factual premise, but does not answer the legal question about whether more is owed.

Nvidia’s 10-K notes indicate that “no customer contracts, existing products, or equity interests were purchased” with “$13.0 billion paid at closing and $4 billion, inclusive of imputed interest, payable within one year.” The goodwill number, as reported above, is about 85% of the $16.9 billion Nvidia booked and around 5.8x the value of the technology asset. Nvidia put significantly more value on the LPU design team and the technology’s future development than on the design itself.

Groq said when the deal was announced that it would continue “to operate as an independent company,” and it joined the Nvidia Cloud Partner program in August. Also in August, “Groq LLC” had a $350 million Series A and a $3.5 billion valuation after raising $650 million in June. Before the deal, in September 2025, the valuation was put at $6.9 billion after a $750 million round. Groq says it now operates 13 data centers and expects to scale from 54 to 200+ MW in 2027. Nvidia was slated to participate in the Series A, which Groq says will support those seeking “clusters of NVIDIA accelerated computing.”

Groq also said in August that it is “among the first adopters of NVIDIA Groq 3 LPX” with Nvidia’s Vera Rubin NVL72, deploying with Dell. Those racks are built on the LPU technology Groq licensed to Nvidia, and Groq claims to be “the only team with hands-on experience operating LPUs in production at scale.” The Financial Times said Groq “pivoted entirely to AI cloud computing, dropping its chip design efforts.”

The suit alleges that the Groq board was conflicted, failing to secure the best terms for every shareholder and denying some of them a vote on the deal. Specifically, it says Ross and other top Groq employees were allowed to “take a discount on those shares and be paid separately for following the technology to Nvidia.” According to the suit, Nvidia hired “nearly all” of Groq’s engineers, as many as 200. However, the final payout is alleged to have ignored potential upside and synergies with Nvidia.

The plaintiffs also say that because Nvidia didn’t buy Groq outright, the $17 billion license payment was taxable as income at Groq, and that the Series A valued the remaining Groq above the price paid to the shareholders who were bought out. They say four “conflicted funds” on Groq’s board, BlackRock, Social Capital, Infinitum, and Disruptive, which are not named as defendants in the case, engineered that gap and profited by staying with Groq after the buyout.

As reported by Axios in December 2025, though, sources close to the deal said that most shareholders would get per-share payouts “tied to the $20 billion valuation.” Around 90% of employees would join Nvidia, with vested shares paid in cash and unvested shares paid in vesting Nvidia stock. Staff who stayed with Groq would be paid for vested shares and get a package including “economic participation in the ongoing company.”

As for the DOJ, the New York Times reported in September that the department sent Nvidia a formal request for information with a fine being possible. Nvidia said at the time that the Groq story was “a prime example of the American system working as designed.” The deal did not go unnoticed by some senators who, in February, put it under the “reverse acqui-hire” deal label. Federal Trade Commission Chair Andrew Ferguson said in January that the agency is “beginning to examine these acqui-hires to make sure they are not an attempt to get around” its merger review process.

The litigation comes not long after Nvidia’s agreement to acquire Hugging Face (HF) a month ago, which included a purchase price and equity for HF employees who join Nvidia, a similar split. The deal is waiting on approval, but unlike the Groq deal, it is an outright purchase of the company. When the Groq deal was announced, Nvidia CEO Jensen Huang told employees in an email, obtained by CNBC, that while Nvidia was adding Groq staff and licensing its IP, “we are not acquiring Groq as a company.”

The legal question on the Groq deal remains open, and more details will come out as the case proceeds and the defendants respond. As for the LPX customers, Nvidia calls Nebius the first AI cloud to adopt LPX and says the racks will be online there later this year. Looking ahead, Nvidia has the LP35, with NVFP4 support, alongside the Rubin Ultra and LP40 for Feynman on its roadmap.

Intel will remain a part of Elon Musk's Terafab project, Lip-Bu Tan, chief executive of Intel, told reporters on Wednesday. Around the same time, Elon Musk, chief executive of SpaceX, Tesla, and xAI, said that Terafab remains committed to building and operating its fab itself, but proposed to lease a part of the fab to TSMC.

Intel will continue its involvement in Terafab, Lip-Bu Tan told Bloomberg prior to the company's event in Japan that commemorates the company's presence in Japan. Back in April, Intel and Terafab, the semiconductor production venture by SpaceX, Tesla, and xAI, announced that the new chipmaker would use Intel's next-generation 14A fabrication process to make chips. Details of the collaboration are still unknown, but there is a general understanding that Intel will license its manufacturing technology to Terafab, though it is unclear whether it will also help ramp up production using the node.

At around the same time, Elon Musk debunked rumors that his companies would invest in Terafab and then partner with TSMC, which will build and operate the fab. Instead, Elon Musk proposes that TSMC sublease a part of Terafab to make chips for its customers.

"No, we will build and run the fab," Elon Musk wrote in an X post. "Let there be ZERO doubt about that. Maybe TSMC subleases part of the Terafab if they want, but nothing more than that."

Offering TSMC, the world's largest foundry that owns and operates dozens of advanced 300-mm fabs around the world, to 'sublease' a part of Terafab is quite an unusual arrangement for many reasons.

First up, TSMC has its own production facilities as well as aggressive plans for about 10 new fab phases in the coming years, and it hardly needs to sublease any capacity or part of the building or site from a third party.

Secondly, semiconductor fabs are not generic facilities: if Terafab is initially equipped and qualified around Intel's 14A process technology, converting part of the facility for TSMC's A14, A13, or A12 processes that the company will use in the back half of the decade would require different process flows, equipment configurations, materials, automation, qualification, and contamination control. Theoretically, TSMC could install a largely independent production line within the same enormous building, but at that point the arrangement would resemble TSMC building and operating its own fab inside a Musk-controlled site rather than simply renting spare manufacturing capacity.

Thirdly, if Intel licenses 14A technology to Terafab, the agreement would almost certainly contain extensive provisions governing access to Intel IP, process information, equipment configurations, and personnel. Putting TSMC engineers and manufacturing operations inside the same facility could create contractual and IP-isolation issues even if TSMC never directly touches the Intel production line. In fact, IP protection would be extraordinary at Terafab, which will complicate its operation.

Fourthly, if indeed two chipmakers end up in the same fab building, or even in the same campus, responsibility for downtime becomes messy. In the case of a Terafab-owned power distribution system, water plant, chemical system, or cooling installation fails and takes someone's production offline, determining operational responsibility and financial liability for potentially hundreds of millions of dollars of affected wafers would be considerably more complicated than at a site controlled by one company.

Finally, if Terafab can equip enough cleanroom space by the end of the decade to satisfy semiconductor requirements of Tesla, SpaceX, and xAI while still leaving substantial capacity available to TSMC, that would raise questions about whether the project had significantly overbuilt capacity in its initial phases.

Since Musk's statements at X are deliberately vague, it is hard to interpret them. In fact, there might be a conceptual problem with Musk's statement. If TSMC installs its own tools, hires its own employees, brings process technology, and production management, while Terafab just provides land, shell, and infrastructure, calling this a 'sublease' undersells what would be a TSMC fab embedded within the Terafab campus. Alternatively, if Terafab provides the tools and infrastructure and TSMC just operates them, that starts to look much closer to precisely the kind of TSMC operational involvement Musk appears to be denying.

Anyhow, while Intel has confirmed its involvement in the project and Musk wants TSMC to be part of it as well, the latest comments raise more questions than they answer.

Qualcomm has reached a deal to license Huawei patents behind the LogicFolding chip-stacking method, Bloomberg reports. The technology, which is used in the Kirin 9050 Pro, splits nearly every block across two bonded dies, and a teardown and die shots show the lower die holds mostly cache and I/O.

Qualcomm’s multiyear, cross-license deal with Huawei has a wide scope, covering 5G devices, AI services, near- and co-packaged optics and networks, a Huawei spokesperson told Bloomberg. Qualcomm also intends to purchase specific Huawei U.S. patents in compute, AI, networking, and other technologies, according to a release. Neither company’s announcement named any patents, LogicFolding, or any chip that uses it.

Bloomberg's report frames the deal as a win for Huawei, validating its chipmaking acumen. The deal remains subject to approval, and Qualcomm will reportedly pay Huawei to license its patents for the first time. According to the report, LogicFolding targets faster data transmission as a workaround for China’s lack of access to EUV lithography machines.

The Kirin 9050 Pro is used in the Huawei Mate XT 2 tri-fold smartphone, launched Sept. 7. Geekerwan, a Chinese tech review channel known for in-depth chip testing, had a lab slice the chip for its teardown. Kurnal, a semiconductor researcher who publishes die-shot analysis, also posted annotated shots of both dies on X. Geekerwan’s cross-section shows the two dies bonded face to face, and both show the execution units on top, with the PLLs also on the lower die.

LogicFolding was first unveiled on May 25 by He Tingbo, president of Huawei’s semiconductor business, at IEEE ISCAS 2026 in Shanghai, under the company’s “Tau Scaling Law,” which uses signal delay rather than transistor size as a measure. Huawei describes both layers as active and working as one. Vertical interconnects work to create shorter signal paths, which can reduce energy consumption. Peking University’s “true 3D” design tool for the technology shows a 30% wire-length cut in its own tests.

Huawei’s papers describe a “Kirin 2026” chip whose figures match the Kirin 9050 Pro’s. In a paper last month, relayed by TrendForce, Huawei said the chip uses a 1.5-micrometer hybrid-bonding pitch with about 50 million interconnects. About 10–15% of those carry signals. Core routing is 20% shorter, with critical paths up to 70% shorter. Power is reduced by as much as 66% for NPU, 58% for GPU, and 41% for a CPU performance core at the same performance level. NPU performance holds 29 TOPS at 63% less frequency and at a lower voltage.

Huawei does not name a process node. On its roadmap is Kirin 2027 at a 1-micrometer pitch and more than 100 million interconnects; for around three years out, a 720-nanometer pitch with over 200 million. It is targeting a 1.4nm-class density by 2031, with LogicFolding in the Ascend 990 AI accelerator around 2030. HiSilicon, Huawei’s chip-design unit, designs the Kirin chips, and SMIC is believed to make them, according to Reuters via TrendForce. It isn’t stated who handles the bonding process.

As for the Kirin 9050 Pro, Geekerwan tested it in a Mate 90 Pro Max phone. Analysis shows that the two dies are bonded with copper-to-copper hybrid bonding, metal layer to metal layer. The bonded circuit layers of both dies sit between two thick layers of silicon rather than directly on the package substrate. For the interconnects, about 80,000 through-silicon vias (TSVs) run through the lower die, taking up, with their keep-out zones, about 8% of the lower die’s usable area, Geekerwan says.

The split spans both dies. In the big CPU core, the execution units are on top, with the L1 and L2 caches directly beneath the load/store units, Geekerwan says. Kurnal's die shots put the GPU and NPU logic over their caches too. The lower die also holds a shared L3, a 12MiB system cache, PLLs, and the LPDDR, PCIe, camera, display, UFS, and USB interfaces, while the top die carries the ISP, modem, and memory controllers. Cache, I/O, and PLLs produce less heat and are less sensitive to the process, so they go below, Geekerwan explains; the denser compute goes on top, on a somewhat more advanced process.

Each die is just over 120 mm², which is smaller than the previous chip’s 140-plus mm². The total silicon area for both is therefore over 240 mm², up 70% overall. Density rose from 155 to 238 MTr/mm² at launch, about 53.5% higher, according to Huawei’s launch numbers. Other notable changes include the NPU’s area, up 150% across both dies, with Geekerwan measuring 68 TOPS INT8. The configuration makes sense and the rationale follows the layout, but an independent die analysis is needed for full understanding.

Huawei’s stacking approach has its competitors. TSMC’s SoIC roadmap set a 6-micrometer bond pitch for 2025 and 4.5 micrometers by 2029, with 3nm chip stacking in volume production last year. Intel’s Foveros Direct is said to have “copper bonding at a pitch of 9µm,” which reached high volume with the Clearwater Forest Xeon, and a second generation targets 3 micrometers. AMD’s first-generation 3D V-Cache stacks a 64MB L3 SRAM die on a complete CPU die, using direct copper bonding at a 9-micrometer pitch. Huawei’s 1.5-micrometer claim comes from its own paper and any comparison has to be taken with a grain of salt.

As to why Qualcomm might be interested, John Han, executive vice president and general manager of Qualcomm Technology Licensing, said the agreement reflects Qualcomm’s “recognition of Huawei’s continued innovation and intellectual property in 5G and other technology fields.” Bloomberg’s report says that at least some of the patents underpin LogicFolding, but no source names the patents. Dr. Ian Cutress, chief analyst at More Than Moore, questioned how new Huawei’s Tau Scaling is, writing on X that it is “a repackaging of what the industry has always done.”

Upon “receipt of the necessary regulatory approvals,” the cross-license and patent purchase deal should proceed. The deal is also subject to Federal Trade Commission review under the Hart-Scott-Rodino Act, Bloomberg reported. That U.S. premerger law sets a minimum deal size, $133.9 million this year, among other tests, and the deal’s value wasn’t disclosed.

Nikkei Asia reported that Qualcomm will be the net payer under the deal. However Qualcomm said on October 6 that reports characterizing it as a net payor on the license agreement are incorrect and that assertions linking the agreement to LogicFold are not accurate. Qualcomm’s licensing revenue stopped including Huawei royalties in fiscal Q2 2025, after the license expired. This follows a long history of Huawei paying for Qualcomm licenses, an agreement first inked in 2001. Huawei says it has brought in more license-related income than it’s spent since 2021. Patents behind its chip-stacking method reportedly join that business under the deal.

The industry now waits to see what comes of the FTC review. Qualcomm’s fiscal Q4 results should come early next month, as last year’s did, but its fiscal year ended Sept. 27, before the deal was announced. Additional independent analysis of the 9050 Pro’s die may come from TechInsights or SemiAnalysis. Also of interest is the next iteration in Huawei’s Kirin 2027, to see if its claims are met. The deal between the two companies currently lacks details on the extent of patent coverage, but the silicon on record can help reveal the nature of Qualcomm’s interest.

Update: 10/12/2026, 02:50 PT: Added passage reflecting Qualcomm's October 6 statement.

Qualcomm will pay Huawei for patent rights under a multi-year cross-licensing agreement that highlights both 5G and AI technologies, and will buy some of Huawei’s U.S. patents outright, the firm announced. The joint announcement comes 25 years after Huawei began to pay Qualcomm for patents, a reversal that reportedly has Qualcomm paying for the first time. The agreement also covers compute and networking patents, and the patent purchase will close once it receives regulatory approval, the South China Morning Post reported. Qualcomm said on October 6 that reports characterizing it as a net payor on the license agreement are incorrect and that assertions linking the agreement to LogicFold are not accurate.

The two companies’ licensing ties date back to 2001, when Huawei, then a Chinese telecom-infrastructure supplier, took a royalty-bearing license to build CDMA network equipment. Qualcomm, which once supplied chips for some Huawei phones, stopped counting royalties from Huawei in its revenue in early 2025.

The “broad patent license agreement” allows “cross licenses” and reflects both companies’ commitment to intellectual property rights and to licensing consistent with “fair, reasonable and non-discriminatory (FRAND) principles.” The deal involves no other business cooperation, Huawei said, according to SCMP; this implies no chip sales are involved. The deal follows a settled back royalty dispute in 2020, the U.S. revoking Qualcomm’s license to sell some hardware to Huawei in 2024, and the expiration of Huawei’s license by early 2025.

Qualcomm’s patent purchase covers compute, AI, networking, and “other technologies,” according to the announcement, but the number of patents was not disclosed, nor was any value figure. Each company credits the other’s portfolio. This suggests that the two are trading official recognition of each other’s patents.

Huawei says that, with the Qualcomm deal, the total value of its patent-licensing contracts will top $6.9 billion, counting from its first licensing income from Motorola in 2011. Since 2021, it says, its licensing business has brought in more than the company pays for other firms’ patents. In August, the company signed a multi-year Wi-Fi patent cross-license with HP and, as of 2025, the company held 165,000 active granted patents worldwide.

Huawei has also gone to court to enforce its patents, as in a 2024 lawsuit against MediaTek. It halted royalty payments to Qualcomm in 2018, and its general counsel testified for the FTC about Qualcomm’s licensing terms in the agency’s 2019 antitrust trial against the chipmaker. Huawei can now take some satisfaction in leveling the playing field with Qualcomm.

No timetable has been given for closing the patent purchase. Qualcomm’s Q4 report is expected next month, but its fiscal year ended before the announcement, so the deal will not make it into those numbers. The company also renewed its Apple license last month, effective April 1, 2027, after the current extension ends. Qualcomm’s relationship with Huawei is now on the other side, as Qualcomm reportedly becomes the one that pays.

Update: 10/12/2026, 02:50 PT: Added passages to the article to reflect Qualcomm's October 6 statement.

Chinese chipmakers have accumulated an estimated 343 immersion DUV lithography chipmaking tools from 2012 to early 2026, many of which can be used to make chips using 7nm-class process technologies, according to a report from the Centre for Technology & Statecraft (CTS). The Washington-based group asserts that this equipment gives Chinese fabs considerable potential to produce sophisticated processors despite their inability to procure ASML's more advanced EUV systems. While the total number of ArFi tools owned by Chinese chipmakers seems plausible, some other estimates look questionable.

China has been particularly aggressive in procuring wafer fabrication equipment in recent years as the U.S. government has been busy imposing various curbs on its semiconductor industry. Since 2012, Chinese chipmakers, including logic and memory makers, have imported 343 immersion DUV lithography scanners from ASML, excluding imports to multinational fabs located within China.

The authors of the report claim that the existing export controls leave an important gap because lithography equipment originally acquired for less advanced process technologies can potentially be reassigned for more sophisticated process technologies, such as 7nm-class nodes (which the industry adopted in 2018 – 2019). This happens at a cost, but if no other options are available, Chinese chipmakers have no choice. They propose to prohibit exports of all immersion DUV systems to China and restrict replacement components and maintenance services for machines installed at advanced fabs, a proposal consistent with the bipartisan MATCH Act introduced in April.

CTS claims that 270 of these immersion DUV tools are ASML's Twinscan NXT:1980i scanners featuring a 38nm resolution and a 2.5nm matched-machine overlay capability crucial for multipatterning for 7nm-class nodes, which can be used to make chips using 7nm-class fabrication technologies. In addition, CTS claims that Chinese fabs own 22 NXT:2050i and six NXT:2000i systems. It is unclear how many of the 296 advanced immersion DUV scanners shipped to China are currently operational.

Dutch authorities introduced licensing requirements for exports of ASML's NXT:2000i and more capable immersion DUV scanners in September 2023, which effectively prevents their shipment to China. As a result, Chinese chipmakers had to opt for the least capable NXT:1980i. CTS now estimates that Chinese fabs purchased approximately 90 NXT:1980i scanners in 2024 and another 89 units in 2025, spending more than $13 billion during the two-year period. While the Netherlands expanded export controls to the NXT:1980i in September 2024, individual exports of this model can still receive approval. Furthermore, ASML can also potentially sell its NXT:1965Ci systems to clients in China, though we are not sure it has all the components needed for these outdated scanners.

ASML's own results reflect unusually high demand from China: the country represented 41% of its net system sales by shipment destination in 2024 and 33% in 2025. That share subsequently declined to 19% in Q1 2026 and 14% in Q2, which is something that ASML had warned about before.

One should keep in mind that the CTS numbers — ~90 NXT:1980i systems in 2024 and 89 in 2025 — cannot be independently reconstructed from ASML's published financial data. At most, ASML's disclosures provide a useful sanity check: China was indeed an exceptionally large destination during precisely those years, while ASML sold 129 and 131 ArFi systems globally in 2024 and 2025, respectively. If CTS' numbers are correct, then Chinese chipmakers bought the lion's share, 70% and 68%, of ASML's immersion DUV tools output in 2024 and 2025 despite export controls introduced in 2024. Meanwhile, the NXT:1980Di systems are readily available on the secondhand market.

*The source mentions the NXT:1980i machines, which probably include the original 1980Di and newer 1980Fi featuring higher productivity. We will use the 'NXT:1980i' name in this story for consistency, even though ASML has never produced a scanner named NXT:1980i.

Russia-based Zelenograd Nanotechnology Center (ZNTC) has completed the third R&D stage of the company's first lithography tool capable of processing 200-mm wafers using a 130nm process technology, reports CNews. The tool is currently being tested internally and is years away from being used at a real fab to produce chips in mass quantities. Blogger Dmitrii Kuznetsov suggests that the device is the "first Russian 130nm-capable lithograph" that consists of components made in Russia. This may not be the case, though.

"The creation of a prototype of a domestically developed photolithography system designed for a 130nm process is an important milestone for Russia's microelectronics industry," Alexander Mikhailov, an analyst with Strategy Partners, told CNews. "It demonstrates that Russia has its own engineering expertise required to develop such equipment and paves the way for developing a range of systems targeting smaller process nodes (90nm and 65nm)."

Truth be told, while the Zelenograd-based ZNTC is responsible for the project, Belarus-based Planar was responsible for developing the lithography system, according to documents seen by CNews (which corroborates earlier reports). In addition to the system itself, Planar was responsible for manufacturing mechanical assemblies and components, as well as commissioning the prototype. Lasers for the unit were developed by Lassard. Meanwhile, ZNTC is responsible for development of the overall system, design of the test and process equipment, projection-lens calculations, as well as process modeling and development, the report claims. Russia's Ministry of Industry and Trade allocated approximately $70 million for the entire development program.

It is estimated that one 130nm-capable ZNTC stepper costs $6.7 million, while its laser light source costs around $600,000, bringing the cost of a single tool to around $7.3 million. To put the number into context, ASML's PAS 5500/150 stepper had a list price of $3.1 million when it was launched in Q1 2001. Implying a cumulative inflation of about 88%, this translates to around $5.8 million in 2026 dollars. Meanwhile, the Russian stepper is a 200-mm machine capable of 130nm fabrication technologies.

Speaking of 130nm manufacturing processes — which Intel and AMD adopted in 2001 and 2002, respectively — Russian chipmakers have historically developed two 130nm-class nodes, but those technologies rely on lithography equipment from ASML. Whether or not ZNTC's stepper could be integrated into existing nodes remains unclear, but ZNTC claims that it is also responsible for process technology 'modeling and developing.' This likely refers to developing/qualifying the lithographic process around this particular machine —resist, exposure dose, focus/process window, masks, alignment/overlay, develop conditions, temperatures, etc. —rather than inventing an entire 130nm technology from scratch.

Given a typical lithography tool development cycle, ZNTC's 130nm stepper is still likely years away from being used for actual chip production. For now, ZNTC's 130 nm step-and-repeat system is still an engineering prototype, which was delivered five months later than expected. The first prototype is currently undergoing internal engineering and acceptance testing, after which ZNTC will have to finalize the design and validate everything from imaging and overlay to reliability and throughput, which will take well over a year. Only after that, it can build prototype machines for actual chipmakers that will have to characterize them and then qualify them for their production flows, which will take months, if not years.

Even established lithography suppliers typically require several years to move from the first integrated engineering system to production deployment, so a realistic timeframe for the Russian machine to begin processing commercial wafers would probably be around 2029 at the earliest. Limited production of the steppers themselves could potentially begin earlier as long as ZNTC has all the required parts, but that should not be confused with their qualification for volume semiconductor manufacturing.

TSMC and Elon Musk's Terafab semiconductor production initiative are discussing a potential collaboration under which TSMC would build and operate a facility that will exclusively serve Elon Musk's Tesla, SpaceX, and xAI companies, according to Tim Culpan’s Culpium newsletter on Friday. Elon Musk confirmed the discussions early on Saturday, but did not elaborate.

"Just discussions, but something may come of it," Musk wrote in an X post, while TSMC has so far remained tight-lipped.

Under the arrangement Culpan considers most probable, TSMC would own and operate the new semiconductor production facility, while SpaceX/Terafab could invest in the venture, commit to buying a guaranteed volume of chips, or combine both approaches. However, the exact ownership structure remains under discussion. Another option would put SpaceX in control of the venture with the majority ownership; TSMC would invest less, but would still provide 'operational expertise' and process technologies. Perhaps, an interesting background detail from Culpium is that TSMC's rumored intentions to build a fab complex in Texas are tied to the foundry's effort to support Terafab.

The proposed 'Plan A' arrangement could resemble TSMC's JASM and ESMC joint ventures in Japan and Germany, where local partners provide capital and demand while TSMC contributes process technology and operates the fabs. The proposed 'Plan B' structure — under which SpaceX will hold the majority ownership of Terafab while TSMC would operate the facility and bring its own process technology — would be completely new for the world's No.1 contract chipmaker, though.

The development certainly raises questions about Intel's role in Terafab. For now, Intel is to supply its 1.4nm-class 14A process technology to Terafab, which would produce chips for Elon Musk's SpaceX, Tesla, and xAI. If TSMC becomes involved, then Intel's 14A could drop out of the game because TSMC will bring its own node.

Since nothing is official at this point, both 'Plan A' and 'Plan B' should be considered as speculations rather than the two options currently on the table, as there might be 'Plan C,' 'Plan D,' and even 'Plan E.'

TSMC is a leading advanced packaging supplier, so Musk's Terafab might be interested in making chips in Texas (presumably using Intel's 14A process technology) and then package them in Texas, which is where TSMC might come into play. Another thing to consider is that while Intel has a broad cross-patent license agreement with TSMC, Terafab does not, so producing chips using an Intel-developed node might infringe one of TSMC's patents, which might become a problem. To that end, Musk needs to keep TSMC close, perhaps to the point of buying into Terafab.

One thing to certainly keep in mind is that Elon Musk barely wants Terafab to become a foundry that competes against Intel Foundry, Samsung Foundry, or TSMC. What he needs is an uninterrupted and surplus supply of custom silicon to SpaceX, Tesla, and xAI to support their AI, automotive, and space vehicles. Given the rather broad strategic goal, Musk is probably very flexible when it comes to both tactics and strategy.

Three companies, Cadence, Synopsys, and Siemens EDA, dominate chip design software. Their software takes you from chip specification to a manufacturable layout. As AI has rapidly advanced, so have their Electronic Design Automation (EDA) agents, all sporting notable improvements in 2026. The addition of a reasoning model helps drive that flow for Cadence’s ChipStack super agent, Synopsys’ AgentEngineer, and Siemens’ Fuse EDA AI agent, each with its own claims to fame. Cadence at Computex on June 1 said its agent reached what it calls Level 5 autonomy. Rob Knoth, Senior Group Director of Strategy and New Ventures at Cadence, told Tom’s Hardware Premium that the demo was “what we call bounded Level 5 in one domain,” with the bulk of super-agent tech at “I’d say advanced Level 4.”

Synopsys said its spec-to-RTL (Register Transfer Level) workflow shown on March 11 reached “L4,” and the company told Tom’s Hardware Premium it now claims L5 capabilities for its long-horizon agents. Siemens’ agent launched March 16 with “self-verifying” loops announced on July 26. Meanwhile, outside these big three, Empyrean’s chairman, Liu Weiping, stated on Sept. 9 that its agent cut a layout task from four weeks to one, according to the South China Morning Post.

While the claims about what these agents do are specific and now known, what they have measured is not. All of the claimed improvements to speed are the vendors’ or their customers’ own figures, with many “up to” or “early evaluation” caveats. These figures often measure different things against different baselines, and the only evaluator Synopsys named in July, AMD, has not provided analysis beyond an endorsement.

From copilot to closure

In an evolving field, it can be difficult to hit a moving target, especially when the reported numbers measure different things. Some clarity is possible by following the distinct stages from human-only to human-reviewed agent autonomy. The agents fundamentally rely on existing technologies with known desired outputs for accurate evaluation.

Progress has so far followed three distinct generations. At Synopsys, by DSO.ai and reinforcement learning in 2020, generative AI capabilities with Synopsys.ai in 2023, and finally an open agentic AI stack from 2025–2026. All decisions must be validated by proven EDA engines, with the agent focused on evaluating intermediate results and determining subsequent actions. A model’s proposal is examined by an existing deterministic engine such as Xcelium, Jasper, Questa, Calibre, or Fusion Compiler within an iteration loop until final verification.

Measuring progress here does not follow a standard, but there are autonomy ladders with a general rating from Level 1 or L1 to Level 5 or L5 or, in Siemens’ case, no numbered level. Cadence, which uses levels, moves from optimization AI to conversational LLM, complex reasoning, agentic workflows, and then finally full autonomy, defined as taking a design from spec to verification “with minimal human intervention.”

Synopsys’ L framework goes from actions of single agents on a single design step to more complex ones with multiple agents, with further development focusing on adaptive learning and, ultimately, the agent’s ability to make decisions autonomously. The critical part for Synopsys is that “human engineers will and must always be in the loop.” Given the claims of progress, it’s clear that ladders, where they exist, are a form of marketing scaffolding that describes the same underlying architecture or loop.

Specification to verified RTL

The greatest claimed gains thus far are in the front-end design and verification stages, taking a specification from RTL to a verified design. This part of the process is a natural fit for LLMs, as the RTL, testbenches, and assertions are code. Where the loop used to wait on human analysis and input, the agents can run simulations in parallel and make decisions with fast, concrete pass-or-fail answers. These loops already existed and are prime real estate for agents to speed things up, with claimed orders-of-magnitude improvements by moving from human to agent on what is often the slowest part of the process, triage.

Getting from the chip specification to verified RTL code involves generating the code from natural language and formal specification, according to Synopsys’ March release. From there, the agents generate unit-level testbenches and engage in a verification loop. In July, Synopsys claimed RTL validation could be up to 50x faster with a 20% improvement in coverage, compared with its own non-agentic flow.

For Cadence’s ChipStack from February, the scope includes “autonomous RTL design, verification, and debug.” Named early users include Altera, Nvidia, and Qualcomm. ChipStack started as a Seattle startup that was acquired in November of last year after a multi-year integration with Xcelium and Jasper. In June, Cadence said RTL validation could happen over 40x faster, with each engineer using ChipStack agents “to run hundreds of dynamic simulations with Cadence Xcelium ... reducing a typical five-week verification loop to less than a day.”

Siemens’ Questa One Agentic Toolkit, detailed in February, has five separate agents: RTL Code Agent, Lint Agent, CDC Agent, Verification Planning Agent, and Debug Agent. These work with mainstream AI coding applications including Claude Code, Cursor, and Siemens’ own Fuse. Akshay Aggarwal, senior director of engineering for MediaTek, noted “immediate and significant” gains. The numbers from Synopsys and Cadence should be read as the vendor’s own ratio comparison to the old loop, as regression loops are already automated. All three companies are now focusing on the decision-making process. For details on specific claims, refer to the table below.

The back end

Things are tougher when you move from RTL verification to implementation. Outside of specific tasks that look like front-end loops, claimed gains are harder to come by. This phase deals with geometry and physics, not code, and the pace is limited by compute. Some tool runtimes are “days to weeks … just running the tool itself,” and a tool call that takes “hours to days” to return a value “really gives the AI industry a much different problem to solve,” Knoth said. Complex trade-offs remove singular pass-or-fail judgments, and mistakes later in the process become much more expensive. Earlier AI integration also already exists for this flow, so the agentic touch is more on experiment-running. This makes things cloudier.

Cadence’s InnoStack runs parallel experiments from synthesis to ECO execution. ViraStack, which is for custom and analog solutions, handles the design flow from drawing to simulation, optimization, and layout porting, with some customers “reporting 3–10x productivity improvements,” according to a report from Futurum in April.

Synopsys’ looping implementation agents, driving Fusion Compiler directly or through other platforms, help “reduce manual engineering effort,” according to AheadComputing, and Synopsys said they improve quality of results, including timing, power, and area.

Siemens Fuse, meanwhile, coordinates at least nine named tools, including Solido for custom IC design and verification, Aprisa for physical implementation, Calibre for signoff verification, and design-for-test with Tessent. Improvements vary, with Solido mentioned as improving characterization turnaround times by more than 10x and token costs by 5x to 10x, according to Siemens. One third party, STMicroelectronics, mentions that the Solido Layout Analyzer is helping “cut down the time we spend debugging complex design blocks by weeks,” according to Non-Volatile Memory Design manager Gianbattista Lo Giudice.

Empyrean, according to the SCMP’s September reporting, is shifting from “humans operating tools” to “humans commanding agents” with its agentic EDA platform. This platform would work with its partners’ agents. One claim is that 3D verification went “from two to three months to less than a month,” according to TrendForce reporting. Empyrean is the largest domestic EDA vendor in China and is state-controlled as of December 2024.

Self-checking agents

What we inevitably keep coming back to with agentic EDA is one simple term: trust. The agents must be trusted to varying degrees to check their own work. Important checkpoints are still verified by a human: “The crucial approval checkpoints are still going to be human-driven,” Anand Thiruvengadam, executive director of product management at Synopsys, told Tom’s Hardware Premium. Inside the loop, the use of reliable tools such as deterministic engines allows for results that can largely be trusted. Outside of this, trust is based on evaluation, and internal verification is only as good as the tests. There remains reliance on what the vendors claim, and that depends on exactly how each defines the self-checking loop and goals.

The Siemens Agent loop, put simply, is: Plan, Act, Reflect, Iterate, over “Develop, Publish, Execute, Refine.” “Self-verifying” in Siemens’ case means that agents “continuously validate decisions against deterministic, physics-based EDA engines.” According to SemiWiki’s Bernard Murphy, describing the Fuse launch, “the orchestrator can trigger repair agents, then re-run validation. This may resolve most errors,” although we were unable to get any comment on specific triggers.

Cadence’s description is that “every action the super agent takes is anchored” in its own proven design and verification engines, to ensure accurate results. These, like Siemens’ solution, can run “within a secure Nvidia OpenShell sandbox” to enforce guardrails and ensure predictability. This allows engineers to “inspect, guide and collaborate as needed” even at Level 5. The human engineer works from their own runtime environment, then “once the super agent finishes that loop … the auto-run environment can interpret, understand, and then fire off that next message, right, that next iteration,” Knoth said.

Synopsys also retains the human element, with the debug workflow’s output as root-cause analysis and resolution through engineers. The flow iteratively runs checks against generated, unit-level testbenches, with the agent handling design and the tests themselves. When a check fails in Synopsys’ Verification AgentEngineer, the logs are consulted, and errors are aggregated to paint a picture of the most likely cause, checked against simulation waveforms. When applying the fix, the agent must prove that the bug has actually been fixed and should be able to produce a bug-fix manifest. Beyond this, the quantity of checkpoints is determined by customers’ trust and desired flexibility, and over time, “they might relax and take away those checkpoints,” Thiruvengadam said. The internal process, such as the specifics on retry limits, the definition of unfixable, and states requiring escalation, remains murky.

Early access everywhere

All of the numbers and roadmaps in the world don’t replace actual value to the customer, or actual customers with a released product. Thus far, the agentic platforms have been in early access and evaluation. Engagements have been listed, and major customers exist, but none are confirmed with a generally available product. General availability hasn't arrived yet, but it has been promised by the end of 2026 by Synopsys, with Cadence’s AuraStack, its PCB and advanced-packaging agent, also due this year. Usable products and workflows exist, but the efforts remain nascent, despite relatively rapid claimed gains over the last year or so.

Cadence ChipStack has been in early access since February. In June, this extended to the promise of Level 5 capabilities with early access for customers in the second half of 2026. Synopsys has debug and implementation workflows, announced in July, available for evaluation on Microsoft Discovery, if requested. Microsoft’s platform is designed to assist in the construction and management of agentic AI workflows related to scientific and engineering fields. Siemens has the Questa One Agentic Toolkit, announced in February, and the Fuse Agent as of March, with promises made in July surrounding self-verifying capabilities in forthcoming releases. Empyrean is also developing its own platform as of the time of writing.

The current stacks largely run on Nvidia’s Nemotron and its OpenShell sandbox. Nemotron is a reasoning model family. OpenShell is an open-source runtime that keeps the agent contained with kernel-level isolation, protecting customer IP and guarding against rogue actions. Nemotron and OpenShell are open, so nothing on record prevents Empyrean from using them, but without announcements, it appears to be the outside case. What each EDA vendor does with this technology and the flexibility it offers its customers are the defining differences.

Earlier this week, Nvidia announced its Open Agent Safety Platform, a combination of OpenShell and the Sentry reference design, an “out-of-band watchdog” that runs on BlueField-4 DPUs to “continuously monitor agent behavior” and can quarantine an agent in milliseconds. Cadence, Synopsys, and Siemens are named among the more than 100 organizations working with Nvidia on the platform. Cadence’s Knoth told Tom’s Hardware Premium that OpenShell “helps ensure the agents are well behaved ... don’t go rogue and start accessing data they’re not supposed to,” as agents need to become productive and trusted. Thiruvengadam from Synopsys echoed these sentiments, with both companies aware of the dangers of rogue agent actions.

Cadence and Synopsys, at least, needed licenses as of May 2025 for EDA sales to China, but the requirement was rescinded as of July of that year. EDA is expected to be critical for the industrial software space “toward the high end of the global value chain” by 2030, according to ChinaTechNews. According to Liu, as reported by the SCMP, Empyrean is trending away from traditional software licenses to a token-consumption pricing model with agentic EDA.

Startups in this space include ChipAgents, Cognichip, Agentrys, Silimate, and Ricursive Intelligence, most funded since December 2025. The big three buy other companies, from startups such as ChipStack to simulation software maker Ansys, as advances put EDA in the spotlight toward the end of 2026. Even with platform-specific flexibility, Nvidia remains the common ground, with its open model family and sandbox being the standard across the big three.

As it stands in 2026, the agents exist, and there are real roadmaps and customer evaluations. The framework hinges on existing technology already worthy of trust. The overall trend is toward harness engineering and, as Knoth told us, the implementation of “an array of specialized engines” to fuel the workflow end to end. Improvements, although currently lacking the independent measurement and precision we would like to see, are real and accelerating, according to vendors and their customers. It will become increasingly important to have proper evaluation of the different agents as they approach Level 5, “L5,” or some equivalent marker that denotes autonomous action.

What we would like to see by the end of the year is some customers named to actually be using the highest level of agent. Specifically, these agents must live outside of a trial or early access mode. This enables oversight and comparison in what will become an incredibly important field. We also anticipate Siemens’ forthcoming releases, which may demonstrate the self-verifying loop. Cadence is worth a close watch to see whether a Level 5 early-access customer is named before the end of the year. The baseline, though, is at production: real customers, real workflows, real products, and a measured improvement.

OpenAI’s Jalapeño ASIC is a seismic shift for the industry, not because of its efficiency or performance, but because of how it was designed. The company was clear from the jump that AI played a big role in the design process of Jalapeño, not only for the hardware itself, but also in the co-design with OpenAI’s software stack, allowing the ASIC to go from initial register-transfer level (RTL) to tapeout in a matter of just nine months. From concept to reveal, the timeline was less than two years. Richard Ho, head of hardware at OpenAI, says the timeline “established a new baseline,” and that the industry is already knocking on OpenAI’s door to learn how the company pulled it off.

“The way I like to think about it is, we’ve established a new baseline. In the old baseline, you’re talking 18 months to two years, roughly. Often that’s even with some existing IP or some more legacy architecture design,” Ho told Tom’s Hardware Premium in an interview. “We’re starting from scratch here. We had nothing. There’s not a line of code here to refer to. What we’ve established is that there’s a new baseline that you can do with a very talented team with the help of AI. Now, does it get shorter? It depends on what you’re trying to do.”

AI usage in chip design is nothing new, predating the era of LLMs entirely. The largest Electronic Design Automation (EDA) companies, Cadence and Synopsys, have a portfolio of AI-assisted chip design tools that have been around for several years. The models OpenAI used were its own internal models, however, and it leveraged both existing EDA tools and its new AI-assisted engineering workflow.

The engineering team used OpenAI’s agentic coding platform, Codex, for the Jalapeño design. “But we think that every engineering team in chip design should be able to use this as a new baseline, because it’s a proof point that the models that are in use — the AI models for us is mostly Codex, Sol, the one before Sol, and now we’re moving on to Astra. These are super capable. Even from when we started that work, back in November 2025, to when we taped out, the models improved enormously. Even from that moment to when we started doing the kernel optimization in May, when the chips were first coming online, we ourselves were shocked at how much better Codex was and what it could do,” Ho said.

Although AI was used during the entire development process, not only for design itself but also in writing and optimizing kernels, Ho continually reiterated the importance of talented engineers guiding those systems. The development story of Jalapeño is one of the few clear examples of AI bolstering a team of human workers, not displacing them.

Ho described the development cycle as a “good model” of how engineering teams should operate in the AI era. “This is how AI should be used. We didn’t replace our engineers; they just became super productive. With a smaller team of really good engineers with a lot of this AI stuff, you could do things faster and better than you could otherwise. I think that’s a good model of how engineering should be approached in the AI age.”

Although OpenAI managed to get working silicon much faster than a traditional development cycle, it wasn’t free of issues. For starters, OpenAI’s B0 stepping of Jalapeño reportedly delivers up to a 25% improvement in performance per watt over the original A0 stepping. That’s closer to a generational improvement than stepping optimization, suggesting that, at least for a brand new hardware team, there may have been design oversights with the original stepping. Attributing that to AI or humans is anyone’s guess.

Other frontier labs are circling for a slice of the pie, as well. Clive Chan, a key engineer on Jalapeño and the second-ever hardware hire at OpenAI, left the company in June to join the hardware team at Anthropic. Ho says there’s already been “a lot of interest in the industry” for OpenAI’s AI-assisted chip design process, and says that “we’ll see more about that quite shortly.”

“I’m not going to preempt anything here. I can tell you that there’s a lot of interest in the industry, and I would also tell you that we feel that there is a lot of benefit in industry generally that we want to enable,” Ho said. “I think that’s something that we’ll see more about quite shortly, to be honest.”

Ho referenced the dozens of AI-first chip design startups in Silicon Valley, suggesting OpenAI may eventually introduce tools of its own to aid other firms with AI chip development. “We have our take on that, and I think at some point we want to tell the world, “Here’s our take on it.” Fundamental to that is Codex and GPT-6 Astra coming out. Those are fundamental, and we can basically point to it; it’s not going to be slideware or vaporware. We can point to it and say, “Here’s what we did, here’s how we did it, and here’s what we got.” It’s going to be very concrete.”

What exactly the “it” Ho is referring to here remains a mystery, though given the context, it sounds like OpenAI may explore some way to productize its AI chip design workflow. Ho says Astra is a big step toward that, and we’ve already seen the model in action performing impressive feats, such as completing Portal autonomously.

Although OpenAI leveraged its own models heavily for Jalapeño's design and validation, it didn’t completely break the mold of traditional EDA workflows, particularly at the end of the design process. Before tapeout, tools from companies like Synopsys and Cadence perform a series of tests for signoff, including static timing analysis and signal integrity analysis. Ho says that OpenAI used this typical EDA flow for Jalapeño.

“But for sign-off, you need to use the standard EDA flows, and we did, because you want to make sure those results are good and correct. There’s no real alternative today. Part of it is this combination of standard flows optimized with AI, optimized by really good engineers,” Ho said.

OpenAI shared a multi-generational roadmap for accelerators. It says its second-gen ASIC is approaching tape-out, and its third generation is already in development. Although Ho said that the Jalapeño development cycle establishes a new baseline for chip design timelines, he was cautious about calling that cycle and cadence.

“Our projects and tape-outs will be dependent on the maturity level of the technologies. We can do very fast execution. Will we do those types of executions back-to-back? I doubt it, because the technology will not be ready for that, and I don’t want to tape out something that is 2% better than what I taped out before, because it’s not worth it to change a fleet,” Ho told us.

The executive was also clear that the Jalapeño timeline isn’t necessarily the same timeline all chips will follow. There were some “pragmatic trade-offs” in the early architecture design, with the team avoiding emerging, complex design points like 3D stacking and co-packaged optics. “Will it take longer? Will it take nine months? I won't say it will take nine months… but I think it will go faster than if you didn't have AI models.”

You can read the full transcript of the interview, which covers a wide range of topics, at Tom's Hardware Premium.

In late August, Architect Labs claimed it had designed a chip that was almost entirely developed by AI, an industry-first achievement. AI is already used to optimize floorplans, placement and routing, verification, and other stages of semiconductor development. Generative AI can assist engineers with RTL code, whereas emerging agentic systems can operate electronic design automation (EDA) tools, analyze results, identify problems, modify designs, and repeat the process with increasingly less human intervention. Meanwhile, human engineers still define and develop architectures and make fundamental design decisions that determine what a chip does and how it works.

This creates a curious feedback loop. Today's AI models run on processors designed by human engineers with growing assistance from AI; those models can then help design more capable processors for the next generation of AI systems. As EDA vendors and semiconductor companies give AI control over progressively larger portions of the design process, the industry is gradually moving from humans using AI tools to design chips toward AI systems participating in the design of the hardware on which their successors will run.

Can machines indeed design machines today? Probably not. But will they be able to do so in the future? That's a big question with important ramifications — and engineers have been pondering it for longer than you might think.

A brief history of AI in chip development

Cadence, Synopsys, and Siemens EDA, all leading developers of EDA software, alongside Ansys — a leading designer of simulation software — rolled out AI-enhanced versions of their tools in the early 2020s, before the generative AI boom took the world by storm.

The first generation of AI-enhanced EDA software primarily used machine learning (ML) and reinforcement learning (RL) to tackle well-defined optimization problems. Given an existing design, a set of constraints, and particular targets, these tools could explore numerous implementation options to optimize placement and routing, and therefore power, performance, and area (PPA), while shrinking development time. Essentially, AI could find a better way to implement a design, but the design itself and its goals were still defined by engineers.

One of the key advantages of these tools was their ability to learn from previous runs and use accumulated data to guide subsequent design-space exploration, something which could reduce the number of iterations needed to meet PPA targets and, in some cases, produce results that would have required considerably more engineering time using conventional methods. Yet the autonomy of these tools is limited, as engineers define constraints, configure flows, run individual tools, analyze their output, and decide what to try next. AI accelerates or optimizes particular stages of chip development, but humans still control the overall design flow. And that's changing with newer generations.

The latest AI-enhanced EDA tools are considerably more ambitious. Generative AI can write or modify RTL and verification code, analyze reports, identify potential points of failure, and even suggest fixes. Meanwhile, emerging agentic systems can operate multiple EDA tools and execute sequences of engineering tasks with very limited human intervention. Such an agent can analyze results, modify a design or its parameters, launch another simulation or implementation run, evaluate the outcome, and repeat the process until it reaches specified targets. As a result, AI is gradually moving from optimizing individual steps inside EDA tools to automating parts of the chip development workflow itself.

From big bang to architectures

In 2023 – 2024, both Cadence and Synopsys announced that hundreds of chip designs have been completed using their AI-enhanced Cadence.ai DSO.ai/VSO.ai/TSO.ai tools. Moreover, leading high-tech companies revealed details about how they used AI to complete their projects. Yet putting Google, Nvidia, OpenAI, and Architect Labs into the same bucket is not right, as they represent different degrees of AI involvement in chip development.

Google, which was among the first high-tech giants to announce the use of AI to develop its AI accelerators, seems to be the least radical. Google's AlphaChip uses reinforcement learning mostly for physical floorplanning: it places circuit blocks and optimizes layouts, but it does not invent the entire design or the architecture itself. Google DeepMind said in 2024 that AlphaChip had been used for the previous three generations of TPUs, meaning Google was well ahead of the general EDA industry with its tools. (The company has not shared AlphaChip's progress in detail since then.)

Nvidia is more interesting because its internal AI systems tend to automate work traditionally performed by hardware engineers. The important distinction is that Nvidia trains specialized models on its own RTL, documentation, and unique accumulated engineering knowledge, something a merchant EDA vendor cannot access. This makes Nvidia an example of a chip designer that turns the engineering data behind its proprietary GPU and, more recently, AI accelerator, CPU, DPU, and network cards into training data for AI. Nonetheless, Nvidia itself draws a clear line between its automation and autonomous chip design.

OpenAI's Jalapeño is probably the strongest real-silicon example we currently have. OpenAI says AI was directly involved in implementation, design-space exploration, verification loops, and arithmetic-circuit optimization, which enabled the company to go from initial design to tapeout in nine months. At Hot Chips, OpenAI disclosed some concrete PPA advantages: Compared with human baselines, AI-assisted designs improved a BF16 multiplier by 56%, an FP4 dot-product block by 21%, and an FP32 accumulator by 10%, while reducing the area of matrix and SIMD units by 10% and 8%, respectively.

OpenAI has not said that AI invented Jalapeño's architecture, so humans have indeed remained responsible for it. But AI was extensively used to turn that architecture into silicon and optimize it ... which brings us to Architect Labs.

Indeed, Architect Labs' Redwood is qualitatively different. Two human architects defined the specification, after which Architect Labs says its AI autonomously generated and verified the logic, generated RTL, verified it, and produced firmware. To top it off, AI also assisted software development, including drivers and kernels. Meanwhile, unlike Google, Nvidia, and OpenAI, the company explicitly describes its system as one that performs machine learning co-design and says it can explore architectures, though without elaboration.

Redwood was 'produced' in under two weeks and runs billion-plus-parameter models, but there is a huge caveat: It has not been taped out. It has never actually been produced as an ASIC; the accelerator runs on an FPGA, and the claimed 3.4X performance-per-watt advantage over Nvidia's Jetson Orin Nano is based on a projected Samsung 8LPP design.

Final words

Just a few years ago, AI in semiconductor development was largely an optimization technology that helped engineers find better ways to implement designs created by humans. Today, it can generate RTL, verify designs, operate EDA tools, and even explore architectural choices, although humans still define what ultimately gets built.

We are therefore considerably closer to machines designing machines, but nowhere near the singularity quite yet. For now, chips are helping design their successors. But they aren't even close to deciding what those successors should be.

Synopsys announced its AgentEngineer solutions, a portfolio of “domain-specific long-horizon agents” built on its new Autopilot Platform. As the company details in a blog post, the portfolio covers six named domains: verification, system validation, implementation, analog and mixed-signal (AMS) design, manufacturing, and simulation and analysis. More than 50 customer engagements are underway, according to the company, and Synopsys confirmed to Tom’s Hardware Premium that general availability is planned for the end of 2026. This follows July, when the company showed agentic AI workflows developed with Nvidia and with Microsoft at DAC, the Design Automation Conference.

The launch brings Synopsys’ plans into focus with a named product line and a target date. The platform’s agents are clearly named and delineated, the engagement count points to customer interest, and a goal for general availability anchors a roadmap for autonomous agents in production. Two of the headline performance figures are restated from July, and the only named customer figure is one company’s range. While Synopsys describes the agents as autonomous, the approval checkpoints remain with humans, the company said.

For companies designing and producing chips who want to leverage the potential efficiency gains of AI, this technology allows them to “accelerate their shift from AI-assisted design to autonomous engineering,” said Ravi Subramanian, chief product management officer at Synopsys.

In a blog post published alongside the release, Anand Thiruvengadam, executive director of product management at Synopsys, detailed three layers: long-horizon AgentEngineers are “domain-specific super agents that orchestrate task agents,” task agents “complete specific, bounded engineering tasks” and can be orchestrated by an AgentEngineer or invoked directly by an engineer, and the tool layer’s engines “execute the requested work” but do not set goals or make decisions. Unlike long-running agents, which may perform one activity for hours or days, long-horizon agents address “goal complexity,” pursuing objectives that can take hundreds or thousands of reasoning steps.

The platform covers everything from orchestration to telemetry, with a “cognitive model” powering what Synopsys calls context intelligence. Access controls, encryption, and runtime guardrails protect customer, partner, and Synopsys IP, which is particularly important when third-party agents share the workflow. Customers can choose commercial, open-source, or fine-tuned language models and deploy on Synopsys Cloud, their own cloud, or on-premises infrastructure. In other words, customers can “bring their own LLMs and data and infrastructure,” Thiruvengadam told Tom’s Hardware Premium.

The blog outlines the verification loop — the agent plans, orchestrates task agents, checks what they return, and adjusts whenever an intermediate result falls short. When a test finds a bug, a root-cause analysis (RCA) agent reads logs, clusters errors, forms a hypothesis, and inspects waveforms to confirm it. The agent then makes “local rewrites of the RTL to prove that the bugs have indeed been fixed” and produces a bug fix manifest. When intermediate results drift from the objective, the agent will “course correct, adapt, react,” he said.

The performance numbers in Synopsys’ release are heady: up to 50x faster verification closure, 20% higher coverage, a 30% productivity boost, 2x better token efficiency, and lower latency. The 50x and 20% figures are not new. Synopsys told Tom’s Hardware Premium that they come from its July work with Nvidia, measured against its own verification workflows without AgentEngineer. The 30% number is at the top of the 10% to 30% range Fujitsu reported for its RTL code generation.

Those productivity gains are measured “compared to what the human experts would have done otherwise or are doing today,” Thiruvengadam said. The 2x token efficiency, meaning fewer tokens for a given task, is customer-reported: an unnamed customer compared Synopsys’ agents with its own, built on commercial agentic harnesses. No figure exists for the latency claim; the release and blog credit it in part to context intelligence, which suggests less time spent waiting on model calls.

Another engagement with results is AheadComputing, whose Vice President of Verification, Alon Mahl, said the Implementation AgentEngineer helped reduce manual engineering effort from RTL handoff through signoff, without giving a number. Intel, MediaTek, and Samsung also endorsed the technology. None gave hard results, but all supported the technology as promising. Today's launch is the portfolio and platform, without production details. Synopsys’ earlier AI tool from 2020, DSO.ai, has passed 100 production tape-outs, while the new agents are still in engagements.

How autonomous are these agents? Each vendor defines autonomy on its own scale, and Synopsys introduced its L1-to-L5 framework last year. “The original vision of L5 was fully autonomous execution. But not just fully autonomous execution, but also complexity,” Thiruvengadam told us, describing L5 as executing a complex workflow autonomously within human guardrails. “That was the idea, and that’s exactly where we are.” Synopsys confirmed that it characterizes the agents as L5. Cadence also claimed Level 5 on its own scale at Computex in June.

Earlier this year, Nvidia chief scientist Bill Dally said AI cut a 10-month, eight-engineer task, porting a standard cell library for GPU design, to one night, but that Nvidia is still “a long way” from having AI design a new GPU end to end.

Human engineers remain in the loop, but the amount of oversight varies. “The guardrails are still going to be defined by the humans, the crucial approval checkpoints are still going to be human-driven,” Thiruvengadam said. “Our customers will have to learn to trust these autonomous systems.” The blog adds that teams can set checkpoints where people inspect results, validate decisions, and redirect the workflow, then “reduce intervention” as confidence grows. No vendor has yet described when its agents stop retrying or escalate to an engineer.

Synopsys says the capabilities are already there; its next goal is general availability. Eyes will be on whether Synopsys reaches general availability by the end of 2026, and names a customer in production when it does. Cadence expects Level 5 early access in the second half of 2026, and Siemens has promised self-verifying capabilities in forthcoming releases. The product exists and works in customers’ hands, and the speedup claims, if they can be realized beyond internal evaluations, and especially if backed by independent testing, appear to be extremely promising.

Intel's 14A (1.4nm-class) process technology is expected to deliver performance 'within 5%' of TSMC's A14 (1.4nm-class) production node, Naga Chandrasekaran, the chief technology and operations officer as well as general manager of Intel Foundry, told investment banking firm KeyBanc (via @Alex_Intel_). Given TSMC's track record of delivering steady performance, power, and area (PPA) gains with every new node, this might sound like entirely good news. However, the statement deserves a closer examination.

Delivering 'within 5%' performance is an ambiguous statement that may mean that 14A will be 5% faster than A14, or that 14A will be 5% slower than A14. While 'within 5%' performance compared to the direct rival of the same class may sound like a good competitive position, in recent years Intel's process technologies trailed TSMC's nodes in transistor density and remained competitive in performance or power. This was, to a large degree, attributed to Intel's historic focus on CPU performance, but not necessarily transistor density, as its own fabs have offset additional costs associated with larger dies.

In fact, actual shipping processors suggest Intel's 18A is at least competitive with TSMC's N2 in maximum achievable CPU frequency as Intel's Core Ultra X9 388H 'Panther Lake' can hit 5.10 GHz (at an 80W max turbo power), AMD's EPYC 9586F has the highest single-core clock of 5.0 GHz (at a default 500W CPU power), Apple's A20 Pro can achieve 4.93 GHz, whereas Apple's M6 can hit 4.78 GHz. These numbers should not be converted directly into a statement such as '18A is X% faster than N2,' because the processors use different architectures, voltages, standard-cell libraries, thermal envelopes, and physical implementations. However, they do provide a useful real-world reference point: the available N2 processors do not show a substantial frequency advantage over 18A. If anything, the highest observed CPU frequencies favor Intel's process.

Based on internal estimates, Intel officially states that compared to its already fast 18A, its 14A is expected to provide 15% – 20% higher performance at the same power, or 25% – 35% lower power at the same frequency and transistor count. By contrast, TSMC expects its A14 to be 10% - 15% faster than N2 at the same power, or 25% - 30% lower power at the same clocks and transistor count.

Combining the observed 18A and N2 CPU frequencies of Intel's 18A and TSMC's N2 with Intel's stated 15% – 20% 14A gain and TSMC's assumed 10% – 15% A14 gain would ordinarily suggest a modest 14A performance advantage of A14 even in most conservative scenarios for Intel. Therefore, Intel's new expectation that 14A will be 'within 5%' of A14 is notably less ambitious than one might infer from the company's published process specifications, even though the 'within 5%' statement does not tell us which process Intel expects to lead.

In fact, advantages of Intel's 14A over TSMC's A14 can be calculated using the highest observed 18A and N2 CPU clocks combined with Intel's and TSMC's official iso power performance projections.

Starting points: Intel 18A = 5.10 GHz (Core Ultra 9 388H); TSMC N2 = 5.00 GHz (EPYC 9586F).

With Intel’s Core Ultra X9 388H and AMD’s EPYC 9586F as the starting points, the official iso-power performance projections imply a 2% – 11.3% potential performance advantage for 14A over A14, depending on the combination of process-performance assumptions.